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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775023093-BC882900-80AF429B/0/0 X-purgate-type: clean X-purgate-size: 3959 On 31.03.2026 18:32, Oleksii Kurochko wrote: > On 3/31/26 5:53 PM, Jan Beulich wrote: >> On 31.03.2026 17:20, Oleksii Kurochko wrote: >>> On 3/30/26 5:13 PM, Jan Beulich wrote: >>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>> domain_use_host_layout() is not really architecture-specific, so move it >>>>> from the Arm header to the common header xen/domain.h and provide a common >>>>> implementation in xen/common/domain.c. domain_use_host_layout() potentially >>>>> is needed for x86 [1]. >>>> >>>> No matter that this may indeed be true, ... >>>> >>>>> Turn the macro into a function to avoid header dependency issues. >>>> >>>> ... this introduces unreachable code on x86, i.e. a Misra rule 2.1 violation. >>> >>> Do we have some deviation tag for such cases when the code temporary >>> isn't used? >> >> I'm sorry, but it'll take me about as long as you to find out. > > Sure, I will take a look. I just thought that maybe you have a solution > already just in your head. Well, I do: Don't make this an out-of-line function. > I wonder >> about "temporary" though: Do you have a clear understanding as to when >> that will change? > > No, I don't. As Stefano mentioned they will need this function one day. > Another option we could use ifndef x86 or ifdef DOM0_LESS and then when > someone will really need it on x86, this ifdef will be dropped. I don't > know if it is better solution. > > It seems like the best one solution will still make a try to make > declare this function as macro. Or an inline function. There's nothing ... >>>>> @@ -2544,6 +2544,12 @@ void thaw_domains(void) >>>>> >>>>> #endif /* CONFIG_SYSTEM_SUSPEND */ >>>>> >>>>> +bool domain_use_host_layout(struct domain *d) >>>>> +{ >>>>> + return is_domain_direct_mapped(d) || >>>>> + (paging_mode_translate(d) && is_hardware_domain(d)); >>>>> +} >>>> >>>> The placement of paging_mode_translate() doesn't match ... >>>> >>>>> --- a/xen/include/xen/domain.h >>>>> +++ b/xen/include/xen/domain.h >>>>> @@ -62,6 +62,22 @@ void domid_free(domid_t domid); >>>>> #define is_domain_direct_mapped(d) ((d)->cdf & CDF_directmap) >>>>> #define is_domain_using_staticmem(d) ((d)->cdf & CDF_staticmem) >>>>> >>>>> +/* >>>>> + * Is the auto-translated domain using the host memory layout? >>>>> + * >>>>> + * domain_use_host_layout() is always False for PV guests. >>>> >>>> ... the description of the function. >>> >>> But why the placement should be different? >> >> If you focus on auto-translated, then imo paging_mode_translate() >> better would guard everything. > > Then it make sense to do in the following way: > bool domain_use_host_layout(struct domain *d) > { > - return is_domain_direct_mapped(d) || > - (paging_mode_translate(d) && is_hardware_domain(d)); > + return paging_mode_translate(d) && > + (is_domain_direct_mapped(d) || is_hardware_domain(d)); > } ... in here which clearly speaks against doing so. And yes, this is what I was asking for (with the function parameter also suitably constified). >>> So if domain_use_host_layout() is fully depends on >>> paging_mode_translate(d) && is_hardware_domain(d) and for which >>> paging_mode_translate() is false if it is PV guest. >>> Thereby domain_use_host_layout() is false too. >>> >>>> >>>> Further, the first sentence above suggests the caller has to check >>>> paging_mode_translate() before calling, which as per the implementation >>>> clearly isn't the intention. >>> >>> Sorry, I don't follow you here. >> >> By starting the comment with "Is the auto-translated domain using", you >> imply the caller checked for that aspect already. At least the way I >> read it. > > My understanding was that it is an explanation what function is checking. For that you'd want to omit "auto-translated" from the first sentence, imo. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <38d93a26-dfce-4d4e-a1d2-c4e8d13c4ead@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1775023183-BCD65185-790A1592/0/0 X-purgate-type: clean X-purgate-size: 1660 On 31.03.2026 21:49, Oleksii Kurochko wrote: > On 3/31/26 6:32 PM, Oleksii Kurochko wrote: >>>>>> @@ -2544,6 +2544,12 @@ void thaw_domains(void) >>>>>>    #endif /* CONFIG_SYSTEM_SUSPEND */ >>>>>> +bool domain_use_host_layout(struct domain *d) >>>>>> +{ >>>>>> +    return is_domain_direct_mapped(d) || >>>>>> +           (paging_mode_translate(d) && is_hardware_domain(d)); >>>>>> +} >>>>> >>>>> The placement of paging_mode_translate() doesn't match ... >>>>> >>>>>> --- a/xen/include/xen/domain.h >>>>>> +++ b/xen/include/xen/domain.h >>>>>> @@ -62,6 +62,22 @@ void domid_free(domid_t domid); >>>>>>    #define is_domain_direct_mapped(d) ((d)->cdf & CDF_directmap) >>>>>>    #define is_domain_using_staticmem(d) ((d)->cdf & CDF_staticmem) >>>>>> +/* >>>>>> + * Is the auto-translated domain using the host memory layout? >>>>>> + * >>>>>> + * domain_use_host_layout() is always False for PV guests. >>>>> >>>>> ... the description of the function. >>>> >>>> But why the placement should be different? >>> >>> If you focus on auto-translated, then imo paging_mode_translate() >>> better would guard everything. >> >> Then it make sense to do in the following way: >>  bool domain_use_host_layout(struct domain *d) >>  { >> -    return is_domain_direct_mapped(d) || >> -           (paging_mode_translate(d) && is_hardware_domain(d)); >> +    return paging_mode_translate(d) && >> +           (is_domain_direct_mapped(d) || is_hardware_domain(d)); >>  } > > This is not really correct. ... because of ... ? (After all, then the comment isn't correct either.) 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775023659-BEE95900-A4246FB9/0/0 X-purgate-type: clean X-purgate-size: 2603 On 31.03.2026 18:02, Oleksii Kurochko wrote: > On 3/30/26 5:34 PM, Jan Beulich wrote: >> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>> p2m_gpa_bits is used by common/device-tree/domain-build.c thereby when >>> CONFIG_DOMAIN_BUILD_HELPERS=y it is necessary to have p2m_gpa_bits properly >>> defined as it is going to be used to find unused regions. >>> >>> Introduce default_gstage_mode to have ability to limit p2m_gpa_bits before >>> p2m_init() is being called as it will be too late. >> >> This is a somewhat strange way of describing things. Of course you want to >> establish globals before doing any per-domain setup. > > Then I will drop that sentence now and avoid similar in the future. > >>> Limit p2m_gpa_bits in guest_mm_init() as it could be that default G-stage >>> MMU mode uses less VA wide bits than IOMMU, >> >> How does a VA come into play here? > > It is what spec uses, for example: > Figure 108. Sv39x4 virtual address (guest physical address). Note the difference between what you quote and what your sentence said: You used VA entirely unqualified. Yes, please ... > I can just use GPA. ... use GPA whenever you mean one. Using VA for two distinct purposes is simply confusing. Even the qualifying by the mode is only of limited help imo, as the casual reader may not be fluent in those modes and their acronyms. >> And what is "less VA wide bits"? > > They could be configured to different modes: IOMMU lets say Sv39 and MMU > - Sv48, so IOMMU could work with 39-bit GPA, but MMU - with 48-bit GPAs. I guessed as much, but this wants wording differently. E.g. "... uses fewer GPA bits than ...". >>> @@ -191,8 +209,13 @@ static void __init gstage_mode_detect(void) >>> >>> void __init guest_mm_init(void) >>> { >>> + unsigned int gpa_bits; >>> + unsigned int paging_levels = default_gstage_mode.paging_levels; >> >> Deriving a global from a default, when ... >> >>> gstage_mode_detect(); >>> >>> + ASSERT(default_gstage_mode.paging_levels <= max_gstage_mode.paging_levels); >> >> ... the default isn't the maximum possible, isn't going to fly. > > I didn't get you here. > > If we want Xen uses Sv39 for G-stage, we want to limit guest's 56-bit > GPA to 39-bit GPA, but not the maximum supported by h/w mode for G-stage > mode. I can only repeat what I thought I had got across already on an earlier series of yours: What mode a guest is going to use is going to be a guest property. The default mode therefore isn't the only mode that may be used at runtime. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <691be850-9145-4bbf-a897-d10a0193b730@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1775024265-B78FC185-50929E90/0/0 X-purgate-type: clean X-purgate-size: 4067 On 31.03.2026 18:14, Oleksii Kurochko wrote: > On 3/30/26 5:51 PM, Jan Beulich wrote: >> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>> The dom0less solution uses defined RAM banks as compile-time constants, >>> so introduce macros to describe guest RAM banks. >>> >>> The reason for 2 banks is that there is typically always a use case for >>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>> there are other things under 4 GB it can conflict with (interrupt >>> controller, PCI BARs, etc.). >> >> Fixed layouts like the one you suggest come with (potentially severe) >> downsides. For example, what if more than 2Gb of MMIO space are needed >> for non-64-bit BARs? > > It looks where usually RAM on RISC-V boards start, so I expect that 2gb > before RAM start is enough for MMIO space. Likely in the common case. Board designers aren't constrained by this, though (aiui). Whereas you set in stone a single, fixed layout. Arm maintainers - since a similar fixed layout is used there iirc, could you chime in here, please? > Answering your question it will be an issue or it will also use some > space before banks, no? I fear I don't understand what you're trying to tell me. > Further, assuming that the space 4G...8G is what >> you expect 64-bit BARs to be put into, what if there's a device with a >> 4G BAR? It'll eat up that entire space, requiring everything else to >> fit in the 2G you reserve below 4G. > > I assume that such big devices could use high memory without any issue. Well, I could go (almost) arbitrarily low with individual BAR size, merely increasing the number of BARs accordingly. Assuming 2G BARs are 64-bit capable is likely fine. Maybe the same is true for 1G and 512M ones as well. Yet a some size the assumption will break. IMO RAM layout wants establishing dynamically based on the MMIO needs of a guest. >>> --- a/xen/include/public/arch-riscv.h >>> +++ b/xen/include/public/arch-riscv.h >>> @@ -50,6 +50,22 @@ typedef uint64_t xen_ulong_t; >>> >>> #if defined(__XEN__) || defined(__XEN_TOOLS__) >>> >>> +#define GUEST_RAM_BANKS 2 >>> + >>> +/* >>> + * The way to find the extended regions (to be exposed to the guest as unused >>> + * address space) relies on the fact that the regions reserved for the RAM >>> + * below are big enough to also accommodate such regions. >>> + */ >>> +#define GUEST_RAM0_BASE xen_mk_ullong(0x80000000) /* 2GB of low RAM @ 2GB */ >>> +#define GUEST_RAM0_SIZE xen_mk_ullong(0x80000000) >> >> Connecting this with my comment on the earlier patch regarding kernel, initrd, >> and DTB fitting in bank 0: How's that going to work with a huge kernel and/or >> initrd (I expect DTBs can't grow very large)? > > The short answer it won't, but does initrd usually so big? Not usually, but nothing keeps it from being arbitrary size. > DTB is limited to 2MB, IIRC. So it isn't expect to grow to much... > > As I mentioned in the reply to earlier patch, I agree that we could > leave bank0 for kernel and all other put to bank1. Kernels can also be arbitrarily large. > Even more I can try to put kernel in ban1 as I don't see any place at > the moment where it will be a problem for RISC-V Linux kernel to be in > high memory. Yes, the less restrictions from the beginning, the less worries later. >>> +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016 GB of RAM @ 8GB */ >>> +#define GUEST_RAM1_SIZE xen_mk_ullong(0xFE00000000) >>> + >>> +#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } >>> +#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } >> >> Why's this needed in the public header? > > xl toolstack could use them so I expected what toolstack will use to > live in this header. But these last two #define-s are merely convenience definitions. They even prescribe a certain data layout in order to be usable. I don't think anything like this should be put in the public headers. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8eb8327bfb2f273cd0fa32ba65e84bb79e8607d4.1774863161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775024396-4A84072C-60EA4758/10/73395122804 X-purgate-type: spam X-purgate-size: 725 On 31.03.2026 21:04, Oleksii Kurochko wrote: > There is no reason to use _UL() in define-s sitting in C file hence use UL > suffix instead. > > Drop 3d argument of INIT_CSR_MASK() and INIT_RO_ONE_MASK() to reduce risk > of incomplete editing after copy-and-paste, or other typo-ing. > > Use _VALID_ infix instead of _AVAIL_ as the mask identifies architecturally > defined bits, not bits available for software use. > > Suggested-by: Jan Beulich > Signed-off-by: Oleksii Kurochko > Reviewed-by: Jan Beulich Seeing this is ready to go in, am I overlooking any dependency on earlier patches, or could this indeed go in right away? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 06:29:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 06:29:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269714.1558626 (Exim 4.92) (envelope-from ) id 1w7p4m-0007Hi-Bt; Wed, 01 Apr 2026 06:29:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269714.1558626; Wed, 01 Apr 2026 06:29:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7p4m-0007Hb-98; Wed, 01 Apr 2026 06:29:16 +0000 Received: by outflank-mailman (input) for mailman id 1269714; Wed, 01 Apr 2026 06:29:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7p4k-0007HV-Mt for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 06:29:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7p4j-005R2s-OG for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:29:13 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccbb32-e002-0a2a0a5209dd-0a2a4502c4d4-6 for ; Wed, 01 Apr 2026 08:29:13 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.55.2) (envelope-from ) id 69ccbb39-63bb-0a2a45020019-d1558030ec58-3 for ; Wed, 01 Apr 2026 08:29:13 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-486507134e4so73107455e9.0 for ; Tue, 31 Mar 2026 23:29:13 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775024953-69371DB8-BDD92897/0/0 X-purgate-type: clean X-purgate-size: 2350 On 31.03.2026 20:31, Mykola Kvach wrote: > From: Mykola Kvach > > SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls > using Wn, only the least significant 32 bits are significant and the > upper 32 bits must be ignored by the implementation. > > So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the > argument registers as an error. Instead, they should be discarded when > decoding the arguments. > > Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be > implementation defined when entering from AArch32. Xen zeros them on > entry, but that guarantee is only relevant for 32-bit domains. > > Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND > to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 > handling unchanged. > > No functional change is intended for PSCI 0.1. > > Suggested-by: Julien Grall > Signed-off-by: Mykola Kvach > Reviewed-by: Bertrand Marquis I thought I might as well include this in my next commit sweep, but isn't this R-b being invalidated by ... > --- > v3: > - use PSCI_ARG_CONV for SYSTEM_SUSPEND ... this change. That's ... > @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) > case PSCI_1_0_FN32_SYSTEM_SUSPEND: > case PSCI_1_0_FN64_SYSTEM_SUSPEND: > { > - register_t epoint = PSCI_ARG(regs, 1); > - register_t cid = PSCI_ARG(regs, 2); > - > - if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND ) > - { > - epoint &= GENMASK(31, 0); > - cid &= GENMASK(31, 0); > - } > + register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64); > + register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64); > > perfc_incr(vpsci_system_suspend); > PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid)); ... this hunk aiui, which is far from merely cosmetic imo. While behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended and for the better, but the change clearly wasn't reviewed by Bertrand, nor - when offering the R-b - did he ask for this extra change. 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pr=C Message-ID: <7d4791ee-05cb-490a-a209-a84a6531f0ca@amd.com> Date: Wed, 1 Apr 2026 08:41:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2] xen/arm: Increase DOM0_FDT_EXTRA_SIZE to support max reserved memory banks To: Oleksandr Tyshchenko , "xen-devel@lists.xenproject.org" CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , "Volodymyr Babchuk" References: <20260331154309.2921483-1-oleksandr_tyshchenko@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <20260331154309.2921483-1-oleksandr_tyshchenko@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD74:EE_|DM4PR12MB7600:EE_ X-MS-Office365-Filtering-Correlation-Id: cd99f44a-2846-4afe-7906-08de8fb9bde4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DlQCr94BEl/KEkk5oTQwnoMG2k92x9dzjuBOsMC1G3kANoJI2r2fGEUo5F1cqokj1tanV84IkilF30p5uFpBu5VI6p3Swkxm8KBBw8vrDlRy75ZZZEfFFkjNeSIzPxHIY7XmKhp9yxOWNgfcI/E282J1W862JwzxIPreA/TgprzLPipBoDp8/8ZOr+yC2r4cR2QRP40I6Z2uXHnAQACcpT3ayUaQumZreE94/oS7z9BxDIoH0ocbMtemKXzq6qNBZ37FG05IcANhxgV8b1wnCpd0DgUJvVDnx2VnzY3P09CqI0fvu9VJmIibIep6mF/5JcMYnGx3XKxet/Yw4jCZjcwgu7zyCdIOSnECXw9hfF5kThgv2xTRPQrZj25erOyZvTKYeV0RdCkS9BTCztRHNBIBNkkLssWoF9wBV16BOi9pvO94wjdsRfCsm2GmhnMj X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 06:41:45.0231 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd99f44a-2846-4afe-7906-08de8fb9bde4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD74.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7600 X-purgate-ID: tlsNG-d62444/1775025711-B4358185-4BB7D0BD/0/0 X-purgate-type: clean X-purgate-size: 3402 On 31/03/2026 17:43, Oleksandr Tyshchenko wrote: > From: Oleksandr Tyshchenko > > Xen fails to construct the hardware domain's device tree with > FDT_ERR_NOSPACE (-3) when the host memory map is highly fragmented > (e.g., numerous reserved memory regions) and the host DTB represents > RAM compactly (e.g., a single reg pair or just a few). > > This occurs because DOM0_FDT_EXTRA_SIZE underestimates the space > required for an extra /memory node. While the host DTB might > represent RAM compactly, make_memory_node() aggregates all > reserved regions into a single reg property. With NR_MEM_BANKS (256) > and 64-bit address/size cells, this property can grow up to > 4KB (256 * 16), easily exceeding the space originally occupied by > the host DTB's nodes plus the current padding, thereby overflowing > the allocated buffer. > > Additionally, the SHM regions require space for discrete sub-nodes > under /reserved-memory node, as well as an appendage to the > main /memory node. Each of the up to NR_SHMEM_BANKS (32) regions > triggers the creation of a sub-node with properties (compatible, > reg, xen,id, and xen,offset). These runtime-generated sub-nodes > require approximately 142 bytes each, while the appendage consumes > an additional 16 bytes per region. > > Fix this by increasing DOM0_FDT_EXTRA_SIZE to account for fragmented > reg properties (NR_MEM_BANKS * 16), the discrete SHM sub-nodes, and > the SHM appendage to the /memory node (NR_SHMEM_BANKS * (160 + 16)). > The SHM overhead is conditionally evaluated to avoid over-allocating > memory when CONFIG_STATIC_SHM=n. > > Signed-off-by: Oleksandr Tyshchenko > --- > V2: > - update commit description > - update in-code comment > - update macro > --- > --- > xen/arch/arm/domain_build.c | 18 ++++++++++++++---- > 1 file changed, 14 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 3cd251beed..07f331eac8 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -98,11 +98,21 @@ int __init parse_arch_dom0_param(const char *s, const char *e) > #endif > > /* > - * Amount of extra space required to dom0's device tree. No new nodes > - * are added (yet) but one terminating reserve map entry (16 bytes) is > - * added. > + * Amount of extra space required to dom0's device tree. This covers > + * nodes generated by Xen, which are not directly copied from the host DTB. > + * It is calculated as: > + * - Space for /hypervisor node (128 bytes). > + * - The reserve map terminator (16 bytes). > + * - Space for a generated /memory node covering all possible reserved > + * memory regions (NR_MEM_BANKS * 16). > + * - Space for a generated /reserved-memory node with discrete SHM sub-nodes, > + * plus the appendage to the main /memory node (NR_SHMEM_BANKS * (160 + 16) > + * bytes). This overhead is dropped when CONFIG_STATIC_SHM is disabled. > */ > -#define DOM0_FDT_EXTRA_SIZE (128 + sizeof(struct fdt_reserve_entry)) > +#define DOM0_FDT_EXTRA_SIZE (128 + sizeof(struct fdt_reserve_entry) + \ > + (NR_MEM_BANKS * 16) + \ NIT: alignment. I'll fix on commit Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 01 06:43:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 06:43:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269733.1558643 (Exim 4.92) (envelope-from ) id 1w7pIm-0002Qu-OJ; Wed, 01 Apr 2026 06:43:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269733.1558643; Wed, 01 Apr 2026 06:43:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pIm-0002Qn-LP; Wed, 01 Apr 2026 06:43:44 +0000 Received: by outflank-mailman (input) for mailman id 1269733; Wed, 01 Apr 2026 06:43:44 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pIl-0002Qh-OC for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 06:43:44 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7pIl-0037F1-2Y for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:43:43 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccbe97-bab6-0a2a0a5309dd-0a2a450ac3bc-38 for ; Wed, 01 Apr 2026 08:43:43 +0200 Received: from [209.85.208.51] (helo=mail-ed1-f51.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.55.2) (envelope-from ) id 69ccbe9e-1772-0a2a450a0019-d155d033e88c-3 for ; Wed, 01 Apr 2026 08:43:43 +0200 Received: by mail-ed1-f51.google.com with SMTP id 4fb4d7f45d1cf-66c05fb27e4so4354828a12.2 for ; Tue, 31 Mar 2026 23:43:42 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Some users treat is_shutting_down narrowly as "shutdown still needs to be driven to completion", while others rely on it more broadly as "the domain is no longer in its normal running state". Make the lifecycle explicit by introducing enum domain_shutdown_state and helper predicates whose names match their semantics: domain_shutting_down() for the transient phase, domain_shutdown_completed() for the final state, and domain_in_shutdown_state() for checks that need the union of both. The conversion is intentionally not mechanical. The old flags were not mutually exclusive: once a domain became fully shut down, is_shutting_down remained set. As a result, sites that previously used the absence of is_shutting_down to exclude both the transient and completed states now use domain_in_shutdown_state(), sites that care specifically about the final state use domain_shutdown_completed(), and only paths that still have work to do before shutdown finalization use domain_shutting_down(). At the same time, make domain_resume() validate its input state and return an error to its callers. Resume is now accepted only from the fully shut down state. This removes the implicit coupling between unrelated users of the old flags and makes the shutdown/resume transitions self-describing. Suggested-by: Jan Beulich Signed-off-by: Mykola Kvach Reviewed-by: Michal Orzel --- Changes in v2: - Drop the shutdown reason restrictions from domain_resume(), so the validation remains compatible with the existing soft-reset flow. - Use clearer helper naming for the three shutdown-state predicates. - Document in the commit message how old is_shutting_down/is_shut_down users map to the new shutdown-state helpers. - Fix label indentation noted during review. Link to discussion: https://patchew.org/Xen/cover.1756392094.git.mykola._5Fkvach@epam.com/bb53d9911b00879c7b25f5258d0e3e48005671f9.1756392094.git.mykola._5Fkvach@epam.com/#a64cff9f-df5f-467b-a944-74e803c64ab9@suse.com --- xen/arch/x86/hvm/viridian/time.c | 2 +- xen/arch/x86/mm.c | 2 +- xen/arch/x86/mm/hap/hap.c | 2 +- xen/arch/x86/mm/shadow/common.c | 5 ++-- xen/arch/x86/mm/shadow/multi.c | 12 +++++---- xen/common/domain.c | 43 +++++++++++++++++++++++--------- xen/common/domctl.c | 4 +-- xen/common/sched/core.c | 2 +- xen/drivers/passthrough/iommu.c | 8 +++--- xen/drivers/passthrough/pci.c | 2 +- xen/include/xen/sched.h | 30 ++++++++++++++++++---- 11 files changed, 77 insertions(+), 35 deletions(-) diff --git a/xen/arch/x86/hvm/viridian/time.c b/xen/arch/x86/hvm/viridian/time.c index 9311858d63..514b1643bc 100644 --- a/xen/arch/x86/hvm/viridian/time.c +++ b/xen/arch/x86/hvm/viridian/time.c @@ -102,7 +102,7 @@ static void time_ref_count_thaw(const struct domain *d) struct viridian_domain *vd = d->arch.hvm.viridian; struct viridian_time_ref_count *trc = &vd->time_ref_count; - if ( d->is_shutting_down || + if ( domain_in_shutdown_state(d) || test_and_set_bit(_TRC_running, &trc->flags) ) return; diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index 4c404b6c13..402bbf2309 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -1219,7 +1219,7 @@ void put_page_from_l1e(l1_pgentry_t l1e, struct domain *l1e_owner) */ #if _PAGE_GNTTAB if ( (l1e_get_flags(l1e) & _PAGE_GNTTAB) && - !l1e_owner->is_shutting_down && !l1e_owner->is_dying ) + !domain_in_shutdown_state(l1e_owner) && !l1e_owner->is_dying ) { gprintk(XENLOG_WARNING, "Attempt to implicitly unmap %pd's grant PTE %" PRIpte "\n", diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5..9db6d8fa9e 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -414,7 +414,7 @@ static mfn_t hap_make_monitor_table(struct vcpu *v) oom: if ( !d->is_dying && - (!d->is_shutting_down || d->shutdown_code != SHUTDOWN_crash) ) + (!domain_in_shutdown_state(d) || d->shutdown_code != SHUTDOWN_crash) ) { printk(XENLOG_G_ERR "%pd: out of memory building monitor pagetable\n", d); diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/common.c index dd2d04d049..14f808dc61 100644 --- a/xen/arch/x86/mm/shadow/common.c +++ b/xen/arch/x86/mm/shadow/common.c @@ -164,7 +164,7 @@ void shadow_promote(struct domain *d, mfn_t gmfn, unsigned int type) /* We should never try to promote a gmfn that has writeable mappings */ ASSERT((page->u.inuse.type_info & PGT_type_mask) != PGT_writable_page || (page->u.inuse.type_info & PGT_count_mask) == 0 - || d->is_shutting_down); + || domain_in_shutdown_state(d)); /* Is the page already shadowed? */ if ( !test_and_set_bit(_PGC_shadowed_pt, &page->count_info) ) @@ -442,7 +442,8 @@ bool shadow_prealloc(struct domain *d, unsigned int type, unsigned int count) count += paging_logdirty_levels(); ret = _shadow_prealloc(d, count); - if ( !ret && (!d->is_shutting_down || d->shutdown_code != SHUTDOWN_crash) ) + if ( !ret && (!domain_in_shutdown_state(d) || + d->shutdown_code != SHUTDOWN_crash) ) /* * Failing to allocate memory required for shadow usage can only result in * a domain crash, do it here rather that relying on every caller to do it. diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 80cd3299fa..a1e9129dd8 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -2373,7 +2373,8 @@ static int cf_check sh_page_fault( * already used for some special purpose (ioreq pages, or granted pages). * If that happens we'll have killed the guest already but it's still not * safe to propagate entries out of the guest PT so get out now. */ - if ( unlikely(d->is_shutting_down && d->shutdown_code == SHUTDOWN_crash) ) + if ( unlikely(domain_in_shutdown_state(d) && + d->shutdown_code == SHUTDOWN_crash) ) { SHADOW_PRINTK("guest is shutting down\n"); goto propagate; @@ -2483,7 +2484,7 @@ static int cf_check sh_page_fault( #if GUEST_PAGING_LEVELS == 3 sh_update_cr3(v, false); #else - ASSERT(d->is_shutting_down); + ASSERT(domain_in_shutdown_state(d)); sh_trace_va(TRC_SHADOW_DOMF_DYING, va); #endif paging_unlock(d); @@ -2497,7 +2498,8 @@ static int cf_check sh_page_fault( && ft == ft_demand_write ) sh_unsync(v, gmfn); - if ( unlikely(d->is_shutting_down && d->shutdown_code == SHUTDOWN_crash) ) + if ( unlikely(domain_in_shutdown_state(d) && + d->shutdown_code == SHUTDOWN_crash) ) { /* We might end up with a crashed domain here if * sh_remove_shadows() in a previous sh_resync() call has @@ -3269,7 +3271,7 @@ static pagetable_t cf_check sh_update_cr3(struct vcpu *v, bool noflush) sh_make_shadow); if ( unlikely(pagetable_is_null(v->arch.paging.shadow.shadow_table[0])) ) { - ASSERT(d->is_dying || d->is_shutting_down); + ASSERT(d->is_dying || domain_in_shutdown_state(d)); return old_entry; } if ( !paging_mode_external(d) && !is_pv_32bit_domain(d) ) @@ -3336,7 +3338,7 @@ static pagetable_t cf_check sh_update_cr3(struct vcpu *v, bool noflush) ASSERT(pagetable_is_null(old_entry)); if ( unlikely(pagetable_is_null(v->arch.paging.shadow.shadow_table[0])) ) { - ASSERT(d->is_dying || d->is_shutting_down); + ASSERT(d->is_dying || domain_in_shutdown_state(d)); return old_entry; } #else diff --git a/xen/common/domain.c b/xen/common/domain.c index bb9e210c28..503836872d 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -191,7 +191,7 @@ static void set_domain_state_info(struct xen_domctl_get_domain_state *info, const struct domain *d) { info->state = XEN_DOMCTL_GETDOMSTATE_STATE_EXIST; - if ( d->is_shut_down ) + if ( domain_shutdown_completed(d) ) info->state |= XEN_DOMCTL_GETDOMSTATE_STATE_SHUTDOWN; if ( d->is_dying == DOMDYING_dying ) info->state |= XEN_DOMCTL_GETDOMSTATE_STATE_DYING; @@ -282,14 +282,14 @@ static void __domain_finalise_shutdown(struct domain *d) BUG_ON(!spin_is_locked(&d->shutdown_lock)); - if ( d->is_shut_down ) + if ( domain_shutdown_completed(d) ) return; for_each_vcpu ( d, v ) if ( !v->paused_for_shutdown ) return; - d->is_shut_down = 1; + d->shutdown_state = DOMSHUTDOWN_complete; domain_changed_state(d); if ( (d->shutdown_code == SHUTDOWN_suspend) && d->suspend_evtchn ) evtchn_send(d, d->suspend_evtchn); @@ -303,7 +303,7 @@ static void vcpu_check_shutdown(struct vcpu *v) spin_lock(&d->shutdown_lock); - if ( d->is_shutting_down ) + if ( domain_shutting_down(d) ) { if ( !v->paused_for_shutdown ) vcpu_pause_nosync(v); @@ -1356,7 +1356,7 @@ int domain_kill(struct domain *d) void __domain_crash(struct domain *d) { - if ( d->is_shutting_down ) + if ( domain_in_shutdown_state(d) ) { /* Print nothing: the domain is already shutting down. */ } @@ -1394,13 +1394,13 @@ int domain_shutdown(struct domain *d, u8 reason) if ( is_hardware_domain(d) ) hwdom_shutdown(reason); - if ( d->is_shutting_down ) + if ( domain_in_shutdown_state(d) ) { spin_unlock(&d->shutdown_lock); return 0; } - d->is_shutting_down = 1; + d->shutdown_state = DOMSHUTDOWN_in_progress; smp_mb(); /* set shutdown status /then/ check for per-cpu deferrals */ @@ -1423,9 +1423,12 @@ int domain_shutdown(struct domain *d, u8 reason) return 0; } -void domain_resume(struct domain *d) +int domain_resume(struct domain *d) { struct vcpu *v; + enum domain_shutdown_state shutdown_state; + unsigned int shutdown_code; + int rc = 0; /* * Some code paths assume that shutdown status does not get reset under @@ -1435,10 +1438,18 @@ void domain_resume(struct domain *d) spin_lock(&d->shutdown_lock); - d->is_shutting_down = d->is_shut_down = 0; + shutdown_state = d->shutdown_state; + shutdown_code = d->shutdown_code; + + if ( !domain_shutdown_completed(d) ) + { + rc = -EINVAL; + goto out_unlock; + } arch_domain_resume(d); + d->shutdown_state = DOMSHUTDOWN_none; d->shutdown_code = SHUTDOWN_CODE_INVALID; for_each_vcpu ( d, v ) @@ -1448,9 +1459,17 @@ void domain_resume(struct domain *d) v->paused_for_shutdown = 0; } + out_unlock: spin_unlock(&d->shutdown_lock); domain_unpause(d); + + if ( rc ) + dprintk(XENLOG_WARNING, + "%pd: Invalid domain state for resume: shutdown_state=%u, shutdown_code=%u\n", + d, shutdown_state, shutdown_code); + + return rc; } int vcpu_start_shutdown_deferral(struct vcpu *v) @@ -1460,7 +1479,7 @@ int vcpu_start_shutdown_deferral(struct vcpu *v) v->defer_shutdown = 1; smp_mb(); /* set deferral status /then/ check for shutdown */ - if ( unlikely(v->domain->is_shutting_down) ) + if ( unlikely(domain_shutting_down(v->domain)) ) vcpu_check_shutdown(v); return v->defer_shutdown; @@ -1470,7 +1489,7 @@ void vcpu_end_shutdown_deferral(struct vcpu *v) { v->defer_shutdown = 0; smp_mb(); /* clear deferral status /then/ check for shutdown */ - if ( unlikely(v->domain->is_shutting_down) ) + if ( unlikely(domain_shutting_down(v->domain)) ) vcpu_check_shutdown(v); } @@ -1802,7 +1821,7 @@ int domain_soft_reset(struct domain *d, bool resuming) rc = arch_domain_soft_reset(d); if ( !rc ) - domain_resume(d); + rc = domain_resume(d); else domain_crash(d); diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 93738931c5..e816ff755c 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -86,7 +86,7 @@ void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) info->flags = (info->nr_online_vcpus ? flags : 0) | ((d->is_dying == DOMDYING_dead) ? XEN_DOMINF_dying : 0) | - (d->is_shut_down ? XEN_DOMINF_shutdown : 0) | + (domain_shutdown_completed(d) ? XEN_DOMINF_shutdown : 0) | (d->controller_pause_count > 0 ? XEN_DOMINF_paused : 0) | (d->debugger_attached ? XEN_DOMINF_debugged : 0) | (is_xenstore_domain(d) ? XEN_DOMINF_xs_domain : 0) | @@ -404,7 +404,7 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) if ( d == current->domain ) /* no domain_pause() */ ret = -EINVAL; else - domain_resume(d); + ret = domain_resume(d); break; case XEN_DOMCTL_createdomain: diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index a57d5dd929..26cdb8a857 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -1540,7 +1540,7 @@ static void cf_check domain_watchdog_timeout(void *data) BUILD_BUG_ON(alignof(*d) < PAGE_SIZE); - if ( d->is_shutting_down || d->is_dying ) + if ( domain_in_shutdown_state(d) || d->is_dying ) return; printk("Watchdog timer %u fired for %pd\n", id, d); diff --git a/xen/drivers/passthrough/iommu.c b/xen/drivers/passthrough/iommu.c index c9425d6971..428ac89f50 100644 --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -355,7 +355,7 @@ long iommu_map(struct domain *d, dfn_t dfn0, mfn_t mfn0, if ( likely(!rc) ) continue; - if ( !d->is_shutting_down && printk_ratelimit() ) + if ( !domain_in_shutdown_state(d) && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU mapping dfn %"PRI_dfn" to mfn %"PRI_mfn" failed: %d\n", d->domain_id, dfn_x(dfn), mfn_x(mfn), rc); @@ -427,7 +427,7 @@ long iommu_unmap(struct domain *d, dfn_t dfn0, unsigned long page_count, if ( likely(!err) ) continue; - if ( !d->is_shutting_down && printk_ratelimit() ) + if ( !domain_in_shutdown_state(d) && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU unmapping dfn %"PRI_dfn" failed: %d\n", d->domain_id, dfn_x(dfn), err); @@ -492,7 +492,7 @@ int iommu_iotlb_flush(struct domain *d, dfn_t dfn, unsigned long page_count, flush_flags); if ( unlikely(rc) ) { - if ( !d->is_shutting_down && printk_ratelimit() ) + if ( !domain_in_shutdown_state(d) && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU IOTLB flush failed: %d, dfn %"PRI_dfn", page count %lu flags %x\n", d->domain_id, rc, dfn_x(dfn), page_count, flush_flags); @@ -517,7 +517,7 @@ int iommu_iotlb_flush_all(struct domain *d, unsigned int flush_flags) flush_flags | IOMMU_FLUSHF_all); if ( unlikely(rc) ) { - if ( !d->is_shutting_down && printk_ratelimit() ) + if ( !domain_in_shutdown_state(d) && printk_ratelimit() ) printk(XENLOG_ERR "d%d: IOMMU IOTLB flush all failed: %d\n", d->domain_id, rc); diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 464bb0fee4..74b53e5430 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -1746,7 +1746,7 @@ void iommu_dev_iotlb_flush_timeout(struct domain *d, struct pci_dev *pdev) pdev->broken = true; - if ( !d->is_shutting_down && printk_ratelimit() ) + if ( !domain_in_shutdown_state(d) && printk_ratelimit() ) printk(XENLOG_ERR "dom%d: ATS device %pp flush failed\n", d->domain_id, &pdev->sbdf); if ( !is_hardware_domain(d) ) diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c..0e55e4df3b 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -222,7 +222,7 @@ struct vcpu bool force_context_switch; /* Require shutdown to be deferred for some asynchronous operation? */ bool defer_shutdown; - /* VCPU is paused following shutdown request (d->is_shutting_down)? */ + /* VCPU is paused following a domain shutdown request? */ bool paused_for_shutdown; /* VCPU need affinity restored */ uint8_t affinity_broken; @@ -382,6 +382,12 @@ struct domain_console { char buf[256]; }; +enum domain_shutdown_state { + DOMSHUTDOWN_none, + DOMSHUTDOWN_in_progress, + DOMSHUTDOWN_complete, +}; + struct domain { domid_t domain_id; @@ -548,10 +554,9 @@ struct domain struct rangeset *iomem_caps; struct rangeset *irq_caps; - /* Guest has shut down (inc. reason code)? */ + /* Guest shutdown state and associated reason code. */ spinlock_t shutdown_lock; - bool is_shutting_down; /* in process of shutting down? */ - bool is_shut_down; /* fully shut down? */ + enum domain_shutdown_state shutdown_state; #define SHUTDOWN_CODE_INVALID ~0u unsigned int shutdown_code; @@ -670,6 +675,21 @@ struct domain unsigned int pending_scrub_index; } __aligned(PAGE_SIZE); +static inline bool domain_shutting_down(const struct domain *d) +{ + return d->shutdown_state == DOMSHUTDOWN_in_progress; +} + +static inline bool domain_shutdown_completed(const struct domain *d) +{ + return d->shutdown_state == DOMSHUTDOWN_complete; +} + +static inline bool domain_in_shutdown_state(const struct domain *d) +{ + return d->shutdown_state != DOMSHUTDOWN_none; +} + static inline struct page_list_head *page_to_list( struct domain *d, const struct page_info *pg) { @@ -824,7 +844,7 @@ static inline void put_pg_owner(struct domain *pg_owner) void domain_destroy(struct domain *d); int domain_kill(struct domain *d); int domain_shutdown(struct domain *d, u8 reason); -void domain_resume(struct domain *d); +int domain_resume(struct domain *d); int domain_soft_reset(struct domain *d, bool resuming); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 06:44:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 06:44:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269743.1558653 (Exim 4.92) (envelope-from ) id 1w7pJS-0002yT-4s; Wed, 01 Apr 2026 06:44:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269743.1558653; Wed, 01 Apr 2026 06:44:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pJS-0002yM-1O; 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pr=C Message-ID: Date: Wed, 1 Apr 2026 08:44:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2] xen/arm: Increase DOM0_FDT_EXTRA_SIZE to support max reserved memory banks From: "Orzel, Michal" To: Oleksandr Tyshchenko , "xen-devel@lists.xenproject.org" CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk References: <20260331154309.2921483-1-oleksandr_tyshchenko@epam.com> <7d4791ee-05cb-490a-a209-a84a6531f0ca@amd.com> Content-Language: en-US In-Reply-To: <7d4791ee-05cb-490a-a209-a84a6531f0ca@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|DS4PR12MB9634:EE_ X-MS-Office365-Filtering-Correlation-Id: a1a802fa-ebaf-4aab-ed74-08de8fba177f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5ZiNp6qcXxS7/WLJqwbEy6Z60boiUJvTMXPh7WybokqWrPmWNtASG/08ocJk7mY1hNgWflOZ2oYylKO4lG55vCDeTQlxPp3D/a5trMfuQZHhK0WkE/ELYNbDvMLab6T+G8wNehwBswL3phPHmqRXYzMi70/oGQaIZTizugkrgpddIOeAiiF+TIjqlMKpFuGJafN9LL57J88jsM7M5pVyBpTivVyIGOkCakIGQ6SWul2HugHDmLBA7I4omZpb0mclshpGrBHjFKgMYE2AwqBECPXIJpVOeKHQrHyY7iobV84h7YCt6C5ppngJ5G3dai6jBVYQR1DVnCQhmR7hq7gFXgIfElInlaO33w9TPjiOG3X+xV86TY+1vYH3aziPjybb7nxvolvsNzQtaO3jYXl0822fy0C86YK3pBRAPpEK2LJdheKzKaTCITYL8LXOgRk6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 06:44:15.3673 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1a802fa-ebaf-4aab-ed74-08de8fba177f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9634 X-purgate-ID: tlsNG-bad1c0/1775025863-69D44A73-921CC7FD/0/0 X-purgate-type: clean X-purgate-size: 3593 On 01/04/2026 08:41, Orzel, Michal wrote: > > > On 31/03/2026 17:43, Oleksandr Tyshchenko wrote: >> From: Oleksandr Tyshchenko >> >> Xen fails to construct the hardware domain's device tree with >> FDT_ERR_NOSPACE (-3) when the host memory map is highly fragmented >> (e.g., numerous reserved memory regions) and the host DTB represents >> RAM compactly (e.g., a single reg pair or just a few). >> >> This occurs because DOM0_FDT_EXTRA_SIZE underestimates the space >> required for an extra /memory node. While the host DTB might >> represent RAM compactly, make_memory_node() aggregates all >> reserved regions into a single reg property. With NR_MEM_BANKS (256) >> and 64-bit address/size cells, this property can grow up to >> 4KB (256 * 16), easily exceeding the space originally occupied by >> the host DTB's nodes plus the current padding, thereby overflowing >> the allocated buffer. >> >> Additionally, the SHM regions require space for discrete sub-nodes >> under /reserved-memory node, as well as an appendage to the >> main /memory node. Each of the up to NR_SHMEM_BANKS (32) regions >> triggers the creation of a sub-node with properties (compatible, >> reg, xen,id, and xen,offset). These runtime-generated sub-nodes >> require approximately 142 bytes each, while the appendage consumes >> an additional 16 bytes per region. >> >> Fix this by increasing DOM0_FDT_EXTRA_SIZE to account for fragmented >> reg properties (NR_MEM_BANKS * 16), the discrete SHM sub-nodes, and >> the SHM appendage to the /memory node (NR_SHMEM_BANKS * (160 + 16)). >> The SHM overhead is conditionally evaluated to avoid over-allocating >> memory when CONFIG_STATIC_SHM=n. >> >> Signed-off-by: Oleksandr Tyshchenko >> --- >> V2: >> - update commit description >> - update in-code comment >> - update macro >> --- >> --- >> xen/arch/arm/domain_build.c | 18 ++++++++++++++---- >> 1 file changed, 14 insertions(+), 4 deletions(-) >> >> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c >> index 3cd251beed..07f331eac8 100644 >> --- a/xen/arch/arm/domain_build.c >> +++ b/xen/arch/arm/domain_build.c >> @@ -98,11 +98,21 @@ int __init parse_arch_dom0_param(const char *s, const char *e) >> #endif >> >> /* >> - * Amount of extra space required to dom0's device tree. No new nodes >> - * are added (yet) but one terminating reserve map entry (16 bytes) is >> - * added. >> + * Amount of extra space required to dom0's device tree. This covers >> + * nodes generated by Xen, which are not directly copied from the host DTB. >> + * It is calculated as: >> + * - Space for /hypervisor node (128 bytes). >> + * - The reserve map terminator (16 bytes). >> + * - Space for a generated /memory node covering all possible reserved >> + * memory regions (NR_MEM_BANKS * 16). >> + * - Space for a generated /reserved-memory node with discrete SHM sub-nodes, >> + * plus the appendage to the main /memory node (NR_SHMEM_BANKS * (160 + 16) >> + * bytes). This overhead is dropped when CONFIG_STATIC_SHM is disabled. >> */ >> -#define DOM0_FDT_EXTRA_SIZE (128 + sizeof(struct fdt_reserve_entry)) >> +#define DOM0_FDT_EXTRA_SIZE (128 + sizeof(struct fdt_reserve_entry) + \ >> + (NR_MEM_BANKS * 16) + \ > NIT: alignment. I'll fix on commit Never mind, the alignment is in fact correct. ~Michal > > Reviewed-by: Michal Orzel > > ~Michal > > From xen-devel-bounces@lists.xenproject.org Wed Apr 01 06:46:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 06:46:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269755.1558661 (Exim 4.92) (envelope-from ) id 1w7pLD-0003Ym-EH; Wed, 01 Apr 2026 06:46:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269755.1558661; Wed, 01 Apr 2026 06:46:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pLD-0003Yf-Bh; Wed, 01 Apr 2026 06:46:15 +0000 Received: by outflank-mailman (input) for mailman id 1269755; Wed, 01 Apr 2026 06:46:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pLC-0003YZ-8o for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Wed, 1 Apr 2026 08:46:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH test-artifacts v3 02/13] Switch Linux builds to use Alpine 3.22 container To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , CC: Andrew Cooper , Stefano Stabellini , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <652a2f219b370af5364d8ef29264acc33a89f676.1774999132.git-series.marmarek@invisiblethingslab.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <652a2f219b370af5364d8ef29264acc33a89f676.1774999132.git-series.marmarek@invisiblethingslab.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|BY5PR12MB4177:EE_ X-MS-Office365-Filtering-Correlation-Id: a60293a3-52a3-4a06-6c33-08de8fba59c0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|22082099003|56012099003; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="xz4EeMhth/eSiNsR" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-d62444/1775026688-BC766185-D48C7004/0/0 X-purgate-type: clean X-purgate-size: 2474 --xz4EeMhth/eSiNsR Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 1 Apr 2026 08:58:04 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: "Orzel, Michal" Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH test-artifacts v3 02/13] Switch Linux builds to use Alpine 3.22 container On Wed, Apr 01, 2026 at 08:46:02AM +0200, Orzel, Michal wrote: > Why not 3.23 if it's already there? Because it wasn't yet when I prepared this patch series :) I can update again and see if any other changes are needed with 3.23. Other patches are independent of this change. >=20 > ~Michal >=20 > On 01/04/2026 01:21, Marek Marczykowski-G=C3=B3recki wrote: > > Slowly phase out 3.18 one. > >=20 > > Signed-off-by: Marek Marczykowski-G=C3=B3recki > > --- > > .gitlab-ci.yml | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > >=20 > > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > > index 17d25ce0f921..36622c723ce9 100644 > > --- a/.gitlab-ci.yml > > +++ b/.gitlab-ci.yml > > @@ -21,14 +21,14 @@ stages: > > tags: > > - arm64 > > variables: > > - CONTAINER: alpine:3.18-arm64-build > > + CONTAINER: alpine:3.22-arm64-build > > =20 > > .x86_64-artifacts: > > extends: .artifacts > > tags: > > - x86_64 > > variables: > > - CONTAINER: alpine:3.18-x86_64-build > > + CONTAINER: alpine:3.22-x86_64-build > > =20 > > # > > # ARM64 artifacts >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --xz4EeMhth/eSiNsR Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnMwfwACgkQ24/THMrX 1yx4Mgf9HlomCIgdYQGzIcdVZXpF299QHlto6g1BSy6RnqxZqtqjI4ry+0Y1QLTJ u414KT2mvB84qGWi2FpKeYvrEm2hGCgo1i3axkV3mc8/S8wfuZXvwF4ukwfbB8Mp ozqPW0br0pZlwjZstfZeSCmn8ZYgR3tKmtgUrXlRK2Fsp1amiAOdLrAwg1ZnQnw1 LyBxl2Y7ZcTqA6JxeVjDuE9YSLXfxYNJV/Qm2trxe/mXWEwcgdhX0RLO8fP/s/t9 v1041rd5Vu+LT/dhy6KbRlPyTVaBXqass8ZCBaLvwHmaAn0WL3wDvZLvPDQ5eKTp Y6FCrLysovLd6Eg6ioV2HkQLSfBdgg== =oXm3 -----END PGP SIGNATURE----- --xz4EeMhth/eSiNsR-- From xen-devel-bounces@lists.xenproject.org Wed Apr 01 07:13:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 07:13:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269785.1558680 (Exim 4.92) (envelope-from ) id 1w7plU-0000xr-Qm; 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AJvYcCUQG5iiZDwaWKpY+sx8XwHLjH1caBKH9oFb5zkfUlGaxbrrWOznQh181nz99lzIfSel9h7GsXzsLVc=@lists.xenproject.org X-Gm-Message-State: AOJu0YxBeWDnwsbL8fXVULHYOvmpPst8U7sf54veiscou4KsJ8e3Ikor 2hiLHpK0+yVQ9hLWvc/6Ofi277WD23Bu33qzdjsiP6elfIWwnb3EI3Y9UFnar3hKm7rV7fZfgzX SlwTwKSnhVGUJbRuprcXoBXVJJu9EdAlOoLVsR6A= X-Gm-Gg: ATEYQzwmyTqyjQwyDsxSG4aKMupN3ot1QoaR8335cL8QbOeO2kom4fEyyjVXVyBu+r6 n12EVifzDjgoJr+hNuhnMPrY0KdETOUJVQOmhpak/PMaMAtZ474yXCuMispuScYU6TB4KBXppew x4iYvprZSBIIIpm+IswQad6gpOZ+CuTWcbE1hWMwgqGdtSChfzAM59Cpcej63Dt1DdklUwS7Qid 00CE+9Qy0rcI6Oh8ixSZXtD55fx5v/nY0WhGqIjQQOnGqZ9962MD/VQV35XqxN8hSjSSN604/vm LMVo X-Received: by 2002:a05:6512:130e:b0:5a1:3d21:7b55 with SMTP id 2adb3069b0e04-5a2c1f35119mr866631e87.43.1775027601442; Wed, 01 Apr 2026 00:13:21 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Mykola Kvach Date: Wed, 1 Apr 2026 10:13:10 +0300 X-Gm-Features: AQROBzCsqScaJPrS9xoojwVZMluMyQDN-QvbeXLOZ0pzS5-wjtEVSbvt33Yg_BE Message-ID: Subject: Re: [PATCH v3] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments To: Jan Beulich Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , xen-devel@lists.xenproject.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1775027602-815891C2-D0B242C1/0/0 X-purgate-type: clean X-purgate-size: 3702 Hi Jan, On Wed, Apr 1, 2026 at 9:29=E2=80=AFAM Jan Beulich wrot= e: > > On 31.03.2026 20:31, Mykola Kvach wrote: > > From: Mykola Kvach > > > > SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls > > using Wn, only the least significant 32 bits are significant and the > > upper 32 bits must be ignored by the implementation. > > > > So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the > > argument registers as an error. Instead, they should be discarded when > > decoding the arguments. > > > > Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be > > implementation defined when entering from AArch32. Xen zeros them on > > entry, but that guarantee is only relevant for 32-bit domains. > > > > Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND > > to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 > > handling unchanged. > > > > No functional change is intended for PSCI 0.1. > > > > Suggested-by: Julien Grall > > Signed-off-by: Mykola Kvach > > Reviewed-by: Bertrand Marquis > > I thought I might as well include this in my next commit sweep, but isn't > this R-b being invalidated by ... > > > --- > > v3: > > - use PSCI_ARG_CONV for SYSTEM_SUSPEND > > ... this change. That's ... > > > @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs,= uint32_t fid) > > case PSCI_1_0_FN32_SYSTEM_SUSPEND: > > case PSCI_1_0_FN64_SYSTEM_SUSPEND: > > { > > - register_t epoint =3D PSCI_ARG(regs, 1); > > - register_t cid =3D PSCI_ARG(regs, 2); > > - > > - if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND ) > > - { > > - epoint &=3D GENMASK(31, 0); > > - cid &=3D GENMASK(31, 0); > > - } > > + register_t epoint =3D PSCI_ARG_CONV(regs, 1, is_conv_64); > > + register_t cid =3D PSCI_ARG_CONV(regs, 2, is_conv_64); > > > > perfc_incr(vpsci_system_suspend); > > PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid))= ; > > ... this hunk aiui, which is far from merely cosmetic imo. While Nobody said that the change had to be purely cosmetic in order to keep the tag. I understood it differently from the official Xen documentation pages. > behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it Exactly. If the changes are not substantial, I do not see a reason to drop the tag ... > clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended > and for the better, but the change clearly wasn't reviewed by Bertrand, > nor - when offering the R-b - did he ask for this extra change. ... and this is also how I understood the Xen patch submission guidelines [1], which say: "Note that if there are several revisions of a patch, you ought to copy tags that have accumulated during the review. For example, if person A and person B added a Reviewed-by: tag to v1 of your patch, include it into v2 of your patch. If you make substantial changes after certain tags were already applied, you will want to consider which ones are no longer applicable (and may require re-providing)." So my understanding was that tags should normally be kept across revisions, unless the changes are substantial enough to make them no longer applicable. In any case, if you do not think the tag should be kept, I am fine with waiting for Bertrand to re-confirm it. Best regards, Mykola [1] https://wiki.xenproject.org/wiki/Submitting_Xen_Project_Patches > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 07:14:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 07:14:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269792.1558689 (Exim 4.92) (envelope-from ) id 1w7pmV-0001QV-4K; Wed, 01 Apr 2026 07:14:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269792.1558689; Wed, 01 Apr 2026 07:14:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pmV-0001QF-0w; Wed, 01 Apr 2026 07:14:27 +0000 Received: by outflank-mailman (input) for mailman id 1269792; Wed, 01 Apr 2026 07:14:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7pmT-0001PJ-Oa for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 07:14:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7pmT-005clS-49 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 09:14:25 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccc5cd-2eae-0a2a0a5409dd-0a2a4506809e-34 for ; Wed, 01 Apr 2026 09:14:25 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.55.2) (envelope-from ) id 69ccc5d0-3034-0a2a45060019-d1558030ddbc-3 for ; Wed, 01 Apr 2026 09:14:24 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4887f49ec5aso19709285e9.1 for ; Wed, 01 Apr 2026 00:14:24 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 01 Apr 2026 00:14:24 -0700 (PDT) Message-ID: Date: Wed, 1 Apr 2026 09:14:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= References: Content-Language: en-US Cc: xen-devel From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775027664-B3A981C2-67D247F9/0/0 X-purgate-type: clean X-purgate-size: 2572 On 27.03.2026 11:19, Marek Marczykowski-Górecki wrote: > I noticed that on some systems, there are a lot of IOMMU faults after > S3. I can see it also on a laptop with MTL, but it affects also the ADL > gitlab runner: > > https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 > (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 > (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear > (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 > (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear > > Interestingly, the 0000:00:1e.6 device is not even listed by lspci. > > The issue is present only on staging, not staging-4.21. > > Bisect says: > > 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit > commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b > Author: Jan Beulich > Date: Thu Jan 22 14:13:35 2026 +0100 > > x86/HPET: drop .set_affinity hook Looking into this, I find several things I can't quite understand (yet). First there is (XEN) [000000456c0fe39f] Disabling HPET for being unreliable which looks to only affect clocksource selection, but not use as broadcast source for CPU-idle management. (This may be an independent issue.) Then there is (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) which should only occur on ARAT-incapable systems. That should only be older hardware. (On my much older Skylake I don't see this line, for example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid is purely featureset based, and hence doesn't expose info about that leaf. The leaf also isn't exposed to domains, so CPUID output in Dom0 isn't useful to look at either. It would need to be CPUID output on a bare metal kernel. Further I suspect the fingered commit may only have uncovered an issue elsewhere. I don't think we clear any context table entries during suspend or resume. Hence in (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context entry is clear the latter message is confusing me. The fault address being zero may, otoh, be a hint of hpet_msi_write() never having run post-resume. Which may be the connection to the dropping of hpet_msi_set_affinity(), as that did call that function. I'll continue looking in that direction as a first step. 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I can see it also on a laptop with MTL, but it affects also the ADL >> gitlab runner: >> >> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 >> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >> >> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. >> >> The issue is present only on staging, not staging-4.21. >> >> Bisect says: >> >> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit >> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b >> Author: Jan Beulich >> Date: Thu Jan 22 14:13:35 2026 +0100 >> >> x86/HPET: drop .set_affinity hook > Looking into this, I find several things I can't quite understand (yet). > First there is > > (XEN) [000000456c0fe39f] Disabling HPET for being unreliable > > which looks to only affect clocksource selection, but not use as > broadcast source for CPU-idle management. (This may be an independent > issue.) > > Then there is > > (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) > > which should only occur on ARAT-incapable systems. That should only be > older hardware. I'm not sure that's a reasonable assertion to draw.  The number of HPET channels is down to the HPET alone, not anything to do with the CPU capabilities. > (On my much older Skylake I don't see this line, for > example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid > is purely featureset based, and hence doesn't expose info about that > leaf. xen-cpuid -p That will get you leaf 6, but there's no human-readable decode of it. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 01 07:34:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 07:34:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269823.1558708 (Exim 4.92) (envelope-from ) id 1w7q65-0005TU-3H; Wed, 01 Apr 2026 07:34:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269823.1558708; Wed, 01 Apr 2026 07:34:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7q64-0005TN-Uh; Wed, 01 Apr 2026 07:34:40 +0000 Received: by outflank-mailman (input) for mailman id 1269823; Wed, 01 Apr 2026 07:34:39 +0000 Received: from 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Wed, 01 Apr 2026 01:11:13 -0700 (PDT) Message-ID: <6020226f-5e38-42f5-923e-2692d17bc4e9@suse.com> Date: Wed, 1 Apr 2026 10:11:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: Andrew Cooper , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <913f75e3-0039-4a7e-9884-7564c329557f@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <913f75e3-0039-4a7e-9884-7564c329557f@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775031074-77348497-3A991F04/0/0 X-purgate-type: clean X-purgate-size: 2559 On 01.04.2026 09:20, Andrew Cooper wrote: > On 01/04/2026 9:14 am, Jan Beulich wrote: >> On 27.03.2026 11:19, Marek Marczykowski-Górecki wrote: >>> I noticed that on some systems, there are a lot of IOMMU faults after >>> S3. I can see it also on a laptop with MTL, but it affects also the ADL >>> gitlab runner: >>> >>> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 >>> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>> >>> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. >>> >>> The issue is present only on staging, not staging-4.21. >>> >>> Bisect says: >>> >>> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit >>> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b >>> Author: Jan Beulich >>> Date: Thu Jan 22 14:13:35 2026 +0100 >>> >>> x86/HPET: drop .set_affinity hook >> Looking into this, I find several things I can't quite understand (yet). >> First there is >> >> (XEN) [000000456c0fe39f] Disabling HPET for being unreliable >> >> which looks to only affect clocksource selection, but not use as >> broadcast source for CPU-idle management. (This may be an independent >> issue.) >> >> Then there is >> >> (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) >> >> which should only occur on ARAT-incapable systems. That should only be >> older hardware. > > I'm not sure that's a reasonable assertion to draw.  The number of HPET > channels is down to the HPET alone, not anything to do with the CPU > capabilities. My statement was about the mere presence of that message, not the number of channels that are reported. >> (On my much older Skylake I don't see this line, for >> example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid >> is purely featureset based, and hence doesn't expose info about that >> leaf. > > xen-cpuid -p > > That will get you leaf 6, but there's no human-readable decode of it. Raw numbers is good enough here. How did I miss that option when looking at --help output? Oh, simply because it isn't shown there. Marek, that'll be better than bare metal kernel data, as it gives us both raw and host policies. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775031249-3332496F-66B8F4DB/0/0 X-purgate-type: clean X-purgate-size: 3783 On 01.04.2026 09:13, Mykola Kvach wrote: > Hi Jan, > > On Wed, Apr 1, 2026 at 9:29 AM Jan Beulich wrote: >> >> On 31.03.2026 20:31, Mykola Kvach wrote: >>> From: Mykola Kvach >>> >>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls >>> using Wn, only the least significant 32 bits are significant and the >>> upper 32 bits must be ignored by the implementation. >>> >>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the >>> argument registers as an error. Instead, they should be discarded when >>> decoding the arguments. >>> >>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be >>> implementation defined when entering from AArch32. Xen zeros them on >>> entry, but that guarantee is only relevant for 32-bit domains. >>> >>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND >>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 >>> handling unchanged. >>> >>> No functional change is intended for PSCI 0.1. >>> >>> Suggested-by: Julien Grall >>> Signed-off-by: Mykola Kvach >>> Reviewed-by: Bertrand Marquis >> >> I thought I might as well include this in my next commit sweep, but isn't >> this R-b being invalidated by ... >> >>> --- >>> v3: >>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND >> >> ... this change. That's ... >> >>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) >>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: >>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: >>> { >>> - register_t epoint = PSCI_ARG(regs, 1); >>> - register_t cid = PSCI_ARG(regs, 2); >>> - >>> - if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND ) >>> - { >>> - epoint &= GENMASK(31, 0); >>> - cid &= GENMASK(31, 0); >>> - } >>> + register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64); >>> + register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64); >>> >>> perfc_incr(vpsci_system_suspend); >>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid)); >> >> ... this hunk aiui, which is far from merely cosmetic imo. While > > Nobody said that the change had to be purely cosmetic in order to keep > the tag. I understood it differently from the official Xen > documentation pages. > >> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it > > Exactly. If the changes are not substantial, I do not see a reason to > drop the tag ... > >> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended >> and for the better, but the change clearly wasn't reviewed by Bertrand, >> nor - when offering the R-b - did he ask for this extra change. > > ... and this is also how I understood the Xen patch submission > guidelines [1], which say: > > "Note that if there are several revisions of a patch, you ought to > copy tags that have accumulated during the review. For example, if > person A and person B added a Reviewed-by: tag to v1 of your patch, > include it into v2 of your patch. If you make substantial changes > after certain tags were already applied, you will want to consider > which ones are no longer applicable (and may require re-providing)." > > So my understanding was that tags should normally be kept across > revisions, unless the changes are substantial enough to make them no > longer applicable. Maybe our understanding of "substantial" differs. To me that's anything changing functionality. Style adjustments, typo corrections, and alike generally aren't substantial (albeit even then there may be exceptions). Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269880.1558755 (Exim 4.92) (envelope-from ) id 1w7qkz-0005Rx-Gt; Wed, 01 Apr 2026 08:16:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269880.1558755; Wed, 01 Apr 2026 08:16:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qkz-0005Rq-E7; Wed, 01 Apr 2026 08:16:57 +0000 Received: by outflank-mailman (input) for mailman id 1269880; Wed, 01 Apr 2026 08:16:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qky-0005EX-9N for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:16:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qkx-00Ez1l-LQ for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:16:55 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd472-e002-0a2a0a5209dd-0a2a4503cd14-16 for ; Wed, 01 Apr 2026 10:16:55 +0200 Received: from [113.46.200.220] (helo=canpmsgout05.his.huawei.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd474-02b3-0a2a45030019-712ec8dc5d7e-3 for ; Wed, 01 Apr 2026 10:16:55 +0200 Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout05.his.huawei.com (SkyGuard) with ESMTPS id 4flyPC3klwz12LG4; Wed, 1 Apr 2026 16:11:27 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id CEA0F40537; Wed, 1 Apr 2026 16:16:50 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:48 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=BAu9Jx0jggsoB9DdjhBMDzv6GW2fgZQZhQIfabnTV1w=; b=0iNno9KssbzJIwOx46kM6OnZNBBxZqavG7rHHC5bdLxsRgIt4sx/XNjUZTTVDZXEoVFcegx0c Yif2aSgMI7B+vjuMbgqzpMuvUrJW1SQ8yRstGcNtfNLWFUMM/xjzPhZAjZffDLNoeTFLUbEByDb +8fyvzP5gn6CQVDmf4awY48= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 2/8] LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval Date: Wed, 1 Apr 2026 16:16:34 +0800 Message-ID: <20260401081640.26875-3-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-33051d/1775031415-CBF2DC9A-FC401EC5/0/0 X-purgate-type: clean X-purgate-size: 1483 As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for loongarch. While at it, add input validation to make the code more robust. Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron --- arch/loongarch/include/asm/acpi.h | 1 + arch/loongarch/kernel/acpi.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h index 7376840fa9f7..8bb101b4557e 100644 --- a/arch/loongarch/include/asm/acpi.h +++ b/arch/loongarch/include/asm/acpi.h @@ -44,6 +44,7 @@ static inline u32 get_acpi_id_for_cpu(unsigned int cpu) { return acpi_core_pic[cpu_logical_map(cpu)].processor_id; } +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); #endif /* !CONFIG_ACPI */ diff --git a/arch/loongarch/kernel/acpi.c b/arch/loongarch/kernel/acpi.c index 1367ca759468..058f0dbe8e8f 100644 --- a/arch/loongarch/kernel/acpi.c +++ b/arch/loongarch/kernel/acpi.c @@ -385,3 +385,12 @@ int acpi_unmap_cpu(int cpu) EXPORT_SYMBOL(acpi_unmap_cpu); #endif /* CONFIG_ACPI_HOTPLUG_CPU */ + +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid) +{ + if (cpu >= nr_cpu_ids) + return -EINVAL; + *uid = acpi_core_pic[cpu_logical_map(cpu)].processor_id; + return 0; +} +EXPORT_SYMBOL_GPL(acpi_get_cpu_uid); -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269881.1558765 (Exim 4.92) (envelope-from ) id 1w7ql0-0005fe-TO; Wed, 01 Apr 2026 08:16:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269881.1558765; Wed, 01 Apr 2026 08:16:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql0-0005fP-OJ; Wed, 01 Apr 2026 08:16:58 +0000 Received: by outflank-mailman (input) for mailman id 1269881; Wed, 01 Apr 2026 08:16:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qkz-0005OH-3h for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:16:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qky-00Ez1l-Fb for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:16:56 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd472-e002-0a2a0a5209dd-0a2a4503cd14-18 for ; Wed, 01 Apr 2026 10:16:56 +0200 Received: from [113.46.200.227] (helo=canpmsgout12.his.huawei.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd473-02b3-0a2a45030019-712ec8e3c802-3 for ; Wed, 01 Apr 2026 10:16:55 +0200 Received: from mail.maildlp.com (unknown [172.19.163.200]) by canpmsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4flyP93zz2znTYc; Wed, 1 Apr 2026 16:11:25 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 2C8174056C; Wed, 1 Apr 2026 16:16:49 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:47 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=cX9nX5J0dlT1awVPQ/6cRzsJrYfbjG8pE8PbO0C/Hhc=; b=i+j26ictNtsg7O/F6lBPFRPqM46wxpGQx6OUUfHHZ8jfyEiP2gCA6kxZgTIcJa4j5pbOBLJLQ c+HcxUl949mY9sPM4NfmX+Zase+tnrgONPI+R/E8bfr+487HRMp/f+b+3k2YIASwaiRxC/kJzyc ytRMmF8nbgor8UF3Ii+ThkQ= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 1/8] arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval Date: Wed, 1 Apr 2026 16:16:33 +0800 Message-ID: <20260401081640.26875-2-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-33051d/1775031416-41B15C9A-04D77A0F/0/0 X-purgate-type: clean X-purgate-size: 2371 As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for arm64. While at it, add input validation to make the code more robust. Reimplement get_cpu_for_acpi_id() based on acpi_get_cpu_uid() for consistency, and move its implementation next to the new function for code coherence. Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron Acked-by: Catalin Marinas --- arch/arm64/include/asm/acpi.h | 14 ++------------ arch/arm64/kernel/acpi.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index c07a58b96329..2219a3301e72 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -118,18 +118,8 @@ static inline u32 get_acpi_id_for_cpu(unsigned int cpu) { return acpi_cpu_get_madt_gicc(cpu)->uid; } - -static inline int get_cpu_for_acpi_id(u32 uid) -{ - int cpu; - - for (cpu = 0; cpu < nr_cpu_ids; cpu++) - if (acpi_cpu_get_madt_gicc(cpu) && - uid == get_acpi_id_for_cpu(cpu)) - return cpu; - - return -EINVAL; -} +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); +int get_cpu_for_acpi_id(u32 uid); static inline void arch_fix_phys_package_id(int num, u32 slot) { } void __init acpi_init_cpus(void); diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index af90128cfed5..24b9d934be54 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -458,3 +458,33 @@ int acpi_unmap_cpu(int cpu) } EXPORT_SYMBOL(acpi_unmap_cpu); #endif /* CONFIG_ACPI_HOTPLUG_CPU */ + +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid) +{ + struct acpi_madt_generic_interrupt *gicc; + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + gicc = acpi_cpu_get_madt_gicc(cpu); + if (!gicc) + return -ENODEV; + + *uid = gicc->uid; + return 0; +} +EXPORT_SYMBOL_GPL(acpi_get_cpu_uid); + +int get_cpu_for_acpi_id(u32 uid) +{ + u32 cpu_uid; + int ret; + + for (int cpu = 0; cpu < nr_cpu_ids; cpu++) { + ret = acpi_get_cpu_uid(cpu, &cpu_uid); + if (ret == 0 && uid == cpu_uid) + return cpu; + } + + return -EINVAL; +} -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269882.1558769 (Exim 4.92) (envelope-from ) id 1w7ql1-0005jE-7N; Wed, 01 Apr 2026 08:16:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269882.1558769; Wed, 01 Apr 2026 08:16:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql1-0005in-1v; Wed, 01 Apr 2026 08:16:59 +0000 Received: by outflank-mailman (input) for mailman id 1269882; Wed, 01 Apr 2026 08:16:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qkz-0005Q0-8o for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:16:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qkx-000XNy-39 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:16:56 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd476-bab6-0a2a0a5309dd-0a2a450280cc-12 for ; Wed, 01 Apr 2026 10:16:56 +0200 Received: from [113.46.200.226] (helo=canpmsgout11.his.huawei.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd475-42fa-0a2a45020019-712ec8e28bec-3 for ; Wed, 01 Apr 2026 10:16:56 +0200 Received: from mail.maildlp.com (unknown [172.19.163.163]) by canpmsgout11.his.huawei.com (SkyGuard) with ESMTPS id 4flyNJ5zjPzKm91; Wed, 1 Apr 2026 16:10:40 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 743394048B; Wed, 1 Apr 2026 16:16:52 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:50 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=BMMryEb1CdnOx2gMiVv+9iHKONhR3XK5c+5CZUibkPo=; b=l/7oJpMqJuYSGHZyOqLiw5LD07h+45LWAipYVAvEt9pYxSp4UxJSqwXgX66M8/EZ74aeSBY3M qLpVsSs+rpKpxDOoVmFTloYQFQ4DUIG80JTpBOmlHJ7rSI3KUDZxGFyGCXDxs8sVu0UH3BlI+It fJwAj4fQtMaqP5gUwirfIBk= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 3/8] RISC-V: ACPI: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval Date: Wed, 1 Apr 2026 16:16:35 +0800 Message-ID: <20260401081640.26875-4-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-720697/1775031416-46B27CD1-77581FE3/0/0 X-purgate-type: clean X-purgate-size: 3045 As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for riscv. While at it, add input validation to make the code more robust. And also update acpi_numa.c and rhct.c to use the new interface instead of the legacy get_acpi_id_for_cpu(). Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron --- arch/riscv/include/asm/acpi.h | 1 + arch/riscv/kernel/acpi.c | 16 ++++++++++++++++ arch/riscv/kernel/acpi_numa.c | 9 ++++++--- drivers/acpi/riscv/rhct.c | 7 ++++++- 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..f3520cc85af3 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -65,6 +65,7 @@ static inline u32 get_acpi_id_for_cpu(int cpu) { return acpi_cpu_get_madt_rintc(cpu)->uid; } +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 71698ee11621..322ea92aa39f 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -337,3 +337,19 @@ int raw_pci_write(unsigned int domain, unsigned int bus, } #endif /* CONFIG_PCI */ + +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid) +{ + struct acpi_madt_rintc *rintc; + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + rintc = acpi_cpu_get_madt_rintc(cpu); + if (!rintc) + return -ENODEV; + + *uid = rintc->uid; + return 0; +} +EXPORT_SYMBOL_GPL(acpi_get_cpu_uid); diff --git a/arch/riscv/kernel/acpi_numa.c b/arch/riscv/kernel/acpi_numa.c index 130769e3a99c..6a2d4289f806 100644 --- a/arch/riscv/kernel/acpi_numa.c +++ b/arch/riscv/kernel/acpi_numa.c @@ -37,11 +37,14 @@ static int __init acpi_numa_get_nid(unsigned int cpu) static inline int get_cpu_for_acpi_id(u32 uid) { - int cpu; + u32 cpu_uid; + int ret; - for (cpu = 0; cpu < nr_cpu_ids; cpu++) - if (uid == get_acpi_id_for_cpu(cpu)) + for (int cpu = 0; cpu < nr_cpu_ids; cpu++) { + ret = acpi_get_cpu_uid(cpu, &cpu_uid); + if (ret == 0 && uid == cpu_uid) return cpu; + } return -EINVAL; } diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c index caa2c16e1697..8f3f38c64a88 100644 --- a/drivers/acpi/riscv/rhct.c +++ b/drivers/acpi/riscv/rhct.c @@ -44,10 +44,15 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const struct acpi_rhct_isa_string *isa_node; struct acpi_table_rhct *rhct; u32 *hart_info_node_offset; - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; + int ret; BUG_ON(acpi_disabled); + ret = acpi_get_cpu_uid(cpu, &acpi_cpu_id); + if (ret != 0) + return ret; + if (!table) { rhct = acpi_get_rhct(); if (!rhct) -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269879.1558746 (Exim 4.92) (envelope-from ) id 1w7qky-0005Ef-8m; Wed, 01 Apr 2026 08:16:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269879.1558746; Wed, 01 Apr 2026 08:16:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qky-0005EY-5G; Wed, 01 Apr 2026 08:16:56 +0000 Received: by outflank-mailman (input) for mailman id 1269879; Wed, 01 Apr 2026 08:16:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qkw-0005EK-OQ for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:16:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qkv-003Uhh-By for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:16:54 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd468-5cb7-0a2a0a5109dd-0a2a4502cf5e-48 for ; Wed, 01 Apr 2026 10:16:53 +0200 Received: from [113.46.200.219] (helo=canpmsgout04.his.huawei.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd472-42fa-0a2a45020019-712ec8dbfa84-3 for ; Wed, 01 Apr 2026 10:16:52 +0200 Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4flyNC08FCz1prLN; Wed, 1 Apr 2026 16:10:35 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 9190740537; Wed, 1 Apr 2026 16:16:47 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:45 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=c9AlrYXsxBFF3IzNBDnKrFfgKSQZlOG3wlCt2foyY+Y=; b=s0jHWYuxfoxkRN+t4KseYGhpk5P2m2+oPxvld1K2wRhg/xq/KJ6rPLjiy3A+eHJcZDd4LECJR hk2c9oJcG9N70ZRCYC/HPCz/7V6gQufIs9IC6ExJohMMFTan9KIJsB7lPAuY/r27HFSh7GQcO9C uY27gGt24m7NlqDK+Rfdv9c= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 0/8] ACPI: Unify CPU UID interface and fix ARM64 TPH steer-tag issue Date: Wed, 1 Apr 2026 16:16:32 +0800 Message-ID: <20260401081640.26875-1-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-720697/1775031413-ADD38CD1-8503821E/0/0 X-purgate-type: clean X-purgate-size: 2769 This patchset unifies ACPI Processor UID retrieval across arm64/loongarch/riscv/x86 via acpi_get_cpu_uid() (with input validation) and fixes ARM64 CPU steer-tag retrieval failure in PCI/TPH: 1-4: Add acpi_get_cpu_uid() for arm64/loongarch/riscv/x86 (update respective users) 5: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h 6: Clean up perf/arm_cspmu 7: Clean up ACPI/PPTT and remove unused get_acpi_id_for_cpu() 8: Pass ACPI Processor UID to Cache Locality _DSM The interface refactor ensures consistent CPU UID retrieval across architectures (no functional changes for valid inputs) and provides the unified interface required for the ARM64 TPH fix --- Changes in v10-resend: - Add Catalin's ack-by for arm64 commit - Add CC to x86@kernel.org Changes in v10: - Refine commit header&log according to Punit's and Bjorn's review - Split perf/arm_cspmu as a separate commit which address Punit's review Changes in v9: - Address Bjorn's review: split commits to each platform so that make them easy to review Changes in v8: - Moving arm64's get_cpu_for_acpi_id() to kernel/acpi.c which address Jeremy's review Chengwen Feng (8): arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval RISC-V: ACPI: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval x86/acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval ACPI: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h perf: arm_cspmu: Switch to acpi_get_cpu_uid() from get_acpi_id_for_cpu() ACPI: PPTT: Use acpi_get_cpu_uid() and remove get_acpi_id_for_cpu() PCI/TPH: Pass ACPI Processor UID to Cache Locality _DSM Documentation/PCI/tph.rst | 4 +-- arch/arm64/include/asm/acpi.h | 17 +--------- arch/arm64/kernel/acpi.c | 30 ++++++++++++++++++ arch/loongarch/include/asm/acpi.h | 5 --- arch/loongarch/kernel/acpi.c | 9 ++++++ arch/riscv/include/asm/acpi.h | 4 --- arch/riscv/kernel/acpi.c | 16 ++++++++++ arch/riscv/kernel/acpi_numa.c | 9 ++++-- arch/x86/include/asm/cpu.h | 1 - arch/x86/include/asm/smp.h | 1 - arch/x86/kernel/acpi/boot.c | 20 ++++++++++++ arch/x86/xen/enlighten_hvm.c | 5 +-- drivers/acpi/pptt.c | 50 ++++++++++++++++++++++-------- drivers/acpi/riscv/rhct.c | 7 ++++- drivers/pci/tph.c | 16 +++++++--- drivers/perf/arm_cspmu/arm_cspmu.c | 6 ++-- include/linux/acpi.h | 11 +++++++ include/linux/pci-tph.h | 4 +-- 18 files changed, 158 insertions(+), 57 deletions(-) -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269883.1558783 (Exim 4.92) (envelope-from ) id 1w7ql3-00068t-Fj; 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dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=/bDHT0vostLWviBcH0LGnrUXN/7+wtQhJKC8xvlaZ1w=; b=I76d5QkgB06G/X/wos41vVtgRQepXQMzc5bCmZUjG61rsMvqBqMxjyiWV13dSj/N0vARfMR+I TIpo+e0ZZ/G2PYTKyAK+od5BAX4GJxZnIIHvWHRL80Tl9ySzHsM4ReaK/m6QcwIZU7CfdK4/sr4 hK45B5FTc4PW95z2AIDDxVc= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 4/8] x86/acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval Date: Wed, 1 Apr 2026 16:16:36 +0800 Message-ID: <20260401081640.26875-5-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-d62444/1775031419-14EE3185-4F85D5D4/0/0 X-purgate-type: clean X-purgate-size: 3673 As a step towards unifying the interface for retrieving ACPI CPU UID across architectures, introduce a new function acpi_get_cpu_uid() for x86. While at it, add input validation to make the code more robust. Update Xen-related code to use acpi_get_cpu_uid() instead of the legacy cpu_acpi_id() function, and remove the now-unused cpu_acpi_id() to clean up redundant code. Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron Reviewed-by: Juergen Gross --- arch/x86/include/asm/acpi.h | 2 ++ arch/x86/include/asm/cpu.h | 1 - arch/x86/include/asm/smp.h | 1 - arch/x86/kernel/acpi/boot.c | 20 ++++++++++++++++++++ arch/x86/xen/enlighten_hvm.c | 5 +++-- 5 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index a03aa6f999d1..92b5c27c4fea 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -157,6 +157,8 @@ static inline bool acpi_has_cpu_in_madt(void) return !!acpi_lapic; } +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); + #define ACPI_HAVE_ARCH_SET_ROOT_POINTER static __always_inline void acpi_arch_set_root_pointer(u64 addr) { diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index ad235dda1ded..57a0786dfd75 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -11,7 +11,6 @@ #ifndef CONFIG_SMP #define cpu_physical_id(cpu) boot_cpu_physical_apicid -#define cpu_acpi_id(cpu) 0 #endif /* CONFIG_SMP */ #ifdef CONFIG_HOTPLUG_CPU diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index 84951572ab81..05d1d479b4cf 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -130,7 +130,6 @@ __visible void smp_call_function_interrupt(struct pt_regs *regs); __visible void smp_call_function_single_interrupt(struct pt_regs *r); #define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu) -#define cpu_acpi_id(cpu) per_cpu(x86_cpu_to_acpiid, cpu) /* * This function is needed by all SMP systems. It must _always_ be valid diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index a3f2fb1fea1b..ceba24f65ae3 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1848,3 +1848,23 @@ void __iomem * (*acpi_os_ioremap)(acpi_physical_address phys, acpi_size size) = x86_acpi_os_ioremap; EXPORT_SYMBOL_GPL(acpi_os_ioremap); #endif + +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid) +{ + u32 acpi_id; + + if (cpu >= nr_cpu_ids) + return -EINVAL; + +#ifdef CONFIG_SMP + acpi_id = per_cpu(x86_cpu_to_acpiid, cpu); + if (acpi_id == CPU_ACPIID_INVALID) + return -ENODEV; +#else + acpi_id = 0; +#endif + + *uid = acpi_id; + return 0; +} +EXPORT_SYMBOL_GPL(acpi_get_cpu_uid); diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c index fe57ff85d004..2f9fa27e5a3c 100644 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -151,6 +151,7 @@ static void xen_hvm_crash_shutdown(struct pt_regs *regs) static int xen_cpu_up_prepare_hvm(unsigned int cpu) { + u32 cpu_uid; int rc = 0; /* @@ -161,8 +162,8 @@ static int xen_cpu_up_prepare_hvm(unsigned int cpu) */ xen_uninit_lock_cpu(cpu); - if (cpu_acpi_id(cpu) != CPU_ACPIID_INVALID) - per_cpu(xen_vcpu_id, cpu) = cpu_acpi_id(cpu); + if (acpi_get_cpu_uid(cpu, &cpu_uid) == 0) + per_cpu(xen_vcpu_id, cpu) = cpu_uid; else per_cpu(xen_vcpu_id, cpu) = cpu; xen_vcpu_setup(cpu); -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269884.1558792 (Exim 4.92) (envelope-from ) id 1w7ql5-0006QW-Op; Wed, 01 Apr 2026 08:17:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269884.1558792; Wed, 01 Apr 2026 08:17:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql5-0006QL-L1; Wed, 01 Apr 2026 08:17:03 +0000 Received: by outflank-mailman (input) for mailman id 1269884; Wed, 01 Apr 2026 08:17:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql4-0006G2-24 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:17:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ql3-00Ez7l-Dz for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:17:01 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd476-2eae-0a2a0a5409dd-0a2a4506e4f2-26 for ; Wed, 01 Apr 2026 10:17:00 +0200 Received: from [113.46.200.217] (helo=canpmsgout02.his.huawei.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd478-0df0-0a2a45060019-712ec8d97316-3 for ; Wed, 01 Apr 2026 10:16:59 +0200 Received: from mail.maildlp.com (unknown [172.19.162.140]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4flyNW224WzcZxn; Wed, 1 Apr 2026 16:10:51 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id BC54C203B2; Wed, 1 Apr 2026 16:16:55 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:53 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=ANvjKw/V+x/xgnK84bsEKs2slfuc72S2wtUZ6Ltd7AU=; b=gAhZczIG65dC2yh+2aADvwVAp++19t5FyGF4ZzbeSLiKAirv37HFkiFuy/A1lWBlr5MpsM4Ut Lnhv1/GDpeZI1w99rpED8gfQlunCOXOTiUjR1yp3rBy23eO6v/Ttq6ZYJsfo+fm/1xgWotDODEb YV0jLZY6lrTP0qpYzZ1KoG4= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 5/8] ACPI: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h Date: Wed, 1 Apr 2026 16:16:37 +0800 Message-ID: <20260401081640.26875-6-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-16d1c6/1775031420-5F93A3D8-FD3324E8/0/0 X-purgate-type: clean X-purgate-size: 3353 Centralize acpi_get_cpu_uid() in include/linux/acpi.h (global scope) and remove arch-specific declarations from arm64/loongarch/riscv/x86 asm/acpi.h. This unifies the interface across architectures and simplifies maintenance by eliminating duplicate prototypes. Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron --- arch/arm64/include/asm/acpi.h | 1 - arch/loongarch/include/asm/acpi.h | 1 - arch/riscv/include/asm/acpi.h | 1 - arch/x86/include/asm/acpi.h | 2 -- include/linux/acpi.h | 11 +++++++++++ 5 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 2219a3301e72..bdb0ecf95b5c 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -118,7 +118,6 @@ static inline u32 get_acpi_id_for_cpu(unsigned int cpu) { return acpi_cpu_get_madt_gicc(cpu)->uid; } -int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); int get_cpu_for_acpi_id(u32 uid); static inline void arch_fix_phys_package_id(int num, u32 slot) { } diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h index 8bb101b4557e..7376840fa9f7 100644 --- a/arch/loongarch/include/asm/acpi.h +++ b/arch/loongarch/include/asm/acpi.h @@ -44,7 +44,6 @@ static inline u32 get_acpi_id_for_cpu(unsigned int cpu) { return acpi_core_pic[cpu_logical_map(cpu)].processor_id; } -int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); #endif /* !CONFIG_ACPI */ diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index f3520cc85af3..6e13695120bc 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -65,7 +65,6 @@ static inline u32 get_acpi_id_for_cpu(int cpu) { return acpi_cpu_get_madt_rintc(cpu)->uid; } -int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 92b5c27c4fea..a03aa6f999d1 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -157,8 +157,6 @@ static inline bool acpi_has_cpu_in_madt(void) return !!acpi_lapic; } -int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); - #define ACPI_HAVE_ARCH_SET_ROOT_POINTER static __always_inline void acpi_arch_set_root_pointer(u64 addr) { diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 4d2f0bed7a06..74a73f0e5944 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -324,6 +324,17 @@ int acpi_unmap_cpu(int cpu); acpi_handle acpi_get_processor_handle(int cpu); +/** + * acpi_get_cpu_uid() - Get ACPI Processor UID of from MADT table + * @cpu: Logical CPU number (0-based) + * @uid: Pointer to store ACPI Processor UID + * + * Return: 0 on success (ACPI Processor ID stored in *uid); + * -EINVAL if CPU number is invalid or out of range; + * -ENODEV if ACPI Processor UID for the CPU is not found. + */ +int acpi_get_cpu_uid(unsigned int cpu, u32 *uid); + #ifdef CONFIG_ACPI_HOTPLUG_IOAPIC int acpi_get_ioapic_id(acpi_handle handle, u32 gsi_base, u64 *phys_addr); #endif -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269885.1558797 (Exim 4.92) (envelope-from ) id 1w7ql6-0006UN-CI; Wed, 01 Apr 2026 08:17:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269885.1558797; Wed, 01 Apr 2026 08:17:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql5-0006Sh-Vy; Wed, 01 Apr 2026 08:17:03 +0000 Received: by outflank-mailman (input) for mailman id 1269885; Wed, 01 Apr 2026 08:17:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql4-0006M0-MF for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:17:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ql4-003Ul3-0o for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:17:02 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd472-5cb7-0a2a0a5109dd-0a2a4501cb74-40 for ; Wed, 01 Apr 2026 10:17:01 +0200 Received: from [113.46.200.222] (helo=canpmsgout07.his.huawei.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd47a-6fc9-0a2a45010019-712ec8de30dc-3 for ; Wed, 01 Apr 2026 10:17:01 +0200 Received: from mail.maildlp.com (unknown [172.19.163.127]) by canpmsgout07.his.huawei.com (SkyGuard) with ESMTPS id 4flyNS2tVFzLlXm; Wed, 1 Apr 2026 16:10:48 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 6117940572; Wed, 1 Apr 2026 16:16:57 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:55 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=zauzEDoW1iZZVg1rc8HmzuZCwLSftmOLfB8Jb8RY2BQ=; b=J5TZKxoHIReSEQmbTRfXFVLNZ+/IUwuE+uW11i8+jkMuLeZGtwJVXLQfuq4LHOSczhwfghmzc YFCMaPt2RTCEgwugJISj0LKEbk2ZW0qVVKN1TRrnTPUfnEonx2LqeBG0wXshmZawXX2M7xbOaMf BcPDzWOBbKROUN5RO0vtU+I= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 6/8] perf: arm_cspmu: Switch to acpi_get_cpu_uid() from get_acpi_id_for_cpu() Date: Wed, 1 Apr 2026 16:16:38 +0800 Message-ID: <20260401081640.26875-7-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-d62444/1775031421-B7CFA185-2B2C221B/0/0 X-purgate-type: clean X-purgate-size: 1347 Update arm_cspmu to use acpi_get_cpu_uid() instead of get_acpi_id_for_cpu(), aligning with unified ACPI CPU UID interface. No functional changes are introduced by this switch (valid inputs retain original behavior). Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron --- drivers/perf/arm_cspmu/arm_cspmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index 34430b68f602..ed72c3d1f796 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -1107,15 +1107,17 @@ static int arm_cspmu_acpi_get_cpus(struct arm_cspmu *cspmu) { struct acpi_apmt_node *apmt_node; int affinity_flag; + u32 cpu_uid; int cpu; + int ret; apmt_node = arm_cspmu_apmt_node(cspmu->dev); affinity_flag = apmt_node->flags & ACPI_APMT_FLAGS_AFFINITY; if (affinity_flag == ACPI_APMT_FLAGS_AFFINITY_PROC) { for_each_possible_cpu(cpu) { - if (apmt_node->proc_affinity == - get_acpi_id_for_cpu(cpu)) { + ret = acpi_get_cpu_uid(cpu, &cpu_uid); + if (ret == 0 && apmt_node->proc_affinity == cpu_uid) { cpumask_set_cpu(cpu, &cspmu->associated_cpus); break; } -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269886.1558802 (Exim 4.92) (envelope-from ) id 1w7ql6-0006fb-V4; Wed, 01 Apr 2026 08:17:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269886.1558802; Wed, 01 Apr 2026 08:17:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql6-0006bx-NW; Wed, 01 Apr 2026 08:17:04 +0000 Received: by outflank-mailman (input) for mailman id 1269886; Wed, 01 Apr 2026 08:17:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql5-0006Pe-Kq for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:17:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ql4-003Ulf-WB for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:17:03 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd474-bab6-0a2a0a5309dd-0a2a4509c454-34 for ; Wed, 01 Apr 2026 10:17:02 +0200 Received: from [113.46.200.219] (helo=canpmsgout04.his.huawei.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd47b-bf79-0a2a45090019-712ec8db9016-3 for ; Wed, 01 Apr 2026 10:17:02 +0200 Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4flyNQ3F6jz1prLN; Wed, 1 Apr 2026 16:10:46 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 093EB40537; Wed, 1 Apr 2026 16:16:59 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:57 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=/eBsZSTPYF/YtxnkPhtkEULxH4VEHo0dKDplLzt2h+U=; b=ypbclQg4Iukdlkqpoizb0I/F7L+DePAd+M0//lXkMgfo2Tebtl3dWlIRb5T+BpmkoHuv3dAUf q4obfVRqfYA+w4THr01Bmp7st54V9VWVLRFBbSiDcMjxC61DIiVgmZCmNOX7nmSXAg0dF57r5Ul C2JQqU6Aei7BxV0EFNUv0ls= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 7/8] ACPI: PPTT: Use acpi_get_cpu_uid() and remove get_acpi_id_for_cpu() Date: Wed, 1 Apr 2026 16:16:39 +0800 Message-ID: <20260401081640.26875-8-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-bad1c0/1775031422-2D951152-EC45E0DA/0/0 X-purgate-type: clean X-purgate-size: 7428 Update acpi/pptt.c to use acpi_get_cpu_uid() and remove unused get_acpi_id_for_cpu() from arm64/loongarch/riscv, completing PPTT's migration to the unified ACPI CPU UID interface Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron --- arch/arm64/include/asm/acpi.h | 4 --- arch/loongarch/include/asm/acpi.h | 5 ---- arch/riscv/include/asm/acpi.h | 4 --- drivers/acpi/pptt.c | 50 +++++++++++++++++++++++-------- 4 files changed, 37 insertions(+), 26 deletions(-) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index bdb0ecf95b5c..8a54ca6ba602 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -114,10 +114,6 @@ static inline bool acpi_has_cpu_in_madt(void) } struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu); -static inline u32 get_acpi_id_for_cpu(unsigned int cpu) -{ - return acpi_cpu_get_madt_gicc(cpu)->uid; -} int get_cpu_for_acpi_id(u32 uid); static inline void arch_fix_phys_package_id(int num, u32 slot) { } diff --git a/arch/loongarch/include/asm/acpi.h b/arch/loongarch/include/asm/acpi.h index 7376840fa9f7..eda9d4d0a493 100644 --- a/arch/loongarch/include/asm/acpi.h +++ b/arch/loongarch/include/asm/acpi.h @@ -40,11 +40,6 @@ extern struct acpi_madt_core_pic acpi_core_pic[MAX_CORE_PIC]; extern int __init parse_acpi_topology(void); -static inline u32 get_acpi_id_for_cpu(unsigned int cpu) -{ - return acpi_core_pic[cpu_logical_map(cpu)].processor_id; -} - #endif /* !CONFIG_ACPI */ #define ACPI_TABLE_UPGRADE_MAX_PHYS ARCH_LOW_ADDRESS_LIMIT diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..26ab37c171bc 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -61,10 +61,6 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } void acpi_init_rintc_map(void); struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); -static inline u32 get_acpi_id_for_cpu(int cpu) -{ - return acpi_cpu_get_madt_rintc(cpu)->uid; -} int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index de5f8c018333..7bd5bc1f225a 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -459,11 +459,14 @@ static void cache_setup_acpi_cpu(struct acpi_table_header *table, { struct acpi_pptt_cache *found_cache; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; struct cacheinfo *this_leaf; unsigned int index = 0; struct acpi_pptt_processor *cpu_node = NULL; + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + return; + while (index < get_cpu_cacheinfo(cpu)->num_leaves) { this_leaf = this_cpu_ci->info_list + index; found_cache = acpi_find_cache_node(table, acpi_cpu_id, @@ -546,7 +549,10 @@ static int topology_get_acpi_cpu_tag(struct acpi_table_header *table, unsigned int cpu, int level, int flag) { struct acpi_pptt_processor *cpu_node; - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; + + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + return -ENOENT; cpu_node = acpi_find_processor_node(table, acpi_cpu_id); if (cpu_node) { @@ -614,18 +620,22 @@ static int find_acpi_cpu_topology_tag(unsigned int cpu, int level, int flag) * * Check the node representing a CPU for a given flag. * - * Return: -ENOENT if the PPTT doesn't exist, the CPU cannot be found or - * the table revision isn't new enough. + * Return: -ENOENT if can't get CPU's ACPI Processor UID, the PPTT doesn't + * exist, the CPU cannot be found or the table revision isn't new + * enough. * 1, any passed flag set * 0, flag unset */ static int check_acpi_cpu_flag(unsigned int cpu, int rev, u32 flag) { struct acpi_table_header *table; - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; struct acpi_pptt_processor *cpu_node = NULL; int ret = -ENOENT; + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + return -ENOENT; + table = acpi_get_pptt(); if (!table) return -ENOENT; @@ -651,7 +661,8 @@ static int check_acpi_cpu_flag(unsigned int cpu, int rev, u32 flag) * in the PPTT. Errors caused by lack of a PPTT table, or otherwise, return 0 * indicating we didn't find any cache levels. * - * Return: -ENOENT if no PPTT table or no PPTT processor struct found. + * Return: -ENOENT if no PPTT table, can't get CPU's ACPI Process UID or no PPTT + * processor struct found. * 0 on success. */ int acpi_get_cache_info(unsigned int cpu, unsigned int *levels, @@ -671,7 +682,9 @@ int acpi_get_cache_info(unsigned int cpu, unsigned int *levels, pr_debug("Cache Setup: find cache levels for CPU=%d\n", cpu); - acpi_cpu_id = get_acpi_id_for_cpu(cpu); + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id)) + return -ENOENT; + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); if (!cpu_node) return -ENOENT; @@ -780,8 +793,9 @@ int find_acpi_cpu_topology_package(unsigned int cpu) * It may not exist in single CPU systems. In simple multi-CPU systems, * it may be equal to the package topology level. * - * Return: -ENOENT if the PPTT doesn't exist, the CPU cannot be found - * or there is no toplogy level above the CPU.. + * Return: -ENOENT if the PPTT doesn't exist, can't get CPU's ACPI + * Processor UID, the CPU cannot be found or there is no toplogy level + * above the CPU. * Otherwise returns a value which represents the package for this CPU. */ @@ -797,7 +811,9 @@ int find_acpi_cpu_topology_cluster(unsigned int cpu) if (!table) return -ENOENT; - acpi_cpu_id = get_acpi_id_for_cpu(cpu); + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + return -ENOENT; + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); if (!cpu_node || !cpu_node->parent) return -ENOENT; @@ -872,7 +888,9 @@ static void acpi_pptt_get_child_cpus(struct acpi_table_header *table_hdr, cpumask_clear(cpus); for_each_possible_cpu(cpu) { - acpi_id = get_acpi_id_for_cpu(cpu); + if (acpi_get_cpu_uid(cpu, &acpi_id) != 0) + continue; + cpu_node = acpi_find_processor_node(table_hdr, acpi_id); while (cpu_node) { @@ -966,10 +984,13 @@ int find_acpi_cache_level_from_id(u32 cache_id) for_each_possible_cpu(cpu) { bool empty; int level = 1; - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; struct acpi_pptt_cache *cache; struct acpi_pptt_processor *cpu_node; + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + continue; + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); if (!cpu_node) continue; @@ -1030,10 +1051,13 @@ int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus) for_each_possible_cpu(cpu) { bool empty; int level = 1; - u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + u32 acpi_cpu_id; struct acpi_pptt_cache *cache; struct acpi_pptt_processor *cpu_node; + if (acpi_get_cpu_uid(cpu, &acpi_cpu_id) != 0) + continue; + cpu_node = acpi_find_processor_node(table, acpi_cpu_id); if (!cpu_node) continue; -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:17:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:17:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269891.1558819 (Exim 4.92) (envelope-from ) id 1w7qlB-0007JV-BO; Wed, 01 Apr 2026 08:17:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269891.1558819; Wed, 01 Apr 2026 08:17:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qlB-0007JI-6m; Wed, 01 Apr 2026 08:17:09 +0000 Received: by outflank-mailman (input) for mailman id 1269891; Wed, 01 Apr 2026 08:17:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ql9-0007FB-V2 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:17:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ql9-003Ulf-Av for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:17:07 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd47c-bab6-0a2a0a5309dd-0a2a450ccf46-30 for ; Wed, 01 Apr 2026 10:17:07 +0200 Received: from [113.46.200.220] (helo=canpmsgout05.his.huawei.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd47d-f40c-0a2a450c0019-712ec8dcccee-3 for ; Wed, 01 Apr 2026 10:17:06 +0200 Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout05.his.huawei.com (SkyGuard) with ESMTPS id 4flyPP34Mzz12LG4; Wed, 1 Apr 2026 16:11:37 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id B64C540537; Wed, 1 Apr 2026 16:17:00 +0800 (CST) Received: from localhost.localdomain (10.50.163.32) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:16:58 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=hE9w7JoPF7q5rCf6KhhEJWJqCptovuDZd/Iy/+tLfKo=; b=qLgUdTXyB2huFMYWwsBs6yJ/F+9lt0zGJ2NBn+WC66I23Xw4lD/MYLZdp/AaESL9MDwbvh4PG 4g/cCYoR/67GmTbgs1X5afshxewzUwAWGLnOlgBOHKQjEtF2bK4P57/PDC46EmJDfRwKl3h1FiZ k+9EKAAKSPQbPzHjYnS4Cu4= From: Chengwen Feng To: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" CC: Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RESEND v10 8/8] PCI/TPH: Pass ACPI Processor UID to Cache Locality _DSM Date: Wed, 1 Apr 2026 16:16:40 +0800 Message-ID: <20260401081640.26875-9-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> References: <20260401081640.26875-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.163.32] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-d25034/1775031427-83F42A3D-4AA409DA/0/0 X-purgate-type: clean X-purgate-size: 5074 pcie_tph_get_cpu_st() uses the Query Cache Locality Features _DSM [1] to retrieve the TPH Steering Tag for memory associated with the CPU identified by its "cpu_uid" parameter, a Linux logical CPU ID. The _DSM requires an ACPI Processor UID, which pcie_tph_get_cpu_st() previously assumed was the same as the Linux logical CPU ID. This is true on x86 but not on arm64, so pcie_tph_get_cpu_st() returned the wrong Steering Tag, resulting in incorrect TPH functionality on arm64. Convert the Linux logical CPU ID to the ACPI Processor UID with acpi_get_cpu_uid() before passing it to the _DSM. Additionally, rename the pcie_tph_get_cpu_st() parameter from "cpu_uid" to "cpu" to reflect that it represents a logical CPU ID (not an ACPI Processor UID). [1] According to ECN_TPH-ST_Revision_20200924 (https://members.pcisig.com/wg/PCI-SIG/document/15470), the input is defined as: "If the target is a processor, then this field represents the ACPI Processor UID of the processor as specified in the MADT. If the target is a processor container, then this field represents the ACPI Processor UID of the processor container as specified in the PPTT." Fixes: d2e8a34876ce ("PCI/TPH: Add Steering Tag support") Cc: stable@vger.kernel.org Signed-off-by: Chengwen Feng Reviewed-by: Jonathan Cameron Reviewed-by: Bjorn Helgaas --- Documentation/PCI/tph.rst | 4 ++-- drivers/pci/tph.c | 16 +++++++++++----- include/linux/pci-tph.h | 4 ++-- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/Documentation/PCI/tph.rst b/Documentation/PCI/tph.rst index e8993be64fd6..b6cf22b9bd90 100644 --- a/Documentation/PCI/tph.rst +++ b/Documentation/PCI/tph.rst @@ -79,10 +79,10 @@ To retrieve a Steering Tag for a target memory associated with a specific CPU, use the following function:: int pcie_tph_get_cpu_st(struct pci_dev *pdev, enum tph_mem_type type, - unsigned int cpu_uid, u16 *tag); + unsigned int cpu, u16 *tag); The `type` argument is used to specify the memory type, either volatile -or persistent, of the target memory. The `cpu_uid` argument specifies the +or persistent, of the target memory. The `cpu` argument specifies the CPU where the memory is associated to. After the ST value is retrieved, the device driver can use the following diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c index ca4f97be7538..b67c9ad14bda 100644 --- a/drivers/pci/tph.c +++ b/drivers/pci/tph.c @@ -236,21 +236,27 @@ static int write_tag_to_st_table(struct pci_dev *pdev, int index, u16 tag) * with a specific CPU * @pdev: PCI device * @mem_type: target memory type (volatile or persistent RAM) - * @cpu_uid: associated CPU id + * @cpu: associated CPU id * @tag: Steering Tag to be returned * * Return the Steering Tag for a target memory that is associated with a - * specific CPU as indicated by cpu_uid. + * specific CPU as indicated by cpu. * * Return: 0 if success, otherwise negative value (-errno) */ int pcie_tph_get_cpu_st(struct pci_dev *pdev, enum tph_mem_type mem_type, - unsigned int cpu_uid, u16 *tag) + unsigned int cpu, u16 *tag) { #ifdef CONFIG_ACPI struct pci_dev *rp; acpi_handle rp_acpi_handle; union st_info info; + u32 cpu_uid; + int ret; + + ret = acpi_get_cpu_uid(cpu, &cpu_uid); + if (ret != 0) + return ret; rp = pcie_find_root_port(pdev); if (!rp || !rp->bus || !rp->bus->bridge) @@ -265,9 +271,9 @@ int pcie_tph_get_cpu_st(struct pci_dev *pdev, enum tph_mem_type mem_type, *tag = tph_extract_tag(mem_type, pdev->tph_req_type, &info); - pci_dbg(pdev, "get steering tag: mem_type=%s, cpu_uid=%d, tag=%#04x\n", + pci_dbg(pdev, "get steering tag: mem_type=%s, cpu=%d, tag=%#04x\n", (mem_type == TPH_MEM_TYPE_VM) ? "volatile" : "persistent", - cpu_uid, *tag); + cpu, *tag); return 0; #else diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h index ba28140ce670..be68cd17f2f8 100644 --- a/include/linux/pci-tph.h +++ b/include/linux/pci-tph.h @@ -25,7 +25,7 @@ int pcie_tph_set_st_entry(struct pci_dev *pdev, unsigned int index, u16 tag); int pcie_tph_get_cpu_st(struct pci_dev *dev, enum tph_mem_type mem_type, - unsigned int cpu_uid, u16 *tag); + unsigned int cpu, u16 *tag); void pcie_disable_tph(struct pci_dev *pdev); int pcie_enable_tph(struct pci_dev *pdev, int mode); u16 pcie_tph_get_st_table_size(struct pci_dev *pdev); @@ -36,7 +36,7 @@ static inline int pcie_tph_set_st_entry(struct pci_dev *pdev, { return -EINVAL; } static inline int pcie_tph_get_cpu_st(struct pci_dev *dev, enum tph_mem_type mem_type, - unsigned int cpu_uid, u16 *tag) + unsigned int cpu, u16 *tag) { return -EINVAL; } static inline void pcie_disable_tph(struct pci_dev *pdev) { } static inline int pcie_enable_tph(struct pci_dev *pdev, int mode) -- 2.17.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:21:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:21:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269979.1558828 (Exim 4.92) (envelope-from ) id 1w7qp1-00034X-UC; Wed, 01 Apr 2026 08:21:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269979.1558828; Wed, 01 Apr 2026 08:21:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qp1-00034Q-RS; Wed, 01 Apr 2026 08:21:07 +0000 Received: by outflank-mailman (input) for mailman id 1269979; Wed, 01 Apr 2026 08:21:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qoz-00034J-Ot for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:21:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qox-000YMk-If for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:21:05 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd55d-2eae-0a2a0a5409dd-0a2a4501a526-36 for ; Wed, 01 Apr 2026 10:21:05 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd570-6fc9-0a2a45010019-d155802cbd2b-3 for ; Wed, 01 Apr 2026 10:21:04 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-486ff201041so64693665e9.1 for ; Wed, 01 Apr 2026 01:21:04 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0275be7d-d1d9-47ee-bec2-bfbbb90b4bae@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1775031664-B78FC185-2F43AE5F/0/0 X-purgate-type: clean X-purgate-size: 7091 On 01.04.2026 09:59, Mykyta Poturai wrote: > On 3/31/26 17:55, Jan Beulich wrote: >> On 09.03.2026 12:08, Mykyta Poturai wrote: >>> --- a/xen/drivers/vpci/header.c >>> +++ b/xen/drivers/vpci/header.c >>> @@ -175,76 +175,92 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, >>> >>> bool vpci_process_pending(struct vcpu *v) >>> { >>> - const struct pci_dev *pdev = v->vpci.pdev; >>> - struct vpci_header *header = NULL; >>> - unsigned int i; >>> - >>> - if ( !pdev ) >>> - return false; >>> - >>> - read_lock(&v->domain->pci_lock); >>> - >>> - if ( !pdev->vpci || (v->domain != pdev->domain) ) >>> + switch ( v->vpci.task ) >>> { >>> - v->vpci.pdev = NULL; >>> - read_unlock(&v->domain->pci_lock); >>> - return false; >>> - } >>> - >>> - header = &pdev->vpci->header; >>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>> + case MODIFY_MEMORY: >>> { >>> - struct vpci_bar *bar = &header->bars[i]; >>> - struct rangeset *mem = v->vpci.bar_mem[i]; >>> - struct map_data data = { >>> - .d = v->domain, >>> - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, >>> - .bar = bar, >>> - }; >>> - int rc; >>> + const struct pci_dev *pdev = v->vpci.memory.pdev; >>> + struct vpci_header *header = NULL; >>> + unsigned int i; >>> >>> - if ( rangeset_is_empty(mem) ) >>> - continue; >>> + if ( !pdev ) >>> + break; >>> >>> - rc = rangeset_consume_ranges(mem, map_range, &data); >>> + read_lock(&v->domain->pci_lock); >>> >>> - if ( rc == -ERESTART ) >>> + if ( !pdev->vpci || (v->domain != pdev->domain) ) >>> { >>> + v->vpci.memory.pdev = NULL; >>> read_unlock(&v->domain->pci_lock); >>> - return true; >>> + break; >>> } >>> >>> - if ( rc ) >>> + header = &pdev->vpci->header; >>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>> { >>> - spin_lock(&pdev->vpci->lock); >>> - /* Disable memory decoding unconditionally on failure. */ >>> - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, >>> - false); >>> - spin_unlock(&pdev->vpci->lock); >>> + struct vpci_bar *bar = &header->bars[i]; >>> + struct rangeset *mem = v->vpci.bar_mem[i]; >>> + struct map_data data = { >>> + .d = v->domain, >>> + .map = v->vpci.memory.cmd & PCI_COMMAND_MEMORY, >>> + .bar = bar, >>> + }; >>> + int rc; >>> + >>> + if ( rangeset_is_empty(mem) ) >>> + continue; >>> >>> - /* Clean all the rangesets */ >>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>> - if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>> - rangeset_purge(v->vpci.bar_mem[i]); >>> + rc = rangeset_consume_ranges(mem, map_range, &data); >>> >>> - v->vpci.pdev = NULL; >>> + if ( rc == -ERESTART ) >>> + { >>> + read_unlock(&v->domain->pci_lock); >>> + return true; >>> + } >>> >>> - read_unlock(&v->domain->pci_lock); >>> + if ( rc ) >>> + { >>> + spin_lock(&pdev->vpci->lock); >>> + /* Disable memory decoding unconditionally on failure. */ >>> + modify_decoding(pdev, v->vpci.memory.cmd & ~PCI_COMMAND_MEMORY, >>> + false); >>> + spin_unlock(&pdev->vpci->lock); >>> + >>> + /* Clean all the rangesets */ >>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>> + if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>> + rangeset_purge(v->vpci.bar_mem[i]); >>> + >>> + v->vpci.memory.pdev = NULL; >>> + >>> + read_unlock(&v->domain->pci_lock); >>> >>> - if ( !is_hardware_domain(v->domain) ) >>> - domain_crash(v->domain); >>> + if ( !is_hardware_domain(v->domain) ) >>> + domain_crash(v->domain); >>> >>> - return false; >>> + break; >>> + } >>> } >>> - } >>> - v->vpci.pdev = NULL; >>> + v->vpci.memory.pdev = NULL; >>> >>> - spin_lock(&pdev->vpci->lock); >>> - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); >>> - spin_unlock(&pdev->vpci->lock); >>> + spin_lock(&pdev->vpci->lock); >>> + modify_decoding(pdev, v->vpci.memory.cmd, v->vpci.memory.rom_only); >>> + spin_unlock(&pdev->vpci->lock); >>> >>> - read_unlock(&v->domain->pci_lock); >>> + read_unlock(&v->domain->pci_lock); >>> + >>> + break; >>> + } >>> + case WAIT: >>> + if ( NOW() < v->vpci.wait.end ) >>> + return true; >>> + v->vpci.wait.callback(v->vpci.wait.data); >>> + break; >> >> As just indicated in reply to patch 6, busy waiting isn't really acceptable. >> This is even more so when the waiting exceeds the typical length of a >> scheduling timeslice. >> >> In that other reply I said to put the vCPU to sleep, but you need to be careful >> there too: The domain may not expect its vCPU to not make any progress for such >> an extended period of time. This may need doing entirely differently: Once the >> command register was written, you may want to record the time after which >> accesses to the VF registers are permitted. Earlier accesses would simply be >> terminated. You may still additionally need a timer, in order to kick off BAR >> mapping after that time. (Yet better would be if the BAR mapping could be >> done during those 100ms. After all that may be a reason why this long a delay >> is specified: Firmware on the device may also require some time to set up the >> BARs accordingly.) > > I am not sure it would work that way. If we look at how linux > initialized sriov, it writes VFE and MSE bits, waits 100ms and then > expects VFs to be operational. If they are not operational at that > moment, then it considers the operation failed and removes all VFs. If > we also wait 100ms before enabling access, the probability of a guest > trying to access something before we allow it would be very high. Well, not really. Our counting of the 100ms necessarily starts before Dom0's. Furthermore it may be acceptable (or even appropriate) to stall premature accesses (because they shouldn't occur in the first place), by blocking the vCPU at that point. A middle route may be possible: Terminate accesses in, say, the first 90ms, and stall the vCPU for any access past that, but before the 100ms expired. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:22:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:22:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1269993.1558837 (Exim 4.92) (envelope-from ) id 1w7qqf-0003dT-Cf; Wed, 01 Apr 2026 08:22:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1269993.1558837; Wed, 01 Apr 2026 08:22:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qqf-0003dM-90; Wed, 01 Apr 2026 08:22:49 +0000 Received: by outflank-mailman (input) for mailman id 1269993; Wed, 01 Apr 2026 08:22:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7qqd-0003dE-Jg for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:22:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7qqc-00AToi-Uv for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:22:46 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccd5d5-e002-0a2a0a5209dd-0a2a450be3d6-8 for ; Wed, 01 Apr 2026 10:22:46 +0200 Received: from [113.46.200.225] (helo=canpmsgout10.his.huawei.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccd5d3-bca8-0a2a450b0019-712ec8e14828-3 for ; Wed, 01 Apr 2026 10:22:46 +0200 Received: from mail.maildlp.com (unknown [172.19.162.92]) by canpmsgout10.his.huawei.com (SkyGuard) with ESMTPS id 4flyW63nb4z1K9VW; Wed, 1 Apr 2026 16:16:34 +0800 (CST) Received: from kwepemk500009.china.huawei.com (unknown [7.202.194.94]) by mail.maildlp.com (Postfix) with ESMTPS id 071664056C; Wed, 1 Apr 2026 16:22:42 +0800 (CST) Received: from [10.67.121.161] (10.67.121.161) by kwepemk500009.china.huawei.com (7.202.194.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 1 Apr 2026 16:22:40 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=dkim header.d=huawei.com header.i="@huawei.com" header.h=From dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=MTNaVMsdonTBgQUg0Ejtg6uI8JOpWHbQuBn8i2Muytk=; b=zfVqdZWZzivpJLTuZeEYbETVgUbpjxcc6vmJiz9VmBmGK7+p3ocbi7KhRl4SW1imGIWS+H+/S GEL7RNT6jhEzLuaPxUUhmMIjHBiCm2o5aipjEt5QgHPSsV8YAFhEn4y9speX8o0Hs3CLk5Jp28M LXlEaI+zkFwl4t8bQIqGT9w= Message-ID: <504b43e1-fa7d-4694-b8af-fe4975823db3@huawei.com> Date: Wed, 1 Apr 2026 16:22:39 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 0/8] ACPI: Unify CPU UID interface and fix ARM64 TPH steer-tag issue To: "Rafael J. Wysocki" CC: Bjorn Helgaas , Catalin Marinas , Will Deacon , Jonathan Corbet , Palmer Dabbelt , Borislav Petkov , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , , , , , , , , , , , , , , , , , , , , , , References: <20260320031737.35048-1-fengchengwen@huawei.com> Content-Language: en-US From: fengchengwen In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.121.161] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To kwepemk500009.china.huawei.com (7.202.194.94) X-purgate-ID: tlsNG-42698a/1775031766-F5BC22A1-E052D146/0/0 X-purgate-type: clean X-purgate-size: 3381 On 3/31/2026 8:24 PM, Rafael J. Wysocki wrote: > On Fri, Mar 20, 2026 at 4:17 AM Chengwen Feng wrote: >> >> This patchset unifies ACPI Processor UID retrieval across >> arm64/loongarch/riscv/x86 via acpi_get_cpu_uid() (with input validation) >> and fixes ARM64 CPU steer-tag retrieval failure in PCI/TPH: >> >> 1-4: Add acpi_get_cpu_uid() for arm64/loongarch/riscv/x86 (update >> respective users) >> 5: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h >> 6: Clean up perf/arm_cspmu >> 7: Clean up ACPI/PPTT and remove unused get_acpi_id_for_cpu() >> 8: Pass ACPI Processor UID to Cache Locality _DSM >> >> The interface refactor ensures consistent CPU UID retrieval across >> architectures (no functional changes for valid inputs) and provides the >> unified interface required for the ARM64 TPH fix. >> >> --- >> Changes in v10: >> - Refine commit header&log according to Punit's and Bjorn's review >> - Split perf/arm_cspmu as a separate commit which address Punit's >> review >> >> Changes in v9: >> - Address Bjorn's review: split commits to each platform so that make >> them easy to review >> >> Changes in v8: >> - Moving arm64's get_cpu_for_acpi_id() to kernel/acpi.c which address >> Jeremy's review >> >> Chengwen Feng (8): >> arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval >> LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval >> RISC-V: ACPI: Add acpi_get_cpu_uid() for unified ACPI CPU UID >> retrieval >> x86/acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval >> ACPI: Centralize acpi_get_cpu_uid() declaration in >> include/linux/acpi.h >> perf: arm_cspmu: Switch to acpi_get_cpu_uid() from >> get_acpi_id_for_cpu() >> ACPI: PPTT: Use acpi_get_cpu_uid() and remove get_acpi_id_for_cpu() >> PCI/TPH: Pass ACPI Processor UID to Cache Locality _DSM >> >> Documentation/PCI/tph.rst | 4 +-- >> arch/arm64/include/asm/acpi.h | 17 +--------- >> arch/arm64/kernel/acpi.c | 30 ++++++++++++++++++ >> arch/loongarch/include/asm/acpi.h | 5 --- >> arch/loongarch/kernel/acpi.c | 9 ++++++ >> arch/riscv/include/asm/acpi.h | 4 --- >> arch/riscv/kernel/acpi.c | 16 ++++++++++ >> arch/riscv/kernel/acpi_numa.c | 9 ++++-- >> arch/x86/include/asm/cpu.h | 1 - >> arch/x86/include/asm/smp.h | 1 - >> arch/x86/kernel/acpi/boot.c | 20 ++++++++++++ >> arch/x86/xen/enlighten_hvm.c | 5 +-- >> drivers/acpi/pptt.c | 50 ++++++++++++++++++++++-------- >> drivers/acpi/riscv/rhct.c | 7 ++++- >> drivers/pci/tph.c | 16 +++++++--- >> drivers/perf/arm_cspmu/arm_cspmu.c | 6 ++-- >> include/linux/acpi.h | 11 +++++++ >> include/linux/pci-tph.h | 4 +-- >> 18 files changed, 158 insertions(+), 57 deletions(-) >> >> -- > > It doesn't look like anyone has a particular heartburn related to this > series, so I could apply it in principle, but I'd appreciate some ACKs > from arch maintainers. > > Why don't you resend it with all of the tags collected so far (and > please add x86@kernel.org to the CC list)? done for resend v10 which with all the review/ack tag, add add x86@kernel.org to CC list Thanks From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:49:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:49:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270015.1558845 (Exim 4.92) (envelope-from ) id 1w7rGX-0008DQ-BN; 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AJvYcCVrKJEphbdlGtDTSYnujoh2zcRbEkMwPV7jnPbMAYMlUK+crzQml2d33NGBJVyXMtItXvQX5AaXJeU=@lists.xenproject.org X-Gm-Message-State: AOJu0YwoBu9bnyVslSLsy8viWHwGMx4RpSh+cys9yGL6Pw8j1ZERjNNf +OYRRoN6xyq2vr5NaBFR/UPE3YgkraxlbBZ3SM4eFIshNqc3k3SmwfW0YS76IKGPHnJilxPos3S RAj66qoU1p3O117cNFUXPLhjwlC/jUPw= X-Gm-Gg: ATEYQzyl4FV/6jOtz9Vi4e+sbLftxdlDFVxUrwgfTeflGYkT2WLp0WyATRsj/iaOCq/ 9/lpSegwXnNGJt1jiRRY82xwTwRbejyDDQhfgdeHwLMd328mGrI+exgT9yNNDso9kwrRE9cdeCw Rkd/khG8D3LreaI0arytweZTjr68zdmHSnhmaZwCXaOJ7XzVvOexL+7wB7+E0rX0dgKui4dNf5Y Rgjk3fd4TH5ftcHCJBidR7vfJnUlLajH1mkU1Rzh1mq3FyME1ToSoIBeTrvyQfSFAZ6tN3J5tNR hOFq X-Received: by 2002:ac2:5fcc:0:b0:5a2:c433:a82 with SMTP id 2adb3069b0e04-5a2c4330ad9mr361667e87.2.1775033370462; Wed, 01 Apr 2026 01:49:30 -0700 (PDT) MIME-Version: 1.0 References: <5b16e00e-9a4d-4a18-8a5e-dde10b42a043@suse.com> In-Reply-To: <5b16e00e-9a4d-4a18-8a5e-dde10b42a043@suse.com> From: Mykola Kvach Date: Wed, 1 Apr 2026 11:49:19 +0300 X-Gm-Features: AQROBzCpNjKvUG3SbuecfJwM4JlrHWgyfWLx9uPuD5FWJ92wv9TITUcMGszK-04 Message-ID: Subject: Re: [PATCH v3] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments To: Jan Beulich Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , xen-devel@lists.xenproject.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1775033371-5D92A3D8-9BBE9142/0/0 X-purgate-type: clean X-purgate-size: 4968 On Wed, Apr 1, 2026 at 11:14=E2=80=AFAM Jan Beulich wro= te: > > On 01.04.2026 09:13, Mykola Kvach wrote: > > Hi Jan, > > > > On Wed, Apr 1, 2026 at 9:29=E2=80=AFAM Jan Beulich = wrote: > >> > >> On 31.03.2026 20:31, Mykola Kvach wrote: > >>> From: Mykola Kvach > >>> > >>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls > >>> using Wn, only the least significant 32 bits are significant and the > >>> upper 32 bits must be ignored by the implementation. > >>> > >>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in th= e > >>> argument registers as an error. Instead, they should be discarded whe= n > >>> decoding the arguments. > >>> > >>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may b= e > >>> implementation defined when entering from AArch32. Xen zeros them on > >>> entry, but that guarantee is only relevant for 32-bit domains. > >>> > >>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPE= ND > >>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 > >>> handling unchanged. > >>> > >>> No functional change is intended for PSCI 0.1. > >>> > >>> Suggested-by: Julien Grall > >>> Signed-off-by: Mykola Kvach > >>> Reviewed-by: Bertrand Marquis > >> > >> I thought I might as well include this in my next commit sweep, but is= n't > >> this R-b being invalidated by ... > >> > >>> --- > >>> v3: > >>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND > >> > >> ... this change. That's ... > >> > >>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *reg= s, uint32_t fid) > >>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: > >>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: > >>> { > >>> - register_t epoint =3D PSCI_ARG(regs, 1); > >>> - register_t cid =3D PSCI_ARG(regs, 2); > >>> - > >>> - if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND ) > >>> - { > >>> - epoint &=3D GENMASK(31, 0); > >>> - cid &=3D GENMASK(31, 0); > >>> - } > >>> + register_t epoint =3D PSCI_ARG_CONV(regs, 1, is_conv_64); > >>> + register_t cid =3D PSCI_ARG_CONV(regs, 2, is_conv_64); > >>> > >>> perfc_incr(vpsci_system_suspend); > >>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid= )); > >> > >> ... this hunk aiui, which is far from merely cosmetic imo. While > > > > Nobody said that the change had to be purely cosmetic in order to keep > > the tag. I understood it differently from the official Xen > > documentation pages. > > > >> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it > > > > Exactly. If the changes are not substantial, I do not see a reason to > > drop the tag ... > > > >> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended > >> and for the better, but the change clearly wasn't reviewed by Bertrand= , > >> nor - when offering the R-b - did he ask for this extra change. > > > > ... and this is also how I understood the Xen patch submission > > guidelines [1], which say: > > > > "Note that if there are several revisions of a patch, you ought to > > copy tags that have accumulated during the review. For example, if > > person A and person B added a Reviewed-by: tag to v1 of your patch, > > include it into v2 of your patch. If you make substantial changes > > after certain tags were already applied, you will want to consider > > which ones are no longer applicable (and may require re-providing)." > > > > So my understanding was that tags should normally be kept across > > revisions, unless the changes are substantial enough to make them no > > longer applicable. > > Maybe our understanding of "substantial" differs. To me that's anything > changing functionality. Style adjustments, typo corrections, and alike > generally aren't substantial (albeit even then there may be exceptions). Thanks for clarifying what you consider substantial. Even under that interpretation, I do not see a functionality change here. "Refactoring" seems like the more accurate term in this case: the internal form changes, but the intended external behavior does not. It may be that we are using "functional change" in slightly different senses here. For v3, the switch to PSCI_ARG_CONV() in SYSTEM_SUSPEND was meant to make this case consistent with the helper-based argument decoding used elsewhere, not to change behavior. In particular, I do not see a functional change for PSCI_1_0_FN64_SYSTEM_SUSPEND: v2 used PSCI_ARG(regs, 1/2), and in v3 PSCI_ARG_CONV(regs, 1/2, is_conv_64) should resolve to the same thing when is_conv_64 is true. If I am missing a behavioral difference in the FN64 case, please point out which one. Best regards, Mykola > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 08:52:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 08:52:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270025.1558855 (Exim 4.92) (envelope-from ) id 1w7rJZ-0001GE-Of; Wed, 01 Apr 2026 08:52:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270025.1558855; Wed, 01 Apr 2026 08:52:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7rJZ-0001G7-Ln; Wed, 01 Apr 2026 08:52:41 +0000 Received: by outflank-mailman (input) for mailman id 1270025; Wed, 01 Apr 2026 08:52:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7rJY-0001G1-3D for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 08:52:40 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7rJV-000i76-Ti for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 10:52:39 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ccdcd4-2eae-0a2a0a5409dd-0a2a450496b4-18 for ; Wed, 01 Apr 2026 10:52:39 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ccdcd7-bb33-0a2a45040019-d155802ad1a9-3 for ; Wed, 01 Apr 2026 10:52:39 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4853e1ce427so81441185e9.3 for ; Wed, 01 Apr 2026 01:52:39 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 01 Apr 2026 01:52:38 -0700 (PDT) Message-ID: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> Date: Wed, 1 Apr 2026 10:52:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 From: Jan Beulich To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1775033559-B253B51B-6B86F8DE/0/0 X-purgate-type: clean X-purgate-size: 3397 On 01.04.2026 09:14, Jan Beulich wrote: > On 27.03.2026 11:19, Marek Marczykowski-Górecki wrote: >> I noticed that on some systems, there are a lot of IOMMU faults after >> S3. I can see it also on a laptop with MTL, but it affects also the ADL >> gitlab runner: >> >> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 >> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >> >> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. >> >> The issue is present only on staging, not staging-4.21. >> >> Bisect says: >> >> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit >> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b >> Author: Jan Beulich >> Date: Thu Jan 22 14:13:35 2026 +0100 >> >> x86/HPET: drop .set_affinity hook > > Looking into this, I find several things I can't quite understand (yet). > First there is > > (XEN) [000000456c0fe39f] Disabling HPET for being unreliable > > which looks to only affect clocksource selection, but not use as > broadcast source for CPU-idle management. (This may be an independent > issue.) > > Then there is > > (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) > > which should only occur on ARAT-incapable systems. That should only be > older hardware. (On my much older Skylake I don't see this line, for > example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid > is purely featureset based, and hence doesn't expose info about that > leaf. The leaf also isn't exposed to domains, so CPUID output in Dom0 > isn't useful to look at either. It would need to be CPUID output on a > bare metal kernel. > > Further I suspect the fingered commit may only have uncovered an issue > elsewhere. I don't think we clear any context table entries during > suspend or resume. Hence in > > (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 > (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context entry is clear > > the latter message is confusing me. > > The fault address being zero may, otoh, be a hint of hpet_msi_write() > never having run post-resume. Which may be the connection to the > dropping of hpet_msi_set_affinity(), as that did call that function. There clearly is an issue with the handling of the max_cstate variable, but I expect you don't use xenpm to limit usable C-states (there clearly is no respective command line option in the log you referenced)? >From what the log has, I conclude hpet_broadcast_resume() is called. Question is whether it does what we want it to. Could you instrument it some, so we have confirmation that it is called, and we also know whether __hpet_setup_msi_irq() is not only called on all 8 channels, but also succeeds there? (If it failed, I suppose we better wouldn't set HPET_TN_FSB and/or HPET_TN_ENABLE.) If, however, it succeeds, I couldn't explain why the fault address would be reported as 0, as then we definitely must have written HPET_Tn_ROUTE. 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Wed, 01 Apr 2026 01:58:51 -0700 (PDT) Message-ID: <69782260-4d92-4979-b624-9c5c6e9a4cba@suse.com> Date: Wed, 1 Apr 2026 10:58:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 From: Jan Beulich To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775033932-2312596F-A91EE571/0/0 X-purgate-type: clean X-purgate-size: 759 On 01.04.2026 09:14, Jan Beulich wrote: > Further I suspect the fingered commit may only have uncovered an issue > elsewhere. I don't think we clear any context table entries during > suspend or resume. Hence in > > (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 > (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context entry is clear > > the latter message is confusing me. Actually, it makes sense. The address being outside of the interrupt remap MMIO window (FEExxxxx), it's subject to DMA translation. Yet the HPET has no entry in the context table; only its IRQs have entries in the intremap table. So it really all looks to be boiling down to missing HPET_Tn_ROUTE writes. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775035329-5C9223D8-BC893BCF/0/0 X-purgate-type: clean X-purgate-size: 5739 On 01.04.2026 10:49, Mykola Kvach wrote: > On Wed, Apr 1, 2026 at 11:14 AM Jan Beulich wrote: >> On 01.04.2026 09:13, Mykola Kvach wrote: >>> On Wed, Apr 1, 2026 at 9:29 AM Jan Beulich wrote: >>>> On 31.03.2026 20:31, Mykola Kvach wrote: >>>>> From: Mykola Kvach >>>>> >>>>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls >>>>> using Wn, only the least significant 32 bits are significant and the >>>>> upper 32 bits must be ignored by the implementation. >>>>> >>>>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the >>>>> argument registers as an error. Instead, they should be discarded when >>>>> decoding the arguments. >>>>> >>>>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be >>>>> implementation defined when entering from AArch32. Xen zeros them on >>>>> entry, but that guarantee is only relevant for 32-bit domains. >>>>> >>>>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND >>>>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 >>>>> handling unchanged. >>>>> >>>>> No functional change is intended for PSCI 0.1. >>>>> >>>>> Suggested-by: Julien Grall >>>>> Signed-off-by: Mykola Kvach >>>>> Reviewed-by: Bertrand Marquis >>>> >>>> I thought I might as well include this in my next commit sweep, but isn't >>>> this R-b being invalidated by ... >>>> >>>>> --- >>>>> v3: >>>>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND >>>> >>>> ... this change. That's ... >>>> >>>>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) >>>>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: >>>>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: >>>>> { >>>>> - register_t epoint = PSCI_ARG(regs, 1); >>>>> - register_t cid = PSCI_ARG(regs, 2); >>>>> - >>>>> - if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND ) >>>>> - { >>>>> - epoint &= GENMASK(31, 0); >>>>> - cid &= GENMASK(31, 0); >>>>> - } >>>>> + register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64); >>>>> + register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64); >>>>> >>>>> perfc_incr(vpsci_system_suspend); >>>>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid)); >>>> >>>> ... this hunk aiui, which is far from merely cosmetic imo. While >>> >>> Nobody said that the change had to be purely cosmetic in order to keep >>> the tag. I understood it differently from the official Xen >>> documentation pages. >>> >>>> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it >>> >>> Exactly. If the changes are not substantial, I do not see a reason to >>> drop the tag ... >>> >>>> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended >>>> and for the better, but the change clearly wasn't reviewed by Bertrand, >>>> nor - when offering the R-b - did he ask for this extra change. >>> >>> ... and this is also how I understood the Xen patch submission >>> guidelines [1], which say: >>> >>> "Note that if there are several revisions of a patch, you ought to >>> copy tags that have accumulated during the review. For example, if >>> person A and person B added a Reviewed-by: tag to v1 of your patch, >>> include it into v2 of your patch. If you make substantial changes >>> after certain tags were already applied, you will want to consider >>> which ones are no longer applicable (and may require re-providing)." >>> >>> So my understanding was that tags should normally be kept across >>> revisions, unless the changes are substantial enough to make them no >>> longer applicable. >> >> Maybe our understanding of "substantial" differs. To me that's anything >> changing functionality. Style adjustments, typo corrections, and alike >> generally aren't substantial (albeit even then there may be exceptions). > > Thanks for clarifying what you consider substantial. > > Even under that interpretation, I do not see a functionality change > here. "Refactoring" seems like the more accurate term in this case: > the internal form changes, but the intended external behavior does > not. > > It may be that we are using "functional change" in slightly different > senses here. > > For v3, the switch to PSCI_ARG_CONV() in SYSTEM_SUSPEND was meant to > make this case consistent with the helper-based argument decoding used > elsewhere, not to change behavior. > > In particular, I do not see a functional change for > PSCI_1_0_FN64_SYSTEM_SUSPEND: v2 used PSCI_ARG(regs, 1/2), and in v3 > PSCI_ARG_CONV(regs, 1/2, is_conv_64) should resolve to the same thing > when is_conv_64 is true. Isn't the whole point of the patch to alter behavior when is_conv_64 is false? For that case PSCI_1_0_FN64_SYSTEM_SUSPEND behavior looks to change in v3, when it didn't in v2. Whereas for PSCI_1_0_FN32_SYSTEM_SUSPEND the v3 change indeed only eliminates open- coding, which one may or may not regard as "substantial". Personally I'm taking what's written in a pretty strict sense: If in doubt, drop tags which may no longer cover all changes they would apply to. (This is, in my interpretation, generally less of a problem for A-b, as that only conveys "this kind of change is okay to make", without covering much of the details. In the case here retaining A-b would probably have been acceptable, albeit there's still room for interpretation. For example, if an A-b was offered based on somebody else's R-b, then likely the A-b would need dropping if the R-b is dropped.) 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Wed, 01 Apr 2026 02:51:11 -0700 (PDT) MIME-Version: 1.0 References: <5b16e00e-9a4d-4a18-8a5e-dde10b42a043@suse.com> <5fb9b5ee-ee71-49ec-b545-62c8ec27fc15@suse.com> In-Reply-To: <5fb9b5ee-ee71-49ec-b545-62c8ec27fc15@suse.com> From: Mykola Kvach Date: Wed, 1 Apr 2026 12:51:00 +0300 X-Gm-Features: AQROBzB70yO3YCeggq1-mH2mrx_MlMC40IhOrPlmmwIj0lwROslqAZfropiRQ-0 Message-ID: Subject: Re: [PATCH v3] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments To: Jan Beulich Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , xen-devel@lists.xenproject.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1775037072-1079541E-8B15F73D/0/0 X-purgate-type: clean X-purgate-size: 6707 On Wed, Apr 1, 2026 at 12:22=E2=80=AFPM Jan Beulich wro= te: > > On 01.04.2026 10:49, Mykola Kvach wrote: > > On Wed, Apr 1, 2026 at 11:14=E2=80=AFAM Jan Beulich = wrote: > >> On 01.04.2026 09:13, Mykola Kvach wrote: > >>> On Wed, Apr 1, 2026 at 9:29=E2=80=AFAM Jan Beulich wrote: > >>>> On 31.03.2026 20:31, Mykola Kvach wrote: > >>>>> From: Mykola Kvach > >>>>> > >>>>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls > >>>>> using Wn, only the least significant 32 bits are significant and th= e > >>>>> upper 32 bits must be ignored by the implementation. > >>>>> > >>>>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in = the > >>>>> argument registers as an error. Instead, they should be discarded w= hen > >>>>> decoding the arguments. > >>>>> > >>>>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may= be > >>>>> implementation defined when entering from AArch32. Xen zeros them o= n > >>>>> entry, but that guarantee is only relevant for 32-bit domains. > >>>>> > >>>>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUS= PEND > >>>>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 > >>>>> handling unchanged. > >>>>> > >>>>> No functional change is intended for PSCI 0.1. > >>>>> > >>>>> Suggested-by: Julien Grall > >>>>> Signed-off-by: Mykola Kvach > >>>>> Reviewed-by: Bertrand Marquis > >>>> > >>>> I thought I might as well include this in my next commit sweep, but = isn't > >>>> this R-b being invalidated by ... > >>>> > >>>>> --- > >>>>> v3: > >>>>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND > >>>> > >>>> ... this change. That's ... > >>>> > >>>>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *r= egs, uint32_t fid) > >>>>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: > >>>>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: > >>>>> { > >>>>> - register_t epoint =3D PSCI_ARG(regs, 1); > >>>>> - register_t cid =3D PSCI_ARG(regs, 2); > >>>>> - > >>>>> - if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND ) > >>>>> - { > >>>>> - epoint &=3D GENMASK(31, 0); > >>>>> - cid &=3D GENMASK(31, 0); > >>>>> - } > >>>>> + register_t epoint =3D PSCI_ARG_CONV(regs, 1, is_conv_64); > >>>>> + register_t cid =3D PSCI_ARG_CONV(regs, 2, is_conv_64); > >>>>> > >>>>> perfc_incr(vpsci_system_suspend); > >>>>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, c= id)); > >>>> > >>>> ... this hunk aiui, which is far from merely cosmetic imo. While > >>> > >>> Nobody said that the change had to be purely cosmetic in order to kee= p > >>> the tag. I understood it differently from the official Xen > >>> documentation pages. > >>> > >>>> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, = it > >>> > >>> Exactly. If the changes are not substantial, I do not see a reason to > >>> drop the tag ... > >>> > >>>> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intend= ed > >>>> and for the better, but the change clearly wasn't reviewed by Bertra= nd, > >>>> nor - when offering the R-b - did he ask for this extra change. > >>> > >>> ... and this is also how I understood the Xen patch submission > >>> guidelines [1], which say: > >>> > >>> "Note that if there are several revisions of a patch, you ought to > >>> copy tags that have accumulated during the review. For example, if > >>> person A and person B added a Reviewed-by: tag to v1 of your patch, > >>> include it into v2 of your patch. If you make substantial changes > >>> after certain tags were already applied, you will want to consider > >>> which ones are no longer applicable (and may require re-providing)." > >>> > >>> So my understanding was that tags should normally be kept across > >>> revisions, unless the changes are substantial enough to make them no > >>> longer applicable. > >> > >> Maybe our understanding of "substantial" differs. To me that's anythin= g > >> changing functionality. Style adjustments, typo corrections, and alike > >> generally aren't substantial (albeit even then there may be exceptions= ). > > > > Thanks for clarifying what you consider substantial. > > > > Even under that interpretation, I do not see a functionality change > > here. "Refactoring" seems like the more accurate term in this case: > > the internal form changes, but the intended external behavior does > > not. > > > > It may be that we are using "functional change" in slightly different > > senses here. > > > > For v3, the switch to PSCI_ARG_CONV() in SYSTEM_SUSPEND was meant to > > make this case consistent with the helper-based argument decoding used > > elsewhere, not to change behavior. > > > > In particular, I do not see a functional change for > > PSCI_1_0_FN64_SYSTEM_SUSPEND: v2 used PSCI_ARG(regs, 1/2), and in v3 > > PSCI_ARG_CONV(regs, 1/2, is_conv_64) should resolve to the same thing > > when is_conv_64 is true. > > Isn't the whole point of the patch to alter behavior when is_conv_64 is > false? For that case PSCI_1_0_FN64_SYSTEM_SUSPEND behavior looks to > change in v3, when it didn't in v2. Whereas for > PSCI_1_0_FN32_SYSTEM_SUSPEND the v3 change indeed only eliminates open- > coding, which one may or may not regard as "substantial". I think the point I was trying to make is slightly narrower: in this code path, is_conv_64 is derived directly from fid via smccc_is_conv_64(fid) before the switch (fid). So for PSCI_1_0_FN64_SYSTEM_SUSPEND, I do not see how is_conv_64 =3D=3D false could arise here: if we are in the FN64 case, the function ID already encodes the 64-bit convention. Conversely, if is_conv_64 is false here, then this cannot be the FN64 case. On that basis, I do not see a behavioral change for the FN64 SYSTEM_SUSPEND case in v3. Best regards, Mykola > > Personally I'm taking what's written in a pretty strict sense: If in > doubt, drop tags which may no longer cover all changes they would > apply to. (This is, in my interpretation, generally less of a problem > for A-b, as that only conveys "this kind of change is okay to make", > without covering much of the details. In the case here retaining A-b > would probably have been acceptable, albeit there's still room for > interpretation. For example, if an A-b was offered based on somebody > else's R-b, then likely the A-b would need dropping if the R-b is > dropped.) > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 10:42:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 10:42:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270116.1558895 (Exim 4.92) (envelope-from ) id 1w7t1z-00028O-3h; Wed, 01 Apr 2026 10:42:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270116.1558895; Wed, 01 Apr 2026 10:42:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7t1z-00028H-0Z; Wed, 01 Apr 2026 10:42:39 +0000 Received: by outflank-mailman (input) for mailman id 1270116; Wed, 01 Apr 2026 10:42:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7t1x-000287-OI for xen-devel@lists.xenproject.org; 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Message-ID: <2e6e0203-da8b-4261-8817-f4590350f8c9@epam.com> Date: Wed, 1 Apr 2026 13:42:33 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/sched: rtds: prevent extratime priority_level wraparound To: Jan Beulich Cc: Dario Faggioli , George Dunlap , Juergen Gross , Meng Xu , "xen-devel@lists.xenproject.org" References: <5b1e5de7-b2b0-4dae-bbe6-03809637d239@suse.com> Content-Language: en-US From: Oleksii Moisieiev In-Reply-To: <5b1e5de7-b2b0-4dae-bbe6-03809637d239@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: FR4P281CA0396.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:cf::10) To DU5PR03MB10263.eurprd03.prod.outlook.com (2603:10a6:10:519::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU5PR03MB10263:EE_|PAVPR03MB9139:EE_ X-MS-Office365-Filtering-Correlation-Id: 71a786e5-97f3-4de0-81d5-08de8fdb626a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024|56012099003|22082099003|18002099003; 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Should I post another version with "Fixes:" or it could be added to the commit message during merge? -- Oleksii On 31/03/2026 11:10, Jan Beulich wrote: > On 31.03.2026 09:54, Oleksii Moisieiev wrote: >> In RTDS, burn_budget() increments priority_level for extratime units >> whenever cur_budget is exhausted. As priority_level is unsigned and was >> unbounded, it could eventually overflow to 0. >> >> A wrapped value of 0 is the highest RTDS priority, so an extratime unit >> could unexpectedly regain top priority and preempt units with active >> real-time reservations, violating EDF intent. >> >> Fix this by saturating priority_level at RTDS_MAX_PRIORITY_LEVEL instead >> of incrementing unconditionally. Budget refill semantics are unchanged. >> >> Normal behavior is unchanged. Once saturated, priority_level remains at >> the lowest priority until the next period update resets it. >> >> Signed-off-by: Oleksii Moisieiev > From the description, this looks to want to have a Fixes: tag added. > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:03:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:03:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270156.1558904 (Exim 4.92) (envelope-from ) id 1w7uIP-0004xW-U4; Wed, 01 Apr 2026 12:03:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270156.1558904; Wed, 01 Apr 2026 12:03:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uIP-0004xP-RR; Wed, 01 Apr 2026 12:03:41 +0000 Received: by outflank-mailman (input) for mailman id 1270156; Wed, 01 Apr 2026 12:03:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uIO-0004wz-Kq for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:03:40 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7uIO-00BHgK-0Y for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:03:40 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd0999-e002-0a2a0a5209dd-0a2a4502e3f0-8 for ; Wed, 01 Apr 2026 14:03:39 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd099b-42fa-0a2a45020019-d155802ed0a6-3 for ; Wed, 01 Apr 2026 14:03:39 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-48702d51cd0so80262575e9.2 for ; Wed, 01 Apr 2026 05:03:39 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2e6e0203-da8b-4261-8817-f4590350f8c9@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775045019-4792ECD1-649FF7FD/0/0 X-purgate-type: clean X-purgate-size: 341 On 01.04.2026 12:42, Oleksii Moisieiev wrote: > I have an R-b from Juergen. Should I post another version with "Fixes:" > > or it could be added to the commit message during merge? It can be folded in while committing, sure, but first you need to collect a maintainer ack. See also "The meaning of nesting" in ./MAINTAINERS. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775046300-F4F5A497-C9044C30/0/0 X-purgate-type: clean X-purgate-size: 6421 On 01.04.2026 11:51, Mykola Kvach wrote: > On Wed, Apr 1, 2026 at 12:22 PM Jan Beulich wrote: >> On 01.04.2026 10:49, Mykola Kvach wrote: >>> On Wed, Apr 1, 2026 at 11:14 AM Jan Beulich wrote: >>>> On 01.04.2026 09:13, Mykola Kvach wrote: >>>>> On Wed, Apr 1, 2026 at 9:29 AM Jan Beulich wrote: >>>>>> On 31.03.2026 20:31, Mykola Kvach wrote: >>>>>>> From: Mykola Kvach >>>>>>> >>>>>>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC calls >>>>>>> using Wn, only the least significant 32 bits are significant and the >>>>>>> upper 32 bits must be ignored by the implementation. >>>>>>> >>>>>>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits in the >>>>>>> argument registers as an error. Instead, they should be discarded when >>>>>>> decoding the arguments. >>>>>>> >>>>>>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits may be >>>>>>> implementation defined when entering from AArch32. Xen zeros them on >>>>>>> entry, but that guarantee is only relevant for 32-bit domains. >>>>>>> >>>>>>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_SUSPEND >>>>>>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC64 >>>>>>> handling unchanged. >>>>>>> >>>>>>> No functional change is intended for PSCI 0.1. >>>>>>> >>>>>>> Suggested-by: Julien Grall >>>>>>> Signed-off-by: Mykola Kvach >>>>>>> Reviewed-by: Bertrand Marquis >>>>>> >>>>>> I thought I might as well include this in my next commit sweep, but isn't >>>>>> this R-b being invalidated by ... >>>>>> >>>>>>> --- >>>>>>> v3: >>>>>>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND >>>>>> >>>>>> ... this change. That's ... >>>>>> >>>>>>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid) >>>>>>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: >>>>>>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: >>>>>>> { >>>>>>> - register_t epoint = PSCI_ARG(regs, 1); >>>>>>> - register_t cid = PSCI_ARG(regs, 2); >>>>>>> - >>>>>>> - if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND ) >>>>>>> - { >>>>>>> - epoint &= GENMASK(31, 0); >>>>>>> - cid &= GENMASK(31, 0); >>>>>>> - } >>>>>>> + register_t epoint = PSCI_ARG_CONV(regs, 1, is_conv_64); >>>>>>> + register_t cid = PSCI_ARG_CONV(regs, 2, is_conv_64); >>>>>>> >>>>>>> perfc_incr(vpsci_system_suspend); >>>>>>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid)); >>>>>> >>>>>> ... this hunk aiui, which is far from merely cosmetic imo. While >>>>> >>>>> Nobody said that the change had to be purely cosmetic in order to keep >>>>> the tag. I understood it differently from the official Xen >>>>> documentation pages. >>>>> >>>>>> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEND, it >>>>> >>>>> Exactly. If the changes are not substantial, I do not see a reason to >>>>> drop the tag ... >>>>> >>>>>> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be intended >>>>>> and for the better, but the change clearly wasn't reviewed by Bertrand, >>>>>> nor - when offering the R-b - did he ask for this extra change. >>>>> >>>>> ... and this is also how I understood the Xen patch submission >>>>> guidelines [1], which say: >>>>> >>>>> "Note that if there are several revisions of a patch, you ought to >>>>> copy tags that have accumulated during the review. For example, if >>>>> person A and person B added a Reviewed-by: tag to v1 of your patch, >>>>> include it into v2 of your patch. If you make substantial changes >>>>> after certain tags were already applied, you will want to consider >>>>> which ones are no longer applicable (and may require re-providing)." >>>>> >>>>> So my understanding was that tags should normally be kept across >>>>> revisions, unless the changes are substantial enough to make them no >>>>> longer applicable. >>>> >>>> Maybe our understanding of "substantial" differs. To me that's anything >>>> changing functionality. Style adjustments, typo corrections, and alike >>>> generally aren't substantial (albeit even then there may be exceptions). >>> >>> Thanks for clarifying what you consider substantial. >>> >>> Even under that interpretation, I do not see a functionality change >>> here. "Refactoring" seems like the more accurate term in this case: >>> the internal form changes, but the intended external behavior does >>> not. >>> >>> It may be that we are using "functional change" in slightly different >>> senses here. >>> >>> For v3, the switch to PSCI_ARG_CONV() in SYSTEM_SUSPEND was meant to >>> make this case consistent with the helper-based argument decoding used >>> elsewhere, not to change behavior. >>> >>> In particular, I do not see a functional change for >>> PSCI_1_0_FN64_SYSTEM_SUSPEND: v2 used PSCI_ARG(regs, 1/2), and in v3 >>> PSCI_ARG_CONV(regs, 1/2, is_conv_64) should resolve to the same thing >>> when is_conv_64 is true. >> >> Isn't the whole point of the patch to alter behavior when is_conv_64 is >> false? For that case PSCI_1_0_FN64_SYSTEM_SUSPEND behavior looks to >> change in v3, when it didn't in v2. Whereas for >> PSCI_1_0_FN32_SYSTEM_SUSPEND the v3 change indeed only eliminates open- >> coding, which one may or may not regard as "substantial". > > I think the point I was trying to make is slightly narrower: in this > code path, is_conv_64 is derived directly from fid via > smccc_is_conv_64(fid) before the switch (fid). > > So for PSCI_1_0_FN64_SYSTEM_SUSPEND, I do not see how > is_conv_64 == false could arise here: if we are in the FN64 case, > the function ID already encodes the 64-bit convention. > > Conversely, if is_conv_64 is false here, then this cannot be the > FN64 case. Ah, I see. To figure that out, I would have had to do a proper review. I was after committing only, which ought to be an entirely mechanical step. > On that basis, I do not see a behavioral change for the FN64 > SYSTEM_SUSPEND case in v3. I agree (now). I'm still not going to pick up that patch, but rather leave it to the Arm maintainers. While not as clear cut as it first seemed to me, I still consider it within the grey area. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:29:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:29:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270187.1558921 (Exim 4.92) (envelope-from ) id 1w7uh3-0000an-0Q; Wed, 01 Apr 2026 12:29:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270187.1558921; Wed, 01 Apr 2026 12:29:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uh2-0000ae-U5; Wed, 01 Apr 2026 12:29:08 +0000 Received: by outflank-mailman (input) for mailman id 1270187; Wed, 01 Apr 2026 12:29:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uh2-0000aY-AA for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:29:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7uh1-005NjJ-MP for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:29:07 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd0f8b-5cb7-0a2a0a5109dd-0a2a450a9b3a-24 for ; Wed, 01 Apr 2026 14:29:07 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd0f93-ee98-0a2a450a0019-d1558036ed79-3 for ; Wed, 01 Apr 2026 14:29:07 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-48541edecf9so81879485e9.1 for ; Wed, 01 Apr 2026 05:29:07 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 01 Apr 2026 05:29:06 -0700 (PDT) Message-ID: <4a4c011e-9666-4416-be1b-33d1dcad5afe@suse.com> Date: Wed, 1 Apr 2026 14:29:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v3] arinc653: don't assume Dom0 is the control domain To: "xen-devel@lists.xenproject.org" Cc: Nathan Studer , Stewart Hildebrand , Juergen Gross References: <89d17a24-0a1f-4f3f-ac2f-f3701a8d78dd@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <89d17a24-0a1f-4f3f-ac2f-f3701a8d78dd@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775046547-0FB450B1-69CB6168/0/0 X-purgate-type: clean X-purgate-size: 1116 Leaving aside highly disaggregated environments, the control domain is what will invoke XEN_SYSCTL_SCHEDOP_putinfo. Its vCPU-s therefore need to be able to run unconditionally, not those of the domain with ID 0 (which may not exist at all). Fixes: 9f0c658baedc ("arinc: add cpu-pool support to scheduler") Signed-off-by: Jan Beulich --- There being no "else" to the if(), what about other control domain vCPU-s? --- v3: Don't mistakenly include the idle domain. v2: New. --- a/xen/common/sched/arinc653.c +++ b/xen/common/sched/arinc653.c @@ -411,10 +411,10 @@ a653sched_alloc_udata(const struct sched spin_lock_irqsave(&sched_priv->lock, flags); /* - * Add every one of dom0's units to the schedule, as long as there are - * slots available. + * Add every one of the control domain's units to the schedule, as long as + * there are slots available. */ - if ( unit->domain->domain_id == 0 ) + if ( is_control_domain(unit->domain) && !is_idle_domain(unit->domain) ) { entry = sched_priv->num_schedule_entries; From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:33:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:33:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270198.1558931 (Exim 4.92) (envelope-from ) id 1w7ulM-00027b-HS; Wed, 01 Apr 2026 12:33:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270198.1558931; Wed, 01 Apr 2026 12:33:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ulM-00027U-Em; Wed, 01 Apr 2026 12:33:36 +0000 Received: by outflank-mailman (input) for mailman id 1270198; Wed, 01 Apr 2026 12:33:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ulL-00027O-1l for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:33:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ulK-00C2Tg-Du for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:33:34 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd108d-5cb7-0a2a0a5109dd-0a2a4508dec8-40 for ; Wed, 01 Apr 2026 14:33:34 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd109e-fab6-0a2a45080019-d155802fbdec-3 for ; Wed, 01 Apr 2026 14:33:34 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-486ff201041so67496455e9.1 for ; Wed, 01 Apr 2026 05:33:34 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 01 Apr 2026 05:33:33 -0700 (PDT) Message-ID: <6d7b4344-8755-4dcd-a5bd-e7e5f982c11f@suse.com> Date: Wed, 1 Apr 2026 14:33:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Ping: [PATCH v2 0/2] EFI: cfg file parsing adjustments From: Jan Beulich To: Marek Marczykowski , Daniel Smith Cc: "xen-devel@lists.xenproject.org" References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775046814-7455F497-28268A60/0/0 X-purgate-type: clean X-purgate-size: 195 On 25.03.2026 14:22, Jan Beulich wrote: > 1: avoid OOB config file reads > 2: move pre_parse() back next to get_value() May I ask for feedback (preferably an ack, as you may guess)? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:35:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:35:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270211.1558940 (Exim 4.92) (envelope-from ) id 1w7umq-0002hi-VM; Wed, 01 Apr 2026 12:35:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270211.1558940; Wed, 01 Apr 2026 12:35:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7umq-0002hb-S2; Wed, 01 Apr 2026 12:35:08 +0000 Received: by outflank-mailman (input) for mailman id 1270211; Wed, 01 Apr 2026 12:35:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7ump-0002hV-Px for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:35:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7ump-002sCg-5k for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:35:07 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd10f9-e002-0a2a0a5209dd-0a2a450a8aa4-6 for ; Wed, 01 Apr 2026 14:35:07 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd10fa-ee98-0a2a450a0019-d155802ae90b-3 for ; Wed, 01 Apr 2026 14:35:07 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-486fba7ce4cso69026615e9.3 for ; Wed, 01 Apr 2026 05:35:06 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775046907-0FB450B1-86594997/0/0 X-purgate-type: clean X-purgate-size: 508 On 24.03.2026 17:34, Jan Beulich wrote: > A number of issues were identified by Kamil, by way of fuzzing. > > 1: EFI: avoid OOB config file reads Leaving aside this one, which was redone quite differently (and re-submitted independently), ... > 2: llc-coloring: improve checking while parsing > 3: ns16550: harden name/value pair parsing > 4: ns16550: harden positional parsing > 5: video/vesa: harden font height parsing ... may I ask for acks (or otherwise) on these ones? Thanks, Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:47:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:47:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270226.1558949 (Exim 4.92) (envelope-from ) id 1w7uzB-0004vY-2d; Wed, 01 Apr 2026 12:47:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270226.1558949; Wed, 01 Apr 2026 12:47:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uzA-0004vR-VX; Wed, 01 Apr 2026 12:47:52 +0000 Received: by outflank-mailman (input) for mailman id 1270226; Wed, 01 Apr 2026 12:47:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7uz9-0004vL-TC for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:47:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7uz9-005Rwc-8x for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:47:51 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd13ea-2eae-0a2a0a5409dd-0a2a4502c192-38 for ; Wed, 01 Apr 2026 14:47:51 +0200 Received: from [209.85.221.49] (helo=mail-wr1-f49.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd13f6-42fa-0a2a45020019-d155dd31dc64-3 for ; Wed, 01 Apr 2026 14:47:51 +0200 Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-43cfe71e5d3so2985690f8f.0 for ; Wed, 01 Apr 2026 05:47:51 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 01 Apr 2026 05:47:50 -0700 (PDT) Message-ID: <1903a57a-524e-4e6d-bd47-a87fadda4aa0@suse.com> Date: Wed, 1 Apr 2026 14:47:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= From: Jan Beulich Subject: [PATCH] VT-d: avoid multi-message-MSI check for HPET Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775047671-AF323CD1-9399B89B/0/0 X-purgate-type: clean X-purgate-size: 746 Having this immediately below a PCI-dev vs HPET conditional is (mildly) confusing. Move that if() into the body of the earlier one. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -513,13 +513,13 @@ static int msi_msg_to_remap_entry( if ( rc ) return rc; + + if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) + nr = msi_desc->msi.nvec; } else set_hpet_source_id(msi_desc->hpet_id, &new_ire); - if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) - nr = msi_desc->msi.nvec; - spin_lock_irqsave(&iommu->intremap.lock, flags); if ( msg == NULL ) From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:57:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:57:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270237.1558958 (Exim 4.92) (envelope-from ) id 1w7v88-0006Wp-Rz; Wed, 01 Apr 2026 12:57:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270237.1558958; Wed, 01 Apr 2026 12:57:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7v88-0006Wi-PI; Wed, 01 Apr 2026 12:57:08 +0000 Received: by outflank-mailman (input) for mailman id 1270237; Wed, 01 Apr 2026 12:57:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7v87-0006Wc-3V for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 12:57:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7v86-004Xoh-4t for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:57:06 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd1607-e002-0a2a0a5209dd-0a2a4507aef2-44 for ; Wed, 01 Apr 2026 14:57:06 +0200 Received: from [209.85.208.41] (helo=mail-ed1-f41.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd1621-ba2d-0a2a45070019-d155d029e406-3 for ; Wed, 01 Apr 2026 14:57:05 +0200 Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-66c4c7e2bb7so2508051a12.0 for ; Wed, 01 Apr 2026 05:57:05 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnNFiAFAwAAAAAACgkQsN6d1ii/Ey+H wQf/YIekTd0xOwsf2o9bcHYob1t5lnJAnZgZ6eDxRL8UQgK0MZbK9Mj69xGHfiqeL5BXI8xhwHBZ k7Q7B/LsoqQqaVvlQkmcqOk4KxTE4Z39swakgaO6x3FnkRqVFmhORuUYuoh2atqfMSttDn6ijpVZ eW/GgmkKdVgs44NNhIiXmDi0qNoEErLchY90RoZz6Skvn9eJ7z4Ql7+9X9uQMXMhrZFpewGvWlfM 7+DOEpUrkI48E6Uk5nlZU6ivHQyECzSwUZW6T4EYaWF2gtQlOxolIEa+0Z8UEAqfMBiJlaPmfLkD NDlQx/it+BH0uVxwDMyQLQETWRHmVgifHqI/lVyt1A== =hV1Y -----END PGP SIGNATURE----- --------------DQCt9CVS1Vvmkgx7LdJwDmwK-- From xen-devel-bounces@lists.xenproject.org Wed Apr 01 12:57:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 12:57:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270249.1558967 (Exim 4.92) (envelope-from ) id 1w7v8s-0007Gs-7f; Wed, 01 Apr 2026 12:57:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270249.1558967; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775048272-77B44497-941A95E2/0/0 X-purgate-type: clean X-purgate-size: 2598 On 10.03.2026 18:08, Oleksii Kurochko wrote: > arch_domain_create() and arch_sanitise_domain_config() are prerequisites for > domain_create(). > > arch_sanitise_domain_config() currently returns 0, as there is no specific > work required at this stage. > > arch_domain_create() performs basic initialization, such as setting up the P2M > and initializing the domain's virtual timer. Does it? I can spot only the former; instead there is ... > --- a/xen/arch/riscv/domain.c > +++ b/xen/arch/riscv/domain.c > @@ -288,6 +288,33 @@ void sync_vcpu_execstate(struct vcpu *v) > /* Nothing to do -- no lazy switching */ > } > > +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) > +{ > + return 0; > +} > + > +int arch_domain_create(struct domain *d, > + struct xen_domctl_createdomain *config, > + unsigned int flags) > +{ > + int rc = 0; > + > + if ( is_idle_domain(d) ) > + return 0; > + > + if ( (rc = p2m_init(d)) != 0) > + goto fail; > + > + d->arch.next_phandle = GUEST_PHANDLE_LAST + 1; ... this, which I can't make any sense of. I can't find matching Arm code either, which might otherwise have helped. > + return rc; > + > + fail: > + d->is_dying = DOMDYING_dead; > + arch_domain_destroy(d); (At least) for the use here, that other function would better also move out of stubs.c at the same time (and no longer have unconditional BUG_ON() in it). > --- a/xen/arch/riscv/stubs.c > +++ b/xen/arch/riscv/stubs.c > @@ -101,14 +101,7 @@ void dump_pageframe_info(struct domain *d) > BUG_ON("unimplemented"); > } > > -int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) > -{ > - BUG_ON("unimplemented"); > -} > - > -int arch_domain_create(struct domain *d, > - struct xen_domctl_createdomain *config, > - unsigned int flags) > +void vcpu_switch_to_aarch64_mode(struct vcpu *v) What is this? Surely nothing with this name should exist under riscv/. > --- a/xen/include/public/device_tree_defs.h > +++ b/xen/include/public/device_tree_defs.h > @@ -14,6 +14,7 @@ > */ > #define GUEST_PHANDLE_GIC (65000) > #define GUEST_PHANDLE_IOMMU (GUEST_PHANDLE_GIC + 1) > +#define GUEST_PHANDLE_LAST GUEST_PHANDLE_IOMMU This, to me, looks like a questionable addition to the public interface. Yet I'm not a DT person, so I may simply be missing why something like this might be wanted (and how stable it then would be, long term). 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charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1775048633-5515D152-7A2A2607/0/0 X-purgate-type: clean X-purgate-size: 2600 On 01.04.2026 14:57, Jürgen Groß wrote: > On 01.04.26 14:29, Jan Beulich wrote: >> Leaving aside highly disaggregated environments, the control domain is >> what will invoke XEN_SYSCTL_SCHEDOP_putinfo. Its vCPU-s therefore need to >> be able to run unconditionally, not those of the domain with ID 0 (which >> may not exist at all). >> >> Fixes: 9f0c658baedc ("arinc: add cpu-pool support to scheduler") >> Signed-off-by: Jan Beulich >> --- >> There being no "else" to the if(), what about other control domain vCPU-s? > > I guess this is a stale leftover. Doesn't matter for committing anyway. > >> --- >> v3: Don't mistakenly include the idle domain. >> v2: New. >> >> --- a/xen/common/sched/arinc653.c >> +++ b/xen/common/sched/arinc653.c >> @@ -411,10 +411,10 @@ a653sched_alloc_udata(const struct sched >> spin_lock_irqsave(&sched_priv->lock, flags); >> >> /* >> - * Add every one of dom0's units to the schedule, as long as there are >> - * slots available. >> + * Add every one of the control domain's units to the schedule, as long as >> + * there are slots available. >> */ >> - if ( unit->domain->domain_id == 0 ) >> + if ( is_control_domain(unit->domain) && !is_idle_domain(unit->domain) ) >> { >> entry = sched_priv->num_schedule_entries; >> > > Hmm, is it really the control domain only which wants to be scheduled initially? > I would think that at least the hardware domain and probably a Xenstore domain > would want to be included, too. > > In the end it might even be that other domains created via dom0less would want > to be able to run initially. They could be part of a mandatory infrastructure. > Why would they need to be created at boot if they are NOT important? This part is easy to answer: Because in a dom0less setup you simply may have no toolstack at all. (At which point there may also be nothing to set a schedule, yes.) > The question is whether the arinc653 scheduler is really meant for such setups. > OTOH just modifying the test to: > > if ( system_state < SYS_STATE_active && > unit->domain->domain_id < DOMID_FIRST_RESERVED ) > > seems to be fine for catching all those cases. > > With or without this modification: > > Reviewed-by: Juergen Gross Thanks, yet I'll have to leave to the maintainers to decide which form it should ultimately take. One remark: A restartable control domain wouldn't pass that conditional. Granted that's looking far into the future. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 13:19:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 13:19:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270274.1558985 (Exim 4.92) (envelope-from ) id 1w7vTv-0002sy-2a; Wed, 01 Apr 2026 13:19:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270274.1558985; Wed, 01 Apr 2026 13:19:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7vTv-0002sr-00; Wed, 01 Apr 2026 13:19:39 +0000 Received: by outflank-mailman (input) for mailman id 1270274; Wed, 01 Apr 2026 13:19:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7vTt-0002sl-Ep for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 13:19:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7vTs-006ySa-Bz for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:19:36 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd1b67-2eae-0a2a0a5409dd-0a2a4508e4f2-2 for ; Wed, 01 Apr 2026 15:19:36 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd1b68-fab6-0a2a45080019-d1558031d4df-3 for ; Wed, 01 Apr 2026 15:19:36 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so57933505e9.0 for ; Wed, 01 Apr 2026 06:19:36 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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AJvYcCXVeJJCOxAIt8amtb9Xj325sZcAmNoInWT0Ph0kzY6xlfNaRKwf8raaU0t6wLNsKT675cOpUHdqiH4=@lists.xenproject.org X-Gm-Message-State: AOJu0Yws5FpEGR84i14qsCuO1wiExVxKoDcJkr5/8HxOJgv6XHNY2EUD YYHuWMiMoxzzrKMxx+KX4/6os22/IHCJLoCLA6j5BqTc+xY8aCjIuCxpEJJzbVbFcA== X-Gm-Gg: ATEYQzxsfFCHAOhj9H1J3t7oT2Ht09kINIpdjAjR1rFNNt8U3JIs6hg6bFEFM0crMiK ieIBhZ3GPw3VnEl45sHhkftuyssPVoe9rn4oMvBUWnv1MQZIrMnEr/l74xIYy8gFgpmbNvMxXvN dry1jliWpWDxdVQ4sbRXEx50wAHH8+5JTpbrvDS4l8vZYopH4MyDqmailaTqvJRgB/XiLGfIXXy WERJOPGoYox845IUmKyrNuRpCYzVelgxxlMwLSiTYHBiWwuUA66q7BmlIgtncgjHfQfbIRbD9Mp n+RkiXo+Mo+SI7EbNbn/oKpDXQJyWgqAXj+Nl8BPg9sYo9N7Hb1yhtSPFByZsCR1Q5puyBbXQb9 Is9ynSmZTzHol/6Yx8jRjBoAFsZVWFYCD4YRj6diyorZzWci/BtCFQJFv7CkE0/WFeMqkS+7YCY PzfZFV0UTXRGz4lVPCobNlHuxcIFIAc9ioN6pDTr0DKd93DTdJcGzh8kJsh10JW+7V7XeGxEXex 1Fdb2Flqiw5O3A= X-Received: by 2002:a05:600c:c04a:b0:486:fbf6:abd4 with SMTP id 5b1f17b1804b1-488835636f1mr45223005e9.9.1775049575591; Wed, 01 Apr 2026 06:19:35 -0700 (PDT) Message-ID: Date: Wed, 1 Apr 2026 15:19:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 04/27] xen/riscv: rework G-stage mode handling To: Oleksii Kurochko Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <2c8f1ea25b8d3ec78b00510fbe604a87e759e194.1773157782.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2c8f1ea25b8d3ec78b00510fbe604a87e759e194.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775049576-7674E497-6799F8DF/0/0 X-purgate-type: clean X-purgate-size: 3413 On 10.03.2026 18:08, Oleksii Kurochko wrote: > Rework G-stage mode handling to make the selected mode descriptor reusable > outside of p2m initialization. > > As max_gstage_mode is going to be reused by code that creates CPU nodes for > guest domains, not only max_gstage_mode->mode but also max_gstage_mode->name > is required. I guess I'm not DT-savvy enough to understand why that would be. > To support this, make max_gstage_mode a global pointer to one of > the entries in a global modes[] array, and remove get_max_supported_mode(). > > Update struct p2m_domain to store a pointer to a mode descriptor instead of > embedding the structure directly. > > Refactor the modes[] array so that mode->name contains only the MMU scheme > name (without the "x4" suffix), as this value is reused when filling the > maximum MMU type passed to the guest. According to DT bindings [1], the MMU > type must not include the "x4" suffix. Use "none" for the Bare mode to match > the DT binding requirements. I expect this DT aspect is also why Sv changes to sv in the table? (Which is a little unhelpful for the printk() where it's used.) > Adjust modes[]->paging_levels to represent the maximum paging level rather > than the total number of levels. This ensures that P2M_ROOT_LEVEL() and its > users behave correctly without relying on hardcoded p2m mode values. > > Finally, drop __initconst from the modes[] declaration, as the array is > referenced via p2m->mode and max_gstage_mode beyond the init stage. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v6.19-rc3#n82 Is a reference into Linux doc really providing something "canonical"? Surely there's an independent spec somewhere? > --- a/xen/arch/riscv/p2m.c > +++ b/xen/arch/riscv/p2m.c > @@ -45,18 +45,32 @@ struct p2m_pte_ctx { > unsigned int level; /* Paging level at which the PTE resides. */ > }; > > -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { > - .mode = HGATP_MODE_OFF, > - .paging_levels = 0, > - .name = "Bare", > -}; > - > /* > * Set to the maximum configured support for IPA bits, so the number of IPA bits can be > * restricted by external entity (e.g. IOMMU). > */ > unsigned int __read_mostly p2m_ipa_bits = PADDR_BITS; > > +static const struct gstage_mode_desc modes[] = { As a function scope static this was a fine identifier. Please consider whether with the wider scope gstage_modes[] might not be better. > + /* > + * Based on the RISC-V spec: > + * Bare mode is always supported, regardless of SXLEN. > + * When SXLEN=32, the only other valid setting for MODE is Sv32. > + * When SXLEN=64, three paged virtual-memory schemes are defined: > + * Sv39, Sv48, and Sv57. > + */ > + [0] = { HGATP_MODE_OFF, 0, "none" }, > +#ifdef CONFIG_RISCV_32 > + [1] = { HGATP_MODE_SV32X4, 1, "sv32" } > +#else > + [2] = { HGATP_MODE_SV39X4, 2, "sv39" }, > + [3] = { HGATP_MODE_SV48X4, 3, "sv48" }, > + [4] = { HGATP_MODE_SV57X4, 4, "sv57" }, > +#endif > +}; The dedicated initializer form isn't adding any value here (whereas it slightly hampers readability). You really don't want the array to be sparsely populated, so perhaps better to leave as it was before? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 13:39:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 13:39:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270290.1558994 (Exim 4.92) (envelope-from ) id 1w7vmr-0006Bf-Ox; Wed, 01 Apr 2026 13:39:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270290.1558994; Wed, 01 Apr 2026 13:39:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7vmr-0006BY-LQ; Wed, 01 Apr 2026 13:39:13 +0000 Received: by outflank-mailman (input) for mailman id 1270290; Wed, 01 Apr 2026 13:39:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7vmq-0006BS-5R for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 13:39:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7vmp-00BePh-Hg for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:39:11 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd1fe8-5cb7-0a2a0a5109dd-0a2a4501e6aa-46 for ; Wed, 01 Apr 2026 15:39:11 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd1fff-6fc9-0a2a45010019-d155802ea9c1-3 for ; Wed, 01 Apr 2026 15:39:11 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-486fe36cfabso6127305e9.1 for ; Wed, 01 Apr 2026 06:39:11 -0700 (PDT) Received: from ?IPV6:2a01:cb15:80df:da00:6d45:ff60:3ad6:d7fa? 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No, there is no any dependency, it could go earlier then other patches of this patch series. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 01 13:49:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 13:49:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270305.1559002 (Exim 4.92) (envelope-from ) id 1w7vwk-00083N-M1; Wed, 01 Apr 2026 13:49:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270305.1559002; Wed, 01 Apr 2026 13:49:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7vwk-00083G-Is; Wed, 01 Apr 2026 13:49:26 +0000 Received: by outflank-mailman (input) for mailman id 1270305; Wed, 01 Apr 2026 13:49:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7vwj-00082P-5T for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 13:49:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7vwi-0074BD-HW for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:49:24 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2253-5cb7-0a2a0a5109dd-0a2a4508bf48-28 for ; Wed, 01 Apr 2026 15:49:24 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2264-fab6-0a2a45080019-d155802ce0af-3 for ; Wed, 01 Apr 2026 15:49:24 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-486b96760easo76685635e9.2 for ; Wed, 01 Apr 2026 06:49:24 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <007c0a0243ac7ff1d1ab3faa4ebcdd6fcd14e485.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775051364-75557497-9D6FEE11/0/0 X-purgate-type: clean X-purgate-size: 4483 On 10.03.2026 18:08, Oleksii Kurochko wrote: > Introduce generation of the riscv,isa string passed to the guest via the > Device Tree riscv,isa property. Title as well as this suggest this is all about guest properties. Then ... > The following changes are introduced: > > - According to the RISC-V privileged specification, M-mode software controls > the XLEN value used by S-mode and U-mode. For RV64 harts, the SXL and UXL > fields of the mstatus register are WARL fields that define the XLEN for > S-mode and U-mode. > > The XLEN value is provided by M-mode software (OpenSBI in the case of Xen) > via the riscv,isa DT property. Introduce and initialize an xlen variable > when parsing the host riscv,isa string in riscv_isa_parse_string(). ... suddenly talk is of host aspects? (See below as to what "xlen" really is meant to hold.) > --- a/xen/arch/riscv/cpufeature.c > +++ b/xen/arch/riscv/cpufeature.c > @@ -38,6 +38,8 @@ struct riscv_isa_ext_data { > /* Host ISA bitmap */ > static __ro_after_init DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX); > > +static __ro_after_init unsigned int xlen; Nit: Attribute between type and identifier please, whenever possible (it isn't neatly possible in riscv_isa above, due to DECLARE_BITMAP()). > @@ -160,6 +162,19 @@ static const struct riscv_isa_ext_data __initconst required_extensions[] = { > RISCV_ISA_EXT_DATA(svpbmt), > }; > > +static const unsigned int __initconst guest_unsupp_exts[] = { > + RISCV_ISA_EXT_f, > + RISCV_ISA_EXT_d, > + RISCV_ISA_EXT_h, > + RISCV_ISA_EXT_q, > + RISCV_ISA_EXT_v, > +}; This could do with a comment clarifying what needs (and what doesn't need) putting here. My expectation would have been that everything in riscv_isa_ext[] which shouldn't be exposed to guests should appear here. Yet then there is V (which riscv_isa_ext[] doesn't have), while e.g. Svade and Svpbmt (which iirc won't be available to guests right away) aren't there. > +static __ro_after_init DECLARE_BITMAP(guest_unsupp_bmp, RISCV_ISA_EXT_MAX); Is the _bmp suffix really needed? riscv_isa, for example, doesn't have it. > +#define MAX_GUEST_ISA_STR_LEN 256 > +char guest_isa_str[MAX_GUEST_ISA_STR_LEN]; __ro_after_init? Yet then - can this really be a global? Isn't the set of extensions available to a guest a per-guest property, i.e. a global could at best represent an upper bound on features? > @@ -193,6 +208,15 @@ static void __init match_isa_ext(const char *name, const char *name_end, > !memcmp(name, ext->name, name_end - name) ) > { > __set_bit(ext->id, bitmap); > + > + if ( riscv_isa_extension_available(guest_unsupp_bmp, ext->id) ) > + break; > + > + if ( ext->id >= RISCV_ISA_EXT_BASE ) > + safe_strcat(guest_isa_str, "_"); > + > + safe_strcat(guest_isa_str, ext->name); Shouldn't you check the (kind-of-)return value? (Yet better would be a build- time check, but I can't think of a way to achieve that.) > @@ -207,13 +231,17 @@ static int __init riscv_isa_parse_string(const char *isa, > #if defined(CONFIG_RISCV_32) > if ( isa[2] != '3' && isa[3] != '2' ) > return -EINVAL; > + xlen = 32; > #elif defined(CONFIG_RISCV_64) > if ( isa[2] != '6' && isa[3] != '4' ) > return -EINVAL; > + xlen = 64; > #else > # error "unsupported RISC-V bitness" > #endif This can be had with an initializer of "xlen". Then the (kind-of-)variable could be const unsigned int. Seeing the use below, is the variable correctly named, though? I.e. shouldn't it be guest_xlen or some such? Independently I expect you will want to support 32-bit guests on 64-bit Xen at some point, in which case encoding this value into a global string won't work very well. > + snprintf(guest_isa_str, sizeof(guest_isa_str), "rv%d", xlen); %u please with unsigned int. This being the only use of the variable (afaics), why is it not function- scope? > @@ -487,6 +515,11 @@ void __init riscv_fill_hwcap(void) > bool all_extns_available = true; > struct trap_info trap; > > + for ( i = 0; i < ARRAY_SIZE(guest_unsupp_exts); i++ ) > + { > + __set_bit(guest_unsupp_exts[i], guest_unsupp_bmp); > + } Nit: No need for braces here. And anyway - can't this be had with an initializer for guest_unsupp_bmp? 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The default mode therefore isn't the only mode that may be used > at runtime. I remember that, but i don't really understand what is wrong now with the ASSERT(). It should be changed or dropped at all when this property you are talking about will be introduced. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 01 13:57:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 13:57:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270328.1559020 (Exim 4.92) (envelope-from ) id 1w7w4d-0001pm-MC; Wed, 01 Apr 2026 13:57:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270328.1559020; Wed, 01 Apr 2026 13:57:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7w4d-0001pf-JG; Wed, 01 Apr 2026 13:57:35 +0000 Received: by outflank-mailman (input) for mailman id 1270328; Wed, 01 Apr 2026 13:57:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7w4b-0001pZ-Vw for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 13:57:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7w4b-00BiaU-27 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:57:33 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2438-2eae-0a2a0a5409dd-0a2a4502d9dc-46 for ; Wed, 01 Apr 2026 15:57:32 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd244c-42fa-0a2a45020019-d1558033c02d-3 for ; Wed, 01 Apr 2026 15:57:32 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-486ff3a0fc1so63746065e9.2 for ; Wed, 01 Apr 2026 06:57:32 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775051852-AE926CD1-2F2D9564/0/0 X-purgate-type: clean X-purgate-size: 1637 On 01.04.2026 15:50, Oleksii Kurochko wrote: > On 4/1/26 8:07 AM, Jan Beulich wrote: >>>>> @@ -191,8 +209,13 @@ static void __init gstage_mode_detect(void) >>>>> >>>>> void __init guest_mm_init(void) >>>>> { >>>>> + unsigned int gpa_bits; >>>>> + unsigned int paging_levels = default_gstage_mode.paging_levels; >>>> Deriving a global from a default, when ... This earlier comment may have been placed a little unhelpfully. The global talked about is p2m_gpa_bits. IOW ... >>>>> gstage_mode_detect(); >>>>> >>>>> + ASSERT(default_gstage_mode.paging_levels <= max_gstage_mode.paging_levels); >>>> ... the default isn't the maximum possible, isn't going to fly. >>> I didn't get you here. >>> >>> If we want Xen uses Sv39 for G-stage, we want to limit guest's 56-bit >>> GPA to 39-bit GPA, but not the maximum supported by h/w mode for G-stage >>> mode. >> I can only repeat what I thought I had got across already on an earlier >> series of yours: What mode a guest is going to use is going to be a guest >> property. The default mode therefore isn't the only mode that may be used >> at runtime. > > I remember that, but i don't really understand what is wrong now with > the ASSERT(). It should be changed or dropped at all when this property > you are talking about will be introduced. ... the comment wasn't about the assertion itself, but the mere existence of default_gstage_mode. Imo you really don't want to redo this later, but maintain per-guest settings per guest right away, even if for the time being all guests may end up with identical settings. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 13:57:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 13:57:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270334.1559029 (Exim 4.92) (envelope-from ) id 1w7w4z-0002Ke-0s; Wed, 01 Apr 2026 13:57:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270334.1559029; Wed, 01 Apr 2026 13:57:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7w4y-0002KX-UY; Wed, 01 Apr 2026 13:57:56 +0000 Received: by outflank-mailman (input) for mailman id 1270334; Wed, 01 Apr 2026 13:57:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7w4x-0002K0-BW for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 13:57:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7w4w-0075oB-NN for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:57:54 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2457-5cb7-0a2a0a5109dd-0a2a4509a278-40 for ; Wed, 01 Apr 2026 15:57:54 +0200 Received: from [209.85.221.47] (helo=mail-wr1-f47.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2462-bf79-0a2a45090019-d155dd2fbcf9-3 for ; Wed, 01 Apr 2026 15:57:54 +0200 Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-43d17bb1c65so428429f8f.0 for ; Wed, 01 Apr 2026 06:57:54 -0700 (PDT) Received: from ?IPV6:2a01:cb15:80df:da00:6d45:ff60:3ad6:d7fa? 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For example, what if more than 2Gb of MMIO space are needed >>> for non-64-bit BARs? >> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >> before RAM start is enough for MMIO space. > Likely in the common case. Board designers aren't constrained by this, > though (aiui). Whereas you set in stone a single, fixed layout. > > Arm maintainers - since a similar fixed layout is used there iirc, > could you chime in here, please? > >> Answering your question it will be an issue or it will also use some >> space before banks, no? > I fear I don't understand what you're trying to tell me. I meant that there is also some space between banks and pretty big which could be used for MMIO which could be used for non-64-bit BARs. > >> Further, assuming that the space 4G...8G is what >>> you expect 64-bit BARs to be put into, what if there's a device with a >>> 4G BAR? It'll eat up that entire space, requiring everything else to >>> fit in the 2G you reserve below 4G. >> I assume that such big devices could use high memory without any issue. > Well, I could go (almost) arbitrarily low with individual BAR size, > merely increasing the number of BARs accordingly. Assuming 2G BARs are > 64-bit capable is likely fine. Maybe the same is true for 1G and 512M > ones as well. Yet a some size the assumption will break. > > IMO RAM layout wants establishing dynamically based on the MMIO needs > of a guest. I have this in my TODO. But with the current implementation of dom0less it requires to have RAM banks defined in compile time. Can we process with the current suggested way with the following update of dom0less code to work with dynamically allocated RAM layout? ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:04:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:04:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270351.1559040 (Exim 4.92) (envelope-from ) id 1w7wB5-0004Ao-NR; Wed, 01 Apr 2026 14:04:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270351.1559040; Wed, 01 Apr 2026 14:04:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wB5-0004Ah-Iq; Wed, 01 Apr 2026 14:04:15 +0000 Received: by outflank-mailman (input) for mailman id 1270351; Wed, 01 Apr 2026 14:04:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wB3-0004Ab-J8 for xen-devel@lists.xenproject.org; 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Wed, 01 Apr 2026 07:04:05 -0700 (PDT) X-Received: by 2002:a05:6122:6087:b0:56c:dacc:9c3a with SMTP id 71dfb90a1353d-56d8a975f93mr1564518e0c.16.1775052245226; Wed, 01 Apr 2026 07:04:05 -0700 (PDT) MIME-Version: 1.0 References: <5bcbeb1d614be413c13196a38d13eb3de5c549e4.1774918270.git.milan_djokic@epam.com> In-Reply-To: <5bcbeb1d614be413c13196a38d13eb3de5c549e4.1774918270.git.milan_djokic@epam.com> From: Nick Rosbrook Date: Wed, 1 Apr 2026 10:03:54 -0400 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDsIAkTT-BXTxpHUg7wEs4HsANEVI2yOsm8f9UXch0MQDO40ngiQI9DM5g Message-ID: Subject: Re: [PATCH v3 06/23] xen/domctl: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu config param To: Milan Djokic Cc: "xen-devel@lists.xenproject.org" , Rahul Singh , Anthony PERARD , George Dunlap , Juergen Gross Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1775052252-64A4C3D8-CE7ECAD2/0/0 X-purgate-type: clean X-purgate-size: 3457 On Mon, Mar 30, 2026 at 9:52=E2=80=AFPM Milan Djokic wrote: > > From: Rahul Singh > > Add new viommu_type field and field values XEN_DOMCTL_CONFIG_VIOMMU_NONE > XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 in xen_arch_domainconfig to > enable/disable vIOMMU support for domains. > > Also add viommu=3D"N" parameter to xl domain configuration to enable the > vIOMMU for the domains. Currently, only the "smmuv3" type is supported > for ARM. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > docs/man/xl.cfg.5.pod.in | 13 +++++++++++++ > tools/golang/xenlight/helpers.gen.go | 2 ++ > tools/golang/xenlight/types.gen.go | 7 +++++++ > tools/include/libxl.h | 5 +++++ > tools/libs/light/libxl_arm.c | 13 +++++++++++++ > tools/libs/light/libxl_types.idl | 6 ++++++ > tools/xl/xl_parse.c | 9 +++++++++ > 7 files changed, 55 insertions(+) > > diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in > index 3aac0bc4fb..4de8db42ac 100644 > --- a/docs/man/xl.cfg.5.pod.in > +++ b/docs/man/xl.cfg.5.pod.in > @@ -3175,6 +3175,19 @@ option. > > =3Dback > > +=3Dover 4 > + > +=3Ditem B > + > +To enable viommu, user must specify the following option in the VM > +config file: > + > +viommu =3D "smmuv3" > + > +Currently, only the "smmuv3" type is supported for ARM. > + > +=3Dback > + > =3Dhead3 x86 > > =3Dover 4 > diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight= /helpers.gen.go > index b0c09da910..b24cfd0533 100644 > --- a/tools/golang/xenlight/helpers.gen.go > +++ b/tools/golang/xenlight/helpers.gen.go > @@ -1273,6 +1273,7 @@ x.ArchArm.NrSpis =3D uint32(xc.arch_arm.nr_spis) > if err :=3D x.ArchArm.ArmSci.fromC(&xc.arch_arm.arm_sci);err !=3D nil { > return fmt.Errorf("converting field ArchArm.ArmSci: %v", err) > } > +x.ArchArm.ViommuType =3D ViommuType(xc.arch_arm.viommu_type) > if err :=3D x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err != =3D nil { > return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err) > } > @@ -1815,6 +1816,7 @@ xc.arch_arm.nr_spis =3D C.uint32_t(x.ArchArm.NrSpis= ) > if err :=3D x.ArchArm.ArmSci.toC(&xc.arch_arm.arm_sci); err !=3D nil { > return fmt.Errorf("converting field ArchArm.ArmSci: %v", err) > } > +xc.arch_arm.viommu_type =3D C.libxl_viommu_type(x.ArchArm.ViommuType) > if err :=3D x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err !=3D= nil { > return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err) > } > diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/t= ypes.gen.go > index e0fd78ec03..e306f9c1ac 100644 > --- a/tools/golang/xenlight/types.gen.go > +++ b/tools/golang/xenlight/types.gen.go > @@ -530,6 +530,12 @@ type ArmSci struct { > Type ArmSciType > } > > +type ViommuType int > +const( > +ViommuTypeNone ViommuType =3D 0 > +ViommuTypeSmmuv3 ViommuType =3D 1 > +) > + > type RdmReserve struct { > Strategy RdmReserveStrategy > Policy RdmReservePolicy > @@ -619,6 +625,7 @@ Vuart VuartType > SveVl SveType > NrSpis uint32 > ArmSci ArmSci > +ViommuType ViommuType > } > ArchX86 struct { > MsrRelaxed Defbool This looks right now. For the golang bits: Acked-by: Nick Rosbrook -Nick From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:07:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:07:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270363.1559048 (Exim 4.92) (envelope-from ) id 1w7wE6-0004iB-3C; Wed, 01 Apr 2026 14:07:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270363.1559048; Wed, 01 Apr 2026 14:07:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wE6-0004i4-0O; Wed, 01 Apr 2026 14:07:22 +0000 Received: by outflank-mailman (input) for mailman id 1270363; Wed, 01 Apr 2026 14:07:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wE4-0004hy-IA for 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AJvYcCXSdujHDL/nI84eBnQYDpviHqP8dlz/NLp8jhVRM5+M9SZcy65OqbLPVFi4cAzMjlprhe8n2qRVR9M=@lists.xenproject.org X-Gm-Message-State: AOJu0YziMJ1xO8wVbL8tzg+2Rwulfvrl2/bmENwUqZawD83YDPuKmZ3a n6htvKxmb1XzEIi4u5rL/d7JHKT3yvIOkjxnaJcYb6N4GO3b6A1M2PfyCkD9klMMDw== X-Gm-Gg: ATEYQzzm/G4cOVLmKcS58XYKyCXpRQXsxkVhjgsyRRyFd227ZY2pptEkaX5ztN+gSA8 4oQDchEZGv0V3k2Fun/a30SkjeQrbNjC7LE7uJ8PTowcMTg4rnRF4Jh1tldkfo5svZXSzKVxABV Pse7K6zUxRSJ68XGYEQoKNRyBZxaaWY/ZhRhPUA6OT/d+f2cQZrAHPIpOGHBIYyzxD2VqS8OPun Or/7zkwjGrDiHjLj8ETHHBcjrUFT38D2uWAlALEGtFdh16qqxYefrGyMata3nC5Gl4kzqsOidpn /Njox7GDjHiFZ/514AZOifFEh+iwieDRN/CdpLsj3ljc05s+srqZjQ9yBs4laEW/n/ZgjmB6EHM IOSbXgPDkgwMSUzQwMtlT6mOwGNVmlR+J6+Oi2RpGdHflFUDye1oMGVbOxkL5hJfJrqEIx327Y7 vq8TQNand3AVqpEs7JYzd7MdwmTLo+8O/wfmoIUhEcZtEV9L0hAimZiUSTyomDcT1aBk7gjP1Rp Oeji9bJEj1JbHE= X-Received: by 2002:a05:6000:26cb:b0:439:c040:cc8a with SMTP id ffacd0b85a97d-43d150b81c3mr6948512f8f.32.1775052709759; Wed, 01 Apr 2026 07:11:49 -0700 (PDT) Message-ID: <7505a281-b481-4f3a-a7df-d8c234f28279@suse.com> Date: Wed, 1 Apr 2026 16:11:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 06/27] xen/riscv: implement make_cpus_node() To: Oleksii Kurochko Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775052711-0F1480B1-44076064/0/0 X-purgate-type: clean X-purgate-size: 4503 On 10.03.2026 18:08, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/Makefile > +++ b/xen/arch/riscv/Makefile > @@ -1,6 +1,7 @@ > obj-y += aplic.o > obj-y += cpufeature.o > obj-y += domain.o > +obj-y += domain-build.o > obj-$(CONFIG_EARLY_PRINTK) += early_printk.o > obj-y += entry.o > obj-y += guestcopy.o Doesn't this belong in patch 02? And then domain-build.init.o? > --- a/xen/arch/riscv/domain-build.c > +++ b/xen/arch/riscv/domain-build.c > @@ -3,8 +3,10 @@ > #include > #include > #include > +#include > #include > > +#include > #include > #include > > @@ -44,3 +46,109 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) > > return 0; > } > + > +int __init make_cpus_node(const struct domain *d, void *fdt) > +{ > + int res; > + const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); > + unsigned int cpu; > + u32 timebase_frequency; uint32_t please. > + bool frequency_valid; > + uint32_t *next_phandle = &((struct domain *)d)->arch.next_phandle; No casting away of const, please. > + dt_dprintk("Create cpus node\n"); > + > + if ( !cpus ) > + { > + dprintk(XENLOG_ERR, "Missing /cpus node in the device tree?\n"); > + return -ENOENT; > + } > + > + frequency_valid = dt_property_read_u32(cpus, "timebase-frequency", > + &timebase_frequency); > + > + res = fdt_begin_node(fdt, "cpus"); > + if ( res ) > + return res; > + > + res = fdt_property_cell(fdt, "#address-cells", 1); > + if ( res ) > + return res; > + > + res = fdt_property_cell(fdt, "#size-cells", 0); > + if ( res ) > + return res; > + > + if ( frequency_valid ) > + res = fdt_property_cell(fdt, "timebase-frequency", timebase_frequency); Handing through a property directly makes me wonder how that's going to fit with migration. I understand migration may not even be a mid-term goal, but still. > + for ( cpu = 0; cpu < d->max_vcpus; cpu++ ) > + { > + char buf[64]; > + uint32_t reg = cpu_to_fdt32(cpu); > + > + snprintf(buf, sizeof(buf), "cpu@%u", cpu); > + res = fdt_begin_node(fdt, buf); > + if ( res ) > + return res; > + > + res = fdt_property(fdt, "reg", ®, sizeof(reg)); > + if ( res ) > + return res; > + > + res = fdt_property_string(fdt, "status", "okay"); > + if ( res ) > + return res; > + > + res = fdt_property_string(fdt, "compatible", "riscv"); > + if ( res ) > + return res; > + > + BUILD_BUG_ON((sizeof("riscv,") + sizeof_field(struct gstage_mode_desc, name) + 1) >= sizeof(buf)); Nit: Overlong line. Also, why +1? The name field has to include a nul, or else ... > + snprintf(buf, sizeof(buf), "riscv,%s", max_gstage_mode->name); ... you can't use plain %s here. > + res = fdt_property_string(fdt, "mmu-type", buf); > + if ( res ) > + return res; > + > + res = fdt_property_string(fdt, "riscv,isa", guest_isa_str); > + if ( res ) > + return res; > + > + res = fdt_property_string(fdt, "device_type", "cpu"); > + if ( res ) > + return res; > + > + res = fdt_begin_node(fdt, "interrupt-controller"); > + if ( res ) > + return res; > + > + res = fdt_property_string(fdt, "compatible", "riscv,cpu-intc"); > + if ( res ) > + return res; > + > + res = fdt_property_cell(fdt, "#interrupt-cells", 1); > + if ( res ) > + return res; > + > + res = fdt_property(fdt, "interrupt-controller", NULL, 0); > + if ( res ) > + return res; > + > + res = fdt_property_u32(fdt, "phandle", (*next_phandle)++); > + if ( res ) > + return res; > + > + /* end of interrupt-controller */ > + res = fdt_end_node(fdt); > + if ( res ) > + return res; > + > + res = fdt_end_node(fdt); > + if ( res ) > + return res; > + } > + > + res = fdt_end_node(fdt); > + > + return res; Simply "return fdt_end_node(fdt);"? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <13714c88-838b-4dc7-bc0b-b6ca590fd944@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775052885-A4DBDA3D-365E61DC/0/0 X-purgate-type: clean X-purgate-size: 8059 On 01.04.2026 16:07, Mykyta Poturai wrote: > On 4/1/26 11:21, Jan Beulich wrote: >> On 01.04.2026 09:59, Mykyta Poturai wrote: >>> On 3/31/26 17:55, Jan Beulich wrote: >>>> On 09.03.2026 12:08, Mykyta Poturai wrote: >>>>> --- a/xen/drivers/vpci/header.c >>>>> +++ b/xen/drivers/vpci/header.c >>>>> @@ -175,76 +175,92 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, >>>>> >>>>> bool vpci_process_pending(struct vcpu *v) >>>>> { >>>>> - const struct pci_dev *pdev = v->vpci.pdev; >>>>> - struct vpci_header *header = NULL; >>>>> - unsigned int i; >>>>> - >>>>> - if ( !pdev ) >>>>> - return false; >>>>> - >>>>> - read_lock(&v->domain->pci_lock); >>>>> - >>>>> - if ( !pdev->vpci || (v->domain != pdev->domain) ) >>>>> + switch ( v->vpci.task ) >>>>> { >>>>> - v->vpci.pdev = NULL; >>>>> - read_unlock(&v->domain->pci_lock); >>>>> - return false; >>>>> - } >>>>> - >>>>> - header = &pdev->vpci->header; >>>>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>> + case MODIFY_MEMORY: >>>>> { >>>>> - struct vpci_bar *bar = &header->bars[i]; >>>>> - struct rangeset *mem = v->vpci.bar_mem[i]; >>>>> - struct map_data data = { >>>>> - .d = v->domain, >>>>> - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, >>>>> - .bar = bar, >>>>> - }; >>>>> - int rc; >>>>> + const struct pci_dev *pdev = v->vpci.memory.pdev; >>>>> + struct vpci_header *header = NULL; >>>>> + unsigned int i; >>>>> >>>>> - if ( rangeset_is_empty(mem) ) >>>>> - continue; >>>>> + if ( !pdev ) >>>>> + break; >>>>> >>>>> - rc = rangeset_consume_ranges(mem, map_range, &data); >>>>> + read_lock(&v->domain->pci_lock); >>>>> >>>>> - if ( rc == -ERESTART ) >>>>> + if ( !pdev->vpci || (v->domain != pdev->domain) ) >>>>> { >>>>> + v->vpci.memory.pdev = NULL; >>>>> read_unlock(&v->domain->pci_lock); >>>>> - return true; >>>>> + break; >>>>> } >>>>> >>>>> - if ( rc ) >>>>> + header = &pdev->vpci->header; >>>>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>> { >>>>> - spin_lock(&pdev->vpci->lock); >>>>> - /* Disable memory decoding unconditionally on failure. */ >>>>> - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, >>>>> - false); >>>>> - spin_unlock(&pdev->vpci->lock); >>>>> + struct vpci_bar *bar = &header->bars[i]; >>>>> + struct rangeset *mem = v->vpci.bar_mem[i]; >>>>> + struct map_data data = { >>>>> + .d = v->domain, >>>>> + .map = v->vpci.memory.cmd & PCI_COMMAND_MEMORY, >>>>> + .bar = bar, >>>>> + }; >>>>> + int rc; >>>>> + >>>>> + if ( rangeset_is_empty(mem) ) >>>>> + continue; >>>>> >>>>> - /* Clean all the rangesets */ >>>>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>> - if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>>>> - rangeset_purge(v->vpci.bar_mem[i]); >>>>> + rc = rangeset_consume_ranges(mem, map_range, &data); >>>>> >>>>> - v->vpci.pdev = NULL; >>>>> + if ( rc == -ERESTART ) >>>>> + { >>>>> + read_unlock(&v->domain->pci_lock); >>>>> + return true; >>>>> + } >>>>> >>>>> - read_unlock(&v->domain->pci_lock); >>>>> + if ( rc ) >>>>> + { >>>>> + spin_lock(&pdev->vpci->lock); >>>>> + /* Disable memory decoding unconditionally on failure. */ >>>>> + modify_decoding(pdev, v->vpci.memory.cmd & ~PCI_COMMAND_MEMORY, >>>>> + false); >>>>> + spin_unlock(&pdev->vpci->lock); >>>>> + >>>>> + /* Clean all the rangesets */ >>>>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>> + if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>>>> + rangeset_purge(v->vpci.bar_mem[i]); >>>>> + >>>>> + v->vpci.memory.pdev = NULL; >>>>> + >>>>> + read_unlock(&v->domain->pci_lock); >>>>> >>>>> - if ( !is_hardware_domain(v->domain) ) >>>>> - domain_crash(v->domain); >>>>> + if ( !is_hardware_domain(v->domain) ) >>>>> + domain_crash(v->domain); >>>>> >>>>> - return false; >>>>> + break; >>>>> + } >>>>> } >>>>> - } >>>>> - v->vpci.pdev = NULL; >>>>> + v->vpci.memory.pdev = NULL; >>>>> >>>>> - spin_lock(&pdev->vpci->lock); >>>>> - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); >>>>> - spin_unlock(&pdev->vpci->lock); >>>>> + spin_lock(&pdev->vpci->lock); >>>>> + modify_decoding(pdev, v->vpci.memory.cmd, v->vpci.memory.rom_only); >>>>> + spin_unlock(&pdev->vpci->lock); >>>>> >>>>> - read_unlock(&v->domain->pci_lock); >>>>> + read_unlock(&v->domain->pci_lock); >>>>> + >>>>> + break; >>>>> + } >>>>> + case WAIT: >>>>> + if ( NOW() < v->vpci.wait.end ) >>>>> + return true; >>>>> + v->vpci.wait.callback(v->vpci.wait.data); >>>>> + break; >>>> >>>> As just indicated in reply to patch 6, busy waiting isn't really acceptable. >>>> This is even more so when the waiting exceeds the typical length of a >>>> scheduling timeslice. >>>> >>>> In that other reply I said to put the vCPU to sleep, but you need to be careful >>>> there too: The domain may not expect its vCPU to not make any progress for such >>>> an extended period of time. This may need doing entirely differently: Once the >>>> command register was written, you may want to record the time after which >>>> accesses to the VF registers are permitted. Earlier accesses would simply be >>>> terminated. You may still additionally need a timer, in order to kick off BAR >>>> mapping after that time. (Yet better would be if the BAR mapping could be >>>> done during those 100ms. After all that may be a reason why this long a delay >>>> is specified: Firmware on the device may also require some time to set up the >>>> BARs accordingly.) >>> >>> I am not sure it would work that way. If we look at how linux >>> initialized sriov, it writes VFE and MSE bits, waits 100ms and then >>> expects VFs to be operational. If they are not operational at that >>> moment, then it considers the operation failed and removes all VFs. If >>> we also wait 100ms before enabling access, the probability of a guest >>> trying to access something before we allow it would be very high. >> >> Well, not really. Our counting of the 100ms necessarily starts before Dom0's. >> Furthermore it may be acceptable (or even appropriate) to stall premature >> accesses (because they shouldn't occur in the first place), by blocking the >> vCPU at that point. A middle route may be possible: Terminate accesses in, >> say, the first 90ms, and stall the vCPU for any access past that, but before >> the 100ms expired. > > Is there any real benefit to doing all this work instead of just waiting > for Dom0 to register the FVs? Implementing it the way you described > would require a relatively complex state machine and two timers per > sriov-capable device. And will also probably require some hacks to > handle partially initialized VFs in Xen. This adds a lot of work and > many possible bugs for not a lot of benefit in my opinion. Odd that you ask me this question. If there was no benefit, why did you do it this way? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2bae9e12-8f71-4ff0-b077-bfb4215e5e14@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775053342-83D43A3D-04901D80/0/0 X-purgate-type: clean X-purgate-size: 3244 On 01.04.2026 15:57, Oleksii Kurochko wrote: > On 4/1/26 8:17 AM, Jan Beulich wrote: >> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>> so introduce macros to describe guest RAM banks. >>>>> >>>>> The reason for 2 banks is that there is typically always a use case for >>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>> there are other things under 4 GB it can conflict with (interrupt >>>>> controller, PCI BARs, etc.). >>>> Fixed layouts like the one you suggest come with (potentially severe) >>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>> for non-64-bit BARs? >>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>> before RAM start is enough for MMIO space. >> Likely in the common case. Board designers aren't constrained by this, >> though (aiui). Whereas you set in stone a single, fixed layout. >> >> Arm maintainers - since a similar fixed layout is used there iirc, >> could you chime in here, please? >> >>> Answering your question it will be an issue or it will also use some >>> space before banks, no? >> I fear I don't understand what you're trying to tell me. > > I meant that there is also some space between banks and pretty big which > could be used for MMIO which could be used for non-64-bit BARs. I don't follow: Bank 0 extends to 4G. There's no space above it, below bank 1, which could be use for non-64-bit BARs. >>> Further, assuming that the space 4G...8G is what >>>> you expect 64-bit BARs to be put into, what if there's a device with a >>>> 4G BAR? It'll eat up that entire space, requiring everything else to >>>> fit in the 2G you reserve below 4G. >>> I assume that such big devices could use high memory without any issue. >> Well, I could go (almost) arbitrarily low with individual BAR size, >> merely increasing the number of BARs accordingly. Assuming 2G BARs are >> 64-bit capable is likely fine. Maybe the same is true for 1G and 512M >> ones as well. Yet a some size the assumption will break. >> >> IMO RAM layout wants establishing dynamically based on the MMIO needs >> of a guest. > > I have this in my TODO. > > But with the current implementation of dom0less it requires to have RAM > banks defined in compile time. Oh well. > Can we process with the current suggested way with the following update > of dom0less code to work with dynamically allocated RAM layout? If you want me to ack such, the limitations will need clearly calling out as such (and why it needs doing like this). Further the public interface wants leaving as tidy as possible, as removing stuff from there is usually not a straightforward thing to do. Ideally, no part of this would be encoded into the public headers, if at all possible. You also may recall that I have reservations towards this work targeting dom0less alone. Yet that's likely okay(ish) as long as this is the mutual understanding of interested parties (and again clearly expressed in relevant places). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775053484-EC75A2A1-6C84F1FE/10/73395122804 X-purgate-type: spam X-purgate-size: 460 On 10.03.2026 18:08, Oleksii Kurochko wrote: > The make_timer_node() function is implemented to return 0, > as RISC-V does not require the creation of a timer node. > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich Yet: Why is this needed then in the first place? If this node may not be required, why would the function need providing? Shouldn't the call site be conditional then? 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cf858959-ed6d-4e58-84d9-08de8ffae43a X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Apr 2026 14:28:06.6600 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cxuC2hW5izi2J5UY8NvTU2x9A3AzRiWMYOY1ia4qBqhVxfl07oMSI/M0oCrTD+PIjBN+b84iSkhIzd7FL1X/BX6NPDtL15BsaxyJ9OOHjaw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR03MB11232 X-purgate-ID: tlsNG-42698a/1775053689-F63C62A1-D5278358/0/0 X-purgate-type: clean X-purgate-size: 1920 In RTDS, removing the last eligible pCPU can kill repl_timer. When a pCPU is later re-added, rt_switch_sched() reinitializes the timer object, but pending entries may already exist in replq. Without re-arming from replq head, replenishment can remain inactive until some unrelated event programs the timer again. This may stall budget replenishment for non-extratime units. Fix this by re-arming repl_timer in rt_switch_sched() immediately after init_timer() when replq is non-empty, using the earliest pending deadline. This keeps behavior unchanged when replq is empty. Add a lightweight regression script, test_rtds_repl_timer_rearm.sh, to verify source-level guards and model the expected re-arm decision logic. Signed-off-by: Oleksii Moisieiev --- xen/common/sched/rt.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/common/sched/rt.c b/xen/common/sched/rt.c index 7b1f64a779..59021e1110 100644 --- a/xen/common/sched/rt.c +++ b/xen/common/sched/rt.c @@ -741,8 +741,17 @@ rt_switch_sched(struct scheduler *new_ops, unsigned in= t cpu, if ( prv->repl_timer.status =3D=3D TIMER_STATUS_invalid || prv->repl_timer.status =3D=3D TIMER_STATUS_killed ) { + struct list_head *replq =3D rt_replq(new_ops); + init_timer(&prv->repl_timer, repl_timer_handler, (void *)new_ops, = cpu); dprintk(XENLOG_DEBUG, "RTDS: timer initialized on cpu %u\n", cpu); + + /* + * When re-adding CPUs after all RTDS CPUs were removed, replq may + * already contain pending replenishment events. Re-arm immediatel= y. + */ + if ( !list_empty(replq) ) + set_timer(&prv->repl_timer, replq_elem(replq->next)->cur_deadl= ine); } =20 sched_idle_unit(cpu)->priv =3D vdata; --=20 2.43.0 base-commit: a7bf8ff218ca05eb3674fdfd2817f6cff471e96a= From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:29:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:29:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270435.1559102 (Exim 4.92) (envelope-from ) id 1w7wZA-0002bj-0c; Wed, 01 Apr 2026 14:29:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270435.1559102; Wed, 01 Apr 2026 14:29:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wZ9-0002bc-U9; Wed, 01 Apr 2026 14:29:07 +0000 Received: by outflank-mailman (input) for mailman id 1270435; Wed, 01 Apr 2026 14:29:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7wZ9-0002bW-5J for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:29:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7wZ8-007BsH-HN for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 16:29:06 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2ba2-bab6-0a2a0a5309dd-0a2a4509c04e-24 for ; Wed, 01 Apr 2026 16:29:06 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2bb2-bf79-0a2a45090019-d1558034ac07-3 for ; Wed, 01 Apr 2026 16:29:06 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-486fb439299so65391735e9.0 for ; Wed, 01 Apr 2026 07:29:06 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775053746-2FD47152-3D53C688/10/73395122804 X-purgate-type: spam X-purgate-size: 977 On 10.03.2026 18:08, Oleksii Kurochko wrote: > No RISC-V-specific nodes need to be created at the moment, > so make_arch_nodes() is implemented to simply return 0. > > Signed-off-by: Oleksii Kurochko Same question as on the previous patch, albeit to a lesser degree: An arch hook may plausibly exist (and be called) uniformly, even if on some arch-es it doesn't do anything. > --- > xen/arch/riscv/Makefile | 1 + > xen/arch/riscv/dom0less-build.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) > create mode 100644 xen/arch/riscv/dom0less-build.c Further, on what basis is this function put in this new file, when the earlier ones live in domain-build.c? > --- a/xen/arch/riscv/Makefile > +++ b/xen/arch/riscv/Makefile > @@ -1,5 +1,6 @@ > obj-y += aplic.o > obj-y += cpufeature.o > +obj-y += dom0less-build.o obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o just like Arm has it? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775053914-17F462A1-59C74028/0/0 X-purgate-type: clean X-purgate-size: 1102 On 01.04.2026 16:28, Oleksii Moisieiev wrote: > In RTDS, removing the last eligible pCPU can kill repl_timer. > When a pCPU is later re-added, rt_switch_sched() reinitializes the > timer object, but pending entries may already exist in replq. > > Without re-arming from replq head, replenishment can remain inactive > until some unrelated event programs the timer again. This may stall > budget replenishment for non-extratime units. > > Fix this by re-arming repl_timer in rt_switch_sched() immediately after > init_timer() when replq is non-empty, using the earliest pending > deadline. > > This keeps behavior unchanged when replq is empty. > > Add a lightweight regression script, > test_rtds_repl_timer_rearm.sh, to verify source-level guards and model > the expected re-arm decision logic. > Signed-off-by: Oleksii Moisieiev What is this last (improperly separated from the S-o-b) paragraph about? No ... > --- > > xen/common/sched/rt.c | 9 +++++++++ > 1 file changed, 9 insertions(+) ... new script is being introduced. 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This may stall >> budget replenishment for non-extratime units. >> >> Fix this by re-arming repl_timer in rt_switch_sched() immediately after >> init_timer() when replq is non-empty, using the earliest pending >> deadline. >> >> This keeps behavior unchanged when replq is empty. >> >> Add a lightweight regression script, >> test_rtds_repl_timer_rearm.sh, to verify source-level guards and model >> the expected re-arm decision logic. >> Signed-off-by: Oleksii Moisieiev > What is this last (improperly separated from the S-o-b) paragraph about? > No ... > Sry for that. this leftover from squashing... Will remove. Made a unit tests to check the behavior. >> --- >> >> xen/common/sched/rt.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) > ... new script is being introduced. > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:38:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:38:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270464.1559129 (Exim 4.92) (envelope-from ) id 1w7wi8-0005ZY-BE; Wed, 01 Apr 2026 14:38:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270464.1559129; Wed, 01 Apr 2026 14:38:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wi8-0005ZR-80; Wed, 01 Apr 2026 14:38:24 +0000 Received: by outflank-mailman (input) for mailman id 1270464; Wed, 01 Apr 2026 14:38:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w7wi6-0005VK-A3 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:38:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7wi5-003JFB-M3 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 16:38:21 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2dd3-2eae-0a2a0a5409dd-0a2a4505e82c-18 for ; Wed, 01 Apr 2026 16:38:21 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2ddd-3760-0a2a45050019-d155802be4d8-3 for ; Wed, 01 Apr 2026 16:38:21 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-487012ce896so43148355e9.0 for ; Wed, 01 Apr 2026 07:38:21 -0700 (PDT) Received: from ?IPV6:2a01:cb15:80df:da00:6d45:ff60:3ad6:d7fa? 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I just thought that maybe you have a solution >> already just in your head. > Well, I do: Don't make this an out-of-line function. > >> I wonder >>> about "temporary" though: Do you have a clear understanding as to when >>> that will change? >> No, I don't. As Stefano mentioned they will need this function one day. >> Another option we could use ifndef x86 or ifdef DOM0_LESS and then when >> someone will really need it on x86, this ifdef will be dropped. I don't >> know if it is better solution. >> >> It seems like the best one solution will still make a try to make >> declare this function as macro. > Or an inline function. There's nothing ... > >>>>>> @@ -2544,6 +2544,12 @@ void thaw_domains(void) >>>>>> >>>>>> #endif /* CONFIG_SYSTEM_SUSPEND */ >>>>>> >>>>>> +bool domain_use_host_layout(struct domain *d) >>>>>> +{ >>>>>> + return is_domain_direct_mapped(d) || >>>>>> + (paging_mode_translate(d) && is_hardware_domain(d)); >>>>>> +} >>>>> The placement of paging_mode_translate() doesn't match ... >>>>> >>>>>> --- a/xen/include/xen/domain.h >>>>>> +++ b/xen/include/xen/domain.h >>>>>> @@ -62,6 +62,22 @@ void domid_free(domid_t domid); >>>>>> #define is_domain_direct_mapped(d) ((d)->cdf & CDF_directmap) >>>>>> #define is_domain_using_staticmem(d) ((d)->cdf & CDF_staticmem) >>>>>> >>>>>> +/* >>>>>> + * Is the auto-translated domain using the host memory layout? >>>>>> + * >>>>>> + * domain_use_host_layout() is always False for PV guests. >>>>> ... the description of the function. >>>> But why the placement should be different? >>> If you focus on auto-translated, then imo paging_mode_translate() >>> better would guard everything. >> Then it make sense to do in the following way: >> bool domain_use_host_layout(struct domain *d) >> { >> - return is_domain_direct_mapped(d) || >> - (paging_mode_translate(d) && is_hardware_domain(d)); >> + return paging_mode_translate(d) && >> + (is_domain_direct_mapped(d) || is_hardware_domain(d)); >> } > ... in here which clearly speaks against doing so. And yes, this is what I > was asking for (with the function parameter also suitably constified). I expect that with an inline function in xen/domain.h compiler will want have paging_mode_translate() be explicitly defined, so an inclusion of xen/paging.h will be needed, but likely I am wrong that it will be needed it the case of inline function. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:38:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:38:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270476.1559138 (Exim 4.92) (envelope-from ) id 1w7wiZ-000635-Iz; Wed, 01 Apr 2026 14:38:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270476.1559138; Wed, 01 Apr 2026 14:38:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wiZ-00062y-GM; Wed, 01 Apr 2026 14:38:51 +0000 Received: by outflank-mailman (input) for mailman id 1270476; Wed, 01 Apr 2026 14:38:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wiX-00062Y-NJ for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:38:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7wiX-00GO0h-39 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 16:38:49 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd2dec-bab6-0a2a0a5309dd-0a2a4503909c-26 for ; Wed, 01 Apr 2026 16:38:49 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2df7-02b3-0a2a45030019-d1558032f1ad-3 for ; Wed, 01 Apr 2026 16:38:47 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-486fb14227cso92586735e9.3 for ; Wed, 01 Apr 2026 07:38:47 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775054327-41D16C9A-8255C78B/0/0 X-purgate-type: clean X-purgate-size: 1659 On 10.03.2026 18:08, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/dom0less-build.c > +++ b/xen/arch/riscv/dom0less-build.c > @@ -3,6 +3,15 @@ > #include > #include > > +#include > + > +int __init make_intc_domU_node(struct kernel_info *kinfo) > +{ > + intc_make_domu_dt_node(kinfo); > + > + return 0; > +} Is this wrapper really needed? Can't what's intc_make_domu_dt_node() right now become make_intc_domU_node()? > @@ -41,6 +41,10 @@ struct intc_hw_operations { > > /* handle external interrupt */ > void (*handle_interrupt)(struct cpu_user_regs *regs); > + > + /* Create interrupt controller node for domain */ > + int (*make_dom_dt_node)(const struct kernel_info *kinfo, > + const struct dt_device_node *intc); An __init-only hook is somewhat risky, just to mention it. In IOMMU code besides struct iommu_ops we have struct iommu_init_ops, just to give an example of where the same could have been the case. > --- a/xen/arch/riscv/intc.c > +++ b/xen/arch/riscv/intc.c > @@ -67,3 +67,11 @@ void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) > intc_set_irq_type(desc, desc->arch.type); > intc_set_irq_priority(desc, priority); > } > + > +int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) > +{ > + if ( intc_hw_ops && intc_hw_ops->make_dom_dt_node ) > + return intc_hw_ops->make_dom_dt_node(kinfo, intc_hw_ops->info->node); > + > + return -ENOSYS; How do you justify this choice of return value? This isn't even a hypercall handler. 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>>>>>>> + * >>>>>>> + * domain_use_host_layout() is always False for PV guests. >>>>>> >>>>>> ... the description of the function. >>>>> >>>>> But why the placement should be different? >>>> >>>> If you focus on auto-translated, then imo paging_mode_translate() >>>> better would guard everything. >>> >>> Then it make sense to do in the following way: >>>  bool domain_use_host_layout(struct domain *d) >>>  { >>> -    return is_domain_direct_mapped(d) || >>> -           (paging_mode_translate(d) && is_hardware_domain(d)); >>> +    return paging_mode_translate(d) && >>> +           (is_domain_direct_mapped(d) || is_hardware_domain(d)); >>>  } >> >> This is not really correct. > > ... because of ... ? (After all, then the comment isn't correct either.) I thought it could break what Arm had before when paging_mode_translate() is false, but it is always true for Arm, so with paging_mode_translate() being true, the new definition is equivalent to what it had before. So looks goods. ~ Oleksii > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:48:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:48:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270509.1559156 (Exim 4.92) (envelope-from ) id 1w7wrd-000075-QU; Wed, 01 Apr 2026 14:48:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270509.1559156; Wed, 01 Apr 2026 14:48:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wrd-00006y-NK; Wed, 01 Apr 2026 14:48:13 +0000 Received: by outflank-mailman (input) for mailman id 1270509; Wed, 01 Apr 2026 14:48:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7wrc-00006s-8e for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 14:48:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7wrb-00GPst-80 for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 16:48:11 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd300e-2eae-0a2a0a5409dd-0a2a4504dbc0-42 for ; Wed, 01 Apr 2026 16:48:10 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd2f3a-bb33-0a2a45040019-d155802ac9c2-3 for ; Wed, 01 Apr 2026 16:44:10 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-48558d6ef83so70235065e9.3 for ; Wed, 01 Apr 2026 07:44:10 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1775054650-B293951B-8D4C63A7/13/0 X-purgate-type: clean X-purgate-size: 9225 On 01.04.2026 16:40, Mykyta Poturai wrote: > > > On 4/1/26 17:14, Jan Beulich wrote: >> On 01.04.2026 16:07, Mykyta Poturai wrote: >>> On 4/1/26 11:21, Jan Beulich wrote: >>>> On 01.04.2026 09:59, Mykyta Poturai wrote: >>>>> On 3/31/26 17:55, Jan Beulich wrote: >>>>>> On 09.03.2026 12:08, Mykyta Poturai wrote: >>>>>>> --- a/xen/drivers/vpci/header.c >>>>>>> +++ b/xen/drivers/vpci/header.c >>>>>>> @@ -175,76 +175,92 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, >>>>>>> >>>>>>> bool vpci_process_pending(struct vcpu *v) >>>>>>> { >>>>>>> - const struct pci_dev *pdev = v->vpci.pdev; >>>>>>> - struct vpci_header *header = NULL; >>>>>>> - unsigned int i; >>>>>>> - >>>>>>> - if ( !pdev ) >>>>>>> - return false; >>>>>>> - >>>>>>> - read_lock(&v->domain->pci_lock); >>>>>>> - >>>>>>> - if ( !pdev->vpci || (v->domain != pdev->domain) ) >>>>>>> + switch ( v->vpci.task ) >>>>>>> { >>>>>>> - v->vpci.pdev = NULL; >>>>>>> - read_unlock(&v->domain->pci_lock); >>>>>>> - return false; >>>>>>> - } >>>>>>> - >>>>>>> - header = &pdev->vpci->header; >>>>>>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>>>> + case MODIFY_MEMORY: >>>>>>> { >>>>>>> - struct vpci_bar *bar = &header->bars[i]; >>>>>>> - struct rangeset *mem = v->vpci.bar_mem[i]; >>>>>>> - struct map_data data = { >>>>>>> - .d = v->domain, >>>>>>> - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, >>>>>>> - .bar = bar, >>>>>>> - }; >>>>>>> - int rc; >>>>>>> + const struct pci_dev *pdev = v->vpci.memory.pdev; >>>>>>> + struct vpci_header *header = NULL; >>>>>>> + unsigned int i; >>>>>>> >>>>>>> - if ( rangeset_is_empty(mem) ) >>>>>>> - continue; >>>>>>> + if ( !pdev ) >>>>>>> + break; >>>>>>> >>>>>>> - rc = rangeset_consume_ranges(mem, map_range, &data); >>>>>>> + read_lock(&v->domain->pci_lock); >>>>>>> >>>>>>> - if ( rc == -ERESTART ) >>>>>>> + if ( !pdev->vpci || (v->domain != pdev->domain) ) >>>>>>> { >>>>>>> + v->vpci.memory.pdev = NULL; >>>>>>> read_unlock(&v->domain->pci_lock); >>>>>>> - return true; >>>>>>> + break; >>>>>>> } >>>>>>> >>>>>>> - if ( rc ) >>>>>>> + header = &pdev->vpci->header; >>>>>>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>>>> { >>>>>>> - spin_lock(&pdev->vpci->lock); >>>>>>> - /* Disable memory decoding unconditionally on failure. */ >>>>>>> - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, >>>>>>> - false); >>>>>>> - spin_unlock(&pdev->vpci->lock); >>>>>>> + struct vpci_bar *bar = &header->bars[i]; >>>>>>> + struct rangeset *mem = v->vpci.bar_mem[i]; >>>>>>> + struct map_data data = { >>>>>>> + .d = v->domain, >>>>>>> + .map = v->vpci.memory.cmd & PCI_COMMAND_MEMORY, >>>>>>> + .bar = bar, >>>>>>> + }; >>>>>>> + int rc; >>>>>>> + >>>>>>> + if ( rangeset_is_empty(mem) ) >>>>>>> + continue; >>>>>>> >>>>>>> - /* Clean all the rangesets */ >>>>>>> - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>>>> - if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>>>>>> - rangeset_purge(v->vpci.bar_mem[i]); >>>>>>> + rc = rangeset_consume_ranges(mem, map_range, &data); >>>>>>> >>>>>>> - v->vpci.pdev = NULL; >>>>>>> + if ( rc == -ERESTART ) >>>>>>> + { >>>>>>> + read_unlock(&v->domain->pci_lock); >>>>>>> + return true; >>>>>>> + } >>>>>>> >>>>>>> - read_unlock(&v->domain->pci_lock); >>>>>>> + if ( rc ) >>>>>>> + { >>>>>>> + spin_lock(&pdev->vpci->lock); >>>>>>> + /* Disable memory decoding unconditionally on failure. */ >>>>>>> + modify_decoding(pdev, v->vpci.memory.cmd & ~PCI_COMMAND_MEMORY, >>>>>>> + false); >>>>>>> + spin_unlock(&pdev->vpci->lock); >>>>>>> + >>>>>>> + /* Clean all the rangesets */ >>>>>>> + for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) >>>>>>> + if ( !rangeset_is_empty(v->vpci.bar_mem[i]) ) >>>>>>> + rangeset_purge(v->vpci.bar_mem[i]); >>>>>>> + >>>>>>> + v->vpci.memory.pdev = NULL; >>>>>>> + >>>>>>> + read_unlock(&v->domain->pci_lock); >>>>>>> >>>>>>> - if ( !is_hardware_domain(v->domain) ) >>>>>>> - domain_crash(v->domain); >>>>>>> + if ( !is_hardware_domain(v->domain) ) >>>>>>> + domain_crash(v->domain); >>>>>>> >>>>>>> - return false; >>>>>>> + break; >>>>>>> + } >>>>>>> } >>>>>>> - } >>>>>>> - v->vpci.pdev = NULL; >>>>>>> + v->vpci.memory.pdev = NULL; >>>>>>> >>>>>>> - spin_lock(&pdev->vpci->lock); >>>>>>> - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); >>>>>>> - spin_unlock(&pdev->vpci->lock); >>>>>>> + spin_lock(&pdev->vpci->lock); >>>>>>> + modify_decoding(pdev, v->vpci.memory.cmd, v->vpci.memory.rom_only); >>>>>>> + spin_unlock(&pdev->vpci->lock); >>>>>>> >>>>>>> - read_unlock(&v->domain->pci_lock); >>>>>>> + read_unlock(&v->domain->pci_lock); >>>>>>> + >>>>>>> + break; >>>>>>> + } >>>>>>> + case WAIT: >>>>>>> + if ( NOW() < v->vpci.wait.end ) >>>>>>> + return true; >>>>>>> + v->vpci.wait.callback(v->vpci.wait.data); >>>>>>> + break; >>>>>> >>>>>> As just indicated in reply to patch 6, busy waiting isn't really acceptable. >>>>>> This is even more so when the waiting exceeds the typical length of a >>>>>> scheduling timeslice. >>>>>> >>>>>> In that other reply I said to put the vCPU to sleep, but you need to be careful >>>>>> there too: The domain may not expect its vCPU to not make any progress for such >>>>>> an extended period of time. This may need doing entirely differently: Once the >>>>>> command register was written, you may want to record the time after which >>>>>> accesses to the VF registers are permitted. Earlier accesses would simply be >>>>>> terminated. You may still additionally need a timer, in order to kick off BAR >>>>>> mapping after that time. (Yet better would be if the BAR mapping could be >>>>>> done during those 100ms. After all that may be a reason why this long a delay >>>>>> is specified: Firmware on the device may also require some time to set up the >>>>>> BARs accordingly.) >>>>> >>>>> I am not sure it would work that way. If we look at how linux >>>>> initialized sriov, it writes VFE and MSE bits, waits 100ms and then >>>>> expects VFs to be operational. If they are not operational at that >>>>> moment, then it considers the operation failed and removes all VFs. If >>>>> we also wait 100ms before enabling access, the probability of a guest >>>>> trying to access something before we allow it would be very high. >>>> >>>> Well, not really. Our counting of the 100ms necessarily starts before Dom0's. >>>> Furthermore it may be acceptable (or even appropriate) to stall premature >>>> accesses (because they shouldn't occur in the first place), by blocking the >>>> vCPU at that point. A middle route may be possible: Terminate accesses in, >>>> say, the first 90ms, and stall the vCPU for any access past that, but before >>>> the 100ms expired. >>> >>> Is there any real benefit to doing all this work instead of just waiting >>> for Dom0 to register the FVs? Implementing it the way you described >>> would require a relatively complex state machine and two timers per >>> sriov-capable device. And will also probably require some hacks to >>> handle partially initialized VFs in Xen. This adds a lot of work and >>> many possible bugs for not a lot of benefit in my opinion. >> >> Odd that you ask me this question. If there was no benefit, why did you do >> it this way? > > Roger asked for this approach in V1, and I saw that it can be done in a > relatively straightforward way, so I implemented it. I didn’t exactly > get what the benefits were, but I assumed that there are some and the > effort is not too big to just do it if the maintainers are asking for it. > > Now with the posibility of redoing everything *again* and making it much > more complex I started to really think if its really needed. So I want > to know your and others' opinions on registering VFs with Dom0. Well, before I voice any view here I'd need to understand why Roger wanted it done like that. (Apparently you must have agreed sufficiently to not ask back.) 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <600b1b66-fd85-4b7f-8bdc-793667bccfec@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775054544-658533D8-99C9EB55/0/0 X-purgate-type: clean X-purgate-size: 3870 On 01.04.2026 16:38, Oleksii Kurochko wrote: > > > On 4/1/26 7:58 AM, Jan Beulich wrote: >> On 31.03.2026 18:32, Oleksii Kurochko wrote: >>> On 3/31/26 5:53 PM, Jan Beulich wrote: >>>> On 31.03.2026 17:20, Oleksii Kurochko wrote: >>>>> On 3/30/26 5:13 PM, Jan Beulich wrote: >>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>> domain_use_host_layout() is not really architecture-specific, so move it >>>>>>> from the Arm header to the common header xen/domain.h and provide a common >>>>>>> implementation in xen/common/domain.c. domain_use_host_layout() potentially >>>>>>> is needed for x86 [1]. >>>>>> No matter that this may indeed be true, ... >>>>>> >>>>>>> Turn the macro into a function to avoid header dependency issues. >>>>>> ... this introduces unreachable code on x86, i.e. a Misra rule 2.1 violation. >>>>> Do we have some deviation tag for such cases when the code temporary >>>>> isn't used? >>>> I'm sorry, but it'll take me about as long as you to find out. >>> Sure, I will take a look. I just thought that maybe you have a solution >>> already just in your head. >> Well, I do: Don't make this an out-of-line function. >> >>> I wonder >>>> about "temporary" though: Do you have a clear understanding as to when >>>> that will change? >>> No, I don't. As Stefano mentioned they will need this function one day. >>> Another option we could use ifndef x86 or ifdef DOM0_LESS and then when >>> someone will really need it on x86, this ifdef will be dropped. I don't >>> know if it is better solution. >>> >>> It seems like the best one solution will still make a try to make >>> declare this function as macro. >> Or an inline function. There's nothing ... >> >>>>>>> @@ -2544,6 +2544,12 @@ void thaw_domains(void) >>>>>>> >>>>>>> #endif /* CONFIG_SYSTEM_SUSPEND */ >>>>>>> >>>>>>> +bool domain_use_host_layout(struct domain *d) >>>>>>> +{ >>>>>>> + return is_domain_direct_mapped(d) || >>>>>>> + (paging_mode_translate(d) && is_hardware_domain(d)); >>>>>>> +} >>>>>> The placement of paging_mode_translate() doesn't match ... >>>>>> >>>>>>> --- a/xen/include/xen/domain.h >>>>>>> +++ b/xen/include/xen/domain.h >>>>>>> @@ -62,6 +62,22 @@ void domid_free(domid_t domid); >>>>>>> #define is_domain_direct_mapped(d) ((d)->cdf & CDF_directmap) >>>>>>> #define is_domain_using_staticmem(d) ((d)->cdf & CDF_staticmem) >>>>>>> >>>>>>> +/* >>>>>>> + * Is the auto-translated domain using the host memory layout? >>>>>>> + * >>>>>>> + * domain_use_host_layout() is always False for PV guests. >>>>>> ... the description of the function. >>>>> But why the placement should be different? >>>> If you focus on auto-translated, then imo paging_mode_translate() >>>> better would guard everything. >>> Then it make sense to do in the following way: >>> bool domain_use_host_layout(struct domain *d) >>> { >>> - return is_domain_direct_mapped(d) || >>> - (paging_mode_translate(d) && is_hardware_domain(d)); >>> + return paging_mode_translate(d) && >>> + (is_domain_direct_mapped(d) || is_hardware_domain(d)); >>> } >> ... in here which clearly speaks against doing so. And yes, this is what I >> was asking for (with the function parameter also suitably constified). > > I expect that with an inline function in xen/domain.h compiler will want > have paging_mode_translate() be explicitly defined, so an inclusion of > xen/paging.h will be needed, but likely I am wrong that it will be > needed it the case of inline function. I don't think you're wrong with that. What I don't understand is why it needs to be xen/domain.h where the function would be placed. If need be you could make an entirely new header, where (presumably) you're not going to have any include recursion concerns. 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For example, what if more than 2Gb of MMIO space are needed >>>>> for non-64-bit BARs? >>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>> before RAM start is enough for MMIO space. >>> Likely in the common case. Board designers aren't constrained by this, >>> though (aiui). Whereas you set in stone a single, fixed layout. >>> >>> Arm maintainers - since a similar fixed layout is used there iirc, >>> could you chime in here, please? >>> >>>> Answering your question it will be an issue or it will also use some >>>> space before banks, no? >>> I fear I don't understand what you're trying to tell me. >> I meant that there is also some space between banks and pretty big which >> could be used for MMIO which could be used for non-64-bit BARs. > I don't follow: Bank 0 extends to 4G. There's no space above it, below > bank 1, which could be use for non-64-bit BARs. So we have two banks: bank[0] -> [0x80000000, 0x100000000) bank[1] -> [0x0200000000, 10000000000) So i think we have some space between them [0x100000000, 0x0200000000) -> 4gb to be used for non-64-bit BARs. And also we have another 2gb before bank[0]. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:58:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:58:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270545.1559193 (Exim 4.92) (envelope-from ) id 1w7x1d-0003iB-Jz; Wed, 01 Apr 2026 14:58:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270545.1559193; Wed, 01 Apr 2026 14:58:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7x1d-0003i3-EW; Wed, 01 Apr 2026 14:58:33 +0000 Received: by outflank-mailman (input) for mailman id 1270545; Wed, 01 Apr 2026 14:58:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7x1b-0003hW-V0 for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm: acpi: Rename local acpi_size to avoid shadowing typedef Date: Wed, 1 Apr 2026 16:58:14 +0200 Message-ID: <20260401145816.169557-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260401145816.169557-1-michal.orzel@amd.com> References: <20260401145816.169557-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000149:EE_|IA1PR12MB9523:EE_ X-MS-Office365-Filtering-Correlation-Id: 4920bb35-0988-49b5-d3d7-08de8fff1eb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MdIC+eLYGsSz9HVa3WNUwB4SBMVQ1V7IFjIqh9OIEu7eb8uKsbU48RZVpbkkVlj1TTusILNq9uCT/6iLCQqiGtGiCKvkgVBoDZp/VmM3AIzX/0utsfwYC5aQJUhJvZwTVK+YfAf6QXokRN/7v5RM2HkPv3N74GPc1cCrYpGnSn1ve9M5ko/7oE30OY2z7pdb0zS6N9TddwVyLn9NuG7Ce7Qkx9dLHRbnWlNdoJUW5RJyB96yNJKMbsYSDwsnZM5kvxp2xU61PLBNfeTQgzv7vjrQl8FW7mmSDi7CFVkLHDG28Kqqfz7TJ2xr6181JemPY9oeTl34u38+qGT2m8n/svVCwD/DbH1g5Z/NHoUQlRKXI0OU8M6N52PckjeJoCgDRaBbKfYO7F/WZ9zqyTWMLLi1vipVVY5dpYX8SX66oVfTJfQi7dL7G9kFjbjCkk3J X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 14:58:22.7348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4920bb35-0988-49b5-d3d7-08de8fff1eb6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000149.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9523 X-purgate-ID: tlsNG-bad1c0/1775055510-5734C152-E07CEAC3/0/0 X-purgate-type: clean X-purgate-size: 2215 Rename the local variable acpi_size to acpi_len in estimate_acpi_efi_size() to avoid shadowing the acpi_size typedef from xen/include/acpi/actypes.h. This resolves a MISRA C Rule 5.6 violation. Signed-off-by: Michal Orzel --- xen/arch/arm/acpi/domain_build.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/acpi/domain_build.c b/xen/arch/arm/acpi/domain_build.c index 1c3555d814cc..5a117001ef11 100644 --- a/xen/arch/arm/acpi/domain_build.c +++ b/xen/arch/arm/acpi/domain_build.c @@ -447,18 +447,18 @@ static int __init acpi_create_fadt(struct domain *d, struct membank tbl_add[]) static int __init estimate_acpi_efi_size(struct domain *d, const struct kernel_info *kinfo) { - size_t efi_size, acpi_size, madt_size; + size_t efi_size, acpi_len, madt_size; u64 addr; struct acpi_table_rsdp *rsdp_tbl; struct acpi_table_header *table; efi_size = estimate_efi_size(kernel_info_get_mem_const(kinfo)->nr_banks); - acpi_size = ROUNDUP(sizeof(struct acpi_table_fadt), 8); - acpi_size += ROUNDUP(sizeof(struct acpi_table_stao), 8); + acpi_len = ROUNDUP(sizeof(struct acpi_table_fadt), 8); + acpi_len += ROUNDUP(sizeof(struct acpi_table_stao), 8); madt_size = gic_get_hwdom_madt_size(d); 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Update domain.c to include instead of the removed private header. This ensures the declarations are visible where the functions are defined, resolving a MISRA C Rule 8.4 violation. Signed-off-by: Michal Orzel --- I'm moving a file with GPL2+ license to a file with GPL2-only. I consider this ok in this case becase the copyright on a file with just prototypes does not make any sense and a license text was most likely blindly copy-pasted like for most of the files in that era. --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/include/asm/vpci.h | 18 ++++++++++++++ xen/arch/arm/vpci.h | 42 --------------------------------- 3 files changed, 19 insertions(+), 43 deletions(-) delete mode 100644 xen/arch/arm/vpci.h diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 581f82bddd48..26380a807cad 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -31,10 +31,10 @@ #include #include #include +#include #include #include -#include "vpci.h" #include "vuart.h" DEFINE_PER_CPU(struct vcpu *, curr_vcpu); diff --git a/xen/arch/arm/include/asm/vpci.h b/xen/arch/arm/include/asm/vpci.h index db04687fc099..0cc6f5a10532 100644 --- a/xen/arch/arm/include/asm/vpci.h +++ b/xen/arch/arm/include/asm/vpci.h @@ -2,6 +2,9 @@ #ifndef ARM_VPCI_H #define ARM_VPCI_H +struct domain; + +#ifdef CONFIG_HAS_VPCI /* Arch-specific MSI data for vPCI. */ struct vpci_arch_msi { }; @@ -10,4 +13,19 @@ struct vpci_arch_msi { struct vpci_arch_msix_entry { }; + +int domain_vpci_init(struct domain *d); +unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d); +#else +static inline int domain_vpci_init(struct domain *d) +{ + return 0; +} + +static inline unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) +{ + return 0; +} +#endif /* CONFIG_HAS_VPCI */ + #endif /* ARM_VPCI_H */ diff --git a/xen/arch/arm/vpci.h b/xen/arch/arm/vpci.h deleted file mode 100644 index 3c713f3fcdb5..000000000000 --- a/xen/arch/arm/vpci.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * xen/arch/arm/vpci.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_VPCI_H__ -#define __ARCH_ARM_VPCI_H__ - -#ifdef CONFIG_HAS_VPCI -int domain_vpci_init(struct domain *d); -unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d); -#else -static inline int domain_vpci_init(struct domain *d) -{ - return 0; -} - -static inline unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) -{ - return 0; -} -#endif - -#endif /* __ARCH_ARM_VPCI_H__ */ - -/* - * Local variables: - * mode: C - * c-file-style: "BSD" - * c-basic-offset: 4 - * indent-tabs-mode: nil - * End: - */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:58:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:58:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270553.1559210 (Exim 4.92) (envelope-from ) id 1w7x1s-0004SU-7z; Wed, 01 Apr 2026 14:58:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270553.1559210; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AcrG56HInp9MW3Ca18f4YugSR/stvOMOudgEeA0EanNL64x1sYPj6DRdXHB6MIODaRXvrtzB7x3+OwaSnh4buHtJGcztcCffXoW1X1od9pgourL/qiHd5EmTkqgXKzqKHQ5D8LcPlgG9BsCbBQaAfA+CkMLbYjStx7D5bnjqY66etAL1Q8EdBn6EGZ0Y9EbsWfv+G8+T9QoYcZGGUHMIT21iszTN6wFyD9Z2XZMrNgJ/upWHmtqIu+1xLH11tpsaTZPxGF7RykppmTSSQHwM8Rjrbrr8wJkZCbb1iOobxlfhbX8qQZdXynFWoFnq9zFLhR/F07MwMGvNTWnZ3EYLiLwbgR3hOSn8HKt3n5mNb1IdgY+Cofun9GanFWvQG3vz6XxIZgH04q6w5PcGQOqitIEhU/hSxf3y+0qhwi6QcRvWdyVetd2eS9sFDw5UiGjW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 14:58:24.1309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18dfb3eb-8378-41f4-44cb-08de8fff1f8c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6937 X-purgate-ID: tlsNG-33051d/1775055525-40F6FC9A-284D97A4/0/0 X-purgate-type: clean X-purgate-size: 2925 Make pci_alloc_host_bridge() and pci_add_host_bridge() in pci-host-common.c, rcar4_pcie_ops and rcar4_pcie_child_ops in pci-host-rcar4.c, and nwl_pcie_ops in pci-host-zynqmp.c static, as they are only used within their respective translation units. Also include pci-host-rcar4.h in pci-host-rcar4.c so that the declarations of its externally visible functions are visible at the point of definition. This resolves MISRA C Rule 8.4 violations. Signed-off-by: Michal Orzel --- xen/arch/arm/pci/pci-host-common.c | 4 ++-- xen/arch/arm/pci/pci-host-rcar4.c | 5 +++-- xen/arch/arm/pci/pci-host-zynqmp.c | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host-common.c index 487c545f3a26..9060afc14d93 100644 --- a/xen/arch/arm/pci/pci-host-common.c +++ b/xen/arch/arm/pci/pci-host-common.c @@ -158,7 +158,7 @@ err_exit: return NULL; } -struct pci_host_bridge *pci_alloc_host_bridge(void) +static struct pci_host_bridge *pci_alloc_host_bridge(void) { struct pci_host_bridge *bridge = xzalloc(struct pci_host_bridge); @@ -170,7 +170,7 @@ struct pci_host_bridge *pci_alloc_host_bridge(void) return bridge; } -void pci_add_host_bridge(struct pci_host_bridge *bridge) +static void pci_add_host_bridge(struct pci_host_bridge *bridge) { list_add_tail(&bridge->node, &pci_host_bridges); } diff --git a/xen/arch/arm/pci/pci-host-rcar4.c b/xen/arch/arm/pci/pci-host-rcar4.c index 9290c6cac5d3..e1e8eb0ee1f9 100644 --- a/xen/arch/arm/pci/pci-host-rcar4.c +++ b/xen/arch/arm/pci/pci-host-rcar4.c @@ -13,6 +13,7 @@ #include #include "pci-designware.h" +#include "pci-host-rcar4.h" #define RCAR4_DWC_VERSION 0x520A @@ -61,7 +62,7 @@ static int __init rcar4_child_cfg_reg_index(struct dt_device_node *np) } /* ECAM ops */ -const struct pci_ecam_ops rcar4_pcie_ops = { +static const struct pci_ecam_ops rcar4_pcie_ops = { .bus_shift = 20, .cfg_reg_index = rcar4_cfg_reg_index, .pci_ops = { @@ -73,7 +74,7 @@ const struct pci_ecam_ops rcar4_pcie_ops = { } }; -const struct pci_ecam_ops rcar4_pcie_child_ops = { +static const struct pci_ecam_ops rcar4_pcie_child_ops = { .bus_shift = 20, .cfg_reg_index = rcar4_child_cfg_reg_index, .pci_ops = { diff --git a/xen/arch/arm/pci/pci-host-zynqmp.c b/xen/arch/arm/pci/pci-host-zynqmp.c index 2c4afa7a19d2..2d98b0069647 100644 --- a/xen/arch/arm/pci/pci-host-zynqmp.c +++ b/xen/arch/arm/pci/pci-host-zynqmp.c @@ -27,7 +27,7 @@ static int __init nwl_cfg_reg_index(struct dt_device_node *np) } /* ECAM ops */ -const struct pci_ecam_ops nwl_pcie_ops = { +static const struct pci_ecam_ops nwl_pcie_ops = { .bus_shift = 20, .cfg_reg_index = nwl_cfg_reg_index, .pci_ops = { -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 14:59:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 14:59:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270584.1559219 (Exim 4.92) (envelope-from ) id 1w7x2o-0005bz-Ha; Wed, 01 Apr 2026 14:59:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270584.1559219; Wed, 01 Apr 2026 14:59:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7x2o-0005bs-Ea; Wed, 01 Apr 2026 14:59:46 +0000 Received: by outflank-mailman (input) for mailman id 1270584; Wed, 01 Apr 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8154eae081d14da89f27bad581270cc5bba6ccfc.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775055952-EC9592A1-5420D53C/0/0 X-purgate-type: clean X-purgate-size: 4271 On 10.03.2026 18:08, Oleksii Kurochko wrote: > Guests using the IMSIC interrupt controller require a corresponding > Device Tree description. Add support for generating an IMSIC node when > building the guest DT. > > Keep a reference to the host IMSIC DT node and reuse its compatible > property while constructing the guest-visible node. Again raises a migration concern. Presumably a guest would then be able to migrate only to other hosts with the same compatible property. > @@ -487,3 +492,111 @@ int __init imsic_init(const struct dt_device_node *node) > > return rc; > } > + > +static int __init imsic_make_reg_property(struct domain *d, void *fdt) > +{ > + __be32 regs[4]; > + > + regs[0] = cpu_to_be32(imsic_cfg.base_addr >> 32); > + regs[1] = cpu_to_be32(imsic_cfg.base_addr); > + regs[2] = cpu_to_be32((IMSIC_MMIO_PAGE_SZ * d->max_vcpus) >> 32); > + regs[3] = cpu_to_be32(IMSIC_MMIO_PAGE_SZ * d->max_vcpus); Might be nice to encode as an initializer of the array variable. There don't look to be any side effects in the expressions used, so Misra should take no issue with this. > + return fdt_property(fdt, "reg", regs, sizeof(regs)); > +} > + > +static int __init imsic_set_interrupt_extended_prop(struct domain *d, > + void *fdt) > +{ > + uint32_t len = 0, pos = 0, cpu, phandle; At least pos and cpu should be of fixed width types. > + uint32_t *irq_ext; > + char buf[64]; Move this one into the loop's scope? > + int res; > + > + irq_ext = xvzalloc_array(uint32_t, d->max_vcpus * 2); > + if ( !irq_ext ) > + return -ENOMEM; > + > + for ( cpu = 0; cpu < d->max_vcpus; cpu++ ) > + { > + snprintf(buf, sizeof(buf), "/cpus/cpu@%u/interrupt-controller", cpu); > + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt, buf)); > + > + if ( phandle <= 0 ) > + return phandle; <= is odd to use on an unsigned type. Arm, in a similar situation, uses != . Yet then - if 0 is an error indicator, aren't you converting this into a success indicator for the caller? > + irq_ext[pos++] = cpu_to_be32(phandle); > + len += sizeof(uint32_t); As before, preferably sizeof() to clarify the connection. It's pretty obvious here, but still. Yet then - do you really need to maintain "len"? Why not use ... > + irq_ext[pos++] = cpu_to_be32(IRQ_S_EXT); > + len += sizeof(uint32_t); > + } > + > + res = fdt_property(fdt, "interrupts-extended", irq_ext, len); ... "d->max_vcpus * 2 * sizeof(*irq_ext)" here? > + XVFREE(irq_ext); This can be just xvfree(), as the variable goes out of scpoe just afterwards anyway. > + return res; > +} > + > +int __init imsic_make_dt_node(const struct kernel_info *kinfo) So this function is unused until the next patch. Acceptable as long as Eclair (or other) scans aren't done for RISC-V, but generally you may want to try to get used to order patches such that this is avoided. > +{ > + uint32_t len; > + const void *data = NULL; Why the initializer? > + int res = 0; > + void *fdt = kinfo->fdt; > + const struct dt_device_node *host_imsic_node = imsic_cfg.host_node; > + uint32_t *next_phandle = &kinfo->bd.d->arch.next_phandle; > + > + res = fdt_begin_node(fdt, host_imsic_node->full_name); > + if ( res ) > + return res; > + > + data = dt_get_property(host_imsic_node, "compatible", &len); > + if ( !data ) > + { > + printk(XENLOG_ERR "%s: Can't find 'compatible' property\n", > + host_imsic_node->full_name); > + > + return -ENOENT; > + } Move fdt_begin_node() down below here? > --- a/xen/arch/riscv/include/asm/imsic.h > +++ b/xen/arch/riscv/include/asm/imsic.h > @@ -57,11 +57,16 @@ struct imsic_config { > /* MSI */ > const struct imsic_msi *msi; > > + /* DT node of IMSIC */ > + const struct dt_device_node *host_node; Does "host" in the name carry much of a meaning? Maybe better dt_node, to (potentially) distinguish it from a NUMA node which also may need tracking for an imsic at some point? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775056232-5535C152-3E42469B/0/0 X-purgate-type: clean X-purgate-size: 2196 On 01.04.2026 16:53, Oleksii Kurochko wrote: > > > On 4/1/26 4:22 PM, Jan Beulich wrote: >> On 01.04.2026 15:57, Oleksii Kurochko wrote: >>> On 4/1/26 8:17 AM, Jan Beulich wrote: >>>> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>>>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>>>> so introduce macros to describe guest RAM banks. >>>>>>> >>>>>>> The reason for 2 banks is that there is typically always a use case for >>>>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>>>> there are other things under 4 GB it can conflict with (interrupt >>>>>>> controller, PCI BARs, etc.). >>>>>> Fixed layouts like the one you suggest come with (potentially severe) >>>>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>>>> for non-64-bit BARs? >>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>> before RAM start is enough for MMIO space. >>>> Likely in the common case. Board designers aren't constrained by this, >>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>> >>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>> could you chime in here, please? >>>> >>>>> Answering your question it will be an issue or it will also use some >>>>> space before banks, no? >>>> I fear I don't understand what you're trying to tell me. >>> I meant that there is also some space between banks and pretty big which >>> could be used for MMIO which could be used for non-64-bit BARs. >> I don't follow: Bank 0 extends to 4G. There's no space above it, below >> bank 1, which could be use for non-64-bit BARs. > > So we have two banks: > bank[0] -> [0x80000000, 0x100000000) > bank[1] -> [0x0200000000, 10000000000) > > So i think we have some space between them [0x100000000, 0x0200000000) > -> 4gb to be used for non-64-bit BARs. But a non-64-bit BAR need to be assigned an address below 0x100000000? > And also we have another 2gb before bank[0]. Yes, but I talked about that before. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 15:16:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 15:16:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270630.1559246 (Exim 4.92) (envelope-from ) id 1w7xJ9-0001df-D1; Wed, 01 Apr 2026 15:16:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270630.1559246; Wed, 01 Apr 2026 15:16:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7xJ9-0001dY-9e; Wed, 01 Apr 2026 15:16:39 +0000 Received: by outflank-mailman (input) for mailman id 1270630; Wed, 01 Apr 2026 15:16:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7xJ7-0001dS-NO for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 15:16:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7xJ6-0053IJ-UW for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 17:16:36 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69cd36c0-2eae-0a2a0a5409dd-0a2a4502c88e-38 for ; Wed, 01 Apr 2026 17:16:36 +0200 Received: from [209.85.218.54] (helo=mail-ej1-f54.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69cd36d4-42fa-0a2a45020019-d155da36e0b1-3 for ; Wed, 01 Apr 2026 17:16:36 +0200 Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-b982b0889d8so859745566b.2 for ; Wed, 01 Apr 2026 08:16:36 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <462b5f7dbe4e5084a35fb869b59327c6c92d1fbf.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775056596-4CBF5CD1-819FB2AD/0/0 X-purgate-type: clean X-purgate-size: 2195 On 10.03.2026 18:08, Oleksii Kurochko wrote: > @@ -295,6 +297,85 @@ static void cf_check aplic_set_irq_type(struct irq_desc *desc, > spin_unlock(&aplic.lock); > } > > +static int __init cf_check aplic_make_dom_dt_node( > + const struct kernel_info *kinfo, > + const struct dt_device_node *aplic_node) Nit: Entirely bogus indentation. > +{ > + uint32_t len; > + const __be32 *regs; > + const void *data = NULL; Again, why the initializer? > + int res = 0; > + void *fdt = kinfo->fdt; > + > + res = imsic_make_dt_node(kinfo); > + if ( res ) > + return res; > + > + res = fdt_begin_node(fdt, aplic_node->full_name); > + if (res) Nit: Style. > + return res; > + > + data = dt_get_property(aplic_node, "#interrupt-cells", &len); > + if ( !data ) > + { > + printk("%s: Can't find '#interrupt-cells' property\n", > + aplic_node->full_name); > + return -FDT_ERR_XEN(ENOENT); > + } Again, pull this up to be first in the function? > + res = fdt_property(fdt, "#interrupt-cells", data, len); > + if ( res ) > + return res; So host properties are again directly handed through to the guest? Shouldn't the number of interrupts (aiui that's the "number of cells" here) a guest gets be independent from the host it runs one? > + regs = dt_get_property(aplic_node, "reg", &len); > + if ( !regs ) > + { > + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); > + return -FDT_ERR_XEN(ENOENT); > + } > + > + res = fdt_property(fdt, "reg", regs, len); > + if ( res ) > + return res; > + > + data = dt_get_property(aplic_node, "riscv,num-sources", &len); > + if ( !data ) > + { > + printk("%s: Can't find 'riscv,num-sources' property\n", > + aplic_node->full_name); > + return -FDT_ERR_XEN(ENOENT); > + } > + > + res = fdt_property(fdt, "riscv,num-sources", data, len); > + if ( res ) > + return res; Or maybe this is the number of interrupts? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 01 16:01:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 16:01:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270662.1559256 (Exim 4.92) (envelope-from ) id 1w7y0c-000251-Q0; Wed, 01 Apr 2026 16:01:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270662.1559256; Wed, 01 Apr 2026 16:01:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7y0c-00024u-LK; Wed, 01 Apr 2026 16:01:34 +0000 Received: by outflank-mailman (input) for mailman id 1270662; Wed, 01 Apr 2026 16:01:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7y0b-00024m-Il for xen-devel@lists.xenproject.org; Wed, 01 Apr 2026 16:01:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w7y0a-00CfIT-By for xen-devel@lists.xenproject.org; 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dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775059290; bh=W9qx/b89lLAH5xKATjSr4FjoF8xSzZzboxnb+4KLYY8=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=gKwgVmSAxxvBbw1CPLzmPJv7PtM7inQR8cZwoafTWDdo4dBnnR87DPqffL+itfKia jLGAooi36YLbRnOlZDk4cfJkhQ70pO4Y86FtHaYjtr6IVn78mKX71s3sBGlNhPgVfG ziq9gdKcEDwgBcmTp0E18lygeAR3rk5K2WKN/2nRQ7PyqfA+eKN4FAJKBKRLZTtLnr oIBzTon1i40EZHvzz3GO0xpnaN4Crt7W9DVWwzKRyQzxha85dZAJOD/SJhCFpnm7pO BqRFv9sXOXsUigZ/ZhYC9HbVHD9HkaSeYly7cBvhskECynru7k7o036e3LI0JumiYc FpuYi+9bF5/xg== Message-ID: Date: Wed, 1 Apr 2026 18:01:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 2/3] of: Factor arguments passed to of_map_id() into a struct To: Frank Li , Vijayanand Jitta Cc: Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Saravana Kannan , Richard Zhu , Lucas Stach , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Prakash Gupta , Vikash Garodia , linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Charan Teja Kalla References: <20260331-parse_iommu_cells-v12-0-decfd305eea9@oss.qualcomm.com> <20260331-parse_iommu_cells-v12-2-decfd305eea9@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775059292-FF348A3D-2E1C22D6/0/0 X-purgate-type: clean X-purgate-size: 2575 On 31/03/2026 16:43, Frank Li wrote: > On Tue, Mar 31, 2026 at 07:34:47PM +0530, Vijayanand Jitta wrote: >> From: Charan Teja Kalla >> >> Change of_map_id() to take a pointer to struct of_phandle_args >> instead of passing target device node and translated IDs separately. >> Update all callers accordingly. >> >> Add an explicit filter_np parameter to of_map_id() and of_map_msi_id() >> to separate the filter input from the output. Previously, the target >> parameter served dual purpose: as an input filter (if non-NULL, only >> match entries targeting that node) and as an output (receiving the >> matched node with a reference held). Now filter_np is the explicit >> input filter and arg->np is the pure output. >> >> Previously, of_map_id() would call of_node_put() on the matched node >> when a filter was provided, making reference ownership inconsistent. >> Remove this internal of_node_put() call so that of_map_id() now always >> transfers ownership of the matched node reference to the caller via >> arg->np. Callers are now consistently responsible for releasing this >> reference with of_node_put(arg->np) when done. >> >> Suggested-by: Rob Herring (Arm) >> Suggested-by: Dmitry Baryshkov >> Signed-off-by: Charan Teja Kalla >> Signed-off-by: Vijayanand Jitta >> --- >> drivers/cdx/cdx_msi.c | 7 ++-- >> drivers/iommu/of_iommu.c | 4 +- >> drivers/irqchip/irq-gic-its-msi-parent.c | 11 ++++-- >> drivers/of/base.c | 68 +++++++++++++++++--------------- >> drivers/of/irq.c | 10 ++++- >> drivers/pci/controller/dwc/pci-imx6.c | 32 +++++++-------- >> >> for imx part. >> >> Reviewed-by: Frank Li So that's an Ack. Leaving a Rb tag for a tiny tiny piece of big patch will give impression that everything is reviewed on v13. And the patch was not reviewed by you. If you cannot certify the reviewers statement of oversight then use acked "For instance, maintainers may use it to signify that they are OK with a patch landing, but they may not have reviewed it as thoroughly as if a Reviewed-by: was provided." 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pr=C Message-ID: Date: Wed, 1 Apr 2026 18:05:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] make ioremap_attr() common To: Jan Beulich , "xen-devel@lists.xenproject.org" CC: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk , Timothy Pearson References: <924f3ef2-7883-4322-a921-edc814c96719@suse.com> <81e4f7e0-df57-4a5b-b16d-fe668682d94c@suse.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <81e4f7e0-df57-4a5b-b16d-fe668682d94c@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC4:EE_|SJ0PR12MB8613:EE_ X-MS-Office365-Filtering-Correlation-Id: 8942affa-c2d1-4618-4cb1-08de900880e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: boHhRra85SIu4ZdrDm0X3dkP7PJDlYbgR3SgHo8oWCpExBsc1bQfwa6kFL5ILxcoPg4cUVmj0gVlDwk4KJyBEifd/LwqlnRvLO+Zf6y44AOqZrFuAAf19GX05lkJ48gFjUWHGSDZdF8RjBBC1DbdFXFAojQR+hQI+4VV8r0Cry6UGSORt8aO8xDfddTyF6P0bRdxR1DiIETbtGJwzFmpFTeajQmkCfLR9kfIBysoByT59TC1zlatWpPYhUlIQphhQBoxJl9S8U7qmL93sbz0DwVsm2JS5qYoC2zPFKfDf4pNlge5HWax0y46CaDE1RIDMwKBUpxD9iIbzbx88lJVks+hGM3k0ZcnWois06K4Apkn7l1Dc1lc0d2WBYh45ayhr6qlXZ7HT3rGgogM6mVuNLSHjNh3wHWqxygit+kjNXAba3SstUJ2td0obAhA51Yr X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2026 16:05:32.9202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8942affa-c2d1-4618-4cb1-08de900880e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8613 X-purgate-ID: tlsNG-c1860d/1775059539-F6151497-3409965B/0/0 X-purgate-type: clean X-purgate-size: 10085 On 19/02/2026 16:51, Jan Beulich wrote: > This core backing function is uniform; what varies across architectures > are the attributes passed and hence the wrappers around it. Yet of course > extra checking or special handling may be needed per arch, so introduce a > suitable hook. Permit such a hook to return both adjusted and un-adjusted > (for the page offset) pointers. > > Signed-off-by: Jan Beulich > --- > Declarations (or inline counterparts) aren't being moved around, to avoid > the need to touch source files using the functions. Quite possibly they > want to consistently go into xen/io.h and asm/io.h. > > Of course ioremap.c could also go into lib/. > > For RISC-V the wrappers likely should become inline functions? > > PPC doesn't reference any of the functions just yet, so gets only a > declaration. > > For Arm, a TODO item is deliberately retained, yet seeing the use of > ioremap_wc() in domain building (which by itself is questionable, see next > patch) I wonder if that's even feasible as long as we don't have > memremap() or alike. > > --- a/xen/arch/arm/include/asm/io.h > +++ b/xen/arch/arm/include/asm/io.h > @@ -1,6 +1,8 @@ > #ifndef _ASM_IO_H > #define _ASM_IO_H > > +#include > + > #if defined(CONFIG_ARM_32) > # include > #elif defined(CONFIG_ARM_64) > @@ -9,6 +11,16 @@ > # error "unknown ARM variant" > #endif > > +#ifdef CONFIG_MPU > +void __iomem *mpu_ioremap_attr(paddr_t start, size_t len, pte_attr_t flags); > +#define arch_ioremap_attr mpu_ioremap_attr > +#else > +/* > + * ioremap_attr() should only be used to remap device address ranges. > + * TODO: Add an arch hook to verify this assumption. > + */ > +#endif > + > #endif > /* > * Local variables: > --- a/xen/arch/arm/include/asm/mm.h > +++ b/xen/arch/arm/include/asm/mm.h > @@ -5,6 +5,7 @@ > #include > #include > #include > +#include > > #if defined(CONFIG_ARM_32) > # include > @@ -200,13 +201,12 @@ extern int prepare_secondary_mm(int cpu) > extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); > /* Helper function to setup memory management */ > void setup_mm_helper(void); > -/* map a physical range in virtual memory */ > -void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int attributes); > > static inline void __iomem *ioremap_nocache(paddr_t start, size_t len) > { > return ioremap_attr(start, len, PAGE_HYPERVISOR_NOCACHE); > } > +#define ioremap ioremap_nocache > > static inline void __iomem *ioremap_cache(paddr_t start, size_t len) > { > --- a/xen/arch/arm/mm.c > +++ b/xen/arch/arm/mm.c > @@ -455,11 +455,6 @@ unsigned long get_upper_mfn_bound(void) > return max_page - 1; > } > > -void *ioremap(paddr_t pa, size_t len) > -{ > - return ioremap_attr(pa, len, PAGE_HYPERVISOR_NOCACHE); > -} > - > /* > * Local variables: > * mode: C > --- a/xen/arch/arm/mmu/pt.c > +++ b/xen/arch/arm/mmu/pt.c > @@ -206,23 +206,6 @@ void clear_fixmap(unsigned int map) > BUG_ON(res != 0); > } > > -/* > - * This function should only be used to remap device address ranges > - * TODO: add a check to verify this assumption > - */ > -void *ioremap_attr(paddr_t start, size_t len, unsigned int attributes) > -{ > - mfn_t mfn = _mfn(PFN_DOWN(start)); > - unsigned int offs = start & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - void *ptr = __vmap(&mfn, nr, 1, 1, attributes, VMAP_DEFAULT); > - > - if ( ptr == NULL ) > - return NULL; > - > - return ptr + offs; > -} > - > static int create_xen_table(lpae_t *entry) > { > mfn_t mfn; > --- a/xen/arch/arm/mpu/mm.c > +++ b/xen/arch/arm/mpu/mm.c > @@ -9,6 +9,8 @@ > #include > #include > #include > + > +#include > #include > #include > #include > @@ -593,7 +595,7 @@ void free_init_memory(void) > spin_unlock(&xen_mpumap_lock); > } > > -void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags) > +void __iomem *mpu_ioremap_attr(paddr_t start, size_t len, pte_attr_t flags) > { > paddr_t start_pg = round_pgdown(start); > paddr_t end_pg = round_pgup(start_pg + len); > --- a/xen/arch/ppc/include/asm/io.h > +++ b/xen/arch/ppc/include/asm/io.h > @@ -13,4 +13,6 @@ > #define writew(v,c) ({ (void)(v); (void)(c); BUG_ON("unimplemented"); }) > #define writel(v,c) ({ (void)(v); (void)(c); BUG_ON("unimplemented"); }) > > +void __iomem *ioremap(paddr_t pa, size_t len); > + > #endif /* __ASM_PPC_IO_H__ */ > --- a/xen/arch/riscv/include/asm/io.h > +++ b/xen/arch/riscv/include/asm/io.h > @@ -41,6 +41,7 @@ > #include > #include > > +void __iomem *ioremap(paddr_t pa, size_t len); > void __iomem *ioremap_cache(paddr_t pa, size_t len); > void __iomem *ioremap_wc(paddr_t pa, size_t len); > > --- a/xen/arch/riscv/mm.c > +++ b/xen/arch/riscv/mm.c > @@ -587,20 +587,6 @@ void *__init arch_vmap_virt_end(void) > return (void *)(VMAP_VIRT_START + VMAP_VIRT_SIZE); > } > > -static void __iomem *ioremap_attr(paddr_t pa, size_t len, > - pte_attr_t attributes) > -{ > - mfn_t mfn = _mfn(PFN_DOWN(pa)); > - unsigned int offs = pa & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - void *ptr = __vmap(&mfn, nr, 1, 1, attributes, VMAP_DEFAULT); > - > - if ( ptr == NULL ) > - return NULL; > - > - return ptr + offs; > -} > - > void __iomem *ioremap_cache(paddr_t pa, size_t len) > { > return ioremap_attr(pa, len, PAGE_HYPERVISOR); > --- a/xen/arch/x86/include/asm/io.h > +++ b/xen/arch/x86/include/asm/io.h > @@ -47,6 +47,9 @@ __OUT(b,"b",char) > __OUT(w,"w",short) > __OUT(l,,int) > > +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr); > +#define arch_ioremap_attr x86_ioremap_attr > + > /* > * Boolean indicator and function used to handle platform specific I/O port > * emulation. > --- a/xen/arch/x86/include/asm/mm.h > +++ b/xen/arch/x86/include/asm/mm.h > @@ -611,7 +611,15 @@ void destroy_perdomain_mapping(struct do > unsigned int nr); > void free_perdomain_mappings(struct domain *d); > > -void __iomem *ioremap_wc(paddr_t pa, size_t len); > +static inline void __iomem *ioremap(paddr_t pa, size_t len) > +{ > + return ioremap_attr(pa, len, PAGE_HYPERVISOR_UCMINUS); > +} > + > +static inline void __iomem *ioremap_wc(paddr_t pa, size_t len) > +{ > + return ioremap_attr(pa, len, PAGE_HYPERVISOR_WC); > +} > > extern int memory_add(unsigned long spfn, unsigned long epfn, unsigned int pxm); > > --- a/xen/arch/x86/mm.c > +++ b/xen/arch/x86/mm.c > @@ -6166,41 +6166,15 @@ void *__init arch_vmap_virt_end(void) > return fix_to_virt(__end_of_fixed_addresses); > } > > -void __iomem *ioremap(paddr_t pa, size_t len) > +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > { > - mfn_t mfn = _mfn(PFN_DOWN(pa)); > - void *va; > - > - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > + WARN_ON(page_is_ram_type(PFN_DOWN(pa), RAM_TYPE_CONVENTIONAL)); > > /* The low first Mb is always mapped. */ > - if ( !((pa + len - 1) >> 20) ) > - va = __va(pa); > - else > - { > - unsigned int offs = pa & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - > - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_UCMINUS, VMAP_DEFAULT); > - if ( va ) > - va += offs; > - } > - > - return (void __force __iomem *)va; > -} > - > -void __iomem *__init ioremap_wc(paddr_t pa, size_t len) > -{ > - mfn_t mfn = _mfn(PFN_DOWN(pa)); > - unsigned int offs = pa & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - void *va; > - > - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > - > - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_WC, VMAP_DEFAULT); > + if ( !((pa + len - 1) >> 20) && attr == PAGE_HYPERVISOR_UCMINUS ) > + return (void __force __iomem *)__va(pa); > > - return (void __force __iomem *)(va ? va + offs : NULL); > + return NULL; > } > > int create_perdomain_mapping(struct domain *d, unsigned long va, > --- a/xen/common/Makefile > +++ b/xen/common/Makefile > @@ -19,6 +19,7 @@ obj-$(CONFIG_GRANT_TABLE) += grant_table > obj-y += guestcopy.o > obj-y += gzip/ > obj-$(CONFIG_HYPFS) += hypfs.o > +obj-y += ioremap.o > obj-$(CONFIG_IOREQ_SERVER) += ioreq.o > obj-y += irq.o > obj-y += kernel.o > --- /dev/null > +++ b/xen/common/ioremap.c > @@ -0,0 +1,42 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > + > +#include > + > +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > +{ > + void __iomem *ptr = NULL; > + unsigned int offs = PAGE_OFFSET(pa); > + > +#ifdef arch_ioremap_attr > + ptr = arch_ioremap_attr(pa, len, attr); I made an observation reviewing this patch. TL;DR: Nothing wrong with this patch For Arm MPU, callers now receive a sub-page-offset-adjusted pointer instead of a page-aligned one. mpu_ioremap_attr computes end_pg = round_pgup(start_pg + len) instead of round_pgup(start + len). Before, this was masked because the returned pointer was page-aligned, so callers effectively started from the page base. Now that the sub-page offset is correctly applied to the returned pointer, a caller using a non-page-aligned start with a len that crosses a page boundary would access memory from a different region. I need to send a fix for MPU. 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This is a scalability bottleneck so to avoid that: 1. Remove the global lock. 2. Make call_data_struct per-CPU. 3. Track which CPUs are currently running on_selected_cpus() using a global CPU mask. This tells CPUs running the interrupt which per-CPU call_data_structs to look at. Since the call data is now per-CPU, skip waiting for CPUs to "check in" for async calls. Instead, delay it until the next time on_selected_cpus() is called by which point there should be nothing to wait for. Signed-off-by: Ross Lagerwall --- xen/common/smp.c | 101 +++++++++++++++++++++++++++++++---------------- 1 file changed, 66 insertions(+), 35 deletions(-) diff --git a/xen/common/smp.c b/xen/common/smp.c index a011f541f1ea..e592e8453fb3 100644 --- a/xen/common/smp.c +++ b/xen/common/smp.c @@ -24,13 +24,15 @@ /* * Structure and data for smp_call_function()/on_selected_cpus(). */ -static DEFINE_SPINLOCK(call_lock); -static struct call_data_struct { +struct call_data_struct { void (*func) (void *info); void *info; int wait; - cpumask_t selected; -} call_data; + cpumask_t selected __cacheline_aligned; +}; + +DEFINE_PER_CPU(struct call_data_struct, call_data); +static cpumask_t tasks; void smp_call_function( void (*func) (void *info), @@ -50,55 +52,84 @@ void on_selected_cpus( void *info, int wait) { + struct call_data_struct *data; + unsigned int cpu = smp_processor_id(); + ASSERT(local_irq_is_enabled()); ASSERT(cpumask_subset(selected, &cpu_online_map)); - spin_lock(&call_lock); + if ( cpumask_empty(selected) ) + return; + + data = &this_cpu(call_data); - cpumask_copy(&call_data.selected, selected); + if ( !data->wait ) + { + /* Wait for any previous async call to complete */ + while ( !cpumask_empty(&data->selected) ) + cpu_relax(); + + cpumask_clear_cpu(cpu, &tasks); + } - if ( cpumask_empty(&call_data.selected) ) - goto out; + data->func = func; + data->info = info; + data->wait = wait; - call_data.func = func; - call_data.info = info; - call_data.wait = wait; + smp_wmb(); - smp_send_call_function_mask(&call_data.selected); + cpumask_copy(&data->selected, selected); - while ( !cpumask_empty(&call_data.selected) ) - cpu_relax(); + cpumask_set_cpu(cpu, &tasks); -out: - spin_unlock(&call_lock); + smp_send_call_function_mask(&data->selected); + + if ( wait ) + { + while ( !cpumask_empty(&data->selected) ) + cpu_relax(); + + cpumask_clear_cpu(cpu, &tasks); + } } void smp_call_function_interrupt(void) { - void (*func)(void *info) = call_data.func; - void *info = call_data.info; unsigned int cpu = smp_processor_id(); - - if ( !cpumask_test_cpu(cpu, &call_data.selected) ) - return; + unsigned int i; + struct call_data_struct *data; + void (*func)(void *info); + void *info; irq_enter(); - if ( unlikely(!func) ) - { - cpumask_clear_cpu(cpu, &call_data.selected); - } - else if ( call_data.wait ) - { - (*func)(info); - smp_mb(); - cpumask_clear_cpu(cpu, &call_data.selected); - } - else + for_each_cpu ( i, &tasks ) { - smp_mb(); - cpumask_clear_cpu(cpu, &call_data.selected); - (*func)(info); + data = &per_cpu(call_data, i); + + if ( !cpumask_test_cpu(cpu, &data->selected) ) + continue; + + smp_rmb(); + func = data->func; + info = data->info; + + if ( unlikely(!func) ) + { + cpumask_clear_cpu(cpu, &data->selected); + } + else if ( data->wait ) + { + (*func)(info); + smp_mb(); + cpumask_clear_cpu(cpu, &data->selected); + } + else + { + smp_mb(); + cpumask_clear_cpu(cpu, &data->selected); + (*func)(info); + } } irq_exit(); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 16:36:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 16:36:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270700.1559274 (Exim 4.92) (envelope-from ) id 1w7yXe-0007Uz-Fv; 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We have observed that the TLB flush lock can be a point of contention for certain workloads, e.g. migrating 10 VMs off a host during a host evacuation. Performance numbers: I wrote a synthetic benchmark to measure the performance. The benchmark has one or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in the selected mask. The executed function simply delays for 500 microseconds. The table below shows the % change in execution time of on_selected_cpus(): 1 thread 2 threads 4 threads 1 CPU in mask 0.02 -35.23 -51.18 2 CPUs in mask 0.01 -47.20 -69.27 4 CPUs in mask -0.02 -42.40 -66.55 8 CPUs in mask -0.03 -47.82 -68.39 16 CPUs in mask 0.12 -41.95 -58.26 32 CPUs in mask 0.02 -25.43 -39.35 64 CPUs in mask 0.00 -24.70 -37.83 With 1 thread (i.e. no contention), there is no regression in execution time. With multiple threads, as expected there is a significant improvement in execution time. As a more practical benchmark to simulate host evacuation, I measured the memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, so without PML). The rate increased by 16% with this patch series, even after the recent deferred TLB flush changes. FWIW, my first attempt at this was to port the SMP call functionality from Linux. I found it didn't scale well as the number of CPUs in the mask increases so I've taken a different approach here. Thanks, Ross Ross Lagerwall (3): x86/hap: Wait for remote CPUs during TLB flush xen/smp: Rewrite on_selected_cpus() to be lockless x86/smp: Rewrite TLB flush using on_selected_cpus() tools/xentrace/xenalyze.c | 2 - xen/arch/x86/include/asm/irq-vectors.h | 1 - xen/arch/x86/include/asm/irq.h | 1 - xen/arch/x86/mm/hap/hap.c | 2 +- xen/arch/x86/smp.c | 30 ++++---- xen/arch/x86/smpboot.c | 1 - xen/common/smp.c | 101 ++++++++++++++++--------- 7 files changed, 80 insertions(+), 58 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 16:36:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 16:36:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270701.1559282 (Exim 4.92) (envelope-from ) id 1w7yXh-0007iX-On; Wed, 01 Apr 2026 16:35:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270701.1559282; Wed, 01 Apr 2026 16:35:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w7yXh-0007iQ-Lf; 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Adjust the call here to retain the existing behaviour so it continues to wait for the remote CPUs to VMExit. Signed-off-by: Ross Lagerwall --- xen/arch/x86/mm/hap/hap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5d3..fb48e470bbf5 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -763,7 +763,7 @@ static bool cf_check flush_tlb(const unsigned long *vcpu_bitmap) * not currently running will already be flushed when scheduled because of * the ASID tickle done in the loop above. */ - on_selected_cpus(mask, NULL, NULL, 0); + on_selected_cpus(mask, NULL, NULL, 1); return true; } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 16:36:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 16:36:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270704.1559299 (Exim 4.92) (envelope-from ) id 1w7yXn-0008CE-70; Wed, 01 Apr 2026 16:35:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270704.1559299; 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This improves performance by allowing TLB flushes on behalf of different guests to happen at the same time. Signed-off-by: Ross Lagerwall --- tools/xentrace/xenalyze.c | 2 -- xen/arch/x86/include/asm/irq-vectors.h | 1 - xen/arch/x86/include/asm/irq.h | 1 - xen/arch/x86/smp.c | 30 +++++++++++--------------- xen/arch/x86/smpboot.c | 1 - 5 files changed, 13 insertions(+), 22 deletions(-) diff --git a/tools/xentrace/xenalyze.c b/tools/xentrace/xenalyze.c index 876d59d42ca5..a32f5f378a84 100644 --- a/tools/xentrace/xenalyze.c +++ b/tools/xentrace/xenalyze.c @@ -866,7 +866,6 @@ const char * hvm_svm_exit_reason_name[HVM_SVM_EXIT_REASON_MAX] = { /* General hvm information */ #define SPURIOUS_APIC_VECTOR 0xff #define ERROR_APIC_VECTOR 0xfe -#define INVALIDATE_TLB_VECTOR 0xfd #define EVENT_CHECK_VECTOR 0xfc #define CALL_FUNCTION_VECTOR 0xfb #define THERMAL_APIC_VECTOR 0xfa @@ -878,7 +877,6 @@ const char * hvm_svm_exit_reason_name[HVM_SVM_EXIT_REASON_MAX] = { const char * hvm_extint_vector_name[EXTERNAL_INTERRUPT_MAX] = { [SPURIOUS_APIC_VECTOR] = "SPURIOS_APIC", [ERROR_APIC_VECTOR] = "ERROR_APIC", - [INVALIDATE_TLB_VECTOR]= "INVALIDATE_TLB", [EVENT_CHECK_VECTOR]= "EVENT_CHECK", [CALL_FUNCTION_VECTOR]= "CALL_FUNCTION", [THERMAL_APIC_VECTOR]= "THERMAL_APIC", diff --git a/xen/arch/x86/include/asm/irq-vectors.h b/xen/arch/x86/include/asm/irq-vectors.h index d75d1c56716a..a1eb160d500b 100644 --- a/xen/arch/x86/include/asm/irq-vectors.h +++ b/xen/arch/x86/include/asm/irq-vectors.h @@ -4,7 +4,6 @@ /* Processor-initiated interrupts are all high priority. */ #define SPURIOUS_APIC_VECTOR 0xff #define ERROR_APIC_VECTOR 0xfe -#define INVALIDATE_TLB_VECTOR 0xfd #define EVENT_CHECK_VECTOR 0xfc #define CALL_FUNCTION_VECTOR 0xfb #define LOCAL_TIMER_VECTOR 0xfa diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h index 7315150b66b4..57cf2f23eb8d 100644 --- a/xen/arch/x86/include/asm/irq.h +++ b/xen/arch/x86/include/asm/irq.h @@ -111,7 +111,6 @@ extern int opt_irq_vector_map; #define platform_legacy_irq(irq) ((irq) < NR_ISA_IRQS) void cf_check event_check_interrupt(void); -void cf_check invalidate_interrupt(void); void cf_check call_function_interrupt(void); void cf_check irq_move_cleanup_interrupt(void); diff --git a/xen/arch/x86/smp.c b/xen/arch/x86/smp.c index 7936294f5fcd..a2a9abbb2f4e 100644 --- a/xen/arch/x86/smp.c +++ b/xen/arch/x86/smp.c @@ -242,21 +242,20 @@ void cf_check send_IPI_mask_phys(const cpumask_t *mask, int vector) local_irq_restore(flags); } -static DEFINE_SPINLOCK(flush_lock); -static cpumask_t flush_cpumask; -static const void *flush_va; -static unsigned int flush_flags; +struct flush_data { + const void *va; + unsigned int flags; +}; -void cf_check invalidate_interrupt(void) +static void cf_check invalidate_cb(void *info) { - unsigned int flags = flush_flags; - ack_APIC_irq(); - perfc_incr(ipis); + struct flush_data *data = info; + unsigned int flags = data->flags; + if ( (flags & FLUSH_VCPU_STATE) && __sync_local_execstate() ) flags &= ~(FLUSH_TLB | FLUSH_TLB_GLOBAL | FLUSH_ROOT_PGTBL); if ( flags & ~(FLUSH_VCPU_STATE | FLUSH_ORDER_MASK) ) - flush_area_local(flush_va, flags); - cpumask_clear_cpu(smp_processor_id(), &flush_cpumask); + flush_area_local(data->va, flags); } void flush_area_mask(const cpumask_t *mask, const void *va, unsigned int flags) @@ -275,21 +274,18 @@ void flush_area_mask(const cpumask_t *mask, const void *va, unsigned int flags) if ( (flags & ~FLUSH_ORDER_MASK) && !cpumask_subset(mask, cpumask_of(cpu)) ) { + cpumask_t flush_cpumask; + struct flush_data data = { .va = va, .flags = flags }; + if ( cpu_has_hypervisor && !(flags & ~(FLUSH_TLB | FLUSH_TLB_GLOBAL | FLUSH_VA_VALID | FLUSH_ORDER_MASK)) && !hypervisor_flush_tlb(mask, va, flags) ) return; - spin_lock(&flush_lock); cpumask_and(&flush_cpumask, mask, &cpu_online_map); cpumask_clear_cpu(cpu, &flush_cpumask); - flush_va = va; - flush_flags = flags; - send_IPI_mask(&flush_cpumask, INVALIDATE_TLB_VECTOR); - while ( !cpumask_empty(&flush_cpumask) ) - cpu_relax(); - spin_unlock(&flush_lock); + on_selected_cpus(&flush_cpumask, invalidate_cb, &data, 1); } } diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 491cbbba33ae..51e6982a1d25 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -1482,6 +1482,5 @@ void __init smp_intr_init(void) /* Direct IPI vectors. */ set_direct_apic_vector(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt); set_direct_apic_vector(EVENT_CHECK_VECTOR, event_check_interrupt); - set_direct_apic_vector(INVALIDATE_TLB_VECTOR, invalidate_interrupt); set_direct_apic_vector(CALL_FUNCTION_VECTOR, call_function_interrupt); } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 01 17:36:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 01 Apr 2026 17:36:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270772.1559309 (Exim 4.92) (envelope-from ) id 1w7zUf-0001KK-ML; Wed, 01 Apr 2026 17:36:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270772.1559309; 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bh=HFjfwUNpk83YJkSRCUxCCTTOgWj5hI8q0tnVjaEpeOY=; b=tGVwmg2nSmfkWisRDUFBFlOvX4EIIgCfl8FtVZeKgzoQYwR4XEzsOzSdGvBZ2t0U3D12iP n9H+mKH7m3loZ7IWUQ1TPMFUzYmmmO6Jo6OhvmwrBt6M0enpq2uDhmdnO3EGCC0F28hH9o QhPURW5W2dBDzCm+vRTWoZS128svGq8= Message-ID: <528bb66e-3eb6-41c7-a33c-43811c8f1afc@ariadne.space> Date: Wed, 1 Apr 2026 10:36:26 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] CI: use Alpine's network setup To: xen-devel@lists.xenproject.org References: <2a02d9e9a4fc47674d771f22e65b202b3dbf6336.1774999414.git-series.marmarek@invisiblethingslab.com> Content-Language: en-US From: Ariadne Conill In-Reply-To: <2a02d9e9a4fc47674d771f22e65b202b3dbf6336.1774999414.git-series.marmarek@invisiblethingslab.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1775064998-BF1480B1-C2B180D2/0/0 X-purgate-type: clean X-purgate-size: 1343 Hi, On 3/31/26 16:24, Marek Marczykowski-Górecki wrote: > This allows Alpine startup script to properly handle service > dependencies - necessary for starting dropbear ssh server. > For the latter, always take the IP address from DHCP, in addition to the > test-local one. > > Signed-off-by: Marek Marczykowski-Górecki > Acked-by: Stefano Stabellini > --- > automation/scripts/qubes-x86-64.sh | 20 +++++++++----------- > 1 file changed, 9 insertions(+), 11 deletions(-) > > diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qubes-x86-64.sh > index 7a59fa5f1116..91c0d5bec829 100755 > --- a/automation/scripts/qubes-x86-64.sh > +++ b/automation/scripts/qubes-x86-64.sh > @@ -214,25 +214,23 @@ cat "${dom0_rootfs_parts[@]}" > binaries/dom0-rootfs.cpio.gz > # test-local configuration > mkdir -p rootfs > cd rootfs > -mkdir -p boot etc/local.d root > +mkdir -p boot etc/local.d root etc/network > cp -a ../automation/scripts/run-tools-tests root/ > > +echo " > +auto xenbr0 > +iface xenbr0 inet dhcp > + bridge-ports eth0 > + bridge-stp 0 > + up ip a a 192.168.0.1/24 dev \$IFACE Why not "address 192.168.0.1/24" here?  The DHCP client will still get run.  You can verify with ifquery(8). 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Q+ZQMjZQ5VOSBjNe" Content-Disposition: inline In-Reply-To: <6020226f-5e38-42f5-923e-2692d17bc4e9@suse.com> X-purgate-ID: tlsNG-c201ff/1775075415-3252396F-5A6CF06A/0/0 X-purgate-type: clean X-purgate-size: 13805 --Q+ZQMjZQ5VOSBjNe Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 1 Apr 2026 22:30:10 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: Andrew Cooper , xen-devel Subject: Re: IOMMU faults after S3 On Wed, Apr 01, 2026 at 10:11:12AM +0200, Jan Beulich wrote: > On 01.04.2026 09:20, Andrew Cooper wrote: > > On 01/04/2026 9:14 am, Jan Beulich wrote: > >> On 27.03.2026 11:19, Marek Marczykowski-G=C3=B3recki wrote: > >>> I noticed that on some systems, there are a lot of IOMMU faults after > >>> S3. I can see it also on a laptop with MTL, but it affects also the A= DL > >>> gitlab runner: > >>> > >>> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 > >>> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:= 00:1e.6] fault addr 0 > >>> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in conte= xt entry is clear > >>> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:= 00:1e.6] fault addr 0 > >>> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in conte= xt entry is clear > >>> > >>> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. > >>> > >>> The issue is present only on staging, not staging-4.21. > >>> > >>> Bisect says: > >>> > >>> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit > >>> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b > >>> Author: Jan Beulich > >>> Date: Thu Jan 22 14:13:35 2026 +0100 > >>> > >>> x86/HPET: drop .set_affinity hook > >> Looking into this, I find several things I can't quite understand (yet= ). > >> First there is > >> > >> (XEN) [000000456c0fe39f] Disabling HPET for being unreliable > >> > >> which looks to only affect clocksource selection, but not use as > >> broadcast source for CPU-idle management. (This may be an independent > >> issue.) > >> > >> Then there is > >> > >> (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) > >> > >> which should only occur on ARAT-incapable systems. That should only be > >> older hardware. > >=20 > > I'm not sure that's a reasonable assertion to draw.=C2=A0 The number of= HPET > > channels is down to the HPET alone, not anything to do with the CPU > > capabilities. >=20 > My statement was about the mere presence of that message, not the number > of channels that are reported. >=20 > >> (On my much older Skylake I don't see this line, for > >> example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid > >> is purely featureset based, and hence doesn't expose info about that > >> leaf. > >=20 > > xen-cpuid -p > >=20 > > That will get you leaf 6, but there's no human-readable decode of it. >=20 > Raw numbers is good enough here. How did I miss that option when looking > at --help output? Oh, simply because it isn't shown there. >=20 > Marek, that'll be better than bare metal kernel data, as it gives us both > raw and host policies. Here is the output from ADL runner: Xen reports there are maximum 120 leaves and 2 MSRs Raw policy: 48 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 00000020:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:77fafbff:bfebfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000005:ffffffff -> 00000040:00000040:00000003:10102020 00000006:ffffffff -> 00df8ff7:00000002:00000409:00000003 00000007:00000000 -> 00000002:239c27eb:98c027ac:fc1cc410 00000007:00000001 -> 00400810:00000000:00000000:00040000 00000007:00000002 -> 00000000:00000000:00000000:00000017 0000000a:ffffffff -> 07300605:00000000:00000007:00008603 0000000b:00000000 -> 00000001:00000002:00000100:00000000 0000000b:00000001 -> 00000007:00000010:00000201:00000000 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00019900:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000008 -> 00000080:00000000:00000001:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 0000000d:0000000b -> 00000010:00000000:00000001:00000000 0000000d:0000000c -> 00000018:00000000:00000001:00000000 0000000d:0000000f -> 00000328:00000000:00000001:00000000 0000000d:00000010 -> 00000008:00000000:00000001:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 000000001488fd6b Host policy: 41 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:77fafbff:bfebfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000005:ffffffff -> 00000040:00000040:00000003:10102020 00000006:ffffffff -> 00df8ff7:00000002:00000409:00000003 00000007:00000000 -> 00000002:239c27eb:984027ac:fc1cc410 00000007:00000001 -> 00000810:00000000:00000000:00040000 00000007:00000002 -> 00000000:00000000:00000000:00000017 0000000b:00000000 -> 00000001:00000002:00000100:00000000 0000000b:00000001 -> 00000007:00000010:00000201:00000000 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000001488fd6b PV Max policy: 58 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:f6f83203:1fc9cbf5 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000007:00000000 -> 00000002:218c0329:18400700:ac004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000001 0000000d:00000000 -> 00000007:00000000:00000340:00000000 0000000d:00000001 -> 00000007:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 80000000:ffffffff -> 80000021:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000123:28100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00001000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 40000000140ae167 HVM Max policy: 65 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:f7fa3223:1fcbfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000007:00000000 -> 00000002:219c07ab:9840070c:bc004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000017 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000021:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000123:2c100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00101000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 40000000140ae167 PV Default policy: 33 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:f6d83203:1fc9cbf5 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000007:00000000 -> 00000002:218c0329:00400700:ac004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000001 0000000d:00000000 -> 00000007:00000000:00000340:00000000 0000000d:00000001 -> 00000007:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:28100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000008:ffffffff -> 0000302e:00001000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000001408e163 HVM Default policy: 40 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 00090672:00800800:f7fa3203:1fcbfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 00000007:00000000 -> 00000002:219c07ab:8040070c:bc004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000017 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 80000006:ffffffff -> 00000000:00000000:05007040:00000000 80000008:ffffffff -> 0000302e:00101000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000001408e163 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --Q+ZQMjZQ5VOSBjNe Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnNgFIACgkQ24/THMrX 1yzIcwf/YF3i17KCsGAt5e7sC+ztxTW6zyo+LhMELsKV/ujAS6OGzleYfsBsw7lr d5C//jAoMgBJhv4q4M99T2rOK06m6Y6hU9mfSNyxx8rw0q02+PpYURfLuKE+BbGI cUI06lvqYQUrfeqY9cuODbDi8tG2EmL4zvucAjamu9PewRu9I8OuJddlZCaZHSSg RcTpGe1Cr413Oiupu0rEbg3nvsU3yyYlitnpBtfG2gnRnQ/XQuanVu+Ny9qfmjOU RwtrJIRYEXQ+v5Vh4MMTiDcOAOeihXY1rqYsNFExnwR9MLEGL+mDs0VCVgnfM2SM KMi0lyXL42NO9dlDWYVzkkYjMmN4uw== =dQVe -----END PGP SIGNATURE----- --Q+ZQMjZQ5VOSBjNe-- From xen-devel-bounces@lists.xenproject.org Wed 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=?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 Message-ID: References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="C5W4Ug/2V60Qa5F1" Content-Disposition: inline In-Reply-To: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> X-purgate-ID: tlsNG-16d1c6/1775085453-6464A3D8-9E5424A5/0/0 X-purgate-type: clean X-purgate-size: 9143 --C5W4Ug/2V60Qa5F1 Content-Type: multipart/mixed; protected-headers=v1; boundary="ArA7zpzUrS2vfZ23" Content-Disposition: inline Date: Thu, 2 Apr 2026 01:17:29 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 --ArA7zpzUrS2vfZ23 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 01, 2026 at 10:52:37AM +0200, Jan Beulich wrote: > On 01.04.2026 09:14, Jan Beulich wrote: > > On 27.03.2026 11:19, Marek Marczykowski-G=C3=B3recki wrote: > >> I noticed that on some systems, there are a lot of IOMMU faults after > >> S3. I can see it also on a laptop with MTL, but it affects also the ADL > >> gitlab runner: > >> > >> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 > >> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:0= 0:1e.6] fault addr 0 > >> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in contex= t entry is clear > >> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:0= 0:1e.6] fault addr 0 > >> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in contex= t entry is clear > >> > >> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. > >> > >> The issue is present only on staging, not staging-4.21. > >> > >> Bisect says: > >> > >> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit > >> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b > >> Author: Jan Beulich > >> Date: Thu Jan 22 14:13:35 2026 +0100 > >> > >> x86/HPET: drop .set_affinity hook > >=20 > > Looking into this, I find several things I can't quite understand (yet). > > First there is > >=20 > > (XEN) [000000456c0fe39f] Disabling HPET for being unreliable > >=20 > > which looks to only affect clocksource selection, but not use as > > broadcast source for CPU-idle management. (This may be an independent > > issue.) > >=20 > > Then there is > >=20 > > (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) > >=20 > > which should only occur on ARAT-incapable systems. That should only be > > older hardware. (On my much older Skylake I don't see this line, for > > example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid > > is purely featureset based, and hence doesn't expose info about that > > leaf. The leaf also isn't exposed to domains, so CPUID output in Dom0 > > isn't useful to look at either. It would need to be CPUID output on a > > bare metal kernel. > >=20 > > Further I suspect the fingered commit may only have uncovered an issue > > elsewhere. I don't think we clear any context table entries during > > suspend or resume. Hence in > >=20 > > (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.= 6] fault addr 0 > > (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context ent= ry is clear > >=20 > > the latter message is confusing me. > >=20 > > The fault address being zero may, otoh, be a hint of hpet_msi_write() > > never having run post-resume. Which may be the connection to the > > dropping of hpet_msi_set_affinity(), as that did call that function. >=20 > There clearly is an issue with the handling of the max_cstate variable, > but I expect you don't use xenpm to limit usable C-states (there clearly > is no respective command line option in the log you referenced)? No, I don't think so. > From what the log has, I conclude hpet_broadcast_resume() is called. I don't think so... I applied changes as attached and got this on resume: (XEN) [ 69.486120] Enabling non-boot CPUs ... (XEN) [ 69.486404] mwait-idle: state C1 is disabled (XEN) [ 69.587869] mwait-idle: state C1 is disabled (XEN) [ 69.588008] mwait-idle: state C1 is disabled (XEN) [ 69.689438] mwait-idle: state C1 is disabled (XEN) [ 69.689608] mwait-idle: state C1 is disabled (XEN) [ 69.791066] mwait-idle: state C1 is disabled (XEN) [ 69.791334] mwait-idle: state C1 is disabled (XEN) [ 69.892938] mwait-idle: state C1 is disabled (XEN) [ 69.893209] mwait-idle: state C1 is disabled (XEN) [ 69.994890] mwait-idle: state C1 is disabled (XEN) [ 69.995096] mwait-idle: state C1 is disabled (XEN) [ 70.096638] mwait-idle: state C1 is disabled (XEN) [ 70.096915] mwait-idle: state C1 is disabled (XEN) [ 70.097093] mwait-idle: state C1 is disabled (XEN) [ 70.097272] mwait-idle: state C1 is disabled (XEN) [ 70.203357] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] f= ault addr 0 (XEN) [ 70.203363] [VT-D]DMAR: reason 02 - Present bit in context entry i= s clear > Question is whether it does what we want it to. Could you instrument it > some, so we have confirmation that it is called, and we also know whether > __hpet_setup_msi_irq() is not only called on all 8 channels, but also > succeeds there? (If it failed, I suppose we better wouldn't set > HPET_TN_FSB and/or HPET_TN_ENABLE.) If, however, it succeeds, I couldn't > explain why the fault address would be reported as 0, as then we > definitely must have written HPET_Tn_ROUTE. >=20 > Jan --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --ArA7zpzUrS2vfZ23 Content-Type: text/plain; charset=utf-8 Content-Disposition: attachment; filename=xen-debug.diff Content-Transfer-Encoding: quoted-printable diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c index 1ea8ae457424..4c5bf079b728 100644 --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -658,6 +658,8 @@ void hpet_broadcast_resume(void) u32 cfg; unsigned int i, n; =20 + printk("%s:%d: hpet_events: %p\n", __func__, __LINE__, hpet_events); + if ( !hpet_events ) return; =20 @@ -667,23 +669,30 @@ void hpet_broadcast_resume(void) =20 if ( num_hpets_used > 0 ) { + printk("%s:%d: num_hpets_used: %d\n", __func__, __LINE__, num_hpet= s_used); /* Stop HPET legacy interrupts */ cfg &=3D ~HPET_CFG_LEGACY; n =3D num_hpets_used; } else if ( hpet_events->flags & HPET_EVT_DISABLE ) + { + printk("%s:%d: hpet_events->flags: %#x\n", __func__, __LINE__, hpe= t_events->flags); return; + } else { /* Start HPET legacy interrupts */ + printk("%s:%d\n", __func__, __LINE__); cfg |=3D HPET_CFG_LEGACY; n =3D 1; } =20 + printk("%s:%d: cfg: %#x\n", __func__, __LINE__, cfg); hpet_write32(cfg, HPET_CFG); =20 for ( i =3D 0; i < n; i++ ) { + printk("%s:%d: i:%d, hpet_events[i].msi.irq: %d, hpet_events[i].fl= ags: %#x\n", __func__, __LINE__, i, hpet_events[i].msi.irq, hpet_events[i].= flags); if ( hpet_events[i].msi.irq >=3D 0 ) __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); =20 @@ -694,6 +703,7 @@ void hpet_broadcast_resume(void) if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) cfg |=3D HPET_TN_FSB; hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); + printk("%s:%d: i:%d, cfg: %#x\n", __func__, __LINE__, i, cfg); =20 hpet_events[i].next_event =3D STIME_MAX; } diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index fed30a919d2c..15113ebdfb6c 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2646,6 +2646,7 @@ static int _disable_pit_irq(bool init) { int ret =3D 1; =20 + printk("%s:%d: using_pit: %d, cpu_has_apic: %d\n", __func__, __LINE__,= using_pit, cpu_has_apic); if ( using_pit || !cpu_has_apic ) return -1; =20 @@ -2655,8 +2656,10 @@ static int _disable_pit_irq(bool init) * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast. */ + printk("%s:%d: cpuidle_using_deep_cstate: %d, boot_cpu_has(X86_FEATURE= _XEN_ARAT): %d\n", __func__, __LINE__, cpuidle_using_deep_cstate(), boot_cp= u_has(X86_FEATURE_XEN_ARAT)); if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT= ) ) { + printk("%s:%d: init: %d\n", __func__, __LINE__, init); init ? hpet_broadcast_init() : hpet_broadcast_resume(); if ( !hpet_broadcast_is_available() ) { --ArA7zpzUrS2vfZ23-- --C5W4Ug/2V60Qa5F1 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnNp4kACgkQ24/THMrX 1ywHdAf8CsgOaRYooAk/aXo7Z4hncTLEcBBOwXYH419N+fqvycjl8MM+NPyQW8aS FbckFM6z/Q/nAKQ3bj+PvGEY/sADvKMrVvzYyY7kwMXMrWU+xgibJsX0hdP6RrU3 sS7uLPEzwfGBd70OKn+RtCZgWsKr8y1sRiMyXrkcW03gOm7i2cOoZfWLL4KSGPjU r86zyD7IhrKyCFwerhvBCKd4hheMPUGlmG0Z3LKPfqiJZmzyTBCgB0i1p/AZBS40 ctVa3BRKADhkhrP+nojy0Jz2LG1XVvB8ol7y/9cS+D55z5KhieILsIx7PUcMUwSW x73jvWolOGkoCD7uRIQbR1fN8EsPMg== =YQri -----END PGP SIGNATURE----- --C5W4Ug/2V60Qa5F1-- From xen-devel-bounces@lists.xenproject.org Thu Apr 02 02:31:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 02:31:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270964.1559336 (Exim 4.92) (envelope-from ) id 1w87pk-0004X6-6T; Thu, 02 Apr 2026 02:31:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270964.1559336; Thu, 02 Apr 2026 02:31:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w87pk-0004Wx-1b; Thu, 02 Apr 2026 02:31:00 +0000 Received: by outflank-mailman (input) for mailman id 1270964; Thu, 02 Apr 2026 02:30:58 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w87pi-0004Wr-UF for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 02:30:58 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1w87pi-005Z3a-25; Thu, 02 Apr 2026 02:30:58 +0000 Received: from [2001:268:9abd:66c7:b99f:63d7:98fa:3237] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1w87pi-00EOeS-0n; Thu, 02 Apr 2026 02:30:58 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=XNBeaCFJnRrOzCHOlR24NIMb8hWks2v97D7twN+FcCI=; b=zSe6pZOGM/HocuH/i49FXELydD ZT7rN1QxUXae4V7vGTVkhcO4NXOadMF8FWSCO9nig3xqTH7ZhkrE7bH9lxtg3eNqZuqN+qHweKOKD Gw8oeGi76QATzjBYM/M4o34ZV7vmG6IhIDEP6/slcyFTq4zzP1wDRXl+W3QUjK9KaOFo=; Message-ID: Date: Thu, 2 Apr 2026 03:30:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] xen/arm: acpi: Rename local acpi_size to avoid shadowing typedef Content-Language: en-GB To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260401145816.169557-1-michal.orzel@amd.com> <20260401145816.169557-2-michal.orzel@amd.com> From: Julien Grall In-Reply-To: <20260401145816.169557-2-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 01/04/2026 15:58, Michal Orzel wrote: > Rename the local variable acpi_size to acpi_len in > estimate_acpi_efi_size() to avoid shadowing the acpi_size typedef > from xen/include/acpi/actypes.h. We can't change actypes.h but I wish they were suffixing the types with _t. > > This resolves a MISRA C Rule 5.6 violation. > > Signed-off-by: Michal Orzel Acked-by: Julien Grall Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Thu Apr 02 02:32:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 02:32:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270972.1559345 (Exim 4.92) (envelope-from ) id 1w87rN-00051K-EQ; Thu, 02 Apr 2026 02:32:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1270972.1559345; Thu, 02 Apr 2026 02:32:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w87rN-00051D-BN; Thu, 02 Apr 2026 02:32:41 +0000 Received: by outflank-mailman (input) for mailman id 1270972; Thu, 02 Apr 2026 02:32:40 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w87rM-000515-RX for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 02:32:40 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1w87rM-005Z5t-25; Thu, 02 Apr 2026 02:32:40 +0000 Received: from [2001:268:9abd:66c7:b99f:63d7:98fa:3237] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1w87rM-00EOhr-1N; Thu, 02 Apr 2026 02:32:40 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=jk79Nf5qcm4Ba3ail7gIn9YqUlOCJh8bmnbe6pvjWUM=; b=gfMBch6uOjwqnK4jfPitlrzw/O e2wLIeTdkI1dTRtufTCALd8FbjEPuRqyrEIo1KWYvPk+3aohU2gs2PQXP6rT5p6XU0fUGkIUGdPNF Efk/7slVsW6JQhS2eb8sZg9rKKv59LJBz6yyOsEKnLLg86dzEyo3xr9XxLuWH/oEB7eU=; Message-ID: <021a8ae4-f29f-4eb9-9f62-25eae32b4ad6@xen.org> Date: Thu, 2 Apr 2026 11:32:30 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/arm: pci: Narrow scope of file-local symbols Content-Language: en-GB To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Mykyta Poturai References: <20260401145816.169557-1-michal.orzel@amd.com> <20260401145816.169557-3-michal.orzel@amd.com> From: Julien Grall In-Reply-To: <20260401145816.169557-3-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 01/04/2026 15:58, Michal Orzel wrote: > Make pci_alloc_host_bridge() and pci_add_host_bridge() in > pci-host-common.c, rcar4_pcie_ops and rcar4_pcie_child_ops in > pci-host-rcar4.c, and nwl_pcie_ops in pci-host-zynqmp.c static, as > they are only used within their respective translation units. > > Also include pci-host-rcar4.h in pci-host-rcar4.c so that the > declarations of its externally visible functions are visible at the > point of definition. > > This resolves MISRA C Rule 8.4 violations. > > Signed-off-by: Michal Orzel Acked-by: Julien Grall Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Thu Apr 02 02:44:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 02:44:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1270990.1559354 (Exim 4.92) (envelope-from ) id 1w882a-0006m0-G4; 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Thu, 02 Apr 2026 02:44:14 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=z0GW4RDS24EFGZmnCHWhCEF0cYKZ1yETgAEawsy0IjE=; b=l6esDJ0iIVUXBCJie4xRO/JGQv MefY3xQ6aYMCaAI7uVJZTi8MIxM9oX+OkZUX2Kh7lAhF3SabeqgrnCjA1wP4DCvnT5d8T3y/2JhV3 Lk4daPDv71Ju4TrH0MeIAivaDexQSAONWXOwTJlhmM4XCVXlbS52vx1RO97LKbuZXC5o=; Message-ID: Date: Thu, 2 Apr 2026 11:44:04 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] xen/arm: vpci: Move content of xen/arch/arm/vpci.h to arch header Content-Language: en-GB To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260401145816.169557-1-michal.orzel@amd.com> <20260401145816.169557-4-michal.orzel@amd.com> From: Julien Grall In-Reply-To: <20260401145816.169557-4-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 01/04/2026 15:58, Michal Orzel wrote: > Move domain_vpci_init() and domain_vpci_get_num_mmio_handlers() > declarations from the private xen/arch/arm/vpci.h into the public > xen/arch/arm/include/asm/vpci.h, and remove the now redundant > private header. Can you provide a brief explanation why we don't couldn't include "vpci.h" from "arch/arm/vpci.c"? Such approach would ... > > Update domain.c to include instead of the removed private > header. > > This ensures the declarations are visible where the functions are > defined, resolving a MISRA C Rule 8.4 violation. > > Signed-off-by: Michal Orzel > --- > I'm moving a file with GPL2+ license to a file with GPL2-only. I consider this > ok in this case becase the copyright on a file with just prototypes does not > make any sense and a license text was most likely blindly copy-pasted like for > most of the files in that era. ... avoid the licensing discussion. I am in the opinion that it is ok to move from GPLv2+ to GPLv2 because the license says "either version 2 of the License, or (at your option) any later version". But I remember not everyone agrees on this interpretation and we never solved the discussion on whether we need to request permission from the original copyright holder. Alternatively, I see this file was only modified by two companies (EPAM and Arm). I see one employee of each company are already CCed. So you could confirm with them if the change is fine. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Thu Apr 02 03:31:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 03:31:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271020.1559363 (Exim 4.92) (envelope-from ) id 1w88mO-0004oR-U3; Thu, 02 Apr 2026 03:31:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271020.1559363; Thu, 02 Apr 2026 03:31:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w88mO-0004oK-Qv; Thu, 02 Apr 2026 03:31:36 +0000 Received: by outflank-mailman (input) for mailman id 1271020; Thu, 02 Apr 2026 03:31:35 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w88mN-0004oE-4e for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 03:31:35 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1w88mM-005aBa-1q; Thu, 02 Apr 2026 03:31:34 +0000 Received: from [2001:268:9abd:66c7:b99f:63d7:98fa:3237] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1w88mL-00ERXg-0f; Thu, 02 Apr 2026 03:31:34 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=txgbhLlqWf03T/qCGMgtK8VOthSG10CY10iyPb0O4Os=; b=c6pfJbXuGOBqlEzcfUAT1H9FK0 knpzRG85M1sVJFuPX5C8tnf3vAlWv+HiPsBIZHTTPNun5piUfFEekjWaEOFSRrxMD3QmUexDKm5uq GZ6GCxV6FMtqCGiD85uOgG+Q6w93OHUttLnNMNtL0YNqDP9WBhyFqlSJ8gMfxdX8w1Hg=; Message-ID: <97c56309-1bbf-471b-88c4-d13af3867f95@xen.org> Date: Thu, 2 Apr 2026 12:31:22 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] make ioremap_wc() x86 only (for the time being) Content-Language: en-GB To: Oleksii Kurochko , Jan Beulich , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Anthony PERARD , Michal Orzel , Alistair Francis , Connor Davis , Bertrand Marquis References: <924f3ef2-7883-4322-a921-edc814c96719@suse.com> <20adacfa-06ce-4508-916d-f15d8f17788f@suse.com> <3bf90b33-c028-4f45-bda0-9d1bd5386c02@gmail.com> <6fa82fcc-d21d-476d-b020-fc40a645a74c@gmail.com> From: Julien Grall In-Reply-To: <6fa82fcc-d21d-476d-b020-fc40a645a74c@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Oleksii, On 30/03/2026 15:24, Oleksii Kurochko wrote: > > > On 3/30/26 4:22 PM, Oleksii Kurochko wrote: >> >> >> On 2/19/26 4:53 PM, Jan Beulich wrote: >>> Its use in domain building is questionable: Already at the point both >>> uses >>> were introduced, ioremap_cache() existed. I can't see why kernel and >>> initrd would need mapping WC, when at the same time other similar >>> mappings >>> (in common/device-tree/) are done WB. >>> >>> With those uses replaced, neither Arm nor RISC-V have a need for the >>> function anymore. >>> >> >> It is okay for RISC-V, but for Arm, IIRC, likely it was done because >> guest might start with cache disabled and PAGE_HYPERVISOR_WC on Arm >> uses "Normal Non-cacheable" what could lead to that guest won't see >> some part of kernel and/or initrd as it could be in a cache and won't >> be flushed to RAM. >> >> But probably I misremembered something and >> clean_and_invalidate_dcache_va_range() or something similar should be >> called before guest is laucned. > > okay, so for this case copy_to_guest_phys_flush_dcache() is called after > initrd and kernel are loaded. Looking at the code, we are using ioremap_wc() on the source side rather than the destination. So the use of copy_to_guest_phys_flush_cache() would not matter as this only applies to the destination. Regarding the source side, the cache only guarantees coherency when either: * the memory attributes are similar between the component that loaded it (most likely the firmware) and Xen * The component that loaded it issued a cache flush I saw Jan mentioned that other part of the device-tree code are using ioremap_cache(). They were adding afterwards and I can't remember why we consisder it was ok. For older mapping we would be switching from a non-cacheable mapping (HYPERVISOR_WC) to a cacheable one (HYPERVISOR). While I agree we should have some consistency in the mappings, I am a bit unease to change the attributes without any written details on why there will not be any impact. Can you share more details? I would also be ok if we decide to keep ioremap_wc() for arm as well. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Thu Apr 02 06:01:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 06:01:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271072.1559372 (Exim 4.92) (envelope-from ) id 1w8B6p-0006AT-5L; Thu, 02 Apr 2026 06:00:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271072.1559372; Thu, 02 Apr 2026 06:00:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8B6p-0006AM-2G; Thu, 02 Apr 2026 06:00:51 +0000 Received: by outflank-mailman (input) for mailman id 1271072; Thu, 02 Apr 2026 06:00:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8B6n-0006AG-EK for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 06:00:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8B6m-008rsg-IM for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:00:48 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce060d-e002-0a2a0a5209dd-0a2a45088202-8 for ; Thu, 02 Apr 2026 08:00:48 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce0610-fab6-0a2a45080019-d155dd32e0ea-3 for ; Thu, 02 Apr 2026 08:00:48 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43d0deb7ad5so451053f8f.2 for ; Wed, 01 Apr 2026 23:00:48 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <97c56309-1bbf-471b-88c4-d13af3867f95@xen.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775109648-75159497-32347FC1/0/0 X-purgate-type: clean X-purgate-size: 3282 On 02.04.2026 05:31, Julien Grall wrote: > Hi Oleksii, > > On 30/03/2026 15:24, Oleksii Kurochko wrote: >> >> >> On 3/30/26 4:22 PM, Oleksii Kurochko wrote: >>> >>> >>> On 2/19/26 4:53 PM, Jan Beulich wrote: >>>> Its use in domain building is questionable: Already at the point both >>>> uses >>>> were introduced, ioremap_cache() existed. I can't see why kernel and >>>> initrd would need mapping WC, when at the same time other similar >>>> mappings >>>> (in common/device-tree/) are done WB. >>>> >>>> With those uses replaced, neither Arm nor RISC-V have a need for the >>>> function anymore. >>>> >>> >>> It is okay for RISC-V, but for Arm, IIRC, likely it was done because >>> guest might start with cache disabled and PAGE_HYPERVISOR_WC on Arm >>> uses "Normal Non-cacheable" what could lead to that guest won't see >>> some part of kernel and/or initrd as it could be in a cache and won't >>> be flushed to RAM. >>> >>> But probably I misremembered something and >>> clean_and_invalidate_dcache_va_range() or something similar should be >>> called before guest is laucned. >> >> okay, so for this case copy_to_guest_phys_flush_dcache() is called after >> initrd and kernel are loaded. > > Looking at the code, we are using ioremap_wc() on the source side rather > than the destination. So the use of copy_to_guest_phys_flush_cache() > would not matter as this only applies to the destination. > > Regarding the source side, the cache only guarantees coherency when either: > * the memory attributes are similar between the component that loaded > it (most likely the firmware) and Xen > * The component that loaded it issued a cache flush > > I saw Jan mentioned that other part of the device-tree code are using > ioremap_cache(). They were adding afterwards and I can't remember why we > consisder it was ok. This sounds like you think it isn't okay. > For older mapping we would be switching from a > non-cacheable mapping (HYPERVISOR_WC) to a cacheable one (HYPERVISOR). Whereas this sounds like you think switching everything to WB (or whatever the correct term on Arm) would be okay. IOW - I'm confused, and hence I'm ... > While I agree we should have some consistency in the mappings, I am a > bit unease to change the attributes without any written details on why > there will not be any impact. ... also unclear as to whether this actually is an objection to the Arm part of the change (incl patch 1). Please clarify. As to written details: Mappings of ordinary RAM shouldn't need any extra documentation when done WB. Any non-standard mappings (like WC) should instead have comments. The absence of such comments indicates to me that at the time the "best thing thought to be available" was used, i.e. WC preferred over UC (which plain ioremap() would have used). Additionally, the use of ioremap_wc() from initrd_load() (not Arm-specific) pretty clearly isn't appropriate for RISC-V, aiui. That said, using ioremap*() for RAM feels bogus in the first place. At the time vmap() didn't exist yet, so it may have been appropriate. If there are reasons not to use it here, perhaps something like Linux'es memremap() should long have been introduced? Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 02 06:09:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 06:09:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271086.1559381 (Exim 4.92) (envelope-from ) id 1w8BF1-0006nO-UI; Thu, 02 Apr 2026 06:09:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271086.1559381; Thu, 02 Apr 2026 06:09:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BF1-0006nH-Qb; Thu, 02 Apr 2026 06:09:19 +0000 Received: by outflank-mailman (input) for mailman id 1271086; Thu, 02 Apr 2026 06:09:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BF1-0006nB-51 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 06:09:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8BF0-008t0F-Hl for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:09:18 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce0806-5cb7-0a2a0a5109dd-0a2a450aea0e-18 for ; Thu, 02 Apr 2026 08:09:18 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce080e-ee98-0a2a450a0019-d155802bb881-3 for ; Thu, 02 Apr 2026 08:09:18 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-48891776099so2070785e9.2 for ; Wed, 01 Apr 2026 23:09:18 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775110158-BE1500B1-E009B9EE/0/0 X-purgate-type: clean X-purgate-size: 2028 On 01.04.2026 18:35, Ross Lagerwall wrote: > Hi, > > This series implements lockless SMP function call and then rewrites x86 TLB > flushing to use SMP function calls. > > We have observed that the TLB flush lock can be a point of contention for > certain workloads, e.g. migrating 10 VMs off a host during a host evacuation. > > Performance numbers: > > I wrote a synthetic benchmark to measure the performance. The benchmark has one > or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in > the selected mask. The executed function simply delays for 500 microseconds. > > The table below shows the % change in execution time of on_selected_cpus(): > > 1 thread 2 threads 4 threads > 1 CPU in mask 0.02 -35.23 -51.18 > 2 CPUs in mask 0.01 -47.20 -69.27 > 4 CPUs in mask -0.02 -42.40 -66.55 > 8 CPUs in mask -0.03 -47.82 -68.39 > 16 CPUs in mask 0.12 -41.95 -58.26 > 32 CPUs in mask 0.02 -25.43 -39.35 > 64 CPUs in mask 0.00 -24.70 -37.83 > > With 1 thread (i.e. no contention), there is no regression in execution time. > With multiple threads, as expected there is a significant improvement in > execution time. > > As a more practical benchmark to simulate host evacuation, I measured the > memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, > so without PML). The rate increased by 16% with this patch series, even > after the recent deferred TLB flush changes. Is this a positive thing though? In the context of some related work something similar was mentioned iirc, accompanied by stating that this is actually problematic. A guest in log-dirty mode generally wants to be making progress, but also wants to be throttled enough to limit re-dirtying, such that subsequent iterations (in particular the final one) of page contents migration won't have to process overly many pages a 2nd time. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775111097-5D92A3D8-69493B11/0/0 X-purgate-type: clean X-purgate-size: 2982 On 31.03.2026 21:04, Oleksii Kurochko wrote: > --- /dev/null > +++ b/xen/arch/riscv/extable.c > @@ -0,0 +1,85 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +#define EX_FIELD(ptr, field) ((unsigned long)&(ptr)->field + (ptr)->field) > + > +static inline unsigned long ex_insn(const struct exception_table_entry *ex) > +{ > + return EX_FIELD(ex, insn); > +} > + > +static inline unsigned long ex_fixup(const struct exception_table_entry *ex) > +{ > + return EX_FIELD(ex, fixup); > +} > + > +static void __init cf_check swap_ex(void *a, void *b) > +{ > + struct exception_table_entry *x = a, *y = b, tmp; > + long delta = b - a; > + > + tmp = *x; > + x->insn = y->insn + delta; > + y->insn = tmp.insn - delta; > + > + x->fixup = y->fixup + delta; > + y->fixup = tmp.fixup - delta; > +} > + > +static int cf_check cmp_ex(const void *a, const void *b) > +{ > + const unsigned long insn_a = ex_insn(a); > + const unsigned long insn_b = ex_insn(b); > + > + /* avoid overflow */ > + return (insn_a > insn_b) - (insn_a < insn_b); What is the (slightly malformed) comment about? I don't see anything close to possibly causing overflow here. > --- /dev/null > +++ b/xen/arch/riscv/include/asm/extable.h > @@ -0,0 +1,58 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef ASM__RISCV__ASM_EXTABLE_H > +#define ASM__RISCV__ASM_EXTABLE_H > + > +#ifdef __ASSEMBLER__ > + > +#define ASM_EXTABLE(insn, fixup) \ > + .pushsection .ex_table, "a"; \ > + .balign 4; \ > + .long ((insn) - .); \ > + .long ((fixup) - .); \ For readability's sake I'm generally advocating for having enough, but not more parentheses than necessary. What's the purpose of the outer pair here and ... > + .popsection; > + > +.macro asm_extable, insn, fixup > + ASM_EXTABLE(\insn, \fixup) > +.endm > + > +#else /* __ASSEMBLER__ */ > + > +#include > +#include > + > +struct cpu_user_regs; > + > +#define ASM_EXTABLE(insn, fixup) \ > + ".pushsection .ex_table, \"a\"\n" \ > + ".balign 4\n" \ > + ".long ((" #insn ") - .)\n" \ > + ".long ((" #fixup ") - .)\n" \ ... here? I'm also uncertain about the use of .long (generally in RISC-V code, and really also in some other architectures). Imo, considering suffixes used in the instruction set (e.g. load/store insns or OP-32 ones in RV64) .word may be the more expressive directive. Preferably with the adjustments: Acked-by: Jan Beulich Happy to carry out while committing, provided you agree. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 02 06:30:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 06:30:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271111.1559399 (Exim 4.92) (envelope-from ) id 1w8BZT-0002oB-S7; Thu, 02 Apr 2026 06:30:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271111.1559399; Thu, 02 Apr 2026 06:30:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BZT-0002o4-OW; Thu, 02 Apr 2026 06:30:27 +0000 Received: by outflank-mailman (input) for mailman id 1271111; Thu, 02 Apr 2026 06:30:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BZS-0002ny-Md for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 06:30:26 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8BZS-000iIe-2h for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:30:26 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce0d00-2eae-0a2a0a5409dd-0a2a450adba8-6 for ; Thu, 02 Apr 2026 08:30:25 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce0d01-ee98-0a2a450a0019-d155802ae8c9-3 for ; Thu, 02 Apr 2026 08:30:25 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4853c1ca73aso4168135e9.2 for ; Wed, 01 Apr 2026 23:30:25 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775111425-0F3490B1-FC35DB84/0/0 X-purgate-type: clean X-purgate-size: 1113 On 31.03.2026 21:04, Oleksii Kurochko wrote: > @@ -78,6 +80,38 @@ > : "memory" ); \ > }) > > +static always_inline bool csr_read_safe(unsigned long csr, > + unsigned long *val) > +{ > +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT > + asm_inline goto ( > + "1: csrr %[val], %[csr]\n" > + ASM_EXTABLE(1b, %l[fault]) > + : [val] "=&r" (*val) Why the & when there's only a single insn? > + : [csr] "i" (csr) > + : > + : fault ); > + > + return true; > + > + fault: > + return false; > +#else > + bool allowed = false; > + > + asm_inline volatile ( > + "1: csrr %[val], %[csr]\n" > + " li %[allowed], 1\n" > + "2:\n" > + ASM_EXTABLE(1b, 2b) > + : [val] "=&r" (*val), [allowed] "+r" (allowed) > + : [csr] "i" (csr) > + : ); Why the excess colon? With these adjusted (again happy to do so while committing, so long as you agree): Reviewed-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 02 06:32:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 06:32:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271121.1559408 (Exim 4.92) (envelope-from ) id 1w8BbX-0003Kt-7C; Thu, 02 Apr 2026 06:32:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271121.1559408; Thu, 02 Apr 2026 06:32:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BbX-0003Km-3Y; Thu, 02 Apr 2026 06:32:35 +0000 Received: by outflank-mailman (input) for mailman id 1271121; Thu, 02 Apr 2026 06:32:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8BbV-0003Ke-Tu for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Thu, 2 Apr 2026 08:32:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] xen/arm: vpci: Move content of xen/arch/arm/vpci.h to arch header To: Julien Grall , CC: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Rahul Singh References: <20260401145816.169557-1-michal.orzel@amd.com> <20260401145816.169557-4-michal.orzel@amd.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000012:EE_|DS7PR12MB5814:EE_ X-MS-Office365-Filtering-Correlation-Id: ea30c74f-5bfb-4ea8-1dd4-08de90819bea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: I8SiPHXfsr4GtcjRG8WObaGmipr17DDfx7iEy1G0AWPnHRnsvFpspRFBmxN5cTocGmjp6cjn2YgRTIqR3YLscDK0GBP1Vk9+98y8UDdJIJzd4V+1T1y1TOpLNpF3KMQnEVBQJzmhDJ6aJWoLZsWQLaqlOl6dE6RCf+oyxLLOB/YanlXJghIrLb3LYOkyWmsrLV5TZFBoyeSUtxyu4saAlGP9yQj7jGAyHB1saRMtEqaq04VL5ms+gvqkyfPtgUvr79kRqDhXezSRCB/UqG5+MupJJBGrmNwZRr60Yw3DctB7nF8ULQ2xv+J9VEoy407D4JfbEBj9evv3kGcR/0gV64uQzpXi5vlILsRv8AJ8JOg1VQwbK6REtx7hYeTuHwBgyQS48YfXvuNsiZCycncvWFGPEOkCtyb90QE0u7KVzVDkrBxgSKX4LDGSWwux39wQto6Cvy7OwT7Bjd3hdZgd8yoy6OruYM5cXk+H7z+AWhyl+xTxK/K/ld624idTPDcSXz8Zdu9jtyIA52p8atwh9KRfLjTp5sTm4KO8RIxrirUA44dqtH5iAfSY+9nUyYdclqkrTorBQyuFnpdoCJDDIJwHFc/2EV6zYY5v+u/NCfDNeWSSDJXYaEnSD2IGALYgnGypvmOq3HwzfbSJoFYtDGdE3Pba3++kkuZmnhNnIWujkynv0N/qRz6Ep37PuJzhb42mXeTxU4rRttWAzOYAQkQ5U1ryoHYgIfW2rX5Z8xU/NdQsILNbMEVKelWlm2L0jHopgxmIX5dwRSQfoIgBlg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aokqyNAL0ooDn7IOE36lPnh+XZQT2U3MedEYYfvRRp1aDSR75/aVlhrm7IlXocUn8425z/UbTQ1H4kWWesh0UrYxP8WVGGl9uWzqJ5+sRvnMMdnXMPi1Kh1JI35XLfUjRDhb6idZ94RUMaQqAEH0HqgBZXWzZdzm8g/NwaT03lxBXYhAiVVrqXuEENWgES7zcUh/PE6PR2XaZz5+PzEJfR8oIw+Ae+ozzLczeUIS+16MK0PfQ06cAAkiCcLqes6zDV6Py26BJdzfUSLs8fC7tNNgdRvsUWTYXBo+RIHY0SAFI7ly1n7xzTCnd/zOFbbmyA1HMjBfMu3FUlhSQAUR1BJix1tNmYJkC84JBgUTCImyGHum6BQdlmQ22HJqJNpkL2nDuMToYPXxqsT1rfdgvfh8ep2AzmGCjCbPi21lsF84JfPWnZPVIYuylFyCyNVM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2026 06:32:27.3620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea30c74f-5bfb-4ea8-1dd4-08de90819bea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000012.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5814 X-purgate-ID: tlsNG-4011c0/1775111552-C481C0B1-5DC809E6/0/0 X-purgate-type: clean X-purgate-size: 1957 +Rahul On 02/04/2026 04:44, Julien Grall wrote: > Hi Michal, > > On 01/04/2026 15:58, Michal Orzel wrote: >> Move domain_vpci_init() and domain_vpci_get_num_mmio_handlers() >> declarations from the private xen/arch/arm/vpci.h into the public >> xen/arch/arm/include/asm/vpci.h, and remove the now redundant >> private header. > > Can you provide a brief explanation why we don't couldn't include > "vpci.h" from "arch/arm/vpci.c"? Such approach would ... Yes, we could but I think it's better not to use local headers if the main ones under include already exists. This matches the x86. > >> >> Update domain.c to include instead of the removed private >> header. >> >> This ensures the declarations are visible where the functions are >> defined, resolving a MISRA C Rule 8.4 violation. >> >> Signed-off-by: Michal Orzel >> --- >> I'm moving a file with GPL2+ license to a file with GPL2-only. I consider this >> ok in this case becase the copyright on a file with just prototypes does not >> make any sense and a license text was most likely blindly copy-pasted like for >> most of the files in that era. > > ... avoid the licensing discussion. I am in the opinion that it is ok to > move from GPLv2+ to GPLv2 because the license says "either version 2 of > the License, or (at your option) any later version". But I remember not > everyone agrees on this interpretation and we never solved the > discussion on whether we need to request permission from the original > copyright holder. > > Alternatively, I see this file was only modified by two companies (EPAM > and Arm). I see one employee of each company are already CCed. So you > could confirm with them if the change is fine. The header was introduced by Rahul Singh from Arm and Oleksandr Andruschenko from EPAM. @Rahul, @Bertrand, @Volodymyr - are you ok to move this file to GPL2-only? ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 02 06:41:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 06:41:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271135.1559417 (Exim 4.92) (envelope-from ) id 1w8Bk1-00057x-WD; Thu, 02 Apr 2026 06:41:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271135.1559417; Thu, 02 Apr 2026 06:41:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Bk1-00057q-Tb; Thu, 02 Apr 2026 06:41:21 +0000 Received: by outflank-mailman (input) for mailman id 1271135; Thu, 02 Apr 2026 06:41:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Bjz-00057k-T9 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 06:41:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8Bjy-006qKl-TD for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:41:18 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce0f8c-bab6-0a2a0a5309dd-0a2a450389f4-10 for ; Thu, 02 Apr 2026 08:41:18 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce0f8e-02b3-0a2a45030019-d1558033c450-3 for ; Thu, 02 Apr 2026 08:41:18 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4888244e9f9so3892885e9.0 for ; Wed, 01 Apr 2026 23:41:18 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775112078-4792AC9A-747ADD21/0/0 X-purgate-type: clean X-purgate-size: 3080 On 31.03.2026 21:04, Oleksii Kurochko wrote: > @@ -495,6 +498,36 @@ void __init riscv_fill_hwcap(void) > panic("HW capabilities parsing failed: %s\n", failure_msg); > } > > + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) > + { > + printk("SSTC is detected but is supported only for Xen usage not for " > + "a guest\n"); Please don't wrap format strings. Them going slightly beyond 80 columns is okay. Them going much beyond that is a good indication that you want to consider re- wording. (Here e.g. "SSTC detected; supported for Xen use, but not for guests".) I question though whether something like this needs logging. > + /* > + * As SSTC for guest isn't supported it is needed temprorary to: Nit: temporary > + * > + * 1. Clear bit RISCV_ISA_EXT_sstc in riscv_isa as theoretuically it Nit: theoretically > + * could be that OpenSBI (it doesn't pass it now) or whatever ran > + * before Xen will add SSTC to riscv,isa string. This bit clear > + * won't allow guest to use SSTC extension as vtimer context > + * switch and restore isn't ready for that. > + */ > + __clear_bit(RISCV_ISA_EXT_sstc, riscv_isa); Seeing your other series, shouldn't this instead be done without affecting riscv_isa? The BUG_ON()s in vtimer.x therefore also look inappropriate. > @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) > if ( deadline <= now ) > return 0; > > - /* > - * TODO: When the SSTC extension is supported, it would be preferable to > - * use the supervisor timer registers directly here for better > - * performance, since an SBI call and mode switch would no longer > - * be required. > - * > - * This would also reduce reliance on a specific SBI implementation. > - * For example, it is not ideal to panic() if sbi_set_timer() returns > - * a non-zero value. Currently it can return 0 or -ENOSUPP, and > - * without SSTC we still need an implementation because only the > - * M-mode timer is available, and it can only be programmed in > - * M-mode. > - */ > - if ( (rc = sbi_set_timer(deadline)) ) > + if ( (rc = set_xen_timer(deadline)) ) > panic("%s: timer wasn't set because: %d\n", __func__, rc); > > /* Enable timer interrupt */ > @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) > > void __init preinit_xen_time(void) > { > + unsigned long tmp; > + > if ( acpi_disabled ) > preinit_dt_xen_time(); > else > panic("%s: ACPI isn't supported\n", __func__); > > boot_clock_cycles = get_cycles(); > + > + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) > + set_xen_timer = sstc_set_xen_timer; > + else > + set_xen_timer = sbi_set_timer; > } Doesn't all of this together eliminate the need for sbi_set_timer as a separate global variable? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775112903-76D4B497-D672ED31/0/0 X-purgate-type: clean X-purgate-size: 5829 On 01.04.2026 22:30, Marek Marczykowski-Górecki wrote: > On Wed, Apr 01, 2026 at 10:11:12AM +0200, Jan Beulich wrote: >> On 01.04.2026 09:20, Andrew Cooper wrote: >>> On 01/04/2026 9:14 am, Jan Beulich wrote: >>>> On 27.03.2026 11:19, Marek Marczykowski-Górecki wrote: >>>>> I noticed that on some systems, there are a lot of IOMMU faults after >>>>> S3. I can see it also on a laptop with MTL, but it affects also the ADL >>>>> gitlab runner: >>>>> >>>>> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 >>>>> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>>>> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>>>> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>>>> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>>>> >>>>> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. >>>>> >>>>> The issue is present only on staging, not staging-4.21. >>>>> >>>>> Bisect says: >>>>> >>>>> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit >>>>> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b >>>>> Author: Jan Beulich >>>>> Date: Thu Jan 22 14:13:35 2026 +0100 >>>>> >>>>> x86/HPET: drop .set_affinity hook >>>> Looking into this, I find several things I can't quite understand (yet). >>>> First there is >>>> >>>> (XEN) [000000456c0fe39f] Disabling HPET for being unreliable >>>> >>>> which looks to only affect clocksource selection, but not use as >>>> broadcast source for CPU-idle management. (This may be an independent >>>> issue.) >>>> >>>> Then there is >>>> >>>> (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) >>>> >>>> which should only occur on ARAT-incapable systems. That should only be >>>> older hardware. >>> >>> I'm not sure that's a reasonable assertion to draw.  The number of HPET >>> channels is down to the HPET alone, not anything to do with the CPU >>> capabilities. >> >> My statement was about the mere presence of that message, not the number >> of channels that are reported. >> >>>> (On my much older Skylake I don't see this line, for >>>> example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid >>>> is purely featureset based, and hence doesn't expose info about that >>>> leaf. >>> >>> xen-cpuid -p >>> >>> That will get you leaf 6, but there's no human-readable decode of it. >> >> Raw numbers is good enough here. How did I miss that option when looking >> at --help output? Oh, simply because it isn't shown there. >> >> Marek, that'll be better than bare metal kernel data, as it gives us both >> raw and host policies. > > Here is the output from ADL runner: > > Xen reports there are maximum 120 leaves and 2 MSRs > Raw policy: 48 leaves, 2 MSRs > CPUID: > leaf subleaf -> eax ebx ecx edx > 00000000:ffffffff -> 00000020:756e6547:6c65746e:49656e69 > 00000001:ffffffff -> 00090672:00800800:77fafbff:bfebfbff > 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 > 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 > 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 > 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 > 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 > 00000005:ffffffff -> 00000040:00000040:00000003:10102020 > 00000006:ffffffff -> 00df8ff7:00000002:00000409:00000003 > 00000007:00000000 -> 00000002:239c27eb:98c027ac:fc1cc410 > 00000007:00000001 -> 00400810:00000000:00000000:00040000 > 00000007:00000002 -> 00000000:00000000:00000000:00000017 > 0000000a:ffffffff -> 07300605:00000000:00000007:00008603 > 0000000b:00000000 -> 00000001:00000002:00000100:00000000 > 0000000b:00000001 -> 00000007:00000010:00000201:00000000 > 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 > 0000000d:00000001 -> 0000000f:00000000:00019900:00000000 > 0000000d:00000002 -> 00000100:00000240:00000000:00000000 > 0000000d:00000008 -> 00000080:00000000:00000001:00000000 > 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 > 0000000d:0000000b -> 00000010:00000000:00000001:00000000 > 0000000d:0000000c -> 00000018:00000000:00000001:00000000 > 0000000d:0000000f -> 00000328:00000000:00000001:00000000 > 0000000d:00000010 -> 00000008:00000000:00000001:00000000 > 80000000:ffffffff -> 80000008:00000000:00000000:00000000 > 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 > 80000002:ffffffff -> 68743231:6e654720:746e4920:52286c65 > 80000003:ffffffff -> 6f432029:54286572:6920294d:32312d35 > 80000004:ffffffff -> 4b303036:00000000:00000000:00000000 > 80000006:ffffffff -> 00000000:00000000:05007040:00000000 > 80000007:ffffffff -> 00000000:00000000:00000000:00000100 > 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 > MSRs: > index -> value > 000000ce -> 0000000080000000 > 0000010a -> 000000001488fd6b > Host policy: 41 leaves, 2 MSRs > CPUID: > leaf subleaf -> eax ebx ecx edx > 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 > 00000001:ffffffff -> 00090672:00800800:77fafbff:bfebfbff > 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 > 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 > 00000004:00000001 -> fc004122:01c0003f:0000003f:00000000 > 00000004:00000002 -> fc01c143:0240003f:000007ff:00000000 > 00000004:00000003 -> fc1fc163:0240003f:00007fff:00000004 > 00000005:ffffffff -> 00000040:00000040:00000003:10102020 > 00000006:ffffffff -> 00df8ff7:00000002:00000409:00000003 And everything as expected: The ARAT bit is set. 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Thu, 02 Apr 2026 00:01:13 -0700 (PDT) Message-ID: <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> Date: Thu, 2 Apr 2026 09:01:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1775113274-2DD57152-703E4107/0/0 X-purgate-type: clean X-purgate-size: 4693 On 02.04.2026 01:17, Marek Marczykowski-Górecki wrote: > On Wed, Apr 01, 2026 at 10:52:37AM +0200, Jan Beulich wrote: >> On 01.04.2026 09:14, Jan Beulich wrote: >>> On 27.03.2026 11:19, Marek Marczykowski-Górecki wrote: >>>> I noticed that on some systems, there are a lot of IOMMU faults after >>>> S3. I can see it also on a laptop with MTL, but it affects also the ADL >>>> gitlab runner: >>>> >>>> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 >>>> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>>> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>>> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>>> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>>> >>>> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. >>>> >>>> The issue is present only on staging, not staging-4.21. >>>> >>>> Bisect says: >>>> >>>> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit >>>> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b >>>> Author: Jan Beulich >>>> Date: Thu Jan 22 14:13:35 2026 +0100 >>>> >>>> x86/HPET: drop .set_affinity hook >>> >>> Looking into this, I find several things I can't quite understand (yet). >>> First there is >>> >>> (XEN) [000000456c0fe39f] Disabling HPET for being unreliable >>> >>> which looks to only affect clocksource selection, but not use as >>> broadcast source for CPU-idle management. (This may be an independent >>> issue.) >>> >>> Then there is >>> >>> (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) >>> >>> which should only occur on ARAT-incapable systems. That should only be >>> older hardware. (On my much older Skylake I don't see this line, for >>> example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid >>> is purely featureset based, and hence doesn't expose info about that >>> leaf. The leaf also isn't exposed to domains, so CPUID output in Dom0 >>> isn't useful to look at either. It would need to be CPUID output on a >>> bare metal kernel. >>> >>> Further I suspect the fingered commit may only have uncovered an issue >>> elsewhere. I don't think we clear any context table entries during >>> suspend or resume. Hence in >>> >>> (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 >>> (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context entry is clear >>> >>> the latter message is confusing me. >>> >>> The fault address being zero may, otoh, be a hint of hpet_msi_write() >>> never having run post-resume. Which may be the connection to the >>> dropping of hpet_msi_set_affinity(), as that did call that function. >> >> There clearly is an issue with the handling of the max_cstate variable, >> but I expect you don't use xenpm to limit usable C-states (there clearly >> is no respective command line option in the log you referenced)? > > No, I don't think so. > >> From what the log has, I conclude hpet_broadcast_resume() is called. > > I don't think so... I applied changes as attached and got this on > resume: > > (XEN) [ 69.486120] Enabling non-boot CPUs ... > (XEN) [ 69.486404] mwait-idle: state C1 is disabled > (XEN) [ 69.587869] mwait-idle: state C1 is disabled > (XEN) [ 69.588008] mwait-idle: state C1 is disabled > (XEN) [ 69.689438] mwait-idle: state C1 is disabled > (XEN) [ 69.689608] mwait-idle: state C1 is disabled > (XEN) [ 69.791066] mwait-idle: state C1 is disabled > (XEN) [ 69.791334] mwait-idle: state C1 is disabled > (XEN) [ 69.892938] mwait-idle: state C1 is disabled > (XEN) [ 69.893209] mwait-idle: state C1 is disabled > (XEN) [ 69.994890] mwait-idle: state C1 is disabled > (XEN) [ 69.995096] mwait-idle: state C1 is disabled > (XEN) [ 70.096638] mwait-idle: state C1 is disabled > (XEN) [ 70.096915] mwait-idle: state C1 is disabled > (XEN) [ 70.097093] mwait-idle: state C1 is disabled > (XEN) [ 70.097272] mwait-idle: state C1 is disabled > (XEN) [ 70.203357] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.6] fault addr 0 > (XEN) [ 70.203363] [VT-D]DMAR: reason 02 - Present bit in context entry is clear That was on the serial console or from xl dmesg? I ask because console_resume() runs after time_resume(), so nothing appearing on the serial console would be expected (I think). Without hpet_broadcast_resume() running, I don't think I could explain how the channels (and their FSB interrupts) would get enabled. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Iyr20FpUSgXtvjbbbrb6yY9pinKqgCdGsXmnW4CuwpH/rk3IjxhciWZCI2pJWqTlDnsOfD6xCXP3zh1ocay/lyIcwIwfj00tCOScYjb5LxL1OcqN6e2yFlrKmciMXZUDUsEJz4fbDFuHrp/OzPCQf9p5xgLgZHwiIyxwqq3aAFYkljsH+nKQtl/l2TJprLGITQrCKTeagpHu0fFXurkP/CDysPtwVuHfupf+lYVItSfrCJmKednZvs1FUh6kfJEBoTzFT2IdGKXzewak3MbtM47lHsVYch+hRyud/qknc5eafcTdHX8PofHkRtiqo9pS4P3NEW7DiVySDJ6ZK/TFUKBpZMwhL/DNrjIZkpkhoyOXIcm+SEiDEubtUx1ZQ/5M2eP6pcBZGssEmvzyevo8XYOmyB3G3yjRejPJplhfrttRgEgbjy7r7jAMFLuFYTWl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2026 07:56:56.4185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6a4d0f9-acb1-4137-9f08-08de908d694e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8909 X-purgate-ID: tlsNG-ebf023/1775116621-3253B51B-0596B155/0/0 X-purgate-type: clean X-purgate-size: 1635 ioremap_attr() computes end_pg as round_pgup(start_pg + len), but start_pg has already had the sub-page offset stripped by round_pgdown(). When start is not page-aligned, the sub-page offset is lost and the resulting MPU protection region can be one page too small, leaving the tail of the requested range covered by something else. Additionally, the function returns maddr_to_virt(start_pg) — the page-aligned base dropping the sub-page offset that callers (e.g. ioremap of an unaligned MMIO base) depend on to reach the correct register block. Fix end_pg to use the original start so the sub-page tail is included in the rounding, and return the original start address to preserve the offset, matching the behaviour of other ioremap implementations. Fixes: efeec4c70798 ("arm/mpu: Implement ioremap_attr for MPU") Signed-off-by: Michal Orzel --- xen/arch/arm/mpu/mm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 6b3b0b06e95d..aff88bd3a9c1 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -596,13 +596,13 @@ void free_init_memory(void) void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags) { paddr_t start_pg = round_pgdown(start); - paddr_t end_pg = round_pgup(start_pg + len); + paddr_t end_pg = round_pgup(start + len); if ( xen_mpumap_update(start_pg, end_pg, flags) ) return NULL; /* Mapped or already mapped */ - return maddr_to_virt(start_pg); + return maddr_to_virt(start); } /* -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 08:09:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 08:09:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271235.1559463 (Exim 4.92) (envelope-from ) id 1w8D6f-0001CC-AH; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bhkLNO4Ucmh0/XDZ" Content-Disposition: inline In-Reply-To: <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> X-purgate-ID: tlsNG-33051d/1775117327-4076BC9A-8DFE98A3/0/0 X-purgate-type: clean X-purgate-size: 18585 --bhkLNO4Ucmh0/XDZ Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 2 Apr 2026 10:08:42 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Thu, Apr 02, 2026 at 09:01:12AM +0200, Jan Beulich wrote: > On 02.04.2026 01:17, Marek Marczykowski-G=C3=B3recki wrote: > > On Wed, Apr 01, 2026 at 10:52:37AM +0200, Jan Beulich wrote: > >> On 01.04.2026 09:14, Jan Beulich wrote: > >>> On 27.03.2026 11:19, Marek Marczykowski-G=C3=B3recki wrote: > >>>> I noticed that on some systems, there are a lot of IOMMU faults after > >>>> S3. I can see it also on a laptop with MTL, but it affects also the = ADL > >>>> gitlab runner: > >>>> > >>>> https://gitlab.com/xen-project/hardware/xen/-/jobs/13661033722 > >>>> (XEN) [ 37.201160] [VT-D]DMAR:[DMA Write] Request device [0000= :00:1e.6] fault addr 0 > >>>> (XEN) [ 37.201164] [VT-D]DMAR: reason 02 - Present bit in cont= ext entry is clear > >>>> (XEN) [ 37.202332] [VT-D]DMAR:[DMA Write] Request device [0000= :00:1e.6] fault addr 0 > >>>> (XEN) [ 37.202339] [VT-D]DMAR: reason 02 - Present bit in cont= ext entry is clear > >>>> > >>>> Interestingly, the 0000:00:1e.6 device is not even listed by lspci. > >>>> > >>>> The issue is present only on staging, not staging-4.21. > >>>> > >>>> Bisect says: > >>>> > >>>> 5ec93b2f19ff8873fca65d38c1164b0a56d3898b is the first bad commit > >>>> commit 5ec93b2f19ff8873fca65d38c1164b0a56d3898b > >>>> Author: Jan Beulich > >>>> Date: Thu Jan 22 14:13:35 2026 +0100 > >>>> > >>>> x86/HPET: drop .set_affinity hook > >>> > >>> Looking into this, I find several things I can't quite understand (ye= t). > >>> First there is > >>> > >>> (XEN) [000000456c0fe39f] Disabling HPET for being unreliable > >>> > >>> which looks to only affect clocksource selection, but not use as > >>> broadcast source for CPU-idle management. (This may be an independent > >>> issue.) > >>> > >>> Then there is > >>> > >>> (XEN) [ 2.760248] HPET: 8 timers usable for broadcast (8 total) > >>> > >>> which should only occur on ARAT-incapable systems. That should only be > >>> older hardware. (On my much older Skylake I don't see this line, for > >>> example.) What does CPUID leaf 6 have on this system? Sadly xen-cpuid > >>> is purely featureset based, and hence doesn't expose info about that > >>> leaf. The leaf also isn't exposed to domains, so CPUID output in Dom0 > >>> isn't useful to look at either. It would need to be CPUID output on a > >>> bare metal kernel. > >>> > >>> Further I suspect the fingered commit may only have uncovered an issue > >>> elsewhere. I don't think we clear any context table entries during > >>> suspend or resume. Hence in > >>> > >>> (XEN) [ 20.554813] [VT-D]DMAR:[DMA Write] Request device [0000:00:1= e.6] fault addr 0 > >>> (XEN) [ 20.554819] [VT-D]DMAR: reason 02 - Present bit in context e= ntry is clear > >>> > >>> the latter message is confusing me. > >>> > >>> The fault address being zero may, otoh, be a hint of hpet_msi_write() > >>> never having run post-resume. Which may be the connection to the > >>> dropping of hpet_msi_set_affinity(), as that did call that function. > >> > >> There clearly is an issue with the handling of the max_cstate variable, > >> but I expect you don't use xenpm to limit usable C-states (there clear= ly > >> is no respective command line option in the log you referenced)? > >=20 > > No, I don't think so. > >=20 > >> From what the log has, I conclude hpet_broadcast_resume() is called. > >=20 > > I don't think so... I applied changes as attached and got this on > > resume: > >=20 > > (XEN) [ 69.486120] Enabling non-boot CPUs ... > > (XEN) [ 69.486404] mwait-idle: state C1 is disabled > > (XEN) [ 69.587869] mwait-idle: state C1 is disabled > > (XEN) [ 69.588008] mwait-idle: state C1 is disabled > > (XEN) [ 69.689438] mwait-idle: state C1 is disabled > > (XEN) [ 69.689608] mwait-idle: state C1 is disabled > > (XEN) [ 69.791066] mwait-idle: state C1 is disabled > > (XEN) [ 69.791334] mwait-idle: state C1 is disabled > > (XEN) [ 69.892938] mwait-idle: state C1 is disabled > > (XEN) [ 69.893209] mwait-idle: state C1 is disabled > > (XEN) [ 69.994890] mwait-idle: state C1 is disabled > > (XEN) [ 69.995096] mwait-idle: state C1 is disabled > > (XEN) [ 70.096638] mwait-idle: state C1 is disabled > > (XEN) [ 70.096915] mwait-idle: state C1 is disabled > > (XEN) [ 70.097093] mwait-idle: state C1 is disabled > > (XEN) [ 70.097272] mwait-idle: state C1 is disabled > > (XEN) [ 70.203357] [VT-D]DMAR:[DMA Write] Request device [0000:00:1e.= 6] fault addr 0 > > (XEN) [ 70.203363] [VT-D]DMAR: reason 02 - Present bit in context ent= ry is clear >=20 > That was on the serial console or from xl dmesg? I ask because console_re= sume() > runs after time_resume(), so nothing appearing on the serial console woul= d be > expected (I think). Ah, right, that's why I don't see my messages. The xl dmesg output (from MTL this time): (XEN) [ 123.477511] Entering ACPI S3 state. (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has= _apic: 1 (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cs= tate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 (XEN) [18446743903.571866] _disable_pit_irq:2662: init: 0 (XEN) [18446743903.571877] hpet_broadcast_resume:661: hpet_events: ffff= 83046bc1f080 (XEN) [18446743903.572020] hpet_broadcast_resume:672: num_hpets_used: 8 (XEN) [18446743903.572029] hpet_broadcast_resume:690: cfg: 0x1 (XEN) [18446743903.572040] hpet_broadcast_resume:695: i:0, hpet_events[= i].msi.irq: 122, hpet_events[i].flags: 0 (XEN) [18446743903.572081] hpet_broadcast_resume:706: i:0, cfg: 0xc134 (XEN) [18446743903.572089] hpet_broadcast_resume:695: i:1, hpet_events[= i].msi.irq: 123, hpet_events[i].flags: 0 (XEN) [18446743903.572123] hpet_broadcast_resume:706: i:1, cfg: 0xc104 (XEN) [18446743903.572132] hpet_broadcast_resume:695: i:2, hpet_events[= i].msi.irq: 124, hpet_events[i].flags: 0 (XEN) [18446743903.572167] hpet_broadcast_resume:706: i:2, cfg: 0xc104 (XEN) [18446743903.572175] hpet_broadcast_resume:695: i:3, hpet_events[= i].msi.irq: 125, hpet_events[i].flags: 0 (XEN) [18446743903.572210] hpet_broadcast_resume:706: i:3, cfg: 0xc104 (XEN) [18446743903.572218] hpet_broadcast_resume:695: i:4, hpet_events[= i].msi.irq: 126, hpet_events[i].flags: 0 (XEN) [18446743903.572252] hpet_broadcast_resume:706: i:4, cfg: 0xc104 (XEN) [18446743903.572261] hpet_broadcast_resume:695: i:5, hpet_events[= i].msi.irq: 127, hpet_events[i].flags: 0 (XEN) [18446743903.572294] hpet_broadcast_resume:706: i:5, cfg: 0xc104 (XEN) [18446743903.572303] hpet_broadcast_resume:695: i:6, hpet_events[= i].msi.irq: 128, hpet_events[i].flags: 0 (XEN) [18446743903.572338] hpet_broadcast_resume:706: i:6, cfg: 0xc104 (XEN) [18446743903.572347] hpet_broadcast_resume:695: i:7, hpet_events[= i].msi.irq: 129, hpet_events[i].flags: 0 (XEN) [18446743903.572382] hpet_broadcast_resume:706: i:7, cfg: 0xc104 And the xen-cpuid -p output from this system: Xen reports there are maximum 120 leaves and 2 MSRs Raw policy: 48 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 00000023:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:20800800:77fafbff:bfebfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000005:ffffffff -> 00000040:00000040:00000003:11112020 00000006:ffffffff -> 00dfcff7:00000002:00000409:00040003 00000007:00000000 -> 00000002:239c27eb:994007ac:fc18c410 00000007:00000001 -> 40400910:00000001:00000000:00040000 00000007:00000002 -> 00000000:00000000:00000000:0000003f 0000000a:ffffffff -> 07300805:00000000:00000007:00008603 0000000b:00000000 -> 00000001:00000002:00000100:00000020 0000000b:00000001 -> 00000007:00000016:00000201:00000020 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00019900:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000008 -> 00000080:00000000:00000001:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 0000000d:0000000b -> 00000010:00000000:00000001:00000000 0000000d:0000000c -> 00000018:00000000:00000001:00000000 0000000d:0000000f -> 00000328:00000000:00000001:00000000 0000000d:00000010 -> 00000008:00000000:00000001:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 000000000d89fd6b Host policy: 41 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:20800800:77fafbff:bfebfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000005:ffffffff -> 00000040:00000040:00000003:11112020 00000006:ffffffff -> 00dfcff7:00000002:00000409:00040003 00000007:00000000 -> 00000002:239c27eb:994007ac:fc18c410 00000007:00000001 -> 40000910:00000001:00000000:00040000 00000007:00000002 -> 00000000:00000000:00000000:0000003f 0000000b:00000000 -> 00000001:00000002:00000100:00000020 0000000b:00000001 -> 00000007:00000016:00000201:00000020 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000000d89fd6b PV Max policy: 58 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:00800800:f6f83203:1fc9cbf5 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000007:00000000 -> 00000002:218c0329:18400700:ac004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000021 0000000d:00000000 -> 00000007:00000000:00000340:00000000 0000000d:00000001 -> 00000007:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 80000000:ffffffff -> 80000021:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000123:28100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00001000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000001d0ae167 HVM Max policy: 65 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:00800800:f7fa3223:1fcbfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000007:00000000 -> 00000002:219c07ab:9840070c:bc004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000037 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000021:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000123:2c100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000007:ffffffff -> 00000000:00000000:00000000:00000100 80000008:ffffffff -> 0000302e:00101000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000001d0ae167 PV Default policy: 33 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:00800800:f6d83203:1fc9cbf5 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000007:00000000 -> 00000002:218c0329:00400700:ac004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000021 0000000d:00000000 -> 00000007:00000000:00000340:00000000 0000000d:00000001 -> 00000007:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:28100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000008:ffffffff -> 0000302e:00001000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000000d08e163 HVM Default policy: 40 leaves, 2 MSRs CPUID: leaf subleaf -> eax ebx ecx edx =20 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 00000001:ffffffff -> 000a06a4:00800800:f7fa3203:1fcbfbff 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 00000007:00000000 -> 00000002:219c07ab:8040070c:bc004410 00000007:00000001 -> 00000810:00000000:00000000:00000000 00000007:00000002 -> 00000000:00000000:00000000:00000037 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 0000000d:00000001 -> 0000000f:00000000:00000000:00000000 0000000d:00000002 -> 00000100:00000240:00000000:00000000 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 80000000:ffffffff -> 80000008:00000000:00000000:00000000 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 80000006:ffffffff -> 00000000:00000000:08007040:00000000 80000008:ffffffff -> 0000302e:00101000:00000000:00000000 MSRs: index -> value =20 000000ce -> 0000000080000000 0000010a -> 400000000d08e163 > Without hpet_broadcast_resume() running, I don't think I could explain ho= w the > channels (and their FSB interrupts) would get enabled. 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To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel , =?UTF-8?B?SsO8cmdlbiBHcm8=?= =?UTF-8?B?w58=?= References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC 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X-purgate-ID: tlsNG-33051d/1775118231-C9F3DC9A-1E7986AF/0/0 X-purgate-type: clean X-purgate-size: 10544 On 27.03.2026 13:47, Marek Marczykowski-Górecki wrote: > Some further observation, this time regarding timers: > > Just before S3: > > (XEN) [ 150.264757] Dumping timer queues: > (XEN) [ 150.265181] CPU00: > (XEN) [ 150.265497] ex= 736us timer=ffff82d040643540 cb=drivers/char/xhci-dbc.c#dbc_uart_poll(ffff82d0404e5e78) > (XEN) [ 150.266590] ex= 460377us timer=ffff82d04065d2c0 cb=arch/x86/time.c#time_calibration(0000000000000000) > (XEN) [ 150.267636] ex= 1377460us timer=ffff82d04065d220 cb=arch/x86/time.c#plt_overflow(0000000000000000) > (XEN) [ 150.268651] ex= 13525100us timer=ffff82d040644c20 cb=arch/x86/cpu/mcheck/intel-nonfatal.c#mce_work_fn(0000000000000000) > (XEN) [ 150.269820] CPU02: > (XEN) [ 150.270126] ex= 616653us timer=ffff830461931070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461931000) > (XEN) [ 150.271276] CPU04: > (XEN) [ 150.271577] ex= 630577us timer=ffff830461935070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461935000) > (XEN) [ 150.272734] ex= 634586us timer=ffff830461921070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461921000) > (XEN) [ 150.273884] CPU06: > (XEN) [ 150.274184] ex= 44474us timer=ffff830461905070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461905000) > (XEN) [ 150.275334] CPU08: > (XEN) [ 150.275633] ex= 11465us timer=ffff83046190d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046190d000) > (XEN) [ 150.276783] CPU09: > (XEN) [ 150.277083] ex= 12465us timer=ffff830461909070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461909000) > (XEN) [ 150.278236] CPU10: > (XEN) [ 150.278536] ex= 14464us timer=ffff830461901070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461901000) > (XEN) [ 150.279686] CPU11: > (XEN) [ 150.279986] ex= 15464us timer=ffff830461911070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461911000) > (XEN) [ 150.281139] CPU12: > (XEN) [ 150.281438] ex= 17463us timer=ffff830461919070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461919000) > (XEN) [ 150.282592] CPU13: > (XEN) [ 150.282890] ex= 347090us timer=ffff830461941070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461941000) > (XEN) [ 150.284040] CPU14: > (XEN) [ 150.284341] ex= 20462us timer=ffff83046191d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046191d000) > (XEN) [ 150.285496] CPU15: > (XEN) [ 150.285806] ex= 470us timer=ffff83046192d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046192d000) > (XEN) [ 150.286972] ex= 15316us timer=ffff8304619cdaa0 cb=drivers/cpufreq/cpufreq_ondemand.c#do_dbs_timer(ffff8304619cdae0) > (XEN) [ 150.288156] ex= 6230us timer=ffff8304619e8ed0 cb=common/sched/core.c#s_timer_fn(0000000000000000) > (XEN) [ 150.289192] CPU16: > (XEN) [ 150.289492] ex= 633594us timer=ffff830461929070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461929000) > (XEN) [ 150.290642] CPU18: > (XEN) [ 150.290942] ex= 614601us timer=ffff830461939070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461939000) > (XEN) [ 150.292094] CPU20: > (XEN) [ 150.292394] ex= 27459us timer=ffff830461915070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461915000) > (XEN) [ 150.293553] ex= 55316us timer=ffff830461979aa0 cb=drivers/cpufreq/cpufreq_ondemand.c#do_dbs_timer(ffff830461979ae0) > (XEN) [ 150.294744] ex= 35413us timer=ffff83046198fdc0 cb=common/sched/core.c#s_timer_fn(0000000000000000) > (XEN) [ 150.295776] CPU21: > (XEN) [ 150.296076] ex= 617580us timer=ffff830461925070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461925000) > > Just after S3: > > (XEN) [ 164.462198] Dumping timer queues: > (XEN) [ 164.462630] CPU00: > (XEN) [ 164.462949] ex= 768us timer=ffff82d040643540 cb=drivers/char/xhci-dbc.c#dbc_uart_poll(ffff82d0404e5e78) > (XEN) [ 164.464064] ex= 1286532us timer=ffff82d04065d220 cb=arch/x86/time.c#plt_overflow(0000000000000000) > (XEN) [ 164.465099] ex= 395997us timer=ffff830461921070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461921000) > (XEN) [ 164.466262] ex= 15327843us timer=ffff82d040644c20 cb=arch/x86/cpu/mcheck/intel-nonfatal.c#mce_work_fn(0000000000000000) > (XEN) [ 164.467461] CPU02: > (XEN) [ 164.467773] ex= 37756us timer=ffff830461931070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461931000) > (XEN) [ 164.468953] CPU04: > (XEN) [ 164.469267] ex= 940042us timer=ffff830461935070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461935000) > (XEN) [ 164.470444] CPU06: > (XEN) [ 164.470759] ex= 485896us timer=ffff830461905070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461905000) > (XEN) [ 164.471937] CPU08: > (XEN) [ 164.472251] ex= 459720us timer=ffff83046190d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046190d000) > (XEN) [ 164.473430] CPU09: > (XEN) [ 164.473745] ex= 1563081us timer=ffff830461909070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461909000) > (XEN) [ 164.474922] CPU10: > (XEN) [ 164.475237] ex= 948204us timer=ffff830461901070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461901000) > (XEN) [ 164.476417] CPU11: > (XEN) [ 164.476732] ex= 948071us timer=ffff830461911070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461911000) > (XEN) [ 164.477912] CPU12: > (XEN) [ 164.478219] ex= 892163us timer=ffff830461919070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461919000) > (XEN) [ 164.479398] CPU13: > (XEN) [ 164.479713] ex= 308429us timer=ffff830461941070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461941000) > (XEN) [ 164.480893] CPU14: > (XEN) [ 164.481208] ex= 954493us timer=ffff83046191d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046191d000) > (XEN) [ 164.482386] CPU15: > (XEN) [ 164.482700] ex= 1487692us timer=ffff83046192d070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff83046192d000) > (XEN) [ 164.483881] CPU16: > (XEN) [ 164.484195] ex= 22890us timer=ffff830461929070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461929000) > (XEN) [ 164.485373] CPU18: > (XEN) [ 164.485688] ex= 85902us timer=ffff830461939070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461939000) > (XEN) [ 164.486864] CPU20: > (XEN) [ 164.487171] ex= 895us timer=ffff830461915070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461915000) > (XEN) [ 164.488358] ex= 17895us timer=ffff830461979aa0 cb=drivers/cpufreq/cpufreq_ondemand.c#do_dbs_timer(ffff830461979ae0) > (XEN) [ 164.489569] ex= 2914us timer=ffff83046198fdc0 cb=common/sched/core.c#s_timer_fn(0000000000000000) > (XEN) [ 164.490633] CPU21: > (XEN) [ 164.490947] ex= 461154us timer=ffff830461925070 cb=common/sched/core.c#vcpu_singleshot_timer_fn(ffff830461925000) > > In the latter case, I see only one cb=common/sched/core.c#s_timer_fn > (two of them before). And also only one > cb=drivers/cpufreq/cpufreq_ondemand.c#do_dbs_timer. Let's start with this one. It's active when the ondemand governor is in use, and when a CPU isn't (in the process of being put into) a C-state. There being only two instances means the system was reasonably idle at the time you dumped the timer queues ahead of entering S3, and just slightly more idle after getting back out of S3. I've just checked my Skylake: Without it ever having gone through an S3 cycle, there's only one instance there when the system is running nothing but an "xl dmesg". If you place enough load on the system to keep all CPUs busy, more instances of the timer should appear. How many of them it'll be does, however, also depend on the scope of the policy (supplied by firmware). The topology ... > Is the s_timer_fn related to runqueues? I have two of them: > > (XEN) [ 11.751480] Adding cpu 0 to runqueue 0 > (XEN) [ 11.753580] First cpu on runqueue, activating > (XEN) [ 11.755731] Adding cpu 2 to runqueue 0 > (XEN) [ 11.757818] Adding cpu 4 to runqueue 0 > (XEN) [ 11.759891] Adding cpu 6 to runqueue 0 > (XEN) [ 11.761955] Adding cpu 8 to runqueue 0 > (XEN) [ 11.764001] Adding cpu 9 to runqueue 0 > (XEN) [ 11.766029] Adding cpu 10 to runqueue 0 > (XEN) [ 11.768045] Adding cpu 11 to runqueue 0 > (XEN) [ 11.770050] Adding cpu 12 to runqueue 1 > (XEN) [ 11.772033] First cpu on runqueue, activating > (XEN) [ 11.774051] Adding cpu 13 to runqueue 1 > (XEN) [ 11.776047] Adding cpu 14 to runqueue 1 > (XEN) [ 11.777993] Adding cpu 15 to runqueue 1 > (XEN) [ 11.779913] Adding cpu 16 to runqueue 1 > (XEN) [ 11.781872] Adding cpu 18 to runqueue 1 > (XEN) [ 11.783912] Adding cpu 20 to runqueue 1 > (XEN) [ 11.785855] Adding cpu 21 to runqueue 1 ... of this system looks somewhat "interesting", judging from these CPU numbers. Assuming the system was (supposedly) equally idle before and after S3, the absence of the 2nd timer(s?) may indicate that some (background?) load that was there before S3 didn't re-appear afterwards. Such background load could be something which monitors and tunes the system. (Yet as indicated, I'm looking at the CPUfreq part only right now. I'm kind of hoping that a scheduler maintainer may look at the other aspect.) > Could the issue be related to those timer differences? Possibly. For the CPUfreq aspect you could simply turn that off to see if it makes a difference. Or you could switch to a governor different from the ondemand one. With the ondemand governor, does the pattern (will require multiple runs) change across S3 that "xenpm get-cpufreq-states" produces? For example, does load move towards CPU0? (Thinking of it, did you check whether interrupt affinities change across S3? More going to CPU0 could also be part of the problem, for example.) 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Thu, 02 Apr 2026 01:39:43 -0700 (PDT) Message-ID: Date: Thu, 2 Apr 2026 10:39:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775119183-642483D8-4995561C/0/0 X-purgate-type: clean X-purgate-size: 5827 On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: > The xl dmesg output (from MTL this time): > > (XEN) [ 123.477511] Entering ACPI S3 state. > (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 XEN_ARAT being off is the one odd aspect here. That'll want tracking down separately. As per xen-cpuid output (below) ARAT is available. > (XEN) [18446743903.571866] _disable_pit_irq:2662: init: 0 > (XEN) [18446743903.571877] hpet_broadcast_resume:661: hpet_events: ffff83046bc1f080 > (XEN) [18446743903.572020] hpet_broadcast_resume:672: num_hpets_used: 8 > (XEN) [18446743903.572029] hpet_broadcast_resume:690: cfg: 0x1 > (XEN) [18446743903.572040] hpet_broadcast_resume:695: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 > (XEN) [18446743903.572081] hpet_broadcast_resume:706: i:0, cfg: 0xc134 > (XEN) [18446743903.572089] hpet_broadcast_resume:695: i:1, hpet_events[i].msi.irq: 123, hpet_events[i].flags: 0 > (XEN) [18446743903.572123] hpet_broadcast_resume:706: i:1, cfg: 0xc104 > (XEN) [18446743903.572132] hpet_broadcast_resume:695: i:2, hpet_events[i].msi.irq: 124, hpet_events[i].flags: 0 > (XEN) [18446743903.572167] hpet_broadcast_resume:706: i:2, cfg: 0xc104 > (XEN) [18446743903.572175] hpet_broadcast_resume:695: i:3, hpet_events[i].msi.irq: 125, hpet_events[i].flags: 0 > (XEN) [18446743903.572210] hpet_broadcast_resume:706: i:3, cfg: 0xc104 > (XEN) [18446743903.572218] hpet_broadcast_resume:695: i:4, hpet_events[i].msi.irq: 126, hpet_events[i].flags: 0 > (XEN) [18446743903.572252] hpet_broadcast_resume:706: i:4, cfg: 0xc104 > (XEN) [18446743903.572261] hpet_broadcast_resume:695: i:5, hpet_events[i].msi.irq: 127, hpet_events[i].flags: 0 > (XEN) [18446743903.572294] hpet_broadcast_resume:706: i:5, cfg: 0xc104 > (XEN) [18446743903.572303] hpet_broadcast_resume:695: i:6, hpet_events[i].msi.irq: 128, hpet_events[i].flags: 0 > (XEN) [18446743903.572338] hpet_broadcast_resume:706: i:6, cfg: 0xc104 > (XEN) [18446743903.572347] hpet_broadcast_resume:695: i:7, hpet_events[i].msi.irq: 129, hpet_events[i].flags: 0 > (XEN) [18446743903.572382] hpet_broadcast_resume:706: i:7, cfg: 0xc104 Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() values might be a good idea, if only to double check.) All values logged look entirely plausible, with XEN_ARAT being off. > And the xen-cpuid -p output from this system: > > Xen reports there are maximum 120 leaves and 2 MSRs > Raw policy: 48 leaves, 2 MSRs > CPUID: > leaf subleaf -> eax ebx ecx edx > 00000000:ffffffff -> 00000023:756e6547:6c65746e:49656e69 > 00000001:ffffffff -> 000a06a4:20800800:77fafbff:bfebfbff > 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 > 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 > 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 > 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 > 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 > 00000005:ffffffff -> 00000040:00000040:00000003:11112020 > 00000006:ffffffff -> 00dfcff7:00000002:00000409:00040003 > 00000007:00000000 -> 00000002:239c27eb:994007ac:fc18c410 > 00000007:00000001 -> 40400910:00000001:00000000:00040000 > 00000007:00000002 -> 00000000:00000000:00000000:0000003f > 0000000a:ffffffff -> 07300805:00000000:00000007:00008603 > 0000000b:00000000 -> 00000001:00000002:00000100:00000020 > 0000000b:00000001 -> 00000007:00000016:00000201:00000020 > 0000000d:00000000 -> 00000207:00000000:00000a88:00000000 > 0000000d:00000001 -> 0000000f:00000000:00019900:00000000 > 0000000d:00000002 -> 00000100:00000240:00000000:00000000 > 0000000d:00000008 -> 00000080:00000000:00000001:00000000 > 0000000d:00000009 -> 00000008:00000a80:00000000:00000000 > 0000000d:0000000b -> 00000010:00000000:00000001:00000000 > 0000000d:0000000c -> 00000018:00000000:00000001:00000000 > 0000000d:0000000f -> 00000328:00000000:00000001:00000000 > 0000000d:00000010 -> 00000008:00000000:00000001:00000000 > 80000000:ffffffff -> 80000008:00000000:00000000:00000000 > 80000001:ffffffff -> 00000000:00000000:00000121:2c100800 > 80000002:ffffffff -> 65746e49:2952286c:726f4320:4d542865 > 80000003:ffffffff -> 6c552029:20617274:35312037:00004835 > 80000006:ffffffff -> 00000000:00000000:08007040:00000000 > 80000007:ffffffff -> 00000000:00000000:00000000:00000100 > 80000008:ffffffff -> 0000302e:00000000:00000000:00000000 > MSRs: > index -> value > 000000ce -> 0000000080000000 > 0000010a -> 000000000d89fd6b > Host policy: 41 leaves, 2 MSRs > CPUID: > leaf subleaf -> eax ebx ecx edx > 00000000:ffffffff -> 0000000d:756e6547:6c65746e:49656e69 > 00000001:ffffffff -> 000a06a4:20800800:77fafbff:bfebfbff > 00000002:ffffffff -> 00feff01:000000f0:00000000:00000000 > 00000004:00000000 -> fc004121:02c0003f:0000003f:00000000 > 00000004:00000001 -> fc004122:03c0003f:0000003f:00000000 > 00000004:00000002 -> fc01c143:03c0003f:000007ff:00000000 > 00000004:00000003 -> fc0fc163:02c0003f:00007fff:00000004 > 00000005:ffffffff -> 00000040:00000040:00000003:11112020 > 00000006:ffffffff -> 00dfcff7:00000002:00000409:00040003 Still ARAT available as per here. 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The benchmark has one >> or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in >> the selected mask. The executed function simply delays for 500 microseconds. >> >> The table below shows the % change in execution time of on_selected_cpus(): >> >> 1 thread 2 threads 4 threads >> 1 CPU in mask 0.02 -35.23 -51.18 >> 2 CPUs in mask 0.01 -47.20 -69.27 >> 4 CPUs in mask -0.02 -42.40 -66.55 >> 8 CPUs in mask -0.03 -47.82 -68.39 >> 16 CPUs in mask 0.12 -41.95 -58.26 >> 32 CPUs in mask 0.02 -25.43 -39.35 >> 64 CPUs in mask 0.00 -24.70 -37.83 >> >> With 1 thread (i.e. no contention), there is no regression in execution time. >> With multiple threads, as expected there is a significant improvement in >> execution time. >> >> As a more practical benchmark to simulate host evacuation, I measured the >> memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, >> so without PML). The rate increased by 16% with this patch series, even >> after the recent deferred TLB flush changes. > > Is this a positive thing though? In the context of some related work something > similar was mentioned iirc, accompanied by stating that this is actually > problematic. A guest in log-dirty mode generally wants to be making progress, > but also wants to be throttled enough to limit re-dirtying, such that > subsequent iterations (in particular the final one) of page contents > migration won't have to process overly many pages a 2nd time. > In the context of a real migration, both the process copying the pages out of the guest and the guest itself will be hitting the TLB flush lock so reducing that bottleneck may increase throughput on both sides. Whether or not the overall migration time increases or decreases depends on many factors (number of migrations in parallel, the rate the guest is dirtying memory, the line speed of the NIC, whether PML is used, ...) which is why I measured a more controlled scenario to demonstrate the change. IMO throttling of a guest during a migration should be something intentional and controlled by userspace policy rather than a side effect of some internal global locks. Ross From xen-devel-bounces@lists.xenproject.org Thu Apr 02 08:40:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 08:40:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271297.1559523 (Exim 4.92) (envelope-from ) id 1w8DbS-0008Gr-RU; Thu, 02 Apr 2026 08:40:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271297.1559523; Thu, 02 Apr 2026 08:40:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8DbS-0008Gk-ON; Thu, 02 Apr 2026 08:40:38 +0000 Received: by outflank-mailman (input) for mailman id 1271297; Thu, 02 Apr 2026 08:40:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8DbR-0008Fz-0w for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:40:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8DbQ-001D7O-DX for xen-devel@lists.xenproject.org; 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The benchmark has one >> or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in >> the selected mask. The executed function simply delays for 500 microseconds. >> >> The table below shows the % change in execution time of on_selected_cpus(): >> >> 1 thread 2 threads 4 threads >> 1 CPU in mask 0.02 -35.23 -51.18 >> 2 CPUs in mask 0.01 -47.20 -69.27 >> 4 CPUs in mask -0.02 -42.40 -66.55 >> 8 CPUs in mask -0.03 -47.82 -68.39 >> 16 CPUs in mask 0.12 -41.95 -58.26 >> 32 CPUs in mask 0.02 -25.43 -39.35 >> 64 CPUs in mask 0.00 -24.70 -37.83 >> >> With 1 thread (i.e. no contention), there is no regression in execution time. >> With multiple threads, as expected there is a significant improvement in >> execution time. >> >> As a more practical benchmark to simulate host evacuation, I measured the >> memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, >> so without PML). The rate increased by 16% with this patch series, even >> after the recent deferred TLB flush changes. > > Is this a positive thing though? In the context of some related work something > similar was mentioned iirc, accompanied by stating that this is actually > problematic. A guest in log-dirty mode generally wants to be making progress, > but also wants to be throttled enough to limit re-dirtying, such that > subsequent iterations (in particular the final one) of page contents > migration won't have to process overly many pages a 2nd time. > In the context of a real migration, both the process copying the pages out of the guest and the guest itself will be hitting the TLB flush lock so reducing that bottleneck may increase throughput on both sides. Whether or not the overall migration time increases or decreases depends on many factors (number of migrations in parallel, the rate the guest is dirtying memory, the line speed of the NIC, whether PML is used, ...) which is why I measured a more controlled scenario to demonstrate the change. IMO throttling of a guest during a migration should be something intentional and controlled by userspace policy rather than a side effect of some internal global locks. Ross From xen-devel-bounces@lists.xenproject.org Thu Apr 02 08:48:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 08:48:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271323.1559532 (Exim 4.92) (envelope-from ) id 1w8DiW-0000y7-MV; Thu, 02 Apr 2026 08:47:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271323.1559532; Thu, 02 Apr 2026 08:47:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8DiW-0000y0-JC; Thu, 02 Apr 2026 08:47:56 +0000 Received: by outflank-mailman (input) for mailman id 1271323; Thu, 02 Apr 2026 08:47:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8DiV-0000xu-Hu for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 08:47:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8DiU-007MfG-SW for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:54 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce2d2c-bab6-0a2a0a5309dd-0a2a45058858-34 for ; Thu, 02 Apr 2026 10:47:54 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce2d3a-3760-0a2a45050019-d155802ca8c1-3 for ; Thu, 02 Apr 2026 10:47:54 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-482f454be5bso18173545e9.0 for ; Thu, 02 Apr 2026 01:47:54 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 02 Apr 2026 01:47:54 -0700 (PDT) Message-ID: <97bfb299-a465-48a3-a036-f217de683c2c@suse.com> Date: Thu, 2 Apr 2026 10:47:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 From: Jan Beulich To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775119674-3153B96F-47482C8D/0/0 X-purgate-type: clean X-purgate-size: 925 On 02.04.2026 10:39, Jan Beulich wrote: > On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >> The xl dmesg output (from MTL this time): >> >> (XEN) [ 123.477511] Entering ACPI S3 state. >> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > > XEN_ARAT being off is the one odd aspect here. That'll want tracking down > separately. As per xen-cpuid output (below) ARAT is available. For this you may want to also add logging to intel_init_arat(): Since opt_arat can be false only due to command line option use, it can only be the function not being called (which looks impossible on plain staging code), or cpu_has_arat being false despite the xen-cpuid output that you supplied earlier (inexplicable as well, at least for now). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <17c4e7b4-297a-4bf9-9160-659723d15e48@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775119792-94962497-DF860817/0/0 X-purgate-type: clean X-purgate-size: 2881 On 02.04.2026 10:40, Ross Lagerwall wrote: > On 4/2/26 7:09 AM, Jan Beulich wrote: >> On 01.04.2026 18:35, Ross Lagerwall wrote: >>> We have observed that the TLB flush lock can be a point of contention for >>> certain workloads, e.g. migrating 10 VMs off a host during a host evacuation. >>> >>> Performance numbers: >>> >>> I wrote a synthetic benchmark to measure the performance. The benchmark has one >>> or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in >>> the selected mask. The executed function simply delays for 500 microseconds. >>> >>> The table below shows the % change in execution time of on_selected_cpus(): >>> >>> 1 thread 2 threads 4 threads >>> 1 CPU in mask 0.02 -35.23 -51.18 >>> 2 CPUs in mask 0.01 -47.20 -69.27 >>> 4 CPUs in mask -0.02 -42.40 -66.55 >>> 8 CPUs in mask -0.03 -47.82 -68.39 >>> 16 CPUs in mask 0.12 -41.95 -58.26 >>> 32 CPUs in mask 0.02 -25.43 -39.35 >>> 64 CPUs in mask 0.00 -24.70 -37.83 >>> >>> With 1 thread (i.e. no contention), there is no regression in execution time. >>> With multiple threads, as expected there is a significant improvement in >>> execution time. >>> >>> As a more practical benchmark to simulate host evacuation, I measured the >>> memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, >>> so without PML). The rate increased by 16% with this patch series, even >>> after the recent deferred TLB flush changes. >> >> Is this a positive thing though? In the context of some related work something >> similar was mentioned iirc, accompanied by stating that this is actually >> problematic. A guest in log-dirty mode generally wants to be making progress, >> but also wants to be throttled enough to limit re-dirtying, such that >> subsequent iterations (in particular the final one) of page contents >> migration won't have to process overly many pages a 2nd time. > > In the context of a real migration, both the process copying the pages > out of the guest and the guest itself will be hitting the TLB flush lock > so reducing that bottleneck may increase throughput on both sides. > Whether or not the overall migration time increases or decreases depends > on many factors (number of migrations in parallel, the rate the guest is > dirtying memory, the line speed of the NIC, whether PML is used, ...) > which is why I measured a more controlled scenario to demonstrate the > change. > > IMO throttling of a guest during a migration should be something > intentional and controlled by userspace policy rather than a side effect > of some internal global locks. I definitely agree here, but side effects going away may make it necessary to add such explicit throttling. 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To: Jan Beulich , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> <5310a923-ab2c-478f-9854-7542a7940778@suse.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <5310a923-ab2c-478f-9854-7542a7940778@suse.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------imUU5YsKuph0YghZe5yj5YrN" X-purgate-ID: tlsNG-ebf023/1775119832-B052B51B-5BAC7417/0/0 X-purgate-type: clean X-purgate-size: 22106 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------imUU5YsKuph0YghZe5yj5YrN Content-Type: multipart/mixed; boundary="------------5RFojAeVNZF4t0PvMZL8y6Wd"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jan Beulich , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel Message-ID: <65173416-63b1-4721-beec-198673e7d234@suse.com> Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? 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--------------w4lFI0WQ1qH7KVcEkuI9evJP-- --------------5RFojAeVNZF4t0PvMZL8y6Wd-- --------------imUU5YsKuph0YghZe5yj5YrN Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnOLdYFAwAAAAAACgkQsN6d1ii/Ey9S kQf/Wve7BCj6o/NqOU+5RNUSNWpNPruX4dwg2IaCX2513+LRiZx41eHFvoAIgV4AZ4HDU1A0A/x5 5wZwmHQmicfHACYtVuUotCkytOABT5TfQBcIv79t65uFjtcUkJ3AbQKvvzHGyEpix7xFxsc2Ur5B 4PWpC9P3qor0U3Ag26jXu9HOLeLyVoqAFIYPXRg6cfmg1sb4W08jYDewljXeeBdAU4a3G6DDj5/t LRE4GWGgo7OOnGLDXGel7Q6FIYNFhiHl0MuOl9OZ8D9v5/bcmnNIJG30ru+dku2y/SXVBURhEmQy P+oAla16YDD4wq4jZIGq5Oz2bINU4g+uEe65lLXMEQ== =qvXM -----END PGP SIGNATURE----- --------------imUU5YsKuph0YghZe5yj5YrN-- From xen-devel-bounces@lists.xenproject.org Thu Apr 02 09:00:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 09:00:27 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <74f15b1db86139b36b721ef9d12b998fe4f0f348.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775120415-1334C41E-922DAA10/0/0 X-purgate-type: clean X-purgate-size: 1521 On 10.03.2026 18:08, Oleksii Kurochko wrote: > aia_init() is going to contain all the stuff related to AIA initialization. > At the moment, it is just Check if SSAIA extension is available and if yes > set is_aia_available to true. And (future) users of aia_available() can't directly call riscv_isa_extension_available()? Nor can aia_available() be a convenience wrapper around that call? It's only ... > --- /dev/null > +++ b/xen/arch/riscv/aia.c > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +static bool __ro_after_init is_aia_available; ... a boolean, yes, but still. > +bool aia_available(void) > +{ > + return is_aia_available; > +} > + > +int __init aia_init(void) > +{ > + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) > + return -ENODEV; > + > + is_aia_available = true; > + > + return 0; > +} Why the return value, when ... > --- a/xen/arch/riscv/intc.c > +++ b/xen/arch/riscv/intc.c > @@ -8,6 +8,7 @@ > #include > #include > > +#include > #include > > static const struct intc_hw_operations *__ro_after_init intc_hw_ops; > @@ -27,6 +28,8 @@ void __init intc_preinit(void) > > void __init intc_init(void) > { > + aia_init(); ... the sole caller doesn't care? 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DAxEOqDSYZNEEJoQ" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-bad1c0/1775122509-2E155152-A8CA5F06/0/0 X-purgate-type: clean X-purgate-size: 11641 --DAxEOqDSYZNEEJoQ Content-Type: multipart/mixed; protected-headers=v1; boundary="NVNT4aiuL2yDymiY" Content-Disposition: inline Date: Thu, 2 Apr 2026 11:35:05 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 --NVNT4aiuL2yDymiY Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: > On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > > The xl dmesg output (from MTL this time): > >=20 > > (XEN) [ 123.477511] Entering ACPI S3 state. > > (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu= _has_apic: 1 > > (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_dee= p_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually > succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() values > might be a good idea, if only to double check.) Updated output: (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, cpu_has= _apic: 1 (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_deep_cs= tate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events: ffff= 83046bc1f080 (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_used: 8 (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_events[= i].msi.irq: 122, hpet_events[i].flags: 0 (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720649] hpet_broadcast_resume:701: i:0, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720665] hpet_broadcast_resume:711: i:0, cfg: 0xc134 (XEN) [18446743899.720674] hpet_broadcast_resume:697: i:1, hpet_events[= i].msi.irq: 123, hpet_events[i].flags: 0 (XEN) [18446743899.720684] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x130 (XEN) [18446743899.720707] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720717] hpet_broadcast_resume:701: i:1, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720728] hpet_broadcast_resume:711: i:1, cfg: 0xc104 (XEN) [18446743899.720737] hpet_broadcast_resume:697: i:2, hpet_events[= i].msi.irq: 124, hpet_events[i].flags: 0 (XEN) [18446743899.720747] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x150 (XEN) [18446743899.720771] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720781] hpet_broadcast_resume:701: i:2, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720797] hpet_broadcast_resume:711: i:2, cfg: 0xc104 (XEN) [18446743899.720805] hpet_broadcast_resume:697: i:3, hpet_events[= i].msi.irq: 125, hpet_events[i].flags: 0 (XEN) [18446743899.720816] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x170 (XEN) [18446743899.720838] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720848] hpet_broadcast_resume:701: i:3, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720863] hpet_broadcast_resume:711: i:3, cfg: 0xc104 (XEN) [18446743899.720872] hpet_broadcast_resume:697: i:4, hpet_events[= i].msi.irq: 126, hpet_events[i].flags: 0 (XEN) [18446743899.720882] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x190 (XEN) [18446743899.720905] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720915] hpet_broadcast_resume:701: i:4, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720931] hpet_broadcast_resume:711: i:4, cfg: 0xc104 (XEN) [18446743899.720939] hpet_broadcast_resume:697: i:5, hpet_events[= i].msi.irq: 127, hpet_events[i].flags: 0 (XEN) [18446743899.720949] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x1b0 (XEN) [18446743899.720971] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.720981] hpet_broadcast_resume:701: i:5, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.720997] hpet_broadcast_resume:711: i:5, cfg: 0xc104 (XEN) [18446743899.721006] hpet_broadcast_resume:697: i:6, hpet_events[= i].msi.irq: 128, hpet_events[i].flags: 0 (XEN) [18446743899.721016] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x1d0 (XEN) [18446743899.721039] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.721048] hpet_broadcast_resume:701: i:6, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.721064] hpet_broadcast_resume:711: i:6, cfg: 0xc104 (XEN) [18446743899.721072] hpet_broadcast_resume:697: i:7, hpet_events[= i].msi.irq: 129, hpet_events[i].flags: 0 (XEN) [18446743899.721082] hpet_msi_write:283: iommu_intremap: 2 (iommu= _intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x1f0 (XEN) [18446743899.721105] hpet_msi_write:287: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743899.721115] hpet_broadcast_resume:701: i:7, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743899.721130] hpet_broadcast_resume:711: i:7, cfg: 0xc104 And the current debug diff attached. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --NVNT4aiuL2yDymiY Content-Type: text/plain; charset=utf-8 Content-Disposition: attachment; filename=xen-debug.diff Content-Transfer-Encoding: quoted-printable diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae435..9916afd5ed68 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -364,6 +364,7 @@ static void __init calculate_host_policy(void) struct cpu_policy *p =3D &host_cpu_policy; unsigned int max_extd_leaf; =20 + printk("%s:%d\n", __func__, __LINE__); *p =3D raw_cpu_policy; =20 p->basic.max_leaf =3D diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 18b3c79dc97f..51a3d1c4b5f3 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -671,6 +671,7 @@ const struct cpu_dev __initconst_cf_clobber intel_cpu_d= ev =3D { =20 void __init intel_init_arat(void) { + printk("%s:%d: opt_arat: %d, cpu_has_arat: %d\n", __func__, __LINE__, = opt_arat, cpu_has_arat); if ( opt_arat && cpu_has_arat ) setup_force_cpu_cap(X86_FEATURE_XEN_ARAT); } diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c index 1ea8ae457424..7731654efa9b 100644 --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -280,9 +280,11 @@ static int hpet_msi_write(struct hpet_event_channel *c= h, struct msi_msg *msg) { ch->msi.msg =3D *msg; =20 + printk("%s:%d: iommu_intremap: %d (iommu_intremap_off: %d), HPET_Tn_RO= UTE(ch->idx): %#x\n", __func__, __LINE__, iommu_intremap, iommu_intremap_of= f, HPET_Tn_ROUTE(ch->idx)); if ( iommu_intremap !=3D iommu_intremap_off ) { int rc =3D iommu_update_ire_from_msi(&ch->msi, msg); + printk("%s:%d: iommu_update_ire_from_msi rc: %d\n", __func__, __LI= NE__, rc); =20 if ( rc < 0 ) return rc; @@ -658,6 +660,8 @@ void hpet_broadcast_resume(void) u32 cfg; unsigned int i, n; =20 + printk("%s:%d: hpet_events: %p\n", __func__, __LINE__, hpet_events); + if ( !hpet_events ) return; =20 @@ -667,25 +671,35 @@ void hpet_broadcast_resume(void) =20 if ( num_hpets_used > 0 ) { + printk("%s:%d: num_hpets_used: %d\n", __func__, __LINE__, num_hpet= s_used); /* Stop HPET legacy interrupts */ cfg &=3D ~HPET_CFG_LEGACY; n =3D num_hpets_used; } else if ( hpet_events->flags & HPET_EVT_DISABLE ) + { + printk("%s:%d: hpet_events->flags: %#x\n", __func__, __LINE__, hpe= t_events->flags); return; + } else { /* Start HPET legacy interrupts */ + printk("%s:%d\n", __func__, __LINE__); cfg |=3D HPET_CFG_LEGACY; n =3D 1; } =20 + printk("%s:%d: cfg: %#x\n", __func__, __LINE__, cfg); hpet_write32(cfg, HPET_CFG); =20 for ( i =3D 0; i < n; i++ ) { + printk("%s:%d: i:%d, hpet_events[i].msi.irq: %d, hpet_events[i].fl= ags: %#x\n", __func__, __LINE__, i, hpet_events[i].msi.irq, hpet_events[i].= flags); if ( hpet_events[i].msi.irq >=3D 0 ) - __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); + { + int ret =3D __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].ms= i.irq)); + printk("%s:%d: i:%d, __hpet_setup_msi_irq ret: %d\n", __func__= , __LINE__, i, ret); + } =20 /* set HPET Tn as oneshot */ cfg =3D hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); @@ -694,6 +708,7 @@ void hpet_broadcast_resume(void) if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) cfg |=3D HPET_TN_FSB; hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); + printk("%s:%d: i:%d, cfg: %#x\n", __func__, __LINE__, i, cfg); =20 hpet_events[i].next_event =3D STIME_MAX; } diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index fed30a919d2c..15113ebdfb6c 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2646,6 +2646,7 @@ static int _disable_pit_irq(bool init) { int ret =3D 1; =20 + printk("%s:%d: using_pit: %d, cpu_has_apic: %d\n", __func__, __LINE__,= using_pit, cpu_has_apic); if ( using_pit || !cpu_has_apic ) return -1; =20 @@ -2655,8 +2656,10 @@ static int _disable_pit_irq(bool init) * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast. */ + printk("%s:%d: cpuidle_using_deep_cstate: %d, boot_cpu_has(X86_FEATURE= _XEN_ARAT): %d\n", __func__, __LINE__, cpuidle_using_deep_cstate(), boot_cp= u_has(X86_FEATURE_XEN_ARAT)); if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT= ) ) { + printk("%s:%d: init: %d\n", __func__, __LINE__, init); init ? hpet_broadcast_init() : hpet_broadcast_resume(); if ( !hpet_broadcast_is_available() ) { diff --git a/xen/source b/xen/source new file mode 120000 index 000000000000..945c9b46d684 --- /dev/null +++ b/xen/source @@ -0,0 +1 @@ +. \ No newline at end of file --NVNT4aiuL2yDymiY-- --DAxEOqDSYZNEEJoQ Content-Type: application/pgp-signature; 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b=VwMhdCqGOsyUJWgBxffbw/0rY4PWAL4JiJEyflejTG68aZyCi6w TnHHgTB8YjaILIthSIeZPzhpWMl9a0X0+DpaipjgwkctcPlRP4y5igt76w7X9pH2 fu3ySfMvFzpCaa5u5EFNvlNouWx4JC0EYXLDzvi/NofGP1f5lw8Y3cn4Gg1qzOYo VZlQ04kBa8qye1kz+SghFZHphQL6RsQRYuKevfxQ2Hk9ipaJ2OrvAUpaGpPyKeE2 O3Bfjuo8zKZm2kP0ekGoypure1j0trvfp5Iuru2AqLJJW2gAgR8cMKMwjsHh6QNr nnvxUra7xj3CGvm7vy/+zJte+qnHHI8lP5A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefhedrtddtgdehieelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfurfetoffkrfgpnffqhgenuceurghi lhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurh epfffhvfevuffkfhggtggujgesghdtreertddtjeenucfhrhhomhepofgrrhgvkhcuofgr rhgtiiihkhhofihskhhiqdfikphrvggtkhhiuceomhgrrhhmrghrvghksehinhhvihhsih gslhgvthhhihhnghhslhgrsgdrtghomheqnecuggftrfgrthhtvghrnhepgfduleetfeev hfefheeiteeliefhjefhleduveetteekveettddvgeeuteefjedunecuvehluhhsthgvrh fuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmhgrrhhmrghrvghksehinhhv ihhsihgslhgvthhhihhnghhslhgrsgdrtghomhdpnhgspghrtghpthhtohepvddpmhhoug gvpehsmhhtphhouhhtpdhrtghpthhtohepjhgsvghulhhitghhsehsuhhsvgdrtghomhdp rhgtphhtthhopeigvghnqdguvghvvghlsehlihhsthhsrdigvghnphhrohhjvggtthdroh hrgh X-ME-Proxy: Feedback-ID: i1568416f:Fastmail Date: Thu, 2 Apr 2026 11:42:52 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 Message-ID: References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <97bfb299-a465-48a3-a036-f217de683c2c@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="mx62jTLu5jLR+11M" Content-Disposition: inline In-Reply-To: <97bfb299-a465-48a3-a036-f217de683c2c@suse.com> X-purgate-ID: tlsNG-bad1c0/1775122976-5475A152-DA4A2FFE/0/0 X-purgate-type: clean X-purgate-size: 2580 --mx62jTLu5jLR+11M Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 2 Apr 2026 11:42:52 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Thu, Apr 02, 2026 at 10:47:53AM +0200, Jan Beulich wrote: > On 02.04.2026 10:39, Jan Beulich wrote: > > On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > >> The xl dmesg output (from MTL this time): > >> > >> (XEN) [ 123.477511] Entering ACPI S3 state. > >> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cp= u_has_apic: 1 > >> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_de= ep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >=20 > > XEN_ARAT being off is the one odd aspect here. That'll want tracking do= wn > > separately. As per xen-cpuid output (below) ARAT is available. >=20 > For this you may want to also add logging to intel_init_arat(): Since opt= _arat > can be false only due to command line option use, it can only be the func= tion > not being called (which looks impossible on plain staging code), or cpu_h= as_arat > being false despite the xen-cpuid output that you supplied earlier (inexp= licable > as well, at least for now). Hm, I got this: (XEN) [ 11.403340] intel_init_arat:674: opt_arat: 1, cpu_has_arat: 0 so, cpu_has_arat=3D0 ... next lines are those, to hint when it happened in the boot process: (XEN) [ 11.409754] mwait-idle: MWAIT substates: 0x11112020 (XEN) [ 11.416130] mwait-idle: v0.4.1 model 0xaa (XEN) [ 11.422396] mwait-idle: lapic_timer_reliable_states 0x2 Looks like calculate_host_policy() runs much later... --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --mx62jTLu5jLR+11M Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnOOhwACgkQ24/THMrX 1yxpOAf+M+z16dMhGpvaOF7lRARXqYIX2Ln+S+KJG2vz60SjG/NPwZGR/YB6QtOI JxXNxyfyOT9FTOUOG2jqBRP+JMoSmwTkebm1Y/fCLDPggJQ8cLXTjSOlRpyYR1bf ssIME+HAgBgy6fWxAAeGPQWA9vmW62QdJvyOf0KQtOQazpyM8tYcZjjMux0wJXMr dEiq3VpbMI0wB0HfQQAUYLzYSV64VKQc1SEhFsLjKM5U3BJ5fsbKSfia2na/u4YS UDe0TPXRS3uHLdcQPOmrwfiMrwrfG/WWsywLlCozAwCJb0ga8qJO6J7Jj4IvTwu/ 5N/1Aq5P7TPuNQsAX13+0d3urQ49fQ== =Wwtv -----END PGP SIGNATURE----- --mx62jTLu5jLR+11M-- From xen-devel-bounces@lists.xenproject.org Thu Apr 02 09:59:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 09:59:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271437.1559602 (Exim 4.92) (envelope-from ) id 1w8EpF-0004rl-08; Thu, 02 Apr 2026 09:58:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271437.1559602; Thu, 02 Apr 2026 09:58:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8EpE-0004re-TB; Thu, 02 Apr 2026 09:58:56 +0000 Received: by outflank-mailman (input) for mailman id 1271437; Thu, 02 Apr 2026 09:58:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8EpD-0004rY-S1 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 09:58:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8EpB-004b1f-MO for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 11:58:55 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce3dd2-5cb7-0a2a0a5109dd-0a2a4508b1ae-34 for ; Thu, 02 Apr 2026 11:58:55 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce3ddd-fab6-0a2a45080019-a0658308d9ec-3 for ; Thu, 02 Apr 2026 11:58:54 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id BF8514270A5C; Thu, 2 Apr 2026 05:58:15 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: bernhard.kaindl@gmail.com, xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] docs: Add Draft Design Documentation for NUMA-aware claim sets Date: Thu, 2 Apr 2026 10:57:35 +0100 Message-Id: <40bc3d33bda11ac8526a50e8165aef1e8642c719.1775123578.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775123934-F6D4B737-C0001AD6/0/0 X-purgate-type: clean X-purgate-size: 97289 The NUMA-aware claims v4 series allowed a domain to claim memory on a single NUMA node, but not across multiple nodes. There was no strong practical need for multi-node claims at the time, as customers generally saw the best performance when domains were aligned 1:1 with NUMA nodes. Jan hinted that a multi-node implementation would look quite different, and also Roger Pau Monné proposed this design earlier: https://lists.xenproject.org/archives/html/xen-devel/2025-06/msg00484.html Quote: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. This is a significant change, and so this design document is intended to provide a reference for the rationale behind the design decisions, and to support review of the implementation. It is integrated into the Sphinx documentation for the Xen hypervisor below ./docs/designs, and is structured in a way that allows readers to easily navigate to the sections that are most relevant to them. It uses Sphinx's integrated C domain, which makes it possible to create surprisingly comprehensive documentation for C code, including function signatures, parameters, return values and types. For reference: https://www.sphinx-doc.org/en/master/usage/domains/c.html Suggested-by: Jan Beulich Suggested-by: Roger Pau Monné Signed-off-by: Bernhard Kaindl -- Dear reviewers, for convenience, the rendered design document is available here for review: https://bernhard-xen.readthedocs.io/en/claim-sets-v1-design/designs/claims/ The Sphinx site can be built and viewed locally with the following commands: git pull git@gitlab.com:bernhardkaindl/xen.git claim-sets-v1-design make -C docs sphinx-env-build # xdg-open docs/sphinx/html/index.html or start a minimal HTTP server: (cd docs/sphinx/html; python -m http.server) The specific acknowledgements are included in the design document. Many thanks to everyone who has contributed to the previous work and implementation of this feature, and to everyone who will review it. Best regards, Bernhard --- .readthedocs.yaml | 4 +- docs/.gitignore | 1 + docs/Makefile | 12 +- docs/conf.py | 36 +- docs/designs/claims/accounting.rst | 270 ++++++++++ docs/designs/claims/design.rst | 330 ++++++++++++ docs/designs/claims/edge-cases.rst | 24 + docs/designs/claims/history.rst | 82 +++ docs/designs/claims/implementation.rst | 502 ++++++++++++++++++ docs/designs/claims/index.rst | 43 ++ docs/designs/claims/installation.rst | 122 +++++ docs/designs/claims/invariants.mmd | 36 ++ docs/designs/claims/protection.rst | 41 ++ docs/designs/claims/retirement.rst | 70 +++ docs/designs/claims/usecases.rst | 39 ++ docs/designs/index.rst | 16 + docs/designs/launch/hyperlaunch.rst | 4 +- .../dom/DOMCTL_claim_memory-data.mmd | 43 ++ .../dom/DOMCTL_claim_memory-seqdia.mmd | 23 + .../dom/DOMCTL_claim_memory-workflow.mmd | 23 + docs/guest-guide/dom/DOMCTL_claim_memory.rst | 81 +++ docs/guest-guide/dom/index.rst | 14 + docs/guest-guide/index.rst | 23 + docs/guest-guide/mem/XENMEM_claim_pages.rst | 100 ++++ docs/guest-guide/mem/index.rst | 12 + docs/hypervisor-guide/index.rst | 7 + docs/index.rst | 7 +- 27 files changed, 1955 insertions(+), 10 deletions(-) create mode 100644 docs/designs/claims/accounting.rst create mode 100644 docs/designs/claims/design.rst create mode 100644 docs/designs/claims/edge-cases.rst create mode 100644 docs/designs/claims/history.rst create mode 100644 docs/designs/claims/implementation.rst create mode 100644 docs/designs/claims/index.rst create mode 100644 docs/designs/claims/installation.rst create mode 100644 docs/designs/claims/invariants.mmd create mode 100644 docs/designs/claims/protection.rst create mode 100644 docs/designs/claims/retirement.rst create mode 100644 docs/designs/claims/usecases.rst create mode 100644 docs/designs/index.rst create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory.rst create mode 100644 docs/guest-guide/dom/index.rst create mode 100644 docs/guest-guide/mem/XENMEM_claim_pages.rst create mode 100644 docs/guest-guide/mem/index.rst diff --git a/.readthedocs.yaml b/.readthedocs.yaml index d3aff7662ebf..f6dbb4ffa86f 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -12,7 +12,9 @@ build: jobs: post_install: # Instead of needing a separate requirements.txt - - python -m pip install --upgrade --no-cache-dir sphinx-rtd-theme + - > + python -m pip install --upgrade --no-cache-dir sphinx-rtd-theme + sphinxcontrib-mermaid sphinx: configuration: docs/conf.py diff --git a/docs/.gitignore b/docs/.gitignore index c3ce50335ae6..80c3d14ede69 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,3 +1,4 @@ +/.sphinx/ /figs/*.png /html/ /man/xl.cfg.5.pod diff --git a/docs/Makefile b/docs/Makefile index 8e68300e3b44..47e9f366ce7a 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -55,6 +55,16 @@ build: html txt pdf man-pages figs sphinx-html: sphinx-build -b html . sphinx/html +# Sphinx build target that sets up a virtual environment and installs +# dependencies. This is intended for use by developers who want to build +# the Sphinx documentation locally. Keep it the dependencies in sync with +# .readthedocs.yaml. +sphinx-env-build: + if [ ! -d .sphinx ]; then python -m venv .sphinx; fi + . .sphinx/bin/activate && \ + pip install sphinx-rtd-theme sphinxcontrib-mermaid && \ + $(MAKE) sphinx-html + .PHONY: html html: $(DOC_HTML) html/index.html @@ -76,7 +86,7 @@ pdf: $(DOC_PDF) clean: clean-man-pages $(MAKE) -C figs clean rm -rf .word_count *.aux *.dvi *.bbl *.blg *.glo *.idx *~ - rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core + rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core .sphinx rm -rf html txt pdf sphinx/html .PHONY: distclean diff --git a/docs/conf.py b/docs/conf.py index 2fb8bafe6589..5e51df6a21b9 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -61,7 +61,33 @@ needs_sphinx = '1.4' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = [] +extensions = ["sphinx.ext.autosectionlabel"] + +try: + import sphinxcontrib.mermaid +except ImportError: + sys.stderr.write(""" + Warning: The Sphinx 'sphinxcontrib.mermaid' extension was not found. + Make sure you have the extension installed to render mermaid diagrams + in the documentation. On Debian-based systems, you can install it with: + sudo apt install python3-sphinxcontrib-mermaid\n + In any case, after installing pipx, you can install the latest versions + of sphinx and the needed extras in an isolated environment with:\n + pipx install sphinx + pipx inject sphinx sphinxcontrib-mermaid sphinx-rtd-theme\n + """) +else: + extensions.append("sphinxcontrib.mermaid") + +# Extension options + +# sphinxcontrib.mermaid +mermaid_init_js = """ +mermaid.initialize({ startOnLoad: true }); +""" + +# sphinx.ext.autosectionlabel +autosectionlabel_prefix_document = True # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] @@ -82,7 +108,7 @@ language = 'en' # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. -exclude_patterns = [u'sphinx/output', 'Thumbs.db', '.DS_Store'] +exclude_patterns = [u'sphinx/output', 'Thumbs.db', '.DS_Store', '.sphinx'] # The name of the Pygments (syntax highlighting) style to use. pygments_style = None @@ -99,7 +125,11 @@ highlight_language = 'none' try: import sphinx_rtd_theme html_theme = 'sphinx_rtd_theme' - html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] + # The sphinx_rtd_theme package versions prior to 3.0.0 require the theme + # path to be added to html_theme_path, while newer are warning about it: + # https://sphinx-rtd-theme.readthedocs.io/en/stable/changelog.html#deprecations + if sphinx_rtd_theme.__version__.split('.') < ['3', '0', '0']: + html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] except ImportError: sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n') diff --git a/docs/designs/claims/accounting.rst b/docs/designs/claims/accounting.rst new file mode 100644 index 000000000000..79843406d92a --- /dev/null +++ b/docs/designs/claims/accounting.rst @@ -0,0 +1,270 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Claims Accounting +----------------- + +.. contents:: Table of Contents + :local: + +.. note:: + Claims accounting state is only updated while holding :c:expr:`heap_lock`. + See :ref:`designs/claims/accounting:Locking of claims accounting` + for details on the locks used to protect claims accounting state. + +This section formalizes the internal state and invariants that Xen must +maintain to ensure correctness. + +For readers following the design in order, the preceding sections are: + +1. :doc:`/designs/claims/design` introduces the overall model and goals. +2. :doc:`/designs/claims/installation` explains how claim sets are installed. +3. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +4. :doc:`/designs/claims/retirement` explains how claims are retired as + allocations succeed. + +Overview +^^^^^^^^ + +.. table:: Table 1: Claims accounting - All accesses, Aggregate state, + and invariants protected by :c:expr:`heap_lock`. + :widths: auto + + ============ ======================================= ======================= + Level Claims must be lower or equal to Available memory + ============ ======================================= ======================= + Node :c:expr:`node_outstanding_claims[node]` :c:expr:`node_avail_pages[node]` + Aggregate state: + + Over all domains: + + SUM(:c:expr:`domain.claims[node]`) + Global :c:expr:`outstanding_claims` = :c:expr:`total_avail_pages` = + Aggregate state: Aggregate state: + + SUM() over all domains: SUM() over all nodes: + + :c:expr:`domain.global_claims` + :c:expr:`node_avail_pages[]` + :c:expr:`domain.node_claims` + + Also, the sum over all nodes: + + :c:expr:`node_outstanding_claims[*]` + Dom global :c:expr:`domain.global_claims` :c:expr:`total_avail_pages` + Dom per-node :c:expr:`domain.claims[node]` :c:expr:`node_avail_pages[node]` + Dom slow tot :c:expr:`domain.global_claims` + :c:expr:`total_avail_pages` + SUM(:c:expr:`domain.claims[node]`) + Aggregate: :c:expr:`domain.node_claims` = + SUM(:c:expr:`domain.claims[node]`) + Domain total :c:expr:`domain.global_claims` :c:expr:`total_avail_pages` + + :c:expr:`domain.node_claims` + Domain mem :c:expr:`domain_tot_pages(domain)` Invariant: must be + - plus :c:expr:`domain.global_claims` lower or equal to + + + plus :c:expr:`domain.node_claims` :c:expr:`domain.max_pages` + ============ ======================================= ======================= + +Claims accounting state +^^^^^^^^^^^^^^^^^^^^^^^ + +When installing claims and retiring them during allocation, the page +allocator updates: + +:c:expr:`domain.global_claims` + The domain's global claim. + +:c:expr:`domain.claims[MAX_NUMNODES]` + The domain's claims for specific NUMA nodes, indexed by node ID. + +Aggregate state +^^^^^^^^^^^^^^^ + +Xen also maintains aggregate state for fast checks in allocator hot paths: + +:c:expr:`outstanding_claims`: + The sum of all claims across all domains for global and node claims. + +:c:expr:`node_outstanding_claims[MAX_NUMNODES]`: + The sum of all claims across all domains for specific NUMA nodes, indexed + by node ID, used for efficient checks in the allocator hot paths to ensure + that node claims do not exceed the available memory on the respective node. + +:c:expr:`domain.node_claims`: + The total of the domain's node claims, + equal to the sum of :c:expr:`domain.claims[MAX_NUMNODES]` for all nodes + and used for efficient checks in the allocator. + +:c:expr:`domain_tot_pages(domain)` + The total pages allocated to the domain, used for validating that claims do + not exceed the domain's maximum page limits. This is the sum of the + domain's global claim and node claims, i.e. :c:expr:`domain.global_claims` + + :c:expr:`domain.node_claims`. + +Claims accounting invariants +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Xen must maintain the following invariants: + +- Global claims: + :c:expr:`outstanding_claims` :math:`\le` :c:expr:`total_avail_pages` + +- Node claims: + :c:expr:`node_outstanding_claims[alloc_node]` :math:`\le` + :c:expr:`node_avail_pages[alloc_node]` +- Domain claims: + :c:expr:`domain.global_claims` + :c:expr:`domain.node_claims` + + :c:expr:`domain_tot_pages(domain)` :math:`\le` :c:expr:`domain.max_pages` + + See :doc:`retirement` for details on the latter invariant. + +Locking of claims accounting +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. c:alias:: domain.page_alloc_lock + +.. c:var:: spinlock_t heap_lock + + Lock for all heap operations including claims. It protects the claims state + and invariants from concurrent updates and ensures that checks in the + allocator hot paths see a consistent view of the claims state. + + If :c:expr:`domain.page_alloc_lock` is needed to check + :c:expr:`domain_tot_pages(domain)` on top of new claims against + :c:expr:`domain.max_pages` for the domain, it needs to be taken + before :c:expr:`heap_lock` for consistent locking order to avoid deadlocks. + +Variables and data structures +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. c:type:: uint8_t nodeid_t + + Type for :term:`NUMA node` IDs. The :c:expr:`memflags` variable of + :c:expr:`xc_populate_physmap()` and related functions for populating + the :term:`physmap` allocates 8 bits in the flags for the node ID, which + limits the theoretical maximum value of ``CONFIG_NR_NUMA_NODES`` at 254, + which is far beyond the current maximum of 64 supported by Xen and should + be sufficient for the foreseeable future. + +.. c:macro:: MAX_NUMNODES + + The maximum number of NUMA nodes supported by Xen. Used for validating + node IDs in the :c:expr:`memory_claim_t` entries of claim sets. + When Xen is built without NUMA support, it is 1. + The default on x86_64 is 64 which is sufficient for current hardware and + allows for efficient storage of e.g. the :c:expr:`node_online_map` for + online nodes and :c:expr:`domain.node_affinity` in a single 64-bit value, + and in the :c:expr:`domain.claims[MAX_NUMNODES]` array. + + ``xen/arch/Kconfig`` limits the maximum number of NUMA nodes to 64. While + Xen can be compiled for up to 254 nodes, configuring machines to split + the installed memory into more than 64 nodes would be unusual. + For example, dual-socket servers, even when using multiple chips per CPU + package should typically be configured for 2 NUMA nodes by default. + +.. c:var:: long total_avail_pages + + Total available pages in the system, including both free and claimed pages. + This is used for validating that global claims do not exceed the total + available memory in the system. + +.. c:var:: long outstanding_claims + + The total global claims across all domains. This is maintained for + efficient checks in the allocator hot paths to ensure the global claims + invariant that total claims do not exceed the total available memory is not + violated. + +.. c:var:: long node_avail_pages[MAX_NUMNODES] + + Available pages for each NUMA node, including both free and claimed pages. + This is used for validating that node claims do not exceed the available + memory on the respective NUMA node. + +.. c:var:: long node_outstanding_claims[MAX_NUMNODES] + + The total claims across all domains for each NUMA node, indexed by node + ID. This is maintained for efficient checks in the allocator hot paths. + +.. c:macro:: domain_tot_pages(domain) + + The total pages allocated to the domain, used for validating that this + allocation and the domain's claims do not exceed :c:expr:`domain.max_pages`. + +.. c:struct:: domain + + .. c:member:: unsigned int global_claims + + The domain's global claim, representing the number of pages claimed + globally for the domain. + + .. c:member:: unsigned int node_claims + + The total of the domain's node claims, equal to the sum of + :c:expr:`claims` for all nodes. + It is maintained for efficient checks in the allocator hot paths + without needing to sum over the per-node claims each time. + + .. c:member:: unsigned int claims[MAX_NUMNODES] + + The domain's claims for each :term:`NUMA node`, indexed by node ID. + + As :c:expr:`domain` is allocated using a dedicated page for each domain, + this allows for efficient and fast storage with direct indexing without + consuming any additional memory for an additional allocation. + + The page allocated for struct :c:expr:`domain` is large enough + to accommodate this array several times, even beyond the current + :c:expr:`MAX_NUMNODES` limit of 64, so it should be sufficient even + for future expansion of the maximum number of supported NUMA nodes + if needed. The allocation has a build-time assertion for safety to + ensure that struct :c:expr:`domain` fits within the allocated page. + + The sum of these claims is stored in :c:expr:`domain.node_claims` + for efficient checks in the allocator hot paths which need to know + the total number of node claims for the :term:`domain`. + + .. c:member:: unsigned int max_pages + + The maximum number of pages the domain is allowed to claim, set at + domain creation time. + + .. c:member:: rspinlock_t page_alloc_lock + + Lock for checking :c:expr:`domain_tot_pages(domain)` on top of new claims + against :c:expr:`domain.max_pages` when installing these new claims. + This is a recursive spinlock to allow for nested calls into the allocator + while holding it, such as when retiring claims during page allocation. + It is taken before :c:expr:`heap_lock` when installing claims to ensure a + consistent locking order and may not be taken while holding + :c:expr:`heap_lock` to avoid deadlocks. + + .. c:member:: nodemask_t node_affinity + + A :c:expr:`nodemask_t` representing the set of NUMA nodes the domain + is affine to. This is used for efficient checks in the allocator hot + paths to quickly get the set of nodes a domain is affine to for + memory allocation decisions. + +.. c:type:: nodemask_t + + A bitmap representing a set of NUMA nodes, used for status information + like :c:expr:`node_online_map` and the :c:expr:`domain.node_affinity` + and to track which nodes are online and which nodes are in a domain's + node affinity. + +.. c:var:: nodemask_t node_online_map + + A bitmap representing which NUMA nodes are currently online in the system. + This is used for validating that claims are only made for online nodes and + for efficient checks in the allocator hot paths to quickly determine which + nodes are online. Currently, Xen does not support hotplug of NUMA nodes, + so this is set at boot time based on the platform firmware configuration + and does not change at runtime. + +Claims Accounting Diagram +^^^^^^^^^^^^^^^^^^^^^^^^^ + +This diagram illustrates the claims accounting state and the invariants: + +.. mermaid:: invariants.mmd + :caption: Diagram: Claims accounting state and invariants diff --git a/docs/designs/claims/design.rst b/docs/designs/claims/design.rst new file mode 100644 index 000000000000..8d313da2387e --- /dev/null +++ b/docs/designs/claims/design.rst @@ -0,0 +1,330 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +############# +Claims Design +############# + +.. contents:: Table of Contents + :backlinks: entry + :local: + +************ +Introduction +************ + +Xen's page allocator supports a :term:`claims` API that allows privileged +:term:`domain builders` to reserve an amount of available memory before +:term:`populating` the :term:`guest physical memory` of new :term:`domains` +they are creating, configuring and building. + +These reservations are called :term:`claims`. They ensure that the claimed +memory remains available for the :term:`domains` when allocating it, even +if other :term:`domains` are allocating memory at the same time. + +:term:`Installing claims` is a privileged operation performed by +:term:`domain builders` before they populate the :term:`guest physical memory`. +This prevents other :term:`domains` from allocating memory earmarked +for :term:`domains` under construction. Xen maintains the per-domain +claim state for pages that are claimed but not yet allocated. + +When claim installation succeeds, Xen updates the claim state to reflect +the new targets and protects the claimed memory until it is allocated or +the claim is released. As Xen allocates pages for the domain, claims are +retired by reducing the claim state by the size of each allocation. + +************ +Design Goals +************ + +The design's primary goals are: + +1. Allow :term:`domain builders` to claim memory + on multiple :term:`NUMA nodes` using a :term:`claim set` atomically. + +2. Preserve the existing :c:expr:`XENMEM_claim_pages` hypercall command + for compatibility with existing :term:`domain builders` and its legacy + semantics, while introducing a new, unrestricted hypercall command for + new use cases such as NUMA-aware claim sets. + +3. Global claims are supported for compatibility with existing domain builders + and for use cases where a flexible claim that can be satisfied from any node + is desirable, such as on UMA machines or as a fallback for memory that comes + available on any node. This means we cannot remove or replace the legacy + global claim call nor the needed variables maintaining the global claim + state. They are still very much needed: claims are not just for NUMA use + cases, but for :term:`parallel domain builds` in general. + + Only on UMA machines is a global claim the same as a claim on node 0, + but the same is not true for NUMA machines, where global claims can claim + more memory than any single node, and the global claim can be used as a + flexible fallback for claiming memory on any node, which can be useful + when preferred NUMA node(s) should be claimed, but may have insufficient + free memory at the time of claim installation, and the global claim can + ensure that the shortfall is available from any node. + +4. Use fast allocation-time claims protection in the allocator's hot paths + to protect claimed memory from parallel allocations from other domain + builders in case of parallel domain builds, and to protect claimed + memory from allocations from already running domains. + +*************** +Design Overview +*************** + +The legacy :ref:`XENMEM_claim_pages` hypercall is superseded by +:c:expr:`XEN_DOMCTL_claim_memory`. This hypercall installs a :term:`claim set`. +It is an array of :c:expr:`memory_claim_t` entries, where each entry specifies +a page count and a target: either a specific NUMA node ID or a special selector +(for example, a global or flexible claim). + +Like legacy claims, claim sets are validated and installed under +:c:expr:`domain.page_alloc_lock` and :c:expr:`heap_lock`: Either the entire +set is accepted, or the request fails with no side effects. Repeated calls +to install claims replace any existing claims for the domain rather than +accumulating. + +As installing claim sets after allocations is not a supported use case, +the legacy behaviour of subtracting existing allocations from installed +claims is somewhat surprising and counterintuitive, and page exchanges +make incremental per-node tracking of already-allocated pages on a per-node +basis difficult. Therefore, claim sets do not retain the legacy behaviour of +subtracting existing allocations, optionally on a per-node basis, from the +installed claims across the individual claim set entries. + +Summary: + +- Legacy domain builders can continue to use the previous (now deprecated) + :c:expr:`XENMEM_claim_pages` hypercall command to install single-node claims + with the legacy semantics and, aside from improvements or fixes to global + claims in general, observe no changes in their behaviour. +- Updated domain builders can take advantage of claim sets to install + NUMA-aware :term:`claims` on multiple :term:`NUMA nodes` and/or globally + in a single step. + +For readers following the design in order, the next sections cover the +following topics: + +1. :doc:`/designs/claims/installation` explains how claim sets are installed. +2. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +3. :doc:`/designs/claims/retirement` explains how claims are retired as + allocations succeed. +4. :doc:`/designs/claims/accounting` describes the accounting model that + underpins those steps. + +******************** +Key design decisions +******************** + +.. glossary:: + + :c:expr:`node_outstanding_claims[MAX_NUMNODES]` + Tracks the sum of all claims on a node. :c:expr:`get_free_buddy()` checks + it before scanning zones on a node, so claimed memory is protected from + other allocations. + + :c:expr:`claims_retire_allocation()` + Retires claims in order: First, it retires claims from the allocation node's + claim. If this is not sufficient, it retires claims from the global claim as + a fallback. This allows the global claim to be used as a flexible fallback + for claiming allocations on any node. Finally, remaining claims are retired + from other nodes to prevent the increase of :c:expr:`domain_tot_pages(domain)` + caused by the allocation on top of + :c:expr:`domain.global_claims` and :c:expr:`domain.node_claims` to exceed + :c:expr:`domain.max_pages`. + + :c:expr:`domain.global_claims` (formerly :c:expr:`domain.outstanding_claims`) + Support for :term:`global claims` is maintained for two reasons: first, + for compatibility with existing domain builders, and second, for use cases + where a flexible claim that can be satisfied from any node is desirable. + + When the preferred NUMA node(s) for a domain do not have sufficient free + memory to satisfy the domain's memory requirements, global claims provide + a flexible fallback for the memory shortfall from the preferred node(s) that + can be satisfied from any available node. + + In this case, :term:`domain builders` can exploit a combination of passing + the preferred node to :c:expr:`xc_domain_populate_physmap()` and + :term:`NUMA node affinity` to steer allocations towards the preferred NUMA + node(s), while letting the global claim ensure that the shortfall is + available. + + This allows the domain builder to define a set of desired NUMA nodes to + allocate from and even specify which nodes to prefer for an allocation, + but the claim for the shortfall is flexible, not specific to any node. + +********* +Non-goals +********* + +Legacy behaviours +================= + +Installing claims is a privileged operation performed by domain builders +before they populate guest memory. As such, tracking previous allocations +is not in scope for claims. + +For the following reasons, claim sets do not retain the legacy behaviour +of subtracting existing allocations from installed claims: + +- Xen does not currently maintain a ``d->node_tot_pages[node]`` count, + and the hypercall to exchange extents of memory with new memory makes + such accounting relatively complicated. + +- The legacy behaviour is somewhat surprising and counterintuitive. + Because installing claims after allocations is not a supported use case, + subtracting existing allocations at installation time is unnecessary. + +- Claim sets are a new API and can provide more intuitive semantics + without subtracting existing allocations from installed claims. This + also simplifies the implementation and makes it easier to maintain. + +Versioned hypercall +=================== + +The :term:`domain builders` using the :c:expr:`XEN_DOMCTL_claim_memory` +hypercall also need to use other version-controlled hypercalls which +are wrapped through the :term:`libxenctrl` library. + +Wrapping this call in :term:`libxenctrl` is therefore a practical approach; +otherwise, we would have a mix of version-controlled and unversioned hypercalls, +which could be confusing for API users and for future maintenance. From the +domain builders' viewpoint, it is more consistent to expose the claims +hypercall in the same way as the other calls they use. + +Stable interfaces also have drawbacks: with stable syscalls, Linux needs +to maintain the old interface indefinitely, which can be a maintenance burden +and can limit the ability to make improvements or changes to the interface +in the future. Linux carries many system call successor families, e.g., oldstat, +stat, newstat, stat64, fstatat, statx, with similar examples including openat, +openat2, clone3, dup3, waitid, mmap2, epoll_create1, pselect6 and many more. +Glibc hides that complexity from users by providing a consistent API, but it +still needs to maintain the old system calls for compatibility. + +In contrast, versioned hypercalls allow for more flexibility and evolution of +the API while still providing a clear path to adopt new features. The reserved +fields and reserved bits in the structures of this hypercall allow for many +future extensions without breaking existing callers. + +******** +Glossary +******** + +.. glossary:: + + claims + Reservations of memory for :term:`domains` that are installed by + :term:`domain builders` before :term:`populating` the domain's memory. + Claims ensure that the reserved memory remains available for the + :term:`domains` when allocating it, even if other :term:`domains` are + allocating memory at the same time. + + claim set + An array of :c:expr:`memory_claim_t` entries, each specifying a page count + and a target (either a NUMA node ID or a special value for global claims), + that can be installed atomically for a domain to reserve memory on multiple + NUMA nodes. The chapter on :ref:`designs/claims/installation:claim sets` + provides further information on the structure and semantics of claim sets. + + claim set installation + installing claim sets + installing claims + The process of validating and installing a claim set for a domain under + :c:expr:`domain.page_alloc_lock` and :c:expr:`heap_lock`, ensuring that + either the entire set is accepted and installed, or the request fails with + no side effects. + The chapter on :ref:`designs/claims/installation:claim set installation` + provides further information on the structure and semantics of claim sets. + + domain builders + Privileged entities (such as :term:`toolstacks` in management :term:`domains`) + responsible for constructing and configuring :term:`domains`, including + installing :term:`claims`, :term:`populating` memory, and setting up other + resources before the :term:`domains` are started. + + domains + Virtual machine instances managed by Xen, built by :term:`domain builders`. + + global claims + :term:`claims` that can be satisfied from any NUMA node, required for + compatibility with existing domain builders and for use cases where + strict node-local placement is not required or not possible, such as on + UMA machines or as a fallback for memory that comes available on any node. + + libxenctrl + A library used by :term:`domain builders` running in privileged + :term:`domains` to interact with the hypervisor, including making + hypercalls to install claims and populate memory. + + libxenguest + A library used by :term:`domain builders` running in privileged + :term:`domains` to interact with the hypervisor, including making + hypercalls to install claims and populate memory. + + meminit + The phase of a domain build where the guest's physical memory is populated, + which involves allocating and mapping physical memory for the domain's guest + :term:`physmap`. This should be performed after installing :term:`claims` + to protect the process against parallel allocations of other domain builder + processes in case of parallel domain builds. + + It is implemented in :term:`libxenguest` and optionally installs + :term:`claims` to ensure the claimed memory is reserved before populating + the :term:`physmap` using calls to :c:expr:`xc_domain_populate_physmap()`. + + nodemask + A bitmap representing a set of NUMA nodes, used for status information + like :c:expr:`node_online_map` and the :c:expr:`domain.node_affinity`. + + node + NUMA node + NUMA nodes + A grouping of CPUs and memory in a NUMA architecture. NUMA nodes have + varying access latencies to memory, and NUMA-aware claims allow + :term:`domain builders` to reserve memory on specific NUMA nodes + for performance reasons. Platform firmware configures what constitutes + a NUMA node, and Xen relies on that configuration for NUMA-related features. + + When this design refers to NUMA nodes, it is referring to the NUMA nodes + as defined by the platform firmware and exposed to Xen, initialized at boot + time and not changing at runtime (so far). + + The NUMA node ID is a numeric identifier for a NUMA node, used whenever code + specifies a NUMA node, such as the target of a claim or indexing into arrays + related to NUMA nodes. + + NUMA node IDs start at 0 and are less than :c:expr:`MAX_NUMNODES`. + + Some NUMA nodes may be offline, and the :c:expr:`node_online_map` is used + to track which nodes are online. Currently, Xen does not support hotplug + of NUMA nodes, so the set of online NUMA nodes is determined at boot time + based on the platform firmware configuration and does not change at runtime. + + NUMA node affinity + The preference of a :term:`domain` for a set of NUMA nodes, which can be used + by :term:`domain builders` to guide memory allocation even when not forcing + the buddy allocator to only consider (or prefer) a specific node when + allocating memory, but even a set of preferred NUMA nodes. + + By default, domains have NUMA node auto-affinity, which means their NUMA + node affinity is determined automatically by the hypervisor based on the + CPU affinity of their vCPUs, but it can be disabled and configured. + + guest physical memory + physmap + The mapping of a domain's guest physical memory to the host's + machine address space. The :term:`physmap` defines how the guest's + physical memory corresponds to the actual memory locations on the host. + + populating + The process of allocating and mapping physical memory for a domain's guest + :term:`physmap`, performed by the :term:`domain builders`, preferably after + installing :term:`claims` to protect the process against parallel allocations + of other domain builder processes in case of parallel domain builds. + + toolstacks + Privileged entities (running in privileged :term:`domains`) responsible for + managing :term:`domains`, including building, configuring, and controlling + their lifecycle using :term:`domain builders`. One toolstack may run + multiple :term:`domain builders` in parallel to build multiple :term:`domains` + at the same time. diff --git a/docs/designs/claims/edge-cases.rst b/docs/designs/claims/edge-cases.rst new file mode 100644 index 000000000000..cfb37ef24259 --- /dev/null +++ b/docs/designs/claims/edge-cases.rst @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Handling Edge Cases +------------------- + +Allocations exceeding claims +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +When an allocation exceeds the domain's claims, the allocator must check +whether unclaimed memory can satisfy the remainder of the request before +rejecting the allocation. + +Previously, if a domain's remaining claim did not fully cover a request, +the allocator rejected the allocation even when enough unclaimed memory +existed to satisfy it. + +This forced the :term:`meminit` API to fall back from ``1G`` pages to ``2M`` +and eventually to ``4K`` pages, reducing performance due to higher TLB +pressure and increased page bookkeeping. + +Supporting the use of unclaimed memory to satisfy the remainder of the +request in such cases lets builders continue to use large pages when the +combination of claims and unclaimed memory allows it, possibly improving +runtime performance in such scenarios. diff --git a/docs/designs/claims/history.rst b/docs/designs/claims/history.rst new file mode 100644 index 000000000000..3c6d745e948c --- /dev/null +++ b/docs/designs/claims/history.rst @@ -0,0 +1,82 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +******************* +Development History +******************* + +.. note:: This section provides historical context on the development of + NUMA-aware claims, including previous implementations and feedback received, + to give a better understanding of the design decisions made in the current + implementation. + +The initial `implementation of single-node claims `_ (by Alejandro Vallejo) +introduced node-exact claims, allowing :term:`domain builders` to claim memory +on one :term:`NUMA node`. It passed a NUMA node in the node bits of the +:c:expr:`xen_memory_reservation.mem_flags` +field of the pre-existing claims hypercall :ref:`XENMEM_claim_pages` and, by +adding the flag ``d->claim_node`` and updating it to the passed node, defined +the target of the claim as either the specified NUMA node or global memory. + +.. sidebar:: Feedback and suggestions for multi-node claim sets + + The initial implementations of single-node claims received feedback from the + community, with multiple suggestions to extend the API to support `multi-node + claim sets `_. This feedback highlighted the need for a more flexible + and extensible design that could accommodate claims on multiple NUMA nodes. + +This design was relatively simple and allowed for a quick implementation of +single-node claims, but it had limitations in terms of flexibility and future +extensibility. + +The `v2 series added a hypercall API for multi-node claims `_, opening the +door to future multi-node claim sets and further work in that direction. + +The `v3 series refactored and improved the implementation `_, protecting +claimed memory against parallel allocations by other domain builders. + +Between v3 and v4, `Roger Pau Monné and Andrew Cooper developed and merged +several critical fixes `_ for Xen's overall claims implementation. +These fixes also allowed Roger to improve the implementation for retiring +claims during domain memory allocation. In turn, this enabled a +fully working implementation that protected claimed memory against parallel +allocations by other domain builders. + +With the `v4 series `_, we submitted the combined work that completed the +fixes for protecting claimed memory on NUMA nodes. The review process indicated +that supporting multiple claim sets would require a `redesign `_ of +claim installation and management, which led to this design document. + +Acknowledgements +---------------- + +The claim sets design builds on the single-node claims implementation +described above and the feedback it generated. The following people +should be acknowledged for their contributions: + +- *Alejandro Vallejo* for initiating the single-node NUMA claims series. +- *Roger Pau Monné* for merging critical fixes and proposing the initial + multi-node claim-sets specification that inspired this design. +- *Andrew Cooper* for integrating and validating the work internally, + helping to stabilise and productise the single-node implementation. +- *Jan Beulich* for providing reviews that led to many improvements. +- *Bernhard Kaindl* for maintaining the single-node series, initiating + the multi-node implementation and authoring this design document. +- *Marcus Granado* and *Edwin Török* for contributing design input, + providing guidance, debugging and testing of single-node implementations. + +.. _fix1: + https://lists.xenproject.org/archives/html/xen-devel/2026-01/msg00164.html + +.. _v1: + https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/ +.. _v1m: + https://lists.xenproject.org/archives/html/xen-devel/2025-06/msg00484.html +.. _v2: + https://lists.xen.org/archives/html/xen-devel/2025-08/msg01076.html +.. _v3: + https://patchew.org/Xen/cover.1757261045.git.bernhard.kaindl@cloud.com/ +.. _v4: + https://lists.xenproject.org/archives/html/xen-devel/2026-02/msg01387.html +.. _v4-03: https://patchwork.kernel.org/project/xen-devel/ + patch/6927e45bf7c2ce56b8849c16a2024edb86034358.1772098423 + .git.bernhard.kaindl@citrix.com/ diff --git a/docs/designs/claims/implementation.rst b/docs/designs/claims/implementation.rst new file mode 100644 index 000000000000..ebc5b045701a --- /dev/null +++ b/docs/designs/claims/implementation.rst @@ -0,0 +1,502 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +##################### +Claims Implementation +##################### + +.. contents:: Table of Contents + :backlinks: entry + :local: + +.. note:: This part describes implementation details of claims and their + interaction with memory allocation in Xen. It covers the functions and + data structures involved in :term:`installing claims`, allocating memory + with :term:`claims`, and handling related edge cases. + +Functions related to the implementation of claims and their interaction +with memory allocation. + +********************** +Installation of claims +********************** + +This section describes the functions and data structures involved +in :term:`installing claims` for domains and the internal functions for +validating and installing claim sets. + +xc_domain_claim_memory() +------------------------ + +.. c:function:: int xc_domain_claim_memory(xc_interface *xch, \ + uint32_t domid, \ + uint32_t nr_claims, \ + memory_claim_t *claims) + + :param xch: The libxenctrl interface to use for the hypercall + :param domid: The ID of the domain for which to install the claim set + :param nr_claims: The number of claims in the claim set + :param claims: The claim set to install for the domain + :type xch: xc_interface * + :type domid: uint32_t + :type nr_claims: uint32_t + :type claims: memory_claim_t * + :returns: 0 on success, or a negative error code on failure. + + Wrapper for :c:expr:`XEN_DOMCTL_claim_memory` to install + :ref:`claim sets ` for a domain. + +domain_set_outstanding_pages() +------------------------------ + +.. c:function:: int domain_set_outstanding_pages(struct domain *d, \ + unsigned long pages) + + :param d: The domain for which to set the outstanding claims + :param pages: The number of pages to claim globally for the domain + :type d: struct domain * + :type pages: unsigned long + :returns: 0 on success, or a negative error code on failure. + + Handles claim installation for :c:expr:`XENMEM_claim_pages` and + :c:expr:`XEN_DOMCTL_claim_memory` with + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` by setting the domain's + :term:`global claims` to the specified number of pages. It calculates + the claims as the requested pages minus the domain's total pages. + When :c:expr:`pages == 0`, it clears the claims of the domain. + +domain_set_node_claims() +------------------------ + +.. c:function:: int domain_set_node_claims(struct domain *d, \ + unsigned int nr_claims, \ + memory_claim_t *claims) + + :param d: The domain for which to set the node claims + :param nr_claims: The number of claims in the claim set + :param claims: The claim set to install for the domain + :type claims: memory_claim_t * + :type d: struct domain * + :type nr_claims: unsigned int + :returns: 0 on success, or a negative error code on failure. + + Handles :term:`installing claim sets`. It performs the validation + of the :term:`claim set` and updates the domain's claims accordingly. + + The function works in four phases: + + 1. Validating claim entries and checking node-local availability + 2. Validating total claims and checking global availability + 3. Resetting any current claims of the domain + 4. Installing the claim set as the domain's claiming state + + Phase 1 checks claim entries for validity and memory availability: + + 1. Target must be :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` or a node. + 2. Each target node may only appear once in the claim set. + 3. For node-local claims, requested pages must not exceed the available + memory on that node after accounting for existing claims. + 4. The explicit padding field must be zero for forward compatibility. + + Phase 2 checks: + + 1. The sum of claims must not exceed globally available memory. + 2. The claims must not exceed the :c:expr:`domain.max_pages` limit. + See :doc:`accounting` and :doc:`retirement` for the accounting + checks that enforce the domain's :c:expr:`domain.max_pages` limit. + +************************************ +Helper functions for managing claims +************************************ + +:c:expr:`claims_retire_global()` and :c:expr:`claims_retire_node()` are helper +functions used to retire claims when necessary: + +- :c:expr:`claims_retire_allocation()` + uses them to retire claims when allocating memory. +- :c:expr:`claims_retire_nodes()` + uses :c:expr:`claims_retire_node()` to reset all node-local claims + of a domain when resetting the claim state of the domain. +- :c:expr:`reserve_offlined_page()` + uses them to recall claims when offlining pages reduces + available memory below the currently claimed memory. See + :ref:`designs/claims/implementation:Offlining memory in presence of claims` + for further information. + +claims_retire_global() +---------------------- + +.. c:function:: unsigned long claims_retire_global(struct domain *d, \ + unsigned long \ + pages_to_retire) + + :param d: The domain for which to retire the global claim + :param pages_to_retire: The number of pages to retire + :type d: struct domain * + :type pages_to_retire: unsigned long + :returns: The number of pages actually retired from the global claim. + + This function retires the specified number of globally claimed pages + and updates the global outstanding totals accordingly. + +claims_retire_node() +-------------------- + +.. c:function:: unsigned long claims_retire_node(struct domain *d, \ + nodeid_t node, \ + unsigned long pages_to_retire) + + :param d: The domain for which to retire the node claim + :param node: The node for which to retire the claim + :param pages_to_retire: The number of pages to retire from the claim + :type d: struct domain * + :type node: nodeid_t + :type pages_to_retire: unsigned long + :returns: The number of pages actually retired from the claim + + This function retires a specified number of pages from a domain's + claim on a specific node. It limits the retirement to the number of + pages actually claimed by the domain on that node and updates the + node-local claims currently held by the domain on that node, + and it updates the global and node-level claim state accordingly. + +claims_retire_nodes() +--------------------- + +.. c:function:: void claims_retire_nodes(struct domain *d) + + :param d: The domain for which to retire the node claims. + :type d: struct domain * + + This function is used by + :ref:`designs/claims/implementation:domain_set_outstanding_pages()` + to reset node-local parts of the domain's claiming state. + +********************** +Allocation with claims +********************** + +The functions below play a key role in allocating memory for domains. + +xc_domain_populate_physmap() +---------------------------- + + .. c:function:: int xc_domain_populate_physmap(xc_interface *xch, \ + uint32_t domid, \ + unsigned long nr_extents, \ + unsigned int extent_order, \ + unsigned int mem_flags, \ + xen_pfn_t *extent_start) + + :param xch: The :term:`libxenctrl` interface + :param domid: The ID of the domain + :param nr_extents: Number of extents + :param extent_order: Order of the extents + :param mem_flags: Allocation flags + :param extent_start: Starting PFN + :type xch: xc_interface * + :type domid: uint32_t + :type nr_extents: unsigned long + :type extent_order: unsigned int + :type mem_flags: unsigned int + :type extent_start: xen_pfn_t * + :returns: 0 on success, or a negative error code on failure. + + This function is a wrapper for the ``XENMEM_populate_physmap`` hypercall, + which is handled by the :c:expr:`populate_physmap()` function in the + hypervisor. It is used by :term:`libxenguest` for populating the + :term:`guest physical memory` of a domain. :term:`domain builders` can + set the :term:`NUMA node affinity` and pass the preferred node to this + function to steer allocations towards the preferred NUMA node(s) and let + :term:`claims` ensure that the memory will be available even in cases + of :term:`parallel domain builds` where multiple domains are being built + at the same time. + + +populate_physmap() +------------------ + +The :term:`meminit` API calls :c:expr:`xc_domain_populate_physmap()` +for populating the :term:`guest physical memory`. It invokes the restartable +``XENMEM_populate_physmap`` hypercall implemented by +:c:expr:`populate_physmap()`. + +.. c:function:: void populate_physmap(struct memop_args *a) + + :param a: Provides status and hypercall restart info + :type a: struct memop_args * + + Allocates memory for building a domain and uses it for populating the + :term:`physmap`. For allocation, it uses + :c:expr:`alloc_domheap_pages()`, which forwards the request to + :c:expr:`alloc_heap_pages()`. + + During domain creation, it adds the ``MEMF_no_scrub`` flag to the request + for populating the :term:`physmap` to optimize domain startup by allowing + the use of unscrubbed pages. + + When that happens, it scrubs the pages as needed using hypercall + continuation to avoid long hypercall latency and watchdog timeouts. + + Domain builders can optimise on-demand scrubbing by running + :term:`physmap` population pinned to the domain's NUMA node, + keeping scrubbing local and avoiding cross-node traffic. + +alloc_heap_pages() +------------------ + +.. c:function:: struct page_info *alloc_heap_pages(unsigned int zone_lo, \ + unsigned int zone_hi, \ + unsigned int order, \ + unsigned int memflags, \ + struct domain *d) + + :param zone_lo: The lowest zone index to consider for allocation + :param zone_hi: The highest zone index to consider for allocation + :param order: The order of the pages to allocate (2^order pages) + :param memflags: Memory allocation flags that may affect the allocation + :param d: The domain for which to allocate memory or NULL + :type zone_lo: unsigned int + :type zone_hi: unsigned int + :type order: unsigned int + :type memflags: unsigned int + :type d: struct domain * + :returns: The allocated page_info structure, or NULL on failure + + This function allocates a contiguous block of pages from the heap. + It checks claims and available memory before attempting the + allocation. On success, it updates relevant counters and retires + claims as necessary. + + It first checks whether the request can be satisfied given the domain's + claims and available memory using :c:expr:`claims_permit_request()`. + If claims and availability permit the request, it calls + :c:expr:`get_free_buddy()` to find a suitable block of free pages + while respecting node and zone constraints. + + If ``MEMF_no_scrub`` is allowed, it may return unscrubbed pages. When that + happens, :c:expr:`populate_physmap()` scrubs them if needed with hypercall + continuation to avoid long hypercall latency and watchdog timeouts. + + Simplified pseudo-code of its logic: +.. code:: C + + struct page_info *alloc_heap_pages(unsigned int zone_lo, + unsigned int zone_hi, + unsigned int order, + unsigned int memflags, + struct domain *d) { + /* Check whether claims and available memory permit the request. + * `avail_pages` and `claims` are placeholders for the appropriate + * global or node-local availability/counts used by the real code. */ + if (!claims_permit_request(d, avail_pages, claims, memflags, + 1UL << order, NUMA_NO_NODE)) + return NULL; + + /* Find a suitable buddy block. Pass the zone range, order and + * memflags so the helper can apply node and zone selection. */ + pg = get_free_buddy(zone_lo, zone_hi, order, memflags, d); + if (!pg) + return NULL; + + claims_retire_allocation(d, 1UL << order, node_of(pg)); + update_counters_and_stats(d, order); + if (pg_has_dirty_pages(pg)) + scrub_dirty_pages(pg); + return pg; + } + +get_free_buddy() +---------------- + +.. c:function:: struct page_info *get_free_buddy(unsigned int zone_lo, \ + unsigned int zone_hi, \ + unsigned int order, \ + unsigned int memflags, \ + const struct domain *d) + + :param zone_lo: The lowest zone index to consider for allocation + :param zone_hi: The highest zone index to consider for allocation + :param order: The order of the pages to allocate (2^order pages) + :param memflags: Flags for conducting the allocation + :param d: domain to allocate memory for or NULL + :type zone_lo: unsigned int + :type zone_hi: unsigned int + :type order: unsigned int + :type memflags: unsigned int + :type d: struct domain * + :returns: The allocated page_info structure, or NULL on failure + + This function finds a suitable block of free pages in the buddy + allocator while respecting claims and node-level available memory. + + Called by :c:expr:`alloc_heap_pages()` after verifying the request is + permissible, it iterates over nodes and zones to find a buddy block + that satisfies the request. It checks node-local claims before + attempting allocation from a node. + + Using :c:expr:`claims_permit_request()`, it checks whether the node + has enough unclaimed memory to satisfy the request or whether the + domain's claims can permit the request on that node after accounting + for outstanding claims. + + If the node can satisfy the request, it searches for a suitable block + in the specified zones. If found, it returns the block; otherwise it + tries the next node until all online nodes are exhausted. + + Simplified pseudo-code of its logic: +.. code:: C + + /* + * preferred_node_or_next_node() represents the policy to first try the + * preferred/requested node then fall back to other online nodes. + */ + struct page_info *get_free_buddy(unsigned int zone_lo, + unsigned int zone_hi, + unsigned int order, + unsigned int memflags, + const struct domain *d) { + nodeid_t request_node = MEMF_get_node(memflags); + + /* + * Iterate over candidate nodes: start with preferred node (if any), + * then try other online nodes according to the normal placement policy. + */ + while (there are more nodes to try) { + nodeid_t node = preferred_node_or_next_node(request_node); + if (!node_allocatable_request(d, node_avail_pages[node], + node_outstanding_claims[node], + memflags, 1UL << order, node)) + goto try_next_node; + + /* Find a zone on this node with a suitable buddy */ + for (int zone = highest_zone; zone >= lowest_zone; zone--) + for (int j = order; j <= MAX_ORDER; j++) + if ((pg = remove_head(&heap(node, zone, j))) != NULL) + return pg; + try_next_node: + if (request_node != NUMA_NO_NODE && (memflags & MEMF_exact_node)) + return NULL; + /* Fall back to the next node and repeat. */ + } + return NULL; + } + +******************************************* +Helper functions for allocation with claims +******************************************* + +For allocating memory while respecting claims, :c:expr:`alloc_heap_pages()` +and :c:expr:`get_free_buddy()` use :c:expr:`claims_permit_request()` to +check whether the claims permit the request before attempting allocation. + +If permitted, the allocation proceeds, and after success, +:c:expr:`claims_retire_allocation()` retires the claims for the allocation +based on the domain's claiming state and the node of the allocation. + +See :ref:`designs/claims/design:Key design decisions` for the +rationale behind this design and the accounting checks that enforce +the :c:expr:`domain.max_pages` limit during allocation with claims. + +claims_permit_request() +----------------------- + +.. c:function:: bool claims_permit_request(const struct domain *d, \ + unsigned long avail_pages, \ + unsigned long claims, \ + unsigned int memflags, \ + unsigned long request, \ + nodeid_t node) + + :param d: domain for which to check + :param avail_pages: pages available globally or on node + :param claims: outstanding claims globally or on node + :param memflags: memory allocation flags for the request + :param request: pages requested for allocation + :param node: node of the request or NUMA_NO_NODE for global + :type d: const struct domain * + :type avail_pages: unsigned long + :type claims: unsigned long + :type memflags: unsigned int + :type request: unsigned long + :type node: nodeid_t + :returns: true if claims and available memory permit the request, \ + false otherwise. + + This function checks whether a memory allocation request can be + satisfied given the current state of available memory and outstanding + claims for the domain. It calculates the amount of unclaimed memory + and determines whether it is sufficient to satisfy the request. + + If unclaimed memory is insufficient, it checks if the domain's claims + can cover the shortfall, taking into account whether the request is + node-specific or global. + +claims_retire_allocation() +-------------------------- + +.. c:function:: void claims_retire_allocation(struct domain *d, \ + unsigned long allocation, \ + nodeid_t alloc_node) + + :param d: The domain for which to retire claims + :param allocation: The number of pages allocated + :param alloc_node: The node on which the allocation was made + :type d: struct domain * + :type allocation: unsigned long + :type alloc_node: nodeid_t + + See :doc:`retirement` for details on retiring claims after allocation. + +************************************** +Offlining memory in presence of claims +************************************** + +When offlining pages, Xen must ensure that available memory on a node or +globally does not fall below outstanding claims. If it does, Xen recalls +claims from domains until accounting is valid again. + +This is triggered by privileged domains via the +``XEN_SYSCTL_page_offline_op`` sysctl or by machine-check memory errors. + +Offlining currently allocated pages does not immediately reduce available +memory: pages are marked offlining and become offline only when freed. +Pages marked offlining will not become available again, so this does not +affect claim invariants. + +However, when already free pages are offlined, free memory can drop +below outstanding claims; in that case the offlining process calls +:c:expr:`reserve_offlined_page()` to offline the page. + +It checks whether offlining the page would cause available memory on the +page's node, or globally, to fall below the respective outstanding claims: + +- When + :c:expr:`node_outstanding_claims[offline_node]` exceeds + :c:expr:`node_avail_pages[offline_node]` for the node of the offlined page, + :c:expr:`reserve_offlined_page()` calls :c:expr:`claims_retire_node()` + to recall claims on that node from domains with claims on the node of the + offlined buddy until the claim accounting of the node is valid again. + +- When total :c:expr:`outstanding_claims` exceeds :c:expr:`total_avail_pages`, + :c:expr:`reserve_offlined_page()` calls :c:expr:`claims_retire_global()` to + recall global claims from domains with global claims until global accounting + is valid again. + +This can violate claim guarantees, but it is necessary to maintain system +stability when memory must be offlined. + +reserve_offlined_page() +----------------------- + +.. c:function:: int reserve_offlined_page(struct page_info *head) + + :param head: The page being offlined + :type head: struct page_info * + :returns: 0 on success, or a negative error code on failure. + + This function is called during the offlining process to offline pages. + + If offlining a page causes available memory to fall below outstanding + claims, it checks the node and global claim accounting and recalls + claims from domains as necessary to ensure accounting invariants hold + after a buddy is offlined. diff --git a/docs/designs/claims/index.rst b/docs/designs/claims/index.rst new file mode 100644 index 000000000000..1d4eff32850b --- /dev/null +++ b/docs/designs/claims/index.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +NUMA-aware Claim Sets +===================== + +Design and implementation of NUMA-aware claim sets. + +Status: Draft for review + +This design first introduces the external behaviour of claim sets: how claims +are installed, how they protect allocations, and how they are retired. +It then covers the underlying accounting model and implementation details. + +For readers following the design in order, the next sections cover the +following topics: + +1. :doc:`/designs/claims/usecases` describes the use cases for claim sets. +2. :doc:`/designs/claims/history` provides the development's historical context +3. :doc:`/designs/claims/design` introduces the overall model and goals. +4. :doc:`/designs/claims/installation` explains how claim sets are installed. +5. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +6. :doc:`/designs/claims/retirement` explains how claims are retired as + allocations succeed. +7. :doc:`/designs/claims/accounting` describes the accounting model that + underpins those steps. + +.. toctree:: :caption: Contents + :maxdepth: 2 + + usecases + history + design + installation + protection + retirement + accounting + implementation + edge-cases + +.. contents:: + :backlinks: entry + :local: diff --git a/docs/designs/claims/installation.rst b/docs/designs/claims/installation.rst new file mode 100644 index 000000000000..70f97abbae66 --- /dev/null +++ b/docs/designs/claims/installation.rst @@ -0,0 +1,122 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +######################## +Claim Installation Paths +######################## + +********** +Claim sets +********** + +A claim set is an array of :c:expr:`memory_claim_t` entries, each specifying +a page count and a target. Targets are either a NUMA node ID, or one of two +special values: + +.. c:macro:: XEN_DOMCTL_CLAIM_MEMORY_GLOBAL + + Value for the :c:expr:`xen_memory_claim.target` field of a claim set entry + to specify a global claim satisfied from any node, useful when strict + per-node placement is not required or as a fallback for memory that + may be populated on any node. + + These claims are retired on allocation only when the allocation node's + claims are exhausted, so they provide a way to claim memory when the + available memory on the allocation nodes is not fully sufficient to + satisfy the domain's needs, but the global pool has sufficient free + memory to cover the shortfall and the domain can tolerate some fallback + to non-preferred nodes without selecting a specific node for the fallback. + + Supported by :c:expr:`XEN_DOMCTL_claim_memory` but not the legacy claim path. + +.. c:macro:: XEN_DOMCTL_CLAIM_MEMORY_LEGACY + + This is a special selector for :c:expr:`xen_memory_claim.target` that can + only be used in a single-entry claim set to indicate that the claim set + should be processed by the legacy claim installation logic. It is not a + valid target for regular claims and is not supported for multi-entry + claim sets and is only used for backward compatibility and is not + intended for use in new code. + +.. note:: The legacy path is deprecated. Use :c:expr:`XEN_DOMCTL_claim_memory` + with :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` for global claims in new + code instead of :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY`. + +.. c:type:: memory_claim_t + + Typedef for :c:expr:`xen_memory_claim`, + the structure for passing claim sets to the hypervisor. + +.. c:struct:: xen_memory_claim + + Underlying structure for passing claim sets to the hypervisor. + + This structure represents an individual claim entry in a claim set. + It specifies the number of pages claimed and the target of the claim, + which can be a specific NUMA node or a special value for global claims. + + The structure includes padding for future expansion, and it is important + to zero-initialise it or use designated initializers to ensure forward + compatibility. Members are as follows: + + .. c:member:: uint64_aligned_t pages + + Number of pages for this claim entry. + + .. c:member:: uint32_t target + + The target of the claim, which can be a specific NUMA node + or a special selector to steer the claim to the global pool + or to invoke the legacy claim path. + Valid values are either a node ID in the range of valid NUMA nodes, or: + + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` for a global claim, or + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` for the legacy claim path. + + .. c:member:: uint32_t pad + + Reserved for future use, must be 0 for forward compatibility. + +.. c:type:: uint64_aligned_t + + 64-bit unsigned integer type with alignment requirements suitable for + representing page counts in the claim structure. + +********************** +Claim set installation +********************** + +Claim set installation is invoked via :c:expr:`XEN_DOMCTL_claim_memory` and +:ref:`designs/claims/implementation:domain_set_node_claims()` implements +the claim set installation logic. + +Claim sets using +:c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` are dispatched to +:ref:`designs/claims/implementation:domain_set_outstanding_pages()` +for the legacy claim installation logic. + +See :doc:`accounting` for details on the claims accounting state. + +************************* +Legacy claim installation +************************* + +.. note:: The legacy path is deprecated. + Use :c:expr:`XEN_DOMCTL_claim_memory` for new code. + +Legacy claims are set via the :ref:`XENMEM_claim_pages` command, +implemented by +:ref:`designs/claims/implementation:domain_set_outstanding_pages()` +with the following semantics: + +- The request contains exactly one global claim entry of the form + :c:expr:`xen_memory_claim.target = XEN_DOMCTL_CLAIM_MEMORY_LEGACY`. +- It sets :c:expr:`domain.global_claims` to the requested pages, minus + the domain's total pages, i.e. the pages allocated to the domain so far, + so that the domain's global outstanding claims reflect the shortfall of + allocated pages from claimed pages: + :c:expr:`xen_memory_claim.pages - domain_tot_pages(domain)`. +- Passing :c:expr:`xen_memory_claim.pages == 0` + clears all claims installed for the domain. + +Aside from the edge cases for allocations exceeding claims and +offlining pages, the legacy path is functionally unchanged. diff --git a/docs/designs/claims/invariants.mmd b/docs/designs/claims/invariants.mmd new file mode 100644 index 000000000000..ac9bfba34d49 --- /dev/null +++ b/docs/designs/claims/invariants.mmd @@ -0,0 +1,36 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +%% Claim variables and their Invariants +flowchart TD + +subgraph "Access under the heap_lock only:" + direction TB + Memory_of_Nodes --"  Contribute to  "--> Overall_Memory + Overall_Memory --"  Available to  "--> Memory_of_Domains +end + +subgraph Memory_of_Nodes["Per-node claims and available memory"] + direction LR + per_node_claims -->|"  less or equal to  "| node_avail_pages + per_node_claims["Claims on the node: + node_outstanding_claims[n]"] + node_avail_pages["Available pages on the node: + node_avail_pages[n]"] +end + +subgraph Overall_Memory["Overall claims and available memory"] + direction LR + outstanding -->|"  less or equal to  "| avail_pages + outstanding["Total claims on the host: + outstanding_claims"] + avail_pages["Available pages on the host: + total_avail_pages"] +end + +subgraph Memory_of_Domains["Per-domain claims and available memory"] + direction LR + claims -->|"  less or equal to  "| available_memory_for_domains + claims["Claims of the domain:
d->claims[n] + d->global_claims"] + available_memory_for_domains["Available pages:
node_avail_pages[n] + total_avail_pages"] +end \ No newline at end of file diff --git a/docs/designs/claims/protection.rst b/docs/designs/claims/protection.rst new file mode 100644 index 000000000000..2de6097d2c74 --- /dev/null +++ b/docs/designs/claims/protection.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Protection of Claims +-------------------- + +Claimed memory must be protected from unrelated allocations while remaining +available to the claiming domain. + +The allocator performs two checks. + +Global check +^^^^^^^^^^^^ + +``alloc_heap_pages()`` first verifies whether the request fits the global +pool after accounting for claims. The request is permitted when either: + +- Enough unclaimed memory exists globally to satisfy the request. +- The requesting domain's outstanding claims cover the shortfall. + +For this check, the domain's applicable claim is +``d->global_claims + d->node_claims``. The domain therefore receives +credit for its complete claim set, whether reservations are global, +per-node, or both. + +Node check +^^^^^^^^^^ + +After passing the global check, the allocator calls ``get_free_buddy()`` +to find free pages. It loops over the NUMA nodes to find a suitable +node with enough free memory to satisfy the request. + +It performs an additional node-local claims check using the domain's claim +for that node (``d->claims[node]``) to determine whether the node is qualified +to satisfy the request before examining that node's free lists. + +Unless the caller requested an exact node, the allocator loops +over nodes until it finds one where the request can be satisfied +by the unclaimed memory and the node-local claim for that node. + +If no qualifying node is found, the allocator rejects the request +due to insufficient memory. diff --git a/docs/designs/claims/retirement.rst b/docs/designs/claims/retirement.rst new file mode 100644 index 000000000000..2912a082b878 --- /dev/null +++ b/docs/designs/claims/retirement.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Claim Retirement +---------------- + +After a successful allocation, +:ref:`designs/claims/implementation:claims_retire_allocation()` retires +claims up to the size of the allocation in the same critical region +that updates the free-page counters. + +The function performs the following steps to retire the matching claims +for this allocation, ensuring the domain's total memory allocation as +:c:expr:`domain_tot_pages(domain)` plus its outstanding claims as +:c:expr:`domain.global_claims + domain.node_claims` remain within the +domain's limits, defined by :c:expr:`domain.max_pages`: + +Step 1: + Retire claims from :c:expr:`domain.claims[alloc_node]` on the allocation + node, up to the size of that claim. +Step 2: + If the allocation exceeds :c:expr:`domain.claims[alloc_node]`, retire the + remaining pages from the global fallback claim :c:expr:`domain.global_claims` + (if one exists). +Step 3: + If the allocation exceeds the combination of those claims, retire the + remaining pages from other per-node claims so that the domain's total + allocation plus claims remain within the domain's :c:expr:`domain.max_pages` + limit. + +Enforcing the :c:expr:`domain.max_pages` limit +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +:c:expr:`domain_tot_pages(domain)` + +:c:expr:`domain.global_claims + domain.node_claims` +must not exceed the :c:expr:`domain.max_pages` limit, otherwise +the domain would exceed its memory entitlement. + +At claim installation time + This check is done by + :c:expr:`domain_set_node_claims()` and + :c:expr:`domain_set_outstanding_pages()`. + +.. :sidebar:: + See :ref:`designs/claims/accounting:Locking of claims accounting` + for the locks used to protect claims accounting state and invariants. + +A memory allocation time + It is also possible for claims to become excessive after allocating memory + if the domain has claims that are not retired by the allocation: + + If allocations would not retire enough claims to keep the sum of the domain's + allocation and claims within the domain's :c:expr:`domain.max_pages` limit, + the combination of the allocation and claims could exceed the domain's limit. + + In this case, the domain's claims could exceed its memory entitlement. + Such excess beyond :c:expr:`domain.max_pages` claims could be actually + physically allocated for that domain, but would still prevent other + domains from using the excess claimed memory. + + :ref:`designs/claims/implementation:claims_retire_allocation()` cannot execute + this exact step race-free during step 3 because it would have to take the + :c:expr:`domain.page_alloc_lock` to inspect the domain's limits + and current allocation. Taking that lock while holding the + :c:expr:`heap_lock` would invert the locking order and could + lead to deadlocks. + +Therefore, :ref:`designs/claims/implementation:claims_retire_allocation()` +retires the remaining allocation from other-node claims to ensure +the sum of the domain's claims and populated pages remains within the +domain's :c:expr:`domain.max_pages` limit. diff --git a/docs/designs/claims/usecases.rst b/docs/designs/claims/usecases.rst new file mode 100644 index 000000000000..5a618f0d0280 --- /dev/null +++ b/docs/designs/claims/usecases.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +######### +Use Cases +######### + +.. glossary:: + + Parallel :term:`domain builds` + + When many domains need to be created and built, many :term:`domain builders` + compete for the same pools of memory, which can lead to inefficient NUMA + placement of :term:`guest physical memory` and thus suboptimal performance + for the domains. + + NUMA-aware claims can help solve this problem and ensure that memory + is available on the appropriate NUMA nodes. + + Domain builds + + The process of constructing and configuring :term:`domains` by + :term:`domain builders`, which includes installing :term:`claims`, + :term:`populating` memory, and setting up other resources before the + :term:`domains` are started. When multiple :term:`domain builders` can + run in parallel, this is referred to as parallel domain builds, which can + benefit from NUMA-aware claims because the domain builders are competing for + the same pools of memory on the NUMA nodes. + + Boot storms + + It is common for many domains to be booted at the same time, such as during + system startup or when large numbers of domains need to be started. + + Parallel migrations + + Similar to :term:`boot storms`, except that the domains are being migrated + instead of booted, which can happen when other hosts are being drained + for maintenance (host evacuation) or when workloads are being rebalanced + across hosts. diff --git a/docs/designs/index.rst b/docs/designs/index.rst new file mode 100644 index 000000000000..036653303231 --- /dev/null +++ b/docs/designs/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Design documents +================ + +Design documents and implementation details for the Xen hypervisor itself. +This is intended for developers working on the Xen hypervisor, +and for those interested in the internal workings of Xen. + +.. toctree:: + :maxdepth: 2 + :numbered: 4 + + launch/hyperlaunch + launch/hyperlaunch-devicetree + claims/index diff --git a/docs/designs/launch/hyperlaunch.rst b/docs/designs/launch/hyperlaunch.rst index 3bed36f97637..aa7c2798a380 100644 --- a/docs/designs/launch/hyperlaunch.rst +++ b/docs/designs/launch/hyperlaunch.rst @@ -2,8 +2,6 @@ Hyperlaunch Design Document ########################### -.. sectnum:: :depth: 4 - This post is a Request for Comment on the included v4 of a design document that describes Hyperlaunch: a new method of launching the Xen hypervisor, relating to dom0less and work from the Hyperlaunch project. We invite discussion of this @@ -13,6 +11,8 @@ Xen Development mailing list. .. contents:: :depth: 3 + :backlinks: entry + :local: Introduction diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd new file mode 100644 index 000000000000..50687392fd20 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd @@ -0,0 +1,43 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +classDiagram +class do_domctl["Args passed to do_domctl()"] { + +uint32_t cmd: XEN_DOMCTL_claim_memory + +uint32_t domain: Domain ID + +xen_domctl_claim_memory: Claim set +} +class xen_domctl_claim_memory["Claim set passed to do_domctl()"] { + +memory_claim_t* claims: Claim entries + +uint32_t nr_claims: Number of claim entries + +uint32_t pad: always 0 for future use +} +class memory_claim_t["Claim set: Array of claim entries"] { + +pages: Pages to claim + +node: Claim selector or node + +pad: always 0 for future use +} +class xc_domain_claim_memory["xc_domain_claim_memory()"] { + +xc_interface* xch + +uint32_t domid + +uint32_t nr_claims + +memory_claim_t* claims +} +class global_claimss["Global and Node claim counters"] { + global free = total_avail_pages - outstanding_claims + node free = node_avail_pages[node] - node_outstanding_claims[node] +} +class claim["XEN_DOMCTL_claim_memory"] { + +domain_set_outstanding_pages() + +domain_set_node_claims() +} +class domain["Claim fields in struct domain"] { + +global_claims - Global claims of the domain + +node_claims - Sum of claims on all nodes of the domain + +claims[] - Array of claims on specific nodes +} +xen_domctl_claim_memory o--> memory_claim_t +do_domctl o--> xen_domctl_claim_memory +xc_domain_claim_memory ..> do_domctl: passes
Claim set +xc_domain_claim_memory ..> claim : calls do_domctl() +claim ..> xen_domctl_claim_memory : reads +claim ..> domain : sets +domain ..> global_claimss : updates outstanding claims diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd new file mode 100644 index 000000000000..05d688c59f13 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd @@ -0,0 +1,23 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +sequenceDiagram + +actor DomainBuilder +participant OcamlStub as OCaml stub for
xc_domain
claim_memory +participant Libxc as xc_domain
claim_memory +participant Domctl as XEN_DOMCTL
claim_memory +#participant DomainLogic as claim_memory +participant Alloc as domain
set
outstanding_pages + +DomainBuilder->>OcamlStub: claims +OcamlStub->>OcamlStub: marshall claims -----> OCaml to C +OcamlStub->>Libxc: claims + +Libxc->>Domctl: do_domctl + +Domctl->>Domctl: copy_from_guest(claim) +Domctl->>Domctl: validate claim +Domctl->>Alloc: set
outstanding_pages +Alloc-->>Domctl: result +Domctl-->>Libxc: rc +Libxc-->>OcamlStub: rc +OcamlStub-->>DomainBuilder: claim_result \ No newline at end of file diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd new file mode 100644 index 000000000000..372f2bb7a616 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd @@ -0,0 +1,23 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +sequenceDiagram + +participant Toolstack +participant Xen +participant NUMA Node memory + +Toolstack->>Xen: XEN_DOMCTL_createdomain +Toolstack->>Xen: XEN_DOMCTL_max_mem(max_pages) + +Toolstack->>Xen: XEN_DOMCTL_claim_memory(pages, node) +Xen->>NUMA Node memory: Claim pages on node +Xen-->>Toolstack: Claim granted + +Toolstack->>Xen: XEN_DOMCTL_set_nodeaffinity(node) + +loop Populate domain memory + Toolstack->>Xen: XENMEM_populate_physmap(memflags:node) + Xen->>NUMA Node memory: alloc from claimed node +end + +Toolstack->>Xen: XEN_DOMCTL_claim_memory(0, NO_NODE) +Xen-->>Toolstack: Remaining claims released diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory.rst b/docs/guest-guide/dom/DOMCTL_claim_memory.rst new file mode 100644 index 000000000000..d435799c57a6 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +.. c:macro:: XEN_DOMCTL_claim_memory + + Hypercall command for installing claim sets for a domain. + + This hypercall command allows :term:`domain builders` to install a + :term:`claim set` targeting :term:`NUMA nodes` and :term:`global claims`. + + The hypervisor tracks the installed claims for each domain and enforces + them during memory allocation, so that claimed memory is protected from + other allocations and the domain's memory requirements can be met even + when other parallel domain builders are also allocating memory for other + domains in parallel. + + :ref:`designs/claims/installation:Claim set installation` describes + how the Xen hypervisor processes the claim sets installed via this + hypercall command. + +API example using libxenctrl +---------------------------- + +The example below shows how a domain builder can install a claim set and +later replace or clear it. :c:expr:`memory_claim_t` contains padding for future +expansion; zero-initialise the structure or use designated initializers to +ensure forward compatibility. + +.. code-block:: C + + #include + + void example_claims(xc_interface *xch, uint32_t domid) + { + /* Claim 1024 pages on node 0, 1024 pages on node 1, and 1024 global */ + memory_claim_t claims[] = { + {.pages = 1024, .node = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + {.pages = 1024, .node = 0}, + {.pages = 1024, .node = 1} + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(claims), claims); + + /* Replace the claim set with claims on nodes 1, 2, and 3 */ + memory_claim_t claims2[] = { + {.pages = 1024, .node = 1}, + {.pages = 1024, .node = 2}, + {.pages = 1024, .node = 3}, + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(claims2), claims2); + + /* Release any remaining claim once the domain is built */ + memory_claim_t clear[] = { + {.pages = 0, .node = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL} + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(clear), clear); + } + +Call sequence diagram +--------------------- + +The following sequence diagram illustrates the call flow for claiming memory +for a domain using this hypercall command from an OCaml domain builder: + +.. mermaid:: DOMCTL_claim_memory-seqdia.mmd + :caption: Sequence diagram: Call flow for claiming memory for a domain + +Claim workflow +-------------- + +This diagram illustrates a workflow for claiming and populating memory: + +.. mermaid:: DOMCTL_claim_memory-workflow.mmd + :caption: Workflow diagram: Claiming and populating memory for a domain + +Used functions & data structures +-------------------------------- + +This diagram illustrates the key functions and data structures involved in +installing claims via the :c:expr:`XEN_DOMCTL_claim_memory` hypercall command: + +.. mermaid:: DOMCTL_claim_memory-data.mmd + :caption: Diagram: Function and data relationships for installing claims diff --git a/docs/guest-guide/dom/index.rst b/docs/guest-guide/dom/index.rst new file mode 100644 index 000000000000..445ccf599047 --- /dev/null +++ b/docs/guest-guide/dom/index.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Domctl Hypercall +================ + +Through domctl hypercalls, toolstacks in privileged domains can perform +operations related to domain management. This includes operations such as +creating, destroying, and modifying domains, as well as querying domain +information. + +.. toctree:: + :maxdepth: 2 + + DOMCTL_claim_memory diff --git a/docs/guest-guide/index.rst b/docs/guest-guide/index.rst index 5455c67479cf..d9611cd7504d 100644 --- a/docs/guest-guide/index.rst +++ b/docs/guest-guide/index.rst @@ -3,6 +3,29 @@ Guest documentation =================== +Xen exposes a set of hypercalls that allow domains and toolstacks in +privileged contexts (such as Dom0) to request services from the hypervisor. + +Through these hypercalls, privileged domains can perform privileged operations +such as querying system information, memory and domain management, +and enabling inter-domain communication via shared memory and event channels. + +These hypercalls are documented in the following sections, grouped by their +functionality. Each section provides an overview of the hypercalls, their +parameters, and examples of how to use them. + +Hypercall API documentation +--------------------------- + +.. toctree:: + :maxdepth: 2 + + dom/index + mem/index + +Hypercall ABI documentation +--------------------------- + .. toctree:: :maxdepth: 2 diff --git a/docs/guest-guide/mem/XENMEM_claim_pages.rst b/docs/guest-guide/mem/XENMEM_claim_pages.rst new file mode 100644 index 000000000000..1e8a50afc856 --- /dev/null +++ b/docs/guest-guide/mem/XENMEM_claim_pages.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: CC-BY-4.0 +.. _XENMEM_claim_pages: + +XENMEM_claim_pages +================== + +.. note:: This API is deprecated; + Use :c:expr:`XEN_DOMCTL_claim_memory` for new code. + +.. c:macro:: XENMEM_claim_pages + + Hypercall command for installing legacy claims. + + :ref:`designs/claims/installation:Legacy claim installation` describes + the API for installing legacy claims via this hypercall command. + + It passes a single claim entry to the hypervisor via a + :c:expr:`xen_memory_reservation` structure with the page count in the + :c:expr:`xen_memory_reservation.nr_extents` field and the domain ID + :c:expr:`xen_memory_reservation.domid` field. The claim entry's target is + implicitly global, and the legacy claim path is invoked in the hypervisor + to process the claim: + +.. c:struct:: xen_memory_reservation + + Structure for passing claim requests to the hypervisor via + :ref:`XENMEM_claim_pages` and other memory reservation hypercalls. + + .. code-block:: C + + struct xen_memory_reservation { + xen_pfn_t *extent_start; /* not used for XENMEM_claim_pages */ + xen_ulong_t nr_extents; /* pass page counts to claim */ + unsigned int extent_order; /* must be 0 */ + unsigned int mem_flags; /* XENMEMF flags. */ + domid_t domid; /* domain to apply the claim to */ + }; + typedef struct xen_memory_reservation xen_memory_reservation_t; + + .. c:member:: xen_ulong_t nr_extents + + For :ref:`XENMEM_claim_pages`, the page count to claim. + + .. c:member:: domid_t domid + + Domain ID for the claim. + + .. c:member:: unsigned int mem_flags + + Must be 0 for :ref:`XENMEM_claim_pages`; not used for claims. + + In principle, it supports all the :c:expr:`XENMEMF_*` flags, including + the possibility of passing a single NUMA node ID, but using it to pass + a NUMA node ID is not currently supported by the legacy claim path. + + During review of the NUMA extension of the legacy claim path, it + was used, but the request was made to instead create a new hypercall + which is now :c:expr:`XEN_DOMCTL_claim_memory` with support for claim sets. + + .. c:member:: unsigned int extent_order + .. c:member:: xen_pfn_t *extent_start + + Both are not used for :ref:`XENMEM_claim_pages`, but are used for other + memory reservation hypercalls. + + See :ref:`designs/claims/installation:Legacy claim installation` for details. + +API example using libxenctrl +---------------------------- + +The example below claims pages, populates the domain, +and then clears the claim. + +.. code-block:: C + + #include + + int build_with_claims(xc_interface *xch, uint32_t domid, + unsigned long nr_pages) + { + int ret; + + /* Claim pages for the domain build. */ + ret = xc_domain_claim_pages(xch, domid, nr_pages); + if ( ret < 0 ) + return ret; + + /* Populate the domain's physmap. */ + ret = xc_domain_populate_physmap(xch, domid, /* ... */); + if ( ret < 0 ) + return ret; + + /* Release any remaining claim after populating the domain memory. */ + ret = xc_domain_claim_pages(xch, domid, 0); + if ( ret < 0 ) + return ret; + + /* Unpause the domain to allow it to run. */ + return xc_unpause_domain(xch, domid); + } diff --git a/docs/guest-guide/mem/index.rst b/docs/guest-guide/mem/index.rst new file mode 100644 index 000000000000..086281f082a0 --- /dev/null +++ b/docs/guest-guide/mem/index.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Memctl Hypercall +================ + +The XENMEM hypercall interface allows guests to perform various control +operations related to memory management. + +.. toctree:: + :maxdepth: 2 + + XENMEM_claim_pages diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.rst index 520fe01554ab..904f8daeb79e 100644 --- a/docs/hypervisor-guide/index.rst +++ b/docs/hypervisor-guide/index.rst @@ -3,9 +3,16 @@ Hypervisor documentation ======================== +.. The toctree of the hypervisor design documentation, + providing an overview and links to the various design + documents are added in the `designs` directory and + are referenced using the `designs/index` page here. + (this is a documentation comment which is not rendered) + .. toctree:: :maxdepth: 2 + ../designs/index code-coverage x86/index diff --git a/docs/index.rst b/docs/index.rst index bd87d736b9c3..b6803f6a341e 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -53,17 +53,18 @@ kind of development environment. hypervisor-guide/index misc/ci - Unsorted documents ------------------ Documents in need of some rearranging. +.. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775124241-F49CB2A1-DDE6FB35/0/0 X-purgate-type: clean X-purgate-size: 7886 On 10.03.2026 18:08, Oleksii Kurochko wrote: > AIA provides a hardware-accelerated mechanism for delivering external > interrupts to domains via "guest interrupt files" located in IMSIC. > A single physical hart can implement multiple such files (up to GEILEN), > allowing several virtual harts to receive interrupts directly from hardware Isn't use of such an optimization coming prematurely? Shouldn't this series focus on getting basic functionality in place? > --- a/xen/arch/riscv/aia.c > +++ b/xen/arch/riscv/aia.c > @@ -1,11 +1,24 @@ > /* SPDX-License-Identifier: GPL-2.0-only */ > > +#include > #include > #include > #include > +#include > +#include > #include > +#include > > +#include > #include > +#include > +#include > + > +/* > + * Bitmap for each physical cpus to detect which VS (guest) > + * interrupt file id was used. > + */ > +DEFINE_PER_CPU(struct vgein_bmp, vgein_bmp); Why can this not be static? All management looks to be in this same file. > @@ -14,12 +27,109 @@ bool aia_available(void) > return is_aia_available; > } > > +int __init vgein_init(unsigned int cpu) If this needs invoking once per CPU being brought up, it can't be __init. Also - static? > +{ > + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); > + > + csr_write(CSR_HGEIE, -1UL); > + vgein->geilen = flsl(csr_read(CSR_HGEIE)); > + csr_write(CSR_HGEIE, 0); > + if ( vgein->geilen ) > + vgein->geilen--; I don't understand this. The "len" in "geilen" stands for "length", I suppose, i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN." This may or may not include bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but that's not unambiguous. Anyway, may I suggest vgein->geilen = flsl(csr_read(CSR_HGEIE) >> 1); instead? > + BUG_ON(!vgein->geilen); You can return (an error, but see the respective remark on the earlier patch), no need to crash the system. That return may want to come after the printk() below, though. > + printk("cpu%d.geilen=%d\n", cpu, vgein->geilen); As before - %u please with unsigned int. > + if ( !vgein->bmp ) Why would this check be needed? > + { > + vgein->bmp = xvzalloc_array(unsigned long, BITS_TO_LONGS(vgein->geilen)); With the determination above, isn't BITS_TO_LONGS(vgein->geilen) == BITS_PER_LONG in all cases? Surely you don't mean to runtime-allocate space for a single unsigned long? So I wonder is the dimension used is wrong. If it isn't, dynamically allocating the owners array may be more useful, as (on RV64) occupies a fixed 512 bytes right now. > + if ( !vgein->bmp ) > + return -ENOMEM; > + } > + > + spin_lock_init(&vgein->lock); > + > + return 0; > +} > + > int __init aia_init(void) > { > + int rc = 0; > + > if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) > return -ENODEV; > > + if ( (rc = vgein_init(0)) ) > + return rc; > + > is_aia_available = true; Ah, this answers a question of mine on the earlier patch: This boolean indicates more than just the extension being available. But why does the description there not simply say so? How am I as a reviewer supposed to know? > - return 0; > + return rc; > +} > + > +unsigned int vgein_assign(struct vcpu *v) > +{ > + unsigned int vgein_id; > + Seemingly undue blank line. > + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor); > + unsigned long *bmp = vgein_bmp->bmp; > + unsigned long flags; > + > + spin_lock_irqsave(&vgein_bmp->lock, flags); > + vgein_id = bitmap_weight(bmp, vgein_bmp->geilen); How can the ID to use be the number of bits which are set? This only works if all set bits are contiguous at the bottom. > + /* > + * All vCPU guest interrupt files are used and we don't support a case > + * when number of vCPU on 1 pCPU is bigger then geilen. > + */ This wants checking in vgein_init() then. CPUs (beyond the boot one) violating this should not be brought online. > + ASSERT(vgein_id < vgein_bmp->geilen); What if not bit is available? By asserting, you assume the caller will not call here when no ID is available. Yet there is no caller of this function, so how can one verify whether this assertion is appropriate? > + bitmap_set(bmp, vgein_id, 1); __set_bit()? > + spin_unlock_irqrestore(&vgein_bmp->lock, flags); > + > + /* > + * The vgein_id shouldn't be zero, as it will indicate that no guest > + * external interrupt source is selected for VS-level external interrupts > + * according to RISC-V priviliged spec: > + * 8.2.1 Hypervisor Status Register (hstatus) in RISC-V priviliged spec: Please avoid section numbers in such references. The section of this name in the version I'm looking at is 21.2.1. > + * The VGEIN (Virtual Guest External Interrupt Number) field selects > + * a guest external interrupt source for VS-level external interrupts. > + * VGEIN is a WLRL field that must be able to hold values between zero > + * and the maximum guest external interrupt number (known as GEILEN), > + * inclusive. > + * When VGEIN=0, no guest external interrupt source is selected for > + * VS-level external interrupts. > + */ > + vgein_id++; Related to my comment regarding GEILEN, this shouldn't be necessary. Keep bits in their natural positions, and simply avoid using bit 0 (either by setting it during init and then never clearing it, or by starting the scan for clear bits at bit 1). > +#ifdef VGEIN_DEBUG > + printk("%s: %pv: vgein_id(%u), xen_cpu%d_bmp=%#lx\n", > + __func__, v, vgein_id, v->processor, *bmp); > +#endif > + > + vcpu_guest_cpu_user_regs(v)->hstatus &= ~HSTATUS_VGEIN; > + vcpu_guest_cpu_user_regs(v)->hstatus |= > + MASK_INSR(vgein_id, HSTATUS_VGEIN); When is this function going to be invoked? (As before, not knowing this is one of the problems with introducing functions with no callers.) > + return vgein_id; > +} > + > +void vgein_release(struct vcpu *v, unsigned int vgen_id) > +{ > + unsigned long flags; > + Another seemingly stray blank line. > + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor); > + > + spin_lock_irqsave(&vgein_bmp->lock, flags); > + bitmap_clear(vgein_bmp->bmp, vgen_id - 1, 1); __clear_bit()? > + spin_unlock_irqrestore(&vgein_bmp->lock, flags); > + > +#ifdef VGEIN_DEBUG > + printk("%s: vgein_id(%u), xen_cpu%d_bmp=%#lx\n", > + __func__, vgen_id, v->processor, *vgein_bmp->bmp); I can't spot a difference from the message in vgein_assign(). How is one to distinguish the two in a log? > --- a/xen/arch/riscv/include/asm/aia.h > +++ b/xen/arch/riscv/include/asm/aia.h > @@ -3,8 +3,26 @@ > #ifndef ASM__RISCV__AIA_H > #define ASM__RISCV__AIA_H > > +#include > +#include > + > +struct vcpu; > + > +struct vgein_bmp { What does the _bmp suffix indicate here? There's ... > + unsigned long *bmp; ... a bitmap field, yes, but ... > + spinlock_t lock; > + struct vcpu *owners[BITS_PER_LONG]; > + unsigned int geilen; > +}; ... the structure as a whole has quite a bit more. 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Thu, 02 Apr 2026 03:23:09 -0700 (PDT) Message-ID: <0b284c32-4dd3-4663-881b-834c47070328@suse.com> Date: Thu, 2 Apr 2026 12:23:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Andrew Cooper Cc: xen-devel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <97bfb299-a465-48a3-a036-f217de683c2c@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775125390-AEF21CD1-987A9CF9/13/0 X-purgate-type: clean X-purgate-size: 3288 On 02.04.2026 11:42, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 10:47:53AM +0200, Jan Beulich wrote: >> On 02.04.2026 10:39, Jan Beulich wrote: >>> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>>> The xl dmesg output (from MTL this time): >>>> >>>> (XEN) [ 123.477511] Entering ACPI S3 state. >>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>> >>> XEN_ARAT being off is the one odd aspect here. That'll want tracking down >>> separately. As per xen-cpuid output (below) ARAT is available. >> >> For this you may want to also add logging to intel_init_arat(): Since opt_arat >> can be false only due to command line option use, it can only be the function >> not being called (which looks impossible on plain staging code), or cpu_has_arat >> being false despite the xen-cpuid output that you supplied earlier (inexplicable >> as well, at least for now). > > Hm, I got this: > > (XEN) [ 11.403340] intel_init_arat:674: opt_arat: 1, cpu_has_arat: 0 > > so, cpu_has_arat=0 ... > next lines are those, to hint when it happened in the boot process: > > (XEN) [ 11.409754] mwait-idle: MWAIT substates: 0x11112020 > (XEN) [ 11.416130] mwait-idle: v0.4.1 model 0xaa > (XEN) [ 11.422396] mwait-idle: lapic_timer_reliable_states 0x2 > > Looks like calculate_host_policy() runs much later... Hmm, yes, and that's the problem. The reason I don't see this is that a newer version of [1] has this --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -628,6 +628,8 @@ void identify_cpu(struct cpuinfo_x86 *c) } /* Now the feature flags better reflect actual CPU features! */ + if (c == &boot_cpu_data) + calculate_host_policy(); xstate_init(c); --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -384,7 +384,7 @@ void calculate_raw_cpu_policy(void) /* Was already added by probe_cpuid_faulting() */ } -static void __init calculate_host_policy(void) +void __init calculate_host_policy(void) { struct cpu_policy *p = &host_cpu_policy; @@ -959,6 +959,7 @@ static void __init calculate_hvm_def_pol void __init init_guest_cpu_policies(void) { + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() uses. */ calculate_host_policy(); if ( IS_ENABLED(CONFIG_PV) ) and of course I'm doing my work (and my analysis) with that in place. I may need to break this out and submit independently, but really the problem here is that the containing series has been sitting largely unreviewed (and hence not in a position to plausibly re-post) for almost 5 years. Andrew, (maybe also Roger) - I'm open to suggestions how to proceed. When your xstate cleanup patches were helped to go in ahead of mine, you promised to help mine going in afterwards. Yet nothing has happened (and I'm tired of re-submitting large pieces of work just for the sake of re-submitting, i.e. without having has [sufficient] feedback on the earlier version). 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Snapshot the CPU interface, distributor and last-CPU redistributor state, disable the ITS to cache its CTLR/CBASER/BASER registers, then restore everything and re-arm the collection on resume. Add list_for_each_entry_continue_reverse() in list.h for the ITS suspend error path that needs to roll back partially saved state. Based on Linux commit dba0bc7b76dc ("irqchip/gic-v3-its: Add ability to save/restore ITS state") Signed-off-by: Mykola Kvach --- Changes in V8: - Reword the CBASER/CWRITER comment to match Xen and drop the stale Linux cmd_write reference. - Clarify the list_for_each_entry_continue_reverse() comment. - Factor out per-ITS helpers for collection setup and resume. - Restore each ITS and re-establish its collection mapping in the same loop, so a failed ITS resume is not followed by MAPC/SYNC on that un-restored instance. - panic in case when resume of an ITS failed - cleanup baser cache during suspend --- xen/arch/arm/gic-v3-its.c | 126 ++++++++++++++++++++++++-- xen/arch/arm/gic-v3.c | 15 ++- xen/arch/arm/include/asm/gic_v3_its.h | 23 +++++ xen/include/xen/list.h | 14 +++ 4 files changed, 166 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 9ba068c46f..fe2865eac9 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -335,6 +335,22 @@ static int its_send_cmd_inv(struct host_its *its, return its_send_command(its, cmd); } +static int gicv3_its_setup_collection_single(struct host_its *its, + unsigned int cpu) +{ + int ret; + + ret = its_send_cmd_mapc(its, cpu, cpu); + if ( ret ) + return ret; + + ret = its_send_cmd_sync(its, cpu); + if ( ret ) + return ret; + + return gicv3_its_wait_commands(its); +} + /* Set up the (1:1) collection mapping for the given host CPU. */ int gicv3_its_setup_collection(unsigned int cpu) { @@ -343,15 +359,7 @@ int gicv3_its_setup_collection(unsigned int cpu) list_for_each_entry(its, &host_its_list, entry) { - ret = its_send_cmd_mapc(its, cpu, cpu); - if ( ret ) - return ret; - - ret = its_send_cmd_sync(its, cpu); - if ( ret ) - return ret; - - ret = gicv3_its_wait_commands(its); + ret = gicv3_its_setup_collection_single(its, cpu); if ( ret ) return ret; } @@ -1209,6 +1217,106 @@ int gicv3_its_init(void) return 0; } +#ifdef CONFIG_SYSTEM_SUSPEND +int gicv3_its_suspend(void) +{ + struct host_its *its; + int ret; + + list_for_each_entry(its, &host_its_list, entry) + { + unsigned int i; + void __iomem *base = its->its_base; + + its->suspend_ctx.ctlr = readl_relaxed(base + GITS_CTLR); + ret = gicv3_disable_its(its); + if ( ret ) + { + writel_relaxed(its->suspend_ctx.ctlr, base + GITS_CTLR); + goto err; + } + + its->suspend_ctx.cbaser = readq_relaxed(base + GITS_CBASER); + + for (i = 0; i < GITS_BASER_NR_REGS; i++) + { + uint64_t baser = readq_relaxed(base + GITS_BASER0 + i * 8); + + its->suspend_ctx.baser[i] = 0; + + if ( !(baser & GITS_VALID_BIT) ) + continue; + + its->suspend_ctx.baser[i] = baser; + } + } + + return 0; + + err: + list_for_each_entry_continue_reverse(its, &host_its_list, entry) + writel_relaxed(its->suspend_ctx.ctlr, its->its_base + GITS_CTLR); + + return ret; +} + +static int gicv3_its_resume_single(struct host_its *its, unsigned int cpu) +{ + void __iomem *base = its->its_base; + unsigned int i; + int ret; + + /* + * Make sure that the ITS is disabled. If it fails to quiesce, + * don't restore it since writing to CBASER or BASER + * registers is undefined according to the GIC v3 ITS + * Specification. + */ + WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE); + ret = gicv3_disable_its(its); + if ( ret ) + return ret; + + writeq_relaxed(its->suspend_ctx.cbaser, base + GITS_CBASER); + + /* + * Writing CBASER resets CREADR to 0, so reset CWRITER to + * keep the command queue pointers aligned. + */ + writeq_relaxed(0, base + GITS_CWRITER); + + /* Restore GITS_BASER from the value cache. */ + for ( i = 0; i < GITS_BASER_NR_REGS; i++ ) + { + uint64_t baser = its->suspend_ctx.baser[i]; + + if ( !(baser & GITS_VALID_BIT) ) + continue; + + writeq_relaxed(baser, base + GITS_BASER0 + i * 8); + } + + writel_relaxed(its->suspend_ctx.ctlr, base + GITS_CTLR); + + return gicv3_its_setup_collection_single(its, cpu); +} + +void gicv3_its_resume(void) +{ + struct host_its *its; + unsigned int cpu = smp_processor_id(); + int ret; + + list_for_each_entry(its, &host_its_list, entry) + { + ret = gicv3_its_resume_single(its, cpu); + if ( ret ) + panic("GICv3: ITS@%"PRIpaddr": failed to restore during resume: %d\n", + its->addr, ret); + } +} + +#endif /* CONFIG_SYSTEM_SUSPEND */ /* * Local variables: diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index d182a71478..ef8318dd50 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -862,7 +862,7 @@ static bool gicv3_enable_lpis(void) return true; } -static int __init gicv3_populate_rdist(void) +static int gicv3_populate_rdist(void) { int i; uint32_t aff; @@ -932,7 +932,7 @@ static int __init gicv3_populate_rdist(void) ret = gicv3_lpi_init_rdist(ptr); if ( ret && ret != -ENODEV && ret != -EBUSY ) { - printk("GICv3: CPU%d: Cannot initialize LPIs: %u\n", + printk("GICv3: CPU%d: Cannot initialize LPIs: %d\n", smp_processor_id(), ret); break; } @@ -2101,10 +2101,14 @@ static int gicv3_suspend(void) gicv3_disable_interface(); - ret = gicv3_disable_redist(); + ret = gicv3_its_suspend(); if ( ret ) goto out_enable_iface; + ret = gicv3_disable_redist(); + if ( ret ) + goto out_its_resume; + /* Save GICR configuration */ gicv3_redist_wait_for_rwp(); @@ -2140,6 +2144,9 @@ static int gicv3_suspend(void) return 0; + out_its_resume: + gicv3_its_resume(); + out_enable_iface: gicv3_hyp_enable(true); WRITE_SYSREG(gicv3_ctx.cpu.ctlr, ICC_CTLR_EL1); @@ -2212,6 +2219,8 @@ static void gicv3_resume(void) gicv3_redist_wait_for_rwp(); + gicv3_its_resume(); + WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2); isb(); diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index 081bd19180..3ca74435c8 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -129,6 +129,13 @@ struct host_its { spinlock_t cmd_lock; void *cmd_buf; unsigned int flags; +#ifdef CONFIG_SYSTEM_SUSPEND + struct suspend_ctx { + uint32_t ctlr; + uint64_t cbaser; + uint64_t baser[GITS_BASER_NR_REGS]; + } suspend_ctx; +#endif }; /* Map a collection for this host CPU to each host ITS. */ @@ -205,6 +212,11 @@ uint64_t gicv3_its_get_cacheability(void); uint64_t gicv3_its_get_shareability(void); unsigned int gicv3_its_get_memflags(void); +#ifdef CONFIG_SYSTEM_SUSPEND +int gicv3_its_suspend(void); +void gicv3_its_resume(void); +#endif + #else #ifdef CONFIG_ACPI @@ -272,6 +284,17 @@ static inline int gicv3_its_make_hwdom_dt_nodes(const struct domain *d, return 0; } +#ifdef CONFIG_SYSTEM_SUSPEND +static inline int gicv3_its_suspend(void) +{ + return 0; +} + +static inline void gicv3_its_resume(void) +{ +} +#endif + #endif /* CONFIG_HAS_ITS */ #endif diff --git a/xen/include/xen/list.h b/xen/include/xen/list.h index 98d8482dab..2aab274157 100644 --- a/xen/include/xen/list.h +++ b/xen/include/xen/list.h @@ -535,6 +535,20 @@ static inline void list_splice_init(struct list_head *list, &(pos)->member != (head); \ (pos) = list_entry((pos)->member.next, typeof(*(pos)), member)) +/** + * list_for_each_entry_continue_reverse - iterate backwards from the given point + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_head within the struct. + * + * Iterate over list of given type backwards, starting from the element previous + * to the current one in list order. + */ +#define list_for_each_entry_continue_reverse(pos, head, member) \ + for ((pos) = list_entry((pos)->member.prev, typeof(*(pos)), member); \ + &(pos)->member != (head); \ + (pos) = list_entry((pos)->member.prev, typeof(*(pos)), member)) + /** * list_for_each_entry_from - iterate over list of given type from the * current point -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271520.1559634 (Exim 4.92) (envelope-from ) id 1w8FaD-00045P-Di; Thu, 02 Apr 2026 10:47:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271520.1559634; Thu, 02 Apr 2026 10:47:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaD-00044A-Ah; Thu, 02 Apr 2026 10:47:29 +0000 Received: by outflank-mailman (input) for mailman id 1271520; Thu, 02 Apr 2026 10:47:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaC-0003yr-3q for xen-devel@lists.xenproject.org; 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Suspending timers in Xen consists of disabling the physical timer and the hypervisor timer on the current CPU. The virtual timer does not need explicit handling here, as it is already disabled on vCPU context switch and its state is restored per-vCPU on the next context restore. Resuming consists of raising TIMER_SOFTIRQ, which prompts the generic timer code to reprogram the hypervisor timer with the correct timeout. Xen does not use or expose the physical timer, so it remains disabled across suspend/resume. Introduce a new helper, disable_phys_hyp_timers(), to encapsulate disabling of the physical and hypervisor timers. Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykola Kvach Acked-by: Julien Grall --- Changes in V7: - Dropped EL1/EL2 wording; use "physical timer" and "hypervisor timer" - Renamed helper to disable_phys_hyp_timers() to reflect its actual scope - Clarified virtual timer handling (disabled on vCPU switch-out, restored on context restore) and added comments in suspend/resume paths - Added resume comment explaining which timers are restored by TIMER_SOFTIRQ --- xen/arch/arm/include/asm/time.h | 5 ++++ xen/arch/arm/time.c | 44 ++++++++++++++++++++++++++++----- 2 files changed, 43 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/time.h index c194dbb9f5..9313b157ea 100644 --- a/xen/arch/arm/include/asm/time.h +++ b/xen/arch/arm/include/asm/time.h @@ -105,6 +105,11 @@ void preinit_xen_time(void); void force_update_vcpu_system_time(struct vcpu *v); +#ifdef CONFIG_SYSTEM_SUSPEND +void time_suspend(void); +void time_resume(void); +#endif /* CONFIG_SYSTEM_SUSPEND */ + #endif /* __ARM_TIME_H__ */ /* * Local variables: diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index a12912a106..f91dc64099 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -296,6 +296,14 @@ static void check_timer_irq_cfg(unsigned int irq, const char *which) static DEFINE_PER_CPU_READ_MOSTLY(struct irqaction, irq_hyp); static DEFINE_PER_CPU_READ_MOSTLY(struct irqaction, irq_virt); +/* Disable physical and hypervisor timers on the current CPU */ +static inline void disable_phys_hyp_timers(void) +{ + WRITE_SYSREG(0, CNTP_CTL_EL0); /* Physical timer disabled */ + WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ + isb(); +} + /* Set up the timer interrupt on this CPU */ void init_timer_interrupt(void) { @@ -306,9 +314,7 @@ void init_timer_interrupt(void) WRITE_SYSREG64(0, CNTVOFF_EL2); /* No VM-specific offset */ /* Do not let the VMs program the physical timer, only read the physical counter */ WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2); - WRITE_SYSREG(0, CNTP_CTL_EL0); /* Physical timer disabled */ - WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Hypervisor's timer disabled */ - isb(); + disable_phys_hyp_timers(); hyp_action->name = "hyptimer"; hyp_action->handler = htimer_interrupt; @@ -333,9 +339,7 @@ void init_timer_interrupt(void) */ static void deinit_timer_interrupt(void) { - WRITE_SYSREG(0, CNTP_CTL_EL0); /* Disable physical timer */ - WRITE_SYSREG(0, CNTHP_CTL_EL2); /* Disable hypervisor's timer */ - isb(); + disable_phys_hyp_timers(); release_irq(timer_irq[TIMER_HYP_PPI], NULL); release_irq(timer_irq[TIMER_VIRT_PPI], NULL); @@ -375,6 +379,34 @@ void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) /* XXX update guest visible wallclock time */ } +#ifdef CONFIG_SYSTEM_SUSPEND + +void time_suspend(void) +{ + /* CNTV already disabled by virt_timer_save() during vcpu context switch. */ + disable_phys_hyp_timers(); +} + +void time_resume(void) +{ + /* + * Raising TIMER_SOFTIRQ triggers generic timer code to reprogram the + * hypervisor timer with the correct timeout (not known here). + * + * Xen doesn't use or expose the physical timer, so it remains disabled + * across suspend/resume. + * + * The virtual timer state is restored per-vCPU on the next context switch. + * + * No further action is needed to restore timekeeping after power down, + * since the system counter is unaffected. See ARM DDI 0487 L.a, D12.1.2 + * "The system counter must be implemented in an always-on power domain." + */ + raise_softirq(TIMER_SOFTIRQ); +} + +#endif /* CONFIG_SYSTEM_SUSPEND */ + static int cpu_time_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271526.1559682 (Exim 4.92) (envelope-from ) id 1w8FaJ-0005NL-6z; Thu, 02 Apr 2026 10:47:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271526.1559682; Thu, 02 Apr 2026 10:47:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaJ-0005N0-3l; Thu, 02 Apr 2026 10:47:35 +0000 Received: by outflank-mailman (input) for mailman id 1271526; Thu, 02 Apr 2026 10:47:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaH-0004vd-62 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaG-00Ej0u-IP for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:32 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce493d-2eae-0a2a0a5409dd-0a2a450be30c-20 for ; Thu, 02 Apr 2026 12:47:32 +0200 Received: from [209.85.208.46] (helo=mail-ed1-f46.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4944-bca8-0a2a450b0019-d155d02eadcf-3 for ; Thu, 02 Apr 2026 12:47:32 +0200 Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-65c4152313fso1006449a12.1 for ; Thu, 02 Apr 2026 03:47:32 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Calling it from the CPU hotplug/resume path then executed discarded code, which could crash Xen. Drop __init so the TEE mediator secondary init can run safely on hotplugged and resumed CPUs. Signed-off-by: Mykola Kvach --- xen/arch/arm/tee/tee.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/tee/tee.c b/xen/arch/arm/tee/tee.c index 8501443c8e..00e561fc78 100644 --- a/xen/arch/arm/tee/tee.c +++ b/xen/arch/arm/tee/tee.c @@ -128,7 +128,7 @@ static int __init tee_init(void) presmp_initcall(tee_init); -void __init init_tee_secondary(void) +void init_tee_secondary(void) { if ( cur_mediator && cur_mediator->ops->init_secondary ) cur_mediator->ops->init_secondary(); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271521.1559642 (Exim 4.92) (envelope-from ) id 1w8FaD-0004Ay-RV; Thu, 02 Apr 2026 10:47:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271521.1559642; Thu, 02 Apr 2026 10:47:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaD-00049E-K6; Thu, 02 Apr 2026 10:47:29 +0000 Received: by outflank-mailman (input) for mailman id 1271521; Thu, 02 Apr 2026 10:47:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaC-0003z0-Jl for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:28 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaC-009q68-0I for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:28 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4936-e002-0a2a0a5209dd-0a2a4507b904-28 for ; Thu, 02 Apr 2026 12:47:27 +0200 Received: from [209.85.208.45] (helo=mail-ed1-f45.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce493f-ba2d-0a2a45070019-d155d02dccda-3 for ; Thu, 02 Apr 2026 12:47:27 +0200 Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-66bb66db39dso1187246a12.0 for ; Thu, 02 Apr 2026 03:47:27 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Therefore, Xen should save/restore the context of GIC on suspend/resume. Note that the context consists of states of registers which are controlled by the hypervisor. Other GIC registers which are accessible by guests are saved/restored on context switch. Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in V8: - disable cpu interface + distributor before suspend - change 0xffffffff to GENMASK; - cosmetic changes; Changes in V7: - Allocate one contiguous memory block for the GICv2 dist suspend context. - gicv2_resume() no longer unconditionally re-enables the distributor/CPU interface; it now writes back the saved CTLR values as-is. - gicv2_alloc_context() now returns 0 on success and panics on failure, since suspend context allocation is not recoverable. --- xen/arch/arm/gic-v2.c | 132 +++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 29 ++++++++ xen/arch/arm/include/asm/gic.h | 12 +++ 3 files changed, 173 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index b23e72a3d0..dbff470962 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -1098,6 +1098,129 @@ static int gicv2_iomem_deny_access(struct domain *d) return iomem_deny_access(d, mfn, mfn + nr); } +#ifdef CONFIG_SYSTEM_SUSPEND + +/* This struct represents block of 32 IRQs */ +struct irq_block { + uint32_t icfgr[2]; /* 2 registers of 16 IRQs each */ + uint32_t ipriorityr[8]; + uint32_t isenabler; + uint32_t isactiver; + uint32_t itargetsr[8]; +}; + +/* GICv2 registers to be saved/restored on system suspend/resume */ +struct gicv2_context { + /* GICC context */ + struct cpu_ctx { + uint32_t ctlr; + uint32_t pmr; + uint32_t bpr; + } cpu; + + /* GICD context */ + struct dist_ctx { + uint32_t ctlr; + /* Includes banked SGI/PPI state for the boot CPU. */ + struct irq_block *irqs; + } dist; +}; + +static struct gicv2_context gic_ctx; + +static int gicv2_suspend(void) +{ + unsigned int i, blocks = DIV_ROUND_UP(gicv2_info.nr_lines, 32); + + /* Save GICC_CTLR configuration. */ + gic_ctx.cpu.ctlr = readl_gicc(GICC_CTLR); + + /* Quiesce the GIC CPU interface before suspend. */ + gicv2_cpu_disable(); + + /* Save GICD configuration */ + gic_ctx.dist.ctlr = readl_gicd(GICD_CTLR); + writel_gicd(0, GICD_CTLR); + + gic_ctx.cpu.pmr = readl_gicc(GICC_PMR); + gic_ctx.cpu.bpr = readl_gicc(GICC_BPR); + + for ( i = 0; i < blocks; i++ ) + { + struct irq_block *irqs = gic_ctx.dist.irqs + i; + size_t j, off = i * sizeof(irqs->isenabler); + + irqs->isenabler = readl_gicd(GICD_ISENABLER + off); + irqs->isactiver = readl_gicd(GICD_ISACTIVER + off); + + off = i * sizeof(irqs->ipriorityr); + for ( j = 0; j < ARRAY_SIZE(irqs->ipriorityr); j++ ) + { + irqs->ipriorityr[j] = readl_gicd(GICD_IPRIORITYR + off + j * 4); + irqs->itargetsr[j] = readl_gicd(GICD_ITARGETSR + off + j * 4); + } + + off = i * sizeof(irqs->icfgr); + for ( j = 0; j < ARRAY_SIZE(irqs->icfgr); j++ ) + irqs->icfgr[j] = readl_gicd(GICD_ICFGR + off + j * 4); + } + + return 0; +} + +static void gicv2_resume(void) +{ + unsigned int i, blocks = DIV_ROUND_UP(gicv2_info.nr_lines, 32); + + gicv2_cpu_disable(); + /* Disable distributor */ + writel_gicd(0, GICD_CTLR); + + for ( i = 0; i < blocks; i++ ) + { + struct irq_block *irqs = gic_ctx.dist.irqs + i; + size_t j, off = i * sizeof(irqs->isenabler); + + writel_gicd(GENMASK(31, 0), GICD_ICENABLER + off); + writel_gicd(irqs->isenabler, GICD_ISENABLER + off); + + writel_gicd(GENMASK(31, 0), GICD_ICACTIVER + off); + writel_gicd(irqs->isactiver, GICD_ISACTIVER + off); + + off = i * sizeof(irqs->ipriorityr); + for ( j = 0; j < ARRAY_SIZE(irqs->ipriorityr); j++ ) + { + writel_gicd(irqs->ipriorityr[j], GICD_IPRIORITYR + off + j * 4); + writel_gicd(irqs->itargetsr[j], GICD_ITARGETSR + off + j * 4); + } + + off = i * sizeof(irqs->icfgr); + for ( j = 0; j < ARRAY_SIZE(irqs->icfgr); j++ ) + writel_gicd(irqs->icfgr[j], GICD_ICFGR + off + j * 4); + } + + /* Make sure all registers are restored and enable distributor */ + writel_gicd(gic_ctx.dist.ctlr, GICD_CTLR); + + /* Restore GIC CPU interface configuration */ + writel_gicc(gic_ctx.cpu.pmr, GICC_PMR); + writel_gicc(gic_ctx.cpu.bpr, GICC_BPR); + + /* Enable GIC CPU interface */ + writel_gicc(gic_ctx.cpu.ctlr, GICC_CTLR); +} + +static void __init gicv2_alloc_context(void) +{ + uint32_t blocks = DIV_ROUND_UP(gicv2_info.nr_lines, 32); + + gic_ctx.dist.irqs = xzalloc_array(struct irq_block, blocks); + if ( !gic_ctx.dist.irqs ) + panic("Failed to allocate memory for GICv2 suspend context\n"); +} + +#endif /* CONFIG_SYSTEM_SUSPEND */ + #ifdef CONFIG_ACPI static unsigned long gicv2_get_hwdom_extra_madt_size(const struct domain *d) { @@ -1302,6 +1425,11 @@ static int __init gicv2_init(void) spin_unlock(&gicv2.lock); +#ifdef CONFIG_SYSTEM_SUSPEND + /* Allocate memory to be used for saving GIC context during the suspend */ + gicv2_alloc_context(); +#endif /* CONFIG_SYSTEM_SUSPEND */ + return 0; } @@ -1345,6 +1473,10 @@ static const struct gic_hw_operations gicv2_ops = { .map_hwdom_extra_mappings = gicv2_map_hwdom_extra_mappings, .iomem_deny_access = gicv2_iomem_deny_access, .do_LPI = gicv2_do_LPI, +#ifdef CONFIG_SYSTEM_SUSPEND + .suspend = gicv2_suspend, + .resume = gicv2_resume, +#endif /* CONFIG_SYSTEM_SUSPEND */ }; /* Set up the GIC */ diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index ee75258fc3..7727ffed5a 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -432,6 +432,35 @@ int gic_iomem_deny_access(struct domain *d) return gic_hw_ops->iomem_deny_access(d); } +#ifdef CONFIG_SYSTEM_SUSPEND + +int gic_suspend(void) +{ + /* Must be called by boot CPU#0 with interrupts disabled */ + ASSERT(!local_irq_is_enabled()); + ASSERT(!smp_processor_id()); + + if ( !gic_hw_ops->suspend || !gic_hw_ops->resume ) + return -ENOSYS; + + return gic_hw_ops->suspend(); +} + +void gic_resume(void) +{ + /* + * Must be called by boot CPU#0 with interrupts disabled after gic_suspend + * has returned successfully. + */ + ASSERT(!local_irq_is_enabled()); + ASSERT(!smp_processor_id()); + ASSERT(gic_hw_ops->resume); + + gic_hw_ops->resume(); +} + +#endif /* CONFIG_SYSTEM_SUSPEND */ + static int cpu_gic_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 8e713aa477..8e8f4ac4c5 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -280,6 +280,12 @@ extern int gicv_setup(struct domain *d); extern void gic_save_state(struct vcpu *v); extern void gic_restore_state(struct vcpu *v); +#ifdef CONFIG_SYSTEM_SUSPEND +/* Suspend/resume */ +extern int gic_suspend(void); +extern void gic_resume(void); +#endif /* CONFIG_SYSTEM_SUSPEND */ + /* SGI (AKA IPIs) */ enum gic_sgi { GIC_SGI_EVENT_CHECK, @@ -423,6 +429,12 @@ struct gic_hw_operations { int (*iomem_deny_access)(struct domain *d); /* Handle LPIs, which require special handling */ void (*do_LPI)(unsigned int lpi); +#ifdef CONFIG_SYSTEM_SUSPEND + /* Save GIC configuration due to the system suspend */ + int (*suspend)(void); + /* Restore GIC configuration due to the system resume */ + void (*resume)(void); +#endif /* CONFIG_SYSTEM_SUSPEND */ }; extern const struct gic_hw_operations *gic_hw_ops; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271527.1559689 (Exim 4.92) (envelope-from ) id 1w8FaJ-0005RK-PK; Thu, 02 Apr 2026 10:47:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271527.1559689; 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As a result, CPUs going offline and back online could end up with stale or missing handlers, breaking delivery of FF-A notifications. Signed-off-by: Mykola Kvach --- xen/arch/arm/tee/ffa_notif.c | 63 ++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 186e726412..513c399594 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -360,10 +360,28 @@ static int32_t ffa_notification_bitmap_destroy(uint16_t vm_id) return ffa_simple_call(FFA_NOTIFICATION_BITMAP_DESTROY, vm_id, 0, 0, 0); } -void ffa_notif_init_interrupt(void) +static DEFINE_PER_CPU_READ_MOSTLY(struct irqaction, sri_irq); + +static int request_sri_irq(void) { int ret; + struct irqaction *sri_action = &this_cpu(sri_irq); + + sri_action->name = "FF-A notif"; + sri_action->handler = notif_irq_handler; + sri_action->dev_id = NULL; + sri_action->free_on_release = 0; + + ret = setup_irq(notif_sri_irq, 0, sri_action); + if ( ret ) + printk(XENLOG_ERR "ffa: setup_irq irq %u failed: error %d\n", + notif_sri_irq, ret); + return ret; +} + +void ffa_notif_init_interrupt(void) +{ if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI ) { /* @@ -376,14 +394,36 @@ void ffa_notif_init_interrupt(void) * pending, while the SPMC in the secure world will not notice that * the interrupt was lost. */ - ret = request_irq(notif_sri_irq, 0, notif_irq_handler, "FF-A notif", - NULL); - if ( ret ) - printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\n", - notif_sri_irq, ret); + request_sri_irq(); } } +static void deinit_ffa_notif_interrupt(void) +{ + if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI ) + release_irq(notif_sri_irq, NULL); +} + +static int cpu_ffa_notif_callback(struct notifier_block *nfb, + unsigned long action, + void *hcpu) +{ + switch ( action ) + { + case CPU_DYING: + deinit_ffa_notif_interrupt(); + break; + default: + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block cpu_ffa_notif_nfb = { + .notifier_call = cpu_ffa_notif_callback, +}; + void ffa_notif_init(void) { const struct arm_smccc_1_2_regs arg = { @@ -392,7 +432,6 @@ void ffa_notif_init(void) }; struct arm_smccc_1_2_regs resp; unsigned int irq; - int ret; /* Only enable fw notification if all ABIs we need are supported */ if ( ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) && @@ -408,13 +447,11 @@ void ffa_notif_init(void) notif_sri_irq = irq; if ( irq >= NR_GIC_SGI ) irq_set_type(irq, IRQ_TYPE_EDGE_RISING); - ret = request_irq(irq, 0, notif_irq_handler, "FF-A notif", NULL); - if ( ret ) - { - printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\n", - irq, ret); + + if ( request_sri_irq() ) return; - } + + register_cpu_notifier(&cpu_ffa_notif_nfb); fw_notif_enabled = true; } } -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271523.1559661 (Exim 4.92) (envelope-from ) id 1w8FaG-0004fZ-9S; Thu, 02 Apr 2026 10:47:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271523.1559661; Thu, 02 Apr 2026 10:47:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaG-0004e6-2Y; Thu, 02 Apr 2026 10:47:32 +0000 Received: by outflank-mailman (input) for mailman id 1271523; Thu, 02 Apr 2026 10:47:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaE-0004Wm-Mn for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaE-00Ej0u-35 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:30 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4935-2eae-0a2a0a5409dd-0a2a4508a782-8 for ; Thu, 02 Apr 2026 12:47:30 +0200 Received: from [209.85.218.53] (helo=mail-ej1-f53.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4941-fab6-0a2a45080019-d155da35c9f8-3 for ; Thu, 02 Apr 2026 12:47:30 +0200 Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-b9c3a9fe80fso90505966b.3 for ; Thu, 02 Apr 2026 03:47:29 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Therefore, Xen should save/restore the context of GIC on suspend/resume. Note that the context consists of states of registers which are controlled by the hypervisor. Other GIC registers which are accessible by guests are saved/restored on context switch. Signed-off-by: Mykola Kvach --- Changes in V8: - use right rdist base for prop/pend baser and ctrl Changes in V7: - restore LPI regs on resume - add timeout during redist disabling - squash with suspend/resume handling for GICv3 eSPI registers - drop ITS guard paths so suspend/resume always runs; switch missing ctx allocation to panic - trim TODO comments; narrow redistributor storage to PPI icfgr - keep distributor context allocation even without ITS; adjust resume to use GENMASK(31, 0) for clearing enables - drop storage of the SGI configuration register, as SGIs are always edge-triggered --- xen/arch/arm/gic-v3-lpi.c | 3 + xen/arch/arm/gic-v3.c | 321 ++++++++++++++++++++++++- xen/arch/arm/include/asm/gic_v3_defs.h | 1 + 3 files changed, 322 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 125f51e61b..01120aeed9 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -466,6 +466,9 @@ static int cpu_callback(struct notifier_block *nfb, unsigned long action, switch ( action ) { case CPU_UP_PREPARE: + if ( system_state == SYS_STATE_resume ) + break; + rc = gicv3_lpi_allocate_pendtable(cpu); if ( rc ) printk(XENLOG_ERR "Unable to allocate the pendtable for CPU%lu\n", diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 34fb065afc..d182a71478 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1072,12 +1072,12 @@ out: return res; } -static void gicv3_hyp_disable(void) +static void gicv3_hyp_enable(bool enable) { register_t hcr; hcr = READ_SYSREG(ICH_HCR_EL2); - hcr &= ~GICH_HCR_EN; + hcr = enable ? (hcr | GICH_HCR_EN) : (hcr & ~GICH_HCR_EN); WRITE_SYSREG(hcr, ICH_HCR_EL2); isb(); } @@ -1184,7 +1184,7 @@ static void gicv3_disable_interface(void) spin_lock(&gicv3.lock); gicv3_cpu_disable(); - gicv3_hyp_disable(); + gicv3_hyp_enable(false); spin_unlock(&gicv3.lock); } @@ -1920,6 +1920,313 @@ static bool gic_dist_supports_lpis(void) return (readl_relaxed(GICD + GICD_TYPER) & GICD_TYPE_LPIS); } +#ifdef CONFIG_SYSTEM_SUSPEND + +/* This struct represent block of 32 IRQs */ +struct dist_irq_block { + uint32_t icfgr[2]; + uint32_t ipriorityr[8]; + uint64_t irouter[32]; + uint32_t isactiver; + uint32_t isenabler; +}; + +struct redist_ctx { + uint32_t ctlr; + uint32_t icfgr; /* only PPIs stored */ + uint32_t igroupr; + uint32_t ipriorityr[8]; + uint32_t isactiver; + uint32_t isenabler; + + uint64_t pendbase; + uint64_t propbase; +}; + +/* GICv3 registers to be saved/restored on system suspend/resume */ +struct gicv3_ctx { + struct dist_ctx { + uint32_t ctlr; + struct dist_irq_block *irqs, *espi_irqs; + } dist; + + /* have only one rdist structure for last running CPU during suspend */ + struct redist_ctx rdist; + + struct cpu_ctx { + uint32_t ctlr; + uint32_t pmr; + uint32_t bpr; + uint32_t sre_el2; + uint32_t grpen; + } cpu; +}; + +static struct gicv3_ctx gicv3_ctx; + +static void __init gicv3_alloc_context(void) +{ + uint32_t blocks = DIV_ROUND_UP(gicv3_info.nr_lines, 32); + + /* The spec allows for systems without any SPIs */ + if ( blocks > 1 ) + { + gicv3_ctx.dist.irqs = xzalloc_array(struct dist_irq_block, blocks - 1); + if ( !gicv3_ctx.dist.irqs ) + panic("Failed to allocate memory for GICv3 suspend context\n"); + } + +#ifdef CONFIG_GICV3_ESPI + if ( !gic_number_espis() ) + return; + + blocks = gic_number_espis() / 32; + gicv3_ctx.dist.espi_irqs = xzalloc_array(struct dist_irq_block, blocks); + if ( !gicv3_ctx.dist.espi_irqs ) + panic("Failed to allocate memory for GICv3 eSPI suspend context\n"); +#endif +} + +static int gicv3_disable_redist(void) +{ + void __iomem *waker = GICD_RDIST_BASE + GICR_WAKER; + s_time_t deadline; + + /* + * Avoid infinite loop if Non-secure does not have access to GICR_WAKER. + * See Arm IHI 0069H.b, 12.11.42 GICR_WAKER: + * When GICD_CTLR.DS == 0 and an access is Non-secure accesses to this + * register are RAZ/WI. + */ + if ( !(readl_relaxed(GICD + GICD_CTLR) & GICD_CTLR_DS) ) + return 0; + + deadline = NOW() + MILLISECS(1000); + + writel_relaxed(readl_relaxed(waker) | GICR_WAKER_ProcessorSleep, waker); + while ( (readl_relaxed(waker) & GICR_WAKER_ChildrenAsleep) == 0 ) + { + if ( NOW() > deadline ) + { + printk("GICv3: Timeout waiting for redistributor to sleep\n"); + return -ETIMEDOUT; + } + cpu_relax(); + udelay(10); + } + + return 0; +} + +#define GET_SPI_REG_OFFSET(name, is_espi) \ + ((is_espi) ? GICD_##name##nE : GICD_##name) + +static void gicv3_store_spi_irq_block(struct dist_irq_block *irqs, + unsigned int i, bool is_espi) +{ + void __iomem *base; + unsigned int irq; + + base = GICD + GET_SPI_REG_OFFSET(ICFGR, is_espi) + i * sizeof(irqs->icfgr); + irqs->icfgr[0] = readl_relaxed(base); + irqs->icfgr[1] = readl_relaxed(base + 4); + + base = GICD + GET_SPI_REG_OFFSET(IPRIORITYR, is_espi); + base += i * sizeof(irqs->ipriorityr); + for ( irq = 0; irq < ARRAY_SIZE(irqs->ipriorityr); irq++ ) + irqs->ipriorityr[irq] = readl_relaxed(base + 4 * irq); + + base = GICD + GET_SPI_REG_OFFSET(IROUTER, is_espi); + base += i * sizeof(irqs->irouter); + for ( irq = 0; irq < ARRAY_SIZE(irqs->irouter); irq++ ) + irqs->irouter[irq] = readq_relaxed_non_atomic(base + 8 * irq); + + base = GICD + GET_SPI_REG_OFFSET(ISACTIVER, is_espi); + base += i * sizeof(irqs->isactiver); + irqs->isactiver = readl_relaxed(base); + + base = GICD + GET_SPI_REG_OFFSET(ISENABLER, is_espi); + base += i * sizeof(irqs->isenabler); + irqs->isenabler = readl_relaxed(base); +} + +static void gicv3_restore_spi_irq_block(struct dist_irq_block *irqs, + unsigned int i, bool is_espi) +{ + void __iomem *base; + unsigned int irq; + + base = GICD + GET_SPI_REG_OFFSET(ICFGR, is_espi) + i * sizeof(irqs->icfgr); + writel_relaxed(irqs->icfgr[0], base); + writel_relaxed(irqs->icfgr[1], base + 4); + + base = GICD + GET_SPI_REG_OFFSET(IPRIORITYR, is_espi); + base += i * sizeof(irqs->ipriorityr); + for ( irq = 0; irq < ARRAY_SIZE(irqs->ipriorityr); irq++ ) + writel_relaxed(irqs->ipriorityr[irq], base + 4 * irq); + + base = GICD + GET_SPI_REG_OFFSET(IROUTER, is_espi); + base += i * sizeof(irqs->irouter); + for ( irq = 0; irq < ARRAY_SIZE(irqs->irouter); irq++ ) + writeq_relaxed_non_atomic(irqs->irouter[irq], base + 8 * irq); + + base = GICD + GET_SPI_REG_OFFSET(ICENABLER, is_espi) + i * 4; + writel_relaxed(GENMASK(31, 0), base); + + base = GICD + GET_SPI_REG_OFFSET(ISENABLER, is_espi); + base += i * sizeof(irqs->isenabler); + writel_relaxed(irqs->isenabler, base); + + base = GICD + GET_SPI_REG_OFFSET(ICACTIVER, is_espi) + i * 4; + writel_relaxed(GENMASK(31, 0), base); + + base = GICD + GET_SPI_REG_OFFSET(ISACTIVER, is_espi); + base += i * sizeof(irqs->isactiver); + writel_relaxed(irqs->isactiver, base); +} + +static int gicv3_suspend(void) +{ + unsigned int i; + void __iomem *base; + int ret; + struct redist_ctx *rdist = &gicv3_ctx.rdist; + + /* Save GICC configuration */ + gicv3_ctx.cpu.ctlr = READ_SYSREG(ICC_CTLR_EL1); + gicv3_ctx.cpu.pmr = READ_SYSREG(ICC_PMR_EL1); + gicv3_ctx.cpu.bpr = READ_SYSREG(ICC_BPR1_EL1); + gicv3_ctx.cpu.sre_el2 = READ_SYSREG(ICC_SRE_EL2); + gicv3_ctx.cpu.grpen = READ_SYSREG(ICC_IGRPEN1_EL1); + + gicv3_disable_interface(); + + ret = gicv3_disable_redist(); + if ( ret ) + goto out_enable_iface; + + /* Save GICR configuration */ + gicv3_redist_wait_for_rwp(); + + base = GICD_RDIST_BASE; + + rdist->ctlr = readl_relaxed(base + GICR_CTLR); + + rdist->propbase = readq_relaxed(base + GICR_PROPBASER); + rdist->pendbase = readq_relaxed(base + GICR_PENDBASER); + + base = GICD_RDIST_SGI_BASE; + + /* Save priority on PPI and SGI interrupts */ + for ( i = 0; i < NR_GIC_LOCAL_IRQS / 4; i++ ) + rdist->ipriorityr[i] = readl_relaxed(base + GICR_IPRIORITYR0 + 4 * i); + + rdist->isactiver = readl_relaxed(base + GICR_ISACTIVER0); + rdist->isenabler = readl_relaxed(base + GICR_ISENABLER0); + rdist->igroupr = readl_relaxed(base + GICR_IGROUPR0); + rdist->icfgr = readl_relaxed(base + GICR_ICFGR1); + + /* Save GICD configuration */ + gicv3_dist_wait_for_rwp(); + gicv3_ctx.dist.ctlr = readl_relaxed(GICD + GICD_CTLR); + + for ( i = 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ ) + gicv3_store_spi_irq_block(gicv3_ctx.dist.irqs + i - 1, i, false); + +#ifdef CONFIG_GICV3_ESPI + for ( i = 0; i < gic_number_espis() / 32; i++ ) + gicv3_store_spi_irq_block(gicv3_ctx.dist.espi_irqs + i, i, true); +#endif + + return 0; + + out_enable_iface: + gicv3_hyp_enable(true); + WRITE_SYSREG(gicv3_ctx.cpu.ctlr, ICC_CTLR_EL1); + isb(); + + return ret; +} + +static void gicv3_resume(void) +{ + int ret; + unsigned int i; + void __iomem *base; + struct redist_ctx *rdist = &gicv3_ctx.rdist; + + writel_relaxed(0, GICD + GICD_CTLR); + + for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 ) + writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4); + + for ( i = 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ ) + gicv3_restore_spi_irq_block(gicv3_ctx.dist.irqs + i - 1, i, false); + +#ifdef CONFIG_GICV3_ESPI + for ( i = 0; i < gic_number_espis() / 32; i++ ) + gicv3_restore_spi_irq_block(gicv3_ctx.dist.espi_irqs + i, i, true); +#endif + + writel_relaxed(gicv3_ctx.dist.ctlr, GICD + GICD_CTLR); + gicv3_dist_wait_for_rwp(); + + ret = gicv3_lpi_init_rdist(GICD_RDIST_BASE); + /* + * If LPIs are already enabled, assume firmware or the still-powered + * redistributor has valid PROPBASER/PENDBASER and skip reprogramming. + * Return -EBUSY so callers can ignore this case. + */ + if ( ret && ret != -ENODEV && ret != -EBUSY ) + panic("GICv3: Failed to re-initialize LPIs during resume\n"); + else if ( ret == -EBUSY ) /* extra checks, just to be sure */ + { + base = GICD_RDIST_BASE; + if ( readq_relaxed(base + GICR_PROPBASER) != rdist->propbase || + readq_relaxed(base + GICR_PENDBASER) != rdist->pendbase ) + { + panic("GICv3: LPIs already enabled with unexpected PROPBASER/PENDBASER during resume\n"); + } + } + + /* Restore GICR (Redistributor) configuration */ + if ( gicv3_enable_redist() ) + panic("GICv3: Failed to re-enable redistributor during resume\n"); + + base = GICD_RDIST_SGI_BASE; + + writel_relaxed(GENMASK(31, 0), base + GICR_ICENABLER0); + gicv3_redist_wait_for_rwp(); + + for ( i = 0; i < NR_GIC_LOCAL_IRQS / 4; i++ ) + writel_relaxed(rdist->ipriorityr[i], base + GICR_IPRIORITYR0 + i * 4); + + writel_relaxed(rdist->isactiver, base + GICR_ISACTIVER0); + writel_relaxed(rdist->igroupr, base + GICR_IGROUPR0); + writel_relaxed(rdist->icfgr, base + GICR_ICFGR1); + + gicv3_redist_wait_for_rwp(); + + writel_relaxed(rdist->isenabler, base + GICR_ISENABLER0); + writel_relaxed(rdist->ctlr, GICD_RDIST_BASE + GICR_CTLR); + + gicv3_redist_wait_for_rwp(); + + WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2); + isb(); + + /* Restore CPU interface (System registers) */ + WRITE_SYSREG(gicv3_ctx.cpu.pmr, ICC_PMR_EL1); + WRITE_SYSREG(gicv3_ctx.cpu.bpr, ICC_BPR1_EL1); + WRITE_SYSREG(gicv3_ctx.cpu.ctlr, ICC_CTLR_EL1); + WRITE_SYSREG(gicv3_ctx.cpu.grpen, ICC_IGRPEN1_EL1); + isb(); + + gicv3_hyp_init(); +} + +#endif /* CONFIG_SYSTEM_SUSPEND */ + /* Set up the GIC */ static int __init gicv3_init(void) { @@ -1994,6 +2301,10 @@ static int __init gicv3_init(void) gicv3_hyp_init(); +#ifdef CONFIG_SYSTEM_SUSPEND + gicv3_alloc_context(); +#endif + out: spin_unlock(&gicv3.lock); @@ -2033,6 +2344,10 @@ static const struct gic_hw_operations gicv3_ops = { #endif .iomem_deny_access = gicv3_iomem_deny_access, .do_LPI = gicv3_do_LPI, +#ifdef CONFIG_SYSTEM_SUSPEND + .suspend = gicv3_suspend, + .resume = gicv3_resume, +#endif }; static int __init gicv3_dt_preinit(struct dt_device_node *node, const void *data) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index c373b94d19..992c8f9c2f 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -94,6 +94,7 @@ #define GICD_TYPE_LPIS (1U << 17) #define GICD_CTLR_RWP (1UL << 31) +#define GICD_CTLR_DS (1U << 6) #define GICD_CTLR_ARE_NS (1U << 4) #define GICD_CTLR_ENABLE_G1A (1U << 1) #define GICD_CTLR_ENABLE_G1 (1U << 0) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271528.1559700 (Exim 4.92) (envelope-from ) id 1w8FaL-0005pC-5R; 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Tested on R-Car H3 Starter Kit. Signed-off-by: Oleksandr Tyshchenko Signed-off-by: Mykola Kvach --- Changes in V7: - moved suspend context allocation before pci stuff --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 305 ++++++++++++++++++++++- 1 file changed, 298 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index ea9fa9ddf3..6765bd3083 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -71,6 +71,8 @@ }) #endif +#define dev_dbg(dev, fmt, ...) \ + dev_print(dev, XENLOG_DEBUG, fmt, ## __VA_ARGS__) #define dev_info(dev, fmt, ...) \ dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__) #define dev_warn(dev, fmt, ...) \ @@ -130,6 +132,24 @@ struct ipmmu_features { unsigned int imuctr_ttsel_mask; }; +#ifdef CONFIG_SYSTEM_SUSPEND + +struct ipmmu_reg_ctx { + unsigned int imttlbr0; + unsigned int imttubr0; + unsigned int imttbcr; + unsigned int imctr; +}; + +struct ipmmu_vmsa_backup { + struct device *dev; + unsigned int *utlbs_val; + unsigned int *asids_val; + struct list_head list; +}; + +#endif + /* Root/Cache IPMMU device's information */ struct ipmmu_vmsa_device { struct device *dev; @@ -142,6 +162,9 @@ struct ipmmu_vmsa_device { struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX]; unsigned int utlb_refcount[IPMMU_UTLB_MAX]; const struct ipmmu_features *features; +#ifdef CONFIG_SYSTEM_SUSPEND + struct ipmmu_reg_ctx *reg_backup[IPMMU_CTX_MAX]; +#endif }; /* @@ -547,6 +570,245 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu, spin_unlock_irqrestore(&mmu->lock, flags); } +#ifdef CONFIG_SYSTEM_SUSPEND + +static DEFINE_SPINLOCK(ipmmu_devices_backup_lock); +static LIST_HEAD(ipmmu_devices_backup); + +static struct ipmmu_reg_ctx root_pgtable[IPMMU_CTX_MAX]; + +static uint32_t ipmmu_imuasid_read(struct ipmmu_vmsa_device *mmu, + unsigned int utlb) +{ + return ipmmu_read(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb))); +} + +static void ipmmu_utlbs_backup(struct ipmmu_vmsa_device *mmu) +{ + struct ipmmu_vmsa_backup *backup_data; + + dev_dbg(mmu->dev, "Handle micro-TLBs backup\n"); + + spin_lock(&ipmmu_devices_backup_lock); + + list_for_each_entry( backup_data, &ipmmu_devices_backup, list ) + { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(backup_data->dev); + unsigned int i; + + if ( to_ipmmu(backup_data->dev) != mmu ) + continue; + + for ( i = 0; i < fwspec->num_ids; i++ ) + { + unsigned int utlb = fwspec->ids[i]; + + backup_data->asids_val[i] = ipmmu_imuasid_read(mmu, utlb); + backup_data->utlbs_val[i] = ipmmu_imuctr_read(mmu, utlb); + } + } + + spin_unlock(&ipmmu_devices_backup_lock); +} + +static void ipmmu_utlbs_restore(struct ipmmu_vmsa_device *mmu) +{ + struct ipmmu_vmsa_backup *backup_data; + + dev_dbg(mmu->dev, "Handle micro-TLBs restore\n"); + + spin_lock(&ipmmu_devices_backup_lock); + + list_for_each_entry( backup_data, &ipmmu_devices_backup, list ) + { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(backup_data->dev); + unsigned int i; + + if ( to_ipmmu(backup_data->dev) != mmu ) + continue; + + for ( i = 0; i < fwspec->num_ids; i++ ) + { + unsigned int utlb = fwspec->ids[i]; + + ipmmu_imuasid_write(mmu, utlb, backup_data->asids_val[i]); + ipmmu_imuctr_write(mmu, utlb, backup_data->utlbs_val[i]); + } + } + + spin_unlock(&ipmmu_devices_backup_lock); +} + +static void ipmmu_domain_backup_context(struct ipmmu_vmsa_domain *domain) +{ + struct ipmmu_vmsa_device *mmu = domain->mmu->root; + struct ipmmu_reg_ctx *regs = mmu->reg_backup[domain->context_id]; + + dev_dbg(mmu->dev, "Handle domain context %u backup\n", domain->context_id); + + regs->imttlbr0 = ipmmu_ctx_read_root(domain, IMTTLBR0); + regs->imttubr0 = ipmmu_ctx_read_root(domain, IMTTUBR0); + regs->imttbcr = ipmmu_ctx_read_root(domain, IMTTBCR); + regs->imctr = ipmmu_ctx_read_root(domain, IMCTR); +} + +static void ipmmu_domain_restore_context(struct ipmmu_vmsa_domain *domain) +{ + struct ipmmu_vmsa_device *mmu = domain->mmu->root; + struct ipmmu_reg_ctx *regs = mmu->reg_backup[domain->context_id]; + + dev_dbg(mmu->dev, "Handle domain context %u restore\n", domain->context_id); + + ipmmu_ctx_write_root(domain, IMTTLBR0, regs->imttlbr0); + ipmmu_ctx_write_root(domain, IMTTUBR0, regs->imttubr0); + ipmmu_ctx_write_root(domain, IMTTBCR, regs->imttbcr); + ipmmu_ctx_write_all(domain, IMCTR, regs->imctr | IMCTR_FLUSH); +} + +/* + * Xen: Unlike Linux implementation, Xen uses a single driver instance + * for handling all IPMMUs. There is no framework for ipmmu_suspend/resume + * callbacks to be invoked for each IPMMU device. So, we need to iterate + * through all registered IPMMUs performing required actions. + * + * Also take care of restoring special settings, such as translation + * table format, etc. + */ +static int __must_check ipmmu_suspend(void) +{ + struct ipmmu_vmsa_device *mmu; + + if ( !iommu_enabled ) + return 0; + + printk(XENLOG_DEBUG "ipmmu: Suspending...\n"); + + spin_lock(&ipmmu_devices_lock); + + list_for_each_entry( mmu, &ipmmu_devices, list ) + { + if ( ipmmu_is_root(mmu) ) + { + unsigned int i; + + for ( i = 0; i < mmu->num_ctx; i++ ) + { + if ( !mmu->domains[i] ) + continue; + ipmmu_domain_backup_context(mmu->domains[i]); + } + } + else + ipmmu_utlbs_backup(mmu); + } + + spin_unlock(&ipmmu_devices_lock); + + return 0; +} + +static void ipmmu_resume(void) +{ + struct ipmmu_vmsa_device *mmu; + + if ( !iommu_enabled ) + return; + + printk(XENLOG_DEBUG "ipmmu: Resuming...\n"); + + spin_lock(&ipmmu_devices_lock); + + list_for_each_entry( mmu, &ipmmu_devices, list ) + { + uint32_t reg; + + /* Do not use security group function */ + reg = IMSCTLR + mmu->features->control_offset_base; + ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) & ~IMSCTLR_USE_SECGRP); + + if ( ipmmu_is_root(mmu) ) + { + unsigned int i; + + /* Use stage 2 translation table format */ + reg = IMSAUXCTLR + mmu->features->control_offset_base; + ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) | IMSAUXCTLR_S2PTE); + + for ( i = 0; i < mmu->num_ctx; i++ ) + { + if ( !mmu->domains[i] ) + continue; + ipmmu_domain_restore_context(mmu->domains[i]); + } + } + else + ipmmu_utlbs_restore(mmu); + } + + spin_unlock(&ipmmu_devices_lock); +} + +static int ipmmu_alloc_ctx_suspend(struct device *dev) +{ + struct ipmmu_vmsa_backup *backup_data; + unsigned int *utlbs_val, *asids_val; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + utlbs_val = xzalloc_array(unsigned int, fwspec->num_ids); + if ( !utlbs_val ) + return -ENOMEM; + + asids_val = xzalloc_array(unsigned int, fwspec->num_ids); + if ( !asids_val ) + { + xfree(utlbs_val); + return -ENOMEM; + } + + backup_data = xzalloc(struct ipmmu_vmsa_backup); + if ( !backup_data ) + { + xfree(utlbs_val); + xfree(asids_val); + return -ENOMEM; + } + + backup_data->dev = dev; + backup_data->utlbs_val = utlbs_val; + backup_data->asids_val = asids_val; + + spin_lock(&ipmmu_devices_backup_lock); + list_add(&backup_data->list, &ipmmu_devices_backup); + spin_unlock(&ipmmu_devices_backup_lock); + + return 0; +} + +#ifdef CONFIG_HAS_PCI +static void ipmmu_free_ctx_suspend(struct device *dev) +{ + struct ipmmu_vmsa_backup *backup_data, *tmp; + + spin_lock(&ipmmu_devices_backup_lock); + + list_for_each_entry_safe( backup_data, tmp, &ipmmu_devices_backup, list ) + { + if ( backup_data->dev == dev ) + { + list_del(&backup_data->list); + xfree(backup_data->utlbs_val); + xfree(backup_data->asids_val); + xfree(backup_data); + break; + } + } + + spin_unlock(&ipmmu_devices_backup_lock); +} +#endif /* CONFIG_HAS_PCI */ + +#endif /* CONFIG_SYSTEM_SUSPEND */ + static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) { uint64_t ttbr; @@ -559,6 +821,9 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) return ret; domain->context_id = ret; +#ifdef CONFIG_SYSTEM_SUSPEND + domain->mmu->root->reg_backup[ret] = &root_pgtable[ret]; +#endif /* * TTBR0 @@ -615,6 +880,9 @@ static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain) ipmmu_ctx_write_root(domain, IMCTR, IMCTR_FLUSH); ipmmu_tlb_sync(domain); +#ifdef CONFIG_SYSTEM_SUSPEND + domain->mmu->root->reg_backup[domain->context_id] = NULL; +#endif ipmmu_domain_free_context(domain->mmu->root, domain->context_id); } @@ -1340,10 +1608,11 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) struct iommu_fwspec *fwspec; #ifdef CONFIG_HAS_PCI + int ret; + if ( dev_is_pci(dev) ) { struct pci_dev *pdev = dev_to_pci(dev); - int ret; if ( devfn != pdev->devfn ) return 0; @@ -1371,6 +1640,15 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) /* Let Xen know that the master device is protected by an IOMMU. */ dt_device_set_protected(dev_to_dt(dev)); } + +#ifdef CONFIG_SYSTEM_SUSPEND + if ( ipmmu_alloc_ctx_suspend(dev) ) + { + dev_err(dev, "Failed to allocate context for suspend\n"); + return -ENOMEM; + } +#endif + #ifdef CONFIG_HAS_PCI if ( dev_is_pci(dev) ) { @@ -1379,26 +1657,28 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) struct pci_host_bridge *bridge; struct iommu_fwspec *fwspec_bridge; unsigned int utlb_osid0 = 0; - int ret; bridge = pci_find_host_bridge(pdev->seg, pdev->bus); if ( !bridge ) { dev_err(dev, "Failed to find host bridge\n"); - return -ENODEV; + ret = -ENODEV; + goto free_suspend_ctx; } fwspec_bridge = dev_iommu_fwspec_get(dt_to_dev(bridge->dt_node)); if ( fwspec_bridge->num_ids < 1 ) { dev_err(dev, "Failed to find host bridge uTLB\n"); - return -ENXIO; + ret = -ENXIO; + goto free_suspend_ctx; } if ( fwspec->num_ids < 1 ) { dev_err(dev, "Failed to find uTLB"); - return -ENXIO; + ret = -ENXIO; + goto free_suspend_ctx; } rcar4_pcie_osid_regs_init(bridge); @@ -1407,7 +1687,7 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) if ( ret < 0 ) { dev_err(dev, "No unused OSID regs\n"); - return ret; + goto free_suspend_ctx; } reg_id = ret; @@ -1422,7 +1702,7 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) { rcar4_pcie_osid_bdf_clear(bridge, reg_id); rcar4_pcie_osid_reg_free(bridge, reg_id); - return ret; + goto free_suspend_ctx; } } #endif @@ -1431,6 +1711,13 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) dev_name(fwspec->iommu_dev), fwspec->num_ids); return 0; +#ifdef CONFIG_HAS_PCI + free_suspend_ctx: +#ifdef CONFIG_SYSTEM_SUSPEND + ipmmu_free_ctx_suspend(dev); +#endif + return ret; +#endif } static int ipmmu_iommu_domain_init(struct domain *d) @@ -1492,6 +1779,10 @@ static const struct iommu_ops ipmmu_iommu_ops = .unmap_page = arm_iommu_unmap_page, .dt_xlate = ipmmu_dt_xlate, .add_device = ipmmu_add_device, +#ifdef CONFIG_SYSTEM_SUSPEND + .suspend = ipmmu_suspend, + .resume = ipmmu_resume, +#endif }; static __init int ipmmu_init(struct dt_device_node *node, const void *data) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271519.1559629 (Exim 4.92) (envelope-from ) id 1w8FaD-0003zE-2M; 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([45.12.26.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3d028955sm76392366b.61.2026.04.02.03.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2026 03:47:24 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775126845; x=1775731645; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=lTzPtWY93Ld+V54zoC04jqY3UY+XBvaAgSHzfOFCgx8=; b=H10uUo8+EILPV4xBcSUbz9SQjNiyIgaFGxL3nmX79r7W9zXR8ekud61IgxpZHP4o7b wJwLuUCNK7UuARE5O/0OmZSXUH1dypjiM1wYyvGzwgUhFUTtwe2ubN9PB4dYsIlga6Vc f3WkGMwAmqgobwGsLhIg2ts2m4lnBzosI3n/wpvkpw2BQoiaiyAYbSuPCfQpLnj0Ws08 eGHEteHUXd4yMCG+cGDeFvQ4+1eL2NE6ynV102OgX+FHY17HXwgfnlNnv3DOCpx8zI5m C+a9tehmgyXQz5/ZhHQbG05iOithWDnG6rr0WxzrvTtHktcaxZWBjVo8tY3AZiRz6el8 oy4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775126845; x=1775731645; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=lTzPtWY93Ld+V54zoC04jqY3UY+XBvaAgSHzfOFCgx8=; b=RR//slf3g0g351eImPuQIevZdGm4RiFRjrupadltfEAj2mriwDbGM+Wb+Gllicm2Oi 9ps04tQ4nOw+zAtVQTLvMXqdmUT2dQiAU4HXgbyxCOBW0/KdWaN+tK0UIeHU51CuelqN SS7PBkwov30K7SaKzj9Bb6/U5wZsnZkiqhdCJvwo2tLnKpHJq+8ZqacrUGAD0a3s1AY/ QdOtpEJ7nVETELt8Ary7HjcUDC7jZZkwyW091/eO8GbJDR7YLzKAJ0/XlO+tgS/iULXd 6XSXC7XfWcLmZHYF3/ZAni0g4B7HJLgWTaVp8dyjneHFkBPfXaG/JaJIUpYA/tZWEt5S 4pCA== X-Gm-Message-State: AOJu0YxMsbQ/KqjCQ8qDDJUSbgziTNBDbiD3GGKE4hFRRuflXc5NaQoV 7HyKHLMIlxdKlcGxGXZFKYoz1OYZCOrih80Pu++7OiZ3C8w/5MVfUNSqlYGIwcwQ X-Gm-Gg: ATEYQzxS78jUNqRfdshIXvfpf/sK8Q8LzM3Cmson6EFXC7hHzO9HtYGu3TdjqivOahG h33iALkr9lmW+WVFHVuD7WTh8G3oRO9nlS4wZ8jXeTr8MgUJnPTLJbMIIzBoOFzQdqWtq2VWyRH jbz5CoinSB4lY/DHfTAqWCksh8pvh4+YSvirrdoOExs1qkfvdJEVK/GPOQbvG25EnU9t5vzO2Pc BLpHNhizTD/fOrnTmklKlmXj17FB3N3//6vT/EApPf4gxJvA+tCS9ZrTAypVlZ3ukKOZugqhnNW qzQqV44Luy3LHuZKFYqK8gZR5wrQQT0LWAOTQninrzU34wSnW2OnorHeWGUzG0yhQFq790Pre5z jy+SORHnF4lzYMPLsofzP8StwQE/qN8+hI+aUCO+uyLDAr6bXSWhy1ppoIo4O+qBVNQD2gcXwm2 wbqk9sPotvGyfyYZxrWxNpFhR7T4SY+/Ttc0Vc X-Received: by 2002:a17:907:a688:b0:b98:549d:8367 with SMTP id a640c23a62f3a-b9c13902737mr477342166b.17.1775126845041; Thu, 02 Apr 2026 03:47:25 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jens Wiklander , Rahul Singh Subject: [PATCH v8 00/13] Add initial Xen Suspend-to-RAM support on ARM64 Date: Thu, 2 Apr 2026 13:45:01 +0300 Message-ID: X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775126846-EF9412A1-304DDA15/0/0 X-purgate-type: clean X-purgate-size: 5285 From: Mykola Kvach This is part 2 of version 8 of the ARM Xen system suspend/resume patch series, based on earlier work by Mirela Simonovic and Mykyta Poturai. The first part is in mainline. NOTE: Most of the code is guarded by CONFIG_SYSTEM_SUSPEND, which can currently only be selected when UNSUPPORTED is set, and thus the functionality is neither enabled by default nor even built. This version is ported to Xen master and includes extensive improvements based on reviewer feedback. The patch series restructures code to improve robustness, maintainability, and implements system Suspend-to-RAM support on ARM64 hardware/control domains. Key updates in this series: - Introduced architecture-specific suspend/resume infrastructure - Integrated GICv2/GICv3 suspend and resume, including memory-backed context save/restore with error handling - Added time and IRQ suspend/resume hooks, ensuring correct timer/interrupt state across suspend cycles - Implemented proper PSCI SYSTEM_SUSPEND invocation and version checks - Improved state management and recovery in error cases during suspend/resume - Added support for IPMMU-VMSA/SMMUv3 context save/restore - Added support for GICv3 eSPI registers context save/restore - Added support for ITS registers context save/restore --- TODOs: - Enable "xl suspend" support on ARM - Add suspend/resume CI test for ARM (QEMU if feasible) - PCI suspend ? --- Detailed changelogs can be found in each patch. Changes in v8: - Rebased to latest master and refreshed the series accordingly. - Added a new GICv3 patch to tolerate retained redistributor LPI state across CPU_OFF/CPU_ON. - GICv2 suspend now disables the CPU interface and distributor before saving state. - GICv3 suspend/resume fixes the redistributor base used for LPI state. - ITS and SMMUv3 suspend/resume paths were tightened, with safer restore/rollback handling and stricter fatal-error handling. - System suspend now checks that all domains are already in SHUTDOWN_suspend before proceeding, and renames the hardware-domain suspend capability/helper for clearer semantics. - Fixed alignment/cleanup issues in the low-level suspend/resume code. Changes in v7: - Timer helper renamed/clarified; virtual/hyper/phys handling documented. - GICv2 uses one context block; restore saved CTLR; panic on alloc failure. - GICv3/eSPI/ITS always suspend/resume; restore LPI/eSPI; rdist timeout. - IPMMU suspend context allocated before PCI setup. - System suspend: control domain drives host suspend. - Dropped v6 IRQ descriptor restore patches; use setup_irq and re-register local IRQs on resume instead. For earlier changelogs, please refer to the previous cover letters. Mirela Simonovic (6): xen/arm: Add suspend and resume timer helpers xen/arm: gic-v2: Implement GIC suspend/resume functions xen/arm: Resume memory management on Xen resume xen/arm: Save/restore context on suspend/resume xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface) xen/arm: Add support for system suspend triggered by hardware domain Mykola Kvach (6): xen/arm: gic-v3: tolerate retained redistributor LPI state across CPU_OFF xen/arm: gic-v3: Implement GICv3 suspend/resume functions xen/arm: gic-v3: add ITS suspend/resume support xen/arm: tee: keep init_tee_secondary() for hotplug and resume xen/arm: ffa: fix notification SRI across CPU hotplug/suspend arm/smmu-v3: add suspend/resume handlers Oleksandr Tyshchenko (1): iommu/ipmmu-vmsa: Implement suspend/resume callbacks xen/arch/arm/Kconfig | 2 + xen/arch/arm/Makefile | 1 + xen/arch/arm/arm64/head.S | 112 ++++++++ xen/arch/arm/gic-v2.c | 132 +++++++++ xen/arch/arm/gic-v3-its.c | 126 +++++++- xen/arch/arm/gic-v3-lpi.c | 80 +++++- xen/arch/arm/gic-v3.c | 349 ++++++++++++++++++++++- xen/arch/arm/gic.c | 29 ++ xen/arch/arm/include/asm/gic.h | 12 + xen/arch/arm/include/asm/gic_v3_defs.h | 1 + xen/arch/arm/include/asm/gic_v3_its.h | 24 ++ xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/include/asm/psci.h | 1 + xen/arch/arm/include/asm/suspend.h | 31 ++ xen/arch/arm/include/asm/time.h | 5 + xen/arch/arm/mmu/smpboot.c | 2 +- xen/arch/arm/psci.c | 23 +- xen/arch/arm/suspend.c | 195 +++++++++++++ xen/arch/arm/tee/ffa_notif.c | 63 +++- xen/arch/arm/tee/tee.c | 2 +- xen/arch/arm/time.c | 44 ++- xen/arch/arm/vpsci.c | 12 +- xen/common/Kconfig | 3 + xen/common/domain.c | 7 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 305 +++++++++++++++++++- xen/drivers/passthrough/arm/smmu-v3.c | 172 ++++++++--- xen/drivers/passthrough/arm/smmu.c | 10 + xen/include/xen/list.h | 14 + 28 files changed, 1670 insertions(+), 89 deletions(-) create mode 100644 xen/arch/arm/suspend.c -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271522.1559656 (Exim 4.92) (envelope-from ) id 1w8FaG-0004d6-04; Thu, 02 Apr 2026 10:47:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271522.1559656; Thu, 02 Apr 2026 10:47:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaF-0004cw-Sq; Thu, 02 Apr 2026 10:47:31 +0000 Received: by outflank-mailman (input) for mailman id 1271522; Thu, 02 Apr 2026 10:47:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaD-0004Am-SA for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:29 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaD-004haJ-8O for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:29 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4932-5cb7-0a2a0a5109dd-0a2a4506ed0e-16 for ; Thu, 02 Apr 2026 12:47:29 +0200 Received: from [209.85.218.50] (helo=mail-ej1-f50.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4941-0df0-0a2a45060019-d155da32a5de-3 for ; Thu, 02 Apr 2026 12:47:29 +0200 Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-b9a0762ed5fso112563066b.1 for ; Thu, 02 Apr 2026 03:47:29 -0700 (PDT) Received: from EPUAKYIW02F7.. ([45.12.26.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3d028955sm76392366b.61.2026.04.02.03.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2026 03:47:27 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775126848; x=1775731648; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OrY9cE1nd2J0of99KnQlF14iwjljRp7bNvn2AnZysGw=; b=L3PM+kaAyXPWdp2b4PzoPDl1+HMP/cbwZ0q3PZmcNcfboIlOZXjhh5gHQcyE7P5Ag3 Ssom/tpJUMz+g79mk12p+p11Vx/yzDQ/PZ79X8yI6ZYgzYzNGePB9wzf4pab6TSS1yEs pPN1+4yiBG+3FXDmRB+s3A5QsfDYVxv2DY5ZAMDrpzmpTP+3kp0V5CGGnBkviq3FtqFS EwNVfdnmKE8a6xZj10YIc79NCAaBfXQ/pL6BLxKmZuBe3hk7WcUaHDazhGIsTXcEKUFv w7GkjCxcuLir3BZ014pHQxCT6vVKVze2dUAoxhqK7Rb0Sb7f5mkIdRW/G8EtReLncKEM bphA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775126848; x=1775731648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OrY9cE1nd2J0of99KnQlF14iwjljRp7bNvn2AnZysGw=; b=SJfaEwqtSzLmI4/MlAqA6wGSMA/USHAIzzztFcN1HXmQS58ypHK/we3qYtBOe7w+ut zXlk2zN56NiEvvc47Y5BZzYaAYzSegsRAkXlCMfmbYnqaqNDuJr+jDQRrPLfFsRmdT8M ixJy+xIlBX4kwYPna4l630sNP+gJikgaUqYzdX/RRHOmNpwdISYUL/4hGHgUE1paWlZf 3lyWFsGdUtk0ueKAIHqg/fqfOgIADkohD+/iblD/HL2M4un6KSdhIMmpIguXg/wbxmTW HKcxky7CUnhlTowi8xG0dWAO0Ta9WedlAWIQRwJTK+InccRIJrJHUzl60d8zz2phzqiA SSlg== X-Gm-Message-State: AOJu0YxrIKkKAHslIGajy3KX+gzhP7PUhodCPQS48xLpGl8C3BQL5lXM eALKluwg4M4sLXVRCFHLIL7ucUgSbNf+YLwGz3xjNqfXulJTnG172kpPt7pprG8a X-Gm-Gg: ATEYQzyeM1ISVBxTfqhC00SAKkeD1igixeMUPiyIikwYN10H0n4Z3aas8+xqG1/h9/G OHa/mEMjzeLnfMAvM27lbuLtnhacxEvwrpl+MgSrkMTiBJv1DnSm5wUcnpvgFQI4+IN1NvBegSO EgKAuORgmBidV0fJgrE7lPm0C3SEBuq4d+vxhflmrTSvYkYqjwFl/9SrmzJ1h9DBBJpFM0W+XGk Wfvj7VudvIUYOmjUi4UQt5/qYmTiw8a/b5bEW9puYX1Q23A/4KAA+7ikg8dPUtiAu4EHEwYiG5u CYpbp/KCakXscDaHmPuXM6/NVymz70/Kt31kvt6chAKvQvqLI8MikT79v01Egknr+NkFZLrn9bf XDi18Kc1z6p0sIuuGbqbb0xBCPHj6HNZi9XZWyeLy0Mi7o0jQLRWRWSqGOKSS/jdMrICrce+SXA myS+7D9WRfcKvrPs6l4xwNRzvXKg== X-Received: by 2002:a17:907:3d56:b0:b94:231f:26ca with SMTP id a640c23a62f3a-b9c46fedc37mr91352666b.20.1775126847635; Thu, 02 Apr 2026 03:47:27 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v8 03/13] xen/arm: gic-v3: tolerate retained redistributor LPI state across CPU_OFF Date: Thu, 2 Apr 2026 13:45:04 +0300 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775126849-5E5303D8-0CBBBD7E/0/0 X-purgate-type: clean X-purgate-size: 8639 From: Mykola Kvach PSCI does not guarantee that a GICv3 redistributor is powered down across CPU_OFF -> CPU_ON. DEN0022F.b says CPU_OFF powers down the calling core (5.5) and CPU_ON brings the core back with a defined initial CPU state (5.6, 6.4). However, PSCI leaves interrupt migration and GIC re-initialization to the supervisory software/firmware stack: the caller must migrate interrupts away before CPU_OFF (5.5.2), and the execution context that is lost in a powerdown state must be saved and restored by software (6.8). PSCI also calls out GIC management explicitly in 6.8, including retargeting SPIs, preventing PPIs/SGIs from targeting a powered down CPU, and reinitializing the CPU interface after CPU_ON. This matches the GIC architecture. IHI0069H.b Chapter 11.1 requires the PE and CPU interface to share a power domain, but explicitly allows the associated redistributor, distributor, and ITS to remain powered while the PE and CPU interface are off. All other GIC power-management behavior is IMPLEMENTATION DEFINED. DEN0050D Chapter 4.2, "Generic Interrupt Controller (GIC)", says the GICv3 redistributor may live either in the AP core power domain or in a relatively always-on parent domain. So after CPU_OFF -> CPU_ON a secondary CPU can legitimately come back to a live redistributor with GICR_CTLR.EnableLPIs still set. Handle that case in the LPI setup path instead of assuming a fully reset redistributor. The LPI path needs special care because the GIC spec makes redistributor LPI state sticky and partially implementation defined. IHI0069H.b 5.1.1 and 5.1.2 say that changing GICR_PROPBASER or GICR_PENDBASER while GICR_CTLR.EnableLPIs == 1 is UNPREDICTABLE. After clearing EnableLPIs, software must wait for GICR_CTLR.RWP == 0 before touching the pending table. The architecture also permits implementations where, once EnableLPIs has been set, clearing it again is not guaranteed to work. Where an ITS is present, the spec strongly recommends moving LPIs to another redistributor before clearing EnableLPIs. Because of that, treat a retained EnableLPIs state as valid when the redistributor still points at Xen's expected PROPBASER/PENDBASER tables. Only try to clear EnableLPIs when the retained configuration does not match Xen's state, and wait for RWP before reprogramming the tables. This is also consistent with platform firmware reality: PSCI and the GIC architecture allow platform-specific redistributor power handling, and not all TF-A platforms force a full redistributor power-off through implementation-defined controls during CPU_OFF. Xen therefore needs to tolerate retained redistributor state on secondary CPU bring-up. Tested using Xen's non-boot CPU disable/enable path on Arm FVP_Base_RevC-2xAEMvA, both with and without: -C gic_distributor.allow-LPIEN-clear=1 -C gic_distributor.GICR-clear-enable-supported=1 and on Orange Pi 5. Signed-off-by: Mykola Kvach --- xen/arch/arm/gic-v3-lpi.c | 77 ++++++++++++++++++++++++++- xen/arch/arm/gic-v3.c | 15 ++++-- xen/arch/arm/include/asm/gic_v3_its.h | 1 + 3 files changed, 87 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index de5052e5cf..125f51e61b 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -81,6 +81,13 @@ static DEFINE_PER_CPU(struct lpi_redist_data, lpi_redist); #define MAX_NR_HOST_LPIS (lpi_data.max_host_lpi_ids - LPI_OFFSET) #define HOST_LPIS_PER_PAGE (PAGE_SIZE / sizeof(union host_lpi)) +#define GICR_PROPBASER_XEN_MASK GENMASK_ULL(51, 12) +/* + * For retained redistributor state, match the pending table by address only. + * Attribute bits such as PTZ may not read back with the programmed value. + */ +#define GICR_PENDBASER_XEN_MASK GENMASK_ULL(51, 16) + static union host_lpi *gic_get_host_lpi(uint32_t plpi) { union host_lpi *block; @@ -296,6 +303,60 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_base) return 0; } +static uint64_t gicv3_lpi_expected_proptable(void) +{ + return virt_to_maddr(lpi_data.lpi_property); +} + +static uint64_t gicv3_lpi_expected_pendtable(void) +{ + return virt_to_maddr(this_cpu(lpi_redist).pending_table); +} + +static bool gicv3_lpi_tables_match(void __iomem *rdist_base) +{ + uint64_t propbase, pendbase; + + if ( !lpi_data.lpi_property || !this_cpu(lpi_redist).pending_table ) + return false; + + propbase = readq_relaxed(rdist_base + GICR_PROPBASER); + pendbase = readq_relaxed(rdist_base + GICR_PENDBASER); + + return ((propbase & GICR_PROPBASER_XEN_MASK) == + (gicv3_lpi_expected_proptable() & GICR_PROPBASER_XEN_MASK)) && + ((pendbase & GICR_PENDBASER_XEN_MASK) == + (gicv3_lpi_expected_pendtable() & GICR_PENDBASER_XEN_MASK)); +} + +static int gicv3_lpi_disable_lpis(void __iomem *rdist_base) +{ + uint32_t reg = readl_relaxed(rdist_base + GICR_CTLR); + int ret; + + if ( !(reg & GICR_CTLR_ENABLE_LPIS) ) + return 0; + + writel_relaxed(reg & ~GICR_CTLR_ENABLE_LPIS, rdist_base + GICR_CTLR); + + /* + * The spec only guarantees programmability when we have observed the bit + * cleared. Where clearing is supported, RWP must reach 0 before touching + * PROPBASER/PENDBASER again. + */ + wmb(); + + ret = gicv3_do_wait_for_rwp(rdist_base); + if ( ret ) + return ret; + + reg = readl_relaxed(rdist_base + GICR_CTLR); + if ( reg & GICR_CTLR_ENABLE_LPIS ) + return -EBUSY; + + return 0; +} + /* * Tell a redistributor about the (shared) property table, allocating one * if not already done. @@ -373,7 +434,21 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base) /* Make sure LPIs are disabled before setting up the tables. */ reg = readl_relaxed(rdist_base + GICR_CTLR); if ( reg & GICR_CTLR_ENABLE_LPIS ) - return -EBUSY; + { + if ( gicv3_lpi_tables_match(rdist_base) ) + return -EBUSY; + + ret = gicv3_lpi_disable_lpis(rdist_base); + if ( ret == -EBUSY ) + { + printk(XENLOG_ERR + "GICv3: CPU%d: LPIs still enabled with unexpected redistributor tables\n", + smp_processor_id()); + return -EINVAL; + } + if ( ret ) + return ret; + } ret = gicv3_lpi_set_pendtable(rdist_base); if ( ret ) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bc07f97c16..34fb065afc 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -274,8 +274,8 @@ static void gicv3_enable_sre(void) isb(); } -/* Wait for completion of a distributor change */ -static void gicv3_do_wait_for_rwp(void __iomem *base) +/* Wait for completion of a distributor/redistributor write-pending change. */ +int gicv3_do_wait_for_rwp(void __iomem *base) { uint32_t val; bool timeout = false; @@ -295,17 +295,22 @@ static void gicv3_do_wait_for_rwp(void __iomem *base) } while ( 1 ); if ( timeout ) + { dprintk(XENLOG_ERR, "RWP timeout\n"); + return -ETIMEDOUT; + } + + return 0; } static void gicv3_dist_wait_for_rwp(void) { - gicv3_do_wait_for_rwp(GICD); + (void)gicv3_do_wait_for_rwp(GICD); } static void gicv3_redist_wait_for_rwp(void) { - gicv3_do_wait_for_rwp(GICD_RDIST_BASE); + (void)gicv3_do_wait_for_rwp(GICD_RDIST_BASE); } static void gicv3_wait_for_rwp(int irq) @@ -925,7 +930,7 @@ static int __init gicv3_populate_rdist(void) gicv3_set_redist_address(rdist_addr, procnum); ret = gicv3_lpi_init_rdist(ptr); - if ( ret && ret != -ENODEV ) + if ( ret && ret != -ENODEV && ret != -EBUSY ) { printk("GICv3: CPU%d: Cannot initialize LPIs: %u\n", smp_processor_id(), ret); diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index fc5a84892c..081bd19180 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -133,6 +133,7 @@ struct host_its { /* Map a collection for this host CPU to each host ITS. */ int gicv3_its_setup_collection(unsigned int cpu); +int gicv3_do_wait_for_rwp(void __iomem *base); #ifdef CONFIG_HAS_ITS -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271531.1559708 (Exim 4.92) (envelope-from ) id 1w8FaM-00068u-VC; Thu, 02 Apr 2026 10:47:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271531.1559708; Thu, 02 Apr 2026 10:47:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaM-00068W-LF; Thu, 02 Apr 2026 10:47:38 +0000 Received: by outflank-mailman (input) for mailman id 1271531; Thu, 02 Apr 2026 10:47:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaK-0005kv-QR for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaK-004haJ-6K for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:36 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4943-5cb7-0a2a0a5109dd-0a2a4502ebd6-10 for ; Thu, 02 Apr 2026 12:47:36 +0200 Received: from [209.85.218.44] (helo=mail-ej1-f44.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4948-42fa-0a2a45020019-d155da2cf1bf-3 for ; Thu, 02 Apr 2026 12:47:36 +0200 Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-b9825ba7e8dso100467666b.3 for ; Thu, 02 Apr 2026 03:47:36 -0700 (PDT) Received: from EPUAKYIW02F7.. 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The suspend callback configures the SMMU to abort new transactions, disables the main translation unit and then drains the command queue to ensure completion of any in-flight commands. The resume callback performs a full device reset via 'arm_smmu_device_reset' to bring the SMMU back to an operational state. Signed-off-by: Mykola Kvach --- Changes in V8: - Honor ARM_SMMU_FEAT_SEV when draining the CMDQ during suspend, matching the existing runtime CMD_SYNC path. - Fold the suspend rollback reset path into a helper and rename the error reporting to describe suspend rollback rather than resume. - Treat SMMU reset failure during resume as fatal instead of logging and continuing with a potentially unusable IOMMU. - cosmetic changes --- xen/drivers/passthrough/arm/smmu-v3.c | 172 ++++++++++++++++++++------ 1 file changed, 136 insertions(+), 36 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index bf153227db..7607ffc9ca 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1814,8 +1814,7 @@ static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, } /* GBPA is "special" */ -static int __init arm_smmu_update_gbpa(struct arm_smmu_device *smmu, - u32 set, u32 clr) +static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) { int ret; u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; @@ -1995,10 +1994,29 @@ err_free_evtq_irq: return ret; } +static int arm_smmu_enable_irqs(struct arm_smmu_device *smmu) +{ + int ret; + u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; + + if ( smmu->features & ARM_SMMU_FEAT_PRI ) + irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; + + /* Enable interrupt generation on the SMMU */ + ret = arm_smmu_write_reg_sync(smmu, irqen_flags, + ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); + if ( ret ) + { + dev_warn(smmu->dev, "failed to enable irqs\n"); + return ret; + } + + return 0; +} + static int __init arm_smmu_setup_irqs(struct arm_smmu_device *smmu) { int ret, irq; - u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; /* Disable IRQs first */ ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, @@ -2028,22 +2046,7 @@ static int __init arm_smmu_setup_irqs(struct arm_smmu_device *smmu) } } - if (smmu->features & ARM_SMMU_FEAT_PRI) - irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; - - /* Enable interrupt generation on the SMMU */ - ret = arm_smmu_write_reg_sync(smmu, irqen_flags, - ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); - if (ret) { - dev_warn(smmu->dev, "failed to enable irqs\n"); - goto err_free_irqs; - } - return 0; - -err_free_irqs: - arm_smmu_free_irqs(smmu); - return ret; } static int arm_smmu_device_disable(struct arm_smmu_device *smmu) @@ -2057,7 +2060,7 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu) return ret; } -static int __init arm_smmu_device_reset(struct arm_smmu_device *smmu) +static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; u32 reg, enables; @@ -2163,17 +2166,9 @@ static int __init arm_smmu_device_reset(struct arm_smmu_device *smmu) } } - ret = arm_smmu_setup_irqs(smmu); - if (ret) { - dev_err(smmu->dev, "failed to setup irqs\n"); + ret = arm_smmu_enable_irqs(smmu); + if ( ret ) return ret; - } - - /* Initialize tasklets for threaded IRQs*/ - tasklet_init(&smmu->evtq_irq_tasklet, arm_smmu_evtq_tasklet, smmu); - tasklet_init(&smmu->priq_irq_tasklet, arm_smmu_priq_tasklet, smmu); - tasklet_init(&smmu->combined_irq_tasklet, arm_smmu_combined_irq_tasklet, - smmu); /* Enable the SMMU interface, or ensure bypass */ if (disable_bypass) { @@ -2181,20 +2176,16 @@ static int __init arm_smmu_device_reset(struct arm_smmu_device *smmu) } else { ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); if (ret) - goto err_free_irqs; + return ret; } ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { dev_err(smmu->dev, "failed to enable SMMU interface\n"); - goto err_free_irqs; + return ret; } return 0; - -err_free_irqs: - arm_smmu_free_irqs(smmu); - return ret; } static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) @@ -2558,10 +2549,23 @@ static int __init arm_smmu_device_probe(struct platform_device *pdev) if (ret) goto out_free; + ret = arm_smmu_setup_irqs(smmu); + if ( ret ) + { + dev_err(smmu->dev, "failed to setup irqs\n"); + goto out_free; + } + + /* Initialize tasklets for threaded IRQs*/ + tasklet_init(&smmu->evtq_irq_tasklet, arm_smmu_evtq_tasklet, smmu); + tasklet_init(&smmu->priq_irq_tasklet, arm_smmu_priq_tasklet, smmu); + tasklet_init(&smmu->combined_irq_tasklet, arm_smmu_combined_irq_tasklet, + smmu); + /* Reset the device */ ret = arm_smmu_device_reset(smmu); if (ret) - goto out_free; + goto out_free_irqs; /* * Keep a list of all probed devices. This will be used to query @@ -2575,6 +2579,8 @@ static int __init arm_smmu_device_probe(struct platform_device *pdev) return 0; +out_free_irqs: + arm_smmu_free_irqs(smmu); out_free: arm_smmu_free_structures(smmu); @@ -2855,6 +2861,96 @@ static void arm_smmu_iommu_xen_domain_teardown(struct domain *d) xfree(xen_domain); } +#ifdef CONFIG_SYSTEM_SUSPEND + +static void arm_smmu_reset_for_suspend_rollback(struct arm_smmu_device *smmu) +{ + int ret = arm_smmu_device_reset(smmu); + + if ( ret ) + dev_err(smmu->dev, "Failed to reset during suspend rollback: %d\n", + ret); +} + +static int arm_smmu_suspend(void) +{ + struct arm_smmu_device *smmu; + int ret = 0; + + list_for_each_entry(smmu, &arm_smmu_devices, devices) + { + bool wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); + + /* Abort all transactions before disable to avoid spurious bypass */ + ret = arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); + if ( ret ) + goto fail; + + /* Disable the SMMU via CR0.EN and all queues except CMDQ */ + ret = arm_smmu_write_reg_sync(smmu, CR0_CMDQEN, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if ( ret ) + { + dev_err(smmu->dev, "Timed-out while disabling smmu\n"); + goto fail; + } + + /* + * At this point the SMMU is completely disabled and won't access + * any translation/config structures, even speculative accesses + * aren't performed as per the IHI0070 spec (section 6.3.9.6). + */ + + /* Wait for the CMDQs to be drained to flush any pending commands */ + ret = queue_poll_cons(&smmu->cmdq.q, true, wfe); + if ( ret ) + { + dev_err(smmu->dev, "Draining queues timed-out\n"); + goto fail; + } + + /* Disable everything */ + ret = arm_smmu_device_disable(smmu); + if ( ret ) + goto fail; + + dev_dbg(smmu->dev, "Suspended smmu\n"); + } + + return 0; + + fail: + /* Reset the device that failed as well as any already-suspended ones. */ + arm_smmu_reset_for_suspend_rollback(smmu); + + list_for_each_entry_continue_reverse(smmu, &arm_smmu_devices, devices) + arm_smmu_reset_for_suspend_rollback(smmu); + + return ret; +} + +static void arm_smmu_resume(void) +{ + int ret; + struct arm_smmu_device *smmu; + + list_for_each_entry(smmu, &arm_smmu_devices, devices) + { + dev_dbg(smmu->dev, "Resuming device\n"); + + /* + * The reset will re-initialize all the base addresses, queues, + * prod and cons maintained within struct arm_smmu_device as well as + * re-enable the interrupts. + */ + ret = arm_smmu_device_reset(smmu); + if ( ret ) + panic("SMMUv3: %s: Failed to reset during resume: %d\n", + dev_name(smmu->dev), ret); + } +} +#endif + static const struct iommu_ops arm_smmu_iommu_ops = { .page_sizes = PAGE_SIZE_4K, .init = arm_smmu_iommu_xen_domain_init, @@ -2867,6 +2963,10 @@ static const struct iommu_ops arm_smmu_iommu_ops = { .unmap_page = arm_iommu_unmap_page, .dt_xlate = arm_smmu_dt_xlate, .add_device = arm_smmu_add_device, +#ifdef CONFIG_SYSTEM_SUSPEND + .suspend = arm_smmu_suspend, + .resume = arm_smmu_resume, +#endif }; static __init int arm_smmu_dt_init(struct dt_device_node *dev, -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271535.1559717 (Exim 4.92) (envelope-from ) id 1w8FaO-0006NJ-II; Thu, 02 Apr 2026 10:47:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271535.1559717; Thu, 02 Apr 2026 10:47:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaO-0006M9-19; Thu, 02 Apr 2026 10:47:40 +0000 Received: by outflank-mailman (input) for mailman id 1271535; Thu, 02 Apr 2026 10:47:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaM-00064W-Hd for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaL-00Ej0u-T9 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:37 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4947-2eae-0a2a0a5409dd-0a2a4505b638-10 for ; Thu, 02 Apr 2026 12:47:37 +0200 Received: from [209.85.218.51] (helo=mail-ej1-f51.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4949-3760-0a2a45050019-d155da33c8ee-3 for ; Thu, 02 Apr 2026 12:47:37 +0200 Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-b97e6e48b24so109055566b.2 for ; Thu, 02 Apr 2026 03:47:37 -0700 (PDT) Received: from EPUAKYIW02F7.. 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This patch adds MMU setup during resume by reusing the existing enable_secondary_cpu_mm function, which enables data cache and the MMU. Before the MMU is enabled, the content of TTBR0_EL2 is changed to point to init_ttbr (page tables used at runtime). Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in v7: - no functional changes, just moved commit --- xen/arch/arm/arm64/head.S | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 72c7b24498..596e960152 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -561,6 +561,30 @@ END(efi_xen_start) #endif /* CONFIG_ARM_EFI */ +#ifdef CONFIG_SYSTEM_SUSPEND + +FUNC(hyp_resume) + /* Initialize the UART if earlyprintk has been enabled. */ +#ifdef CONFIG_EARLY_PRINTK + bl init_uart +#endif + PRINT_ID("- Xen resuming -\r\n") + + bl check_cpu_mode + bl cpu_init + + ldr x0, =start + adr x20, start /* x20 := paddr (start) */ + sub x20, x20, x0 /* x20 := phys-offset */ + ldr lr, =mmu_resumed + b enable_secondary_cpu_mm + +mmu_resumed: + b . +END(hyp_resume) + +#endif /* CONFIG_SYSTEM_SUSPEND */ + /* * Local variables: * mode: ASM -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271537.1559723 (Exim 4.92) (envelope-from ) id 1w8FaP-0006U2-Gm; Thu, 02 Apr 2026 10:47:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271537.1559723; Thu, 02 Apr 2026 10:47:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaO-0006RL-IG; Thu, 02 Apr 2026 10:47:40 +0000 Received: by outflank-mailman (input) for mailman id 1271537; Thu, 02 Apr 2026 10:47:39 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaM-00067Z-PE for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaM-00Ej0u-4t for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:38 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4947-2eae-0a2a0a5409dd-0a2a4505b638-12 for ; Thu, 02 Apr 2026 12:47:38 +0200 Received: from [209.85.218.45] (helo=mail-ej1-f45.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce494a-3760-0a2a45050019-d155da2da5b5-3 for ; Thu, 02 Apr 2026 12:47:38 +0200 Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-b9a0762ed5fso112580866b.1 for ; Thu, 02 Apr 2026 03:47:38 -0700 (PDT) Received: from EPUAKYIW02F7.. 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This is implemented in prepare_resume_ctx and before the return from the hyp_resume function. The prepare_resume_ctx must be invoked just before the PSCI system suspend call is issued to the ATF. The prepare_resume_ctx must return a non-zero value so that the calling 'if' statement evaluates to true, causing the system suspend to be invoked. Upon resume, the context saved on suspend will be restored, including the link register. Therefore, after restoring the context, the control flow will return to the address pointed to by the saved link register, which is the place from which prepare_resume_ctx was called. To ensure that the calling 'if' statement does not again evaluate to true and initiate system suspend, hyp_resume must return a zero value after restoring the context. Note that the order of saving register context into cpu_context structure must match the order of restoring. Support for ARM32 is not implemented. Instead, compilation fails with a build-time error if suspend is enabled for ARM32. Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in v8: - fix alignments in code Changes in v7: - no changes --- xen/arch/arm/Makefile | 1 + xen/arch/arm/arm64/head.S | 90 +++++++++++++++++++++++++++++- xen/arch/arm/include/asm/suspend.h | 26 +++++++++ xen/arch/arm/suspend.c | 14 +++++ 4 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/suspend.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 69200b2728..c36158271a 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -51,6 +51,7 @@ obj-y += setup.o obj-y += shutdown.o obj-y += smp.o obj-y += smpboot.o +obj-$(CONFIG_SYSTEM_SUSPEND) += suspend.o obj-$(CONFIG_SYSCTL) += sysctl.o obj-y += time.o obj-y += traps.o diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 596e960152..2cb02ee314 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -562,6 +562,52 @@ END(efi_xen_start) #endif /* CONFIG_ARM_EFI */ #ifdef CONFIG_SYSTEM_SUSPEND +/* + * int prepare_resume_ctx(struct cpu_context *ptr) + * + * x0 - pointer to the storage where callee's context will be saved + * + * CPU context saved here will be restored on resume in hyp_resume function. + * prepare_resume_ctx shall return a non-zero value. Upon restoring context + * hyp_resume shall return value zero instead. From C code that invokes + * prepare_resume_ctx, the return value is interpreted to determine whether + * the context is saved (prepare_resume_ctx) or restored (hyp_resume). + */ +FUNC(prepare_resume_ctx) + /* Store callee-saved registers */ + stp x19, x20, [x0], #16 + stp x21, x22, [x0], #16 + stp x23, x24, [x0], #16 + stp x25, x26, [x0], #16 + stp x27, x28, [x0], #16 + stp x29, lr, [x0], #16 + + /* Store stack-pointer */ + mov x2, sp + str x2, [x0], #8 + + /* Store system control registers */ + mrs x2, VBAR_EL2 + str x2, [x0], #8 + mrs x2, VTCR_EL2 + str x2, [x0], #8 + mrs x2, VTTBR_EL2 + str x2, [x0], #8 + mrs x2, TPIDR_EL2 + str x2, [x0], #8 + mrs x2, MDCR_EL2 + str x2, [x0], #8 + mrs x2, HSTR_EL2 + str x2, [x0], #8 + mrs x2, CPTR_EL2 + str x2, [x0], #8 + mrs x2, HCR_EL2 + str x2, [x0], #8 + + /* prepare_resume_ctx must return a non-zero value */ + mov x0, #1 + ret +END(prepare_resume_ctx) FUNC(hyp_resume) /* Initialize the UART if earlyprintk has been enabled. */ @@ -580,7 +626,49 @@ FUNC(hyp_resume) b enable_secondary_cpu_mm mmu_resumed: - b . + /* Now we can access the cpu_context, so restore the context here */ + ldr x0, =cpu_context + + /* Restore callee-saved registers */ + ldp x19, x20, [x0], #16 + ldp x21, x22, [x0], #16 + ldp x23, x24, [x0], #16 + ldp x25, x26, [x0], #16 + ldp x27, x28, [x0], #16 + ldp x29, lr, [x0], #16 + + /* Restore stack pointer */ + ldr x2, [x0], #8 + mov sp, x2 + + /* Restore system control registers */ + ldr x2, [x0], #8 + msr VBAR_EL2, x2 + ldr x2, [x0], #8 + msr VTCR_EL2, x2 + ldr x2, [x0], #8 + msr VTTBR_EL2, x2 + ldr x2, [x0], #8 + msr TPIDR_EL2, x2 + ldr x2, [x0], #8 + msr MDCR_EL2, x2 + ldr x2, [x0], #8 + msr HSTR_EL2, x2 + ldr x2, [x0], #8 + msr CPTR_EL2, x2 + ldr x2, [x0], #8 + msr HCR_EL2, x2 + isb + + /* + * Since context is restored return from this function will appear + * as return from prepare_resume_ctx. To distinguish a return from + * prepare_resume_ctx which is called upon finalizing the suspend, + * as opposed to return from this function which executes on resume, + * we need to return zero value here. + */ + mov x0, #0 + ret END(hyp_resume) #endif /* CONFIG_SYSTEM_SUSPEND */ diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/asm/suspend.h index 31a98a1f1b..c127fa3d78 100644 --- a/xen/arch/arm/include/asm/suspend.h +++ b/xen/arch/arm/include/asm/suspend.h @@ -3,6 +3,8 @@ #ifndef ARM_SUSPEND_H #define ARM_SUSPEND_H +#include + struct domain; struct vcpu; struct vcpu_guest_context; @@ -14,6 +16,30 @@ struct resume_info { void arch_domain_resume(struct domain *d); +#ifdef CONFIG_SYSTEM_SUSPEND +#ifdef CONFIG_ARM_64 +struct cpu_context { + register_t callee_regs[12]; + register_t sp; + register_t vbar_el2; + register_t vtcr_el2; + register_t vttbr_el2; + register_t tpidr_el2; + register_t mdcr_el2; + register_t hstr_el2; + register_t cptr_el2; + register_t hcr_el2; +} __aligned(16); +#else +#error "Define cpu_context structure for arm32" +#endif + +extern struct cpu_context cpu_context; + +int prepare_resume_ctx(struct cpu_context *ptr); +void hyp_resume(void); +#endif /* CONFIG_SYSTEM_SUSPEND */ + #endif /* ARM_SUSPEND_H */ /* diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c new file mode 100644 index 0000000000..e38566b0b7 --- /dev/null +++ b/xen/arch/arm/suspend.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +struct cpu_context cpu_context = {}; + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271541.1559727 (Exim 4.92) (envelope-from ) id 1w8FaQ-0006iW-I0; Thu, 02 Apr 2026 10:47:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271541.1559727; Thu, 02 Apr 2026 10:47:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaQ-0006fr-2F; Thu, 02 Apr 2026 10:47:42 +0000 Received: by outflank-mailman (input) for mailman id 1271541; Thu, 02 Apr 2026 10:47:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaN-0006KE-Vk for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:39 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaN-009qA7-Bp for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:39 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce493f-e002-0a2a0a5209dd-0a2a450a8a2e-32 for ; Thu, 02 Apr 2026 12:47:39 +0200 Received: from [209.85.218.47] (helo=mail-ej1-f47.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce494b-ee98-0a2a450a0019-d155da2fc914-3 for ; Thu, 02 Apr 2026 12:47:39 +0200 Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-b9c3a9fe80fso90523266b.3 for ; Thu, 02 Apr 2026 03:47:39 -0700 (PDT) Received: from EPUAKYIW02F7.. ([45.12.26.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3d028955sm76392366b.61.2026.04.02.03.47.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2026 03:47:37 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775126858; x=1775731658; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=81pZ/JS38wYFIEh/dUJCFhVaISUWS/A04krI0+LMlhc=; b=SDOkkIyDwrY3ZrWFPgJIw6PL8GyiWY1v5MhVp/l8F+tUoVVT/nTNpetUO+QpqS1r7K zVp0FZBbGrtCJBMqBNCcvsowgw4zpY8/YUEW9LeDtnsBMtWUXeO41YE3oLdFMqGqHvt1 CP1Wya6R0lmaSa4W8qlwbgV7YGRiT5Uoug0MX+p/T/V5BeDhjvPrUP8hUHsriXHQWI89 zQXbF1otUr7OzWXseQR0+sbz18giN8vhqxhocfzc9F7XS8gynS+P19Wkv7non3zH2veW O4IpKpNz5B2Dp+I9e3i8/FpyhTxtC3mH2r/U+FuHjhbiKZGp5e71qaN+2byVyCSmvRDi NyZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775126858; x=1775731658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=81pZ/JS38wYFIEh/dUJCFhVaISUWS/A04krI0+LMlhc=; b=jPQX7Jh21qUuiZbps5Ze29GE8Z71NPr2wQJ7qKKNDo2RFaY3Zh6l3MrMjDA5lhCIQ2 IuY9n3ZamtEm5zF87bN0HYqFS0zdj1rDk+zbBZeCDFtqlz9hqJlKdncZj5xM0OnUxRkH yqLQmxfB6NIiOik8wXuyI+U4i2ey6fzd/e/M7kh4qTYJFePPLd+AZE3DiDVEU6QhXYqI XvxGtU3nnmyK7BjsHd1oZ/HmWk9xMgGhVFJePsb2kbRtFr0e8fTKhQ5PobBALrWtkJWe qIoPbulXdNr5h1fJDW6dVJthPAsra0pX5wLBiLzQ2IvBJEQRAjk/nQGSorUSFf5VIPw3 4lEw== X-Gm-Message-State: AOJu0YyGkOx6Tne3XBgqnG7RjihFwrKo0JtI+eoHbceW/KVhBkeQHgkM si+F6AC9gVRA+PSPQAhbud76IBCKxt+hbWl0Y7Ho65J4BAx+NSMscCS7Uq4sy+It X-Gm-Gg: ATEYQzx9FrkaJ3Hf5CgmnbwtWadW6wmisEoY0mpleq6oJPr11SMkZvFMHzeNgxcuh7/ NBmatmBV9ALkWiZ9THJNtVIAjuK5KVMT+Cs89XM0E3XjqWk7RxXl73BVwNHBpRAUg22ZPCWSDbL VFkNcolwKBKfFcGTzSlfnsxAou71R8POyudW5RSwiY/OEpSexywPhAg81pesMKgjXpmDkX4G+JO eEwLy+8z59PQFwbJTcFF9X0r0utCFsL9SuZBIbTZuehvf5+WxDi6XGvhx5ATFIaP2WGstdonS2V 1Tayzk2mflimsLaIvEszKY42uNYwD+UhUa8migUBHB+ovhQJsnDWRiPkGpFNvFhEY3N4qiyu87W u25+z7xbSUIySgCzZzuWR0QQwSp5Mgs0gk2w+NNcvrtwGbd96E60otacDvOZEe8q5mA8JYAOIRl fGxAM+jhf2gQUFC23q0QIW5KoQGQ== X-Received: by 2002:a17:906:a50:b0:b98:8d3a:7d26 with SMTP id a640c23a62f3a-b9c138fa8bemr342137866b.15.1775126858181; Thu, 02 Apr 2026 03:47:38 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v8 12/13] xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface) Date: Thu, 2 Apr 2026 13:45:13 +0300 Message-ID: <8767d4129cd5bc56086172e58320539be7da4059.1775125380.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1775126859-BE3510B1-A701E6B6/0/0 X-purgate-type: clean X-purgate-size: 2949 From: Mirela Simonovic Invoke PSCI SYSTEM_SUSPEND to finalize Xen's suspend sequence on ARM64 platforms. Pass the resume entry point (hyp_resume) as the first argument to EL3. The resume handler is currently a stub and will be implemented later in assembly. Ignore the context ID argument, as is done in Linux. Only enable this path when CONFIG_SYSTEM_SUSPEND is set and PSCI version is >= 1.0. Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in v7: - no changes --- xen/arch/arm/include/asm/psci.h | 1 + xen/arch/arm/psci.c | 23 ++++++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h index 48a93e6b79..bb3c73496e 100644 --- a/xen/arch/arm/include/asm/psci.h +++ b/xen/arch/arm/include/asm/psci.h @@ -23,6 +23,7 @@ int call_psci_cpu_on(int cpu); void call_psci_cpu_off(void); void call_psci_system_off(void); void call_psci_system_reset(void); +int call_psci_system_suspend(void); /* Range of allocated PSCI function numbers */ #define PSCI_FNUM_MIN_VALUE _AC(0,U) diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index b6860a7760..c9d126b195 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -17,17 +17,20 @@ #include #include #include +#include /* * While a 64-bit OS can make calls with SMC32 calling conventions, for * some calls it is necessary to use SMC64 to pass or return 64-bit values. - * For such calls PSCI_0_2_FN_NATIVE(x) will choose the appropriate + * For such calls PSCI_*_FN_NATIVE(x) will choose the appropriate * (native-width) function ID. */ #ifdef CONFIG_ARM_64 #define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN64_##name +#define PSCI_1_0_FN_NATIVE(name) PSCI_1_0_FN64_##name #else #define PSCI_0_2_FN_NATIVE(name) PSCI_0_2_FN32_##name +#define PSCI_1_0_FN_NATIVE(name) PSCI_1_0_FN32_##name #endif uint32_t psci_ver; @@ -60,6 +63,24 @@ void call_psci_cpu_off(void) } } +int call_psci_system_suspend(void) +{ +#ifdef CONFIG_SYSTEM_SUSPEND + struct arm_smccc_res res; + + if ( psci_ver < PSCI_VERSION(1, 0) ) + return PSCI_NOT_SUPPORTED; + + /* 2nd argument (context ID) is not used */ + arm_smccc_smc(PSCI_1_0_FN_NATIVE(SYSTEM_SUSPEND), __pa(hyp_resume), &res); + return PSCI_RET(res); +#else + dprintk(XENLOG_WARNING, + "SYSTEM_SUSPEND not supported (CONFIG_SYSTEM_SUSPEND disabled)\n"); + return PSCI_NOT_SUPPORTED; +#endif +} + void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:47:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:47:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271546.1559732 (Exim 4.92) (envelope-from ) id 1w8FaR-0006uD-Ld; Thu, 02 Apr 2026 10:47:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271546.1559732; Thu, 02 Apr 2026 10:47:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaR-0006sC-4i; Thu, 02 Apr 2026 10:47:43 +0000 Received: by outflank-mailman (input) for mailman id 1271546; Thu, 02 Apr 2026 10:47:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8FaP-0006V5-2R for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:47:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8FaO-009qA7-Ef for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:47:40 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce4948-e002-0a2a0a5209dd-0a2a450c8ce0-20 for ; Thu, 02 Apr 2026 12:47:40 +0200 Received: from [209.85.218.45] (helo=mail-ej1-f45.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce494c-f40c-0a2a450c0019-d155da2db009-3 for ; Thu, 02 Apr 2026 12:47:40 +0200 Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-b8f97c626aaso122290666b.2 for ; Thu, 02 Apr 2026 03:47:40 -0700 (PDT) Received: from EPUAKYIW02F7.. ([45.12.26.38]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9c3d028955sm76392366b.61.2026.04.02.03.47.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2026 03:47:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775126860; x=1775731660; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PNu7eJ7Z0b3llwWlHGEbTagm+9rNR0YOT8JLveV1JGo=; b=KbGPLCldm1ssHRBbB1PjHxZV4J4qieBqYD1xDaTjCJl7e/yJ//qd0XEpJR2zRdSocS ZQAWJrK5m0bDoHP/uXSNJcZ8y/o6gJmTEVvTu1iTsOPqTkLYcZsBE1qgj9jxspDQz1L4 5krMpNBx/Gd8K4HFKZ8ZPKTMWHQvWIWY2lUQ0mz94SVgV5Y9KtvggPCt1vduNCVSArA7 D2CcmNA5n9YAR/z1kWbyR/THqBftvr5xnIb5ONiyndhVwgwBwfJ/HVqX1J2/HYAQDT4o rdP2ap/v7LySDZn7g7IDeOati7/MKyRR7OQtmNjg/L7A5ThJl5FWnsxAgaLZWhQLoHyE emCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775126860; x=1775731660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=PNu7eJ7Z0b3llwWlHGEbTagm+9rNR0YOT8JLveV1JGo=; b=YNat4XG4aWdaWH4ArFu/kAToUf/pXRrJZBWnvxoTo3yNXtNgTF6COzGO6hMxrudAjo 9XnmXlU8NzIWR+1d7UDFUGXwY+ZTWoLIwKzZQ7HdWeH5Df+NtgQmw1JAGr4xHEnCg8H0 NsCOBggaawCAdWTIW9V01dPrfn0pUg+gqJgmJMYG+jABVuCohhK5miN684YQEBxa+FQ+ qKr43TcwMVR+h/r0QqZsyi7QcUUZ3JKcett6rysAREs70Gg8dcl6MSDjfoQH6Z2YIVG1 Zq1bcHr3nospWcJJdwLgCQ0s79hFaj5K0zypZWvHH6VcnPOWVp1N7pN3yaqtAb+TFuyQ TqDQ== X-Gm-Message-State: AOJu0YxOKPtSQmRzA9cWSgOCOVuPGrqOgFX3tsP4L/gnHgMf3BKVWXkG nV248zl47P3pUHLnGI0C3csMi6tRqugP+OUEHlZsmuzkowiBRRPBQzNQtnr26ejn X-Gm-Gg: ATEYQzxnLd9O2cxo0RJ9n88S8VczcX1T+qFGxTSocNYiZzM57/bHoO04XGNf9irtKk5 iq1T3rbl2HEeTyqfbdcQevZKcdSnYljRZLX+C/3LUoESMmYTdPMP65rEB+a49vV5ryxQza5syRA NV7xQbssNwLG5HWjwW5T8AuKQejS/m8z5cuFVOt34jjPq9KL++/SfGX44t6AAhtcPRFlLScTZEd sTQ1AhHPKxQFx9LmMJzpQZ0/Doh2QW4Be4zsdO4CK5VFbyzYNClDVDrJhrdXkiW7a58E036GS8T lQkez+/rnFNLoFu+raeKr5OI7UauNIvevYnFAaDLp6DpGz1gokEa7hQibHSrp81nHB8oovsAm15 jei8vtho8CTtJL67kCdxQmoNq3C2i+BMYmWJqGGlao7Vixow9bYdeV9asyVBnJKln7YjnCoVff9 Z/XQPh3KrD7aoGhsflb2EHg8z5d1CkHSynLZM1 X-Received: by 2002:a17:907:6d16:b0:b9c:4248:7773 with SMTP id a640c23a62f3a-b9c42487e4amr138809366b.26.1775126859321; Thu, 02 Apr 2026 03:47:39 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Rahul Singh Subject: [PATCH v8 13/13] xen/arm: Add support for system suspend triggered by hardware domain Date: Thu, 2 Apr 2026 13:45:14 +0300 Message-ID: <9b0f8922cd33df2b8e8038d639c1b8d8d73ce401.1775125380.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775126860-FFF42A3D-F1949B49/0/0 X-purgate-type: clean X-purgate-size: 14142 From: Mirela Simonovic Trigger Xen suspend when the hardware domain initiates suspend via SHUTDOWN_suspend. Redirect system suspend to CPU#0 to ensure the suspend logic runs on the boot CPU, as required. Introduce full suspend/resume infrastructure gated by CONFIG_SYSTEM_SUSPEND, including logic to: - disable and enable non-boot physical CPUs - freeze and thaw domains - suspend and resume the GIC, timer, iommu and console - maintain system state before and after suspend On boot, init_ttbr is normally initialized during secondary CPU hotplug. On uniprocessor systems, this would leave init_ttbr uninitialized, causing resume to fail. To address this, the boot CPU now sets init_ttbr during suspend. Remove the restriction in the vPSCI interface preventing suspend from the hardware domain. Select HAS_SYSTEM_SUSPEND for ARM_64. Introduce CONFIG_HAS_HWDOM_SYSTEM_SUSPEND as an architecture-selected capability for platforms where the hardware domain survives SHUTDOWN_suspend without hwdom_shutdown(). ARM_64 selects it with SYSTEM_SUSPEND enabled; other architectures keep the existing behaviour. Note: the code is behind CONFIG_HAS_SYSTEM_SUSPEND, which is currently only selected when UNSUPPORTED is set and when MPU isn't set, so the functionality is built but disabled by default. Signed-off-by: Mirela Simonovic Signed-off-by: Saeed Nowshadi Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in V8: - Add a pre-suspend check in system_suspend() after scheduler_disable() to require all domains to be in the shut down state with SHUTDOWN_suspend before proceeding with the global suspend flow. - Drop the common-level depends on !ARM_64 || !SYSTEM_SUSPEND from CONFIG_HAS_HWDOM_SHUTDOWN_ON_SUSPEND and model the ARM64 suspend case with an arch-selected capability instead. - Rename CONFIG_HAS_HWDOM_SHUTDOWN_ON_SUSPEND to CONFIG_HAS_HWDOM_SYSTEM_SUSPEND. - Rename need_hwdom_shutdown() to want_hwdom_shutdown(). Changes in V7: - Control domain is responsible for host suspend - Move the is_hardware_domain check into host_system_suspend() - Add an empty inline host_system_suspend() function when SYSTEM_SUSPEND config is disabled - Use IS_ENABLED() for config checking instead of #ifdef - Replace #ifdef checks in domain_shutdown() with IS_ENABLED() to simplify control flow. - Factor hardware domain shutdown condition into a helper (need_hwdom_shutdown()) to avoid preprocessor directives inside the function. - Squash with iommu suspend/resume commit --- xen/arch/arm/Kconfig | 2 + xen/arch/arm/include/asm/mm.h | 2 + xen/arch/arm/include/asm/suspend.h | 7 +- xen/arch/arm/mmu/smpboot.c | 2 +- xen/arch/arm/suspend.c | 181 +++++++++++++++++++++++++++++ xen/arch/arm/vpsci.c | 12 +- xen/common/Kconfig | 3 + xen/common/domain.c | 7 +- xen/drivers/passthrough/arm/smmu.c | 10 ++ 9 files changed, 220 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fda..c2e63ce8ff 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -8,6 +8,8 @@ config ARM_64 depends on !ARM_32 select 64BIT select HAS_FAST_MULTIPLY + select HAS_HWDOM_SYSTEM_SUSPEND if SYSTEM_SUSPEND + select HAS_SYSTEM_SUSPEND if !MPU && UNSUPPORTED select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH config ARM diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 72a6928624..87b54a55dc 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -360,6 +360,8 @@ static inline void page_set_xenheap_gfn(struct page_info *p, gfn_t gfn) } while ( (y = cmpxchg(&p->u.inuse.type_info, x, nx)) != x ); } +void set_init_ttbr(lpae_t *root); + #endif /* __ARCH_ARM_MM__ */ /* * Local variables: diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/asm/suspend.h index c127fa3d78..c36ba23b10 100644 --- a/xen/arch/arm/include/asm/suspend.h +++ b/xen/arch/arm/include/asm/suspend.h @@ -38,7 +38,12 @@ extern struct cpu_context cpu_context; int prepare_resume_ctx(struct cpu_context *ptr); void hyp_resume(void); -#endif /* CONFIG_SYSTEM_SUSPEND */ +void host_system_suspend(struct domain *d); + +#else /* !CONFIG_SYSTEM_SUSPEND */ + +static inline void host_system_suspend(struct domain *d) { (void)d; } +#endif #endif /* ARM_SUSPEND_H */ diff --git a/xen/arch/arm/mmu/smpboot.c b/xen/arch/arm/mmu/smpboot.c index 37e91d72b7..ff508ecf40 100644 --- a/xen/arch/arm/mmu/smpboot.c +++ b/xen/arch/arm/mmu/smpboot.c @@ -72,7 +72,7 @@ static void clear_boot_pagetables(void) clear_table(boot_third); } -static void set_init_ttbr(lpae_t *root) +void set_init_ttbr(lpae_t *root) { /* * init_ttbr is part of the identity mapping which is read-only. So diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c index e38566b0b7..4d1289776b 100644 --- a/xen/arch/arm/suspend.c +++ b/xen/arch/arm/suspend.c @@ -1,9 +1,190 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include +#include +#include +#include +#include +#include + struct cpu_context cpu_context = {}; +static int can_system_suspend(void) +{ + int ret = 0; + struct domain *d; + + rcu_read_lock(&domlist_read_lock); + + for_each_domain ( d ) + { + bool domain_suspended; + + spin_lock(&d->shutdown_lock); + domain_suspended = d->is_shut_down && + d->shutdown_code == SHUTDOWN_suspend; + spin_unlock(&d->shutdown_lock); + + if ( domain_suspended ) + continue; + + printk(XENLOG_ERR + "System suspend requires all domains to be shut down for suspend (dom%d: isn't in suspend state)\n", + d->domain_id); + + ret = -EBUSY; + break; + } + + rcu_read_unlock(&domlist_read_lock); + + return ret; +} + +/* Xen suspend. data identifies the domain that initiated suspend. */ +static void system_suspend(void *data) +{ + int status; + unsigned long flags; + struct domain *d = (struct domain *)data; + + BUG_ON(system_state != SYS_STATE_active); + + system_state = SYS_STATE_suspend; + + printk("Xen suspending...\n"); + + freeze_domains(); + scheduler_disable(); + + status = can_system_suspend(); + if ( status ) + { + system_state = SYS_STATE_resume; + goto resume_scheduler; + } + + /* + * Non-boot CPUs have to be disabled on suspend and enabled on resume + * (hotplug-based mechanism). Disabling non-boot CPUs will lead to PSCI + * CPU_OFF to be called by each non-boot CPU. Depending on the underlying + * platform capabilities, this may lead to the physical powering down of + * CPUs. + */ + status = disable_nonboot_cpus(); + if ( status ) + { + system_state = SYS_STATE_resume; + goto resume_nonboot_cpus; + } + + time_suspend(); + + status = iommu_suspend(); + if ( status ) + { + system_state = SYS_STATE_resume; + goto resume_time; + } + + console_start_sync(); + status = console_suspend(); + if ( status ) + { + dprintk(XENLOG_ERR, "Failed to suspend the console, err=%d\n", status); + system_state = SYS_STATE_resume; + goto resume_end_sync; + } + + local_irq_save(flags); + status = gic_suspend(); + if ( status ) + { + system_state = SYS_STATE_resume; + goto resume_irqs; + } + + set_init_ttbr(xen_pgtable); + + /* + * Enable identity mapping before entering suspend to simplify + * the resume path + */ + update_boot_mapping(true); + + if ( prepare_resume_ctx(&cpu_context) ) + { + status = call_psci_system_suspend(); + /* + * If suspend is finalized properly by above system suspend PSCI call, + * the code below in this 'if' branch will never execute. Execution + * will continue from hyp_resume which is the hypervisor's resume point. + * In hyp_resume CPU context will be restored and since link-register is + * restored as well, it will appear to return from prepare_resume_ctx. + * The difference in returning from prepare_resume_ctx on system suspend + * versus resume is in function's return value: on suspend, the return + * value is a non-zero value, on resume it is zero. That is why the + * control flow will not re-enter this 'if' branch on resume. + */ + if ( status ) + dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=%d\n", + status); + } + + system_state = SYS_STATE_resume; + update_boot_mapping(false); + + gic_resume(); + + resume_irqs: + local_irq_restore(flags); + + console_resume(); + resume_end_sync: + console_end_sync(); + + iommu_resume(); + + resume_time: + time_resume(); + + resume_nonboot_cpus: + /* + * The rcu_barrier() has to be added to ensure that the per cpu area is + * freed before a non-boot CPU tries to initialize it (_free_percpu_area() + * has to be called before the init_percpu_area()). This scenario occurs + * when non-boot CPUs are hot-unplugged on suspend and hotplugged on resume. + */ + rcu_barrier(); + enable_nonboot_cpus(); + + resume_scheduler: + scheduler_enable(); + thaw_domains(); + + system_state = SYS_STATE_active; + + printk("Resume (status %d)\n", status); + + domain_resume(d); +} + +static DECLARE_TASKLET(system_suspend_tasklet, system_suspend, NULL); + +void host_system_suspend(struct domain *d) +{ + system_suspend_tasklet.data = (void *)d; + /* + * The suspend procedure has to be finalized by the pCPU#0 (non-boot pCPUs + * will be disabled during the suspend). + */ + tasklet_schedule_on_cpu(&system_suspend_tasklet, 0); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c index bd87ec430d..8fb9172186 100644 --- a/xen/arch/arm/vpsci.c +++ b/xen/arch/arm/vpsci.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -232,8 +233,7 @@ static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid) if ( is_64bit_domain(d) && is_thumb ) return PSCI_INVALID_ADDRESS; - /* SYSTEM_SUSPEND is not supported for the hardware domain yet */ - if ( is_hardware_domain(d) ) + if ( !IS_ENABLED(CONFIG_SYSTEM_SUSPEND) && is_hardware_domain(d) ) return PSCI_NOT_SUPPORTED; /* Ensure that all CPUs other than the calling one are offline */ @@ -266,6 +266,9 @@ static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid) "SYSTEM_SUSPEND requested, epoint=%#"PRIregister", cid=%#"PRIregister"\n", epoint, cid); + if ( is_control_domain(d) ) + host_system_suspend(d); + return rc; } @@ -290,7 +293,10 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id) return 0; case PSCI_1_0_FN32_SYSTEM_SUSPEND: case PSCI_1_0_FN64_SYSTEM_SUSPEND: - return is_hardware_domain(current->domain) ? PSCI_NOT_SUPPORTED : 0; + if ( IS_ENABLED(CONFIG_SYSTEM_SUSPEND) || + !is_hardware_domain(current->domain) ) + return 0; + fallthrough; default: return PSCI_NOT_SUPPORTED; } diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 0a20aa0a12..feb1336f46 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -137,6 +137,9 @@ config HAS_EX_TABLE config HAS_FAST_MULTIPLY bool +config HAS_HWDOM_SYSTEM_SUSPEND + bool + config HAS_IOPORTS bool diff --git a/xen/common/domain.c b/xen/common/domain.c index bb9e210c28..d3edfb2a13 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1375,6 +1375,11 @@ void __domain_crash(struct domain *d) domain_shutdown(d, SHUTDOWN_crash); } +static inline bool want_hwdom_shutdown(uint8_t reason) +{ + return !IS_ENABLED(CONFIG_HAS_HWDOM_SYSTEM_SUSPEND) || + reason != SHUTDOWN_suspend; +} int domain_shutdown(struct domain *d, u8 reason) { @@ -1391,7 +1396,7 @@ int domain_shutdown(struct domain *d, u8 reason) d->shutdown_code = reason; reason = d->shutdown_code; - if ( is_hardware_domain(d) ) + if ( is_hardware_domain(d) && want_hwdom_shutdown(reason) ) hwdom_shutdown(reason); if ( d->is_shutting_down ) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 22d306d0cb..45f29ef8ec 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2947,6 +2947,13 @@ static void arm_smmu_iommu_domain_teardown(struct domain *d) xfree(xen_domain); } +#ifdef CONFIG_SYSTEM_SUSPEND +static int arm_smmu_suspend(void) +{ + return -ENOSYS; +} +#endif + static const struct iommu_ops arm_smmu_iommu_ops = { .page_sizes = PAGE_SIZE_4K, .init = arm_smmu_iommu_domain_init, @@ -2960,6 +2967,9 @@ static const struct iommu_ops arm_smmu_iommu_ops = { .map_page = arm_iommu_map_page, .unmap_page = arm_iommu_unmap_page, .dt_xlate = arm_smmu_dt_xlate_generic, +#ifdef CONFIG_SYSTEM_SUSPEND + .suspend = arm_smmu_suspend, +#endif }; static struct arm_smmu_device *find_smmu(const struct device *dev) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 10:48:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 10:48:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271638.1559755 (Exim 4.92) (envelope-from ) id 1w8Fb0-00024D-QY; Thu, 02 Apr 2026 10:48:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271638.1559755; Thu, 02 Apr 2026 10:48:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Fb0-000246-Mj; Thu, 02 Apr 2026 10:48:18 +0000 Received: by outflank-mailman (input) for mailman id 1271638; Thu, 02 Apr 2026 10:48:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Faz-00021o-CY for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 10:48:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8Fax-004mWN-7H for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:48:16 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce495b-5cb7-0a2a0a5109dd-0a2a4509bee0-48 for ; Thu, 02 Apr 2026 12:48:16 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce4970-bf79-0a2a45090019-d1558029dc9f-3 for ; Thu, 02 Apr 2026 12:48:16 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-48557c8ad47so5649975e9.0 for ; Thu, 02 Apr 2026 03:48:16 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 02 Apr 2026 03:48:15 -0700 (PDT) Message-ID: <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> Date: Thu, 2 Apr 2026 12:48:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1775126896-55752152-FB4D72CC/0/0 X-purgate-type: clean X-purgate-size: 2289 On 02.04.2026 11:35, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: >> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>> The xl dmesg output (from MTL this time): >>> >>> (XEN) [ 123.477511] Entering ACPI S3 state. >>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually >> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() values >> might be a good idea, if only to double check.) > > Updated output: > > (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 > (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events: ffff83046bc1f080 > (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_used: 8 > (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 > (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 > (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 (iommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 > (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_from_msi rc: 0 So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausible. The high half is, however, the address that the low half value is written to. It's hard to imagine that it would be zero when the low half isn't, but it is about the last thing I can think of which could explain observed behavior. (Yet then, all of this is pretty meaningless; see below.) > And the current debug diff attached. Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very useful. You want to move that part of logging to the bottom of hpet_msi_write(), or maybe to where you also log the per-channel cfg value in hpet_broadcast_resume() (thus making the logging overall less verbose). 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The benchmark has one >>>> or more CPUs in Xen calling on_selected_cpus() with between 1 and 64 CPUs in >>>> the selected mask. The executed function simply delays for 500 microseconds. >>>> >>>> The table below shows the % change in execution time of on_selected_cpus(): >>>> >>>> 1 thread 2 threads 4 threads >>>> 1 CPU in mask 0.02 -35.23 -51.18 >>>> 2 CPUs in mask 0.01 -47.20 -69.27 >>>> 4 CPUs in mask -0.02 -42.40 -66.55 >>>> 8 CPUs in mask -0.03 -47.82 -68.39 >>>> 16 CPUs in mask 0.12 -41.95 -58.26 >>>> 32 CPUs in mask 0.02 -25.43 -39.35 >>>> 64 CPUs in mask 0.00 -24.70 -37.83 >>>> >>>> With 1 thread (i.e. no contention), there is no regression in execution time. >>>> With multiple threads, as expected there is a significant improvement in >>>> execution time. >>>> >>>> As a more practical benchmark to simulate host evacuation, I measured the >>>> memory dirtying rate across 10 VMs after enabling log dirty (on an AMD system, >>>> so without PML). The rate increased by 16% with this patch series, even >>>> after the recent deferred TLB flush changes. >>> >>> Is this a positive thing though? In the context of some related work something >>> similar was mentioned iirc, accompanied by stating that this is actually >>> problematic. A guest in log-dirty mode generally wants to be making progress, >>> but also wants to be throttled enough to limit re-dirtying, such that >>> subsequent iterations (in particular the final one) of page contents >>> migration won't have to process overly many pages a 2nd time. >> >> In the context of a real migration, both the process copying the pages >> out of the guest and the guest itself will be hitting the TLB flush lock >> so reducing that bottleneck may increase throughput on both sides. >> Whether or not the overall migration time increases or decreases depends >> on many factors (number of migrations in parallel, the rate the guest is >> dirtying memory, the line speed of the NIC, whether PML is used, ...) >> which is why I measured a more controlled scenario to demonstrate the >> change. >> >> IMO throttling of a guest during a migration should be something >> intentional and controlled by userspace policy rather than a side effect >> of some internal global locks. > > I definitely agree here, but side effects going away may make it necessary to > add such explicit throttling. > Explicit throttling is much more important for the already existing case of Intel systems with PML. With log dirty enabled, a VM on an Intel system can dirty memory an order of magnitude faster than an AMD system without PML. As an aside, for the same test an Intel machine without PML is still a lot faster than AMD so there is probably something to improve in this area for AMD machines. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9b0f8922cd33df2b8e8038d639c1b8d8d73ce401.1775125380.git.mykola_kvach@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775127660-EE3542A1-3CD4198C/0/0 X-purgate-type: clean X-purgate-size: 1927 On 02.04.2026 12:45, Mykola Kvach wrote: > +/* Xen suspend. data identifies the domain that initiated suspend. */ > +static void system_suspend(void *data) > +{ > + int status; > + unsigned long flags; > + struct domain *d = (struct domain *)data; > + > + BUG_ON(system_state != SYS_STATE_active); > + > + system_state = SYS_STATE_suspend; > + > + printk("Xen suspending...\n"); > + > + freeze_domains(); > + scheduler_disable(); > + > + status = can_system_suspend(); > + if ( status ) > + { > + system_state = SYS_STATE_resume; > + goto resume_scheduler; > + } > + > + /* > + * Non-boot CPUs have to be disabled on suspend and enabled on resume > + * (hotplug-based mechanism). Disabling non-boot CPUs will lead to PSCI > + * CPU_OFF to be called by each non-boot CPU. Depending on the underlying > + * platform capabilities, this may lead to the physical powering down of > + * CPUs. > + */ > + status = disable_nonboot_cpus(); > + if ( status ) > + { > + system_state = SYS_STATE_resume; > + goto resume_nonboot_cpus; > + } > + > + time_suspend(); > + > + status = iommu_suspend(); > + if ( status ) > + { > + system_state = SYS_STATE_resume; > + goto resume_time; > + } So you've frozen the system just to get ... > --- a/xen/drivers/passthrough/arm/smmu.c > +++ b/xen/drivers/passthrough/arm/smmu.c > @@ -2947,6 +2947,13 @@ static void arm_smmu_iommu_domain_teardown(struct domain *d) > xfree(xen_domain); > } > > +#ifdef CONFIG_SYSTEM_SUSPEND > +static int arm_smmu_suspend(void) > +{ > + return -ENOSYS; > +} > +#endif ... unconditional failure from here? Also, ENOSYS is clearly inappropriate to use here. EOPNOTSUPP or something yet better distinguishable, please (if this can't be dropped altogether). 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM4PR03MB11152.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2b5291b2-224d-4df2-2a23-08de90a7844f X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2026 11:03:48.4663 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yr+QQrRCfl734s8GYNx4ctuJidJ4neiIXiDFDrS0i/g8IGPys6UOmucJqPa7ZInS7ladvLpt/x6jmk4JLXMx2ULeAwFvVsuAQNj04dU79Fo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB6984 X-purgate-ID: tlsNG-bad1c0/1775127830-2E74A152-E7EA62D9/0/0 X-purgate-type: clean X-purgate-size: 2697 When building Xen with CONFIG_STATIC_SHM=3Dn, booting a hardware domain with exactly NR_MEM_BANKS (256) reserved-memory regions causes a panic: (XEN) Xen BUG at common/device-tree/domain-build.c:497 (XEN) Xen call trace: (XEN) [<00000a0000289aa8>] make_memory_node+0x178/0x234 (PC) This occurs due to an off-by-one error in the bounds checking of the reg array in make_memory_node(). The check: BUG_ON(nr_cells >=3D ARRAY_SIZE(reg)); incorrectly triggers when the array is exactly full (i.e., when nr_cells =3D=3D ARRAY_SIZE(reg)), preventing the 256th and final valid memory region from being written. When CONFIG_STATIC_SHM=3Dy, this bug remains hidden because DT_MEM_NODE_REG_RANGE_SIZE adds extra space for SHM banks. This extra capacity prevents the array from ever reaching its maximum limit while processing the 256th memory region. Fix this by changing the condition to strictly greater than (>). Apply the exact same fix to shm_mem_node_fill_reg_range() to prevent the same error. Signed-off-by: Oleksandr Tyshchenko --- For context, this issue was also discovered while testing maximum limits. I did not notice it while working on my previous DOM0_FDT_EXTRA_SIZE patch because my .config had CONFIG_STATIC_SHM=3Dy enabled at the time, which masks the error. --- xen/common/device-tree/domain-build.c | 2 +- xen/common/device-tree/static-shmem.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree= /domain-build.c index 6708c9dd66..540627b74e 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -494,7 +494,7 @@ int __init make_memory_node(const struct kernel_info *k= info, int addrcells, continue; =20 nr_cells +=3D reg_size; - BUG_ON(nr_cells >=3D ARRAY_SIZE(reg)); + BUG_ON(nr_cells > ARRAY_SIZE(reg)); dt_child_set_range(&cells, addrcells, sizecells, start, size); } =20 diff --git a/xen/common/device-tree/static-shmem.c b/xen/common/device-tree= /static-shmem.c index 79f23caa77..4c4cc1b123 100644 --- a/xen/common/device-tree/static-shmem.c +++ b/xen/common/device-tree/static-shmem.c @@ -838,7 +838,7 @@ void __init shm_mem_node_fill_reg_range(const struct ke= rnel_info *kinfo, paddr_t size =3D mem->bank[i].size; =20 *nr_cells +=3D addrcells + sizecells; - BUG_ON(*nr_cells >=3D DT_MEM_NODE_REG_RANGE_SIZE); + BUG_ON(*nr_cells > DT_MEM_NODE_REG_RANGE_SIZE); dt_child_set_range(&cells, addrcells, sizecells, start, size); } } --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 11:31:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 11:31:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271729.1559791 (Exim 4.92) (envelope-from ) id 1w8GGU-00035I-OR; Thu, 02 Apr 2026 11:31:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271729.1559791; Thu, 02 Apr 2026 11:31:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8GGU-00035B-LG; Thu, 02 Apr 2026 11:31:10 +0000 Received: by outflank-mailman (input) for mailman id 1271729; Thu, 02 Apr 2026 11:31:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8GGT-000355-KM for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 11:31:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8GGT-0066G9-0g for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 13:31:09 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce537c-e002-0a2a0a5209dd-0a2a450bb440-2 for ; Thu, 02 Apr 2026 13:31:08 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce537c-bca8-0a2a450b0019-d1558032b851-3 for ; Thu, 02 Apr 2026 13:31:08 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-48891776099so6362445e9.2 for ; Thu, 02 Apr 2026 04:31:08 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8196fa8f000e384af697a44cb3d50ece966e82a7.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775129468-EF7422A1-62C998B7/0/0 X-purgate-type: clean X-purgate-size: 3283 On 10.03.2026 18:08, Oleksii Kurochko wrote: > Each vCPU interacting with the IMSIC requires state to track the > associated guest interrupt file and its backing context. > > Introduce a per-vCPU structure to hold IMSIC-related state, including > the guest interrupt file identifier and the CPU providing the backing > VS-file. Access to the guest file identifier is protected by a lock. > > Initialize this structure during vCPU setup and store it in arch_vcpu. > The initial state marks the VS-file as software-backed until it becomes > associated with a physical CPU. > > Add helpers to retrieve and update the guest interrupt file identifier. Yet again a functions with no callers. > --- a/xen/arch/riscv/imsic.c > +++ b/xen/arch/riscv/imsic.c > @@ -59,6 +59,29 @@ do { \ > csr_clear(CSR_SIREG, v); \ > } while (0) > > +unsigned int vcpu_guest_file_id(const struct vcpu *v) > +{ > + struct imsic_state *imsic_state = v->arch.imsic_state; > + unsigned long flags; > + unsigned int vsfile_id; > + > + read_lock_irqsave(&imsic_state->vsfile_lock, flags); > + vsfile_id = imsic_state->guest_file_id; > + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); What purpose does this locking have? Already ... > + return vsfile_id; ... here the value can be stale, if indeed there is a chance of races. Did you perhaps mean to use ACCESS_ONCE() here and where the value is set? > @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_node *node, > return 0; > } > > +int __init vcpu_imsic_init(struct vcpu *v) __init for a function involved in setting up a vCPU? > +{ > + struct imsic_state *imsic_state; > + > + /* Allocate IMSIC context */ > + imsic_state = xvzalloc(struct imsic_state); > + if ( !imsic_state ) > + return -ENOMEM; > + > + v->arch.imsic_state = imsic_state; > + > + /* Setup IMSIC context */ > + rwlock_init(&imsic_state->vsfile_lock); > + > + imsic_state->guest_file_id = imsic_state->vsfile_pcpu = NR_CPUS; Iirc Misra dislikes such double assignments, so better avoid them right away. (As per a comment at the bottom this may need splitting anyway.) > --- a/xen/arch/riscv/include/asm/domain.h > +++ b/xen/arch/riscv/include/asm/domain.h > @@ -52,6 +52,8 @@ struct arch_vcpu { > > struct vtimer vtimer; > > + struct imsic_state *imsic_state; Just like it's "vtimer", perhaps also "vimsic_state" for both the field and the struct tag? > @@ -64,8 +65,20 @@ struct imsic_config { > spinlock_t lock; > }; > > +struct imsic_state { > + /* IMSIC VS-file */ > + rwlock_t vsfile_lock; > + unsigned int guest_file_id; > + /* > + * (vsfile_pcpu >= 0) => h/w IMSIC VS-file > + * (vsfile_pcpu == NR_CPUS) => s/w IMSIC SW-file > + */ > + unsigned long vsfile_pcpu; And why unsigned long, when unsigned int will do (as about everywhere else for CPU numbers)? That'll also shrink the structure size by 8 bytes. As to the comment - as per vcpu_imsic_init() NR_CPUS also has some special meaning for guest_file_id, yet there's no comment there. How do file ID and NR_CPUS fit together anyway? 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The >>>>> benchmark has one >>>>> or more CPUs in Xen calling on_selected_cpus() with between 1 and >>>>> 64 CPUs in >>>>> the selected mask. The executed function simply delays for 500 >>>>> microseconds. >>>>> >>>>> The table below shows the % change in execution time of >>>>> on_selected_cpus(): >>>>> >>>>>                     1 thread   2 threads    4 threads >>>>> 1 CPU in mask     0.02       -35.23       -51.18 >>>>> 2 CPUs in mask    0.01       -47.20       -69.27 >>>>> 4 CPUs in mask    -0.02      -42.40       -66.55 >>>>> 8 CPUs in mask    -0.03      -47.82       -68.39 >>>>> 16 CPUs in mask   0.12       -41.95       -58.26 >>>>> 32 CPUs in mask   0.02       -25.43       -39.35 >>>>> 64 CPUs in mask   0.00       -24.70       -37.83 >>>>> >>>>> With 1 thread (i.e. no contention), there is no regression in >>>>> execution time. >>>>> With multiple threads, as expected there is a significant >>>>> improvement in >>>>> execution time. >>>>> >>>>> As a more practical benchmark to simulate host evacuation, I >>>>> measured the >>>>> memory dirtying rate across 10 VMs after enabling log dirty (on an >>>>> AMD system, >>>>> so without PML). The rate increased by 16% with this patch series, >>>>> even >>>>> after the recent deferred TLB flush changes. >>>> >>>> Is this a positive thing though? In the context of some related >>>> work something >>>> similar was mentioned iirc, accompanied by stating that this is >>>> actually >>>> problematic. A guest in log-dirty mode generally wants to be making >>>> progress, >>>> but also wants to be throttled enough to limit re-dirtying, such that >>>> subsequent iterations (in particular the final one) of page contents >>>> migration won't have to process overly many pages a 2nd time. >>> >>> In the context of a real migration, both the process copying the pages >>> out of the guest and the guest itself will be hitting the TLB flush >>> lock >>> so reducing that bottleneck may increase throughput on both sides. >>> Whether or not the overall migration time increases or decreases >>> depends >>> on many factors (number of migrations in parallel, the rate the >>> guest is >>> dirtying memory, the line speed of the NIC, whether PML is used, ...) >>> which is why I measured a more controlled scenario to demonstrate the >>> change. >>> >>> IMO throttling of a guest during a migration should be something >>> intentional and controlled by userspace policy rather than a side >>> effect >>> of some internal global locks. >> >> I definitely agree here, but side effects going away may make it >> necessary to >> add such explicit throttling. >> > > Explicit throttling is much more important for the already existing > case of Intel systems with PML. With log dirty enabled, a VM on an Intel > system can dirty memory an order of magnitude faster than an AMD system > without PML. > > As an aside, for the same test an Intel machine without PML is still a > lot faster than AMD so there is probably something to improve in this > area for AMD machines.  AMD have PML on the way.  https://docs.amd.com/v/u/en-US/69208_1.00_AMD64_PML_PUB There is a mis-step with how support for Intel's PML is done, meaning that draining the vCPU's PML buffers is extraordinarily expensive even when there's no action to take.  (Specifically, the remote VMCS acquire) A better option is this:  When logdirty is active, any VMExit will drain the PML buffer into the logdirty bitmap before processing the main exit reason.  This way, you drain all the PML buffers by just IPI-ing the domain dirty mask. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 02 11:58:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 11:58:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271763.1559808 (Exim 4.92) (envelope-from ) id 1w8Gh9-0006cu-1H; Thu, 02 Apr 2026 11:58:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271763.1559808; Thu, 02 Apr 2026 11:58:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Gh8-0006cn-Ur; Thu, 02 Apr 2026 11:58:42 +0000 Received: by outflank-mailman (input) for mailman id 1271763; Thu, 02 Apr 2026 11:58:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Gh7-0006ch-BF for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 11:58:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8Gh6-008pgi-Nl for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 13:58:40 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce59e8-bab6-0a2a0a5309dd-0a2a4501982e-20 for ; Thu, 02 Apr 2026 13:58:40 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce59f0-6fc9-0a2a45010019-d155dd32f097-3 for ; Thu, 02 Apr 2026 13:58:40 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43d23305225so379660f8f.2 for ; Thu, 02 Apr 2026 04:58:40 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1775131120-16AF5185-DDCAC4BE/0/0 X-purgate-type: clean X-purgate-size: 4906 On 10.03.2026 18:08, Oleksii Kurochko wrote: > @@ -47,6 +48,19 @@ struct intc_hw_operations { > const struct dt_device_node *intc); > }; > > +struct vintc_ops { > + /* Initialize some vINTC-related stuff for a vCPU */ > + int (*vcpu_init)(struct vcpu *vcpu); v as the parameter name, to fit our convention? (Same below for the other hook.) > + /* Check if a register is virtual interrupt controller MMIO */ > + int (*is_access)(const struct vcpu *vcpu, const unsigned long addr); What does "register" in the comment refer to. All I see is an address. (The const will also want dropping from the parameter in this declaration.) > +}; > + > +struct vintc { > + const struct intc_info *info; Isn't this referencing a physical INTC's structure? Why would the virtual one's properties have to match that of the physical one? > --- /dev/null > +++ b/xen/arch/riscv/include/asm/vaplic.h > @@ -0,0 +1,36 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * xen/arch/riscv/vaplic.c > + * > + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support > + * > + * Copyright (c) Microchip. > + */ > + > +#ifndef ASM__RISCV__VAPLIC_H > +#define ASM__RISCV__VAPLIC_H > + > +#include > +#include > + > +#include > + > +struct domain; > + > +#define to_vaplic(v) container_of(v, struct vaplic, base) I'm confused here, maybe first of all because of the use of v. v is our common identified for struct vcpu * instances. Using it in a macro like this one suggests a struct vcpu * needs passing into the macro. Yet from the two uses of the macro that doesn't look to be the case. Perhaps best to have a struct domain * passed into here? > +struct vaplic_regs { > + uint32_t domaincfg; > + uint32_t smsiaddrcfg; > + uint32_t smsiaddrcfgh; The latter two aren't used, and generally I'd expect a h-suffixed field to exist only for RV32. (The un-suffixed field then would need to be unsigned long, of course.) > +}; > + > +struct vaplic { > + struct vintc base; How does "base" fit with the type of the field? > --- a/xen/arch/riscv/intc.c > +++ b/xen/arch/riscv/intc.c > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > #include Why is this change needed all of the sudden? > --- /dev/null > +++ b/xen/arch/riscv/vaplic.c > @@ -0,0 +1,74 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * xen/arch/riscv/vaplic.c > + * > + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support > + * > + * Copyright (c) Microchip. > + * Copyright (c) Vates > + */ > + > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +#include "aplic-priv.h" > + > +static int __init cf_check vcpu_vaplic_init(struct vcpu *v) > +{ > + int rc = 0; > + > + rc = vcpu_imsic_init(v); > + if ( rc ) > + return rc; > + > + imsic_set_guest_file_id(v, vgein_assign(v)); And vgein_assign() can't fail? (Rhetorical question - of course it can. That function shouldn't assert that it can fine a valid ID.) But then - aren't you limiting the number of vCPU-s a host can handle by the number vgein IDs? > + return rc; > +} > + > +static const struct vintc_ops vaplic_ops = { > + .vcpu_init = vcpu_vaplic_init, > +}; > + > +static struct vintc * __init vaplic_alloc(void) > +{ > + struct vaplic *v = NULL; Onve again - why the initializer? In fact, ... > + v = xvzalloc(struct vaplic); ... this could be the initializer. > + if ( !v ) > + return NULL; > + > + return &v->base; > +} If you returned and ... > +int __init domain_vaplic_init(struct domain *d) > +{ > + int ret = 0; > + > + d->arch.vintc = vaplic_alloc(); ... stored struct vaplic *, the slightly odd to_vaplic() macro wouldn't be needed. > + if ( !d->arch.vintc ) > + { > + ret = -ENOMEM; > + goto fail; Nit: goto when simply return could be used. > + } > + > + d->arch.vintc->ops = &vaplic_ops; Are other kinds of ops structures going to appear? If not, why the extra indirection? > + to_vaplic(d->arch.vintc)->regs.domaincfg = > + APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_DM; > + > + fail: > + return ret; > +} > + > +void __init domain_vaplic_deinit(struct domain *d) > +{ > + struct vaplic *vaplic = to_vaplic(d->arch.vintc); > + > + XVFREE(vaplic); If this cleared the struct domain field, then yes. But the way it is, just xvfree() will suffice. (Re-work following other remarks may want it to become XVFREE() again, though.) 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> } > > -void __iomem *ioremap(paddr_t pa, size_t len) > +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > { > - mfn_t mfn = _mfn(PFN_DOWN(pa)); > - void *va; > - > - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > + WARN_ON(page_is_ram_type(PFN_DOWN(pa), RAM_TYPE_CONVENTIONAL)); > > /* The low first Mb is always mapped. */ > - if ( !((pa + len - 1) >> 20) ) > - va = __va(pa); > - else > - { > - unsigned int offs = pa & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - > - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_UCMINUS, VMAP_DEFAULT); > - if ( va ) > - va += offs; > - } > - > - return (void __force __iomem *)va; > -} > - > -void __iomem *__init ioremap_wc(paddr_t pa, size_t len) > -{ > - mfn_t mfn = _mfn(PFN_DOWN(pa)); > - unsigned int offs = pa & (PAGE_SIZE - 1); > - unsigned int nr = PFN_UP(offs + len); > - void *va; > - > - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > - > - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_WC, VMAP_DEFAULT); > + if ( !((pa + len - 1) >> 20) && attr == PAGE_HYPERVISOR_UCMINUS ) > + return (void __force __iomem *)__va(pa); Sorry, I'm possibly a bit lost: I see that on the bootstrap page-tables we map the VGA hole (0xa0000-0xc0000) as UC-, but I'm not seeing this being done to the directmap? > > - return (void __force __iomem *)(va ? va + offs : NULL); > + return NULL; > } > > int create_perdomain_mapping(struct domain *d, unsigned long va, > --- a/xen/common/Makefile > +++ b/xen/common/Makefile > @@ -19,6 +19,7 @@ obj-$(CONFIG_GRANT_TABLE) += grant_table > obj-y += guestcopy.o > obj-y += gzip/ > obj-$(CONFIG_HYPFS) += hypfs.o > +obj-y += ioremap.o > obj-$(CONFIG_IOREQ_SERVER) += ioreq.o > obj-y += irq.o > obj-y += kernel.o > --- /dev/null > +++ b/xen/common/ioremap.c > @@ -0,0 +1,42 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > + > +#include > + > +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > +{ > + void __iomem *ptr = NULL; > + unsigned int offs = PAGE_OFFSET(pa); > + > +#ifdef arch_ioremap_attr > + ptr = arch_ioremap_attr(pa, len, attr); > + if ( PAGE_OFFSET(ptr) ) > + return ptr; IMO it's a bit confusing to deal with the offset addition detached form here, I would rather do: if ( ptr != NULL ) { ASSERT(PAGE_OFFSET(ptr) == offs); return PAGE_OFFSET(ptr) ? ptr : ptr + off; } And get rid of the !ptr check in the if below. So that when arch_ioremap_attr() succeeds it's all dealt with in the #ifdef protected block. > +#endif > + > + if ( IS_ENABLED(CONFIG_HAS_VMAP) && !ptr ) > + { > + mfn_t mfn = _mfn(PFN_DOWN(pa)); > + > + ptr = (void __force __iomem *)__vmap(&mfn, PFN_UP(offs + len), 1, 1, > + attr, VMAP_DEFAULT); > + } > + > + if ( !ptr ) > + return NULL; > + > + return ptr + offs; I would also join the NULL checking using a ternary operator: return ptr ? ptr + off : NULL; Thanks, Roger. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <10654a6c38fa929b5fdf6f214badfe4f60fe78d4.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775132525-40B6DC9A-B9543FF6/0/0 X-purgate-type: clean X-purgate-size: 6213 On 10.03.2026 18:08, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/setup.h > +++ b/xen/arch/riscv/include/asm/setup.h > @@ -5,6 +5,10 @@ > > #include > > +struct domain; > +struct dt_device_node; > +struct rangeset; > + > #define max_init_domid (0) > > void setup_mm(void); > @@ -13,6 +17,19 @@ void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len); > > void init_csr_masks(void); > > +/* TODO: move somewhere to common header? */ Counter question: Why ... > +/* > + * Retrieves the interrupts configuration from a device tree node and maps > + * those interrupts to the target domain. > + * > + * Returns: > + * < 0 error > + * 0 success > + */ > +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, > + bool need_mapping, > + struct rangeset *irq_ranges); ... is this not an inline function, when ... > --- a/xen/arch/riscv/intc.c > +++ b/xen/arch/riscv/intc.c > @@ -79,3 +79,11 @@ int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) > > return -ENOSYS; > } > + > +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, > + bool need_mapping, > + struct rangeset *irq_ranges) > +{ > + return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, > + irq_ranges); > +} ... it's merely a wrapper around an indirect function call? And then the function isn't used anywhere anyway. > --- a/xen/arch/riscv/vaplic.c > +++ b/xen/arch/riscv/vaplic.c > @@ -9,6 +9,7 @@ > */ > > #include > +#include > #include > #include > > @@ -19,6 +20,113 @@ > > #include "aplic-priv.h" > > +struct vaplic_priv { > + /* Contains a legal interrupts for a domain */ > + uint32_t auth_irq_bmp[APLIC_NUM_REGS]; > +}; With it apparently plural that is correct, the first "a" wants dropping from the comment. > +static bool is_irq_shared_among_domains(const struct domain *d, > + const unsigned int irq_num) > +{ > + struct domain *tmp; const > + unsigned int reg_num = irq_num / APLIC_NUM_REGS; > + unsigned int bit_pos = irq_num % APLIC_NUM_REGS; > + > + for_each_domain ( tmp ) See other uses of the construct for how this needs synchronizing. But looping over all domains looks pretty inefficient anyway for ... > + { > + uint32_t *auth_irq_bmp; > + > + if ( tmp == d ) > + continue; > + > + auth_irq_bmp = tmp->arch.vintc->private; > + > + if ( auth_irq_bmp[reg_num] & BIT(bit_pos, U) ) > + { > + printk("%s: irq%d is shared between %pd and %pd\n", __func__, > + irq_num, tmp, d); > + > + return true; > + } ... the intended purpose. If IRQs can't be shared, can't you maintain global state of which ones are in use _somewhere_? > + } > + > + return false; > +} This together with ... > +int vaplic_map_device_irqs_to_domain(struct domain *d, > + struct dt_device_node *dev, > + bool need_mapping, > + struct rangeset *irq_ranges) > +{ > + unsigned int i, nirq; > + int res, irq; > + struct dt_raw_irq rirq; > + uint32_t *auth_irq_bmp = d->arch.vintc->private; > + unsigned int reg_num; > + > + nirq = dt_number_of_irq(dev); > + > + /* Give permission and map IRQs */ > + for ( i = 0; i < nirq; i++ ) > + { > + res = dt_device_get_raw_irq(dev, i, &rirq); > + if ( res ) > + { > + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", > + i, dt_node_full_name(dev)); > + return res; > + } > + > + /* > + * Don't map IRQ that have no physical meaning > + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. > + */ > + if ( rirq.controller != dt_interrupt_controller ) > + { > + dt_dprintk("irq %u not connected to primary controller." > + "Connected to %s\n", i, > + dt_node_full_name(rirq.controller)); > + continue; > + } > + > + irq = platform_get_irq(dev, i); > + if ( irq < 0 ) > + { > + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); > + return irq; > + } > + > + res = irq_permit_access(d, irq); > + if ( res ) > + { > + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, > + irq); This time the other way around: %d please with plain int. (Again at least once further down.) > + return res; > + } > + > + reg_num = irq / APLIC_NUM_REGS; > + > + if ( is_irq_shared_among_domains(d, irq) ) > + { > + printk("%s: Shared IRQ isn't supported\n", __func__); > + return -EINVAL; > + } > + > + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); ... all of this leaves me with the impression that IRQ numbering isn't really virtualized. IRQs are merely split into groups, one group per domain (and maybe some unused). How are you going to fit in truly virtual IRQs? > + dt_dprintk(" - IRQ: %u\n", irq); > + > + if ( irq_ranges ) > + { > + res = rangeset_add_singleton(irq_ranges, irq); > + if ( res ) > + return res; > + } What is irq_ranges? > @@ -34,6 +142,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu *v) > > static const struct vintc_ops vaplic_ops = { > .vcpu_init = vcpu_vaplic_init, > + .map_device_irqs_to_domain = vaplic_map_device_irqs_to_domain, > }; What about the inverse function, needed for domain cleanup? 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Thu, 02 Apr 2026 05:42:55 -0700 (PDT) Message-ID: Date: Thu, 2 Apr 2026 14:42:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] make ioremap_attr() common To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk , Timothy Pearson References: <924f3ef2-7883-4322-a921-edc814c96719@suse.com> <81e4f7e0-df57-4a5b-b16d-fe668682d94c@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775133776-FF348A3D-880614EF/0/0 X-purgate-type: clean X-purgate-size: 3866 On 02.04.2026 14:15, Roger Pau Monné wrote: > On Thu, Feb 19, 2026 at 04:51:54PM +0100, Jan Beulich wrote: >> --- a/xen/arch/x86/mm.c >> +++ b/xen/arch/x86/mm.c >> @@ -6166,41 +6166,15 @@ void *__init arch_vmap_virt_end(void) >> return fix_to_virt(__end_of_fixed_addresses); >> } >> >> -void __iomem *ioremap(paddr_t pa, size_t len) >> +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) >> { >> - mfn_t mfn = _mfn(PFN_DOWN(pa)); >> - void *va; >> - >> - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); >> + WARN_ON(page_is_ram_type(PFN_DOWN(pa), RAM_TYPE_CONVENTIONAL)); >> >> /* The low first Mb is always mapped. */ >> - if ( !((pa + len - 1) >> 20) ) >> - va = __va(pa); >> - else >> - { >> - unsigned int offs = pa & (PAGE_SIZE - 1); >> - unsigned int nr = PFN_UP(offs + len); >> - >> - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_UCMINUS, VMAP_DEFAULT); >> - if ( va ) >> - va += offs; >> - } >> - >> - return (void __force __iomem *)va; >> -} >> - >> -void __iomem *__init ioremap_wc(paddr_t pa, size_t len) >> -{ >> - mfn_t mfn = _mfn(PFN_DOWN(pa)); >> - unsigned int offs = pa & (PAGE_SIZE - 1); >> - unsigned int nr = PFN_UP(offs + len); >> - void *va; >> - >> - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); >> - >> - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_WC, VMAP_DEFAULT); >> + if ( !((pa + len - 1) >> 20) && attr == PAGE_HYPERVISOR_UCMINUS ) >> + return (void __force __iomem *)__va(pa); > > Sorry, I'm possibly a bit lost: I see that on the bootstrap > page-tables we map the VGA hole (0xa0000-0xc0000) as UC-, but I'm not > seeing this being done to the directmap? I'm not changing that aspect here, do I? ioremap() used the direct map (apparently assuming the cache attribute is suitable), and so do I now. Yet then, to address the point you make anyway, I certainly see use of __PAGE_HYPERVISOR_UCMINUS in l1_directmap[]. >> --- /dev/null >> +++ b/xen/common/ioremap.c >> @@ -0,0 +1,42 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#include >> +#include >> +#include >> + >> +#include >> + >> +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) >> +{ >> + void __iomem *ptr = NULL; >> + unsigned int offs = PAGE_OFFSET(pa); >> + >> +#ifdef arch_ioremap_attr >> + ptr = arch_ioremap_attr(pa, len, attr); >> + if ( PAGE_OFFSET(ptr) ) >> + return ptr; > > IMO it's a bit confusing to deal with the offset addition detached > form here, I would rather do: > > if ( ptr != NULL ) > { > ASSERT(PAGE_OFFSET(ptr) == offs); > return PAGE_OFFSET(ptr) ? ptr : ptr + off; > } > > And get rid of the !ptr check in the if below. So that when > arch_ioremap_attr() succeeds it's all dealt with in the #ifdef > protected block. Possible, yet I deemed the other variant better. The assertion you suggest isn't valid anyway (see the last sentence of the description and xen/arch/arm/mpu/mm.c:ioremap_attr() prior to Michal's "xen/arm: mpu: Fix ioremap_attr region size and return value"). Now that that's changing, things may indeed be possible to simplify here. >> +#endif >> + >> + if ( IS_ENABLED(CONFIG_HAS_VMAP) && !ptr ) >> + { >> + mfn_t mfn = _mfn(PFN_DOWN(pa)); >> + >> + ptr = (void __force __iomem *)__vmap(&mfn, PFN_UP(offs + len), 1, 1, >> + attr, VMAP_DEFAULT); >> + } >> + >> + if ( !ptr ) >> + return NULL; >> + >> + return ptr + offs; > > I would also join the NULL checking using a ternary operator: > > return ptr ? ptr + off : NULL; Can do, sure. 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pr=C Message-ID: <865ae6a0-15e0-4a27-9537-0c5e6cb0a1cb@amd.com> Date: Thu, 2 Apr 2026 14:45:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/device-tree: Fix off-by-one bounds check in make_memory_node() To: Oleksandr Tyshchenko , "xen-devel@lists.xenproject.org" CC: Stefano Stabellini , Julien Grall , Bertrand Marquis References: <20260402110330.3580124-1-oleksandr_tyshchenko@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <20260402110330.3580124-1-oleksandr_tyshchenko@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|MN2PR12MB4126:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b0ce731-8a0a-49b6-f0bf-08de90b5afbb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: 5KoNdoBUJxpPIlmSgkJ7t7bYZEdtlWceF0nUJygc3BrhUY8iA7K7ghgND1QkQrBN8QSAif0VjyGXqP37Jap1WD/Uf0OQNHxoXBprtDaku8PHni2ZIDZAKtsV8ZNhw7knJCw5Wwk29h7fHHgoyyviEV9FmNfCujbPr0Ea+JbWrxGal/qxG1ZMIWdeTLHDFquf7C+yE5s+p7+FaDxcvon8woHO9YVUOA6/vKHBttgvbLgzQAaq+vFNmU5WPNGcESHpoS1pUCD9RMOxAewFJt/3QCEsL9lrj2BJk/NwkKFvmI1ZT+m/qdk0vMQKcTGjqFCD95AAPuGVTLdjkPx7SlmFTKfpD2L7+14IBql3FfshTgx6+aPnrZwGsQWdBQq55lU8jnSUny9AUghgBqanZ7QacET9PLGPAFns3A0pbCf4CAFS3PTOIngac3OyJr5+5AXAyDaoT0tdSQ/bM4de8FCElj+WsuXS5OkuLLCiwk1tktDLZDQMxocFvSJVsA+IMBdszfBlyTbkYp2l7XYHmVml36eHXtrVT8D986i7GnlklxS/sF+2Xdxo7ispRD9MCtWB4FPP8VqhIcA4ZjNT/3lspHn+lh9uyzOX23nJ/7Vd3oCZaDK8O0y/iBHhwvTKCKOz7zrzqNg5QJFqT8wSRrxQj27EEd5ocr3eqUIiycVICGE/GBmPF7vf+4SpxbwrKOw4EiQ1WwvB7h8RradgV61ubRns5+fe0ja+2+WoewHMBk7CE4woGrWzkHBG+o1kTjthHXARRTFhR32x5tOsOF8D7w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Vc6/8abjOR/WhcjOXKkQXh5zx3spC3HtKeM4U6sy4Cg1KtxNMNgVfqqdRymqo2880atk5/Y6NVxN63oqAhinJaQQq9Nmr4sgN1URs/Z2rkImDOSu0heJ3jcsPnUw7XQV8nWcjgJfcgff951tL+NO/YX4HxoKviCAl4d0vGrCHVNQ07cOIJQVElbE9q+pPjg+TQ28a8bkAOLvekBxG9LFxOwsbJux6c5lyCYPumi3kKSb9bYoUw4ZkZ47a/q+4N43tcwtkT6XmzNNaOV4aRcFhhWFePttwq/zlUPh58Tli457LeZDomHDOU+U6xhqfiyIAJWEqoOK88A0OkSzsNvJNJ1yBsSFjXKECrrGxEzVk8+/7iEeSrYkp2lrQYCbl+3apMv67BVZUm0MiLZWD5PnxPP1AncKJaVaN7oTIDK6s9dXMh8b4vPXNvluyLEOUngb X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2026 12:45:14.4598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b0ce731-8a0a-49b6-f0bf-08de90b5afbb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4126 X-purgate-ID: tlsNG-720697/1775133923-4CDF6CD1-32F2E584/0/0 X-purgate-type: clean X-purgate-size: 1416 On 02/04/2026 13:03, Oleksandr Tyshchenko wrote: > When building Xen with CONFIG_STATIC_SHM=n, booting a hardware > domain with exactly NR_MEM_BANKS (256) reserved-memory regions > causes a panic: > > (XEN) Xen BUG at common/device-tree/domain-build.c:497 > (XEN) Xen call trace: > (XEN) [<00000a0000289aa8>] make_memory_node+0x178/0x234 (PC) > > This occurs due to an off-by-one error in the bounds checking of > the reg array in make_memory_node(). The check: > BUG_ON(nr_cells >= ARRAY_SIZE(reg)); > incorrectly triggers when the array is exactly full (i.e., when > nr_cells == ARRAY_SIZE(reg)), preventing the 256th and final valid > memory region from being written. > > When CONFIG_STATIC_SHM=y, this bug remains hidden because AFAICT it remains hidden as long as you don't add NR_SHMEM_BANKS banks. In that case you will also hit this problem. > DT_MEM_NODE_REG_RANGE_SIZE adds extra space for SHM banks. > This extra capacity prevents the array from ever reaching its > maximum limit while processing the 256th memory region. > > Fix this by changing the condition to strictly greater than (>). > Apply the exact same fix to shm_mem_node_fill_reg_range() to > prevent the same error. > > Signed-off-by: Oleksandr Tyshchenko This should have a Fixes tag. With that: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 02 12:51:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 12:51:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271859.1559857 (Exim 4.92) (envelope-from ) id 1w8HWc-0007tt-OY; Thu, 02 Apr 2026 12:51:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271859.1559857; Thu, 02 Apr 2026 12:51:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8HWc-0007tl-LV; Thu, 02 Apr 2026 12:51:54 +0000 Received: by outflank-mailman (input) for mailman id 1271859; Thu, 02 Apr 2026 12:51:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w8HWb-0007tc-Gr for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 12:51:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8HWa-00FAUJ-Sc for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 14:51:52 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce6668-e002-0a2a0a5209dd-0a2a450c8076-0 for ; Thu, 02 Apr 2026 14:51:52 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce6668-f40c-0a2a450c0019-d1558036e0a6-3 for ; Thu, 02 Apr 2026 14:51:52 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-486b96760easo9214975e9.2 for ; Thu, 02 Apr 2026 05:51:52 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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To: Oleksii Kurochko Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <2097fefb49fca36f641ddd7d7fb31e796a03619e.1773157782.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2097fefb49fca36f641ddd7d7fb31e796a03619e.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775134312-A51BBA3D-BC82449B/10/73395122804 X-purgate-type: spam X-purgate-size: 2380 On 10.03.2026 18:08, Oleksii Kurochko wrote: > These definitions are required for correct decoding of APLIC MMIO > accesses and target configuration, and will be used by both the > physical and virtual APLIC implementations. > > No functional change is intended by this patch; it only centralises > hardware definitions that were previously missing. > > Co-developed-by: Romain Caritey > Signed-off-by: Oleksii Kurochko I can commit this as is (with my ack added), but I'd like you to consider again my remark elsewhere as to ... > --- a/xen/arch/riscv/include/asm/aplic.h > +++ b/xen/arch/riscv/include/asm/aplic.h > @@ -17,6 +17,11 @@ > > #define APLIC_NUM_REGS 32 > > +#define APLIC_REG_OFFSET_MASK 0x3FFF > +#define APLIC_TARGET_IPRIO_MASK 0xFF > +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 > +#define APLIC_TARGET_EIID_MASK 0x7FF > + > #define APLIC_DOMAINCFG_IE BIT(8, U) > #define APLIC_DOMAINCFG_DM BIT(2, U) > > @@ -27,6 +32,36 @@ > #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 > #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 > > +#define APLIC_DOMAINCFG 0x0000 > +#define APLIC_SOURCECFG_BASE 0x0004 > +#define APLIC_SOURCECFG_LAST 0x0FFC > + > +#define APLIC_SMSICFGADDR 0x1BC8 > +#define APLIC_SMSICFGADDRH 0x1BCC > + > +#define APLIC_SETIP_BASE 0x1C00 > +#define APLIC_SETIP_LAST 0x1C7C > +#define APLIC_SETIPNUM 0x1CDC > + > +#define APLIC_CLRIP_BASE 0x1D00 > +#define APLIC_CLRIP_LAST 0x1D7C > +#define APLIC_CLRIPNUM 0x1DDC > + > +#define APLIC_SETIE_BASE 0x1E00 > +#define APLIC_SETIE_LAST 0x1E7C > +#define APLIC_SETIENUM 0x1EDC > + > +#define APLIC_CLRIE_BASE 0x1F00 > +#define APLIC_CLRIE_LAST 0x1F7C > +#define APLIC_CLRIENUM 0x1FDC > + > +#define APLIC_SETIPNUM_LE 0x2000 > + > +#define APLIC_GENMSI 0x3000 > + > +#define APLIC_TARGET_BASE 0x3004 > +#define APLIC_TARGET_LAST 0x3FFC ... the case of hex digits vs the need to have L (and hence U) suffixes in upper case for Misra's sake. Those suffixes are easier to spot as such when the hex digits use lower case. Then even for un-suffixed numbers lower case is preferable imo, for overall consistency. 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Message-ID: References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="fej7YXlfo2xZKE7n" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-d25034/1775134938-8254FA3D-92A60490/0/0 X-purgate-type: clean X-purgate-size: 9770 --fej7YXlfo2xZKE7n Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 2 Apr 2026 15:02:15 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel , =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-G=C3=B3recki w= rote: > Some further observation, this time regarding timers: In the meantime Roger suggested it might be about C-states. So, I just tried booting with max_cstate=3D0. I got this: [2026-04-02 11:41:57] (XEN) [ 4.327519] mwait-idle: disabled But then xenpm reports C1 is still used: # xenpm get-cpuidle-states=20 Max possible C-state: C0 cpu id : 0 total C-states : 2 idle time(ms) : 3727115 C0 : transition [ 0] residency [ 3769835 ms] C1 : transition [ 0] residency [ 0 ms] cpu id : 1 total C-states : 2 idle time(ms) : 3763654 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769838 ms] cpu id : 2 total C-states : 2 idle time(ms) : 3729168 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769838 ms] cpu id : 3 total C-states : 2 idle time(ms) : 3750226 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769840 ms] cpu id : 4 total C-states : 2 idle time(ms) : 3726369 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769840 ms] cpu id : 5 total C-states : 2 idle time(ms) : 3755733 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769840 ms] cpu id : 6 total C-states : 2 idle time(ms) : 3725747 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769841 ms] cpu id : 7 total C-states : 2 idle time(ms) : 3730190 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769841 ms] cpu id : 8 total C-states : 2 idle time(ms) : 3716485 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769841 ms] cpu id : 9 total C-states : 2 idle time(ms) : 3710830 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769842 ms] cpu id : 10 total C-states : 2 idle time(ms) : 3704881 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769842 ms] cpu id : 11 total C-states : 2 idle time(ms) : 3719333 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769842 ms] cpu id : 12 total C-states : 2 idle time(ms) : 3715059 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769842 ms] cpu id : 13 total C-states : 2 idle time(ms) : 3711681 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769843 ms] cpu id : 14 total C-states : 2 idle time(ms) : 3709380 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769843 ms] cpu id : 15 total C-states : 2 idle time(ms) : 3720119 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769843 ms] cpu id : 16 total C-states : 2 idle time(ms) : 3737637 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769844 ms] cpu id : 17 total C-states : 2 idle time(ms) : 3737662 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769844 ms] cpu id : 18 total C-states : 2 idle time(ms) : 3729870 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769844 ms] cpu id : 19 total C-states : 2 idle time(ms) : 3745564 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769845 ms] cpu id : 20 total C-states : 2 idle time(ms) : 3717089 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769845 ms] cpu id : 21 total C-states : 2 idle time(ms) : 3590257 C0 : transition [ 1] residency [ 0 ms] C1 : transition [ 1] residency [ 3769845 ms] And the issue still happens... Honestly, I'm confused about the above output. The system is mostly idle, but I wouldn't expect it to be _that_ idle - there is xenstored + xenconsoled running, plus occasional xl create for testing with short-lived domU. Does it really all happen only on CPU0 here? --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --fej7YXlfo2xZKE7n Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnOaNcACgkQ24/THMrX 1yyp+AgAj4GAG/xT8PTinO9+JGlXbFwmYWi9ykBHcTslns7tHSyNirLLKjlnA1sP TIboxm6BrjOxHIdpQJK5AXfSGVX2Lms3JFCW1J235h7eKSqh+XxVhYR9hzRNTQBo G1FxX3vd00WMx+AoWC2GCCK124j/Yha5Fw8WRbIC4ba1SkluScUmlCytstUkp+Sj c1GBYjaDgOIn2DXnXVxjSwz2QBb92MpJdMQ+RaICtYEbaXGGIfAd4yaBdIdtIYT+ S3ajEsLVWJ8lMHKWF4ejEaWUpc6rkgVkFzslaLz8Y2eUEIfsfpZ+yl+vrkguflaf KRvz9J5Iab4ZoR0Eh3qBqJnaFihz8Q== =HOe2 -----END PGP SIGNATURE----- --fej7YXlfo2xZKE7n-- From xen-devel-bounces@lists.xenproject.org Thu Apr 02 13:03:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 13:03:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271884.1559878 (Exim 4.92) (envelope-from ) id 1w8Hi0-0001jN-4d; Thu, 02 Apr 2026 13:03:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271884.1559878; Thu, 02 Apr 2026 13:03:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Hi0-0001jG-1e; Thu, 02 Apr 2026 13:03:40 +0000 Received: by outflank-mailman (input) for mailman id 1271884; Thu, 02 Apr 2026 13:03:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Hhy-0001j6-L3 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 13:03:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8Hhy-008CQ1-1C for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 15:03:38 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce6923-5cb7-0a2a0a5109dd-0a2a4504edbe-18 for ; Thu, 02 Apr 2026 15:03:37 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce6929-bb33-0a2a45040019-d155802cc582-3 for ; Thu, 02 Apr 2026 15:03:37 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-486fd3a577eso7607815e9.1 for ; Thu, 02 Apr 2026 06:03:37 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel , =?UTF-8?B?SsO8cmdlbiBHcm8=?= =?UTF-8?B?w58=?= , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1775135017-3373251B-757BA64C/0/0 X-purgate-type: clean X-purgate-size: 502 On 02.04.2026 15:02, Marek Marczykowski-Górecki wrote: > On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-Górecki wrote: >> Some further observation, this time regarding timers: > > In the meantime Roger suggested it might be about C-states. So, I just > tried booting with max_cstate=0. I got this: > > [2026-04-02 11:41:57] (XEN) [ 4.327519] mwait-idle: disabled > > But then xenpm reports C1 is still used: Of course, that represents use of the HLT insn. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0fc9adf790d4f981e8117bd9759c7e64bb11e439.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775135445-83746A3D-F2DA4913/0/0 X-purgate-type: clean X-purgate-size: 1404 On 10.03.2026 18:08, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/aplic.c > +++ b/xen/arch/riscv/aplic.c > @@ -38,6 +38,7 @@ static struct aplic_priv aplic = { > > static struct intc_info __ro_after_init aplic_info = { > .hw_version = INTC_APLIC, > + .private = &aplic, Isn't this the host instance again? How can you ... > --- a/xen/arch/riscv/vaplic.c > +++ b/xen/arch/riscv/vaplic.c > @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, > return 0; > } > > +static int cf_check vaplic_is_access(const struct vcpu *vcpu, > + const unsigned long addr) > +{ > + const struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); > + const struct aplic_priv *priv = vaplic->base.info->private; > + const paddr_t paddr_end = priv->paddr_start + priv->size; > + > + /* check if it is an APLIC access */ > + if ( priv->paddr_start <= addr && addr < paddr_end ) ... use that here? Or asked differently, again: Where's the virtualization, i.e. the abstraction away from host properties? Furthermore, is it really sufficient to check just the starting address of an access? Shouldn't the last byte accessed also fall into the range in question? > + return 1; > + > + return 0; > +} This function looks to want to return bool (and then use true/false). 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> >> } > >> > >> -void __iomem *ioremap(paddr_t pa, size_t len) > >> +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > >> { > >> - mfn_t mfn = _mfn(PFN_DOWN(pa)); > >> - void *va; > >> - > >> - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > >> + WARN_ON(page_is_ram_type(PFN_DOWN(pa), RAM_TYPE_CONVENTIONAL)); > >> > >> /* The low first Mb is always mapped. */ > >> - if ( !((pa + len - 1) >> 20) ) > >> - va = __va(pa); > >> - else > >> - { > >> - unsigned int offs = pa & (PAGE_SIZE - 1); > >> - unsigned int nr = PFN_UP(offs + len); > >> - > >> - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_UCMINUS, VMAP_DEFAULT); > >> - if ( va ) > >> - va += offs; > >> - } > >> - > >> - return (void __force __iomem *)va; > >> -} > >> - > >> -void __iomem *__init ioremap_wc(paddr_t pa, size_t len) > >> -{ > >> - mfn_t mfn = _mfn(PFN_DOWN(pa)); > >> - unsigned int offs = pa & (PAGE_SIZE - 1); > >> - unsigned int nr = PFN_UP(offs + len); > >> - void *va; > >> - > >> - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); > >> - > >> - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_WC, VMAP_DEFAULT); > >> + if ( !((pa + len - 1) >> 20) && attr == PAGE_HYPERVISOR_UCMINUS ) > >> + return (void __force __iomem *)__va(pa); > > > > Sorry, I'm possibly a bit lost: I see that on the bootstrap > > page-tables we map the VGA hole (0xa0000-0xc0000) as UC-, but I'm not > > seeing this being done to the directmap? > > I'm not changing that aspect here, do I? ioremap() used the direct map > (apparently assuming the cache attribute is suitable), and so do I now. > > Yet then, to address the point you make anyway, I certainly see use of > __PAGE_HYPERVISOR_UCMINUS in l1_directmap[]. Yes, sorry, I know you are not adding this here. Just took a look at the code, and I couldn't find where the directmap entries for the low 1M get adjusted to use UC-. I should have made the comment clearer. > >> --- /dev/null > >> +++ b/xen/common/ioremap.c > >> @@ -0,0 +1,42 @@ > >> +/* SPDX-License-Identifier: GPL-2.0-only */ > >> + > >> +#include > >> +#include > >> +#include > >> + > >> +#include > >> + > >> +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) > >> +{ > >> + void __iomem *ptr = NULL; > >> + unsigned int offs = PAGE_OFFSET(pa); > >> + > >> +#ifdef arch_ioremap_attr > >> + ptr = arch_ioremap_attr(pa, len, attr); > >> + if ( PAGE_OFFSET(ptr) ) > >> + return ptr; > > > > IMO it's a bit confusing to deal with the offset addition detached > > form here, I would rather do: > > > > if ( ptr != NULL ) > > { > > ASSERT(PAGE_OFFSET(ptr) == offs); > > return PAGE_OFFSET(ptr) ? ptr : ptr + off; > > } > > > > And get rid of the !ptr check in the if below. So that when > > arch_ioremap_attr() succeeds it's all dealt with in the #ifdef > > protected block. > > Possible, yet I deemed the other variant better. OK, I'm not going to insist then. It just took me a bit to notice the extra !ptr check in the if condition below. > The assertion you suggest isn't valid anyway (see the last sentence of the > description and xen/arch/arm/mpu/mm.c:ioremap_attr() prior to Michal's > "xen/arm: mpu: Fix ioremap_attr region size and return value"). Now that > that's changing, things may indeed be possible to simplify here. Oh, I see, right you are. It should be: ASSERT(!PAGE_OFFSET(ptr) || PAGE_OFFSET(ptr) == offs); Thanks, Roger. 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ZeCWVrsmPc3PCgY3" Content-Disposition: inline In-Reply-To: <0b284c32-4dd3-4663-881b-834c47070328@suse.com> X-purgate-ID: tlsNG-42698a/1775138530-EF9412A1-A3C9AF4F/0/0 X-purgate-type: clean X-purgate-size: 5075 --ZeCWVrsmPc3PCgY3 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 2 Apr 2026 16:02:06 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: Andrew Cooper , xen-devel , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: IOMMU faults after S3 On Thu, Apr 02, 2026 at 12:23:08PM +0200, Jan Beulich wrote: > On 02.04.2026 11:42, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Apr 02, 2026 at 10:47:53AM +0200, Jan Beulich wrote: > >> On 02.04.2026 10:39, Jan Beulich wrote: > >>> On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > >>>> The xl dmesg output (from MTL this time): > >>>> > >>>> (XEN) [ 123.477511] Entering ACPI S3 state. > >>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, = cpu_has_apic: 1 > >>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_= deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >>> > >>> XEN_ARAT being off is the one odd aspect here. That'll want tracking = down > >>> separately. As per xen-cpuid output (below) ARAT is available. > >> > >> For this you may want to also add logging to intel_init_arat(): Since = opt_arat > >> can be false only due to command line option use, it can only be the f= unction > >> not being called (which looks impossible on plain staging code), or cp= u_has_arat > >> being false despite the xen-cpuid output that you supplied earlier (in= explicable > >> as well, at least for now). > >=20 > > Hm, I got this: > >=20 > > (XEN) [ 11.403340] intel_init_arat:674: opt_arat: 1, cpu_has_arat= : 0 > >=20 > > so, cpu_has_arat=3D0 ... > > next lines are those, to hint when it happened in the boot process: > >=20 > > (XEN) [ 11.409754] mwait-idle: MWAIT substates: 0x11112020 > > (XEN) [ 11.416130] mwait-idle: v0.4.1 model 0xaa > > (XEN) [ 11.422396] mwait-idle: lapic_timer_reliable_states 0x2 > >=20 > > Looks like calculate_host_policy() runs much later... >=20 > Hmm, yes, and that's the problem. The reason I don't see this is that a n= ewer > version of [1] has this > > --- a/xen/arch/x86/cpu/common.c > +++ b/xen/arch/x86/cpu/common.c > @@ -628,6 +628,8 @@ void identify_cpu(struct cpuinfo_x86 *c) > } > =20 > /* Now the feature flags better reflect actual CPU features! */ > + if (c =3D=3D &boot_cpu_data) > + calculate_host_policy(); > =20 > xstate_init(c); > =20 > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -384,7 +384,7 @@ void calculate_raw_cpu_policy(void) > /* Was already added by probe_cpuid_faulting() */ > } > =20 > -static void __init calculate_host_policy(void) > +void __init calculate_host_policy(void) > { > struct cpu_policy *p =3D &host_cpu_policy; > =20 > @@ -959,6 +959,7 @@ static void __init calculate_hvm_def_pol > =20 > void __init init_guest_cpu_policies(void) > { > + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() u= ses. */ > calculate_host_policy(); > =20 > if ( IS_ENABLED(CONFIG_PV) ) >=20 > and of course I'm doing my work (and my analysis) with that in place. FWIW, with this patch applied I get: (XEN) [18446743899.051851] _disable_pit_irq:2649: using_pit: 0, cpu_has_api= c: 1 (XEN) [18446743899.051865] _disable_pit_irq:2659: cpuidle_using_deep_cstate= : 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 1 And no IOMMU faults anymore. > I may need to break this out and submit independently, but really the pro= blem > here is that the containing series has been sitting largely unreviewed (a= nd > hence not in a position to plausibly re-post) for almost 5 years. Andrew, > (maybe also Roger) - I'm open to suggestions how to proceed. When your xs= tate > cleanup patches were helped to go in ahead of mine, you promised to help = mine > going in afterwards. Yet nothing has happened (and I'm tired of re-submit= ting > large pieces of work just for the sake of re-submitting, i.e. without hav= ing > has [sufficient] feedback on the earlier version). >=20 > Jan >=20 > [1] https://lists.xen.org/archives/html/xen-devel/2021-04/msg01336.html --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --ZeCWVrsmPc3PCgY3 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnOdt4ACgkQ24/THMrX 1yzHWggAhjmKXWAUnZLU2gP7Hf9Muj88OfxSbxUvk9QJGkt/LHnn9BWFw/Af5Vzd 2cb3s0Bhh3dNhZQCF7/Bqz2B1Ih3q8jH8x3pijIb3h5tBmenJadyPW58WEdSqZxg 7m6P7QUQkqQHNrzn/WTbIckUleDipk9Zxwqjhi1RKXZJBYmYabKMskdvd7A1t9of jMlNIV1dQQIyRIhWMXAo3NzSnqRTykA//aMWXtsbGz2Yl4+PmdV8vV9aMAgUJVC9 xnnRQkbSGHDhVX2Lr/7AH2B8wvwFP5P+EDqcsvNpvHFvhbfLyLZZMe8C0eXCQ/p9 11aOidTUEDwE+q/RUN9MD4ClXDCmqQ== =Rg5l -----END PGP SIGNATURE----- --ZeCWVrsmPc3PCgY3-- From xen-devel-bounces@lists.xenproject.org Thu Apr 02 14:19:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 14:19:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1271988.1559922 (Exim 4.92) (envelope-from ) id 1w8Isq-0004FR-EO; Thu, 02 Apr 2026 14:18:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1271988.1559922; Thu, 02 Apr 2026 14:18:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Isq-0004FK-BK; Thu, 02 Apr 2026 14:18:56 +0000 Received: by outflank-mailman (input) for mailman id 1271988; Thu, 02 Apr 2026 14:18:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Isp-0004FE-52 for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 14:18:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8Iso-006i0p-HZ for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 16:18:54 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce7ab5-2eae-0a2a0a5409dd-0a2a450bebea-44 for ; Thu, 02 Apr 2026 16:18:54 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce7ace-bca8-0a2a450b0019-d155802fa845-3 for ; Thu, 02 Apr 2026 16:18:54 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-482f454be5bso22003065e9.0 for ; Thu, 02 Apr 2026 07:18:54 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775139534-F4BCA2A1-0F354E63/0/0 X-purgate-type: clean X-purgate-size: 8616 On 10.03.2026 18:08, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/vaplic.c > +++ b/xen/arch/riscv/vaplic.c > @@ -20,6 +20,16 @@ > > #include "aplic-priv.h" > > +#define APLIC_REG_GET(addr, offset) \ > + readl((void *)((vaddr_t)(addr) + offset)) > +#define APLIC_REG_SET(addr, offset, value) \ > + writel(value, (void *)((vaddr_t)(addr) + offset)) Why is addr properly parenthesized, but offset isn't? > +#define AUTH_IRQ_BIT(irqnum) (auth_irq_bmp[(irqnum) / APLIC_NUM_REGS] & \ > + BIT((irqnum) % APLIC_NUM_REGS, U)) > + > +#define regval_to_irqn(reg_val) ((reg_val) / sizeof(uint32_t)) I'm trying to make sense of the division here, but I think the main issue is with naming: It's not a "register value" which is passed into here, but a register index (offset from a range's base register). > @@ -127,6 +137,164 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, > return 0; > } > > +static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t *iprio) > +{ > + *iprio &= APLIC_TARGET_IPRIO_MASK; > + *iprio |= (hart_id << APLIC_TARGET_HART_IDX_SHIFT); > +} > + > +static void vaplic_update_target(const struct imsic_config *imsic, > + const int guest_id, > + const unsigned long hart_id, uint32_t *value) > +{ > + unsigned long group_index; > + unsigned int hhxw = imsic->group_index_bits; > + unsigned int lhxw = imsic->hart_index_bits; > + unsigned int hhxs = imsic->group_index_shift - IMSIC_MMIO_PAGE_SHIFT * 2; > + unsigned long base_ppn = imsic->msi[hart_id].base_addr >> IMSIC_MMIO_PAGE_SHIFT; > + > + group_index = (base_ppn >> (hhxs + 12)) & (BIT(hhxw, UL) - 1); And there's no constant available to make this literal 12 more descriptive? > + *value &= APLIC_TARGET_EIID_MASK; > + *value |= guest_id << APLIC_TARGET_GUEST_IDX_SHIFT; > + *value |= hart_id << APLIC_TARGET_HART_IDX_SHIFT; > + *value |= group_index << (lhxw + APLIC_TARGET_HART_IDX_SHIFT) ; > +} Both functions returning void right now, why would they need to return their result via indirection? > +#define CALC_REG_VALUE(base) \ > +{ \ > + uint32_t index; \ > + uint32_t tmp_val; \ Combine these two, or have the variables have initializers? > + index = regval_to_irqn(offset - base); \ There's no "offset" declared or passed into here, nor ... > + tmp_val = APLIC_REG_GET(priv->regs, aplic_addr) & ~auth_irq_bmp[index]; \ ... "priv", nor ... > + value &= auth_irq_bmp[index]; \ > + value |= tmp_val; \ ... "value". It may remain like this, but then it wants putting inside the sole function that uses it, and be #undef-ed at the end of the function. > +} Please wrap in do/while(0), for use sites to be required to have semicolons (and hence look like normal statements). Or make it a statement expression properly returning the calculated value. > +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, > + unsigned long addr, uint32_t value) > +{ > + struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); > + struct aplic_priv *priv = vaplic->base.info->private; > + uint32_t offset = addr & APLIC_REG_OFFSET_MASK; See ./CODING_STYLE as to uses of fixed-width types. > + unsigned long aplic_addr = addr - priv->paddr_start; > + const uint32_t *auth_irq_bmp = vcpu->domain->arch.vintc->private; > + > + switch ( offset ) > + { > + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: And (taking this just as example) any misaligned accesses falling in this range are fine? > + CALC_REG_VALUE(APLIC_SETIP_BASE); > + break; > + > + case APLIC_CLRIP_BASE ... APLIC_CLRIP_LAST: > + CALC_REG_VALUE(APLIC_CLRIP_BASE); > + break; > + > + case APLIC_SETIE_BASE ... APLIC_SETIE_LAST: > + CALC_REG_VALUE(APLIC_SETIE_BASE); > + break; > + > + case APLIC_CLRIE_BASE ... APLIC_CLRIE_LAST: > + CALC_REG_VALUE(APLIC_CLRIE_BASE); > + break; > + > + case APLIC_SOURCECFG_BASE ... APLIC_SOURCECFG_LAST: > + /* We don't suppert delagation, so bit10 if sourcecfg should be 0 */ > + ASSERT(!(value & BIT(10, U))); And that bit doesn't have a proper #define? > + /* > + * As sourcecfg register starts from 1: > + * 0x0000 domaincfg > + * 0x0004 sourcecfg[1] > + * 0x0008 sourcecfg[2] > + * ... > + * 0x0FFC sourcecfg[1023] > + * It is necessary to calculate an interrupt number by substracting Nit: subtracting > + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. > + */ > + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) > + /* interrupt not enabled, ignore it */ Throughout the series: Please adhere to ./CODING_STYLE. > + return 0; > + > + break; And any value is okay to write? > + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: > + struct vcpu *target_vcpu = NULL; > + > + /* > + * Look at vaplic_emulate_load() for explanation why > + * APLIC_GENMSI is substracted. > + */ There's no vaplic_emulate_load() - how can I go look there? Also same typo again as above. > + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) > + /* interrupt not enabled, ignore it */ > + return 0; > + > + for ( int i = 0; i < vcpu->domain->max_vcpus; i++ ) unsigned int > + { > + struct vcpu *v = vcpu->domain->vcpu[i]; > + > + if ( v->vcpu_id == (value >> APLIC_TARGET_HART_IDX_SHIFT) ) > + { > + target_vcpu = v; > + break; > + } > + } > + > + ASSERT(target_vcpu); What guarantees the pointer to be non-NULL? The incoming value can be arbitrary, afaict. > + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) > + { > + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor), > + &value); > + } > + else > + vaplic_update_target(priv->imsic_cfg, > + vcpu_guest_file_id(target_vcpu), > + cpuid_to_hartid(target_vcpu->processor), > + &value); I'm struggling with the naming here: When DM is clear, a function with "dm" in the name is called. For the latter one, unless other uses are intended speaking against that, instead of the middle two arguments simply pass target_vcpu? Also please omit the braces consistently from both branches. > + break; > + > + case APLIC_SETIPNUM: > + case APLIC_SETIPNUM_LE: What about APLIC_SETIPNUM_BE? > + case APLIC_CLRIPNUM: > + case APLIC_SETIENUM: > + case APLIC_CLRIENUM: > + if ( AUTH_IRQ_BIT(value) ) > + break; Aren't you easily overrunning auth_irq_bmp[] here? > + return 0; > + > + case APLIC_DOMAINCFG: > + /* > + * TODO: > + * The domaincfg register has this format: > + * bits 31:24 read-only 0x80 > + * bit 8 IE > + * bit 7 read-only 0 > + * bit 2 DM (WARL) > + * bit 0 BE (WARL) > + * > + * The most interesting bit for us is IE(Interrupt Enable) bit. > + * At the moment, at least, Linux doesn't use domaincfg.IE bit to > + * disable interrupts globally, but if one day someone will use it > + * then extra actions should be done. > + */ > + > + printk_once("%s: Nothing to do, domaincfg is set by aplic during " > + "initialization in Xen\n", __func__); As per the comment it's not "nothing to do", but your choice to ignore writes even if they may be relevant. > + return 0; > + > + default: > + panic("%s: unsupported register offset: %#x\n", __func__, offset); Crashing the host for the guest doing something odd? It's odd that the function only ever returns 0 anyway - it could simply return an error here (if the itention is to not ignore such writes). As it's not clear what values other than zero such a function may return, I also can't comment on its (and the hook's) return type (may want to be bool instead of int). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775139792-2272296F-242D17DB/0/0 X-purgate-type: clean X-purgate-size: 3379 On 02.04.2026 16:02, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 12:23:08PM +0200, Jan Beulich wrote: >> On 02.04.2026 11:42, Marek Marczykowski-Górecki wrote: >>> On Thu, Apr 02, 2026 at 10:47:53AM +0200, Jan Beulich wrote: >>>> On 02.04.2026 10:39, Jan Beulich wrote: >>>>> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>>>>> The xl dmesg output (from MTL this time): >>>>>> >>>>>> (XEN) [ 123.477511] Entering ACPI S3 state. >>>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>>>> >>>>> XEN_ARAT being off is the one odd aspect here. That'll want tracking down >>>>> separately. As per xen-cpuid output (below) ARAT is available. >>>> >>>> For this you may want to also add logging to intel_init_arat(): Since opt_arat >>>> can be false only due to command line option use, it can only be the function >>>> not being called (which looks impossible on plain staging code), or cpu_has_arat >>>> being false despite the xen-cpuid output that you supplied earlier (inexplicable >>>> as well, at least for now). >>> >>> Hm, I got this: >>> >>> (XEN) [ 11.403340] intel_init_arat:674: opt_arat: 1, cpu_has_arat: 0 >>> >>> so, cpu_has_arat=0 ... >>> next lines are those, to hint when it happened in the boot process: >>> >>> (XEN) [ 11.409754] mwait-idle: MWAIT substates: 0x11112020 >>> (XEN) [ 11.416130] mwait-idle: v0.4.1 model 0xaa >>> (XEN) [ 11.422396] mwait-idle: lapic_timer_reliable_states 0x2 >>> >>> Looks like calculate_host_policy() runs much later... >> >> Hmm, yes, and that's the problem. The reason I don't see this is that a newer >> version of [1] has this >> >> --- a/xen/arch/x86/cpu/common.c >> +++ b/xen/arch/x86/cpu/common.c >> @@ -628,6 +628,8 @@ void identify_cpu(struct cpuinfo_x86 *c) >> } >> >> /* Now the feature flags better reflect actual CPU features! */ >> + if (c == &boot_cpu_data) >> + calculate_host_policy(); >> >> xstate_init(c); >> >> --- a/xen/arch/x86/cpu-policy.c >> +++ b/xen/arch/x86/cpu-policy.c >> @@ -384,7 +384,7 @@ void calculate_raw_cpu_policy(void) >> /* Was already added by probe_cpuid_faulting() */ >> } >> >> -static void __init calculate_host_policy(void) >> +void __init calculate_host_policy(void) >> { >> struct cpu_policy *p = &host_cpu_policy; >> >> @@ -959,6 +959,7 @@ static void __init calculate_hvm_def_pol >> >> void __init init_guest_cpu_policies(void) >> { >> + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() uses. */ >> calculate_host_policy(); >> >> if ( IS_ENABLED(CONFIG_PV) ) >> >> and of course I'm doing my work (and my analysis) with that in place. > > FWIW, with this patch applied I get: > (XEN) [18446743899.051851] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743899.051865] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 1 > > And no IOMMU faults anymore. Right, because then - as intended - HPET broadcast isn't used. You'd see them again if you put "no-arat" on the command line. (And we really want to figure out that issue, if at all possible.) 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ISpOtCzGrGc4UBsj" Content-Disposition: inline In-Reply-To: <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> X-purgate-ID: tlsNG-d62444/1775141254-168F4185-1F0BEAB7/0/0 X-purgate-type: clean X-purgate-size: 14224 --ISpOtCzGrGc4UBsj Content-Type: multipart/mixed; protected-headers=v1; boundary="XVDyUL3T4K294TsS" Content-Disposition: inline Date: Thu, 2 Apr 2026 16:47:31 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 --XVDyUL3T4K294TsS Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 02, 2026 at 12:48:14PM +0200, Jan Beulich wrote: > On 02.04.2026 11:35, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: > >> On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > >>> The xl dmesg output (from MTL this time): > >>> > >>> (XEN) [ 123.477511] Entering ACPI S3 state. > >>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, c= pu_has_apic: 1 > >>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_d= eep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >=20 > >> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually > >> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() val= ues > >> might be a good idea, if only to double check.) > >=20 > > Updated output: > >=20 > > (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, cpu= _has_apic: 1 > > (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_dee= p_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > > (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 > > (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events: = ffff83046bc1f080 > > (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_use= d: 8 > > (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 > > (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_eve= nts[i].msi.irq: 122, hpet_events[i].flags: 0 > > (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 (i= ommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 > > (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_fro= m_msi rc: 0 >=20 > So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausible. T= he high > half is, however, the address that the low half value is written to. It's= hard > to imagine that it would be zero when the low half isn't, but it is about= the > last thing I can think of which could explain observed behavior. (Yet the= n, all > of this is pretty meaningless; see below.) >=20 > > And the current debug diff attached. >=20 > Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very useful. Y= ou want > to move that part of logging to the bottom of hpet_msi_write(), or maybe = to > where you also log the per-channel cfg value in hpet_broadcast_resume() (= thus > making the logging overall less verbose). This test is with the updated patch (attached) + your extra calculate_host_policy() call and "no-arat" on cmdline: (XEN) [18446743900.569705] _disable_pit_irq:2649: using_pit: 0, cpu_has= _apic: 1 (XEN) [18446743900.569720] _disable_pit_irq:2659: cpuidle_using_deep_cs= tate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 (XEN) [18446743900.569730] _disable_pit_irq:2662: init: 0 (XEN) [18446743900.569741] hpet_broadcast_resume:662: hpet_events: ffff= 83046bc1f080 (XEN) [18446743900.569885] hpet_broadcast_resume:673: num_hpets_used: 8 (XEN) [18446743900.569893] hpet_broadcast_resume:691: cfg: 0x1 (XEN) [18446743900.569905] hpet_broadcast_resume:696: i:0, hpet_events[= i].msi.irq: 122, hpet_events[i].flags: 0 (XEN) [18446743900.569935] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.569946] hpet_broadcast_resume:700: i:0, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.569970] hpet_broadcast_resume:710: i:0, cfg: 0xc134,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x110 (XEN) [18446743900.569980] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x110 (XEN) [18446743900.569989] hpet_broadcast_resume:696: i:1, hpet_events[= i].msi.irq: 123, hpet_events[i].flags: 0 (XEN) [18446743900.570012] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570022] hpet_broadcast_resume:700: i:1, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570040] hpet_broadcast_resume:710: i:1, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x130 (XEN) [18446743900.570050] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x130 (XEN) [18446743900.570059] hpet_broadcast_resume:696: i:2, hpet_events[= i].msi.irq: 124, hpet_events[i].flags: 0 (XEN) [18446743900.570082] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570092] hpet_broadcast_resume:700: i:2, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570105] hpet_broadcast_resume:710: i:2, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x150 (XEN) [18446743900.570114] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x150 (XEN) [18446743900.570123] hpet_broadcast_resume:696: i:3, hpet_events[= i].msi.irq: 125, hpet_events[i].flags: 0 (XEN) [18446743900.570145] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570155] hpet_broadcast_resume:700: i:3, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570172] hpet_broadcast_resume:710: i:3, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x170 (XEN) [18446743900.570181] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x170 (XEN) [18446743900.570191] hpet_broadcast_resume:696: i:4, hpet_events[= i].msi.irq: 126, hpet_events[i].flags: 0 (XEN) [18446743900.570214] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570225] hpet_broadcast_resume:700: i:4, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570242] hpet_broadcast_resume:710: i:4, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x190 (XEN) [18446743900.570251] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x190 (XEN) [18446743900.570260] hpet_broadcast_resume:696: i:5, hpet_events[= i].msi.irq: 127, hpet_events[i].flags: 0 (XEN) [18446743900.570282] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570292] hpet_broadcast_resume:700: i:5, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570309] hpet_broadcast_resume:710: i:5, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x1b0 (XEN) [18446743900.570318] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x1b0 (XEN) [18446743900.570327] hpet_broadcast_resume:696: i:6, hpet_events[= i].msi.irq: 128, hpet_events[i].flags: 0 (XEN) [18446743900.570351] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570361] hpet_broadcast_resume:700: i:6, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570374] hpet_broadcast_resume:710: i:6, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x1d0 (XEN) [18446743900.570383] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x1d0 (XEN) [18446743900.570392] hpet_broadcast_resume:696: i:7, hpet_events[= i].msi.irq: 129, hpet_events[i].flags: 0 (XEN) [18446743900.570415] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 (XEN) [18446743900.570425] hpet_broadcast_resume:700: i:7, __hpet_setup= _msi_irq ret: 0 (XEN) [18446743900.570442] hpet_broadcast_resume:710: i:7, cfg: 0xc104,= HPET_Tn_ROUTE(hpet_events[i].idx): 0x1f0 (XEN) [18446743900.570451] hpet_broadcast_resume:713: HPET_Tn_ROUTE(hpe= t_events[i].idx): 0x1f0 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --XVDyUL3T4K294TsS Content-Type: text/plain; charset=utf-8 Content-Disposition: attachment; filename=0001-DEBUG.patch Content-Transfer-Encoding: quoted-printable =46rom 34e6a34cf0504233776337ace8ac69a92297984e Mon Sep 17 00:00:00 2001 =46rom: =3D?UTF-8?q?Marek=3D20Marczykowski-G=3DC3=3DB3recki?=3D Date: Thu, 2 Apr 2026 11:09:32 +0200 Subject: [PATCH] DEBUG --- xen/arch/x86/cpu-policy.c | 1 + xen/arch/x86/cpu/intel.c | 1 + xen/arch/x86/hpet.c | 17 ++++++++++++++++- xen/arch/x86/time.c | 3 +++ xen/source | 1 + 5 files changed, 22 insertions(+), 1 deletion(-) create mode 120000 xen/source diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae435..9916afd5ed68 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -364,6 +364,7 @@ static void __init calculate_host_policy(void) struct cpu_policy *p =3D &host_cpu_policy; unsigned int max_extd_leaf; =20 + printk("%s:%d\n", __func__, __LINE__); *p =3D raw_cpu_policy; =20 p->basic.max_leaf =3D diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 18b3c79dc97f..51a3d1c4b5f3 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -671,6 +671,7 @@ const struct cpu_dev __initconst_cf_clobber intel_cpu_d= ev =3D { =20 void __init intel_init_arat(void) { + printk("%s:%d: opt_arat: %d, cpu_has_arat: %d\n", __func__, __LINE__, = opt_arat, cpu_has_arat); if ( opt_arat && cpu_has_arat ) setup_force_cpu_cap(X86_FEATURE_XEN_ARAT); } diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c index 1ea8ae457424..cef060cb18bb 100644 --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -283,6 +283,7 @@ static int hpet_msi_write(struct hpet_event_channel *ch= , struct msi_msg *msg) if ( iommu_intremap !=3D iommu_intremap_off ) { int rc =3D iommu_update_ire_from_msi(&ch->msi, msg); + printk("%s:%d: iommu_update_ire_from_msi rc: %d\n", __func__, __LI= NE__, rc); =20 if ( rc < 0 ) return rc; @@ -658,6 +659,8 @@ void hpet_broadcast_resume(void) u32 cfg; unsigned int i, n; =20 + printk("%s:%d: hpet_events: %p\n", __func__, __LINE__, hpet_events); + if ( !hpet_events ) return; =20 @@ -667,25 +670,35 @@ void hpet_broadcast_resume(void) =20 if ( num_hpets_used > 0 ) { + printk("%s:%d: num_hpets_used: %d\n", __func__, __LINE__, num_hpet= s_used); /* Stop HPET legacy interrupts */ cfg &=3D ~HPET_CFG_LEGACY; n =3D num_hpets_used; } else if ( hpet_events->flags & HPET_EVT_DISABLE ) + { + printk("%s:%d: hpet_events->flags: %#x\n", __func__, __LINE__, hpe= t_events->flags); return; + } else { /* Start HPET legacy interrupts */ + printk("%s:%d\n", __func__, __LINE__); cfg |=3D HPET_CFG_LEGACY; n =3D 1; } =20 + printk("%s:%d: cfg: %#x\n", __func__, __LINE__, cfg); hpet_write32(cfg, HPET_CFG); =20 for ( i =3D 0; i < n; i++ ) { + printk("%s:%d: i:%d, hpet_events[i].msi.irq: %d, hpet_events[i].fl= ags: %#x\n", __func__, __LINE__, i, hpet_events[i].msi.irq, hpet_events[i].= flags); if ( hpet_events[i].msi.irq >=3D 0 ) - __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); + { + int ret =3D __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].ms= i.irq)); + printk("%s:%d: i:%d, __hpet_setup_msi_irq ret: %d\n", __func__= , __LINE__, i, ret); + } =20 /* set HPET Tn as oneshot */ cfg =3D hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); @@ -694,8 +707,10 @@ void hpet_broadcast_resume(void) if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) cfg |=3D HPET_TN_FSB; hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); + printk("%s:%d: i:%d, cfg: %#x, HPET_Tn_ROUTE(hpet_events[i].idx): = %#x\n", __func__, __LINE__, i, cfg, HPET_Tn_ROUTE(hpet_events[i].idx)); =20 hpet_events[i].next_event =3D STIME_MAX; + printk("%s:%d: HPET_Tn_ROUTE(hpet_events[i].idx): %#x\n", __func__= , __LINE__, HPET_Tn_ROUTE(hpet_events[i].idx)); } } =20 diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index fed30a919d2c..15113ebdfb6c 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2646,6 +2646,7 @@ static int _disable_pit_irq(bool init) { int ret =3D 1; =20 + printk("%s:%d: using_pit: %d, cpu_has_apic: %d\n", __func__, __LINE__,= using_pit, cpu_has_apic); if ( using_pit || !cpu_has_apic ) return -1; =20 @@ -2655,8 +2656,10 @@ static int _disable_pit_irq(bool init) * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast. */ + printk("%s:%d: cpuidle_using_deep_cstate: %d, boot_cpu_has(X86_FEATURE= _XEN_ARAT): %d\n", __func__, __LINE__, cpuidle_using_deep_cstate(), boot_cp= u_has(X86_FEATURE_XEN_ARAT)); if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT= ) ) { + printk("%s:%d: init: %d\n", __func__, __LINE__, init); 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Thu, 02 Apr 2026 07:53:33 -0700 (PDT) Message-ID: <92e0151b-3fb1-4108-9788-f0fbac43512b@suse.com> Date: Thu, 2 Apr 2026 16:53:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1775141613-B62E9185-6D6F6108/0/0 X-purgate-type: clean X-purgate-size: 2778 On 02.04.2026 16:47, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 12:48:14PM +0200, Jan Beulich wrote: >> On 02.04.2026 11:35, Marek Marczykowski-Górecki wrote: >>> On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: >>>> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>>>> The xl dmesg output (from MTL this time): >>>>> >>>>> (XEN) [ 123.477511] Entering ACPI S3 state. >>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>> >>>> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually >>>> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() values >>>> might be a good idea, if only to double check.) >>> >>> Updated output: >>> >>> (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>> (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>> (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 >>> (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events: ffff83046bc1f080 >>> (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_used: 8 >>> (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 >>> (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 >>> (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 (iommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 >>> (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_from_msi rc: 0 >> >> So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausible. The high >> half is, however, the address that the low half value is written to. It's hard >> to imagine that it would be zero when the low half isn't, but it is about the >> last thing I can think of which could explain observed behavior. (Yet then, all >> of this is pretty meaningless; see below.) >> >>> And the current debug diff attached. >> >> Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very useful. You want >> to move that part of logging to the bottom of hpet_msi_write(), or maybe to >> where you also log the per-channel cfg value in hpet_broadcast_resume() (thus >> making the logging overall less verbose). > > This test is with the updated patch (attached) + your extra > calculate_host_policy() call and "no-arat" on cmdline: And IOMMU faults still occurring as before, I expect. Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you don't log the high halves at all. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 02 14:58:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 14:58:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272063.1559959 (Exim 4.92) (envelope-from ) id 1w8JUz-0002g1-7Z; Thu, 02 Apr 2026 14:58:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272063.1559959; Thu, 02 Apr 2026 14:58:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8JUz-0002fu-4B; Thu, 02 Apr 2026 14:58:21 +0000 Received: by outflank-mailman (input) for mailman id 1272063; Thu, 02 Apr 2026 14:58:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8JUy-0002fo-3p for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 14:58:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8JUx-005QZB-Gd for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 16:58:19 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce8405-2eae-0a2a0a5409dd-0a2a4506df86-20 for ; Thu, 02 Apr 2026 16:58:19 +0200 Received: from [209.85.221.41] (helo=mail-wr1-f41.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce840b-0df0-0a2a45060019-d155dd29a936-3 for ; Thu, 02 Apr 2026 16:58:19 +0200 Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-43cf3ee0fc1so1527574f8f.1 for ; Thu, 02 Apr 2026 07:58:19 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775141899-5C9223D8-47B1F03A/0/0 X-purgate-type: clean X-purgate-size: 729 On 10.03.2026 18:08, Oleksii Kurochko wrote: > @@ -96,4 +97,7 @@ void intc_handle_external_irqs(struct cpu_user_regs *regs); > > int intc_make_domu_dt_node(const struct kernel_info *kinfo); > > +int domain_vintc_init(struct domain *d); > +void domain_vintc_deinit(struct domain *d); The former has a caller added, but the later hasn't. > @@ -87,3 +88,42 @@ int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, > return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, > irq_ranges); > } > + > +int __init domain_vintc_init(struct domain *d) The __init here and below is questionable again. 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Additionally, before do_initcalls() call > scheduler_init() which is needed because of cpupool_create_pool() > is called by do_initcalls(); otherwise BUG_ON(IS_ERR(pool)) will occur > in inside cpupool_create_pool(). > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Thu Apr 02 15:03:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 15:03:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272094.1559986 (Exim 4.92) (envelope-from ) id 1w8JZl-0005Dl-AD; Thu, 02 Apr 2026 15:03:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272094.1559986; Thu, 02 Apr 2026 15:03:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8JZl-0005De-7L; Thu, 02 Apr 2026 15:03:17 +0000 Received: by outflank-mailman (input) for mailman id 1272094; Thu, 02 Apr 2026 15:03:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w8JZj-0005DP-Fd for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 15:03:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8JZi-002R86-SB for xen-devel@lists.xenproject.org; Thu, 02 Apr 2026 17:03:14 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ce852f-2eae-0a2a0a5409dd-0a2a4507a756-10 for ; Thu, 02 Apr 2026 17:03:14 +0200 Received: from [209.85.218.41] (helo=mail-ej1-f41.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69ce8532-ba2d-0a2a45070019-d155da29f04a-3 for ; Thu, 02 Apr 2026 17:03:14 +0200 Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-b7cf4a975d2so126686366b.2 for ; Thu, 02 Apr 2026 08:03:14 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Jan > --- a/xen/arch/riscv/setup.c > +++ b/xen/arch/riscv/setup.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -154,6 +155,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, > > timer_init(); > > + rcu_init(); > + > local_irq_enable(); > > console_init_postirq(); From xen-devel-bounces@lists.xenproject.org Thu Apr 02 15:52:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 15:52:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272143.1559994 (Exim 4.92) (envelope-from ) id 1w8KLI-0003OW-N7; Thu, 02 Apr 2026 15:52:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272143.1559994; Thu, 02 Apr 2026 15:52:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8KLI-0003OP-KQ; Thu, 02 Apr 2026 15:52:24 +0000 Received: by outflank-mailman (input) for mailman id 1272143; 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Factor out a function to check ELF notes and reuse it even for PVH. Signed-off-by: Frediano Ziglio -- Changes since v1: - fix typo in title; - fix minor formatting issue; - use is_hardware_domain instead of checking is_pv_shim; - reduce indentation returning earlier; - return error instead of jumping to cleanup code. --- xen/arch/x86/dom0_build.c | 14 ++++++++++++++ xen/arch/x86/hvm/dom0_build.c | 3 +++ xen/arch/x86/include/asm/dom0_build.h | 2 ++ xen/arch/x86/pv/dom0_build.c | 10 ++-------- 4 files changed, 21 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c index 864dd9e53e..a33ce77321 100644 --- a/xen/arch/x86/dom0_build.c +++ b/xen/arch/x86/dom0_build.c @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); } +int __init dom0_check_parms( + struct domain *d, const struct elf_dom_parms *parms) +{ + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) + return 0; + + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) + { + printk("Kernel does not support Dom0 operation\n"); + return -EINVAL; + } + + return 0; +} /* * If allocation isn't specified, reserve 1/16th of available memory for diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c index d69a83b089..f95a00acfd 100644 --- a/xen/arch/x86/hvm/dom0_build.c +++ b/xen/arch/x86/hvm/dom0_build.c @@ -699,6 +699,9 @@ static int __init pvh_load_kernel( if ( !check_and_adjust_load_address(d, &elf, &parms) ) return -ENOSPC; + if ( (rc = dom0_check_parms(d, &parms)) != 0 ) + return rc; + elf_set_vcpu(&elf, v); rc = elf_load_binary(&elf); if ( rc < 0 ) diff --git a/xen/arch/x86/include/asm/dom0_build.h b/xen/arch/x86/include/asm/dom0_build.h index ff021c24af..b7bbfcbe6a 100644 --- a/xen/arch/x86/include/asm/dom0_build.h +++ b/xen/arch/x86/include/asm/dom0_build.h @@ -8,6 +8,8 @@ extern unsigned int dom0_memflags; +int dom0_check_parms(struct domain *d, + const struct elf_dom_parms *parms); unsigned long dom0_compute_nr_pages(struct domain *d, struct elf_dom_parms *parms, unsigned long initrd_len); diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index 075a3646c2..d50e1b9f78 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -494,14 +494,8 @@ static int __init dom0_construct(const struct boot_domain *bd) return -EINVAL; } - if ( parms.elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type != XEN_ENT_NONE ) - { - if ( !pv_shim && !test_bit(XENFEAT_dom0, parms.f_supported) ) - { - printk("Kernel does not support Dom0 operation\n"); - return -EINVAL; - } - } + if ( (rc = dom0_check_parms(d, &parms)) != 0 ) + return rc; nr_pages = dom0_compute_nr_pages(d, &parms, initrd_len); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 15:58:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 15:58:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272170.1560012 (Exim 4.92) (envelope-from ) id 1w8KR1-0004bU-Gi; Thu, 02 Apr 2026 15:58:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272170.1560012; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 37fd81aa-4626-4d1b-e613-08de90d0a56b X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2026 15:58:13.6007 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Y85V/52DYENo7Jt/oaLS9lO91crE1LNNxB2EpsDgdwMVYKj5siL72sCAZ1zMSoS0nc5BCsKaLkMm+Xavc51BwdUEpO7WFdr8dT+gdal/YhI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3PR03MB10987 X-purgate-ID: tlsNG-c1860d/1775145497-75557497-01D7A56A/0/0 X-purgate-type: clean X-purgate-size: 2229 Hi Michal, "Orzel, Michal" writes: > +Rahul > > On 02/04/2026 04:44, Julien Grall wrote: >> Hi Michal, >>=20 >> On 01/04/2026 15:58, Michal Orzel wrote: >>> Move domain_vpci_init() and domain_vpci_get_num_mmio_handlers() >>> declarations from the private xen/arch/arm/vpci.h into the public >>> xen/arch/arm/include/asm/vpci.h, and remove the now redundant >>> private header. >>=20 >> Can you provide a brief explanation why we don't couldn't include=20 >> "vpci.h" from "arch/arm/vpci.c"? Such approach would ... > Yes, we could but I think it's better not to use local headers if the mai= n ones > under include already exists. This matches the x86. > >>=20 >>> >>> Update domain.c to include instead of the removed private >>> header. >>> >>> This ensures the declarations are visible where the functions are >>> defined, resolving a MISRA C Rule 8.4 violation. >>> >>> Signed-off-by: Michal Orzel >>> --- >>> I'm moving a file with GPL2+ license to a file with GPL2-only. I consid= er this >>> ok in this case becase the copyright on a file with just prototypes doe= s not >>> make any sense and a license text was most likely blindly copy-pasted l= ike for >>> most of the files in that era. >>=20 >> ... avoid the licensing discussion. I am in the opinion that it is ok to= =20 >> move from GPLv2+ to GPLv2 because the license says "either version 2 of= =20 >> the License, or (at your option) any later version". But I remember not= =20 >> everyone agrees on this interpretation and we never solved the=20 >> discussion on whether we need to request permission from the original=20 >> copyright holder. >>=20 >> Alternatively, I see this file was only modified by two companies (EPAM= =20 >> and Arm). I see one employee of each company are already CCed. So you=20 >> could confirm with them if the change is fine. > The header was introduced by Rahul Singh from Arm and Oleksandr Andrusche= nko > from EPAM. @Rahul, @Bertrand, @Volodymyr - are you ok to move this file t= o > GPL2-only? Yes, I'm okay with that: Acked-by: Volodymyr Babchuk --=20 WBR, Volodymyr= From xen-devel-bounces@lists.xenproject.org Thu Apr 02 16:50:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 16:50:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272228.1560022 (Exim 4.92) (envelope-from ) id 1w8LFb-0004Pr-Cw; Thu, 02 Apr 2026 16:50:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272228.1560022; Thu, 02 Apr 2026 16:50:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8LFb-0004Pk-A4; Thu, 02 Apr 2026 16:50:35 +0000 Received: by outflank-mailman (input) for mailman id 1272228; Thu, 02 Apr 2026 16:50:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8LFZ-0004Pe-HM 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b=aElk5qmfZZJ9iZZUjNdBcZIqrEJhu+DjsLMIlE8gpr4yqf7i/rjBS2XBp3lArEFZ7R1GgI5GX6oDELY8iH1yVB1JHWvt1+CXvLdsxy0bQ7/HWgGSFTSUmeMfE7T4I0Hxs8dx/ATmeVsb+Z+VkFsTrUQsIDCj5+/DD/mhsF8/NjcUg+JeUUlg7v/j52f7wr8lHTScKP9hDmoGMB8+BNuSmHYjCEm0xzmYPnNdQwWvG5AVz+LV+WvHh047JLppRn7nAqze878TIzyRpbSA2VYjm5yUK3ntzF6cNPOGDNy/x7CAS6VDOZLuocn9jKZxcs6MCcTmo5OX4dkvpwyBgd5F+g== From: Oleksandr Tyshchenko To: "Orzel, Michal" , "xen-devel@lists.xenproject.org" CC: Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH] xen/device-tree: Fix off-by-one bounds check in make_memory_node() Thread-Topic: [PATCH] xen/device-tree: Fix off-by-one bounds check in make_memory_node() Thread-Index: AQHcwpBhsnhldIRLa0qtQ6xVjLEK7LXLt/YAgABFcwA= Date: Thu, 2 Apr 2026 16:53:52 +0000 Message-ID: References: <20260402110330.3580124-1-oleksandr_tyshchenko@epam.com> <865ae6a0-15e0-4a27-9537-0c5e6cb0a1cb@amd.com> In-Reply-To: <865ae6a0-15e0-4a27-9537-0c5e6cb0a1cb@amd.com> Accept-Language: en-US, ru-RU Content-Language: en-US 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b=otAbQHMCd2XCp6gI3vakfNOCplAruUhpRsEnPt2nBwQjZaqW22uhSw4WuDAheQkDrZuOVp/s0xXtzNmQ7iM+sKgz8rDCfapeVphsaLKhpuG8JgNu3vZpHdNtpKuXGes/Vxgy9rhBnrdrs/MnWuzjqSOeNQ7etv6j/mIEAr+JiiH+AOlkK6LfzChJAUFQRFIwbocd7rLhUz//WyYJdWYJeWQ5nxcExaq2irNAiJHqYPDH1/AGbJKm3vhQ6uJGDDucpO74+7TnLxsDLCs3m/rMy5cozvPAlFNNfMQheFfzgV9kGMEHI6xXu0ajhEFQpbLRXfvWz2azpf9JlRB/X8cqRw== From: Volodymyr Babchuk To: Mykola Kvach CC: "xen-devel@lists.xenproject.org" , Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: Re: [PATCH 4/4] xen/arm: its: pre-initialize ITS quirks before LPI setup Thread-Topic: [PATCH 4/4] xen/arm: its: pre-initialize ITS quirks before LPI setup Thread-Index: AQHcvEPnDsMTi8ib6UWvK8EWGL+9fw== Date: Thu, 2 Apr 2026 17:02:28 +0000 Message-ID: <87341dthwc.fsf@epam.com> References: In-Reply-To: (Mykola Kvach's message of "Wed, 25 Mar 2026 12:38:33 +0200") Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: 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X-MS-Exchange-CrossTenant-Network-Message-Id: 1df2077f-3790-485c-f12e-08de90d99ee2 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2026 17:02:28.1109 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Has+XzRvg8J0WDvKqmNyqoEpmY0I0tSXLLDf3hwSndm0kfa9U71/YG5U6q+bKi/e30F04CRt9jl5E2oljLJtvH83xH7ZQd4IRH9J9+62g4k= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0301MB6670 X-purgate-ID: tlsNG-ebf023/1775149351-B031451B-6E1DB5E0/0/0 X-purgate-type: clean X-purgate-size: 6190 Hi, Mykola Kvach writes: > From: Mykola Kvach > > In the current initialization flow, gicv3_init() calls gicv3_dist_init() > before gicv3_its_init(). > > When LPIs are supported, gicv3_dist_init() calls > gicv3_lpi_init_host_lpis(), which initializes host LPI state and allocate= s > the boot CPU pending table before ITS quirk flags are computed. Non-boot > CPUs allocate their pending tables later from the CPU_UP_PREPARE notifier= , > while redistributor LPI programming happens separately in > gicv3_lpi_init_rdist(). > > This means the boot CPU LPI setup can observe default ITS memory attribut= es > before dma-noncoherent and other ITS quirks are applied. > > Introduce gicv3_its_preinit() and call it before gicv3_dist_init(). This > keeps the actual ITS hardware initialization in gicv3_its_init(), but mov= es > ITS discovery, quirk validation and quirk flag setup early enough for the > subsequent LPI initialization to use the correct attributes. I must say that it was hard to review this patch, because it does more description says. > > Signed-off-by: Mykola Kvach > --- > TODO: Think about separating Redistributor/LPI attributes from ITS. > --- > xen/arch/arm/gic-v3-its.c | 36 +++++++++++++++++---------- > xen/arch/arm/gic-v3.c | 7 ++++++ > xen/arch/arm/include/asm/gic_v3_its.h | 5 ++++ > 3 files changed, 35 insertions(+), 13 deletions(-) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index ee432088cd..0251d91630 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -63,6 +63,7 @@ struct its_quirk { > uint32_t flags; > }; > =20 > +/* TODO: Separate Redistributor/LPI attributes from ITS quirks. */ > static uint32_t __ro_after_init its_quirk_flags; > =20 > static bool gicv3_its_match_quirk_gen4(const struct host_its *hw_its) > @@ -148,9 +149,15 @@ static uint32_t gicv3_its_collect_quirks(const struc= t host_its *hw_its, > return flags; > } > =20 > -static void gicv3_its_enable_quirks(struct host_its *hw_its) > +static void gicv3_its_enable_quirks(void) > { > const struct its_quirk *quirk; > + const struct host_its *hw_its; > + > + if ( list_empty(&host_its_list) ) > + return; > + > + hw_its =3D list_first_entry(&host_its_list, struct host_its, entry); > =20 > its_quirk_flags =3D gicv3_its_collect_quirks(hw_its, &quirk); > =20 > @@ -603,16 +610,10 @@ static int gicv3_its_init_single_its(struct host_it= s *hw_its) > uint64_t reg; > int i, ret; > =20 > - hw_its->its_base =3D ioremap_nocache(hw_its->addr, hw_its->size); > - if ( !hw_its->its_base ) > - return -ENOMEM; > - > ret =3D gicv3_disable_its(hw_its); > if ( ret ) > return ret; > =20 > - gicv3_its_enable_quirks(hw_its); > - > reg =3D readq_relaxed(hw_its->its_base + GITS_TYPER); > hw_its->devid_bits =3D GITS_TYPER_DEVICE_ID_BITS(reg); > hw_its->evid_bits =3D GITS_TYPER_EVENT_ID_BITS(reg); > @@ -1161,6 +1162,11 @@ static void add_to_host_its_list(paddr_t addr, pad= dr_t size, > its_data->size =3D size; > its_data->dt_node =3D node; > =20 > + its_data->its_base =3D ioremap_nocache(its_data->addr, its_data->siz= e); It is very confusing that add_to_host_its_list() function ioremaps ITS. It should not do this. Or at least renamed it to map_and_add_to_host_its_list() or consider moving this to gicv3_its_preinit(), maybe? > + if ( !its_data->its_base ) > + panic("GICv3: Cannot map ITS frame: 0x%lx, 0x%lx\n", > + its_data->addr, its_data->size); > + > printk("GICv3: Found ITS @0x%lx\n", addr); > =20 > list_add_tail(&its_data->entry, &host_its_list); > @@ -1238,16 +1244,22 @@ static void gicv3_its_acpi_init(void) > =20 > #endif > =20 > -int gicv3_its_init(void) > +void __init gicv3_its_preinit(void) > { > - struct host_its *hw_its; > - int ret; > - > if ( acpi_disabled ) > gicv3_its_dt_init(dt_interrupt_controller); > else > gicv3_its_acpi_init(); > =20 > + gicv3_its_validate_quirks(); > + gicv3_its_enable_quirks(); > +} > + > +int gicv3_its_init(void) > +{ > + struct host_its *hw_its; > + int ret; > + > list_for_each_entry(hw_its, &host_its_list, entry) > { > ret =3D gicv3_its_init_single_its(hw_its); > @@ -1255,8 +1267,6 @@ int gicv3_its_init(void) > return ret; > } > =20 > - gicv3_its_validate_quirks(); > - > return 0; > } > =20 > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index bc07f97c16..6e44d23d64 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -1974,6 +1974,13 @@ static int __init gicv3_init(void) > =20 > spin_lock(&gicv3.lock); > =20 > + if ( gic_dist_supports_lpis() ) > + /* > + * Apply ITS quirks before gicv3_dist_init() sets up host LPIs, > + * so pending tables use the correct ITS memory attributes. > + */ > + gicv3_its_preinit(); > + > gicv3_dist_init(); > =20 > if ( gic_dist_supports_lpis() ) > diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include= /asm/gic_v3_its.h > index fc5a84892c..e1d7522ea5 100644 > --- a/xen/arch/arm/include/asm/gic_v3_its.h > +++ b/xen/arch/arm/include/asm/gic_v3_its.h > @@ -156,6 +156,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); > =20 > /* Initialize the host structures for LPIs and the host ITSes. */ > int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); > +void gicv3_its_preinit(void); > int gicv3_its_init(void); > =20 > /* Store the physical address and ID for each redistributor as read from= DT. */ > @@ -219,6 +220,10 @@ static inline int gicv3_its_deny_access(struct domai= n *d) > return 0; > } > =20 > +static inline void gicv3_its_preinit(void) > +{ > +} > + > static inline bool gicv3_its_host_has_its(void) > { > return false; --=20 WBR, Volodymyr= From xen-devel-bounces@lists.xenproject.org Thu Apr 02 18:38:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 18:38:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272334.1560048 (Exim 4.92) (envelope-from ) id 1w8MwC-0000Qv-BA; Thu, 02 Apr 2026 18:38:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272334.1560048; Thu, 02 Apr 2026 18:38:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8MwC-0000Qo-8V; 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b=HJZjQlZinVrWadmtCHtqIDba4pKXx+aeAp+4IKeqrfKY7MbERwOZlC6S4tdyUi9i3z5EQw+JATRnzwQv2gc53uHTihlylN8xHn/cVm9pKQlKxqgBaQb11bIU8v9gFyeqNX1J/kPj9I0tsIQ7kstyePdH+J2o9uuBVn9t0GnvrYhnprpa7flvaGtJ3Wtc+b36m+s4XI4bTYCUU1OwEBskufZqG2TtwhY8HPrrKTsOOJT10tqxoI8tlL7tDPjYzMSHceyUEdyTYCZL2gq6aPmmEgV0Gfsfs0rjB7XthMfFiTBtVlY6d1Gmd2D7THfLO3XnTwwADXVyzwP5Mhl0m9zBhA== From: Oleksandr Tyshchenko To: "xen-devel@lists.xenproject.org" CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Ayan Kumar Halder Subject: [PATCH V2] xen/device-tree: Fix off-by-one bounds check in make_memory_node() Thread-Topic: [PATCH V2] xen/device-tree: Fix off-by-one bounds check in make_memory_node() Thread-Index: AQHcws/qu0Bt5vsAHEqQEICE62xUmQ== Date: Thu, 2 Apr 2026 18:38:35 +0000 Message-ID: <20260402183834.3660003-1-oleksandr_tyshchenko@epam.com> Accept-Language: en-US, ru-RU Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM4PR03MB11152.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 664bf726-6373-48e6-7918-08de90e70cad X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2026 18:38:35.7281 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: J1MM2j5L5EK1Kk9cHeC9CiPF/LRCykjsOmvA1LrBJyodECzHP5+de3BeH6J5cdTOaj7gvUk2EbY4l54S07F0J1aGzogoT6uBx81+kTEsnmU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR03MB9408 X-purgate-ID: tlsNG-bad1c0/1775155118-2DD57152-E3D40AC0/0/0 X-purgate-type: clean X-purgate-size: 2949 When building Xen with CONFIG_STATIC_SHM=3Dn, booting a hardware domain with exactly NR_MEM_BANKS (256) reserved-memory regions causes a panic: (XEN) Xen BUG at common/device-tree/domain-build.c:497 (XEN) Xen call trace: (XEN) [<00000a0000289aa8>] make_memory_node+0x178/0x234 (PC) This occurs due to an off-by-one error in the bounds checking of the reg array in make_memory_node(). The check: BUG_ON(nr_cells >=3D ARRAY_SIZE(reg)); incorrectly triggers when the array is exactly full (i.e., when nr_cells =3D=3D ARRAY_SIZE(reg)), preventing the 256th and final valid memory region from being written. When CONFIG_STATIC_SHM=3Dy, this bug is usually hidden because DT_MEM_NODE_REG_RANGE_SIZE adds extra space for SHM banks. This extra capacity prevents the array from reaching its maximum limit while processing the 256th memory region. However, if a domain is configured with exactly NR_MEM_BANKS and NR_SHMEM_BANKS, the array will completely fill up and trigger the same panic. Fix this by changing the condition to strictly greater than (>). Apply the exact same fix to shm_mem_node_fill_reg_range() to prevent the same error. Fixes: cd8015b634b0 ("ARM/dom0: Avoid using a variable length array in make= _memory_node()") Fixes: 7846f7699fea ("xen/arm: List static shared memory regions as /memory= nodes") Signed-off-by: Oleksandr Tyshchenko Reviewed-by: Michal Orzel --- V2: - slightly update commit desc (according to Michal's remark) - add Fixes tags - add R-b tag --- --- xen/common/device-tree/domain-build.c | 2 +- xen/common/device-tree/static-shmem.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree= /domain-build.c index 6708c9dd66..540627b74e 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -494,7 +494,7 @@ int __init make_memory_node(const struct kernel_info *k= info, int addrcells, continue; =20 nr_cells +=3D reg_size; - BUG_ON(nr_cells >=3D ARRAY_SIZE(reg)); + BUG_ON(nr_cells > ARRAY_SIZE(reg)); dt_child_set_range(&cells, addrcells, sizecells, start, size); } =20 diff --git a/xen/common/device-tree/static-shmem.c b/xen/common/device-tree= /static-shmem.c index 79f23caa77..4c4cc1b123 100644 --- a/xen/common/device-tree/static-shmem.c +++ b/xen/common/device-tree/static-shmem.c @@ -838,7 +838,7 @@ void __init shm_mem_node_fill_reg_range(const struct ke= rnel_info *kinfo, paddr_t size =3D mem->bank[i].size; =20 *nr_cells +=3D addrcells + sizecells; - BUG_ON(*nr_cells >=3D DT_MEM_NODE_REG_RANGE_SIZE); + BUG_ON(*nr_cells > DT_MEM_NODE_REG_RANGE_SIZE); dt_child_set_range(&cells, addrcells, sizecells, start, size); } } --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Thu Apr 02 23:06:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 02 Apr 2026 23:06:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272433.1560057 (Exim 4.92) (envelope-from ) id 1w8R7W-0005Lf-5z; Thu, 02 Apr 2026 23:06:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272433.1560057; Thu, 02 Apr 2026 23:06:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8R7W-0005LY-3M; Thu, 02 Apr 2026 23:06:38 +0000 Received: by outflank-mailman (input) for mailman id 1272433; Thu, 02 Apr 2026 23:06:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8R7U-0005LS-Lq for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="fbsx/PxUsQ8mae8A" Content-Disposition: inline In-Reply-To: <92e0151b-3fb1-4108-9788-f0fbac43512b@suse.com> X-purgate-ID: tlsNG-d25034/1775171194-80D5BA3D-E652C045/0/0 X-purgate-type: clean X-purgate-size: 8514 --fbsx/PxUsQ8mae8A Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 3 Apr 2026 01:06:30 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Thu, Apr 02, 2026 at 04:53:31PM +0200, Jan Beulich wrote: > On 02.04.2026 16:47, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Apr 02, 2026 at 12:48:14PM +0200, Jan Beulich wrote: > >> On 02.04.2026 11:35, Marek Marczykowski-G=C3=B3recki wrote: > >>> On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: > >>>> On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > >>>>> The xl dmesg output (from MTL this time): > >>>>> > >>>>> (XEN) [ 123.477511] Entering ACPI S3 state. > >>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0,= cpu_has_apic: 1 > >>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using= _deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >>> > >>>> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actua= lly > >>>> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() v= alues > >>>> might be a good idea, if only to double check.) > >>> > >>> Updated output: > >>> > >>> (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, c= pu_has_apic: 1 > >>> (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_d= eep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >>> (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 > >>> (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events= : ffff83046bc1f080 > >>> (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_u= sed: 8 > >>> (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 > >>> (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_e= vents[i].msi.irq: 122, hpet_events[i].flags: 0 > >>> (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 = (iommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 > >>> (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_f= rom_msi rc: 0 > >> > >> So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausible= =2E The high > >> half is, however, the address that the low half value is written to. I= t's hard > >> to imagine that it would be zero when the low half isn't, but it is ab= out the > >> last thing I can think of which could explain observed behavior. (Yet = then, all > >> of this is pretty meaningless; see below.) > >> > >>> And the current debug diff attached. > >> > >> Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very useful= =2E You want > >> to move that part of logging to the bottom of hpet_msi_write(), or may= be to > >> where you also log the per-channel cfg value in hpet_broadcast_resume(= ) (thus > >> making the logging overall less verbose). > >=20 > > This test is with the updated patch (attached) + your extra > > calculate_host_policy() call and "no-arat" on cmdline: >=20 > And IOMMU faults still occurring as before, I expect. >=20 > Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you don't = log > the high halves at all. I was missing hpet_read32 there... Updated: (XEN) [ 116.921573] Entering ACPI S3 state. (XEN) [18446743895.088893] _disable_pit_irq:2649: using_pit: 0, cpu_has_api= c: 1 (XEN) [18446743895.088907] _disable_pit_irq:2659: cpuidle_using_deep_cstate= : 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 (XEN) [18446743895.088918] _disable_pit_irq:2662: init: 0 (XEN) [18446743895.088928] hpet_broadcast_resume:662: hpet_events: ffff8304= 6bc1f080 (XEN) [18446743895.089072] hpet_broadcast_resume:673: num_hpets_used: 8 (XEN) [18446743895.089081] hpet_broadcast_resume:691: cfg: 0x1 (XEN) [18446743895.089092] hpet_broadcast_resume:696: i:0, hpet_events[i].m= si.irq: 122, hpet_events[i].flags: 0 (XEN) [18446743895.089122] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089132] hpet_broadcast_resume:700: i:0, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089168] hpet_broadcast_resume:710: i:0, cfg: 0xc134, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xf18 (XEN) [18446743895.089180] hpet_broadcast_resume:696: i:1, hpet_events[i].m= si.irq: 123, hpet_events[i].flags: 0 (XEN) [18446743895.089203] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089213] hpet_broadcast_resume:700: i:1, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089242] hpet_broadcast_resume:710: i:1, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xf38 (XEN) [18446743895.089254] hpet_broadcast_resume:696: i:2, hpet_events[i].m= si.irq: 124, hpet_events[i].flags: 0 (XEN) [18446743895.089278] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089288] hpet_broadcast_resume:700: i:2, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089316] hpet_broadcast_resume:710: i:2, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xf58 (XEN) [18446743895.089327] hpet_broadcast_resume:696: i:3, hpet_events[i].m= si.irq: 125, hpet_events[i].flags: 0 (XEN) [18446743895.089350] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089361] hpet_broadcast_resume:700: i:3, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089390] hpet_broadcast_resume:710: i:3, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xf78 (XEN) [18446743895.089401] hpet_broadcast_resume:696: i:4, hpet_events[i].m= si.irq: 126, hpet_events[i].flags: 0 (XEN) [18446743895.089425] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089436] hpet_broadcast_resume:700: i:4, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089465] hpet_broadcast_resume:710: i:4, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xf98 (XEN) [18446743895.089476] hpet_broadcast_resume:696: i:5, hpet_events[i].m= si.irq: 127, hpet_events[i].flags: 0 (XEN) [18446743895.089499] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089509] hpet_broadcast_resume:700: i:5, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089540] hpet_broadcast_resume:710: i:5, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfb8 (XEN) [18446743895.089551] hpet_broadcast_resume:696: i:6, hpet_events[i].m= si.irq: 128, hpet_events[i].flags: 0 (XEN) [18446743895.089574] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089584] hpet_broadcast_resume:700: i:6, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089622] hpet_broadcast_resume:710: i:6, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfd8 (XEN) [18446743895.089633] hpet_broadcast_resume:696: i:7, hpet_events[i].m= si.irq: 129, hpet_events[i].flags: 0 (XEN) [18446743895.089655] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743895.089665] hpet_broadcast_resume:700: i:7, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743895.089702] hpet_broadcast_resume:710: i:7, cfg: 0xc104, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xff8 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --fbsx/PxUsQ8mae8A Content-Type: application/pgp-signature; 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Fri, 03 Apr 2026 07:33:52 +0200 Received: from 0002-arm-xen.resend.eml (unknown [111.196.245.197]) by APP-03 (Coremail) with SMTP id rQCowACHqeA9Uc9pjEK7DA--.32598S2; Fri, 03 Apr 2026 13:33:49 +0800 (CST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Pengpeng Hou Date: Fri, 3 Apr 2026 10:42:09 +0800 Message-ID: <20260403151502.2-dt-arm-xen-resend-pengpeng@iscas.ac.cn> To: Stefano Stabellini Cc: xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pengpeng@iscas.ac.cn Subject: [PATCH] ARM: xen: validate hypervisor compatible before parsing its version X-CM-TRANSID:rQCowACHqeA9Uc9pjEK7DA--.32598S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr4rtFWkCF4rJr1kZF1UKFg_yoW8Zw4fpF Zakr9avFWrt3WxWa4IyFyv9Fy5GF4kXrW2qFykZ3Wjyrnrtw1rXrWIvF1SvFn3ArW8W343 ZrWjyFn5AF47X3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s 0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r106r15McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IY64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v26r126r1D MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr 0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0E wIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJV W8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAI cVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjG-e7UUUUU== X-Originating-IP: [111.196.245.197] X-CM-SenderInfo: pshqw1xhqjqxpvfd2hldfou0/ X-purgate-ID: tlsNG-42698a/1775194433-F47D42A1-6AE0A4CF/0/0 X-purgate-type: clean X-purgate-size: 2060 fdt_find_hyper_node() reads the raw compatible property and then derives hyper_node.version from a prefix match before later printing it with %s. Flat DT properties are external boot input, and this path does not prove that the compatible string is NUL-terminated within its declared bounds. Fetch the first compatible entry with fdt_stringlist_get() so malformed unterminated properties are rejected before the version suffix is parsed. Signed-off-by: Pengpeng Hou --- arch/arm/xen/enlighten.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 4feed2c2498d..f69290a4c639 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -218,8 +219,9 @@ static __initdata struct { static int __init fdt_find_hyper_node(unsigned long node, const char *uname, int depth, void *data) { - const void *s = NULL; + const char *s = NULL; int len; + size_t prefix_len = strlen(hyper_node.prefix); if (depth != 1 || strcmp(uname, "hypervisor") != 0) return 0; @@ -227,10 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, if (of_flat_dt_is_compatible(node, hyper_node.compat)) hyper_node.found = true; - s = of_get_flat_dt_prop(node, "compatible", &len); - if (strlen(hyper_node.prefix) + 3 < len && - !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) - hyper_node.version = s + strlen(hyper_node.prefix); + s = fdt_stringlist_get(initial_boot_params, node, "compatible", 0, &len); + if (s && len > prefix_len + 2 && + !strncmp(hyper_node.prefix, s, prefix_len)) + hyper_node.version = s + prefix_len; /* * Check if Xen supports EFI by checking whether there is the -- 2.50.1 (Apple Git-155) From xen-devel-bounces@lists.xenproject.org Fri Apr 03 06:03:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 06:03:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272521.1560066 (Exim 4.92) (envelope-from ) id 1w8Xcj-0002Va-11; Fri, 03 Apr 2026 06:03:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272521.1560066; Fri, 03 Apr 2026 06:03:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8Xci-0002VT-Uf; Fri, 03 Apr 2026 06:03:16 +0000 Received: by outflank-mailman (input) for mailman id 1272521; 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none X-purgate-ID: tlsNG-33051d/1775184601-41311C9A-214F4CF7/0/0 X-purgate-type: clean X-purgate-size: 3762 Message-Id: From: xen-devel-bounces@lists.xenproject.org Date: Fri, 03 Apr 2026 06:03:17 +0000 >From beef0e250a8453d76f9c6fb530a61b8110d4bd53 Mon Sep 17 00:00:00 2001 From: Pengpeng Hou Date: Fri, 3 Apr 2026 10:42:09 +0800 Message-ID: <20260403111502.2-dt-arm-xen-pengpeng@iscas.ac.cn> To: Stefano Stabellini Cc: xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pengpeng@iscas.ac.cn Subject: [PATCH] ARM: xen: validate hypervisor compatible before parsing its version X-CM-TRANSID:rQCowACXtt3UKs9pxlS4DA--.8142S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr4rtFWkCF4rJr1kZF1UKFg_yoW8Zw4fpF Zakr9avFWrt3WxWa4IyFyv9Fy5GF4kXrW2qFykZ3Wjyrnrtw1rXrWIvF1SvFn3ArW8W343 ZrWjyFn5AF47X3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkm14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvEwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_JF0_ Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxV WUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI 7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r 1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI 42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU5oGQDUUUU X-Originating-IP: [111.196.245.197] X-CM-SenderInfo: pshqw1xhqjqxpvfd2hldfou0/ fdt_find_hyper_node() reads the raw compatible property and then derives hyper_node.version from a prefix match before later printing it with %s. Flat DT properties are external boot input, and this path does not prove that the compatible string is NUL-terminated within its declared bounds. Fetch the first compatible entry with fdt_stringlist_get() so malformed unterminated properties are rejected before the version suffix is parsed. Signed-off-by: Pengpeng Hou --- arch/arm/xen/enlighten.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 4feed2c2498d..f69290a4c639 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -218,8 +219,9 @@ static __initdata struct { static int __init fdt_find_hyper_node(unsigned long node, const char *uname, int depth, void *data) { - const void *s = NULL; + const char *s = NULL; int len; + size_t prefix_len = strlen(hyper_node.prefix); if (depth != 1 || strcmp(uname, "hypervisor") != 0) return 0; @@ -227,10 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, if (of_flat_dt_is_compatible(node, hyper_node.compat)) hyper_node.found = true; - s = of_get_flat_dt_prop(node, "compatible", &len); - if (strlen(hyper_node.prefix) + 3 < len && - !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) - hyper_node.version = s + strlen(hyper_node.prefix); + s = fdt_stringlist_get(initial_boot_params, node, "compatible", 0, &len); + if (s && len > prefix_len + 2 && + !strncmp(hyper_node.prefix, s, prefix_len)) + hyper_node.version = s + prefix_len; /* * Check if Xen supports EFI by checking whether there is the -- 2.50.1 (Apple Git-155) From xen-devel-bounces@lists.xenproject.org Fri Apr 03 08:54:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 08:54:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272690.1560105 (Exim 4.92) (envelope-from ) id 1w8aIg-0006Ft-91; Fri, 03 Apr 2026 08:54:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272690.1560105; Fri, 03 Apr 2026 08:54:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8aIg-0006Fm-6I; Fri, 03 Apr 2026 08:54:46 +0000 Received: by outflank-mailman (input) for mailman id 1272690; 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bh=6pUPD6ERaLox44Hs8k1Jg3sa3tTqiLYmT0AJ6/LvpnM=; b=MDIPul3+5BkdjsO4liiSuZCzLuEiGCE6Sgl1xE2JVAJ+CA+a8BhfBN0j34g1pZ5gT69X1GQKPwQvhkzYgsOfuGMi22ytstbyAOjfi7nhUBo7CiUj0p0W+Z0A+R8sVRCbj+sJoNxWS1kBbnOqZ1gwz0ZoLO3Q6xjHjVXyee3GPd0= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Message-ID: Date: Fri, 3 Apr 2026 04:47:22 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arinc653: don't assume Dom0 is the control domain To: Jan Beulich , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= CC: Nathan Studer , Stewart Hildebrand , "xen-devel@lists.xenproject.org" References: <89d17a24-0a1f-4f3f-ac2f-f3701a8d78dd@suse.com> <4a4c011e-9666-4416-be1b-33d1dcad5afe@suse.com> <73e51afc-ae7c-4d08-9054-75dab660bf42@suse.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vryGxbmzsLPt6iutfMC0oxnj37X2B4seVkhebo6fjFgJqe+GIjCxMY3oc1JKlX0AvTC0XL2sDmQOAnUv0MBcZiS0/Fw+whPjGJzjb7ubXi6etKlmBozPRz1dO3T3ayZcawnIu24zz+Bpj03b21K3b8o8/A+6j3ytnDquUAOCmlhWnumVTaYm0rJHI4EeMZyveTyMrCyKp9xgRPMLWe5ds6ZHSvhrcZK22+eY2elh+5vFHrv3CGMeR0cjZ3q1F71QHmCounBFJFXbau5VHtsjasAvR6mM4mT4Wt1Rhmk6eboODoXCIbidbfCSffvxsbNILErpu5SigHfeUR14gDbJxBpatW+q3MLWCZd5jzdQMU73FJmNeR/VSomYq/EXj+xdjafpzbCIilqhMYml+hlEN02IP1bbsqhWvc8dbYcIBa09RYeCwNwxGtSGTbEvos7E X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 08:54:36.8438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 277b0599-881b-4467-111e-08de915ea24f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF00016159.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5762 X-purgate-ID: tlsNG-d62444/1775206482-B62E9185-E787EA1F/0/0 X-purgate-type: clean X-purgate-size: 4143 On 4/1/26 09:03, Jan Beulich wrote: > On 01.04.2026 14:57, Jürgen Groß wrote: >> On 01.04.26 14:29, Jan Beulich wrote: >>> Leaving aside highly disaggregated environments, the control domain is >>> what will invoke XEN_SYSCTL_SCHEDOP_putinfo. Its vCPU-s therefore need to >>> be able to run unconditionally, not those of the domain with ID 0 (which >>> may not exist at all). >>> >>> Fixes: 9f0c658baedc ("arinc: add cpu-pool support to scheduler") >>> Signed-off-by: Jan Beulich >>> --- >>> There being no "else" to the if(), what about other control domain vCPU-s? >> >> I guess this is a stale leftover. Doesn't matter for committing anyway. >> >>> --- >>> v3: Don't mistakenly include the idle domain. >>> v2: New. >>> >>> --- a/xen/common/sched/arinc653.c >>> +++ b/xen/common/sched/arinc653.c >>> @@ -411,10 +411,10 @@ a653sched_alloc_udata(const struct sched >>> spin_lock_irqsave(&sched_priv->lock, flags); >>> >>> /* >>> - * Add every one of dom0's units to the schedule, as long as there are >>> - * slots available. >>> + * Add every one of the control domain's units to the schedule, as long as >>> + * there are slots available. >>> */ >>> - if ( unit->domain->domain_id == 0 ) >>> + if ( is_control_domain(unit->domain) && !is_idle_domain(unit->domain) ) >>> { >>> entry = sched_priv->num_schedule_entries; >>> >> >> Hmm, is it really the control domain only which wants to be scheduled initially? >> I would think that at least the hardware domain and probably a Xenstore domain >> would want to be included, too. >> >> In the end it might even be that other domains created via dom0less would want >> to be able to run initially. They could be part of a mandatory infrastructure. >> Why would they need to be created at boot if they are NOT important? > > This part is easy to answer: Because in a dom0less setup you simply may have > no toolstack at all. (At which point there may also be nothing to set a > schedule, yes.) This is a known limitation. In a dom0less/hyperlaunch scenario, as future work, I would like to see the ability to configure the ARINC653 schedule in device tree, which would likely extend the existing boot time cpu pool work. >> The question is whether the arinc653 scheduler is really meant for such setups. >> OTOH just modifying the test to: >> >> if ( system_state < SYS_STATE_active && >> unit->domain->domain_id < DOMID_FIRST_RESERVED ) >> >> seems to be fine for catching all those cases. >> >> With or without this modification: >> >> Reviewed-by: Juergen Gross > > Thanks, yet I'll have to leave to the maintainers to decide which form it > should ultimately take. One remark: A restartable control domain wouldn't > pass that conditional. Granted that's looking far into the future. It may not be desirable to schedule domUs until the control domain has had a say in the matter, considering that the default schedule is unlikely to contain the desired minor frame runtimes. It's less clear whether to include hardware and xenstore domains in the default schedule, though I'm leaning toward only including the domain with ability to invoke XEN_SYSCTL_SCHEDOP_putinfo for now (i.e. the control domain). Hm, the suggested 'system_state < SYS_STATE_active' check is possibly a good addition. This reinforces that the default schedule's purpose is merely to get a system booting until a user-provided schedule can be installed. Without this check, restarting the control domain could result in new entries being added while old entries remain, possibly ending up with duplicates and/or exhausting the schedule. However, the restarted domain would need to retain its uuid if it expects to be scheduled after restart. Lastly, we may consider restricting the default schedule to Pool-0, and eventually we may want a mechanism to disable the default schedule altogether (e.g. when boot time cpupools are in use), but I don't think it's necessary to conflate those with the current patch. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 256f5695-61d4-4dbc-a40a-08de91637d82 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Apr 2026 09:29:22.6610 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pJHEKfU//YA4XFzdNJyLnqX4KLMu5UjYwIh/8ozuEpoqGeR+4pVAp1JG1NZwnUEFz5mOn5+cjdnMzR/tS1HU8DIvYztYlianASNtGGFVx9Q= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7236 X-purgate-ID: tlsNG-33051d/1775208564-C9136C9A-C712BD37/0/0 X-purgate-type: clean X-purgate-size: 1847 In RTDS, removing the last eligible pCPU can kill repl_timer. When a pCPU is later re-added, rt_switch_sched() reinitializes the timer object, but pending entries may already exist in replq. Without re-arming from replq head, replenishment can remain inactive until some unrelated event programs the timer again. This may stall budget replenishment for non-extratime units. Fix this by re-arming repl_timer in rt_switch_sched() immediately after init_timer() when replq is non-empty, using the earliest pending deadline. This keeps behavior unchanged when replq is empty. Signed-off-by: Oleksii Moisieiev --- Changes in v2: - update commit description, remove unneeded paragraph xen/common/sched/rt.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/common/sched/rt.c b/xen/common/sched/rt.c index 7b1f64a779..59021e1110 100644 --- a/xen/common/sched/rt.c +++ b/xen/common/sched/rt.c @@ -741,8 +741,17 @@ rt_switch_sched(struct scheduler *new_ops, unsigned in= t cpu, if ( prv->repl_timer.status =3D=3D TIMER_STATUS_invalid || prv->repl_timer.status =3D=3D TIMER_STATUS_killed ) { + struct list_head *replq =3D rt_replq(new_ops); + init_timer(&prv->repl_timer, repl_timer_handler, (void *)new_ops, = cpu); dprintk(XENLOG_DEBUG, "RTDS: timer initialized on cpu %u\n", cpu); + + /* + * When re-adding CPUs after all RTDS CPUs were removed, replq may + * already contain pending replenishment events. Re-arm immediatel= y. + */ + if ( !list_empty(replq) ) + set_timer(&prv->repl_timer, replq_elem(replq->next)->cur_deadl= ine); } =20 sched_idle_unit(cpu)->priv =3D vdata; --=20 2.43.0 base-commit: a7bf8ff218ca05eb3674fdfd2817f6cff471e96a= From xen-devel-bounces@lists.xenproject.org Fri Apr 03 10:11:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 10:11:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1272784.1560143 (Exim 4.92) (envelope-from ) id 1w8bUc-0008NQ-8u; Fri, 03 Apr 2026 10:11:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1272784.1560143; Fri, 03 Apr 2026 10:11:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8bUc-0008NJ-5W; Fri, 03 Apr 2026 10:11:10 +0000 Received: by outflank-mailman (input) for mailman id 1272784; Fri, 03 Apr 2026 10:11:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8bUa-0008ND-Au for xen-devel@lists.xenproject.org; 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Factor out a function to check ELF notes and reuse it even > for PVH. > > Signed-off-by: Frediano Ziglio > -- > Changes since v1: > - fix typo in title; > - fix minor formatting issue; > - use is_hardware_domain instead of checking is_pv_shim; > - reduce indentation returning earlier; > - return error instead of jumping to cleanup code. > --- > xen/arch/x86/dom0_build.c | 14 ++++++++++++++ > xen/arch/x86/hvm/dom0_build.c | 3 +++ > xen/arch/x86/include/asm/dom0_build.h | 2 ++ > xen/arch/x86/pv/dom0_build.c | 10 ++-------- > 4 files changed, 21 insertions(+), 8 deletions(-) > > diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c > index 864dd9e53e..a33ce77321 100644 > --- a/xen/arch/x86/dom0_build.c > +++ b/xen/arch/x86/dom0_build.c > @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, > return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); > } > > +int __init dom0_check_parms( > + struct domain *d, const struct elf_dom_parms *parms) d should be const also. > +{ > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) > + return 0; > + > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) > + { > + printk("Kernel does not support Dom0 operation\n"); > + return -EINVAL; > + } > + > + return 0; > +} > > /* > * If allocation isn't specified, reserve 1/16th of available memory for > diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c > index d69a83b089..f95a00acfd 100644 > --- a/xen/arch/x86/hvm/dom0_build.c > +++ b/xen/arch/x86/hvm/dom0_build.c > @@ -699,6 +699,9 @@ static int __init pvh_load_kernel( > if ( !check_and_adjust_load_address(d, &elf, &parms) ) > return -ENOSPC; > > + if ( (rc = dom0_check_parms(d, &parms)) != 0 ) > + return rc; I would do the check ahead of check_and_adjust_load_address(), as then we could avoid the load address adjustment if we detect earlier than the dom0 feature is not present. But that's just my taste. I can adjust the const-ification of d on commit if there are no further objections: Reviewed-by: Roger Pau Monné Thanks, Roger. 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Message-ID: References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="IAFUchFxljARC2be" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-ebf023/1775224512-3212551B-8CF3F5C1/0/0 X-purgate-type: clean X-purgate-size: 1836 --IAFUchFxljARC2be Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 3 Apr 2026 15:55:07 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel , =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? On Thu, Apr 02, 2026 at 03:02:15PM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-G=C3=B3recki= wrote: > > Some further observation, this time regarding timers: >=20 > In the meantime Roger suggested it might be about C-states. So, I just > tried booting with max_cstate=3D0. I got this: We had a design session on this issue, and managed to find (thanks Roger!) that adding: tsc_mode=3D'always_emulate' to the domU config fixes the issue. Now, the question is how to fix it properly... --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --IAFUchFxljARC2be Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnPxrsACgkQ24/THMrX 1yxMjQf+ISAAxXFtNjrTNrWA/GXqU1GQjp3JY1Rcze1mkNkMkDtKcd7C4f8A4ing o5uwsZJhHAjOxHqt3RN0RoWw1gb5q70aOe50sBmtZ7+AEQI9LRHHh3Ug2v6v6PS2 7QFN7PrBG6Nh4Q34YzMZ5koZwoJDUJCghGprhR8L+tP/dIgSrMDPIlK0+JcVrXRm U5uRHG4XYGrRvRSYt0xw8a3zkN2fz2F1KZ51oud9eBacDZeR4YeTrWP0zZAepxP2 qCTnGJiSmu6TJ24kcgb3k0wPxSR+wGDMSdT5DIFzKL77RRMZMtGhEdI47ocwTExh ZLwXbVvdkB46Y1iKzqTHEKrcDjBaiw== =wCLO -----END PGP SIGNATURE----- --IAFUchFxljARC2be-- From xen-devel-bounces@lists.xenproject.org Fri Apr 03 18:51:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 18:51:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273254.1560194 (Exim 4.92) (envelope-from ) id 1w8jbq-00033D-Vu; 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pr=C Message-ID: <746e808c-6219-4f84-bb53-a49a95ed4085@amd.com> Date: Fri, 3 Apr 2026 14:51:01 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] vpci: allow queueing of mapping operations To: Mykyta Poturai , "xen-devel@lists.xenproject.org" CC: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <20260324030513.700217-1-stewart.hildebrand@amd.com> <20260324030513.700217-3-stewart.hildebrand@amd.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE16:EE_|SAVPR12MB999143:EE_ X-MS-Office365-Filtering-Correlation-Id: d44835ee-67ec-4494-7524-08de91b1f4ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|18002099003|56012099003|13003099007|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4yau+5MtKFQewfJYaYqbUIutXYgHCHzAUlHA12LYYEgNmBlvpMNc6lZx3qIJH5Fh8LBc9+dJKHb4hkliAhp7Kn6t/Bbb327cbv7/CTpda9+Us7N0EGeUxzX8QEDIrcAta8PUBMFsZPcBDsfzSAFv03MJmXFqtohvxD4gMN0KSmgzeviDKEhJMWjg7AFSmQxwt2mqJoSxkL671hzrdeLhGNK8uUioy+glS7OhEeRjBIg6RalzVnAa6MiMUoA1O91QvFtnN7XZa1c6gCMHAhfiNHaie9iZ/9Bl+/IeCL8s1oZNevSL4rk1tk92V2Zwf9PfDpblwdXplCOvoS31zC+bEfJyIFyUH+ndek4463+PbuyhAuEggJE1PbzIWdzI7/2NePfvFgWwaTNDYY0xbF4TitChod9heRGuMxTNIQ6mNtAIJn/lcgYI0CvSyIS7SryE X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 18:51:03.4617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d44835ee-67ec-4494-7524-08de91b1f4ca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAVPR12MB999143 X-purgate-ID: tlsNG-42698a/1775242268-F53CE2A1-837B41EB/0/0 X-purgate-type: clean X-purgate-size: 2015 On 4/2/26 11:52, Mykyta Poturai wrote: > On 3/24/26 05:04, Stewart Hildebrand wrote: >> Introduce vPCI BAR mapping task queue. Store information necessary in an >> array in struct vpci_vcpu to perform multiple p2m operations associated >> with single device. >> >> This is preparatory work for further changes that need to perform >> multiple unmap/map operations before returning to guest. >> >> At the moment, only a single slot is needed in the array. However, when >> multiple operations are queued and pending, there is a check in >> modify_bars() to skip BARs already in the requested state that is not >> accurate. Remove this check. >> >> Signed-off-by: Stewart Hildebrand >> --- >> apply_map() and vpci_process_map_task() are very similar. Should we try >> to combine them into a single function? >> >> v2->v3: >> * base on ("vpci: Use pervcpu ranges for BAR mapping") from [1] >> * rework with fixed array of map/unmap slots >> >> [1] https://lore.kernel.org/xen-devel/cover.1772806036.git.mykyta_poturai@epam.com/T/#t >> >> v1->v2: >> * new patch > > Hi everyone, > > > Would it be possible to move back to a dynamically allocated number of > tasks? This would help with mapping SR-IOV virtual functions a lot. > @Stewart @Roger, what are your thoughts? Yes, assuming each VF will need another queued map operation, and there could be a lot of VFs, statically pre-allocating that much seems wasteful. Only the control and/or hardware domains will queue a lot of operations, and only when enabling SR-IOV. DomUs will only queue 1 operation (possibly 2 if we will allow domU BAR writes with memory decoding enabled). So I'll plan to switch back to dynamically allocated map tasks for v4. > Alternatively, I can continue with an approach described in SR-IOV > series, where VFs are handled separately. I figured out how to return to > do_softirq after mapping each VF, so it should not block the CPU for too > long. > From xen-devel-bounces@lists.xenproject.org Fri Apr 03 21:24:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 21:24:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273326.1560203 (Exim 4.92) (envelope-from ) id 1w8m01-0003lP-2v; Fri, 03 Apr 2026 21:24:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273326.1560203; Fri, 03 Apr 2026 21:24:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8m01-0003lI-0M; Fri, 03 Apr 2026 21:24:17 +0000 Received: by outflank-mailman (input) for mailman id 1273326; Fri, 03 Apr 2026 21:24:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8lzz-0003lA-RL for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="4Ae0y7aT9vuqArIi" Content-Disposition: inline In-Reply-To: <1de15ce0-9f7e-4253-80a7-ecd94caa4325@vates.tech> X-purgate-ID: tlsNG-ef75cf/1775251454-8975241E-EA13BEEB/0/0 X-purgate-type: clean X-purgate-size: 1920 --4Ae0y7aT9vuqArIi Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 3 Apr 2026 23:24:07 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Teddy Astie Cc: Val Packett , Demi Marie Obenour , Xen developer discussion , dri-devel@lists.freedesktop.org, linux-mm@kvack.org, Ariadne Conill Subject: Re: Why memory lending is needed for GPU acceleration On Tue, Mar 31, 2026 at 09:42:22AM +0000, Teddy Astie wrote: > XEN_GNTDEV_DMABUF has been designed for GPU use-cases, and more > precisely for paravirtualizing a display. The only issue I would have > with it is that grants are not scalable for GPU 3D use cases (with > hundreds of MB to share). FWIW we do use grants for graphics buffers already - window composition buffers specifically. We do run xen with extra options for that: gnttab_max_frames=3D2048 gnttab_max_maptrack_frames=3D4096 And similarly, on domU side: echo 1073741824 > /sys/module/xen_gntalloc/parameters/limit --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --4Ae0y7aT9vuqArIi Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnQL/gACgkQ24/THMrX 1yxbGQf+OgsupCAnm7yeXU50i8UAUbaCxLl6LTgomVWE8BqqFLLzbd1uZRBaxgwi 08KM6UwaNDnWYrJjTzzuVajjgvb364NRxaCcDQMU1gg9QaScwe0rvqNXjTCyyZIZ KcGYITuyNobu6TEOlxjMZCYe09hjh5Tv6YIAjNytG/v4Wj0BeLd6dpU3y/K79rsz k5Q2KuSQNJBm0DrX1xHtYDI34Ecs8kMi+QNmTxBNirLjkzswlCpewSvOONNsy8Ff 8k+hGeZuhbRQMidzb/toBQpk5p82359YvtUwGWz6rn/YnryTk6+3x3Vr1octMvgz 5SPKxfVNDvikjgpYpZpWowiX1sDLHw== =Aya7 -----END PGP SIGNATURE----- --4Ae0y7aT9vuqArIi-- From xen-devel-bounces@lists.xenproject.org Fri Apr 03 23:48:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 03 Apr 2026 23:48:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273371.1560213 (Exim 4.92) (envelope-from ) id 1w8oF9-0003TV-KQ; Fri, 03 Apr 2026 23:48:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273371.1560213; Fri, 03 Apr 2026 23:48:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8oF9-0003TO-H5; Fri, 03 Apr 2026 23:48:03 +0000 Received: by outflank-mailman (input) for mailman id 1273371; Fri, 03 Apr 2026 23:48:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w8oF7-0003TI-Td for xen-devel@lists.xenproject.org; Fri, 03 Apr 2026 23:48:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w8oF7-009MjX-9u for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 01:48:01 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d051af-5cb7-0a2a0a5109dd-0a2a4507bfd6-6 for ; Sat, 04 Apr 2026 01:48:01 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d051af-ba2d-0a2a45070019-aceafc1f8c1a-3 for ; Sat, 04 Apr 2026 01:48:00 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id D209643BAA; Fri, 3 Apr 2026 23:47:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 134E6C4CEF7; Fri, 3 Apr 2026 23:47:57 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775260078; bh=A/UuuA1NVFkJMO81wS0G58dAgB2oCFTP3hEqag6xc8c=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=GJl0pGY4rSCZdff2BVZvDGgyy/PfbnKnWwsgH/4L92t8PypTgMmGCNS58Ab86tTra 5NKgnGl1oFDIfLg5xe7Yf3J2iHFHk1dG/uQJIpLQZCr7OY69AvYjJbzqUvwIG5ryxW /zHLZ7IKxVrKRxpWHSJqMKRfyYiC4zkjF00C+Mr/fAQNgp5PD7J8FsmEdIv0nrnPJ7 oyCUPGhqIjOsXeb7MNN/AuSy3sJrTQrP8nqmEA0x2ct7z32sJgecpC+AMcB8jxGYdN F8GCcJKKje1tvzAR8OCYbqtAHMk2ve3lIHaBQZiOZtuhLaglBgnEPpP4XEeXVnmdWS Jga7pSoh180UQ== Date: Fri, 3 Apr 2026 16:47:49 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Pengpeng Hou cc: Stefano Stabellini , xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: xen: validate hypervisor compatible before parsing its version In-Reply-To: <20260403151502.2-dt-arm-xen-resend-pengpeng@iscas.ac.cn> Message-ID: References: <20260403151502.2-dt-arm-xen-resend-pengpeng@iscas.ac.cn> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-ef75cf/1775260081-1274A41E-A6D6C45C/0/0 X-purgate-type: clean X-purgate-size: 2310 On Fri, 3 Apr 2026, Pengpeng Hou wrote: > fdt_find_hyper_node() reads the raw compatible property and then > derives hyper_node.version from a prefix match before later printing it > with %s. Flat DT properties are external boot input, and this path does > not prove that the compatible string is NUL-terminated within its > declared bounds. > > Fetch the first compatible entry with fdt_stringlist_get() so malformed > unterminated properties are rejected before the version suffix is > parsed. > > Signed-off-by: Pengpeng Hou > --- > arch/arm/xen/enlighten.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c > index 4feed2c2498d..f69290a4c639 100644 > --- a/arch/arm/xen/enlighten.c > +++ b/arch/arm/xen/enlighten.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -218,8 +219,9 @@ static __initdata struct { > static int __init fdt_find_hyper_node(unsigned long node, const char *uname, > int depth, void *data) > { > - const void *s = NULL; > + const char *s = NULL; > int len; > + size_t prefix_len = strlen(hyper_node.prefix); > > if (depth != 1 || strcmp(uname, "hypervisor") != 0) > return 0; > @@ -227,10 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, > if (of_flat_dt_is_compatible(node, hyper_node.compat)) > hyper_node.found = true; > > - s = of_get_flat_dt_prop(node, "compatible", &len); > - if (strlen(hyper_node.prefix) + 3 < len && > - !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) > - hyper_node.version = s + strlen(hyper_node.prefix); > + s = fdt_stringlist_get(initial_boot_params, node, "compatible", 0, &len); > + if (s && len > prefix_len + 2 && > + !strncmp(hyper_node.prefix, s, prefix_len)) > + hyper_node.version = s + prefix_len; I'd prefer to go with: s = of_get_flat_dt_prop(node, "compatible", &len); if (s && len > 0 && strnlen(s, len) < len && len > prefix_len + 3 && !strncmp(hyper_node.prefix, s, prefix_len)) From xen-devel-bounces@lists.xenproject.org Sat Apr 04 11:32:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 11:32:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273628.1560239 (Exim 4.92) (envelope-from ) id 1w8zEv-0001ut-PR; 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Sat, 04 Apr 2026 04:32:29 -0700 (PDT) MIME-Version: 1.0 References: <20260402155512.80170-1-frediano.ziglio@cloud.com> In-Reply-To: From: Frediano Ziglio Date: Sat, 4 Apr 2026 12:32:18 +0100 X-Gm-Features: AQROBzA2RkU_b1hqzlm5riiCwhlWPKxXibwghJW3qQteUFSuVYYYfA4AzhDVtUk Message-ID: Subject: Re: [PATCH v2] xen/x86: Check supported features even for PVH dom0 To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: xen-devel@lists.xenproject.org, Frediano Ziglio , Jan Beulich , Andrew Cooper Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1775302351-30D3796F-605BCF37/0/0 X-purgate-type: clean X-purgate-size: 2761 On Fri, 3 Apr 2026 at 11:11, Roger Pau Monn=C3=A9 wr= ote: > > On Thu, Apr 02, 2026 at 04:55:10PM +0100, Frediano Ziglio wrote: > > The supported features ELF notes was tested only if the dom0 was > > PV. Factor out a function to check ELF notes and reuse it even > > for PVH. > > > > Signed-off-by: Frediano Ziglio > > -- > > Changes since v1: > > - fix typo in title; > > - fix minor formatting issue; > > - use is_hardware_domain instead of checking is_pv_shim; > > - reduce indentation returning earlier; > > - return error instead of jumping to cleanup code. > > --- > > xen/arch/x86/dom0_build.c | 14 ++++++++++++++ > > xen/arch/x86/hvm/dom0_build.c | 3 +++ > > xen/arch/x86/include/asm/dom0_build.h | 2 ++ > > xen/arch/x86/pv/dom0_build.c | 10 ++-------- > > 4 files changed, 21 insertions(+), 8 deletions(-) > > > > diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c > > index 864dd9e53e..a33ce77321 100644 > > --- a/xen/arch/x86/dom0_build.c > > +++ b/xen/arch/x86/dom0_build.c > > @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struc= t domain *d, > > return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); > > } > > > > +int __init dom0_check_parms( > > + struct domain *d, const struct elf_dom_parms *parms) > > d should be const also. > > > +{ > > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type =3D=3D = XEN_ENT_NONE ) > > + return 0; > > + > > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_sup= ported) ) > > + { > > + printk("Kernel does not support Dom0 operation\n"); > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > > > /* > > * If allocation isn't specified, reserve 1/16th of available memory f= or > > diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_buil= d.c > > index d69a83b089..f95a00acfd 100644 > > --- a/xen/arch/x86/hvm/dom0_build.c > > +++ b/xen/arch/x86/hvm/dom0_build.c > > @@ -699,6 +699,9 @@ static int __init pvh_load_kernel( > > if ( !check_and_adjust_load_address(d, &elf, &parms) ) > > return -ENOSPC; > > > > + if ( (rc =3D dom0_check_parms(d, &parms)) !=3D 0 ) > > + return rc; > > I would do the check ahead of check_and_adjust_load_address(), as then > we could avoid the load address adjustment if we detect earlier than > the dom0 feature is not present. But that's just my taste. > > I can adjust the const-ification of d on commit if there are no > further objections: > > Reviewed-by: Roger Pau Monn=C3=A9 > > Thanks, Roger. Fine with me. Frediano From xen-devel-bounces@lists.xenproject.org Sat Apr 04 15:02:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 15:02:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273752.1560274 (Exim 4.92) (envelope-from ) id 1w92Vw-0001DZ-B3; Sat, 04 Apr 2026 15:02:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273752.1560274; Sat, 04 Apr 2026 15:02:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w92Vw-0001DR-7h; Sat, 04 Apr 2026 15:02:20 +0000 Received: by outflank-mailman (input) for mailman id 1273752; Sat, 04 Apr 2026 15:02:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w92Vv-0001DL-1d for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 15:02:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w92Vu-007yaP-AA for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 17:02:18 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d127e8-e002-0a2a0a5209dd-0a2a450b9104-24 for ; Sat, 04 Apr 2026 17:02:18 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d127f9-bca8-0a2a450b0019-ac6904fe9486-3 for ; Sat, 04 Apr 2026 17:02:17 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 32414600CB; Sat, 4 Apr 2026 15:02:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9BB2C19421; Sat, 4 Apr 2026 15:02:06 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775314935; bh=yS1a8GmMxhd+gaXjsrUMOyEcZUcN2vLf71oRyrhAVkk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fcd1WH1uMPDFcW95A5bP6twrmSlGywxDbhV9K4GUdxmnw9OhLho72J9OlIZREDDfv Evf5eg+FhGKnEBZMEi0xrGzL0W0wBBPFC5ZbOalQpNWyhGwDm3HuLGvy/jgjYAq60X Jsa257f9xIzRC/LnmHpxdh9mv/JRHNm7utYMn96WoZP6ZRATrlwe1+3BmjlR9bxRPR tiA87cPHB5ojtZQJ2zSKPbtecnXGON24oyWbrZcP9XuN+XivvmLrVCQGu5orrMZe/a +xDtWMIwREbTcGNYdTKbgyxE7aDCuXqmHaashK055GEOETa+XQlaspyrGVn7GrwOhI UHZOaAkc+kiUA== From: Danilo Krummrich To: Russell King , Greg Kroah-Hartman , "Rafael J. Wysocki" , Ioana Ciornei , Nipun Gupta , Nikhil Agarwal , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Bjorn Helgaas , Armin Wolf , Bjorn Andersson , Mathieu Poirier , Vineeth Vijayan , Peter Oberparleiter , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Harald Freudenberger , Holger Dengler , Mark Brown , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?q?Eugenio=20P=C3=A9rez?= , Alex Williamson , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , "Christophe Leroy (CS GROUP)" Cc: linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org, linux-spi@vger.kernel.org, virtualization@lists.linux.dev, kvm@vger.kernel.org, xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, Danilo Krummrich , Michael Kelley , Gui-Dong Han Subject: [PATCH v2] Drivers: hv: vmbus: use generic driver_override infrastructure Date: Sat, 4 Apr 2026 17:01:49 +0200 Message-ID: <20260404150155.3473682-1-dakr@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775314938-EC3642A1-FAE8CD37/0/0 X-purgate-type: clean X-purgate-size: 4285 When a driver is probed through __driver_attach(), the bus' match() callback is called without the device lock held, thus accessing the driver_override field without a lock, which can cause a UAF. Fix this by using the driver-core driver_override infrastructure taking care of proper locking internally. Note that calling match() from __driver_attach() without the device lock held is intentional. [1] Tested-by: Michael Kelley Reviewed-by: Michael Kelley Link: https://lore.kernel.org/driver-core/DGRGTIRHA62X.3RY09D9SOK77P@kernel.org/ [1] Reported-by: Gui-Dong Han Closes: https://bugzilla.kernel.org/show_bug.cgi?id=220789 Fixes: d765edbb301c ("vmbus: add driver_override support") Signed-off-by: Danilo Krummrich --- Changes in v2: - Change patch subject and comments according to Michael's suggestion. --- drivers/hv/vmbus_drv.c | 43 ++++++++++-------------------------------- include/linux/hyperv.h | 5 ----- 2 files changed, 10 insertions(+), 38 deletions(-) diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c index bc4fc1951ae1..ba7326ec6add 100644 --- a/drivers/hv/vmbus_drv.c +++ b/drivers/hv/vmbus_drv.c @@ -541,34 +541,6 @@ static ssize_t device_show(struct device *dev, } static DEVICE_ATTR_RO(device); -static ssize_t driver_override_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct hv_device *hv_dev = device_to_hv_device(dev); - int ret; - - ret = driver_set_override(dev, &hv_dev->driver_override, buf, count); - if (ret) - return ret; - - return count; -} - -static ssize_t driver_override_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct hv_device *hv_dev = device_to_hv_device(dev); - ssize_t len; - - device_lock(dev); - len = sysfs_emit(buf, "%s\n", hv_dev->driver_override); - device_unlock(dev); - - return len; -} -static DEVICE_ATTR_RW(driver_override); - /* Set up per device attributes in /sys/bus/vmbus/devices/ */ static struct attribute *vmbus_dev_attrs[] = { &dev_attr_id.attr, @@ -599,7 +571,6 @@ static struct attribute *vmbus_dev_attrs[] = { &dev_attr_channel_vp_mapping.attr, &dev_attr_vendor.attr, &dev_attr_device.attr, - &dev_attr_driver_override.attr, NULL, }; @@ -711,9 +682,11 @@ static const struct hv_vmbus_device_id *hv_vmbus_get_id(const struct hv_driver * { const guid_t *guid = &dev->dev_type; const struct hv_vmbus_device_id *id; + int ret; - /* When driver_override is set, only bind to the matching driver */ - if (dev->driver_override && strcmp(dev->driver_override, drv->name)) + /* If a driver override is set, only bind to the matching driver */ + ret = device_match_driver_override(&dev->device, &drv->driver); + if (ret == 0) return NULL; /* Look at the dynamic ids first, before the static ones */ @@ -721,8 +694,11 @@ static const struct hv_vmbus_device_id *hv_vmbus_get_id(const struct hv_driver * if (!id) id = hv_vmbus_dev_match(drv->id_table, guid); - /* driver_override will always match, send a dummy id */ - if (!id && dev->driver_override) + /* + * If there's a matching driver override, this function should succeed, + * thus return a dummy device ID if no matching ID is found. + */ + if (!id && ret > 0) id = &vmbus_device_null; return id; @@ -1024,6 +1000,7 @@ static const struct dev_pm_ops vmbus_pm = { /* The one and only one */ static const struct bus_type hv_bus = { .name = "vmbus", + .driver_override = true, .match = vmbus_match, .shutdown = vmbus_shutdown, .remove = vmbus_remove, diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h index dfc516c1c719..bf689d07d750 100644 --- a/include/linux/hyperv.h +++ b/include/linux/hyperv.h @@ -1272,11 +1272,6 @@ struct hv_device { u16 device_id; struct device device; - /* - * Driver name to force a match. Do not set directly, because core - * frees it. Use driver_set_override() to set or clear it. - */ - const char *driver_override; struct vmbus_channel *channel; struct kset *channels_kset; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Sat Apr 04 15:08:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 15:08:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273762.1560283 (Exim 4.92) (envelope-from ) id 1w92bS-0001rF-TH; Sat, 04 Apr 2026 15:08:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273762.1560283; Sat, 04 Apr 2026 15:08:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w92bS-0001r8-QO; Sat, 04 Apr 2026 15:08:02 +0000 Received: by outflank-mailman (input) for mailman id 1273762; Sat, 04 Apr 2026 15:08:01 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w92bR-0001r2-Nm for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 15:08:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w92bR-00AxRE-0A for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 17:08:01 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d128db-2eae-0a2a0a5409dd-0a2a450cc12c-12 for ; Sat, 04 Apr 2026 17:08:00 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d1294f-f40c-0a2a450c0019-ac6904fea140-3 for ; Sat, 04 Apr 2026 17:08:00 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 09D4760008; Sat, 4 Apr 2026 15:07:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11D01C19421; Sat, 4 Apr 2026 15:07:49 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:To:From:Subject:Cc:References:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775315278; bh=vsboea1jS0mbXrEN888C7vI6KSnNsfnadcjKrpMmAnY=; h=Date:To:From:Subject:Cc:References:In-Reply-To:From; b=BqFwLyJnTBhpomTB+sXRdwyVaWyzA1LM4x/jRCX0BFGrA8JpgKS8rfJ3LIpPDY9yk p+d1jqhJ1Mjf2wU0RpwYFVVUOlAbdMj9UlGnuClj9FmR1QC9ZSfTvrkB18QTB/RfaR 3w4rXTh/VlmdJJ+A6SXPJawUID7A7XZSgzuHSGqEFu6Tbouz8uVWV9o1VaA1GFu7gI 3NdNsOM8C1NHzuvTeKFcIyrqClEFUe0UqumonfV9MfwITs9dnEyWj08ERsdYv9WbWd 01HVmLT594g3v4oxts7zZYAk6RxZP3qVHdO7PiI+5yTu0pvGRJP4QeyHxy5PzJrrxp 3oxcw/dlirZ+g== Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 04 Apr 2026 17:07:48 +0200 Message-Id: To: "Russell King" , "Greg Kroah-Hartman" , "Rafael J. Wysocki" , "Ioana Ciornei" , "Nipun Gupta" , "Nikhil Agarwal" , "K. Y. Srinivasan" , "Haiyang Zhang" , "Wei Liu" , "Dexuan Cui" , "Long Li" , "Bjorn Helgaas" , "Armin Wolf" , "Bjorn Andersson" , "Mathieu Poirier" , "Vineeth Vijayan" , "Peter Oberparleiter" , "Heiko Carstens" , "Vasily Gorbik" , "Alexander Gordeev" , "Christian Borntraeger" , "Sven Schnelle" , "Harald Freudenberger" , "Holger Dengler" , "Mark Brown" , "Michael S. Tsirkin" , "Jason Wang" , "Xuan Zhuo" , =?utf-8?q?Eugenio_P=C3=A9rez?= , "Alex Williamson" , "Juergen Gross" , "Stefano Stabellini" , "Oleksandr Tyshchenko" , "Christophe Leroy (CS GROUP)" From: "Danilo Krummrich" Subject: Re: (subset) [PATCH 00/12] treewide: Convert buses to use generic driver_override Cc: , , , , , , , , , , , , , , "Danilo Krummrich" References: <20260324005919.2408620-1-dakr@kernel.org> In-Reply-To: <20260324005919.2408620-1-dakr@kernel.org> X-purgate-ID: tlsNG-d25034/1775315280-83945A3D-E95B2C17/0/0 X-purgate-type: clean X-purgate-size: 974 On Tue Mar 24, 2026 at 1:59 AM CET, Danilo Krummrich wrote: > Danilo Krummrich (12): > PCI: use generic driver_override infrastructure > platform/wmi: use generic driver_override infrastructure > vdpa: use generic driver_override infrastructure > s390/cio: use generic driver_override infrastructure > s390/ap: use generic driver_override infrastructure Applied to driver-core-testing, thanks! > amba: use generic driver_override infrastructure > cdx: use generic driver_override infrastructure > hv: vmbus: use generic driver_override infrastructure > rpmsg: use generic driver_override infrastructure I have not picked these up, as they have not received ACKs from the corresponding subsystem maintainers so far. > bus: fsl-mc: use generic driver_override infrastructure > spi: use generic driver_override infrastructure These have already been picked up via the respective subsystem trees -- tha= nks! Thanks, Danilo From xen-devel-bounces@lists.xenproject.org Sat Apr 04 16:56:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 16:56:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273815.1560292 (Exim 4.92) (envelope-from ) id 1w94IQ-0007JF-Cu; Sat, 04 Apr 2026 16:56:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273815.1560292; Sat, 04 Apr 2026 16:56:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94IQ-0007J8-9r; Sat, 04 Apr 2026 16:56:30 +0000 Received: by outflank-mailman (input) for mailman id 1273815; Sat, 04 Apr 2026 16:56:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94IO-0007J1-FN for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 16:56:28 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w94IN-003sCG-Rl for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 18:56:27 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d14272-bab6-0a2a0a5309dd-0a2a450ca3fc-34 for ; Sat, 04 Apr 2026 18:56:27 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d142b9-f40c-0a2a450c0019-aceafc1fa3d6-3 for ; Sat, 04 Apr 2026 18:56:27 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id C91694059C; Sat, 4 Apr 2026 16:56:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A189EC19421; Sat, 4 Apr 2026 16:56:09 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:From:To:Cc:References:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775321784; bh=z0EKK9uCRclvxyjrhd1+SN0RRq/OFfBzrXy9eOqqb1Y=; h=Date:Subject:From:To:Cc:References:In-Reply-To:From; b=Pvkgz2VYtss1MeKDd1hCnXOqFhZSJT7sCBgib4Ld40MuoHbsbTzaQtqEQlHI315/z sSsTrUhsdTJPdFsI6MsazCxIagVra3Yz7Nj6ieza8kV78SqaqqkR1jw4ERelqbogu8 P2C5HKTLPE156wtoOmaEhBjNWmWs1/5XjIm7Pn+IztUEvzTxOWgE4ijDSgxwxt7sHW /z+by/VjXh6iXK4C6vfLmsq7Ld8muhOBjOIJmJuiMgdiDbMtkSfkPxjp0+PDXt64DF SAsEhipno3UJ1XHvp0XZyChIymjhWJhckqoZh6Dfi1SExI1b8SJikdcJieSIN27yIj n1QGwKpOYjS/A== Message-ID: Date: Sat, 4 Apr 2026 18:56:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/12] bus: fsl-mc: use generic driver_override infrastructure From: "Christophe Leroy (CS GROUP)" To: Ioana Ciornei , Danilo Krummrich Cc: Russell King , Greg Kroah-Hartman , "Rafael J. Wysocki" , Nipun Gupta , Nikhil Agarwal , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Bjorn Helgaas , Armin Wolf , Bjorn Andersson , Mathieu Poirier , Vineeth Vijayan , Peter Oberparleiter , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Harald Freudenberger , Holger Dengler , Mark Brown , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C4=82=C2=A9rez?= , Alex Williamson , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org, linux-spi@vger.kernel.org, virtualization@lists.linux.dev, kvm@vger.kernel.org, xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, Gui-Dong Han References: <20260324005919.2408620-1-dakr@kernel.org> <20260324005919.2408620-3-dakr@kernel.org> <4c5e9bad-82f0-4714-99c2-8ccd79a45043@kernel.org> Content-Language: fr-FR In-Reply-To: <4c5e9bad-82f0-4714-99c2-8ccd79a45043@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775321787-81F52A3D-CE7E2EFD/0/0 X-purgate-type: clean X-purgate-size: 3496 Le 28/03/2026 à 13:10, Christophe Leroy (CS GROUP) a écrit : > > > Le 25/03/2026 à 13:01, Ioana Ciornei a écrit : >> On Tue, Mar 24, 2026 at 01:59:06AM +0100, Danilo Krummrich wrote: >>> When a driver is probed through __driver_attach(), the bus' match() >>> callback is called without the device lock held, thus accessing the >>> driver_override field without a lock, which can cause a UAF. >>> >>> Fix this by using the driver-core driver_override infrastructure taking >>> care of proper locking internally. >>> >>> Note that calling match() from __driver_attach() without the device lock >>> held is intentional. [1] >>> >>> Link: https://eur01.safelinks.protection.outlook.com/? >>> url=https%3A%2F%2Flore.kernel.org%2Fdriver- >>> core%2FDGRGTIRHA62X.3RY09D9SOK77P%40kernel.org%2F&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7C4b9262ddecdd4ce29f9808de8a66485e%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639100369055903282%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BRfjlUkq7oWV%2F0v2S2B%2BEuxCY%2FLRQv6qHiEWiupd6kc%3D&reserved=0 [1] >>> Reported-by: Gui-Dong Han >>> Closes: https://eur01.safelinks.protection.outlook.com/? >>> url=https%3A%2F%2Fbugzilla.kernel.org%2Fshow_bug.cgi%3Fid%3D220789&data=05%7C02%7Cchristophe.leroy%40csgroup.eu%7C4b9262ddecdd4ce29f9808de8a66485e%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639100369055936232%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=XL1K1ICiygOZnlvDUbQFe192KnLsBQms0HFNGCuyz%2Fw%3D&reserved=0 >>> Fixes: 1f86a00c1159 ("bus/fsl-mc: add support for 'driver_override' >>> in the mc-bus") >>> Signed-off-by: Danilo Krummrich >> >> Tested-by: Ioana Ciornei >> Signed-off-by: Ioana Ciornei >> > > > Applied, thanks Have to drop it for now, build fails: CALL scripts/checksyscalls.sh CC drivers/bus/fsl-mc/fsl-mc-bus.o drivers/bus/fsl-mc/fsl-mc-bus.c: In function 'fsl_mc_bus_match': drivers/bus/fsl-mc/fsl-mc-bus.c:92:15: error: implicit declaration of function 'device_match_driver_override' [-Werror=implicit-function-declaration] 92 | ret = device_match_driver_override(dev, drv); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/bus/fsl-mc/fsl-mc-bus.c: At top level: drivers/bus/fsl-mc/fsl-mc-bus.c:321:10: error: 'const struct bus_type' has no member named 'driver_override' 321 | .driver_override = true, | ^~~~~~~~~~~~~~~ drivers/bus/fsl-mc/fsl-mc-bus.c:321:28: warning: initialization of 'const char *' from 'int' makes pointer from integer without a cast [-Wint-conversion] 321 | .driver_override = true, | ^~~~ drivers/bus/fsl-mc/fsl-mc-bus.c:321:28: note: (near initialization for 'fsl_mc_bus_type.dev_name') cc1: some warnings being treated as errors make[5]: *** [scripts/Makefile.build:289: drivers/bus/fsl-mc/fsl-mc-bus.o] Error 1 make[4]: *** [scripts/Makefile.build:546: drivers/bus/fsl-mc] Error 2 make[3]: *** [scripts/Makefile.build:546: drivers/bus] Error 2 make[2]: *** [scripts/Makefile.build:546: drivers] Error 2 make[1]: *** [/home/chleroy/linux-powerpc/Makefile:2101: .] Error 2 make: *** [Makefile:248: __sub-make] Error 2 Christophe From xen-devel-bounces@lists.xenproject.org Sat Apr 04 16:59:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 16:59:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273825.1560300 (Exim 4.92) (envelope-from ) id 1w94L4-0007sP-Pq; Sat, 04 Apr 2026 16:59:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273825.1560300; Sat, 04 Apr 2026 16:59:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94L4-0007sI-N3; Sat, 04 Apr 2026 16:59:14 +0000 Received: by outflank-mailman (input) for mailman id 1273825; Sat, 04 Apr 2026 16:59:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94L3-0007sB-5J for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 16:59:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w94L2-003sNx-Hl for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 18:59:12 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d1430e-bab6-0a2a0a5309dd-0a2a4505c9c6-22 for ; Sat, 04 Apr 2026 18:59:12 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d1435e-3760-0a2a45050019-aceafc1fd69e-3 for ; Sat, 04 Apr 2026 18:59:12 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 0732D40212; Sat, 4 Apr 2026 16:59:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6DDF2C19421; Sat, 4 Apr 2026 16:58:54 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775321949; bh=2nmDBifOoextQmoTG695I77JtU4IfJ6hHi18F/uovOA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=pzHa0ltJ7P/3nc4QK7/bV808HOZOGXaMyVekR/DB1WE+018orzHWLwztSYy1/aXtb SzI8tsEInej9eoHjBzyIJaVGBr9u74dLFfrXcTThineYb99ODPDwsaOS5PNoPpADEf RKWNJ7Ic0kSfp5FmUOXVQ6PFQBKcfI9b1bar1hvVu+oDjNbThyquuuXTFP/2f4hh2r sNZXBYXoEYlp3D9Lzsjn9fgXUhLg5zak6jG42FprWSVJLQdnerHFANSStlrij56Tl/ nq4W3Agf2uSQ+xhFuLGyUpc0A63CtjXoWAelZzEtiaPysfp3k4jpj5PHDxaigPyBx2 FsekL+yzYor6g== Message-ID: <76355cb5-0b5d-4a29-9702-8d020a79f4c0@kernel.org> Date: Sat, 4 Apr 2026 18:58:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: (subset) [PATCH 00/12] treewide: Convert buses to use generic driver_override To: Danilo Krummrich , Russell King , Greg Kroah-Hartman , "Rafael J. Wysocki" , Ioana Ciornei , Nipun Gupta , Nikhil Agarwal , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Bjorn Helgaas , Armin Wolf , Bjorn Andersson , Mathieu Poirier , Vineeth Vijayan , Peter Oberparleiter , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Harald Freudenberger , Holger Dengler , Mark Brown , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= , Alex Williamson , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , "Christophe Leroy (CS GROUP)" Cc: linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org, linux-spi@vger.kernel.org, virtualization@lists.linux.dev, kvm@vger.kernel.org, xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org References: <20260324005919.2408620-1-dakr@kernel.org> Content-Language: fr-FR From: "Christophe Leroy (CS GROUP)" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775321952-2292196F-DDB74BE1/0/0 X-purgate-type: clean X-purgate-size: 1207 Le 04/04/2026 à 17:07, Danilo Krummrich a écrit : > On Tue Mar 24, 2026 at 1:59 AM CET, Danilo Krummrich wrote: >> Danilo Krummrich (12): >> PCI: use generic driver_override infrastructure >> platform/wmi: use generic driver_override infrastructure >> vdpa: use generic driver_override infrastructure >> s390/cio: use generic driver_override infrastructure >> s390/ap: use generic driver_override infrastructure > > Applied to driver-core-testing, thanks! > >> amba: use generic driver_override infrastructure >> cdx: use generic driver_override infrastructure >> hv: vmbus: use generic driver_override infrastructure >> rpmsg: use generic driver_override infrastructure > > I have not picked these up, as they have not received ACKs from the > corresponding subsystem maintainers so far. > >> bus: fsl-mc: use generic driver_override infrastructure I droped it from soc_fsl tree, some dependency must be missing. Feal free to take it if you can, it is acked-by Ioana. >> spi: use generic driver_override infrastructure > > These have already been picked up via the respective subsystem trees -- thanks! > > Thanks, > Danilo From xen-devel-bounces@lists.xenproject.org Sat Apr 04 17:04:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 17:04:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273841.1560310 (Exim 4.92) (envelope-from ) id 1w94QG-00012d-C5; Sat, 04 Apr 2026 17:04:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273841.1560310; Sat, 04 Apr 2026 17:04:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94QG-00012W-9N; Sat, 04 Apr 2026 17:04:36 +0000 Received: by outflank-mailman (input) for mailman id 1273841; Sat, 04 Apr 2026 17:04:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94QF-00012Q-TT for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 17:04:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w94QF-003tOI-9E for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 19:04:35 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d14455-bab6-0a2a0a5309dd-0a2a450aece0-24 for ; Sat, 04 Apr 2026 19:04:35 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d144a1-ee98-0a2a450a0019-aceafc1f9a0c-3 for ; Sat, 04 Apr 2026 19:04:34 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 979924060D; Sat, 4 Apr 2026 17:04:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6663AC19421; Sat, 4 Apr 2026 17:04:23 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Cc:To:From:Subject:References:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775322272; bh=7PzP6n6U4E9ZflmrRkBSMwOeYsGN0d+ge+8bYc26zsY=; h=Date:Cc:To:From:Subject:References:In-Reply-To:From; b=fe5eJq1d99JHNmPB8IpFig8PRyyyj5sltf3KPYrDsk0N8TKZGpBePJLkrkPDItx5u OD9XiP1BsdzxhDnieDTpdRavUaIxIOsfwema+FPuAf2OftNWG3RNzfc/+E74+vzYXL hr6gl/9eoMudVQ+SB7i9KoJ64jNeCH7KBFn19c9SoYtuyJxnlnjg/gnFezKFCEM8UT pXBEauClp409xFE/+hMuTZWOGegzPULPyvlbewkUUrLyfkmmluI/xnbmAAlztMocbH 5TCceEPtW/9Z41b0BUe5ZnMFG66SCb9IcaE5AfJKxdvb9nrxftJLbDrCkbK9ayIBu8 7zufDNhS7HSYw== Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 04 Apr 2026 19:04:21 +0200 Message-Id: Cc: "Russell King" , "Greg Kroah-Hartman" , "Rafael J. Wysocki" , "Ioana Ciornei" , "Nipun Gupta" , "Nikhil Agarwal" , "K. Y. Srinivasan" , "Haiyang Zhang" , "Wei Liu" , "Dexuan Cui" , "Long Li" , "Bjorn Helgaas" , "Armin Wolf" , "Bjorn Andersson" , "Mathieu Poirier" , "Vineeth Vijayan" , "Peter Oberparleiter" , "Heiko Carstens" , "Vasily Gorbik" , "Alexander Gordeev" , "Christian Borntraeger" , "Sven Schnelle" , "Harald Freudenberger" , "Holger Dengler" , "Mark Brown" , "Michael S. Tsirkin" , "Jason Wang" , "Xuan Zhuo" , =?utf-8?q?Eugenio_P=C3=A9rez?= , "Alex Williamson" , "Juergen Gross" , "Stefano Stabellini" , "Oleksandr Tyshchenko" , , , , , , , , , , , , , , To: "Christophe Leroy (CS GROUP)" From: "Danilo Krummrich" Subject: Re: (subset) [PATCH 00/12] treewide: Convert buses to use generic driver_override References: <20260324005919.2408620-1-dakr@kernel.org> <76355cb5-0b5d-4a29-9702-8d020a79f4c0@kernel.org> In-Reply-To: <76355cb5-0b5d-4a29-9702-8d020a79f4c0@kernel.org> X-purgate-ID: tlsNG-4011c0/1775322275-C481C0B1-1A2EBE86/0/0 X-purgate-type: clean X-purgate-size: 1399 On Sat Apr 4, 2026 at 6:58 PM CEST, Christophe Leroy (CS GROUP) wrote: > > > Le 04/04/2026 =C3=A0 17:07, Danilo Krummrich a =C3=A9crit=C2=A0: >> On Tue Mar 24, 2026 at 1:59 AM CET, Danilo Krummrich wrote: >>> Danilo Krummrich (12): >>> PCI: use generic driver_override infrastructure >>> platform/wmi: use generic driver_override infrastructure >>> vdpa: use generic driver_override infrastructure >>> s390/cio: use generic driver_override infrastructure >>> s390/ap: use generic driver_override infrastructure >>=20 >> Applied to driver-core-testing, thanks! >>=20 >>> amba: use generic driver_override infrastructure >>> cdx: use generic driver_override infrastructure >>> hv: vmbus: use generic driver_override infrastructure >>> rpmsg: use generic driver_override infrastructure >>=20 >> I have not picked these up, as they have not received ACKs from the >> corresponding subsystem maintainers so far. >>=20 >>> bus: fsl-mc: use generic driver_override infrastructure > > I droped it from soc_fsl tree, some dependency must be missing. > > Feal free to take it if you can, it is acked-by Ioana. It is based on v7.0-rc5; if you want I can pick it up. >>> spi: use generic driver_override infrastructure >>=20 >> These have already been picked up via the respective subsystem trees -- = thanks! >>=20 >> Thanks, >> Danilo From xen-devel-bounces@lists.xenproject.org Sat Apr 04 17:12:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 17:12:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273859.1560319 (Exim 4.92) (envelope-from ) id 1w94Xw-0002ps-5b; Sat, 04 Apr 2026 17:12:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273859.1560319; Sat, 04 Apr 2026 17:12:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94Xw-0002pl-2v; Sat, 04 Apr 2026 17:12:32 +0000 Received: by outflank-mailman (input) for mailman id 1273859; Sat, 04 Apr 2026 17:12:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w94Xv-0002pf-3c for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 17:12:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w94Xu-00CKAX-GC for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 19:12:30 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d14646-e002-0a2a0a5209dd-0a2a4508e3d0-20 for ; Sat, 04 Apr 2026 19:12:30 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d145c8-fab6-0a2a45080019-aceafc1fc7d0-3 for ; Sat, 04 Apr 2026 19:09:29 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id AE6C643C1D; Sat, 4 Apr 2026 17:09:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6956BC19421; Sat, 4 Apr 2026 17:09:12 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775322567; bh=u8kt7OrQ/vRwebR8QID4XnX8+JNDMp1i5iK/K6bdNDA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Mur2l9g+deVKWOVOfXlkgvgdKFA4eMN3VFsDjrp+nvoKeM3X3pstiyexcKEvOeD0a RbWpztozc0h4lQoSWYVOnXtkhFF+JRtMTTya2FNPQi3D7loBz93/IYN7Ge2fCwnYY6 Re4J05NhHq8kCVMn7SJKTXcUdNw54AUQcOdwffM3zMjz7evbLjl/s54+7J+0y2RhZM +Mi+DO81POzfix85rvYo25MmliRWwTmiQ4w8GEjh3lU6Bg01dUBrobNBgfy2tPEGch AFl8Q1R0jHMSDedYpY3Yug+qqjGh5y0LuX4UV4lD2NPGO2GuUGdy7lPrJwFQklpETH wOUF3U6ODslbQ== Message-ID: Date: Sat, 4 Apr 2026 19:09:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: (subset) [PATCH 00/12] treewide: Convert buses to use generic driver_override To: Danilo Krummrich Cc: Russell King , Greg Kroah-Hartman , "Rafael J. Wysocki" , Ioana Ciornei , Nipun Gupta , Nikhil Agarwal , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Bjorn Helgaas , Armin Wolf , Bjorn Andersson , Mathieu Poirier , Vineeth Vijayan , Peter Oberparleiter , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Harald Freudenberger , Holger Dengler , Mark Brown , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= , Alex Williamson , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , linux-kernel@vger.kernel.org, driver-core@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, linux-s390@vger.kernel.org, linux-spi@vger.kernel.org, virtualization@lists.linux.dev, kvm@vger.kernel.org, xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org References: <20260324005919.2408620-1-dakr@kernel.org> <76355cb5-0b5d-4a29-9702-8d020a79f4c0@kernel.org> Content-Language: fr-FR From: "Christophe Leroy (CS GROUP)" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775322570-F7B44497-16658D0D/37/8700017816-1414974 X-purgate-type: clean X-purgate-size: 1558 Le 04/04/2026 à 19:04, Danilo Krummrich a écrit : > On Sat Apr 4, 2026 at 6:58 PM CEST, Christophe Leroy (CS GROUP) wrote: >> >> >> Le 04/04/2026 à 17:07, Danilo Krummrich a écrit : >>> On Tue Mar 24, 2026 at 1:59 AM CET, Danilo Krummrich wrote: >>>> Danilo Krummrich (12): >>>> PCI: use generic driver_override infrastructure >>>> platform/wmi: use generic driver_override infrastructure >>>> vdpa: use generic driver_override infrastructure >>>> s390/cio: use generic driver_override infrastructure >>>> s390/ap: use generic driver_override infrastructure >>> >>> Applied to driver-core-testing, thanks! >>> >>>> amba: use generic driver_override infrastructure >>>> cdx: use generic driver_override infrastructure >>>> hv: vmbus: use generic driver_override infrastructure >>>> rpmsg: use generic driver_override infrastructure >>> >>> I have not picked these up, as they have not received ACKs from the >>> corresponding subsystem maintainers so far. >>> >>>> bus: fsl-mc: use generic driver_override infrastructure >> >> I droped it from soc_fsl tree, some dependency must be missing. >> >> Feal free to take it if you can, it is acked-by Ioana. > > It is based on v7.0-rc5; if you want I can pick it up. Yes please pick it up as my tree is based on rc1. Thanks Christophe > >>>> spi: use generic driver_override infrastructure >>> >>> These have already been picked up via the respective subsystem trees -- thanks! >>> >>> Thanks, >>> Danilo > From xen-devel-bounces@lists.xenproject.org Sat Apr 04 19:20:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 04 Apr 2026 19:20:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273911.1560327 (Exim 4.92) (envelope-from ) id 1w96Xm-0001xN-1r; Sat, 04 Apr 2026 19:20:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273911.1560327; Sat, 04 Apr 2026 19:20:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w96Xl-0001xG-V8; Sat, 04 Apr 2026 19:20:29 +0000 Received: by outflank-mailman (input) for mailman id 1273911; Sat, 04 Apr 2026 19:20:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w96Xk-0001xA-6N for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 19:20:28 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w96Xi-00BNq2-RA for xen-devel@lists.xenproject.org; Sat, 04 Apr 2026 21:20:26 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d16411-5cb7-0a2a0a5109dd-0a2a4503d914-28 for ; Sat, 04 Apr 2026 21:20:26 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d16479-02b3-0a2a45030019-aceafc1f9f56-3 for ; Sat, 04 Apr 2026 21:20:26 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 1359541720; Sat, 4 Apr 2026 19:20:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00214C19421; Sat, 4 Apr 2026 19:20:14 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:Cc:To:From:References:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775330423; bh=Gm9FGkRc1QRpNSImSwgwSEPvOU2SLgI61ARuYW5LgUM=; h=Date:Subject:Cc:To:From:References:In-Reply-To:From; b=jmGUx9ea8KKZGI+yk4InrpqyltSpIFXbxzumeqJLrPMsCCsI1AmriWu84nJMybHDm YQX3Ac/MMmi2g9ubzYQwGTmoLjoD5HvqXXGENZ7sZF+bdgDoJQgXEb5+YyoFBlZFth rIDl6Or9j72Pxfg8gbRbLoxXUMFAACLFbQ4DfxU/vKJfbDZ88r7qcAUikXvNARJnPR UKzC1aGXBRx4bgxjkQ5ETAqx1gHtveCsTmzJzi7+wf9pVTh4t9trQOG4pictre3Zqy coxYtZTwXCoUTOSXcrTxyqOyBWyu2eDrD5N4/86+0enySLlkVbuU3KeCQL6A1XpL4u dWWtgOZ4j3TJA== Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sat, 04 Apr 2026 21:20:13 +0200 Message-Id: Subject: Re: (subset) [PATCH 00/12] treewide: Convert buses to use generic driver_override Cc: "Russell King" , "Greg Kroah-Hartman" , "Rafael J. Wysocki" , "Ioana Ciornei" , "Nipun Gupta" , "Nikhil Agarwal" , "K. Y. Srinivasan" , "Haiyang Zhang" , "Wei Liu" , "Dexuan Cui" , "Long Li" , "Bjorn Helgaas" , "Armin Wolf" , "Bjorn Andersson" , "Mathieu Poirier" , "Vineeth Vijayan" , "Peter Oberparleiter" , "Heiko Carstens" , "Vasily Gorbik" , "Alexander Gordeev" , "Christian Borntraeger" , "Sven Schnelle" , "Harald Freudenberger" , "Holger Dengler" , "Mark Brown" , "Michael S. Tsirkin" , "Jason Wang" , "Xuan Zhuo" , =?utf-8?q?Eugenio_P=C3=A9rez?= , "Alex Williamson" , "Juergen Gross" , "Stefano Stabellini" , "Oleksandr Tyshchenko" , , , , , , , , , , , , , , To: "Christophe Leroy (CS GROUP)" From: "Danilo Krummrich" References: <20260324005919.2408620-1-dakr@kernel.org> <76355cb5-0b5d-4a29-9702-8d020a79f4c0@kernel.org> In-Reply-To: X-purgate-ID: tlsNG-33051d/1775330426-42319C9A-8B47D58F/0/0 X-purgate-type: clean X-purgate-size: 178 On Sat Apr 4, 2026 at 7:09 PM CEST, Christophe Leroy (CS GROUP) wrote: > Yes please pick it up as my tree is based on rc1. Applied the patch to driver-core-testing, thanks! From xen-devel-bounces@lists.xenproject.org Sun Apr 05 02:15:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 05 Apr 2026 02:15:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1273969.1560361 (Exim 4.92) (envelope-from ) id 1w9D11-0007LJ-Fc; Sun, 05 Apr 2026 02:15:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1273969.1560361; Sun, 05 Apr 2026 02:15:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9D11-0007LB-AN; Sun, 05 Apr 2026 02:15:07 +0000 Received: by outflank-mailman (input) for mailman id 1273969; Sun, 05 Apr 2026 02:15:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9D10-0007L2-Kz for xen-devel@lists.xenproject.org; Sun, 05 Apr 2026 02:15:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9D0y-00HESx-8N for xen-devel@lists.xenproject.org; Sun, 05 Apr 2026 04:15:04 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d1c4b5-e002-0a2a0a5209dd-0a2a4504aa54-36 for ; Sun, 05 Apr 2026 04:15:02 +0200 Received: from [159.226.251.21] (helo=cstnet.cn) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d1c5a3-bb33-0a2a45040019-9fe2fb15c5ca-3 for ; Sun, 05 Apr 2026 04:15:01 +0200 Received: from 0005-arm-xen-v2.eml (unknown [111.196.245.197]) by APP-01 (Coremail) with SMTP id qwCowADnjGihxdFpUAU5DA--.3582S2; Sun, 05 Apr 2026 10:14:57 +0800 (CST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Pengpeng Hou Date: Sun, 5 Apr 2026 08:42:00 +0800 Message-ID: <20260405094005.5-arm-xen-v2-pengpeng@iscas.ac.cn> To: Stefano Stabellini Cc: xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pengpeng@iscas.ac.cn In-Reply-To: <20260403111502.2-dt-arm-xen-pengpeng@iscas.ac.cn> References: <20260403111502.2-dt-arm-xen-pengpeng@iscas.ac.cn> Subject: [PATCH v2] ARM: xen: validate hypervisor compatible before parsing its version X-CM-TRANSID:qwCowADnjGihxdFpUAU5DA--.3582S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Zr4rKFW7Jw13Zryxtry5urg_yoW8CFyDpF WFg3sIvFWfta4xW34IyFWDWFy5G3WkXrW7XFyku3W7Ars8t34rKrW2qr1SvF93Ary8G3ya vrW0yF18AF4UJaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr 1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IY64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkF7I0En4kS14v26r12 6r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI 0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y 0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxV W8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1l IxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjiID7UUUU U== X-Originating-IP: [111.196.245.197] X-CM-SenderInfo: pshqw1xhqjqxpvfd2hldfou0/ X-purgate-ID: tlsNG-ebf023/1775355302-3152351B-AFCB4424/0/0 X-purgate-type: clean X-purgate-size: 1932 fdt_find_hyper_node() reads the raw compatible property and then derives hyper_node.version from a prefix match before later printing it with %s. Flat DT properties are external boot input, and this path does not prove that the first compatible entry is NUL-terminated within the returned property length. Keep the existing flat-DT lookup path, but verify that the first compatible entry terminates within the returned property length before deriving the version suffix from it. Signed-off-by: Pengpeng Hou --- Changes since v1: - keep `of_get_flat_dt_prop()` instead of switching to `fdt_stringlist_get()` - validate the first compatible entry with bounded `strnlen()` arch/arm/xen/enlighten.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 4feed2c2..25a0ce3b 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -218,8 +218,9 @@ static __initdata struct { static int __init fdt_find_hyper_node(unsigned long node, const char *uname, int depth, void *data) { - const void *s = NULL; + const char *s = NULL; int len; + size_t prefix_len = strlen(hyper_node.prefix); if (depth != 1 || strcmp(uname, "hypervisor") != 0) return 0; @@ -228,9 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, hyper_node.found = true; s = of_get_flat_dt_prop(node, "compatible", &len); - if (strlen(hyper_node.prefix) + 3 < len && - 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xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 Message-ID: References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="C0DK1UxqrVq6HEXJ" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-c201ff/1775382087-3999196F-EEBA8345/0/0 X-purgate-type: clean X-purgate-size: 11170 --C0DK1UxqrVq6HEXJ Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Sun, 5 Apr 2026 11:41:18 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Kevin Brodsky Cc: Andrew Cooper , xen-devel , Boris Ostrovsky Subject: Re: kernel BUG around vmap/vfree - xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 On Thu, Feb 26, 2026 at 02:41:12PM +0100, J=C3=BCrgen Gro=C3=9F wrote: > On 26.02.26 14:27, Andrew Cooper wrote: > > On 26/02/2026 1:17 pm, Marek Marczykowski-G=C3=B3recki wrote: > > > Hi, > > >=20 > > > When testing Linux 7.0-rc1 in PV dom0, I hit the following panic > > > sometimes: > > >=20 > > > [ 436.849614] ------------[ cut here ]------------ > > > [ 436.849669] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:78! > > > [ 436.849693] Oops: invalid opcode: 0000 [#1] SMP NOPTI > > > [ 436.849710] CPU: 3 UID: 0 PID: 4021 Comm: kworker/u25:1 Not tainte= d 7.0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) > > > [ 436.849729] Hardware name: Star Labs StarBook/StarBook, BIOS 8.97 = 10/03/2023 > > > [ 436.849743] Workqueue: i915_flip intel_atomic_commit_work [i915] > > > [ 436.850226] RIP: e030:xen_enter_lazy_mmu+0x24/0x30 > > > [ 436.850245] Code: 90 90 90 90 90 90 f3 0f 1e fa 0f 1f 44 00 00 65 = 8b 05 b8 e5 02 03 85 c0 75 10 65 c7 05 a9 e5 02 03 01 00 00 00 c3 cc cc cc = cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90 > > > [ 436.850270] RSP: e02b:ffffc90045727a68 EFLAGS: 00010202 > > > [ 436.850283] RAX: 0000000000000001 RBX: ffff8881042fa6d0 RCX: 000ff= fffffe00000 > > > [ 436.850296] RDX: 0000000000000001 RSI: ffff88810a5a2980 RDI: 00000= 00000000000 > > > [ 436.850308] RBP: ffffc90049eda000 R08: ffffc90049edc000 R09: ffffc= 90049edc000 > > > [ 436.850320] R10: ffffc90049edc000 R11: ffffc90049edbfff R12: ffffc= 90049edc000 > > > [ 436.850332] R13: ffffc90045727bb0 R14: ffffc90045727b28 R15: 80000= 0000000006b > > > [ 436.850356] FS: 0000000000000000(0000) GS:ffff888201e6e000(0000) = knlGS:0000000000000000 > > > [ 436.850371] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 > > > [ 436.850383] CR2: 00006543dbade250 CR3: 0000000115ef1000 CR4: 00000= 00000050660 > > > [ 436.850401] Call Trace: > > > [ 436.850410] > > > [ 436.850420] vmap_pages_pud_range+0x47c/0x530 > > > [ 436.850439] vmap_small_pages_range_noflush+0x1f1/0x2b0 > > > [ 436.850451] ? __get_vm_area_node+0x10a/0x170 > > > [ 436.850465] vmap+0x79/0xd0 > > > [ 436.850476] i915_gem_object_map_page+0x13b/0x210 [i915] > > > [ 436.850812] i915_gem_object_pin_map+0x1e2/0x210 [i915] > > > [ 436.851123] i915_gem_object_pin_map_unlocked+0x2d/0xa0 [i915] > > > [ 436.851424] intel_dsb_buffer_create+0xed/0x1a0 [i915] > > > [ 436.851778] intel_dsb_prepare+0xca/0x1a0 [i915] > > > [ 436.852110] intel_atomic_dsb_finish+0x92/0x350 [i915] > > > [ 436.852456] intel_atomic_commit_tail+0x326/0xd40 [i915] > > > [ 436.852769] process_one_work+0x18d/0x380 > > > [ 436.852779] worker_thread+0x196/0x300 > > > [ 436.852787] ? __pfx_worker_thread+0x10/0x10 > > > [ 436.852796] kthread+0xe3/0x120 > > > [ 436.852805] ? __pfx_kthread+0x10/0x10 > > > [ 436.852815] ret_from_fork+0x19e/0x260 > > > [ 436.852824] ? __pfx_kthread+0x10/0x10 > > > [ 436.852832] ret_from_fork_asm+0x1a/0x30 > > > [ 436.852842] > > > [ 436.852847] Modules linked in: snd_seq_dummy snd_hrtimer snd_hda_c= odec_intelhdmi snd_hda_codec_hdmi snd_hda_codec_alc269 snd_hda_codec_realte= k_lib snd_hda_scodec_component snd_hda_codec_generic snd_hda_intel snd_sof_= pci_intel_tgl snd_sof_pci_intel_cnl snd_sof_intel_hda_generic soundwire_int= el snd_sof_intel_hda_sdw_bpt snd_sof_intel_hda_common snd_soc_hdac_hda snd_= sof_intel_hda_mlink snd_sof_intel_hda soundwire_cadence snd_sof_pci snd_sof= _xtensa_dsp snd_sof snd_sof_utils snd_soc_acpi_intel_match snd_soc_acpi_int= el_sdca_quirks soundwire_generic_allocation snd_soc_sdw_utils snd_soc_acpi = crc8 intel_rapl_msr soundwire_bus intel_rapl_common snd_soc_sdca snd_soc_av= s snd_soc_hda_codec snd_hda_ext_core snd_hda_codec vfat intel_uncore_freque= ncy_common fat snd_hda_core snd_intel_dspcfg snd_intel_sdw_acpi snd_hwdep i= ntel_powerclamp snd_soc_core iwlwifi snd_compress spi_nor iTCO_wdt ac97_bus= intel_pmc_bxt ee1004 mtd snd_pcm_dmaengine snd_seq cfg80211 snd_seq_device= pcspkr spi_intel_pci snd_pcm rfkill spi_intel snd_timer snd > > > [ 436.852939] i2c_i801 soundcore i2c_smbus idma64 intel_pmc_core pm= t_telemetry pmt_discovery pmt_class intel_hid intel_pmc_ssram_telemetry int= el_scu_pltdrv sparse_keymap joydev loop fuse xenfs nfnetlink vsock_loopback= vmw_vsock_virtio_transport_common vmw_vsock_vmci_transport vsock zram vmw_= vmci lz4hc_compress lz4_compress dm_thin_pool dm_persistent_data dm_bio_pri= son dm_crypt xe drm_ttm_helper drm_suballoc_helper gpu_sched drm_gpuvm drm_= exec drm_gpusvm_helper i915 i2c_algo_bit drm_buddy hid_multitouch i2c_hid_a= cpi ghash_clmulni_intel video nvme wmi ttm i2c_hid nvme_core nvme_keyring d= rm_display_helper nvme_auth xhci_pci pinctrl_tigerlake thunderbolt hkdf cec= xhci_hcd intel_vsec serio_raw xen_acpi_processor xen_privcmd xen_pciback x= en_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_dh_rdac scsi_dh_emc scsi= _dh_alua uinput i2c_dev > > > [ 436.853183] ---[ end trace 0000000000000000 ]--- > > >=20 > > > or this: > > >=20 > > > [ 548.736884] ------------[ cut here ]------------ > > > [ 548.736907] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:85! > > > [ 548.736923] Oops: invalid opcode: 0000 [#1] SMP NOPTI > > > [ 548.736935] CPU: 0 UID: 0 PID: 206 Comm: kworker/0:2 Not tainted 7= =2E0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) > > > [ 548.736949] Hardware name: LENOVO 2347A45/2347A45, BIOS CBET4000 N= itrokey-v0.2.0-2608-ga649597 01/01/1970 > > > [ 548.736962] Workqueue: events delayed_vfree_work > > > [ 548.736976] RIP: e030:xen_leave_lazy_mmu+0x44/0x50 > > > [ 548.736989] Code: 02 03 83 f8 01 75 23 65 c7 05 6c e4 02 03 00 00 = 00 00 65 ff 0d 7d b8 02 03 74 05 c3 cc cc cc cc e8 61 5d fd ff c3 cc cc cc = cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90 > > > [ 548.737010] RSP: e02b:ffffc90040607cf0 EFLAGS: 00010297 > > > [ 548.737018] RAX: 0000000000000000 RBX: ffff888164a70408 RCX: 00000= 00000000000 > > > [ 548.737029] RDX: 0000000000000000 RSI: 000ffffffffff000 RDI: ffff8= 881069c0000 > > > [ 548.737039] RBP: ffffc90049681000 R08: ffffc90049681000 R09: 00000= 00000000027 > > > [ 548.737050] R10: 0000000000000027 R11: fefefefefefefeff R12: ffffc= 90049681000 > > > [ 548.737060] R13: ffff8881002fd258 R14: 0000000000000000 R15: ffffc= 90040607dac > > > [ 548.737079] FS: 0000000000000000(0000) GS:ffff8881f88ee000(0000) = knlGS:0000000000000000 > > > [ 548.737090] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 > > > [ 548.737099] CR2: 000055576c2e6058 CR3: 000000010d47b000 CR4: 00000= 00000050660 > > > [ 548.737115] Call Trace: > > > [ 548.737123] > > > [ 548.737128] vunmap_pmd_range.isra.0+0x1f1/0x2e0 > > > [ 548.737142] vunmap_p4d_range+0x17d/0x290 > > > [ 548.737151] __vunmap_range_noflush+0x182/0x1d0 > > > [ 548.737161] ? _raw_spin_unlock+0xe/0x30 > > > [ 548.737171] remove_vm_area+0x40/0x70 > > > [ 548.737180] vfree.part.0+0x1b/0x290 > > > [ 548.737189] delayed_vfree_work+0x35/0x50 > > > [ 548.737198] process_one_work+0x18d/0x380 > > > [ 548.737207] worker_thread+0x196/0x300 > > > [ 548.737215] ? __pfx_worker_thread+0x10/0x10 > > > [ 548.737224] kthread+0xe3/0x120 > > > [ 548.737233] ? __pfx_kthread+0x10/0x10 > > > [ 548.737242] ret_from_fork+0x19e/0x260 > > > [ 548.737250] ? __pfx_kthread+0x10/0x10 > > > [ 548.737258] ret_from_fork_asm+0x1a/0x30 > > > [ 548.737269] > > > [ 548.737274] Modules linked in: vfat fat snd_seq_dummy snd_hrtimer = ath9k ath9k_common snd_hda_codec_intelhdmi snd_hda_codec_hdmi ath9k_hw snd_= hda_codec_alc269 snd_hda_codec_realtek_lib snd_hda_scodec_component snd_hda= _codec_generic snd_hda_intel snd_hda_codec mac80211 snd_hda_core snd_intel_= dspcfg snd_intel_sdw_acpi snd_hwdep ath snd_seq snd_seq_device snd_ctl_led = cfg80211 snd_pcm at24 thinkpad_acpi intel_rapl_msr i2c_i801 snd_timer spars= e_keymap iTCO_wdt intel_rapl_common platform_profile intel_powerclamp intel= _pmc_bxt pcspkr i2c_smbus rfkill libarc4 snd soundcore mei_me e1000e mei jo= ydev lpc_ich loop fuse xenfs nfnetlink vsock_loopback vmw_vsock_virtio_tran= sport_common vmw_vsock_vmci_transport vsock zram vmw_vmci lz4hc_compress lz= 4_compress dm_thin_pool dm_persistent_data dm_bio_prison dm_crypt i915 i2c_= algo_bit drm_buddy ghash_clmulni_intel ttm sdhci_pci drm_display_helper sdh= ci_uhs2 sdhci video xhci_pci cqhci wmi cec xhci_hcd ehci_pci mmc_core ehci_= hcd serio_raw xen_acpi_processor xen_privcmd xen_pciback > > > [ 548.737348] xen_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_d= h_rdac scsi_dh_emc scsi_dh_alua uinput i2c_dev > > > [ 548.737469] ---[ end trace 0000000000000000 ]--- > > >=20 > > > I don't have clear pattern when this happens, one was during host > > > suspend, but the other was during "normal" test run (starting/stopping > > > domUs and running stuff around them). Note also one of those is Intel > > > and the other AMD, so it isn't really hardware specific. > > >=20 > > > Slightly more details with links (especially serial0.txt in the logs > > > tab) at > > > https://github.com/QubesOS/qubes-linux-kernel/pull/662#issuecomment-3= 963326188 > > >=20 > > > Any idea? > > >=20 > >=20 > > That looks like the issue Juergen fixed with: > >=20 > > https://lore.kernel.org/xen-devel/20260220123715.834848-1-jgross@suse.c= om/ >=20 > No, it doesn't. The fix is already in rc1, and the crash was quite early = during > boot (before any secondary CPUs were brought up). >=20 > I guess this problem is related to the lazy_mmu_state series [1]. FWIW, the issue still happens on 7.0-rc6. > Juergen >=20 > [1]: https://lore.kernel.org/lkml/20251215150323.2218608-1-kevin.brodsky@= arm.com/ --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --C0DK1UxqrVq6HEXJ Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnSLj4ACgkQ24/THMrX 1yymYwf+L8DVCpnBOyKU8gkMp1NPN7ipNFMkj0k8jb9gqrRurhwocXwCFkRlvpoI RhoqB0cC1yPh5B/7vCJz7Yz7JfHVxpFpfXOr0gjLFvtIqHM+hxGrd5eSSauknZ9z iOOOmjGuMCS1f1dNPceCbV0N0cwocJm2CJb06veRVOETdhrJnsPZ1lki1Z1SQpxO ajlyYWJlEOYOnMsCj03l55sxpcoyekuD+WSeDnGNOMNUJIYcDVXVYLb524x6IJV9 62Gm7tFpGLBttlFHGakT8nWk93Fl3AGgB+UIfSaB1gMpk+mLUvyyrom/UEIBxzMe 6nJGbEerWbdgcBZOgR+5Qox+nt0nxg== =Ofpl -----END PGP SIGNATURE----- --C0DK1UxqrVq6HEXJ-- From xen-devel-bounces@lists.xenproject.org Mon Apr 06 09:07:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 09:07:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274196.1560379 (Exim 4.92) (envelope-from ) id 1w9fux-0007tp-Kf; Mon, 06 Apr 2026 09:06:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274196.1560379; Mon, 06 Apr 2026 09:06:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9fux-0007ti-H7; Mon, 06 Apr 2026 09:06:47 +0000 Received: by outflank-mailman (input) for mailman id 1274196; Mon, 06 Apr 2026 09:06:45 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9fuv-0007tc-Ra for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 09:06:45 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1w9fuw-00COtD-01 for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 09:06:45 +0000 Received: from mail-lf1-f41.google.com ([209.85.167.41]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1w9fuw-002gaR-03 for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 09:06:45 +0000 Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-5a2c9932781so3780490e87.1 for ; Mon, 06 Apr 2026 02:06:45 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xenproject.org; s=20200302mail; h=Content-Type:To:Subject:Message-ID:Date: From:MIME-Version; bh=uRb9zU1nhO8e66PvPrcitDqoBWT7m96rvAgdxUxGxxs=; b=mYSZfzT kWYD341u2Uz2w/rIJJwJ+q4QpGR6Qid3R2rds/c2vj5uOocP+gdze1/9fm/NRrd6UlqpshNWKVh9B x7OyiapT72MiHC0aCZtjzEq5fziYIy/fH1+Ap5GndSqesaDZ4t8MrK8ReJl+L8xhlhaPaVW4w6v69 45puPP0Sto=; X-Gm-Message-State: AOJu0YzCnj97ZOndULFE5VDV1okf/mTf1xOg9N3ma8O2V2wNE4Xb0RPk 9OzywR8f1syHfV90YLfqq4gYLB5VgoKzLefOwQdA7iTr8X+cYly7Eubydk612e0CI4QUi8O6pJ4 lGr2+tXZyy98RnSqN8M3O5Zjhv1owdco= X-Received: by 2002:a05:6512:3a93:b0:5a1:334a:dd62 with SMTP id 2adb3069b0e04-5a2c8d8f938mr4230825e87.13.1775466403726; Mon, 06 Apr 2026 02:06:43 -0700 (PDT) MIME-Version: 1.0 From: Cody Zuschlag Date: Mon, 6 Apr 2026 11:06:32 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDr_VmetOvd5rMOvgnacPtnetEjpPE4300kz-lR7yQQw5yD1vBdap3V09I Message-ID: Subject: [ANNOUNCE] Call for agenda items for April 9 Xen Community Call @ 15:00 UTC To: xen-devel@lists.xenproject.org Content-Type: multipart/alternative; boundary="0000000000004e0cfb064ec6fc20" --0000000000004e0cfb064ec6fc20 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi everyone, It=E2=80=99s time for the April Xen Project Community Call, happening this = Thursday at 4 pm UK time. We=E2=80=99d love to have you join. You=E2=80=99re welcome to participate o= r just listen in. It=E2=80=99s a good chance to stay aligned, hear what others are workin= g on, and share updates across the community. *Preparation: *Please take a moment to review and update the agenda ahead of the call: =F0=9F=91=89 Agenda *Feel free to:*- Add topics or updates - Clean up anything that=E2=80=99s no longer relevant - Drop in links to patches, threads, or docs where helpful *Call Details: *Date: Thursday, 9 April 2026 Time: 15:00 UTC (agenda starts at 15:05 UTC) Find your local timezone here Join: https://meet.jit.si/XenProjectCommunityCall We=E2=80=99ll open the room at 15:00 UTC and start the agenda at 15:05 UTC = to give folks a few minutes to join. Want to be CC=E2=80=99d on future calls? Add or remove yourself from our Sign-up Sheet . See you there! Cody Zuschlag Xen Project - Community Manager --0000000000004e0cfb064ec6fc20 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi everyone,

It=E2=80=99s time for the April X= en Project Community Call, happening this Thursday at 4 pm UK time.

= We=E2=80=99d love to have you join. You=E2=80=99re welcome to participate o= r just listen in. It=E2=80=99s a good chance to stay aligned, hear what oth= ers are working on, and share updates across the community.

Prepa= ration: =C2=A0
Please take a moment to review and update the agenda = ahead of the call: =C2=A0
=F0=9F=91=89=C2=A0Agenda

Feel free to:
- Add topics or updates = =C2=A0
- Clean up anything that=E2=80=99s no longer relevant =C2=A0
-= Drop in links to patches, threads, or docs where helpful =C2=A0

= Call Details: =C2=A0
Date: Thursday, 9 April 2026 =C2=A0
Time: 15= :00 UTC (agenda starts at 15:05 UTC) =C2=A0
Find your local timezone here =C2=A0
Join: https://meet.jit.si/XenProjectC= ommunityCall =C2=A0

We=E2=80=99ll open the room at 15:00 UTC and= start the agenda at 15:05 UTC to give folks a few minutes to join.

Want to be CC=E2=80=99d on future calls?
Add or remove= yourself from our=C2=A0Sign-up Sheet.

See you= there!


Cody Zuschlag
Xen Project - Community Manager
--0000000000004e0cfb064ec6fc20-- From xen-devel-bounces@lists.xenproject.org Mon Apr 06 14:59:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 14:59:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274219.1560388 (Exim 4.92) (envelope-from ) id 1w9lQA-0005Zp-9p; Mon, 06 Apr 2026 14:59:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274219.1560388; Mon, 06 Apr 2026 14:59:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9lQA-0005Zi-6N; Mon, 06 Apr 2026 14:59:22 +0000 Received: by outflank-mailman (input) for mailman id 1274219; Mon, 06 Apr 2026 14:59:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9lQ8-0005Za-Hn for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 14:59:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9lQ6-001A8P-Qa for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 16:59:18 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d3c9e9-e002-0a2a0a5209dd-0a2a450ae32c-44 for ; Mon, 06 Apr 2026 16:59:18 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d3ca44-ee98-0a2a450a0019-aceafc1f8362-3 for ; Mon, 06 Apr 2026 16:59:18 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id E4B394456D for ; Mon, 6 Apr 2026 14:59:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA74EC2BCAF for ; Mon, 6 Apr 2026 14:59:15 +0000 (UTC) Received: by mail-oi1-f175.google.com with SMTP id 5614622812f47-470145d7e6fso691448b6e.2 for ; Mon, 06 Apr 2026 07:59:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="References:In-Reply-To:From:Date:Subject:To:Cc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775487555; bh=xQ7o66TtbbwulQnJW5l2ZtOfYQA79hhGSfn9VhPlO6U=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=MLkaENd1y02jG6YsphOhuZTp0iQI96L6WFY5DEmo/DZ6WCfvoSBDZJV2ohYZSu1N9 ac4WV6CKVr3vtjWO5PyYEkAdXK0hp0G+RobW161z0dcu3s/VU0gY22kCs+MYXqUHBH Liz1EHAuKjE4fTRx4+YsiI+t4vTTDKeLdDI2YZy0dAHG/YzL3nR/Rt8+yoiTCr6Y7R 31IDqYUjMqFbupJ1fx/4xFWsQpHeFVPqQZdMM9fWEudaIkvMRtjafaQw7H2b7xvoYg xYFQlwgI/yUaOmD2NLJlqgiOeQ45VmSMD64YK+4sRFnv7nXs5NX2dbzF574dvLBFqO XtniXv49RXROw== X-Forwarded-Encrypted: i=1; AJvYcCU51LRlYmWTCYBjiS/bjkT9ql4tNGOEY6NcTvJ8Z2Nm+kVowu+C0zb9v1qaVSMgLjzaDu/SZk+JDQc=@lists.xenproject.org X-Gm-Message-State: AOJu0YxKOfxsclLcyuqDDA9OgUVaLOPDta6cLHRj7l7qwWuGEwmTeH6u B/hZFKMpn1qX5YrPlfw62E0KbC5UlITqn6wBWTFYUxCZgTEbLpFTaJRX4pdGxO908N7omtEPdjk zT9IFfK4asM5RtRD2M1z//rHtZeBYcrI= X-Received: by 2002:a05:6808:1910:b0:468:776:1ead with SMTP id 5614622812f47-46ef5af739fmr6450744b6e.21.1775487554002; Mon, 06 Apr 2026 07:59:14 -0700 (PDT) MIME-Version: 1.0 References: <20260401081640.26875-1-fengchengwen@huawei.com> In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> From: "Rafael J. Wysocki" Date: Mon, 6 Apr 2026 16:58:58 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDy996ma1a9twY_5lJC3Avr9hchzSyUdEAhSG92k1NHCBaaPp2eIIIoft4 Message-ID: Subject: Re: [PATCH RESEND v10 0/8] ACPI: Unify CPU UID interface and fix ARM64 TPH steer-tag issue To: Chengwen Feng Cc: Bjorn Helgaas , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Jonathan Corbet , WANG Xuerui , Thomas Gleixner , Dave Hansen , "H . Peter Anvin" , Juergen Gross , Boris Ostrovsky , Len Brown , Sunil V L , Mark Rutland , Jonathan Cameron , Kees Cook , Yanteng Si , Sean Christopherson , Kai Huang , Tom Lendacky , Thomas Huth , Thorsten Blum , Kevin Loughlin , Zheyun Shen , Peter Zijlstra , Pawan Gupta , Xin Li , "Ahmed S . Darwish" , Sohil Mehta , Ilkka Koskinen , Robin Murphy , James Clark , Besar Wicaksono , Ma Ke , Wei Huang , Andy Gospodarek , Somnath Kotur , punit.agrawal@oss.qualcomm.com, guohanjun@huawei.com, suzuki.poulose@arm.com, ryan.roberts@arm.com, chenl311@chinatelecom.cn, masahiroy@kernel.org, wangyuquan1236@phytium.com.cn, anshuman.khandual@arm.com, heinrich.schuchardt@canonical.com, Eric.VanTassell@amd.com, wangzhou1@hisilicon.com, wanghuiqiang@huawei.com, liuyonglong@huawei.com, linux-pci@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-perf-users@vger.kernel.org, stable@vger.kernel.org, x86@kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1775487558-BE3510B1-C94A14ED/0/0 X-purgate-type: clean X-purgate-size: 3276 On Wed, Apr 1, 2026 at 10:16=E2=80=AFAM Chengwen Feng wrote: > > This patchset unifies ACPI Processor UID retrieval across > arm64/loongarch/riscv/x86 via acpi_get_cpu_uid() (with input validation) > and fixes ARM64 CPU steer-tag retrieval failure in PCI/TPH: > > 1-4: Add acpi_get_cpu_uid() for arm64/loongarch/riscv/x86 (update > respective users) > 5: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h > 6: Clean up perf/arm_cspmu > 7: Clean up ACPI/PPTT and remove unused get_acpi_id_for_cpu() > 8: Pass ACPI Processor UID to Cache Locality _DSM > > The interface refactor ensures consistent CPU UID retrieval across > architectures (no functional changes for valid inputs) and provides the > unified interface required for the ARM64 TPH fix > > --- > Changes in v10-resend: > - Add Catalin's ack-by for arm64 commit > - Add CC to x86@kernel.org > > Changes in v10: > - Refine commit header&log according to Punit's and Bjorn's review > - Split perf/arm_cspmu as a separate commit which address Punit's > review > > Changes in v9: > - Address Bjorn's review: split commits to each platform so that make > them easy to review > > Changes in v8: > - Moving arm64's get_cpu_for_acpi_id() to kernel/acpi.c which address > Jeremy's review > > Chengwen Feng (8): > arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval > LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval > RISC-V: ACPI: Add acpi_get_cpu_uid() for unified ACPI CPU UID > retrieval > x86/acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval > ACPI: Centralize acpi_get_cpu_uid() declaration in > include/linux/acpi.h > perf: arm_cspmu: Switch to acpi_get_cpu_uid() from > get_acpi_id_for_cpu() > ACPI: PPTT: Use acpi_get_cpu_uid() and remove get_acpi_id_for_cpu() > PCI/TPH: Pass ACPI Processor UID to Cache Locality _DSM > > Documentation/PCI/tph.rst | 4 +-- > arch/arm64/include/asm/acpi.h | 17 +--------- > arch/arm64/kernel/acpi.c | 30 ++++++++++++++++++ > arch/loongarch/include/asm/acpi.h | 5 --- > arch/loongarch/kernel/acpi.c | 9 ++++++ > arch/riscv/include/asm/acpi.h | 4 --- > arch/riscv/kernel/acpi.c | 16 ++++++++++ > arch/riscv/kernel/acpi_numa.c | 9 ++++-- > arch/x86/include/asm/cpu.h | 1 - > arch/x86/include/asm/smp.h | 1 - > arch/x86/kernel/acpi/boot.c | 20 ++++++++++++ > arch/x86/xen/enlighten_hvm.c | 5 +-- > drivers/acpi/pptt.c | 50 ++++++++++++++++++++++-------- > drivers/acpi/riscv/rhct.c | 7 ++++- > drivers/pci/tph.c | 16 +++++++--- > drivers/perf/arm_cspmu/arm_cspmu.c | 6 ++-- > include/linux/acpi.h | 11 +++++++ > include/linux/pci-tph.h | 4 +-- > 18 files changed, 158 insertions(+), 57 deletions(-) > > -- Applied as 7.1 material, but please note that I haven't tagged it explicitly for "stable". The last patch carries a Fixes: tag which should be suitable for "stable" to pick it up and you may as well request the whole series to be picked up by "stable" when it hits the mainline. Thanks! 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Message-ID: References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="F629bKJhvAiDwbl3" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-d62444/1775489405-BC766185-E61D7C9F/0/0 X-purgate-type: clean X-purgate-size: 3042 --F629bKJhvAiDwbl3 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Mon, 6 Apr 2026 17:29:58 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel , =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? On Fri, Apr 03, 2026 at 03:55:07PM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > On Thu, Apr 02, 2026 at 03:02:15PM +0200, Marek Marczykowski-G=C3=B3recki= wrote: > > On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-G=C3=B3rec= ki wrote: > > > Some further observation, this time regarding timers: > >=20 > > In the meantime Roger suggested it might be about C-states. So, I just > > tried booting with max_cstate=3D0. I got this: >=20 > We had a design session on this issue, and managed to find (thanks Roger!) > that adding: >=20 > tsc_mode=3D'always_emulate' >=20 > to the domU config fixes the issue. Now, the question is how to fix it > properly... I also did another test with NTP inside domU (after host S3): $ ntpdate -q pool.ntp.org 2026-04-06 00:07:01.559218 (+0200) -0.216281 +/- 0.012486 pool.ntp.org 141.= 144.241.16 s2 no-leap $ ntpdate -q pool.ntp.org 2026-04-06 00:57:40.852612 (+0200) -0.255782 +/- 0.013022 pool.ntp.org 185.= 252.140.125 s2 no-leap $ ntpdate -q pool.ntp.org 2026-04-06 13:07:57.647126 (+0200) -0.791802 +/- 0.056578 pool.ntp.org 185.= 248.188.98 s1 no-leap $ ntpdate -q pool.ntp.org 2026-04-06 13:08:01.844118 (+0200) -0.832599 +/- 0.012563 pool.ntp.org 185.= 248.188.98 s1 no-leap $ ntpdate -q 141.144.241.16 2026-04-06 13:08:47.835271 (+0200) -0.819725 +/- 0.028655 141.144.241.16 s2= no-leap $ ntpdate -q 141.144.241.16 2026-04-06 13:08:51.290526 (+0200) -0.833668 +/- 0.015501 141.144.241.16 s2= no-leap $ ntpdate -q 141.144.241.16 2026-04-06 13:08:56.136567 (+0200) -0.832294 +/- 0.014493 141.144.241.16 s2= no-leap $ ntpdate -q 141.144.241.16 2026-04-06 17:21:41.017554 (+0200) -1.044511 +/- 0.021817 141.144.241.16 s2= no-leap So, domU's clock definitely drifts. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --F629bKJhvAiDwbl3 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnT0XYACgkQ24/THMrX 1yynEwf/eRO74GKeVMvcaA9wOJKDjsLG/ZweEvDhjBWJRfwMXyWfOFb/CbUfBWDc CBcOa5DtGph5YQnU9ckWdyN16HlW0GiDSuY/X99KfcUpCFXaJLdxSLlJdRBXFHvh vinuBwUty868tWz8wED0OvRlmZOK6X8SwAi26ea6ur4FJ5JRC2Gjjv8efqY2HLjM kEqg5jxUCMSGivAl/HVrlYSIGiZZhQ6f0/647JlFMzww6zNS0Xvew+80egOQniqy rrOLtyrIWSnmHJj/dqAKfTmj2WwwWmgBJNpuU/LS93C16lgLqnUMHdxbCK2jfYu6 xJkXeln+ATuroCLIbyouNn+N59LlTw== =tz0q -----END PGP SIGNATURE----- --F629bKJhvAiDwbl3-- From xen-devel-bounces@lists.xenproject.org Mon Apr 06 15:43:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 15:43:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274238.1560405 (Exim 4.92) (envelope-from ) id 1w9m6j-0003gC-F2; Mon, 06 Apr 2026 15:43:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274238.1560405; Mon, 06 Apr 2026 15:43:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9m6j-0003g5-C3; Mon, 06 Apr 2026 15:43:21 +0000 Received: by outflank-mailman (input) for mailman id 1274238; Mon, 06 Apr 2026 15:43:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1w9m6h-0003fz-At for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 15:43:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9m6g-001FUV-8x for xen-devel@lists.xenproject.org; Mon, 06 Apr 2026 17:43:18 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d3d465-2eae-0a2a0a5409dd-0a2a4501e4ba-40 for ; Mon, 06 Apr 2026 17:43:18 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d3d496-6fc9-0a2a45010019-d1558034b4a3-3 for ; Mon, 06 Apr 2026 17:43:18 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-488af96f6b2so15926475e9.0 for ; Mon, 06 Apr 2026 08:43:18 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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For example, what if more than 2Gb of MMIO space are needed >>>>>>> for non-64-bit BARs? >>>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>>> before RAM start is enough for MMIO space. >>>>> Likely in the common case. Board designers aren't constrained by this, >>>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>>> >>>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>>> could you chime in here, please? >>>>> >>>>>> Answering your question it will be an issue or it will also use some >>>>>> space before banks, no? >>>>> I fear I don't understand what you're trying to tell me. >>>> I meant that there is also some space between banks and pretty big which >>>> could be used for MMIO which could be used for non-64-bit BARs. >>> I don't follow: Bank 0 extends to 4G. There's no space above it, below >>> bank 1, which could be use for non-64-bit BARs. >> >> So we have two banks: >> bank[0] -> [0x80000000, 0x100000000) >> bank[1] -> [0x0200000000, 10000000000) >> >> So i think we have some space between them [0x100000000, 0x0200000000) >> -> 4gb to be used for non-64-bit BARs. > > But a non-64-bit BAR need to be assigned an address below 0x100000000? Right, I had in mind that RV32 uses for guest Sv32x4 which could translate 34-bit GPA into 34-bit MPA and automatically applied that to 32-bit BAR... I can keep first 4gb for MMIO purpose and start bank[0] at 4gb as 34 MPA address space is more then enough to cover reserved 2gb of bank[0] after 4gb. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 06 16:39:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 16:39:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274256.1560433 (Exim 4.92) (envelope-from ) id 1w9myh-0002Y3-3i; Mon, 06 Apr 2026 16:39:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274256.1560433; Mon, 06 Apr 2026 16:39:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9myh-0002Xu-0Y; Mon, 06 Apr 2026 16:39:07 +0000 Received: by outflank-mailman (input) for mailman id 1274256; Mon, 06 Apr 2026 16:39:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9myf-00027P-Ca for xen-devel@lists.xenproject.org; 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Mon, 6 Apr 2026 16:39:01 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=epam.com header.i="@epam.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:x-ms-exchange-senderadcheck" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=i8N9QNy8aaTGxZqft+2igwW6+IS8WUXVv5SE5xM43FxqweV9jk4BuMYB4IhgLs5tGaNUQ8C0J2MSnHZwpss2zLWOOwZbfDP1I4znVwxNeYasDJ64TOicqAM/+z5f1gf8KcW+dQD1/yIB2zWKa3mu9S2gO5KiIXmwMxbNRU2TQu3/7uHn3U1NmivY47rL/zVXP8gkuW3jZ3O1g+FCwHumxRgjg1njZhMp1nwt9OgneYtYchsl6fY8LsCa3gK6TcimUrNi+Vmx/9kJ5TW1AspWb1vcpRz2Ego8dZlgEH0x/Oj0WFOec/OEpGHqnncRuWz0K2NQjlB/KGT9wnt2n1zgXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0eeed215-86eb-4173-346b-08de93fb024f X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2026 16:39:01.7722 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: BnaRi+Lf9AQvWinzP8aFenbB9JoGb2cuPbLKUzCyvucKc2I9IROwLCo+cGq+I2cMaZUCxTHJBMuMWDynIcs1S059S/3CxBemN2Egt8d7Nps= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6817 X-purgate-ID: tlsNG-16d1c6/1775493544-64A4C3D8-EDE9E374/0/0 X-purgate-type: clean X-purgate-size: 1003 According to the "7.1 Return Codes" section of DEN0028 [1] INVALID_PARAMETER code (-3) is returned when one of the call parameters has a non-supported value. Adding this error code to the common smccc header file. [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6 Signed-off-by: Oleksii Moisieiev --- xen/arch/arm/include/asm/smccc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 441b3ab65d..478444fb09 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -381,6 +381,7 @@ void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs = *args, 0x3FFF) =20 /* SMCCC error codes */ +#define ARM_SMCCC_INVALID_PARAMETER (-3) #define ARM_SMCCC_NOT_REQUIRED (-2) #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1) --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 16:39:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 16:39:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274255.1560421 (Exim 4.92) (envelope-from ) id 1w9myf-0002AP-OY; Mon, 06 Apr 2026 16:39:05 +0000 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b=QFHWvLObFTWy1nosQLJUaX8xTaLbfo1QOQJMyinUgvYSRLQfnS1uXsgwuDNLR2b6bhy6aAjZeNvOcEWj8Lj5p+f8SlDR5X4ZTCRbu+UBsko/gDRIK7ODRgSmFLfbhzOYUXogXfvG+qk2vilA97dKtLufl1y4b0OCGtfVQGA/QEKtqrTq7PIQsL8gDP1BNIRVHUMhNeHVgBICoqHGpii4PSYfPte7r1Q5j3rOnau7gSOg3uOuQ1rqYWBiVgVP22gzxmQj7aQGG9YJK6nuei7pd4RIWlT2wNJqtLwgBBC+N8+itySvnqhOVPXm5hZSEdaI9TXskSP6vE8D/gFniW66cA== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Andrew Cooper , Anthony PERARD , Bertrand Marquis , Jan Beulich , Juergen Gross , Julien Grall , Michal Orzel , Oleksii Moisieiev , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano Stabellini , Volodymyr Babchuk , Grygorii Strashko Subject: [PATCH v11 1/6] xen/domctl: chain SCI handling before IOMMU in assign_device domctl Thread-Topic: [PATCH v11 1/6] xen/domctl: chain SCI handling before IOMMU in assign_device domctl Thread-Index: AQHcxePfx39ACAuRcE2aBj5D+lufNQ== Date: Mon, 6 Apr 2026 16:39:01 +0000 Message-ID: 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b=FZSb0PlNnIGZOj4JK2FINfGROyu5gh5oQ4uSynL51jLKHfPeI/d7Py0wE0/xXLcU7F+mB/Br+U5ZasXukfDJpo49h08AHK0TPgmUWPn0e8FZf6eApTKNJuFGzJ8xOwzti4T5L2ee1fgYmRRwRVjQScAcys8oUFhZwAoHEWmKmmRZ1nqq77VFmWCVqtawOgLnynsFkDLOGI/JCf1fRMdWuulmOsRv0LIVRYCnz8zKftTWUyht4UvB0d5WaK1D0xcFnTWammAmABr5+nyOpR75VTh4ZLOa8kah6Ttc7xYM2s2E2ygSR9V6/+8ouuYduoHPnxDYLPGdG0sq61dbVAuT4A== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Andrew Cooper , Anthony PERARD , Bertrand Marquis , Jan Beulich , Juergen Gross , Julien Grall , Michal Orzel , Oleksii Moisieiev , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Stefano Stabellini , Volodymyr Babchuk , Grygorii Strashko Subject: [PATCH v11 4/6] xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver Thread-Topic: [PATCH v11 4/6] xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver Thread-Index: AQHcxePgRqI3n96hREefP/HRl0OEDw== Date: Mon, 6 Apr 2026 16:39:02 +0000 Message-ID: <1cdbcff5f26743172add46587390f17dec12fb08.1775493499.git.oleksii_moisieiev@epam.com> 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X-MS-Exchange-CrossTenant-Network-Message-Id: f20ce1df-2239-43e7-9c73-08de93fb0348 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2026 16:39:02.5185 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KDKR+3u0DXfFsHKauJ1d6oCZcS0jt+J4ya+G2pUb/Vq+i9phK8/qvB1C0Cb+xxTTFn7nhJqjxGsvLvmjB8mZeOqbMC4Y2mloah8bkdUVhRE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6817 X-purgate-ID: tlsNG-16d1c6/1775493545-5DF2D078-AC4E314B/0/0 X-purgate-type: clean X-purgate-size: 68366 This patch introduces SCI driver to support for ARM EL3 Trusted Firmware-A (TF-A) which provides SCMI interface with multi-agent support, as shown below. +-----------------------------------------+ | | | EL3 TF-A SCMI | +-------+--+-------+--+-------+--+-------++ |shmem1 | |shmem0 | |shmem2 | |shmemX | +-----+-+ +---+---+ +--+----+ +---+---+ smc-id1 | | | | agent1 | | | | +-----v--------+---------+-----------+----+ | | | | | | | | | | +--------------+---------+-----------+----+ smc-id0 | smc-id2| smc-idX| agent0 | agent2 | agentX | | | | +----v---+ +--v-----+ +--v-----+ | | | | | | | Dom0 | | Dom1 | | DomX | | | | | | | | | | | | | +--------+ +--------+ +--------+ The EL3 SCMI multi-agent firmware is expected to provide SCMI SMC shared memory transport for every Agent in the system. The SCMI Agent transport channel defined by pair: - smc-id: SMC id used for Doorbell - shmem: shared memory for messages transfer, Xen page aligned. Shared memort is mapped with the following flags: MT_DEVICE_nGnRE. The follwoing SCMI Agents are expected to be defined by SCMI FW to enable S= CMI multi-agent functionality under Xen: - Xen management agent: trusted agents that accesses to the Base Protocol commands to configure agent specific permissions - OSPM VM agents: non-trusted agent, one for each Guest domain which is allowed direct HW access. At least one OSPM VM agent has to be provided by FW if HW is handled only by Dom0 or Driver Domain. The EL3 SCMI FW is expected to implement following Base protocol messages: - BASE_DISCOVER_AGENT (optional if agent_id was provided) - BASE_RESET_AGENT_CONFIGURATION (optional) - BASE_SET_DEVICE_PERMISSIONS (optional) The SCI SCMI SMC multi-agent driver implements following functionality: - The driver is initialized from the Xen SCMI container ``xen_scmi_config`` (compatible ``xen,sci``) placed under ``/chosen/xen``. Only the ``arm,scmi-smc`` node that is a child of this container will bind to Xen; other SCMI nodes (for example under ``/firmware``) are ignored to avoid stealing the host OSPM instance. scmi_shm_1: sram@47ff1000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff1000 0x0 0x1000>; }; scmi_xen: scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0x82000003>; <--- Xen management agent smc-id #address-cells =3D < 1>; #size-cells =3D < 0>; #access-controller-cells =3D < 1>; shmem =3D <&scmi_shm_1>; <--- Xen management agent shmem }; - The driver obtains Xen specific SCMI Agent's configuration from the Host DT, probes Agents and builds SCMI Agents list. The Agents configuration is taken from "scmi-secondary-agents" property where first item is "arm,smc-id", second - "arm,scmi-shmem" phandle and third is optional "agent_id": / { chosen { xen { ranges; xen_scmi_config { compatible =3D "xen,sci"; #address-cells =3D <2>; #size-cells =3D <2>; ranges; scmi_shm_0: sram@47ff0000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff0000 0x0 0x1000>; }; /* Xen SCMI management channel */ scmi_shm_1: sram@47ff1000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff1000 0x0 0x1000>; }; scmi_shm_2: sram@47ff2000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff2000 0x0 0x1000>; }; scmi_shm_3: sram@47ff3000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff3000 0x0 0x1000>; }; scmi-secondary-agents =3D < 0x82000002 &scmi_shm_0 0 0x82000004 &scmi_shm_2 2 0x82000005 &scmi_shm_3 3>; <--- func_id, shmem, agent_id #scmi-secondary-agents-cells =3D <3>; xen,dom0-sci-agent-id =3D <0>; scmi_xen: scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0x82000003>; <--- Xen management agent func_id #address-cells =3D <1>; #size-cells =3D <0>; #access-controller-cells =3D <1>; shmem =3D <&scmi_shm_1>; <--- Xen management agent shmem }; }; }; }; }; / { /* * Host SCMI OSPM channel - provided to the Dom0 as is if SCMI * enabled for it, ignored by Xen multi-agent mediator */ scmi_shm: sram@47ff0000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x47ff0000 0x0 0x1000>; }; firmware { scmi: scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0x82000002>; <--- Host OSPM agent smc-id #address-cells =3D < 1>; #size-cells =3D < 0>; shmem =3D <&scmi_shm>; <--- Host OSPM agent shmem protocol@X{ }; }; }; }; This approach allows defining multiple SCMI Agents by adding Xen-specific properties under the ``/chosen`` node to the Host Device Tree, leaving the main part unchanged. The Host DT SCMI channel will be passed to Dom0. The Xen management agent is described as a ``scmi_xen`` node under the ``xen,sci`` comaptible node, which is used by Xen to control other SCMI Agents in the system. All secondary agents' configurations are provided in the ``scmi-secondary-agents`` property with an optional ``agent_id`` field. The ``agent_id`` from the ``scmi-secondary-agents`` property is used to identify the agent in the system and can be omitted by setting ``#scmi-secondary-agents-cells =3D <2>``, so the Secondary Agents configuration will look like this: / { chosen { xen { xen_scmi_config { compatible =3D "xen,sci"; #address-cells =3D <2>; #size-cells =3D <2>; ranges; /* Shared memory nodes as defined earlier */ scmi-secondary-agents =3D < 0x82000003 &scmi_shm_0 0x82000004 &scmi_shm_2 0x82000005 &scmi_shm_3 0x82000006 &scmi_shm_4>; #scmi-secondary-agents-cells =3D <2>; }; }; }; } In this case, Xen will use the ``SCMI_BASE_DISCOVER_AGENT`` call to discover the ``agent_id`` for each secondary agent. Providing the ``agent_id`` in the ``scmi-secondary-agents`` property allows skipping the discovery call, which is useful when the secondary agent's shared memory is not accessible by Xen or when boot time is important because it allows skipping the agent discovery procedure. Note that Xen is the only one entry in the system which need to know about SCMI multi-agent support. SMC ID Configuration and SCMI Connection Compatibility: The configuration allows the same device tree to work for both baremetal Linux and Linux Dom0. This is achieved because: - Baremetal Linux uses: func_id 0x82000002, scmi-shmem 0x47ff0000 - Dom0 Linux uses: func_id 0x82000002, scmi-shmem 0x47ff0000 - Xen management uses: func_id 0x82000003, scmi-shmem 0x47ff1000 This works because the privileged SCMI connection in EL3 firmware is not tied exclusively to func_id 0x82000002. The EL3 firmware supports multiple SCMI agents with different SMC IDs and shared memory regions. Each agent (Dom0 via 0x82000002, Xen via 0x82000003, other domains via additional func_ids) has an independent communication channel to the firmware. The key distinction is that Xen's management channel (0x82000003) is used for privileged operations like agent configuration and device permissions (BASE_SET_DEVICE_PERMISSIONS, BASE_RESET_AGENT_CONFIGURATION), while Dom0's channel (0x82000002) is used for standard SCMI protocol operations (power, clock, sensor management, etc.). The firmware enforces different permission levels for each agent based on their agent_id, not the SMC ID. Therefore, there is no conflict: Linux Dom0 retains its standard SCMI connection for hardware management, while Xen uses its separate privileged channel for mediating access between multiple domains. - It implements the SCI subsystem interface required for configuring and enabling SCMI functionality for Dom0/hwdom and Guest domains. To enable SCMI functionality for domain it has to be configured with unique supported SCMI Agent_id and use corresponding SCMI SMC shared memory transport [smc-id, shmem] defined for this SCMI Agent_id. - Once Xen domain is configured it can communicate with EL3 SCMI FW: -- zero-copy, the guest domain puts SCMI message in shmem; -- the guest triggers SMC exception with smc-id (doorbell); -- the Xen driver catches exception, do checks and synchronously forwards it to EL3 FW. - the Xen driver sends BASE_RESET_AGENT_CONFIGURATION message to Xen management agent channel on domain destroy event. This allows to reset resources used by domain and so implement use-case like domain reboot. Dom0 Enable SCMI SMC: - set xen,dom0-sci-agent-id=3D under the xen,sci container in the Host DT. If the property is absent, SCMI is disabled for Dom0 and all SCMI nodes are removed from the Dom0 DT. The driver updates the Dom0 DT SCMI node "arm,smc-id" value and fixes up the shmem node according to the assigned agent_id. - pass dom0=3Dsci-agent-id=3D in Xen command line. if not provid= ed SCMI will be disabled for Dom0 and all SCMI nodes removed from Dom0 DT. The driver updates Dom0 DT SCMI node "arm,smc-id" value and fix up shmem node according to assigned agent_id. Guest domains enable SCMI SMC: - xl.cfg: add configuration option as below arm_sci =3D "type=3Dscmi_smc_multiagent,agent_id=3D2" - xl.cfg: enable access to the "arm,scmi-shmem" which should correspond assigned agent_id for the domain, for example: iomem =3D [ "47ff2,1@22001", ] - DT: add SCMI nodes to the Driver domain partial device tree as in the below example. The "arm,smc-id" should correspond assigned agent_id for the domain: passthrough { scmi_shm_0: sram@22001000 { compatible =3D "arm,scmi-shmem"; reg =3D <0x0 0x22001000 0x0 0x1000>; }; firmware { compatible =3D "simple-bus"; scmi: scmi { compatible =3D "arm,scmi-smc"; arm,smc-id =3D <0x82000004>; shmem =3D <&scmi_shm_0>; ... } } } SCMI "4.2.1.1 Device specific access control" The XEN SCI SCMI SMC multi-agent driver performs "access-controller" provider function in case EL3 SCMI FW implements SCMI "4.2.1.1 Device specific access control" and provides the BASE_SET_DEVICE_PERMISSIONS command to configure the devices that an agents have access to. The DT SCMI node should "#access-controller-cells=3D<1>" property and DT devices should be bound to the Xen SCMI. &i2c1 { access-controllers =3D <&scmi 0>; }; The Dom0 and dom0less domains DT devices will be processed automatically through sci_assign_dt_device() call, but to assign SCMI devices from toolstack the xl.cfg:"dtdev" property shall be used: dtdev =3D [ "/soc/i2c@e6508000", ] xl.cfg:dtdev will contain all nodes which are under SCMI management (not only those which are behind IOMMU). Additionally, this patch adds documentation for the pre-existing scmi-smc-passthrough command line option, which was previously undocumented. [0] https://developer.arm.com/documentation/den0056 [1] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/= tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml [2] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/= tree/Documentation/devicetree/bindings/access-controllers/access-controller= s.yaml Signed-off-by: Grygorii Strashko Signed-off-by: Oleksii Moisieiev --- (no changes since v10) Changes in v10: - Fix tabs in MAINTAINERS file - remove duplicate SPDX tag from scmi-shmem.c - add cast to ARM_SMCCC_INVALID_PARAMETER to settle the sign since ARM_SMCCC_INVALID_PARAMETER is -3 which is part of the spec and resp is the default smccc call structure. - update free_channel_list. Add spinlock to avoid race condition and a comment with a description of the function work - preserve error of smc_create_channel in scmi_probe - check scmi shmem address alignment as wel as it is done for size - check for d->arch.sci_data !=3D NULL in scmi_handle_call - use SCMI_SHMEM_MAPPED size for iomem_permit_access - change len type to unsigned in shmem_{get|put}_message - rename shmem_channel_is_free to shmem_channel_status - add comment about skipping message status when getting message response - Set correct agent_id ranges for dom0less and a toolstack. Agent_id 0 is not binded for dom0 so can be reused. Also mentioned that UINT8_MAX (255) is treated as invalid agent_id. - Split hypervisor and toolstack changes into separate commits - move init list and spin init after initial checks in probe call - fix typo in comments - clean resources when sci_register returns an error. Changes in v9: - sort and refactor MAINTAINERS enties - remove Spurious changes - add extra check to avoid ASSERT when calling unmap_channel_memory from assign device method - set correct tx flag to SCMI_BASE_AGENT_PERMISSIONS_RESET when freeing resources. Flag should be set to 1 according to the section 4.2.2.12 [0]. - fix dt node copmaring - moved channel->shmem check from ASSERT in unmap_memory_channel to "if" statement. This will prevent firing ASSERT if unmap_channel_memory was called twice on the same channel. Changes in v8: - update xen_scmi func_id in commit description - updated documentation with the new DT format - updated opt_dom0_scmi_agent_id setting to avoid it to be equal SCMI_AGENT_ID_INVALID. - changed SCMI_AGENT_ID_INVALID from 0xff to UINT8_MAX which makes code more clear showing that UINT8_MAX is theated like invalid agent_id and couldn't be used. Also excluded SCMI_AGENT_ID_INVALID from acceptable value range - remove outdated xen,config property ignore, added xen,sci compatible to skip_matches in handle_node - add documentation for pre-existing scmi-smc-passthrough command line option in alphabetically correct location (in 's' section) - add note to commit description about documentation for previously undocumented scmi-smc-passthrough - Fix SMC IDs in DT examples (Xen management uses 0x82000003, Dom0 uses 0x8= 2000002) - Add explicit note explaining why Dom0 and Xen channels do not conflict - Document dom0less multi-agent configuration example (xen,sci_type / xen,s= ci-agent-id) - Add scmi_xen node to agent-discovery example with #scmi-secondary-agents-= cells =3D 2 - Drop dom0=3Dsci-agent-id command line handling; Dom0 SCMI is now enabled = via xen,dom0-sci-agent-id in the xen,sci DT container - Refresh docs and examples to mention the DT property instead of the cmdli= ne option Changes in v7: - rework scmi nodes for xen to match on compatible string instead of the direct path Changes in v6: - updated scmi-shmem to use io.h from generic location - update scmi_agent_id parameter to be provided inside dom0=3D parameter list and have the following format "dom0=3Dsci-agent-id=3D0" This change was done as a response for Stefano comment and requires a lot of code changes, but produces much cleaner solution that's why I've added it to the code. - fix file comments and return codes - fix lenght checks in shmem_{get,put}_message to use offsetof - remove len member from scmi_channel structure as it is not used - set scmi-secondary-agents property to be mandatory since if no secondary agents were provided then there is no sence to enable scmi when no secondary agents are populated to the Domains - update documentation in booting.txt, added xen_scmi node to the example - adjust d->arch.sci_enabled value in scmi_domain_destroy - fix lock management in smc_create_channel call - avoid extra map_channel_memory command for Xen management channel because collect_agent_id call unmaps memory if DOMID_XEN is not set. So for Xen management channel we can init domain_id ad DOMID_XEN before calling collect_agent_id so memory shouldn't be unmapped. Changes in v5: - fix device-tree example format in booting.txt, added ";" after "}". - update define in scmi-proto.h - update define in scmi-shmem.h file - scmi_assign_device - do not ignore -EOPNOTSUPP return code of the do_smc_xfer - remove overwriting agent_channel->agent_id after SCMI_BASE_DISCOVER_AGENT call - add multi-agent files to the MAINTAINERS - add SCMI multi-agent description to the SUPPORT.md - handle ARM_SMCCC_INVALID_PARAMETER return code and return -EINVAL for smc call - updated collect_agents function. Set agent_id parameter as optional in scmi-secondary-agents device-tree property - introduce "#scmi-secondary-agents-cells" parameter to set if agent_id was provided - reanme xen,scmi-secondary-agents property to scmi-secondary-agents - move memcpu_toio/fromio for the generic place - update Xen to get management channel from /chosen/xen,config node - get hypervisor channnel from node instead of using hardcoded - update handling scmi and shmem nodes for the domain - Set multi-agent driver to support only Arm64 Changes in v4: - toolstack comments from Anthony PERARD - added dom0less support - added doc for "xen,scmi-secondary-agents" MAINTAINERS | 1 + SUPPORT.md | 11 + docs/misc/arm/device-tree/booting.txt | 197 +++++ xen/arch/arm/dom0less-build.c | 11 + xen/arch/arm/domain_build.c | 39 + xen/arch/arm/firmware/Kconfig | 12 + xen/arch/arm/firmware/Makefile | 1 + xen/arch/arm/firmware/scmi-proto.h | 164 ++++ xen/arch/arm/firmware/scmi-shmem.c | 118 +++ xen/arch/arm/firmware/scmi-shmem.h | 45 ++ xen/arch/arm/firmware/scmi-smc-multiagent.c | 830 ++++++++++++++++++++ xen/include/public/arch-arm.h | 3 + 12 files changed, 1432 insertions(+) create mode 100644 xen/arch/arm/firmware/scmi-proto.h create mode 100644 xen/arch/arm/firmware/scmi-shmem.c create mode 100644 xen/arch/arm/firmware/scmi-shmem.h create mode 100644 xen/arch/arm/firmware/scmi-smc-multiagent.c diff --git a/MAINTAINERS b/MAINTAINERS index bf00be928c..def49c327e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,7 @@ SCI MEDIATORS R: Oleksii Moisieiev S: Supported F: xen/arch/arm/firmware/sci.c +F: xen/arch/arm/firmware/scmi-*.[ch] F: xen/arch/arm/include/asm/firmware/sci.h =20 SEABIOS UPSTREAM diff --git a/SUPPORT.md b/SUPPORT.md index d441bccf37..03e3985da2 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -956,6 +956,17 @@ by hwdom. Some platforms use SCMI for access to system= -level resources. =20 Status: Supported =20 +### Arm: SCMI SMC multi-agent support + +Enable support for the multi-agent configuration of the EL3 Firmware, whic= h +allows Xen to provide an SCMI interface to the Domains. +Xen manages access permissions to the HW resources and provides an SCMI in= terface +to the Domains. Each Domain is represented as a separate Agent, which can +communicate with EL3 Firmware using a dedicated shared memory region, and +notifications are passed through by Xen. + + Status, ARM64: Tech Preview + ### ARM: Guest PSCI support =20 Emulated PSCI interface exposed to guests. We support all mandatory diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 977b428608..f0d1c458c9 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,21 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. =20 + - "scmi_smc_multiagent" + + Enables ARM SCMI SMC multi-agent support for the guest by enabling SCM= I over + SMC calls forwarding from domain to the EL3 firmware (like ARM + Trusted Firmware-A) with a multi SCMI OSPM agent support. + The SCMI agent_id should be specified for the guest with "xen,sci-agen= t-id" + property. + +- "xen,sci-agent-id" + + Specifies ARM SCMI agent id for the guest. This option is mandatory if= the + SCMI SMC "scmi_smc_multiagent" support is enabled for the guest. The a= gent ids + of guest must be unique and in the range [0..254]. UINT8_MAX (255) is + treated as invalid. + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 @@ -824,3 +839,185 @@ The automatically allocated static shared memory will= get mapped at 0x80000000 in DomU1 guest physical address space, and at 0x90000000 in Dom= U2 guest physical address space. DomU1 is explicitly defined as the owner dom= ain, and DomU2 is the borrower domain. + +SCMI SMC multi-agent support +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + +For enabling the ARM SCMI SMC multi-agent support (enabled by CONFIG_SCMI_= SMC_MA) +the Xen specific SCMI Agent's configuration shall be provided in the Host = DT +according to the SCMI compliant EL3 Firmware specification with ARM SMC/HV= C +transport. The SCMI configuration must live under the Xen SCMI container +"xen,sci" beneath "/chosen" (for example "/chosen/xen/xen_scmi_config/scmi= "). The +Xen SCMI mediator will bind only to the "arm,scmi-smc" node that is a chil= d of +this "xen,sci" container; any other "arm,scmi-smc" nodes (for example unde= r +"/firmware") are ignored to avoid stealing the host's SCMI OSPM instance. + +- scmi-secondary-agents + + Defines a set of SCMI agents configuration supported by SCMI EL3 FW an= d + available for Xen. Each Agent defined as triple consisting of: + SMC/HVC function_id assigned for the agent transport ("arm,smc-id"), + phandle to SCMI SHM assigned for the agent transport ("arm,scmi-shmem"= ), + SCMI agent_id (optional) if not set - Xen will determine Agent ID for + each provided channel using BASE_DISCOVER_AGENT message. + +- xen,dom0-sci-agent-id + + Optional. Specifies the Dom0/hwdom SCMI agent_id inside the ``xen,sci`= ` + container. When provided, Dom0 will be configured for SCMI multi-agent + support; when omitted, SCMI remains disabled for Dom0. The value must + match the ``func_id`` and shmem pairing that EL3 firmware exposes for + Dom0 (for example via ``/firmware/scmi``). + +As an example: + +/ { + chosen { + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scmi_shm_0: sram@47ff0000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff0000 0x0 0x1000>; + }; + + /* Xen SCMI management channel */ + scmi_shm_1: sram@47ff1000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff1000 0x0 0x1000>; + }; + + scmi_shm_2: sram@47ff2000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff2000 0x0 0x1000>; + }; + + scmi_shm_3: sram@47ff3000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff3000 0x0 0x1000>; + }; + + xen,dom0-sci-agent-id =3D <0>; <--- dom0 agent id + scmi-secondary-agents =3D < + 0x82000002 &scmi_shm_0 0 + 0x82000004 &scmi_shm_2 2 + 0x82000005 &scmi_shm_3 3>; <--- func_id, shmem, agent_= id + #scmi-secondary-agents-cells =3D <3>; + + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; <--- Xen management agent= func_id + #address-cells =3D <1>; + #size-cells =3D <0>; + #access-controller-cells =3D <1>; + shmem =3D <&scmi_shm_1>; <--- Xen management agent shm= em + }; + }; + }; + }; +}; + +Note: This example keeps the Host DT unchanged for Dom0 and baremetal Linu= x +by using func_id 0x82000002 / shmem 0x47ff0000 for Dom0, while Xen uses a +separate privileged channel func_id 0x82000003 / shmem 0x47ff1000. EL3 +firmware enforces permissions per agent_id, so there is no conflict betwee= n +Dom0 and Xen channels. + +- #scmi-secondary-agents-cells + + Defines whether Agent_id is set in the "scmi-secondary-agents" propert= y. + Possible values are: 2, 3. + When set to 3 (the default), expect agent_id to be present in the seco= ndary + agents list. + When set to 2, agent_id will be discovered for each channel using + BASE_DISCOVER_AGENT message. + + +Example: + +/ { + chosen { + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* Shared memory nodes as in the previous example */ + + scmi-secondary-agents =3D < + 0x82000002 &scmi_shm_0 + 0x82000004 &scmi_shm_2 + 0x82000005 &scmi_shm_3 + 0x82000006 &scmi_shm_4>; + #scmi-secondary-agents-cells =3D <2>; + + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; <--- Xen management agent= func_id + #address-cells =3D <1>; + #size-cells =3D <0>; + #access-controller-cells =3D <1>; + shmem =3D <&scmi_shm_1>; <--- Xen management agent shm= em + }; + }; + }; + }; +}; + +Dom0less example (multi-agent) +------------------------------- + +Below is a minimal dom0less configuration showing how to enable SCMI SMC +multi-agent for a pre-defined guest domain using xen,sci_type and +xen,sci-agent-id, together with the Xen SCMI container: + +chosen { + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* Xen management channel shared memory */ + scmi_shm_1: sram@47ff1000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff1000 0x0 0x1000>; + }; + + scmi_shm_domu: sram@47ff2000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff2000 0x0 0x1000>; + }; + + scmi-secondary-agents =3D < + 0x82000004 &scmi_shm_domu 2>; + #scmi-secondary-agents-cells =3D <3>; + + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #access-controller-cells =3D <1>; + shmem =3D <&scmi_shm_1>; + }; + }; + }; + + xen,domain@1 { + compatible =3D "xen,domain"; + xen,sci_type =3D "scmi_smc_multiagent"; + xen,sci-agent-id =3D <2>; + /* Additional domain properties (memory, cpus, kernels, etc.) */ + }; +}; diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c10538..1f8c1d851d 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -299,6 +299,17 @@ static int __init domu_dt_sci_parse(struct dt_device_n= ode *node, d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE; else if ( !strcmp(sci_type, "scmi_smc") ) d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC; + else if ( !strcmp(sci_type, "scmi_smc_multiagent") ) + { + uint32_t agent_id =3D 0; + + if ( !dt_property_read_u32(node, "xen,sci-agent-id", &agent_id) || + agent_id >=3D UINT8_MAX ) + return -EINVAL; + + d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA= ; + d_cfg->arch.arm_sci_agent_id =3D agent_id; + } else { printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n"= , diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 986a456f17..c09f50040e 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -86,6 +86,37 @@ int __init parse_arch_dom0_param(const char *s, const ch= ar *e) return -EINVAL; } =20 +/* SCMI agent ID for dom0 obtained from xen,sci container */ +#define SCMI_AGENT_ID_INVALID UINT8_MAX + +static uint8_t __init get_dom0_scmi_agent_id(void) +{ + const struct dt_device_node *config_node; + u32 val; + const struct dt_property *prop; + + config_node =3D dt_find_compatible_node(NULL, NULL, "xen,sci"); + if ( !config_node ) + return SCMI_AGENT_ID_INVALID; + + prop =3D dt_find_property(config_node, "xen,dom0-sci-agent-id", NULL); + if ( !prop ) + return SCMI_AGENT_ID_INVALID; + + if ( !dt_property_read_u32(config_node, "xen,dom0-sci-agent-id", &val)= ) + return SCMI_AGENT_ID_INVALID; + + if ( val >=3D SCMI_AGENT_ID_INVALID ) + { + printk(XENLOG_WARNING + "Invalid xen,dom0-sci-agent-id=3D%u, SCMI disabled for Dom0\n= ", + val); + return SCMI_AGENT_ID_INVALID; + } + + return val; +} + /* Override macros from asm/page.h to make them work with mfn_t */ #undef virt_to_mfn #define virt_to_mfn(va) _mfn(__virt_to_mfn(va)) @@ -1459,6 +1490,7 @@ static int __init handle_node(struct domain *d, struc= t kernel_info *kinfo, DT_MATCH_TYPE("memory"), /* The memory mapped timer is not supported by Xen. */ DT_MATCH_COMPATIBLE("arm,armv7-timer-mem"), + DT_MATCH_COMPATIBLE("xen,sci"), { /* sentinel */ }, }; static const struct dt_device_match timer_matches[] __initconst =3D @@ -1947,6 +1979,13 @@ void __init create_dom0(void) dom0_cfg.arch.tee_type =3D tee_get_type(); dom0_cfg.max_vcpus =3D dom0_max_vcpus(); =20 + /* Set up SCMI agent ID if provided in the xen,sci container */ + dom0_cfg.arch.arm_sci_agent_id =3D get_dom0_scmi_agent_id(); + dom0_cfg.arch.arm_sci_type =3D (dom0_cfg.arch.arm_sci_agent_id !=3D + SCMI_AGENT_ID_INVALID) ? + XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA : + XEN_DOMCTL_CONFIG_ARM_SCI_NONE; + if ( iommu_enabled ) dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu; =20 diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig index 5c5f0880c4..972cd9b173 100644 --- a/xen/arch/arm/firmware/Kconfig +++ b/xen/arch/arm/firmware/Kconfig @@ -29,6 +29,18 @@ config SCMI_SMC driver domain. Use with EL3 firmware which supports only single SCMI OSPM agent. =20 +config SCMI_SMC_MA + bool "Enable ARM SCMI SMC multi-agent driver" + depends on ARM_64 + select ARM_SCI + help + Enables SCMI SMC/HVC multi-agent in XEN to pass SCMI requests from Doma= ins + to EL3 firmware (TF-A) which supports multi-agent feature. + This feature allows to enable SCMI per Domain using unique SCMI agent_i= d, + so Domain is identified by EL3 firmware as an SCMI Agent and can access + allowed platform resources through dedicated SMC/HVC Shared memory base= d + transport. + endchoice =20 endmenu diff --git a/xen/arch/arm/firmware/Makefile b/xen/arch/arm/firmware/Makefil= e index 71bdefc24a..37927e690e 100644 --- a/xen/arch/arm/firmware/Makefile +++ b/xen/arch/arm/firmware/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_ARM_SCI) +=3D sci.o obj-$(CONFIG_SCMI_SMC) +=3D scmi-smc.o +obj-$(CONFIG_SCMI_SMC_MA) +=3D scmi-shmem.o scmi-smc-multiagent.o diff --git a/xen/arch/arm/firmware/scmi-proto.h b/xen/arch/arm/firmware/scm= i-proto.h new file mode 100644 index 0000000000..49f63cfc0a --- /dev/null +++ b/xen/arch/arm/firmware/scmi-proto.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Arm System Control and Management Interface definitions + * Version 3.0 (DEN0056C) + * + * Copyright (c) 2025 EPAM Systems + */ + +#ifndef ARM_FIRMWARE_SCMI_PROTO_H_ +#define ARM_FIRMWARE_SCMI_PROTO_H_ + +#include + +#define SCMI_SHORT_NAME_MAX_SIZE 16 + +/* SCMI status codes. See section 4.1.4 */ +#define SCMI_SUCCESS 0 +#define SCMI_NOT_SUPPORTED (-1) +#define SCMI_INVALID_PARAMETERS (-2) +#define SCMI_DENIED (-3) +#define SCMI_NOT_FOUND (-4) +#define SCMI_OUT_OF_RANGE (-5) +#define SCMI_BUSY (-6) +#define SCMI_COMMS_ERROR (-7) +#define SCMI_GENERIC_ERROR (-8) +#define SCMI_HARDWARE_ERROR (-9) +#define SCMI_PROTOCOL_ERROR (-10) + +/* Protocol IDs */ +#define SCMI_BASE_PROTOCOL 0x10 + +/* Base protocol message IDs */ +#define SCMI_BASE_PROTOCOL_VERSION 0x0 +#define SCMI_BASE_PROTOCOL_ATTIBUTES 0x1 +#define SCMI_BASE_PROTOCOL_MESSAGE_ATTRIBUTES 0x2 +#define SCMI_BASE_DISCOVER_AGENT 0x7 +#define SCMI_BASE_SET_DEVICE_PERMISSIONS 0x9 +#define SCMI_BASE_RESET_AGENT_CONFIGURATION 0xB + +typedef struct scmi_msg_header { + uint8_t id; + uint8_t type; + uint8_t protocol; + uint32_t status; +} scmi_msg_header_t; + +/* Table 2 Message header format */ +#define SCMI_HDR_ID GENMASK(7, 0) +#define SCMI_HDR_TYPE GENMASK(9, 8) +#define SCMI_HDR_PROTO GENMASK(17, 10) + +#define SCMI_FIELD_GET(_mask, _reg) = \ + ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1))) +#define SCMI_FIELD_PREP(_mask, _val) = \ + (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask)) + +static inline uint32_t pack_scmi_header(scmi_msg_header_t *hdr) +{ + return SCMI_FIELD_PREP(SCMI_HDR_ID, hdr->id) | + SCMI_FIELD_PREP(SCMI_HDR_TYPE, hdr->type) | + SCMI_FIELD_PREP(SCMI_HDR_PROTO, hdr->protocol); +} + +static inline void unpack_scmi_header(uint32_t msg_hdr, scmi_msg_header_t = *hdr) +{ + hdr->id =3D SCMI_FIELD_GET(SCMI_HDR_ID, msg_hdr); + hdr->type =3D SCMI_FIELD_GET(SCMI_HDR_TYPE, msg_hdr); + hdr->protocol =3D SCMI_FIELD_GET(SCMI_HDR_PROTO, msg_hdr); +} + +static inline int scmi_to_xen_errno(int scmi_status) +{ + if ( scmi_status =3D=3D SCMI_SUCCESS ) + return 0; + + switch ( scmi_status ) + { + case SCMI_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SCMI_INVALID_PARAMETERS: + return -EINVAL; + case SCMI_DENIED: + return -EACCES; + case SCMI_NOT_FOUND: + return -ENOENT; + case SCMI_OUT_OF_RANGE: + return -ERANGE; + case SCMI_BUSY: + return -EBUSY; + case SCMI_COMMS_ERROR: + return -ENOTCONN; + case SCMI_GENERIC_ERROR: + return -EIO; + case SCMI_HARDWARE_ERROR: + return -ENXIO; + case SCMI_PROTOCOL_ERROR: + return -EBADMSG; + default: + return -EINVAL; + } +} + +/* PROTOCOL_VERSION */ +#define SCMI_VERSION_MINOR GENMASK(15, 0) +#define SCMI_VERSION_MAJOR GENMASK(31, 16) + +struct scmi_msg_prot_version_p2a { + uint32_t version; +} __packed; + +/* BASE PROTOCOL_ATTRIBUTES */ +#define SCMI_BASE_ATTR_NUM_PROTO GENMASK(7, 0) +#define SCMI_BASE_ATTR_NUM_AGENT GENMASK(15, 8) + +struct scmi_msg_base_attributes_p2a { + uint32_t attributes; +} __packed; + +/* + * BASE_DISCOVER_AGENT + */ +#define SCMI_BASE_AGENT_ID_OWN 0xFFFFFFFF + +struct scmi_msg_base_discover_agent_a2p { + uint32_t agent_id; +} __packed; + +struct scmi_msg_base_discover_agent_p2a { + uint32_t agent_id; + char name[SCMI_SHORT_NAME_MAX_SIZE]; +} __packed; + +/* + * BASE_SET_DEVICE_PERMISSIONS + */ +#define SCMI_BASE_DEVICE_ACCESS_ALLOW BIT(0, UL) + +struct scmi_msg_base_set_device_permissions_a2p { + uint32_t agent_id; + uint32_t device_id; + uint32_t flags; +} __packed; + +/* + * BASE_RESET_AGENT_CONFIGURATION + */ +#define SCMI_BASE_AGENT_PERMISSIONS_RESET BIT(0, UL) + +struct scmi_msg_base_reset_agent_cfg_a2p { + uint32_t agent_id; + uint32_t flags; +} __packed; + +#endif /* ARM_FIRMWARE_SCMI_PROTO_H_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/firmware/scmi-shmem.c b/xen/arch/arm/firmware/scm= i-shmem.c new file mode 100644 index 0000000000..e36745a85e --- /dev/null +++ b/xen/arch/arm/firmware/scmi-shmem.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SMC/HVC shmem transport implementation used by + * SCI SCMI multi-agent driver. + * + * Oleksii Moisieiev + * Copyright (c) 2025 EPAM Systems + */ + +#include +#include +#include + +#include "scmi-proto.h" +#include "scmi-shmem.h" + +static inline int +shmem_channel_status(const volatile struct scmi_shared_mem __iomem *shmem) +{ + return (readl(&shmem->channel_status) & + SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE) ? 0 : -EBUSY; +} + +int shmem_put_message(volatile struct scmi_shared_mem __iomem *shmem, + scmi_msg_header_t *hdr, void *data, unsigned int len= ) +{ + int ret; + + if ( (len + offsetof(struct scmi_shared_mem, msg_payload)) > + SCMI_SHMEM_MAPPED_SIZE ) + { + printk(XENLOG_ERR "scmi: Wrong size of smc message. Data is invali= d\n"); + return -EINVAL; + } + + ret =3D shmem_channel_status(shmem); + if ( ret ) + return ret; + + writel_relaxed(0x0, &shmem->channel_status); + /* Writing 0x0 right now, but "shmem"_FLAG_INTR_ENABLED can be set */ + writel_relaxed(0x0, &shmem->flags); + writel_relaxed(sizeof(shmem->msg_header) + len, &shmem->length); + writel(pack_scmi_header(hdr), &shmem->msg_header); + + if ( len > 0 && data ) + memcpy_toio(shmem->msg_payload, data, len); + + return 0; +} + +int shmem_get_response(const volatile struct scmi_shared_mem __iomem *shme= m, + scmi_msg_header_t *hdr, void *data, unsigned int le= n) +{ + int recv_len; + int ret; + /* + * First word of msg_payload carries the returned status; exclude it f= rom + * recv_len so only the protocol payload is copied back to the caller. + */ + int pad =3D sizeof(hdr->status); + + if ( len >=3D SCMI_SHMEM_MAPPED_SIZE - + offsetof(struct scmi_shared_mem, msg_payload) ) + { + printk(XENLOG_ERR + "scmi: Wrong size of input smc message. Data may be invalid= \n"); + return -EINVAL; + } + + ret =3D shmem_channel_status(shmem); + if ( ret ) + return ret; + + recv_len =3D readl(&shmem->length) - sizeof(shmem->msg_header); + + if ( recv_len < 0 ) + { + printk(XENLOG_ERR + "scmi: Wrong size of smc message. Data may be invalid\n"); + return -EINVAL; + } + + unpack_scmi_header(readl(&shmem->msg_header), hdr); + + hdr->status =3D readl(&shmem->msg_payload); + recv_len =3D recv_len > pad ? recv_len - pad : 0; + + ret =3D scmi_to_xen_errno(hdr->status); + if ( ret ) + { + printk(XENLOG_DEBUG "scmi: Error received: %d\n", ret); + return ret; + } + + if ( recv_len > len ) + { + printk(XENLOG_ERR + "scmi: Not enough buffer for message %d, expecting %d\n", + recv_len, len); + return -EINVAL; + } + + if ( recv_len > 0 ) + memcpy_fromio(data, shmem->msg_payload + pad, recv_len); + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/firmware/scmi-shmem.h b/xen/arch/arm/firmware/scm= i-shmem.h new file mode 100644 index 0000000000..722263aa77 --- /dev/null +++ b/xen/arch/arm/firmware/scmi-shmem.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Arm System Control and Management Interface definitions + * Version 3.0 (DEN0056C) + * Shared Memory based Transport + * + * Copyright (c) 2024 EPAM Systems + */ + +#ifndef ARM_FIRMWARE_SCMI_SHMEM_H_ +#define ARM_FIRMWARE_SCMI_SHMEM_H_ + +#include + +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE BIT(0, UL) +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1, UL) + +struct scmi_shared_mem { + uint32_t reserved; + uint32_t channel_status; + uint32_t reserved1[2]; + uint32_t flags; + uint32_t length; + uint32_t msg_header; + uint8_t msg_payload[]; +}; + +#define SCMI_SHMEM_MAPPED_SIZE PAGE_SIZE + +int shmem_put_message(volatile struct scmi_shared_mem __iomem *shmem, + scmi_msg_header_t *hdr, void *data, unsigned int len= ); + +int shmem_get_response(const volatile struct scmi_shared_mem __iomem *shme= m, + scmi_msg_header_t *hdr, void *data, unsigned int le= n); +#endif /* ARM_FIRMWARE_SCMI_SHMEM_H_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/firmware/scmi-smc-multiagent.c b/xen/arch/arm/fir= mware/scmi-smc-multiagent.c new file mode 100644 index 0000000000..113af22ec3 --- /dev/null +++ b/xen/arch/arm/firmware/scmi-smc-multiagent.c @@ -0,0 +1,830 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCI SCMI multi-agent driver, using SMC/HVC shmem as transport. + * + * Oleksii Moisieiev + * Copyright (c) 2025 EPAM Systems + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "scmi-proto.h" +#include "scmi-shmem.h" + +#define SCMI_SECONDARY_AGENTS "scmi-secondary-agents" + +struct scmi_channel { + uint32_t agent_id; + uint32_t func_id; + domid_t domain_id; + uint64_t paddr; + struct scmi_shared_mem __iomem *shmem; + spinlock_t lock; + struct list_head list; +}; + +struct scmi_data { + struct list_head channel_list; + spinlock_t channel_list_lock; + uint32_t func_id; + bool initialized; + uint32_t shmem_phandle; + uint32_t hyp_channel_agent_id; + struct dt_device_node *dt_dev; +}; + +static struct scmi_data scmi_data; + +static bool scmi_is_under_xen_sci(const struct dt_device_node *node) +{ + const struct dt_device_node *p; + + for ( p =3D node->parent; p; p =3D p->parent ) + if ( dt_device_is_compatible(p, "xen,sci") ) + return true; + + return false; +} + +static int send_smc_message(struct scmi_channel *chan_info, + scmi_msg_header_t *hdr, void *data, int len) +{ + struct arm_smccc_res resp; + int ret; + + ret =3D shmem_put_message(chan_info->shmem, hdr, data, len); + if ( ret ) + return ret; + + arm_smccc_1_1_smc(chan_info->func_id, 0, 0, 0, 0, 0, 0, 0, &resp); + + if ( resp.a0 =3D=3D (unsigned long)ARM_SMCCC_INVALID_PARAMETER ) + return -EINVAL; + + if ( resp.a0 ) + return -EOPNOTSUPP; + + return 0; +} + +static int do_smc_xfer(struct scmi_channel *chan_info, scmi_msg_header_t *= hdr, + void *tx_data, int tx_size, void *rx_data, int rx_s= ize) +{ + int ret =3D 0; + + ASSERT(chan_info && chan_info->shmem); + + if ( !hdr ) + return -EINVAL; + + spin_lock(&chan_info->lock); + + printk(XENLOG_DEBUG + "scmi: agent_id =3D %d msg_id =3D %x type =3D %d, proto =3D %x\= n", + chan_info->agent_id, hdr->id, hdr->type, hdr->protocol); + + ret =3D send_smc_message(chan_info, hdr, tx_data, tx_size); + if ( ret ) + goto clean; + + ret =3D shmem_get_response(chan_info->shmem, hdr, rx_data, rx_size); + +clean: + printk(XENLOG_DEBUG + "scmi: get smc response agent_id =3D %d msg_id =3D %x proto =3D= %x res=3D%d\n", + chan_info->agent_id, hdr->id, hdr->protocol, ret); + + spin_unlock(&chan_info->lock); + + return ret; +} + +static struct scmi_channel *get_channel_by_id(uint32_t agent_id) +{ + struct scmi_channel *curr; + bool found =3D false; + + spin_lock(&scmi_data.channel_list_lock); + list_for_each_entry(curr, &scmi_data.channel_list, list) + { + if ( curr->agent_id =3D=3D agent_id ) + { + found =3D true; + break; + } + } + + spin_unlock(&scmi_data.channel_list_lock); + if ( found ) + return curr; + + return NULL; +} + +static struct scmi_channel *acquire_scmi_channel(struct domain *d, + uint32_t agent_id) +{ + struct scmi_channel *curr; + struct scmi_channel *ret =3D ERR_PTR(-ENOENT); + + spin_lock(&scmi_data.channel_list_lock); + list_for_each_entry(curr, &scmi_data.channel_list, list) + { + if ( curr->agent_id =3D=3D agent_id ) + { + if ( curr->domain_id !=3D DOMID_INVALID ) + { + ret =3D ERR_PTR(-EEXIST); + break; + } + + curr->domain_id =3D d->domain_id; + ret =3D curr; + break; + } + } + + spin_unlock(&scmi_data.channel_list_lock); + + return ret; +} + +static void relinquish_scmi_channel(struct scmi_channel *channel) +{ + ASSERT(channel !=3D NULL); + + spin_lock(&scmi_data.channel_list_lock); + channel->domain_id =3D DOMID_INVALID; + spin_unlock(&scmi_data.channel_list_lock); +} + +static int map_channel_memory(struct scmi_channel *channel) +{ + ASSERT(channel && channel->paddr); + channel->shmem =3D ioremap_nocache(channel->paddr, SCMI_SHMEM_MAPPED_S= IZE); + if ( !channel->shmem ) + return -ENOMEM; + + channel->shmem->channel_status =3D SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE; + printk(XENLOG_DEBUG "scmi: Got shmem %lx after vmap %p\n", channel->pa= ddr, + channel->shmem); + + return 0; +} + +static void unmap_channel_memory(struct scmi_channel *channel) +{ + ASSERT(channel); + + if ( !channel->shmem ) + return; + + iounmap(channel->shmem); + channel->shmem =3D NULL; +} + +static struct scmi_channel *smc_create_channel(uint32_t agent_id, + uint32_t func_id, uint64_t = addr) +{ + struct scmi_channel *channel, *curr; + + spin_lock(&scmi_data.channel_list_lock); + + /* Check if channel already exists while holding the lock */ + list_for_each_entry(curr, &scmi_data.channel_list, list) + { + if ( curr->agent_id =3D=3D agent_id ) + { + spin_unlock(&scmi_data.channel_list_lock); + return ERR_PTR(-EEXIST); + } + } + + channel =3D xmalloc(struct scmi_channel); + if ( !channel ) + { + spin_unlock(&scmi_data.channel_list_lock); + return ERR_PTR(-ENOMEM); + } + + spin_lock_init(&channel->lock); + channel->agent_id =3D agent_id; + channel->func_id =3D func_id; + channel->domain_id =3D DOMID_INVALID; + channel->shmem =3D NULL; + channel->paddr =3D addr; + list_add_tail(&channel->list, &scmi_data.channel_list); + + spin_unlock(&scmi_data.channel_list_lock); + return channel; +} + +static void free_channel_list(void) +{ + struct scmi_channel *curr, *_curr; + /* + * Called only on the __init error path, before any runtime users exis= t, + * so no other thread is iterating channel_list. Keep the lock for the + * whole drain for clarity and to avoid misleading readers about possi= ble + * concurrent access. + */ + spin_lock(&scmi_data.channel_list_lock); + list_for_each_entry_safe(curr, _curr, &scmi_data.channel_list, list) + { + list_del(&curr->list); + xfree(curr); + } + spin_unlock(&scmi_data.channel_list_lock); +} + +static int __init +scmi_dt_read_hyp_channel_addr(struct dt_device_node *scmi_node, u64 *addr, + u64 *size) +{ + struct dt_device_node *shmem_node; + const __be32 *prop; + + prop =3D dt_get_property(scmi_node, "shmem", NULL); + if ( !prop ) + return -EINVAL; + + shmem_node =3D dt_find_node_by_phandle(be32_to_cpu(*prop)); + if ( IS_ERR_OR_NULL(shmem_node) ) + { + printk(XENLOG_ERR + "scmi: Device tree error, can't parse reserved memory %ld\n= ", + PTR_ERR(shmem_node)); + return PTR_ERR(shmem_node); + } + + return dt_device_get_address(shmem_node, 0, addr, size); +} + +/* + * Handle Dom0 SCMI specific DT nodes + * + * Make a decision on copying SCMI specific nodes into Dom0 device tree. + * For SCMI multi-agent case: + * - shmem nodes will not be copied and generated instead if SCMI + * is enabled for Dom0 + * - scmi node will be copied if SCMI is enabled for Dom0 + */ +static bool scmi_dt_handle_node(struct domain *d, struct dt_device_node *n= ode) +{ + static const struct dt_device_match shmem_matches[] __initconst =3D { + DT_MATCH_COMPATIBLE("arm,scmi-shmem"), + { /* sentinel */ }, + }; + static const struct dt_device_match scmi_matches[] __initconst =3D { + DT_MATCH_PATH("/firmware/scmi"), + { /* sentinel */ }, + }; + + if ( !scmi_data.initialized ) + return false; + + /* skip scmi shmem node for dom0 if scmi not enabled */ + if ( dt_match_node(shmem_matches, node) && !sci_domain_is_enabled(d) ) + { + dt_dprintk(" Skip scmi shmem node\n"); + return true; + } + + /* drop scmi if not enabled */ + if ( dt_match_node(scmi_matches, node) && !sci_domain_is_enabled(d) ) + { + dt_dprintk(" Skip scmi node\n"); + return true; + } + + return false; +} + +static int scmi_assign_device(uint32_t agent_id, uint32_t device_id, + uint32_t flags) +{ + struct scmi_msg_base_set_device_permissions_a2p tx; + struct scmi_channel *channel; + scmi_msg_header_t hdr; + + channel =3D get_channel_by_id(scmi_data.hyp_channel_agent_id); + if ( !channel ) + return -EINVAL; + + hdr.id =3D SCMI_BASE_SET_DEVICE_PERMISSIONS; + hdr.type =3D 0; + hdr.protocol =3D SCMI_BASE_PROTOCOL; + + tx.agent_id =3D agent_id; + tx.device_id =3D device_id; + tx.flags =3D flags; + + return do_smc_xfer(channel, &hdr, &tx, sizeof(tx), NULL, 0); +} + +static int scmi_dt_assign_device(struct domain *d, + struct dt_phandle_args *ac_spec) +{ + struct scmi_channel *agent_channel; + uint32_t scmi_device_id =3D ac_spec->args[0]; + int ret; + + if ( !d->arch.sci_data ) + return 0; + + /* The access-controllers is specified for DT dev, but it's not a SCMI= */ + if ( !scmi_data.dt_dev || + !dt_node_path_is_equal(ac_spec->np, scmi_data.dt_dev->full_name) = ) + return 0; + + agent_channel =3D d->arch.sci_data; + + spin_lock(&agent_channel->lock); + + ret =3D scmi_assign_device(agent_channel->agent_id, scmi_device_id, + SCMI_BASE_DEVICE_ACCESS_ALLOW); + if ( ret ) + { + printk(XENLOG_ERR + "scmi: could not assign dev for %pd agent:%d dev_id:%u (%d)= ", + d, agent_channel->agent_id, scmi_device_id, ret); + } + + spin_unlock(&agent_channel->lock); + return ret; +} + +static int collect_agent_id(struct scmi_channel *agent_channel) +{ + int ret; + scmi_msg_header_t hdr; + struct scmi_msg_base_discover_agent_p2a da_rx; + struct scmi_msg_base_discover_agent_a2p da_tx; + + ret =3D map_channel_memory(agent_channel); + if ( ret ) + return ret; + + hdr.id =3D SCMI_BASE_DISCOVER_AGENT; + hdr.type =3D 0; + hdr.protocol =3D SCMI_BASE_PROTOCOL; + + da_tx.agent_id =3D agent_channel->agent_id; + + ret =3D do_smc_xfer(agent_channel, &hdr, &da_tx, sizeof(da_tx), &da_rx= , + sizeof(da_rx)); + if ( agent_channel->domain_id !=3D DOMID_XEN ) + unmap_channel_memory(agent_channel); + if ( ret ) + return ret; + + printk(XENLOG_DEBUG "id=3D0x%x name=3D%s\n", da_rx.agent_id, da_rx.nam= e); + agent_channel->agent_id =3D da_rx.agent_id; + return 0; +} + +static __init int collect_agents(struct dt_device_node *scmi_node) +{ + const struct dt_device_node *config_node; + const __be32 *prop; + uint32_t len; + const __be32 *end; + uint32_t cells_per_entry =3D 3; /* Default to 3 cells if property is a= bsent. */ + + config_node =3D dt_find_compatible_node(NULL, NULL, "xen,sci"); + if ( !config_node ) + { + printk(XENLOG_WARNING "scmi: xen,sci node not found, no agents to = collect.\n"); + return -ENOENT; + } + + /* Check for the optional '#scmi-secondary-agents-cells' property. */ + if ( dt_property_read_u32(config_node, "#scmi-secondary-agents-cells", + &cells_per_entry) ) + { + if ( cells_per_entry !=3D 2 && cells_per_entry !=3D 3 ) + { + printk(XENLOG_ERR "scmi: Invalid #scmi-secondary-agents-cells = value: %u\n", + cells_per_entry); + return -EINVAL; + } + } + + prop =3D dt_get_property(config_node, SCMI_SECONDARY_AGENTS, &len); + if ( !prop ) + { + printk(XENLOG_ERR "scmi: No %s property found, no agents to collec= t.\n", + SCMI_SECONDARY_AGENTS); + return -EINVAL; + } + + /* Validate that the property length is a multiple of the cell size. *= / + if ( len =3D=3D 0 || len % (cells_per_entry * sizeof(uint32_t)) !=3D 0= ) + { + printk(XENLOG_ERR "scmi: Invalid length of %s property: %u for %u = cells per entry\n", + SCMI_SECONDARY_AGENTS, len, cells_per_entry); + return -EINVAL; + } + + end =3D (const __be32 *)((const u8 *)prop + len); + + for ( ; prop < end; ) + { + uint32_t agent_id; + uint32_t smc_id; + uint32_t shmem_phandle; + struct dt_device_node *node; + u64 addr, size; + int ret; + struct scmi_channel *agent_channel; + + smc_id =3D be32_to_cpu(*prop++); + shmem_phandle =3D be32_to_cpu(*prop++); + + if ( cells_per_entry =3D=3D 3 ) + agent_id =3D be32_to_cpu(*prop++); + else + agent_id =3D SCMI_BASE_AGENT_ID_OWN; + + node =3D dt_find_node_by_phandle(shmem_phandle); + if ( !node ) + { + printk(XENLOG_ERR "scmi: Could not find shmem node for agent %= u\n", + agent_id); + return -EINVAL; + } + + ret =3D dt_device_get_address(node, 0, &addr, &size); + if ( ret ) + { + printk(XENLOG_ERR + "scmi: Could not read shmem address for agent %u: %d\n"= , + agent_id, ret); + return ret; + } + + if ( !IS_ALIGNED(size, SCMI_SHMEM_MAPPED_SIZE) || + !IS_ALIGNED(addr, SCMI_SHMEM_MAPPED_SIZE) ) + { + printk(XENLOG_ERR "scmi: shmem memory is not aligned\n"); + return -EINVAL; + } + + agent_channel =3D smc_create_channel(agent_id, smc_id, addr); + if ( IS_ERR(agent_channel) ) + { + printk(XENLOG_ERR "scmi: Could not create channel for agent %u= : %ld\n", + agent_id, PTR_ERR(agent_channel)); + return PTR_ERR(agent_channel); + } + + if ( cells_per_entry =3D=3D 2 ) + { + ret =3D collect_agent_id(agent_channel); + if ( ret ) + return ret; + } + + printk(XENLOG_DEBUG "scmi: Agent %u SMC %X addr %lx\n", agent_chan= nel->agent_id, + smc_id, (unsigned long)addr); + } + + return 0; +} + +static int scmi_domain_init(struct domain *d, + struct xen_domctl_createdomain *config) +{ + struct scmi_channel *channel; + int ret; + + if ( !scmi_data.initialized ) + return 0; + + /* + * SCMI support is configured via: + * - For dom0: xen,dom0-sci-agent-id property under the xen,sci contai= ner + * - For dom0less: xen,sci-agent-id in the domain node + * The config->arch.arm_sci_type and config->arch.arm_sci_agent_id + * are already set by domain_build.c or dom0less-build.c + */ + + if ( config->arch.arm_sci_type =3D=3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE ) + return 0; + + channel =3D acquire_scmi_channel(d, config->arch.arm_sci_agent_id); + if ( IS_ERR(channel) ) + { + printk(XENLOG_ERR + "scmi: Failed to acquire SCMI channel for agent_id %u: %ld\= n", + config->arch.arm_sci_agent_id, PTR_ERR(channel)); + return PTR_ERR(channel); + } + + printk(XENLOG_INFO + "scmi: Acquire channel id =3D 0x%x, domain_id =3D %d paddr =3D = 0x%lx\n", + channel->agent_id, channel->domain_id, channel->paddr); + + /* + * Dom0 (if present) needs to have an access to the guest memory range + * to satisfy iomem_access_permitted() check in XEN_DOMCTL_iomem_permi= ssion + * domctl. + */ + if ( hardware_domain && !is_hardware_domain(d) ) + { + ret =3D iomem_permit_access(hardware_domain, paddr_to_pfn(channel-= >paddr), + paddr_to_pfn(channel->paddr + + SCMI_SHMEM_MAPPED_SIZE - 1)); + if ( ret ) + goto error; + } + + d->arch.sci_data =3D channel; + d->arch.sci_enabled =3D true; + + return 0; + +error: + relinquish_scmi_channel(channel); + return ret; +} + +int scmi_domain_sanitise_config(struct xen_domctl_createdomain *config) +{ + if ( config->arch.arm_sci_type !=3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE && + config->arch.arm_sci_type !=3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC= _MA ) + { + dprintk(XENLOG_INFO, "scmi: Unsupported ARM_SCI type\n"); + return -EINVAL; + } + + return 0; +} + +static int scmi_relinquish_resources(struct domain *d) +{ + int ret; + struct scmi_channel *channel, *agent_channel; + scmi_msg_header_t hdr; + struct scmi_msg_base_reset_agent_cfg_a2p tx; + + if ( !d->arch.sci_data ) + return 0; + + agent_channel =3D d->arch.sci_data; + + spin_lock(&agent_channel->lock); + tx.agent_id =3D agent_channel->agent_id; + spin_unlock(&agent_channel->lock); + + channel =3D get_channel_by_id(scmi_data.hyp_channel_agent_id); + if ( !channel ) + { + printk(XENLOG_ERR + "scmi: Unable to get Hypervisor scmi channel for domain %d\= n", + d->domain_id); + return -EINVAL; + } + + hdr.id =3D SCMI_BASE_RESET_AGENT_CONFIGURATION; + hdr.type =3D 0; + hdr.protocol =3D SCMI_BASE_PROTOCOL; + + tx.flags =3D SCMI_BASE_AGENT_PERMISSIONS_RESET; + + ret =3D do_smc_xfer(channel, &hdr, &tx, sizeof(tx), NULL, 0); + if ( ret =3D=3D -EOPNOTSUPP ) + return 0; + + return ret; +} + +static void scmi_domain_destroy(struct domain *d) +{ + struct scmi_channel *channel; + + if ( !d->arch.sci_data ) + return; + + channel =3D d->arch.sci_data; + spin_lock(&channel->lock); + + relinquish_scmi_channel(channel); + printk(XENLOG_DEBUG "scmi: Free domain %d\n", d->domain_id); + + d->arch.sci_data =3D NULL; + d->arch.sci_enabled =3D false; + + spin_unlock(&channel->lock); +} + +static bool scmi_handle_call(struct cpu_user_regs *regs) +{ + uint32_t fid =3D (uint32_t)get_user_reg(regs, 0); + struct scmi_channel *agent_channel; + struct domain *d =3D current->domain; + struct arm_smccc_res resp; + bool res =3D false; + + if ( (!sci_domain_is_enabled(d)) || (!d->arch.sci_data) ) + return false; + + agent_channel =3D d->arch.sci_data; + spin_lock(&agent_channel->lock); + + if ( agent_channel->func_id !=3D fid ) + { + res =3D false; + goto unlock; + } + + arm_smccc_1_1_smc(fid, + get_user_reg(regs, 1), + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &resp); + + set_user_reg(regs, 0, resp.a0); + set_user_reg(regs, 1, resp.a1); + set_user_reg(regs, 2, resp.a2); + set_user_reg(regs, 3, resp.a3); + res =3D true; +unlock: + spin_unlock(&agent_channel->lock); + + return res; +} + +static const struct sci_mediator_ops scmi_ops =3D { + .domain_init =3D scmi_domain_init, + .domain_destroy =3D scmi_domain_destroy, + .relinquish_resources =3D scmi_relinquish_resources, + .handle_call =3D scmi_handle_call, + .dom0_dt_handle_node =3D scmi_dt_handle_node, + .domain_sanitise_config =3D scmi_domain_sanitise_config, + .assign_dt_device =3D scmi_dt_assign_device, +}; + +static int __init scmi_check_smccc_ver(void) +{ + if ( smccc_ver < ARM_SMCCC_VERSION_1_1 ) + { + printk(XENLOG_WARNING + "scmi: No SMCCC 1.1 support, SCMI calls forwarding disabled= \n"); + return -ENOSYS; + } + + return 0; +} + +static int __init scmi_dt_hyp_channel_read(struct dt_device_node *scmi_nod= e, + struct scmi_data *scmi_data, + u64 *addr) +{ + int ret; + u64 size; + + if ( !dt_property_read_u32(scmi_node, "arm,smc-id", &scmi_data->func_i= d) ) + { + printk(XENLOG_ERR "scmi: unable to read smc-id from DT\n"); + return -ENOENT; + } + + ret =3D scmi_dt_read_hyp_channel_addr(scmi_node, addr, &size); + if ( IS_ERR_VALUE(ret) ) + return -ENOENT; + + if ( !IS_ALIGNED(size, SCMI_SHMEM_MAPPED_SIZE) ) + { + printk(XENLOG_ERR "scmi: shmem memory is not aligned\n"); + return -EINVAL; + } + + return 0; +} + +static __init int scmi_probe(struct dt_device_node *scmi_node, const void = *data) +{ + u64 addr; + int ret; + struct scmi_channel *channel; + unsigned int n_agents; + scmi_msg_header_t hdr; + struct scmi_msg_base_attributes_p2a rx; + + ASSERT(scmi_node !=3D NULL); + + /* + * Only bind to the SCMI node provided by Xen under the xen,sci contai= ner + * (e.g. /chosen/xen/xen_scmi_config/scmi). This avoids binding to fir= mware + * SCMI nodes that belong to the host OSPM and keeps the mediator scop= ed to + * Xen-provided configuration only. + */ + if ( !scmi_is_under_xen_sci(scmi_node) ) + return -ENODEV; + + if ( !acpi_disabled ) + { + printk(XENLOG_WARNING "scmi: is not supported when using ACPI\n"); + return -EINVAL; + } + + ret =3D scmi_check_smccc_ver(); + if ( ret ) + return ret; + + ret =3D scmi_dt_hyp_channel_read(scmi_node, &scmi_data, &addr); + if ( ret ) + return ret; + + INIT_LIST_HEAD(&scmi_data.channel_list); + spin_lock_init(&scmi_data.channel_list_lock); + + scmi_data.dt_dev =3D scmi_node; + + channel =3D smc_create_channel(SCMI_BASE_AGENT_ID_OWN, scmi_data.func_= id, addr); + if ( IS_ERR(channel) ) + { + ret =3D PTR_ERR(channel); + goto out; + } + + /* Mark as Xen management channel before collecting agent ID */ + channel->domain_id =3D DOMID_XEN; + + /* Request agent id for Xen management channel */ + ret =3D collect_agent_id(channel); + if ( ret ) + goto error; + + /* Save the agent id for Xen management channel */ + scmi_data.hyp_channel_agent_id =3D channel->agent_id; + + hdr.id =3D SCMI_BASE_PROTOCOL_ATTIBUTES; + hdr.type =3D 0; + hdr.protocol =3D SCMI_BASE_PROTOCOL; + + ret =3D do_smc_xfer(channel, &hdr, NULL, 0, &rx, sizeof(rx)); + if ( ret ) + goto error; + + n_agents =3D SCMI_FIELD_GET(SCMI_BASE_ATTR_NUM_AGENT, rx.attributes); + printk(XENLOG_DEBUG "scmi: Got agent count %d\n", n_agents); + ret =3D collect_agents(scmi_node); + if ( ret ) + goto error; + + ret =3D sci_register(&scmi_ops); + if ( ret ) + { + printk(XENLOG_ERR "SCMI: mediator already registered (ret =3D %d)\= n", + ret); + goto error; + } + + scmi_data.initialized =3D true; + goto out; + +error: + unmap_channel_memory(channel); + free_channel_list(); +out: + return ret; +} + +static const struct dt_device_match scmi_smc_match[] __initconst =3D { + DT_MATCH_COMPATIBLE("arm,scmi-smc"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(scmi_smc_ma, "SCMI SMC MEDIATOR", DEVICE_FIRMWARE) + .dt_match =3D scmi_smc_match, + .init =3D scmi_probe, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index d30a288592..8f0f68544e 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -329,6 +329,7 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); =20 #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 +#define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA 2 =20 struct xen_arch_domainconfig { /* IN/OUT */ @@ -355,6 +356,8 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t arm_sci_agent_id; }; #endif /* __XEN__ || __XEN_TOOLS__ */ =20 --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 16:39:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 16:39:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274257.1560439 (Exim 4.92) (envelope-from ) id 1w9myh-0002bM-Ek; Mon, 06 Apr 2026 16:39:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274257.1560439; Mon, 06 Apr 2026 16:39:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9myh-0002as-9T; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bc3fb145-af4b-48f4-89f8-08de93fb0323 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2026 16:39:02.1128 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3EfzXaYo2ao5+7rfmijynTWYL/Q5FfnOOKH4AZrovJVI+dpmKl4XCRb9+WeGeJWL6Je4ckbdKmx8z/QMvqOWmm9ecjQ5tKU1c4+N6NspZIc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6817 X-purgate-ID: tlsNG-16d1c6/1775493545-AEB333D8-EC0B7C7B/0/0 X-purgate-type: clean X-purgate-size: 8506 Introduce memcpy_fromio() and memcpy_toio() helpers to copy between regular memory and MMIO space on Arm. The generic prototypes live in io.h so other architectures can provide their own implementations. These helpers handle alignment safely by using ordered byte accesses for any leading/trailing unaligned bytes and ordered 32-bit accesses for the aligned bulk transfer. Using the ordered `readb/readl` and `writeb/writel` accessors avoids unintended endianness conversion while respecting device ordering requirements on ARM32/ARM64 hardware that may not support 64-bit MMIO atomically. The interface lives in the generic header so other architectures can provide their own implementations (as macros or functions). The ARM implementation is placed under `arch/arm/lib/` (mirroring the x86 reference layout) and is split into separate compilation units added via the architecture-specific lib Makefile. Signed-off-by: Oleksii Moisieiev --- (no changes since v10) Changes in v10: - removed extra include in memcpy-{to/from}io.c files Changes in v9: - reword commit description to refer to memcpy_fromio and memcpy_toio - ordering obj-y in Makefile - rename ALL_LIBS to ARCH_LIBS - drop io.h and move definitions to the common header, fix comments to be arch neutral - update comments for memcpy_{from/to}io implementation Changes in v8: - switched to ordered accessors to address the ordering and barrier concerns. - updated the documentation to match the implementation and explicitly state the supported access sizes and granularity. - rename memcpy_* implementation files to memcpu-* to follow naming convension - fix indentation to match Xen style - fix intendation to match Xen style - move memcpy-{from/to}io to more convenient library place Changes in v7: - x86 guidance: removed the speculative note; header now just says each arch supplies its own implementation or macro. - name spacing: dropped the double-underscore; the helpers are now memcpy_fromio / memcpy_toio. The header also explicitly allows an arch to define these as macros before including it. - updated io.c to keep 32-bit transfers safe on arm32 - moved to __raw_read*/__raw_write* accessors to avoid endianness conversio= n. - split the helpers into separate compilation units Changes in v6: - sorted objs in Makefile alhabetically - added newline at the end of Makefile - used uint{N}_t intead of u{N} - add comment about why 32 bit IO operations were used - updated cast opertaions to avoid dropping constness which is wrong - move function definitions to generic place so the could be reused by other arch - add SPDX tag to io.c Changes in v5: - move memcpy_toio/fromio to the generic place xen/arch/arm/Makefile | 1 + xen/arch/arm/arch.mk | 1 + xen/arch/arm/lib/Makefile | 2 ++ xen/arch/arm/lib/memcpy-fromio.c | 55 ++++++++++++++++++++++++++++++++ xen/arch/arm/lib/memcpy-toio.c | 55 ++++++++++++++++++++++++++++++++ xen/include/xen/io.h | 10 ++++++ 6 files changed, 124 insertions(+) create mode 100644 xen/arch/arm/lib/Makefile create mode 100644 xen/arch/arm/lib/memcpy-fromio.c create mode 100644 xen/arch/arm/lib/memcpy-toio.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 7494a0f926..5b8e170e01 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -8,6 +8,7 @@ ifneq ($(CONFIG_NO_PLAT),y) obj-y +=3D platforms/ endif obj-y +=3D firmware/ +obj-y +=3D lib/ obj-$(CONFIG_TEE) +=3D tee/ obj-$(CONFIG_HAS_VPCI) +=3D vpci.o =20 diff --git a/xen/arch/arm/arch.mk b/xen/arch/arm/arch.mk index dea8dbd18a..009bb22c45 100644 --- a/xen/arch/arm/arch.mk +++ b/xen/arch/arm/arch.mk @@ -2,6 +2,7 @@ # arm-specific definitions =20 ARCH_LIBS-y +=3D arch/arm/$(ARCH)/lib/lib.a +ARCH_LIBS-y +=3D arch/arm/lib/lib.a =20 $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) $(call cc-option-add,CFLAGS,CC,-Wnested-externs) diff --git a/xen/arch/arm/lib/Makefile b/xen/arch/arm/lib/Makefile new file mode 100644 index 0000000000..07a0d9186c --- /dev/null +++ b/xen/arch/arm/lib/Makefile @@ -0,0 +1,2 @@ +lib-y +=3D memcpy-fromio.o +lib-y +=3D memcpy-toio.o diff --git a/xen/arch/arm/lib/memcpy-fromio.c b/xen/arch/arm/lib/memcpy-fro= mio.c new file mode 100644 index 0000000000..3b27ab2949 --- /dev/null +++ b/xen/arch/arm/lib/memcpy-fromio.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * Arm implementation notes / limitations: + * - Uses ordered 8-bit for leading/trailing unaligned bytes and ordered + * 32-bit accesses for the aligned bulk; no wider accesses are issued. + * - Only suitable for devices that tolerate 8-bit and 32-bit accesses; + * do not use with devices requiring strictly 16-bit or 64-bit accesses. + * - MMIO must be mapped with appropriate device attributes to preserve + * ordering; no extra barriers beyond the ordered accessors are added. + * - If source or destination is misaligned, leading bytes are copied + * byte-by-byte until both sides are 32-bit aligned, then bulk copy uses + * 32-bit accesses. + */ + +void memcpy_fromio(void *to, const volatile void __iomem *from, + size_t count) +{ + while ( count && (!IS_ALIGNED((unsigned long)from, 4) || + !IS_ALIGNED((unsigned long)to, 4)) ) + { + *(uint8_t *)to =3D readb(from); + from++; + to++; + count--; + } + + while ( count >=3D 4 ) + { + *(uint32_t *)to =3D readl(from); + from +=3D 4; + to +=3D 4; + count -=3D 4; + } + + while ( count ) + { + *(uint8_t *)to =3D readb(from); + from++; + to++; + count--; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 8 + * tab-width: 8 + * indent-tabs-mode: t + * End: + */ diff --git a/xen/arch/arm/lib/memcpy-toio.c b/xen/arch/arm/lib/memcpy-toio.= c new file mode 100644 index 0000000000..a6ad08b805 --- /dev/null +++ b/xen/arch/arm/lib/memcpy-toio.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * Arm implementation notes / limitations: + * - Uses ordered 8-bit for leading/trailing unaligned bytes and ordered + * 32-bit accesses for the aligned bulk; no wider accesses are issued. + * - Only suitable for devices that tolerate 8-bit and 32-bit accesses; + * do not use with devices requiring strictly 16-bit or 64-bit accesses. + * - MMIO must be mapped with appropriate device attributes to preserve + * ordering; no extra barriers beyond the ordered accessors are added. + * - If source or destination is misaligned, leading bytes are copied + * byte-by-byte until both sides are 32-bit aligned, then bulk copy uses + * 32-bit accesses. + */ + +void memcpy_toio(volatile void __iomem *to, const void *from, + size_t count) +{ + while ( count && (!IS_ALIGNED((unsigned long)to, 4) || + !IS_ALIGNED((unsigned long)from, 4)) ) + { + writeb(*(const uint8_t *)from, to); + from++; + to++; + count--; + } + + while ( count >=3D 4 ) + { + writel(*(const uint32_t *)from, to); + from +=3D 4; + to +=3D 4; + count -=3D 4; + } + + while ( count ) + { + writeb(*(const uint8_t *)from, to); + from++; + to++; + count--; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 8 + * tab-width: 8 + * indent-tabs-mode: t + * End: + */ diff --git a/xen/include/xen/io.h b/xen/include/xen/io.h index 164a20c5d7..1bb164b6ef 100644 --- a/xen/include/xen/io.h +++ b/xen/include/xen/io.h @@ -67,4 +67,14 @@ static inline bool write_mmio(volatile void __iomem *mem= , unsigned long data, return true; } =20 +/* + * Copy between regular memory and MMIO space. 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b=YNh8M6zv/jwEB98LKw5OMOWWCzpm2OgWeVtV8GbdAK1pf8gtZ0d13Lw7P54jUyGC6rHLkkf52MTJ/5S8ZA+hJSRnKGX51ITzteE5ncCzN6LJTmYy7HpLeAMrLKUIKCbPREmbUX+Tfbq8WuGyLpyhfhRR1Lhdrp//nPJy3zahvRfjRTgp3lMQweYHWyRrcoAQn3lM6vRxlWmIfZ9a3DUQT30jcs7yM1ej3Bfy7NdpGotKYmbSXZVp2j6IxikahqtxEQPrC+D4KUzcac02BkQ11zCtjjLiOcqMqIevWvRKqgwDCwdryJqYuWks6YD8u2DJnj8cDZpK3qY72cApaZU6wA== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Andrew Cooper , Anthony PERARD , Bertrand Marquis , Jan Beulich , Juergen Gross , Julien Grall , Michal Orzel , Oleksii Moisieiev , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Stefano Stabellini , Volodymyr Babchuk , Grygorii Strashko Subject: [PATCH v11 5/6] tools/xl/libxl: wire up SCMI SMC multi-agent configuration Thread-Topic: [PATCH v11 5/6] tools/xl/libxl: wire up SCMI SMC multi-agent configuration Thread-Index: AQHcxePgoYX5wHyqiEi/h1nBRfSR5g== Date: Mon, 6 Apr 2026 16:39:02 +0000 Message-ID: <34173027f83b00181688d33a5adf4b6a1f0e031a.1775493499.git.oleksii_moisieiev@epam.com> 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X-MS-Exchange-CrossTenant-Network-Message-Id: 3f01544f-a4c2-4cb4-548c-08de93fb0374 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2026 16:39:02.8147 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: r+T6ILgFiPZcq8QGPHZEArH8ZYKRUqb/ZZ5Tk9l1TvC70OfSArMYhyz1eGiJGPmxr3wBH5jGIVxQAFbPC9Ds8hLTNaOApo0SdGGwUiZduew= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6817 X-purgate-ID: tlsNG-16d1c6/1775493545-5E9323D8-ECE35C10/0/0 X-purgate-type: clean X-purgate-size: 6139 Plumb the SCMI SMC multi-agent type through the toolstack: - Extend libxl_arm_sci_type enumeration with scmi_smc_multiagent (value 2) - Add agent_id field to libxl_arm_sci structure for per-domain agent assign= ment - Update libxl_arm.c to translate libxl config to XEN_DOMCTL_CONFIG_ARM_SCI= _SCMI_SMC_MA and pass agent_id to the hypervisor via xen_domctl_createdomain - Add xl.cfg parsing for arm_sci=3D"type=3Dscmi_smc_multiagent,agent_id=3DN= " - Document the new xl.cfg options in xl.cfg.5.pod.in This completes the userspace side of multi-agent SCMI, allowing xl create and dom0less configurations to assign unique agent_id values to domains. Signed-off-by: Grygorii Strashko Signed-off-by: Oleksii Moisieiev --- Changes in v11: - Fix agent_id documentation: clarify it applies to SCMI SMC multi-agent support only, not plain SCMI SMC (reviewer feedback) - Remove "non-zero" from agent_id description to match accepted range [0..254] - Remove "UINT8_MAX (255) is treated as invalid" from user documentation as unnecessary implementation detail - Add LIBXL_HAVE_SCMI_SMC_MULTIAGENT feature macro in libxl.h to advertise the new scmi_smc_multiagent type and agent_id field - Add agent_id validation in libxl__arch_domain_build_info_setdefault() to reject invalid values at the libxl level, not only in xl Changes in v10: - Split hypervisor and toolstack changes into separate commits docs/man/xl.cfg.5.pod.in | 13 +++++++++++++ tools/include/libxl.h | 8 ++++++++ tools/libs/light/libxl_arm.c | 13 +++++++++++++ tools/libs/light/libxl_types.idl | 4 +++- tools/xl/xl_parse.c | 12 ++++++++++++ 5 files changed, 49 insertions(+), 1 deletion(-) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 27c455210b..f642558892 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -3156,8 +3156,21 @@ single SCMI OSPM agent support. Should be used together with B Xen command line option. =20 +=3Ditem B + +Enables ARM SCMI SMC multi-agent support for the guest by enabling SCMI ov= er +SMC calls forwarding from domain to the EL3 firmware (like Trusted Firmwar= e-A) +with a multi SCMI OSPM agent support. The SCMI B should be +specified for the guest. + =3Dback =20 +=3Ditem B + +Specifies an ARM SCI agent id for the guest. This option is mandatory +if the SCMI SMC multi-agent support is enabled for the guest. The agent id= s of +domains existing on a single host must be unique and in the range [0..254]= . + =3Dback =20 =3Dback diff --git a/tools/include/libxl.h b/tools/include/libxl.h index bc35e412da..99f2734447 100644 --- a/tools/include/libxl.h +++ b/tools/include/libxl.h @@ -318,6 +318,14 @@ */ #define LIBXL_HAVE_BUILDINFO_ARCH_ARM_SCI 1 =20 +/* + * LIBXL_HAVE_SCMI_SMC_MULTIAGENT indicates that the + * LIBXL_ARM_SCI_TYPE_SCMI_SMC_MULTIAGENT value is available in the + * libxl_arm_sci_type enumeration and the agent_id field is available + * in the libxl_arm_sci structure. + */ +#define LIBXL_HAVE_SCMI_SMC_MULTIAGENT 1 + /* * LIBXL_HAVE_SOFT_RESET indicates that libxl supports performing * 'soft reset' for domains and there is 'soft_reset' shutdown reason diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c index e4407d6e3f..3adb90c286 100644 --- a/tools/libs/light/libxl_arm.c +++ b/tools/libs/light/libxl_arm.c @@ -240,6 +240,10 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, case LIBXL_ARM_SCI_TYPE_SCMI_SMC: config->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC; break; + case LIBXL_ARM_SCI_TYPE_SCMI_SMC_MULTIAGENT: + config->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_M= A; + config->arch.arm_sci_agent_id =3D d_config->b_info.arch_arm.arm_sc= i.agent_id; + break; default: LOG(ERROR, "Unknown ARM_SCI type %d", d_config->b_info.arch_arm.arm_sci.type); @@ -1837,6 +1841,15 @@ int libxl__arch_domain_build_info_setdefault(libxl__= gc *gc, } } =20 + /* Sanitise ARM SCI agent_id parameter */ + if (b_info->arch_arm.arm_sci.type =3D=3D LIBXL_ARM_SCI_TYPE_SCMI_SMC_M= ULTIAGENT && + b_info->arch_arm.arm_sci.agent_id >=3D UINT8_MAX) { + LOG(ERROR, + "Invalid ARM SCI agent_id: %u. Valid range is [0..254]", + b_info->arch_arm.arm_sci.agent_id); + return ERROR_FAIL; + } + if (b_info->type !=3D LIBXL_DOMAIN_TYPE_PV) return 0; =20 diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_type= s.idl index 4a958f69f4..9bfbf09145 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -554,11 +554,13 @@ libxl_sve_type =3D Enumeration("sve_type", [ =20 libxl_arm_sci_type =3D Enumeration("arm_sci_type", [ (0, "none"), - (1, "scmi_smc") + (1, "scmi_smc"), + (2, "scmi_smc_multiagent") ], init_val =3D "LIBXL_ARM_SCI_TYPE_NONE") =20 libxl_arm_sci =3D Struct("arm_sci", [ ("type", libxl_arm_sci_type), + ("agent_id", uint8) ]) =20 libxl_rdm_reserve =3D Struct("rdm_reserve", [ diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 1cc41f1bff..2f1b475022 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -1306,6 +1306,18 @@ static int parse_arm_sci_config(XLU_Config *cfg, lib= xl_arm_sci *arm_sci, } } =20 + if (MATCH_OPTION("agent_id", ptr, oparg)) { + unsigned long val =3D parse_ulong(oparg); + + if ( val >=3D UINT8_MAX ) { + fprintf(stderr, "An invalid ARM_SCI agent_id specified (%l= u). Valid range [0..254]\n", + val); + ret =3D ERROR_INVAL; + goto out; + } + arm_sci->agent_id =3D val; + } + ptr =3D strtok(NULL, ","); } =20 --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 16:39:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 16:39:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274261.1560469 (Exim 4.92) (envelope-from ) id 1w9myk-0003Qw-2W; Mon, 06 Apr 2026 16:39:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274261.1560469; Mon, 06 Apr 2026 16:39:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9myj-0003QN-Tf; Mon, 06 Apr 2026 16:39:09 +0000 Received: by outflank-mailman (input) for mailman id 1274261; Mon, 06 Apr 2026 16:39:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9myh-0002gs-PI for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 39c805a7-70d5-447a-a831-08de93fb0394 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Apr 2026 16:39:03.1460 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ThfrslhLI5Ix7SFWuhhmSh3EsMN0XzQRrSEqjRuOBsYufoB/ArqztpYI2zoJqSw2JohoQu8CsR9I8U6YqfuUf/H3EOxKR2/g97YgK/yXMdM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6817 X-purgate-ID: tlsNG-16d1c6/1775493547-5E12E3D8-633038CC/0/0 X-purgate-type: clean X-purgate-size: 18936 From: Grygorii Strashko Add SCI SCMI SMC multi-agent driver documentation. It includes a detailed description of the SCMI multi-agent driver. This document explains the driver's functionality, configuration, and the compilation process. The Xen SCMI multi-agent driver is designed to provide SCMI access to system resources from different domains. Signed-off-by: Grygorii Strashko Signed-off-by: Oleksii Moisieiev --- (no changes since v10) Changes in v10: - rephrase section about /firmware/scmi. Mentioned that this node is taken from Host DT and copied unmodified. - fix xen,reg address for secondary domains for Dom0less configuration Changes in v8: - update documentation to match the last DT format - fixed RST: "... code-block:: dts" -> ".. code-block:: dts" - update documentation with dom0less configuration example - update documentation with new param xen,dom0-sci-agent-id instead of the command line parameter Changes in v7: - update documentation in section of the xen_scmi configuration which is matched by "xen,sci" compatible instead of the direct path. Changes in v6: - remove all HVC mentions from the multi-agent doc - update sci-agent-id parameter description in the documentation - add missing Sign-of - minor fixes across the document Changes in v5: - rework multi-agent driver to leave Host Device-tree unmodified .../arm/firmware/arm-scmi.rst | 422 ++++++++++++++++++ 1 file changed, 422 insertions(+) diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervi= sor-guide/arm/firmware/arm-scmi.rst index d9698f4e4b..8791bc665e 100644 --- a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst +++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst @@ -36,6 +36,8 @@ The below sections describe SCMI support options availabl= e for Xen. =20 | [1] `Arm SCMI `= _ | [2] `System Control and Management Interface (SCMI) bindings `_ +| [3] `Generic Domain Access Controllers bindings `_ + =20 Simple SCMI over SMC calls forwarding driver (EL3) ------------------------------------------------------ @@ -189,3 +191,423 @@ except explicitly enabling SCMI with "arm_sci" xl.cfg= option. -> xen,reg =3D <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>; -> xen,force-assign-without-iommu; }; + +SCMI SMC multi-agent driver (EL3) +------------------------------------- + +The SCMI SMC multi-agent driver enables support for ARM EL3 Trusted Firmwa= re-A (TF-A) which +provides SCMI interface with multi-agent support, as shown below. + +:: + + +-----------------------------------------+ + | | + | EL3 TF-A SCMI | + +-------+--+-------+--+-------+--+-------++ + |shmem1 | |shmem0 | |shmem2 | |shmemX | + +-----+-+ +---+---+ +--+----+ +---+---+ + smc-id1 | | | | + agent1 | | | | + +-----v--------+---------+-----------+----+ + | | | | | + | | | | | + +--------------+---------+-----------+----+ + smc-id0 | smc-id2| smc-idX| + agent0 | agent2 | agentX | + | | | + +----v---+ +--v-----+ +--v-----+ + | | | | | | + | Dom0 | | Dom1 | | DomX | + | | | | | | + | | | | | | + +--------+ +--------+ +--------+ + +The EL3 SCMI multi-agent firmware is expected to provide SCMI SMC shared-m= emory transport +for every Agent in the system. The SCMI Agent transport channel defined by= pair: + +- smc-id: SMC function id used for Doorbell +- shmem: shared memory for messages transfer, **Xen page aligned**. + Shared memory is mapped with the following flags: MT_DEVICE_nGnRE and _P= AGE_DEVICE, indicating that this + memory is mapped as device memory. + +The following SCMI Agents are expected to be defined by SCMI FW to enable = SCMI multi-agent functionality +under Xen: + +- Xen management agent: trusted agents that accesses to the Base Protocol = commands to configure + agent specific permissions +- OSPM VM agents: non-trusted agent, one for each Guest domain which is a= llowed direct HW access. + At least one OSPM VM agent has to be provided by FW if HW is handled onl= y by Dom0 or Driver Domain. + +The EL3 SCMI FW is expected to implement following Base protocol messages: + +- BASE_DISCOVER_AGENT (optional if agent_id was provided) +- BASE_RESET_AGENT_CONFIGURATION (optional) +- BASE_SET_DEVICE_PERMISSIONS (optional) + +The number of supported SCMI agents and their transport specifications are= SCMI FW implementation +specific. + +Compiling with multi-agent support +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +To build with the SCMI SMC multi-agent driver support, enable Kconfig opti= on: + +:: + + CONFIG_SCMI_SMC_MA + + +Driver functionality +^^^^^^^^^^^^^^^^^^^^ + +The SCI SCMI SMC multi-agent driver implements following functionality: + +- The driver is initialized from the Xen SCMI container ``xen_scmi_config`= ` + under ``/chosen/xen`` (for example ``/chosen/xen/xen_scmi_config/scmi``)= . + Only one SCMI interface is supported. The SCMI configuration must live u= nder + the Xen SCMI container ``xen,sci`` beneath ``/chosen``. + The Xen SCMI mediator will bind only to the "arm,scmi-smc" node that is = a child of + this "xen,sci" container; any other "arm,scmi-smc" nodes (for example un= der + "/firmware") are ignored to avoid stealing the host's SCMI OSPM instance= . + +.. code-block:: dts + + scmi_shm_1: sram@47ff1000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff1000 0x0 0x1000>; + }; + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; <--- Xen management agent smc-id + #address-cells =3D < 1>; + #size-cells =3D < 0>; + #access-controller-cells =3D < 1>; + shmem =3D <&scmi_shm_1>; <--- Xen management agent shmem + }; + +.. note:: + This layout keeps the Host DT unchanged for Dom0 and baremetal Linux by + using func_id 0x82000002 / shmem 0x47ff0000 for Dom0, while Xen uses a + separate privileged channel func_id 0x82000003 / shmem 0x47ff1000. EL3 + firmware enforces permissions per agent_id, so there is no conflict bet= ween + Dom0 and Xen channels. + +- The driver obtains Xen specific SCMI Agent's configuration from the Host= DT, probes Agents and + builds SCMI Agents list. The Agents configuration is taken from "scmi-se= condary-agents" + property where first item is "arm,smc-id", second - "arm,scmi-shmem" pha= ndle and third is + optional "agent_id": + +.. code-block:: dts + + chosen { + ranges; <--- set default ranges so address can be translated when pa= rsing scmi_shm node + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; <--- set default ranges so address can be translated whe= n parsing scmi_shm node + scmi-secondary-agents =3D < + 0x82000002 &scmi_shm_0 0 + 0x82000004 &scmi_shm_2 2 + 0x82000005 &scmi_shm_3 3 + 0x82000006 &scmi_shm_4 4>; + #scmi-secondary-agents-cells =3D <3>; <--- optional, default 3 + xen,dom0-sci-agent-id =3D <0>; /* Dom0 agent ID */ + + scmi_shm_0 : sram@47ff0000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff0000 0x0 0x1000>; + }; + + scmi_shm_2: sram@47ff2000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff2000 0x0 0x1000>; + }; + scmi_shm_3: sram@47ff3000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff3000 0x0 0x1000>; + }; + scmi_shm_4: sram@47ff4000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff4000 0x0 0x1000>; + }; + + // Xen SCMI management channel + scmi_shm_1: sram@47ff1000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff1000 0x0 0x1000>; + }; + + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; <--- Xen management agent smc-i= d + #address-cells =3D < 1>; + #size-cells =3D < 0>; + #access-controller-cells =3D < 1>; + shmem =3D <&scmi_shm_1>; <--- Xen management agent shmem + }; + }; + }; + }; + + /{ + // Host SCMI OSPM channel - provided to the Dom0 as is if SCMI ena= bled for it + scmi_shm: sram@47ff0000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff0000 0x0 0x1000>; + }; + + firmware { + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000002>; <--- Host OSPM agent smc-id + #address-cells =3D < 1>; + #size-cells =3D < 0>; + shmem =3D <&scmi_shm>; <--- Host OSPM agent shmem + + protocol@X{ + }; + }; + }; + }; + + This approach allows defining multiple SCMI Agents by adding Xen-specifi= c properties under + the ``/chosen`` node to the Host Device Tree, leaving the main part unch= anged. The Host DT + SCMI channel will be passed to Dom0. + + The Xen management agent is described as a ``scmi_xen`` node under the `= `xen,sci`` compatible node, + which is used by Xen to control other SCMI Agents in the system. + + All secondary agents' configurations are provided in the ``scmi-secondar= y-agents`` property with + an optional ``agent_id`` field. + + The ``agent_id`` from the ``scmi-secondary-agents`` property is used to = identify the agent in the + system and can be omitted by setting ``#scmi-secondary-agents-cells =3D = <2>``, so the Secondary + Agents configuration will look like this: + +.. code-block:: dts + + chosen { + xen { + xen_scmi_config { + compatible =3D "xen,sci"; + scmi-secondary-agents =3D < + 0x82000002 &scmi_shm_0 + 0x82000004 &scmi_shm_2 + 0x82000005 &scmi_shm_3 + 0x82000006 &scmi_shm_4>; + #scmi-secondary-agents-cells =3D <2>; + }; + }; + } + + In this case, Xen will use the ``SCMI_BASE_DISCOVER_AGENT`` call to disc= over the ``agent_id`` + for each secondary agent. Providing the ``agent_id`` in the ``scmi-secon= dary-agents`` property + allows skipping the discovery call, which is useful when the secondary a= gent's shared memory is + not accessible by Xen or when boot time is important because it allows s= kipping the agent + discovery procedure. + +.. note:: + + Note that Xen is the only one entry in the system which need to know a= bout SCMI multi-agent support. + +- The driver implements the SCI subsystem interface required for configuri= ng and enabling SCMI + functionality for Dom0/hwdom and Guest domains. To enable SCMI functiona= lity for guest domain + it has to be configured with unique supported SCMI Agent_id and use corr= esponding SCMI SMC + shared-memory transport ``[smc-id, shmem]`` defined for this SCMI Agent_= id. + +- Once Xen domain is configured it can communicate with EL3 SCMI FW: + + - zero-copy, the guest domain puts/gets SCMI message in/from shmem; + - the guest triggers SMC exception with agent "smc-id" (doorbell); + - the Xen driver catches exception, do checks and synchronously forwards= it to EL3 FW. + +- the Xen driver sends BASE_RESET_AGENT_CONFIGURATION message to Xen manag= ement agent channel on + domain destroy event. This allows to reset resources used by domain and = so implement use-case + like domain reboot. + + +Configure SCMI for Dom0 +^^^^^^^^^^^^^^^^^^^^^^^ +Set the Dom0 SCMI agent ID in the device tree using the Xen SCMI container= under ``/chosen``. +Add ``xen,dom0-sci-agent-id`` to the ``xen,sci`` node. If the property is = absent, SCMI stays +disabled for Dom0 and the SCMI nodes are removed from Dom0 DT. + +.. code-block:: dts + + chosen { + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + xen,dom0-sci-agent-id =3D <0>; /* Dom0 agent ID */ + /* scmi-secondary-agents and scmi_xen as shown above */ + }; + }; + }; + +The Host DT ``/firmware/scmi`` node is copied to the Dom0 DT unmodified. H= owever, for Dom0 SCMI +configuration, Xen actually relies on ``scmi-secondary-agents`` and ``xen,= dom0-sci-agent-id`` +properties from the ``xen,sci`` container under ``/chosen``. If the ``/fir= mware/scmi`` node is +missing or disabled, or if ``xen,dom0-sci-agent-id`` is not provided, the = Dom0 SCMI agent will not +be configured. + +.. note:: + + The ``xen,dom0-sci-agent-id`` value must match the ``func_id`` and ``shm= em`` pairing provided by + the EL3 firmware for Dom0 (for example in the ``/firmware/scmi`` node). + +Configure SCMI for for guest domain with toolstack +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +* In domain's xl.cfg file add **"arm_sci"** option as below + +:: + + arm_sci =3D "type=3Dscmi_smc_multiagent,agent_id=3D2" + +* In domain's xl.cfg file enable access to the "arm,scmi-shmem" which shou= ld correspond + assigned "agent_id" for the domain, for example: + +:: + + iomem =3D [ + "47ff2,1@22001", + ] + +.. note:: It's up to the user to select guest IPA for mapping SCMI shared-= memory. + +* Add SCMI nodes to the Driver domain partial device tree as in the below = example. + The "arm,smc-id" should correspond assigned agent_id for the domain: + +.. code:: + + passthrough { + scmi_shm_0: sram@22001000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x22001000 0x0 0x1000>; + }; + + firmware { + compatible =3D "simple-bus"; + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000004>; <--- smc-id for agent_id= =3D2 + shmem =3D <&scmi_shm_0>; + ... + } + } + } + +**Device specific access control** + +The XEN SCMI SMC multi-agent driver performs "access-controller" provider = function in case +EL3 SCMI FW implements SCMI "4.2.1.1 Device specific access control" and p= rovides the +BASE_SET_DEVICE_PERMISSIONS command to configure the devices that an agent= s have access to. +The Host DT SCMI node should have "#access-controller-cells=3D<1>" propert= y and DT devices should +be bound to the SCMI node using Access Controllers bindings [3]. + +For example: + +.. code-block:: dts + + &i2c1 { + access-controllers =3D <&scmi 0>; + }; + +Use domain's xl.cfg file **"dtdev"** property to assign SCMI devices from = toolstack to the guest: + +:: + + dtdev =3D [ + "/soc/i2c@e6508000", + ] + +.. note:: + + xl.cfg:"dtdev" need contain all nodes which are under SCMI management = (not only those which are + behind IOMMU) and passed-through to the guest domain. + +Configure SCMI for predefined domains (dom0less) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +* add "xen,sci_type" and "xen,sci-agent-id" properties for required DomU (= "xen,domain") node + +:: + + xen,sci_type=3D"scmi_smc_multiagent" + xen,sci-agent-id=3D2 + +* add scmi nodes to the Driver domain partial device tree the same way as = above (toolstack case) and + enable access to the "arm,scmi-shmem" according to the dom0less document= ation. For example: + +.. code-block:: dts + + scmi_shm_0: sram@22001000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x00 0x22001000 0x00 0x1000>; + -> xen,reg =3D <0x0 0x47ff2000 0x0 0x1000 0x0 0x22001000>; + -> xen,force-assign-without-iommu; + }; + +* For SCMI device access control configure pass-through devices in the gue= st partial DT according to + the dom0less documentation and ensure that devices SCMI management has "= xen,path" property set: + +Example (dom0less, multi-agent): + +.. code-block:: dts + + chosen { + xen { + ranges; + xen_scmi_config { + compatible =3D "xen,sci"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* Xen management channel shared memory */ + scmi_shm_1: sram@47ff1000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff1000 0x0 0x1000>; + }; + + scmi_shm_domu: sram@47ff2000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x47ff2000 0x0 0x1000>; + }; + + scmi-secondary-agents =3D < + 0x82000004 &scmi_shm_domu 2>; + #scmi-secondary-agents-cells =3D <3>; + + scmi_xen: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82000003>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #access-controller-cells =3D <1>; + shmem =3D <&scmi_shm_1>; + }; + }; + }; + + xen,domain@1 { + compatible =3D "xen,domain"; + xen,sci_type =3D "scmi_smc_multiagent"; + xen,sci-agent-id =3D <2>; + /* other domain properties here */ + }; + }; + +.. code-block:: dts + + i2c@e6508000 { + ... + reg =3D <0x00 0xe6508000 0x00 0x1000>; + -> xen,path =3D "/soc/i2c@e6508000" + -> xen,reg =3D <0x0 0xe6508000 0x0 0x1000 0x0 0xe6508000>; + -> xen,force-assign-without-iommu; + }; --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 17:46:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 17:46:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274337.1560478 (Exim 4.92) (envelope-from ) id 1w9o1Q-0005fT-JL; Mon, 06 Apr 2026 17:46:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274337.1560478; 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Mon, 06 Apr 2026 19:45:58 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 06B3960103; Mon, 6 Apr 2026 17:45:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3A70C4CEF7; Mon, 6 Apr 2026 17:45:55 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775497556; bh=eGWDO6+7WjkWzY6Nuvk55mQI2p6QMYb3HOtGf9ZPtvs=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=hUoM9ayNjSVoFMJafY8c5o6aAvUJb/dRfyfVfa9S9mwp4NqtU+js5Y3gVVoICyhyv Arw9WZw193LcuzHf4v0Zbc4ovk11fUbqcWx59M3vbvYoquPnBXUrzbQFShQsznjNxE b8rcoh1/+vDJnJQc+cIcMFjBKHFNlk5DHKM3nTj6tBQSTfRnG9+tbWv0kJuMF75W23 iRVbRHKq0aJTgHoTKWSd3d2qhDq+B5U7yGz1NOoduP/aGfPTW1sVsZHzEnnAa+tInQ SA+sZK/dRcPRjiF4SIuGLFvICDGgbw1flUV4Mo60kWTqAd/uATN0RV8ms07d3Z47Cc kUTMIxPcVLbXw== Date: Mon, 6 Apr 2026 10:45:54 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Pengpeng Hou cc: Stefano Stabellini , xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, jgross@suse.com Subject: Re: [PATCH v2] ARM: xen: validate hypervisor compatible before parsing its version In-Reply-To: <20260405094005.5-arm-xen-v2-pengpeng@iscas.ac.cn> Message-ID: References: <20260403111502.2-dt-arm-xen-pengpeng@iscas.ac.cn> <20260405094005.5-arm-xen-v2-pengpeng@iscas.ac.cn> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-4011c0/1775497558-0F7470B1-931AE95D/0/0 X-purgate-type: clean X-purgate-size: 2139 On Sun, 5 Apr 2026, Pengpeng Hou wrote: > fdt_find_hyper_node() reads the raw compatible property and then derives > hyper_node.version from a prefix match before later printing it with %s. > Flat DT properties are external boot input, and this path does not prove > that the first compatible entry is NUL-terminated within the returned > property length. > > Keep the existing flat-DT lookup path, but verify that the first > compatible entry terminates within the returned property length before > deriving the version suffix from it. > > Signed-off-by: Pengpeng Hou Reviewed-by: Stefano Stabellini > --- > Changes since v1: > - keep `of_get_flat_dt_prop()` instead of switching to `fdt_stringlist_get()` > - validate the first compatible entry with bounded `strnlen()` > > arch/arm/xen/enlighten.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c > index 4feed2c2..25a0ce3b 100644 > --- a/arch/arm/xen/enlighten.c > +++ b/arch/arm/xen/enlighten.c > @@ -218,8 +218,9 @@ static __initdata struct { > static int __init fdt_find_hyper_node(unsigned long node, const char *uname, > int depth, void *data) > { > - const void *s = NULL; > + const char *s = NULL; > int len; > + size_t prefix_len = strlen(hyper_node.prefix); > > if (depth != 1 || strcmp(uname, "hypervisor") != 0) > return 0; > @@ -228,9 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, > hyper_node.found = true; > > s = of_get_flat_dt_prop(node, "compatible", &len); > - if (strlen(hyper_node.prefix) + 3 < len && > - !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) > - hyper_node.version = s + strlen(hyper_node.prefix); > + if (s && len > 0 && strnlen(s, len) < len && > + len > prefix_len + 3 && > + !strncmp(hyper_node.prefix, s, prefix_len)) > + hyper_node.version = s + prefix_len; > > /* > * Check if Xen supports EFI by checking whether there is the > -- > 2.50.1 > From xen-devel-bounces@lists.xenproject.org Mon Apr 06 19:12:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 19:12:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274354.1560495 (Exim 4.92) (envelope-from ) id 1w9pN5-0008Mh-P5; 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pr=C From: Stewart Hildebrand To: CC: Mykyta Poturai , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Stewart Hildebrand" , Mykyta Poturai Subject: [PATCH v4 1/4] vpci: Use pervcpu ranges for BAR mapping Date: Mon, 6 Apr 2026 15:11:55 -0400 Message-ID: <20260406191203.97662-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260406191203.97662-1-stewart.hildebrand@amd.com> References: <20260406191203.97662-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708F:EE_|DS0PR12MB6462:EE_ X-MS-Office365-Filtering-Correlation-Id: fa5b2dc2-93e2-4b79-286e-08de94106bfa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|22082099003|18002099003|56012099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +uxT6HA7v7tEkDnHfXeiG84qUZrlP6mWQ5AT6sEZt4UAHyztezm7l6e/JwFLRQQ5R8fjnZS5lFseEK7egxjF+SfnuD9em73GkuTExtmnEP2Lkdxh991pbpgYTIzi4Xk0fdrYxPhIXICSag0ti9sL/Sc8AH8/9wnzDQZocvFaleobSqdAG10IyFkr0bRknT/3If63RTheryU8X8tCHcTZn8lz/87jZsWVWTtOCDQyZ4/X5uai/IR2mf8R7wSAZQUoIeRWjR1UmoGk+hY+qNLYARjEBi+M1GT/FzMYgzFR/FCVUTgai2Mcm1zdrhoVKQ2FTTbjnzYFmC7VE2CK8+VOuE7J/DIos/xNZpgNfmxSjcm7AmYyxK2zAHi11G3Fw4sjGQ5VRiPlXJ3JvsNgjqadp6AS6voHANapLjEckabxIEueaxEmK79Sw0Yfjswgv9Kg X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2026 19:12:18.4559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa5b2dc2-93e2-4b79-286e-08de94106bfa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6462 X-purgate-ID: tlsNG-c201ff/1775502745-3053396F-03571682/0/0 X-purgate-type: clean X-purgate-size: 13875 From: Mykyta Poturai There is no need to store ranges for each PCI device, as they are only used during the mapping/unmapping process and can be reused for each device. This also allows to avoid the need to allocate and destroy rangesets for each device. Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() macro to free a rangeset and set the pointer to NULL. Amends: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") Signed-off-by: Mykyta Poturai Signed-off-by: Stewart Hildebrand --- It seems a bit awkward to introduce various vpci vcpu alloc/dealloc functions here only to undo most of it in the next patch. Thoughts on folding the next patch into this one? v3->v4: * no change v2->v3: * new patch in this series, borrowed from [1] * add Amends tag * remove unused variable i due to rebasing over 998060dd9101 ("vPCI: move vpci_init_capabilities() to a separate file") * enclose entire struct vpci_vcpu inside #ifdef __XEN__ * s/bar_mem/mem/ * use ARRAY_SIZE * put init/destroy in functions * only allocate for domains with vPCI and idle domain * replace 'if ( !mem ) continue;' with ASSERT v1->v2 (in SR-IOV series [1]): * new patch [1] https://lore.kernel.org/xen-devel/cover.1772806036.git.mykyta_poturai@epam.com/T/#t --- xen/common/domain.c | 5 +++ xen/drivers/vpci/header.c | 67 ++++++++++++++------------------------ xen/drivers/vpci/vpci.c | 36 +++++++++++++++++--- xen/include/xen/rangeset.h | 7 ++++ xen/include/xen/vpci.h | 10 ++++-- 5 files changed, 75 insertions(+), 50 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index bb9e210c2895..5ef7db8f0960 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -455,6 +455,8 @@ static int vcpu_teardown(struct vcpu *v) */ static void vcpu_destroy(struct vcpu *v) { + vpci_vcpu_destroy(v); + free_vcpu_struct(v); } @@ -512,6 +514,9 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) if ( arch_vcpu_create(v) != 0 ) goto fail_sched; + if ( vpci_vcpu_init(v) ) + goto fail_sched; + d->vcpu[vcpu_id] = v; if ( vcpu_id != 0 ) { diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index a760d8c32fd6..89dce932f3b1 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -196,6 +196,7 @@ bool vpci_process_pending(struct vcpu *v) for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; + struct rangeset *mem = v->vpci.mem[i]; struct map_data data = { .d = v->domain, .map = v->vpci.cmd & PCI_COMMAND_MEMORY, @@ -203,10 +204,10 @@ bool vpci_process_pending(struct vcpu *v) }; int rc; - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; - rc = rangeset_consume_ranges(bar->mem, map_range, &data); + rc = rangeset_consume_ranges(mem, map_range, &data); if ( rc == -ERESTART ) { @@ -224,8 +225,8 @@ bool vpci_process_pending(struct vcpu *v) /* Clean all the rangesets */ for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) - if ( !rangeset_is_empty(header->bars[i].mem) ) - rangeset_purge(header->bars[i].mem); + if ( !rangeset_is_empty(v->vpci.mem[i]) ) + rangeset_purge(v->vpci.mem[i]); v->vpci.pdev = NULL; @@ -260,13 +261,14 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; + struct rangeset *mem = current->vpci.mem[i]; struct map_data data = { .d = d, .map = true, .bar = bar }; - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; - while ( (rc = rangeset_consume_ranges(bar->mem, map_range, - &data)) == -ERESTART ) + while ( (rc = rangeset_consume_ranges(mem, map_range, &data)) == + -ERESTART ) { /* * It's safe to drop and reacquire the lock in this context @@ -331,13 +333,13 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; + struct rangeset *mem = current->vpci.mem[i]; unsigned long start = PFN_DOWN(bar->addr); unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); unsigned long start_guest = PFN_DOWN(bar->guest_addr); unsigned long end_guest = PFN_DOWN(bar->guest_addr + bar->size - 1); - if ( !bar->mem ) - continue; + ASSERT(mem); if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type != VPCI_BAR_ROM @@ -354,7 +356,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) continue; } - ASSERT(rangeset_is_empty(bar->mem)); + ASSERT(rangeset_is_empty(mem)); /* * Make sure that the guest set address has the same page offset @@ -369,7 +371,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) return -EINVAL; } - rc = rangeset_add_range(bar->mem, start_guest, end_guest); + rc = rangeset_add_range(mem, start_guest, end_guest); if ( rc ) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", @@ -380,12 +382,12 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) /* Check for overlap with the already setup BAR ranges. */ for ( j = 0; j < i; j++ ) { - struct vpci_bar *prev_bar = &header->bars[j]; + struct rangeset *prev_mem = current->vpci.mem[j]; - if ( rangeset_is_empty(prev_bar->mem) ) + if ( rangeset_is_empty(prev_mem) ) continue; - rc = rangeset_remove_range(prev_bar->mem, start_guest, end_guest); + rc = rangeset_remove_range(prev_mem, start_guest, end_guest); if ( rc ) { gprintk(XENLOG_WARNING, @@ -395,7 +397,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) } } - rc = pci_sanitize_bar_memory(bar->mem); + rc = pci_sanitize_bar_memory(mem); if ( rc ) { gprintk(XENLOG_WARNING, @@ -412,14 +414,14 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + vmsix_table_size(pdev->vpci, i) - 1); - for ( j = 0; j < ARRAY_SIZE(header->bars); j++ ) + for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) { - const struct vpci_bar *bar = &header->bars[j]; + struct rangeset *mem = current->vpci.mem[j]; - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; - rc = rangeset_remove_range(bar->mem, start, end); + rc = rangeset_remove_range(mem, start, end); if ( rc ) { gprintk(XENLOG_WARNING, @@ -469,8 +471,9 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( j = 0; j < ARRAY_SIZE(header->bars); j++) { const struct vpci_bar *bar = &header->bars[j]; + struct rangeset *mem = current->vpci.mem[j]; - if ( !rangeset_overlaps_range(bar->mem, start, end) || + if ( !rangeset_overlaps_range(mem, start, end) || /* * If only the ROM enable bit is toggled check against * other BARs in the same device for overlaps, but not @@ -481,7 +484,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) bar->type == VPCI_BAR_ROM) ) continue; - rc = rangeset_remove_range(bar->mem, start, end); + rc = rangeset_remove_range(mem, start, end); if ( rc ) { gprintk(XENLOG_WARNING, @@ -732,18 +735,6 @@ static void cf_check rom_write( } } -static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *bar, - unsigned int i) -{ - char str[32]; - - snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); - - bar->mem = rangeset_new(pdev->domain, str, RANGESETF_no_print); - - return !bar->mem ? -ENOMEM : 0; -} - int vpci_init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -853,10 +844,6 @@ int vpci_init_header(struct pci_dev *pdev) else bars[i].type = VPCI_BAR_MEM32; - rc = bar_add_rangeset(pdev, &bars[i], i); - if ( rc ) - goto fail; - rc = pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, (i == num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) @@ -909,12 +896,6 @@ int vpci_init_header(struct pci_dev *pdev) 4, rom); if ( rc ) rom->type = VPCI_BAR_EMPTY; - else - { - rc = bar_add_rangeset(pdev, rom, num_bars); - if ( rc ) - goto fail; - } } else if ( !is_hwdom ) { diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 0ac9ec8b0475..8e6343653078 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -24,6 +24,37 @@ #ifdef __XEN__ +void vpci_vcpu_destroy(struct vcpu *v) +{ + unsigned int i; + + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) + return; + + for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) + RANGESET_DESTROY(v->vpci.mem[i]); +} + +int vpci_vcpu_init(struct vcpu *v) +{ + unsigned int i; + + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) + return 0; + + for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) + { + char str[32]; + + snprintf(str, sizeof(str), "%pv:BAR%u", v, i); + v->vpci.mem[i] = rangeset_new(v->domain, str, RANGESETF_no_print); + if ( !v->vpci.mem[i] ) + return -ENOMEM; + } + + return 0; +} + #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT static int assign_virtual_sbdf(struct pci_dev *pdev) { @@ -89,8 +120,6 @@ struct vpci_register *vpci_get_register(const struct vpci *vpci, void vpci_deassign_device(struct pci_dev *pdev) { - unsigned int i; - ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); if ( !has_vpci(pdev->domain) || !pdev->vpci ) @@ -116,9 +145,6 @@ void vpci_deassign_device(struct pci_dev *pdev) } spin_unlock(&pdev->vpci->lock); - for ( i = 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) - rangeset_destroy(pdev->vpci->header.bars[i].mem); - xfree(pdev->vpci); pdev->vpci = NULL; } diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index 817505badf6f..f01e00ec9234 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -40,6 +40,13 @@ struct rangeset *rangeset_new( void rangeset_destroy( struct rangeset *r); +/* Destroy a rangeset, and zero the pointer to it. */ +#define RANGESET_DESTROY(r) \ + ({ \ + rangeset_destroy(r); \ + (r) = NULL; \ + }) + /* * Set a limit on the number of ranges that may exist in set @r. * NOTE: This must be called while @r is empty. diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 877aa391d178..b55bacbe6e01 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -19,6 +19,9 @@ */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) +void vpci_vcpu_destroy(struct vcpu *v); +int vpci_vcpu_init(struct vcpu *v); + /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); @@ -54,7 +57,6 @@ struct vpci { uint64_t guest_addr; uint64_t size; uint64_t resizable_sizes; - struct rangeset *mem; enum { VPCI_BAR_EMPTY, VPCI_BAR_IO, @@ -152,14 +154,15 @@ struct vpci { #endif }; +#ifdef __XEN__ struct vpci_vcpu { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ const struct pci_dev *pdev; + struct rangeset *mem[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; uint16_t cmd; bool rom_only : 1; }; -#ifdef __XEN__ void vpci_dump_msi(void); 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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Mykyta Poturai" Subject: [PATCH v4 0/4] vpci: allow 32-bit BAR writes with memory decoding enabled Date: Mon, 6 Apr 2026 15:11:54 -0400 Message-ID: <20260406191203.97662-1-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|DS4PR12MB9636:EE_ X-MS-Office365-Filtering-Correlation-Id: b2188676-22be-4a58-57c3-08de94106582 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|13003099007|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: V3WrIhzENCDAGrOM8jWQQMsfxnvo1sqVPey7SgQ2F0JMMCqV9NDL2eSlxLIRym071g/oDxczjIulA0CwVZg8DkpxwkJ6xurKxr+pvdjClDRdzk9qM0tmo+jwgnXcHI4ERfMVZDBQx5J2eCWWMN4HjXZtQkSXucvOacE9QvC1O0CS4/LkvVaaCK4kHJNngXK0gflUICFjXtT9gBUFHlbCaZF3DRSZrfNZujqtWsJ74sYidlvvxe37s9n1hyCywVWetbT/ReDwsjxwQ63YdFTAb3AlZlEdQfHrbt4239d76bKPVqHxAvD4Jvvf9zZVyY+43XZdiQub6GsZ+zGtB8QXVUw1+mUPBzeZ3n2vS2yd3pnvUtuckEoRB7VrwMk7W4hzml0Nl4LKGis3tfE4LoVVef/tl5CwremK368gGU0frvSGgX65IVMxeDmVksYnu4AxmYOy8K9TsE6q2k6OL9MpcoPAov/pH2y4W1IA5fJWgI3TrysamUosj/a4AowJq2yFPdHg6cJHzNQ8k3UK+nFGPM5xrhN6+P6IwIBPt8OS/HMlw2UrSsNdhabAIIMqqGrj7VREwwMP8Nsv7ZRyiaRC7viBT1ImBcYaXGqQLzioh80HF2a8ghbrAqT7WdXCwLsS3/K4r0meUmvAYHm9/CAcgn1xd0LUJuiOsIPGrvMZmqXjlmUDiFaGtVq9F2rtycetLwH5WKcY58o0SpsjAFxgEsy1Awm2ut4Q8ckWs25aVWk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(13003099007)(18002099003)(56012099003);DIR:OUT;SFP:1101; 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Pipeline: https://gitlab.com/xen-project/people/stewarthildebrand/xen/-/pipelines/2432615038 v3->v4: * switch back to dynamically allocated queue elements v2->v3: * add ("vpci: Use pervcpu ranges for BAR mapping") * rework with fixed array of map/unmap slots v1->v2: * new approach with queued p2m operations RFC->v1: * rework BAR mapping machinery to support unmap-then-map operation v3: https://lore.kernel.org/xen-devel/20260324030513.700217-1-stewart.hildebrand@amd.com/T/#t v2: https://lore.kernel.org/xen-devel/20250723163744.13095-1-stewart.hildebrand@amd.com/T/#t v1: https://lore.kernel.org/xen-devel/20250531125405.268984-1-stewart.hildebrand@amd.com/T/#t RFC: https://lore.kernel.org/xen-devel/20250312195019.382926-1-stewart.hildebrand@amd.com/T/#t Mykyta Poturai (1): vpci: Use pervcpu ranges for BAR mapping Stewart Hildebrand (3): vpci: allow queueing of mapping operations vpci: allow BAR map/unmap without affecting memory decoding bit vpci: allow 32-bit BAR writes with memory decoding enabled xen/common/domain.c | 2 + xen/drivers/vpci/header.c | 333 ++++++++++++++++++++++++-------------- xen/drivers/vpci/vpci.c | 10 +- xen/include/xen/vpci.h | 22 ++- 4 files changed, 239 insertions(+), 128 deletions(-) base-commit: 33ceaa28275ca4e298616689ef96f19efaa87c35 -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 19:12:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 19:12:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274358.1560505 (Exim 4.92) (envelope-from ) id 1w9pNF-0000HY-69; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tdGllGUK8TiRaZWvVqFEsyu4uOoRMu93WYGtX/iLMdg=; b=0qTb0+uRhafBHRHwVP9nqpl9R/tudSlOewmfMjhHbrxMjdVRYo39x5sV0MlxhfW91WZvZqxdigeZTjhYQ2ouXM7vKce2ayxMWMjxEbBvvY2mfA+x3feJB5o4D1sbw/A6jTRS5sKSteSNwB5MCqKZPtm+b9Bw7OXbLegjDwB6DOo= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Mykyta Poturai" Subject: [PATCH v4 2/4] vpci: allow queueing of mapping operations Date: Mon, 6 Apr 2026 15:11:56 -0400 Message-ID: <20260406191203.97662-3-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260406191203.97662-1-stewart.hildebrand@amd.com> References: <20260406191203.97662-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|PH0PR12MB5680:EE_ X-MS-Office365-Filtering-Correlation-Id: 26a4cc13-f6bd-41fc-fab9-08de9410700c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3XvrUkjh8W/iUp+zpqbnOR7jk1qqNxFh0P3TE/VBbLTecE55CrOM+SvhH2GK1gQc3swr6BCluTSgLf0BifMfDt8aEevu2jHCGcOaj5qgliFoX2B653MXt/ujf5LodjdqT0EYHp2WycundMAQzqGwsYAGUEnZ0QDJsApKq9YFCfQUntzsiw0F+L9bubrtjZRPLn5wU+Fn6y+jb0B7BltOqUFHBWMh8BFdvH/GblidwYcDg589IMw3nY05WujJG3MgTHyw+a8iX+xGwi+D9cxQcaekp5TiwdsvnqbK/lywVWOrGkhpJMDLruHFaEOhDhHnDV6qtUOSjaCXN8xfXPexTNpDJH9atCSQy08EldURibHM4KjLkWtJpyCwZopuxMVESLGAPPytnzN2MACZA7ipu8Qlg5B+4jlyS/rjiOfmZS4KpVqA7RlAz0E55NM+A7m6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2026 19:12:25.2126 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26a4cc13-f6bd-41fc-fab9-08de9410700c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5680 X-purgate-ID: tlsNG-c1860d/1775502754-F5B54497-CB89D6D1/0/0 X-purgate-type: clean X-purgate-size: 19758 Introduce vPCI BAR mapping task queue. Store information needed to map/unmap BARs in struct vpci_map_task. Allow queueing of BAR map/unmap operations in a list, thus making it possible to perform multiple p2m operations associated with single PCI device. This is preparatory work for further changes that need to perform multiple unmap/map operations before returning to guest. At the moment, only a single operation will be queued. However, when multiple operations are queued, there is a check in modify_bars() to skip BARs already in the requested state that will no longer be accurate. Remove this check in preparation of upcoming changes. Signed-off-by: Stewart Hildebrand --- apply_map() and vpci_process_map_task() are very similar. Should we try to combine them into a single function? I concede that the dynamic allocation/deallocation of struct vpci_map_task is not ideal. However, to support SR-IOV, there will be a need to queue many mapping operations (one per VF), and statically pre-allocating that much would seem wasteful. Only the hardware and/or control domain would need to queue many operations, and only when configuring SR-IOV. v3->v4: * switch back to dynamically allocated queue elements v2->v3: * base on ("vpci: Use pervcpu ranges for BAR mapping") from [1] * rework with fixed array of map/unmap slots [1] https://lore.kernel.org/xen-devel/cover.1772806036.git.mykyta_poturai@epam.com/T/#t v1->v2: * new patch --- xen/common/domain.c | 5 +- xen/drivers/vpci/header.c | 227 ++++++++++++++++++++++++++----------- xen/drivers/vpci/vpci.c | 30 +---- xen/include/xen/rangeset.h | 7 -- xen/include/xen/vpci.h | 21 ++-- 5 files changed, 179 insertions(+), 111 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index 5ef7db8f0960..b1931be9870b 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -455,8 +455,6 @@ static int vcpu_teardown(struct vcpu *v) */ static void vcpu_destroy(struct vcpu *v) { - vpci_vcpu_destroy(v); - free_vcpu_struct(v); } @@ -514,8 +512,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) if ( arch_vcpu_create(v) != 0 ) goto fail_sched; - if ( vpci_vcpu_init(v) ) - goto fail_sched; + vpci_vcpu_init(v); d->vcpu[vcpu_id] = v; if ( vcpu_id != 0 ) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 89dce932f3b1..146915e28c50 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -35,7 +36,7 @@ struct map_data { struct domain *d; - const struct vpci_bar *bar; + const struct vpci_bar_map *bar; bool map; }; @@ -174,32 +175,20 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, ASSERT_UNREACHABLE(); } -bool vpci_process_pending(struct vcpu *v) +static int vpci_process_map_task(const struct pci_dev *pdev, + struct vpci_map_task *task) { - const struct pci_dev *pdev = v->vpci.pdev; - struct vpci_header *header = NULL; unsigned int i; - if ( !pdev ) - return false; - - read_lock(&v->domain->pci_lock); - - if ( !pdev->vpci || (v->domain != pdev->domain) ) - { - v->vpci.pdev = NULL; - read_unlock(&v->domain->pci_lock); - return false; - } + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); - header = &pdev->vpci->header; - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar = &header->bars[i]; - struct rangeset *mem = v->vpci.mem[i]; + struct vpci_bar_map *bar = &task->bars[i]; + struct rangeset *mem = bar->mem; struct map_data data = { - .d = v->domain, - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, + .d = pdev->domain, + .map = task->cmd & PCI_COMMAND_MEMORY, .bar = bar, }; int rc; @@ -210,58 +199,116 @@ bool vpci_process_pending(struct vcpu *v) rc = rangeset_consume_ranges(mem, map_range, &data); if ( rc == -ERESTART ) - { - read_unlock(&v->domain->pci_lock); - return true; - } + return rc; if ( rc ) { spin_lock(&pdev->vpci->lock); /* Disable memory decoding unconditionally on failure. */ - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, - false); + modify_decoding(pdev, task->cmd & ~PCI_COMMAND_MEMORY, false); spin_unlock(&pdev->vpci->lock); - /* Clean all the rangesets */ - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) - if ( !rangeset_is_empty(v->vpci.mem[i]) ) - rangeset_purge(v->vpci.mem[i]); + if ( !is_hardware_domain(pdev->domain) ) + domain_crash(pdev->domain); + + return rc; + } + } + + spin_lock(&pdev->vpci->lock); + modify_decoding(pdev, task->cmd, task->rom_only); + spin_unlock(&pdev->vpci->lock); + + return 0; +} + +static void destroy_map_task(struct vpci_map_task *task) +{ + unsigned int i; + + if ( !task ) + { + ASSERT_UNREACHABLE(); + return; + } + + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) + rangeset_destroy(task->bars[i].mem); + + xvfree(task); +} + +static void clear_map_queue(struct vcpu *v) +{ + struct vpci_map_task *task; + + while ( (task = list_first_entry_or_null(&v->vpci.task_queue, + struct vpci_map_task, + next)) != NULL ) + { + list_del(&task->next); + destroy_map_task(task); + } +} + +bool vpci_process_pending(struct vcpu *v) +{ + const struct pci_dev *pdev = v->vpci.pdev; + struct vpci_map_task *task; - v->vpci.pdev = NULL; + if ( !pdev ) + return false; + read_lock(&v->domain->pci_lock); + + if ( !pdev->vpci || (v->domain != pdev->domain) ) + { + clear_map_queue(v); + v->vpci.pdev = NULL; + read_unlock(&v->domain->pci_lock); + return false; + } + + while ( (task = list_first_entry_or_null(&v->vpci.task_queue, + struct vpci_map_task, + next)) != NULL ) + { + int rc = vpci_process_map_task(pdev, task); + + if ( rc == -ERESTART ) + { read_unlock(&v->domain->pci_lock); + return true; + } - if ( !is_hardware_domain(v->domain) ) - domain_crash(v->domain); + list_del(&task->next); + destroy_map_task(task); - return false; + if ( rc ) + { + clear_map_queue(v); + break; } } v->vpci.pdev = NULL; - spin_lock(&pdev->vpci->lock); - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); - spin_unlock(&pdev->vpci->lock); - read_unlock(&v->domain->pci_lock); return false; } static int __init apply_map(struct domain *d, const struct pci_dev *pdev, - uint16_t cmd) + struct vpci_map_task *task) { - struct vpci_header *header = &pdev->vpci->header; int rc = 0; unsigned int i; ASSERT(rw_is_write_locked(&d->pci_lock)); - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar = &header->bars[i]; - struct rangeset *mem = current->vpci.mem[i]; + struct vpci_bar_map *bar = &task->bars[i]; + struct rangeset *mem = bar->mem; struct map_data data = { .d = d, .map = true, .bar = bar }; if ( rangeset_is_empty(mem) ) @@ -281,15 +328,52 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, } } if ( !rc ) - modify_decoding(pdev, cmd, false); + modify_decoding(pdev, task->cmd, false); return rc; } -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, + uint16_t cmd, bool rom_only) +{ + struct vpci_map_task *task; + unsigned int i; + + task = xvzalloc(struct vpci_map_task); + + if ( !task ) + return NULL; + + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) + { + if ( !MAPPABLE_BAR(&pdev->vpci->header.bars[i]) ) + continue; + + task->bars[i].mem = rangeset_new(pdev->domain, NULL, + RANGESETF_no_print); + + if ( !task->bars[i].mem ) + { + destroy_map_task(task); + return NULL; + } + + task->bars[i].addr = pdev->vpci->header.bars[i].addr; + task->bars[i].guest_addr = pdev->vpci->header.bars[i].guest_addr; + } + + task->cmd = cmd; + task->rom_only = rom_only; + + return task; +} + +static void defer_map(const struct pci_dev *pdev, struct vpci_map_task *task) { struct vcpu *curr = current; + ASSERT(!curr->vpci.pdev || curr->vpci.pdev == pdev); + /* * FIXME: when deferring the {un}map the state of the device should not * be trusted. For example the enable bit is toggled after the device @@ -297,8 +381,8 @@ static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) * started for the same device if the domain is not well-behaved. */ curr->vpci.pdev = pdev; - curr->vpci.cmd = cmd; - curr->vpci.rom_only = rom_only; + list_add_tail(&task->next, &curr->vpci.task_queue); + /* * Raise a scheduler softirq in order to prevent the guest from resuming * execution with pending mapping operations, to trigger the invocation @@ -313,11 +397,17 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) struct pci_dev *tmp; const struct domain *d; const struct vpci_msix *msix = pdev->vpci->msix; + struct vpci_map_task *task; unsigned int i, j; int rc; ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); + task = alloc_map_task(pdev, cmd, rom_only); + + if ( !task ) + return -ENOMEM; + /* * Create a rangeset per BAR that represents the current device memory * region and compare it against all the currently active BAR memory @@ -333,19 +423,18 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar = &header->bars[i]; - struct rangeset *mem = current->vpci.mem[i]; + struct rangeset *mem = task->bars[i].mem; unsigned long start = PFN_DOWN(bar->addr); unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); unsigned long start_guest = PFN_DOWN(bar->guest_addr); unsigned long end_guest = PFN_DOWN(bar->guest_addr + bar->size - 1); - ASSERT(mem); + if ( !mem ) + continue; if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type != VPCI_BAR_ROM - : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) || - /* Skip BARs already in the requested state. */ - bar->enabled == !!(cmd & PCI_COMMAND_MEMORY) ) + : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) ) continue; if ( !pci_check_bar(pdev, _mfn(start), _mfn(end)) ) @@ -368,7 +457,8 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) gprintk(XENLOG_G_WARNING, "%pp: can't map BAR%u - offset mismatch: %#lx vs %#lx\n", &pdev->sbdf, i, bar->guest_addr, bar->addr); - return -EINVAL; + rc = -EINVAL; + goto fail; } rc = rangeset_add_range(mem, start_guest, end_guest); @@ -376,13 +466,13 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", start_guest, end_guest, rc); - return rc; + goto fail; } /* Check for overlap with the already setup BAR ranges. */ for ( j = 0; j < i; j++ ) { - struct rangeset *prev_mem = current->vpci.mem[j]; + struct rangeset *prev_mem = task->bars[j].mem; if ( rangeset_is_empty(prev_mem) ) continue; @@ -393,7 +483,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove overlapping range [%lx, %lx]: %d\n", &pdev->sbdf, start_guest, end_guest, rc); - return rc; + goto fail; } } @@ -403,7 +493,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to sanitize BAR#%u memory: %d\n", &pdev->sbdf, i, rc); - return rc; + goto fail; } } @@ -414,9 +504,9 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + vmsix_table_size(pdev->vpci, i) - 1); - for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) + for ( j = 0; j < ARRAY_SIZE(task->bars); j++ ) { - struct rangeset *mem = current->vpci.mem[j]; + struct rangeset *mem = task->bars[j].mem; if ( rangeset_is_empty(mem) ) continue; @@ -427,7 +517,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove MSIX table [%lx, %lx]: %d\n", &pdev->sbdf, start, end, rc); - return rc; + goto fail; } } } @@ -471,7 +561,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) for ( j = 0; j < ARRAY_SIZE(header->bars); j++) { const struct vpci_bar *bar = &header->bars[j]; - struct rangeset *mem = current->vpci.mem[j]; + struct rangeset *mem = task->bars[j].mem; if ( !rangeset_overlaps_range(mem, start, end) || /* @@ -490,7 +580,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove [%lx, %lx]: %d\n", &pdev->sbdf, start, end, rc); - return rc; + goto fail; } } } @@ -513,12 +603,19 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) * will always be to establish mappings and process all the BARs. */ ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); - return apply_map(pdev->domain, pdev, cmd); + rc = apply_map(pdev->domain, pdev, task); + destroy_map_task(task); + return rc; } - defer_map(pdev, cmd, rom_only); + defer_map(pdev, task); return 0; + + fail: + destroy_map_task(task); + + return rc; } static void cf_check cmd_write( diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 8e6343653078..ce9fb5b357ff 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -24,35 +24,9 @@ #ifdef __XEN__ -void vpci_vcpu_destroy(struct vcpu *v) +void vpci_vcpu_init(struct vcpu *v) { - unsigned int i; - - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) - return; - - for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) - RANGESET_DESTROY(v->vpci.mem[i]); -} - -int vpci_vcpu_init(struct vcpu *v) -{ - unsigned int i; - - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) - return 0; - - for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) - { - char str[32]; - - snprintf(str, sizeof(str), "%pv:BAR%u", v, i); - v->vpci.mem[i] = rangeset_new(v->domain, str, RANGESETF_no_print); - if ( !v->vpci.mem[i] ) - return -ENOMEM; - } - - return 0; + INIT_LIST_HEAD(&v->vpci.task_queue); } #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index f01e00ec9234..817505badf6f 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -40,13 +40,6 @@ struct rangeset *rangeset_new( void rangeset_destroy( struct rangeset *r); -/* Destroy a rangeset, and zero the pointer to it. */ -#define RANGESET_DESTROY(r) \ - ({ \ - rangeset_destroy(r); \ - (r) = NULL; \ - }) - /* * Set a limit on the number of ranges that may exist in set @r. * NOTE: This must be called while @r is empty. diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index b55bacbe6e01..e34f7abe6da2 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -19,8 +19,7 @@ */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) -void vpci_vcpu_destroy(struct vcpu *v); -int vpci_vcpu_init(struct vcpu *v); +void vpci_vcpu_init(struct vcpu *v); /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); @@ -155,14 +154,23 @@ struct vpci { }; #ifdef __XEN__ -struct vpci_vcpu { +struct vpci_map_task { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ - const struct pci_dev *pdev; - struct rangeset *mem[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; + struct list_head next; + struct vpci_bar_map { + uint64_t addr; + uint64_t guest_addr; + struct rangeset *mem; + } bars[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; uint16_t cmd; bool rom_only : 1; }; +struct vpci_vcpu { + const struct pci_dev *pdev; + struct list_head task_queue; +}; + void vpci_dump_msi(void); /* Arch-specific vPCI MSI helpers. */ @@ -207,8 +215,7 @@ bool vpci_ecam_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int len, #else /* !CONFIG_HAS_VPCI */ struct vpci_vcpu {}; -static inline void vpci_vcpu_destroy(struct vcpu *v) { } -static inline int vpci_vcpu_init(struct vcpu *v) { return 0; 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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 3/4] vpci: allow BAR map/unmap without affecting memory decoding bit Date: Mon, 6 Apr 2026 15:11:57 -0400 Message-ID: <20260406191203.97662-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260406191203.97662-1-stewart.hildebrand@amd.com> References: <20260406191203.97662-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708E:EE_|DS0PR12MB6630:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ca8c865-67e4-4bcf-4710-08de941073d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|13003099007|18002099003|56012099003|22082099003; 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This will allow hardware domain to reposition BARs without affecting the memory decoding bit. Signed-off-by: Stewart Hildebrand --- This also lays some groundwork to allow domUs to toggle the guest view without affecting hardware, a step toward addressing the FIXME in [1]. [1] https://lore.kernel.org/xen-devel/20250814160358.95543-4-roger.pau@citrix.com/ v3->v4: * rebase on dynamically allocated map queue v2->v3: * use bool * switch to task->map in more places v1->v2: * new patch --- xen/drivers/vpci/header.c | 43 +++++++++++++++++++++------------------ xen/include/xen/vpci.h | 1 + 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 146915e28c50..20fe380552f4 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -117,11 +117,12 @@ static int cf_check map_range( * BAR's enable bit has changed with the memory decoding bit already enabled. * If rom_only is not set then it's the memory decoding bit that changed. */ -static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, - bool rom_only) +static void modify_decoding(const struct pci_dev *pdev, + struct vpci_map_task *task) { struct vpci_header *header = &pdev->vpci->header; - bool map = cmd & PCI_COMMAND_MEMORY; + bool rom_only = task->rom_only; + bool map = task->map; unsigned int i; for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) @@ -168,7 +169,7 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, if ( !rom_only ) { - pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); + pci_conf_write16(pdev->sbdf, PCI_COMMAND, task->cmd); header->bars_mapped = map; } else @@ -188,7 +189,7 @@ static int vpci_process_map_task(const struct pci_dev *pdev, struct rangeset *mem = bar->mem; struct map_data data = { .d = pdev->domain, - .map = task->cmd & PCI_COMMAND_MEMORY, + .map = task->map, .bar = bar, }; int rc; @@ -203,9 +204,11 @@ static int vpci_process_map_task(const struct pci_dev *pdev, if ( rc ) { - spin_lock(&pdev->vpci->lock); /* Disable memory decoding unconditionally on failure. */ - modify_decoding(pdev, task->cmd & ~PCI_COMMAND_MEMORY, false); + task->cmd &= ~PCI_COMMAND_MEMORY; + task->map = false; + spin_lock(&pdev->vpci->lock); + modify_decoding(pdev, task); spin_unlock(&pdev->vpci->lock); if ( !is_hardware_domain(pdev->domain) ) @@ -216,7 +219,7 @@ static int vpci_process_map_task(const struct pci_dev *pdev, } spin_lock(&pdev->vpci->lock); - modify_decoding(pdev, task->cmd, task->rom_only); + modify_decoding(pdev, task); spin_unlock(&pdev->vpci->lock); return 0; @@ -328,13 +331,14 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, } } if ( !rc ) - modify_decoding(pdev, task->cmd, false); + modify_decoding(pdev, task); return rc; } static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, - uint16_t cmd, bool rom_only) + uint16_t cmd, bool rom_only, + bool map) { struct vpci_map_task *task; unsigned int i; @@ -364,6 +368,7 @@ static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, task->cmd = cmd; task->rom_only = rom_only; + task->map = map; return task; } @@ -391,7 +396,8 @@ static void defer_map(const struct pci_dev *pdev, struct vpci_map_task *task) raise_softirq(SCHEDULE_SOFTIRQ); } -static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) +static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only, + bool map) { struct vpci_header *header = &pdev->vpci->header; struct pci_dev *tmp; @@ -403,7 +409,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); - task = alloc_map_task(pdev, cmd, rom_only); + task = alloc_map_task(pdev, cmd, rom_only, map); if ( !task ) return -ENOMEM; @@ -602,7 +608,7 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) * be called iff the memory decoding bit is enabled, thus the operation * will always be to establish mappings and process all the BARs. */ - ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); + ASSERT(map && !rom_only); rc = apply_map(pdev->domain, pdev, task); destroy_map_task(task); return rc; @@ -646,7 +652,7 @@ static void cf_check cmd_write( * memory decoding bit has not been changed, so leave everything as-is, * hoping the guest will realize and try again. */ - modify_bars(pdev, cmd, false); + modify_bars(pdev, cmd, false, cmd & PCI_COMMAND_MEMORY); else pci_conf_write16(pdev->sbdf, reg, cmd); } @@ -810,11 +816,8 @@ static void cf_check rom_write( header->rom_enabled = new_enabled; pci_conf_write32(pdev->sbdf, reg, val); } - /* - * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note that - * this fabricated command is never going to be written to the register. - */ - else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) ) + /* Note that the command value 0 will never be written to the register */ + else if ( modify_bars(pdev, 0, true, new_enabled) ) /* * No memory has been added or removed from the p2m (because the actual * p2m changes are deferred in defer_map) and the ROM enable bit has @@ -1004,7 +1007,7 @@ int vpci_init_header(struct pci_dev *pdev) goto fail; } - return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0; + return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false, true) : 0; fail: pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index e34f7abe6da2..e6d40827a43a 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -164,6 +164,7 @@ struct vpci_map_task { } bars[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; uint16_t cmd; bool rom_only : 1; + bool map : 1; }; struct vpci_vcpu { -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 06 19:12:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 06 Apr 2026 19:12:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274367.1560523 (Exim 4.92) (envelope-from ) id 1w9pNP-0000vC-UH; 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pr=C From: Stewart Hildebrand To: CC: Stewart Hildebrand , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 4/4] vpci: allow 32-bit BAR writes with memory decoding enabled Date: Mon, 6 Apr 2026 15:11:58 -0400 Message-ID: <20260406191203.97662-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260406191203.97662-1-stewart.hildebrand@amd.com> References: <20260406191203.97662-1-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017091:EE_|SA0PR12MB4480:EE_ X-MS-Office365-Filtering-Correlation-Id: 5348181e-dcf2-40d8-6071-08de941077da X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|13003099007|22082099003|56012099003|18002099003; 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If firmware initializes a 32-bit BAR to a bad address, Linux may try to write a new address to the 32-bit BAR without disabling memory decoding. Since Xen refuses such writes, the BAR (and thus PCI device) will be non-functional. Allow the hardware domain to issue 32-bit BAR writes with memory decoding enabled. This increases the compatibility of PVH dom0 with more hardware. Note that Linux aims at disabling memory decoding before writing 64-bit BARs. Continue to refuse 64-bit BAR writes in Xen while those BARs are mapped for now to avoid mapping half-updated BARs in p2m. Resolves: https://gitlab.com/xen-project/xen/-/issues/197 Signed-off-by: Stewart Hildebrand --- v3->v4: * rebase on dynamically allocated map queue v2->v3: * minor tweaks for fixed number of map/unmap slots v1->v2: * rework on top of queued BAR map/unmap operation machinery RFC->v1: * keep memory decoding enabled in hardware * allow write while memory decoding is enabled for 32-bit BARs only * rework BAR mapping machinery to support unmap-then-map operation --- xen/drivers/vpci/header.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 20fe380552f4..dc4f585b4e40 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -670,6 +670,7 @@ static void cf_check bar_write( { struct vpci_bar *bar = data; bool hi = false; + uint16_t cmd = 0; ASSERT(is_hardware_domain(pdev->domain)); @@ -683,19 +684,29 @@ static void cf_check bar_write( val &= PCI_BASE_ADDRESS_MEM_MASK; /* - * Xen only cares whether the BAR is mapped into the p2m, so allow BAR - * writes as long as the BAR is not mapped into the p2m. + * Allow 64-bit BAR writes only when the BAR is not mapped in p2m. Always + * allow 32-bit BAR writes. */ if ( bar->enabled ) { - /* If the value written is the current one avoid printing a warning. */ - if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) - gprintk(XENLOG_WARNING, - "%pp: ignored BAR %zu write while mapped\n", - &pdev->sbdf, bar - pdev->vpci->header.bars + hi); - return; - } + if ( bar->type == VPCI_BAR_MEM32 ) + { + if ( val == bar->addr ) + return; + cmd = pci_conf_read16(pdev->sbdf, PCI_COMMAND); + modify_bars(pdev, cmd, false, false); + } + else + { + /* If the value written is the same avoid printing a warning. */ + if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) + gprintk(XENLOG_WARNING, + "%pp: ignored BAR %zu write while mapped\n", + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); + return; + } + } /* * Update the cached address, so that when memory decoding is enabled @@ -715,6 +726,9 @@ static void cf_check bar_write( } pci_conf_write32(pdev->sbdf, reg, val); + + if ( bar->enabled ) + modify_bars(pdev, cmd, false, true); } static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 02:25:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 02:25:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274421.1560532 (Exim 4.92) (envelope-from ) id 1w9w7d-0000iU-Ow; Tue, 07 Apr 2026 02:24:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274421.1560532; Tue, 07 Apr 2026 02:24:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9w7d-0000iM-K8; Tue, 07 Apr 2026 02:24:57 +0000 Received: by outflank-mailman (input) for mailman id 1274421; Tue, 07 Apr 2026 02:24:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9w7c-0000iG-JR for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 02:24:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9w7b-000YU8-HP for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 04:24:55 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d46a93-bab6-0a2a0a5309dd-0a2a450cabae-32 for ; Tue, 07 Apr 2026 04:24:55 +0200 Received: from [124.126.103.232] (helo=mailgw.kylinos.cn) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d46af4-f40c-0a2a450c0019-7c7e67e8e51a-3 for ; Tue, 07 Apr 2026 04:24:54 +0200 Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 730094213; Tue, 07 Apr 2026 10:24:46 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none X-UUID: f224c9a4322811f1aa26b74ffac11d73-20260407 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:7e94b4d7-7953-4c7f-a6e2-6f9af9de78fd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:7435d5df1d566edbeea2e54162a75b2b,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:102|123|850|898,TC:nil,Content:0|15|50,E DM:-3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA :0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: f224c9a4322811f1aa26b74ffac11d73-20260407 X-User: zhaoguohan@kylinos.cn From: zhaoguohan@kylinos.cn To: jgross@suse.com, sstabellini@kernel.org Cc: oleksandr_tyshchenko@epam.com, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, GuoHan Zhao Subject: [PATCH] xen/manage: unwind partial shutdown watcher setup on error Date: Tue, 7 Apr 2026 10:24:43 +0800 Message-ID: <20260407022443.12971-1-zhaoguohan@kylinos.cn> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775528695-FE74EA3D-5C680B20/0/0 X-purgate-type: clean X-purgate-size: 2011 From: GuoHan Zhao setup_shutdown_watcher() registers shutdown_watch first, then the sysrq watch, and finally publishes the supported feature-* nodes in xenstore. If sysrq watch registration fails, or xenbus_printf() fails after one or more feature nodes were created, the function returns immediately without undoing the earlier setup. This leaves the system in a partially initialized state, with registered watches and/or stale xenstore entries despite the function reporting failure. Unwind the partial setup before returning an error by unregistering any watches that were already registered and removing feature nodes that were already published. Signed-off-by: GuoHan Zhao --- drivers/xen/manage.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/xen/manage.c b/drivers/xen/manage.c index e20c40a62e64..18bf09e0192a 100644 --- a/drivers/xen/manage.c +++ b/drivers/xen/manage.c @@ -343,12 +343,11 @@ static int setup_shutdown_watcher(void) return err; } - #ifdef CONFIG_MAGIC_SYSRQ err = register_xenbus_watch(&sysrq_watch); if (err) { pr_err("Failed to set sysrq watcher\n"); - return err; + goto err_unregister_shutdown; } #endif @@ -361,11 +360,26 @@ static int setup_shutdown_watcher(void) if (err) { pr_err("%s: Error %d writing %s\n", __func__, err, node); - return err; + goto err_remove_features; } } return 0; + +err_remove_features: + while (--idx >= 0) { + if (!shutdown_handlers[idx].flag) + continue; + snprintf(node, FEATURE_PATH_SIZE, "feature-%s", + shutdown_handlers[idx].command); + xenbus_rm(XBT_NIL, "control", node); + } +#ifdef CONFIG_MAGIC_SYSRQ + unregister_xenbus_watch(&sysrq_watch); +#endif +err_unregister_shutdown: + unregister_xenbus_watch(&shutdown_watch); + return err; } static int shutdown_event(struct notifier_block *notifier, -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 06:14:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 06:14:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274438.1560541 (Exim 4.92) (envelope-from ) id 1w9zhy-0002eR-1m; Tue, 07 Apr 2026 06:14:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274438.1560541; Tue, 07 Apr 2026 06:14:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zhx-0002eI-Sk; Tue, 07 Apr 2026 06:14:41 +0000 Received: by outflank-mailman (input) for mailman id 1274438; Tue, 07 Apr 2026 06:14:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zhx-0002eC-6i for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 06:14:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9zhv-002tEl-VH for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 08:14:39 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4a0cb-2eae-0a2a0a5409dd-0a2a45028af4-32 for ; Tue, 07 Apr 2026 08:14:39 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4a0cf-42fa-0a2a45020019-d155dd33d9ec-3 for ; Tue, 07 Apr 2026 08:14:39 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43d02a71526so2627876f8f.3 for ; Mon, 06 Apr 2026 23:14:39 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. [37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d1e4f5016sm50588982f8f.33.2026.04.06.23.14.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Apr 2026 23:14:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=suse.com header.i="@suse.com" header.h="Content-Transfer-Encoding:In-Reply-To:Autocrypt:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1775542479; x=1776147279; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:autocrypt:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:from:to:cc:subject:date:message-id:reply-to; bh=tV1fizWcuooj1WZi3D6VF5H/rrwxbj+in7H8cAwzJ9M=; b=LBiDHuOGKQy+c5JXjhwrKgPBon0bFP3yXlXD9vm5pw1qpjdN/EK6mJxClQ3qU6QceL c7ONpPWbqqjZS08k9LhWDSFqofTWy1raPvou6K7TQidHGrESK/a06+IIwv2bxMD2ps5V g+qsijrcA7vl0A6/FoPspIt3LTmHLOm8bC+AKuXGM8N1X3TkAgYcsZ293l42QdEuU65S YBMZIL/ImYo22n2JB4OoYT/o8Vm4cXL/5CzdDygFPaHX1XA0JfbPXQcRPfTgDK5HpZXj kyYy++kUiNOoYTbJzCNyfe6oLBagdF5VFYXGzYM1UA8gDjTMdWhsedYpuMwAuoQtlMM2 PH2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775542479; x=1776147279; h=content-transfer-encoding:in-reply-to:autocrypt:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=tV1fizWcuooj1WZi3D6VF5H/rrwxbj+in7H8cAwzJ9M=; b=UZYb/kaBgy/gkjPtE35mvojAL77AN5BjgYi5VdpAlo/OudfDoczOQ6AwBktzGeYBZp /zpswLI1TWuiKogP4xLzx/ukrFjlw5oXAoKbrAZ/kNpR7XoeFl7ItcQfLbs/DI8kZ4sB AuK8ZFcyEnzs6wcoVRlRUos3ZN5od9pAqaW02y3kprXQlio47tM6WSNEs9MA/6/cdB/I ctdu/0qdfGh/yVhTPk/357svCAWpHjZp5bxuaCnQwItsWDfbaBiMnMDu0BOVl6CjLD7C gIE1M7gUHb65lbidLHS+oVSAALa2ZCMwz3OVOVhVh2SxsD0s8/2TUxukqoWhaNi9re6J aNnQ== X-Gm-Message-State: AOJu0YyoWgKyoxu1+5/pG28KFEkxDmAk70coX2KNqk5tU6PqwxRQA3tz IWTMzFHwvRiYznXIfy+6/cub4TstPuhCowdPW3s+YNM6d84aB2Hi44Wmknc/qKho8A== X-Gm-Gg: AeBDietTBI2EVxk0O82bEdtUag00uHLLBuHuAQTy+aH1WRjjcOMQMjNj9id4Z7FkJk+ TPb3Esu8CMpl33nDTKZP2WL7KHR9fQUD1TG2smCkL/mlnSabxdehcCI6NyY+f5Rd3HuepigWX80 E34E5Wff9ZRA49kBORuWdofevJkDr5fPnU/bLlev9tLmhsyIZEjyACmHJjdSDrfy9avvp3JcNUc z5fM7ap8AmisqA6sEAVwFG1tyTC9y/Hc6p7phgLc+XkeHnddl3s1e8lLfR+7LxZjW5j71dj2VOQ Ca2QI/psU5FKpP6YQLAOagqkpyapjz3uhJfFiObVz6TCzA5dpVavy/st14upkQZWppO7dQTAqft sXA36ZeTTYdJ4bPdJuopp4ksTrxm9JlpraCdPucJimh4Al6T5YvM1qCvsm07N74LBtfuhUDZbSl /VhGxlTyDtSs5T1bfMZH+tbOqTpmBRtz/tKcOgxOlDdL8QCvZQ42VwZWrQ1LXbNsYp/+fT1gzMn tGokU9GODykCQw= X-Received: by 2002:a05:6000:186c:b0:43b:41df:705e with SMTP id ffacd0b85a97d-43d2930fc4fmr22489562f8f.49.1775542478909; Mon, 06 Apr 2026 23:14:38 -0700 (PDT) Message-ID: Date: Tue, 7 Apr 2026 08:14:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel , =?UTF-8?B?SsO8cmdlbiBHcm8=?= =?UTF-8?B?w58=?= , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775542479-447CBCD1-BC2D604D/0/0 X-purgate-type: clean X-purgate-size: 855 On 03.04.2026 15:55, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 03:02:15PM +0200, Marek Marczykowski-Górecki wrote: >> On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-Górecki wrote: >>> Some further observation, this time regarding timers: >> >> In the meantime Roger suggested it might be about C-states. So, I just >> tried booting with max_cstate=0. I got this: > > We had a design session on this issue, and managed to find (thanks Roger!) > that adding: > > tsc_mode='always_emulate' > > to the domU config fixes the issue. Now, the question is how to fix it > properly... Seeing also the remarks on Matrix, what we will hence need to figure is what TSC parameters (of the system and/or the VM) change across suspend. As per Matrix everything looked at so far was apparently stable. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775542687-10F5E41E-53F6A628/0/0 X-purgate-type: clean X-purgate-size: 4508 On 03.04.2026 10:47, Stewart Hildebrand wrote: > On 4/1/26 09:03, Jan Beulich wrote: >> On 01.04.2026 14:57, Jürgen Groß wrote: >>> On 01.04.26 14:29, Jan Beulich wrote: >>>> Leaving aside highly disaggregated environments, the control domain is >>>> what will invoke XEN_SYSCTL_SCHEDOP_putinfo. Its vCPU-s therefore need to >>>> be able to run unconditionally, not those of the domain with ID 0 (which >>>> may not exist at all). >>>> >>>> Fixes: 9f0c658baedc ("arinc: add cpu-pool support to scheduler") >>>> Signed-off-by: Jan Beulich >>>> --- >>>> There being no "else" to the if(), what about other control domain vCPU-s? >>> >>> I guess this is a stale leftover. Doesn't matter for committing anyway. >>> >>>> --- >>>> v3: Don't mistakenly include the idle domain. >>>> v2: New. >>>> >>>> --- a/xen/common/sched/arinc653.c >>>> +++ b/xen/common/sched/arinc653.c >>>> @@ -411,10 +411,10 @@ a653sched_alloc_udata(const struct sched >>>> spin_lock_irqsave(&sched_priv->lock, flags); >>>> >>>> /* >>>> - * Add every one of dom0's units to the schedule, as long as there are >>>> - * slots available. >>>> + * Add every one of the control domain's units to the schedule, as long as >>>> + * there are slots available. >>>> */ >>>> - if ( unit->domain->domain_id == 0 ) >>>> + if ( is_control_domain(unit->domain) && !is_idle_domain(unit->domain) ) >>>> { >>>> entry = sched_priv->num_schedule_entries; >>>> >>> >>> Hmm, is it really the control domain only which wants to be scheduled initially? >>> I would think that at least the hardware domain and probably a Xenstore domain >>> would want to be included, too. >>> >>> In the end it might even be that other domains created via dom0less would want >>> to be able to run initially. They could be part of a mandatory infrastructure. >>> Why would they need to be created at boot if they are NOT important? >> >> This part is easy to answer: Because in a dom0less setup you simply may have >> no toolstack at all. (At which point there may also be nothing to set a >> schedule, yes.) > > This is a known limitation. In a dom0less/hyperlaunch scenario, as future work, > I would like to see the ability to configure the ARINC653 schedule in device > tree, which would likely extend the existing boot time cpu pool work. > >>> The question is whether the arinc653 scheduler is really meant for such setups. >>> OTOH just modifying the test to: >>> >>> if ( system_state < SYS_STATE_active && >>> unit->domain->domain_id < DOMID_FIRST_RESERVED ) >>> >>> seems to be fine for catching all those cases. >>> >>> With or without this modification: >>> >>> Reviewed-by: Juergen Gross >> >> Thanks, yet I'll have to leave to the maintainers to decide which form it >> should ultimately take. One remark: A restartable control domain wouldn't >> pass that conditional. Granted that's looking far into the future. > > It may not be desirable to schedule domUs until the control domain has had a say > in the matter, considering that the default schedule is unlikely to contain the > desired minor frame runtimes. It's less clear whether to include hardware and > xenstore domains in the default schedule, though I'm leaning toward only > including the domain with ability to invoke XEN_SYSCTL_SCHEDOP_putinfo for now > (i.e. the control domain). > > Hm, the suggested 'system_state < SYS_STATE_active' check is possibly a good > addition. This reinforces that the default schedule's purpose is merely to get a > system booting until a user-provided schedule can be installed. Without this > check, restarting the control domain could result in new entries being added > while old entries remain, possibly ending up with duplicates and/or exhausting > the schedule. However, the restarted domain would need to retain its uuid if it > expects to be scheduled after restart. > > Lastly, we may consider restricting the default schedule to Pool-0, and > eventually we may want a mechanism to disable the default schedule altogether > (e.g. when boot time cpupools are in use), but I don't think it's necessary to > conflate those with the current patch. So what does all of this mean for the patch here? Should I switch to Jürgen's suggestion? Should I merely add the system_state check, but otherwise keep as is? Or should I not change anything? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 06:23:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 06:23:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274458.1560558 (Exim 4.92) (envelope-from ) id 1w9zqP-0004q7-4i; Tue, 07 Apr 2026 06:23:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274458.1560558; Tue, 07 Apr 2026 06:23:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zqP-0004q0-29; Tue, 07 Apr 2026 06:23:25 +0000 Received: by outflank-mailman (input) for mailman id 1274458; Tue, 07 Apr 2026 06:23:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zqN-0004pu-17 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 06:23:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9zqM-00Enko-9R for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 08:23:22 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4a2c5-2eae-0a2a0a5409dd-0a2a4508dbbc-46 for ; Tue, 07 Apr 2026 08:23:22 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4a2d9-fab6-0a2a45080019-d155dd32bd34-3 for ; Tue, 07 Apr 2026 08:23:22 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43cfd96354aso2750385f8f.1 for ; Mon, 06 Apr 2026 23:23:22 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <912263a2-8dff-414e-bea4-64428ce2ec36@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775543002-94365497-10DC61EB/0/0 X-purgate-type: clean X-purgate-size: 2822 On 06.04.2026 17:43, Oleksii Kurochko wrote: > > > On 4/1/26 5:10 PM, Jan Beulich wrote: >> On 01.04.2026 16:53, Oleksii Kurochko wrote: >>> >>> >>> On 4/1/26 4:22 PM, Jan Beulich wrote: >>>> On 01.04.2026 15:57, Oleksii Kurochko wrote: >>>>> On 4/1/26 8:17 AM, Jan Beulich wrote: >>>>>> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>>>>>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>>>>>> so introduce macros to describe guest RAM banks. >>>>>>>>> >>>>>>>>> The reason for 2 banks is that there is typically always a use case for >>>>>>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>>>>>> there are other things under 4 GB it can conflict with (interrupt >>>>>>>>> controller, PCI BARs, etc.). >>>>>>>> Fixed layouts like the one you suggest come with (potentially severe) >>>>>>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>>>>>> for non-64-bit BARs? >>>>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>>>> before RAM start is enough for MMIO space. >>>>>> Likely in the common case. Board designers aren't constrained by this, >>>>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>>>> >>>>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>>>> could you chime in here, please? >>>>>> >>>>>>> Answering your question it will be an issue or it will also use some >>>>>>> space before banks, no? >>>>>> I fear I don't understand what you're trying to tell me. >>>>> I meant that there is also some space between banks and pretty big which >>>>> could be used for MMIO which could be used for non-64-bit BARs. >>>> I don't follow: Bank 0 extends to 4G. There's no space above it, below >>>> bank 1, which could be use for non-64-bit BARs. >>> >>> So we have two banks: >>> bank[0] -> [0x80000000, 0x100000000) >>> bank[1] -> [0x0200000000, 10000000000) >>> >>> So i think we have some space between them [0x100000000, 0x0200000000) >>> -> 4gb to be used for non-64-bit BARs. >> >> But a non-64-bit BAR need to be assigned an address below 0x100000000? > > Right, I had in mind that RV32 uses for guest Sv32x4 which could > translate 34-bit GPA into 34-bit MPA and automatically applied that to > 32-bit BAR... > > I can keep first 4gb for MMIO purpose and start bank[0] at 4gb as 34 MPA > address space is more then enough to cover reserved 2gb of bank[0] after > 4gb. Yet having no memory below 4G won't work for guests wanting to run in bare mode? Don't guests even start up in bare mode (and hence 32-bit ones need to have some of their memory below 4G in all cases)? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 06:29:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 06:29:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274467.1560568 (Exim 4.92) (envelope-from ) id 1w9zwY-0005a2-Pr; Tue, 07 Apr 2026 06:29:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274467.1560568; Tue, 07 Apr 2026 06:29:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zwY-0005Zv-ND; Tue, 07 Apr 2026 06:29:46 +0000 Received: by outflank-mailman (input) for mailman id 1274467; Tue, 07 Apr 2026 06:29:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1w9zwX-0005Zn-TI for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 06:29:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1w9zwW-002wGl-Oa for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 08:29:44 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4a453-e002-0a2a0a5209dd-0a2a4507c196-12 for ; Tue, 07 Apr 2026 08:29:44 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4a458-ba2d-0a2a45070019-d1558035b044-3 for ; Tue, 07 Apr 2026 08:29:44 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-483487335c2so46425025e9.2 for ; Mon, 06 Apr 2026 23:29:44 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 06 Apr 2026 23:29:43 -0700 (PDT) Message-ID: <47b140b2-596b-47db-9c0c-43672f445036@suse.com> Date: Tue, 7 Apr 2026 08:29:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> <92e0151b-3fb1-4108-9788-f0fbac43512b@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775543384-10D5F41E-EBD2CF76/0/0 X-purgate-type: clean X-purgate-size: 7845 On 03.04.2026 01:06, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 04:53:31PM +0200, Jan Beulich wrote: >> On 02.04.2026 16:47, Marek Marczykowski-Górecki wrote: >>> On Thu, Apr 02, 2026 at 12:48:14PM +0200, Jan Beulich wrote: >>>> On 02.04.2026 11:35, Marek Marczykowski-Górecki wrote: >>>>> On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: >>>>>> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>>>>>> The xl dmesg output (from MTL this time): >>>>>>> >>>>>>> (XEN) [ 123.477511] Entering ACPI S3 state. >>>>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>>>> >>>>>> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() actually >>>>>> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE() values >>>>>> might be a good idea, if only to double check.) >>>>> >>>>> Updated output: >>>>> >>>>> (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>>> (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>>>> (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 >>>>> (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_events: ffff83046bc1f080 >>>>> (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets_used: 8 >>>>> (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 >>>>> (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 >>>>> (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: 2 (iommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 >>>>> (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire_from_msi rc: 0 >>>> >>>> So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausible. The high >>>> half is, however, the address that the low half value is written to. It's hard >>>> to imagine that it would be zero when the low half isn't, but it is about the >>>> last thing I can think of which could explain observed behavior. (Yet then, all >>>> of this is pretty meaningless; see below.) >>>> >>>>> And the current debug diff attached. >>>> >>>> Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very useful. You want >>>> to move that part of logging to the bottom of hpet_msi_write(), or maybe to >>>> where you also log the per-channel cfg value in hpet_broadcast_resume() (thus >>>> making the logging overall less verbose). >>> >>> This test is with the updated patch (attached) + your extra >>> calculate_host_policy() call and "no-arat" on cmdline: >> >> And IOMMU faults still occurring as before, I expect. >> >> Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you don't log >> the high halves at all. > > I was missing hpet_read32 there... > > Updated: > (XEN) [ 116.921573] Entering ACPI S3 state. > (XEN) [18446743895.088893] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743895.088907] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > (XEN) [18446743895.088918] _disable_pit_irq:2662: init: 0 > (XEN) [18446743895.088928] hpet_broadcast_resume:662: hpet_events: ffff83046bc1f080 > (XEN) [18446743895.089072] hpet_broadcast_resume:673: num_hpets_used: 8 > (XEN) [18446743895.089081] hpet_broadcast_resume:691: cfg: 0x1 > (XEN) [18446743895.089092] hpet_broadcast_resume:696: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 > (XEN) [18446743895.089122] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089132] hpet_broadcast_resume:700: i:0, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089168] hpet_broadcast_resume:710: i:0, cfg: 0xc134, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf18 Okay, this would appear to clarify that the address really isn't correct. Yet I'm confused now by the low half values: In your earlier log there was hpet_broadcast_resume:710: i:0, cfg: 0xc134, HPET_Tn_ROUTE(hpet_events[i].idx): 0x110 and alike, i.e. clearly a non-zero value. Now all low halves are zero. I'll try to figure how the logged values here could result, but consistent data (or an explantation for the apparent inconsistency) would help. Jan > (XEN) [18446743895.089180] hpet_broadcast_resume:696: i:1, hpet_events[i].msi.irq: 123, hpet_events[i].flags: 0 > (XEN) [18446743895.089203] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089213] hpet_broadcast_resume:700: i:1, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089242] hpet_broadcast_resume:710: i:1, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf38 > (XEN) [18446743895.089254] hpet_broadcast_resume:696: i:2, hpet_events[i].msi.irq: 124, hpet_events[i].flags: 0 > (XEN) [18446743895.089278] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089288] hpet_broadcast_resume:700: i:2, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089316] hpet_broadcast_resume:710: i:2, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf58 > (XEN) [18446743895.089327] hpet_broadcast_resume:696: i:3, hpet_events[i].msi.irq: 125, hpet_events[i].flags: 0 > (XEN) [18446743895.089350] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089361] hpet_broadcast_resume:700: i:3, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089390] hpet_broadcast_resume:710: i:3, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf78 > (XEN) [18446743895.089401] hpet_broadcast_resume:696: i:4, hpet_events[i].msi.irq: 126, hpet_events[i].flags: 0 > (XEN) [18446743895.089425] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089436] hpet_broadcast_resume:700: i:4, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089465] hpet_broadcast_resume:710: i:4, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf98 > (XEN) [18446743895.089476] hpet_broadcast_resume:696: i:5, hpet_events[i].msi.irq: 127, hpet_events[i].flags: 0 > (XEN) [18446743895.089499] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089509] hpet_broadcast_resume:700: i:5, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089540] hpet_broadcast_resume:710: i:5, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfb8 > (XEN) [18446743895.089551] hpet_broadcast_resume:696: i:6, hpet_events[i].msi.irq: 128, hpet_events[i].flags: 0 > (XEN) [18446743895.089574] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089584] hpet_broadcast_resume:700: i:6, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089622] hpet_broadcast_resume:710: i:6, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfd8 > (XEN) [18446743895.089633] hpet_broadcast_resume:696: i:7, hpet_events[i].msi.irq: 129, hpet_events[i].flags: 0 > (XEN) [18446743895.089655] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743895.089665] hpet_broadcast_resume:700: i:7, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743895.089702] hpet_broadcast_resume:710: i:7, cfg: 0xc104, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xff8 > > > > From xen-devel-bounces@lists.xenproject.org Tue Apr 07 06:46:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 06:46:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274476.1560576 (Exim 4.92) (envelope-from ) id 1wA0Cs-0008Lj-3E; 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Mon, 06 Apr 2026 23:46:35 -0700 (PDT) Message-ID: <6dccae5f-fe09-4f35-9e4a-7a38fb21e8d1@suse.com> Date: Tue, 7 Apr 2026 08:46:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Marek Marczykowski From: Jan Beulich Subject: [PATCH] x86/cpu-policy: set up host policy earlier Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1775544395-47B2BC9A-AF9FE16B/0/0 X-purgate-type: clean X-purgate-size: 2089 In order to use cpu_has_* expanding to host_cpu_policy.*, the host policy needs setting up alongside boot_cpu_data.x86_capability[]. Arrange for that towards the end of identify_cpu(). Fixes: 894bd7617924 ("x86/Intel: use host CPU policy for ARAT checking") Reported-by: Marek Marczykowski-Górecki Signed-off-by: Jan Beulich --- In the longer run we may need to (also) update the host policy from setup_{force,clear}_cpu_cap(). This really was part of one of the XSTATE cleanup patches at the head of the AMX series. This explains the specific placement ahead of the call to xstate_init()). Likely anything from there downwards shouldn't really live in identify_cpu() anyway. --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -586,6 +586,8 @@ void identify_cpu(struct cpuinfo_x86 *c) } /* Now the feature flags better reflect actual CPU features! */ + if (c == &boot_cpu_data) + calculate_host_policy(); xstate_init(c); --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -359,7 +359,7 @@ void calculate_raw_cpu_policy(void) /* Was already added by probe_cpuid_faulting() */ } -static void __init calculate_host_policy(void) +void __init calculate_host_policy(void) { struct cpu_policy *p = &host_cpu_policy; unsigned int max_extd_leaf; @@ -904,6 +904,7 @@ static void __init calculate_hvm_def_pol void __init init_guest_cpu_policies(void) { + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() uses. */ calculate_host_policy(); if ( IS_ENABLED(CONFIG_PV) ) --- a/xen/arch/x86/include/asm/cpu-policy.h +++ b/xen/arch/x86/include/asm/cpu-policy.h @@ -30,4 +30,10 @@ void recalculate_cpuid_policy(struct dom */ void calculate_raw_cpu_policy(void); +/* + * Collect the host CPU policy. Called after collecting enough CPUID output, + * and again after all feature overrides have been put in place. + */ +void calculate_host_policy(void); + #endif /* X86_CPU_POLICY_H */ From xen-devel-bounces@lists.xenproject.org Tue Apr 07 06:48:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 06:48:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274486.1560587 (Exim 4.92) (envelope-from ) id 1wA0ET-0000aF-Ho; Tue, 07 Apr 2026 06:48:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274486.1560587; Tue, 07 Apr 2026 06:48:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA0ET-0000a8-E1; Tue, 07 Apr 2026 06:48:17 +0000 Received: by outflank-mailman (input) for mailman id 1274486; Tue, 07 Apr 2026 06:48:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA0ES-0000a2-7a for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 06:48:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA0ER-000JkJ-JG for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 08:48:15 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4a8af-5cb7-0a2a0a5109dd-0a2a4503cf04-0 for ; Tue, 07 Apr 2026 08:48:15 +0200 Received: from [209.85.221.53] (helo=mail-wr1-f53.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4a8af-02b3-0a2a45030019-d155dd35d444-3 for ; Tue, 07 Apr 2026 08:48:15 +0200 Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-43cfbd17589so3587214f8f.0 for ; Mon, 06 Apr 2026 23:48:15 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1775544495-4056AC9A-CFC90C49/0/0 X-purgate-type: clean X-purgate-size: 3296 On 02.04.2026 16:02, Marek Marczykowski-Górecki wrote: > On Thu, Apr 02, 2026 at 12:23:08PM +0200, Jan Beulich wrote: >> On 02.04.2026 11:42, Marek Marczykowski-Górecki wrote: >>> On Thu, Apr 02, 2026 at 10:47:53AM +0200, Jan Beulich wrote: >>>> On 02.04.2026 10:39, Jan Beulich wrote: >>>>> On 02.04.2026 10:08, Marek Marczykowski-Górecki wrote: >>>>>> The xl dmesg output (from MTL this time): >>>>>> >>>>>> (XEN) [ 123.477511] Entering ACPI S3 state. >>>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >>>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >>>>> >>>>> XEN_ARAT being off is the one odd aspect here. That'll want tracking down >>>>> separately. As per xen-cpuid output (below) ARAT is available. >>>> >>>> For this you may want to also add logging to intel_init_arat(): Since opt_arat >>>> can be false only due to command line option use, it can only be the function >>>> not being called (which looks impossible on plain staging code), or cpu_has_arat >>>> being false despite the xen-cpuid output that you supplied earlier (inexplicable >>>> as well, at least for now). >>> >>> Hm, I got this: >>> >>> (XEN) [ 11.403340] intel_init_arat:674: opt_arat: 1, cpu_has_arat: 0 >>> >>> so, cpu_has_arat=0 ... >>> next lines are those, to hint when it happened in the boot process: >>> >>> (XEN) [ 11.409754] mwait-idle: MWAIT substates: 0x11112020 >>> (XEN) [ 11.416130] mwait-idle: v0.4.1 model 0xaa >>> (XEN) [ 11.422396] mwait-idle: lapic_timer_reliable_states 0x2 >>> >>> Looks like calculate_host_policy() runs much later... >> >> Hmm, yes, and that's the problem. The reason I don't see this is that a newer >> version of [1] has this >> >> --- a/xen/arch/x86/cpu/common.c >> +++ b/xen/arch/x86/cpu/common.c >> @@ -628,6 +628,8 @@ void identify_cpu(struct cpuinfo_x86 *c) >> } >> >> /* Now the feature flags better reflect actual CPU features! */ >> + if (c == &boot_cpu_data) >> + calculate_host_policy(); >> >> xstate_init(c); >> >> --- a/xen/arch/x86/cpu-policy.c >> +++ b/xen/arch/x86/cpu-policy.c >> @@ -384,7 +384,7 @@ void calculate_raw_cpu_policy(void) >> /* Was already added by probe_cpuid_faulting() */ >> } >> >> -static void __init calculate_host_policy(void) >> +void __init calculate_host_policy(void) >> { >> struct cpu_policy *p = &host_cpu_policy; >> >> @@ -959,6 +959,7 @@ static void __init calculate_hvm_def_pol >> >> void __init init_guest_cpu_policies(void) >> { >> + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() uses. */ >> calculate_host_policy(); >> >> if ( IS_ENABLED(CONFIG_PV) ) >> >> and of course I'm doing my work (and my analysis) with that in place. > > FWIW, with this patch applied I get: > (XEN) [18446743899.051851] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743899.051865] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 1 > > And no IOMMU faults anymore. I've Cc-ed you on the formal patch submission; please clarify whether I may translate the above to Tested-by:. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260402155512.80170-1-frediano.ziglio@cloud.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775544959-EEB482A1-4A929AB7/0/0 X-purgate-type: clean X-purgate-size: 811 On 02.04.2026 17:55, Frediano Ziglio wrote: > --- a/xen/arch/x86/dom0_build.c > +++ b/xen/arch/x86/dom0_build.c > @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, > return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); > } > > +int __init dom0_check_parms( I understand the "dom0" in the name is owing to the filename and perhaps adjacent other similar functions, yet ... > + struct domain *d, const struct elf_dom_parms *parms) > +{ > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) > + return 0; > + > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) ... if this was about solely Dom0, no is_hardware_domain() should be present here. Maybe s/dom0/initdom/ ? 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Mon, 06 Apr 2026 23:57:07 -0700 (PDT) Message-ID: <572b62e7-30de-4a23-8602-98a38e02acb7@suse.com> Date: Tue, 7 Apr 2026 08:57:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/x86: Check supported features even for PVH dom0 To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Frediano Ziglio Cc: xen-devel@lists.xenproject.org, Frediano Ziglio , Andrew Cooper References: <20260402155512.80170-1-frediano.ziglio@cloud.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775545028-64A4C3D8-0D763C1B/0/0 X-purgate-type: clean X-purgate-size: 2506 On 03.04.2026 12:11, Roger Pau Monné wrote: > On Thu, Apr 02, 2026 at 04:55:10PM +0100, Frediano Ziglio wrote: >> The supported features ELF notes was tested only if the dom0 was >> PV. Factor out a function to check ELF notes and reuse it even >> for PVH. >> >> Signed-off-by: Frediano Ziglio >> -- >> Changes since v1: >> - fix typo in title; >> - fix minor formatting issue; >> - use is_hardware_domain instead of checking is_pv_shim; >> - reduce indentation returning earlier; >> - return error instead of jumping to cleanup code. >> --- >> xen/arch/x86/dom0_build.c | 14 ++++++++++++++ >> xen/arch/x86/hvm/dom0_build.c | 3 +++ >> xen/arch/x86/include/asm/dom0_build.h | 2 ++ >> xen/arch/x86/pv/dom0_build.c | 10 ++-------- >> 4 files changed, 21 insertions(+), 8 deletions(-) >> >> diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c >> index 864dd9e53e..a33ce77321 100644 >> --- a/xen/arch/x86/dom0_build.c >> +++ b/xen/arch/x86/dom0_build.c >> @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, >> return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); >> } >> >> +int __init dom0_check_parms( >> + struct domain *d, const struct elf_dom_parms *parms) > > d should be const also. > >> +{ >> + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) >> + return 0; >> + >> + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) >> + { >> + printk("Kernel does not support Dom0 operation\n"); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> >> /* >> * If allocation isn't specified, reserve 1/16th of available memory for >> diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c >> index d69a83b089..f95a00acfd 100644 >> --- a/xen/arch/x86/hvm/dom0_build.c >> +++ b/xen/arch/x86/hvm/dom0_build.c >> @@ -699,6 +699,9 @@ static int __init pvh_load_kernel( >> if ( !check_and_adjust_load_address(d, &elf, &parms) ) >> return -ENOSPC; >> >> + if ( (rc = dom0_check_parms(d, &parms)) != 0 ) >> + return rc; > > I would do the check ahead of check_and_adjust_load_address(), as then > we could avoid the load address adjustment if we detect earlier than > the dom0 feature is not present. But that's just my taste. +1, perhaps even yet a few more lines further up. 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Tue, 07 Apr 2026 01:08:10 -0700 (PDT) From: =?UTF-8?B?TWF0ecOhxaE=?= Kroupa To: xen-devel@lists.xen.org Subject: Xen on Zen 3 Date: Tue, 07 Apr 2026 10:08:07 +0200 Message-ID: <5490687.niJfEyVGOH@rivendell.hailstone.cz> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart6521316.E0xQCEvomI" Content-Transfer-Encoding: 7Bit X-purgate-ID: tlsNG-bad1c0/1775549291-5D1F5152-EB3E9FC2/0/0 X-purgate-type: clean X-purgate-size: 19301 This is a multi-part message in MIME format. --nextPart6521316.E0xQCEvomI Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hi, I am trying to run Xen on a bare metal with Zen 3 microarchitecture (to be= =20 specific Ryzen 9 5950X). I am using Fedora 43 as Dom0 in PVH mode. However,= the=20 Linux kernel crashes early in the boot causing Xen to reboot. I am not exac= tly=20 sure if Linux or Xen is the problematic part. The kernel boots fine without= =20 Xen. Before Ryzen 9 I had Ryzen 5 3400G (Zen+) which booted even with Xen. The Xen is a backported from Fedora 44 (not yet released) because I need Xe= n=20 4.21 features, mainly ReBAR support for the Arc B50 GPU. Package specificat= ion=20 with build commands can be found on https://src.fedoraproject.org/rpms/xen/ blob/f44/f/xen.spec. There are also downstream patches and configuration. I have set up a serial link, so I have some logs. They are in the attachmen= t.=20 I have used gdb to translate the binary offset to source code line. The=20 problematic line is https://elixir.bootlin.com/linux/v6.19.10/source/arch/x= 86/ kernel/amd_node.c#L296. It seems that linux is detecting zero PCI roots on= =20 non-zero number of nodes causing division by zero. System information Boot mode: UEFI Secure boot: disabled IOMMU: enabled SR-IOV: enabled Above 4G decoding & rebar: enabled Xen cmdline: placeholder dom0=3Dpvh dom0_mem=3D36G com1=3D115200,8n1=20 console=3Dcom1,vga no-real-mode edd=3Doff Linux cmdline: placeholder root=3DUUID=3D5a7af636-54c3-4f76-a164-c1138de257= ad ro=20 rootflags=3Dsubvol=3D@ rhgb quiet console=3Dhvc0 earlyprintk=3Dxen Xen version: 4.21.1 Linux version: 6.19.10 If you need more logs or other information, I will be more than happy to=20 provide it. Thank you in advance Maty=C3=A1=C5=A1 Kroupa --nextPart6521316.E0xQCEvomI Content-Disposition: attachment; filename="xen-4.21.1-linux-6.19.10.log" Content-Transfer-Encoding: quoted-printable Content-Type: text/x-log; charset="UTF-8"; name="xen-4.21.1-linux-6.19.10.log" error: ../../grub-core/commands/loadenv.c:216:sparse file not allowed. GRUB version 2.12 +--------------------------------------------------------------------------= =2D-+||||||||||||||||||||||+-----------------------------------------------= =2D----------------------------+ Use the ^ and v keys to select which e= ntry is highlighted. =20 Press enter to boot the selected OS, `e' to edit the commands =20 before booting or `c' for a command-line. ESC to return =20 previous menu. = Fedora Linux (6.19.10-200.fc43.x86_64) 43 (Server Edition) = Fedora Linux (6.19.9-200.fc43.x86_64) 43 (Server Edition) = Fedora Linux (6.19.8-200.fc43.x86_64) 43 (Server Edition) = Fedora Linux (6.6.84-200.fc41.x86_64) 43 (Server Edition) = Fedora Linux (0-rescue-9a85b9092f254228a1dc4273a335191f) 43 (Server Ed= itio>*Fedora, with Xen 4.21.1 and Linux 6.19.10-200.fc43.x86_64 = Fedora, with Xen 4.21.1 and Linux 6.19.9-200.fc43.x86_64 = Fedora, with Xen 4.21.1 and Linux 6.19.8-200.fc43.x86_64 = Fedora, with Xen 4.21.1 and Linux 6.6.84-200.fc41.x86_64 = UEFI Firmware Settings = = The highlighted entry will be executed automatically in 5s. = The highlighted entry will be executed automatically in = 4s. The highlighted entry will be executed automatically= in 3s. = = Fedora, with Xen 4.21.1 and Linux 6.19.10-= 200.fc43.x86_64 *Fedora Linux (0-rescue-9a85b9092f254228a1= dc4273a335191f) 43 (Server Editio> Fedora Linux (0-rescue-9a85b9092f254228a= 1dc4273a335191f) 43 (Server Editio>*Fedora, with Xen 4.21.1 and Linux 6.19.= 10-200.fc43.x86_64 Loading Xen 4.21.1 ... Loading Linux 6.19.10-200.fc43.x86_64 ... Loading initial ramdisk ... Xen 4.21.1 (XEN) Xen version 4.21.1 (mockbuild@) (gcc (GCC) 15.2.1 20260123 (Red Hat 1= 5.2.1-7)) debug=3Dn Thu Apr 2 00:00:00 UTC 2026 (XEN) Latest ChangeSet:=20 (XEN) build-id: 86b71d479f28fc1106fffdfe76c8e7037e2e70fa (XEN) CPU Vendor: AMD, Family 25 (0x19), Model 33 (0x21), Stepping 2 (raw 0= 0a20f12) (XEN) BSP microcode revision: 0x0a201213 (XEN) Bootloader: GRUB 2.12 (XEN) Command line: placeholder dom0=3Dpvh dom0_mem=3D36G com1=3D115200,8n1= console=3Dcom1,vga no-real-mode edd=3Doff (XEN) Xen image load base address: 0xb6a00000 (XEN) Video information: (XEN) VGA is graphics mode 1920x1080, 32 bpp (XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds (XEN) Disc information: (XEN) Found 0 MBR signatures (XEN) Found 3 EDD information structures (XEN) Using IDT event delivery (XEN) Enabling Supervisor Shadow Stacks (XEN) - Disabling PV32 due to CET (XEN) EFI RAM map: (XEN) [0000000000000000, 000000000009ffff] (usable) (XEN) [00000000000a0000, 00000000000fffff] (reserved) (XEN) [0000000000100000, 0000000009bfefff] (usable) (XEN) [0000000009bff000, 0000000009ffffff] (reserved) (XEN) [000000000a000000, 000000000a1fffff] (usable) (XEN) [000000000a200000, 000000000a20dfff] (ACPI NVS) (XEN) [000000000a20e000, 000000000affffff] (usable) (XEN) [000000000b000000, 000000000b01ffff] (reserved) (XEN) [000000000b020000, 00000000bb13afff] (usable) (XEN) [00000000bb13b000, 00000000bc947fff] (reserved) (XEN) [00000000bc948000, 00000000bc988fff] (ACPI data) (XEN) [00000000bc989000, 00000000bd07cfff] (ACPI NVS) (XEN) [00000000bd07d000, 00000000bdbfefff] (reserved) (XEN) [00000000bdbff000, 00000000beffffff] (usable) (XEN) [00000000bf000000, 00000000bfffffff] (reserved) (XEN) [00000000f0000000, 00000000f7ffffff] (reserved) (XEN) [00000000fd200000, 00000000fd2fffff] (reserved) (XEN) [00000000fd600000, 00000000fd7fffff] (reserved) (XEN) [00000000fea00000, 00000000fea0ffff] (reserved) (XEN) [00000000feb80000, 00000000fec01fff] (reserved) (XEN) [00000000fec10000, 00000000fec10fff] (reserved) (XEN) [00000000fec30000, 00000000fec30fff] (reserved) (XEN) [00000000fed00000, 00000000fed00fff] (reserved) (XEN) [00000000fed40000, 00000000fed44fff] (reserved) (XEN) [00000000fed80000, 00000000fed8ffff] (reserved) (XEN) [00000000fedc2000, 00000000fedcffff] (reserved) (XEN) [00000000fedd4000, 00000000fedd5fff] (reserved) (XEN) [00000000ff000000, 00000000ffffffff] (reserved) (XEN) [0000000100000000, 0000000c3f2fffff] (usable) (XEN) [0000000c3f300000, 0000000c3fffffff] (reserved) (XEN) ACPI: RSDP BD066014, 0024 (r2 ALASKA) (XEN) ACPI: XSDT BD065728, 00CC (r1 ALASKA A M I 1072009 AMI 1000013) (XEN) ACPI: FACP BC97A000, 0114 (r6 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: DSDT BC973000, 60DA (r2 ALASKA A M I 1072009 INTL 20120913) (XEN) ACPI: FACS BD060000, 0040 (XEN) ACPI: SSDT BC980000, 8CE9 (r2 AMD AmdTable 2 MSFT 4000000) (XEN) ACPI: SSDT BC97C000, 3CB6 (r2 AMD AMD AOD 1 INTL 20120913) (XEN) ACPI: SSDT BC97B000, 01CC (r2 ALASKA CPUSSDT 1072009 AMI 1072009) (XEN) ACPI: FIDT BC972000, 009C (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: MCFG BC971000, 003C (r1 ALASKA A M I 1072009 MSFT 10013) (XEN) ACPI: AAFT BC970000, 00F1 (r1 ALASKA OEMAAFT 1072009 MSFT 97) (XEN) ACPI: HPET BC96F000, 0038 (r1 ALASKA A M I 1072009 AMI 5) (XEN) ACPI: IVRS BC96E000, 00D0 (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: BGRT BC96D000, 0038 (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: TPM2 BC96C000, 004C (r4 ALASKA A M I 1 AMI 0) (XEN) ACPI: PCCT BC96B000, 006E (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: SSDT BC962000, 8033 (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: CRAT BC960000, 1710 (r1 AMD AmdTable 1 AMD 1) (XEN) ACPI: CDIT BC95F000, 0029 (r1 AMD AmdTable 1 AMD 1) (XEN) ACPI: SSDT BC95B000, 37C4 (r2 AMD MYRTLE 1 INTL 20120913) (XEN) ACPI: SSDT BC95A000, 00BF (r1 AMD AmdTable 1000 INTL 20120913) (XEN) ACPI: WSMT BC959000, 0028 (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: APIC BC958000, 015E (r3 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: SSDT BC956000, 10AF (r2 AMD MYRTLE 1 INTL 20120913) (XEN) ACPI: FPDT BC955000, 0044 (r1 ALASKA A M I 1072009 AMI 1000013) (XEN) System RAM: 49075MB (50253492kB) (XEN) No NUMA configuration found (XEN) Faking a node at 0000000000000000-0000000c3f300000 (XEN) Domain heap initialised (XEN) vesafb: framebuffer at 0x000000f800000000, mapped to 0xffff82c0002030= 00, using 8128k, total 8128k (XEN) vesafb: mode is 1920x1080x32, linelength=3D7680, font 8x16 (XEN) vesafb: Truecolor: size=3D8:8:8:8, shift=3D24:16:8:0 (XEN) SMBIOS 3.3 present. (XEN) PCI: MCFG configuration 0: base f0000000 segment 0000 buses 00 - 7f (XEN) PCI: MCFG area at f0000000 reserved in E820 (XEN) PCI: Using MCFG for segment 0000 bus 00-7f (XEN) Using APIC driver default (XEN) ACPI: PM-Timer IO Port: 0x808 (32 bits) (XEN) ACPI: v5 SLEEP INFO: control[0:0], status[0:0] (XEN) ACPI: SLEEP INFO: pm1x_cnt[1:804,1:0], pm1x_evt[1:800,1:0] (XEN) ACPI: 32/64X FACS address mismatch in FADT - bd060000/000000000000000= 0, using 32 (XEN) ACPI: wakeup_vec[bd06000c], vec_size[20] (XEN) Overriding APIC driver with bigsmp (XEN) ACPI: IOAPIC (id[0x21] address[0xfec00000] gsi_base[0]) (XEN) IOAPIC[0]: apic_id 33, version 33, address 0xfec00000, GSI 0-23 (XEN) ACPI: IOAPIC (id[0x22] address[0xfec01000] gsi_base[24]) (XEN) IOAPIC[1]: apic_id 34, version 33, address 0xfec01000, GSI 24-55 (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) (XEN) ACPI: HPET id: 0x10228201 base: 0xfed00000 (XEN) ACPI: BGRT: invalidating v1 image at 0xb762c018 (XEN) Using ACPI (MADT) for SMP configuration information (XEN) SMP: Allowing 32 CPUs (0 hotplug CPUs) (XEN) IRQ limits: 56 GSI, 6600 MSI/MSI-X (XEN) AMD-Vi: IOMMU Extended Features: (XEN) - Peripheral Page Service Request (XEN) - NX bit (XEN) - Invalidate All Command (XEN) - Performance Counters (XEN) - Host Address Translation Size: 0x2 (XEN) - Guest Address Translation Size: 0 (XEN) - Guest CR3 Root Table Level: 0x1 (XEN) - Maximum PASID: 0xf (XEN) - SMI Filter Register: 0x1 (XEN) - SMI Filter Register Count: 0x2 (XEN) - Guest Virtual APIC Modes: 0x1 (XEN) - Dual PPR Log: 0x2 (XEN) - Dual Event Log: 0x2 (XEN) - User / Supervisor Page Protection (XEN) - Device Table Segmentation: 0x3 (XEN) - PPR Log Overflow Early Warning (XEN) - PPR Automatic Response (XEN) - Memory Access Routing and Control: 0x1 (XEN) - Block StopMark Message (XEN) - Performance Optimization (XEN) - MSI Capability MMIO Access (XEN) - Guest I/O Protection (XEN) - Host Access (XEN) - Enhanced PPR Handling (XEN) - Attribute Forward (XEN) - Virtualized IOMMU (XEN) - VMGuard I/O Support (XEN) - VM Table Size: 0x2 (XEN) Switched to APIC driver x2apic_mixed (XEN) CPU0: 2200 ... 3400 MHz (XEN) xstate: size: 0x988 and states: 0x207 (XEN) CPU0: AMD Fam19h machine check reporting enabled (XEN) Speculative mitigation facilities: (XEN) Hardware hints: STIBP_ALWAYS IBRS_FAST IBRS_SAME_MODE (XEN) Hardware features: IBPB IBRS STIBP SSBD PSFD (XEN) Compiled-in support: INDIRECT_THUNK RETURN_THUNK SHADOW_PAGING HARD= EN_ARRAY HARDEN_BRANCH HARDEN_GUEST_ACCESS HARDEN_LOCK (XEN) Xen settings: BTI-Thunk: JMP, SPEC_CTRL: IBRS+ STIBP+ SSBD- PSFD-, = Other: VERW BRANCH_HARDEN (XEN) Support for HVM VMs: MSR_SPEC_CTRL MSR_VIRT_SPEC_CTRL RSB VERW IBPB= =2Dentry (XEN) Support for PV VMs: VERW IBPB-entry (XEN) XPTI (64-bit PV only): Dom0 disabled, DomU disabled (without PCID) (XEN) PV L1TF shadowing: Dom0 disabled, DomU disabled (XEN) Using scheduler: SMP Credit Scheduler rev2 (credit2) (XEN) Initializing Credit2 scheduler (XEN) load_precision_shift: 18 (XEN) load_window_shift: 30 (XEN) underload_balance_tolerance: 0 (XEN) overload_balance_tolerance: -3 (XEN) runqueues arrangement: socket (XEN) cap enforcement granularity: 10ms (XEN) load tracking window length 1073741824 ns (XEN) Platform timer is 14.318MHz HPET (XEN) Detected 3393.617 MHz processor. (XEN) Freed 1008kB unused BSS memory (XEN) alt table ffff82d04049bfb8 -> ffff82d0404b328e (XEN) AMD-Vi: IOMMU 0 Enabled. (XEN) I/O virtualisation enabled (XEN) - Dom0 mode: Relaxed (XEN) Interrupt remapping enabled (XEN) Enabling APIC mode. Using 2 I/O APICs (XEN) ENABLING IO-APIC IRQs (XEN) -> Using new ACK method (XEN) ..TIMER: vector=3D0xF0 apic1=3D0 pin1=3D2 apic2=3D-1 pin2=3D-1 (XEN) Wallclock source: CMOS RTC (XEN) Defaulting to alternative key handling; send 'A' to switch to normal = mode. (XEN) Allocated console ring of 128 KiB. (XEN) HVM: ASIDs enabled (XEN) SVM: Supported advanced features: (XEN) - Nested Page Tables (NPT) (XEN) - Last Branch Record (LBR) Virtualisation (XEN) - Next-RIP Saved on #VMEXIT (XEN) - VMCB Clean Bits (XEN) - TLB flush by ASID (XEN) - DecodeAssists (XEN) - Virtual VMLOAD/VMSAVE (XEN) - Virtual GIF (XEN) - Pause-Intercept Filter (XEN) - Pause-Intercept Filter Threshold (XEN) - TSC Rate MSR (XEN) - NPT Supervisor Shadow Stack (XEN) - MSR_SPEC_CTRL virtualisation (XEN) HVM: SVM enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB, 1GB (XEN) Brought up 32 CPUs (XEN) Scheduling granularity: cpu, 1 CPU per sched-resource (XEN) Initializing Credit2 scheduler (XEN) load_precision_shift: 18 (XEN) load_window_shift: 30 (XEN) underload_balance_tolerance: 0 (XEN) overload_balance_tolerance: -3 (XEN) runqueues arrangement: socket (XEN) cap enforcement granularity: 10ms (XEN) load tracking window length 1073741824 ns (XEN) Adding cpu 0 to runqueue 0 (XEN) First cpu on runqueue, activating (XEN) Adding cpu 1 to runqueue 0 (XEN) Adding cpu 2 to runqueue 0 (XEN) Adding cpu 3 to runqueue 0 (XEN) Adding cpu 4 to runqueue 0 (XEN) Adding cpu 5 to runqueue 0 (XEN) Adding cpu 6 to runqueue 0 (XEN) Adding cpu 7 to runqueue 0 (XEN) Adding cpu 8 to runqueue 0 (XEN) Adding cpu 9 to runqueue 0 (XEN) Adding cpu 10 to runqueue 0 (XEN) Adding cpu 11 to runqueue 0 (XEN) Adding cpu 12 to runqueue 0 (XEN) Adding cpu 13 to runqueue 0 (XEN) Adding cpu 14 to runqueue 0 (XEN) Adding cpu 15 to runqueue 0 (XEN) Adding cpu 16 to runqueue 1 (XEN) First cpu on runqueue, activating (XEN) Adding cpu 17 to runqueue 1 (XEN) Adding cpu 18 to runqueue 1 (XEN) Adding cpu 19 to runqueue 1 (XEN) Adding cpu 20 to runqueue 1 (XEN) Adding cpu 21 to runqueue 1 (XEN) Adding cpu 22 to runqueue 1 (XEN) Adding cpu 23 to runqueue 1 (XEN) Adding cpu 24 to runqueue 1 (XEN) Adding cpu 25 to runqueue 1 (XEN) Adding cpu 26 to runqueue 1 (XEN) Adding cpu 27 to runqueue 1 (XEN) Adding cpu 28 to runqueue 1 (XEN) Adding cpu 29 to runqueue 1 (XEN) Adding cpu 30 to runqueue 1 (XEN) Adding cpu 31 to runqueue 1 (XEN) mcheck_poll: Machine check polling timer started. (XEN) NX (Execute Disable) protection active (XEN) d0 has maximum 6656 PIRQs (XEN) *** Building a PVH Dom0 *** (XEN) Initial low memory virq threshold set at 0x4000 pages. (XEN) Scrubbing Free RAM in background (XEN) Std. Loglevel: Errors, warnings and info (XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings) (XEN) Xen is relinquishing VGA console. (XEN) *** Serial input to DOM0 (type 'CTRL-a' three times to switch input) (XEN) Freed 724kB init memory Poking KASLR using RDRAND RDTSC... [ 0.622790] Oops: divide error: 0000 [#1] SMP NOPTI [ 0.622790] fbcon: Taking over console [ 0.623479] CPU: 4 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.19.10-200= =2Efc43.x86_64 #1 PREEMPT(lazy)=20 [ 0.623479] Hardware name: To Be Filled By O.E.M. B450M Steel Legend/B45= 0M Steel Legend, BIOS P10.43 06/25/2025 [ 0.623479] RIP: 0010:amd_smn_init+0x1ea/0x280 [ 0.623479] Code: c7 c7 13 de 16 83 e8 85 7c 44 fd eb 6f 48 89 df e8 0b = 18 ca fc 48 89 c3 48 85 c0 0f 84 5b ff ff ff 44 89 e8 31 d2 45 8d 7d 01 <66= > f7 f5 66 85 d2 75 42 66 90 eb 2c 41 0f b7 ce 48 8d b3 c8 00 00 [ 0.623479] RSP: 0018:ffffc9000004fe28 EFLAGS: 00010246 [ 0.623479] RAX: 0000000000000000 RBX: ffff888103ee6000 RCX: 00000000000= 00005 [ 0.623479] RDX: 0000000000000000 RSI: ffff888103ee6000 RDI: 00000000000= 00000 [ 0.623479] RBP: 0000000000000000 R08: 0000000000000282 R09: ffff8881015= cbf70 [ 0.623479] R10: ffffc9000004fe28 R11: ffffffff84a4c880 R12: 00000000000= 00002 [ 0.623479] R13: 0000000000000000 R14: 0000000000000000 R15: 00000000000= 00001 [ 0.623479] FS: 0000000000000000(0000) GS:ffff88898e5ef000(0000) knlGS:= 0000000000000000 [ 0.623479] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 0.623479] CR2: 0000000000000000 CR3: 0000000003a2e000 CR4: 00000000007= 50ef0 [ 0.623479] PKRU: 55555554 [ 0.623479] Call Trace: [ 0.623479] [ 0.623479] ? __pfx_amd_smn_init+0x10/0x10 [ 0.623479] do_one_initcall+0x5b/0x300 [ 0.623479] do_initcalls+0x148/0x170 [ 0.623479] kernel_init_freeable+0xf9/0x140 [ 0.623479] ? __pfx_kernel_init+0x10/0x10 [ 0.623479] kernel_init+0x1a/0x140 [ 0.623479] ret_from_fork+0x130/0x1a0 [ 0.623479] ? __pfx_kernel_init+0x10/0x10 [ 0.623479] ret_from_fork_asm+0x1a/0x30 [ 0.623479] [ 0.623479] Modules linked in: [ 0.623480] ---[ end trace 0000000000000000 ]--- [ 0.623499] RIP: 0010:amd_smn_init+0x1ea/0x280 [ 0.623508] Code: c7 c7 13 de 16 83 e8 85 7c 44 fd eb 6f 48 89 df e8 0b = 18 ca fc 48 89 c3 48 85 c0 0f 84 5b ff ff ff 44 89 e8 31 d2 45 8d 7d 01 <66= > f7 f5 66 85 d2 75 42 66 90 eb 2c 41 0f b7 ce 48 8d b3 c8 00 00 [ 0.623534] RSP: 0018:ffffc9000004fe28 EFLAGS: 00010246 [ 0.623547] RAX: 0000000000000000 RBX: ffff888103ee6000 RCX: 00000000000= 00005 [ 0.623559] RDX: 0000000000000000 RSI: ffff888103ee6000 RDI: 00000000000= 00000 [ 0.623571] RBP: 0000000000000000 R08: 0000000000000282 R09: ffff8881015= cbf70 [ 0.623583] R10: ffffc9000004fe28 R11: ffffffff84a4c880 R12: 00000000000= 00002 [ 0.623595] R13: 0000000000000000 R14: 0000000000000000 R15: 00000000000= 00001 [ 0.623608] FS: 0000000000000000(0000) GS:ffff88898e5ef000(0000) knlGS:= 0000000000000000 [ 0.623623] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 0.623634] CR2: 0000000000000000 CR3: 0000000003a2e000 CR4: 00000000007= 50ef0 [ 0.623646] PKRU: 55555554 [ 0.623653] Kernel panic - not syncing: Attempted to kill init! exitcode= =3D0x0000000b (XEN) Hardware Dom0 crashed: rebooting machine in 5 seconds. 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AJvYcCUqoALe9wpj6Ik9Ir8y2P8bm8Dj5QAJPNK9CdP6pLUUMMij5LFvNU/Rj9M7naXZn6RbOVKBF+uSHkk=@lists.xenproject.org X-Gm-Message-State: AOJu0YwnN8qGENo6Ih7MY14N0/ELJfSqoTU4sHWeTNINkoVOjntvJ8uF IIpJNaeeB6oGWGXJE4JO2+Yk9YDj/aI2fvIRdE10ARaob4MwnrSPtK6u X-Gm-Gg: AeBDievH9D9JD9muxXDjpCm0ybtkRJiVs8WdbEq67Fxp5EQNLcWviklstk6idF/72LL RHmaGvWCV9nMZYoceuJaNj6L2bDp/87Z+KW5Q87TChq8NOAt7HehvVXrTiKGzk25MYuGdAkUKHZ AN2yyVpl1LKtYwhAALAwgZimpn7UjQyklB+R+jrzcGMZewCWTEu537nT+irjIc+f849NBGbgqNw XfCm8yWV3Tunu4jvTnMecaOm4Vn7+aKXcmo7VZBjXH35/Bwm42/31yIxzsb/+URk8yR6EbU7qvM cZlr4HTISzqrh6G4esYdKm67jvl5T7Hxi9QBwbXTPVSAu6PvAN7kwi8PcpHWO1omqiNvCqWL8Li hjDzT1UzaCWAgCaPjQQUJmx6DaXDFJsDDIVp9FImq8qEoNFiXs4yOIkam/iQNAcdIJeOGESg1ZY 2m4FV0nlgFzsXE8AixHybs63T6iQQjYAJsBK8Kvt46W789Bhoglq5iKqJ7c1xP7fbHDKYETjv0L SsLt8G8aQnyjQ== X-Received: by 2002:a17:907:3f90:b0:b9b:207c:f7af with SMTP id a640c23a62f3a-b9c679f3b83mr807071666b.42.1775552063361; Tue, 07 Apr 2026 01:54:23 -0700 (PDT) Message-ID: <538d86ca-2a87-4d22-bdd6-ecee3f89cead@gmail.com> Date: Tue, 7 Apr 2026 10:54:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/11] xen/riscv: add definition of guest RAM banks To: Jan Beulich Cc: Romain Caritey , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <8278256f3d270b456d19cb9891b89b88a46548a5.1774281309.git.oleksii.kurochko@gmail.com> <1a3a316e-f0ea-4514-95d6-9813d6d5ca76@suse.com> <691be850-9145-4bbf-a897-d10a0193b730@gmail.com> <2bae9e12-8f71-4ff0-b077-bfb4215e5e14@gmail.com> <0e37083a-42ab-4c99-83fc-b77f519394b9@suse.com> <912263a2-8dff-414e-bea4-64428ce2ec36@gmail.com> <4a1f7cfb-df74-4083-a681-f79911da10e1@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <4a1f7cfb-df74-4083-a681-f79911da10e1@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775552064-33F3651B-3E6D2920/10/73395122804 X-purgate-type: spam X-purgate-size: 3719 On 4/7/26 8:23 AM, Jan Beulich wrote: > On 06.04.2026 17:43, Oleksii Kurochko wrote: >> >> >> On 4/1/26 5:10 PM, Jan Beulich wrote: >>> On 01.04.2026 16:53, Oleksii Kurochko wrote: >>>> >>>> >>>> On 4/1/26 4:22 PM, Jan Beulich wrote: >>>>> On 01.04.2026 15:57, Oleksii Kurochko wrote: >>>>>> On 4/1/26 8:17 AM, Jan Beulich wrote: >>>>>>> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>>>>>>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>>>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>>>>>>> so introduce macros to describe guest RAM banks. >>>>>>>>>> >>>>>>>>>> The reason for 2 banks is that there is typically always a use case for >>>>>>>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>>>>>>> there are other things under 4 GB it can conflict with (interrupt >>>>>>>>>> controller, PCI BARs, etc.). >>>>>>>>> Fixed layouts like the one you suggest come with (potentially severe) >>>>>>>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>>>>>>> for non-64-bit BARs? >>>>>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>>>>> before RAM start is enough for MMIO space. >>>>>>> Likely in the common case. Board designers aren't constrained by this, >>>>>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>>>>> >>>>>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>>>>> could you chime in here, please? >>>>>>> >>>>>>>> Answering your question it will be an issue or it will also use some >>>>>>>> space before banks, no? >>>>>>> I fear I don't understand what you're trying to tell me. >>>>>> I meant that there is also some space between banks and pretty big which >>>>>> could be used for MMIO which could be used for non-64-bit BARs. >>>>> I don't follow: Bank 0 extends to 4G. There's no space above it, below >>>>> bank 1, which could be use for non-64-bit BARs. >>>> >>>> So we have two banks: >>>> bank[0] -> [0x80000000, 0x100000000) >>>> bank[1] -> [0x0200000000, 10000000000) >>>> >>>> So i think we have some space between them [0x100000000, 0x0200000000) >>>> -> 4gb to be used for non-64-bit BARs. >>> >>> But a non-64-bit BAR need to be assigned an address below 0x100000000? >> >> Right, I had in mind that RV32 uses for guest Sv32x4 which could >> translate 34-bit GPA into 34-bit MPA and automatically applied that to >> 32-bit BAR... >> >> I can keep first 4gb for MMIO purpose and start bank[0] at 4gb as 34 MPA >> address space is more then enough to cover reserved 2gb of bank[0] after >> 4gb. > > Yet having no memory below 4G won't work for guests wanting to run in bare > mode? Don't guests even start up in bare mode (and hence 32-bit ones need > to have some of their memory below 4G in all cases)? I thought about such use case but decided that no one will want to run guest in bare mode and that is why we have: if ( max_gstage_mode.mode == HGATP_MODE_OFF ) panic("Xen expects that G-stage won't be Bare mode\n"); Probably it is wrong assumption and we really want to support Bare mode for guest too. Let me know if I have to drop the panic above... Then it isn't clear what will be the best layout for the current limitation that guest RAM should be compile-time constant for dom0less solution. It looks to me that giving 2gb reserved for MMIO and 2gb for guest RAM is fair enough. As an option 3gb for MMIO and 1gb for guest RAM will be enough as only Bare model will have such small amount of RAM, for other modes part of bank[1] could be used. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:05:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:05:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274552.1560643 (Exim 4.92) (envelope-from ) id 1wA2NQ-0003Gw-5q; Tue, 07 Apr 2026 09:05:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274552.1560643; Tue, 07 Apr 2026 09:05:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA2NQ-0003Gp-33; Tue, 07 Apr 2026 09:05:40 +0000 Received: by outflank-mailman (input) for mailman id 1274552; Tue, 07 Apr 2026 09:05:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA2NO-0003GT-Ih for xen-devel@lists.xen.org; Tue, 07 Apr 2026 09:05:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA2NN-000w4h-Gk for xen-devel@lists.xen.org; Tue, 07 Apr 2026 11:05:37 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4c8de-5cb7-0a2a0a5109dd-0a2a4508ccd2-16 for ; Tue, 07 Apr 2026 11:05:37 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4c8e1-fab6-0a2a45080019-d1558031d46e-3 for ; Tue, 07 Apr 2026 11:05:37 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so43541705e9.0 for ; Tue, 07 Apr 2026 02:05:37 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 07 Apr 2026 02:05:36 -0700 (PDT) Message-ID: <1f1cfdeb-adbd-420d-a187-d0007fcad123@suse.com> Date: Tue, 7 Apr 2026 11:05:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Xen on Zen 3 To: =?UTF-8?B?TWF0ecOhxaEgS3JvdXBh?= References: <5490687.niJfEyVGOH@rivendell.hailstone.cz> Content-Language: en-US Cc: xen-devel@lists.xen.org From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5490687.niJfEyVGOH@rivendell.hailstone.cz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775552737-F7149497-34A61169/0/0 X-purgate-type: clean X-purgate-size: 2132 On 07.04.2026 10:08, Matyáš Kroupa wrote: > Hi, > I am trying to run Xen on a bare metal with Zen 3 microarchitecture (to be > specific Ryzen 9 5950X). I am using Fedora 43 as Dom0 in PVH mode. However, the > Linux kernel crashes early in the boot causing Xen to reboot. I am not exactly > sure if Linux or Xen is the problematic part. The kernel boots fine without > Xen. Before Ryzen 9 I had Ryzen 5 3400G (Zen+) which booted even with Xen. > > The Xen is a backported from Fedora 44 (not yet released) because I need Xen > 4.21 features, mainly ReBAR support for the Arc B50 GPU. Package specification > with build commands can be found on https://src.fedoraproject.org/rpms/xen/ > blob/f44/f/xen.spec. There are also downstream patches and configuration. > > I have set up a serial link, so I have some logs. They are in the attachment. > I have used gdb to translate the binary offset to source code line. The > problematic line is https://elixir.bootlin.com/linux/v6.19.10/source/arch/x86/ > kernel/amd_node.c#L296. It seems that linux is detecting zero PCI roots on > non-zero number of nodes causing division by zero. Not exactly, there is an earlier exit from the function when num_roots is 0. If that line is the problem one, then presumably num_roots < num_nodes, thus yielding roots_per_node as 0. Sadly you didn't enable enough verbosity for pr_debug("Found %d AMD root devices\n", num_roots); to actually leave a trace in the log. I'd guess the value to be 1, but there being multiple nodes at the same time. You may want to instrument the function a little more to be certain. Seeing static inline u16 amd_num_nodes(void) { return topology_amd_nodes_per_pkg() * topology_max_packages(); } I'm not overly surprised of problems, though. Our topology representation still has a lot of work to do before the data can be reliably used. For your immediate purpose you may want to change the "!num_roots" check into a "num_roots < num_nodes" one (on the assumption that num_nodes can't be 0). Whether that's acceptable upstream I don't know, of course. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <538d86ca-2a87-4d22-bdd6-ecee3f89cead@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775552983-1039741E-746A4110/0/0 X-purgate-type: clean X-purgate-size: 4245 On 07.04.2026 10:54, Oleksii Kurochko wrote: > > > On 4/7/26 8:23 AM, Jan Beulich wrote: >> On 06.04.2026 17:43, Oleksii Kurochko wrote: >>> >>> >>> On 4/1/26 5:10 PM, Jan Beulich wrote: >>>> On 01.04.2026 16:53, Oleksii Kurochko wrote: >>>>> >>>>> >>>>> On 4/1/26 4:22 PM, Jan Beulich wrote: >>>>>> On 01.04.2026 15:57, Oleksii Kurochko wrote: >>>>>>> On 4/1/26 8:17 AM, Jan Beulich wrote: >>>>>>>> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>>>>>>>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>>>>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>>>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>>>>>>>> so introduce macros to describe guest RAM banks. >>>>>>>>>>> >>>>>>>>>>> The reason for 2 banks is that there is typically always a use case for >>>>>>>>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>>>>>>>> there are other things under 4 GB it can conflict with (interrupt >>>>>>>>>>> controller, PCI BARs, etc.). >>>>>>>>>> Fixed layouts like the one you suggest come with (potentially severe) >>>>>>>>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>>>>>>>> for non-64-bit BARs? >>>>>>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>>>>>> before RAM start is enough for MMIO space. >>>>>>>> Likely in the common case. Board designers aren't constrained by this, >>>>>>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>>>>>> >>>>>>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>>>>>> could you chime in here, please? >>>>>>>> >>>>>>>>> Answering your question it will be an issue or it will also use some >>>>>>>>> space before banks, no? >>>>>>>> I fear I don't understand what you're trying to tell me. >>>>>>> I meant that there is also some space between banks and pretty big which >>>>>>> could be used for MMIO which could be used for non-64-bit BARs. >>>>>> I don't follow: Bank 0 extends to 4G. There's no space above it, below >>>>>> bank 1, which could be use for non-64-bit BARs. >>>>> >>>>> So we have two banks: >>>>> bank[0] -> [0x80000000, 0x100000000) >>>>> bank[1] -> [0x0200000000, 10000000000) >>>>> >>>>> So i think we have some space between them [0x100000000, 0x0200000000) >>>>> -> 4gb to be used for non-64-bit BARs. >>>> >>>> But a non-64-bit BAR need to be assigned an address below 0x100000000? >>> >>> Right, I had in mind that RV32 uses for guest Sv32x4 which could >>> translate 34-bit GPA into 34-bit MPA and automatically applied that to >>> 32-bit BAR... >>> >>> I can keep first 4gb for MMIO purpose and start bank[0] at 4gb as 34 MPA >>> address space is more then enough to cover reserved 2gb of bank[0] after >>> 4gb. >> >> Yet having no memory below 4G won't work for guests wanting to run in bare >> mode? Don't guests even start up in bare mode (and hence 32-bit ones need >> to have some of their memory below 4G in all cases)? > > I thought about such use case but decided that no one will want to run > guest in bare mode and that is why we have: > if ( max_gstage_mode.mode == HGATP_MODE_OFF ) > panic("Xen expects that G-stage won't be Bare mode\n"); How does HGATP matter here? We're talking of guest physical address space layout, and hence it's SATP which matters. > Probably it is wrong assumption and we really want to support Bare mode > for guest too. Let me know if I have to drop the panic above... > > Then it isn't clear what will be the best layout for the current > limitation that guest RAM should be compile-time constant for dom0less > solution. > It looks to me that giving 2gb reserved for MMIO and 2gb for guest RAM > is fair enough. > As an option 3gb for MMIO and 1gb for guest RAM will be enough as only > Bare model will have such small amount of RAM, for other modes part of > bank[1] could be used. All of which only supports my take that you don't want to make guest memory layout an ABI property. Using compile-time determined banks for now may be okay(ish), but in the longer run things will want determining dynamically (or specifying via per-guest config). Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:19:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:19:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274571.1560661 (Exim 4.92) (envelope-from ) id 1wA2b0-0005h6-Kw; Tue, 07 Apr 2026 09:19:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274571.1560661; Tue, 07 Apr 2026 09:19:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA2b0-0005gz-HG; Tue, 07 Apr 2026 09:19:42 +0000 Received: by outflank-mailman (input) for mailman id 1274571; Tue, 07 Apr 2026 09:19:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wA2az-0005gd-Do for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:19:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA2av-000zZj-O5 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:19:37 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4cc24-bab6-0a2a0a5309dd-0a2a4503ac08-26 for ; Tue, 07 Apr 2026 11:19:37 +0200 Received: from [209.85.218.48] (helo=mail-ej1-f48.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4cc29-02b3-0a2a45030019-d155da30e904-3 for ; Tue, 07 Apr 2026 11:19:37 +0200 Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-b9c9d03524cso354524566b.3 for ; Tue, 07 Apr 2026 02:19:37 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775553577-C9337C9A-48BC6800/10/73395122804 X-purgate-type: spam X-purgate-size: 4513 On 4/7/26 11:09 AM, Jan Beulich wrote: > On 07.04.2026 10:54, Oleksii Kurochko wrote: >> >> >> On 4/7/26 8:23 AM, Jan Beulich wrote: >>> On 06.04.2026 17:43, Oleksii Kurochko wrote: >>>> >>>> >>>> On 4/1/26 5:10 PM, Jan Beulich wrote: >>>>> On 01.04.2026 16:53, Oleksii Kurochko wrote: >>>>>> >>>>>> >>>>>> On 4/1/26 4:22 PM, Jan Beulich wrote: >>>>>>> On 01.04.2026 15:57, Oleksii Kurochko wrote: >>>>>>>> On 4/1/26 8:17 AM, Jan Beulich wrote: >>>>>>>>> On 31.03.2026 18:14, Oleksii Kurochko wrote: >>>>>>>>>> On 3/30/26 5:51 PM, Jan Beulich wrote: >>>>>>>>>>> On 23.03.2026 17:29, Oleksii Kurochko wrote: >>>>>>>>>>>> The dom0less solution uses defined RAM banks as compile-time constants, >>>>>>>>>>>> so introduce macros to describe guest RAM banks. >>>>>>>>>>>> >>>>>>>>>>>> The reason for 2 banks is that there is typically always a use case for >>>>>>>>>>>> low memory under 4 GB, but the bank under 4 GB ends up being small because >>>>>>>>>>>> there are other things under 4 GB it can conflict with (interrupt >>>>>>>>>>>> controller, PCI BARs, etc.). >>>>>>>>>>> Fixed layouts like the one you suggest come with (potentially severe) >>>>>>>>>>> downsides. For example, what if more than 2Gb of MMIO space are needed >>>>>>>>>>> for non-64-bit BARs? >>>>>>>>>> It looks where usually RAM on RISC-V boards start, so I expect that 2gb >>>>>>>>>> before RAM start is enough for MMIO space. >>>>>>>>> Likely in the common case. Board designers aren't constrained by this, >>>>>>>>> though (aiui). Whereas you set in stone a single, fixed layout. >>>>>>>>> >>>>>>>>> Arm maintainers - since a similar fixed layout is used there iirc, >>>>>>>>> could you chime in here, please? >>>>>>>>> >>>>>>>>>> Answering your question it will be an issue or it will also use some >>>>>>>>>> space before banks, no? >>>>>>>>> I fear I don't understand what you're trying to tell me. >>>>>>>> I meant that there is also some space between banks and pretty big which >>>>>>>> could be used for MMIO which could be used for non-64-bit BARs. >>>>>>> I don't follow: Bank 0 extends to 4G. There's no space above it, below >>>>>>> bank 1, which could be use for non-64-bit BARs. >>>>>> >>>>>> So we have two banks: >>>>>> bank[0] -> [0x80000000, 0x100000000) >>>>>> bank[1] -> [0x0200000000, 10000000000) >>>>>> >>>>>> So i think we have some space between them [0x100000000, 0x0200000000) >>>>>> -> 4gb to be used for non-64-bit BARs. >>>>> >>>>> But a non-64-bit BAR need to be assigned an address below 0x100000000? >>>> >>>> Right, I had in mind that RV32 uses for guest Sv32x4 which could >>>> translate 34-bit GPA into 34-bit MPA and automatically applied that to >>>> 32-bit BAR... >>>> >>>> I can keep first 4gb for MMIO purpose and start bank[0] at 4gb as 34 MPA >>>> address space is more then enough to cover reserved 2gb of bank[0] after >>>> 4gb. >>> >>> Yet having no memory below 4G won't work for guests wanting to run in bare >>> mode? Don't guests even start up in bare mode (and hence 32-bit ones need >>> to have some of their memory below 4G in all cases)? >> >> I thought about such use case but decided that no one will want to run >> guest in bare mode and that is why we have: >> if ( max_gstage_mode.mode == HGATP_MODE_OFF ) >> panic("Xen expects that G-stage won't be Bare mode\n"); > > How does HGATP matter here? We're talking of guest physical address space > layout, and hence it's SATP which matters. oh, right, it is hgatp. > >> Probably it is wrong assumption and we really want to support Bare mode >> for guest too. Let me know if I have to drop the panic above... >> >> Then it isn't clear what will be the best layout for the current >> limitation that guest RAM should be compile-time constant for dom0less >> solution. >> It looks to me that giving 2gb reserved for MMIO and 2gb for guest RAM >> is fair enough. >> As an option 3gb for MMIO and 1gb for guest RAM will be enough as only >> Bare model will have such small amount of RAM, for other modes part of >> bank[1] could be used. > > All of which only supports my take that you don't want to make guest > memory layout an ABI property. Using compile-time determined banks for > now may be okay(ish), but in the longer run things will want determining > dynamically (or specifying via per-guest config). I've already planned to move it to some arch specific header instead of ABI header. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:23:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:23:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274580.1560669 (Exim 4.92) (envelope-from ) id 1wA2ec-0007A2-38; Tue, 07 Apr 2026 09:23:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274580.1560669; Tue, 07 Apr 2026 09:23:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA2ec-00079v-0O; Tue, 07 Apr 2026 09:23:26 +0000 Received: by outflank-mailman (input) for mailman id 1274580; Tue, 07 Apr 2026 09:23:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA2ea-00079p-IV for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:23:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA2eZ-00BNtW-P1 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:23:23 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4ccff-2eae-0a2a0a5409dd-0a2a45069cee-16 for ; Tue, 07 Apr 2026 11:23:23 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d4cd0a-0df0-0a2a45060019-d98c6eaca682-1 for ; Tue, 07 Apr 2026 11:23:22 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FCE71A00; Tue, 7 Apr 2026 02:23:16 -0700 (PDT) Received: from [10.43.20.57] (e126510-lin.lund.arm.com [10.43.20.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 706433F7D8; Tue, 7 Apr 2026 02:23:20 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775553801; bh=IkPnuzV+3P8ZkIbAwdqeXO4+v1PveLJudtk7SO76pNw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=VoPGsk5Ha2+Uko33aogP9uF/8fLqKBwHXCVhw0E2i9dMFGXgz2Ts4vs45Y8mLSzKe 6T/4OP+86ckjYH97YfD5JGR+fT+hiG4YahKMJ0V2/IRh1ZGs96/cT0u51D1pO3PJQ/ VO/XNUffoZ+p2Z21RyYRRJtdOgXpmemOY0Ls2Xv8= Message-ID: <5d068304-837d-4aef-b8a7-87c91ccf96b4@arm.com> Date: Tue, 7 Apr 2026 11:23:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: kernel BUG around vmap/vfree - xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Cc: Andrew Cooper , xen-devel , Boris Ostrovsky References: From: Kevin Brodsky Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1775553803-642483D8-9AA2B5E3/0/0 X-purgate-type: clean X-purgate-size: 10441 On 05/04/2026 11:41, Marek Marczykowski-G=C3=B3recki wrote: > On Thu, Feb 26, 2026 at 02:41:12PM +0100, J=C3=BCrgen Gro=C3=9F wrote: >> On 26.02.26 14:27, Andrew Cooper wrote: >>> On 26/02/2026 1:17 pm, Marek Marczykowski-G=C3=B3recki wrote: >>>> Hi, >>>> >>>> When testing Linux 7.0-rc1 in PV dom0, I hit the following panic >>>> sometimes: >>>> >>>> [ 436.849614] ------------[ cut here ]------------ >>>> [ 436.849669] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:7= 8! >>>> [ 436.849693] Oops: invalid opcode: 0000 [#1] SMP NOPTI >>>> [ 436.849710] CPU: 3 UID: 0 PID: 4021 Comm: kworker/u25:1 Not taint= ed 7.0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) >>>> [ 436.849729] Hardware name: Star Labs StarBook/StarBook, BIOS 8.97= 10/03/2023 >>>> [ 436.849743] Workqueue: i915_flip intel_atomic_commit_work [i915] >>>> [ 436.850226] RIP: e030:xen_enter_lazy_mmu+0x24/0x30 >>>> [ 436.850245] Code: 90 90 90 90 90 90 f3 0f 1e fa 0f 1f 44 00 00 65= 8b 05 b8 e5 02 03 85 c0 75 10 65 c7 05 a9 e5 02 03 01 00 00 00 c3 cc cc = cc cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90= >>>> [ 436.850270] RSP: e02b:ffffc90045727a68 EFLAGS: 00010202 >>>> [ 436.850283] RAX: 0000000000000001 RBX: ffff8881042fa6d0 RCX: 000f= ffffffe00000 >>>> [ 436.850296] RDX: 0000000000000001 RSI: ffff88810a5a2980 RDI: 0000= 000000000000 >>>> [ 436.850308] RBP: ffffc90049eda000 R08: ffffc90049edc000 R09: ffff= c90049edc000 >>>> [ 436.850320] R10: ffffc90049edc000 R11: ffffc90049edbfff R12: ffff= c90049edc000 >>>> [ 436.850332] R13: ffffc90045727bb0 R14: ffffc90045727b28 R15: 8000= 00000000006b >>>> [ 436.850356] FS: 0000000000000000(0000) GS:ffff888201e6e000(0000)= knlGS:0000000000000000 >>>> [ 436.850371] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 >>>> [ 436.850383] CR2: 00006543dbade250 CR3: 0000000115ef1000 CR4: 0000= 000000050660 >>>> [ 436.850401] Call Trace: >>>> [ 436.850410] >>>> [ 436.850420] vmap_pages_pud_range+0x47c/0x530 >>>> [ 436.850439] vmap_small_pages_range_noflush+0x1f1/0x2b0 >>>> [ 436.850451] ? __get_vm_area_node+0x10a/0x170 >>>> [ 436.850465] vmap+0x79/0xd0 >>>> [ 436.850476] i915_gem_object_map_page+0x13b/0x210 [i915] >>>> [ 436.850812] i915_gem_object_pin_map+0x1e2/0x210 [i915] >>>> [ 436.851123] i915_gem_object_pin_map_unlocked+0x2d/0xa0 [i915] >>>> [ 436.851424] intel_dsb_buffer_create+0xed/0x1a0 [i915] >>>> [ 436.851778] intel_dsb_prepare+0xca/0x1a0 [i915] >>>> [ 436.852110] intel_atomic_dsb_finish+0x92/0x350 [i915] >>>> [ 436.852456] intel_atomic_commit_tail+0x326/0xd40 [i915] >>>> [ 436.852769] process_one_work+0x18d/0x380 >>>> [ 436.852779] worker_thread+0x196/0x300 >>>> [ 436.852787] ? __pfx_worker_thread+0x10/0x10 >>>> [ 436.852796] kthread+0xe3/0x120 >>>> [ 436.852805] ? __pfx_kthread+0x10/0x10 >>>> [ 436.852815] ret_from_fork+0x19e/0x260 >>>> [ 436.852824] ? __pfx_kthread+0x10/0x10 >>>> [ 436.852832] ret_from_fork_asm+0x1a/0x30 >>>> [ 436.852842] >>>> [ 436.852847] Modules linked in: snd_seq_dummy snd_hrtimer snd_hda_= codec_intelhdmi snd_hda_codec_hdmi snd_hda_codec_alc269 snd_hda_codec_rea= ltek_lib snd_hda_scodec_component snd_hda_codec_generic snd_hda_intel snd= _sof_pci_intel_tgl snd_sof_pci_intel_cnl snd_sof_intel_hda_generic soundw= ire_intel snd_sof_intel_hda_sdw_bpt snd_sof_intel_hda_common snd_soc_hdac= _hda snd_sof_intel_hda_mlink snd_sof_intel_hda soundwire_cadence snd_sof_= pci snd_sof_xtensa_dsp snd_sof snd_sof_utils snd_soc_acpi_intel_match snd= _soc_acpi_intel_sdca_quirks soundwire_generic_allocation snd_soc_sdw_util= s snd_soc_acpi crc8 intel_rapl_msr soundwire_bus intel_rapl_common snd_so= c_sdca snd_soc_avs snd_soc_hda_codec snd_hda_ext_core snd_hda_codec vfat = intel_uncore_frequency_common fat snd_hda_core snd_intel_dspcfg snd_intel= _sdw_acpi snd_hwdep intel_powerclamp snd_soc_core iwlwifi snd_compress sp= i_nor iTCO_wdt ac97_bus intel_pmc_bxt ee1004 mtd snd_pcm_dmaengine snd_se= q cfg80211 snd_seq_device pcspkr spi_intel_pci snd_pcm rfkill spi_intel s= nd_timer snd >>>> [ 436.852939] i2c_i801 soundcore i2c_smbus idma64 intel_pmc_core p= mt_telemetry pmt_discovery pmt_class intel_hid intel_pmc_ssram_telemetry = intel_scu_pltdrv sparse_keymap joydev loop fuse xenfs nfnetlink vsock_loo= pback vmw_vsock_virtio_transport_common vmw_vsock_vmci_transport vsock zr= am vmw_vmci lz4hc_compress lz4_compress dm_thin_pool dm_persistent_data d= m_bio_prison dm_crypt xe drm_ttm_helper drm_suballoc_helper gpu_sched drm= _gpuvm drm_exec drm_gpusvm_helper i915 i2c_algo_bit drm_buddy hid_multito= uch i2c_hid_acpi ghash_clmulni_intel video nvme wmi ttm i2c_hid nvme_core= nvme_keyring drm_display_helper nvme_auth xhci_pci pinctrl_tigerlake thu= nderbolt hkdf cec xhci_hcd intel_vsec serio_raw xen_acpi_processor xen_pr= ivcmd xen_pciback xen_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_dh_= rdac scsi_dh_emc scsi_dh_alua uinput i2c_dev >>>> [ 436.853183] ---[ end trace 0000000000000000 ]--- >>>> >>>> or this: >>>> >>>> [ 548.736884] ------------[ cut here ]------------ >>>> [ 548.736907] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:8= 5! >>>> [ 548.736923] Oops: invalid opcode: 0000 [#1] SMP NOPTI >>>> [ 548.736935] CPU: 0 UID: 0 PID: 206 Comm: kworker/0:2 Not tainted = 7.0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) >>>> [ 548.736949] Hardware name: LENOVO 2347A45/2347A45, BIOS CBET4000 = Nitrokey-v0.2.0-2608-ga649597 01/01/1970 >>>> [ 548.736962] Workqueue: events delayed_vfree_work >>>> [ 548.736976] RIP: e030:xen_leave_lazy_mmu+0x44/0x50 >>>> [ 548.736989] Code: 02 03 83 f8 01 75 23 65 c7 05 6c e4 02 03 00 00= 00 00 65 ff 0d 7d b8 02 03 74 05 c3 cc cc cc cc e8 61 5d fd ff c3 cc cc = cc cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90= >>>> [ 548.737010] RSP: e02b:ffffc90040607cf0 EFLAGS: 00010297 >>>> [ 548.737018] RAX: 0000000000000000 RBX: ffff888164a70408 RCX: 0000= 000000000000 >>>> [ 548.737029] RDX: 0000000000000000 RSI: 000ffffffffff000 RDI: ffff= 8881069c0000 >>>> [ 548.737039] RBP: ffffc90049681000 R08: ffffc90049681000 R09: 0000= 000000000027 >>>> [ 548.737050] R10: 0000000000000027 R11: fefefefefefefeff R12: ffff= c90049681000 >>>> [ 548.737060] R13: ffff8881002fd258 R14: 0000000000000000 R15: ffff= c90040607dac >>>> [ 548.737079] FS: 0000000000000000(0000) GS:ffff8881f88ee000(0000)= knlGS:0000000000000000 >>>> [ 548.737090] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 >>>> [ 548.737099] CR2: 000055576c2e6058 CR3: 000000010d47b000 CR4: 0000= 000000050660 >>>> [ 548.737115] Call Trace: >>>> [ 548.737123] >>>> [ 548.737128] vunmap_pmd_range.isra.0+0x1f1/0x2e0 >>>> [ 548.737142] vunmap_p4d_range+0x17d/0x290 >>>> [ 548.737151] __vunmap_range_noflush+0x182/0x1d0 >>>> [ 548.737161] ? _raw_spin_unlock+0xe/0x30 >>>> [ 548.737171] remove_vm_area+0x40/0x70 >>>> [ 548.737180] vfree.part.0+0x1b/0x290 >>>> [ 548.737189] delayed_vfree_work+0x35/0x50 >>>> [ 548.737198] process_one_work+0x18d/0x380 >>>> [ 548.737207] worker_thread+0x196/0x300 >>>> [ 548.737215] ? __pfx_worker_thread+0x10/0x10 >>>> [ 548.737224] kthread+0xe3/0x120 >>>> [ 548.737233] ? __pfx_kthread+0x10/0x10 >>>> [ 548.737242] ret_from_fork+0x19e/0x260 >>>> [ 548.737250] ? __pfx_kthread+0x10/0x10 >>>> [ 548.737258] ret_from_fork_asm+0x1a/0x30 >>>> [ 548.737269] >>>> [ 548.737274] Modules linked in: vfat fat snd_seq_dummy snd_hrtimer= ath9k ath9k_common snd_hda_codec_intelhdmi snd_hda_codec_hdmi ath9k_hw s= nd_hda_codec_alc269 snd_hda_codec_realtek_lib snd_hda_scodec_component sn= d_hda_codec_generic snd_hda_intel snd_hda_codec mac80211 snd_hda_core snd= _intel_dspcfg snd_intel_sdw_acpi snd_hwdep ath snd_seq snd_seq_device snd= _ctl_led cfg80211 snd_pcm at24 thinkpad_acpi intel_rapl_msr i2c_i801 snd_= timer sparse_keymap iTCO_wdt intel_rapl_common platform_profile intel_pow= erclamp intel_pmc_bxt pcspkr i2c_smbus rfkill libarc4 snd soundcore mei_m= e e1000e mei joydev lpc_ich loop fuse xenfs nfnetlink vsock_loopback vmw_= vsock_virtio_transport_common vmw_vsock_vmci_transport vsock zram vmw_vmc= i lz4hc_compress lz4_compress dm_thin_pool dm_persistent_data dm_bio_pris= on dm_crypt i915 i2c_algo_bit drm_buddy ghash_clmulni_intel ttm sdhci_pci= drm_display_helper sdhci_uhs2 sdhci video xhci_pci cqhci wmi cec xhci_hc= d ehci_pci mmc_core ehci_hcd serio_raw xen_acpi_processor xen_privcmd xen= _pciback >>>> [ 548.737348] xen_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_= dh_rdac scsi_dh_emc scsi_dh_alua uinput i2c_dev >>>> [ 548.737469] ---[ end trace 0000000000000000 ]--- >>>> >>>> I don't have clear pattern when this happens, one was during host >>>> suspend, but the other was during "normal" test run (starting/stoppi= ng >>>> domUs and running stuff around them). Note also one of those is Inte= l >>>> and the other AMD, so it isn't really hardware specific. >>>> >>>> Slightly more details with links (especially serial0.txt in the logs= >>>> tab) at >>>> https://github.com/QubesOS/qubes-linux-kernel/pull/662#issuecomment-= 3963326188 >>>> >>>> Any idea? >>>> >>> That looks like the issue Juergen fixed with: >>> >>> https://lore.kernel.org/xen-devel/20260220123715.834848-1-jgross@suse= =2Ecom/ >> No, it doesn't. The fix is already in rc1, and the crash was quite ear= ly during >> boot (before any secondary CPUs were brought up). >> >> I guess this problem is related to the lazy_mmu_state series [1]. That may well be the case - it seems that xen_enter_lazy_mmu() is called while already in lazy MMU mode (first splat), and xen_leave_lazy_mmu() is called without being in lazy MMU mode (second splat). I expect this is something specific to Xen, which I didn't get the chance to test. Looking at the series again I don't see anything obviously wrong, but I think the riskiest change is commit 291b3abed657 ("x86/xen: use lazy_mmu_state when context-switching") - worth trying to revert it. If that doesn't help, I'd suggest bisecting the following range: 58852f24f956..291b3abed657 Sorry for the trouble! - Kevin > FWIW, the issue still happens on 7.0-rc6. > >> Juergen >> >> [1]: https://lore.kernel.org/lkml/20251215150323.2218608-1-kevin.brods= ky@arm.com/ From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:57:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:57:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274591.1560687 (Exim 4.92) (envelope-from ) id 1wA3B7-0003CR-Hr; Tue, 07 Apr 2026 09:57:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274591.1560687; Tue, 07 Apr 2026 09:57:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3B7-0003CK-EO; Tue, 07 Apr 2026 09:57:01 +0000 Received: by outflank-mailman (input) for mailman id 1274591; Tue, 07 Apr 2026 09:56:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3B5-0003CE-Rw for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:56:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3B4-00Fch6-Pk for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:56:58 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d4e6-e002-0a2a0a5209dd-0a2a450ca214-22 for ; Tue, 07 Apr 2026 11:56:58 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d4e9-f40c-0a2a450c0019-a0658308be38-3 for ; Tue, 07 Apr 2026 11:56:58 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id E4006421B5C5; Tue, 7 Apr 2026 05:56:17 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Juergen Gross , "Daniel P. Smith" Subject: [PATCH 0/5] xen: Introduce NUMA-aware claim sets for domains Date: Tue, 7 Apr 2026 10:54:25 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775555818-FFB44A3D-68112756/0/0 X-purgate-type: clean X-purgate-size: 2870 Hi all, This series extends Xen's memory claim handling to support claim sets spanning multiple NUMA nodes. Earlier review raised the concern that claims would need to evolve from a single claim into a multi-node model. Roger Pau Monné described the core requirement well: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. -- Roger Pau Monné This series implements that model. A claim set can contain multiple node-specific claims and an optional global claim for memory that may come from any NUMA node. The new domctl installs the full claim set atomically, and the allocator is updated so that claim checks and claim consumption follow the new semantics. The series has been reworked substantially in response to earlier review. Because of that, it is likely best reviewed as a fresh series rather than incrementally. Patch summary: 1. xen/mm: Refactor retiring claims in preparation for use in functional changes 2. xen/mm: Claims check: Allow free pages to cover a shortfall of claims 3. xen/mm: Optimise getting free page counts per NUMA node 4. xen/mm: Split d->outstanding_pages to global_claims & node_claims 5. xen/mm: Introduce Claim Sets for multiple NUMA nodes The design document submitted ahead of this series may also help with review. It explains the background, design rationale, and implementation details. Rendered version: https://bernhardk-xen-review.readthedocs.io/node-claims-v5/designs/claims/ Posted version: https://lists.xenproject.org/archives/html/xen-devel/2026-04/msg00108.html Many thanks to everyone who contributed to the earlier work and review, especially Alejandro Vallejo, Jan Beulich, Andrew Cooper, Roger Pau Monné, Marcus Granado, and Edwin Török. Thanks for your review. Bernhard Kaindl Bernhard Kaindl (5): xen/mm: Refactor retiring claims in preparation for functional changes xen/mm: alloc pages: Allow free pages to cover a shortfall of claims xen/mm: Optimise getting free page counts per NUMA node xen/mm: Split d->outstanding_pages to global_claims & node_claims xen/mm: Introduce Claim Sets for multiple NUMA nodes tools/include/xenctrl.h | 4 + tools/libs/ctrl/xc_domain.c | 38 +++ xen/common/domctl.c | 56 +++- xen/common/page_alloc.c | 379 ++++++++++++++++++++++++++-- xen/include/public/domctl.h | 32 +++ xen/include/public/memory.h | 9 + xen/include/xen/mm.h | 3 + xen/include/xen/sched.h | 13 +- xen/xsm/flask/hooks.c | 1 + xen/xsm/flask/policy/access_vectors | 1 + 10 files changed, 509 insertions(+), 27 deletions(-) -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:58:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:58:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274609.1560695 (Exim 4.92) (envelope-from ) id 1wA3CV-0003lu-S3; Tue, 07 Apr 2026 09:58:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274609.1560695; Tue, 07 Apr 2026 09:58:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3CV-0003ln-PD; Tue, 07 Apr 2026 09:58:27 +0000 Received: by outflank-mailman (input) for mailman id 1274609; Tue, 07 Apr 2026 09:58:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3CT-0003lT-VY for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:58:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3CT-003ivl-BJ for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:58:25 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d531-e002-0a2a0a5209dd-0a2a4504c78a-28 for ; Tue, 07 Apr 2026 11:58:25 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d540-bb33-0a2a45040019-a0658308a392-3 for ; Tue, 07 Apr 2026 11:58:25 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id D41E0421B0E1; Tue, 7 Apr 2026 05:57:44 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 1/5] xen/mm: Refactor retiring claims in preparation for functional changes Date: Tue, 7 Apr 2026 10:54:26 +0100 Message-Id: <2d450d0fe8434679b5810c0d0e11d088aa757b2f.1775505670.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1775555905-B273A51B-67D0CA99/0/0 X-purgate-type: clean X-purgate-size: 3471 Refactor retiring claims into a function to make the claims accounting model easier to follow ahead of adding functional changes. Those functional changes are NUMA claims and retiring claims when offlining pages if all those pages on the host are claimed. For these functional changes, we need to return the number of retired claims. Signed-off-by: Bernhard Kaindl --- This 1st commit of this series is shared with another series which fixes a number of bugs in reserve_offline_page(). If you could ack it to be merged independent of the review of this series, we can shave it off both series in the next review rounds of both series. History: Except from the function name change and extending it to return the number of retired pages (which is required by both series) this commit is the equivalent of commit 1 of the NUMA claims series v4, with minor changes: 1) The review comments have been applied. 2) In earlier series, I had chosen to use "releasing" and "consuming". Instead, speak of "retiring" claims (as they are no longer active), which can be used in all contexts, when using the claim for an allocation, when resetting a claim and when we've to recall claims when offlining. 2) The 2nd function made sense to be migrated to be part of the main NUMA claims commit so it is no longer a part of this commit. --- xen/common/page_alloc.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index b1edef87124f..3b0909cc3ce1 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -518,6 +518,24 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages) return d->tot_pages; } +/* Retire a portion of the global claims of a domain on global memory */ +static unsigned long claims_retire_global(struct domain *d, + unsigned long pages_to_retire) +{ + unsigned long retired; + + ASSERT(spin_is_locked(&heap_lock)); + + /* If the withdrawal is larger than the claims, don't withdraw beyond */ + retired = min(d->outstanding_pages + 0UL, pages_to_retire); + + /* Assert the invariant of outstanding_claims not going negative */ + ASSERT(retired <= outstanding_claims); + outstanding_claims -= retired; + d->outstanding_pages -= retired; + return retired; +} + int domain_set_outstanding_pages(struct domain *d, unsigned long pages) { int ret = -ENOMEM; @@ -535,8 +553,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { - outstanding_claims -= d->outstanding_pages; - d->outstanding_pages = 0; + claims_retire_global(d, d->outstanding_pages); ret = 0; goto out; } @@ -1067,11 +1084,7 @@ static struct page_info *alloc_heap_pages( * the domain being destroyed before creation is finished. Losing part * of the claim makes no difference. */ - unsigned long outstanding = min(d->outstanding_pages + 0UL, request); - - BUG_ON(outstanding > outstanding_claims); - outstanding_claims -= outstanding; - d->outstanding_pages -= outstanding; + claims_retire_global(d, request); } check_low_mem_virq(); -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:58:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:58:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274617.1560704 (Exim 4.92) (envelope-from ) id 1wA3Ch-00044L-97; Tue, 07 Apr 2026 09:58:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274617.1560704; Tue, 07 Apr 2026 09:58:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3Ch-00044E-61; Tue, 07 Apr 2026 09:58:39 +0000 Received: by outflank-mailman (input) for mailman id 1274617; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 55a5a121-8d89-4dc3-5dc3-08de948c3b97 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2026 09:58:34.8990 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +mcOphYUUJ9SPMeZ2aIjglOzRUXo3USqQaOBmAVZQPGXO/eEM8fCIMDX9TAfYIKU71FJyxiggvGvebgS7J9RSg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB8294 X-purgate-ID: tlsNG-42698a/1775555917-EF5432A1-602F276A/0/0 X-purgate-type: clean X-purgate-size: 3372 Allow for removing devices from SMMUv3. arm_smmu_deassign_dev handles most of the work by disabling ATS and zeroing STEs. Additionally, unset the dt_device_is_protected flag and free no longer needed smmu_master. Tested on QEMU with SRIOV series[1] by repeatedly enabling/disabling VFs. [1]: https://patchew.org/Xen/cover.1772806036.git.mykyta._5Fpoturai@epam.co= m/ Signed-off-by: Mykyta Poturai --- xen/drivers/passthrough/arm/smmu-v3.c | 59 +++++++++++++++++++++++++++ xen/include/xen/device_tree.h | 5 +++ 2 files changed, 64 insertions(+) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index bf153227db..b5b834a7b7 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1493,6 +1493,64 @@ static int arm_smmu_assign_dev(struct domain *d, u8 = devfn, struct device *dev, static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, struct device *dev); =20 +static int arm_smmu_remove_device(u8 devfn, struct device *dev) +{ + int ret =3D 0; + struct arm_smmu_master *master; + struct iommu_fwspec *fwspec; + + fwspec =3D dev_iommu_fwspec_get(dev); + if ( !fwspec ) + return -ENODEV; + + master =3D dev_iommu_priv_get(dev); + if ( !master ) + return -ENODEV; + +#ifdef CONFIG_HAS_PCI + if ( dev_is_pci(dev) ) + { + struct pci_dev *pdev =3D dev_to_pci(dev); + + if ( pdev->domain ) + { + ret =3D arm_smmu_deassign_dev(pdev->domain, devfn, dev); + if ( ret ) + printk(XENLOG_WARNING "Failed to deassign device %pp from SMMU\n", + &pdev->sbdf); + } + } +#endif + + if ( !dev_is_pci(dev) ) + { + if ( !dt_device_is_protected(dev_to_dt(dev)) ) + { + dev_err(dev, "Not added to SMMUv3\n"); + ret =3D -ENODEV; + goto out_free; + } + + if ( master->domain && master->domain->d ) + { + ret =3D arm_smmu_deassign_dev(master->domain->d, 0, dev); + if ( ret ) + dev_warn(dev, "Failed to deassign device from SMMU\n"); + } + dt_device_unset_protected(dev_to_dt(dev)); + } + + arm_smmu_disable_pasid(master); + + dev_info(dev, "Removed master device (SMMUv3 %s StreamIds %u)\n", + dev_name(fwspec->iommu_dev), fwspec->num_ids); + +out_free: + xfree(master); + dev_iommu_priv_set(dev, NULL); + return ret; +} + static int arm_smmu_add_device(u8 devfn, struct device *dev) { int i, ret; @@ -2867,6 +2925,7 @@ static const struct iommu_ops arm_smmu_iommu_ops =3D = { .unmap_page =3D arm_iommu_unmap_page, .dt_xlate =3D arm_smmu_dt_xlate, .add_device =3D arm_smmu_add_device, + .remove_device =3D arm_smmu_remove_device, }; =20 static __init int arm_smmu_dt_init(struct dt_device_node *dev, diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 06d7643622..1f9608cdcd 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -305,6 +305,11 @@ static inline void dt_device_set_protected(struct dt_d= evice_node *device) device->is_protected =3D true; } =20 +static inline void dt_device_unset_protected(struct dt_device_node *device= ) +{ + device->is_protected =3D false; +} + static inline bool dt_device_is_protected(const struct dt_device_node *dev= ice) { return device->is_protected; --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:59:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:59:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274644.1560714 (Exim 4.92) (envelope-from ) id 1wA3DE-0004jk-JA; Tue, 07 Apr 2026 09:59:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274644.1560714; Tue, 07 Apr 2026 09:59:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3DE-0004jd-Fh; Tue, 07 Apr 2026 09:59:12 +0000 Received: by outflank-mailman (input) for mailman id 1274644; Tue, 07 Apr 2026 09:59:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3DD-0004i6-49 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:59:11 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3DC-0065UD-G4 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:59:10 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d56a-e002-0a2a0a5209dd-0a2a450bb540-48 for ; Tue, 07 Apr 2026 11:59:10 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d56d-bca8-0a2a450b0019-a06583088bca-3 for ; Tue, 07 Apr 2026 11:59:10 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id D8A6B421B5D1; Tue, 7 Apr 2026 05:58:29 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 2/5] xen/mm: alloc pages: Allow free pages to cover a shortfall of claims Date: Tue, 7 Apr 2026 10:54:27 +0100 Message-Id: <1bd422498a1b258d3a733d12b5ca286d9d48ba58.1775505670.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775555950-EC75A2A1-07870CD3/0/0 X-purgate-type: clean X-purgate-size: 3139 When an allocation has a shortfall of claims but free, unclaimed memory can cover this shortfall, allow the allocation to proceed. In preparation for NUMA claims, refactor this check into a reusable function. This will enable the same logic to be applied for NUMA nodes. Suggested-by: Jan Beulich Signed-off-by: Bernhard Kaindl --- Changes since v4: Extracted into a dedicated patch and merged the formerly separate functions into one, as suggested by Jan Beulich. Signed-off-by: Bernhard Kaindl --- xen/common/page_alloc.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 3b0909cc3ce1..0fab1630e318 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -873,6 +873,42 @@ static void check_and_stop_scrub(struct page_info *head) } } +/* + * Allow the request when unclaimed pages suffice, or when a refcounted + * domain's outstanding claims cover the shortfall. + */ +static bool claims_permit_request(const struct domain *d, + unsigned long avail_pages, + unsigned long competing_claims, + unsigned int memflags, + unsigned long requested_pages) +{ + unsigned long unclaimed_pages; + + ASSERT(spin_is_locked(&heap_lock)); + ASSERT(avail_pages >= competing_claims); + + /* Start from the free pages not already claimed by other domains. */ + unclaimed_pages = avail_pages - competing_claims; + + /* Allow the request to proceed when unclaimed pages suffice. */ + if ( requested_pages <= unclaimed_pages ) + return true; + + /* + * If unclaimed pages are insufficient, only a refcounted domain allocation + * may use claims to cover the shortfall. + */ + if ( !d || (memflags & MEMF_no_refcount) ) + return false; + + /* + * Allow the request to proceed when combination of unclaimed pages and the + * claims held by the domain cover the shortfall for the requested_pages. + */ + return requested_pages <= unclaimed_pages + d->outstanding_pages; +} + static struct page_info *get_free_buddy(unsigned int zone_lo, unsigned int zone_hi, unsigned int order, unsigned int memflags, @@ -1017,9 +1053,8 @@ static struct page_info *alloc_heap_pages( * Claimed memory is considered unavailable unless the request * is made by a domain with sufficient unclaimed pages. */ - if ( (outstanding_claims + request > total_avail_pages) && - ((memflags & MEMF_no_refcount) || - !d || d->outstanding_pages < request) ) + if ( !claims_permit_request(d, total_avail_pages, outstanding_claims, + memflags, request) ) { spin_unlock(&heap_lock); return NULL; -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 09:59:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 09:59:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274661.1560722 (Exim 4.92) (envelope-from ) id 1wA3Dr-0005Hq-Ps; Tue, 07 Apr 2026 09:59:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274661.1560722; Tue, 07 Apr 2026 09:59:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3Dr-0005Hj-NE; Tue, 07 Apr 2026 09:59:51 +0000 Received: by outflank-mailman (input) for mailman id 1274661; Tue, 07 Apr 2026 09:59:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3Dq-0005HV-VJ for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 09:59:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3Dq-003jGU-B0 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:59:50 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d587-5cb7-0a2a0a5109dd-0a2a450a8c80-46 for ; Tue, 07 Apr 2026 11:59:50 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d595-ee98-0a2a450a0019-a0658309e398-3 for ; Tue, 07 Apr 2026 11:59:50 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 06FD18185BFD; Tue, 7 Apr 2026 05:58:58 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Alejandro Vallejo Subject: [PATCH 3/5] xen/mm: Optimise getting free page counts per NUMA node Date: Tue, 7 Apr 2026 10:54:28 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1775555990-BEF4B0B1-32B2EA45/0/0 X-purgate-type: clean X-purgate-size: 3145 From: Alejandro Vallejo Introduce per-node free page counters which enhance the efficiency of avail_node_heap_pages(): - It no longer needs to iterate over all zones of a node. - It is utilised by the numainfo hypercall and the debug-key 'u' to display NUMA information in the printk buffer - This aggregate will be needed for the node-specific claims feature to determine the number of free pages in a node in the hot path of get_free_buddy() without looping over all zones of a node. Signed-off-by: Alejandro Vallejo Signed-off-by: Bernhard Kaindl --- Applied Jan's review: https://lists.xenproject.org/archives/html/xen-devel/2026-03/msg00144.html Changes: - Removed accessor macro - Abandoned conversion to unsigned long --- xen/common/page_alloc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 0fab1630e318..95bae26d1c1f 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -485,7 +485,20 @@ static unsigned long node_need_scrub[MAX_NUMNODES]; static unsigned long *avail[MAX_NUMNODES]; static long total_avail_pages; +/* + * Sum of the free pages in all zones of that node. + * Provided via sysctl by NUMA node placement decisions of domain builders and + * for monitoring. It is also logged with debug-key 'u' for NUMA debugging. + */ +static long node_avail_pages[MAX_NUMNODES]; +/* + * The global heap lock, protecting access to the heap and related structures. + * It protects the heap and claims of the buddy allocator and d->*claims. + * The locking order is: d->page_alloc_lock (optional) -> heap_lock + * - Numerous external callers holding d->page_alloc_lock call functions + * taking the heap_lock. Note: Violating it would cause an ABBA deadlock. + */ static DEFINE_SPINLOCK(heap_lock); static long outstanding_claims; /* total outstanding claims by all domains */ @@ -1097,6 +1110,8 @@ static struct page_info *alloc_heap_pages( } } + ASSERT(node_avail_pages[node] >= request); + node_avail_pages[node] -= request; ASSERT(avail[node][zone] >= request); avail[node][zone] -= request; total_avail_pages -= request; @@ -1287,6 +1302,7 @@ static int reserve_offlined_page(struct page_info *head) if ( !page_state_is(cur_head, offlined) ) continue; + node_avail_pages[node]--; avail[node][zone]--; total_avail_pages--; ASSERT(total_avail_pages >= 0); @@ -1611,6 +1627,7 @@ static void free_heap_pages( } } + node_avail_pages[node] += 1 << order; avail[node][zone] += 1 << order; total_avail_pages += 1 << order; if ( need_scrub ) @@ -2878,7 +2895,7 @@ unsigned long avail_domheap_pages_region( unsigned long avail_node_heap_pages(unsigned int nodeid) { - return avail_heap_pages(MEMZONE_XEN, NR_ZONES -1, nodeid); + return node_avail_pages[nodeid]; } -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:00:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:00:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274692.1560732 (Exim 4.92) (envelope-from ) id 1wA3EZ-0006qh-2a; Tue, 07 Apr 2026 10:00:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274692.1560732; Tue, 07 Apr 2026 10:00:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3EY-0006qa-V9; Tue, 07 Apr 2026 10:00:34 +0000 Received: by outflank-mailman (input) for mailman id 1274692; Tue, 07 Apr 2026 10:00:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3EX-0006qU-Fv for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 10:00:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3EW-00BX2n-S5 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 12:00:32 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d5bc-5cb7-0a2a0a5109dd-0a2a4508c27c-36 for ; Tue, 07 Apr 2026 12:00:32 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d5bf-fab6-0a2a45080019-a065830986ba-3 for ; Tue, 07 Apr 2026 12:00:32 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id A239A818B931; Tue, 7 Apr 2026 05:59:41 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 4/5] xen/mm: Split d->outstanding_pages to global_claims & node_claims Date: Tue, 7 Apr 2026 10:54:29 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775556032-F694D497-7F31FCBA/0/0 X-purgate-type: clean X-purgate-size: 6932 In preparation for extending claims, rename d->outstanding_pages to d->global_claims to keep the naming easy to reason about with the addition of NUMA node claims. Add d->node_claims as the aggregate of the domain's node claims for the hot path of the allocator and include it together with d->global_claims when reporting the total claims state of d. Signed-off-by: Bernhard Kaindl --- xen/common/domctl.c | 2 +- xen/common/page_alloc.c | 33 +++++++++++++++------------------ xen/include/xen/sched.h | 7 +++++-- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 93738931c575..2cc5a4ff32fd 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -97,7 +97,7 @@ void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) info->tot_pages = domain_tot_pages(d); info->max_pages = d->max_pages; - info->outstanding_pages = d->outstanding_pages; + info->outstanding_pages = d->global_claims + d->node_claims; #ifdef CONFIG_MEM_SHARING info->shr_pages = atomic_read(&d->shr_pages); #endif diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 95bae26d1c1f..a4d71f844889 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -540,12 +540,12 @@ static unsigned long claims_retire_global(struct domain *d, ASSERT(spin_is_locked(&heap_lock)); /* If the withdrawal is larger than the claims, don't withdraw beyond */ - retired = min(d->outstanding_pages + 0UL, pages_to_retire); + retired = min(d->global_claims + 0UL, pages_to_retire); /* Assert the invariant of outstanding_claims not going negative */ ASSERT(retired <= outstanding_claims); outstanding_claims -= retired; - d->outstanding_pages -= retired; + d->global_claims -= retired; return retired; } @@ -557,8 +557,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* * Two locks are needed here: * - d->page_alloc_lock: protects accesses to d->{tot,max,extra}_pages. - * - heap_lock: protects accesses to d->outstanding_pages, total_avail_pages - * and outstanding_claims. + * - heap_lock: Protects accesses to the claims and avail_pages state. */ nrspin_lock(&d->page_alloc_lock); spin_lock(&heap_lock); @@ -566,13 +565,13 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { - claims_retire_global(d, d->outstanding_pages); + claims_retire_global(d, d->global_claims); ret = 0; goto out; } - /* only one active claim per domain please */ - if ( d->outstanding_pages ) + /* Reject updating global claims and we can't update node claims */ + if ( d->global_claims || d->node_claims ) { ret = -EINVAL; goto out; @@ -599,8 +598,8 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) goto out; /* yay, claim fits in available memory, stake the claim, success! */ - d->outstanding_pages = claim; - outstanding_claims += d->outstanding_pages; + d->global_claims = claim; + outstanding_claims += claim; ret = 0; out: @@ -896,7 +895,7 @@ static bool claims_permit_request(const struct domain *d, unsigned int memflags, unsigned long requested_pages) { - unsigned long unclaimed_pages; + unsigned long unclaimed_pages, applicable_claims; ASSERT(spin_is_locked(&heap_lock)); ASSERT(avail_pages >= competing_claims); @@ -919,7 +918,7 @@ static bool claims_permit_request(const struct domain *d, * Allow the request to proceed when combination of unclaimed pages and the * claims held by the domain cover the shortfall for the requested_pages. */ - return requested_pages <= unclaimed_pages + d->outstanding_pages; + return requested_pages <= unclaimed_pages + d->global_claims; } static struct page_info *get_free_buddy(unsigned int zone_lo, @@ -1067,7 +1066,7 @@ static struct page_info *alloc_heap_pages( * is made by a domain with sufficient unclaimed pages. */ if ( !claims_permit_request(d, total_avail_pages, outstanding_claims, - memflags, request) ) + memflags, request, NUMA_NO_NODE) ) { spin_unlock(&heap_lock); return NULL; @@ -1117,18 +1116,16 @@ static struct page_info *alloc_heap_pages( total_avail_pages -= request; ASSERT(total_avail_pages >= 0); - if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) ) + if ( d && d->global_claims && !(memflags & MEMF_no_refcount) ) { /* * Adjust claims in the same locked region where total_avail_pages is * adjusted, not doing so would lead to a window where the amount of * free memory (avail - claimed) would be incorrect. * - * Note that by adjusting the claimed amount here it's possible for - * pages to fail to be assigned to the claiming domain while already - * having been subtracted from d->outstanding_pages. Such claimed - * amount is then lost, as the pages that fail to be assigned to the - * domain are freed without replenishing the claim. This is fine given + * Note, after retiring claims for the allocation here, assign_pages() + * could fail. The domain looses The retired claims as the not assigned + * pages are freed without replenishing the claim. This is fine given * claims are only to be used during physmap population as part of * domain build, and any failure in assign_pages() there will result in * the domain being destroyed before creation is finished. Losing part diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..2995c99aa34a 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -413,8 +413,11 @@ struct domain unsigned int tot_pages; unsigned int xenheap_pages; /* pages allocated from Xen heap */ - /* Pages claimed but not possessed, protected by global heap_lock. */ - unsigned int outstanding_pages; + + /* All claims are protected by the heap_lock */ + unsigned int global_claims; /* Global Host-level claims */ + unsigned int node_claims; /* Sum of the Node-specific claims */ + unsigned int max_pages; /* maximum value for domain_tot_pages() */ unsigned int extra_pages; /* pages not included in domain_tot_pages() */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:01:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:01:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274731.1560740 (Exim 4.92) (envelope-from ) id 1wA3Fd-0007SN-FW; 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Instead if the separator(s) looked for isn't > found, that pointed-to field would be updated to hold NULL. Hence the > important check in get_token() is for token to be non-NULL after the call > (which get_token()'s callers rely upon), while the checking of param_name > is left there just in case. > > Fixes: 97fd49a7e074 ("ns16550: add support for UART parameters to be specifed with name-value pairs") > Reported-by: Kamil Frankowicz > Signed-off-by: Jan Beulich Acked-by: Andrew Cooper From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:02:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:02:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274742.1560750 (Exim 4.92) (envelope-from ) id 1wA3GA-0007ul-NT; Tue, 07 Apr 2026 10:02:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274742.1560750; Tue, 07 Apr 2026 10:02:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3GA-0007ue-Jg; Tue, 07 Apr 2026 10:02:14 +0000 Received: by outflank-mailman (input) for mailman id 1274742; Tue, 07 Apr 2026 10:02:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3G9-0007uW-Sc for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 10:02:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3G9-001uQb-8T for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 12:02:13 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4d61f-2eae-0a2a0a5409dd-0a2a450cba62-46 for ; Tue, 07 Apr 2026 12:02:13 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4d624-f40c-0a2a450c0019-a0658309a622-3 for ; Tue, 07 Apr 2026 12:02:12 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id A2FC0818BA72; Tue, 7 Apr 2026 06:01:21 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Daniel P. Smith" , Marcus Granado , Alejandro Vallejo Subject: [PATCH 5/5] xen/mm: Introduce Claim Sets for multiple NUMA nodes Date: Tue, 7 Apr 2026 10:54:30 +0100 Message-Id: <4af33fea53f1956155cca7d5ea74c0802e6ae4d8.1775505670.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775556133-83348A3D-325C9D5B/0/0 X-purgate-type: clean X-purgate-size: 28557 This patch extends Xen's memory claim handling to support claim sets spanning multiple NUMA nodes. Earlier review raised the concern that claims would need to evolve from a single claim into a multi-node model. Roger Pau Monné described the core requirement well: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. -- Roger Pau Monné This patch implements that model. A claim set can contain multiple node-specific claims and an optional global claim for memory that may come from any NUMA node. The new domctl installs the full claim set atomically, and the allocator is updated so that claim checks and claim consumption follow the new semantics. This patch adds: 1. Atomic installation of multi-node claim sets with a domctl. 2. Allocation-time claim checks. 3. Claim retirement on successful allocation using claims. 4. Retention of the legacy claim interface without functional change. Suggested-by: Jan Beulich Suggested-by: Marcus Granado Signed-off-by: Alejandro Vallejo Signed-off-by: Roger Pau Monné Signed-off-by: Bernhard Kaindl --- The design document submitted ahead of this series may help with review. It explains the background, design rationale, and implementation details. Rendered version: https://bernhardk-xen-review.readthedocs.io/node-claims-v5/designs/claims/ Posted version: https://lists.xenproject.org/archives/html/xen-devel/2026-04/msg00108.html Many thanks to everyone who contributed to the earlier work and review, especially Alejandro Vallejo, Jan Beulich, Andrew Cooper, Roger Pau Monné, Marcus Granado, and Edwin Török. Many thanks to everyone who contributed to the previous work, reviews, and implementation of this feature. Thanks, Bernhard --- tools/include/xenctrl.h | 4 + tools/libs/ctrl/xc_domain.c | 38 ++++ xen/common/domctl.c | 54 ++++++ xen/common/page_alloc.c | 279 +++++++++++++++++++++++++++- xen/include/public/domctl.h | 32 ++++ xen/include/public/memory.h | 9 + xen/include/xen/mm.h | 3 + xen/include/xen/sched.h | 6 + xen/xsm/flask/hooks.c | 1 + xen/xsm/flask/policy/access_vectors | 1 + 10 files changed, 422 insertions(+), 5 deletions(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index d5dbf69c8968..a0a9f2143b32 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -2659,6 +2659,10 @@ int xc_domain_set_llc_colors(xc_interface *xch, uint32_t domid, const uint32_t *llc_colors, uint32_t num_llc_colors); +int xc_domain_claim_memory(xc_interface *xch, uint32_t domid, + uint32_t nr_claims, + memory_claim_t *claims); + #if defined(__arm__) || defined(__aarch64__) int xc_dt_overlay(xc_interface *xch, void *overlay_fdt, uint32_t overlay_fdt_size, uint8_t overlay_op); diff --git a/tools/libs/ctrl/xc_domain.c b/tools/libs/ctrl/xc_domain.c index 01c0669c8863..32cd91187d44 100644 --- a/tools/libs/ctrl/xc_domain.c +++ b/tools/libs/ctrl/xc_domain.c @@ -1070,6 +1070,44 @@ int xc_domain_remove_from_physmap(xc_interface *xch, return xc_memory_op(xch, XENMEM_remove_from_physmap, &xrfp, sizeof(xrfp)); } +/* Claim the guest memory for a domain before starting the domain build */ +int xc_domain_claim_memory(xc_interface *xch, + uint32_t domid, + uint32_t nr_claims, + memory_claim_t *claims) +{ + struct xen_domctl domctl = {}; + DECLARE_HYPERCALL_BOUNCE(claims, sizeof(*claims) * nr_claims, + XC_HYPERCALL_BUFFER_BOUNCE_IN); + int ret; + + if ( xc_hypercall_bounce_pre(xch, claims) ) + return -1; + + domctl.cmd = XEN_DOMCTL_claim_memory; + domctl.domain = domid; + domctl.u.claim_memory.nr_claims = nr_claims; + set_xen_guest_handle(domctl.u.claim_memory.claims, claims); + + ret = do_domctl(xch, &domctl); + + xc_hypercall_bounce_post(xch, claims); + + return ret; +} + +/* + * Legacy API for claiming pages, replaced by xc_domain_claim_memory() + * + * Note: This hypercall is deprecated by xc_domain_claim_memory() + * which provides the same claim semantics described above, and thus can be + * used as drop-in replacement and is extended for NUMA-node-specific claims. + * This hypercall should not be used by new code. + * + * See the following documentation pages for more information: + * docs/guest-guide/dom/DOMCTL_claim_memory.rst + * docs/guest-guide/mem/XENMEM_claim_pages.rst + */ int xc_domain_claim_pages(xc_interface *xch, uint32_t domid, unsigned long nr_pages) diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 2cc5a4ff32fd..16d239c75bde 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -51,6 +51,51 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemask, MAX_NUMNODES); } +/* Claim memory for a domain (or if a claim exists, release the claim) */ +static int claim_memory(struct domain *d, + const struct xen_domctl_claim_memory *uinfo) +{ + memory_claim_t *claims; + int rc = -EFAULT; + + /* alloc_color_heap_page() does not handle claims, reject LLC coloring. */ + if ( llc_coloring_enabled ) + return -EOPNOTSUPP; + + if ( !uinfo->nr_claims || uinfo->pad ) + return -EINVAL; + + /* Only calls for the supported number of nodes + a global claim can pass */ + if ( uinfo->nr_claims > MAX_NUMNODES + 1 ) + return -E2BIG; + + /* + * Under domctl_lock, domain_kill() sets d->is_dying and retires claims. + * If it set, this is in the past and we should reject the claim request. + */ + if ( d->is_dying ) + return -ESRCH; + + claims = xmalloc_array(memory_claim_t, uinfo->nr_claims); + if ( claims == NULL ) + return -ENOMEM; + + if ( copy_from_guest(claims, uinfo->claims, uinfo->nr_claims) ) + goto out; + + rc = -EINVAL; /* Default error code for invalid claim args */ + if ( claims[0].target == XEN_DOMCTL_CLAIM_MEMORY_LEGACY && + uinfo->nr_claims == 1 ) + /* Implement installing a legacy claim for backwards compatibility */ + rc = domain_set_outstanding_pages(d, claims[0].pages); + else + /* domain_install_claim_set() performs validation of the claim set */ + rc = domain_install_claim_set(d, uinfo->nr_claims, claims); + out: + xfree(claims); + return rc; +} + void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) { struct vcpu *v; @@ -865,6 +910,15 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) copyback = true; break; + case XEN_DOMCTL_claim_memory: + /* Use the same XSM hook as XENMEM_claim_pages */ + ret = xsm_claim_pages(XSM_PRIV, d); + if ( ret ) + break; + + ret = claim_memory(d, &op->u.claim_memory); + break; + default: ret = arch_do_domctl(op, d, u_domctl); break; diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index a4d71f844889..2b32b1aa8fba 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -502,6 +502,9 @@ static long node_avail_pages[MAX_NUMNODES]; static DEFINE_SPINLOCK(heap_lock); static long outstanding_claims; /* total outstanding claims by all domains */ +/* Sum of the outstanding claims of all domains on that node. */ +static long node_outstanding_claims[MAX_NUMNODES]; + static unsigned long avail_heap_pages( unsigned int zone_lo, unsigned int zone_hi, unsigned int node) { @@ -549,6 +552,164 @@ static unsigned long claims_retire_global(struct domain *d, return retired; } +/* Release outstanding claims on a specific node */ +static unsigned long claims_retire_node(struct domain *d, nodeid_t node, + unsigned long release) +{ + unsigned long consumed = 0; + + ASSERT(spin_is_locked(&heap_lock)); + + /* If the allocation was larger than the claims, do not release beyond it */ + if ( d->claims[node] ) /* Release the claims for this node */ + { + /* Use min_t for clarity to make the comparison type explicit */ + consumed = min_t(unsigned long, release, d->claims[node]); + d->claims[node] -= consumed; + + ASSERT(consumed <= outstanding_claims); + outstanding_claims -= consumed; + + ASSERT(consumed <= node_outstanding_claims[node]); + node_outstanding_claims[node] -= consumed; + + ASSERT(consumed <= d->node_claims); + d->node_claims -= consumed; + } + return consumed; +} + +/* Release all outstanding claims on all online nodes */ +static void claims_retire_nodes(struct domain *d) +{ + nodeid_t node; + + for_each_online_node ( node ) + { + claims_retire_node(d, node, d->claims[node]); + } + ASSERT(d->node_claims == 0); +} + +/* Validate a claim set and install it if valid. */ +int domain_install_claim_set(struct domain *d, unsigned int nr_claims, + memory_claim_t *claim_set) +{ + nodemask_t nodes; + uint32_t target; + uint64_t pages, tot_pages, max_pages, node_requests = 0, global_request = 0; + bool global_target_seen = false; + int ret = -EINVAL; + + nrspin_lock(&d->page_alloc_lock); + spin_lock(&heap_lock); + + /* + * Phase 1: Check and process the individual claim entries. + * Result: Extracted global claims and the sum of the node-local claims. + */ + nodes_clear(nodes); + for ( int i = 0; i < nr_claims; i++ ) + { + target = claim_set[i].target; + pages = claim_set[i].pages; + if ( claim_set[i].pad ) /* Check before handling global claims */ + goto out; + + if ( target == XEN_DOMCTL_CLAIM_MEMORY_GLOBAL ) + { + if ( global_target_seen ) /* Only one global target allowed */ + goto out; + + global_request = pages; /* Will be checked with the total claims */ + global_target_seen = true; + continue; + } + + if ( target >= MAX_NUMNODES || !node_online(target) ) + { + ret = -ENOENT; /* Node not valid or not online */ + goto out; + } + if ( nodemask_test(target, &nodes) || /* Duplicate node in claim set */ + /* Check for overflow before we add the pages to node_requests */ + pages > ((typeof(d->node_claims))-1) - node_requests ) + goto out; + node_set(target, nodes); + + ASSERT(node_outstanding_claims[target] >= 0 && + node_avail_pages[target] >= node_outstanding_claims[target]); + if ( pages > (uint64_t)(node_avail_pages[target] - + node_outstanding_claims[target]) + + d->claims[target] ) /* current claim deduction */ + { + ret = -ENOMEM; /* Claim exceeds available memory on node */ + goto out; + } + node_requests += pages; /* Will be checked with the total claims */ + } + + max_pages = d->max_pages; + tot_pages = domain_tot_pages(d); + /* + * Check that the total of claims and current pages fits in d->max_pages. + * Subtract sequentially from max_pages instead of adding the claims: + * each subtraction is safe because the prior comparison guarantees + * the subtrahend doesn't exceed the remaining budget. This avoids + * overflow regardless of the type widths of the claims and max_pages, + * as long as the claims are non-negative (which they are, as unsigned) + * and max_pages is not negative, which we check as well here. + */ + if ( global_request > max_pages || + node_requests > max_pages - global_request || + tot_pages > max_pages - global_request - node_requests ) + goto out; /* claims + domain_tot_pages exceeds max_pages: EINVAL */ + + /* + * Check that replacing the domain's current claims with the new claim set + * fits within the system-wide unclaimed memory. + * + * The right-hand side subtracts all outstanding claims from the total + * available memory, then adds this domain's current claims back because + * phase 3 retires them before installing the replacement claims. + */ + ASSERT(outstanding_claims >= 0 && total_avail_pages >= outstanding_claims); + if ( global_request + node_requests > + (uint64_t)(total_avail_pages - outstanding_claims) + d->global_claims + + d->node_claims ) + { + ret = -ENOMEM; + goto out; /* Total claim exceeds available unclaimed memory: ENOMEM */ + } + + /* Phase 3: Recall the domain's current claims */ + claims_retire_global(d, d->global_claims); + claims_retire_nodes(d); + + /* Phase 4: Install claim set: Global claims and overall node claims */ + outstanding_claims += global_request + node_requests; + d->global_claims = global_request; + d->node_claims = node_requests; + + /* Phase 5: Install the individual node claims */ + for ( int i = 0; i < nr_claims; i++ ) + { + target = claim_set[i].target; + pages = claim_set[i].pages; + if ( target >= MAX_NUMNODES ) /* Skip non-node claim targets */ + continue; + + /* Install the node claim and update the node's total claims claims. */ + d->claims[target] = pages; + node_outstanding_claims[target] += pages; + } + ret = 0; +out: + spin_unlock(&heap_lock); + nrspin_unlock(&d->page_alloc_lock); + return ret; +} + int domain_set_outstanding_pages(struct domain *d, unsigned long pages) { int ret = -ENOMEM; @@ -565,6 +726,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { + claims_retire_nodes(d); claims_retire_global(d, d->global_claims); ret = 0; goto out; @@ -608,6 +770,87 @@ out: return ret; } +/* + * Retire the claims to cover a successful allocation. + * + * The claims for an allocation are retired in order of specificity: + * + * 1.) Firstly, the claim for the node the allocation was from (if any), + * 2.) Secondly, followed by global claims as a fallback (if any), and + * 3.) Finally, other remaining node claims from other nodes (if any). + * + * This order ensures that the most specific claims are retired first, + * and that the global claim is only used as a fallback if the node-specific + * claim is insufficient to cover the allocation or non-existant in case + * the domain doesn't have a claim on the alloc_node. This preserves the + * intent of the claims system to allow domains to reserve memory on + * specific nodes and only use global claims as a fallback when necessary. + * + * Finally, if the domain doesn't have sufficient claims on the alloc_node + * and the global fallback claim doesn't cover the remains of the allocation, + * but as the domain still has other claims, retire the remaining portion + * of the allocation from those claims. + * + * This final step ensures that the domain's total claims (global + node + * claims) are always retired to cover the allocation, which in turn + * prevents domain_tot_pages(d) + d->global_claims + d->node_claims + * from exceeding the domain's d->max_pages limit. + * + * If this final step was not taken, then it would be possible for a domain to + * block off more than its share of system memory as defined by d->max_pages. + * + * Note: We can't reliably check d->max_pages here, at least not under the + * d->page_alloc_lock as taking it here would violate the locking order, + * but we can ensure that the domain's claims are always retired to cover + * the allocation, which is sufficient to preserve the intent of d->max_pages + * cap the domain's memory usage and claims to d->max_pages. While we could + * add checking it without lock as a best effort check, a domain builder is + * not supposed to claim memory on one set of nodes and then allocate from + * another set of nodes, so it would not be meaningful to add such a check, + * and the final check covers our bases to handle such misbehaviour anyway. + */ +static void claims_retire_allocation(struct domain *d, + unsigned long allocated_pages, + nodeid_t alloc_node) +{ + unsigned long pages_to_retire = allocated_pages; + + ASSERT(spin_is_locked(&heap_lock)); + + /* 1.) Retire the allocation from the alloc_node's claim insofar possible */ + if ( d->claims[alloc_node] ) + { + pages_to_retire -= claims_retire_node(d, alloc_node, pages_to_retire); + if ( pages_to_retire == 0 ) + return; /* The allocation is fully consumed by alloc_node claim */ + } + + /* 2.) Retire remains of the allocation from the global / fallback claims */ + pages_to_retire -= claims_retire_global(d, pages_to_retire); + + if ( pages_to_retire == 0 || !d->node_claims ) + return; /* Allocation fully consumed or the domain has no claims left */ + + /* + * 3.) Finally, if the domain doesn't have sufficient claims on alloc_node + * and the global fallback claim didn't cover the remains of the allocation, + * consume the remaining portion of the allocation from the domain's other + * node claims. See the function comment for the details behind this step. + */ + pages_to_retire = min(pages_to_retire, d->node_claims + 0UL); + if ( pages_to_retire ) + { + nodeid_t node; + + for_each_online_node ( node ) + { + pages_to_retire -= claims_retire_node(d, node, pages_to_retire); + if ( pages_to_retire == 0 ) + break; + } + } +} + #ifdef CONFIG_SYSCTL void get_outstanding_claims(uint64_t *free_pages, uint64_t *outstanding_pages) { @@ -893,7 +1136,7 @@ static bool claims_permit_request(const struct domain *d, unsigned long avail_pages, unsigned long competing_claims, unsigned int memflags, - unsigned long requested_pages) + unsigned long requested_pages, nodeid_t node) { unsigned long unclaimed_pages, applicable_claims; @@ -918,7 +1161,25 @@ static bool claims_permit_request(const struct domain *d, * Allow the request to proceed when combination of unclaimed pages and the * claims held by the domain cover the shortfall for the requested_pages. */ - return requested_pages <= unclaimed_pages + d->global_claims; + if ( node == NUMA_NO_NODE ) + /* + * We are checking global claims: For the global claims check, + * we apply the domain's global claims and node claims: The domain + * can use any of its claims to allow the global check to proceed. + * + * get_free_buddy() will repeat this check using a node which + * will check if either the node has enough unclaimed pages + * or the domain enough claims for the node (see below). + */ + applicable_claims = d->node_claims + d->global_claims; + else + /* + * We are checking node-specific claims: For the node-specific claims + * check, we may only apply the domain's claim on that specific node. + */ + applicable_claims = d->claims[node]; + + return requested_pages <= unclaimed_pages + applicable_claims; } static struct page_info *get_free_buddy(unsigned int zone_lo, @@ -970,9 +1231,15 @@ static struct page_info *get_free_buddy(unsigned int zone_lo, */ for ( ; ; ) { + /* Ensure the target node and the claims permit this allocation */ + if ( !claims_permit_request(d, node_avail_pages[node], + node_outstanding_claims[node], memflags, + 1UL << order, node) ) + goto try_next_node; + zone = zone_hi; do { - /* Check if target node can support the allocation. */ + /* Check if this target zone on node can support the allocation. */ if ( !avail[node] || (avail[node][zone] < (1UL << order)) ) continue; @@ -999,6 +1266,8 @@ static struct page_info *get_free_buddy(unsigned int zone_lo, } } while ( zone-- > zone_lo ); /* careful: unsigned zone may wrap */ + try_next_node: + /* If MEMF_exact_node was passed, we may not skip to a different node */ if ( (memflags & MEMF_exact_node) && req_node != NUMA_NO_NODE ) return NULL; @@ -1116,7 +1385,7 @@ static struct page_info *alloc_heap_pages( total_avail_pages -= request; ASSERT(total_avail_pages >= 0); - if ( d && d->global_claims && !(memflags & MEMF_no_refcount) ) + if ( d && !(memflags & MEMF_no_refcount) ) { /* * Adjust claims in the same locked region where total_avail_pages is @@ -1131,7 +1400,7 @@ static struct page_info *alloc_heap_pages( * the domain being destroyed before creation is finished. Losing part * of the claim makes no difference. */ - claims_retire_global(d, request); + claims_retire_allocation(d, request, node); } check_low_mem_virq(); diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..a4f08248e6ee 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -1276,6 +1276,36 @@ struct xen_domctl_get_domain_state { uint64_t unique_id; /* Unique domain identifier. */ }; +struct xen_memory_claim { + uint64_aligned_t pages; /* Number of pages to claim */ + uint32_t target; /* Node and/or claim type like legacy or a global claim */ + uint32_t pad; /* Explicit padding: Reserved, initialize to 0 on input */ +}; +typedef struct xen_memory_claim memory_claim_t; +DEFINE_XEN_GUEST_HANDLE(memory_claim_t); + +/* Special claim targets for the target field of memory_claim_t */ +#define XEN_DOMCTL_CLAIM_MEMORY_LEGACY 0x40000000U /* No node, legacy claim */ +#define XEN_DOMCTL_CLAIM_MEMORY_GLOBAL 0x80000000U /* No node, global claim */ + +/* + * XEN_DOMCTL_claim_memory + * + * Claim memory for a guest domain. It sets aside an amount of memory + * (it is not pre-allocated) for the purpose of satisfying future memory + * allocation requests for building the guest's physical address space. + * Memory can be claimed on a set of nodes, or globally (without node + * affinity), or with legacy behavior. The set of claims is a claim set. See + * docs/guest-guide/dom/DOMCTL_claim_memory.rsti and docs/designs/claims/. + */ +struct xen_domctl_claim_memory { + /* IN: Array of struct xen_memory_claim */ + XEN_GUEST_HANDLE_64(memory_claim_t) claims; + /* IN: Number of claims in the claims array handle. */ + uint32_t nr_claims; + uint32_t pad; /* Explicit padding: Reserved, initialize to 0 on input */ +}; + struct xen_domctl { /* Stable domctl ops: interface_version is required to be 0. */ uint32_t cmd; @@ -1368,6 +1398,7 @@ struct xen_domctl { #define XEN_DOMCTL_gsi_permission 88 #define XEN_DOMCTL_set_llc_colors 89 #define XEN_DOMCTL_get_domain_state 90 /* stable interface */ +#define XEN_DOMCTL_claim_memory 91 #define XEN_DOMCTL_gdbsx_guestmemio 1000 #define XEN_DOMCTL_gdbsx_pausevcpu 1001 #define XEN_DOMCTL_gdbsx_unpausevcpu 1002 @@ -1436,6 +1467,7 @@ struct xen_domctl { #endif struct xen_domctl_set_llc_colors set_llc_colors; struct xen_domctl_get_domain_state get_domain_state; + struct xen_domctl_claim_memory claim_memory; uint8_t pad[128]; } u; }; diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h index bd9fc37b5297..ccec095f8660 100644 --- a/xen/include/public/memory.h +++ b/xen/include/public/memory.h @@ -569,6 +569,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_mem_sharing_op_t); * for 10, only 7 additional pages are claimed. * * Caller must be privileged or the hypercall fails. + * + * Note: This hypercall is deprecated by XEN_DOMCTL_claim_memory + * which provides the same claim semantics described above, and thus can be + * used as drop-in replacement and is extended for NUMA-node-specific claims. + * This hypercall should not be used by new code. + * + * See the following documentation pages for more information: + * docs/guest-guide/dom/DOMCTL_claim_memory.rst + * docs/guest-guide/mem/XENMEM_claim_pages.rst */ #define XENMEM_claim_pages 24 diff --git a/xen/include/xen/mm.h b/xen/include/xen/mm.h index b80bec00c124..b2d6a6f266ba 100644 --- a/xen/include/xen/mm.h +++ b/xen/include/xen/mm.h @@ -69,6 +69,7 @@ #include #include #include +#include #include struct page_info; @@ -131,6 +132,8 @@ int populate_pt_range(unsigned long virt, unsigned long nr_mfns); /* Claim handling */ unsigned long __must_check domain_adjust_tot_pages(struct domain *d, long pages); +int domain_install_claim_set(struct domain *d, unsigned int nr_claims, + memory_claim_t *claims); int domain_set_outstanding_pages(struct domain *d, unsigned long pages); void get_outstanding_claims(uint64_t *free_pages, uint64_t *outstanding_pages); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 2995c99aa34a..d31f4546e3b0 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -417,6 +417,12 @@ struct domain /* All claims are protected by the heap_lock */ unsigned int global_claims; /* Global Host-level claims */ unsigned int node_claims; /* Sum of the Node-specific claims */ + /* + * struct domain is allocated in a dedicated page with more than enough + * spare capacity. It's efficient to use that page to store the + * per-node claims in it instead allocating a separate array for it. + */ + unsigned int claims[MAX_NUMNODES]; /* Array of per-NUMA-node claims */ unsigned int max_pages; /* maximum value for domain_tot_pages() */ unsigned int extra_pages; /* pages not included in domain_tot_pages() */ diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index b250b2706535..adfcf081a33c 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -651,6 +651,7 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd, /* These have individual XSM hooks (common/domctl.c) */ case XEN_DOMCTL_getdomaininfo: + case XEN_DOMCTL_claim_memory: case XEN_DOMCTL_scheduler_op: case XEN_DOMCTL_irq_permission: case XEN_DOMCTL_iomem_permission: diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors index ce907d50a45e..77db6f4cb38e 100644 --- a/xen/xsm/flask/policy/access_vectors +++ b/xen/xsm/flask/policy/access_vectors @@ -218,6 +218,7 @@ class domain2 # XEN_DOMCTL_scheduler_op with XEN_DOMCTL_SCHEDOP_putinfo setscheduler # XENMEM_claim_pages +# XEN_DOMCTL_claim_memory setclaim # XEN_DOMCTL_cacheflush cacheflush -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:02:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:02:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274747.1560759 (Exim 4.92) (envelope-from ) id 1wA3GP-0008Fp-1W; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OHzTrA9J+n9/U7Mb" Content-Disposition: inline In-Reply-To: <47b140b2-596b-47db-9c0c-43672f445036@suse.com> X-purgate-ID: tlsNG-ebf023/1775556147-3052B51B-079D0E49/0/0 X-purgate-type: clean X-purgate-size: 9550 --OHzTrA9J+n9/U7Mb Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 7 Apr 2026 12:02:23 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Tue, Apr 07, 2026 at 08:29:48AM +0200, Jan Beulich wrote: > On 03.04.2026 01:06, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Apr 02, 2026 at 04:53:31PM +0200, Jan Beulich wrote: > >> On 02.04.2026 16:47, Marek Marczykowski-G=C3=B3recki wrote: > >>> On Thu, Apr 02, 2026 at 12:48:14PM +0200, Jan Beulich wrote: > >>>> On 02.04.2026 11:35, Marek Marczykowski-G=C3=B3recki wrote: > >>>>> On Thu, Apr 02, 2026 at 10:39:41AM +0200, Jan Beulich wrote: > >>>>>> On 02.04.2026 10:08, Marek Marczykowski-G=C3=B3recki wrote: > >>>>>>> The xl dmesg output (from MTL this time): > >>>>>>> > >>>>>>> (XEN) [ 123.477511] Entering ACPI S3 state. > >>>>>>> (XEN) [18446743903.571842] _disable_pit_irq:2649: using_pit: = 0, cpu_has_apic: 1 > >>>>>>> (XEN) [18446743903.571856] _disable_pit_irq:2659: cpuidle_usi= ng_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >>>>> > >>>>>> Hmm, but what you didn't log is whether __hpet_setup_msi_irq() act= ually > >>>>>> succeeded everywhere. (And if it did, also logging HPET_Tn_ROUTE()= values > >>>>>> might be a good idea, if only to double check.) > >>>>> > >>>>> Updated output: > >>>>> > >>>>> (XEN) [18446743899.720395] _disable_pit_irq:2649: using_pit: 0,= cpu_has_apic: 1 > >>>>> (XEN) [18446743899.720409] _disable_pit_irq:2659: cpuidle_using= _deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >>>>> (XEN) [18446743899.720420] _disable_pit_irq:2662: init: 0 > >>>>> (XEN) [18446743899.720431] hpet_broadcast_resume:663: hpet_even= ts: ffff83046bc1f080 > >>>>> (XEN) [18446743899.720579] hpet_broadcast_resume:674: num_hpets= _used: 8 > >>>>> (XEN) [18446743899.720587] hpet_broadcast_resume:692: cfg: 0x1 > >>>>> (XEN) [18446743899.720599] hpet_broadcast_resume:697: i:0, hpet= _events[i].msi.irq: 122, hpet_events[i].flags: 0 > >>>>> (XEN) [18446743899.720612] hpet_msi_write:283: iommu_intremap: = 2 (iommu_intremap_off: 0), HPET_Tn_ROUTE(ch->idx): 0x110 > >>>>> (XEN) [18446743899.720638] hpet_msi_write:287: iommu_update_ire= _from_msi rc: 0 > >>>> > >>>> So it succeeds, and the low half of HPET_Tn_ROUTE also looks plausib= le. The high > >>>> half is, however, the address that the low half value is written to.= It's hard > >>>> to imagine that it would be zero when the low half isn't, but it is = about the > >>>> last thing I can think of which could explain observed behavior. (Ye= t then, all > >>>> of this is pretty meaningless; see below.) > >>>> > >>>>> And the current debug diff attached. > >>>> > >>>> Hmm, you log HPET_Tn_ROUTE _before_ our update. That's not very usef= ul. You want > >>>> to move that part of logging to the bottom of hpet_msi_write(), or m= aybe to > >>>> where you also log the per-channel cfg value in hpet_broadcast_resum= e() (thus > >>>> making the logging overall less verbose). > >>> > >>> This test is with the updated patch (attached) + your extra > >>> calculate_host_policy() call and "no-arat" on cmdline: > >> > >> And IOMMU faults still occurring as before, I expect. > >> > >> Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you don= 't log > >> the high halves at all. > >=20 > > I was missing hpet_read32 there... > >=20 > > Updated: > > (XEN) [ 116.921573] Entering ACPI S3 state. > > (XEN) [18446743895.088893] _disable_pit_irq:2649: using_pit: 0, cpu_has= _apic: 1 > > (XEN) [18446743895.088907] _disable_pit_irq:2659: cpuidle_using_deep_cs= tate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > > (XEN) [18446743895.088918] _disable_pit_irq:2662: init: 0 > > (XEN) [18446743895.088928] hpet_broadcast_resume:662: hpet_events: ffff= 83046bc1f080 > > (XEN) [18446743895.089072] hpet_broadcast_resume:673: num_hpets_used: 8 > > (XEN) [18446743895.089081] hpet_broadcast_resume:691: cfg: 0x1 > > (XEN) [18446743895.089092] hpet_broadcast_resume:696: i:0, hpet_events[= i].msi.irq: 122, hpet_events[i].flags: 0 > > (XEN) [18446743895.089122] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089132] hpet_broadcast_resume:700: i:0, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089168] hpet_broadcast_resume:710: i:0, cfg: 0xc134,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xf18 >=20 > Okay, this would appear to clarify that the address really isn't correct.= Yet I'm > confused now by the low half values: In your earlier log there was >=20 > hpet_broadcast_resume:710: i:0, cfg: 0xc134, HPET_Tn_ROUTE(hpet_events[i]= =2Eidx): 0x110 My earlier logging included literal HPET_Tn_ROUTE() macro output, not hpet_read32() of it... > and alike, i.e. clearly a non-zero value. Now all low halves are zero. I'= ll try > to figure how the logged values here could result, but consistent data (o= r an > explantation for the apparent inconsistency) would help. >=20 > Jan >=20 > > (XEN) [18446743895.089180] hpet_broadcast_resume:696: i:1, hpet_events[= i].msi.irq: 123, hpet_events[i].flags: 0 > > (XEN) [18446743895.089203] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089213] hpet_broadcast_resume:700: i:1, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089242] hpet_broadcast_resume:710: i:1, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xf38 > > (XEN) [18446743895.089254] hpet_broadcast_resume:696: i:2, hpet_events[= i].msi.irq: 124, hpet_events[i].flags: 0 > > (XEN) [18446743895.089278] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089288] hpet_broadcast_resume:700: i:2, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089316] hpet_broadcast_resume:710: i:2, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xf58 > > (XEN) [18446743895.089327] hpet_broadcast_resume:696: i:3, hpet_events[= i].msi.irq: 125, hpet_events[i].flags: 0 > > (XEN) [18446743895.089350] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089361] hpet_broadcast_resume:700: i:3, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089390] hpet_broadcast_resume:710: i:3, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xf78 > > (XEN) [18446743895.089401] hpet_broadcast_resume:696: i:4, hpet_events[= i].msi.irq: 126, hpet_events[i].flags: 0 > > (XEN) [18446743895.089425] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089436] hpet_broadcast_resume:700: i:4, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089465] hpet_broadcast_resume:710: i:4, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xf98 > > (XEN) [18446743895.089476] hpet_broadcast_resume:696: i:5, hpet_events[= i].msi.irq: 127, hpet_events[i].flags: 0 > > (XEN) [18446743895.089499] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089509] hpet_broadcast_resume:700: i:5, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089540] hpet_broadcast_resume:710: i:5, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xfb8 > > (XEN) [18446743895.089551] hpet_broadcast_resume:696: i:6, hpet_events[= i].msi.irq: 128, hpet_events[i].flags: 0 > > (XEN) [18446743895.089574] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089584] hpet_broadcast_resume:700: i:6, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089622] hpet_broadcast_resume:710: i:6, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xfd8 > > (XEN) [18446743895.089633] hpet_broadcast_resume:696: i:7, hpet_events[= i].msi.irq: 129, hpet_events[i].flags: 0 > > (XEN) [18446743895.089655] hpet_msi_write:286: iommu_update_ire_from_ms= i rc: 0 > > (XEN) [18446743895.089665] hpet_broadcast_resume:700: i:7, __hpet_setup= _msi_irq ret: 0 > > (XEN) [18446743895.089702] hpet_broadcast_resume:710: i:7, cfg: 0xc104,= hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROU= TE(hpet_events[i].idx) + 4): 0xff8 > >=20 > >=20 > >=20 > >=20 >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --OHzTrA9J+n9/U7Mb Content-Type: application/pgp-signature; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="cjd2LFgO4eOZHcdQ" Content-Disposition: inline In-Reply-To: <6dccae5f-fe09-4f35-9e4a-7a38fb21e8d1@suse.com> X-purgate-ID: tlsNG-d25034/1775556250-81557A3D-F6E7FC3D/0/0 X-purgate-type: clean X-purgate-size: 3613 --cjd2LFgO4eOZHcdQ Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 7 Apr 2026 12:04:05 +0200 From: Marek Marczykowski To: Jan Beulich Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH] x86/cpu-policy: set up host policy earlier On Tue, Apr 07, 2026 at 08:46:39AM +0200, Jan Beulich wrote: > In order to use cpu_has_* expanding to host_cpu_policy.*, the host policy > needs setting up alongside boot_cpu_data.x86_capability[]. Arrange for > that towards the end of identify_cpu(). >=20 > Fixes: 894bd7617924 ("x86/Intel: use host CPU policy for ARAT checking") > Reported-by: Marek Marczykowski-G=C3=B3recki > Signed-off-by: Jan Beulich Tested-by: Marek Marczykowski-G=C3=B3recki > --- > In the longer run we may need to (also) update the host policy from > setup_{force,clear}_cpu_cap(). >=20 > This really was part of one of the XSTATE cleanup patches at the head of > the AMX series. This explains the specific placement ahead of the call to > xstate_init()). Likely anything from there downwards shouldn't really > live in identify_cpu() anyway. >=20 > --- a/xen/arch/x86/cpu/common.c > +++ b/xen/arch/x86/cpu/common.c > @@ -586,6 +586,8 @@ void identify_cpu(struct cpuinfo_x86 *c) > } > =20 > /* Now the feature flags better reflect actual CPU features! */ > + if (c =3D=3D &boot_cpu_data) > + calculate_host_policy(); > =20 > xstate_init(c); > =20 > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -359,7 +359,7 @@ void calculate_raw_cpu_policy(void) > /* Was already added by probe_cpuid_faulting() */ > } > =20 > -static void __init calculate_host_policy(void) > +void __init calculate_host_policy(void) > { > struct cpu_policy *p =3D &host_cpu_policy; > unsigned int max_extd_leaf; > @@ -904,6 +904,7 @@ static void __init calculate_hvm_def_pol > =20 > void __init init_guest_cpu_policies(void) > { > + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() u= ses. */ > calculate_host_policy(); > =20 > if ( IS_ENABLED(CONFIG_PV) ) > --- a/xen/arch/x86/include/asm/cpu-policy.h > +++ b/xen/arch/x86/include/asm/cpu-policy.h > @@ -30,4 +30,10 @@ void recalculate_cpuid_policy(struct dom > */ > void calculate_raw_cpu_policy(void); > =20 > +/* > + * Collect the host CPU policy. Called after collecting enough CPUID ou= tput, > + * and again after all feature overrides have been put in place. > + */ > +void calculate_host_policy(void); > + > #endif /* X86_CPU_POLICY_H */ --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --cjd2LFgO4eOZHcdQ Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnU1pUACgkQ24/THMrX 1yyRNwf5AaCNJWlZelP3p1Zxxjnvpi55wsCFEkSrysaDmsxbUr+X7cNNEPo9mv/p g4f4OzfIuHPj7CRdJmBFaJhi2xD/dwjZ7c+3o5yDUVF6nBJi87NQouCARg3nEobF Te3QbhCI72hDOfei6W2KIydS3EEWJDBRYCjvvIj7Ol0JuF4vGcckQBi9EFJ3txZp wiXnBvw1mAVL1NTNrcN+geaUeksthzA9TVlPx4ZxX4pVzv8R8/GKwI1s4xlLuqQA JWeU8Ggy8SuESpvxsQ54ivntWx7da2Z3y4++y47bs4p8qXjEooNLtzEPPDhgPVOO rlHtqaNELadnG5C0iovEUF+xg/p07g== =kwlA -----END PGP SIGNATURE----- --cjd2LFgO4eOZHcdQ-- From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:04:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:04:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274788.1560786 (Exim 4.92) (envelope-from ) id 1wA3I7-0001ED-0E; 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Tue, 07 Apr 2026 03:14:56 -0700 (PDT) From: =?UTF-8?B?TWF0ecOhxaE=?= Kroupa To: Jan Beulich Cc: xen-devel@lists.xen.org Subject: Re: Xen on Zen 3 Date: Tue, 07 Apr 2026 12:14:55 +0200 Message-ID: <4454038.v2OnDr8pfo@rivendell.hailstone.cz> In-Reply-To: <1f1cfdeb-adbd-420d-a187-d0007fcad123@suse.com> References: <5490687.niJfEyVGOH@rivendell.hailstone.cz> <1f1cfdeb-adbd-420d-a187-d0007fcad123@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-purgate-ID: tlsNG-ef75cf/1775556897-8A54B41E-4E55C232/0/0 X-purgate-type: clean X-purgate-size: 1114 Dne =C3=BAter=C3=BD 7. dubna 2026 11:05:40, st=C5=99edoevropsk=C3=BD letn= =C3=AD =C4=8Das, Jan Beulich=20 napsal(a): > Not exactly, there is an earlier exit from the function when num_roots is= 0. > If that line is the problem one, then presumably num_roots < num_nodes, t= hus > yielding roots_per_node as 0. Sadly you didn't enable enough verbosity for >=20 > pr_debug("Found %d AMD root devices\n", num_roots); >=20 > to actually leave a trace in the log. I'd guess the value to be 1, but th= ere > being multiple nodes at the same time. You may want to instrument the > function a little more to be certain. I booted it with either loglevel=3D8 or ignore_loglevel, but could not get = the=20 pr_debug to output anything. It did however print a lot of pci and other de= bug=20 messages as expected. =20 > For your immediate purpose you may want to change the "!num_roots" check > into a "num_roots < num_nodes" one (on the assumption that num_nodes > can't be 0). Whether that's acceptable upstream I don't know, of course. I'll try that later Maty=C3=A1=C5=A1 Kroupa From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:23:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:23:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274828.1560803 (Exim 4.92) (envelope-from ) id 1wA3aV-00059i-NG; Tue, 07 Apr 2026 10:23:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274828.1560803; Tue, 07 Apr 2026 10:23:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3aV-00059b-KV; Tue, 07 Apr 2026 10:23:15 +0000 Received: by outflank-mailman (input) for mailman id 1274828; Tue, 07 Apr 2026 10:23:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3aU-00059V-LL for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 10:23:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3aU-00BZBi-14 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 12:23:14 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4db11-bab6-0a2a0a5309dd-0a2a450588ea-2 for ; Tue, 07 Apr 2026 12:23:13 +0200 Received: from [209.85.221.44] (helo=mail-wr1-f44.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4db10-3760-0a2a45050019-d155dd2ce9cf-3 for ; Tue, 07 Apr 2026 12:23:12 +0200 Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-43b95e5b3afso2664464f8f.3 for ; Tue, 07 Apr 2026 03:23:12 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 07 Apr 2026 03:23:12 -0700 (PDT) Message-ID: <8c9e5404-24bf-410d-a2e8-551cb87c6400@suse.com> Date: Tue, 7 Apr 2026 12:23:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 From: Jan Beulich To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <090b8b8f-141b-4a24-92eb-879c0a0c73e1@suse.com> <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> <92e0151b-3fb1-4108-9788-f0fbac43512b@suse.com> <47b140b2-596b-47db-9c0c-43672f445036@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <47b140b2-596b-47db-9c0c-43672f445036@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775557392-2272296F-229F0C6D/0/0 X-purgate-type: clean X-purgate-size: 4004 On 07.04.2026 08:29, Jan Beulich wrote: > On 03.04.2026 01:06, Marek Marczykowski-Górecki wrote: >> On Thu, Apr 02, 2026 at 04:53:31PM +0200, Jan Beulich wrote: >>> Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you don't log >>> the high halves at all. >> >> I was missing hpet_read32 there... >> >> Updated: >> (XEN) [ 116.921573] Entering ACPI S3 state. >> (XEN) [18446743895.088893] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 >> (XEN) [18446743895.088907] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 >> (XEN) [18446743895.088918] _disable_pit_irq:2662: init: 0 >> (XEN) [18446743895.088928] hpet_broadcast_resume:662: hpet_events: ffff83046bc1f080 >> (XEN) [18446743895.089072] hpet_broadcast_resume:673: num_hpets_used: 8 >> (XEN) [18446743895.089081] hpet_broadcast_resume:691: cfg: 0x1 >> (XEN) [18446743895.089092] hpet_broadcast_resume:696: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 >> (XEN) [18446743895.089122] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 >> (XEN) [18446743895.089132] hpet_broadcast_resume:700: i:0, __hpet_setup_msi_irq ret: 0 >> (XEN) [18446743895.089168] hpet_broadcast_resume:710: i:0, cfg: 0xc134, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xf18 > > Okay, this would appear to clarify that the address really isn't correct. Yet I'm > confused now by the low half values: In your earlier log there was > > hpet_broadcast_resume:710: i:0, cfg: 0xc134, HPET_Tn_ROUTE(hpet_events[i].idx): 0x110 > > and alike, i.e. clearly a non-zero value. Now all low halves are zero. I'll try > to figure how the logged values here could result, but consistent data (or an > explantation for the apparent inconsistency) would help. Could you give the patch below a try? Jan x86/HPET: channel handling in hpet_broadcast_resume() The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for the (possible) channel put in legacy mode we don't do so during boot either. Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an all-zero message (when the passed in CPU mask has no online CPUs). Nothing would later call msi_compose_msg() / hpet_msi_write(), and hence nothing would later produce a well-formed message template in hpet_events[].msi.msg. Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") Reported-by: Marek Marczykowski-Górecki Signed-off-by: Jan Beulich --- As to the Fixes: tag: The issue for the HPET resume case is the cpumask_intersects(desc->arch.cpu_mask, &cpu_online_map) check in msi_compose_msg(). The earlier cpumask_empty() wasn't a problem, as cpu_mask_to_apicid() returning a bogus (offline) value didn't have any bad effect: Before use, a valid destination would have been put in place, but other parts of .msg were properly set up. Furthermore we also didn't clear the entire message prior to that change. --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -685,12 +685,18 @@ void hpet_broadcast_resume(void) for ( i = 0; i < n; i++ ) { if ( hpet_events[i].msi.irq >= 0 ) + { + struct irq_desc *desc = irq_to_desc(hpet_events[i].msi.irq); + + cpumask_copy(desc->arch.cpu_mask, cpumask_of(smp_processor_id())); + __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); + } /* set HPET Tn as oneshot */ cfg = hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC); - cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; + cfg |= HPET_TN_32BIT; if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) cfg |= HPET_TN_FSB; hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:26:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:26:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274837.1560813 (Exim 4.92) (envelope-from ) id 1wA3dL-0005hZ-3N; Tue, 07 Apr 2026 10:26:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274837.1560813; Tue, 07 Apr 2026 10:26:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3dL-0005hS-0i; Tue, 07 Apr 2026 10:26:11 +0000 Received: by outflank-mailman (input) for mailman id 1274837; Tue, 07 Apr 2026 10:26:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3dK-0005hM-7p for xen-devel@lists.xen.org; Tue, 07 Apr 2026 10:26:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3dJ-003qFl-JU for xen-devel@lists.xen.org; Tue, 07 Apr 2026 12:26:09 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4dbb7-e002-0a2a0a5209dd-0a2a4506da5a-42 for ; Tue, 07 Apr 2026 12:26:09 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4dbc1-0df0-0a2a45060019-d1558036b980-3 for ; Tue, 07 Apr 2026 12:26:09 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-48374014a77so64800215e9.3 for ; Tue, 07 Apr 2026 03:26:09 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 07 Apr 2026 03:26:08 -0700 (PDT) Message-ID: Date: Tue, 7 Apr 2026 12:26:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Xen on Zen 3 To: =?UTF-8?B?TWF0ecOhxaEgS3JvdXBh?= Cc: xen-devel@lists.xen.org References: <5490687.niJfEyVGOH@rivendell.hailstone.cz> <1f1cfdeb-adbd-420d-a187-d0007fcad123@suse.com> <4454038.v2OnDr8pfo@rivendell.hailstone.cz> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4454038.v2OnDr8pfo@rivendell.hailstone.cz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775557569-5FB3B3D8-6B705426/0/0 X-purgate-type: clean X-purgate-size: 938 On 07.04.2026 12:14, Matyáš Kroupa wrote: > Dne úterý 7. dubna 2026 11:05:40, středoevropský letní čas, Jan Beulich > napsal(a): >> Not exactly, there is an earlier exit from the function when num_roots is 0. >> If that line is the problem one, then presumably num_roots < num_nodes, thus >> yielding roots_per_node as 0. Sadly you didn't enable enough verbosity for >> >> pr_debug("Found %d AMD root devices\n", num_roots); >> >> to actually leave a trace in the log. I'd guess the value to be 1, but there >> being multiple nodes at the same time. You may want to instrument the >> function a little more to be certain. > > I booted it with either loglevel=8 or ignore_loglevel, but could not get the > pr_debug to output anything. It did however print a lot of pci and other debug > messages as expected. Iirc loglevel options don't affect pr_debug(); dynamic-printk options need using instead. Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:30:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:30:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274848.1560822 (Exim 4.92) (envelope-from ) id 1wA3hm-0007Ic-Nw; Tue, 07 Apr 2026 10:30:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274848.1560822; Tue, 07 Apr 2026 10:30:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3hm-0007IV-LH; Tue, 07 Apr 2026 10:30:46 +0000 Received: by outflank-mailman (input) for mailman id 1274848; Tue, 07 Apr 2026 10:30:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3hl-0007IP-Bm for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 10:30:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3hk-00Flbu-Nk for xen-devel@lists.xenproject.org; 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> > - if ( start > end || (end - start) > (UINT_MAX - *num_colors) || > - (*num_colors + (end - start)) >= max_num_colors ) > + if ( end >= NR_LLC_COLORS || start > end || > + (end - start) >= (UINT_MAX - *num_colors) || > + (*num_colors + (end - start + 1)) >= max_num_colors ) > return -EINVAL; > > /* Colors are range checked in check_colors() */ > I think this is correct, so Acked-by: Andrew Cooper However, the parsing logic is also ridiculous.  Most of the complexity comes because of parsing a bitmap but storing it longhand in an array of unsigned ints. Instead, the global variables default_colors, dom0_colors and xen_colors should be bitmaps sized by NR_LLC_COLORS, and d->llc_colours should be a bitmap sized by xen_num_colors (which itself is bound by NR_LLC_COLORS). With the default of 32 colours, this would involve no memory allocation at all, even on 32bit builds of Xen. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:34:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:34:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274858.1560831 (Exim 4.92) (envelope-from ) id 1wA3lj-0008Hn-7Z; Tue, 07 Apr 2026 10:34:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274858.1560831; Tue, 07 Apr 2026 10:34:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3lj-0008Hg-3t; Tue, 07 Apr 2026 10:34:51 +0000 Received: by outflank-mailman (input) for mailman id 1274858; Tue, 07 Apr 2026 10:34:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3lh-0008Ha-Eq for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Julien Grall , "Rahul Singh" , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 0/2] Final series to make Arm MISRA allcode green Date: Tue, 7 Apr 2026 12:34:31 +0200 Message-ID: <20260407103434.90838-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256F:EE_|SN7PR12MB8129:EE_ X-MS-Office365-Filtering-Correlation-Id: 9354d2c5-2aef-4520-51b8-08de94914754 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700016|13003099007|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: 3UVMJK7D7phlmZPR6yxBKqmHvLNzpmrtcpnmOyNdGbkICV3qumbqp/+n8CuNgpsM3+I+Q5hpgLU8xGgW1o4wZ4y8h12ndc3MT5EjO+1IXvVWizkPXxQ+D/4IfT84hfOwQxlac8lt+F5jMN/5x8LMdHfapEb1ARWXs6dPBScOBJXR7lG1VxXw3GBNzO4WDM741FJVyygUE32Hh5/nxR1jx1DHBf0peo5Jn1pp0jRloOPdU6Kj2rXf7SFh6RUOapzxi3n/q+Mc/QeeGESwMArfVm7rERKxtppA/id49+eIJ0SlMwr0R1rK0pnYFQEYU0i0dN/REulgOcn7n7RLgNIRTk11xhZSRos3WY22mHd5xmCdQPU3umaepZcoy5nbhMXnRmb6O/3/IqygH0kn8iz8glRCIy3o6UZt8C0tGb+bzMr06hY4u0GeakraHP/rokACY4vzhtV2KbL8SkbXQ3LufZRHMD8hudJVKLmV0/ImHWPzf1WUppMxKAVbJSPeRjdjygW2euLlCqat4TMr/3+LG7Iz9OfxKBjnwqgTemLyraConCBcOIp1KP7zPoXuv/DTkLpLi+kx5aFQqLfcVR1r++Rw3h/iPOOlrSkI+n4LxzzzJ6sxtME8Ow9ix4rQyVLdpgS2oArimuyDAdG0DqVN+Nsc0KoBnzwGE5pt/622FTfccG+Z4jcDtLBlBfntNAlQasuz4ErvZnl6IlweIoGl5DuqdyVMGpDEBrJeYqRYykI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700016)(13003099007)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cA+pluvGF2ujYmVSAntr2OEn3vRwcPx7R+6KTGzcifznC5SCIEyiMWC1/H/0SpjyQrx7bOtaUblwCbFjdKm6sZDURRQ2pu+DED0SfhpgowHIHjEnvHsTJHL4urYfPXC5W6g8iR6J1DjOUZh0XzXQM8RPn+EzKneJ3f3F0Cum8bS+xyNJkn6bsP0keETW8ljvWLHjf3IsGP0+cmqvaeorGBTNBOUZH9+l0nbSFPIVm44AOc7ZakxnZe5jaLzt0bAwM8lwdf9yp7FH5nQ4/ftEFqUFHD04k8sIwVNTPE/igswIQ3s1GdetHU/iOJSxtIFp8NHYq2VzmfolejTpc8B6+d5jbLmcGatc96wClDNpHnHAtGu567R1xVwNkmmSdE+XrR1sOIvyVAE/suWmGDe2feuXTJxhQMFCiTbE+ZUCnXgCJ95CselUX4bjqJ7quMCF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2026 10:34:42.0610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9354d2c5-2aef-4520-51b8-08de94914754 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8129 X-purgate-ID: tlsNG-bad1c0/1775558087-5D5EB152-D325D88C/0/0 X-purgate-type: clean X-purgate-size: 408 No more regressions for clean guidelines: https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 Michal Orzel (2): iommu/arm: smmu: Fix variable shadowing iommu/arm: ipmmu-vmsa: Fix variable shadowing xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- xen/drivers/passthrough/arm/smmu.c | 7 +++---- 2 files changed, 5 insertions(+), 8 deletions(-) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:34:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:34:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274859.1560839 (Exim 4.92) (envelope-from ) id 1wA3ll-0008VY-Do; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 2/2] iommu/arm: ipmmu-vmsa: Fix variable shadowing Date: Tue, 7 Apr 2026 12:34:33 +0200 Message-ID: <20260407103434.90838-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260407103434.90838-1-michal.orzel@amd.com> References: <20260407103434.90838-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022573:EE_|DM4PR12MB6398:EE_ X-MS-Office365-Filtering-Correlation-Id: d2d4ad18-a010-4583-496f-08de9491492c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 0SWErfz8ZB7oFhnH7++AZKjW6MMPL0SZiFPvvN2tynAuxZ5N9N6owEB6NplcF7eGCGOsYPOGTYBVnEPZhdfFGUsXu1Hi6by7dKfe8n8Qu95BEAXrdfJrRsaXMgTXan0Hk/PZXrKe6AT1tnTG7f+gMD9b2f/XxqCs9Ceoz8zHkgdw/uY6nkpG5eVpS0OS1d1/MIqMympkLVO7Kat6xEq/QltAfryzkqzCvVyypenOUPk+1+PGjF4f7iEj/pUanOH2uycQ/28DwbXxBYQ67ilWaXwWvKXvnJycadqeKPeWq9DI0WOZPXLYlA24sBvwuWRDahPz9Qf+bt7F38qkXQelxKZffySH00ob+aPmQ+dlw29q/14NV87eT0nRQ1J6RApdEfUQKR+JmjQ0jZShNXKIkprrlU5HVYj5ohWBJjvKXJcQ5/y5yGPV9Q8Nhb/zI+/xB043h34ySwf+aXY9znGGfn71bUOi27VX4v6AMBJj7RNWXPSGK8f5rajgbvkrSkM02aHkmy9VHjnaktYj3Afm73gHfC5BXeB/8CPhtJLqtG3fjM43vQpBnvq3uXT3K3Tou0pMGyQJo35eO0fDwbw0Jwga9Hr8GA8VPGZmGSeVI6k5ZtUqH3HOqD1DmyXwIOV9D+cryF1rJzaaus5ZCIVqFH+1VNfjFjZZ5Geydr+pNmMJA4ycXIZpGL40nZDttVI7+eXPUj1NKHhqLJTy8bafeeHUpLxTBcRwzuY2w/CDO4d43huWr7IlZeQo1v0OkJ1qWERc88JUtKz7/2F2Dvhl7w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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Remove the unused 'ret' declaration from ipmmu_assign_device() where the function-scope 'ret' is sufficient. This fixes MISRA C R5.3. Signed-off-by: Michal Orzel --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index ea9fa9ddf3ce..fa9ab9cb1330 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -65,8 +65,8 @@ printk(lvl "ipmmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ else \ { \ - struct pci_dev *pdev = dev_to_pci((dev)); \ - printk(lvl "ipmmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ + struct pci_dev *pci_dev = dev_to_pci((dev)); \ + printk(lvl "ipmmu: %pp: " fmt, &pci_dev->sbdf, ## __VA_ARGS__); \ } \ }) #endif @@ -1171,8 +1171,6 @@ static int ipmmu_assign_device(struct domain *d, u8 devfn, struct device *dev, /* dom_io is used as a sentinel for quarantined devices */ if ( d == dom_io ) { - int ret; - /* * Try to de-assign: do not return error if it was already * de-assigned. -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:34:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:34:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274860.1560849 (Exim 4.92) (envelope-from ) id 1wA3ln-0000Jp-PS; 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Remove the unused 'ret' declaration from arm_smmu_dt_add_device_generic() where the function-scope 'ret' is sufficient. Fix shadowing of 'domain' in arm_smmu_assign_dev() by removing the inner-scope redeclaration, using the function-scope variable instead. This fixes MISRA C R5.3. Signed-off-by: Michal Orzel --- xen/drivers/passthrough/arm/smmu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 22d306d0cb80..d63c9015510e 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -130,8 +130,8 @@ typedef enum irqreturn irqreturn_t; printk(lvl "smmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ else \ { \ - struct pci_dev *pdev = dev_to_pci((dev)); \ - printk(lvl "smmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ + struct pci_dev *pci_dev = dev_to_pci((dev)); \ + printk(lvl "smmu: %pp: " fmt, &pci_dev->sbdf, ## __VA_ARGS__); \ } \ }) #endif @@ -927,7 +927,6 @@ static int arm_smmu_dt_add_device_generic(u8 devfn, struct device *dev) if ( dev_is_pci(dev) ) { struct pci_dev *pdev = dev_to_pci(dev); - int ret; /* Ignore calls for phantom functions */ if ( devfn != pdev->devfn ) @@ -2788,7 +2787,7 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, /* dom_io is used as a sentinel for quarantined devices */ if ( d == dom_io ) { - struct iommu_domain *domain = dev_iommu_domain(dev); + domain = dev_iommu_domain(dev); if ( !iommu_quarantine ) return 0; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:37:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:37:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274883.1560858 (Exim 4.92) (envelope-from ) id 1wA3o6-0001Nx-45; Tue, 07 Apr 2026 10:37:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274883.1560858; Tue, 07 Apr 2026 10:37:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3o6-0001Nq-1B; Tue, 07 Apr 2026 10:37:18 +0000 Received: by outflank-mailman (input) for mailman id 1274883; Tue, 07 Apr 2026 10:37:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA3o5-0001NY-2b for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 10:37:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA3o4-004vN7-AN for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 12:37:16 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4de52-e002-0a2a0a5209dd-0a2a450b9d98-46 for ; Tue, 07 Apr 2026 12:37:16 +0200 Received: from [209.85.221.41] (helo=mail-wr1-f41.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4de5c-bca8-0a2a450b0019-d155dd29e101-3 for ; Tue, 07 Apr 2026 12:37:16 +0200 Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-43b87970468so3816833f8f.3 for ; Tue, 07 Apr 2026 03:37:16 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <884db6ba-19c3-4073-b1e4-631d286ec5d2@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775558236-17B402A1-49F9C31D/0/0 X-purgate-type: clean X-purgate-size: 2053 On 07.04.2026 12:30, Andrew Cooper wrote: > On 24/03/2026 4:37 pm, Jan Beulich wrote: >> We can easily avoid the risk of wrapping UINT_MAX <-> 0 by applying a >> check against the compile-time-constant maximum number of colors. >> >> Additionally the overflow checks suffered from an off-by-1, as the parsed >> ranges are inclusive (e.g. end == start being possible, requiring 1 array >> slot, while availability of 0 slots was checked in that case). >> >> Fixes: 6cdea3444eaf ("xen/arm: add Dom0 cache coloring support") >> Reported-by: Kamil Frankowicz >> Signed-off-by: Jan Beulich >> >> --- a/xen/common/llc-coloring.c >> +++ b/xen/common/llc-coloring.c >> @@ -76,8 +76,9 @@ static int __init parse_color_config(con >> else /* Single value */ >> end = start; >> >> - if ( start > end || (end - start) > (UINT_MAX - *num_colors) || >> - (*num_colors + (end - start)) >= max_num_colors ) >> + if ( end >= NR_LLC_COLORS || start > end || >> + (end - start) >= (UINT_MAX - *num_colors) || >> + (*num_colors + (end - start + 1)) >= max_num_colors ) >> return -EINVAL; >> >> /* Colors are range checked in check_colors() */ >> > > I think this is correct, so Acked-by: Andrew Cooper > Thanks. > However, the parsing logic is also ridiculous.  Most of the complexity > comes because of parsing a bitmap but storing it longhand in an array of > unsigned ints. > > Instead, the global variables default_colors, dom0_colors and xen_colors > should be bitmaps sized by NR_LLC_COLORS, and d->llc_colours should be a > bitmap sized by xen_num_colors (which itself is bound by NR_LLC_COLORS). > > With the default of 32 colours, this would involve no memory allocation > at all, even on 32bit builds of Xen. It's pretty space inefficient, yes, but the parsing wouldn't become simpler when using bitmaps, would it? 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There is an optional mmu-type property for each cpu: https://github.com/riscv-non-isa/riscv-device-tree-doc/blob/master/bindings/riscv/cpus.txt#L73 > >> To support this, make max_gstage_mode a global pointer to one of >> the entries in a global modes[] array, and remove get_max_supported_mode(). >> >> Update struct p2m_domain to store a pointer to a mode descriptor instead of >> embedding the structure directly. >> >> Refactor the modes[] array so that mode->name contains only the MMU scheme >> name (without the "x4" suffix), as this value is reused when filling the >> maximum MMU type passed to the guest. According to DT bindings [1], the MMU >> type must not include the "x4" suffix. Use "none" for the Bare mode to match >> the DT binding requirements. > > I expect this DT aspect is also why Sv changes to sv in the table? (Which > is a little unhelpful for the printk() where it's used.) Yes. According to the link above the following options could be passed: "riscv,sv32" "riscv,sv39" "riscv,sv48" > >> Adjust modes[]->paging_levels to represent the maximum paging level rather >> than the total number of levels. This ensures that P2M_ROOT_LEVEL() and its >> users behave correctly without relying on hardcoded p2m mode values. >> >> Finally, drop __initconst from the modes[] declaration, as the array is >> referenced via p2m->mode and max_gstage_mode beyond the init stage. >> >> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v6.19-rc3#n82 > > Is a reference into Linux doc really providing something "canonical"? Surely > there's an independent spec somewhere? I wasn't able to find better source for arch-specific definitions. For example, the source mentioned above has outdated mmu-type properties which should also contain riscv,sv57 and riscv,none. > >> --- a/xen/arch/riscv/p2m.c >> +++ b/xen/arch/riscv/p2m.c >> @@ -45,18 +45,32 @@ struct p2m_pte_ctx { >> unsigned int level; /* Paging level at which the PTE resides. */ >> }; >> >> -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { >> - .mode = HGATP_MODE_OFF, >> - .paging_levels = 0, >> - .name = "Bare", >> -}; >> - >> /* >> * Set to the maximum configured support for IPA bits, so the number of IPA bits can be >> * restricted by external entity (e.g. IOMMU). >> */ >> unsigned int __read_mostly p2m_ipa_bits = PADDR_BITS; >> >> +static const struct gstage_mode_desc modes[] = { > > As a function scope static this was a fine identifier. Please consider whether > with the wider scope gstage_modes[] might not be better. > >> + /* >> + * Based on the RISC-V spec: >> + * Bare mode is always supported, regardless of SXLEN. >> + * When SXLEN=32, the only other valid setting for MODE is Sv32. >> + * When SXLEN=64, three paged virtual-memory schemes are defined: >> + * Sv39, Sv48, and Sv57. >> + */ >> + [0] = { HGATP_MODE_OFF, 0, "none" }, >> +#ifdef CONFIG_RISCV_32 >> + [1] = { HGATP_MODE_SV32X4, 1, "sv32" } >> +#else >> + [2] = { HGATP_MODE_SV39X4, 2, "sv39" }, >> + [3] = { HGATP_MODE_SV48X4, 3, "sv48" }, >> + [4] = { HGATP_MODE_SV57X4, 4, "sv57" }, >> +#endif >> +}; > > The dedicated initializer form isn't adding any value here (whereas it slightly > hampers readability). You really don't want the array to be sparsely populated, > so perhaps better to leave as it was before? I need modes[] to be outside of gstage_mode_detect() as it then could be re-used. For example, if expected G-stage mode should be passed by DTS property then in DTS property we'll have something like: chosen { ... DOMU1 { mmu-type="riscv,sv48"; ... } ... } And I will need to have another functions something like: static unsigned int find_gstage_mode(const char *mmu_type) {...} which will re-use modes[] to find a correspondent mode and return an index (or return just correspondent mode) for that mode to then re-use it to initialize p2m->mode: p2m->mode = &modes[find_gstage_mode(mmu_type)]; ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 07 10:52:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 10:52:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274904.1560876 (Exim 4.92) (envelope-from ) id 1wA42t-00052L-MW; Tue, 07 Apr 2026 10:52:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274904.1560876; Tue, 07 Apr 2026 10:52:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA42t-00052E-Ji; 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>>> >>> - if ( start > end || (end - start) > (UINT_MAX - *num_colors) || >>> - (*num_colors + (end - start)) >= max_num_colors ) >>> + if ( end >= NR_LLC_COLORS || start > end || >>> + (end - start) >= (UINT_MAX - *num_colors) || >>> + (*num_colors + (end - start + 1)) >= max_num_colors ) >>> return -EINVAL; >>> >>> /* Colors are range checked in check_colors() */ >>> >> I think this is correct, so Acked-by: Andrew Cooper >> > Thanks. > >> However, the parsing logic is also ridiculous.  Most of the complexity >> comes because of parsing a bitmap but storing it longhand in an array of >> unsigned ints. >> >> Instead, the global variables default_colors, dom0_colors and xen_colors >> should be bitmaps sized by NR_LLC_COLORS, and d->llc_colours should be a >> bitmap sized by xen_num_colors (which itself is bound by NR_LLC_COLORS). >> >> With the default of 32 colours, this would involve no memory allocation >> at all, even on 32bit builds of Xen. > It's pretty space inefficient, yes, but the parsing wouldn't become simpler > when using bitmaps, would it? Yes it would. The current logic has opencoded bitmap helpers, and removing *num_colors simplifies all the boundary conditions (you simply don't need a cursor when collecting into a real bitmap.) ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 07 11:27:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 11:27:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274916.1560886 (Exim 4.92) (envelope-from ) id 1wA4ad-000185-Ai; Tue, 07 Apr 2026 11:27:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274916.1560886; Tue, 07 Apr 2026 11:27:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA4ad-00017y-6D; Tue, 07 Apr 2026 11:27:27 +0000 Received: by outflank-mailman (input) for mailman id 1274916; Tue, 07 Apr 2026 11:27:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA4ab-00017e-Oo for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <7ea3a5d8-f9ff-4296-9b3e-07b9ba184e6f@amd.com> Date: Tue, 7 Apr 2026 07:27:16 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arinc653: don't assume Dom0 is the control domain To: Jan Beulich CC: Nathan Studer , Stewart Hildebrand , "xen-devel@lists.xenproject.org" , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= References: <89d17a24-0a1f-4f3f-ac2f-f3701a8d78dd@suse.com> <4a4c011e-9666-4416-be1b-33d1dcad5afe@suse.com> <73e51afc-ae7c-4d08-9054-75dab660bf42@suse.com> <4dfd48a9-37c1-4f28-87f3-19646a339b08@suse.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: <4dfd48a9-37c1-4f28-87f3-19646a339b08@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: None (SATLEXMB04.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468D:EE_|CH3PR12MB9454:EE_ X-MS-Office365-Filtering-Correlation-Id: f53c86a0-05db-409c-32a7-08de94989f48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|30052699003|82310400026|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tETvIO5kuCuTVuletiykbkKwrx8IHcOi+8qcPmxqdIr06yzFITnHvyODfS5FDGIw9c7+q1cyAZsM8T/hKcu2nv+A3B6kY5OWGNKXy8gwO/A9wnIOskV92k4lFHxkq7Xkc2UaOwYmc6XnQecBDlrMQRzrZg/E7ApQPSeauCrAxYUIGhMD/jfkA6j0yMDSj4pfsgDLmkLWhrhCdT7DS8wEpelu9jj8145P2sHEpagJUhlAQ+PgF1z34xNibN3KVHTCTS7scKk7rFrnGYFh1WlkKFfcC3LjTpl3z5m49+E7G7CDei2rKAAOQCfouBBR3teSIpzsQE2akk0Aon0tIw1Q8O6wi9yvLTuC4qgPIAD7ET2iPQVEgUJ8hkBh54SNREhNekCvTSVvi0bOkJFcK0+72b4fEOOmdJB6mcDrW5CWHUXxMG8Wz0H6X4DyB/TKRIcM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Apr 2026 11:27:16.1041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f53c86a0-05db-409c-32a7-08de94989f48 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9454 X-purgate-ID: tlsNG-720697/1775561244-AD53CCD1-50166499/0/0 X-purgate-type: clean X-purgate-size: 4815 On 4/7/26 02:18, Jan Beulich wrote: > On 03.04.2026 10:47, Stewart Hildebrand wrote: >> On 4/1/26 09:03, Jan Beulich wrote: >>> On 01.04.2026 14:57, Jürgen Groß wrote: >>>> On 01.04.26 14:29, Jan Beulich wrote: >>>>> Leaving aside highly disaggregated environments, the control domain is >>>>> what will invoke XEN_SYSCTL_SCHEDOP_putinfo. Its vCPU-s therefore need to >>>>> be able to run unconditionally, not those of the domain with ID 0 (which >>>>> may not exist at all). >>>>> >>>>> Fixes: 9f0c658baedc ("arinc: add cpu-pool support to scheduler") >>>>> Signed-off-by: Jan Beulich >>>>> --- >>>>> There being no "else" to the if(), what about other control domain vCPU-s? >>>> >>>> I guess this is a stale leftover. Doesn't matter for committing anyway. >>>> >>>>> --- >>>>> v3: Don't mistakenly include the idle domain. >>>>> v2: New. >>>>> >>>>> --- a/xen/common/sched/arinc653.c >>>>> +++ b/xen/common/sched/arinc653.c >>>>> @@ -411,10 +411,10 @@ a653sched_alloc_udata(const struct sched >>>>> spin_lock_irqsave(&sched_priv->lock, flags); >>>>> >>>>> /* >>>>> - * Add every one of dom0's units to the schedule, as long as there are >>>>> - * slots available. >>>>> + * Add every one of the control domain's units to the schedule, as long as >>>>> + * there are slots available. >>>>> */ >>>>> - if ( unit->domain->domain_id == 0 ) >>>>> + if ( is_control_domain(unit->domain) && !is_idle_domain(unit->domain) ) >>>>> { >>>>> entry = sched_priv->num_schedule_entries; >>>>> >>>> >>>> Hmm, is it really the control domain only which wants to be scheduled initially? >>>> I would think that at least the hardware domain and probably a Xenstore domain >>>> would want to be included, too. >>>> >>>> In the end it might even be that other domains created via dom0less would want >>>> to be able to run initially. They could be part of a mandatory infrastructure. >>>> Why would they need to be created at boot if they are NOT important? >>> >>> This part is easy to answer: Because in a dom0less setup you simply may have >>> no toolstack at all. (At which point there may also be nothing to set a >>> schedule, yes.) >> >> This is a known limitation. In a dom0less/hyperlaunch scenario, as future work, >> I would like to see the ability to configure the ARINC653 schedule in device >> tree, which would likely extend the existing boot time cpu pool work. >> >>>> The question is whether the arinc653 scheduler is really meant for such setups. >>>> OTOH just modifying the test to: >>>> >>>> if ( system_state < SYS_STATE_active && >>>> unit->domain->domain_id < DOMID_FIRST_RESERVED ) >>>> >>>> seems to be fine for catching all those cases. >>>> >>>> With or without this modification: >>>> >>>> Reviewed-by: Juergen Gross >>> >>> Thanks, yet I'll have to leave to the maintainers to decide which form it >>> should ultimately take. One remark: A restartable control domain wouldn't >>> pass that conditional. Granted that's looking far into the future. >> >> It may not be desirable to schedule domUs until the control domain has had a say >> in the matter, considering that the default schedule is unlikely to contain the >> desired minor frame runtimes. It's less clear whether to include hardware and >> xenstore domains in the default schedule, though I'm leaning toward only >> including the domain with ability to invoke XEN_SYSCTL_SCHEDOP_putinfo for now >> (i.e. the control domain). >> >> Hm, the suggested 'system_state < SYS_STATE_active' check is possibly a good >> addition. This reinforces that the default schedule's purpose is merely to get a >> system booting until a user-provided schedule can be installed. Without this >> check, restarting the control domain could result in new entries being added >> while old entries remain, possibly ending up with duplicates and/or exhausting >> the schedule. However, the restarted domain would need to retain its uuid if it >> expects to be scheduled after restart. >> >> Lastly, we may consider restricting the default schedule to Pool-0, and >> eventually we may want a mechanism to disable the default schedule altogether >> (e.g. when boot time cpupools are in use), but I don't think it's necessary to >> conflate those with the current patch. > > So what does all of this mean for the patch here? Should I switch to Jürgen's > suggestion? Should I merely add the system_state check, but otherwise keep as > is? Or should I not change anything? I think the patch is good as is, but I just want to give it a few more days to give Nate or others a chance to chime in. I'll follow up next week if there's no further discussion. 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="r45afIgNHStFFFQy" Content-Disposition: inline In-Reply-To: <8c9e5404-24bf-410d-a2e8-551cb87c6400@suse.com> X-purgate-ID: tlsNG-d25034/1775561687-8274EA3D-2A28951C/0/0 X-purgate-type: clean X-purgate-size: 9874 --r45afIgNHStFFFQy Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 7 Apr 2026 13:34:43 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Tue, Apr 07, 2026 at 12:23:16PM +0200, Jan Beulich wrote: > On 07.04.2026 08:29, Jan Beulich wrote: > > On 03.04.2026 01:06, Marek Marczykowski-G=C3=B3recki wrote: > >> On Thu, Apr 02, 2026 at 04:53:31PM +0200, Jan Beulich wrote: > >>> Sadly you now log the low halves of HPET_Tn_ROUTE twice, while you do= n't log > >>> the high halves at all. > >> > >> I was missing hpet_read32 there... > >> > >> Updated: > >> (XEN) [ 116.921573] Entering ACPI S3 state. > >> (XEN) [18446743895.088893] _disable_pit_irq:2649: using_pit: 0, cpu_ha= s_apic: 1 > >> (XEN) [18446743895.088907] _disable_pit_irq:2659: cpuidle_using_deep_c= state: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > >> (XEN) [18446743895.088918] _disable_pit_irq:2662: init: 0 > >> (XEN) [18446743895.088928] hpet_broadcast_resume:662: hpet_events: fff= f83046bc1f080 > >> (XEN) [18446743895.089072] hpet_broadcast_resume:673: num_hpets_used: 8 > >> (XEN) [18446743895.089081] hpet_broadcast_resume:691: cfg: 0x1 > >> (XEN) [18446743895.089092] hpet_broadcast_resume:696: i:0, hpet_events= [i].msi.irq: 122, hpet_events[i].flags: 0 > >> (XEN) [18446743895.089122] hpet_msi_write:286: iommu_update_ire_from_m= si rc: 0 > >> (XEN) [18446743895.089132] hpet_broadcast_resume:700: i:0, __hpet_setu= p_msi_irq ret: 0 > >> (XEN) [18446743895.089168] hpet_broadcast_resume:710: i:0, cfg: 0xc134= , hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_RO= UTE(hpet_events[i].idx) + 4): 0xf18 > >=20 > > Okay, this would appear to clarify that the address really isn't correc= t. Yet I'm > > confused now by the low half values: In your earlier log there was > >=20 > > hpet_broadcast_resume:710: i:0, cfg: 0xc134, HPET_Tn_ROUTE(hpet_events[= i].idx): 0x110 > >=20 > > and alike, i.e. clearly a non-zero value. Now all low halves are zero. = I'll try > > to figure how the logged values here could result, but consistent data = (or an > > explantation for the apparent inconsistency) would help. >=20 > Could you give the patch below a try? >=20 > Jan >=20 > x86/HPET: channel handling in hpet_broadcast_resume() >=20 > The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() > and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for > the (possible) channel put in legacy mode we don't do so during boot > either. >=20 > Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an > all-zero message (when the passed in CPU mask has no online CPUs). Nothing > would later call msi_compose_msg() / hpet_msi_write(), and hence nothing > would later produce a well-formed message template in > hpet_events[].msi.msg. >=20 > Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") > Reported-by: Marek Marczykowski-G=C3=B3recki > Signed-off-by: Jan Beulich This appears to fix the IOMMU faults. Started with no-arat, the debug output is now this: (XEN) [18446743900.509455] _disable_pit_irq:2649: using_pit: 0, cpu_has_api= c: 1 (XEN) [18446743900.509470] _disable_pit_irq:2659: cpuidle_using_deep_cstate= : 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 (XEN) [18446743900.509480] _disable_pit_irq:2662: init: 0 (XEN) [18446743900.509491] hpet_broadcast_resume:662: hpet_events: ffff8304= 61b3f080 (XEN) [18446743900.509636] hpet_broadcast_resume:673: num_hpets_used: 8 (XEN) [18446743900.509644] hpet_broadcast_resume:691: cfg: 0x1 (XEN) [18446743900.509656] hpet_broadcast_resume:696: i:0, hpet_events[i].m= si.irq: 122, hpet_events[i].flags: 0 (XEN) [18446743900.509687] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.509698] hpet_broadcast_resume:705: i:0, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.509728] hpet_broadcast_resume:715: i:0, cfg: 0xc130, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00f18 (XEN) [18446743900.509739] hpet_broadcast_resume:696: i:1, hpet_events[i].m= si.irq: 123, hpet_events[i].flags: 0 (XEN) [18446743900.509762] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.509772] hpet_broadcast_resume:705: i:1, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.509803] hpet_broadcast_resume:715: i:1, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00f38 (XEN) [18446743900.509814] hpet_broadcast_resume:696: i:2, hpet_events[i].m= si.irq: 124, hpet_events[i].flags: 0 (XEN) [18446743900.509838] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.509848] hpet_broadcast_resume:705: i:2, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.509877] hpet_broadcast_resume:715: i:2, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00f58 (XEN) [18446743900.509888] hpet_broadcast_resume:696: i:3, hpet_events[i].m= si.irq: 125, hpet_events[i].flags: 0 (XEN) [18446743900.509912] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.509922] hpet_broadcast_resume:705: i:3, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.509952] hpet_broadcast_resume:715: i:3, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00f78 (XEN) [18446743900.509963] hpet_broadcast_resume:696: i:4, hpet_events[i].m= si.irq: 126, hpet_events[i].flags: 0 (XEN) [18446743900.509987] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.509997] hpet_broadcast_resume:705: i:4, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.510027] hpet_broadcast_resume:715: i:4, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00f98 (XEN) [18446743900.510038] hpet_broadcast_resume:696: i:5, hpet_events[i].m= si.irq: 127, hpet_events[i].flags: 0 (XEN) [18446743900.510062] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.510072] hpet_broadcast_resume:705: i:5, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.510102] hpet_broadcast_resume:715: i:5, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00fb8 (XEN) [18446743900.510113] hpet_broadcast_resume:696: i:6, hpet_events[i].m= si.irq: 128, hpet_events[i].flags: 0 (XEN) [18446743900.510138] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.510149] hpet_broadcast_resume:705: i:6, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.510179] hpet_broadcast_resume:715: i:6, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00fd8 (XEN) [18446743900.510191] hpet_broadcast_resume:696: i:7, hpet_events[i].m= si.irq: 129, hpet_events[i].flags: 0 (XEN) [18446743900.510214] hpet_msi_write:286: iommu_update_ire_from_msi rc= : 0 (XEN) [18446743900.510224] hpet_broadcast_resume:705: i:7, __hpet_setup_msi= _irq ret: 0 (XEN) [18446743900.510253] hpet_broadcast_resume:715: i:7, cfg: 0xc100, hpe= t_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(h= pet_events[i].idx) + 4): 0xfee00ff8 > --- > As to the Fixes: tag: The issue for the HPET resume case is the > cpumask_intersects(desc->arch.cpu_mask, &cpu_online_map) check in > msi_compose_msg(). The earlier cpumask_empty() wasn't a problem, as > cpu_mask_to_apicid() returning a bogus (offline) value didn't have any bad > effect: Before use, a valid destination would have been put in place, but > other parts of .msg were properly set up. Furthermore we also didn't clear > the entire message prior to that change. >=20 > --- a/xen/arch/x86/hpet.c > +++ b/xen/arch/x86/hpet.c > @@ -685,12 +685,18 @@ void hpet_broadcast_resume(void) > for ( i =3D 0; i < n; i++ ) > { > if ( hpet_events[i].msi.irq >=3D 0 ) > + { > + struct irq_desc *desc =3D irq_to_desc(hpet_events[i].msi.irq= ); > + > + cpumask_copy(desc->arch.cpu_mask, cpumask_of(smp_processor_i= d())); > + > __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); > + } > =20 > /* set HPET Tn as oneshot */ > cfg =3D hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); > cfg &=3D ~(HPET_TN_LEVEL | HPET_TN_PERIODIC); > - cfg |=3D HPET_TN_ENABLE | HPET_TN_32BIT; > + cfg |=3D HPET_TN_32BIT; > if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) > cfg |=3D HPET_TN_FSB; > hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --r45afIgNHStFFFQy Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnU69MACgkQ24/THMrX 1yzXvAf7B0UW9UyjQV7OjCvh48ZppaP+IhfIwk44lYnzr5XBxaYw8ciZHmA7ejYg dweE0Np/WVgZcN+54TkDoc7nVKcABG7OvW11itmFhqTsUmljWwXSETQEqexgQb9m Hu2LtbKIuUCn3yCOfEblwSmrs6VLie0g68isAXnA1KkiuNMAIIuUBty4PrRMm3g+ CVsuLLNYZ8/oFQNgAdPm90VxHDk5Kq2SvNiOEk4aFRSTh00TJp9g/edof4h+Q8dq rrZMMdXUaKWJpAhrNNnHNkrbTLQjiHuDpX+JMTx/he9p7wv+GY8AIdxfIYCJZ12y hMGhfX86/B/M8hxllmrJOAl4Z0XXIw== =wqQI -----END PGP SIGNATURE----- --r45afIgNHStFFFQy-- From xen-devel-bounces@lists.xenproject.org Tue Apr 07 11:52:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 11:52:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274937.1560902 (Exim 4.92) (envelope-from ) id 1wA4yg-0005nx-G3; Tue, 07 Apr 2026 11:52:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274937.1560902; Tue, 07 Apr 2026 11:52:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA4yg-0005nq-DD; Tue, 07 Apr 2026 11:52:18 +0000 Received: by outflank-mailman (input) for mailman id 1274937; Tue, 07 Apr 2026 11:52:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA4ye-0005nk-UK for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 11:52:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA4ye-00BrlQ-A3 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 13:52:16 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d4efed-2eae-0a2a0a5409dd-0a2a4507c88a-12 for ; Tue, 07 Apr 2026 13:52:16 +0200 Received: from [209.85.221.43] (helo=mail-wr1-f43.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d4efef-ba2d-0a2a45070019-d155dd2ba5b1-3 for ; Tue, 07 Apr 2026 13:52:15 +0200 Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-43cf5fbacc9so2375064f8f.1 for ; Tue, 07 Apr 2026 04:52:15 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 07 Apr 2026 04:52:14 -0700 (PDT) Message-ID: <9a5a290f-0abb-4afb-b58d-da21b40ac761@suse.com> Date: Tue, 7 Apr 2026 13:52:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: IOMMU faults after S3 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: xen-devel References: <933a3e95-33d2-4e20-a4d5-2d8b20c2da7f@suse.com> <2caff339-4ce9-42ea-9b78-afeac42b6f0f@suse.com> <92e0151b-3fb1-4108-9788-f0fbac43512b@suse.com> <47b140b2-596b-47db-9c0c-43672f445036@suse.com> <8c9e5404-24bf-410d-a2e8-551cb87c6400@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775562735-8895941E-9347A65A/0/0 X-purgate-type: clean X-purgate-size: 5423 On 07.04.2026 13:34, Marek Marczykowski-Górecki wrote: > On Tue, Apr 07, 2026 at 12:23:16PM +0200, Jan Beulich wrote: >> x86/HPET: channel handling in hpet_broadcast_resume() >> >> The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() >> and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for >> the (possible) channel put in legacy mode we don't do so during boot >> either. >> >> Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an >> all-zero message (when the passed in CPU mask has no online CPUs). Nothing >> would later call msi_compose_msg() / hpet_msi_write(), and hence nothing >> would later produce a well-formed message template in >> hpet_events[].msi.msg. >> >> Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") >> Reported-by: Marek Marczykowski-Górecki >> Signed-off-by: Jan Beulich > > This appears to fix the IOMMU faults. > Started with no-arat, the debug output is now this: Same question here: May I translate this to Tested-by:? Jan > (XEN) [18446743900.509455] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [18446743900.509470] _disable_pit_irq:2659: cpuidle_using_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 0 > (XEN) [18446743900.509480] _disable_pit_irq:2662: init: 0 > (XEN) [18446743900.509491] hpet_broadcast_resume:662: hpet_events: ffff830461b3f080 > (XEN) [18446743900.509636] hpet_broadcast_resume:673: num_hpets_used: 8 > (XEN) [18446743900.509644] hpet_broadcast_resume:691: cfg: 0x1 > (XEN) [18446743900.509656] hpet_broadcast_resume:696: i:0, hpet_events[i].msi.irq: 122, hpet_events[i].flags: 0 > (XEN) [18446743900.509687] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.509698] hpet_broadcast_resume:705: i:0, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.509728] hpet_broadcast_resume:715: i:0, cfg: 0xc130, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00f18 > (XEN) [18446743900.509739] hpet_broadcast_resume:696: i:1, hpet_events[i].msi.irq: 123, hpet_events[i].flags: 0 > (XEN) [18446743900.509762] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.509772] hpet_broadcast_resume:705: i:1, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.509803] hpet_broadcast_resume:715: i:1, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00f38 > (XEN) [18446743900.509814] hpet_broadcast_resume:696: i:2, hpet_events[i].msi.irq: 124, hpet_events[i].flags: 0 > (XEN) [18446743900.509838] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.509848] hpet_broadcast_resume:705: i:2, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.509877] hpet_broadcast_resume:715: i:2, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00f58 > (XEN) [18446743900.509888] hpet_broadcast_resume:696: i:3, hpet_events[i].msi.irq: 125, hpet_events[i].flags: 0 > (XEN) [18446743900.509912] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.509922] hpet_broadcast_resume:705: i:3, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.509952] hpet_broadcast_resume:715: i:3, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00f78 > (XEN) [18446743900.509963] hpet_broadcast_resume:696: i:4, hpet_events[i].msi.irq: 126, hpet_events[i].flags: 0 > (XEN) [18446743900.509987] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.509997] hpet_broadcast_resume:705: i:4, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.510027] hpet_broadcast_resume:715: i:4, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00f98 > (XEN) [18446743900.510038] hpet_broadcast_resume:696: i:5, hpet_events[i].msi.irq: 127, hpet_events[i].flags: 0 > (XEN) [18446743900.510062] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.510072] hpet_broadcast_resume:705: i:5, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.510102] hpet_broadcast_resume:715: i:5, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00fb8 > (XEN) [18446743900.510113] hpet_broadcast_resume:696: i:6, hpet_events[i].msi.irq: 128, hpet_events[i].flags: 0 > (XEN) [18446743900.510138] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.510149] hpet_broadcast_resume:705: i:6, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.510179] hpet_broadcast_resume:715: i:6, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00fd8 > (XEN) [18446743900.510191] hpet_broadcast_resume:696: i:7, hpet_events[i].msi.irq: 129, hpet_events[i].flags: 0 > (XEN) [18446743900.510214] hpet_msi_write:286: iommu_update_ire_from_msi rc: 0 > (XEN) [18446743900.510224] hpet_broadcast_resume:705: i:7, __hpet_setup_msi_irq ret: 0 > (XEN) [18446743900.510253] hpet_broadcast_resume:715: i:7, cfg: 0xc100, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx)): 0, hpet_read32(HPET_Tn_ROUTE(hpet_events[i].idx) + 4): 0xfee00ff8 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 11:56:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 11:56:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274946.1560912 (Exim 4.92) (envelope-from ) id 1wA52n-0006LY-W1; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="+vHHedGGbCLoiHVv" Content-Disposition: inline In-Reply-To: <9a5a290f-0abb-4afb-b58d-da21b40ac761@suse.com> X-purgate-ID: tlsNG-ef75cf/1775562991-1059641E-8B96A51C/0/0 X-purgate-type: clean X-purgate-size: 2348 --+vHHedGGbCLoiHVv Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 7 Apr 2026 13:56:27 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel Subject: Re: IOMMU faults after S3 On Tue, Apr 07, 2026 at 01:52:18PM +0200, Jan Beulich wrote: > On 07.04.2026 13:34, Marek Marczykowski-G=C3=B3recki wrote: > > On Tue, Apr 07, 2026 at 12:23:16PM +0200, Jan Beulich wrote: > >> x86/HPET: channel handling in hpet_broadcast_resume() > >> > >> The per-channel ENABLE bit is to solely be driven by hpet_enable_chann= el() > >> and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except = for > >> the (possible) channel put in legacy mode we don't do so during boot > >> either. > >> > >> Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an > >> all-zero message (when the passed in CPU mask has no online CPUs). Not= hing > >> would later call msi_compose_msg() / hpet_msi_write(), and hence nothi= ng > >> would later produce a well-formed message template in > >> hpet_events[].msi.msg. > >> > >> Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") > >> Reported-by: Marek Marczykowski-G=C3=B3recki > >> Signed-off-by: Jan Beulich > >=20 > > This appears to fix the IOMMU faults. > > Started with no-arat, the debug output is now this: >=20 > Same question here: May I translate this to Tested-by:? Yes. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --+vHHedGGbCLoiHVv Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnU8OsACgkQ24/THMrX 1ywIuwf/duVlrhOTtwSFrltnWpHalptZacYYoSRQwBkreihrEfqr4Icopn2SQk1G NqJp5CGwZJjm67CxAtrs0XObNTHte9fuffbZigRQ3yFX2JV651APMSS+GymYROre gf3N9lv8Gq3HDJk+yjMk4MyH6pKtHOi0TNR0qm5FVhJlrfr+JvObm17ZPi5c5Oon 0hfQ77vMgKTQQF8KTd791WqW3nfZWfmjWlhLsQyrOfcipwcojdFrDXxz/7trgBwC jfNOJ+aazX8p00JB+LXq+khG1HqduN7ipu2qG8ks3BdmHPdR4PkDHQCJPDq9Vh7b eVsGXsSQ+/uN/GCTwjkE6E+xZ4dxgQ== =TLG8 -----END PGP SIGNATURE----- --+vHHedGGbCLoiHVv-- From xen-devel-bounces@lists.xenproject.org Tue Apr 07 12:01:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 12:01:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274956.1560922 (Exim 4.92) (envelope-from ) id 1wA57Y-0007x7-MM; Tue, 07 Apr 2026 12:01:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274956.1560922; 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Message-ID: References: <29775afa-e17b-4c44-a2a8-4ef4bc7cdf0f@suse.com> <88c65ec7-b7f7-4d8b-a453-d707440b43cb@suse.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bQ5tYmjyiuSDb3TB" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-d25034/1775563285-FDD53A3D-8C6BA6C1/0/0 X-purgate-type: clean X-purgate-size: 5634 --bQ5tYmjyiuSDb3TB Content-Type: multipart/mixed; protected-headers=v1; boundary="JAoCyMYCO6UJ7qb2" Content-Disposition: inline Date: Tue, 7 Apr 2026 14:01:20 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: xen-devel , =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: Slow (higher scheduling latency?) system after S3 - regression 4.17 -> 4.19 ? --JAoCyMYCO6UJ7qb2 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Apr 07, 2026 at 08:14:42AM +0200, Jan Beulich wrote: > On 03.04.2026 15:55, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Apr 02, 2026 at 03:02:15PM +0200, Marek Marczykowski-G=C3=B3rec= ki wrote: > >> On Fri, Mar 27, 2026 at 01:47:55PM +0100, Marek Marczykowski-G=C3=B3re= cki wrote: > >>> Some further observation, this time regarding timers: > >> > >> In the meantime Roger suggested it might be about C-states. So, I just > >> tried booting with max_cstate=3D0. I got this: > >=20 > > We had a design session on this issue, and managed to find (thanks Roge= r!) > > that adding: > >=20 > > tsc_mode=3D'always_emulate' > >=20 > > to the domU config fixes the issue. Now, the question is how to fix it > > properly... >=20 > Seeing also the remarks on Matrix, what we will hence need to figure is w= hat > TSC parameters (of the system and/or the VM) change across suspend. As per > Matrix everything looked at so far was apparently stable. I added some more logging (based on=20 https://sandpile.org/x86/msr.htm | grep TSC) - see attached debug patch. The output before and after S3: =3D=3D> msr-before.txt <=3D=3D (XEN) [ 118.910886] MSR 00000010: 000000cd6d18d6c1 (XEN) [ 118.911110] MSR 0000003b: 0000000000000000 (XEN) [ 118.911331] MSR c0000103: 0000000000000000 (XEN) [ 118.911559] Fixup #GP[0000]: ffff82d04029ad8d [arch/x86/cpu/in= tel.c#debug_tsc+0x76/0x84] -> ffff82d04029ad83 (XEN) [ 118.912029] MSR 000006e0: 0000000000000000 (XEN) [ 118.912253] MSR 000000e7: 000000064cf8ec5e (XEN) [ 118.912473] MSR 000000e8: 000000065d09c019 (XEN) [ 118.912687] MSR 0000064e: 000000052ec83116 =3D=3D> msr-after.txt <=3D=3D (XEN) [ 146.396099] MSR 00000010: 00000012fac68ccd (XEN) [ 146.396329] MSR 0000003b: 0000000000000000 (XEN) [ 146.396553] MSR c0000103: 0000000000000000 (XEN) [ 146.396777] Fixup #GP[0000]: ffff82d04029ad8d [arch/x86/cpu/in= tel.c#debug_tsc+0x76/0x84] -> ffff82d04029ad83 (XEN) [ 146.397248] MSR 000006e0: 0000000000000000 (XEN) [ 146.397470] MSR 000000e7: 00000001e41a578a (XEN) [ 146.397690] MSR 000000e8: 000000017dc5b211 (XEN) [ 146.397909] MSR 0000064e: 000000014eddbe8f Nothing interesting here... What other values would make sense to compare? --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --JAoCyMYCO6UJ7qb2 Content-Type: text/plain; charset=utf-8 Content-Disposition: attachment; filename=0001-DEBUG-TSC.patch Content-Transfer-Encoding: quoted-printable =46rom 2d1bd9c15e605136c7817fe824a7c429cbfb137d Mon Sep 17 00:00:00 2001 =46rom: =3D?UTF-8?q?Marek=3D20Marczykowski-G=3DC3=3DB3recki?=3D Date: Tue, 7 Apr 2026 13:55:41 +0200 Subject: [PATCH] DEBUG TSC --- xen/arch/x86/cpu/intel.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 51a3d1c4b5f3..846c6a704a3f 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -4,6 +4,7 @@ #include #include #include +#include =20 #include #include @@ -675,3 +676,30 @@ void __init intel_init_arat(void) if ( opt_arat && cpu_has_arat ) setup_force_cpu_cap(X86_FEATURE_XEN_ARAT); } + +static void cf_check debug_tsc(unsigned char key) +{ + uint64_t val; + int msr_idx[] =3D { 0x10, // TSC + 0x3b, // TSC_ADJUST + 0xc0000103, // TSC_AUX + 0xc0000104, // TSC_RATIO + 0x06e0, // TSC_DEADLINE + 0xe7, // MPERF + 0xe8, // APERF + 0x64e, // PPERF + 0 }; + + for ( int i =3D 0; msr_idx[i]; i++ ) + { + if ( !rdmsr_safe(msr_idx[i], &val) ) + printk("MSR %08x: %016lx\n", msr_idx[i], val); + } +} + +static int __init cf_check register_debug_tsc(void) +{ + register_keyhandler('1', debug_tsc, "Extra TSC debug", false); + return 0; +} +__initcall(register_debug_tsc); --=20 2.53.0 --JAoCyMYCO6UJ7qb2-- --bQ5tYmjyiuSDb3TB Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnU8hAACgkQ24/THMrX 1ywuIAgAm1QhozTGwws97jc5c+BB2Y8ViruL769uzkNd24Hr1BZJBtDsOSlVwQWW Oz25zIA47k2toJD+veU4KYTNgWUW/OACkiQMW/0F2ozYIRXqBSYmwDOip+jFQaMo LoOh+G6KUKmLLsjbdrrPMr+rB1kl8Udl/Qcdct69/GOp/iEQFIS91suQjN2VlSiJ ojNyhyTpPWuIwUrs/83f3MPz1jr+JMHN476L6fyhftMf5SayguMtDDHRIQlnzK4w 5r44nVFvHT914TomqGePOgoINLGSkPgVbAcr7gnbzFlJAkfASQNvwU14MimmGyFn ZKhKNw0bfgdBhix6X/HR9GxFfaUkZg== =sP3B -----END PGP SIGNATURE----- --bQ5tYmjyiuSDb3TB-- From xen-devel-bounces@lists.xenproject.org Tue Apr 07 12:49:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 12:49:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274972.1560929 (Exim 4.92) (envelope-from ) id 1wA5ro-0005Ja-1Z; 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h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=XBhl/6GqAkL8d+rCqjrRRK3sBt6sW2T0Uhx1QbOr1A6z9bKKZo5Zbe+BUHswkfpRK e8hBzCPj7JE6iWCidEmhHWpWsJ+qu9+IvxgbPxW9PvrszZe6lSnFY7PohrscItGvCD diGOr/yAjnUphg/cRwBE3NLxECbDqbGG1Io8g5JQrzjtfnX0Uzb0XRvloqT7FmhzIQ rKkWeH6MxsJ+hU1IMvNpr5MioNhcduWgfnGHWdfpLgVrtQSWidQuYmGHO0uIwt/y0Z ssvfg409UVdwvYd1bOMMWiNcOUtodxHS35F8NYgfE44aezZ7UAi8S58Ew/qsDXxzak z5aWWbGnd3prA== From: "Teddy Astie" Subject: =?utf-8?Q?[PATCH]=20MAINTAINERS:=20Add=20myself=20as=20x86=20reviewer?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775566148852 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" Message-Id: <20260407124840.80174-2-teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.4ef5e6487b0943b7995d36e71b58647b?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260407:md Date: Tue, 07 Apr 2026 12:49:10 +0000 MIME-Version: 1.0 Content-Type: text/plain; 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Signed-off-by: Teddy Astie --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1ac61da59a..77f72e52f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -225,6 +225,7 @@ M:=09Jan Beulich M:=09Andrew Cooper M:=09Roger Pau Monn=C3=A9 R:=09Jason Andryuk +R:=09Teddy Astie S:=09Supported F:=09xen/drivers/passthrough/amd/ @@ -233,6 +234,7 @@ M:=09Jan Beulich M:=09Andrew Cooper M:=09Roger Pau Monn=C3=A9 R:=09Jason Andryuk +R:=09Teddy Astie S:=09Supported F:=09xen/arch/x86/cpu/vpmu_amd.c F:=09xen/arch/x86/hvm/svm/ @@ -613,6 +615,7 @@ X86 ARCHITECTURE M:=09Jan Beulich M:=09Andrew Cooper M:=09Roger Pau Monn=C3=A9 +R:=09Teddy Astie S:=09Supported L:=09xen-devel@lists.xenproject.org F:=09xen/arch/x86/ -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 07 13:33:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 13:33:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274987.1560950 (Exim 4.92) (envelope-from ) id 1wA6YK-0003NU-7V; Tue, 07 Apr 2026 13:33:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274987.1560950; Tue, 07 Apr 2026 13:33:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA6YK-0003NL-45; Tue, 07 Apr 2026 13:33:12 +0000 Received: by outflank-mailman (input) for mailman id 1274987; Tue, 07 Apr 2026 13:33:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA6YJ-0003Mx-0d for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 13:33:11 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA6YH-00CKk5-Ur for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 15:33:09 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d50789-bab6-0a2a0a5309dd-0a2a4506eacc-40 for ; Tue, 07 Apr 2026 15:33:09 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d50795-0df0-0a2a45060019-d1558030c9b1-3 for ; Tue, 07 Apr 2026 15:33:09 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so9694925e9.3 for ; Tue, 07 Apr 2026 06:33:09 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 07 Apr 2026 06:33:09 -0700 (PDT) Message-ID: Date: Tue, 7 Apr 2026 15:33:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Marek Marczykowski From: Jan Beulich Subject: [PATCH] x86/HPET: channel handling in hpet_broadcast_resume() Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775568789-AF7393D8-EAABA65A/0/0 X-purgate-type: clean X-purgate-size: 2216 The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for the (possible) channel put in legacy mode we don't do so during boot either. Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an all-zero message (when the passed in CPU mask has no online CPUs). Nothing would later call msi_compose_msg() / hpet_msi_write(), and hence nothing would later produce a well-formed message template in hpet_events[].msi.msg. Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") Reported-by: Marek Marczykowski-Górecki Signed-off-by: Jan Beulich Tested-by: Marek Marczykowski-Górecki --- As to the Fixes: tag: The issue for the HPET resume case is the cpumask_intersects(desc->arch.cpu_mask, &cpu_online_map) check in msi_compose_msg(). The earlier cpumask_empty() wasn't a problem, as cpu_mask_to_apicid() returning a bogus (offline) value didn't have any bad effect: Before use, a valid destination would have been put in place, but other parts of .msg were properly set up. Furthermore we also didn't clear the entire message prior to that change. Many thanks got to Marek for tirelessly trying out various debugging suggestions. --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -685,12 +685,18 @@ void hpet_broadcast_resume(void) for ( i = 0; i < n; i++ ) { if ( hpet_events[i].msi.irq >= 0 ) + { + struct irq_desc *desc = irq_to_desc(hpet_events[i].msi.irq); + + cpumask_copy(desc->arch.cpu_mask, cpumask_of(smp_processor_id())); + __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); + } /* set HPET Tn as oneshot */ cfg = hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC); - cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; + cfg |= HPET_TN_32BIT; if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) cfg |= HPET_TN_FSB; hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); From xen-devel-bounces@lists.xenproject.org Tue Apr 07 13:37:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 13:37:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1274999.1560970 (Exim 4.92) (envelope-from ) id 1wA6cW-0004CP-Pa; Tue, 07 Apr 2026 13:37:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1274999.1560970; Tue, 07 Apr 2026 13:37:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA6cW-0004CI-N3; Tue, 07 Apr 2026 13:37:32 +0000 Received: by outflank-mailman (input) for mailman id 1274999; Tue, 07 Apr 2026 13:37:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA6cV-0004CC-D6 for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 13:37:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA6cU-00GRJr-PG for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 15:37:30 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d50893-2eae-0a2a0a5409dd-0a2a4504a4e0-8 for ; Tue, 07 Apr 2026 15:37:30 +0200 Received: from [209.85.221.52] (helo=mail-wr1-f52.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d5089a-bb33-0a2a45040019-d155dd34b505-3 for ; Tue, 07 Apr 2026 15:37:30 +0200 Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-43b8e8e7432so4122989f8f.1 for ; Tue, 07 Apr 2026 06:37:30 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260407124840.80174-2-teddy.astie@vates.tech> Content-Type: text/plain; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775569432-F6F4A497-28181E2B/0/0 X-purgate-type: clean X-purgate-size: 2740 On 07.04.2026 12:47, Oleksii Kurochko wrote: > On 4/1/26 3:19 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> --- a/xen/arch/riscv/p2m.c >>> +++ b/xen/arch/riscv/p2m.c >>> @@ -45,18 +45,32 @@ struct p2m_pte_ctx { >>> unsigned int level; /* Paging level at which the PTE resides. */ >>> }; >>> >>> -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { >>> - .mode = HGATP_MODE_OFF, >>> - .paging_levels = 0, >>> - .name = "Bare", >>> -}; >>> - >>> /* >>> * Set to the maximum configured support for IPA bits, so the number of IPA bits can be >>> * restricted by external entity (e.g. IOMMU). >>> */ >>> unsigned int __read_mostly p2m_ipa_bits = PADDR_BITS; >>> >>> +static const struct gstage_mode_desc modes[] = { >> >> As a function scope static this was a fine identifier. Please consider whether >> with the wider scope gstage_modes[] might not be better. >> >>> + /* >>> + * Based on the RISC-V spec: >>> + * Bare mode is always supported, regardless of SXLEN. >>> + * When SXLEN=32, the only other valid setting for MODE is Sv32. >>> + * When SXLEN=64, three paged virtual-memory schemes are defined: >>> + * Sv39, Sv48, and Sv57. >>> + */ >>> + [0] = { HGATP_MODE_OFF, 0, "none" }, >>> +#ifdef CONFIG_RISCV_32 >>> + [1] = { HGATP_MODE_SV32X4, 1, "sv32" } >>> +#else >>> + [2] = { HGATP_MODE_SV39X4, 2, "sv39" }, >>> + [3] = { HGATP_MODE_SV48X4, 3, "sv48" }, >>> + [4] = { HGATP_MODE_SV57X4, 4, "sv57" }, >>> +#endif >>> +}; >> >> The dedicated initializer form isn't adding any value here (whereas it slightly >> hampers readability). You really don't want the array to be sparsely populated, >> so perhaps better to leave as it was before? > > I need modes[] to be outside of gstage_mode_detect() as it then could be > re-used. Sure, and I didn't say "where it was before". I said "as it was before", i.e. without dedicated initializers. Jan > For example, if expected G-stage mode should be passed by DTS > property then in DTS property we'll have something like: > chosen { > ... > DOMU1 { > mmu-type="riscv,sv48"; > ... > } > ... > } > > And I will need to have another functions something like: > static unsigned int find_gstage_mode(const char *mmu_type) {...} > which will re-use modes[] to find a correspondent mode and return an > index (or return just correspondent mode) for that mode to then re-use > it to initialize p2m->mode: > p2m->mode = &modes[find_gstage_mode(mmu_type)]; > > ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 07 13:48:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 13:48:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275026.1560998 (Exim 4.92) (envelope-from ) id 1wA6mo-0006wq-7A; Tue, 07 Apr 2026 13:48:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275026.1560998; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775569687-EF14D2A1-2564C7DF/0/0 X-purgate-type: clean X-purgate-size: 1944 On 4/7/26 13:34, Michal Orzel wrote: Hello Michal > Rename 'pdev' to 'pci_dev' in the dev_print_pci() macro to avoid NIT: The macro is named dev_print, not dev_print_pci. > shadowing local 'pdev' variables at call sites. > > Remove the unused 'ret' declaration from ipmmu_assign_device() where > the function-scope 'ret' is sufficient. > > This fixes MISRA C R5.3. > > Signed-off-by: Michal Orzel Reviewed-by: Oleksandr Tyshchenko > --- > xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > index ea9fa9ddf3ce..fa9ab9cb1330 100644 > --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c > +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > @@ -65,8 +65,8 @@ > printk(lvl "ipmmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ > else \ > { \ > - struct pci_dev *pdev = dev_to_pci((dev)); \ > - printk(lvl "ipmmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ > + struct pci_dev *pci_dev = dev_to_pci((dev)); \ > + printk(lvl "ipmmu: %pp: " fmt, &pci_dev->sbdf, ## __VA_ARGS__); \ > } \ > }) > #endif > @@ -1171,8 +1171,6 @@ static int ipmmu_assign_device(struct domain *d, u8 devfn, struct device *dev, > /* dom_io is used as a sentinel for quarantined devices */ > if ( d == dom_io ) > { > - int ret; > - > /* > * Try to de-assign: do not return error if it was already > * de-assigned. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <71483b96126964a7cfcb24253cb04379a9f662c1.1773157782.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775569963-3052B51B-CEF7893F/10/73395122804 X-purgate-type: spam X-purgate-size: 629 On 10.03.2026 18:08, Oleksii Kurochko wrote: > For debug purpose is enough to have only print messages from guest what is > now implemented in vsbi_legacy_ecall_handler(). > > For full guesst console support it will better to have something similar to > [1], thereby there is nothing specific should be done, at least, for now > and init_vuart() is provided to make dom0less code buildable. > > [1] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602041533440.3175371@ubuntu-linux-20-04-desktop/ > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Tue Apr 07 14:10:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 14:10:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275044.1561017 (Exim 4.92) (envelope-from ) id 1wA78d-000357-7P; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775571038; x=1775841038; bh=ijHox48zfwhifLBy2nWwxBWaZv3Ku8mFkgnfo6+c9Ik=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=TGrejU11l/v1fEBn9oYMugyxH4kjOsVplYjVVfJYaIKyhLblFzGuHd43P1yuN4mI1 3xJxr2NDlSnwWjY9n3sDR8BThCiRNJL4eMO8fu57xjiT+aJwJbPSmlraHCnwQSSZAt 6ta/KMsXawGTJWm+wf3LqLXYtVWXWmISOmII0dbHz0d2U7TBbDgHafysMUJgCrlR0d +7CWwsWY+HHipblMuxIGLqSAQ2sZPy3nvdr2+ttbHDn+IN7LM9hiQyTauVFRs1e1KI 0lsDxBEXnp4xDDMQrWNk1wMudIsRLJzyY223+gs9NllU6Xg0975oNHH4qOZQ5VZqRU 4ayeVyhH4MsPQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775571038; x=1775831538; i=teddy.astie@vates.tech; bh=ijHox48zfwhifLBy2nWwxBWaZv3Ku8mFkgnfo6+c9Ik=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=U7TcAtP7ezIpKZRHjVWg8JcfNWodRmbmFKhoa8l+NqGkMc73chIB666TZn/RJO7gZ 0RxUARzotAKFh2JT0NYXFZBLSqFspGmfNOUK6Pjcnri2AK7V21EF4gXhQd4GmWjUpM 9nvqIUXhjGc4ywvGIHVpEPx62J9oNwWljlrNuY06Wx6xFoUhj8RFPLwI/2UZQ8N7gn 7lsw+l59Tb6H1no5NEOhx0g1Alx/poLaOmNE+yHyKdot83w7SSszO0lhk4X5uRl2pV 5PPXre25vpE6e1g9O4yDqj/g96yGVjtoqbVdkRjOHdeFpQrkPUs4jZ11c4T2GzKHKQ iHlc/0ZG/4NCA== From: "Teddy Astie" Subject: =?utf-8?Q?[PATCH=20v10]=20xenpm:=20Add=20get-core-temp=20subcommand?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775571036889 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Oleksii Kurochko" , "Community Manager" , "Anthony PERARD" Message-Id: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.23bd0bc15e884cac9101909b7eb64678?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260407:md Date: Tue, 07 Apr 2026 14:10:37 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1775571039-46F21CD1-A94C944A/0/0 X-purgate-type: clean X-purgate-size: 6994 get-core-temp allows querying the per-core CPU temperature and per-package one on processors that supports Digital Temperature Sensors (most Intel processors; as usual Dom0 drivers cannot work due to misalignment between Dom0 vCPU and pCPUs). Signed-off-by: Teddy Astie --- v4: https://lore.kernel.org/xen-devel/cover.1766158766.git.teddy.astie@vate= s.tech/ v5: Removed trailing whitespace. v6: Report errors through errno and use strerror() to display them v7: - Rename get-intel-temp with get-dts-temp - handle properly errno - make process return a error code if no data v8: - update Changelog - improve error handling - rename core-dts-temp with get-core-temp v9: - exit with EXIT_{SUCCESS,FAILURE} instead of errno v10: - make error handling more uniform - removed "No data" message - stop querying package temperature on failure CHANGELOG.md | 2 + tools/misc/xenpm.c | 121 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 122 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 166df43c63..c8cb125fae 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,6 +16,8 @@ The format is based on [Keep a Changelog](https://keepach= angelog.com/en/1.0.0/) mitigate (by rate-limiting) the system wide impact of an HVM guest misusing atomic instructions. - Support for CPIO microcode in discrete multiboot modules. + - Introduce get-core-temp to xenpm to query CPU temperatures on Intel + platforms. - On Arm: - Support for guest suspend and resume to/from RAM via vPSCI. diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index e4902d2e82..3371bb5be7 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -32,11 +32,14 @@ #include +#include + #define MAX_PKG_RESIDENCIES 12 #define MAX_CORE_RESIDENCIES 8 static xc_interface *xc_handle; static unsigned int max_cpu_nr; +static xc_physinfo_t physinfo; /* help message */ void show_help(void) @@ -93,6 +96,7 @@ void show_help(void) " units default to \= "us\" if unspecified.\n" " truncates un-repre= sentable values.\n" " 0 lets the hardwar= e decide.\n" + " get-core-temp [cpuid] get CPU temperature for = or all (Intel only)\n" " start [seconds] start collect Cx/Px stat= istics,\n" " output after CTRL-C or S= IGINT or several seconds.\n" " enable-turbo-mode [cpuid] enable Turbo Mode for pr= ocessors that support it.\n" @@ -1354,6 +1358,121 @@ void enable_turbo_mode(int argc, char *argv[]) errno, strerror(errno)); } +static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, i= nt *temp) +{ + xc_resource_entry_t entries[] =3D { + { .idx =3D package ? MSR_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STA= TUS }, + { .idx =3D MSR_TEMPERATURE_TARGET }, + }; + struct xc_resource_op ops =3D { + .cpu =3D cpu, + .entries =3D entries, + .nr_entries =3D ARRAY_SIZE(entries), + }; + int tjmax; + + int ret =3D xc_resource_op(xch, 1, &ops); + + switch ( ret ) + { + case 0: + /* This CPU isn't online or can't query this MSR */ + errno =3D ENODATA; + return -1; + + case 1: + { + /* + * The CPU doesn't support MSR_TEMPERATURE_TARGET, we assume it's = 100 + * which is correct aside a few selected Atom CPUs. Check Linux + * kernel's coretemp.c for more information. + */ + static bool has_reported_once =3D false; + + if ( !has_reported_once ) + { + fprintf(stderr, "MSR_TEMPERATURE_TARGET is not supported, assu= me " + "tjmax =3D 100, readings may be incorrect.\n")= ; + has_reported_once =3D true; + } + + tjmax =3D 100; + break; + } + + case 2: + tjmax =3D (entries[1].val >> 16) & 0xff; + break; + + default: + if ( ret > 0 ) + { + fprintf(stderr, "Got unexpected xc_resource_op return value: %= d", ret); + errno =3D EINVAL; + } + return -1; + } + + *temp =3D tjmax - ((entries[0].val >> 16) & 0xff); + return 0; +} + +static void get_core_temp(int argc, char *argv[]) +{ + int temp =3D -1, cpu =3D -1; + unsigned int socket; + bool has_data =3D false; + + if ( argc > 0 ) + parse_cpuid(argv[0], &cpu); + + if ( cpu !=3D -1 ) + { + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) + { + fprintf(stderr, "Unable to fetch temperature (%d - %s)\n", + errno, strerror(errno)); + exit(EXIT_FAILURE); + } + else + printf("CPU%d: %d=C2=B0C\n", cpu, temp); + return; + } + + /* Per socket measurement */ + for ( socket =3D 0, cpu =3D 0; cpu < max_cpu_nr; + socket++, cpu +=3D physinfo.cores_per_socket * physinfo.threads_= per_core ) + { + if ( fetch_dts_temp(xc_handle, cpu, true, &temp) ) + { + fprintf(stderr, + "[Package%u] Unable to fetch temperature (%d - %s)\n", + cpu, errno, strerror(errno)); + /* CPU may not support package temperatures, but still support= DTS */ + break; + } + + has_data =3D true; + printf("Package%u: %d=C2=B0C\n", socket, temp); + } + + for ( cpu =3D 0; cpu < max_cpu_nr; cpu +=3D physinfo.threads_per_core = ) + { + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) + { + fprintf(stderr, "[CPU%d] Unable to fetch temperature (%d - %s)= \n", + cpu, errno, strerror(errno)); + continue; + } + + has_data =3D true; + printf("CPU%d: %d=C2=B0C\n", cpu, temp); + } + + if ( !has_data ) + exit(EXIT_FAILURE); +} + void disable_turbo_mode(int argc, char *argv[]) { int cpuid =3D -1; @@ -1618,12 +1737,12 @@ struct { { "set-max-cstate", set_max_cstate_func}, { "enable-turbo-mode", enable_turbo_mode }, { "disable-turbo-mode", disable_turbo_mode }, + { "get-core-temp", get_core_temp }, }; int main(int argc, char *argv[]) { int i, ret =3D 0; - xc_physinfo_t physinfo; int nr_matches =3D 0; int matches_main_options[ARRAY_SIZE(main_options)]; -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 07 14:11:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 14:11:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275048.1561024 (Exim 4.92) (envelope-from ) id 1wA799-0003Ur-Ea; Tue, 07 Apr 2026 14:11:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275048.1561024; Tue, 07 Apr 2026 14:11:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA799-0003Uk-Bb; Tue, 07 Apr 2026 14:11:15 +0000 Received: by outflank-mailman (input) for mailman id 1275048; Tue, 07 Apr 2026 14:11:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wA798-0003SF-4J for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 14:11:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA797-0022M9-GM for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 16:11:13 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d5107c-5cb7-0a2a0a5109dd-0a2a4502a0ea-14 for ; Tue, 07 Apr 2026 16:11:13 +0200 Received: from [209.85.221.47] (helo=mail-wr1-f47.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d51081-42fa-0a2a45020019-d155dd2fb559-3 for ; Tue, 07 Apr 2026 16:11:13 +0200 Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-43b8e8e7432so4153722f8f.1 for ; Tue, 07 Apr 2026 07:11:13 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775571073-AD53CCD1-2F6E46A4/10/73395122804 X-purgate-type: spam X-purgate-size: 4000 On 10.03.2026 18:09, Oleksii Kurochko wrote: > Enable dom0less support for RISC-V by selecting HAS_DOM0LESS and > providing the minimal architecture hooks required by the common > dom0less infrastructure. > > Add stub implementations for architecture-specific helpers used when > building domains from the device tree. These currently perform no > additional work but allow the generic dom0less code to build and run > on RISC-V. > > Introduce max_init_domid as a runtime variable rather than a constant > so that it can be updated during dom0less domain creation. > > Provide missing helpers and definitions required by the domain > construction code, I'm wondering about the splitting among patches: There's half a dozen (effectively stub) functions which are added here, and then there is the single init_vuart() which was split out into the earlier patch. What's the pattern behind this, i.e. why isn't init_vuart() also being added here? > including domain bitness helpers and the > p2m_set_allocation() prototype. > > Additionally define the guest magic memory region in the public > RISC-V interface. > > Signed-off-by: Oleksii Kurochko > --- > Open questions: > - Move declaration of p2m_set_allocation() to xen/fdt-domain-build.h or > xen/dom0less-build.h as it is used in common code of Dom0less and > there is not too much sense in declaration of it for each arch which > supports Dom0less. It could be ifdef-ed in common header as, at the > momemnt, it is used only for Dom0less. Having a common declaration of p2m_set_allocation() is certainly a sensible thing to do, but not in DT or dom0less headers. p2m-common.h is, going from file names, the only plausible place for it to go. Whether that (a) works and (b) makes sense are separate questions. > - Shouldn't declaration/defintion of max_init_domid move to common code > instead of having it for each architecture separately? If yes, then what > would be the best place. What would you use to decide whether the declaration or #define is needed? (Plausible headers to put it can surely be found: console.h, domain.h, and perhaps more.) > --- a/xen/arch/riscv/include/asm/domain.h > +++ b/xen/arch/riscv/include/asm/domain.h > @@ -20,6 +20,14 @@ struct hvm_domain > uint64_t params[HVM_NR_PARAMS]; > }; > > +#ifdef CONFIG_RISCV_64 > +#define is_32bit_domain(d) (0) > +#define is_64bit_domain(d) (1) > +#else > +#define is_32bit_domain(d) (1) > +#define is_64bit_domain(d) (0) > +#endif First, please use true/false. Then, while I agree with the RV32 part, 32-bit guests surely will need to be an option on a 64-bit hypervisor. Imo you'd better introduced a field in struct arch_domain to carry that information (or to derive it from) right away. That wouldn't be set to non-zero for the time being, i.e. that same constant-true/false would still result. Otherwise I don't see why you use #ifdef; you could then have things simpler as #define is_32bit_domain(d) IS_ENABLED(CONFIG_RISCV_32) #define is_64bit_domain(d) IS_ENABLED(CONFIG_RISCV_64) (but I specifically don't recommend going this route). > --- a/xen/arch/riscv/setup.c > +++ b/xen/arch/riscv/setup.c > @@ -32,6 +32,8 @@ > #include > #include > > +domid_t max_init_domid = 0; The initializer isn't of much use, is it? Instead add __read_mostly, like Arm has it? > --- a/xen/include/public/arch-riscv.h > +++ b/xen/include/public/arch-riscv.h > @@ -58,6 +58,9 @@ typedef uint64_t xen_ulong_t; > #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE } > #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE } > > +#define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) > +#define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) What is this, and why does it need putting in the public interface? Plus how come the numbers are exactly the same as what Arm uses? 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The error paths are just an artefact of the hook functions needing to return something. The best effort unwind is also something that doesn't exist in real hardware, and makes the logic more complicated to follow. Instead, use an ASSERT_UNREACHABLE() with a fallback of injecting #DF. Hitting this path is an error in Xen. While adjusting, remove {read,write}_segment() and use {read,write}_msr() to access MSR_GS_BASE. There's no need to access the other parts of the GS segment, and this is less work behind the scenes. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné v2: * Retain x86_emul_reset_event() * Pass an error code for #DF * Drop goto done now that generate_exception() is used * Use 2x{read,write}_msr() Tested using LKGS's extention of the test emulator for SWAPGS. --- xen/arch/x86/x86_emulate/0f01.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0f01.c index 6c10979dd650..54bd6faf0f2c 100644 --- a/xen/arch/x86/x86_emulate/0f01.c +++ b/xen/arch/x86/x86_emulate/0f01.c @@ -189,22 +189,24 @@ int x86emul_0f01(struct x86_emulate_state *s, generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); fail_if(!ops->read_segment || !ops->read_msr || !ops->write_segment || !ops->write_msr); - if ( (rc = ops->read_segment(x86_seg_gs, &sreg, - ctxt)) != X86EMUL_OKAY || - (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + if ( (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, ctxt)) != X86EMUL_OKAY || - (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, - ctxt, false)) != X86EMUL_OKAY ) + (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) != X86EMUL_OKAY ) goto done; - sreg.base = msr_val; - if ( (rc = ops->write_segment(x86_seg_gs, &sreg, - ctxt)) != X86EMUL_OKAY ) + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt, false)) != X86EMUL_OKAY || + (rc = ops->write_msr(MSR_GS_BASE, msr_val, + ctxt, false)) != X86EMUL_OKAY ) { - /* Best effort unwind (i.e. no real error checking). */ - if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, - ctxt, false) == X86EMUL_EXCEPTION ) - x86_emul_reset_event(ctxt); - goto done; + /* + * In real hardware, access to the registers cannot fail. It is + * an error in Xen if the writes fail given that both MSRs have + * equivalent checks. + */ + ASSERT_UNREACHABLE(); + x86_emul_reset_event(ctxt); + generate_exception(X86_EXC_DF, 0); } break; -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 07 14:28:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 14:28:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275071.1561044 (Exim 4.92) (envelope-from ) id 1wA7Py-00067b-72; Tue, 07 Apr 2026 14:28:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275071.1561044; Tue, 07 Apr 2026 14:28:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA7Py-00067U-3E; Tue, 07 Apr 2026 14:28:38 +0000 Received: by outflank-mailman (input) for mailman id 1275071; Tue, 07 Apr 2026 14:28:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA7Pw-00067O-5m for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775572113; x=1775832613; i=teddy.astie@vates.tech; bh=wulGuTlcR8Sn4nzBb9YK+YbQVPxoyiSgvH5ZgGYc+/w=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=rWvaWa++IEb19cf8UrhBU4gW1Su6QcNaMd/Xy1PlyeFE1EzKM2p7z33FhL0ALeuez TvCcO9LX2HEx/eVM50Lc353QsGXwiVTs965Fxa70q7vadNTcz+yOj5ja+eALclZvvU xMiwtpkhmLgwVEqz8Ub8+rf6Ru4v65BVcIMQICZn1As3zIiFRFtHsvABi9K/2SvqFI e+4C7SE97yZNpXB3kHdpNGiXeZByHq9qG/dGmjbSdPw2XWMlvUN7IAAfsnbPrWNAjl 7HW1P/d+/Em+5DgRSYAX2G97PftDtn2WK+mDcmXOurOoERkVW7rJKzY77sHBNBlEpB pv69GmmXWxDCw== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH]=20x86/HPET:=20channel=20handling=20in=20hpet=5Fbroadcast=5Fresume()?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775572112605 Message-Id: To: "Jan Beulich" , xen-devel@lists.xenproject.org Cc: "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Marek Marczykowski" References: In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.9635abaa79d7495a902f1a97067a8fcc?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260407:md Date: Tue, 07 Apr 2026 14:28:33 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1775572115-80360A3D-80950A2E/0/0 X-purgate-type: clean X-purgate-size: 2721 Le 07/04/2026 =C3=A0 15:35, Jan Beulich a =C3=A9crit=C2=A0: > The per-channel ENABLE bit is to solely be driven by hpet_enable_channel(= ) > and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for > the (possible) channel put in legacy mode we don't do so during boot > either. > > Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an > all-zero message (when the passed in CPU mask has no online CPUs). Nothin= g > would later call msi_compose_msg() / hpet_msi_write(), and hence nothing > would later produce a well-formed message template in > hpet_events[].msi.msg. > > Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") > Reported-by: Marek Marczykowski-G=C3=B3recki > Signed-off-by: Jan Beulich > Tested-by: Marek Marczykowski-G=C3=B3recki > --- > As to the Fixes: tag: The issue for the HPET resume case is the > cpumask_intersects(desc->arch.cpu_mask, &cpu_online_map) check in > msi_compose_msg(). The earlier cpumask_empty() wasn't a problem, as > cpu_mask_to_apicid() returning a bogus (offline) value didn't have any ba= d > effect: Before use, a valid destination would have been put in place, but > other parts of .msg were properly set up. Furthermore we also didn't clea= r > the entire message prior to that change. > > Many thanks got to Marek for tirelessly trying out various debugging > suggestions. > > --- a/xen/arch/x86/hpet.c > +++ b/xen/arch/x86/hpet.c > @@ -685,12 +685,18 @@ void hpet_broadcast_resume(void) > for ( i =3D 0; i < n; i++ ) > { > if ( hpet_events[i].msi.irq >=3D 0 ) > + { > + struct irq_desc *desc =3D irq_to_desc(hpet_events[i].msi.irq= ); > + > + cpumask_copy(desc->arch.cpu_mask, cpumask_of(smp_processor_i= d())); > + > __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); We can directly reuse "desc" here since irq_to_desc(...) isn't supposed to change value with cpumask_copy(). i.e `__hpet_setup_msi_irq(desc);` > + } > > /* set HPET Tn as oneshot */ > cfg =3D hpet_read32(HPET_Tn_CFG(hpet_events[i].idx)); > cfg &=3D ~(HPET_TN_LEVEL | HPET_TN_PERIODIC); > - cfg |=3D HPET_TN_ENABLE | HPET_TN_32BIT; > + cfg |=3D HPET_TN_32BIT; > if ( !(hpet_events[i].flags & HPET_EVT_LEGACY) ) > cfg |=3D HPET_TN_FSB; > hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx)); > Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 07 15:12:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 15:12:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275105.1561068 (Exim 4.92) (envelope-from ) id 1wA85w-0004Bk-D7; Tue, 07 Apr 2026 15:12:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275105.1561068; Tue, 07 Apr 2026 15:12:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA85w-0004Bd-A3; Tue, 07 Apr 2026 15:12:00 +0000 Received: by outflank-mailman (input) for mailman id 1275105; Tue, 07 Apr 2026 15:11:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA85v-0004BX-Kx for xen-devel@lists.xenproject.org; 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I'll put this into the patch as-is; it's unclear to me though > whether I could legitimately commit the patch with this. (It really > doesn't depend on earlier patches in the series, after all.) For an off-by-default change like this, it's fine.  There needs to be another patch swapping a for A when we get access to real hardware, where any other changes can be accommodated. In the meantime AMD have published a spec https://docs.amd.com/v/u/en-US/69192-PUB so feel free to upgrade to a regular A-by. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 07 15:19:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 15:19:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275116.1561077 (Exim 4.92) (envelope-from ) id 1wA8D0-0004q5-2h; Tue, 07 Apr 2026 15:19:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275116.1561077; Tue, 07 Apr 2026 15:19:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8Cz-0004py-WC; Tue, 07 Apr 2026 15:19:18 +0000 Received: by outflank-mailman (input) for mailman id 1275116; Tue, 07 Apr 2026 15:19:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8Cz-0004ps-Ag for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 15:19:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA8Cy-00CaI6-JD for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 17:19:16 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d52066-2eae-0a2a0a5409dd-0a2a4504defc-20 for ; Tue, 07 Apr 2026 17:19:16 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d52074-bb33-0a2a45040019-d155802cbc14-3 for ; Tue, 07 Apr 2026 17:19:16 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488a4bc360bso16916465e9.0 for ; Tue, 07 Apr 2026 08:19:16 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260407142351.73049-1-andrew.cooper3@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775575156-33B3051B-4A2DAA39/0/0 X-purgate-type: clean X-purgate-size: 775 On 07.04.2026 16:23, Andrew Cooper wrote: > In real hardware, accesses to the registers cannot fail. The error paths are > just an artefact of the hook functions needing to return something. > > The best effort unwind is also something that doesn't exist in real hardware, > and makes the logic more complicated to follow. Instead, use an > ASSERT_UNREACHABLE() with a fallback of injecting #DF. Hitting this path is > an error in Xen. > > While adjusting, remove {read,write}_segment() and use {read,write}_msr() to > access MSR_GS_BASE. There's no need to access the other parts of the GS > segment, and this is less work behind the scenes. > > Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Tue Apr 07 15:27:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 15:27:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275124.1561086 (Exim 4.92) (envelope-from ) id 1wA8KW-0006OS-Q0; Tue, 07 Apr 2026 15:27:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275124.1561086; Tue, 07 Apr 2026 15:27:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8KW-0006OL-N2; Tue, 07 Apr 2026 15:27:04 +0000 Received: by outflank-mailman (input) for mailman id 1275124; Tue, 07 Apr 2026 15:27:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8KV-0006OF-0i for xen-devel@lists.xen.org; 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Tue, 07 Apr 2026 08:27:00 -0700 (PDT) From: =?UTF-8?B?TWF0ecOhxaE=?= Kroupa To: Jan Beulich Cc: xen-devel@lists.xen.org Subject: Re: Xen on Zen 3 Date: Tue, 07 Apr 2026 17:26:59 +0200 Message-ID: <3426323.0QQBjFxQff@rivendell.hailstone.cz> In-Reply-To: References: <5490687.niJfEyVGOH@rivendell.hailstone.cz> <4454038.v2OnDr8pfo@rivendell.hailstone.cz> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart24824718.vTCxPXJkl2" Content-Transfer-Encoding: 7Bit X-purgate-ID: tlsNG-ef75cf/1775575621-83B4041E-2C8F7BFC/0/0 X-purgate-type: clean X-purgate-size: 51764 This is a multi-part message in MIME format. --nextPart24824718.vTCxPXJkl2 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" > I'd guess the value to be 1, but there > being multiple nodes at the same time. You may want to instrument the > function a little more to be certain. I managed to get the dyndbg working and you were right, there is 1 root dev= ice, 2 max logical packages and 1 node per package. I have searched how lin= ux gets the number of max logical packages and it seems to have something t= o with the bitmap weight of the package-domain APIC map. Those are probably= different on bare metal and Xen. Last time I forgot to attach logs, this time I put that right now. Maty=C3=A1=C5=A1 Kroupa --nextPart24824718.vTCxPXJkl2 Content-Disposition: attachment; filename="xen-4.21.1-linux-6.19.10-dyndbg.txt" Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="UTF-8"; name="xen-4.21.1-linux-6.19.10-dyndbg.txt" Loading Xen 4.21.1 ... Loading Linux 6.19.10-200.fc43.x86_64 ... Loading initial ramdisk ... Xen 4.21.1 (XEN) Xen version 4.21.1 (mockbuild@) (gcc (GCC) 15.2.1 20260123 (Red Hat 15.2.1-7)) debug=n Mon Apr 6 00:00:00 UTC 2026 (XEN) Latest ChangeSet: (XEN) build-id: 11ab961ff2580581f074fd57a1954e7cea23875c (XEN) CPU Vendor: AMD, Family 25 (0x19), Model 33 (0x21), Stepping 2 (raw 00a20f12) (XEN) BSP microcode revision: 0x0a201213 (XEN) Bootloader: GRUB 2.12 (XEN) Command line: placeholder dom0=pvh dom0_mem=36G com1=115200,8n1 console=com1,vga no-real-mode edd=off (XEN) Xen image load base address: 0xb6a00000 (XEN) Video information: (XEN) VGA is graphics mode 1920x1080, 32 bpp (XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds (XEN) Disc information: (XEN) Found 0 MBR signatures (XEN) Found 3 EDD information structures (XEN) Using IDT event delivery (XEN) Enabling Supervisor Shadow Stacks (XEN) - Disabling PV32 due to CET (XEN) EFI RAM map: (XEN) [0000000000000000, 000000000009ffff] (usable) (XEN) [00000000000a0000, 00000000000fffff] (reserved) (XEN) [0000000000100000, 0000000009bfefff] (usable) (XEN) [0000000009bff000, 0000000009ffffff] (reserved) (XEN) [000000000a000000, 000000000a1fffff] (usable) (XEN) [000000000a200000, 000000000a20dfff] (ACPI NVS) (XEN) [000000000a20e000, 000000000affffff] (usable) (XEN) [000000000b000000, 000000000b01ffff] (reserved) (XEN) [000000000b020000, 00000000bb13afff] (usable) (XEN) [00000000bb13b000, 00000000bc947fff] (reserved) (XEN) [00000000bc948000, 00000000bc988fff] (ACPI data) (XEN) [00000000bc989000, 00000000bd07cfff] (ACPI NVS) (XEN) [00000000bd07d000, 00000000bdbfefff] (reserved) (XEN) [00000000bdbff000, 00000000beffffff] (usable) (XEN) [00000000bf000000, 00000000bfffffff] (reserved) (XEN) [00000000f0000000, 00000000f7ffffff] (reserved) (XEN) [00000000fd200000, 00000000fd2fffff] (reserved) (XEN) [00000000fd600000, 00000000fd7fffff] (reserved) (XEN) [00000000fea00000, 00000000fea0ffff] (reserved) (XEN) [00000000feb80000, 00000000fec01fff] (reserved) (XEN) [00000000fec10000, 00000000fec10fff] (reserved) (XEN) [00000000fec30000, 00000000fec30fff] (reserved) (XEN) [00000000fed00000, 00000000fed00fff] (reserved) (XEN) [00000000fed40000, 00000000fed44fff] (reserved) (XEN) [00000000fed80000, 00000000fed8ffff] (reserved) (XEN) [00000000fedc2000, 00000000fedcffff] (reserved) (XEN) [00000000fedd4000, 00000000fedd5fff] (reserved) (XEN) [00000000ff000000, 00000000ffffffff] (reserved) (XEN) [0000000100000000, 0000000c3f2fffff] (usable) (XEN) [0000000c3f300000, 0000000c3fffffff] (reserved) (XEN) ACPI: RSDP BD066014, 0024 (r2 ALASKA) (XEN) ACPI: XSDT BD065728, 00CC (r1 ALASKA A M I 1072009 AMI 1000013) (XEN) ACPI: FACP BC97A000, 0114 (r6 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: DSDT BC973000, 60DA (r2 ALASKA A M I 1072009 INTL 20120913) (XEN) ACPI: FACS BD060000, 0040 (XEN) ACPI: SSDT BC980000, 8CE9 (r2 AMD AmdTable 2 MSFT 4000000) (XEN) ACPI: SSDT BC97C000, 3CB6 (r2 AMD AMD AOD 1 INTL 20120913) (XEN) ACPI: SSDT BC97B000, 01CC (r2 ALASKA CPUSSDT 1072009 AMI 1072009) (XEN) ACPI: FIDT BC972000, 009C (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: MCFG BC971000, 003C (r1 ALASKA A M I 1072009 MSFT 10013) (XEN) ACPI: AAFT BC970000, 00F1 (r1 ALASKA OEMAAFT 1072009 MSFT 97) (XEN) ACPI: HPET BC96F000, 0038 (r1 ALASKA A M I 1072009 AMI 5) (XEN) ACPI: IVRS BC96E000, 00D0 (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: BGRT BC96D000, 0038 (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: TPM2 BC96C000, 004C (r4 ALASKA A M I 1 AMI 0) (XEN) ACPI: PCCT BC96B000, 006E (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: SSDT BC962000, 8033 (r2 AMD AmdTable 1 AMD 1) (XEN) ACPI: CRAT BC960000, 1710 (r1 AMD AmdTable 1 AMD 1) (XEN) ACPI: CDIT BC95F000, 0029 (r1 AMD AmdTable 1 AMD 1) (XEN) ACPI: SSDT BC95B000, 37C4 (r2 AMD MYRTLE 1 INTL 20120913) (XEN) ACPI: SSDT BC95A000, 00BF (r1 AMD AmdTable 1000 INTL 20120913) (XEN) ACPI: WSMT BC959000, 0028 (r1 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: APIC BC958000, 015E (r3 ALASKA A M I 1072009 AMI 10013) (XEN) ACPI: SSDT BC956000, 10AF (r2 AMD MYRTLE 1 INTL 20120913) (XEN) ACPI: FPDT BC955000, 0044 (r1 ALASKA A M I 1072009 AMI 1000013) (XEN) System RAM: 49075MB (50253492kB) (XEN) No NUMA configuration found (XEN) Faking a node at 0000000000000000-0000000c3f300000 (XEN) Domain heap initialised (XEN) vesafb: framebuffer at 0x000000f800000000, mapped to 0xffff82c000203000, using 8128k, total 8128k (XEN) vesafb: mode is 1920x1080x32, linelength=7680, font 8x16 (XEN) vesafb: Truecolor: size=8:8:8:8, shift=24:16:8:0 (XEN) SMBIOS 3.3 present. (XEN) PCI: MCFG configuration 0: base f0000000 segment 0000 buses 00 - 7f (XEN) PCI: MCFG area at f0000000 reserved in E820 (XEN) PCI: Using MCFG for segment 0000 bus 00-7f (XEN) Using APIC driver default (XEN) ACPI: PM-Timer IO Port: 0x808 (32 bits) (XEN) ACPI: v5 SLEEP INFO: control[0:0], status[0:0] (XEN) ACPI: SLEEP INFO: pm1x_cnt[1:804,1:0], pm1x_evt[1:800,1:0] (XEN) ACPI: 32/64X FACS address mismatch in FADT - bd060000/0000000000000000, using 32 (XEN) ACPI: wakeup_vec[bd06000c], vec_size[20] (XEN) Overriding APIC driver with bigsmp (XEN) ACPI: IOAPIC (id[0x21] address[0xfec00000] gsi_base[0]) (XEN) IOAPIC[0]: apic_id 33, version 33, address 0xfec00000, GSI 0-23 (XEN) ACPI: IOAPIC (id[0x22] address[0xfec01000] gsi_base[24]) (XEN) IOAPIC[1]: apic_id 34, version 33, address 0xfec01000, GSI 24-55 (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) (XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) (XEN) ACPI: HPET id: 0x10228201 base: 0xfed00000 (XEN) ACPI: BGRT: invalidating v1 image at 0xb762c018 (XEN) Using ACPI (MADT) for SMP configuration information (XEN) SMP: Allowing 32 CPUs (0 hotplug CPUs) (XEN) IRQ limits: 56 GSI, 6600 MSI/MSI-X (XEN) AMD-Vi: IOMMU Extended Features: (XEN) - Peripheral Page Service Request (XEN) - NX bit (XEN) - Invalidate All Command (XEN) - Performance Counters (XEN) - Host Address Translation Size: 0x2 (XEN) - Guest Address Translation Size: 0 (XEN) - Guest CR3 Root Table Level: 0x1 (XEN) - Maximum PASID: 0xf (XEN) - SMI Filter Register: 0x1 (XEN) - SMI Filter Register Count: 0x2 (XEN) - Guest Virtual APIC Modes: 0x1 (XEN) - Dual PPR Log: 0x2 (XEN) - Dual Event Log: 0x2 (XEN) - User / Supervisor Page Protection (XEN) - Device Table Segmentation: 0x3 (XEN) - PPR Log Overflow Early Warning (XEN) - PPR Automatic Response (XEN) - Memory Access Routing and Control: 0x1 (XEN) - Block StopMark Message (XEN) - Performance Optimization (XEN) - MSI Capability MMIO Access (XEN) - Guest I/O Protection (XEN) - Host Access (XEN) - Enhanced PPR Handling (XEN) - Attribute Forward (XEN) - Virtualized IOMMU (XEN) - VMGuard I/O Support (XEN) - VM Table Size: 0x2 (XEN) Switched to APIC driver x2apic_mixed (XEN) CPU0: 2200 ... 3400 MHz (XEN) xstate: size: 0x988 and states: 0x207 (XEN) CPU0: AMD Fam19h machine check reporting enabled (XEN) Speculative mitigation facilities: (XEN) Hardware hints: STIBP_ALWAYS IBRS_FAST IBRS_SAME_MODE (XEN) Hardware features: IBPB IBRS STIBP SSBD PSFD (XEN) Compiled-in support: INDIRECT_THUNK RETURN_THUNK SHADOW_PAGING HARDEN_ARRAY HARDEN_BRANCH HARDEN_GUEST_ACCESS HARDEN_LOCK (XEN) Xen settings: BTI-Thunk: JMP, SPEC_CTRL: IBRS+ STIBP+ SSBD- PSFD-, Other: VERW BRANCH_HARDEN (XEN) Support for HVM VMs: MSR_SPEC_CTRL MSR_VIRT_SPEC_CTRL RSB VERW IBPB-entry (XEN) Support for PV VMs: VERW IBPB-entry (XEN) XPTI (64-bit PV only): Dom0 disabled, DomU disabled (without PCID) (XEN) PV L1TF shadowing: Dom0 disabled, DomU disabled (XEN) Using scheduler: SMP Credit Scheduler rev2 (credit2) (XEN) Initializing Credit2 scheduler (XEN) load_precision_shift: 18 (XEN) load_window_shift: 30 (XEN) underload_balance_tolerance: 0 (XEN) overload_balance_tolerance: -3 (XEN) runqueues arrangement: socket (XEN) cap enforcement granularity: 10ms (XEN) load tracking window length 1073741824 ns (XEN) Platform timer is 14.318MHz HPET (XEN) Detected 3393.640 MHz processor. (XEN) Freed 1008kB unused BSS memory (XEN) alt table ffff82d04049bfb8 -> ffff82d0404b328e (XEN) AMD-Vi: IOMMU 0 Enabled. (XEN) I/O virtualisation enabled (XEN) - Dom0 mode: Relaxed (XEN) Interrupt remapping enabled (XEN) Enabling APIC mode. Using 2 I/O APICs (XEN) ENABLING IO-APIC IRQs (XEN) -> Using new ACK method (XEN) ..TIMER: vector=0xF0 apic1=0 pin1=2 apic2=-1 pin2=-1 (XEN) Wallclock source: CMOS RTC (XEN) Defaulting to alternative key handling; send 'A' to switch to normal mode. (XEN) Allocated console ring of 128 KiB. (XEN) HVM: ASIDs enabled (XEN) SVM: Supported advanced features: (XEN) - Nested Page Tables (NPT) (XEN) - Last Branch Record (LBR) Virtualisation (XEN) - Next-RIP Saved on #VMEXIT (XEN) - VMCB Clean Bits (XEN) - TLB flush by ASID (XEN) - DecodeAssists (XEN) - Virtual VMLOAD/VMSAVE (XEN) - Virtual GIF (XEN) - Pause-Intercept Filter (XEN) - Pause-Intercept Filter Threshold (XEN) - TSC Rate MSR (XEN) - NPT Supervisor Shadow Stack (XEN) - MSR_SPEC_CTRL virtualisation (XEN) HVM: SVM enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB, 1GB (XEN) Brought up 32 CPUs (XEN) Scheduling granularity: cpu, 1 CPU per sched-resource (XEN) Initializing Credit2 scheduler (XEN) load_precision_shift: 18 (XEN) load_window_shift: 30 (XEN) underload_balance_tolerance: 0 (XEN) overload_balance_tolerance: -3 (XEN) runqueues arrangement: socket (XEN) cap enforcement granularity: 10ms (XEN) load tracking window length 1073741824 ns (XEN) Adding cpu 0 to runqueue 0 (XEN) First cpu on runqueue, activating (XEN) Adding cpu 1 to runqueue 0 (XEN) Adding cpu 2 to runqueue 0 (XEN) Adding cpu 3 to runqueue 0 (XEN) Adding cpu 4 to runqueue 0 (XEN) Adding cpu 5 to runqueue 0 (XEN) Adding cpu 6 to runqueue 0 (XEN) Adding cpu 7 to runqueue 0 (XEN) Adding cpu 8 to runqueue 0 (XEN) Adding cpu 9 to runqueue 0 (XEN) Adding cpu 10 to runqueue 0 (XEN) Adding cpu 11 to runqueue 0 (XEN) Adding cpu 12 to runqueue 0 (XEN) Adding cpu 13 to runqueue 0 (XEN) Adding cpu 14 to runqueue 0 (XEN) Adding cpu 15 to runqueue 0 (XEN) Adding cpu 16 to runqueue 1 (XEN) First cpu on runqueue, activating (XEN) Adding cpu 17 to runqueue 1 (XEN) Adding cpu 18 to runqueue 1 (XEN) Adding cpu 19 to runqueue 1 (XEN) Adding cpu 20 to runqueue 1 (XEN) Adding cpu 21 to runqueue 1 (XEN) Adding cpu 22 to runqueue 1 (XEN) Adding cpu 23 to runqueue 1 (XEN) Adding cpu 24 to runqueue 1 (XEN) Adding cpu 25 to runqueue 1 (XEN) Adding cpu 26 to runqueue 1 (XEN) Adding cpu 27 to runqueue 1 (XEN) Adding cpu 28 to runqueue 1 (XEN) Adding cpu 29 to runqueue 1 (XEN) Adding cpu 30 to runqueue 1 (XEN) Adding cpu 31 to runqueue 1 (XEN) mcheck_poll: Machine check polling timer started. (XEN) NX (Execute Disable) protection active (XEN) d0 has maximum 6656 PIRQs (XEN) *** Building a PVH Dom0 *** (XEN) Initial low memory virq threshold set at 0x4000 pages. (XEN) Scrubbing Free RAM in background (XEN) Std. Loglevel: Errors, warnings and info (XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings) (XEN) Xen is relinquishing VGA console. (XEN) *** Serial input to DOM0 (type 'CTRL-a' three times to switch input) (XEN) Freed 724kB init memory [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] APIC: Static calls initialized [ 0.000000] efi: EFI v2.7 by American Megatrends [ 0.000000] efi: ACPI=0xbd066000 ACPI 2.0=0xbd066014 TPMFinalLog=0xbd030000 SMBIOS=0xbda22000 SMBIOS 3.0=0xbda21000 (MEMATTR=0xb753c018 unusable) ESRT=0xbc954018 MOKvar=0xbda6d000 [ 0.000000] secureboot: Secure boot disabled [ 0.000000] SMBIOS 3.3.0 present. [ 0.000000] DMI: To Be Filled By O.E.M. B450M Steel Legend/B450M Steel Legend, BIOS P10.43 06/25/2025 [ 0.000000] DMI: Memory slots populated: 4/4 [ 0.000000] Hypervisor detected: Xen HVM [ 0.000000] Xen version 4.21. [ 0.000003] HVMOP_pagetable_dying not supported [ 0.065007] tsc: Fast TSC calibration failed [ 0.065023] tsc: Detected 3393.640 MHz processor [ 0.065189] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.065193] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.065204] last_pfn = 0xc3f300 max_arch_pfn = 0x400000000 [ 0.065232] MTRR map: 5 entries (4 fixed + 1 variable; max 21), built from 9 variable MTRRs [ 0.065236] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT [ 0.066982] CPU MTRRs all blank - virtualized system. [ 0.066996] last_pfn = 0xbefff max_arch_pfn = 0x400000000 [ 0.070252] esrt: Reserving ESRT space from 0x00000000bc954018 to 0x00000000bc954050. [ 0.070259] Using GB pages for direct mapping [ 0.071080] secureboot: Secure boot disabled [ 0.071083] RAMDISK: [mem 0x05600000-0x0872ffff] [ 0.071090] ACPI: Early table checksum verification disabled [ 0.071095] ACPI: RSDP 0x00000000BEFFFD00 000024 (v02 ALASKA) [ 0.071100] ACPI: XSDT 0x00000000BEFFFD24 000084 (v01 ALASKA A M I 01072009 AMI 01000013) [ 0.071107] ACPI: APIC 0x00000000BEFFFDA8 000258 (v03 ALASKA A M I 01072009 AMI 00010013) [ 0.071113] ACPI: FACP 0x00000000BC97A000 000114 (v06 ALASKA A M I 01072009 AMI 00010013) [ 0.071156] ACPI: DSDT 0x00000000BC973000 0060DA (v02 ALASKA A M I 01072009 INTL 20120913) [ 0.071161] ACPI: FACS 0x00000000BD060000 000040 [ 0.071166] ACPI: SSDT 0x00000000BC980000 008CE9 (v02 AMD AmdTable 00000002 MSFT 04000000) [ 0.071171] ACPI: SSDT 0x00000000BC97C000 003CB6 (v02 AMD AMD AOD 00000001 INTL 20120913) [ 0.071176] ACPI: SSDT 0x00000000BC97B000 0001CC (v02 ALASKA CPUSSDT 01072009 AMI 01072009) [ 0.071182] ACPI: MCFG 0x00000000BC971000 00003C (v01 ALASKA A M I 01072009 MSFT 00010013) [ 0.071187] ACPI: TPM2 0x00000000BC96C000 00004C (v04 ALASKA A M I 00000001 AMI 00000000) [ 0.071192] ACPI: SSDT 0x00000000BC962000 008033 (v02 AMD AmdTable 00000001 AMD 00000001) [ 0.071197] ACPI: SSDT 0x00000000BC95B000 0037C4 (v02 AMD MYRTLE 00000001 INTL 20120913) [ 0.071203] ACPI: SSDT 0x00000000BC95A000 0000BF (v01 AMD AmdTable 00001000 INTL 20120913) [ 0.071208] ACPI: SSDT 0x00000000BC956000 0010AF (v02 AMD MYRTLE 00000001 INTL 20120913) [ 0.071213] ACPI: FPDT 0x00000000BC955000 000044 (v01 ALASKA A M I 01072009 AMI 01000013) [ 0.071217] ACPI: Reserving APIC table memory at [mem 0xbefffda8-0xbeffffff] [ 0.071220] ACPI: Reserving FACP table memory at [mem 0xbc97a000-0xbc97a113] [ 0.071222] ACPI: Reserving DSDT table memory at [mem 0xbc973000-0xbc9790d9] [ 0.071225] ACPI: Reserving FACS table memory at [mem 0xbd060000-0xbd06003f] [ 0.071227] ACPI: Reserving SSDT table memory at [mem 0xbc980000-0xbc988ce8] [ 0.071229] ACPI: Reserving SSDT table memory at [mem 0xbc97c000-0xbc97fcb5] [ 0.071232] ACPI: Reserving SSDT table memory at [mem 0xbc97b000-0xbc97b1cb] [ 0.071234] ACPI: Reserving MCFG table memory at [mem 0xbc971000-0xbc97103b] [ 0.071236] ACPI: Reserving TPM2 table memory at [mem 0xbc96c000-0xbc96c04b] [ 0.071239] ACPI: Reserving SSDT table memory at [mem 0xbc962000-0xbc96a032] [ 0.071241] ACPI: Reserving SSDT table memory at [mem 0xbc95b000-0xbc95e7c3] [ 0.071243] ACPI: Reserving SSDT table memory at [mem 0xbc95a000-0xbc95a0be] [ 0.071246] ACPI: Reserving SSDT table memory at [mem 0xbc956000-0xbc9570ae] [ 0.071248] ACPI: Reserving FPDT table memory at [mem 0xbc955000-0xbc955043] [ 0.071454] No NUMA configuration found [ 0.071457] Faking a node at [mem 0x0000000000000000-0x0000000c3f2fffff] [ 0.071468] NODE_DATA(0) allocated [mem 0x943f27280-0x943f51fff] [ 0.071657] Zone ranges: [ 0.071659] DMA [mem 0x0000000000001000-0x0000000000ffffff] [ 0.071662] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] [ 0.071665] Normal [mem 0x0000000100000000-0x0000000c3f2fffff] [ 0.071668] Device empty [ 0.071671] Movable zone start for each node [ 0.071674] Early memory node ranges [ 0.071676] node 0: [mem 0x0000000000001000-0x000000000009ffff] [ 0.071679] node 0: [mem 0x0000000000100000-0x0000000009bfefff] [ 0.071682] node 0: [mem 0x000000000a000000-0x000000000a1fffff] [ 0.071684] node 0: [mem 0x000000000a20e000-0x000000000affffff] [ 0.071686] node 0: [mem 0x000000000b020000-0x00000000bb13afff] [ 0.071689] node 0: [mem 0x00000000bdbff000-0x00000000beffefff] [ 0.071691] node 0: [mem 0x0000000100000000-0x0000000c3f2fffff] [ 0.071698] Initmem setup node 0 [mem 0x0000000000001000-0x0000000c3f2fffff] [ 0.071704] On node 0, zone DMA: 1 pages in unavailable ranges [ 0.071722] On node 0, zone DMA: 96 pages in unavailable ranges [ 0.071858] On node 0, zone DMA32: 1025 pages in unavailable ranges [ 0.071873] On node 0, zone DMA32: 14 pages in unavailable ranges [ 0.075072] On node 0, zone DMA32: 32 pages in unavailable ranges [ 0.075202] On node 0, zone DMA32: 10948 pages in unavailable ranges [ 0.145002] On node 0, zone Normal: 4097 pages in unavailable ranges [ 0.145037] On node 0, zone Normal: 3328 pages in unavailable ranges [ 0.146328] ACPI: PM-Timer IO Port: 0x808 [ 0.146374] IOAPIC[0]: apic_id 33, version 17, address 0xfec00000, GSI 0-23 [ 0.146398] IOAPIC[1]: apic_id 34, version 17, address 0xfec01000, GSI 24-55 [ 0.146402] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.146405] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.146410] ACPI: Using ACPI (MADT) for SMP configuration information [ 0.146419] CPU topo: Max. logical packages: 2 [ 0.146421] CPU topo: Max. logical nodes: 1 [ 0.146424] CPU topo: Num. nodes per package: 1 [ 0.146430] CPU topo: Max. logical dies: 2 [ 0.146433] CPU topo: Max. dies per package: 1 [ 0.146444] CPU topo: Max. threads per core: 1 [ 0.146447] CPU topo: Num. cores per package: 16 [ 0.146449] CPU topo: Num. threads per package: 16 [ 0.146452] CPU topo: Allowing 32 present CPUs plus 0 hotplug CPUs [ 0.146478] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.146481] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000fffff] [ 0.146485] PM: hibernation: Registered nosave memory: [mem 0x09bff000-0x09ffffff] [ 0.146488] PM: hibernation: Registered nosave memory: [mem 0x0a200000-0x0a20dfff] [ 0.146491] PM: hibernation: Registered nosave memory: [mem 0x0b000000-0x0b01ffff] [ 0.146494] PM: hibernation: Registered nosave memory: [mem 0xbb13b000-0xbdbfefff] [ 0.146497] PM: hibernation: Registered nosave memory: [mem 0xbefff000-0xffffffff] [ 0.146501] [mem 0xc0000000-0xefffffff] available for PCI devices [ 0.146507] Booting kernel on Xen PVH [ 0.146510] Xen version: 4.21.1 [ 0.146514] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns [ 0.151561] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:32 nr_cpu_ids:32 nr_node_ids:1 [ 0.153193] percpu: Embedded 84 pages/cpu s221184 r8192 d114688 u524288 [ 0.153201] pcpu-alloc: s221184 r8192 d114688 u524288 alloc=1*2097152 [ 0.153205] pcpu-alloc: [0] 00 01 02 03 [0] 04 05 06 07 [ 0.153212] pcpu-alloc: [0] 08 09 10 11 [0] 12 13 14 15 [ 0.153219] pcpu-alloc: [0] 16 17 18 19 [0] 20 21 22 23 [ 0.153225] pcpu-alloc: [0] 24 25 26 27 [0] 28 29 30 31 [ 0.153252] xen: PV spinlocks enabled [ 0.153256] PV qspinlock hash table entries: 256 (order: 0, 4096 bytes, linear) [ 0.153260] Kernel command line: placeholder root=UUID=5a7af636-54c3-4f76-a164-c1138de257ad ro rootflags=subvol=@ rhgb quiet console=hvc0 earlyprintk=xen loglevel=8 "dyndbg=file amd_node.c +p" [ 0.153350] Unknown kernel command line parameters "placeholder rhgb", will be passed to user space. [ 0.153368] random: crng init done [ 0.153371] printk: log buffer data + meta data: 262144 + 917504 = 1179648 bytes [ 0.159204] Dentry cache hash table entries: 8388608 (order: 14, 67108864 bytes, linear) [ 0.162209] Inode-cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear) [ 0.162306] software IO TLB: area num 32. [ 0.173962] Fallback order for Node 0: 0 [ 0.173969] Built 1 zonelists, mobility grouping on. Total pages: 12563371 [ 0.173975] Policy zone: Normal [ 0.174203] mem auto-init: stack:all(zero), heap alloc:on, heap free:off [ 0.269440] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=32, Nodes=1 Poking KASLR using RDRAND RDTSC... [ 0.280270] ftrace: allocating 63414 entries in 248 pages [ 0.280275] ftrace: allocated 248 pages with 5 groups [ 0.280866] Dynamic Preempt: lazy [ 0.280976] rcu: Preemptible hierarchical RCU implementation. [ 0.280978] rcu: RCU event tracing is enabled. [ 0.280981] rcu: RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=32. [ 0.280984] Trampoline variant of Tasks RCU enabled. [ 0.280986] Rude variant of Tasks RCU enabled. [ 0.280988] Tracing variant of Tasks RCU enabled. [ 0.280990] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies. [ 0.280993] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=32 [ 0.281011] RCU Tasks: Setting shift to 5 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=32. [ 0.281015] RCU Tasks Rude: Setting shift to 5 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=32. [ 0.281019] RCU Tasks Trace: Setting shift to 5 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=32. [ 0.284778] Using NULL legacy PIC [ 0.284781] NR_IRQS: 524544, nr_irqs: 1224, preallocated irqs: 0 [ 0.285120] xen:events: Using FIFO-based ABI [ 0.285131] xen:events: Xen HVM callback vector for event delivery is enabled [ 0.285177] rcu: srcu_init: Setting srcu_struct sizes based on contention. [ 0.285270] kfence: initialized - using 2097152 bytes for 255 objects at 0x(____ptrval____)-0x(____ptrval____) [ 0.285337] Console: colour dummy device 80x25 [ 0.285342] printk: legacy console [tty0] enabled [ 0.285541] printk: legacy console [hvc0] enabled [ 0.285541] printk: legacy console [hvc0] enabled [ 0.285550] printk: legacy bootconsole [xenboot0] disabled [ 0.285550] printk: legacy bootconsole [xenboot0] disabled [ 0.285583] ACPI: Core revision 20250807 [ 0.300833] Failed to register legacy timer interrupt [ 0.300840] APIC: Switch to symmetric I/O mode setup [ 0.301293] x2apic enabled [ 0.301817] APIC: Switched APIC routing to: physical x2apic [ 0.301895] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x30ead6a4c9c, max_idle_ns: 440795297796 ns [ 0.301912] Calibrating delay loop (skipped), value calculated using timer frequency.. 6787.28 BogoMIPS (lpj=3393640) [ 0.301985] x86/cpu: User Mode Instruction Prevention (UMIP) activated [ 0.302017] Last level iTLB entries: 4KB 512, 2MB 512, 4MB 256 [ 0.302025] Last level dTLB entries: 4KB 2048, 2MB 2048, 4MB 1024, 1GB 0 [ 0.302038] mitigations: Enabled attack vectors: user_kernel, user_user, guest_host, guest_guest, SMT mitigations: auto [ 0.302052] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl [ 0.302063] Transient Scheduler Attacks: Mitigation: Clear CPU buffers [ 0.302071] Spectre V2 : Mitigation: Retpolines [ 0.302077] Speculative Return Stack Overflow: Mitigation: Safe RET [ 0.302085] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization [ 0.302096] Spectre V2 : Spectre v2 / SpectreRSB: Filling RSB on context switch and VMEXIT [ 0.302105] Spectre V2 : Enabling Restricted Speculation for firmware calls [ 0.302113] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier [ 0.302124] active return thunk: srso_alias_return_thunk [ 0.302146] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' [ 0.302155] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' [ 0.302163] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' [ 0.302170] x86/fpu: Supporting XSAVE feature 0x200: 'Protection Keys User registers' [ 0.302179] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 [ 0.302187] x86/fpu: xstate_offset[9]: 832, xstate_sizes[9]: 8 [ 0.302195] x86/fpu: Enabled xstate features 0x207, context size is 840 bytes, using 'compacted' format. [ 0.302910] Freeing SMP alternatives memory: 56K [ 0.302910] pid_max: default: 32768 minimum: 301 [ 0.302910] Yama: becoming mindful. [ 0.302910] SELinux: Initializing. [ 0.302910] LSM support for eBPF active [ 0.302910] landlock: Up and running. [ 0.302910] Mount-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 0.302910] Mountpoint-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 0.302910] clocksource: xen: mask: 0xffffffffffffffff max_cycles: 0x1cd42e4dffb, max_idle_ns: 881590591483 ns [ 0.302910] Xen: using vcpuop timer interface [ 0.302910] installing Xen timer for CPU 0 [ 0.302910] smpboot: CPU0: AMD Ryzen 9 5950X 16-Core Processor (family: 0x19, model: 0x21, stepping: 0x2) [ 0.302910] cpu 0 spinlock event irq 28 [ 0.302910] Performance Events: PMU not available due to virtualization, using software events only. [ 0.302910] signal: max sigframe size: 3376 [ 0.302910] rcu: Hierarchical SRCU implementation. [ 0.302910] rcu: Max phase no-delay instances is 400. [ 0.302910] Timer migration: 2 hierarchy levels; 8 children per group; 2 crossnode level [ 0.359391] NMI watchdog: Perf NMI watchdog permanently disabled [ 0.359660] smp: Bringing up secondary CPUs ... [ 0.359824] installing Xen timer for CPU 1 [ 0.359889] smpboot: x86: Booting SMP configuration: [ 0.359898] .... node #0, CPUs: #1 [ 0.361128] installing Xen timer for CPU 2 [ 0.361219] #2 [ 0.361608] installing Xen timer for CPU 3 [ 0.361689] #3 [ 0.362112] installing Xen timer for CPU 4 [ 0.362189] #4 [ 0.362581] installing Xen timer for CPU 5 [ 0.362663] #5 [ 0.363109] installing Xen timer for CPU 6 [ 0.363202] #6 [ 0.363612] installing Xen timer for CPU 7 [ 0.363702] #7 [ 0.364123] installing Xen timer for CPU 8 [ 0.364203] #8 [ 0.364545] installing Xen timer for CPU 9 [ 0.364631] #9 [ 0.364997] installing Xen timer for CPU 10 [ 0.365084] #10 [ 0.365451] installing Xen timer for CPU 11 [ 0.365531] #11 [ 0.365955] installing Xen timer for CPU 12 [ 0.366062] #12 [ 0.366407] installing Xen timer for CPU 13 [ 0.366482] #13 [ 0.366832] installing Xen timer for CPU 14 [ 0.366932] #14 [ 0.367308] installing Xen timer for CPU 15 [ 0.367407] #15 [ 0.367802] installing Xen timer for CPU 16 [ 0.367890] #16 [ 0.368283] installing Xen timer for CPU 17 [ 0.368384] #17 [ 0.368846] installing Xen timer for CPU 18 [ 0.368978] #18 [ 0.369408] installing Xen timer for CPU 19 [ 0.369519] #19 [ 0.369991] installing Xen timer for CPU 20 [ 0.370110] #20 [ 0.370551] installing Xen timer for CPU 21 [ 0.370680] #21 [ 0.371143] installing Xen timer for CPU 22 [ 0.371256] #22 [ 0.371695] installing Xen timer for CPU 23 [ 0.371812] #23 [ 0.372261] installing Xen timer for CPU 24 [ 0.372383] #24 [ 0.372818] installing Xen timer for CPU 25 [ 0.372940] #25 [ 0.373402] installing Xen timer for CPU 26 [ 0.373515] #26 [ 0.373950] installing Xen timer for CPU 27 [ 0.374077] #27 [ 0.374519] installing Xen timer for CPU 28 [ 0.374635] #28 [ 0.375078] installing Xen timer for CPU 29 [ 0.375194] #29 [ 0.375586] installing Xen timer for CPU 30 [ 0.375688] #30 [ 0.376132] installing Xen timer for CPU 31 [ 0.376246] #31 [ 0.377089] cpu 1 spinlock event irq 153 [ 0.378076] cpu 2 spinlock event irq 154 [ 0.379031] cpu 3 spinlock event irq 155 [ 0.380017] cpu 4 spinlock event irq 156 [ 0.381042] cpu 5 spinlock event irq 157 [ 0.382021] cpu 6 spinlock event irq 158 [ 0.383039] cpu 7 spinlock event irq 159 [ 0.384023] cpu 8 spinlock event irq 160 [ 0.385038] cpu 9 spinlock event irq 161 [ 0.386022] cpu 10 spinlock event irq 162 [ 0.387040] cpu 11 spinlock event irq 163 [ 0.388023] cpu 12 spinlock event irq 164 [ 0.389025] cpu 13 spinlock event irq 165 [ 0.390037] cpu 14 spinlock event irq 166 [ 0.391026] cpu 15 spinlock event irq 167 [ 0.392013] cpu 16 spinlock event irq 168 [ 0.393005] cpu 17 spinlock event irq 169 [ 0.394031] cpu 18 spinlock event irq 170 [ 0.395005] cpu 19 spinlock event irq 171 [ 0.396017] cpu 20 spinlock event irq 172 [ 0.397005] cpu 21 spinlock event irq 173 [ 0.398001] cpu 22 spinlock event irq 174 [ 0.399005] cpu 23 spinlock event irq 175 [ 0.400003] cpu 24 spinlock event irq 176 [ 0.401003] cpu 25 spinlock event irq 177 [ 0.402003] cpu 26 spinlock event irq 178 [ 0.403003] cpu 27 spinlock event irq 179 [ 0.404002] cpu 28 spinlock event irq 180 [ 0.404993] cpu 29 spinlock event irq 181 [ 0.406017] cpu 30 spinlock event irq 182 [ 0.406993] cpu 31 spinlock event irq 183 [ 0.407207] smp: Brought up 1 node, 32 CPUs [ 0.407220] smpboot: Total of 32 processors activated (217192.96 BogoMIPS) [ 0.408613] Memory: 36627636K/50253484K available (22589K kernel code, 4588K rwdata, 17848K rodata, 5196K init, 5796K bss, 13585756K reserved, 0K cma-reserved) [ 0.409528] devtmpfs: initialized [ 0.409599] x86/mm: Memory block size: 128MB [ 0.415459] ACPI: PM: Registering ACPI NVS region [mem 0x0a200000-0x0a20dfff] (57344 bytes) [ 0.415459] ACPI: PM: Registering ACPI NVS region [mem 0xbc989000-0xbd07cfff] (7290880 bytes) [ 0.415921] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns [ 0.415972] posixtimers hash table entries: 16384 (order: 6, 262144 bytes, linear) [ 0.416023] futex hash table entries: 8192 (524288 bytes on 1 NUMA nodes, total 512 KiB, linear). [ 0.416270] PM: RTC time: 11:42:23, date: 2026-04-07 [ 0.417104] NET: Registered PF_NETLINK/PF_ROUTE protocol family [ 0.417135] xen:grant_table: Grant tables using version 1 layout [ 0.417163] Grant table initialized [ 0.418162] DMA: preallocated 4096 KiB GFP_KERNEL pool for atomic allocations [ 0.418336] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations [ 0.418516] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations [ 0.418539] audit: initializing netlink subsys (disabled) [ 0.418583] audit: type=2000 audit(1775562143.863:1): state=initialized audit_enabled=0 res=1 [ 0.418583] thermal_sys: Registered thermal governor 'fair_share' [ 0.418583] thermal_sys: Registered thermal governor 'bang_bang' [ 0.418583] thermal_sys: Registered thermal governor 'step_wise' [ 0.418583] thermal_sys: Registered thermal governor 'user_space' [ 0.420010] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 [ 0.420517] PCI: ECAM [mem 0xf0000000-0xf7ffffff] (base 0xf0000000) for domain 0000 [bus 00-7f] [ 0.420543] PCI: Using configuration type 1 for base access [ 0.420736] kprobes: kprobe jump-optimization is enabled. All kprobes are optimized if possible. [ 0.421021] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages [ 0.421034] HugeTLB: 16380 KiB vmemmap can be freed for a 1.00 GiB page [ 0.421045] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages [ 0.421055] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page [ 0.435710] raid6: skipped pq benchmark and selected avx2x4 [ 0.435722] raid6: using avx2x2 recovery algorithm [ 0.435806] fbcon: Taking over console [ 0.435847] ACPI: Added _OSI(Module Device) [ 0.435855] ACPI: Added _OSI(Processor Device) [ 0.435864] ACPI: Added _OSI(Processor Aggregator Device) [ 0.465547] ACPI: 8 ACPI AML tables successfully acquired and loaded [ 0.468587] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored [ 0.476748] ACPI: Interpreter enabled [ 0.476776] ACPI: PM: (supports S0 S3 S4 S5) [ 0.476786] ACPI: Using IOAPIC for interrupt routing [ 0.478526] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug [ 0.478541] PCI: Ignoring E820 reservations for host bridge windows [ 0.479180] ACPI: Enabled 3 GPEs in block 00 to 1F [ 0.499677] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.499694] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3] [ 0.499860] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug LTR DPC] [ 0.500156] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] [ 0.500180] acpi PNP0A08:00: [Firmware Info]: ECAM [mem 0xf0000000-0xf7ffffff] for domain 0000 [bus 00-7f] only partially covers this bridge [ 0.500927] PCI host bridge to bus 0000:00 [ 0.500954] pci_bus 0000:00: root bus resource [io 0x0000-0x03af window] [ 0.500966] pci_bus 0000:00: root bus resource [io 0x03e0-0x0cf7 window] [ 0.500977] pci_bus 0000:00: root bus resource [io 0x03b0-0x03df window] [ 0.500988] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] [ 0.500999] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000dffff window] [ 0.501013] pci_bus 0000:00: root bus resource [mem 0xc0000000-0xfcffffff window] [ 0.501026] pci_bus 0000:00: root bus resource [mem 0xc40000000-0xffffffffff window] [ 0.501039] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.501081] pci 0000:00:00.0: [1022:1480] type 00 class 0x060000 conventional PCI endpoint [ 0.501399] pci 0000:00:00.2: [1022:1481] type 00 class 0x080600 conventional PCI endpoint [ 0.501681] pci 0000:00:01.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.501909] pci 0000:00:01.1: [1022:1483] type 01 class 0x060400 PCIe Root Port [ 0.501975] pci 0000:00:01.1: PCI bridge to [bus 01] [ 0.502000] pci 0000:00:01.1: bridge window [mem 0xfcc00000-0xfccfffff] [ 0.502219] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold [ 0.502623] pci 0000:00:01.3: [1022:1483] type 01 class 0x060400 PCIe Root Port [ 0.502690] pci 0000:00:01.3: PCI bridge to [bus 02-06] [ 0.502710] pci 0000:00:01.3: bridge window [io 0xe000-0xffff] [ 0.502725] pci 0000:00:01.3: bridge window [mem 0xfc500000-0xfc8fffff] [ 0.502777] pci 0000:00:01.3: enabling Extended Tags [ 0.502950] pci 0000:00:01.3: PME# supported from D0 D3hot D3cold [ 0.503357] pci 0000:00:02.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.503577] pci 0000:00:03.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.503812] pci 0000:00:03.1: [1022:1483] type 01 class 0x060400 PCIe Root Port [ 0.503886] pci 0000:00:03.1: PCI bridge to [bus 07-0a] [ 0.503914] pci 0000:00:03.1: bridge window [mem 0xfb000000-0xfc3fffff] [ 0.503947] pci 0000:00:03.1: bridge window [mem 0xf800000000-0xfc007fffff 64bit pref] [ 0.504165] pci 0000:00:03.1: PME# supported from D0 D3hot D3cold [ 0.504567] pci 0000:00:04.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.504785] pci 0000:00:05.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.505009] pci 0000:00:07.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.505243] pci 0000:00:07.1: [1022:1484] type 01 class 0x060400 PCIe Root Port [ 0.505310] pci 0000:00:07.1: PCI bridge to [bus 0b] [ 0.505372] pci 0000:00:07.1: enabling Extended Tags [ 0.505551] pci 0000:00:07.1: PME# supported from D0 D3hot D3cold [ 0.505939] pci 0000:00:08.0: [1022:1482] type 00 class 0x060000 conventional PCI endpoint [ 0.506169] pci 0000:00:08.1: [1022:1484] type 01 class 0x060400 PCIe Root Port [ 0.506235] pci 0000:00:08.1: PCI bridge to [bus 0c] [ 0.506259] pci 0000:00:08.1: bridge window [mem 0xfc900000-0xfcbfffff] [ 0.506308] pci 0000:00:08.1: enabling Extended Tags [ 0.506493] pci 0000:00:08.1: PME# supported from D0 D3hot D3cold [ 0.506909] pci 0000:00:14.0: [1022:790b] type 00 class 0x0c0500 conventional PCI endpoint [ 0.507154] pci 0000:00:14.3: [1022:790e] type 00 class 0x060100 conventional PCI endpoint [ 0.507428] pci 0000:00:18.0: [1022:1440] type 00 class 0x060000 conventional PCI endpoint [ 0.507606] pci 0000:00:18.1: [1022:1441] type 00 class 0x060000 conventional PCI endpoint [ 0.507782] pci 0000:00:18.2: [1022:1442] type 00 class 0x060000 conventional PCI endpoint [ 0.508000] pci 0000:00:18.3: [1022:1443] type 00 class 0x060000 conventional PCI endpoint [ 0.508181] pci 0000:00:18.4: [1022:1444] type 00 class 0x060000 conventional PCI endpoint [ 0.508362] pci 0000:00:18.5: [1022:1445] type 00 class 0x060000 conventional PCI endpoint [ 0.508538] pci 0000:00:18.6: [1022:1446] type 00 class 0x060000 conventional PCI endpoint [ 0.508715] pci 0000:00:18.7: [1022:1447] type 00 class 0x060000 conventional PCI endpoint [ 0.509189] pci 0000:01:00.0: [1987:5012] type 00 class 0x010802 PCIe Endpoint [ 0.509919] pci 0000:01:00.0: BAR 0 [mem 0xfcc00000-0xfcc03fff 64bit] [ 0.511735] pci 0000:00:01.1: PCI bridge to [bus 01] [ 0.511910] pci 0000:02:00.0: [1022:43d5] type 00 class 0x0c0330 PCIe Legacy Endpoint [ 0.512102] pci 0000:02:00.0: BAR 0 [mem 0xfc8a0000-0xfc8a7fff 64bit] [ 0.512141] pci 0000:02:00.0: enabling Extended Tags [ 0.512301] pci 0000:02:00.0: PME# supported from D3hot D3cold [ 0.512670] pci 0000:02:00.1: [1022:43c8] type 00 class 0x010601 PCIe Legacy Endpoint [ 0.513061] pci 0000:02:00.1: BAR 5 [mem 0xfc880000-0xfc89ffff] [ 0.513075] pci 0000:02:00.1: ROM [mem 0xfc800000-0xfc87ffff pref] [ 0.513101] pci 0000:02:00.1: enabling Extended Tags [ 0.513216] pci 0000:02:00.1: PME# supported from D3hot D3cold [ 0.513476] pci 0000:02:00.2: [1022:43c6] type 01 class 0x060400 PCIe Switch Upstream Port [ 0.513554] pci 0000:02:00.2: PCI bridge to [bus 03-06] [ 0.513575] pci 0000:02:00.2: bridge window [io 0xe000-0xffff] [ 0.513591] pci 0000:02:00.2: bridge window [mem 0xfc500000-0xfc7fffff] [ 0.513652] pci 0000:02:00.2: enabling Extended Tags [ 0.513768] pci 0000:02:00.2: PME# supported from D3hot D3cold [ 0.514074] pci 0000:00:01.3: PCI bridge to [bus 02-06] [ 0.514295] pci 0000:03:00.0: [1022:43c7] type 01 class 0x060400 PCIe Switch Downstream Port [ 0.514376] pci 0000:03:00.0: PCI bridge to [bus 04] [ 0.514456] pci 0000:03:00.0: enabling Extended Tags [ 0.514605] pci 0000:03:00.0: PME# supported from D3hot D3cold [ 0.514900] pci 0000:03:01.0: [1022:43c7] type 01 class 0x060400 PCIe Switch Downstream Port [ 0.514983] pci 0000:03:01.0: PCI bridge to [bus 05] [ 0.515006] pci 0000:03:01.0: bridge window [io 0xf000-0xffff] [ 0.515022] pci 0000:03:01.0: bridge window [mem 0xfc700000-0xfc7fffff] [ 0.515088] pci 0000:03:01.0: enabling Extended Tags [ 0.515240] pci 0000:03:01.0: PME# supported from D3hot D3cold [ 0.515537] pci 0000:03:04.0: [1022:43c7] type 01 class 0x060400 PCIe Switch Downstream Port [ 0.515617] pci 0000:03:04.0: PCI bridge to [bus 06] [ 0.515638] pci 0000:03:04.0: bridge window [io 0xe000-0xefff] [ 0.515654] pci 0000:03:04.0: bridge window [mem 0xfc500000-0xfc6fffff] [ 0.515719] pci 0000:03:04.0: enabling Extended Tags [ 0.515867] pci 0000:03:04.0: PME# supported from D3hot D3cold [ 0.516190] pci 0000:02:00.2: PCI bridge to [bus 03-06] [ 0.516310] pci 0000:03:00.0: PCI bridge to [bus 04] [ 0.516483] pci 0000:05:00.0: [10ec:8168] type 00 class 0x020000 PCIe Endpoint [ 0.516699] pci 0000:05:00.0: BAR 0 [io 0xf000-0xf0ff] [ 0.516725] pci 0000:05:00.0: BAR 2 [mem 0xfc704000-0xfc704fff 64bit] [ 0.516747] pci 0000:05:00.0: BAR 4 [mem 0xfc700000-0xfc703fff 64bit] [ 0.517016] pci 0000:05:00.0: supports D1 D2 [ 0.517029] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.517537] pci 0000:03:01.0: PCI bridge to [bus 05] [ 0.517708] pci 0000:06:00.0: [1000:0087] type 00 class 0x010700 PCIe Endpoint [ 0.517828] pci 0000:06:00.0: BAR 0 [io 0xe000-0xe0ff] [ 0.517844] pci 0000:06:00.0: BAR 1 [mem 0xfc640000-0xfc64ffff 64bit] [ 0.517861] pci 0000:06:00.0: BAR 3 [mem 0xfc600000-0xfc63ffff 64bit] [ 0.517878] pci 0000:06:00.0: ROM [mem 0xfc500000-0xfc5fffff pref] [ 0.517906] pci 0000:06:00.0: enabling Extended Tags [ 0.518114] pci 0000:06:00.0: supports D1 D2 [ 0.518302] pci 0000:06:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:03:04.0 (capable of 63.008 Gb/s with 8.0 GT/s PCIe x8 link) [ 0.518473] pci 0000:03:04.0: PCI bridge to [bus 06] [ 0.518897] pci 0000:07:00.0: [8086:e2ff] type 01 class 0x060400 PCIe Switch Upstream Port [ 0.519217] pci 0000:07:00.0: BAR 0 [mem 0xfc00000000-0xfc007fffff 64bit pref] [ 0.519243] pci 0000:07:00.0: PCI bridge to [bus 08-0a] [ 0.519278] pci 0000:07:00.0: bridge window [mem 0xfb000000-0xfc3fffff] [ 0.519321] pci 0000:07:00.0: bridge window [mem 0xf800000000-0xfbffffffff 64bit pref] [ 0.519927] pci 0000:07:00.0: PME# supported from D0 D3hot D3cold [ 0.520607] pci 0000:07:00.0: 63.008 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x8 link at 0000:00:03.1 (capable of 252.056 Gb/s with 32.0 GT/s PCIe x8 link) [ 0.520986] pci 0000:00:03.1: PCI bridge to [bus 07-0a] [ 0.521316] pci 0000:08:01.0: [8086:e2f0] type 01 class 0x060400 PCIe Switch Downstream Port [ 0.521405] pci 0000:08:01.0: PCI bridge to [bus 09] [ 0.521429] pci 0000:08:01.0: bridge window [mem 0xfb000000-0xfc1fffff] [ 0.521465] pci 0000:08:01.0: bridge window [mem 0xf800000000-0xfbffffffff 64bit pref] [ 0.521630] pci 0000:08:01.0: PME# supported from D0 D3hot D3cold [ 0.521976] pci 0000:08:02.0: [8086:e2f1] type 01 class 0x060400 PCIe Switch Downstream Port [ 0.522073] pci 0000:08:02.0: PCI bridge to [bus 0a] [ 0.522099] pci 0000:08:02.0: bridge window [mem 0xfc300000-0xfc3fffff] [ 0.522307] pci 0000:08:02.0: PME# supported from D0 D3hot D3cold [ 0.522787] pci 0000:07:00.0: PCI bridge to [bus 08-0a] [ 0.522956] pci 0000:09:00.0: [8086:e212] type 00 class 0x030000 PCIe Endpoint [ 0.596925] pci 0000:09:00.0: BAR 0 [mem 0xfb000000-0xfbffffff 64bit] [ 0.596945] pci 0000:09:00.0: BAR 2 [mem 0xf800000000-0xfbffffffff 64bit pref] [ 0.596967] pci 0000:09:00.0: ROM [mem 0xfc000000-0xfc1fffff pref] [ 0.597358] pci 0000:09:00.0: PME# supported from D0 D3hot [ 0.599097] pci 0000:08:01.0: PCI bridge to [bus 09] [ 0.599278] pci 0000:0a:00.0: [8086:e2f7] type 00 class 0x040300 PCIe Endpoint [ 0.599422] pci 0000:0a:00.0: BAR 0 [mem 0xfc300000-0xfc303fff 64bit] [ 0.599509] pci 0000:0a:00.0: PME# supported from D3hot D3cold [ 0.600261] pci 0000:08:02.0: PCI bridge to [bus 0a] [ 0.600499] pci 0000:0b:00.0: [1022:148a] type 00 class 0x130000 PCIe Endpoint [ 0.600607] pci 0000:0b:00.0: enabling Extended Tags [ 0.601172] pci 0000:00:07.1: PCI bridge to [bus 0b] [ 0.601336] pci 0000:0c:00.0: [1022:1485] type 00 class 0x130000 PCIe Endpoint [ 0.601445] pci 0000:0c:00.0: enabling Extended Tags [ 0.601954] pci 0000:0c:00.1: [1022:1486] type 00 class 0x108000 PCIe Endpoint [ 0.602047] pci 0000:0c:00.1: BAR 2 [mem 0xfca00000-0xfcafffff] [ 0.602064] pci 0000:0c:00.1: BAR 5 [mem 0xfcb08000-0xfcb09fff] [ 0.602090] pci 0000:0c:00.1: enabling Extended Tags [ 0.602541] pci 0000:0c:00.3: [1022:149c] type 00 class 0x0c0330 PCIe Endpoint [ 0.605219] pci 0000:0c:00.3: BAR 0 [mem 0xfc900000-0xfc9fffff 64bit] [ 0.605254] pci 0000:0c:00.3: enabling Extended Tags [ 0.605409] pci 0000:0c:00.3: PME# supported from D0 D3hot D3cold [ 0.605754] pci 0000:0c:00.4: [1022:1487] type 00 class 0x040300 PCIe Endpoint [ 0.605842] pci 0000:0c:00.4: BAR 0 [mem 0xfcb00000-0xfcb07fff] [ 0.605879] pci 0000:0c:00.4: enabling Extended Tags [ 0.606023] pci 0000:0c:00.4: PME# supported from D0 D3hot D3cold [ 0.606383] pci 0000:00:08.1: PCI bridge to [bus 0c] [ 0.611478] ACPI: PCI: Interrupt link LNKA configured for IRQ 0 [ 0.611575] ACPI: PCI: Interrupt link LNKB configured for IRQ 0 [ 0.611657] ACPI: PCI: Interrupt link LNKC configured for IRQ 0 [ 0.611753] ACPI: PCI: Interrupt link LNKD configured for IRQ 0 [ 0.611844] ACPI: PCI: Interrupt link LNKE configured for IRQ 0 [ 0.611930] ACPI: PCI: Interrupt link LNKF configured for IRQ 0 [ 0.612006] ACPI: PCI: Interrupt link LNKG configured for IRQ 0 [ 0.612081] ACPI: PCI: Interrupt link LNKH configured for IRQ 0 [ 0.613305] xen:balloon: Initialising balloon driver [ 0.613928] iommu: Default domain type: Translated [ 0.613930] iommu: DMA domain TLB invalidation policy: lazy mode [ 0.615031] SCSI subsystem initialized [ 0.615053] libata version 3.00 loaded. [ 0.615053] ACPI: bus type USB registered [ 0.615053] usbcore: registered new interface driver usbfs [ 0.615053] usbcore: registered new interface driver hub [ 0.615053] usbcore: registered new device driver usb [ 0.615053] pps_core: LinuxPPS API ver. 1 registered [ 0.615053] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti [ 0.615053] PTP clock support registered [ 0.615053] EDAC MC: Ver: 3.0.0 [ 0.615958] efivars: Registered efivars operations [ 0.616210] NetLabel: Initializing [ 0.616220] NetLabel: domain hash size = 128 [ 0.616229] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO [ 0.616258] NetLabel: unlabeled traffic allowed by default [ 0.616270] mctp: management component transport protocol core [ 0.616281] NET: Registered PF_MCTP protocol family [ 0.616302] PCI: Using ACPI for IRQ routing [ 0.625913] PCI: pci_cache_line_size set to 64 bytes [ 0.626741] e820: reserve RAM buffer [mem 0x09bff000-0x0bffffff] [ 0.626752] e820: reserve RAM buffer [mem 0x0a200000-0x0bffffff] [ 0.626762] e820: reserve RAM buffer [mem 0x0b000000-0x0bffffff] [ 0.626772] e820: reserve RAM buffer [mem 0xbb13b000-0xbbffffff] [ 0.626782] e820: reserve RAM buffer [mem 0xbefffd00-0xbfffffff] [ 0.626792] e820: reserve RAM buffer [mem 0xc3f300000-0xc3fffffff] [ 0.627097] pci 0000:09:00.0: vgaarb: setting as boot VGA device [ 0.627138] pci 0000:09:00.0: vgaarb: bridge control possible [ 0.627149] pci 0000:09:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none [ 0.627162] vgaarb: loaded [ 0.627162] pci 0000:00:00.0: Reserving PCI config space [ 0.627162] Found 1 AMD root devices [ 0.627162] Oops: divide error: 0000 [#1] SMP NOPTI [ 0.627162] CPU: 5 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.19.10-200.fc43.x86_64 #1 PREEMPT(lazy) [ 0.627162] Hardware name: To Be Filled By O.E.M. B450M Steel Legend/B450M Steel Legend, BIOS P10.43 06/25/2025 [ 0.627162] RIP: 0010:amd_smn_init+0x1ea/0x280 [ 0.627162] Code: c7 c7 13 de 16 83 e8 85 7c 44 fd eb 6f 48 89 df e8 0b 18 ca fc 48 89 c3 48 85 c0 0f 84 5b ff ff ff 44 89 e8 31 d2 45 8d 7d 01 <66> f7 f5 66 85 d2 75 42 eb 02 eb 2c 41 0f b7 ce 48 8d b3 c8 00 00 [ 0.627162] RSP: 0018:ffffc9000004fe28 EFLAGS: 00010246 [ 0.627162] RAX: 0000000000000000 RBX: ffff888103fd9000 RCX: 0000000000000005 [ 0.627162] RDX: 0000000000000000 RSI: ffff888103fd9000 RDI: 0000000000000000 [ 0.627164] RBP: 0000000000000000 R08: 0000000000000282 R09: ffff8881040a2f90 [ 0.627176] R10: ffffc9000004fe28 R11: ffffffff84a4c880 R12: 0000000000000002 [ 0.627188] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000001 [ 0.627202] FS: 0000000000000000(0000) GS:ffff88898e66f000(0000) knlGS:0000000000000000 [ 0.627215] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 0.627227] CR2: 0000000000000000 CR3: 0000000003a2e000 CR4: 0000000000750ef0 [ 0.627241] PKRU: 55555554 [ 0.627248] Call Trace: [ 0.627254] [ 0.627261] ? __pfx_amd_smn_init+0x10/0x10 [ 0.627269] do_one_initcall+0x5b/0x300 [ 0.627281] do_initcalls+0x148/0x170 [ 0.627291] kernel_init_freeable+0xf9/0x140 [ 0.627301] ? __pfx_kernel_init+0x10/0x10 [ 0.627311] kernel_init+0x1a/0x140 [ 0.627319] ret_from_fork+0x130/0x1a0 [ 0.627328] ? __pfx_kernel_init+0x10/0x10 [ 0.627338] ret_from_fork_asm+0x1a/0x30 [ 0.627349] [ 0.627355] Modules linked in: [ 0.627364] ---[ end trace 0000000000000000 ]--- [ 0.627373] RIP: 0010:amd_smn_init+0x1ea/0x280 [ 0.627382] Code: c7 c7 13 de 16 83 e8 85 7c 44 fd eb 6f 48 89 df e8 0b 18 ca fc 48 89 c3 48 85 c0 0f 84 5b ff ff ff 44 89 e8 31 d2 45 8d 7d 01 <66> f7 f5 66 85 d2 75 42 eb 02 eb 2c 41 0f b7 ce 48 8d b3 c8 00 00 [ 0.627407] RSP: 0018:ffffc9000004fe28 EFLAGS: 00010246 [ 0.627417] RAX: 0000000000000000 RBX: ffff888103fd9000 RCX: 0000000000000005 [ 0.627428] RDX: 0000000000000000 RSI: ffff888103fd9000 RDI: 0000000000000000 [ 0.627440] RBP: 0000000000000000 R08: 0000000000000282 R09: ffff8881040a2f90 [ 0.627452] R10: ffffc9000004fe28 R11: ffffffff84a4c880 R12: 0000000000000002 [ 0.627463] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000001 [ 0.627476] FS: 0000000000000000(0000) GS:ffff88898e66f000(0000) knlGS:0000000000000000 [ 0.627488] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 0.627498] CR2: 0000000000000000 CR3: 0000000003a2e000 CR4: 0000000000750ef0 [ 0.627510] PKRU: 55555554 [ 0.627517] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b (XEN) Hardware Dom0 crashed: rebooting machine in 5 seconds. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1775575682-BCB64185-4B92CA64/0/0 X-purgate-type: clean X-purgate-size: 2228 On 07.04.2026 16:28, Teddy Astie wrote: > Le 07/04/2026 à 15:35, Jan Beulich a écrit : >> The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() >> and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for >> the (possible) channel put in legacy mode we don't do so during boot >> either. >> >> Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an >> all-zero message (when the passed in CPU mask has no online CPUs). Nothing >> would later call msi_compose_msg() / hpet_msi_write(), and hence nothing >> would later produce a well-formed message template in >> hpet_events[].msi.msg. >> >> Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") >> Reported-by: Marek Marczykowski-Górecki >> Signed-off-by: Jan Beulich >> Tested-by: Marek Marczykowski-Górecki >> --- >> As to the Fixes: tag: The issue for the HPET resume case is the >> cpumask_intersects(desc->arch.cpu_mask, &cpu_online_map) check in >> msi_compose_msg(). The earlier cpumask_empty() wasn't a problem, as >> cpu_mask_to_apicid() returning a bogus (offline) value didn't have any bad >> effect: Before use, a valid destination would have been put in place, but >> other parts of .msg were properly set up. Furthermore we also didn't clear >> the entire message prior to that change. >> >> Many thanks got to Marek for tirelessly trying out various debugging >> suggestions. >> >> --- a/xen/arch/x86/hpet.c >> +++ b/xen/arch/x86/hpet.c >> @@ -685,12 +685,18 @@ void hpet_broadcast_resume(void) >> for ( i = 0; i < n; i++ ) >> { >> if ( hpet_events[i].msi.irq >= 0 ) >> + { >> + struct irq_desc *desc = irq_to_desc(hpet_events[i].msi.irq); >> + >> + cpumask_copy(desc->arch.cpu_mask, cpumask_of(smp_processor_id())); >> + >> __hpet_setup_msi_irq(irq_to_desc(hpet_events[i].msi.irq)); > > We can directly reuse "desc" here since irq_to_desc(...) isn't supposed > to change value with cpumask_copy(). > > i.e `__hpet_setup_msi_irq(desc);` Oh, indeed - how did I not spot this? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 16:00:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 16:00:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275148.1561108 (Exim 4.92) (envelope-from ) id 1wA8qx-0004N0-N6; Tue, 07 Apr 2026 16:00:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275148.1561108; Tue, 07 Apr 2026 16:00:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8qx-0004Mt-KD; Tue, 07 Apr 2026 16:00:35 +0000 Received: by outflank-mailman (input) for mailman id 1275148; Tue, 07 Apr 2026 16:00:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA8qv-0004Mn-CS for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 16:00:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA8qu-004wDb-MZ for xen-devel@lists.xenproject.org; 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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775577630; x=1775847630; bh=Dstru+kHoZmtS5qezTht3r8KRsk+jJpHtfrwwofsbNk=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Gix4KMYJ41zY2aQC3rgRV2t9YRPtOS6NlN6981dZByX3DoT+y++kJTfbqHxfXE3za 1iMtSObOWx6smp2Gx2q7h797FCdNCuTHCqt1iNd5QcS2RcUeUw2+DFIuBWLFTlKM5f GiToabz9+zDAl9q9iHh6/edHSQVvvL3t+69mQ9DdhW9/1SeN5pH6WECXa+MK8kAlgr kKVxrXteyYH592SZ/zujf3igy4rcCISbLxB/tr4phSIMAyb09XD69sbvZSsdfbHK5b aW59mJwf/HhzptGAE38qWxxkW+Mp+KTgKEgtLPHWTpK0LRhs/52HpQIi+7eWm97vJF 7cLAKrsxObUQA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775577630; x=1775838130; i=teddy.astie@vates.tech; bh=Dstru+kHoZmtS5qezTht3r8KRsk+jJpHtfrwwofsbNk=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=i7RSvmCglU0uYfR+41mqWWXTB0AVb39e+HpO2a9+h2SNTBjJGKWPGi/6H2Bn/9I8z l0nhS2f1tuOWrVShpRWwgMxjAZxLQc+fcsszJ1ztnYtVDyZflTpvSMFMlSPpOEZ6QQ ZcmBl6lPcodmZfij9Opd5TcvYb1fqoL7b0EFYbilozvq6l2dFuaG3f2mh4IyDTNSzc VV4KlUpA+ybUMlla0pK+QK51LKJh2hEXdz9BdIyBmD6UycKyLrP7B9aHSCYIV2Kgda /wFzGVRvSGpia19hXFBIr9BIHzRZw+pVJ73KksBzJpjJAm5qLuNAZIYf+/I93RvPXq DVFla4nbdI7Eg== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=20v2]=20x86/emul:=20Remove=20fallback=20path=20from=20SWAPGS?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775577629235 Message-Id: To: "Andrew Cooper" , Xen-devel Cc: "Jan Beulich" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" References: <20260407142351.73049-1-andrew.cooper3@citrix.com> In-Reply-To: <20260407142351.73049-1-andrew.cooper3@citrix.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.a08d790daf4144f5afd24c13c8ce5860?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260407:md Date: Tue, 07 Apr 2026 16:00:30 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1775577632-B3B3051B-5D34BB8B/0/0 X-purgate-type: clean X-purgate-size: 3876 Le 07/04/2026 =C3=A0 16:27, Andrew Cooper a =C3=A9crit=C2=A0: > In real hardware, accesses to the registers cannot fail. The error paths= are > just an artefact of the hook functions needing to return something. > > The best effort unwind is also something that doesn't exist in real hardw= are, > and makes the logic more complicated to follow. Instead, use an > ASSERT_UNREACHABLE() with a fallback of injecting #DF. Hitting this path= is > an error in Xen. > > While adjusting, remove {read,write}_segment() and use {read,write}_msr()= to > access MSR_GS_BASE. There's no need to access the other parts of the GS > segment, and this is less work behind the scenes. > > Signed-off-by: Andrew Cooper > --- > CC: Jan Beulich > CC: Roger Pau Monn=C3=A9 > > v2: > * Retain x86_emul_reset_event() > * Pass an error code for #DF > * Drop goto done now that generate_exception() is used > * Use 2x{read,write}_msr() > > Tested using LKGS's extention of the test emulator for SWAPGS. > --- > xen/arch/x86/x86_emulate/0f01.c | 28 +++++++++++++++------------- > 1 file changed, 15 insertions(+), 13 deletions(-) > > diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0= f01.c > index 6c10979dd650..54bd6faf0f2c 100644 > --- a/xen/arch/x86/x86_emulate/0f01.c > +++ b/xen/arch/x86/x86_emulate/0f01.c > @@ -189,22 +189,24 @@ int x86emul_0f01(struct x86_emulate_state *s, > generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); > fail_if(!ops->read_segment || !ops->read_msr || > !ops->write_segment || !ops->write_msr); Do we still need checks for ops->{read,write}_segment if we're not using them anymore ? > - if ( (rc =3D ops->read_segment(x86_seg_gs, &sreg, > - ctxt)) !=3D X86EMUL_OKAY || > - (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, > + if ( (rc =3D ops->read_msr(MSR_GS_BASE, &sreg.base, > ctxt)) !=3D X86EMUL_OKAY || > - (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, > - ctxt, false)) !=3D X86EMUL_OKAY ) > + (rc =3D ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, > + ctxt)) !=3D X86EMUL_OKAY ) > goto done; > - sreg.base =3D msr_val; > - if ( (rc =3D ops->write_segment(x86_seg_gs, &sreg, > - ctxt)) !=3D X86EMUL_OKAY ) > + if ( (rc =3D ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, > + ctxt, false)) !=3D X86EMUL_OKAY || > + (rc =3D ops->write_msr(MSR_GS_BASE, msr_val, > + ctxt, false)) !=3D X86EMUL_OKAY ) > { > - /* Best effort unwind (i.e. no real error checking). */ > - if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, > - ctxt, false) =3D=3D X86EMUL_EXCEPTION ) > - x86_emul_reset_event(ctxt); > - goto done; > + /* > + * In real hardware, access to the registers cannot fail. I= t is > + * an error in Xen if the writes fail given that both MSRs h= ave > + * equivalent checks. > + */ > + ASSERT_UNREACHABLE(); > + x86_emul_reset_event(ctxt); > + generate_exception(X86_EXC_DF, 0); > } > break; > The rest looks good to me (with or without ops->{read,write}_segment fail_if() change). Reviewed-by: Teddy Astie Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 07 16:10:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 16:10:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275156.1561116 (Exim 4.92) (envelope-from ) id 1wA90U-00061s-IZ; Tue, 07 Apr 2026 16:10:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275156.1561116; Tue, 07 Apr 2026 16:10:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA90U-00061l-G4; Tue, 07 Apr 2026 16:10:26 +0000 Received: by outflank-mailman (input) for mailman id 1275156; Tue, 07 Apr 2026 16:10:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA90T-00061f-7b for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 16:10:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA90Q-002irY-KR for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 18:10:24 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d52c56-5cb7-0a2a0a5109dd-0a2a4504c234-40 for ; Tue, 07 Apr 2026 18:10:24 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d52c6f-bb33-0a2a45040019-d155dd32f1bf-3 for ; Tue, 07 Apr 2026 18:10:23 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43cfb723698so4595299f8f.3 for ; Tue, 07 Apr 2026 09:10:23 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1775578224-B253B51B-161D86F4/0/0 X-purgate-type: clean X-purgate-size: 2526 On 07.04.2026 18:00, Teddy Astie wrote: > Le 07/04/2026 à 16:27, Andrew Cooper a écrit : >> --- a/xen/arch/x86/x86_emulate/0f01.c >> +++ b/xen/arch/x86/x86_emulate/0f01.c >> @@ -189,22 +189,24 @@ int x86emul_0f01(struct x86_emulate_state *s, >> generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); >> fail_if(!ops->read_segment || !ops->read_msr || >> !ops->write_segment || !ops->write_msr); > > Do we still need checks for ops->{read,write}_segment if we're not using > them anymore ? > >> - if ( (rc = ops->read_segment(x86_seg_gs, &sreg, >> - ctxt)) != X86EMUL_OKAY || >> - (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, >> + if ( (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, >> ctxt)) != X86EMUL_OKAY || >> - (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, >> - ctxt, false)) != X86EMUL_OKAY ) >> + (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, >> + ctxt)) != X86EMUL_OKAY ) >> goto done; >> - sreg.base = msr_val; >> - if ( (rc = ops->write_segment(x86_seg_gs, &sreg, >> - ctxt)) != X86EMUL_OKAY ) >> + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, >> + ctxt, false)) != X86EMUL_OKAY || >> + (rc = ops->write_msr(MSR_GS_BASE, msr_val, >> + ctxt, false)) != X86EMUL_OKAY ) >> { >> - /* Best effort unwind (i.e. no real error checking). */ >> - if ( ops->write_msr(MSR_SHADOW_GS_BASE, msr_val, >> - ctxt, false) == X86EMUL_EXCEPTION ) >> - x86_emul_reset_event(ctxt); >> - goto done; >> + /* >> + * In real hardware, access to the registers cannot fail. It is >> + * an error in Xen if the writes fail given that both MSRs have >> + * equivalent checks. >> + */ >> + ASSERT_UNREACHABLE(); >> + x86_emul_reset_event(ctxt); >> + generate_exception(X86_EXC_DF, 0); >> } >> break; >> > > The rest looks good to me (with or without ops->{read,write}_segment > fail_if() change). As the patch was already committed, would you mind sending an incremental patch? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 07 16:25:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 16:25:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275166.1561126 (Exim 4.92) (envelope-from ) id 1wA9Eq-0007ky-RP; Tue, 07 Apr 2026 16:25:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275166.1561126; Tue, 07 Apr 2026 16:25:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA9Eq-0007kr-OT; Tue, 07 Apr 2026 16:25:16 +0000 Received: by outflank-mailman (input) for mailman id 1275166; Tue, 07 Apr 2026 16:25:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA9Ep-0007kj-5b for xen-devel@lists.xenproject.org; Tue, 07 Apr 2026 16:25:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wA9En-004zDx-Hc for xen-devel@lists.xenproject.org; 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The error paths are >> just an artefact of the hook functions needing to return something. >> >> The best effort unwind is also something that doesn't exist in real hardware, >> and makes the logic more complicated to follow. Instead, use an >> ASSERT_UNREACHABLE() with a fallback of injecting #DF. Hitting this path is >> an error in Xen. >> >> While adjusting, remove {read,write}_segment() and use {read,write}_msr() to >> access MSR_GS_BASE. There's no need to access the other parts of the GS >> segment, and this is less work behind the scenes. >> >> Signed-off-by: Andrew Cooper >> --- >> CC: Jan Beulich >> CC: Roger Pau Monné >> >> v2: >> * Retain x86_emul_reset_event() >> * Pass an error code for #DF >> * Drop goto done now that generate_exception() is used >> * Use 2x{read,write}_msr() >> >> Tested using LKGS's extention of the test emulator for SWAPGS. >> --- >> xen/arch/x86/x86_emulate/0f01.c | 28 +++++++++++++++------------- >> 1 file changed, 15 insertions(+), 13 deletions(-) >> >> diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0f01.c >> index 6c10979dd650..54bd6faf0f2c 100644 >> --- a/xen/arch/x86/x86_emulate/0f01.c >> +++ b/xen/arch/x86/x86_emulate/0f01.c >> @@ -189,22 +189,24 @@ int x86emul_0f01(struct x86_emulate_state *s, >> generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); >> fail_if(!ops->read_segment || !ops->read_msr || >> !ops->write_segment || !ops->write_msr); > Do we still need checks for ops->{read,write}_segment if we're not using > them anymore ? Oh, yes they can be dropped now. Please send a new patch.  I've already committed this to unblock some of Jan's work. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 07 17:13:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 17:13:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275244.1561155 (Exim 4.92) (envelope-from ) id 1wA9zI-0006sn-1z; Tue, 07 Apr 2026 17:13:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275244.1561155; Tue, 07 Apr 2026 17:13:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA9zH-0006sg-VP; Tue, 07 Apr 2026 17:13:15 +0000 Received: by outflank-mailman (input) for mailman id 1275244; Tue, 07 Apr 2026 17:13:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wA9zG-0006sa-Rz for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Xmja7yza/4PH/AGb" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-720697/1775581994-46D20CD1-497B3F5A/0/0 X-purgate-type: clean X-purgate-size: 1473 --Xmja7yza/4PH/AGb Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Tue, 7 Apr 2026 19:13:10 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Cody Zuschlag Cc: xen-devel@lists.xenproject.org Subject: Re: [ANNOUNCE] Call for agenda items for April 9 Xen Community Call @ 15:00 UTC On Mon, Apr 06, 2026 at 11:06:32AM +0200, Cody Zuschlag wrote: > *Preparation: *Please take a moment to review and update the agenda ahead > of the call: > =F0=9F=91=89 Agenda > Agenda on google docs this time? --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --Xmja7yza/4PH/AGb Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnVOyYACgkQ24/THMrX 1yxszQf+IYbTprONyaBHM0xdCs+8EeP7YSSPWHnX0e805PzqPs5uxnOkdxQG3FOo EDM0qCg/natm1dUTftum6aWsIsWSnhwNF6wzV5+xPIrawc9UruCjQJ1DUxMD1xrm 9gbh0F204lT+ORf4SgZE7XwZId3QeSbMWMBKstsRcxJauhQEnpCeCEoKp2vIlCqg XZTCeTAsI5wxAdY1NdS5kDpAX1uR+aQ+2Z4EFiv/UJMPgm2Vxgd5xewsQKteHnxv ynKEDnML6J7D3KfsGRADUbueJ5a9WRmfzZPSOkfcPm+ekjUVF9mbyG/JLyhf6Jv6 g1pQpIRTlDePDpxCmTHalc9OcNgd7g== =eZDJ -----END PGP SIGNATURE----- --Xmja7yza/4PH/AGb-- From xen-devel-bounces@lists.xenproject.org Tue Apr 07 20:02:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 20:02:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275321.1561180 (Exim 4.92) (envelope-from ) id 1wACci-0003Bx-HX; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43056d0c-dab5-4045-1752-08de94e08a01 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2026 20:02:04.1871 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: F4b7e/Ec4HV9OXQ95rDBx35uTFWRZoiV3/sIRKWq6DQGHogHhYOmQNpDjSHNYihX9phG3aeaM3f6Qf2OWU/WPE9UCuOo359alTQcnX1cLjg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7510 X-purgate-ID: tlsNG-4011c0/1775592126-0EB4D0B1-35D6F21F/0/0 X-purgate-type: clean X-purgate-size: 5667 Hi Saman, Saman Dehghan writes: > This patch enables building Xen for the arm64 using the Clang/LLVM compil= er. > Changes include: > - Add explicit -march=3Darmv8 flag for arm64 builds. > - Introduce `READ_FP_SYSREG` and `WRITE_FP_SYSREG` to encapsulate the req= uired > `.arch_extension fp` directive for system fp register access. > - Add ".arch_extension fp" to the inline assembly for `save_state` and > `restore_state`. > It breaks GCC-based build (see below) Also, are you going to address to other issues that I tried to tackle in https://patchew.org/Xen/20241129014850.2852844-1-volodymyr._5Fbabchuk@epam.= com/ ? > Signed-off-by: Saman Dehghan > --- > README | 2 ++ > xen/arch/arm/arch.mk | 1 + > xen/arch/arm/arm64/vfp.c | 34 ++++++++++++++++++++++++++-------- > 3 files changed, 29 insertions(+), 8 deletions(-) > > diff --git a/README b/README > index 889a4ea906..67c1aa7fe6 100644 > --- a/README > +++ b/README > @@ -45,6 +45,8 @@ provided by your OS distributor: > - For ARM: > - GCC 5.1 or later > - GNU Binutils 2.25 or later > + or > + - Clang/LLVM 11 or later > - For RISC-V 64-bit: > - GCC 12.2 or later > - GNU Binutils 2.39 or later > diff --git a/xen/arch/arm/arch.mk b/xen/arch/arm/arch.mk > index 9c4bedfb3b..bcf548069b 100644 > --- a/xen/arch/arm/arch.mk > +++ b/xen/arch/arm/arch.mk > @@ -13,6 +13,7 @@ ifeq ($(CONFIG_MPU),y) > CFLAGS-$(CONFIG_ARM_64) +=3D -march=3Darmv8-r > else > CFLAGS-$(CONFIG_ARM_64) +=3D -mcpu=3Dgeneric > +CFLAGS-$(CONFIG_ARM_64) +=3D -march=3Darmv8 This breaks build for me: cc1: error: unknown value 'armv8' for '-march' cc1: note: valid arguments are: armv8-a armv8.1-a armv8.2-a armv8.3-a armv8= .4-a armv8.5-a armv8.6-a armv8.7-a armv8.8-a armv8.9-a armv8-r armv9-a armv= 9.1-a armv9.2-a armv9.3-a armv9.4-a armv9.5-a; did you mean 'armv8-a'? > endif > CFLAGS-$(CONFIG_ARM_64) +=3D -mgeneral-regs-only # No fp registers etc > $(call cc-option-add,CFLAGS-$(CONFIG_ARM_64),CC,-mno-outline-atomics) > diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c > index c4f89c7b0e..cd5c97cfd0 100644 > --- a/xen/arch/arm/arm64/vfp.c > +++ b/xen/arch/arm/arm64/vfp.c > @@ -6,7 +6,8 @@ > =20 > static inline void save_state(uint64_t *fpregs) > { > - asm volatile("stp q0, q1, [%1, #16 * 0]\n\t" > + asm volatile(".arch_extension fp\n\t" > + "stp q0, q1, [%1, #16 * 0]\n\t" > "stp q2, q3, [%1, #16 * 2]\n\t" > "stp q4, q5, [%1, #16 * 4]\n\t" > "stp q6, q7, [%1, #16 * 6]\n\t" > @@ -22,12 +23,14 @@ static inline void save_state(uint64_t *fpregs) > "stp q26, q27, [%1, #16 * 26]\n\t" > "stp q28, q29, [%1, #16 * 28]\n\t" > "stp q30, q31, [%1, #16 * 30]\n\t" > + ".arch_extension nofp\n\t" > : "=3DQ" (*fpregs) : "r" (fpregs)); > } > =20 > static inline void restore_state(const uint64_t *fpregs) > { > - asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t" > + asm volatile(".arch_extension fp\n\t" > + "ldp q0, q1, [%1, #16 * 0]\n\t" > "ldp q2, q3, [%1, #16 * 2]\n\t" > "ldp q4, q5, [%1, #16 * 4]\n\t" > "ldp q6, q7, [%1, #16 * 6]\n\t" > @@ -43,9 +46,24 @@ static inline void restore_state(const uint64_t *fpreg= s) > "ldp q26, q27, [%1, #16 * 26]\n\t" > "ldp q28, q29, [%1, #16 * 28]\n\t" > "ldp q30, q31, [%1, #16 * 30]\n\t" > + ".arch_extension nofp\n\t" > : : "Q" (*fpregs), "r" (fpregs)); > } > =20 > +#define WRITE_FP_SYSREG(v, name) do { \ > + uint64_t _r =3D (v); \ > + asm volatile(".arch_extension fp\n\t" \ > + "msr "__stringify(name)", %0\n\t" \ > + ".arch_extension nofp" : : "r" (_r)); \ > +} while (0) > + > +#define READ_FP_SYSREG(name) ({ \ > + uint64_t _r; \ > + asm volatile(".arch_extension fp\n\t" \ > + "mrs %0, "__stringify(name)"\n\t" \ > + ".arch_extension nofp" : "=3Dr" (_r)); \ > +_r; }) > + > void vfp_save_state(struct vcpu *v) > { > if ( !cpu_has_fp ) > @@ -56,10 +74,10 @@ void vfp_save_state(struct vcpu *v) > else > save_state(v->arch.vfp.fpregs); > =20 > - v->arch.vfp.fpsr =3D READ_SYSREG(FPSR); > - v->arch.vfp.fpcr =3D READ_SYSREG(FPCR); > + v->arch.vfp.fpsr =3D READ_FP_SYSREG(FPSR); > + v->arch.vfp.fpcr =3D READ_FP_SYSREG(FPCR); > if ( is_32bit_domain(v->domain) ) > - v->arch.vfp.fpexc32_el2 =3D READ_SYSREG(FPEXC32_EL2); > + v->arch.vfp.fpexc32_el2 =3D READ_FP_SYSREG(FPEXC32_EL2); > } > =20 > void vfp_restore_state(struct vcpu *v) > @@ -72,8 +90,8 @@ void vfp_restore_state(struct vcpu *v) > else > restore_state(v->arch.vfp.fpregs); > =20 > - WRITE_SYSREG(v->arch.vfp.fpsr, FPSR); > - WRITE_SYSREG(v->arch.vfp.fpcr, FPCR); > + WRITE_FP_SYSREG(v->arch.vfp.fpsr, FPSR); > + WRITE_FP_SYSREG(v->arch.vfp.fpcr, FPCR); > if ( is_32bit_domain(v->domain) ) > - WRITE_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); > + WRITE_FP_SYSREG(v->arch.vfp.fpexc32_el2, FPEXC32_EL2); > } --=20 WBR, Volodymyr= From xen-devel-bounces@lists.xenproject.org Tue Apr 07 20:30:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 20:30:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275333.1561188 (Exim 4.92) (envelope-from ) id 1wAD4U-0007EM-KP; Tue, 07 Apr 2026 20:30:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275333.1561188; Tue, 07 Apr 2026 20:30:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAD4U-0007EF-HL; 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charset=US-ASCII X-purgate-ID: tlsNG-4011c0/1775593847-BC3610B1-D6A22261/0/0 X-purgate-type: clean X-purgate-size: 2259 On Tue, 7 Apr 2026, Michal Orzel wrote: > Rename 'pdev' to 'pci_dev' in the dev_print_pci() macro to avoid > shadowing local 'pdev' variables at call sites. > > Remove the unused 'ret' declaration from arm_smmu_dt_add_device_generic() > where the function-scope 'ret' is sufficient. > > Fix shadowing of 'domain' in arm_smmu_assign_dev() by removing the > inner-scope redeclaration, using the function-scope variable instead. > > This fixes MISRA C R5.3. > > Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini > --- > xen/drivers/passthrough/arm/smmu.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c > index 22d306d0cb80..d63c9015510e 100644 > --- a/xen/drivers/passthrough/arm/smmu.c > +++ b/xen/drivers/passthrough/arm/smmu.c > @@ -130,8 +130,8 @@ typedef enum irqreturn irqreturn_t; > printk(lvl "smmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ > else \ > { \ > - struct pci_dev *pdev = dev_to_pci((dev)); \ > - printk(lvl "smmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ > + struct pci_dev *pci_dev = dev_to_pci((dev)); \ > + printk(lvl "smmu: %pp: " fmt, &pci_dev->sbdf, ## __VA_ARGS__); \ > } \ > }) > #endif > @@ -927,7 +927,6 @@ static int arm_smmu_dt_add_device_generic(u8 devfn, struct device *dev) > if ( dev_is_pci(dev) ) > { > struct pci_dev *pdev = dev_to_pci(dev); > - int ret; > > /* Ignore calls for phantom functions */ > if ( devfn != pdev->devfn ) > @@ -2788,7 +2787,7 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, > /* dom_io is used as a sentinel for quarantined devices */ > if ( d == dom_io ) > { > - struct iommu_domain *domain = dev_iommu_domain(dev); > + domain = dev_iommu_domain(dev); > if ( !iommu_quarantine ) > return 0; > > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Tue Apr 07 20:32:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 20:32:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275340.1561197 (Exim 4.92) (envelope-from ) id 1wAD5i-0007mx-Su; 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s=k20201202; t=1775593922; bh=5JPbz7ZvJhy4OvxwPpdeqCLBT41FR4vzxedbyx+6XyU=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=bn1ZOO27Oom4tJRCmprrVSJY0kjA7o6sP76x8hUyPzS1bD9QozqPwivl+lLikx+rs wRSZfwqB4oUsA7y9FW/1NdjnKBfpqgJr18BqFXAVmGkF1nSd4RwqRUc9AZDmCF/yDc lPOFJSSTPwObofNpGCT6PVY4XuSoXv6eE387KyVVWm/uxEnSsCIdwLEKjcGMNKLaF8 VC4ECbZ3BFZXNhmrAD+UxIAmXmFjxDHAE7HWNWSb6o9AG/+Nm64VT8PhCmxu2iwP1J BYXvhPcHfAMkvC1dFlWD/uGNTujpuG+ySzeSH+8iT9nZf5VW/XADn7xicik+Xwl3+K 4QPTQL0dnlLZw== Date: Tue, 7 Apr 2026 13:32:00 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Michal Orzel cc: xen-devel@lists.xenproject.org, Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 2/2] iommu/arm: ipmmu-vmsa: Fix variable shadowing In-Reply-To: <20260407103434.90838-3-michal.orzel@amd.com> Message-ID: References: <20260407103434.90838-1-michal.orzel@amd.com> <20260407103434.90838-3-michal.orzel@amd.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-d25034/1775593924-8055FA3D-8A72AB62/0/0 X-purgate-type: clean X-purgate-size: 1864 On Tue, 7 Apr 2026, Michal Orzel wrote: > Rename 'pdev' to 'pci_dev' in the dev_print_pci() macro to avoid > shadowing local 'pdev' variables at call sites. > > Remove the unused 'ret' declaration from ipmmu_assign_device() where > the function-scope 'ret' is sufficient. > > This fixes MISRA C R5.3. > > Signed-off-by: Michal Orzel Reviewed-by: Stefano Stabellini > --- > xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > index ea9fa9ddf3ce..fa9ab9cb1330 100644 > --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c > +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > @@ -65,8 +65,8 @@ > printk(lvl "ipmmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__); \ > else \ > { \ > - struct pci_dev *pdev = dev_to_pci((dev)); \ > - printk(lvl "ipmmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__); \ > + struct pci_dev *pci_dev = dev_to_pci((dev)); \ > + printk(lvl "ipmmu: %pp: " fmt, &pci_dev->sbdf, ## __VA_ARGS__); \ > } \ > }) > #endif > @@ -1171,8 +1171,6 @@ static int ipmmu_assign_device(struct domain *d, u8 devfn, struct device *dev, > /* dom_io is used as a sentinel for quarantined devices */ > if ( d == dom_io ) > { > - int ret; > - > /* > * Try to de-assign: do not return error if it was already > * de-assigned. > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Tue Apr 07 21:59:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 07 Apr 2026 21:59:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275361.1561207 (Exim 4.92) (envelope-from ) id 1wAERd-0001GN-0T; Tue, 07 Apr 2026 21:58:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275361.1561207; Tue, 07 Apr 2026 21:58:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAERc-0001GG-U1; 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> } > + else > + { > + /* > + * Xen doesn't use PKS, so the guest support for it has opted to not use > + * the VMCS load/save controls for efficiency reasons. This depends on > + * the exact vmentry/exit behaviour, so don't expose PKS in other > + * situations until someone has cross-checked the behaviour for safety. > + */ > + __clear_bit(X86_FEATURE_PKS, fs); > + } > > if ( !cpu_has_vmx_msrlist ) > __clear_bit(X86_FEATURE_MSRLIST, fs); > > - /* > - * Xen doesn't use PKS, so the guest support for it has opted to not use > - * the VMCS load/save controls for efficiency reasons. This depends on > - * the exact vmentry/exit behaviour, so don't expose PKS in other > - * situations until someone has cross-checked the behaviour for safety. > - */ > - if ( !cpu_has_vmx ) > - __clear_bit(X86_FEATURE_PKS, fs); > - > /* > * Make adjustments to possible (nested) virtualization features exposed > * to the guest > These clauses aren't logically doing the same thing.  So while the compiler can merge them, I don't think it's a good idea to do so at a source level. The "if ( vmx ) " block we can just see the end of is for features which need to cross-check extra VMX capabilities.  Each of RDTSCP, INVPCID and XSAVES are #UD unless explicitly enabled.  MPX is the odd-one out, checking the load/save capabilities. I suspect this list is incomplete.  These cross-checks shouldn't fail on real hardware, where the VMX capabilities should match the native features, but nested virt is rife with enumeration bugs here. The second "if ( !vmx )" clause is different.  This is really "I wired up PKS based on how Intel works, and if AMD ever gains it it will definitely need context switching changes to work".  This is in lieu of having dedicated Intel/AMD annotations for features. The MSRLIST addition from the prior patch is arguably misplaced, except it's trying to cover both of the aspects. AMD are making no obvious moves to add PKS, and I expect MSRLIST is even lower down their priority list. Overall, we need checks here for every guest-visible feature which: * has VMCS/VMCB controls which are enumerated separately * needs new context switching considerations Maybe the "if ( !vmx )" shouldn't really be written this way.  I'm open to suggestions, but making it an else block isn't a solution. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 02:47:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 02:47:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275377.1561216 (Exim 4.92) (envelope-from ) id 1wAIx8-0002QZ-Le; Wed, 08 Apr 2026 02:47:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275377.1561216; Wed, 08 Apr 2026 02:47:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAIx8-0002QR-Gm; Wed, 08 Apr 2026 02:47:38 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epghhithhhuhgsrdgtohhmpdhkvghrnhgvlhdrohhrghenucevlhhushhtvghrufhiiigv pedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehmrghrmhgrrhgvkhesihhnvhhishhisg hlvghthhhinhhgshhlrggsrdgtohhmpdhnsggprhgtphhtthhopeehpdhmohguvgepshhm thhpohhuthdprhgtphhtthhopehkvghvihhnrdgsrhhoughskhihsegrrhhmrdgtohhmpd hrtghpthhtohepjhhgrhhoshhssehsuhhsvgdrtghomhdprhgtphhtthhopegrnhgurhgv fidrtghoohhpvghrfeestghithhrihigrdgtohhmpdhrtghpthhtohepgigvnhdquggvvh gvlheslhhishhtshdrgigvnhhprhhojhgvtghtrdhorhhgpdhrtghpthhtohepsghorhhi shdrohhsthhrohhvshhkhiesohhrrggtlhgvrdgtohhm X-ME-Proxy: Feedback-ID: i1568416f:Fastmail Date: Wed, 8 Apr 2026 04:47:29 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Kevin Brodsky Cc: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Andrew Cooper , xen-devel , Boris Ostrovsky Subject: Re: kernel BUG around vmap/vfree - xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 Message-ID: References: <5d068304-837d-4aef-b8a7-87c91ccf96b4@arm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="MOg8fIXj0kDdUuxl" Content-Disposition: inline In-Reply-To: <5d068304-837d-4aef-b8a7-87c91ccf96b4@arm.com> X-purgate-ID: tlsNG-720697/1775616454-45132CD1-6BF24663/0/0 X-purgate-type: clean X-purgate-size: 16199 --MOg8fIXj0kDdUuxl Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 8 Apr 2026 04:47:29 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Kevin Brodsky Cc: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Andrew Cooper , xen-devel , Boris Ostrovsky Subject: Re: kernel BUG around vmap/vfree - xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 On Tue, Apr 07, 2026 at 11:23:17AM +0200, Kevin Brodsky wrote: > On 05/04/2026 11:41, Marek Marczykowski-G=C3=B3recki wrote: > > On Thu, Feb 26, 2026 at 02:41:12PM +0100, J=C3=BCrgen Gro=C3=9F wrote: > >> On 26.02.26 14:27, Andrew Cooper wrote: > >>> On 26/02/2026 1:17 pm, Marek Marczykowski-G=C3=B3recki wrote: > >>>> Hi, > >>>> > >>>> When testing Linux 7.0-rc1 in PV dom0, I hit the following panic > >>>> sometimes: > >>>> > >>>> [ 436.849614] ------------[ cut here ]------------ > >>>> [ 436.849669] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:7= 8! > >>>> [ 436.849693] Oops: invalid opcode: 0000 [#1] SMP NOPTI > >>>> [ 436.849710] CPU: 3 UID: 0 PID: 4021 Comm: kworker/u25:1 Not taint= ed 7.0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) > >>>> [ 436.849729] Hardware name: Star Labs StarBook/StarBook, BIOS 8.97= 10/03/2023 > >>>> [ 436.849743] Workqueue: i915_flip intel_atomic_commit_work [i915] > >>>> [ 436.850226] RIP: e030:xen_enter_lazy_mmu+0x24/0x30 > >>>> [ 436.850245] Code: 90 90 90 90 90 90 f3 0f 1e fa 0f 1f 44 00 00 65= 8b 05 b8 e5 02 03 85 c0 75 10 65 c7 05 a9 e5 02 03 01 00 00 00 c3 cc cc cc= cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90 > >>>> [ 436.850270] RSP: e02b:ffffc90045727a68 EFLAGS: 00010202 > >>>> [ 436.850283] RAX: 0000000000000001 RBX: ffff8881042fa6d0 RCX: 000f= ffffffe00000 > >>>> [ 436.850296] RDX: 0000000000000001 RSI: ffff88810a5a2980 RDI: 0000= 000000000000 > >>>> [ 436.850308] RBP: ffffc90049eda000 R08: ffffc90049edc000 R09: ffff= c90049edc000 > >>>> [ 436.850320] R10: ffffc90049edc000 R11: ffffc90049edbfff R12: ffff= c90049edc000 > >>>> [ 436.850332] R13: ffffc90045727bb0 R14: ffffc90045727b28 R15: 8000= 00000000006b > >>>> [ 436.850356] FS: 0000000000000000(0000) GS:ffff888201e6e000(0000)= knlGS:0000000000000000 > >>>> [ 436.850371] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 > >>>> [ 436.850383] CR2: 00006543dbade250 CR3: 0000000115ef1000 CR4: 0000= 000000050660 > >>>> [ 436.850401] Call Trace: > >>>> [ 436.850410] > >>>> [ 436.850420] vmap_pages_pud_range+0x47c/0x530 > >>>> [ 436.850439] vmap_small_pages_range_noflush+0x1f1/0x2b0 > >>>> [ 436.850451] ? __get_vm_area_node+0x10a/0x170 > >>>> [ 436.850465] vmap+0x79/0xd0 > >>>> [ 436.850476] i915_gem_object_map_page+0x13b/0x210 [i915] > >>>> [ 436.850812] i915_gem_object_pin_map+0x1e2/0x210 [i915] > >>>> [ 436.851123] i915_gem_object_pin_map_unlocked+0x2d/0xa0 [i915] > >>>> [ 436.851424] intel_dsb_buffer_create+0xed/0x1a0 [i915] > >>>> [ 436.851778] intel_dsb_prepare+0xca/0x1a0 [i915] > >>>> [ 436.852110] intel_atomic_dsb_finish+0x92/0x350 [i915] > >>>> [ 436.852456] intel_atomic_commit_tail+0x326/0xd40 [i915] > >>>> [ 436.852769] process_one_work+0x18d/0x380 > >>>> [ 436.852779] worker_thread+0x196/0x300 > >>>> [ 436.852787] ? __pfx_worker_thread+0x10/0x10 > >>>> [ 436.852796] kthread+0xe3/0x120 > >>>> [ 436.852805] ? __pfx_kthread+0x10/0x10 > >>>> [ 436.852815] ret_from_fork+0x19e/0x260 > >>>> [ 436.852824] ? __pfx_kthread+0x10/0x10 > >>>> [ 436.852832] ret_from_fork_asm+0x1a/0x30 > >>>> [ 436.852842] > >>>> [ 436.852847] Modules linked in: snd_seq_dummy snd_hrtimer snd_hda_= codec_intelhdmi snd_hda_codec_hdmi snd_hda_codec_alc269 snd_hda_codec_realt= ek_lib snd_hda_scodec_component snd_hda_codec_generic snd_hda_intel snd_sof= _pci_intel_tgl snd_sof_pci_intel_cnl snd_sof_intel_hda_generic soundwire_in= tel snd_sof_intel_hda_sdw_bpt snd_sof_intel_hda_common snd_soc_hdac_hda snd= _sof_intel_hda_mlink snd_sof_intel_hda soundwire_cadence snd_sof_pci snd_so= f_xtensa_dsp snd_sof snd_sof_utils snd_soc_acpi_intel_match snd_soc_acpi_in= tel_sdca_quirks soundwire_generic_allocation snd_soc_sdw_utils snd_soc_acpi= crc8 intel_rapl_msr soundwire_bus intel_rapl_common snd_soc_sdca snd_soc_a= vs snd_soc_hda_codec snd_hda_ext_core snd_hda_codec vfat intel_uncore_frequ= ency_common fat snd_hda_core snd_intel_dspcfg snd_intel_sdw_acpi snd_hwdep = intel_powerclamp snd_soc_core iwlwifi snd_compress spi_nor iTCO_wdt ac97_bu= s intel_pmc_bxt ee1004 mtd snd_pcm_dmaengine snd_seq cfg80211 snd_seq_devic= e pcspkr spi_intel_pci snd_pcm rfkill spi_intel snd_timer snd > >>>> [ 436.852939] i2c_i801 soundcore i2c_smbus idma64 intel_pmc_core p= mt_telemetry pmt_discovery pmt_class intel_hid intel_pmc_ssram_telemetry in= tel_scu_pltdrv sparse_keymap joydev loop fuse xenfs nfnetlink vsock_loopbac= k vmw_vsock_virtio_transport_common vmw_vsock_vmci_transport vsock zram vmw= _vmci lz4hc_compress lz4_compress dm_thin_pool dm_persistent_data dm_bio_pr= ison dm_crypt xe drm_ttm_helper drm_suballoc_helper gpu_sched drm_gpuvm drm= _exec drm_gpusvm_helper i915 i2c_algo_bit drm_buddy hid_multitouch i2c_hid_= acpi ghash_clmulni_intel video nvme wmi ttm i2c_hid nvme_core nvme_keyring = drm_display_helper nvme_auth xhci_pci pinctrl_tigerlake thunderbolt hkdf ce= c xhci_hcd intel_vsec serio_raw xen_acpi_processor xen_privcmd xen_pciback = xen_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_dh_rdac scsi_dh_emc scs= i_dh_alua uinput i2c_dev > >>>> [ 436.853183] ---[ end trace 0000000000000000 ]--- > >>>> > >>>> or this: > >>>> > >>>> [ 548.736884] ------------[ cut here ]------------ > >>>> [ 548.736907] kernel BUG at arch/x86/include/asm/xen/hypervisor.h:8= 5! > >>>> [ 548.736923] Oops: invalid opcode: 0000 [#1] SMP NOPTI > >>>> [ 548.736935] CPU: 0 UID: 0 PID: 206 Comm: kworker/0:2 Not tainted = 7.0.0-0.rc1.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) > >>>> [ 548.736949] Hardware name: LENOVO 2347A45/2347A45, BIOS CBET4000 = Nitrokey-v0.2.0-2608-ga649597 01/01/1970 > >>>> [ 548.736962] Workqueue: events delayed_vfree_work > >>>> [ 548.736976] RIP: e030:xen_leave_lazy_mmu+0x44/0x50 > >>>> [ 548.736989] Code: 02 03 83 f8 01 75 23 65 c7 05 6c e4 02 03 00 00= 00 00 65 ff 0d 7d b8 02 03 74 05 c3 cc cc cc cc e8 61 5d fd ff c3 cc cc cc= cc <0f> 0b 66 2e 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90 > >>>> [ 548.737010] RSP: e02b:ffffc90040607cf0 EFLAGS: 00010297 > >>>> [ 548.737018] RAX: 0000000000000000 RBX: ffff888164a70408 RCX: 0000= 000000000000 > >>>> [ 548.737029] RDX: 0000000000000000 RSI: 000ffffffffff000 RDI: ffff= 8881069c0000 > >>>> [ 548.737039] RBP: ffffc90049681000 R08: ffffc90049681000 R09: 0000= 000000000027 > >>>> [ 548.737050] R10: 0000000000000027 R11: fefefefefefefeff R12: ffff= c90049681000 > >>>> [ 548.737060] R13: ffff8881002fd258 R14: 0000000000000000 R15: ffff= c90040607dac > >>>> [ 548.737079] FS: 0000000000000000(0000) GS:ffff8881f88ee000(0000)= knlGS:0000000000000000 > >>>> [ 548.737090] CS: e030 DS: 0000 ES: 0000 CR0: 0000000080050033 > >>>> [ 548.737099] CR2: 000055576c2e6058 CR3: 000000010d47b000 CR4: 0000= 000000050660 > >>>> [ 548.737115] Call Trace: > >>>> [ 548.737123] > >>>> [ 548.737128] vunmap_pmd_range.isra.0+0x1f1/0x2e0 > >>>> [ 548.737142] vunmap_p4d_range+0x17d/0x290 > >>>> [ 548.737151] __vunmap_range_noflush+0x182/0x1d0 > >>>> [ 548.737161] ? _raw_spin_unlock+0xe/0x30 > >>>> [ 548.737171] remove_vm_area+0x40/0x70 > >>>> [ 548.737180] vfree.part.0+0x1b/0x290 > >>>> [ 548.737189] delayed_vfree_work+0x35/0x50 > >>>> [ 548.737198] process_one_work+0x18d/0x380 > >>>> [ 548.737207] worker_thread+0x196/0x300 > >>>> [ 548.737215] ? __pfx_worker_thread+0x10/0x10 > >>>> [ 548.737224] kthread+0xe3/0x120 > >>>> [ 548.737233] ? __pfx_kthread+0x10/0x10 > >>>> [ 548.737242] ret_from_fork+0x19e/0x260 > >>>> [ 548.737250] ? __pfx_kthread+0x10/0x10 > >>>> [ 548.737258] ret_from_fork_asm+0x1a/0x30 > >>>> [ 548.737269] > >>>> [ 548.737274] Modules linked in: vfat fat snd_seq_dummy snd_hrtimer= ath9k ath9k_common snd_hda_codec_intelhdmi snd_hda_codec_hdmi ath9k_hw snd= _hda_codec_alc269 snd_hda_codec_realtek_lib snd_hda_scodec_component snd_hd= a_codec_generic snd_hda_intel snd_hda_codec mac80211 snd_hda_core snd_intel= _dspcfg snd_intel_sdw_acpi snd_hwdep ath snd_seq snd_seq_device snd_ctl_led= cfg80211 snd_pcm at24 thinkpad_acpi intel_rapl_msr i2c_i801 snd_timer spar= se_keymap iTCO_wdt intel_rapl_common platform_profile intel_powerclamp inte= l_pmc_bxt pcspkr i2c_smbus rfkill libarc4 snd soundcore mei_me e1000e mei j= oydev lpc_ich loop fuse xenfs nfnetlink vsock_loopback vmw_vsock_virtio_tra= nsport_common vmw_vsock_vmci_transport vsock zram vmw_vmci lz4hc_compress l= z4_compress dm_thin_pool dm_persistent_data dm_bio_prison dm_crypt i915 i2c= _algo_bit drm_buddy ghash_clmulni_intel ttm sdhci_pci drm_display_helper sd= hci_uhs2 sdhci video xhci_pci cqhci wmi cec xhci_hcd ehci_pci mmc_core ehci= _hcd serio_raw xen_acpi_processor xen_privcmd xen_pciback > >>>> [ 548.737348] xen_blkback xen_gntalloc xen_gntdev xen_evtchn scsi_= dh_rdac scsi_dh_emc scsi_dh_alua uinput i2c_dev > >>>> [ 548.737469] ---[ end trace 0000000000000000 ]--- > >>>> > >>>> I don't have clear pattern when this happens, one was during host > >>>> suspend, but the other was during "normal" test run (starting/stoppi= ng > >>>> domUs and running stuff around them). Note also one of those is Intel > >>>> and the other AMD, so it isn't really hardware specific. > >>>> > >>>> Slightly more details with links (especially serial0.txt in the logs > >>>> tab) at > >>>> https://github.com/QubesOS/qubes-linux-kernel/pull/662#issuecomment-= 3963326188 > >>>> > >>>> Any idea? > >>>> > >>> That looks like the issue Juergen fixed with: > >>> > >>> https://lore.kernel.org/xen-devel/20260220123715.834848-1-jgross@suse= =2Ecom/ > >> No, it doesn't. The fix is already in rc1, and the crash was quite ear= ly during > >> boot (before any secondary CPUs were brought up). > >> > >> I guess this problem is related to the lazy_mmu_state series [1]. >=20 > That may well be the case - it seems that xen_enter_lazy_mmu() is called > while already in lazy MMU mode (first splat), and xen_leave_lazy_mmu() > is called without being in lazy MMU mode (second splat). I expect this > is something specific to Xen, which I didn't get the chance to test. >=20 > Looking at the series again I don't see anything obviously wrong, but I > think the riskiest change is commit 291b3abed657 ("x86/xen: use > lazy_mmu_state when context-switching") - worth trying to revert it. With that reverted (on top of 7.0-rc6, didn't updated to rc7 yet), I still got panic, although might be a bit different one: [ 8.099973] BUG: unable to handle page fault for address: ffff8880080006= 70 [ 8.100004] #PF: supervisor write access in kernel mode [ 8.100021] #PF: error_code(0x0003) - permissions violation [ 8.100037] PGD 3a00067 P4D 3a00067 PUD 3a01067 PMD 7cd7063 PTE 80000000= 08000021 [ 8.100063] Oops: Oops: 0003 [#1] SMP PTI [ 8.100079] CPU: 0 UID: 0 PID: 226 Comm: kworker/0:2 Not tainted 7.0.0-0= =2Erc6.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full)=20 [ 8.100110] Workqueue: events do_free_init [ 8.100126] RIP: 0010:native_set_pte+0x4/0x10 [ 8.100145] Code: 00 03 c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 00 = 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 f3 0f 1e fa <48= > 89 37 c3 cc cc cc cc 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 [ 8.100195] RSP: 0018:ffffc90000c97c48 EFLAGS: 00010287 [ 8.100212] RAX: e00c4f3d8b48c03e RBX: ffff888008000670 RCX: e0000000000= 0003e [ 8.100234] RDX: e00c4f3d8b48c13e RSI: e00c4f3d8b48c03e RDI: ffff8880080= 00670 [ 8.100260] RBP: e00c4f3d8b48c13e R08: 0000000000000000 R09: 00000000000= 00001 [ 8.100282] R10: 0000003b0c274b73 R11: e00000000000013e R12: ffffc90000c= 97cf0 [ 8.100304] R13: ffffffffc04ce000 R14: fffc4f3d8b48cfff R15: e0000000000= 0013e [ 8.100327] FS: 0000000000000000(0000) GS:ffff888094e81000(0000) knlGS:= 0000000000000000 [ 8.100350] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 8.100369] CR2: ffff888008000670 CR3: 000000000242e003 CR4: 00000000001= 706f0 [ 8.100394] Call Trace: [ 8.100404] [ 8.100413] __change_page_attr+0x24f/0x350 [ 8.100429] __change_page_attr_set_clr+0x61/0xd0 [ 8.100446] change_page_attr_set_clr+0x103/0x1a0 [ 8.100467] set_memory_nx+0x39/0x50 [ 8.100481] __execmem_cache_free+0x35/0xb0 [ 8.100496] execmem_free+0x9f/0x180 [ 8.100510] ? nft_chain_nat_exit+0xe70/0xe70 [nft_chain_nat] [ 8.100531] do_free_init+0x2e/0x60 [ 8.100545] process_one_work+0x198/0x390 [ 8.100559] worker_thread+0x1af/0x320 [ 8.100573] ? __pfx_worker_thread+0x10/0x10 [ 8.103338] kthread+0xe3/0x120 [ 8.103355] ? __pfx_kthread+0x10/0x10 [ 8.103369] ret_from_fork+0x19e/0x260 [ 8.103384] ? __pfx_kthread+0x10/0x10 [ 8.103397] ret_from_fork_asm+0x1a/0x30 [ 8.103412] [ 8.103421] Modules linked in: xenfs nft_reject_inet nf_reject_ipv4 nf_r= eject_ipv6 nft_reject nft_redir nft_ct nft_chain_nat nf_nat nf_conntrack nf= _defrag_ipv6 nf_defrag_ipv4 nf_tables binfmt_misc intel_rapl_msr intel_rapl= _common ghash_clmulni_intel xen_netfront xen_privcmd xen_gntdev xen_gntallo= c xen_blkback xen_evtchn fuse loop nfnetlink ip_tables overlay xen_blkfront [ 8.103529] CR2: ffff888008000670 [ 8.103542] ---[ end trace 0000000000000000 ]--- [ 8.103558] RIP: 0010:native_set_pte+0x4/0x10 [ 8.103576] Code: 00 03 c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 00 = 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 f3 0f 1e fa <48= > 89 37 c3 cc cc cc cc 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 [ 8.103625] RSP: 0018:ffffc90000c97c48 EFLAGS: 00010287 [ 8.103641] RAX: e00c4f3d8b48c03e RBX: ffff888008000670 RCX: e0000000000= 0003e [ 8.103664] RDX: e00c4f3d8b48c13e RSI: e00c4f3d8b48c03e RDI: ffff8880080= 00670 [ 8.103686] RBP: e00c4f3d8b48c13e R08: 0000000000000000 R09: 00000000000= 00001 [ 8.103708] R10: 0000003b0c274b73 R11: e00000000000013e R12: ffffc90000c= 97cf0 [ 8.103730] R13: ffffffffc04ce000 R14: fffc4f3d8b48cfff R15: e0000000000= 0013e [ 8.103753] FS: 0000000000000000(0000) GS:ffff888094e81000(0000) knlGS:= 0000000000000000 [ 8.103775] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 8.103794] CR2: ffff888008000670 CR3: 000000000242e003 CR4: 00000000001= 706f0 [ 8.103820] Kernel panic - not syncing: Fatal exception [ 8.103929] Kernel Offset: disabled > If > that doesn't help, I'd suggest bisecting the following range: > 58852f24f956..291b3abed657 It will take some time, as the issue doesn't happen every time. > Sorry for the trouble! >=20 > - Kevin >=20 > > FWIW, the issue still happens on 7.0-rc6. > > > >> Juergen > >> > >> [1]: https://lore.kernel.org/lkml/20251215150323.2218608-1-kevin.brods= ky@arm.com/ --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --MOg8fIXj0kDdUuxl Content-Type: application/pgp-signature; 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Tue, 07 Apr 2026 20:47:44 -0700 (PDT) X-Received: by 2002:a17:903:2ec7:b0:2b2:454f:b951 with SMTP id d9443c01a7336-2b28176a3cemr203121315ad.29.1775620063681; Tue, 07 Apr 2026 20:47:43 -0700 (PDT) Message-ID: <92ee00a9-0094-4481-9156-709b94ba3b82@oss.qualcomm.com> Date: Wed, 8 Apr 2026 09:16:39 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v12 3/3] of: Respect #{iommu,msi}-cells in maps To: Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Saravana Kannan , Richard Zhu , Lucas Stach , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Prakash Gupta , Vikash Garodia Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Charan Teja Kalla References: <20260331-parse_iommu_cells-v12-0-decfd305eea9@oss.qualcomm.com> <20260331-parse_iommu_cells-v12-3-decfd305eea9@oss.qualcomm.com> Content-Language: en-US From: Vijayanand Jitta In-Reply-To: <20260331-parse_iommu_cells-v12-3-decfd305eea9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=etfvCIpX c=1 sm=1 tr=0 ts=69d5cfe1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=OsyBWCJeBE2wmg0BnjgA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: U8d-0kMs7f8J6_CcJR3QfzqrrMY0MBgb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA4MDAzMSBTYWx0ZWRfX1IwYNaWQUeib aTFZNA0JEu4boU+zo2DdRFlGoIACV9Xlm8xA0QIe29DPrQ+mRsRwi+XLXMXo/j7rPWlKBL52/g0 Gokk5gDVIkzy2f1Ci/R/YZ0mq3swjh/2oflafswhUTwyFQrC8Tbqno75kfmatdSzWsQWrNkYPJi lOYuXso3SyM5fZDbyuOP465odbUPq4DI+e+2Ucnlvgo4LYj1XBDySqCIChV4Jk5kuqh94HIqQg1 QUSI9Z0Zg6TNWbHS1Nysytx/1BDSe4qb9DCC/stlwFtBwo8DhYE1Mbr22B/kJP69IkWGgxqgn1i uvMCKjm0O4kjbQHn5HDaez4vvEtQKwwR97WZDITuul9ZkOzJSAmPi5Rp/zOkZRvkBx12SGqj4o3 NaBtgtIqDEK4osMzNWaIO4XPat7rPhGT2K+Yy7mwNUEQzwzxvHa5GvNzjyJlDYrJ/YHi4mrP9iq HnP/jTbjphKtEcMdbHA== X-Proofpoint-GUID: U8d-0kMs7f8J6_CcJR3QfzqrrMY0MBgb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-08_01,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 spamscore=0 clxscore=1015 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080031 X-purgate-ID: tlsNG-16d1c6/1775620067-AE12E3D8-58714942/0/0 X-purgate-type: clean X-purgate-size: 12730 On 3/31/2026 7:34 PM, Vijayanand Jitta wrote: > From: Robin Murphy > > So far our parsing of {iommu,msi}-map properties has always blindly > assumed that the output specifiers will always have exactly 1 cell. > This typically does happen to be the case, but is not actually enforced > (and the PCI msi-map binding even explicitly states support for 0 or 1 > cells) - as a result we've now ended up with dodgy DTs out in the field > which depend on this behaviour to map a 1-cell specifier for a 2-cell > provider, despite that being bogus per the bindings themselves. > > Since there is some potential use in being able to map at least single > input IDs to multi-cell output specifiers (and properly support 0-cell > outputs as well), add support for properly parsing and using the target > nodes' #cells values, albeit with the unfortunate complication of still > having to work around expectations of the old behaviour too. > > Since there are multi-cell output specifiers, the callers of of_map_id() > may need to get the exact cell output value for further processing. > Update of_map_id() to set args_count in the output to reflect the actual > number of output specifier cells. > > Signed-off-by: Robin Murphy > Signed-off-by: Charan Teja Kalla > Signed-off-by: Vijayanand Jitta > --- > drivers/of/base.c | 155 ++++++++++++++++++++++++++++++++++++++++------------- > include/linux/of.h | 6 ++- > 2 files changed, 123 insertions(+), 38 deletions(-) > > diff --git a/drivers/of/base.c b/drivers/of/base.c > index b3d002015192..7b22e2484e1c 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c > @@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu) > return cache_level; > } > > +/* > + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while > + * specifying only 1 cell. Fortunately they all consist of value '1' > + * as the 2nd cell entry with the same target, so check for that pattern. > + * > + * Example: > + * IOMMU node: > + * #iommu-cells = <2>; > + * > + * Device node: > + * iommu-map = <0x0000 &smmu 0x0000 0x1>, > + * <0x0100 &smmu 0x0100 0x1>; > + */ > +static bool of_check_bad_map(const __be32 *map, int len) > +{ > + __be32 phandle = map[1]; > + > + if (len % 4) > + return false; > + for (int i = 0; i < len; i += 4) { > + if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1)) > + return false; > + } > + return true; > +} > + > /** > * of_map_id - Translate an ID through a downstream mapping. > * @np: root complex device node. > * @id: device ID to map. > * @map_name: property name of the map to use. > + * @cells_name: property name of target specifier cells. > * @map_mask_name: optional property name of the mask to use. > * @filter_np: optional device node to filter matches by, or NULL to match any. > * If non-NULL, only map entries targeting this node will be matched. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] will contain the translated ID. If a map entry was > - * matched, @arg->np will be set to the target node with a reference > - * held that the caller must release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * as defined by @cells_name in the target node, and > + * @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np will be set > + * to the target node with a reference held that the caller must release > + * with of_node_put(). > * > * Given a device ID, look up the appropriate implementation-defined > * platform ID and/or the target device which receives transactions on that > @@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu) > * Return: 0 on success or a standard error code on failure. > */ > int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, struct of_phandle_args *arg) > { > u32 map_mask, masked_id; > - int map_len; > + int map_bytes, map_len, offset = 0; > + bool bad_map = false; > const __be32 *map = NULL; > > if (!np || !map_name || !arg) > return -EINVAL; > > - map = of_get_property(np, map_name, &map_len); > + map = of_get_property(np, map_name, &map_bytes); > if (!map) { > if (filter_np) > return -ENODEV; > @@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id, > return 0; > } > > - if (!map_len || map_len % (4 * sizeof(*map))) { > - pr_err("%pOF: Error: Bad %s length: %d\n", np, > - map_name, map_len); > - return -EINVAL; > - } > + if (map_bytes % sizeof(*map)) > + goto err_map_len; > + map_len = map_bytes / sizeof(*map); > > /* The default is to select all bits. */ > map_mask = 0xffffffff; > @@ -2153,39 +2183,82 @@ int of_map_id(const struct device_node *np, u32 id, > of_property_read_u32(np, map_mask_name, &map_mask); > > masked_id = map_mask & id; > - for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { > + > + while (offset < map_len) { > struct device_node *phandle_node; > - u32 id_base = be32_to_cpup(map + 0); > - u32 phandle = be32_to_cpup(map + 1); > - u32 out_base = be32_to_cpup(map + 2); > - u32 id_len = be32_to_cpup(map + 3); > + u32 id_base, phandle, id_len, id_off, cells = 0; > + const __be32 *out_base; > + > + if (map_len - offset < 2) > + goto err_map_len; > + > + id_base = be32_to_cpup(map + offset); > > if (id_base & ~map_mask) { > - pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", > - np, map_name, map_name, > - map_mask, id_base); > + pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n", > + np, map_name, map_mask_name, map_mask, id_base); > return -EFAULT; > } > > - if (masked_id < id_base || masked_id >= id_base + id_len) > - continue; > - > + phandle = be32_to_cpup(map + offset + 1); > phandle_node = of_find_node_by_phandle(phandle); > if (!phandle_node) > return -ENODEV; > > + if (!bad_map && of_property_read_u32(phandle_node, cells_name, &cells)) { > + pr_err("%pOF: missing %s property\n", phandle_node, cells_name); > + of_node_put(phandle_node); > + return -EINVAL; > + } > + > + if (map_len - offset < 3 + cells) { > + of_node_put(phandle_node); > + goto err_map_len; > + } > + > + if (offset == 0 && cells == 2) { > + bad_map = of_check_bad_map(map, map_len); > + if (bad_map) { > + pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n", > + np, map_name, cells_name); > + cells = 1; > + } > + } > + > + out_base = map + offset + 2; > + offset += 3 + cells; > + > + id_len = be32_to_cpup(map + offset - 1); > + if (id_len > 1 && cells > 1) { > + /* > + * With 1 output cell we reasonably assume its value > + * has a linear relationship to the input; with more, > + * we'd need help from the provider to know what to do. > + */ > + pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n", > + np, map_name, id_len, cells); > + of_node_put(phandle_node); > + return -EINVAL; > + } > + id_off = masked_id - id_base; > + if (masked_id < id_base || id_off >= id_len) { > + of_node_put(phandle_node); > + continue; > + } > + > if (filter_np && filter_np != phandle_node) { > of_node_put(phandle_node); > continue; > } > > arg->np = phandle_node; > - arg->args[0] = masked_id - id_base + out_base; > - arg->args_count = 1; > + for (int i = 0; i < cells; i++) > + arg->args[i] = id_off + be32_to_cpu(out_base[i]); > + arg->args_count = cells; > > pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", > - np, map_name, map_mask, id_base, out_base, > - id_len, id, masked_id - id_base + out_base); > + np, map_name, map_mask, id_base, be32_to_cpup(out_base), > + id_len, id, id_off + be32_to_cpup(out_base)); > return 0; > } > > @@ -2196,6 +2269,10 @@ int of_map_id(const struct device_node *np, u32 id, > arg->args[0] = id; > arg->args_count = 1; > return 0; > + > +err_map_len: > + pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes); > + return -EINVAL; > } > EXPORT_SYMBOL_GPL(of_map_id); > > @@ -2205,18 +2282,21 @@ EXPORT_SYMBOL_GPL(of_map_id); > * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform > * stream/device ID) used as the lookup key in the iommu-map table. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] contains the translated ID. If a map entry was matched, > - * @arg->np holds a reference to the target node that the caller must > - * release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * and @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np holds a > + * reference to the target node that the caller must release with > + * of_node_put(). > * > - * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". > + * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells", > + * and "iommu-map-mask". > * > * Return: 0 on success or a standard error code on failure. > */ > int of_map_iommu_id(const struct device_node *np, u32 id, > struct of_phandle_args *arg) > { > - return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); > + return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg); > } > EXPORT_SYMBOL_GPL(of_map_iommu_id); > > @@ -2229,17 +2309,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); > * to match any. If non-NULL, only map entries targeting this node will > * be matched. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] contains the translated ID. If a map entry was matched, > - * @arg->np holds a reference to the target node that the caller must > - * release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * and @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np holds a > + * reference to the target node that the caller must release with > + * of_node_put(). > * > - * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". > + * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells", > + * and "msi-map-mask". > * > * Return: 0 on success or a standard error code on failure. > */ > int of_map_msi_id(const struct device_node *np, u32 id, > const struct device_node *filter_np, struct of_phandle_args *arg) > { > - return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); > + return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg); > } > EXPORT_SYMBOL_GPL(of_map_msi_id); > diff --git a/include/linux/of.h b/include/linux/of.h > index 8548cd9eb4f1..51ac8539f2c3 100644 > --- a/include/linux/of.h > +++ b/include/linux/of.h > @@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur); > bool of_console_check(const struct device_node *dn, char *name, int index); > > int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, struct of_phandle_args *arg); > > int of_map_iommu_id(const struct device_node *np, u32 id, > @@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag > } > > static inline int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, > struct of_phandle_args *arg) > { > Gentle ping. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <48df7b1b-5d07-4eeb-8028-6a90c12a6e2a@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775628544-32D2796F-E2271E38/0/0 X-purgate-type: clean X-purgate-size: 3403 On 07.04.2026 23:58, Andrew Cooper wrote: > On 24/11/2025 2:59 pm, Jan Beulich wrote: >> --- a/xen/arch/x86/cpu-policy.c >> +++ b/xen/arch/x86/cpu-policy.c >> @@ -812,19 +812,20 @@ static void __init calculate_hvm_max_pol >> if ( !cpu_has_vmx_xsaves ) >> __clear_bit(X86_FEATURE_XSAVES, fs); >> } >> + else >> + { >> + /* >> + * Xen doesn't use PKS, so the guest support for it has opted to not use >> + * the VMCS load/save controls for efficiency reasons. This depends on >> + * the exact vmentry/exit behaviour, so don't expose PKS in other >> + * situations until someone has cross-checked the behaviour for safety. >> + */ >> + __clear_bit(X86_FEATURE_PKS, fs); >> + } >> >> if ( !cpu_has_vmx_msrlist ) >> __clear_bit(X86_FEATURE_MSRLIST, fs); >> >> - /* >> - * Xen doesn't use PKS, so the guest support for it has opted to not use >> - * the VMCS load/save controls for efficiency reasons. This depends on >> - * the exact vmentry/exit behaviour, so don't expose PKS in other >> - * situations until someone has cross-checked the behaviour for safety. >> - */ >> - if ( !cpu_has_vmx ) >> - __clear_bit(X86_FEATURE_PKS, fs); >> - >> /* >> * Make adjustments to possible (nested) virtualization features exposed >> * to the guest >> > > These clauses aren't logically doing the same thing.  So while the > compiler can merge them, I don't think it's a good idea to do so at a > source level. > > The "if ( vmx ) " block we can just see the end of is for features which > need to cross-check extra VMX capabilities.  Each of RDTSCP, INVPCID and > XSAVES are #UD unless explicitly enabled.  MPX is the odd-one out, > checking the load/save capabilities. > > I suspect this list is incomplete.  These cross-checks shouldn't fail on > real hardware, where the VMX capabilities should match the native > features, but nested virt is rife with enumeration bugs here. > > The second "if ( !vmx )" clause is different.  This is really "I wired > up PKS based on how Intel works, and if AMD ever gains it it will > definitely need context switching changes to work".  This is in lieu of > having dedicated Intel/AMD annotations for features. Right, and this is what I'm using the new "else" body for later in the series. > The MSRLIST addition from the prior patch is arguably misplaced, except > it's trying to cover both of the aspects. Why is it misplaced? Where else would you want it to go? The VMX aspect, as you say, is included in cpu_has_vmx_msrlist, so it doesn't need separate checking for VMX. > AMD are making no obvious moves to add PKS, and I expect MSRLIST is even > lower down their priority list. > > Overall, we need checks here for every guest-visible feature which: > * has VMCS/VMCB controls which are enumerated separately > * needs new context switching considerations Which in this series are USER-MSR and MSR-IMM. Hence this prereq change, to simplify the additions there. > Maybe the "if ( !vmx )" shouldn't really be written this way.  I'm open > to suggestions, but making it an else block isn't a solution. Well in this situation I guess it's you to make suggestions. I have made mine by way of this submission. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 07:34:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 07:34:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275464.1561275 (Exim 4.92) (envelope-from ) id 1wANQ8-0006D6-RK; Wed, 08 Apr 2026 07:33:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275464.1561275; Wed, 08 Apr 2026 07:33:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wANQ8-0006Cz-Og; Wed, 08 Apr 2026 07:33:52 +0000 Received: by outflank-mailman (input) for mailman id 1275464; Wed, 08 Apr 2026 07:33:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wANQ7-0006Ct-HU for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 07:33:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wANQ6-000yRK-F1 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 09:33:50 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d604d6-2eae-0a2a0a5409dd-0a2a450a9eae-28 for ; Wed, 08 Apr 2026 09:33:50 +0200 Received: from [198.2.180.46] (helo=mail180-46.suw31.mandrillapp.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d604dc-ee98-0a2a450a0019-c602b42ed8a3-3 for ; Wed, 08 Apr 2026 09:33:49 +0200 Received: from pmta11.mandrill.prod.suw01.rsglab.com (localhost [127.0.0.1]) by mail180-46.suw31.mandrillapp.com (Mailchimp) with ESMTP id 4frFDX3KFpz8XS3d2 for ; Wed, 8 Apr 2026 07:33:48 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id f394fed23b2e4ce4865f10734d71a531; Wed, 08 Apr 2026 07:33:48 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775633628; x=1775903628; bh=lf/7x995PIuMmZC7YZDG2jKn3t9Oc495yOkrRXw8d4M=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=cAfLHoz+9gelA+wWjlBpE5/+7ZLnszfyOQEwdGb41ArKa/AhC+x4g6dfKobJRrjKJ YrUZ4ylR6PSokkdrxPlOR2xD1NrsqelHwBLyYsrv4GFmL460KJH8wxTMCQQo0Sqjs7 0WaxpO7ogofHR1UVmSFucR2N5Cgaix7PQJOprr7wNNRrzS7aanYtzFnw2w1MV0wvyq YCuIn6vPln3WVZFO81jxk4gZuOMBQg3IEDJPT73jC7QXPWERgH/sd32yNNUzBBgL6Y UPvKfLxbN+iM1hv8G6K6A0hzHehDMqxuYwrCmv9EAi7U09UJ09sx5LuE3AiB79MsIX 4BtPF+u2htLEw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775633628; x=1775894128; i=thierry.escande@vates.tech; bh=lf/7x995PIuMmZC7YZDG2jKn3t9Oc495yOkrRXw8d4M=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=kgD+GOfVL4hQRh+lUUqs1M6Grgfznzt40ooRn5aKRJRPf+yHks52SAVp6XPUsSR0r ODnWINq2XR8hRcrmC7s0ALaVBwGt3TRawjZIvQTaMzBWwIrxYJUqok+a3rFtXfWF0s qCUM+rU5X6KR0fWow9I6nGcknD1ZtRN2qXv8e3KgxQtPTfyPkpy9xxXTyPXLdrw6vx i1SKDWzFBEznwUJrCQbljhs8A/ziY5wtc5JaYjHyjPkqzrT2TuIOJrd+HQl3E6hn4H rJN9HSEG7G12QqBokWoaDLAekqI8AemO4neWsbfzV/q3rCBWaIiEBzQGopfcTZxcPt W3Drd1rjmk9lQ== From: "Thierry Escande" Subject: =?utf-8?Q?Re:=20[PATCH=200/4]=20Xen:=20Add=20Q35=20initial=20support=20for=20HVM=20guests?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775633627298 Message-Id: <7db25729-b4ab-41d4-8790-097b5338fe17@vates.tech> To: "=?utf-8?Q?Daniel=20P.=20Berrang=C3=A9?=" , "Anthony PERARD" Cc: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" , qemu-devel@nongnu.org, "Paolo Bonzini" , "Richard Henderson" , "Michael S. Tsirkin" , "Eduardo Habkost" , xen-devel@lists.xenproject.org References: <20260313164649.794591-1-thierry.escande@vates.tech> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.f394fed23b2e4ce4865f10734d71a531?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260408:md Date: Wed, 08 Apr 2026 07:33:48 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1775633630-BE54E0B1-4237DA9F/0/0 X-purgate-type: clean X-purgate-size: 2595 Hi, On 3/24/26 10:59, Daniel P. Berrang=C3=A9 wrote: > On Tue, Mar 24, 2026 at 09:28:00AM +0000, Anthony PERARD wrote: >> On Sat, Mar 14, 2026 at 03:16:15PM +0100, Marek Marczykowski-G=C3=B3reck= i wrote: >>> On Fri, Mar 13, 2026 at 04:46:56PM +0000, Thierry Escande wrote: >>>> This patch series introduces Q35 chipset support for Xen HVM guests. T= his is >>>> based on the work from Alexey Gerasimenko (See patchset [1] for refere= nce). >>>> >>>> This series does not implement device passthrough as this will need mo= re work >>>> on the Xen side to support multiple PCI buses. Since Q35 chipset does = not >>>> support device hotplugging and with current Xen mechanism for device >>>> passthrough, they have to be plugged to a new PCIe root port, i.e. not= the PCI >>>> bus 0. >>> >>> I always found it weird that Xen does hot-plugging of PCI passthrough >>> devices... Wouldn't it be easier to change this (connect them from the >>> very start, via QEMU cmdline) and declare hotplug as unsupported (at >>> least at this time)? I realize it's more complex change at the toolstac= k >>> side, but overall may simplify things and maybe even improve >>> reliability. >> >> Skipping hot-plug on Q35 sounds good to me. >> >> I though we could keep using QMP to do cold plug, with the experimental >> "--preconfig", but "device_add" isn't allowed :-(. So yes, doing this >> via command line sounds fine. >> >> In libxl, we might be able to transform the json for `device_add` into >> the command line counterpart for `-device` fairly easily so the argument >> are only generated in a single place. Then we could skip the QMP >> "device_add" in libxl when it's already done via command line. > > -device accepts JSON directly, so there's no transformation you > need to do from the QMP JSON. For example: > > -device '{"driver":"pcie-root-port","port":8,"chassis":1,"id":"pci.1","= bus":"pcie.0","multifunction":true,"addr":"0x1"}' > > Likewise -object, -audiodev and -netdev accept QMP JSON too Thanks for your help and directions. I have a few patches that I will send soon as RFC to gather your feedback. They add a 'hotplug' option for pci devices, enabled by default, to control if the device should be hot-plugged using QMP 'device_add' command or through Qemu command line with `-device xen-pci-passthrough,...'. The 'device_add' command is skipped but the 'pci-query' check remains. Regards, -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 08:35:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 08:35:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275493.1561284 (Exim 4.92) (envelope-from ) id 1wAONA-0006Tc-EE; Wed, 08 Apr 2026 08:34:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275493.1561284; Wed, 08 Apr 2026 08:34:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAONA-0006TV-AJ; Wed, 08 Apr 2026 08:34:52 +0000 Received: by outflank-mailman (input) for mailman id 1275493; Wed, 08 Apr 2026 08:34:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAON9-0006TP-5t for xen-devel@lists.xenproject.org; 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charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775637290-21B3896F-1106AE6A/0/0 X-purgate-type: clean X-purgate-size: 1193 Remove these checks now that we don't use these 2 ops anymore. Amends: 4bedbe47eef4f ("x86/emul: Remove fallback path from SWAPGS") Signed-off-by: Teddy Astie --- xen/arch/x86/x86_emulate/0f01.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0f01.c index 54bd6faf0f..4d36c7d289 100644 --- a/xen/arch/x86/x86_emulate/0f01.c +++ b/xen/arch/x86/x86_emulate/0f01.c @@ -187,8 +187,7 @@ int x86emul_0f01(struct x86_emulate_state *s, case 0xf8: /* swapgs */ generate_exception_if(!mode_64bit(), X86_EXC_UD); generate_exception_if(!mode_ring0(), X86_EXC_GP, 0); - fail_if(!ops->read_segment || !ops->read_msr || - !ops->write_segment || !ops->write_msr); + fail_if(!ops->read_msr || !ops->write_msr); if ( (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, ctxt)) != X86EMUL_OKAY || (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, -- 2.53.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 08:39:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 08:39:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275505.1561292 (Exim 4.92) (envelope-from ) id 1wAORR-00077K-Tv; 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AJvYcCVz4WTxLIs9Z+bfEgeRNwFc2id1L5Ap4MYjGprVyZIYklMsTmPlqhGQzql1dBRX90KOBdptRrg2Zf4=@lists.xenproject.org X-Gm-Message-State: AOJu0YzPJvbiWiNcxmAvkiG8ijXfvuEX0EVcQN+TMqB8xqLYsXxM7KFV 1dJMvrNd3s/vG2iqn/LRyXTzDG4bwMCYPvBwyuyROEEw1N/kfrRoIChv X-Gm-Gg: AeBDietWOjw0ciKvD9f+hQKqFS0Cgl/b1DuIlzCEL1A1lvWGkwNqtzSDL7LiiRU52UB 100qFaxG626DiUc+EX2oXuKPddLrS/Ih3w9QSTqYjpYSc0+vi7BLSWao2zmBP+lmCimhwvU8+zQ 5kwux2KOHMcmGmbUJ8YEk1mFNi1EXaAT0uqPmTcS8drYSd6K58l44PYjs2ya8f0Xvne1CVEBUoO ZZuCbyIwP97gJ3tl3VybyBDBoxIL63YL7xl5JhAybiLdX3YLL6EJeM0rdhBx0Jot/GoZjLWxNer 8jhtLT+YtSuWt27EBSRS7sCRPSjl+aZ+ce+npBZPigQtB/wbfQimCMVq1t0uhSv/guJwGcUn4qN QXt9ggVakdKI1heWJj73QaxrnHgHDL+FVUUXiD2kn2NssNFPWJnshMaf8TMDwHXX2K9ZZOaiAkS lSlO4pW81EWdtwbfU1lQX5xfYUdfJBZ3duvjfTQX3tnH+YMGK6gjwsWaXgFC98YMZpkTx/7NG3c E0= X-Received: by 2002:a05:600c:6986:b0:487:2671:fb8f with SMTP id 5b1f17b1804b1-488996ecbf3mr258854265e9.8.1775640543674; Wed, 08 Apr 2026 02:29:03 -0700 (PDT) Message-ID: <4ebcb77b-7666-4087-b7c4-07e64260e5de@gmail.com> Date: Wed, 8 Apr 2026 11:29:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] xen/riscv: add exception table support To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Oleksii Kurochko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775640544-BE54E0B1-E9372992/10/73395122804 X-purgate-type: spam X-purgate-size: 3559 On 4/2/26 8:24 AM, Jan Beulich wrote: > On 31.03.2026 21:04, Oleksii Kurochko wrote: >> --- /dev/null >> +++ b/xen/arch/riscv/extable.c >> @@ -0,0 +1,85 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> + >> +#define EX_FIELD(ptr, field) ((unsigned long)&(ptr)->field + (ptr)->field) >> + >> +static inline unsigned long ex_insn(const struct exception_table_entry *ex) >> +{ >> + return EX_FIELD(ex, insn); >> +} >> + >> +static inline unsigned long ex_fixup(const struct exception_table_entry *ex) >> +{ >> + return EX_FIELD(ex, fixup); >> +} >> + >> +static void __init cf_check swap_ex(void *a, void *b) >> +{ >> + struct exception_table_entry *x = a, *y = b, tmp; >> + long delta = b - a; >> + >> + tmp = *x; >> + x->insn = y->insn + delta; >> + y->insn = tmp.insn - delta; >> + >> + x->fixup = y->fixup + delta; >> + y->fixup = tmp.fixup - delta; >> +} >> + >> +static int cf_check cmp_ex(const void *a, const void *b) >> +{ >> + const unsigned long insn_a = ex_insn(a); >> + const unsigned long insn_b = ex_insn(b); >> + >> + /* avoid overflow */ >> + return (insn_a > insn_b) - (insn_a < insn_b); > > What is the (slightly malformed) comment about? I don't see anything close > to possibly causing overflow here. Originally, I thought to imeplement this function something like: return insn_a - insn_b; It'd get integer overflow when insn_a is a very small number and insn_b is very large. It could drop the comment to avoid confusion. > >> --- /dev/null >> +++ b/xen/arch/riscv/include/asm/extable.h >> @@ -0,0 +1,58 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#ifndef ASM__RISCV__ASM_EXTABLE_H >> +#define ASM__RISCV__ASM_EXTABLE_H >> + >> +#ifdef __ASSEMBLER__ >> + >> +#define ASM_EXTABLE(insn, fixup) \ >> + .pushsection .ex_table, "a"; \ >> + .balign 4; \ >> + .long ((insn) - .); \ >> + .long ((fixup) - .); \ > > For readability's sake I'm generally advocating for having enough, but > not more parentheses than necessary. What's the purpose of the outer pair > here and ... > >> + .popsection; >> + >> +.macro asm_extable, insn, fixup >> + ASM_EXTABLE(\insn, \fixup) >> +.endm >> + >> +#else /* __ASSEMBLER__ */ >> + >> +#include >> +#include >> + >> +struct cpu_user_regs; >> + >> +#define ASM_EXTABLE(insn, fixup) \ >> + ".pushsection .ex_table, \"a\"\n" \ >> + ".balign 4\n" \ >> + ".long ((" #insn ") - .)\n" \ >> + ".long ((" #fixup ") - .)\n" \ > > ... here? It looked visually better to me but I am okay to drop them. > > I'm also uncertain about the use of .long (generally in RISC-V code, and > really also in some other architectures). Imo, considering suffixes used > in the instruction set (e.g. load/store insns or OP-32 ones in RV64) .word > may be the more expressive directive. Agree, we could use .word instead of .long. > > Preferably with the adjustments: > Acked-by: Jan Beulich Thanks a lot. > Happy to carry out while committing, provided you agree. I would be happy with that. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 08 09:38:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 09:38:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275538.1561320 (Exim 4.92) (envelope-from ) id 1wAPMp-0007Tf-L6; Wed, 08 Apr 2026 09:38:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275538.1561320; Wed, 08 Apr 2026 09:38:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPMp-0007TY-IC; Wed, 08 Apr 2026 09:38:35 +0000 Received: by outflank-mailman (input) for mailman id 1275538; Wed, 08 Apr 2026 09:38:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wAPMo-0007TS-OB for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 09:38:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAPMo-00ElvW-43 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 11:38:34 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d62218-e002-0a2a0a5209dd-0a2a4508dd3a-26 for ; Wed, 08 Apr 2026 11:38:34 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d62219-fab6-0a2a45080019-d155802cd034-3 for ; Wed, 08 Apr 2026 11:38:33 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4889e045bc6so41717875e9.2 for ; Wed, 08 Apr 2026 02:38:33 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Agree, the & isn't needed here. > >> + : [csr] "i" (csr) >> + : >> + : fault ); >> + >> + return true; >> + >> + fault: >> + return false; >> +#else >> + bool allowed = false; >> + >> + asm_inline volatile ( >> + "1: csrr %[val], %[csr]\n" >> + " li %[allowed], 1\n" >> + "2:\n" >> + ASM_EXTABLE(1b, 2b) >> + : [val] "=&r" (*val), [allowed] "+r" (allowed) >> + : [csr] "i" (csr) >> + : ); > > Why the excess colon? Missed to proper cleanup. It could be also dropped. > > With these adjusted (again happy to do so while committing, so long > as you agree): I would be happy with that. > Reviewed-by: Jan Beulich Thanks! ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 08 09:45:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 09:45:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275547.1561329 (Exim 4.92) (envelope-from ) id 1wAPTH-0000av-Br; Wed, 08 Apr 2026 09:45:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275547.1561329; Wed, 08 Apr 2026 09:45:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPTH-0000ao-7i; Wed, 08 Apr 2026 09:45:15 +0000 Received: by outflank-mailman (input) for mailman id 1275547; Wed, 08 Apr 2026 09:45:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPTF-0000ai-Q6 for xen-devel@lists.xenproject.org; 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>>> +} >>> + >>> +static inline unsigned long ex_fixup(const struct >>> exception_table_entry *ex) >>> +{ >>> +    return EX_FIELD(ex, fixup); >>> +} >>> + >>> +static void __init cf_check swap_ex(void *a, void *b) >>> +{ >>> +    struct exception_table_entry *x = a, *y = b, tmp; >>> +    long delta = b - a; >>> + >>> +    tmp = *x; >>> +    x->insn = y->insn + delta; >>> +    y->insn = tmp.insn - delta; >>> + >>> +    x->fixup = y->fixup + delta; >>> +    y->fixup = tmp.fixup - delta; >>> +} >>> + >>> +static int cf_check cmp_ex(const void *a, const void *b) >>> +{ >>> +    const unsigned long insn_a = ex_insn(a); >>> +    const unsigned long insn_b = ex_insn(b); >>> + >>> +    /* avoid overflow */ >>> +    return (insn_a > insn_b) - (insn_a < insn_b); >> >> What is the (slightly malformed) comment about? I don't see anything >> close >> to possibly causing overflow here. > > Originally, I thought to imeplement this function something like: >   return insn_a - insn_b; > > It'd get integer overflow when insn_a is a very small number and > insn_b is very large. > > It could drop the comment to avoid confusion. "insn_a - insn_b" is a very common bug in cmp() functions.  It does cause the sort/search to malfunction when the subtraction overflows. However, the form you've got (a > b) - (b > a) is a very common correct form.  I'd drop the comment. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 09:46:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 09:46:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275554.1561338 (Exim 4.92) (envelope-from ) id 1wAPU9-00013y-Iq; Wed, 08 Apr 2026 09:46:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275554.1561338; Wed, 08 Apr 2026 09:46:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPU9-00013r-Fp; Wed, 08 Apr 2026 09:46:09 +0000 Received: by outflank-mailman (input) for mailman id 1275554; Wed, 08 Apr 2026 09:46:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPU8-00012V-7m for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 09:46:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAPU7-004ggW-Ii for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 11:46:07 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d623dd-5cb7-0a2a0a5109dd-0a2a4504a398-8 for ; Wed, 08 Apr 2026 11:46:07 +0200 Received: from [162.55.131.47] (helo=support.bugseng.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d623df-bb33-0a2a45040019-a237832f9b02-3 for ; Wed, 08 Apr 2026 11:46:07 +0200 Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) (Authenticated sender: nicola) by support.bugseng.com (Postfix) with ESMTPA id 14C154EE3C0D; Wed, 8 Apr 2026 11:46:07 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: bugseng.com; arc=none smtp.remote-ip=162.55.131.47 ARC-Seal: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; cv=none; t=1775641567; b=JGjmYZyOAsbwuiMD6FjKmlW9mfxp0Xd5VNrZ2Ehc+hZJX81lpWJHN47hzBf1btyS28KF 35zzqMAohzPTt2kUbMY+KIF55ygDPJm4j+ACyXnby1ZEQsC8EfO0NJ4b6I8pNdV+HzGJZ aEbSrkUTbsLe6VSXm4iSv7HW11juSu493f9oApy/KXiip+djaHFk86KqNcenqVfo+DhEP hPR3Hv9uYmew/sZbQLt9J17mUos3z1n3nX1NfOuQKa3yS6TqnBFAT3M4XVNrMA3tpneMl imw8dCG3xDkIyqXPJTOyYbD7Ch5PZkxc7qifDdMzM44T+Zrg2T665LNQnRmq8E6FIq25g 2qxD0/PIdx6QysWeoZI1W0BBV0EWqqmjIwX1IR1sZYhUwMdaUwgwgTyra9Ng90qqBzuil ccapBQeu2HGAJdulVU26bn/s8tgpWgaulOg8GwHqBm5d1qyqicObtU3JRkFGMhTz20W9P 0CHPPEhhmthZEBXTETayArgVfit42/iL6XZZq2p5hy0lX4QwproFtdjYktI2AoHXnf/aB pGsigGGqcFK0qCpRJ7yyek7J0o9ofBw3cssCDHnI2iKbFNvH7drzD0iXA4ddaY5wBXVIG nHech8r348uFvGojvBFG+TkW/AC/pUBuVS/mZuLn+crS+lolJvV/xzKKJcB8pr4= ARC-Message-Signature: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; c=relaxed/relaxed; t=1775641567; h=MIME-Version:Date:From:To:Cc:Subject:In-Reply-To:References: Message-ID:X-Sender:Organization:Content-Type: Content-Transfer-Encoding; bh=o8pjVGQOPOGXPvv25UbA6zDoKtK4aRmloMG823Xxr4U=; b=WI0IRWj82rjflsWEmcNDF/GDafBVAhBkCM51CwGy49S4crzcy7tJbX/juT+tgHHaSDSf RgHzcqQr1cR6+X2Ax3LXNVHDiVgUW7JpIXDHTnTajPVEZoBUdLjaqrE+IV/dJraP/R9Bq KWB0tCLJSCzwyk4/xIbmZgJpGHWwbdr2g7qCSAVuAcFN1bwYU2M8cVHsk2f3WIGbTawP6 IWMbzMxzWg2cfZLUUmqrJ6GVtmA9xHhTJcUl9qF6bBL+C9rHUbHNz9sg3mzSNvuQdaOk4 YvMQpoF9nbbf4xOux/zOOeinxaHTr2iC0OkS6C13TyHEOL8lBCVEcNJ2tIqB6Afu4t+Ld mAddu0scRYd1Mn+Q0eBM2A4atUbtdkqzbVZbCxeASE00he4MV34/WTcsr3X5fsyW6UII9 rflSJtoSZ+/8+cupLoWQHL0Z4rQ4VzPRhyuHDhmFcxY2OUhHXGfWsM9NOJNsYTcGlo48T V7ksOkv0EwxTEtouIdmj/lW0kmd2vh2GE4pWCk7l1R5vDOwjR871p+rv1w3Tqr9WXsz0O +DK3oc3ZrD2VyjBQpUYHpsWmeECXNuzEJ+pn5FjQOJWJL1etppF1tE8kU2v1zB/uq7Z6b WwEyhyR2zW0nd0s4IqEy8Qs67dr+1gKUC13adtcJn5JNT0omBiloe5pZ41qXfAU= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Wed, 08 Apr 2026 11:46:07 +0200 From: Nicola Vetrini To: Andrew Cooper , Michal Orzel Cc: xen-devel@lists.xenproject.org, Julien Grall , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 0/2] Final series to make Arm MISRA allcode green In-Reply-To: <68cea196-efdc-4481-9e4b-bb450bcd2071@citrix.com> References: <20260407103434.90838-1-michal.orzel@amd.com> <68cea196-efdc-4481-9e4b-bb450bcd2071@citrix.com> Message-ID: X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775641567-3172251B-88AE9EBC/0/0 X-purgate-type: clean X-purgate-size: 896 On 2026-04-08 11:22, Andrew Cooper wrote: > On 07/04/2026 11:34 am, Michal Orzel wrote: >> No more regressions for clean guidelines: >> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >> >> Michal Orzel (2): >> iommu/arm: smmu: Fix variable shadowing >> iommu/arm: ipmmu-vmsa: Fix variable shadowing >> >> xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >> xen/drivers/passthrough/arm/smmu.c | 7 +++---- >> 2 files changed, 5 insertions(+), 8 deletions(-) > > If all the violations are fixed, should this test be made blocking? > > ~Andrew Only if they are also clean on x86; otherwise an arm-specific list of clean rules should be made (probably better). @Michal what do you prefer? -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 09:51:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 09:51:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275566.1561346 (Exim 4.92) (envelope-from ) id 1wAPZB-0002rg-6s; Wed, 08 Apr 2026 09:51:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275566.1561346; Wed, 08 Apr 2026 09:51:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPZB-0002rZ-4B; Wed, 08 Apr 2026 09:51:21 +0000 Received: by outflank-mailman (input) for mailman id 1275566; Wed, 08 Apr 2026 09:51:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) 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action=none header.from=citrix.com; Message-ID: <14185c87-84c0-4019-a3f6-50587b941350@citrix.com> Date: Wed, 8 Apr 2026 10:51:11 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , xen-devel@lists.xenproject.org, Julien Grall , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 0/2] Final series to make Arm MISRA allcode green To: Nicola Vetrini , Michal Orzel References: <20260407103434.90838-1-michal.orzel@amd.com> <68cea196-efdc-4481-9e4b-bb450bcd2071@citrix.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P123CA0489.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1ab::8) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|PH7PR03MB7135:EE_ X-MS-Office365-Filtering-Correlation-Id: 7cf7f9b5-b2b4-4ec8-2c1b-08de95545fb0 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=?utf-8?B?dUJFYlNMSHNvNExlWS9saU1YbVU4OEtKNmgvVXVNc2pUVkw4b3BIc3BkTDZC?= =?utf-8?B?K0cwVXowZWJyTFVLWWNVd3BaZkpqUG5lTmZnUEV1VXdveXpveVUvOUxtS1JR?= =?utf-8?B?ZS95a2dNMmIwZUQ5ZXZBemhUUnYxN2hSSjc0RDhnT25FTHRod3NJcEc1cFZ6?= =?utf-8?B?V3dlRWE1WUQySjBYRm45amxKM3lPMCtmQU42TzFnR3VhRGYwRHlvUyt6RXEw?= =?utf-8?Q?CPNVLUWfGGhIzDck=3D?= X-OriginatorOrg: citrix.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7cf7f9b5-b2b4-4ec8-2c1b-08de95545fb0 X-MS-Exchange-CrossTenant-AuthSource: CH8PR03MB8275.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 09:51:14.9969 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 62Snx6t+0J5kjvw/ZtOzryUyv4Y4JMdL4vsmD2MxCaDKC0yZmqDed0DPZYCBN9WQrUJXyf3tng/8F4F0/ZJNPuorFvLy/ECROfurg7z7fuM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR03MB7135 X-purgate-ID: tlsNG-42698a/1775641878-EFD472A1-8637F84E/0/0 X-purgate-type: clean X-purgate-size: 1398 On 08/04/2026 10:46 am, Nicola Vetrini wrote: > On 2026-04-08 11:22, Andrew Cooper wrote: >> On 07/04/2026 11:34 am, Michal Orzel wrote: >>> No more regressions for clean guidelines: >>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >>> >>> Michal Orzel (2): >>>   iommu/arm: smmu: Fix variable shadowing >>>   iommu/arm: ipmmu-vmsa: Fix variable shadowing >>> >>>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >>>  xen/drivers/passthrough/arm/smmu.c       | 7 +++---- >>>  2 files changed, 5 insertions(+), 8 deletions(-) >> >> If all the violations are fixed, should this test be made blocking? >> >> ~Andrew > > Only if they are also clean on x86; otherwise an arm-specific list of > clean rules should be made (probably better). @Michal what do you prefer? > All I'm suggesting is this: xen.git/xen$ git diff diff --git a/automation/gitlab-ci/analyze.yaml b/automation/gitlab-ci/analyze.yaml index 4e9af9d60224..f01798c5dee6 100644 --- a/automation/gitlab-ci/analyze.yaml +++ b/automation/gitlab-ci/analyze.yaml @@ -149,7 +149,7 @@ eclair-ARM64-allcode:        CONFIG_STACK_PROTECTOR=y        CONFIG_UNSUPPORTED=y        CONFIG_VM_EVENT=y -  allow_failure: true +  allow_failure: false    eclair-ARM64-testing:    extends: eclair-ARM64-allcode so regressions become blocking. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:03:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:03:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275577.1561356 (Exim 4.92) (envelope-from ) id 1wAPlF-0004n4-6w; Wed, 08 Apr 2026 10:03:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275577.1561356; Wed, 08 Apr 2026 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linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Vijayanand Jitta , Charan Teja Kalla X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775642611; l=6465; i=vijayanand.jitta@oss.qualcomm.com; s=20260301; h=from:subject:message-id; bh=k94qEoqP6LeaqMjZ56JkwcDL9Caxb++/1ywGR2aNrcE=; b=Fa93m6jMAv59XO0RGhV08H7u/lbeMgEu+VO89mYeYe9+udo03+OfW5l6aRjt+/+cujOgn9u6U /txq4POfFP1D4nQK6IieIAafLv29dRyBbPOkaAXwmZAh5zFPlwXVp/j X-Developer-Key: i=vijayanand.jitta@oss.qualcomm.com; a=ed25519; pk=Lpi7Cs3wHe8KZtqvyci7FTOLzsKpEHKGCaPNZw+1zRI= X-Proofpoint-ORIG-GUID: LRXHuetsYPN4AIdrux3S5NkkT1dYfojD X-Proofpoint-GUID: LRXHuetsYPN4AIdrux3S5NkkT1dYfojD X-Authority-Analysis: v=2.4 cv=WZs8rUhX c=1 sm=1 tr=0 ts=69d62800 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=NEAV23lmAAAA:8 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=qMDWySynzQg1s02BiloA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=TjNXssC_j7lpFel5tvFf:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA4MDA5MSBTYWx0ZWRfXwTNtKqxCEoD2 CVkeZaP3+CfDG5O+zhjTHt/VC7/RVzguDDx2pbGbRh2Pn6SYfHdvdODmTT7RqkfgzKS2h4GrB79 vXK8D9sO3f944OtipA3xjougtS2o084VN2V8wqOFjLGAFpzht9KX4wZTSAYz0eGCQmDNxdvPxds /vOgmS1BHlAqQu3cQ9wN0K73FcVJx/5tfy743KQP2Zxyl9Rt+MEQV7J3fJEPG6RBHGhEraoTgJe EHfjYxm/btGBy9i7xCmUFG9NbiYeMPiCVgEMsV5qqqyB1CJMYa+FInQMXNaem7A3aEBtb/FDH+0 OIrR+Vc+V43SjWWti2u63Q7IMz/LzaJ3oHzdnS9Cqw3hO5NzqbWBiXDDcSsWeWDFrG4/zVsDJMc OnftxPFn7l1JSIJn6cu3oz34N2Hl9ayPw3JO1NKk5Jd2c+WpEO5mSDs/D1H6xSiujZ0AK5f10Sc S9FSExVml65w60vbkdg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080091 X-purgate-ID: tlsNG-ef75cf/1775642626-89B5041E-287AF279/0/0 X-purgate-type: clean X-purgate-size: 6467 So far our parsing of {iommu,msi}-map properties has always blindly assumed that the output specifiers will always have exactly 1 cell. This typically does happen to be the case, but is not actually enforced (and the PCI msi-map binding even explicitly states support for 0 or 1 cells) - as a result we've now ended up with dodgy DTs out in the field which depend on this behaviour to map a 1-cell specifier for a 2-cell provider, despite that being bogus per the bindings themselves. Since there is some potential use[1] in being able to map at least single input IDs to multi-cell output specifiers (and properly support 0-cell outputs as well), add support for properly parsing and using the target nodes' #cells values, albeit with the unfortunate complication of still having to work around expectations of the old behaviour too. -- Robin. Unlike single #{}-cell, it is complex to establish a linear relation between input 'id' and output specifier for multi-cell properties, thus it is always expected that len never going to be > 1. These changes have been tested on QEMU for the arm64 architecture. Since, this would also need update in dt-schema, raised PR[2] for the same. [1] https://lore.kernel.org/all/20250627-video_cb-v3-0-51e18c0ffbce@quicinc.com/ [2] PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184 Robin, Could this series be pulled into an immutable branch/tag, if it doesn't make it into the v7.1 merge window? There are client changes dependent on it, So it would help to get them moving forward rather than waiting another cycle. Thanks, Vijay V13: - Fix bad_map handling in of_map_id(): 'cells' is re-initialized to 0 on each loop iteration, so the !bad_map guard was insufficient, cells stayed 0 for all entries after the first. Fix by explicitly setting cells=1 when bad_map is true on every iteration. - Collected Acked-by from Frank Li. Link to v12: https://patch.msgid.link/20260331-parse_iommu_cells-v12-0-decfd305eea9@oss.qualcomm.com V12: - Call of_node_put() unconditionally in imx_pcie_add_lut_by_rid() thereby addressing comments from Bjorn Helgaas. Link to v11: https://lore.kernel.org/r/20260325-parse_iommu_cells-v11-0-1fefa5c0e82c@oss.qualcomm.com V11: - Added explicit filter_np parameter to of_map_id() and of_map_msi_id() per Dmitry Baryshkov's review feedback, making the filter explicit instead of overloading arg->np as both input filter and output parameter. - Removed of_node_put() from inside of_map_id(), making the caller responsible for reference management. Updated of_msi_xlate() to properly handle reference counting. - Collected ACKed by tags, and fixed minor typos. Link to v10: https://lore.kernel.org/r/20260309-parse_iommu_cells-v10-0-c62fcaa5a1d8@oss.qualcomm.com V10: - Move of_map_iommu_id()/of_map_msi_id() from include/linux/of.h to drivers/of/base.c as out-of-line helpers per feedback from Marc Zyngier and Rob Herring. - Add kernel-doc to document both helpers for discoverability and usage clarity. - Fix of_map_msi_id() wrapper and all its callers (cdx_msi.c, irq-gic-its-msi-parent.c, drivers/of/irq.c) to correctly use the new struct of_phandle_args-based API with proper of_node_put() handling as per feeback from Dmitry. Link to v9: https://lore.kernel.org/r/20260301-parse_iommu_cells-v9-0-4d1bceecc5e1@oss.qualcomm.com V9: - Updated TO/CC list based on feedback to include all relevant maintainers. - No functional changes to the patches themselves. Link to V8: https://lore.kernel.org/all/20260226074245.3098486-1-vijayanand.jitta@oss.qualcomm.com/ V8: - Removed mentions of of_map_args from commit message to match code. Link to V7: https://lore.kernel.org/all/20260210101157.2145113-1-vijayanand.jitta@oss.qualcomm.com/ V7: - Removed of_map_id_args structure and replaced it with of_phandle_args as suggested by Dmitry. Link to V6: https://lore.kernel.org/all/20260121055400.937856-1-vijayanand.jitta@oss.qualcomm.com/ V6: - Fixed build error reported by kernel test bot. Link to V5: https://lore.kernel.org/all/20260118181125.1436036-1-vijayanand.jitta@oss.qualcomm.com/ V5: - Fixed Build Warnings. - Raised PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184 Link to V4: https://lore.kernel.org/all/20251231114257.2382820-1-vijayanand.jitta@oss.qualcomm.com/ V4: - Added Reviewed-by tag. - Resolved warnings reported by kernel test bot, minor code reorganization. Link to V3: https://lore.kernel.org/all/20251221213602.2413124-1-vijayanand.jitta@oss.qualcomm.com/ V3: - Added Reviewed-by tag. - Updated of_map_id_args struct as a wrapper to of_phandle_args and added comment description as suggested by Rob Herring. Link to V2: https://lore.kernel.org/all/20251204095530.8627-1-vijayanand.jitta@oss.qualcomm.com/ V2: - Incorporated the patches from Robin that does the clean implementation. - Dropped the patches the were adding multi-map support from this series as suggested. V1: https://lore.kernel.org/all/cover.1762235099.git.charan.kalla@oss.qualcomm.com/ RFC: https://lore.kernel.org/all/20250928171718.436440-1-charan.kalla@oss.qualcomm.com/#r Signed-off-by: Vijayanand Jitta --- --- Charan Teja Kalla (1): of: Factor arguments passed to of_map_id() into a struct Robin Murphy (2): of: Add convenience wrappers for of_map_id() of: Respect #{iommu,msi}-cells in maps drivers/cdx/cdx_msi.c | 8 +- drivers/iommu/of_iommu.c | 6 +- drivers/irqchip/irq-gic-its-msi-parent.c | 11 +- drivers/of/base.c | 215 ++++++++++++++++++++++++------- drivers/of/irq.c | 11 +- drivers/pci/controller/dwc/pci-imx6.c | 34 +++-- drivers/pci/controller/pcie-apple.c | 6 +- drivers/xen/grant-dma-ops.c | 5 +- include/linux/of.h | 30 ++++- 9 files changed, 242 insertions(+), 84 deletions(-) --- base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31 change-id: 20260301-parse_iommu_cells-1c33768aebba Best regards, -- Vijayanand Jitta From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:03:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:03:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275579.1561364 (Exim 4.92) (envelope-from ) id 1wAPlP-00052U-Dg; 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This will also make it easier to then change of_map_id() to correctly account for specifier cells. Reviewed-by: Rob Herring (Arm) Reviewed-by: Frank Li Acked-by: Marc Zyngier Acked-by: Bjorn Helgaas Signed-off-by: Robin Murphy Signed-off-by: Vijayanand Jitta --- drivers/cdx/cdx_msi.c | 3 +-- drivers/iommu/of_iommu.c | 4 +--- drivers/irqchip/irq-gic-its-msi-parent.c | 2 +- drivers/of/base.c | 38 ++++++++++++++++++++++++++++++++ drivers/of/irq.c | 3 +-- drivers/pci/controller/dwc/pci-imx6.c | 6 ++--- drivers/pci/controller/pcie-apple.c | 3 +-- drivers/xen/grant-dma-ops.c | 3 +-- include/linux/of.h | 18 +++++++++++++++ 9 files changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 91b95422b263..63b3544ec997 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -128,8 +128,7 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_id(parent->of_node, cdx_dev->msi_dev_id, "msi-map", "msi-map-mask", - NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 6b989a62def2..a511ecf21fcd 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -48,9 +48,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct of_phandle_args iommu_spec = { .args_count = 1 }; int err; - err = of_map_id(master_np, *id, "iommu-map", - "iommu-map-mask", &iommu_spec.np, - iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index d36b278ae66c..b63343a227a9 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -180,7 +180,7 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u struct device_node *msi_ctrl __free(device_node) = NULL; - return of_map_id(dev->of_node, dev->id, "msi-map", "msi-map-mask", &msi_ctrl, dev_id); + return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index 57420806c1a2..ae04487bd614 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2201,3 +2201,41 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } EXPORT_SYMBOL_GPL(of_map_id); + +/** + * of_map_iommu_id - Translate an ID using "iommu-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the iommu-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_iommu_id); + +/** + * of_map_msi_id - Translate an ID using "msi-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the msi-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 6367c67732d2..e37c1b3f8736 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -817,8 +817,7 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_id(parent_dev->of_node, id_in, "msi-map", - "msi-map-mask", msi_np, &id_out)) + if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) break; if (!of_check_msi_parent(parent_dev->of_node, msi_np)) break; diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index a5b8d0b71677..bff8289f804a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1144,8 +1144,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) u32 sid = 0; target = NULL; - err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", - &target, &sid_i); + err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); if (target) { of_node_put(target); } else { @@ -1158,8 +1157,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) } target = NULL; - err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", - &target, &sid_m); + err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); /* * err_m target diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index 2d92fc79f6dd..a0937b7b3c4d 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -764,8 +764,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_id(port->pcie->dev->of_node, rid, "iommu-map", - "iommu-map-mask", NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); if (err) return err; diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index c2603e700178..1b7696b2d762 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -325,8 +325,7 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_id(np, rid, "iommu-map", "iommu-map-mask", &iommu_spec.np, - iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index be6ec4916adf..fe841f3cc747 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -465,6 +465,12 @@ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, struct device_node **target, u32 *id_out); +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); struct kimage; @@ -934,6 +940,18 @@ static inline int of_map_id(const struct device_node *np, u32 id, return -EINVAL; } +static inline int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return -EINVAL; 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Update all callers accordingly. Add an explicit filter_np parameter to of_map_id() and of_map_msi_id() to separate the filter input from the output. Previously, the target parameter served dual purpose: as an input filter (if non-NULL, only match entries targeting that node) and as an output (receiving the matched node with a reference held). Now filter_np is the explicit input filter and arg->np is the pure output. Previously, of_map_id() would call of_node_put() on the matched node when a filter was provided, making reference ownership inconsistent. Remove this internal of_node_put() call so that of_map_id() now always transfers ownership of the matched node reference to the caller via arg->np. Callers are now consistently responsible for releasing this reference with of_node_put(arg->np) when done. Acked-by: Frank Li Suggested-by: Rob Herring (Arm) Suggested-by: Dmitry Baryshkov Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta --- drivers/cdx/cdx_msi.c | 7 ++-- drivers/iommu/of_iommu.c | 4 +- drivers/irqchip/irq-gic-its-msi-parent.c | 11 ++++-- drivers/of/base.c | 68 +++++++++++++++++--------------- drivers/of/irq.c | 10 ++++- drivers/pci/controller/dwc/pci-imx6.c | 32 +++++++-------- drivers/pci/controller/pcie-apple.c | 5 ++- drivers/xen/grant-dma-ops.c | 4 +- include/linux/of.h | 14 ++++--- 9 files changed, 89 insertions(+), 66 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 63b3544ec997..6924e07c7528 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -121,22 +121,23 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, struct device *dev, int nvec, msi_alloc_info_t *info) { + struct of_phandle_args msi_spec = {}; struct cdx_device *cdx_dev = to_cdx_device(dev); struct device *parent = cdx_dev->cdx->dev; struct msi_domain_info *msi_info; - u32 dev_id; int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &msi_spec); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; } + of_node_put(msi_spec.np); #ifdef GENERIC_MSI_DOMAIN_OPS /* Set the device Id to be passed to the GIC-ITS */ - info->scratchpad[0].ul = dev_id; + info->scratchpad[0].ul = msi_spec.args[0]; #endif msi_info = msi_get_domain_info(msi_domain->parent); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index a511ecf21fcd..a18bb60f6f3d 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -45,10 +45,10 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct device *dev, const u32 *id) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; int err; - err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index b63343a227a9..dd5f84b6470a 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -152,6 +152,8 @@ static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev, static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u32 *dev_id, phys_addr_t *pa) { + struct device_node *msi_ctrl __free(device_node) = NULL; + struct of_phandle_args msi_spec = {}; struct of_phandle_iterator it; int ret; @@ -178,9 +180,12 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u } } - struct device_node *msi_ctrl __free(device_node) = NULL; - - return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); + ret = of_map_msi_id(dev->of_node, dev->id, NULL, &msi_spec); + if (!ret) { + msi_ctrl = msi_spec.np; + *dev_id = msi_spec.args[0]; + } + return ret; } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index ae04487bd614..b3d002015192 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2102,36 +2102,37 @@ int of_find_last_cache_level(unsigned int cpu) * @id: device ID to map. * @map_name: property name of the map to use. * @map_mask_name: optional property name of the mask to use. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional device node to filter matches by, or NULL to match any. + * If non-NULL, only map entries targeting this node will be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] will contain the translated ID. If a map entry was + * matched, @arg->np will be set to the target node with a reference + * held that the caller must release with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that - * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or - * @id_out may be NULL if only the other is required. If @target points to - * a non-NULL device node pointer, only entries targeting that node will be - * matched; if it points to a NULL value, it will receive the device node of - * the first matching target phandle, with a reference held. + * ID, as per the "iommu-map" and "msi-map" bindings. * * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; int map_len; const __be32 *map = NULL; - if (!np || !map_name || (!target && !id_out)) + if (!np || !map_name || !arg) return -EINVAL; map = of_get_property(np, map_name, &map_len); if (!map) { - if (target) + if (filter_np) return -ENODEV; /* Otherwise, no map implies no translation */ - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } @@ -2173,18 +2174,14 @@ int of_map_id(const struct device_node *np, u32 id, if (!phandle_node) return -ENODEV; - if (target) { - if (*target) - of_node_put(phandle_node); - else - *target = phandle_node; - - if (*target != phandle_node) - continue; + if (filter_np && filter_np != phandle_node) { + of_node_put(phandle_node); + continue; } - if (id_out) - *id_out = masked_id - id_base + out_base; + arg->np = phandle_node; + arg->args[0] = masked_id - id_base + out_base; + arg->args_count = 1; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", np, map_name, map_mask, id_base, out_base, @@ -2193,11 +2190,11 @@ int of_map_id(const struct device_node *np, u32 id, } pr_info("%pOF: no %s translation for id 0x%x on %pOF\n", np, map_name, - id, target && *target ? *target : NULL); + id, filter_np); /* Bypasses translation */ - if (id_out) - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2207,17 +2204,19 @@ EXPORT_SYMBOL_GPL(of_map_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); + return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2226,16 +2225,21 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the msi-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional MSI controller node to filter matches by, or NULL + * to match any. If non-NULL, only map entries targeting this node will + * be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); + return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index e37c1b3f8736..f86a56bd81fc 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -817,8 +817,16 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) + struct of_phandle_args msi_spec = {}; + + if (!of_map_msi_id(parent_dev->of_node, id_in, *msi_np, &msi_spec)) { + id_out = msi_spec.args[0]; + if (!*msi_np) + *msi_np = msi_spec.np; + else + of_node_put(msi_spec.np); break; + } if (!of_check_msi_parent(parent_dev->of_node, msi_np)) break; } diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bff8289f804a..c0544d9c0921 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1137,30 +1137,32 @@ static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) { + struct of_phandle_args iommu_spec = {}; + struct of_phandle_args msi_spec = {}; struct device *dev = imx_pcie->pci->dev; - struct device_node *target; u32 sid_i, sid_m; int err_i, err_m; u32 sid = 0; - target = NULL; - err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); - if (target) { - of_node_put(target); - } else { + err_i = of_map_iommu_id(dev->of_node, rid, &iommu_spec); + if (!err_i) + sid_i = iommu_spec.args[0]; + of_node_put(iommu_spec.np); + if (!err_i && !iommu_spec.np) { /* - * "target == NULL && err_i == 0" means RID out of map range. - * Use 1:1 map RID to streamID. Hardware can't support this - * because the streamID is only 6 bits + * "iommu_spec.np == NULL && err_i == 0" means RID out of map + * range. Use 1:1 map RID to streamID. Hardware can't support + * this because the streamID is only 6 bits. */ err_i = -EINVAL; } - target = NULL; - err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); - + err_m = of_map_msi_id(dev->of_node, rid, NULL, &msi_spec); + if (!err_m) + sid_m = msi_spec.args[0]; + of_node_put(msi_spec.np); /* - * err_m target + * err_m msi_spec.np * 0 NULL RID out of range. Use 1:1 map RID to * streamID, Current hardware can't * support it, so return -EINVAL. @@ -1168,10 +1170,8 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) * 0 != NULL Get correct streamID from RID * != 0 != NULL Invalid combination */ - if (!err_m && !target) + if (!err_m && !msi_spec.np) return -EINVAL; - else if (target) - of_node_put(target); /* Find streamID map entry for RID in msi-map */ /* * msi-map iommu-map diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index a0937b7b3c4d..c2cffc0659f4 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -755,6 +755,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d { u32 sid, rid = pci_dev_id(pdev); struct apple_pcie_port *port; + struct of_phandle_args iommu_spec = {}; int idx, err; port = apple_pcie_get_port(pdev); @@ -764,10 +765,12 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, &iommu_spec); if (err) return err; + of_node_put(iommu_spec.np); + sid = iommu_spec.args[0]; mutex_lock(&port->pcie->lock); idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0); diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index 1b7696b2d762..2aa1a772a0ff 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -319,13 +319,13 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct device_node *np, domid_t *backend_domid) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; if (dev_is_pci(dev)) { struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index fe841f3cc747..8548cd9eb4f1 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -463,13 +463,13 @@ bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + struct of_phandle_args *arg); int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); @@ -935,19 +935,21 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag static inline int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:04:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:04:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275597.1561382 (Exim 4.92) (envelope-from ) id 1wAPmM-0006E6-3U; Wed, 08 Apr 2026 10:04:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275597.1561382; Wed, 08 Apr 2026 10:04:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAPmM-0006Dz-0Z; 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Wed, 08 Apr 2026 03:04:14 -0700 (PDT) From: Vijayanand Jitta Date: Wed, 08 Apr 2026 15:33:27 +0530 Subject: [PATCH v13 3/3] of: Respect #{iommu,msi}-cells in maps MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260408-parse_iommu_cells-v13-3-fa921e92661b@oss.qualcomm.com> References: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com> In-Reply-To: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com> To: Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Saravana Kannan , Richard Zhu , Lucas Stach , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Prakash Gupta , Vikash Garodia Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Vijayanand Jitta , Charan Teja Kalla X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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This typically does happen to be the case, but is not actually enforced (and the PCI msi-map binding even explicitly states support for 0 or 1 cells) - as a result we've now ended up with dodgy DTs out in the field which depend on this behaviour to map a 1-cell specifier for a 2-cell provider, despite that being bogus per the bindings themselves. Since there is some potential use in being able to map at least single input IDs to multi-cell output specifiers (and properly support 0-cell outputs as well), add support for properly parsing and using the target nodes' #cells values, albeit with the unfortunate complication of still having to work around expectations of the old behaviour too. Since there are multi-cell output specifiers, the callers of of_map_id() may need to get the exact cell output value for further processing. Update of_map_id() to set args_count in the output to reflect the actual number of output specifier cells. Signed-off-by: Robin Murphy Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta --- drivers/of/base.c | 157 +++++++++++++++++++++++++++++++++++++++++------------ include/linux/of.h | 6 +- 2 files changed, 125 insertions(+), 38 deletions(-) diff --git a/drivers/of/base.c b/drivers/of/base.c index b3d002015192..2554e4f1a181 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu) return cache_level; } +/* + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while + * specifying only 1 cell. Fortunately they all consist of value '1' + * as the 2nd cell entry with the same target, so check for that pattern. + * + * Example: + * IOMMU node: + * #iommu-cells = <2>; + * + * Device node: + * iommu-map = <0x0000 &smmu 0x0000 0x1>, + * <0x0100 &smmu 0x0100 0x1>; + */ +static bool of_check_bad_map(const __be32 *map, int len) +{ + __be32 phandle = map[1]; + + if (len % 4) + return false; + for (int i = 0; i < len; i += 4) { + if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1)) + return false; + } + return true; +} + /** * of_map_id - Translate an ID through a downstream mapping. * @np: root complex device node. * @id: device ID to map. * @map_name: property name of the map to use. + * @cells_name: property name of target specifier cells. * @map_mask_name: optional property name of the mask to use. * @filter_np: optional device node to filter matches by, or NULL to match any. * If non-NULL, only map entries targeting this node will be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] will contain the translated ID. If a map entry was - * matched, @arg->np will be set to the target node with a reference - * held that the caller must release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * as defined by @cells_name in the target node, and + * @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np will be set + * to the target node with a reference held that the caller must release + * with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that @@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu) * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; - int map_len; + int map_bytes, map_len, offset = 0; + bool bad_map = false; const __be32 *map = NULL; if (!np || !map_name || !arg) return -EINVAL; - map = of_get_property(np, map_name, &map_len); + map = of_get_property(np, map_name, &map_bytes); if (!map) { if (filter_np) return -ENODEV; @@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } - if (!map_len || map_len % (4 * sizeof(*map))) { - pr_err("%pOF: Error: Bad %s length: %d\n", np, - map_name, map_len); - return -EINVAL; - } + if (map_bytes % sizeof(*map)) + goto err_map_len; + map_len = map_bytes / sizeof(*map); /* The default is to select all bits. */ map_mask = 0xffffffff; @@ -2153,39 +2183,84 @@ int of_map_id(const struct device_node *np, u32 id, of_property_read_u32(np, map_mask_name, &map_mask); masked_id = map_mask & id; - for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { + + while (offset < map_len) { struct device_node *phandle_node; - u32 id_base = be32_to_cpup(map + 0); - u32 phandle = be32_to_cpup(map + 1); - u32 out_base = be32_to_cpup(map + 2); - u32 id_len = be32_to_cpup(map + 3); + u32 id_base, phandle, id_len, id_off, cells = 0; + const __be32 *out_base; + + if (map_len - offset < 2) + goto err_map_len; + + id_base = be32_to_cpup(map + offset); if (id_base & ~map_mask) { - pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", - np, map_name, map_name, - map_mask, id_base); + pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n", + np, map_name, map_mask_name, map_mask, id_base); return -EFAULT; } - if (masked_id < id_base || masked_id >= id_base + id_len) - continue; - + phandle = be32_to_cpup(map + offset + 1); phandle_node = of_find_node_by_phandle(phandle); if (!phandle_node) return -ENODEV; + if (bad_map) { + cells = 1; + } else if (of_property_read_u32(phandle_node, cells_name, &cells)) { + pr_err("%pOF: missing %s property\n", phandle_node, cells_name); + of_node_put(phandle_node); + return -EINVAL; + } + + if (map_len - offset < 3 + cells) { + of_node_put(phandle_node); + goto err_map_len; + } + + if (offset == 0 && cells == 2) { + bad_map = of_check_bad_map(map, map_len); + if (bad_map) { + pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n", + np, map_name, cells_name); + cells = 1; + } + } + + out_base = map + offset + 2; + offset += 3 + cells; + + id_len = be32_to_cpup(map + offset - 1); + if (id_len > 1 && cells > 1) { + /* + * With 1 output cell we reasonably assume its value + * has a linear relationship to the input; with more, + * we'd need help from the provider to know what to do. + */ + pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n", + np, map_name, id_len, cells); + of_node_put(phandle_node); + return -EINVAL; + } + id_off = masked_id - id_base; + if (masked_id < id_base || id_off >= id_len) { + of_node_put(phandle_node); + continue; + } + if (filter_np && filter_np != phandle_node) { of_node_put(phandle_node); continue; } arg->np = phandle_node; - arg->args[0] = masked_id - id_base + out_base; - arg->args_count = 1; + for (int i = 0; i < cells; i++) + arg->args[i] = id_off + be32_to_cpu(out_base[i]); + arg->args_count = cells; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", - np, map_name, map_mask, id_base, out_base, - id_len, id, masked_id - id_base + out_base); + np, map_name, map_mask, id_base, be32_to_cpup(out_base), + id_len, id, id_off + be32_to_cpup(out_base)); return 0; } @@ -2196,6 +2271,10 @@ int of_map_id(const struct device_node *np, u32 id, arg->args[0] = id; arg->args_count = 1; return 0; + +err_map_len: + pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes); + return -EINVAL; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2205,18 +2284,21 @@ EXPORT_SYMBOL_GPL(of_map_id); * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells", + * and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); + return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2229,17 +2311,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * to match any. If non-NULL, only map entries targeting this node will * be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells", + * and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); + return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/include/linux/of.h b/include/linux/of.h index 8548cd9eb4f1..51ac8539f2c3 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur); bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, @@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag } static inline int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:21:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:21:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275628.1561391 (Exim 4.92) (envelope-from ) id 1wAQ21-0001FO-J4; Wed, 08 Apr 2026 10:21:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275628.1561391; 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arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Wed, 08 Apr 2026 12:21:07 +0200 From: Nicola Vetrini To: Andrew Cooper Cc: Michal Orzel , xen-devel@lists.xenproject.org, Julien Grall , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 0/2] Final series to make Arm MISRA allcode green In-Reply-To: <14185c87-84c0-4019-a3f6-50587b941350@citrix.com> References: <20260407103434.90838-1-michal.orzel@amd.com> <68cea196-efdc-4481-9e4b-bb450bcd2071@citrix.com> <14185c87-84c0-4019-a3f6-50587b941350@citrix.com> Message-ID: <7fbcb3d1ccdcf6fabb45f5805b504096@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775643668-5C9223D8-D77379F1/0/0 X-purgate-type: clean X-purgate-size: 1751 On 2026-04-08 11:51, Andrew Cooper wrote: > On 08/04/2026 10:46 am, Nicola Vetrini wrote: >> On 2026-04-08 11:22, Andrew Cooper wrote: >>> On 07/04/2026 11:34 am, Michal Orzel wrote: >>>> No more regressions for clean guidelines: >>>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >>>> >>>> Michal Orzel (2): >>>>   iommu/arm: smmu: Fix variable shadowing >>>>   iommu/arm: ipmmu-vmsa: Fix variable shadowing >>>> >>>>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >>>>  xen/drivers/passthrough/arm/smmu.c       | 7 +++---- >>>>  2 files changed, 5 insertions(+), 8 deletions(-) >>> >>> If all the violations are fixed, should this test be made blocking? >>> >>> ~Andrew >> >> Only if they are also clean on x86; otherwise an arm-specific list of >> clean rules should be made (probably better). @Michal what do you >> prefer? >> > > All I'm suggesting is this: > > xen.git/xen$ git diff > diff --git a/automation/gitlab-ci/analyze.yaml > b/automation/gitlab-ci/analyze.yaml > index 4e9af9d60224..f01798c5dee6 100644 > --- a/automation/gitlab-ci/analyze.yaml > +++ b/automation/gitlab-ci/analyze.yaml > @@ -149,7 +149,7 @@ eclair-ARM64-allcode: >        CONFIG_STACK_PROTECTOR=y >        CONFIG_UNSUPPORTED=y >        CONFIG_VM_EVENT=y > -  allow_failure: true > +  allow_failure: false >   >  eclair-ARM64-testing: >    extends: eclair-ARM64-allcode > > > so regressions become blocking. > > ~Andrew Ah, yes, indeed. I didn't look at the patches but given the diff it makes sense -- Nicola Vetrini, B.Sc. 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> > } > > > > +int __init dom0_check_parms( > > I understand the "dom0" in the name is owing to the filename and perhaps > adjacent other similar functions, yet ... > > > + struct domain *d, const struct elf_dom_parms *parms) > > +{ > > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) > > + return 0; > > + > > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) > > ... if this was about solely Dom0, no is_hardware_domain() should be present > here. Maybe s/dom0/initdom/ ? I think the naming of the feature flag is not very useful TBH. What is the kernel really advertising when setting XENFEAT_dom0? I've assumed it was the capability of running as a hardware domain, which requires a different set of functionality inside of the kernel to deal with hardware devices. We might want to take this opportunity to clarify in the headers what XENFEAT_dom0 means. Thanks, Roger. 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Wed, 08 Apr 2026 03:22:47 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 12:22:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie From: Jan Beulich Subject: [PATCH v10] x86emul: support LKGS Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775643767-1135C41E-FD4B9E4F/0/0 X-purgate-type: clean X-purgate-size: 9390 Provide support for this insn, which is a prereq to FRED. CPUID-wise, while its and FRED's enumerators were already introduced, their dependency still needs adding. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). I've also dropped the test harness read_segment() change. It generally would be correct to have, but isn't needed anymore with neither SWAPGS nor LKGS handling using the hook. --- v10: Drop FRED dependency on LKGS. Replace "best effort unwind". Avoid ->read_segment(). Re-base. v9: Re-base. v8: Re-base. v6: Use MSR constants in test harness. S->s in cpufeatureset.h. Add NMI_SRC feature bits. Re-base. v5: Re-base. v3: Add dependency on LM. Re-base. v2: Use X86_EXC_*. Add comments. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -673,6 +673,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt); } +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -682,8 +686,25 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p = 1; + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg == x86_seg_gs ) + gs_base = reg->base; + return X86EMUL_OKAY; } +#endif static int read_msr( unsigned int reg, @@ -696,6 +717,20 @@ static int read_msr( *val = ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; +#ifdef __x86_64__ + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val = gs_base; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val = gs_base_shadow; + return X86EMUL_OKAY; +#endif + case MSR_TSC_AUX: #define TSC_AUX_VALUE 0xCACACACA *val = TSC_AUX_VALUE; @@ -705,6 +740,32 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt, + bool explicit) +{ + switch ( reg ) + { + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base = val; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow = val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 @@ -1339,6 +1400,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment = write_segment; + emulops.write_msr = write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] = 0x0f; instr[1] = 0x01; instr[2] = 0xf8; + regs.eip = (unsigned long)&instr[0]; + gs_base = 0xffffeeeecccc8888UL; + gs_base_shadow = 0x0000111122224444UL; + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || + (regs.eip != (unsigned long)&instr[3]) || + (gs_base != 0x0000111122224444UL) || + (gs_base_shadow != 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] = 0xf2; instr[1] = 0x0f; instr[2] = 0x00; instr[3] = 0x72; instr[4] = 0x02; + regs.eip = (unsigned long)&instr[0]; + regs.edx = (unsigned long)res; + res[0] = 0x00004444; + res[1] = 0x8888cccc; + i = cpu_policy.extd.nscb; cpu_policy.extd.nscb = true; /* for AMD */ + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || + (regs.eip != (unsigned long)&instr[5]) || + (gs_base != 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cpu_policy.extd.nscb = i; + emulops.write_segment = NULL; + emulops.write_msr = NULL; #endif printf("okay\n"); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -85,6 +85,7 @@ bool emul_test_init(void) cpu_policy.feat.invpcid = true; cpu_policy.feat.adx = true; cpu_policy.feat.rdpid = true; + cpu_policy.feat.lkgs = true; cpu_policy.feat.wrmsrns = true; cpu_policy.extd.clzero = true; --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -744,8 +744,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |= DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |= SrcMem16; + s->desc |= SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -608,6 +608,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2899,8 +2899,37 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, X86_EXC_UD); + + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2, + X86_EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr); + if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) != X86EMUL_OKAY || + (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, + ctxt)) != X86EMUL_OKAY ) + goto done; + dst.orig_val = sreg.base; /* Preserve full GS Base. */ + if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg, + ctxt, ops)) != X86EMUL_OKAY ) + goto done; + /* Write (32-bit) base into SHADOW_GS. */ + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt, false)) != X86EMUL_OKAY || + (sreg.base = dst.orig_val, /* Reinstate full GS Base. */ + (rc = ops->write_segment(x86_seg_gs, &sreg, + ctxt)) != X86EMUL_OKAY) ) + { + /* + * In real hardware, access to the registers cannot fail. It + * is an error in Xen if the writes fail. + */ + ASSERT_UNREACHABLE(); + x86_emul_reset_event(ctxt); + generate_exception(X86_EXC_DF, 0); + } break; } break; --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -282,7 +282,8 @@ def crunch_numbers(state): # superpages, PCID and PKU are only available in 4 level paging. # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD], + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD, + LKGS], # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775644222-AED20CD1-3697A19D/0/0 X-purgate-type: clean X-purgate-size: 1513 On 08.04.2026 12:22, Roger Pau Monné wrote: > On Tue, Apr 07, 2026 at 08:56:03AM +0200, Jan Beulich wrote: >> On 02.04.2026 17:55, Frediano Ziglio wrote: >>> --- a/xen/arch/x86/dom0_build.c >>> +++ b/xen/arch/x86/dom0_build.c >>> @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, >>> return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); >>> } >>> >>> +int __init dom0_check_parms( >> >> I understand the "dom0" in the name is owing to the filename and perhaps >> adjacent other similar functions, yet ... >> >>> + struct domain *d, const struct elf_dom_parms *parms) >>> +{ >>> + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) >>> + return 0; >>> + >>> + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) >> >> ... if this was about solely Dom0, no is_hardware_domain() should be present >> here. Maybe s/dom0/initdom/ ? > > I think the naming of the feature flag is not very useful TBH. What > is the kernel really advertising when setting XENFEAT_dom0? I've > assumed it was the capability of running as a hardware domain, which > requires a different set of functionality inside of the kernel to deal > with hardware devices. Yes, that's my understanding. > We might want to take this opportunity to clarify in the headers what > XENFEAT_dom0 means. I'm not opposed, yet this isn't directly related to giving the function an appropriate name. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:38:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:38:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275669.1561428 (Exim 4.92) (envelope-from ) id 1wAQIb-0004pl-MQ; Wed, 08 Apr 2026 10:38:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275669.1561428; Wed, 08 Apr 2026 10:38:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQIb-0004pe-Jh; Wed, 08 Apr 2026 10:38:17 +0000 Received: by outflank-mailman (input) for mailman id 1275669; Wed, 08 Apr 2026 10:38:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQIa-0004pW-05 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 10:38:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAQIV-001bk2-U1 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:38:11 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d6300c-5cb7-0a2a0a5109dd-0a2a450c9eb8-22 for ; Wed, 08 Apr 2026 12:38:11 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d63012-f40c-0a2a450c0019-d98c6eacbd6a-1 for ; Wed, 08 Apr 2026 12:38:10 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E09153161; Wed, 8 Apr 2026 03:38:03 -0700 (PDT) Received: from [10.57.32.84] (unknown [10.57.32.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7F14B3F632; Wed, 8 Apr 2026 03:38:08 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775644689; bh=RbEAcqkGAzhWYYGDpNUfMtQ/+eT1N+kit4vG5ASyXOQ=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=N+msIMnXHv+BtqjbmyFmNQx/03MDaRVEtDG3zltALUtkZ6HtWowAYb6mAu7FhOGbe kFfe5JkjGOIVvtG2js3xVrqJymQgLWp0h3I89vgh5kitbjMOZa80e5iJiA72gC8ZYl 4eUrwpkPNnIEZpEdrGkPDGbiR2CBz6aN+prqL3t0= Message-ID: <756bcd3b-51c1-4ee4-bb09-4c0c0514764c@arm.com> Date: Wed, 8 Apr 2026 12:38:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: kernel BUG around vmap/vfree - xen_enter_lazy_mmu()/xen_leave_lazy_mmu() - Linux 7.0-rc1 To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= , Andrew Cooper , xen-devel , Boris Ostrovsky References: <5d068304-837d-4aef-b8a7-87c91ccf96b4@arm.com> From: Kevin Brodsky Content-Language: en-GB In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775644690-83F42A3D-C100407C/0/0 X-purgate-type: clean X-purgate-size: 5523 On 08/04/2026 04:47, Marek Marczykowski-Górecki wrote: >> That may well be the case - it seems that xen_enter_lazy_mmu() is called >> while already in lazy MMU mode (first splat), and xen_leave_lazy_mmu() >> is called without being in lazy MMU mode (second splat). I expect this >> is something specific to Xen, which I didn't get the chance to test. >> >> Looking at the series again I don't see anything obviously wrong, but I >> think the riskiest change is commit 291b3abed657 ("x86/xen: use >> lazy_mmu_state when context-switching") - worth trying to revert it. > With that reverted (on top of 7.0-rc6, didn't updated to rc7 yet), I > still got panic, although might be a bit different one: > > [ 8.099973] BUG: unable to handle page fault for address: ffff888008000670 > [ 8.100004] #PF: supervisor write access in kernel mode > [ 8.100021] #PF: error_code(0x0003) - permissions violation > [ 8.100037] PGD 3a00067 P4D 3a00067 PUD 3a01067 PMD 7cd7063 PTE 8000000008000021 > [ 8.100063] Oops: Oops: 0003 [#1] SMP PTI > [ 8.100079] CPU: 0 UID: 0 PID: 226 Comm: kworker/0:2 Not tainted 7.0.0-0.rc6.1.qubes.1001.fc41.x86_64 #1 PREEMPT(full) > [ 8.100110] Workqueue: events do_free_init > [ 8.100126] RIP: 0010:native_set_pte+0x4/0x10 > [ 8.100145] Code: 00 03 c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 f3 0f 1e fa <48> 89 37 c3 cc cc cc cc 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 > [ 8.100195] RSP: 0018:ffffc90000c97c48 EFLAGS: 00010287 > [ 8.100212] RAX: e00c4f3d8b48c03e RBX: ffff888008000670 RCX: e00000000000003e > [ 8.100234] RDX: e00c4f3d8b48c13e RSI: e00c4f3d8b48c03e RDI: ffff888008000670 > [ 8.100260] RBP: e00c4f3d8b48c13e R08: 0000000000000000 R09: 0000000000000001 > [ 8.100282] R10: 0000003b0c274b73 R11: e00000000000013e R12: ffffc90000c97cf0 > [ 8.100304] R13: ffffffffc04ce000 R14: fffc4f3d8b48cfff R15: e00000000000013e > [ 8.100327] FS: 0000000000000000(0000) GS:ffff888094e81000(0000) knlGS:0000000000000000 > [ 8.100350] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 8.100369] CR2: ffff888008000670 CR3: 000000000242e003 CR4: 00000000001706f0 > [ 8.100394] Call Trace: > [ 8.100404] > [ 8.100413] __change_page_attr+0x24f/0x350 > [ 8.100429] __change_page_attr_set_clr+0x61/0xd0 > [ 8.100446] change_page_attr_set_clr+0x103/0x1a0 > [ 8.100467] set_memory_nx+0x39/0x50 > [ 8.100481] __execmem_cache_free+0x35/0xb0 > [ 8.100496] execmem_free+0x9f/0x180 > [ 8.100510] ? nft_chain_nat_exit+0xe70/0xe70 [nft_chain_nat] > [ 8.100531] do_free_init+0x2e/0x60 > [ 8.100545] process_one_work+0x198/0x390 > [ 8.100559] worker_thread+0x1af/0x320 > [ 8.100573] ? __pfx_worker_thread+0x10/0x10 > [ 8.103338] kthread+0xe3/0x120 > [ 8.103355] ? __pfx_kthread+0x10/0x10 > [ 8.103369] ret_from_fork+0x19e/0x260 > [ 8.103384] ? __pfx_kthread+0x10/0x10 > [ 8.103397] ret_from_fork_asm+0x1a/0x30 > [ 8.103412] > [ 8.103421] Modules linked in: xenfs nft_reject_inet nf_reject_ipv4 nf_reject_ipv6 nft_reject nft_redir nft_ct nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 nf_tables binfmt_misc intel_rapl_msr intel_rapl_common ghash_clmulni_intel xen_netfront xen_privcmd xen_gntdev xen_gntalloc xen_blkback xen_evtchn fuse loop nfnetlink ip_tables overlay xen_blkfront > [ 8.103529] CR2: ffff888008000670 > [ 8.103542] ---[ end trace 0000000000000000 ]--- > [ 8.103558] RIP: 0010:native_set_pte+0x4/0x10 > [ 8.103576] Code: 00 03 c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 f3 0f 1e fa <48> 89 37 c3 cc cc cc cc 0f 1f 40 00 90 90 90 90 90 90 90 90 90 90 > [ 8.103625] RSP: 0018:ffffc90000c97c48 EFLAGS: 00010287 > [ 8.103641] RAX: e00c4f3d8b48c03e RBX: ffff888008000670 RCX: e00000000000003e > [ 8.103664] RDX: e00c4f3d8b48c13e RSI: e00c4f3d8b48c03e RDI: ffff888008000670 > [ 8.103686] RBP: e00c4f3d8b48c13e R08: 0000000000000000 R09: 0000000000000001 > [ 8.103708] R10: 0000003b0c274b73 R11: e00000000000013e R12: ffffc90000c97cf0 > [ 8.103730] R13: ffffffffc04ce000 R14: fffc4f3d8b48cfff R15: e00000000000013e > [ 8.103753] FS: 0000000000000000(0000) GS:ffff888094e81000(0000) knlGS:0000000000000000 > [ 8.103775] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 8.103794] CR2: ffff888008000670 CR3: 000000000242e003 CR4: 00000000001706f0 > [ 8.103820] Kernel panic - not syncing: Fatal exception > [ 8.103929] Kernel Offset: disabled That is probably the same root cause indeed (lazy MMU appearing disabled in __xet_set_pte() while it should be enabled). >> If >> that doesn't help, I'd suggest bisecting the following range: >> 58852f24f956..291b3abed657 > It will take some time, as the issue doesn't happen every time. Understood. Here are the commits that are expected to have a functional effect on x86 (in reverse chronological order): - 291b3abed657 ("x86/xen: use lazy_mmu_state when context-switching") - 5ab246749569 ("mm: enable lazy_mmu sections to nest") - 9273dfaeaca8 ("mm: bail out of lazy_mmu_mode_* in interrupt context") - 66bdd779d344 ("x86/xen: simplify flush_lazy_mmu()") Hope that helps, let me know if you have any further information. It would be worth enabling CONFIG_DEBUG_VM and then checking if any WARN() splat appears in the log. - Kevin From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:40:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:40:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275678.1561436 (Exim 4.92) (envelope-from ) id 1wAQKN-0006T9-0Q; Wed, 08 Apr 2026 10:40:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275678.1561436; Wed, 08 Apr 2026 10:40:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQKM-0006T2-U4; Wed, 08 Apr 2026 10:40:06 +0000 Received: by outflank-mailman (input) for mailman id 1275678; Wed, 08 Apr 2026 10:40:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQKM-0006LU-2Z for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KY5/pArWC7EIPmuBUMuvKaE7JdvSJmw7RWf9I+27LGVu4KMYebcOEX1mqbrO1A2f/FEApb54i4iKIukw45nnXbHsJ8UsOxjMMHMFeXYZzjfM5Ui7eueqPCaASuFjmkqdwMPdZxixNWI5zjDQGFaRLzyqUiRJ1nf1+bGy+8thuZkW6m16pha57LZEyPQh9JQG0qzClsya+wvGzrFXt7joG4l5Gsvk1OxP5vaG2yHrTYRO++ColT3MR4/HE0n0eclqaqSk4HoWusgAprlSqIQO9jjsjgGNs/CGwTKvm3xtTuISoWg8OBdQ9Uk5TpLRQkCQorJrbgVUZJq6Ps+42ZypgsvVkfq8ndpenZYGf7Kq5oFJLXptr9ii/00hTYfupy2qKNncQcgYE9zMfCd/JYlPZUckesngM9jUMZzL4NyuXTDTRHBHJB4Jy7zSIN23SgIY X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 10:37:55.1649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28cbb902-b975-40a8-26fb-08de955ae4d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8333 X-purgate-ID: tlsNG-c201ff/1775644684-3133496F-4CF43354/0/0 X-purgate-type: clean X-purgate-size: 1983 On 08/04/2026 12:21, Nicola Vetrini wrote: > On 2026-04-08 11:51, Andrew Cooper wrote: >> On 08/04/2026 10:46 am, Nicola Vetrini wrote: >>> On 2026-04-08 11:22, Andrew Cooper wrote: >>>> On 07/04/2026 11:34 am, Michal Orzel wrote: >>>>> No more regressions for clean guidelines: >>>>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >>>>> >>>>> Michal Orzel (2): >>>>>   iommu/arm: smmu: Fix variable shadowing >>>>>   iommu/arm: ipmmu-vmsa: Fix variable shadowing >>>>> >>>>>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >>>>>  xen/drivers/passthrough/arm/smmu.c       | 7 +++---- >>>>>  2 files changed, 5 insertions(+), 8 deletions(-) >>>> >>>> If all the violations are fixed, should this test be made blocking? >>>> >>>> ~Andrew >>> >>> Only if they are also clean on x86; otherwise an arm-specific list of >>> clean rules should be made (probably better). @Michal what do you >>> prefer? >>> >> >> All I'm suggesting is this: >> >> xen.git/xen$ git diff >> diff --git a/automation/gitlab-ci/analyze.yaml >> b/automation/gitlab-ci/analyze.yaml >> index 4e9af9d60224..f01798c5dee6 100644 >> --- a/automation/gitlab-ci/analyze.yaml >> +++ b/automation/gitlab-ci/analyze.yaml >> @@ -149,7 +149,7 @@ eclair-ARM64-allcode: >>        CONFIG_STACK_PROTECTOR=y >>        CONFIG_UNSUPPORTED=y >>        CONFIG_VM_EVENT=y >> -  allow_failure: true >> +  allow_failure: false >>   >>  eclair-ARM64-testing: >>    extends: eclair-ARM64-allcode >> >> >> so regressions become blocking. >> >> ~Andrew > > Ah, yes, indeed. I didn't look at the patches but given the diff it > makes sense In general that's a good idea and something I had in mind. That said, we will likely be expanding the list of enabled features there as soon as one arrives. What should we do in that case? Make sure that before adding new =y option, the allcode passes in our Xen fork? ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:53:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:53:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275691.1561446 (Exim 4.92) (envelope-from ) id 1wAQXK-0008Pr-4N; Wed, 08 Apr 2026 10:53:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275691.1561446; Wed, 08 Apr 2026 10:53:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQXK-0008Pk-1R; Wed, 08 Apr 2026 10:53:30 +0000 Received: by outflank-mailman (input) for mailman id 1275691; Wed, 08 Apr 2026 10:53:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 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citrix.com X-MS-Exchange-CrossTenant-Network-Message-Id: 13586c6a-7f8e-45fe-7c02-08de955b84ce X-MS-Exchange-CrossTenant-AuthSource: CH8PR03MB8275.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 10:42:23.7700 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: X+MpSR6QXjkX/jgm10LOUYbmirYUNe+wdqN/OrXfcSt2YNChy4VoxUXeEUwmhkQGYXofqvSEUZ5ZwYY0goEErxckE7BR0Mu6xubnvLrvWfc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR03MB6520 X-purgate-ID: tlsNG-720697/1775644947-44BF5CD1-9FBAF00D/13/0 X-purgate-type: clean X-purgate-size: 2197 On 08/04/2026 11:36 am, Orzel, Michal wrote: > > On 08/04/2026 12:21, Nicola Vetrini wrote: >> On 2026-04-08 11:51, Andrew Cooper wrote: >>> On 08/04/2026 10:46 am, Nicola Vetrini wrote: >>>> On 2026-04-08 11:22, Andrew Cooper wrote: >>>>> On 07/04/2026 11:34 am, Michal Orzel wrote: >>>>>> No more regressions for clean guidelines: >>>>>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >>>>>> >>>>>> Michal Orzel (2): >>>>>>   iommu/arm: smmu: Fix variable shadowing >>>>>>   iommu/arm: ipmmu-vmsa: Fix variable shadowing >>>>>> >>>>>>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >>>>>>  xen/drivers/passthrough/arm/smmu.c       | 7 +++---- >>>>>>  2 files changed, 5 insertions(+), 8 deletions(-) >>>>> If all the violations are fixed, should this test be made blocking? >>>>> >>>>> ~Andrew >>>> Only if they are also clean on x86; otherwise an arm-specific list of >>>> clean rules should be made (probably better). @Michal what do you >>>> prefer? >>>> >>> All I'm suggesting is this: >>> >>> xen.git/xen$ git diff >>> diff --git a/automation/gitlab-ci/analyze.yaml >>> b/automation/gitlab-ci/analyze.yaml >>> index 4e9af9d60224..f01798c5dee6 100644 >>> --- a/automation/gitlab-ci/analyze.yaml >>> +++ b/automation/gitlab-ci/analyze.yaml >>> @@ -149,7 +149,7 @@ eclair-ARM64-allcode: >>>        CONFIG_STACK_PROTECTOR=y >>>        CONFIG_UNSUPPORTED=y >>>        CONFIG_VM_EVENT=y >>> -  allow_failure: true >>> +  allow_failure: false >>>   >>>  eclair-ARM64-testing: >>>    extends: eclair-ARM64-allcode >>> >>> >>> so regressions become blocking. >>> >>> ~Andrew >> Ah, yes, indeed. I didn't look at the patches but given the diff it >> makes sense > In general that's a good idea and something I had in mind. That said, we will > likely be expanding the list of enabled features there as soon as one arrives. > What should we do in that case? Make sure that before adding new =y option, the > allcode passes in our Xen fork? New code could be clean as it goes in.  At this point, it's not interestingly different from "does it compile" as a prerequisite. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 10:58:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 10:58:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275702.1561455 (Exim 4.92) (envelope-from ) id 1wAQc4-0000tG-OC; Wed, 08 Apr 2026 10:58:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275702.1561455; Wed, 08 Apr 2026 10:58:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAQc4-0000t9-Kx; Wed, 08 Apr 2026 10:58:24 +0000 Received: by outflank-mailman (input) for mailman id 1275702; Wed, 08 Apr 2026 10:58:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wAQc3-0000t3-MG for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 10:58:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAQc3-001evq-2F for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:58:23 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d634c6-e002-0a2a0a5209dd-0a2a450bdbdc-12 for ; Wed, 08 Apr 2026 12:58:23 +0200 Received: from [209.85.208.53] (helo=mail-ed1-f53.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d634ce-bca8-0a2a450b0019-d155d035ed88-3 for ; Wed, 08 Apr 2026 12:58:23 +0200 Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-66e129e457dso6094764a12.1 for ; Wed, 08 Apr 2026 03:58:22 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Them going slightly beyond 80 columns is okay. > Them going much beyond that is a good indication that you want to consider re- > wording. (Here e.g. "SSTC detected; supported for Xen use, but not for guests".) I will reword log message in the form you suggested. > > I question though whether something like this needs logging. It is just a debug reminder that something should be additionally done. I will do it dprintk() so it won't appear in release builds. > >> + /* >> + * As SSTC for guest isn't supported it is needed temprorary to: > > Nit: temporary > >> + * >> + * 1. Clear bit RISCV_ISA_EXT_sstc in riscv_isa as theoretuically it > > Nit: theoretically > >> + * could be that OpenSBI (it doesn't pass it now) or whatever ran >> + * before Xen will add SSTC to riscv,isa string. This bit clear >> + * won't allow guest to use SSTC extension as vtimer context >> + * switch and restore isn't ready for that. >> + */ >> + __clear_bit(RISCV_ISA_EXT_sstc, riscv_isa); > > Seeing your other series, shouldn't this instead be done without affecting > riscv_isa? The BUG_ON()s in vtimer.x therefore also look inappropriate. It is incorrect to use __clear_bit(). What should be used instead is __set_bit(), because in the current boot process OpenSBI does not add "sstc" to the riscv,isa string. Therefore, we need to set the RISCV_ISA_EXT_sstc bit manually. This change will affect BUG_ON() checks in vtimer.c, which I plan to remove. If SSTC is not supported for the guest, there is nothing we can do anyway. It might make sense to reintroduce these BUG_ON() checks once an unsupported bitmap is implemented [1]. At that point, we could have something like the following in the vtimer save and restore context functions in vtimer.c: BUG_ON(!riscv_isa_extension_available(guest_unsupp_bmp, RISCV_ISA_EXT_sstc)); On the other hand, using BUG_ON() in the vtimer save and restore functions is of limited value. If SSTC support for guests is added in the future, these functions will need to be updated anyway, so such checks may become redundant. [1] https://lore.kernel.org/xen-devel/007c0a0243ac7ff1d1ab3faa4ebcdd6fcd14e485.1773157782.git.oleksii.kurochko@gmail.com/ > >> @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) >> if ( deadline <= now ) >> return 0; >> >> - /* >> - * TODO: When the SSTC extension is supported, it would be preferable to >> - * use the supervisor timer registers directly here for better >> - * performance, since an SBI call and mode switch would no longer >> - * be required. >> - * >> - * This would also reduce reliance on a specific SBI implementation. >> - * For example, it is not ideal to panic() if sbi_set_timer() returns >> - * a non-zero value. Currently it can return 0 or -ENOSUPP, and >> - * without SSTC we still need an implementation because only the >> - * M-mode timer is available, and it can only be programmed in >> - * M-mode. >> - */ >> - if ( (rc = sbi_set_timer(deadline)) ) >> + if ( (rc = set_xen_timer(deadline)) ) >> panic("%s: timer wasn't set because: %d\n", __func__, rc); >> >> /* Enable timer interrupt */ >> @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) >> >> void __init preinit_xen_time(void) >> { >> + unsigned long tmp; >> + >> if ( acpi_disabled ) >> preinit_dt_xen_time(); >> else >> panic("%s: ACPI isn't supported\n", __func__); >> >> boot_clock_cycles = get_cycles(); >> + >> + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) >> + set_xen_timer = sstc_set_xen_timer; >> + else >> + set_xen_timer = sbi_set_timer; >> } > > Doesn't all of this together eliminate the need for sbi_set_timer as a > separate global variable? There's still a need for that SBI-level dispatch. However, sbi_set_timer doesn't need to be a global variable (exported from sbi.h). Since the only external user after this patch is the time.c, sbi_set_timer could be refactored into a plain static internal pointer with a non-static wrapper function: // sbi.c — keep dispatch internal static int (* __ro_after_init sbi_set_timer_fn)(uint64_t) = sbi_set_timer_v01; int cf_check sbi_set_timer(uint64_t stime_value) { return sbi_set_timer_fn(stime_value); } Do you mean this? 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pr=C Message-ID: <1b0e5252-f28c-425e-b982-f023f8976ec4@amd.com> Date: Wed, 8 Apr 2026 13:01:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] Final series to make Arm MISRA allcode green To: Andrew Cooper , Nicola Vetrini CC: , Julien Grall , "Rahul Singh" , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260407103434.90838-1-michal.orzel@amd.com> <68cea196-efdc-4481-9e4b-bb450bcd2071@citrix.com> <14185c87-84c0-4019-a3f6-50587b941350@citrix.com> <7fbcb3d1ccdcf6fabb45f5805b504096@bugseng.com> <18ab9849-f525-46cf-a244-d8125bef1655@amd.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004687:EE_|CY3PR12MB9580:EE_ X-MS-Office365-Filtering-Correlation-Id: 856d90d5-a1ab-49c7-b5ae-08de955e2ba8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2HWXbgsXwKIBwG+PWe2tJw+HXT52QkbsLBn+Gz3Qb/mXD2vRTpU7jIa4CN3G9DO3VaF8KbxgeKaqE7A0kOdcvOMCIWu1QyCe3wS8C5NNypjFArQVy2l2HslRhfXlvlycIroeg9yvQqkBHiPzOUIwQy6q2l+m5N7/OOqDrMGP1yhQXpi5nshbomlmVluQW9nCHkopkHdV7oRE0S6O2pPVZ6SIrwB/lsNBicGsAGYL2fKFH3RmFL1y1uLpbu70n/wXUHsVF/9z9yZiyzdwssc4CD15BrFvcDwbFUW1sZeSOtTixmfPyk0L4PDu7TFXEUQPkunU6kD6J4VJvylXSSLhDH8ZHHGehB3d0PVrcbvqgqJU0/ycnHpciukgqx6uf6FClXV0/IFOWP3dryK6/QyElgdA3kiI5DOna8Iokyv8+h7t/4etn3pQGUIyyfdo03Fy X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 11:01:22.4710 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 856d90d5-a1ab-49c7-b5ae-08de955e2ba8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9580 X-purgate-ID: tlsNG-d25034/1775646086-FD358A3D-5A7C1E0E/0/0 X-purgate-type: clean X-purgate-size: 2565 On 08/04/2026 12:42, Andrew Cooper wrote: > On 08/04/2026 11:36 am, Orzel, Michal wrote: >> >> On 08/04/2026 12:21, Nicola Vetrini wrote: >>> On 2026-04-08 11:51, Andrew Cooper wrote: >>>> On 08/04/2026 10:46 am, Nicola Vetrini wrote: >>>>> On 2026-04-08 11:22, Andrew Cooper wrote: >>>>>> On 07/04/2026 11:34 am, Michal Orzel wrote: >>>>>>> No more regressions for clean guidelines: >>>>>>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2433943072 >>>>>>> >>>>>>> Michal Orzel (2): >>>>>>>   iommu/arm: smmu: Fix variable shadowing >>>>>>>   iommu/arm: ipmmu-vmsa: Fix variable shadowing >>>>>>> >>>>>>>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++---- >>>>>>>  xen/drivers/passthrough/arm/smmu.c       | 7 +++---- >>>>>>>  2 files changed, 5 insertions(+), 8 deletions(-) >>>>>> If all the violations are fixed, should this test be made blocking? >>>>>> >>>>>> ~Andrew >>>>> Only if they are also clean on x86; otherwise an arm-specific list of >>>>> clean rules should be made (probably better). @Michal what do you >>>>> prefer? >>>>> >>>> All I'm suggesting is this: >>>> >>>> xen.git/xen$ git diff >>>> diff --git a/automation/gitlab-ci/analyze.yaml >>>> b/automation/gitlab-ci/analyze.yaml >>>> index 4e9af9d60224..f01798c5dee6 100644 >>>> --- a/automation/gitlab-ci/analyze.yaml >>>> +++ b/automation/gitlab-ci/analyze.yaml >>>> @@ -149,7 +149,7 @@ eclair-ARM64-allcode: >>>>        CONFIG_STACK_PROTECTOR=y >>>>        CONFIG_UNSUPPORTED=y >>>>        CONFIG_VM_EVENT=y >>>> -  allow_failure: true >>>> +  allow_failure: false >>>>   >>>>  eclair-ARM64-testing: >>>>    extends: eclair-ARM64-allcode >>>> >>>> >>>> so regressions become blocking. >>>> >>>> ~Andrew >>> Ah, yes, indeed. I didn't look at the patches but given the diff it >>> makes sense >> In general that's a good idea and something I had in mind. That said, we will >> likely be expanding the list of enabled features there as soon as one arrives. >> What should we do in that case? Make sure that before adding new =y option, the >> allcode passes in our Xen fork? > > New code could be clean as it goes in.  At this point, it's not > interestingly different from "does it compile" as a prerequisite. I can see there are some missing features like static memory/shared memory but they are tested as part of AMD (it would still be good to have all listed in allcode). Additionally, we could enable early printk with some dummy values to cover early_printk.c ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 08 11:27:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 11:27:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275749.1561490 (Exim 4.92) (envelope-from ) id 1wAR4G-0006WE-Fi; Wed, 08 Apr 2026 11:27:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275749.1561490; Wed, 08 Apr 2026 11:27:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAR4G-0006W7-BV; Wed, 08 Apr 2026 11:27:32 +0000 Received: by outflank-mailman (input) for mailman id 1275749; Wed, 08 Apr 2026 11:27:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAR4F-0006Vz-6b for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 11:27:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAR4E-005guk-Io for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:27:30 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d63b91-bab6-0a2a0a5309dd-0a2a450ca434-46 for ; Wed, 08 Apr 2026 13:27:30 +0200 Received: from [209.85.221.54] (helo=mail-wr1-f54.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d63b2a-f40c-0a2a450c0019-d155dd36d1e1-3 for ; Wed, 08 Apr 2026 13:25:30 +0200 Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-43cfde3c3f3so5923938f8f.3 for ; Wed, 08 Apr 2026 04:25:30 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775647530-FDD53A3D-800E6822/0/0 X-purgate-type: clean X-purgate-size: 2574 On 08.04.2026 12:58, Oleksii Kurochko wrote: > On 4/2/26 8:41 AM, Jan Beulich wrote: >> On 31.03.2026 21:04, Oleksii Kurochko wrote: >>> @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) >>> if ( deadline <= now ) >>> return 0; >>> >>> - /* >>> - * TODO: When the SSTC extension is supported, it would be preferable to >>> - * use the supervisor timer registers directly here for better >>> - * performance, since an SBI call and mode switch would no longer >>> - * be required. >>> - * >>> - * This would also reduce reliance on a specific SBI implementation. >>> - * For example, it is not ideal to panic() if sbi_set_timer() returns >>> - * a non-zero value. Currently it can return 0 or -ENOSUPP, and >>> - * without SSTC we still need an implementation because only the >>> - * M-mode timer is available, and it can only be programmed in >>> - * M-mode. >>> - */ >>> - if ( (rc = sbi_set_timer(deadline)) ) >>> + if ( (rc = set_xen_timer(deadline)) ) >>> panic("%s: timer wasn't set because: %d\n", __func__, rc); >>> >>> /* Enable timer interrupt */ >>> @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) >>> >>> void __init preinit_xen_time(void) >>> { >>> + unsigned long tmp; >>> + >>> if ( acpi_disabled ) >>> preinit_dt_xen_time(); >>> else >>> panic("%s: ACPI isn't supported\n", __func__); >>> >>> boot_clock_cycles = get_cycles(); >>> + >>> + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) >>> + set_xen_timer = sstc_set_xen_timer; >>> + else >>> + set_xen_timer = sbi_set_timer; >>> } >> >> Doesn't all of this together eliminate the need for sbi_set_timer as a >> separate global variable? > There's still a need for that SBI-level dispatch. However, sbi_set_timer > doesn't need to be a global variable (exported from sbi.h). Since the > only external user after this patch is the time.c, sbi_set_timer could > be refactored into a plain static internal pointer with a non-static > wrapper function: > > // sbi.c — keep dispatch internal > static int (* __ro_after_init sbi_set_timer_fn)(uint64_t) = > sbi_set_timer_v01; > > int cf_check sbi_set_timer(uint64_t stime_value) > { > return sbi_set_timer_fn(stime_value); > } > > Do you mean this? No. Why is it that we'd still need both set_xen_timer and sbi_set_timer as distinct variables? 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CPUID-wise, > while its and FRED's enumerators were already introduced, their dependency > still needs adding. > > While adding a testcase, also add a SWAPGS one. In order to not affect > the behavior of pre-existing tests, install write_{segment,msr} hooks > only transiently. > > Signed-off-by: Jan Beulich > --- > For PV save_segments() would need adjustment, Not really.  CPL3 must never have a way of modifying GS_KERN, hence ... > but the insn being restricted to ring 0 means PV guests can't use it anyway ... the CPL0 restriction. Arguably I should have had this in one of the FRED patches: diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1151997758c6..3364e774ada7 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1952,7 +1952,7 @@ static void load_segments(struct vcpu *n)   * changes to bases can also be made with the WR{FS,GS}BASE instructions, when   * enabled.   * - * Guests however cannot use SWAPGS, so there is no mechanism to modify the + * Guests cannot use SWAPGS or LKGS, so there is no mechanism to modify the   * inactive GS base behind Xen's back.  Therefore, Xen's copy of the inactive   * GS base is still accurate, and doesn't need reading back from hardware.   * but I don't think it's appropriate to merge into this patch. > (unless we wanted to emulate it as another privileged insn). We already have "LKGS" in hypercall form.  It's spelt SEGBASE_GS_USER_SEL and has existed for 20 years or so. I don't see any reason to extend emul_priv_op(). > > I've also dropped the test harness read_segment() change. It generally > would be correct to have, but isn't needed anymore with neither SWAPGS > nor LKGS handling using the hook. Dropping read_segment() makes your patch depend on Teddy's, now that test_x86_emulator is blocking in CI. This matters for backports.  I expect I'll be backporting guest support in not-too-long. > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -2899,8 +2899,37 @@ x86_emulate( > break; > } > break; > - default: > - generate_exception_if(true, X86_EXC_UD); > + > + case 6: /* lkgs */ > + generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2, > + X86_EXC_UD); > + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD); > + vcpu_must_have(lkgs); > + fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr); > + if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, > + ctxt)) != X86EMUL_OKAY || > + (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, > + ctxt)) != X86EMUL_OKAY ) > + goto done; > + dst.orig_val = sreg.base; /* Preserve full GS Base. */ "Preserve current GS Base." > + if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg, > + ctxt, ops)) != X86EMUL_OKAY ) > + goto done; > + /* Write (32-bit) base into SHADOW_GS. */ "Write new base into SHADOW_GS.  Zero extended from GDT/LDT." > + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, > + ctxt, false)) != X86EMUL_OKAY || > + (sreg.base = dst.orig_val, /* Reinstate full GS Base. */ "Reinstate original GS base." > + (rc = ops->write_segment(x86_seg_gs, &sreg, > + ctxt)) != X86EMUL_OKAY) ) > + { > + /* > + * In real hardware, access to the registers cannot fail. It > + * is an error in Xen if the writes fail. > + */ > + ASSERT_UNREACHABLE(); > + x86_emul_reset_event(ctxt); > + generate_exception(X86_EXC_DF, 0); > + } > break; > } > break; This patch needs one more hunk: diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae435..9d8195e2ae56 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -765,14 +765,25 @@ static void __init calculate_hvm_max_policy(void)       */      __set_bit(X86_FEATURE_NO_LMSL, fs);   -    /* -     * On AMD, PV guests are entirely unable to use SYSENTER as Xen runs in -     * long mode (and init_amd() has cleared it out of host capabilities), but -     * HVM guests are able if running in protected mode. -     */ -    if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && -         raw_cpu_policy.basic.sep ) -        __set_bit(X86_FEATURE_SEP, fs); +    if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) +    { +        /* +         * On AMD, PV guests are unable to use SYSENTER as Xen runs in long +         * mode (and init_amd() has cleared it out of host capabilities), but +         * HVM guests are able if running in protected mode. +         */ +        if ( raw_cpu_policy.basic.sep ) +            __set_bit(X86_FEATURE_SEP, fs); + +        /* +         * NullSelectorClearsBase is really a "hardware doesn't have this bug +         * any more" bit.  All FRED-capable hardware has NSCB properties, so +         * disallow a configuration which suggest/causes behaviour the OS isn't +         * expecting. +         */ +        if ( !test_bit(X86_FEATURE_NSCB, fs) ) +            __clear_bit(X86_FEATURE_LKGS, fs); +    }        /*       * VIRT_SSBD is exposed in the default policy as a result of because otherwise a CPU Policy could hide NCSB and LKGS would be have correctly when executed normally but malfunction in the emulator. This hunk is in lieu of having vendor-dependent deep-deps calculations, although it would need duplicating in userspace too. Because this is only a link between an AMD-only feature and a common feature, I think I can express it by only having a per-vendor deep_features bitmap and keeping a shared deep_deps matrix. Perhaps I should prototype that instead, but it would become another dependency for this patch. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 11:34:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 11:34:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275787.1561506 (Exim 4.92) (envelope-from ) id 1wARBH-0000WN-ET; Wed, 08 Apr 2026 11:34:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275787.1561506; Wed, 08 Apr 2026 11:34:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARBH-0000WG-Ba; Wed, 08 Apr 2026 11:34:47 +0000 Received: by outflank-mailman (input) for mailman id 1275787; Wed, 08 Apr 2026 11:34:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARBF-0000Un-OR for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 11:34:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARBF-009oGY-43 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:34:45 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d63d4e-bab6-0a2a0a5309dd-0a2a45039f58-48 for ; Wed, 08 Apr 2026 13:34:44 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d63d54-02b3-0a2a45030019-d1558036e0be-3 for ; Wed, 08 Apr 2026 13:34:44 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so50984305e9.2 for ; Wed, 08 Apr 2026 04:34:44 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 04:34:44 -0700 (PDT) Message-ID: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> Date: Wed, 8 Apr 2026 13:34:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Marek Marczykowski From: Jan Beulich Subject: [PATCH] x86/cpuidle: split the max_cstate variable Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775648084-42B1DC9A-06BB0736/0/0 X-purgate-type: clean X-purgate-size: 12120 The admin can control the upper bound wanted not only via command line option, but also via XEN_SYSCTL_pm_op_set_max_cstate. While decisions how to set up the system are okay this way as long as we deem the command line option a strict upper bound, what to do during S3 resume should not be based on that potentially varying value. Decisions there need to use solely the strict upper bound we may have enforced ourselves (or which was forced onto us via command line option). Rather than altering pit_broadcast_is_available(), drop the function altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just for that to call into acpi/cpu_idle.c again. Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits") Signed-off-by: Jan Beulich --- cpuidle_disable_deep_cstate(), when called from handle_rtc_once(), is still somewhat of a problem: Boot time and resume time runs of _disable_pit_irq() may still behave differently because of that. If we wanted the sysctl to possibly move the maximum C-state beyond what was given on the command line, things would get yet more complicated, as we'd then need to re-configure the driver that's in use. I wonder how useful the ACPI_STATE_C #define-s really are. Plain 1 is used in e.g. probe_c3_errata(), and the plain 7 doesn't even have a respective constant (nor would that be suitable, as that's not really an ACPI state). --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -119,7 +119,7 @@ bool lapic_timer_init(void) lapic_timer_off = hpet_broadcast_enter; lapic_timer_on = hpet_broadcast_exit; } - else if ( pit_broadcast_is_available() ) + else if ( cpuidle_usable_deep_cstate() ) { lapic_timer_off = pit_broadcast_enter; lapic_timer_on = pit_broadcast_exit; @@ -131,12 +131,15 @@ bool lapic_timer_init(void) } void (*__read_mostly pm_idle_save)(void); -unsigned int max_cstate __read_mostly = UINT_MAX; + +unsigned int max_usable_cstate __read_mostly = UINT_MAX; +unsigned int max_allowed_cstate __read_mostly = UINT_MAX; unsigned int max_csubstate __read_mostly = UINT_MAX; static int __init cf_check parse_cstate(const char *s) { - max_cstate = simple_strtoul(s, &s, 0); + max_allowed_cstate = simple_strtoul(s, &s, 0); + max_usable_cstate = max_allowed_cstate; if ( *s == ',' ) max_csubstate = simple_strtoul(s + 1, NULL, 0); return 0; @@ -413,10 +416,11 @@ static void cf_check dump_cx(unsigned ch unsigned int cpu; printk("'%c' pressed -> printing ACPI Cx structures\n", key); - if ( max_cstate < UINT_MAX ) + if ( max_cstate() < UINT_MAX ) { - printk("max state: C%u\n", max_cstate); - if ( max_csubstate < UINT_MAX ) + printk("max state: C%u\n", max_cstate()); + if ( max_allowed_cstate <= max_usable_cstate && + max_csubstate < UINT_MAX ) printk("max sub-state: %u\n", max_csubstate); else printk("max sub-state: unlimited\n"); @@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle u32 exp = 0, pred = 0; u32 irq_traced[4] = { 0 }; - if ( max_cstate > 0 && power && + if ( max_cstate() > 0 && power && (next_state = cpuidle_current_governor->select(power)) > 0 ) { unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 - : max_cstate; + : max_cstate(); do { cx = &power->states[next_state]; } while ( (cx->type > max_state || cx->entry_method == ACPI_CSTATE_EM_NONE || (cx->entry_method == ACPI_CSTATE_EM_FFH && - cx->type == max_cstate && + cx->type == max_allowed_cstate && (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) && --next_state ); if ( next_state ) @@ -1448,7 +1452,7 @@ static void amd_cpuidle_init(struct acpi for ( i = 0; i < nr; ++i ) { - if ( cx[i].type > max_cstate ) + if ( cx[i].type > max_cstate() ) break; power->states[i + 1] = cx[i]; power->states[i + 1].idx = i + 1; @@ -1611,21 +1615,22 @@ int pmstat_reset_cx_stat(unsigned int cp void cpuidle_disable_deep_cstate(void) { - if ( max_cstate > ACPI_STATE_C1 ) + if ( max_usable_cstate > ACPI_STATE_C1 ) { if ( local_apic_timer_c2_ok ) - max_cstate = ACPI_STATE_C2; + max_usable_cstate = ACPI_STATE_C2; else - max_cstate = ACPI_STATE_C1; + max_usable_cstate = ACPI_STATE_C1; } hpet_disable_legacy_broadcast(); } -bool cpuidle_using_deep_cstate(void) +bool cpuidle_usable_deep_cstate(void) { - return xen_cpuidle && max_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2 - : ACPI_STATE_C1); + return xen_cpuidle && + max_usable_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2 + : ACPI_STATE_C1); } static int cf_check cpu_callback( --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -384,12 +384,12 @@ static void probe_c3_errata(const struct }; /* Serialized by the AP bringup code. */ - if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && + if ( max_usable_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && x86_match_cpu(models) ) { printk(XENLOG_WARNING "Disabling C-states C3 and C6 due to CPU errata\n"); - max_cstate = 1; + max_usable_cstate = 1; } } --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1045,15 +1045,16 @@ static void cf_check mwait_idle(void) u64 before, after; u32 exp = 0, pred = 0, irq_traced[4] = { 0 }; - if (max_cstate > 0 && power && + if (max_cstate() > 0 && power && (next_state = cpuidle_current_governor->select(power)) > 0) { unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 - : max_cstate; + : max_cstate(); do { cx = &power->states[next_state]; - } while ((cx->type > max_state || (cx->type == max_cstate && - MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && + } while ((cx->type > max_state || + (cx->type == max_allowed_cstate && + MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && --next_state); if (!next_state) cx = NULL; @@ -1458,7 +1459,7 @@ static void __init sklh_idle_state_table u64 msr; /* if PC10 disabled via cmdline max_cstate=7 or shallower */ - if (max_cstate <= 7) + if (max_cstate() <= 7) return; /* if PC10 not present in CPUID.MWAIT.EDX */ @@ -1623,7 +1624,7 @@ static int __init mwait_idle_probe(void) !mwait_substates) return -ENODEV; - if (!max_cstate || !opt_mwait_idle) { + if (!max_cstate() || !opt_mwait_idle) { pr_debug(PREFIX "disabled\n"); return -EPERM; } @@ -1714,8 +1715,8 @@ static int cf_check mwait_idle_cpu_init( hint = flg2MWAIT(cpuidle_state_table[cstate].flags); state = MWAIT_HINT2CSTATE(hint) + 1; - if (state > max_cstate) { - printk(PREFIX "max C-state %u reached\n", max_cstate); + if (state > max_cstate()) { + printk(PREFIX "max C-state %u reached\n", max_cstate()); break; } --- a/xen/arch/x86/include/asm/time.h +++ b/xen/arch/x86/include/asm/time.h @@ -31,7 +31,6 @@ int cpu_frequency_change(u64 freq); void cf_check pit_broadcast_enter(void); void cf_check pit_broadcast_exit(void); -int pit_broadcast_is_available(void); uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks); --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -517,7 +517,7 @@ static int64_t __init cf_check init_hpet bool disable_hpet = false; if ( hpet_address && strcmp(opt_clocksource, pts->id) && - cpuidle_using_deep_cstate() ) + cpuidle_usable_deep_cstate() ) { if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0), PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL ) @@ -2655,7 +2655,7 @@ static int _disable_pit_irq(bool init) * XXX dom0 may rely on RTC interrupt delivery, so only enable * hpet_broadcast if FSB mode available or if force_hpet_broadcast. */ - if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) + if ( cpuidle_usable_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) { init ? hpet_broadcast_init() : hpet_broadcast_resume(); if ( !hpet_broadcast_is_available() ) @@ -2707,11 +2707,6 @@ void cf_check pit_broadcast_exit(void) reprogram_timer(this_cpu(timer_deadline)); } -int pit_broadcast_is_available(void) -{ - return cpuidle_using_deep_cstate(); -} - void send_timer_event(struct vcpu *v) { send_guest_vcpu_virq(v, VIRQ_TIMER); @@ -2999,7 +2994,7 @@ static void cf_check dump_softtsc(unsign else if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC ) ) { printk("TSC has constant rate, "); - if ( max_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 ) + if ( max_usable_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 ) printk("no deep Cstates, passed warp test, deemed reliable, "); else printk("deep Cstates possible, so not reliable, "); --- a/xen/include/xen/acpi.h +++ b/xen/include/xen/acpi.h @@ -142,30 +142,33 @@ int acpi_gsi_to_irq (u32 gsi, unsigned i #ifdef CONFIG_ACPI_CSTATE /* - * max_cstate sets the highest legal C-state. - * max_cstate = 0: C0 okay, but not C1 - * max_cstate = 1: C1 okay, but not C2 - * max_cstate = 2: C2 okay, but not C3 etc. - - * max_csubstate sets the highest legal C-state sub-state. Only applies to the - * highest legal C-state. - * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E - * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 - * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 - * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 + * max_{allowed,usable}_cstate sets the highest allowed / usable C-state, where + * "allowed" is command line / sysctl based. + * max_*_cstate = 0: C0 okay, but not C1 + * max_*_cstate = 1: C1 okay, but not C2 + * max_*_cstate = 2: C2 okay, but not C3 etc. + * + * max_csubstate sets the highest allowed C-state sub-state. Only applies to + * the highest allowed C-state. + * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E + * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 + * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 + * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 */ -extern unsigned int max_cstate; +extern unsigned int max_usable_cstate; +extern unsigned int max_allowed_cstate; extern unsigned int max_csubstate; +#define max_cstate() min(max_usable_cstate, max_allowed_cstate) + static inline unsigned int acpi_get_cstate_limit(void) { - return max_cstate; + return max_allowed_cstate; } static inline void acpi_set_cstate_limit(unsigned int new_limit) { - max_cstate = new_limit; - return; + max_allowed_cstate = new_limit; } static inline unsigned int acpi_get_csubstate_limit(void) --- a/xen/include/xen/cpuidle.h +++ b/xen/include/xen/cpuidle.h @@ -89,7 +89,7 @@ struct cpuidle_governor extern int8_t xen_cpuidle; extern struct cpuidle_governor *cpuidle_current_governor; -bool cpuidle_using_deep_cstate(void); +bool cpuidle_usable_deep_cstate(void); void cpuidle_disable_deep_cstate(void); #define CPUIDLE_DRIVER_STATE_START 1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 11:52:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 11:52:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275806.1561516 (Exim 4.92) (envelope-from ) id 1wARSF-0003kF-00; Wed, 08 Apr 2026 11:52:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275806.1561516; Wed, 08 Apr 2026 11:52:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARSE-0003k8-Sy; Wed, 08 Apr 2026 11:52:18 +0000 Received: by outflank-mailman (input) for mailman id 1275806; Wed, 08 Apr 2026 11:52:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wARSD-0003k2-86 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 11:52:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARSC-005mAP-5W for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:52:16 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d6416f-e002-0a2a0a5209dd-0a2a450bab44-2 for ; Wed, 08 Apr 2026 13:52:16 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d6416f-bca8-0a2a450b0019-d1558036c048-3 for ; Wed, 08 Apr 2026 13:52:15 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso40338505e9.2 for ; Wed, 08 Apr 2026 04:52:15 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Currently it can return 0 or -ENOSUPP, and >>>> - * without SSTC we still need an implementation because only the >>>> - * M-mode timer is available, and it can only be programmed in >>>> - * M-mode. >>>> - */ >>>> - if ( (rc = sbi_set_timer(deadline)) ) >>>> + if ( (rc = set_xen_timer(deadline)) ) >>>> panic("%s: timer wasn't set because: %d\n", __func__, rc); >>>> >>>> /* Enable timer interrupt */ >>>> @@ -85,10 +84,17 @@ int reprogram_timer(s_time_t timeout) >>>> >>>> void __init preinit_xen_time(void) >>>> { >>>> + unsigned long tmp; >>>> + >>>> if ( acpi_disabled ) >>>> preinit_dt_xen_time(); >>>> else >>>> panic("%s: ACPI isn't supported\n", __func__); >>>> >>>> boot_clock_cycles = get_cycles(); >>>> + >>>> + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) >>>> + set_xen_timer = sstc_set_xen_timer; >>>> + else >>>> + set_xen_timer = sbi_set_timer; >>>> } >>> >>> Doesn't all of this together eliminate the need for sbi_set_timer as a >>> separate global variable? >> There's still a need for that SBI-level dispatch. However, sbi_set_timer >> doesn't need to be a global variable (exported from sbi.h). Since the >> only external user after this patch is the time.c, sbi_set_timer could >> be refactored into a plain static internal pointer with a non-static >> wrapper function: >> >> // sbi.c — keep dispatch internal >> static int (* __ro_after_init sbi_set_timer_fn)(uint64_t) = >> sbi_set_timer_v01; >> >> int cf_check sbi_set_timer(uint64_t stime_value) >> { >> return sbi_set_timer_fn(stime_value); >> } >> >> Do you mean this? > > No. Why is it that we'd still need both set_xen_timer and sbi_set_timer > as distinct variables? We don't need, it just a question of design I think. extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) could be renamed to set_xen_timer. And then re-init set_xen_timer here in preinit_xen_time() if SSTC is available: if ( csr_read_safe(CSR_STIMECMP, &tmp) ) set_xen_timer = sstc_set_xen_timer; ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:00:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:00:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275818.1561524 (Exim 4.92) (envelope-from ) id 1wARZn-0005Yj-21; Wed, 08 Apr 2026 12:00:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275818.1561524; Wed, 08 Apr 2026 12:00:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARZm-0005Yc-Vc; Wed, 08 Apr 2026 12:00:06 +0000 Received: by outflank-mailman (input) for mailman id 1275818; Wed, 08 Apr 2026 12:00:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARZl-0005Nl-Qm for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:00:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARZl-00FRXj-2g for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:00:05 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d64339-e002-0a2a0a5209dd-0a2a4507cb8c-30 for ; Wed, 08 Apr 2026 14:00:04 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d64344-ba2d-0a2a45070019-d1558031b1c0-3 for ; Wed, 08 Apr 2026 14:00:04 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4888375f735so58160395e9.3 for ; Wed, 08 Apr 2026 05:00:04 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9b9dd025-fd4d-4fa1-abb4-ad10c86f839e@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775649604-13B4041E-E68E4F2C/0/0 X-purgate-type: clean X-purgate-size: 6360 On 08.04.2026 13:34, Andrew Cooper wrote: > On 08/04/2026 11:22 am, Jan Beulich wrote: >> --- >> For PV save_segments() would need adjustment, > > Not really.  CPL3 must never have a way of modifying GS_KERN, hence ... > >> but the insn being restricted to ring 0 means PV guests can't use it anyway > > ... the CPL0 restriction. > > Arguably I should have had this in one of the FRED patches: > > --- a/xen/arch/x86/domain.c > +++ b/xen/arch/x86/domain.c > @@ -1952,7 +1952,7 @@ static void load_segments(struct vcpu *n) >   * changes to bases can also be made with the WR{FS,GS}BASE instructions, when >   * enabled. >   * > - * Guests however cannot use SWAPGS, so there is no mechanism to modify the > + * Guests cannot use SWAPGS or LKGS, so there is no mechanism to modify the >   * inactive GS base behind Xen's back.  Therefore, Xen's copy of the inactive >   * GS base is still accurate, and doesn't need reading back from hardware. >   * > > > but I don't think it's appropriate to merge into this patch. > >> (unless we wanted to emulate it as another privileged insn). > > We already have "LKGS" in hypercall form.  It's spelt > SEGBASE_GS_USER_SEL and has existed for 20 years or so. Hmm, yes. > I don't see any reason to extend emul_priv_op(). Nor do I. Nevertheless I wanted to mention the PV aspect. >> I've also dropped the test harness read_segment() change. It generally >> would be correct to have, but isn't needed anymore with neither SWAPGS >> nor LKGS handling using the hook. > > Dropping read_segment() makes your patch depend on Teddy's, now that > test_x86_emulator is blocking in CI. I'm not dropping read_segment() from there. I've dropped a change to that function that v9 had. That depends on your change (which has gone in), but not Teddy's. Or else I may not understand what you mean. >> --- a/xen/arch/x86/x86_emulate/x86_emulate.c >> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c >> @@ -2899,8 +2899,37 @@ x86_emulate( >> break; >> } >> break; >> - default: >> - generate_exception_if(true, X86_EXC_UD); >> + >> + case 6: /* lkgs */ >> + generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2, >> + X86_EXC_UD); >> + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD); >> + vcpu_must_have(lkgs); >> + fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr); >> + if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, >> + ctxt)) != X86EMUL_OKAY || >> + (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, >> + ctxt)) != X86EMUL_OKAY ) >> + goto done; >> + dst.orig_val = sreg.base; /* Preserve full GS Base. */ > > "Preserve current GS Base." > >> + if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg, >> + ctxt, ops)) != X86EMUL_OKAY ) >> + goto done; >> + /* Write (32-bit) base into SHADOW_GS. */ > > "Write new base into SHADOW_GS.  Zero extended from GDT/LDT." > >> + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, >> + ctxt, false)) != X86EMUL_OKAY || >> + (sreg.base = dst.orig_val, /* Reinstate full GS Base. */ > > "Reinstate original GS base." I can make these adjustments, sure, yet I think my forms were clear enough. > This patch needs one more hunk: > > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -765,14 +765,25 @@ static void __init calculate_hvm_max_policy(void) >       */ >      __set_bit(X86_FEATURE_NO_LMSL, fs); >   > -    /* > -     * On AMD, PV guests are entirely unable to use SYSENTER as Xen runs in > -     * long mode (and init_amd() has cleared it out of host > capabilities), but > -     * HVM guests are able if running in protected mode. > -     */ > -    if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && > -         raw_cpu_policy.basic.sep ) > -        __set_bit(X86_FEATURE_SEP, fs); > +    if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) > +    { > +        /* > +         * On AMD, PV guests are unable to use SYSENTER as Xen runs in long > +         * mode (and init_amd() has cleared it out of host > capabilities), but > +         * HVM guests are able if running in protected mode. > +         */ > +        if ( raw_cpu_policy.basic.sep ) > +            __set_bit(X86_FEATURE_SEP, fs); > + > +        /* > +         * NullSelectorClearsBase is really a "hardware doesn't have > this bug > +         * any more" bit.  All FRED-capable hardware has NSCB > properties, so > +         * disallow a configuration which suggest/causes behaviour the > OS isn't > +         * expecting. > +         */ > +        if ( !test_bit(X86_FEATURE_NSCB, fs) ) > +            __clear_bit(X86_FEATURE_LKGS, fs); > +    } >   >      /* >       * VIRT_SSBD is exposed in the default policy as a result of > > > because otherwise a CPU Policy could hide NCSB and LKGS would be have > correctly when executed normally but malfunction in the emulator. A policy cannot validly hide NSCB, as the flag - whichever way it is set - describes how the underlying hardware works. We'd need to intercept and emulate all selector loads to allow flag and hardware behavior to be out of sync. I.e. what you say for LKGS would be true for all selector loads. > This hunk is in lieu of having vendor-dependent deep-deps calculations, > although it would need duplicating in userspace too. > > Because this is only a link between an AMD-only feature and a common > feature, I think I can express it by only having a per-vendor > deep_features bitmap and keeping a shared deep_deps matrix. > > Perhaps I should prototype that instead, but it would become another > dependency for this patch. Please do, albeit as per above I don't think it's truly a prereq to the one here. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:06:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:06:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275842.1561534 (Exim 4.92) (envelope-from ) id 1wARfV-0006KA-Li; Wed, 08 Apr 2026 12:06:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275842.1561534; Wed, 08 Apr 2026 12:06:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARfV-0006K3-Ig; Wed, 08 Apr 2026 12:06:01 +0000 Received: by outflank-mailman (input) for mailman id 1275842; Wed, 08 Apr 2026 12:06:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARfU-0006Jx-C8 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:06:00 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARfT-009uHY-J0 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:05:59 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d644a6-5cb7-0a2a0a5109dd-0a2a450cd984-2 for ; Wed, 08 Apr 2026 14:05:59 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d644a7-f40c-0a2a450c0019-d1558033ed9c-3 for ; Wed, 08 Apr 2026 14:05:59 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-488afb0427eso36095075e9.1 for ; Wed, 08 Apr 2026 05:05:59 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775649959-83F42A3D-95AD36AD/0/0 X-purgate-type: clean X-purgate-size: 179 I found an old todo item, carrying out of which then made me notice another anomaly. 1: make ioremap_attr() common 2: make ioremap_wc() x86 only (for the time being) Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:07:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:07:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275849.1561544 (Exim 4.92) (envelope-from ) id 1wARgu-0006ot-1u; Wed, 08 Apr 2026 12:07:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275849.1561544; Wed, 08 Apr 2026 12:07:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARgt-0006om-T4; Wed, 08 Apr 2026 12:07:27 +0000 Received: by outflank-mailman (input) for mailman id 1275849; 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Wed, 08 Apr 2026 05:07:25 -0700 (PDT) Message-ID: <72526f3a-726a-4a1e-8d80-1a336175c1af@suse.com> Date: Wed, 8 Apr 2026 14:07:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 1/2] make ioremap_attr() common From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk References: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775650045-AFB3B3D8-ED1932D8/0/0 X-purgate-type: clean X-purgate-size: 9895 This core backing function is uniform; what varies across architectures are the attributes passed and hence the wrappers around it. Yet of course extra checking or special handling may be needed per arch, so introduce a suitable hook. Signed-off-by: Jan Beulich --- Declarations (or inline counterparts) aren't being moved around, to avoid the need to touch source files using the functions. Quite possibly they want to consistently go into xen/io.h and asm/io.h. Of course ioremap.c could also go into lib/. For RISC-V the wrappers likely should become inline functions? PPC doesn't reference any of the functions just yet, so gets only a declaration. For Arm, a TODO item is deliberately retained, yet seeing the use of ioremap_wc() in domain building (which by itself is questionable, see next patch) I wonder if that's even feasible as long as we don't have memremap() or alike. --- v2: Use conditional operator in ioremap_attr()'s final return. Re-base and leverage that to simplify ioremap_attr() itself. --- a/xen/arch/arm/include/asm/io.h +++ b/xen/arch/arm/include/asm/io.h @@ -1,6 +1,8 @@ #ifndef _ASM_IO_H #define _ASM_IO_H +#include + #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) @@ -9,6 +11,16 @@ # error "unknown ARM variant" #endif +#ifdef CONFIG_MPU +void __iomem *mpu_ioremap_attr(paddr_t start, size_t len, pte_attr_t flags); +#define arch_ioremap_attr mpu_ioremap_attr +#else +/* + * ioremap_attr() should only be used to remap device address ranges. + * TODO: Add an arch hook to verify this assumption. + */ +#endif + #endif /* * Local variables: --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -5,6 +5,7 @@ #include #include #include +#include #if defined(CONFIG_ARM_32) # include @@ -200,13 +201,12 @@ extern int prepare_secondary_mm(int cpu) extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); /* Helper function to setup memory management */ void setup_mm_helper(void); -/* map a physical range in virtual memory */ -void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int attributes); static inline void __iomem *ioremap_nocache(paddr_t start, size_t len) { return ioremap_attr(start, len, PAGE_HYPERVISOR_NOCACHE); } +#define ioremap ioremap_nocache static inline void __iomem *ioremap_cache(paddr_t start, size_t len) { --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -455,11 +455,6 @@ unsigned long get_upper_mfn_bound(void) return max_page - 1; } -void *ioremap(paddr_t pa, size_t len) -{ - return ioremap_attr(pa, len, PAGE_HYPERVISOR_NOCACHE); -} - /* * Local variables: * mode: C --- a/xen/arch/arm/mmu/pt.c +++ b/xen/arch/arm/mmu/pt.c @@ -206,23 +206,6 @@ void clear_fixmap(unsigned int map) BUG_ON(res != 0); } -/* - * This function should only be used to remap device address ranges - * TODO: add a check to verify this assumption - */ -void *ioremap_attr(paddr_t start, size_t len, unsigned int attributes) -{ - mfn_t mfn = _mfn(PFN_DOWN(start)); - unsigned int offs = start & (PAGE_SIZE - 1); - unsigned int nr = PFN_UP(offs + len); - void *ptr = __vmap(&mfn, nr, 1, 1, attributes, VMAP_DEFAULT); - - if ( ptr == NULL ) - return NULL; - - return ptr + offs; -} - static int create_xen_table(lpae_t *entry) { mfn_t mfn; --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -9,6 +9,8 @@ #include #include #include + +#include #include #include #include @@ -593,7 +595,7 @@ void free_init_memory(void) spin_unlock(&xen_mpumap_lock); } -void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags) +void __iomem *mpu_ioremap_attr(paddr_t start, size_t len, pte_attr_t flags) { paddr_t start_pg = round_pgdown(start); paddr_t end_pg = round_pgup(start + len); --- a/xen/arch/ppc/include/asm/io.h +++ b/xen/arch/ppc/include/asm/io.h @@ -13,4 +13,6 @@ #define writew(v,c) ({ (void)(v); (void)(c); BUG_ON("unimplemented"); }) #define writel(v,c) ({ (void)(v); (void)(c); BUG_ON("unimplemented"); }) +void __iomem *ioremap(paddr_t pa, size_t len); + #endif /* __ASM_PPC_IO_H__ */ --- a/xen/arch/riscv/include/asm/io.h +++ b/xen/arch/riscv/include/asm/io.h @@ -41,6 +41,7 @@ #include #include +void __iomem *ioremap(paddr_t pa, size_t len); void __iomem *ioremap_cache(paddr_t pa, size_t len); void __iomem *ioremap_wc(paddr_t pa, size_t len); --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -587,20 +587,6 @@ void *__init arch_vmap_virt_end(void) return (void *)(VMAP_VIRT_START + VMAP_VIRT_SIZE); } -static void __iomem *ioremap_attr(paddr_t pa, size_t len, - pte_attr_t attributes) -{ - mfn_t mfn = _mfn(PFN_DOWN(pa)); - unsigned int offs = pa & (PAGE_SIZE - 1); - unsigned int nr = PFN_UP(offs + len); - void *ptr = __vmap(&mfn, nr, 1, 1, attributes, VMAP_DEFAULT); - - if ( ptr == NULL ) - return NULL; - - return ptr + offs; -} - void __iomem *ioremap_cache(paddr_t pa, size_t len) { return ioremap_attr(pa, len, PAGE_HYPERVISOR); --- a/xen/arch/x86/include/asm/io.h +++ b/xen/arch/x86/include/asm/io.h @@ -47,6 +47,9 @@ __OUT(b,"b",char) __OUT(w,"w",short) __OUT(l,,int) +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr); +#define arch_ioremap_attr x86_ioremap_attr + /* * Boolean indicator and function used to handle platform specific I/O port * emulation. --- a/xen/arch/x86/include/asm/mm.h +++ b/xen/arch/x86/include/asm/mm.h @@ -611,7 +611,15 @@ void destroy_perdomain_mapping(struct do unsigned int nr); void free_perdomain_mappings(struct domain *d); -void __iomem *ioremap_wc(paddr_t pa, size_t len); +static inline void __iomem *ioremap(paddr_t pa, size_t len) +{ + return ioremap_attr(pa, len, PAGE_HYPERVISOR_UCMINUS); +} + +static inline void __iomem *ioremap_wc(paddr_t pa, size_t len) +{ + return ioremap_attr(pa, len, PAGE_HYPERVISOR_WC); +} extern int memory_add(unsigned long spfn, unsigned long epfn, unsigned int pxm); --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -6167,41 +6167,15 @@ void *__init arch_vmap_virt_end(void) return fix_to_virt(__end_of_fixed_addresses); } -void __iomem *ioremap(paddr_t pa, size_t len) +void __iomem *x86_ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) { - mfn_t mfn = _mfn(PFN_DOWN(pa)); - void *va; - - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); + WARN_ON(page_is_ram_type(PFN_DOWN(pa), RAM_TYPE_CONVENTIONAL)); /* The low first Mb is always mapped. */ - if ( !((pa + len - 1) >> 20) ) - va = __va(pa); - else - { - unsigned int offs = pa & (PAGE_SIZE - 1); - unsigned int nr = PFN_UP(offs + len); - - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_UCMINUS, VMAP_DEFAULT); - if ( va ) - va += offs; - } - - return (void __force __iomem *)va; -} - -void __iomem *__init ioremap_wc(paddr_t pa, size_t len) -{ - mfn_t mfn = _mfn(PFN_DOWN(pa)); - unsigned int offs = pa & (PAGE_SIZE - 1); - unsigned int nr = PFN_UP(offs + len); - void *va; - - WARN_ON(page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL)); - - va = __vmap(&mfn, nr, 1, 1, PAGE_HYPERVISOR_WC, VMAP_DEFAULT); + if ( !((pa + len - 1) >> 20) && attr == PAGE_HYPERVISOR_UCMINUS ) + return (void __force __iomem *)__va(pa); - return (void __force __iomem *)(va ? va + offs : NULL); + return NULL; } int create_perdomain_mapping(struct domain *d, unsigned long va, --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_EVTCHN_FIFO) += event_fifo. obj-$(CONFIG_GRANT_TABLE) += grant_table.o obj-y += gzip/ obj-$(CONFIG_HYPFS) += hypfs.o +obj-y += ioremap.o obj-$(CONFIG_IOREQ_SERVER) += ioreq.o obj-y += irq.o obj-y += kernel.o --- /dev/null +++ b/xen/common/ioremap.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include + +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr) +{ + void __iomem *ptr = NULL; + unsigned int offs = PAGE_OFFSET(pa); + +#ifdef arch_ioremap_attr + ptr = arch_ioremap_attr(pa, len, attr); + if ( ptr ) + return ptr; +#endif + + if ( IS_ENABLED(CONFIG_HAS_VMAP) ) + { + mfn_t mfn = _mfn(PFN_DOWN(pa)); + + ptr = (void __force __iomem *)__vmap(&mfn, PFN_UP(offs + len), 1, 1, + attr, VMAP_DEFAULT); + } + + return ptr ? ptr + offs : NULL; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ --- a/xen/include/xen/vmap.h +++ b/xen/include/xen/vmap.h @@ -121,9 +121,10 @@ void vfree(void *va); * * @param pa Physical base address of the MMIO region. * @param len Length of the MMIO region in octets. + * @param attr Attributes for the mapping. * @return Pointer to the mapped area on success; NULL otherwise. */ -void __iomem *ioremap(paddr_t pa, size_t len); +void __iomem *ioremap_attr(paddr_t pa, size_t len, pte_attr_t attr); /* Return the number of pages in the mapping starting at address 'va' */ unsigned int vmap_size(const void *va); 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Wed, 08 Apr 2026 05:09:04 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:09:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 2/2] make ioremap_wc() x86 only (for the time being) From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk References: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775650145-C9B3BC9A-DE5420CB/10/73395122804 X-purgate-type: spam X-purgate-size: 2835 Its use in domain building is questionable: Already at the point both uses were introduced, ioremap_cache() existed. I can't see why kernel and initrd would need mapping WC, when at the same time other similar mappings (in common/device-tree/) are done WB. With those uses replaced, neither Arm nor RISC-V have a need for the function anymore. Amends: d8972aa9645f ("xen/arm: kernel: Rework kernel_zimage_load to use the generic copy helper") Amends: bb7e6d565d92 ("xen/arm: domain_build: Rework initrd_load to use the generic copy helper") Signed-off-by: Jan Beulich Reviewed-by: Oleksii Kurochko --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -213,11 +213,6 @@ static inline void __iomem *ioremap_cach return ioremap_attr(start, len, PAGE_HYPERVISOR); } -static inline void __iomem *ioremap_wc(paddr_t start, size_t len) -{ - return ioremap_attr(start, len, PAGE_HYPERVISOR_WC); -} - /* XXX -- account for base */ #define mfn_valid(mfn) ({ \ unsigned long __m_f_n = mfn_x(mfn); \ --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -148,7 +148,7 @@ static void __init kernel_zimage_load(st printk("Loading zImage from %"PRIpaddr" to %"PRIpaddr"-%"PRIpaddr"\n", paddr, load_addr, load_addr + len); - kernel = ioremap_wc(paddr, len); + kernel = ioremap_cache(paddr, len); if ( !kernel ) panic("Unable to map the %pd kernel\n", info->bd.d); --- a/xen/arch/riscv/include/asm/io.h +++ b/xen/arch/riscv/include/asm/io.h @@ -43,7 +43,6 @@ void __iomem *ioremap(paddr_t pa, size_t len); void __iomem *ioremap_cache(paddr_t pa, size_t len); -void __iomem *ioremap_wc(paddr_t pa, size_t len); /* Generic IO read/write. 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Wed, 08 Apr 2026 05:12:04 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:12:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie From: Jan Beulich Subject: [PATCH v10] x86: use / "support" UDB Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775650325-2ED4F152-29B1A2FA/0/0 X-purgate-type: clean X-purgate-size: 2238 With opcode D6h now firmly reserved as another #UD-raising one in 64-bit mode, use that instead of the two-byte UD2 for bug frame marking. While there also make a minor adjustment to the emulator. Signed-off-by: Jan Beulich --- One of the table entries in stub_selftest() uses UD1, yet in not quite an appropriate way: The 0x90 following it (presumably meant to be a NOP) really is a ModR/M byte, requiring a displacement to follow. Wouldn't we better adjust that (e.g. using 0xcc instead)? --- v10: Shrink the actual emulator change to just a comment adjustment. Extend .byte directive commentary. v9: New. --- a/xen/arch/x86/include/asm/bug.h +++ b/xen/arch/x86/include/asm/bug.h @@ -21,7 +21,7 @@ #ifndef __ASSEMBLER__ -#define BUG_INSTR "ud2" +#define BUG_INSTR ".byte 0xd6" /* UDB, requiring gas 2.46 */ #define BUG_ASM_CONST "c" #else /* !__ASSEMBLER__ */ @@ -37,7 +37,7 @@ .error "Invalid BUGFRAME index" .endif - .L\@ud: ud2a + .L\@ud: .byte 0xd6 /* UDB, requiring gas 2.46 */ .pushsection .rodata.str1, "aMS", @progbits, 1 .L\@s1: .asciz "\file_str" --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1338,7 +1338,7 @@ void asmlinkage do_trap(struct cpu_user_ void asmlinkage do_invalid_op(struct cpu_user_regs *regs) { - u8 bug_insn[2]; + uint8_t bug_insn; const void *eip = (const void *)regs->rip; int id; @@ -1350,8 +1350,8 @@ void asmlinkage do_invalid_op(struct cpu } if ( !is_active_kernel_text(regs->rip) || - copy_from_unsafe(bug_insn, eip, sizeof(bug_insn)) || - memcmp(bug_insn, "\xf\xb", sizeof(bug_insn)) ) + copy_from_unsafe(&bug_insn, eip, sizeof(bug_insn)) || + bug_insn != 0xd6 /* UDB */ ) goto die; id = do_bug_frame(regs, regs->rip); --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -651,7 +651,7 @@ decode_onebyte(struct x86_emulate_state case 0xce: /* into */ case 0xd4: /* aam */ case 0xd5: /* aad */ - case 0xd6: /* salc */ + case 0xd6: /* salc / udb */ s->not_64bit = true; break; From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:20:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:20:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275934.1561585 (Exim 4.92) (envelope-from ) id 1wARta-0003hS-6G; Wed, 08 Apr 2026 12:20:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275934.1561585; Wed, 08 Apr 2026 12:20:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARta-0003hL-3N; Wed, 08 Apr 2026 12:20:34 +0000 Received: by outflank-mailman (input) for mailman id 1275934; Wed, 08 Apr 2026 12:20:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARtY-0003hE-Mj for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:20:32 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARtY-007lJO-2f for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:20:32 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d64802-e002-0a2a0a5209dd-0a2a450996ca-14 for ; Wed, 08 Apr 2026 14:20:31 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d6480f-bf79-0a2a45090019-d155802bc0eb-3 for ; Wed, 08 Apr 2026 14:20:31 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso40694015e9.2 for ; Wed, 08 Apr 2026 05:20:31 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 05:20:31 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:20:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v2 0/3] x86: CET-SS related adjustments To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; 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There are a few open aspects; see individual patches. v2, besides addressing small issues, is mainly a re-base over FRED work finally having gone in. 1: record SSP at non-guest entry points 2: traps: use entry_ssp in fixup_exception_return() 3: prefer shadow stack for producing call traces Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:21:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:21:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275942.1561594 (Exim 4.92) (envelope-from ) id 1wARu9-00049b-F1; Wed, 08 Apr 2026 12:21:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275942.1561594; Wed, 08 Apr 2026 12:21:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARu9-00049U-C5; Wed, 08 Apr 2026 12:21:09 +0000 Received: by outflank-mailman (input) for mailman id 1275942; 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Wed, 08 Apr 2026 05:22:32 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:22:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 1/3] x86: record SSP at non-guest entry points From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775650953-0F9440B1-E8CC9AC6/0/0 X-purgate-type: clean X-purgate-size: 6855 We will want to use that value for call trace generation, and likely also to eliminate the somewhat fragile shadow stack searching done in fixup_exception_return(). For those purposes, guest-only entry points do not need to record that value. To keep the saving code simple, record our own SSP that corresponds to an exception frame, pointing to the top of the shadow stack counterpart of what the CPU has saved on the regular stack. Consuming code can then work its way from there. Signed-off-by: Jan Beulich --- For PUSH_AND_CLEAR_GPRS and POP_GPRS, putting the new field right next to the error code isn't entirely nice; putting it ahead of %r15 would entail other changes, though. An option may be to not make SSP handling part of the macros in the first place. Thoughts? For POP_GPRS, does it really matter that it doesn't alter EFLAGS? Neither of the two currene uses relies on it, and without that requirement we could use ADD in place of LEA. (Of course there are also POP-based ways of getting rid of the SSP slot.) --- v2: Add comment ahead of SAVE_ALL. Add comma between its parameters. Re-base. --- a/xen/arch/x86/hvm/svm/entry.S +++ b/xen/arch/x86/hvm/svm/entry.S @@ -103,7 +103,7 @@ __UNLIKELY_END(nsvm_hap) vmrun - SAVE_ALL + SAVE_ALL ssp=0 GET_CURRENT(bx) --- a/xen/arch/x86/hvm/vmx/entry.S +++ b/xen/arch/x86/hvm/vmx/entry.S @@ -22,7 +22,7 @@ #include FUNC(vmx_asm_vmexit_handler) - SAVE_ALL + SAVE_ALL ssp=0 mov %cr2,%rax GET_CURRENT(bx) @@ -171,7 +171,7 @@ UNLIKELY_END(realmode) .Lvmx_vmentry_fail: sti - SAVE_ALL + SAVE_ALL ssp=0 /* * SPEC_CTRL_ENTRY notes --- a/xen/arch/x86/include/asm/asm_defns.h +++ b/xen/arch/x86/include/asm/asm_defns.h @@ -219,7 +219,11 @@ static always_inline void stac(void) #endif #ifdef __ASSEMBLER__ -.macro SAVE_ALL compat=0 +/* + * Use sites may override ssp to 0. It should never be overridden to 1. + * NB: compat=1 implies ssp=0. + */ +.macro SAVE_ALL compat=0, ssp=IS_ENABLED(CONFIG_XEN_SHSTK) addq $-(UREGS_error_code-UREGS_r15), %rsp cld movq %rdi,UREGS_rdi(%rsp) @@ -233,6 +237,9 @@ static always_inline void stac(void) movq %rax,UREGS_rax(%rsp) xor %eax, %eax .if !\compat +.if \ssp + rdsspq %rcx +.endif movq %r8,UREGS_r8(%rsp) movq %r9,UREGS_r9(%rsp) movq %r10,UREGS_r10(%rsp) @@ -262,6 +269,9 @@ static always_inline void stac(void) xor %r13d, %r13d xor %r14d, %r14d xor %r15d, %r15d +#ifdef CONFIG_XEN_SHSTK + mov %rcx, UREGS_entry_ssp(%rsp) +#endif .endm #define LOAD_ONE_REG(reg, compat) \ @@ -313,9 +323,14 @@ static always_inline void stac(void) .endm /* - * Push and clear GPRs + * Push and clear GPRs. + * + * Use sites may override ssp to 0. It should never be overridden to 1. */ -.macro PUSH_AND_CLEAR_GPRS +.macro PUSH_AND_CLEAR_GPRS ssp=IS_ENABLED(CONFIG_XEN_SHSTK) +#ifdef CONFIG_XEN_SHSTK + push $0 +#endif push %rdi xor %edi, %edi push %rsi @@ -326,6 +341,9 @@ static always_inline void stac(void) xor %ecx, %ecx push %rax xor %eax, %eax + .if \ssp + rdsspq %rcx + .endif push %r8 xor %r8d, %r8d push %r9 @@ -352,6 +370,9 @@ static always_inline void stac(void) xor %r14d, %r14d push %r15 xor %r15d, %r15d + .if \ssp + mov %rcx, UREGS_entry_ssp(%rsp) + .endif .endm /* @@ -373,6 +394,9 @@ static always_inline void stac(void) pop %rdx pop %rsi pop %rdi +#ifdef CONFIG_XEN_SHSTK + lea 8(%rsp), %rsp +#endif .endm #ifdef CONFIG_PV32 --- a/xen/arch/x86/include/asm/cpu-user-regs.h +++ b/xen/arch/x86/include/asm/cpu-user-regs.h @@ -27,6 +27,15 @@ struct cpu_user_regs union { uint64_t rsi; uint32_t esi; uint16_t si; uint8_t sil; }; union { uint64_t rdi; uint32_t edi; uint16_t di; uint8_t dil; }; +#ifdef CONFIG_XEN_SHSTK + /* + * This points _at_ the corresponding shadow stack frame; it is _not_ the + * outer context's SSP. That, if the outer context has CET-SS enabled, + * is stored in the top slot of the pointed to shadow stack frame. + */ + uint64_t entry_ssp; +#endif + /* * During IDT delivery for exceptions with an error code, hardware pushes * to this point. Entry_vector is filled in by software. --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -53,6 +53,9 @@ void __dummy__(void) OFFSET(UREGS_eflags, struct cpu_user_regs, rflags); OFFSET(UREGS_rsp, struct cpu_user_regs, rsp); OFFSET(UREGS_ss, struct cpu_user_regs, ss); +#ifdef CONFIG_XEN_SHSTK + OFFSET(UREGS_entry_ssp, struct cpu_user_regs, entry_ssp); +#endif DEFINE(UREGS_kernel_sizeof, sizeof(struct cpu_user_regs)); BLANK(); --- a/xen/arch/x86/x86_64/entry.S +++ b/xen/arch/x86/x86_64/entry.S @@ -275,7 +275,7 @@ FUNC(lstar_enter) pushq $0 BUILD_BUG_ON(TRAP_syscall & 0xff) movb $TRAP_syscall >> 8, EFRAME_entry_vector + 1(%rsp) - SAVE_ALL + SAVE_ALL ssp=0 GET_STACK_END(14) @@ -315,7 +315,7 @@ FUNC(cstar_enter) pushq $0 BUILD_BUG_ON(TRAP_syscall & 0xff) movb $TRAP_syscall >> 8, EFRAME_entry_vector + 1(%rsp) - SAVE_ALL + SAVE_ALL ssp=0 GET_STACK_END(14) @@ -359,7 +359,7 @@ LABEL(sysenter_eflags_saved, 0) pushq $0 BUILD_BUG_ON(TRAP_syscall & 0xff) movb $TRAP_syscall >> 8, EFRAME_entry_vector + 1(%rsp) - SAVE_ALL + SAVE_ALL ssp=0 GET_STACK_END(14) @@ -415,7 +415,7 @@ FUNC(entry_int80) ALTERNATIVE "", clac, X86_FEATURE_XEN_SMAP pushq $0 movb $0x80, EFRAME_entry_vector(%rsp) - SAVE_ALL + SAVE_ALL ssp=0 GET_STACK_END(14) --- a/xen/arch/x86/x86_64/entry-fred.S +++ b/xen/arch/x86/x86_64/entry-fred.S @@ -10,7 +10,7 @@ /* The Ring3 entry point is required to be 4k aligned. */ FUNC(entry_FRED_R3, 4096) - PUSH_AND_CLEAR_GPRS + PUSH_AND_CLEAR_GPRS ssp=0 mov %rsp, %rdi call entry_from_pv @@ -38,7 +38,7 @@ LABEL(eretu, 0) END(eretu_exit_to_guest) FUNC(eretu_error_dom_crash) - PUSH_AND_CLEAR_GPRS + PUSH_AND_CLEAR_GPRS ssp=0 sti call asm_domain_crash_synchronous /* Does not return */ END(eretu_error_dom_crash) From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:23:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:23:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275955.1561613 (Exim 4.92) (envelope-from ) id 1wARwB-00056b-2w; Wed, 08 Apr 2026 12:23:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275955.1561613; Wed, 08 Apr 2026 12:23:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARwA-00056U-W5; Wed, 08 Apr 2026 12:23:14 +0000 Received: by outflank-mailman (input) for mailman id 1275955; Wed, 08 Apr 2026 12:23:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARw9-00054e-Mc for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:23:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARw9-001tBn-2b for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:23:13 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d648a0-bab6-0a2a0a5309dd-0a2a450bada0-44 for ; Wed, 08 Apr 2026 14:23:12 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d648b0-bca8-0a2a450b0019-d155dd32c59d-3 for ; Wed, 08 Apr 2026 14:23:12 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43d572f7437so124452f8f.1 for ; Wed, 08 Apr 2026 05:23:12 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 05:23:12 -0700 (PDT) Message-ID: <79c90706-0530-4b72-9b43-f003dfe87291@suse.com> Date: Wed, 8 Apr 2026 14:23:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 2/3] x86/traps: use entry_ssp in fixup_exception_return() From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775650992-EE54B2A1-38389B42/0/0 X-purgate-type: clean X-purgate-size: 5807 With the value recorded on entry there's no need anymore to go hunt for the respective exception frame on the shadow stack. By deriving "ptr" from that field (without any offset), it then ends up pointin one slot lower than before. Therefore all array indexes need incrementing, nicely doing away with all the negative ones. Signed-off-by: Jan Beulich --- Indentation of the prior inner (but not innermost) if()'s body is deliberately left untouched, to aid review. It'll be adjusted in a separate follow-on patch. --- v2: IS_ENABLED() -> #ifdef. Re-base. --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -690,19 +690,6 @@ unsigned long get_stack_trace_bottom(uns } } -static unsigned long get_shstk_bottom(unsigned long sp) -{ - /* SAF-11-safe */ - switch ( get_stack_page(sp) ) - { -#ifdef CONFIG_XEN_SHSTK - case 0: return ROUNDUP(sp, IST_SHSTK_SIZE) - sizeof(unsigned long); - case 5: return ROUNDUP(sp, PAGE_SIZE) - sizeof(unsigned long); -#endif - default: return sp - sizeof(unsigned long); - } -} - unsigned long get_stack_dump_bottom(unsigned long sp) { switch ( get_stack_page(sp) ) @@ -1187,26 +1174,28 @@ void asmlinkage noreturn do_unhandled_tr static void fixup_exception_return(struct cpu_user_regs *regs, unsigned long fixup, unsigned long stub_ra) { - if ( IS_ENABLED(CONFIG_XEN_SHSTK) ) +#ifdef CONFIG_XEN_SHSTK { - unsigned long ssp, *ptr, *base; + unsigned long ssp = rdssp(); - if ( (ssp = rdssp()) == SSP_NO_SHSTK ) - goto shstk_done; + if ( ssp != SSP_NO_SHSTK ) + { + unsigned long *ptr = _p(regs->entry_ssp); + unsigned long primary_shstk = + (ssp & ~(STACK_SIZE - 1)) + + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8; - ptr = _p(ssp); - base = _p(get_shstk_bottom(ssp)); + BUG_ON((regs->entry_ssp ^ primary_shstk) >> PAGE_SHIFT); - for ( ; ptr < base; ++ptr ) - { /* - * Search for %rip. The shstk currently looks like this: + * The shstk currently looks like this: * * tok [Supervisor token, == &tok | BUSY, only with FRED inactive] * ... [Pointed to by SSP for most exceptions, empty in IST cases] * %cs [== regs->cs] * %rip [== regs->rip] - * SSP [Likely points to 3 slots higher, above %cs] + * SSP [Pointed to by entry_ssp; Likely points to 3 slots + * higher, above %cs] * ... [call tree to this function, likely 2/3 slots] * * and we want to overwrite %rip with fixup. There are two @@ -1219,13 +1208,10 @@ static void fixup_exception_return(struc * * Check for both regs->rip and regs->cs matching. */ - if ( ptr[0] == regs->rip && ptr[1] == regs->cs ) - { - unsigned long primary_shstk = - (ssp & ~(STACK_SIZE - 1)) + - (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8; + BUG_ON(ptr[1] != regs->rip || ptr[2] != regs->cs); - wrss(fixup, ptr); + { + wrss(fixup, &ptr[1]); if ( !stub_ra ) goto shstk_done; @@ -1242,7 +1228,7 @@ static void fixup_exception_return(struc * - if we're on an IST stack, we need to increment the * original SSP. */ - BUG_ON((ptr[-1] ^ primary_shstk) >> PAGE_SHIFT); + BUG_ON((ptr[0] ^ primary_shstk) >> PAGE_SHIFT); if ( (ssp ^ primary_shstk) >> PAGE_SHIFT ) { @@ -1251,39 +1237,30 @@ static void fixup_exception_return(struc * addresses actually match. Then increment the interrupted * context's SSP. */ - BUG_ON(stub_ra != *(unsigned long*)ptr[-1]); - wrss(ptr[-1] + 8, &ptr[-1]); + BUG_ON(stub_ra != *(unsigned long*)ptr[0]); + wrss(ptr[0] + 8, &ptr[0]); goto shstk_done; } /* Make sure the two return addresses actually match. */ - BUG_ON(stub_ra != ptr[2]); + BUG_ON(stub_ra != ptr[3]); /* Move exception frame, updating SSP there. */ - wrss(ptr[1], &ptr[2]); /* %cs */ - wrss(ptr[0], &ptr[1]); /* %rip */ - wrss(ptr[-1] + 8, &ptr[0]); /* SSP */ + wrss(ptr[2], &ptr[3]); /* %cs */ + wrss(ptr[1], &ptr[2]); /* %rip */ + wrss(ptr[0] + 8, &ptr[1]); /* SSP */ /* Move all newer entries. */ - while ( --ptr != _p(ssp) ) - wrss(ptr[-1], &ptr[0]); + while ( ptr-- != _p(ssp) ) + wrss(ptr[0], &ptr[1]); /* Finally account for our own stack having shifted up. */ asm volatile ( "incsspd %0" :: "r" (2) ); - - goto shstk_done; } } - - /* - * We failed to locate and fix up the shadow IRET frame. This could - * be due to shadow stack corruption, or bad logic above. We cannot - * continue executing the interrupted context. - */ - BUG(); - } shstk_done: +#endif /* CONFIG_XEN_SHSTK */ /* Fixup the regular stack. */ regs->rip = fixup; From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:23:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:23:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275962.1561621 (Exim 4.92) (envelope-from ) id 1wARwj-0005ZM-AX; Wed, 08 Apr 2026 12:23:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275962.1561621; Wed, 08 Apr 2026 12:23:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARwj-0005ZF-7q; Wed, 08 Apr 2026 12:23:49 +0000 Received: by outflank-mailman (input) for mailman id 1275962; Wed, 08 Apr 2026 12:23:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wARwi-0005Z3-5n for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:23:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wARwf-005bLj-WE for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:23:47 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d648d1-e002-0a2a0a5209dd-0a2a4503c760-6 for ; Wed, 08 Apr 2026 14:23:47 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d648d3-02b3-0a2a45030019-d155802ad825-3 for ; Wed, 08 Apr 2026 14:23:47 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4887fd35e60so40745305e9.2 for ; Wed, 08 Apr 2026 05:23:47 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 05:23:46 -0700 (PDT) Message-ID: <4bcc73db-38da-446e-b277-cf94c49002a1@suse.com> Date: Wed, 8 Apr 2026 14:23:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v2 3/3] x86: prefer shadow stack for producing call traces From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775651027-43301C9A-490F1BA4/0/0 X-purgate-type: clean X-purgate-size: 3337 Shadow stacks contain little more than return addresses, and they in particular allow precise call traces also without FRAME_POINTER. Signed-off-by: Jan Beulich --- While the 'E' for exception frames is probably okay, I'm not overly happy with the 'C' (for CET). I would have preferred 'S' (for shadow), but we use that character already. As an alternative to suppressing output for the top level exception frame, adding the new code ahead of the 'R' output line (and then also ahead of the stack top read) could be considered. Perhaps having a printk() for the PV entry case is meaningless, for - no frame being pushed when entered from CPL=3 (64-bit PV), - no entry possible from CPL<3 (32-bit PV disabled when CET is active)? In which case the comment probably should just be "Bogus." and the code merely be "break;". Quite likely a number of other uses of is_active_kernel_text() also want amending with in_stub(). --- v2: IS_ENABLED() -> #ifdef. Re-base. --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include @@ -705,6 +706,13 @@ unsigned long get_stack_dump_bottom(unsi } } +#ifdef CONFIG_XEN_SHSTK +static bool in_stub(unsigned long addr) +{ + return !((this_cpu(stubs.addr) ^ addr) >> STUB_BUF_SHIFT); +} +#endif + #if !defined(CONFIG_FRAME_POINTER) /* @@ -797,6 +805,52 @@ static void show_trace(const struct cpu_ !is_active_kernel_text(tos) ) printk(" [<%p>] R %pS\n", _p(regs->rip), _p(regs->rip)); +#ifdef CONFIG_XEN_SHSTK + if ( rdssp() != SSP_NO_SHSTK ) + { + const unsigned long *ptr = _p(regs->entry_ssp); + unsigned int n; + + for ( n = 0; (unsigned long)ptr & (PAGE_SIZE - sizeof(*ptr)); ++n ) + { + unsigned long val = *ptr; + + if ( is_active_kernel_text(val) || in_stub(val) ) + { + /* Normal return address entry. */ + printk(" [<%p>] C %pS\n", _p(val), _p(val)); + ++ptr; + } + else if ( !((val ^ *ptr) >> (PAGE_SHIFT + STACK_ORDER)) ) + { + if ( val & (sizeof(val) - 1) ) + { + /* Most likely a supervisor token. */ + break; + } + + /* + * Ought to be a hypervisor interruption frame. But don't + * (re)log the current frame's %rip. + */ + if ( n || ptr[1] != regs->rip ) + printk(" [<%p>] E %pS\n", _p(ptr[1]), _p(ptr[1])); + ptr = _p(val); + } + else + { + /* Ought to be a PV guest hypercall/interruption frame. */ + printk(" %04lx:[<%p>] E\n", ptr[2], _p(ptr[1])); + ptr = 0; + } + } + + /* Fall back to legacy stack trace if nothing was logged at all. */ + if ( n ) + return; + } +#endif /* CONFIG_XEN_SHSTK */ + if ( fault ) { printk(" [Fault on access]\n"); From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:27:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:27:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275979.1561631 (Exim 4.92) (envelope-from ) id 1wAS0R-0006RW-UG; Wed, 08 Apr 2026 12:27:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275979.1561631; Wed, 08 Apr 2026 12:27:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAS0R-0006RP-QM; Wed, 08 Apr 2026 12:27:39 +0000 Received: by outflank-mailman (input) for mailman id 1275979; Wed, 08 Apr 2026 12:27:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAS0Q-0006P0-7h for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:27:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAS0P-005uX6-Fw for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:27:37 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d649ac-2eae-0a2a0a5409dd-0a2a45049042-18 for ; Wed, 08 Apr 2026 14:27:37 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d649b9-bb33-0a2a45040019-d1558035e112-3 for ; Wed, 08 Apr 2026 14:27:37 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso42082445e9.3 for ; Wed, 08 Apr 2026 05:27:37 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <00a42bdd-8d9b-4828-b789-8d6163c0314c@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775651257-3132C51B-8C895C61/0/0 X-purgate-type: clean X-purgate-size: 1999 On 08.04.2026 14:21, Mykyta Poturai wrote: > On 3/30/26 15:19, Jan Beulich wrote: >> On 30.03.2026 13:59, Mykyta Poturai wrote: >>> For the purposes of certification, we want as little code as possible to >>> be unconditionally compiled in. Make CPU hotplug and SMT operations >>> configurable to ease the process. This will also help with introducing >>> CPU hotplug on Arm, where it needs to be configurable. >>> >>> Signed-off-by: Mykyta Poturai >> >> Looks largely okay from a technical pov; one nit and one (repeated) remark >> below. >> >>> --- a/xen/arch/x86/sysctl.c >>> +++ b/xen/arch/x86/sysctl.c >>> @@ -53,6 +53,11 @@ static long cf_check smt_up_down_helper(void *data) >>> unsigned int cpu, sibling_mask = boot_cpu_data.x86_num_siblings - 1; >>> int ret = 0; >>> >>> + if ( !IS_ENABLED(CONFIG_CPU_HOTPLUG) ) >>> + { >>> + ASSERT_UNREACHABLE(); >>> + return -EOPNOTSUPP; >>> + } >>> opt_smt = up; >> >> Another blank line above this one perhaps? >> >>> --- a/xen/common/Kconfig >>> +++ b/xen/common/Kconfig >>> @@ -637,6 +637,14 @@ config SYSTEM_SUSPEND >>> >>> If unsure, say N. >>> >>> +config CPU_HOTPLUG >>> + bool "CPU online/offline support" >>> + depends on X86 >>> + default y >>> + help >>> + Enable support for bringing CPUs online and offline at runtime. On >>> + X86 this is required for disabling SMT. >> >> The name of this option may need input from others; I'm not quite convinced >> that this is a good name, as there's no true "hot-plugging" involved here. >> IOW I fear the present name is misleading. > > My first idea was "CONFIG_RUNTIME_CPU_CONTROL" I can switch back to it. I could live with that, for at least not being misleading. CPU_ONLINE or CPU_ONLINE_OFFLINE might be another option, possibly better suited to later become a dependency (select) of a true CPU_HOTPLUG. As said, input from others may be helpful. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:35:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:35:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1275992.1561640 (Exim 4.92) (envelope-from ) id 1wAS7S-0008I4-Jm; Wed, 08 Apr 2026 12:34:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1275992.1561640; Wed, 08 Apr 2026 12:34:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAS7S-0008Hw-Gd; Wed, 08 Apr 2026 12:34:54 +0000 Received: by outflank-mailman (input) for mailman id 1275992; Wed, 08 Apr 2026 12:34:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAS7R-0008Hq-Tp for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:34:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAS7Q-008eTB-RK for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:34:52 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d64b5d-bab6-0a2a0a5309dd-0a2a4509a234-40 for ; Wed, 08 Apr 2026 14:34:52 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d64b6c-bf79-0a2a45090019-d1558031edb8-3 for ; Wed, 08 Apr 2026 14:34:52 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488afb0427eso36378955e9.1 for ; Wed, 08 Apr 2026 05:34:52 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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AJvYcCUAcgsWp5nA9hOqIRYtX/IdiKEeHdgSPA084pufUB6U+NiZ3swvk6MVfyleLAptG2nQz82nE+2AWEU=@lists.xenproject.org X-Gm-Message-State: AOJu0YymPFK2X22cNKWmSxrBa6/aM8kALaJr5OkVjpGftv1zpTC72wZI 7TXOqFcgPmP/kyBB/WChpqywdOK80kuz2B4ulyDOeBSz/rsLLQUKJP+g12bf4wG+SA== X-Gm-Gg: AeBDiet11qbdv42gXDhzXoAulaLwZSplqlzQtvOuzKgTr6lItwKjgxSog7JMVhESczN u8erqYKThQnsHVr0KSgdU1gQPV73C35keXQUxaqCaXMT9xugflRTqosirXBBnAQTTWLDJtuhULL KWvsvl1NmW//tqefpoSdyVFJFWlqI9fRDNwJyNR0rzsHnzyfaIqVTKlqDqhCoSYP5Lkj7CvwPHh M7mLr//JFe+1hUUtUL2y4r+uIZRN005KvB4Poj8OsIG9N4g3Ka4vF57QM2bjny7rpNwdxzdYPHH jtaZjJzYqBpq0uYRL0ypgib4BhBKh9D96kCtQY95gHjWoy4oxqFLlf00EcLawWZzrK3wsA9DzwY +vJbIyXdZbCwqnk6NsAhu9lzdIWVzFOreh+2W9rymUAb7NQ3nwrhJF3ej2QxdWdeyrcxlIiJQEp LLfcnMjQ+tVGGEoSjX5SxcYPdN7S3p9VGJ9DKbi6kRE6TCfsr5vmewcAtHtTtf303y9+csyrFIr KjoNcE4LJohBS4= X-Received: by 2002:a05:600c:4689:b0:488:be21:54ae with SMTP id 5b1f17b1804b1-488be21569bmr98992405e9.0.1775651692055; Wed, 08 Apr 2026 05:34:52 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 14:34:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10] xenpm: Add get-core-temp subcommand To: Teddy Astie Cc: Oleksii Kurochko , Community Manager , Anthony PERARD , xen-devel@lists.xenproject.org References: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1775651692-2F34C152-F5F2749C/0/0 X-purgate-type: clean X-purgate-size: 3605 On 07.04.2026 16:10, Teddy Astie wrote: > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -16,6 +16,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) > mitigate (by rate-limiting) the system wide impact of an HVM guest > misusing atomic instructions. > - Support for CPIO microcode in discrete multiboot modules. > + - Introduce get-core-temp to xenpm to query CPU temperatures on Intel > + platforms. Would you mind inserting "command" or "option" before "to xenpm"? > @@ -1354,6 +1358,121 @@ void enable_turbo_mode(int argc, char *argv[]) > errno, strerror(errno)); > } > > +static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *temp) > +{ > + xc_resource_entry_t entries[] = { > + { .idx = package ? MSR_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS }, > + { .idx = MSR_TEMPERATURE_TARGET }, > + }; > + struct xc_resource_op ops = { > + .cpu = cpu, > + .entries = entries, > + .nr_entries = ARRAY_SIZE(entries), > + }; > + int tjmax; > + > + int ret = xc_resource_op(xch, 1, &ops); > + > + switch ( ret ) > + { > + case 0: > + /* This CPU isn't online or can't query this MSR */ > + errno = ENODATA; > + return -1; > + > + case 1: > + { > + /* > + * The CPU doesn't support MSR_TEMPERATURE_TARGET, we assume it's 100 > + * which is correct aside a few selected Atom CPUs. Check Linux > + * kernel's coretemp.c for more information. > + */ > + static bool has_reported_once = false; > + > + if ( !has_reported_once ) > + { > + fprintf(stderr, "MSR_TEMPERATURE_TARGET is not supported, assume " > + "tjmax = 100, readings may be incorrect.\n"); > + has_reported_once = true; > + } > + > + tjmax = 100; > + break; > + } > + > + case 2: > + tjmax = (entries[1].val >> 16) & 0xff; > + break; > + > + default: > + if ( ret > 0 ) > + { > + fprintf(stderr, "Got unexpected xc_resource_op return value: %d", ret); > + errno = EINVAL; > + } > + return -1; > + } > + > + *temp = tjmax - ((entries[0].val >> 16) & 0xff); > + return 0; > +} > + > +static void get_core_temp(int argc, char *argv[]) > +{ > + int temp = -1, cpu = -1; cpu's initializer is needed, but why would temp need one? You rely on ... > + unsigned int socket; > + bool has_data = false; > + > + if ( argc > 0 ) > + parse_cpuid(argv[0], &cpu); > + > + if ( cpu != -1 ) > + { > + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) > + { > + fprintf(stderr, "Unable to fetch temperature (%d - %s)\n", > + errno, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + else > + printf("CPU%d: %d°C\n", cpu, temp); > + return; > + } > + > + /* Per socket measurement */ > + for ( socket = 0, cpu = 0; cpu < max_cpu_nr; > + socket++, cpu += physinfo.cores_per_socket * physinfo.threads_per_core ) > + { > + if ( fetch_dts_temp(xc_handle, cpu, true, &temp) ) ... fetch_dts_temp() to always update it in the success case anyway, both here and in the other loop further down. Other than this (happy to adjust while committing, provided you agree): Reviewed-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 12:56:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 12:56:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276006.1561649 (Exim 4.92) (envelope-from ) id 1wASRe-0003FE-6J; Wed, 08 Apr 2026 12:55:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276006.1561649; Wed, 08 Apr 2026 12:55:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASRe-0003F7-3W; Wed, 08 Apr 2026 12:55:46 +0000 Received: by outflank-mailman (input) for mailman id 1276006; Wed, 08 Apr 2026 12:55:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASRd-0003Et-2V for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 12:55:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wASRa-007rbZ-TL for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 14:55:42 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65044-5cb7-0a2a0a5109dd-0a2a450c9820-18 for ; Wed, 08 Apr 2026 14:55:42 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d6504e-f40c-0a2a450c0019-d1558032b12d-3 for ; Wed, 08 Apr 2026 14:55:42 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4888375f735so58779715e9.3 for ; Wed, 08 Apr 2026 05:55:42 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Factor out a function to check ELF notes and reuse it even for PVH. Signed-off-by: Frediano Ziglio -- Changes since v1: - fix typo in title; - fix minor formatting issue; - use is_hardware_domain instead of checking is_pv_shim; - reduce indentation returning earlier; - return error instead of jumping to cleanup code. Changes since v2: - rename dom0_check_parms to initdom_check_parms; - move call to initdom_check_parms in PVH code earlier; - make "struct domain" constant. --- xen/arch/x86/dom0_build.c | 14 ++++++++++++++ xen/arch/x86/hvm/dom0_build.c | 3 +++ xen/arch/x86/include/asm/dom0_build.h | 2 ++ xen/arch/x86/pv/dom0_build.c | 10 ++-------- 4 files changed, 21 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c index 864dd9e53e..56eba8f59a 100644 --- a/xen/arch/x86/dom0_build.c +++ b/xen/arch/x86/dom0_build.c @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); } +int __init initdom_check_parms( + const struct domain *d, const struct elf_dom_parms *parms) +{ + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) + return 0; + + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) + { + printk("Kernel does not support Dom0 operation\n"); + return -EINVAL; + } + + return 0; +} /* * If allocation isn't specified, reserve 1/16th of available memory for diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c index d69a83b089..aa06cdb2f7 100644 --- a/xen/arch/x86/hvm/dom0_build.c +++ b/xen/arch/x86/hvm/dom0_build.c @@ -692,6 +692,9 @@ static int __init pvh_load_kernel( return -EINVAL; } + if ( (rc = initdom_check_parms(d, &parms)) != 0 ) + return rc; + /* Copy the OS image and free temporary buffer. */ elf.dest_base = (void *)(parms.virt_kstart - parms.virt_base); elf.dest_size = parms.virt_kend - parms.virt_kstart; diff --git a/xen/arch/x86/include/asm/dom0_build.h b/xen/arch/x86/include/asm/dom0_build.h index ff021c24af..1332f18cc6 100644 --- a/xen/arch/x86/include/asm/dom0_build.h +++ b/xen/arch/x86/include/asm/dom0_build.h @@ -8,6 +8,8 @@ extern unsigned int dom0_memflags; +int initdom_check_parms(const struct domain *d, + const struct elf_dom_parms *parms); unsigned long dom0_compute_nr_pages(struct domain *d, struct elf_dom_parms *parms, unsigned long initrd_len); diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c index 075a3646c2..12d8ba744a 100644 --- a/xen/arch/x86/pv/dom0_build.c +++ b/xen/arch/x86/pv/dom0_build.c @@ -494,14 +494,8 @@ static int __init dom0_construct(const struct boot_domain *bd) return -EINVAL; } - if ( parms.elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type != XEN_ENT_NONE ) - { - if ( !pv_shim && !test_bit(XENFEAT_dom0, parms.f_supported) ) - { - printk("Kernel does not support Dom0 operation\n"); - return -EINVAL; - } - } + if ( (rc = initdom_check_parms(d, &parms)) != 0 ) + return rc; nr_pages = dom0_compute_nr_pages(d, &parms, initrd_len); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:06:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:06:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276054.1561673 (Exim 4.92) (envelope-from ) id 1wASbg-0006AL-Dg; Wed, 08 Apr 2026 13:06:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276054.1561673; Wed, 08 Apr 2026 13:06:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASbg-0006AE-AZ; Wed, 08 Apr 2026 13:06:08 +0000 Received: by outflank-mailman (input) for mailman id 1276054; Wed, 08 Apr 2026 13:06:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASbe-0006A8-Jj for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:06:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wASbd-0022Ft-L4 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:06:05 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d652b4-2eae-0a2a0a5409dd-0a2a45089810-40 for ; Wed, 08 Apr 2026 15:06:05 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d652bc-fab6-0a2a45080019-d1558035e9db-3 for ; Wed, 08 Apr 2026 15:06:05 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-488a29e6110so43851465e9.3 for ; Wed, 08 Apr 2026 06:06:05 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775653565-7654F497-8EF1F296/0/0 X-purgate-type: clean X-purgate-size: 3942 On 01.04.2026 08:41, Mykola Kvach wrote: > From: Mykola Kvach > > The shutdown flow currently overloads is_shutting_down and > is_shut_down to represent multiple phases of the shutdown lifecycle. > Some users treat is_shutting_down narrowly as "shutdown still needs to > be driven to completion", while others rely on it more broadly as > "the domain is no longer in its normal running state". > > Make the lifecycle explicit by introducing enum > domain_shutdown_state and helper predicates whose names match their > semantics: domain_shutting_down() for the transient phase, > domain_shutdown_completed() for the final state, and > domain_in_shutdown_state() for checks that need the union of both. > > The conversion is intentionally not mechanical. The old flags were not > mutually exclusive: once a domain became fully shut down, > is_shutting_down remained set. As a result, sites that previously > used the absence of is_shutting_down to exclude both the transient and > completed states now use domain_in_shutdown_state(), sites that care > specifically about the final state use domain_shutdown_completed(), > and only paths that still have work to do before shutdown finalization > use domain_shutting_down(). In how far is the distinction between domain_shutting_down() and domain_in_shutdown_state() really necessary? What you describe above still leaves me pretty clueless as to almost(?) all of the uses of the latter (where I think the former could be used just as well). Many paths simply can't be taken anymore for a fully shut down domain, so the distinction between the two is moot there. I'm also concerned of the name domain_in_shutdown_state() itself. To me this is far closer to domain_shutdown_completed() than to the union of both states. See how e.g. x86 CPUs can be "in shutdown state", i.e. not responding to anything but a reset or init signal. IOW an entirely mechanical replacement might in fact be easier to look at. And in the one rare case where the distinction might indeed be relevant, "domain_shutting_down() || domain_shutdown_completed()" could be used. > @@ -1423,9 +1423,12 @@ int domain_shutdown(struct domain *d, u8 reason) > return 0; > } > > -void domain_resume(struct domain *d) > +int domain_resume(struct domain *d) > { > struct vcpu *v; > + enum domain_shutdown_state shutdown_state; > + unsigned int shutdown_code; > + int rc = 0; > > /* > * Some code paths assume that shutdown status does not get reset under > @@ -1435,10 +1438,18 @@ void domain_resume(struct domain *d) > > spin_lock(&d->shutdown_lock); > > - d->is_shutting_down = d->is_shut_down = 0; > + shutdown_state = d->shutdown_state; > + shutdown_code = d->shutdown_code; > + > + if ( !domain_shutdown_completed(d) ) > + { > + rc = -EINVAL; > + goto out_unlock; > + } I can't help the impression that you're mixing two things here - adjustment to how shutdown state is tracked, and enforcement of completed shutdown right here. This separate change likely would better be split out, and then come with a description saying not only what is being changed, but also why, and why the change is correct for both call sites. > @@ -1448,9 +1459,17 @@ void domain_resume(struct domain *d) > v->paused_for_shutdown = 0; > } > > + out_unlock: > spin_unlock(&d->shutdown_lock); > > domain_unpause(d); > + > + if ( rc ) > + dprintk(XENLOG_WARNING, > + "%pd: Invalid domain state for resume: shutdown_state=%u, shutdown_code=%u\n", > + d, shutdown_state, shutdown_code); The shutdown code doesn't affect whether the function would fail. The extra variable just to log it anyway is therefore a little irritating. Is there any reason to this that I'm overlooking? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:10:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:10:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276098.1561699 (Exim 4.92) (envelope-from ) id 1wASgK-0000b4-EF; Wed, 08 Apr 2026 13:10:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276098.1561699; Wed, 08 Apr 2026 13:10:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASgK-0000ax-AY; Wed, 08 Apr 2026 13:10:56 +0000 Received: by outflank-mailman (input) for mailman id 1276098; Wed, 08 Apr 2026 13:10:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASgJ-0000ak-HB for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:10:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wASgI-005LQL-TP for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:10:54 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d653c9-bab6-0a2a0a5309dd-0a2a4505adcc-34 for ; Wed, 08 Apr 2026 15:10:54 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d653de-3760-0a2a45050019-d155802db8a5-3 for ; Wed, 08 Apr 2026 15:10:54 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so50971605e9.2 for ; Wed, 08 Apr 2026 06:10:54 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 06:10:54 -0700 (PDT) Message-ID: <13f9a1c9-5722-44cc-b044-6bdbc7e845a9@suse.com> Date: Wed, 8 Apr 2026 15:10:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: Xen 4.21.1 released To: xen-announce@lists.xenproject.org Cc: "xen-devel@lists.xenproject.org" Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775653854-2233C96F-1AF07233/0/0 X-purgate-type: clean X-purgate-size: 449 All, we're pleased to announce the release of another bug fixing Xen version. (A little late, sorry.) Xen 4.21.1 is available from its git repository http://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=refs/heads/stable-4.21 (tag RELEASE-4.21.1) or from the XenProject download page https://xenproject.org/resources/downloads/. We recommend all users of the 4.21 stable series to update to this first point release. Regards, Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:13:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:13:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276115.1561708 (Exim 4.92) (envelope-from ) id 1wASit-00018x-S1; Wed, 08 Apr 2026 13:13:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276115.1561708; Wed, 08 Apr 2026 13:13:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASit-00018q-P6; Wed, 08 Apr 2026 13:13:35 +0000 Received: by outflank-mailman (input) for mailman id 1276115; Wed, 08 Apr 2026 13:13:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASis-00018g-Qs for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:13:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wASis-007v1I-4F for xen-devel@lists.xenproject.org; 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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775654012; x=1775924012; bh=/AOHxtvS+brt5jEvLfI+mHBuRJlyZx+552KE9mHGmIQ=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=cyhp/qIK6HnbmHn3fp3jVdsc+/Kyk/WDttzB6DGFaQ+Pf6Kd8CT+3RM6IkRKUWq9Y 9lc5i0LMU3G3nXJJS9Vu9j58K+2ID3zIc3TJ7m8IvgJ7UAt+v6G7bKF9zhgcq+pVcu jc+gChrJh5SFJ5U36x1eN33iWXe2Zkos10USRbvWZ/iLW4CfEWYS+9Df3vD1v7bD7A ulxmCK/g5W/s8KGaD+feEbAmUUHx0JW7/23GnQkqmrq6/nfVYbCHNaZWpI6/bL1RZ6 7ohZolikaah19E2lE/r27SrhG3gg9ujF0oDo6dfX/KDdtufvWBLpyT4o229+kVaVRY qUNfb2MOWgWsw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775654012; x=1775914512; i=teddy.astie@vates.tech; bh=/AOHxtvS+brt5jEvLfI+mHBuRJlyZx+552KE9mHGmIQ=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=iYrcCps/v24Da/gW0CO2IHbl4YN30T983MHVkLagDnT93OYJjR/S+VDTG8KmbJCrK D/EKM3yWUA/7u9Z6rx1BvGQ/8s1hhklhhQioTkta3QGY/0dp87D8QBG8T9wNP6u1tZ Fj4xYqHp4BPs4nL55XhBrl3n+Dzw8V5QMD8+cIVApwIYOYpcOKg0hcj53bmdwS4JCb e39xIiXHa5GLSqvS3w62Wf16jS5LzXOSWK3d0JhYeBVktPsVfhz1HS1wpgo7JkqgvQ aQM4ZMs+V3WA8lBOxJLW8ybLzJ/0qTSpiMXMi6siWRvyOimRk7GXUxex/Kfrz/oVMs h20HWg9ZUNIEw== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=20v10]=20xenpm:=20Add=20get-core-temp=20subcommand?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775654009868 Message-Id: <9bad4d4c-b6db-4cce-b43b-2970d333c0ce@vates.tech> To: "Jan Beulich" Cc: "Oleksii Kurochko" , "Community Manager" , "Anthony PERARD" , xen-devel@lists.xenproject.org References: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.1e0d2cfd041d4ac49ab68c2a468eb9b5?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260408:md Date: Wed, 08 Apr 2026 13:13:32 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d62444/1775654014-BC967185-C1FBC070/0/0 X-purgate-type: clean X-purgate-size: 4252 Le 08/04/2026 =C3=A0 14:36, Jan Beulich a =C3=A9crit=C2=A0: > On 07.04.2026 16:10, Teddy Astie wrote: >> --- a/CHANGELOG.md >> +++ b/CHANGELOG.md >> @@ -16,6 +16,8 @@ The format is based on [Keep a Changelog](https://keep= achangelog.com/en/1.0.0/) >> mitigate (by rate-limiting) the system wide impact of an HVM gues= t >> misusing atomic instructions. >> - Support for CPIO microcode in discrete multiboot modules. >> + - Introduce get-core-temp to xenpm to query CPU temperatures on Inte= l >> + platforms. > > Would you mind inserting "command" or "option" before "to xenpm"? > Some like > Introduce get-core-temp option to xenpm command ... ? (or something like that) I don't have any issue with rewording it. >> @@ -1354,6 +1358,121 @@ void enable_turbo_mode(int argc, char *argv[]) >> errno, strerror(errno)); >> } >> >> +static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package= , int *temp) >> +{ >> + xc_resource_entry_t entries[] =3D { >> + { .idx =3D package ? MSR_PACKAGE_THERM_STATUS : MSR_IA32_THERM_= STATUS }, >> + { .idx =3D MSR_TEMPERATURE_TARGET }, >> + }; >> + struct xc_resource_op ops =3D { >> + .cpu =3D cpu, >> + .entries =3D entries, >> + .nr_entries =3D ARRAY_SIZE(entries), >> + }; >> + int tjmax; >> + >> + int ret =3D xc_resource_op(xch, 1, &ops); >> + >> + switch ( ret ) >> + { >> + case 0: >> + /* This CPU isn't online or can't query this MSR */ >> + errno =3D ENODATA; >> + return -1; >> + >> + case 1: >> + { >> + /* >> + * The CPU doesn't support MSR_TEMPERATURE_TARGET, we assume it= 's 100 >> + * which is correct aside a few selected Atom CPUs. Check Linux >> + * kernel's coretemp.c for more information. >> + */ >> + static bool has_reported_once =3D false; >> + >> + if ( !has_reported_once ) >> + { >> + fprintf(stderr, "MSR_TEMPERATURE_TARGET is not supported, a= ssume " >> + "tjmax =3D 100, readings may be incorrect.\= n"); >> + has_reported_once =3D true; >> + } >> + >> + tjmax =3D 100; >> + break; >> + } >> + >> + case 2: >> + tjmax =3D (entries[1].val >> 16) & 0xff; >> + break; >> + >> + default: >> + if ( ret > 0 ) >> + { >> + fprintf(stderr, "Got unexpected xc_resource_op return value= : %d", ret); >> + errno =3D EINVAL; >> + } >> + return -1; >> + } >> + >> + *temp =3D tjmax - ((entries[0].val >> 16) & 0xff); >> + return 0; >> +} >> + >> +static void get_core_temp(int argc, char *argv[]) >> +{ >> + int temp =3D -1, cpu =3D -1; > > cpu's initializer is needed, but why would temp need one? You rely on ... > >> + unsigned int socket; >> + bool has_data =3D false; >> + >> + if ( argc > 0 ) >> + parse_cpuid(argv[0], &cpu); >> + >> + if ( cpu !=3D -1 ) >> + { >> + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) >> + { >> + fprintf(stderr, "Unable to fetch temperature (%d - %s)\n", >> + errno, strerror(errno)); >> + exit(EXIT_FAILURE); >> + } >> + else >> + printf("CPU%d: %d=C2=B0C\n", cpu, temp); >> + return; >> + } >> + >> + /* Per socket measurement */ >> + for ( socket =3D 0, cpu =3D 0; cpu < max_cpu_nr; >> + socket++, cpu +=3D physinfo.cores_per_socket * physinfo.threa= ds_per_core ) >> + { >> + if ( fetch_dts_temp(xc_handle, cpu, true, &temp) ) > > ... fetch_dts_temp() to always update it in the success case anyway, both= here and > in the other loop further down. > Indeed, that's not really required anymore. > Other than this (happy to adjust while committing, provided you agree): > Reviewed-by: Jan Beulich > Looks good to me with the changes. > Jan > Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:22:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:22:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276134.1561717 (Exim 4.92) (envelope-from ) id 1wASrd-00039g-Mg; Wed, 08 Apr 2026 13:22:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276134.1561717; Wed, 08 Apr 2026 13:22:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASrd-00039Z-JR; Wed, 08 Apr 2026 13:22:37 +0000 Received: by outflank-mailman (input) for mailman id 1276134; Wed, 08 Apr 2026 13:22:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wASrb-00039T-TU for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:22:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wASrb-008oiI-9H for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:22:35 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65691-5cb7-0a2a0a5109dd-0a2a4503c97a-34 for ; Wed, 08 Apr 2026 15:22:35 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d6569a-02b3-0a2a45030019-d155802de980-3 for ; Wed, 08 Apr 2026 15:22:35 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-488a29e6110so44140895e9.3 for ; Wed, 08 Apr 2026 06:22:35 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260408125521.104660-1-frediano.ziglio@cloud.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775654555-C9F3DC9A-2B84C115/0/0 X-purgate-type: clean X-purgate-size: 1129 On 08.04.2026 14:55, Frediano Ziglio wrote: > The supported features ELF notes was tested only if the dom0 was > PV. Factor out a function to check ELF notes and reuse it even > for PVH. > > Signed-off-by: Frediano Ziglio Reviewed-by: Jan Beulich > --- a/xen/arch/x86/dom0_build.c > +++ b/xen/arch/x86/dom0_build.c > @@ -320,6 +320,20 @@ unsigned long __init dom0_paging_pages(const struct domain *d, > return DIV_ROUND_UP(memkb, 1024) << (20 - PAGE_SHIFT); > } > > +int __init initdom_check_parms( > + const struct domain *d, const struct elf_dom_parms *parms) > +{ > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) > + return 0; > + > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) > + { > + printk("Kernel does not support Dom0 operation\n"); > + return -EINVAL; > + } > + > + return 0; > +} Merely as a remark - personally I would have made a function like this return a boolean. Both call sites would imo benefit from that. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:55:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:55:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276215.1561780 (Exim 4.92) (envelope-from ) id 1wATNp-0002AP-FF; Wed, 08 Apr 2026 13:55:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276215.1561780; Wed, 08 Apr 2026 13:55:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNp-0002AI-Br; Wed, 08 Apr 2026 13:55:53 +0000 Received: by outflank-mailman (input) for mailman id 1276215; Wed, 08 Apr 2026 13:55:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNn-0001w4-C5 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:55:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wATNm-00AFz6-OB for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:55:50 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65e54-e002-0a2a0a5209dd-0a2a4502d0da-48 for ; Wed, 08 Apr 2026 15:55:50 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d65e65-42fa-0a2a45020019-d98c6eacbcc8-1 for ; Wed, 08 Apr 2026 15:55:50 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE14A2D95; Wed, 8 Apr 2026 06:55:43 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 538EB3F641; Wed, 8 Apr 2026 06:55:48 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656549; bh=MZfKdfd+Fjj1nByHopUcpOrzmuP31AXPE7A1SX/KVCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kece+ckOVuHEDt+c/9tCpgkrxKngvpG1tEBgmcyidiwZ3p1OHEQHQUAHP7pPUU3A2 gxKcYy1aY2+wxvShLu/vmmgvoENvxwEt87duuVzn1GeC6DZWaByS+0awZahbr9/+V4 50lnYBTq18dbPms5Uro++lahgvoc/jiRQBeU3zHM= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 3/3] arm/mpu: Implement p2m tables Date: Wed, 8 Apr 2026 14:55:31 +0100 Message-Id: <20260408135531.1744388-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775656550-ACB37CD1-35573629/0/0 X-purgate-type: clean X-purgate-size: 5725 From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 12 +++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 78 ++++++++++++++++++++++++++-- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ #define MPU_REGION_RES0 (0xFFFFULL << 48) +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/mpu/p2m.h index e46d9e757a1d..39fc0c944916 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,20 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ +#include +#include +#include + struct p2m_domain; +/* + * The architecture allows at most 255 EL2 MPU memory regions. The size of the + * MPU structure entry (pr_t) is 32 Bytes on AArch64 (requiring two 4KB pages) + * and 16 bytes on AArch32 (requiring one 4KB page). + */ +#define P2M_ROOT_PAGES DIV_ROUND_UP(255 * sizeof(pr_t), PAGE_SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..ec8f630acd90 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,69 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + void *table = alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping table\n", + d); + return -ENOMEM; + } + + p2m->root = virt_to_page(table); + + for (int i = 0; i < P2M_ROOT_PAGES; i++) + clear_page(page_to_virt(p2m->root + i)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m = p2m_get_hostp2m(d); + int rc = 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid = INVALID_VMID; + p2m->max_mapped_gfn = _gfn(0); + p2m->lowest_mapped_gfn = _gfn(ULONG_MAX); + + p2m->default_access = p2m_access_rwx; + /* mem_access is NOT supported in MPU system. */ + p2m->mem_access_enabled = false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPUS); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU_ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] = INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so that + * p2m_teardown() and related functions know to do something. + */ + p2m->domain = d; + + rc = p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr = ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + rc = p2m_alloc_table(d); + if ( rc ) + { + p2m_free_vmid(d); + return rc; + } + + return 0; } void p2m_save_state(struct vcpu *p) @@ -46,7 +105,20 @@ void p2m_restore_state(struct vcpu *n) void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m = p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root = NULL; + + p2m_free_vmid(d); + + p2m->domain = NULL; } bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:55:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:55:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276213.1561764 (Exim 4.92) (envelope-from ) id 1wATNl-0001ir-Ua; Wed, 08 Apr 2026 13:55:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276213.1561764; Wed, 08 Apr 2026 13:55:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNl-0001ik-QT; Wed, 08 Apr 2026 13:55:49 +0000 Received: by outflank-mailman (input) for mailman id 1276213; Wed, 08 Apr 2026 13:55:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNk-0001VL-Od for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:55:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wATNk-0081Hn-4Q for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:55:48 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65e64-2eae-0a2a0a5409dd-0a2a4505be88-0 for ; Wed, 08 Apr 2026 15:55:48 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d65e63-3760-0a2a45050019-d98c6eacbd58-1 for ; Wed, 08 Apr 2026 15:55:47 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CFD1F2D95; Wed, 8 Apr 2026 06:55:40 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EAF2A3F641; Wed, 8 Apr 2026 06:55:44 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656546; bh=Jbkn6tr6DeeBrY5TgQXpfTzOB7k0l9K2i9UHo4esCJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=janao23xhFbReleouDkYkbSn4pi/0x26slL4ykiuIE20zLLYWoXQ9WNlLe9Wl4VnT QTPD+N6S0V2vPzkNsVUz4KIhrWX3d+mEXH8btNJcyTyXaUpbxRE/PZnYZgy9lMmB/b dJhw9QR0DpXo+8LOzV82SpdNN+vT0NU49Oj04lQQ= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v3 1/3] arm/mpu: implement setup_virt_paging for MPU system Date: Wed, 8 Apr 2026 14:55:29 +0100 Message-Id: <20260408135531.1744388-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775656547-3133496F-1045722C/0/0 X-purgate-type: clean X-purgate-size: 7460 From: Penny Zheng Implement setup_virt_paging for aarch64 MPU systems, taking tare of stage 2 address translation regime, IPA bits, supported VMID length configuration and vtcr_el2/vstcr_el2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey --- v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Seperate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..fda512dc7c8f 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ #include #include +#include #include void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 = READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] = {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits == PA bits, compare against "pabits". + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits = pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identify the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa != MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b0010. */ + if ( (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &= ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation output + * address space to access the Secure PA space as Armv8r only implements + * secure state. + */ + vtcr_el2 &= ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16bits VMID only if all cores + * are supporting it. + * + * Set the VS bit only if 16 bit VIMD is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |= VTCR_VS; + max_vmid = MAX_VMID_16_BIT; + } + else + vtcr_el2 &= ~VTCR_VS; + + p2m_vmid_allocator_init(); + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address space. + * To make sure that all stage 2 translations for the Secure PA space access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if they + * are different, we set SC bit 1. + */ + vstcr_el2 &= ~VSTCR_EL2_SA; + vstcr_el2 |= VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + ( MAX_VMID == MAX_VMID_16_BIT ) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"); } /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ #define VTCR_RES1 (_AC(1,UL)<<31) +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ extern register_t __cpu_logical_map[]; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:55:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:55:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276212.1561753 (Exim 4.92) (envelope-from ) id 1wATNk-0001VT-MA; Wed, 08 Apr 2026 13:55:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276212.1561753; Wed, 08 Apr 2026 13:55:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNk-0001VM-JT; Wed, 08 Apr 2026 13:55:48 +0000 Received: by outflank-mailman (input) for mailman id 1276212; Wed, 08 Apr 2026 13:55:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNj-0001VF-QE for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:55:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wATNj-00AFz6-0F for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:55:47 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65e54-e002-0a2a0a5209dd-0a2a4502d0da-42 for ; Wed, 08 Apr 2026 15:55:46 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d65e61-42fa-0a2a45020019-d98c6eacd486-1 for ; Wed, 08 Apr 2026 15:55:45 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC5331E32; Wed, 8 Apr 2026 06:55:38 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D6933F641; Wed, 8 Apr 2026 06:55:43 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656544; bh=6jm2CBfhm1vHhwvDDHpJ8C9jaQr+z0/7OM17rg20cUo=; h=From:To:Cc:Subject:Date:From; b=D/P91ZGXYt5TDvIAzgbbLH4rk8ee+mzdfj3uLEvIRefDkEGAAO4AHsHy64LyI5Jc5 h1fMTiAIx4fEab8kei9dsej0NA6ZmvXYoBzmzwrHiDx2NJ85aYH7hO/99AGmrUBUqh WC47FWOJ2pN81KaQ8b3gmYkTctR1daDOXpn9udK0= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 0/3] Fifth MPU Series Date: Wed, 8 Apr 2026 14:55:28 +0100 Message-Id: <20260408135531.1744388-1-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775656546-4792ECD1-994ADA36/0/0 X-purgate-type: clean X-purgate-size: 1363 This series continues to further the ongoing work to introduce support for MPU systems in Xen. The patches in this series aim to implement MPU specific p2m functions. Harry Ramsey (2): arm/mpu: Introduce `v8r_el1_msa` device tree property for domains arm/mpu: Implement p2m tables Penny Zheng (1): arm/mpu: implement setup_virt_paging for MPU system docs/misc/arm/device-tree/booting.txt | 12 ++++ xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/dom0less-build.c | 24 +++++++ xen/arch/arm/domain.c | 4 ++ xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/domain.h | 7 +++ xen/arch/arm/include/asm/mpu.h | 5 ++ xen/arch/arm/include/asm/mpu/p2m.h | 12 ++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/include/asm/processor.h | 8 +++ xen/arch/arm/mpu/arm32/mm.c | 5 ++ xen/arch/arm/mpu/arm64/mm.c | 5 ++ xen/arch/arm/mpu/p2m.c | 78 ++++++++++++++++++++++- xen/include/public/arch-arm.h | 2 + 17 files changed, 261 insertions(+), 7 deletions(-) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 13:55:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 13:55:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276214.1561771 (Exim 4.92) (envelope-from ) id 1wATNn-0001w9-7i; Wed, 08 Apr 2026 13:55:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276214.1561771; Wed, 08 Apr 2026 13:55:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNn-0001w1-57; Wed, 08 Apr 2026 13:55:51 +0000 Received: by outflank-mailman (input) for mailman id 1276214; Wed, 08 Apr 2026 13:55:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wATNl-0001ij-So for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 13:55:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wATNl-0081Hn-8N for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:55:49 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d65e64-2eae-0a2a0a5409dd-0a2a4505be88-10 for ; Wed, 08 Apr 2026 15:55:49 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.0) (envelope-from ) id 69d65e64-3760-0a2a45050019-d98c6eacd16c-1 for ; Wed, 08 Apr 2026 15:55:48 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 440191E32; Wed, 8 Apr 2026 06:55:42 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DC7F63F641; Wed, 8 Apr 2026 06:55:46 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656548; bh=v5LF9EBgnpQL3pb+wunpmzDERz+oj+KrD99jf6QSUyw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KlPwKuHMTA3nm6OSjAxLvuR9Qvyu1Bs4h2BMjvm8xbW1beM0vu/VITGIND60fgeBW Njl8aP1nGuhPfHde+wdmASMyeVPa9v8wipSdgR03K1GwRVbGtI3wyc3xCZEXSW8fql Oolf4ht585ZHaQ5pcKahZyOpaA7fnLGXe+fzUsGM= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Wed, 8 Apr 2026 14:55:30 +0100 Message-Id: <20260408135531.1744388-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1775656549-38BE896F-DE5C9B4A/0/0 X-purgate-type: clean X-purgate-size: 6467 From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 i.e. MPU(default) or MMU. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 12 ++++++++++++ xen/arch/arm/dom0less-build.c | 24 ++++++++++++++++++++++++ xen/arch/arm/domain.c | 4 ++++ xen/arch/arm/include/asm/domain.h | 7 +++++++ xen/arch/arm/include/asm/mpu.h | 5 +++++ xen/arch/arm/mpu/arm32/mm.c | 5 +++++ xen/arch/arm/mpu/arm64/mm.c | 5 +++++ xen/include/public/arch-arm.h | 2 ++ 8 files changed, 64 insertions(+) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt index 977b4286082f..b1a329c0e8d9 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,18 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems, a domain + should use PMSAv8 (MPU) at EL1 or VMSAv8 (MMU) at EL1. + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. + + - "mpu" + Enables PMSAv8 at EL1. (Default) + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..456dc553bb23 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #ifdef CONFIG_VGICV2 @@ -315,6 +316,7 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node, struct xen_domctl_createdomain *d_cfg = &bd->create_cfg; unsigned int flags = bd->create_flags; uint32_t val; + const char *v8r_el1_msa; d_cfg->arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE; d_cfg->flags |= XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap; @@ -322,6 +324,28 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); + if (!dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa)) + { +#ifdef CONFIG_MPU + if ( !strcmp(v8r_el1_msa, "mmu") ) + { + if ( !has_v8r_vmsa_support() ) + panic("Platform does not support VMSA at EL1 (v8r_el1_msa)\n"); + d_cfg->arch.v8r_el1_msa = MPU_EL1_VMSA; + } + else if ( !strcmp(v8r_el1_msa, "mpu") ) + { + d_cfg->arch.v8r_el1_msa = MPU_EL1_PMSA; + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + panic("PMSA is not valid for domain without static allocation and direct map (v8r_el1_msa)\n"); + } + else + panic("Invalid device tree option for v8r_el1_msa\n"); +#else + panic("'v8r_el1_msa' property found, but CONFIG_MPU not selected\n"); +#endif + } + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq = GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..c044293acd39 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -725,6 +725,10 @@ int arch_domain_create(struct domain *d, if ( (rc = sci_domain_init(d, config)) != 0 ) goto fail; +#ifdef CONFIG_MPU + d->arch.v8r_el1_msa = config->arch.v8r_el1_msa; +#endif + return 0; fail: diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..fd0a83046893 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -30,6 +30,9 @@ enum domain_type { #define is_64bit_domain(d) (0) #endif +#define MPU_EL1_PMSA 0 +#define MPU_EL1_VMSA 1 + /* * Is the domain using the host memory layout? * @@ -128,6 +131,10 @@ struct arch_domain #endif struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; struct arch_vcpu diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 72fa5b00b861..8a8c01086206 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -27,6 +27,11 @@ #ifndef __ASSEMBLER__ +/* + * Utility function to determine if an Armv8-R processor supports VMSA. + */ +bool has_v8r_vmsa_support(void); + /* * Set base address of MPU protection region. * diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..5eaeb3400e6c 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -38,6 +38,11 @@ break; \ } +bool has_v8r_vmsa_support(void) +{ + return false; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions through * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..b07e729a7d05 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -32,6 +32,11 @@ break; \ } +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac == MM64_MSA_FRAC_VMSA_SUPPORT; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions through * registers: diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..23df2f24cb09 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -355,6 +355,8 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; }; #endif /* __XEN__ || __XEN_TOOLS__ */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Apr 08 14:26:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 14:26:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276256.1561790 (Exim 4.92) (envelope-from ) id 1wATqq-0008Af-J1; Wed, 08 Apr 2026 14:25:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276256.1561790; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QCksOqbixVEpTvS9hZR23IqJQvFnnQ86AU85cemBFlcWNWBmSHodV/y0QzgYNYrUhiONm4q+NJkRuqTLxmSTGGSffDYK3QtBgyjRoqJRU3f0mnH1gKG9O2VAz8E4+Hf/YSQOv4wlCOK+NqDVU2v0tR9bEso3rAi/5tCmMgfAGamiyPbywWljbW3CqKa6dl8zD626GtGhGgP9Qbr621TEFGOfF2lS5w8STK8V5vhR3G9hIf6l74UQG3u7U7DIli6xcDqbTUdHEIl6ZIhNllBYr1o8XanMo3WRMoaY5ofg4S0kxiZw32Ephc/Lv9CFyfsgCGXU0c3hOkG4aXua1xkaA8v0+hgXchxk0Kwro5vnXXjTbkppD6xeNtQuR41h6i6KFcBjuOFvIiSmpUMMnAicfFm9/DUOYG7IiDXt7nQO0aTE7j8fjKN5qeM272mYmZmg X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2026 14:25:45.1709 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d569e302-a090-439f-380a-08de957ab8d6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C6.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9320 X-purgate-ID: tlsNG-16d1c6/1775658350-5EB333D8-4DD0E899/0/0 X-purgate-type: clean X-purgate-size: 5436 Hi Ayan, > On 18 Mar 2026, at 14:09, Ayan Kumar Halder w= rote: >=20 > One key requirement of Xen functional safety is to reduce the number > of lines of code to be safety certified. Besides, a safety certified > Xen requires a static hardware configuration to be defined. This static > hardware configuration is described as per the test hardware/emulator > hardware configuration against which Xen is verified. >=20 > Introduce GICV3_NR_LRS with the two aims in mind: > 1. User should set the number of GICV3 list registers as per the test > hardware so that the unwanted code can be removed using GCC's dead > code elimination or preprocessor's config. > 2. By doing #1, one can ensure that there is no untested code due to > unsupported hardware platform and thus there is no safety impact due > to untested code. >=20 > However if the user does not set GICV3_NR_LRS, then it is set to 0. > Thus Xen will fallback to the default scenario (i.e. read the hardware > register to determine the number of LRS). >=20 > 1. In gicv3_save_lrs()/gicv3_restore_lrs(), use the number of list > registers from GICV3_NR_LRS (if defined) instead of gicv3_info.nr_lrs. > This ensures that if the hardware does not support more than 4 LRs > (for example), the code accessing LR 4-15 is never reached. The > compiler can eliminate the unsupported cases as the switch case uses a > constant conditional. >=20 > 2. RAZ/WI for the unsupported LRs. >=20 > Signed-off-by: Ayan Kumar Halder > Signed-off-by: Michal Orzel > --- > Changelog: >=20 > v1 - 1. s/lrs/LRS > 2. Implement RAZ/WI instead of panic >=20 > Few comments which were not addressed > 1. Do "gicv3_info.nr_lrs to LRS" in gicv3_hyp_init() and keep the code > unchanged in gicv3_save_lrs()/gicv3_restore_lrs() -- This prevents the > compiler from doing dead code elimination as the switch condition cannot > be evaluated at compile time. > I am not sure how to get around this issue. >=20 > xen/arch/arm/Kconfig | 9 +++++++++ > xen/arch/arm/gic-v3.c | 14 ++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) >=20 > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig > index 2f2b501fda..6540013f97 100644 > --- a/xen/arch/arm/Kconfig > +++ b/xen/arch/arm/Kconfig > @@ -276,6 +276,15 @@ config PCI_PASSTHROUGH >=20 > endmenu >=20 > +config GICV3_NR_LRS > + int "Number of GICv3 Link Registers supported" if EXPERT > + depends on GICV3 > + range 0 16 16 is the maximum supported since ICH_VTR_EL2.ListRegs is 4 bits [1],=20 however how are we handling the case when GICV3_NR_LRS is greater than the supported number of LR registers? Shall we check that in gicv3_hyp_init()? > + default 0 > + help > + Controls the number of Link registers to be accessed. > + Keep it set to 0 to use a value obtained from a hardware register. > + > menu "ARM errata workaround via the alternative framework" > depends on HAS_ALTERNATIVE >=20 > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index bc07f97c16..eaae95eb4d 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -51,6 +51,8 @@ static DEFINE_PER_CPU(void __iomem*, rbase); > #define GICD (gicv3.map_dbase) > #define GICD_RDIST_BASE (this_cpu(rbase)) > #define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K) > +#define LRS (CONFIG_GICV3_NR_LRS ?: \ > + gicv3_info.nr_lrs) >=20 > /* > * Saves all 16(Max) LR registers. Though number of LRs implemented > @@ -59,7 +61,7 @@ static DEFINE_PER_CPU(void __iomem*, rbase); > static inline void gicv3_save_lrs(struct vcpu *v) > { > /* Fall through for all the cases */ > - switch ( gicv3_info.nr_lrs ) > + switch ( LRS ) > { > case 16: > v->arch.gic.v3.lr[15] =3D READ_SYSREG_LR(15); > @@ -121,7 +123,7 @@ static inline void gicv3_save_lrs(struct vcpu *v) > static inline void gicv3_restore_lrs(const struct vcpu *v) > { > /* Fall through for all the cases */ > - switch ( gicv3_info.nr_lrs ) > + switch ( LRS ) > { > case 16: > WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); > @@ -178,6 +180,10 @@ static inline void gicv3_restore_lrs(const struct vc= pu *v) >=20 > static uint64_t gicv3_ich_read_lr(int lr) > { > + /* RAZ for unsupported LR */ > + if ( lr >=3D LRS ) > + return 0; > + > switch ( lr ) > { > case 0: return READ_SYSREG_LR(0); > @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) >=20 > static void gicv3_ich_write_lr(int lr, uint64_t val) > { > + /* WI for unsupported LR */ > + if ( lr >=3D LRS ) > + return; > + > switch ( lr ) > { > case 0: Now, since we are using CONFIG_GICV3_NR_LRS or gicv3_info.nr_lrs in gicv3_s= ave_lrs/gicv3_restore_lrs, there are other part of the codebase using nr_lrs (gic_get_nr_lrs() is one = of them), but all the callers of that function will use the HW nr_lrs and not the CONFIG_GICV3_NR_LRS, so I think= some work needs to be done to align them or there will be mismatches at runtime with possible loss of = information. [1] https://developer.arm.com/documentation/111179/2025-09_ASL1/AArch64-Reg= isters/ICH-VTR-EL2--Interrupt-Controller-VGIC-Type-Register Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 08 15:21:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 15:21:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276280.1561799 (Exim 4.92) (envelope-from ) id 1wAUiY-0000CD-KI; Wed, 08 Apr 2026 15:21:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276280.1561799; Wed, 08 Apr 2026 15:21:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAUiY-0000C6-Hb; Wed, 08 Apr 2026 15:21:22 +0000 Received: by outflank-mailman (input) for mailman id 1276280; Wed, 08 Apr 2026 15:21:21 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAUiX-0000C0-NB for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:21:21 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAUiW-00Fs0p-V0 for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 17:21:20 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d67263-e002-0a2a0a5209dd-0a2a4508cc20-28 for ; Wed, 08 Apr 2026 17:21:20 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d67270-fab6-0a2a45080019-d155dd33bdd2-3 for ; Wed, 08 Apr 2026 17:21:20 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43cfd96354aso3984002f8f.1 for ; Wed, 08 Apr 2026 08:21:20 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775661680-F7149497-C060318B/0/0 X-purgate-type: clean X-purgate-size: 587 On 01.04.2026 18:35, Ross Lagerwall wrote: > A future change to on_selected_cpus() will change the semantics of the > wait parameter so that it doesn't wait for remote CPUs to "check in" if > wait == 0. Adjust the call here to retain the existing behaviour so it > continues to wait for the remote CPUs to VMExit. Doesn't this go too far though? IOW wouldn't we better make the "wait" parameter a tristate then? As to the semantic change, peeking at patch 2 I don't see you discussing the safety of doing so for the several other callers that also pass 0 right now. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 08 15:27:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 15:27:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276289.1561807 (Exim 4.92) (envelope-from ) id 1wAUo6-0000lA-6V; Wed, 08 Apr 2026 15:27:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276289.1561807; Wed, 08 Apr 2026 15:27:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAUo6-0000l3-3i; Wed, 08 Apr 2026 15:27:06 +0000 Received: by outflank-mailman (input) for mailman id 1276289; Wed, 08 Apr 2026 15:27:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wAUo5-0000kx-1C for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 15:27:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAUo3-006TgT-Ul for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 17:27:03 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d673a4-e002-0a2a0a5209dd-0a2a45089a66-34 for ; Wed, 08 Apr 2026 17:27:03 +0200 Received: from [209.85.218.50] (helo=mail-ej1-f50.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d673c7-fab6-0a2a45080019-d155da32bd90-3 for ; Wed, 08 Apr 2026 17:27:03 +0200 Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-b9c3e2cf3c0so1015691966b.1 for ; Wed, 08 Apr 2026 08:27:03 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Oprofile themselves removed support for Xen in 2014 >> prior to the version 1.0 release, and there has been no development since >> before then in Xen. >> + - Domains can no longer run on a system with CPUs of a vendor different from >> + the one they were initially launched on. This affects live migrations and >> + save/restore workflows across mixed-vendor hosts. Cross-vendor emulation >> + has always been unreliable, but since 2017 with the advent of speculation >> + security it became unsustainably so. > > c/s 0f1cb96e9785294f149ab3c7feb90c0eb9daeede was when it got added to Xen. > > I'm certain there's a whitepaper somewhere from AMD about this, but I > can't locate it.  It was partly marketing about how you could buy AMD > hardware (which was cheaper) and live-migrate your Intel VMs without > interruption.  It would have been nice to find for posterity. > > For the changelog, can I suggest this: > > diff --git a/CHANGELOG.md b/CHANGELOG.md > index c191e504aba9..377711d40953 100644 > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -23,6 +23,12 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) >     - Xenoprofile support.  Oprofile themselves removed support for Xen in 2014 >       prior to the version 1.0 release, and there has been no development since >       before then in Xen. > +   - Cross-vendor support; guests can now only be configured as the same > +     vendor as the host CPU.  When added back in 2009, with enough trickery > +     Intel and AMD CPUs could be made to be compatible enough to live migrate > +     a guest, but the vendors have been diverging since then in ways that Xen > +     cannot compensate for, and the advent of speculative security issues has > +     put to rest any possibility of this being a viable option. > >   - Removed xenpm tool on non-x86 platforms as it doesn't actually provide >     anything useful outside of x86. > > > which is closer to the style of the surrounding bullet points.  Also > s/domain/guest/ which is a subtle but important distinction made by the > Security Team when discussing configurations. With applying of suggested changes to CHANGELOG.md: Acked-by: Oleksii Kurochko # CHANGELOG.md Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 08 15:41:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 15:41:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276299.1561817 (Exim 4.92) (envelope-from ) id 1wAV1i-0003wN-BY; Wed, 08 Apr 2026 15:41:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276299.1561817; Wed, 08 Apr 2026 15:41:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAV1i-0003wG-8c; Wed, 08 Apr 2026 15:41:10 +0000 Received: by outflank-mailman (input) for mailman id 1276299; Wed, 08 Apr 2026 15:41:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAV1g-0003w8-7y for xen-devel@lists.xenproject.org; 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Message-ID: Date: Wed, 8 Apr 2026 16:40:59 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: Re: [PATCH v3 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains To: Luca Fancellu , xen-devel@lists.xenproject.org References: <20260408135531.1744388-1-luca.fancellu@arm.com> <20260408135531.1744388-3-luca.fancellu@arm.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: <20260408135531.1744388-3-luca.fancellu@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P265CA0266.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:37c::8) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|PH8PR03MB7173:EE_ X-MS-Office365-Filtering-Correlation-Id: ca13cb5c-6fc6-455f-ff78-08de95853d85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|22082099003|56012099003|18002099003; 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> /* IN */ > uint8_t arm_sci_type; > + /* IN */ > + uint8_t v8r_el1_msa; > }; > #endif /* __XEN__ || __XEN_TOOLS__ */ > This isn't ok as the singular change to the public headers.  (Also, I haven't had time to fix the other API abuses that have crept into ARM's arch domain config) You're introducing a new hypercall input parameter (which is fine), but has no defines (ones private to xen/arch/arm/include/asm/domain.h are not permitted for use in the public API), and for which there is no input validation.  Userspace can currently pass any arbitrary byte here which will be copied into d->arch.v8r_el1_msa, not that there's any consumer of this field I can see in the series. Frankly, I think this series is chopped up too much.  You really must not be introducing new hypercall parameters like this without the whole series which lets you `xl create` such a VM. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 15:49:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 15:49:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276308.1561825 (Exim 4.92) (envelope-from ) id 1wAV9S-0004c6-28; Wed, 08 Apr 2026 15:49:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276308.1561825; Wed, 08 Apr 2026 15:49:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAV9R-0004bz-VR; Wed, 08 Apr 2026 15:49:09 +0000 Received: by outflank-mailman (input) for mailman id 1276308; Wed, 08 Apr 2026 15:49:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAV9Q-0004br-Ho for xen-devel@lists.xenproject.org; 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Message-ID: Date: Wed, 8 Apr 2026 16:48:47 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] x86/hap: Wait for remote CPUs during TLB flush To: Jan Beulich Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <20260401163521.3603665-1-ross.lagerwall@citrix.com> <20260401163521.3603665-2-ross.lagerwall@citrix.com> Content-Language: en-US From: Ross Lagerwall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: LNXP265CA0085.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:76::25) To CH8PR03MB8274.namprd03.prod.outlook.com (2603:10b6:610:2ba::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8274:EE_|BY5PR03MB5220:EE_ X-MS-Office365-Filtering-Correlation-Id: e44d8523-396c-4236-90fa-08de95865b95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016|22082099003|56012099003|18002099003; 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Adjust the call here to retain the existing behaviour so it >> continues to wait for the remote CPUs to VMExit. > > Doesn't this go too far though? IOW wouldn't we better make the "wait" > parameter a tristate then? From what I can see, the current wait == 0 behaviour only exists as a limitation of the implementation: The local CPU needs to wait for all the remote CPUs to have read "func" and "info" before dropping the lock to avoid a race condition. With that limitation removed, I don't see a valid reason to maintain this beahviour as an option, though I could be convinced otherwise. > > As to the semantic change, peeking at patch 2 I don't see you discussing > the safety of doing so for the several other callers that also pass 0 > right now. > I did audit the other callers (including via smp_call_function() and on_each_cpu()) and I believe they are all fine as is. I can update the commit message to say something along these lines. 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AJvYcCUpwUlB37Yb+QuNUB0+7kNcfaIaQelQ1hyh2/cGLtLEVYoywl0d6h0E3TcnZYGhhhfWKLvkMGyTOrs=@lists.xenproject.org X-Gm-Message-State: AOJu0YwNtNCap4dU/3zufgYqbvLjY9bTsZY1+ELT07BpzUK8j7BwkO0W Mieg3sjx/oPL23nzCXjgfGvObv1ubeqYrAYOqCYt2J8ODXrfegxnzJfErbTTIvinMg== X-Gm-Gg: AeBDies6w7alz5+KGaATM9E7K6yQHqFNehXpIeQc7fnol/HdUL/BLMUTElwQMyjSN1s dB1745E5EurrP4YsA74lHDSdwGJTWh4vHmDz+Dp6IAfDKLF0nSMlusOAg4NabxNAKM9yHWElpy2 hjPLqDfYPH2PrPBCSVUTb12StuE1HcjvQ0o+05bcdsgvU+MGKJJ5qfRIyjRkLCFvlMi5tj8wg7G QyT9mBqMgMaagw6PuR3MAdD3Nmme+yHpsMD086gpzieFuC3l/ckOPltbQZg05AHeESxyV4KF9cx AN5j6cKvSGv815l0e+N3iCtURposG2Kd93FSkQJ0PT1RpkfrNMQYUnH6apwljhy1lmZP8MxYXbe 0ocBotyMzSDXIK3v5TOuyw+mgb0swOAThSbdMdvpGrhzHhELdHqY0QHHvvrOF2nBAjUamrlQQOc dAyTkfQFg2gE21h1xEoRkp2Xw+bg3BBE0q5QaOy7QbOgQhQYuP5FuQUS68TuBPqoIY6lUA0FwVh A+XJPVriP8mha4= X-Received: by 2002:a05:600c:548d:b0:485:3423:727d with SMTP id 5b1f17b1804b1-488cd068ce8mr3762285e9.26.1775664692269; Wed, 08 Apr 2026 09:11:32 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 18:11:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] xen/smp: Rewrite on_selected_cpus() to be lockless To: Ross Lagerwall Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20260401163521.3603665-1-ross.lagerwall@citrix.com> <20260401163521.3603665-3-ross.lagerwall@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260401163521.3603665-3-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775664692-B2B3851B-B2D308B2/0/0 X-purgate-type: clean X-purgate-size: 4574 On 01.04.2026 18:35, Ross Lagerwall wrote: > --- a/xen/common/smp.c > +++ b/xen/common/smp.c > @@ -24,13 +24,15 @@ > /* > * Structure and data for smp_call_function()/on_selected_cpus(). > */ > -static DEFINE_SPINLOCK(call_lock); > -static struct call_data_struct { > +struct call_data_struct { > void (*func) (void *info); > void *info; > int wait; > - cpumask_t selected; > -} call_data; > + cpumask_t selected __cacheline_aligned; > +}; > + > +DEFINE_PER_CPU(struct call_data_struct, call_data); > +static cpumask_t tasks; Only first pass feedback for now (I still need to go over all of this more thoroughly). Having cpumask_t variables anywhere (not just on the stack, where they're particularly problematic) isn't very nice. Can this become cpumask_var_t? (We really also need to deal with the one in smp_call_function(), for example.) > @@ -50,55 +52,84 @@ void on_selected_cpus( > void *info, > int wait) > { > + struct call_data_struct *data; > + unsigned int cpu = smp_processor_id(); > + > ASSERT(local_irq_is_enabled()); > ASSERT(cpumask_subset(selected, &cpu_online_map)); > > - spin_lock(&call_lock); > + if ( cpumask_empty(selected) ) > + return; > + > + data = &this_cpu(call_data); > > - cpumask_copy(&call_data.selected, selected); > + if ( !data->wait ) > + { > + /* Wait for any previous async call to complete */ > + while ( !cpumask_empty(&data->selected) ) > + cpu_relax(); > + > + cpumask_clear_cpu(cpu, &tasks); Since you set this bit again almost immediately, the above can only be to make sure that ... > + } > > - if ( cpumask_empty(&call_data.selected) ) > - goto out; > + data->func = func; > + data->info = info; > + data->wait = wait; ... these updates and ... > - call_data.func = func; > - call_data.info = info; > - call_data.wait = wait; > + smp_wmb(); > > - smp_send_call_function_mask(&call_data.selected); > + cpumask_copy(&data->selected, selected); ... and this copying happen with the bit clear. Don't you need another barrier then, though (between cpumask_clear_cpu() and the writes)? Further isn't the barrier you add coming too early? While the bit in tasks is clear, nobody's going to look at ->selected. Doesn't the barrier need to live here, to isolate from ... > - while ( !cpumask_empty(&call_data.selected) ) > - cpu_relax(); > + cpumask_set_cpu(cpu, &tasks); ... this? > -out: > - spin_unlock(&call_lock); > + smp_send_call_function_mask(&data->selected); > + > + if ( wait ) > + { > + while ( !cpumask_empty(&data->selected) ) > + cpu_relax(); > + > + cpumask_clear_cpu(cpu, &tasks); > + } > } > > void smp_call_function_interrupt(void) > { > - void (*func)(void *info) = call_data.func; > - void *info = call_data.info; > unsigned int cpu = smp_processor_id(); > - > - if ( !cpumask_test_cpu(cpu, &call_data.selected) ) > - return; > + unsigned int i; > + struct call_data_struct *data; > + void (*func)(void *info); > + void *info; Please move into the loop's scope whatever can be moved there. > irq_enter(); > > - if ( unlikely(!func) ) > - { > - cpumask_clear_cpu(cpu, &call_data.selected); > - } > - else if ( call_data.wait ) > - { > - (*func)(info); > - smp_mb(); > - cpumask_clear_cpu(cpu, &call_data.selected); > - } > - else > + for_each_cpu ( i, &tasks ) > { > - smp_mb(); > - cpumask_clear_cpu(cpu, &call_data.selected); > - (*func)(info); > + data = &per_cpu(call_data, i); > + > + if ( !cpumask_test_cpu(cpu, &data->selected) ) > + continue; > + > + smp_rmb(); This barrier looks as if it also needs to move (up). Jan > + func = data->func; > + info = data->info; > + > + if ( unlikely(!func) ) > + { > + cpumask_clear_cpu(cpu, &data->selected); > + } > + else if ( data->wait ) > + { > + (*func)(info); > + smp_mb(); > + cpumask_clear_cpu(cpu, &data->selected); > + } > + else > + { > + smp_mb(); > + cpumask_clear_cpu(cpu, &data->selected); > + (*func)(info); > + } > } > > irq_exit(); From xen-devel-bounces@lists.xenproject.org Wed Apr 08 16:36:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 16:36:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276336.1561844 (Exim 4.92) (envelope-from ) id 1wAVsh-0004UR-QE; Wed, 08 Apr 2026 16:35:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276336.1561844; Wed, 08 Apr 2026 16:35:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAVsh-0004UK-Mg; Wed, 08 Apr 2026 16:35:55 +0000 Received: by outflank-mailman (input) for mailman id 1276336; Wed, 08 Apr 2026 16:35:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAVsf-0004UE-Un for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 16:35:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAVsd-006NwQ-BB for xen-devel@lists.xenproject.org; Wed, 08 Apr 2026 18:35:52 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d683b6-2eae-0a2a0a5409dd-0a2a4501ddc8-34 for ; Wed, 08 Apr 2026 18:35:52 +0200 Received: from [209.85.128.67] (helo=mail-wm1-f67.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d683e8-6fc9-0a2a45010019-d1558043d0db-3 for ; Wed, 08 Apr 2026 18:35:52 +0200 Received: by mail-wm1-f67.google.com with SMTP id 5b1f17b1804b1-4889e045bc6so113215e9.2 for ; Wed, 08 Apr 2026 09:35:52 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. [78.146.242.105]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d1e4d2738sm61201338f8f.24.2026.04.08.09.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2026 09:35:51 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1775666152; x=1776270952; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=UN00C5w8mxxKS6BZsJBcm/d7Q6sznRAtUQSRYmu6l/8=; b=Bp8npXhrI4YjYq1Bj6SQMBRI4jk4GhUQ/bT87MLgs9i1kSXieNxUyGYxxlprzGGm4z UXLIYHkMDsY7VqmBc7QvxApxBCYHp5odkIKzi/5R8sk9M87PAtn1ld9NeqXvLmIYfSdp F0BjBiT/T+9zDv57DP8vlz1rhpZnuMz+XIXCM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775666152; x=1776270952; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=UN00C5w8mxxKS6BZsJBcm/d7Q6sznRAtUQSRYmu6l/8=; b=ZR+aRKt+bdcJtGJKdU8FoyrGJvge1UK650N65Uk0Yv5X69y/9NLFEfZISYnGf/uTEc sTeeUstHwqi6dLHT9JVWjjrF2AzT/PvrbkPKDo9tYzCEbDydVDcv3gXZvO35EMbMi1ye 0YXY/tV8n+Br+mINsB/VdibXN/9qGTG51lqU9IAbjydZhKF7uO2RjW0zV3T7h1ifO31E ZTB8aAnERxilWyP8N5dvjnvrlQbuIp3SHS/E959C/lNtiaWAKiUkHWrC7svdfwwhENrR NAGG3erFGL6Rsf/3PmE+BObNsdNDRLmMVGQkk/HJioSmP4Hsdpgqb9MNNFbPc9cfV/rn fiRw== X-Gm-Message-State: AOJu0YwIbcE/GLeP8PghA9WGlammfBxP/8wKJWDeh9xr/d1aHgwcFs8l /r6a9nZS2wYhN5EWllAC7nKN/34I20CBCDcDM6kuCOlzTSow+DBKyuqs49oQipeKVvyLjoEmgUJ V3+vKbJFs6hf4 X-Gm-Gg: AeBDievE6OBve+oCRS7tpDatpaX1F+8sEkuEA6lc6BmrV/jeGI7c7j99ZL8EYukw0Nk 4Qdoptyx6PMLUvXK5Wj5P61EW7n3L9Qe50cnRWpy3U/ewPSnobw8N78JQ9N70gHbdJ18ioonXjV dBaz7Eb+wwKlCsU8qvdKzphTGtNlAN1Rm6HXzfTCJVDkCYy5NN0tnIrZ4G4NR2+tm/+8hT9wcxU Zhwi+YcsmxfNviDW7DhDyBzAhMBRLZdQMrYZa3E3KVEb8Gypon4xoipDzEjwhz6Qa8y5HjKJ+Ef UTD4z9MB5U8HdY/Y8pzdkB82OHcsbE98WRFq45f1BrjVXxZpx3rogBOzrdh2nhitfOEy8ZpAfxP iLs6U7bddZcIGk1NrfAQKGagiSXaoVdvFbOpUo1236XCAvS7CPJi8GobkdzCtiVZxAMGC9F130K 8nGJmHVF+C7gv/BbGvlqi8XFHfwV6fBXdnk4xDTVF3Gb+CXDkIlLGdDCvk39bi6ZGReiCVCYk5i L/v X-Received: by 2002:a05:600c:858c:b0:488:9439:880d with SMTP id 5b1f17b1804b1-488cd087322mr5197785e9.29.1775666151565; Wed, 08 Apr 2026 09:35:51 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH] x86/gen-cpuid: Split deep_features by vendor Date: Wed, 8 Apr 2026 17:35:49 +0100 Message-Id: <20260408163549.135245-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1775666152-150E0185-2BB1BED4/0/0 X-purgate-type: clean X-purgate-size: 8689 AMD CPUs need LKGS depend on NSCB, but this dependency cannot be unconditional as it will break FRED on Intel CPUs which don't need to enumerate the absence of a bug. The deep dependecy logic is formed of two parts; a deep_features bitmap indicating which features have dependencies, and deep_deps; the mapping of feature to dependent features. Given that NSCB is an unconnected root of a dependency, we can have the row in deep_deps and conditionally exclude it the deep_features level. Rename INIT_DEEP_FEATURES to INIT_ALL_DEEP_FEATURES and add AMD and INTEL forms too. In both xc_cpuid_apply_policy() and sanitise_featureset(), choose the appropriate {amd,intel}_deep_features based on vendor. Introduce the NSCB <-> LKGS dependency and exclude the NSCB row from intel_deep_features. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie Only compile tested so far. --- tools/libs/guest/xg_cpuid_x86.c | 14 +++++++++++++- xen/arch/x86/cpu-policy.c | 16 ++++++++++++++-- xen/arch/x86/lib/cpu-policy/cpuid.c | 2 +- xen/include/public/arch-x86/cpufeatureset.h | 2 +- xen/tools/gen-cpuid.py | 20 +++++++++++++++++--- 5 files changed, 46 insertions(+), 8 deletions(-) diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x86.c index 0db6d77cd801..0b00672c4762 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -650,9 +650,12 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, if ( featureset ) { + static const uint32_t amd_deep_features[] = INIT_AMD_DEEP_FEATURES; + static const uint32_t intel_deep_features[] = INIT_INTEL_DEEP_FEATURES; + + const uint32_t *deep_features; uint32_t disabled_features[FEATURESET_NR_ENTRIES], feat[FEATURESET_NR_ENTRIES] = {}; - static const uint32_t deep_features[] = INIT_DEEP_FEATURES; unsigned int i, b; /* @@ -670,6 +673,15 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, memcpy(feat, featureset, sizeof(*featureset) * user_len); + /* + * At the time of writing, amd_deep_features contains one extra + * dependency over intel for a "hardware no longer has this bug" bit. + */ + if ( p->policy.x86_vendor & (X86_VENDOR_AMD|X86_VENDOR_HYGON) ) + deep_features = amd_deep_features; + else + deep_features = intel_deep_features; + /* Disable deep dependencies of disabled features. */ for ( i = 0; i < ARRAY_SIZE(disabled_features); ++i ) disabled_features[i] = ~feat[i] & deep_features[i]; diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae435..2228c52ffc79 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -39,7 +39,8 @@ static const uint32_t __initconst hvm_shadow_def_featuremask[] = INIT_HVM_SHADOW_DEF_FEATURES; static const uint32_t __initconst hvm_hap_def_featuremask[] = INIT_HVM_HAP_DEF_FEATURES; -static const uint32_t deep_features[] = INIT_DEEP_FEATURES; +static const uint32_t amd_deep_features[] = INIT_AMD_DEEP_FEATURES; +static const uint32_t intel_deep_features[] = INIT_INTEL_DEEP_FEATURES; static const struct feature_name { const char *name; @@ -158,11 +159,21 @@ static void zero_leaves(struct cpuid_leaf *l, static void sanitise_featureset(uint32_t *fs) { + const uint32_t *deep_features; /* bitmap_for_each() uses unsigned longs. Extend with zeroes. */ uint32_t disabled_features[ ROUNDUP(FSCAPINTS, sizeof(unsigned long)/sizeof(uint32_t))] = {}; unsigned int i; + /* + * At the time of writing, amd_deep_features contains one extra dependency + * over intel for a "hardware no longer has this bug" bit. + */ + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD|X86_VENDOR_HYGON) ) + deep_features = amd_deep_features; + else + deep_features = intel_deep_features; + for ( i = 0; i < FSCAPINTS; ++i ) { /* Clamp to known mask. */ @@ -1110,7 +1121,8 @@ static void __init __maybe_unused build_assertions(void) BUILD_BUG_ON(ARRAY_SIZE(pv_max_featuremask) != FSCAPINTS); BUILD_BUG_ON(ARRAY_SIZE(hvm_shadow_max_featuremask) != FSCAPINTS); BUILD_BUG_ON(ARRAY_SIZE(hvm_hap_max_featuremask) != FSCAPINTS); - BUILD_BUG_ON(ARRAY_SIZE(deep_features) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(amd_deep_features) != FSCAPINTS); + BUILD_BUG_ON(ARRAY_SIZE(intel_deep_features) != FSCAPINTS); /* Find some more clever allocation scheme if this trips. */ BUILD_BUG_ON(sizeof(struct cpu_policy) > PAGE_SIZE); diff --git a/xen/arch/x86/lib/cpu-policy/cpuid.c b/xen/arch/x86/lib/cpu-policy/cpuid.c index 3162e795bc21..73ea68690b4a 100644 --- a/xen/arch/x86/lib/cpu-policy/cpuid.c +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c @@ -293,7 +293,7 @@ void x86_cpu_policy_clear_out_of_range_leaves(struct cpu_policy *p) const uint32_t *x86_cpu_policy_lookup_deep_deps(uint32_t feature) { - static const uint32_t deep_features[] = INIT_DEEP_FEATURES; + static const uint32_t deep_features[] = INIT_ALL_DEEP_FEATURES; static const struct { uint32_t feature; uint32_t fs[FEATURESET_NR_ENTRIES]; diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index c4d3276f2f89..acee5a0544a0 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -326,7 +326,7 @@ XEN_CPUFEATURE(NO_NEST_BP, 11*32+ 0) /*A No Nested Data Breakpoints */ XEN_CPUFEATURE(FS_GS_NS, 11*32+ 1) /*S| FS/GS base MSRs non-serialising */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ XEN_CPUFEATURE(VERW_CLEAR, 11*32+ 5) /*!A| VERW clears microarchitectural buffers */ -XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */ +XEN_CPUFEATURE(NSCB, 11*32+ 6) /*!A Null Selector Clears Base (and limit too) */ XEN_CPUFEATURE(AUTO_IBRS, 11*32+ 8) /*S Automatic IBRS */ XEN_CPUFEATURE(AMD_FSRS, 11*32+10) /*A Fast Short REP STOSB */ XEN_CPUFEATURE(AMD_FSRC, 11*32+11) /*A Fast Short REP CMPSB */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 13d85a43482a..a0fff6c45676 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -344,6 +344,12 @@ def crunch_numbers(state): # The ARCH_CAPS CPUID bit enumerates the availability of the whole register. ARCH_CAPS: feat_range(RDCL_NO, RDCL_NO + 63), + # AMD-only special case. NullSelectorClearsBase is really a "hardware + # doesn't have this bug any more" bit. All FRED-capable hardware has + # NSCB properties, so disallow configurations which would cause LGKS + # to behave unexpectedly. + NSCB: [LKGS], + # The behaviour described by RRSBA depend on eIBRS being active. EIBRS: [RRSBA], @@ -383,9 +389,13 @@ def crunch_numbers(state): state.deep_deps[feat] = seen - state.deep_features = deps.keys() state.nr_deep_deps = len(state.deep_deps.keys()) + # deep_features is split per vendor to exlcude certain rows from + # processing. + state.all_deep_features = set(deps.keys()) + state.intel_deep_features = state.all_deep_features - set((NSCB, )) + # Calculate the bitfield name declarations. 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For those purposes, guest-only entry points do > not need to record that value. > > To keep the saving code simple, record our own SSP that corresponds to > an exception frame, pointing to the top of the shadow stack counterpart > of what the CPU has saved on the regular stack. Consuming code can then > work its way from there. > > Signed-off-by: Jan Beulich > --- > For PUSH_AND_CLEAR_GPRS and POP_GPRS, putting the new field right next to > the error code isn't entirely nice; putting it ahead of %r15 would entail > other changes, though. An option may be to not make SSP handling part of > the macros in the first place. Thoughts? I have a firm dislike for SAVE/RESTORE_ALL, both for their substantial complexity/inefficiency, and mixing of unrelated tasks. I have several series trying to purge them.  I suppose I really ought to try and finish this off properly. While classing SSP as a "register" is probably fine, the ssp= parameter (and particular it's asymmetric nature) is on the wrong side of the "complex" argument IMO. > For POP_GPRS, does it really matter that it doesn't alter EFLAGS? Yes.  The SYSCALL fix for one (reviewed, but waiting on final testing before I commit). Then the VT-x code when swapped to use POP_GPRS. To take a step back, you say that putting it ahead of %r15 would entail other changes.  What changes? The resulting asm would be far cleaner.  It would be an rdssp;push on one side, and a pop into any register on the other side.  Furthermore, given that the ssp= doesn't exclude storing it for some user frames, just store it for all.  It's one push/pop into a hot cacheline, and makes a substantial reduction in complexity. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:03:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:03:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276362.1561861 (Exim 4.92) (envelope-from ) id 1wAWJI-00012Q-2M; Wed, 08 Apr 2026 17:03:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276362.1561861; Wed, 08 Apr 2026 17:03:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAWJH-00012J-Vy; Wed, 08 Apr 2026 17:03:23 +0000 Received: by outflank-mailman (input) for mailman id 1276362; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: da4f20a2-a374-4e51-eaeb-08de9590bb52 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2026 17:03:18.2615 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: aKtsO1I2IQ4qez60gJsT5SvoCAMNRV0S+uw5CXSFw+jJNc1BVHWwFiFHMabOt/5Ufe4+JXbkr936iOFVmjIEA7Iy/PWFCFuiViHx1piZw9s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR03MB7657 X-purgate-ID: tlsNG-d62444/1775667801-B62E9185-27CF83AC/0/0 X-purgate-type: clean X-purgate-size: 2951 In scif_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally writing TIE|RIE|REIE into the Serial Control Register (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, RX data ready, receive error) with no handler registered to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. The fix adds an early return inside the error branch. The interrupt-enable write to SCSCR is skipped entirely when no handler is registered. SCIF TX continues to operate correctly after this change. The Xen serial framework never calls serial_async_transmit() for SCIF, so port->txbuf is always NULL. This causes __serial_putc() to take the synchronous finite-capacity path, which polls the SCFSR_TDFE hardware flag directly and does not depend on the interrupt mechanism. As a secondary clean-up, the hardware error-flag clearing sequence is moved to before the setup_irq() call so that error bits accumulated since init_preirq() are cleared unconditionally, regardless of whether IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev --- xen/drivers/char/scif-uart.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 888821a3b8..673a2d3800 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct seri= al_port *port) uart->irqaction.name =3D "scif_uart"; uart->irqaction.dev_id =3D port; =20 - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", - uart->irq); - /* Clear all errors */ if ( scif_readw(uart, params->status_reg) & params->error_mask ) scif_writew(uart, params->status_reg, ~params->error_mask); if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", + uart->irq); + /* + * If the IRQ handler could not be installed (setup_irq failed), + * do not enable TX/RX or error interrupts. Serial transmit will + * fall back to polling mode. + */ + return; + } + /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | params->irq_flags); --=20 2.43.0 base-commit: 599e3daf63ee2a83bb7096c452aa05b4aea84f2f branch: amoi_dfmea_scif= From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:23:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:23:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276424.1561895 (Exim 4.92) (envelope-from ) id 1wAWd4-0005QW-6H; Wed, 08 Apr 2026 17:23:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276424.1561895; Wed, 08 Apr 2026 17:23:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAWd4-0005QN-3f; Wed, 08 Apr 2026 17:23:50 +0000 Received: by outflank-mailman (input) for mailman id 1276424; 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Wed, 08 Apr 2026 17:23:45 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775669025; x=1775939025; bh=bL/Y0h09vhas0clUhCqZuQCPZsSmUUKUpgqhUdmmhks=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=AkuGAWul21I7hqPr7vG5L4oaDg6JuP/l8JnQqIRW+1hRaONFUZYgaUiXOqD1FHOmb IcNy4U/BqDnZBrwgUOCBBn5mLtX/o8nvvI+mhIExq/RiFkWfDik8LnDYCo2loIYYEp O9loGTWF3FLrC1oquRTlW5UZdYFhNoJV6ztyNt9BXvxri6A0awKvK1icNQUdTd2Z+E S1sLVF0pqP7CDGdXQSl8J+Vzi85Mc3QKuOOodt8Mlj2cS/AbUz4qlyrpBxE1P1Xsmv 5v046kdgKnjF70Xbvoz3qqOADi9sJDGxE99ifZCxZHs/qpP+HSywSGNRHwNhr+Tiu9 gn+6Tlz8RoQSA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775669025; x=1775929525; i=thierry.escande@vates.tech; bh=bL/Y0h09vhas0clUhCqZuQCPZsSmUUKUpgqhUdmmhks=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=a2BE5wjKAyRaDbTphxwyPGO/DgF0jM9cK+4dPpThdNIDVOsQt45QMBSjDxTOV6Lvc abdDRqsCDYx53WSGv7a3G03uAB4rZWYqqbfyR9hrc+8t6OlmGEiV0vtKYdh3BM5aa8 HTNg43kZT8tKMbgb0nEJIEZbM1PvRV4S7V4mO2VuQg+T7RbTTSD/htyzg8R10eo/g3 rh1dY17f8P29zcAYNv+scOh5yW++S/swbpxaXaXBO4lrbDV8PS4zxKa3LpyzTUJrFm yoPtGBC4s1FRdFAUMAfKoF/puW7MxvCqVmcfXcMWbyMzzqQ+npwtrhXY3YmCI39ITD C3uCg8i8FMBaw== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=201/3]=20xl:=20Add=20pci=20device=20hotplug=20option?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775669024628 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260408172320.539750-2-thierry.escande@vates.tech> In-Reply-To: <20260408172320.539750-1-thierry.escande@vates.tech> References: <20260408172320.539750-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.a9ac9385157d4fe2811a2f8d5aeda822?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260408:md Date: Wed, 08 Apr 2026 17:23:45 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775669028-2E74A152-EAE45717/0/0 X-purgate-type: clean X-purgate-size: 2895 This option is used to passthrough PCI devices using the Qemu command line (-device driver,...) instead of the QMP hot-plug mechanism. This is needed for Q35 support since its PCI root bus doesn't support hotplugging. If not specified, the default behavior is to use hotplug via QMP. Signed-off-by: Thierry Escande --- tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 ++ tools/xl/xl_parse.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl index a7893460f0..aca0e93793 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -922,6 +922,7 @@ libxl_device_pci = Struct("device_pci", [ ("seize", bool), ("rdm_policy", libxl_rdm_reserve_policy), ("name", string), + ("hotplug", bool), ]) libxl_device_rdm = Struct("device_rdm", [ diff --git a/tools/libs/util/libxlu_pci.c b/tools/libs/util/libxlu_pci.c index 294482c6d7..f6440c878b 100644 --- a/tools/libs/util/libxlu_pci.c +++ b/tools/libs/util/libxlu_pci.c @@ -192,6 +192,8 @@ int xlu_pci_parse_spec_string(XLU_Config *cfg, libxl_device_pci *pci, name_present = true; pci->name = strdup(val); if (!pci->name) ret = ERROR_NOMEM; + } else if (!strcmp(key, "hotplug")) { + pci->hotplug = atoi(val); } else { XLU__PCI_ERR(cfg, "Unknown PCI_SPEC_STRING option: %s", key); ret = ERROR_INVAL; diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 48c72dce9c..7ea2a76662 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -1361,6 +1361,7 @@ void parse_config_data(const char *config_source, int pci_msitranslate = 0; int pci_permissive = 0; int pci_seize = 0; + int pci_hotplug = 1; int i, e; int num_llc_colors; int num_xs_quota; @@ -1699,6 +1700,9 @@ void parse_config_data(const char *config_source, if (!xlu_cfg_get_long (config, "pci_seize", &l, 0)) pci_seize = l; + if (!xlu_cfg_get_long (config, "pci_hotplug", &l, 0)) + pci_hotplug = l; + if (!xlu_cfg_get_string(config, "rdm", &buf, 0)) { libxl_rdm_reserve rdm; if (!xlu_rdm_parse(config, &rdm, buf)) { @@ -1720,6 +1724,7 @@ void parse_config_data(const char *config_source, pci->power_mgmt = pci_power_mgmt; pci->permissive = pci_permissive; pci->seize = pci_seize; + pci->hotplug = pci_hotplug; /* * Like other pci option, the per-device policy always follows * the global policy by default. -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:23:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:23:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276423.1561887 (Exim 4.92) (envelope-from ) id 1wAWcy-0005D6-W2; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775669020; x=1775939020; bh=xxNIkKDN7lXNq1YcBt2lBjJMfrZZXPZ7kai8JheAc4c=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=qiMdTQWE1bdnulNELNeIvu60g+5c5C6AgFZqutAvC6wZvfwhfR77YwHqQlAn11SwO 1OgkSIZomjfhOHNtNLk1WRAc8u0TBhNE7Mq02a2Jnll4ImFPI1SAA4+bIA3dbwZZYw fI3FVEc81NkRsjPyuN1/ieY12O/QxVWqVUmQyXhiobXZY5HbK0if6F1i1/QglSOLQy KS3Z4rlc15OTrqWnsL+Q9N+fO4zGcHAxV6gp/HcAnHELIrvcGMH4eMNGJz94hR3zqg 92F+uotoUBU0CSOiSgoF1/+PHJgu0r5jTKIXyj8OfWHGc2ByXIHvDIllNWwNb8q0qJ xC/1GKK6cVcBg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775669020; x=1775929520; i=thierry.escande@vates.tech; bh=xxNIkKDN7lXNq1YcBt2lBjJMfrZZXPZ7kai8JheAc4c=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=cRDh1wQGpCSsGYEveRboT3EZRfkLWw28GtuggH8cRt18dHs1zXRNAvDm9xftmdlXB 30yxtc9b5N1EOfTscxGui7UR8G+/VhfQYzI9mVmVpXYJYlzOIo/Rnd41mbDKK0REuo oPtQdFxzq+7NEkiZ1dCWNpWjr4VE1g888HpQkMRPP+45NZtH0hF05nL0S2G71728Hg GxJHz9idyd+EPgqvW5QdzEztsduUG/uTTj0vtLULmTxJHifINmuv1jKQeUHcwmBzzO fEk+ElhPnC3ICzJlJngzYzrJeCZU56YTubFX1Oz4t2Opr3LkeEJrXsyh3d75J2PRzn y6bZ4Cih1mPEg== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=200/3]=20xl:=20Allow=20PCI=20devices=20to=20be=20passthrough'd=20via=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775669019256 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260408172320.539750-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.c66f53c3790a424abefe018ecad7fdfe?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260408:md Date: Wed, 08 Apr 2026 17:23:40 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775669021-54D5F152-527CBC20/0/0 X-purgate-type: clean X-purgate-size: 2481 This series adds support for a new 'hotplug' option for PCI devices to be passthrough'd to guests. The current mechanism for device passthrough uses QMP device_add command to hot-plug PCI devices to the guest Qemu instance. This is an issue for guests running on Q35 chipset (preliminary support posted at [1]) since the Q35 PCI root bus does not support hotplug. Devices could be hotplugged to a secondary PCI bus but Xen only support 1 PCI bus for now. The 'hotplug' option allows to control how devices are attached to the guest, either by using the legacy QMP mechanism (this is the default) or by passing it directly to the Qemu command line using xen-pci-passthrough device. Example usage in cfg file: pci = [ "00:03.0,seize=1,hotplug=0" ] Since Qemu -device option accepts parameters in json format, this patchset adds a new internal function libxl__device_pci_get_qmp_json() that generates the device json object used for both QMP hotplug and command line passing. Also, the function libxl_pci_assignable() is made available from libxl.h for access in libxl_dm.c. I don't know if it's ok to make it public or if it should stay private. Maybe it should be renamed as libxl_device_pci_assignable() to match the other PCI device APIs. This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. Disabling the hotplug mechanism might be made mandatory for Q35 machines later, once Q35 support is merged upstream. [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.escande@vates.tech/ Thierry Escande (3): xl: Add pci device hotplug option libxl: Allow PCI device passthrough using -device Qemu command line docs: provide description for pci hotplug option docs/man/xl-pci-configuration.5.pod | 17 ++++++++++++ docs/man/xl.cfg.5.pod.in | 6 +++++ tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 31 ++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 2 ++ tools/libs/light/libxl_pci.c | 41 ++++++++++++++++++++++------- tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 ++ tools/xl/xl_parse.c | 5 ++++ 9 files changed, 96 insertions(+), 10 deletions(-) -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:23:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:23:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276425.1561905 (Exim 4.92) (envelope-from ) id 1wAWdA-0005hj-DW; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775669032; x=1775939032; bh=7/8Qd+P7SPVDgY0eBLO5nKimQuCthoxn0Jd92VJL7wU=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=jZazIJ0jtqK0cqYE93+/V8XeLf8Yjrc5neEFcG92fAIu8nH8ixZBnxhOpquNEYBx4 TQuEwPv9OIRSe2KRYM1bshjh9bkhVymd9MimGM2Nb8CgzHKCy0Q30hJ9TwP0qAqPPS 5tmEvbcIGjYzB5nOrss/SBrI/m9MY1Hhi092Tdl+Xrx0SpnkuylvvwdBK8aYCG/UHb BZYdrwXLHhBd3nozJ+kKVV4oZse2vIovxbdlhbFaE4Bayk8rLmO/1ufffG+qt9qFQb qZo+1/KGWp3124sgN76Ja+aftxu5hJIc045swJs/c/4otr5aOMjNk0pQanLhOMPV+w qP3JlWNKH0Awg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775669032; x=1775929532; i=thierry.escande@vates.tech; bh=7/8Qd+P7SPVDgY0eBLO5nKimQuCthoxn0Jd92VJL7wU=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=E3itFUbe/nZOklJZtVcEesSu0M7DPkwzIAzJmgtTf2Nd3p9lMXWJSGOtPLZ9sWAqk b4ZUumkX/jypTAv1JETOqF6U7q3o6ZAqLxBQkItJfmjbaG0WbMLZ/9fukQm85voWGW ub6r6dAstkniBpjxcstjr1kezyCwBhilaBf55RsjFF9N11EVHsDf0DN/wk9zwc5WNr /P6lW0N2SsAo6tnkaKkXYUy3EkLKVEXEq3YG3rD6YulGlB7gaE4N53PpzEhv9F1Wbt uH/7CyuMVWoMpL2yj1uIk0PdsZoRJF5XOed7+MkwdAMu+vqS76MAYGXrTWTnlniTB+ pacSjYaac9v3w== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=202/3]=20libxl:=20Allow=20PCI=20device=20passthrough=20using=20-device=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775669030410 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260408172320.539750-3-thierry.escande@vates.tech> In-Reply-To: <20260408172320.539750-1-thierry.escande@vates.tech> References: <20260408172320.539750-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.c0022b9fc07d4103bf9af3bb4037bf57?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260408:md Date: Wed, 08 Apr 2026 17:23:52 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775669034-83D4741E-F54737BC/0/0 X-purgate-type: clean X-purgate-size: 7318 This change makes use of the new option 'hotplug' for host PCI devices passthrough'd to the guest. If hotplug=0 is used in the pci device configuration table, the device will be attached to the guest using the Qemu command line as '-device xen-pci-passthrough,hostaddr=...' The host device configuration is passed to the -device option as a json array, just like it's done for hotplug using QMP. The json array is created by a new internal function libxl__device_pci_get_qmp_json() that is also used by pci_add_qmp_device_add(). Then, instead of sending the 'device_add' command, the device_add callback is called to perform the 'query-pci' check to make sure the passthrough'd device is present. In the same way at shutdown, the device is not removed using QMP and only the pci_remove_done() function is called. As with QMP, the use of the 'hotplug=0' option honors the 'seize' option by adding the PCI device to the assignable list if needed. Example use: pci = [ "00:03.0,seize=1,hotplug=0" ] Signed-off-by: Thierry Escande --- tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 31 +++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 2 ++ tools/libs/light/libxl_pci.c | 41 +++++++++++++++++++++++-------- 4 files changed, 65 insertions(+), 10 deletions(-) diff --git a/tools/include/libxl.h b/tools/include/libxl.h index 7c098edab6..66fb07ad67 100644 --- a/tools/include/libxl.h +++ b/tools/include/libxl.h @@ -2666,6 +2666,7 @@ int libxl_device_pci_assignable_add(libxl_ctx *ctx, libxl_device_pci *pci, int r int libxl_device_pci_assignable_remove(libxl_ctx *ctx, libxl_device_pci *pci, int rebind); libxl_device_pci *libxl_device_pci_assignable_list(libxl_ctx *ctx, int *num); void libxl_device_pci_assignable_list_free(libxl_device_pci *list, int num); +bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci); /* CPUID handling */ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str); diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c index 511ec76a65..96bb620f87 100644 --- a/tools/libs/light/libxl_dm.c +++ b/tools/libs/light/libxl_dm.c @@ -1169,6 +1169,37 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, } } } + + if (guest_config->num_pcidevs) { + libxl_device_pci *pci; + libxl__json_object *qmp_json; + const char *json_str; +#ifndef HAVE_LIBJSONC +# error Missing JSON library +#endif + json_object *jso = NULL; + + for (i = 0; i < guest_config->num_pcidevs; i++) { + libxl_ctx *ctx = libxl__gc_owner(gc); + pci = &guest_config->pcidevs[i]; + + if (pci->hotplug) + continue; + + if (!libxl_pci_assignable(ctx, pci) && pci->seize) { + rc = libxl_device_pci_assignable_add(ctx, pci, 1); + if (rc) + return rc; + } + qmp_json = libxl__device_pci_get_qmp_json(gc, pci); + rc = libxl__json_object_to_json_object(gc, &jso, qmp_json); + if (rc) + return rc; + json_str = json_object_to_json_string_ext(jso, + JSON_C_TO_STRING_PLAIN); + flexarray_vappend(dm_args, "-device", json_str, NULL); + } + } } if (libxl_defbool_val(b_info->u.hvm.nographic) && (!sdl && !vnc)) { diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h index b65e0064b9..06b5a14409 100644 --- a/tools/libs/light/libxl_internal.h +++ b/tools/libs/light/libxl_internal.h @@ -1729,6 +1729,8 @@ _hidden int libxl__device_pci_setdefault(libxl__gc *gc, uint32_t domid, libxl_device_pci *pci, bool hotplug); _hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, const libxl_domain_config *d_config); +_hidden libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci); /* from libxl_dtdev */ diff --git a/tools/libs/light/libxl_pci.c b/tools/libs/light/libxl_pci.c index 49d272d0de..3ef2c43412 100644 --- a/tools/libs/light/libxl_pci.c +++ b/tools/libs/light/libxl_pci.c @@ -1098,16 +1098,10 @@ out: pci_add_dm_done(egc, pas, rc); /* must be last */ } -static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci) { - STATE_AO_GC(pas->aodev->ao); libxl__json_object *args = NULL; - int rc; - - /* Convenience aliases */ - libxl_domid domid = pas->domid; - libxl_device_pci *pci = &pas->pci; - libxl__ev_qmp *const qmp = &pas->qmp; libxl__qmp_param_add_string(gc, &args, "driver", "xen-pci-passthrough"); @@ -1134,11 +1128,30 @@ static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) if (pci->permissive) libxl__qmp_param_add_bool(gc, &args, "permissive", true); + return args; +} + +static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +{ + STATE_AO_GC(pas->aodev->ao); + libxl__json_object *args = NULL; + int rc = 0; + + /* Convenience aliases */ + libxl_domid domid = pas->domid; + libxl_device_pci *pci = &pas->pci; + libxl__ev_qmp *const qmp = &pas->qmp; + + args = libxl__device_pci_get_qmp_json(gc, pci); + qmp->ao = pas->aodev->ao; qmp->domid = domid; qmp->payload_fd = -1; qmp->callback = pci_add_qmp_device_add_cb; - rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + if (pci->hotplug) + rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + else + pci_add_qmp_device_add_cb(egc, qmp, NULL, 0); if (rc) goto out; return; @@ -1509,7 +1522,7 @@ int libxl_device_pci_add(libxl_ctx *ctx, uint32_t domid, return AO_INPROGRESS; } -static bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) +bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) { libxl_device_pci *pcis; int num; @@ -1820,6 +1833,14 @@ static void do_pci_remove(libxl__egc *egc, pci_remove_state *prs) libxl_domain_type type = libxl__domain_type(gc, domid); libxl_device_pci *pci = &prs->pci; int rc, num; + + /* Passthrough'd device has been passed to Qemu command line so there is + * no need to remove it via QMP */ + if (!pci->hotplug) { + pci_remove_done(egc, prs, 0); + return; + } + pcis = libxl_device_pci_list(ctx, domid, &num); if (!pcis) { rc = ERROR_FAIL; -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:24:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:24:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276428.1561913 (Exim 4.92) (envelope-from ) id 1wAWdE-00060c-NW; Wed, 08 Apr 2026 17:24:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276428.1561913; Wed, 08 Apr 2026 17:24:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAWdE-00060V-Ka; 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charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775669037-AF122CD1-A241C7AF/0/0 X-purgate-type: clean X-purgate-size: 1877 This patch adds description for the 'hotplug' PCI option, allowing devices to be attached to the guest using the legacy QMP hotplug mechanism or by passing them to the Qemu command line using '-device'. Signed-off-by: Thierry Escande --- docs/man/xl-pci-configuration.5.pod | 17 +++++++++++++++++ docs/man/xl.cfg.5.pod.in | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/docs/man/xl-pci-configuration.5.pod b/docs/man/xl-pci-configuration.5.pod index 0691f06ad3..8b664173cb 100644 --- a/docs/man/xl-pci-configuration.5.pod +++ b/docs/man/xl-pci-configuration.5.pod @@ -166,6 +166,23 @@ dom0 without confirmation. Please use with care. =back +=item B=I + +=over 4 + +=item Description + +Tells L to use QMP hotplug mechanism to attach assignable device to +the guest, or to pass it via Qemu command line using +'B<-device xen-pci-passthrough,...>'. The default is to use the legacy QMP +mechanism. + +=item Default Value + +1 + +=back + =item B=I =over 4 diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 3aac0bc4fb..181aaffa0f 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -1230,6 +1230,12 @@ B<(HVM only)> Changes the default value of B for all PCI devices passed through to this VM. See B above. +=item B + +B<(HVM only)> Changes the default value of B for all PCI +devices passed through to this VM. See L for +more details. + =item B Enable graphics device PCI passthrough. This option makes an assigned -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:35:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:35:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276459.1561922 (Exim 4.92) (envelope-from ) id 1wAWnq-0000GZ-LI; Wed, 08 Apr 2026 17:34:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276459.1561922; Wed, 08 Apr 2026 17:34:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAWnq-0000GR-IV; Wed, 08 Apr 2026 17:34:58 +0000 Received: by outflank-mailman (input) for mailman id 1276459; Wed, 08 Apr 2026 17:34:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAWnp-0000GJ-QP for xen-devel@lists.xenproject.org; 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By deriving "ptr" > from that field (without any offset), it then ends up pointin one slot pointing > --- a/xen/arch/x86/traps.c > +++ b/xen/arch/x86/traps.c > @@ -1187,26 +1174,28 @@ void asmlinkage noreturn do_unhandled_tr > static void fixup_exception_return(struct cpu_user_regs *regs, > unsigned long fixup, unsigned long stub_ra) > { > - if ( IS_ENABLED(CONFIG_XEN_SHSTK) ) > +#ifdef CONFIG_XEN_SHSTK > { > - unsigned long ssp, *ptr, *base; > + unsigned long ssp = rdssp(); > > - if ( (ssp = rdssp()) == SSP_NO_SHSTK ) > - goto shstk_done; > + if ( ssp != SSP_NO_SHSTK ) > + { > + unsigned long *ptr = _p(regs->entry_ssp); > + unsigned long primary_shstk = > + (ssp & ~(STACK_SIZE - 1)) + > + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8; > > - ptr = _p(ssp); > - base = _p(get_shstk_bottom(ssp)); > + BUG_ON((regs->entry_ssp ^ primary_shstk) >> PAGE_SHIFT); This BUG() isn't correct. We can be in a fixup while in an IST handler, at which point SSP does not point to the primary shstk.  e.g. wrmsr_safe() in #MC. If you're looking to at least roughly bound it, check that it's any where in the stack range.  The WRSS below will #PF if SSP isn't referring to a shadow stack. Alternatively, add an is_shstk_page() predicate which checks for get_stack_page() == 5,0 which are the two shstk frames in the block of 8. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 17:54:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 17:54:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276471.1561932 (Exim 4.92) (envelope-from ) id 1wAX6N-0003WR-5T; Wed, 08 Apr 2026 17:54:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276471.1561932; Wed, 08 Apr 2026 17:54:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAX6N-0003WK-2R; Wed, 08 Apr 2026 17:54:07 +0000 Received: by outflank-mailman (input) for mailman id 1276471; Wed, 08 Apr 2026 17:54:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAX6M-0003WE-6t for xen-devel@lists.xenproject.org; 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Message-ID: <7ca7679f-c160-44c2-98ed-f1b1761255d4@citrix.com> Date: Wed, 8 Apr 2026 18:53:58 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie Subject: Re: [PATCH v2 3/3] x86: prefer shadow stack for producing call traces To: Jan Beulich , "xen-devel@lists.xenproject.org" References: <4bcc73db-38da-446e-b277-cf94c49002a1@suse.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: <4bcc73db-38da-446e-b277-cf94c49002a1@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO6P123CA0047.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:310::16) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|CO1PR03MB7796:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a4bcb27-151d-4de5-e2db-08de9597d134 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|22082099003|18002099003|56012099003; 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Do you have an example of what such a backtrace now looks like ? > Signed-off-by: Jan Beulich > --- > While the 'E' for exception frames is probably okay, I'm not overly > happy with the 'C' (for CET). I would have preferred 'S' (for shadow), > but we use that character already. > > As an alternative to suppressing output for the top level exception > frame, adding the new code ahead of the 'R' output line (and then also > ahead of the stack top read) could be considered. > > Perhaps having a printk() for the PV entry case is meaningless, for > - no frame being pushed when entered from CPL=3 (64-bit PV), > - no entry possible from CPL<3 (32-bit PV disabled when CET is active)? > In which case the comment probably should just be "Bogus." and the code > merely be "break;". Yes, PV32 doesn't exist when CET-SS is active, and PV64 doesn't push a frame.  regs->ssp will point to the supervisor token (IDT delivery) or on the boundary with the regular stack (FRED). > Quite likely a number of other uses of is_active_kernel_text() also want > amending with in_stub(). There are very few things which can exist on a shadow stack. 1) Tokens (supervisor, restore or prev) 2) Return address 3) Old-SSP 4) Old-CS Intel recommend not allowing code or stacks to be in the bottom 64k of the address space to prevent type confusion between Old-CS and the other values.  Xen matches this expectation, but it might be wise to check for it explicitly. Notably, we cannot ever get a value matching in_stub() (outside of general memory corruption). On SYSCALL/SYSENTER, SSP is set to 0, and we don't re-establish a proper SSP until the SETSSBSY after leaving the stub.  Similarly on SYSRET, the CLRSSBSY sets SSP to 0 too. An NMI hitting these paths should find regs->ssp pointing at it's own shadow stack, with an Old-SSP of 0. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 18:05:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 18:05:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276483.1561941 (Exim 4.92) (envelope-from ) id 1wAXGr-0005ZX-6u; Wed, 08 Apr 2026 18:04:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276483.1561941; Wed, 08 Apr 2026 18:04:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAXGr-0005ZQ-47; Wed, 08 Apr 2026 18:04:57 +0000 Received: by outflank-mailman (input) for mailman id 1276483; Wed, 08 Apr 2026 18:04:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAXGp-0005ZK-QW for xen-devel@lists.xenproject.org; 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Message-ID: <99200edd-3a99-4043-88b7-a7f3ee2c7a44@citrix.com> Date: Wed, 8 Apr 2026 19:04:46 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie Subject: Re: [PATCH v10] x86: use / "support" UDB To: Jan Beulich , "xen-devel@lists.xenproject.org" References: Content-Language: en-GB From: Andrew Cooper In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P123CA0229.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1a6::18) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|PH0PR03MB5878:EE_ X-MS-Office365-Filtering-Correlation-Id: 95a32de1-fa79-4d16-95b0-08de95995358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: JYXwYNrMnNyai5f3yFvb/EGNPd4299I78FIVAUkerbD1Vzmoa3JAjagceOrm2ZwF3IizdsF1yYsPpCrxfJtYtejVZkNkKOXAWKH/ScJmd8puFMZHRfRtWyGqbI3GaSGpp8YOl6auNuU1pPAq/4Ap7xx5QtGdB8ZLQc8VkRd4JwxRjqRKgJn6izKVFe/YyXzqawOlZgJ0Pv+mcPIJVxGtAyOXw0q2M9NVhPeJXXg3RqXSvOQH1IvUNGcANzsl+DzibT9zj4vbD2LbMh7TbOX3xrQflTeYpgfXkPZomSR9+qcbg2W3TgVseqwxYxmyWOzT+kpeoeD6iaiWhmCe115pQ3719YsycFiOoC0bAz7uPBGBM7f/ap+SbSq0J1qmSMOrueO2Q3YaWl4yJHc5uOmmgEQeE1gvyucc0nmSKW1xK5rd1iwoQxRFMVU+iwRYXLJN7WEEIt6gduJmRr7nAzPdrlOQ0OjVLrD20NWHQC/HCBAGsJ9JDReaD9XOnaDaiDIxklvFOMG2e2cBld6grVcR2EOffzXON10uB1yNnbJrtAjCxbTGs50Jdv0S7uVZ7TXxBLl4Ydx5ZfKoTBmsastZPimYIjCRIh+X9pSKMWPZn/QvR5gjKCgevvfc8Pu0bLLpnlYFJJLnMnhRrUU/42NZYQd9aPHHKPQO690j9XMWd0gx5HpMwqo5DyqRuzSDWxGPdW/v7TSBVO5NF/2NAp5ywu7pbTKu91KICBAcPRbQ8Wg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH8PR03MB8275.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(366016)(1800799024)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; 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Wouldn't we > better adjust that (e.g. using 0xcc instead)? That looks too much like breakpoint padding as opposed to nop padding. What about: diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c index a9b6c6b904f5..24440ccd03e3 100644 --- a/xen/arch/x86/extable.c +++ b/xen/arch/x86/extable.c @@ -157,7 +157,7 @@ int __init cf_check stub_selftest(void)          union stub_exception_token res;      } tests[] __initconst = {  #define endbr64 0xf3, 0x0f, 0x1e, 0xfa -        { .opc = { endbr64, 0x0f, 0xb9, 0x90 }, /* ud1 */ +        { .opc = { endbr64, 0x0f, 0xb9, 0x00 }, /* ud1 (%rax),%eax */            .res.fields.trapnr = X86_EXC_UD },          { .opc = { endbr64, 0x90, 0x02, 0x00 }, /* nop; add (%rax),%al */            .rax = 0x0123456789abcdef, which also brings it in line with the adjacent example? ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 08 21:11:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 21:11:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276576.1561965 (Exim 4.92) (envelope-from ) id 1wAaBB-00060H-3l; Wed, 08 Apr 2026 21:11:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276576.1561965; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="QESya23L83tZWxwF" Content-Disposition: inline In-Reply-To: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> X-purgate-ID: tlsNG-bad1c0/1775682673-57543152-C54B51C6/0/0 X-purgate-type: clean X-purgate-size: 14966 --QESya23L83tZWxwF Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 8 Apr 2026 23:11:07 +0200 From: Marek Marczykowski To: Jan Beulich Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Roger Pau =?utf-8?B?TW9ubsOp?= , Teddy Astie Subject: Re: [PATCH] x86/cpuidle: split the max_cstate variable On Wed, Apr 08, 2026 at 01:34:43PM +0200, Jan Beulich wrote: > The admin can control the upper bound wanted not only via command line > option, but also via XEN_SYSCTL_pm_op_set_max_cstate. While decisions how > to set up the system are okay this way as long as we deem the command line > option a strict upper bound, what to do during S3 resume should not be > based on that potentially varying value. Decisions there need to use > solely the strict upper bound we may have enforced ourselves (or which was > forced onto us via command line option). >=20 > Rather than altering pit_broadcast_is_available(), drop the function > altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just > for that to call into acpi/cpu_idle.c again. >=20 > Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs upda= ting only the lower 32 bits") > Signed-off-by: Jan Beulich What should be observable effect, in absence of max_cstate option and "xenpm set-max-cstate" calls? The "slow after S3" issue still happens. I tested this on top of the two other patches: - [PATCH] x86/HPET: channel handling in hpet_broadcast_resume() - [PATCH] x86/cpu-policy: set up host policy earlier > --- > cpuidle_disable_deep_cstate(), when called from handle_rtc_once(), is > still somewhat of a problem: Boot time and resume time runs of > _disable_pit_irq() may still behave differently because of that. In the above test, both on boot and resume I got: (XEN) [ 9.916522] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 (XEN) [ 9.921198] _disable_pit_irq:2659: cpuidle_usable_deep_cstate: 1, = boot_cpu_has(X86_FEATURE_XEN_ARAT): 1 > If we wanted the sysctl to possibly move the maximum C-state beyond what > was given on the command line, things would get yet more complicated, as > we'd then need to re-configure the driver that's in use. >=20 > I wonder how useful the ACPI_STATE_C #define-s really are. Plain 1 is > used in e.g. probe_c3_errata(), and the plain 7 doesn't even have a > respective constant (nor would that be suitable, as that's not really an > ACPI state). >=20 > --- a/xen/arch/x86/acpi/cpu_idle.c > +++ b/xen/arch/x86/acpi/cpu_idle.c > @@ -119,7 +119,7 @@ bool lapic_timer_init(void) > lapic_timer_off =3D hpet_broadcast_enter; > lapic_timer_on =3D hpet_broadcast_exit; > } > - else if ( pit_broadcast_is_available() ) > + else if ( cpuidle_usable_deep_cstate() ) > { > lapic_timer_off =3D pit_broadcast_enter; > lapic_timer_on =3D pit_broadcast_exit; > @@ -131,12 +131,15 @@ bool lapic_timer_init(void) > } > =20 > void (*__read_mostly pm_idle_save)(void); > -unsigned int max_cstate __read_mostly =3D UINT_MAX; > + > +unsigned int max_usable_cstate __read_mostly =3D UINT_MAX; > +unsigned int max_allowed_cstate __read_mostly =3D UINT_MAX; > unsigned int max_csubstate __read_mostly =3D UINT_MAX; > =20 > static int __init cf_check parse_cstate(const char *s) > { > - max_cstate =3D simple_strtoul(s, &s, 0); > + max_allowed_cstate =3D simple_strtoul(s, &s, 0); > + max_usable_cstate =3D max_allowed_cstate; > if ( *s =3D=3D ',' ) > max_csubstate =3D simple_strtoul(s + 1, NULL, 0); > return 0; > @@ -413,10 +416,11 @@ static void cf_check dump_cx(unsigned ch > unsigned int cpu; > =20 > printk("'%c' pressed -> printing ACPI Cx structures\n", key); > - if ( max_cstate < UINT_MAX ) > + if ( max_cstate() < UINT_MAX ) > { > - printk("max state: C%u\n", max_cstate); > - if ( max_csubstate < UINT_MAX ) > + printk("max state: C%u\n", max_cstate()); > + if ( max_allowed_cstate <=3D max_usable_cstate && > + max_csubstate < UINT_MAX ) > printk("max sub-state: %u\n", max_csubstate); > else > printk("max sub-state: unlimited\n"); > @@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle > u32 exp =3D 0, pred =3D 0; > u32 irq_traced[4] =3D { 0 }; > =20 > - if ( max_cstate > 0 && power && > + if ( max_cstate() > 0 && power && > (next_state =3D cpuidle_current_governor->select(power)) > 0 ) > { > unsigned int max_state =3D sched_has_urgent_vcpu() ? ACPI_STATE_= C1 > - : max_cstate; > + : max_cstate(); > =20 > do { > cx =3D &power->states[next_state]; > } while ( (cx->type > max_state || > cx->entry_method =3D=3D ACPI_CSTATE_EM_NONE || > (cx->entry_method =3D=3D ACPI_CSTATE_EM_FFH && > - cx->type =3D=3D max_cstate && > + cx->type =3D=3D max_allowed_cstate && > (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)= ) && > --next_state ); > if ( next_state ) > @@ -1448,7 +1452,7 @@ static void amd_cpuidle_init(struct acpi > =20 > for ( i =3D 0; i < nr; ++i ) > { > - if ( cx[i].type > max_cstate ) > + if ( cx[i].type > max_cstate() ) > break; > power->states[i + 1] =3D cx[i]; > power->states[i + 1].idx =3D i + 1; > @@ -1611,21 +1615,22 @@ int pmstat_reset_cx_stat(unsigned int cp > =20 > void cpuidle_disable_deep_cstate(void) > { > - if ( max_cstate > ACPI_STATE_C1 ) > + if ( max_usable_cstate > ACPI_STATE_C1 ) > { > if ( local_apic_timer_c2_ok ) > - max_cstate =3D ACPI_STATE_C2; > + max_usable_cstate =3D ACPI_STATE_C2; > else > - max_cstate =3D ACPI_STATE_C1; > + max_usable_cstate =3D ACPI_STATE_C1; > } > =20 > hpet_disable_legacy_broadcast(); > } > =20 > -bool cpuidle_using_deep_cstate(void) > +bool cpuidle_usable_deep_cstate(void) > { > - return xen_cpuidle && max_cstate > (local_apic_timer_c2_ok ? ACPI_ST= ATE_C2 > - : ACPI_ST= ATE_C1); > + return xen_cpuidle && > + max_usable_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2 > + : ACPI_STATE_C1); > } > =20 > static int cf_check cpu_callback( > --- a/xen/arch/x86/cpu/intel.c > +++ b/xen/arch/x86/cpu/intel.c > @@ -384,12 +384,12 @@ static void probe_c3_errata(const struct > }; > =20 > /* Serialized by the AP bringup code. */ > - if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && > + if ( max_usable_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)= ) && > x86_match_cpu(models) ) > { > printk(XENLOG_WARNING > "Disabling C-states C3 and C6 due to CPU errata\n"); > - max_cstate =3D 1; > + max_usable_cstate =3D 1; > } > } > =20 > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -1045,15 +1045,16 @@ static void cf_check mwait_idle(void) > u64 before, after; > u32 exp =3D 0, pred =3D 0, irq_traced[4] =3D { 0 }; > =20 > - if (max_cstate > 0 && power && > + if (max_cstate() > 0 && power && > (next_state =3D cpuidle_current_governor->select(power)) > 0) { > unsigned int max_state =3D sched_has_urgent_vcpu() ? ACPI_STATE_C1 > - : max_cstate; > + : max_cstate(); > =20 > do { > cx =3D &power->states[next_state]; > - } while ((cx->type > max_state || (cx->type =3D=3D max_cstate && > - MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > + } while ((cx->type > max_state || > + (cx->type =3D=3D max_allowed_cstate && > + MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > --next_state); > if (!next_state) > cx =3D NULL; > @@ -1458,7 +1459,7 @@ static void __init sklh_idle_state_table > u64 msr; > =20 > /* if PC10 disabled via cmdline max_cstate=3D7 or shallower */ > - if (max_cstate <=3D 7) > + if (max_cstate() <=3D 7) > return; > =20 > /* if PC10 not present in CPUID.MWAIT.EDX */ > @@ -1623,7 +1624,7 @@ static int __init mwait_idle_probe(void) > !mwait_substates) > return -ENODEV; > =20 > - if (!max_cstate || !opt_mwait_idle) { > + if (!max_cstate() || !opt_mwait_idle) { > pr_debug(PREFIX "disabled\n"); > return -EPERM; > } > @@ -1714,8 +1715,8 @@ static int cf_check mwait_idle_cpu_init( > hint =3D flg2MWAIT(cpuidle_state_table[cstate].flags); > state =3D MWAIT_HINT2CSTATE(hint) + 1; > =20 > - if (state > max_cstate) { > - printk(PREFIX "max C-state %u reached\n", max_cstate); > + if (state > max_cstate()) { > + printk(PREFIX "max C-state %u reached\n", max_cstate()); > break; > } > =20 > --- a/xen/arch/x86/include/asm/time.h > +++ b/xen/arch/x86/include/asm/time.h > @@ -31,7 +31,6 @@ int cpu_frequency_change(u64 freq); > =20 > void cf_check pit_broadcast_enter(void); > void cf_check pit_broadcast_exit(void); > -int pit_broadcast_is_available(void); > =20 > uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks); > =20 > --- a/xen/arch/x86/time.c > +++ b/xen/arch/x86/time.c > @@ -517,7 +517,7 @@ static int64_t __init cf_check init_hpet > bool disable_hpet =3D false; > =20 > if ( hpet_address && strcmp(opt_clocksource, pts->id) && > - cpuidle_using_deep_cstate() ) > + cpuidle_usable_deep_cstate() ) > { > if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0), > PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_INTEL ) > @@ -2655,7 +2655,7 @@ static int _disable_pit_irq(bool init) > * XXX dom0 may rely on RTC interrupt delivery, so only enable > * hpet_broadcast if FSB mode available or if force_hpet_broadcast. > */ > - if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_AR= AT) ) > + if ( cpuidle_usable_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_A= RAT) ) > { > init ? hpet_broadcast_init() : hpet_broadcast_resume(); > if ( !hpet_broadcast_is_available() ) > @@ -2707,11 +2707,6 @@ void cf_check pit_broadcast_exit(void) > reprogram_timer(this_cpu(timer_deadline)); > } > =20 > -int pit_broadcast_is_available(void) > -{ > - return cpuidle_using_deep_cstate(); > -} > - > void send_timer_event(struct vcpu *v) > { > send_guest_vcpu_virq(v, VIRQ_TIMER); > @@ -2999,7 +2994,7 @@ static void cf_check dump_softtsc(unsign > else if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC ) ) > { > printk("TSC has constant rate, "); > - if ( max_cstate <=3D ACPI_STATE_C2 && tsc_max_warp =3D=3D 0 ) > + if ( max_usable_cstate <=3D ACPI_STATE_C2 && tsc_max_warp =3D=3D= 0 ) > printk("no deep Cstates, passed warp test, deemed reliable, = "); > else > printk("deep Cstates possible, so not reliable, "); > --- a/xen/include/xen/acpi.h > +++ b/xen/include/xen/acpi.h > @@ -142,30 +142,33 @@ int acpi_gsi_to_irq (u32 gsi, unsigned i > =20 > #ifdef CONFIG_ACPI_CSTATE > /* > - * max_cstate sets the highest legal C-state. > - * max_cstate =3D 0: C0 okay, but not C1 > - * max_cstate =3D 1: C1 okay, but not C2 > - * max_cstate =3D 2: C2 okay, but not C3 etc. > - > - * max_csubstate sets the highest legal C-state sub-state. Only applies = to the > - * highest legal C-state. > - * max_cstate =3D 1, max_csubstate =3D 0 =3D=3D> C0, C1 okay, but not C1E > - * max_cstate =3D 1, max_csubstate =3D 1 =3D=3D> C0, C1 and C1E okay, bu= t not C2 > - * max_cstate =3D 2, max_csubstate =3D 0 =3D=3D> C0, C1, C1E, C2 okay, b= ut not C3 > - * max_cstate =3D 2, max_csubstate =3D 1 =3D=3D> C0, C1, C1E, C2 okay, b= ut not C3 > + * max_{allowed,usable}_cstate sets the highest allowed / usable C-state= , where > + * "allowed" is command line / sysctl based. > + * max_*_cstate =3D 0: C0 okay, but not C1 > + * max_*_cstate =3D 1: C1 okay, but not C2 > + * max_*_cstate =3D 2: C2 okay, but not C3 etc. > + * > + * max_csubstate sets the highest allowed C-state sub-state. Only applie= s to > + * the highest allowed C-state. > + * max_allowed_cstate =3D 1, max_csubstate =3D 0 =3D=3D> C0, C1 okay, bu= t not C1E > + * max_allowed_cstate =3D 1, max_csubstate =3D 1 =3D=3D> C0, C1 and C1E = okay, but not C2 > + * max_allowed_cstate =3D 2, max_csubstate =3D 0 =3D=3D> C0, C1, C1E, C2= okay, but not C3 > + * max_allowed_cstate =3D 2, max_csubstate =3D 1 =3D=3D> C0, C1, C1E, C2= okay, but not C3 > */ > =20 > -extern unsigned int max_cstate; > +extern unsigned int max_usable_cstate; > +extern unsigned int max_allowed_cstate; > extern unsigned int max_csubstate; > =20 > +#define max_cstate() min(max_usable_cstate, max_allowed_cstate) > + > static inline unsigned int acpi_get_cstate_limit(void) > { > - return max_cstate; > + return max_allowed_cstate; > } > static inline void acpi_set_cstate_limit(unsigned int new_limit) > { > - max_cstate =3D new_limit; > - return; > + max_allowed_cstate =3D new_limit; > } > =20 > static inline unsigned int acpi_get_csubstate_limit(void) > --- a/xen/include/xen/cpuidle.h > +++ b/xen/include/xen/cpuidle.h > @@ -89,7 +89,7 @@ struct cpuidle_governor > extern int8_t xen_cpuidle; > extern struct cpuidle_governor *cpuidle_current_governor; > =20 > -bool cpuidle_using_deep_cstate(void); > +bool cpuidle_usable_deep_cstate(void); > void cpuidle_disable_deep_cstate(void); > =20 > #define CPUIDLE_DRIVER_STATE_START 1 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --QESya23L83tZWxwF Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnWxGsACgkQ24/THMrX 1yyduAf/WsNYO6OcTfuk9TEpSOc9H1MgPkYS1TY3m5ZyQc60KwjvMlnUkFwlR2j8 hxKT/1htjFHuvBcY0efO5TSM9kbnfqZC+wjqc1L7D1UNVZJs7NJDQWtYp0UeBBGx 9TBE+s97exUrcQttVqLi8mhTHoDZV/CoUauU3ZNvUsV7s0QMAojxCQObLz+uEecm 5T8CtHL70esiVx/I1d8t0du+dW78xwOPV3UHZdtI7fVZxySiBinZ3qEb3dThonym Qkf+8O+aFe4OFnlLZCBamt2a4CpZMWq5Mpnu5bsk7Xmh2jNY5IbDE1dbEa8SuX6C p6s+g01iokPL+jEWWflQveku2IHTtA== =Kngx -----END PGP SIGNATURE----- --QESya23L83tZWxwF-- From xen-devel-bounces@lists.xenproject.org Wed Apr 08 23:41:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 08 Apr 2026 23:41:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276606.1561976 (Exim 4.92) (envelope-from ) id 1wAcWF-0000hZ-Go; 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Update all relevant domid_alloc() call sites and harden the domid_alloc() input value check. Also, fix problem with passing invalid domain IDs in XEN_DOMCTL_createdomain: turns out libxl__domain_make() (toolstack) uses 0xffff as domain ID. Amends: 2d5065060710 ("xen/domain: unify domain ID allocation") Signed-off-by: Denis Mukhin --- Changes since v6: - fixed libxl_domid_valid_guest() check in libxl_create.c - Link to v6: https://lore.kernel.org/xen-devel/20260307025451.3148078-2-dmukhin@ford.com/ - CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/2438790748 --- tools/libs/light/libxl_create.c | 4 +++- tools/tests/domid/harness.h | 1 + tools/tests/domid/test-domid.c | 12 ++++++------ xen/common/device-tree/dom0less-build.c | 2 +- xen/common/domctl.c | 3 +-- xen/common/domid.c | 5 ++++- xen/include/public/xen.h | 7 +++++++ 7 files changed, 23 insertions(+), 11 deletions(-) diff --git a/tools/libs/light/libxl_create.c b/tools/libs/light/libxl_create.c index bfc9149096a3..6fd62d140389 100644 --- a/tools/libs/light/libxl_create.c +++ b/tools/libs/light/libxl_create.c @@ -681,8 +681,10 @@ int libxl__domain_make(libxl__gc *gc, libxl_domain_config *d_config, continue; local_domid = v; + } else if (libxl_domid_valid_guest(info->domid)) { + local_domid = info->domid; } else { - local_domid = info->domid; /* May not be valid */ + local_domid = DOMID_ANY; } ret = xc_domain_create(ctx->xch, &local_domid, &create); diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h index 17eb22a9a854..65da0d075a2b 100644 --- a/tools/tests/domid/harness.h +++ b/tools/tests/domid/harness.h @@ -41,6 +41,7 @@ extern unsigned long find_next_zero_bit(const unsigned long *addr, #define DOMID_FIRST_RESERVED (100) #define DOMID_INVALID (101) +#define DOMID_ANY (102) #endif /* _TEST_HARNESS_ */ diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.c index 5915c4699a5c..71cc4e7fd86d 100644 --- a/tools/tests/domid/test-domid.c +++ b/tools/tests/domid/test-domid.c @@ -41,20 +41,20 @@ int main(int argc, char **argv) domid_free(expected); /* - * Test that that two consecutive calls of domid_alloc(DOMID_INVALID) + * Test that that two consecutive calls of domid_alloc(DOMID_ANY) * will never return the same ID. * NB: ID#0 is reserved and shall not be allocated by - * domid_alloc(DOMID_INVALID). + * domid_alloc(DOMID_ANY). */ for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ ) { - allocated = domid_alloc(DOMID_INVALID); + allocated = domid_alloc(DOMID_ANY); verify(allocated == expected, "TEST 3: expected %u allocated %u\n", expected, allocated); } for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ ) { - allocated = domid_alloc(DOMID_INVALID); + allocated = domid_alloc(DOMID_ANY); verify(allocated == DOMID_INVALID, "TEST 4: expected %u allocated %u\n", DOMID_INVALID, allocated); } @@ -64,7 +64,7 @@ int main(int argc, char **argv) domid_free(expected); for ( expected = 1; expected < DOMID_FIRST_RESERVED / 2; expected++ ) { - allocated = domid_alloc(DOMID_INVALID); + allocated = domid_alloc(DOMID_ANY); verify(allocated == expected, "TEST 5: expected %u allocated %u\n", expected, allocated); } @@ -72,7 +72,7 @@ int main(int argc, char **argv) /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */ expected = DOMID_FIRST_RESERVED - 1; domid_free(DOMID_FIRST_RESERVED - 1); - allocated = domid_alloc(DOMID_INVALID); + allocated = domid_alloc(DOMID_ANY); verify(allocated == expected, "TEST 6: expected %u allocated %u\n", expected, allocated); diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 840d14419da2..3c18dae5e625 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -852,7 +852,7 @@ void __init create_domUs(void) if ( (max_init_domid + 1) >= DOMID_FIRST_RESERVED ) panic("No more domain IDs available\n"); - domid = domid_alloc(DOMID_INVALID); + domid = domid_alloc(DOMID_ANY); if ( domid == DOMID_INVALID ) panic("Error allocating ID for domain %s\n", dt_node_name(node)); diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 93738931c575..b969f5ada6cc 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -409,8 +409,7 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) case XEN_DOMCTL_createdomain: { - /* NB: ID#0 is reserved, find the first suitable ID instead. */ - domid_t domid = domid_alloc(op->domain ?: DOMID_INVALID); + domid_t domid = domid_alloc(op->domain); if ( domid == DOMID_INVALID ) { diff --git a/xen/common/domid.c b/xen/common/domid.c index 2387ddb08300..b0258e477c1a 100644 --- a/xen/common/domid.c +++ b/xen/common/domid.c @@ -19,7 +19,7 @@ static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED); * @param domid Domain ID hint: * - If an explicit domain ID is provided, verify its availability and use it * if ID is not used; - * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] range, + * - If DOMID_ANY is provided, search [1..DOMID_FIRST_RESERVED-1] range, * starting from the last used ID. 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ID#0 is reserved for * the first boot domain (currently, dom0) and excluded from the allocation @@ -31,6 +31,9 @@ domid_t domid_alloc(domid_t domid) { static domid_t domid_last; + if ( domid >= DOMID_FIRST_RESERVED && domid != DOMID_ANY ) + return DOMID_INVALID; + spin_lock(&domid_lock); /* Exact match. */ diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index b12fd10e6315..f35a6f21f063 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -608,6 +608,13 @@ DEFINE_XEN_GUEST_HANDLE(mmuext_op_t); /* DOMID_INVALID is used to identify pages with unknown owner. */ #define DOMID_INVALID xen_mk_uint(0x7FF4) +/* + * DOMID_ANY is used to signal no specific domain ID requested. + * Handler should pick a valid ID, or handle it as a broadcast value + * depending on the context. + */ +#define DOMID_ANY xen_mk_uint(0x7FF5) + /* Idle domain. */ #define DOMID_IDLE xen_mk_uint(0x7FFF) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 00:13:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 00:13:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276623.1561984 (Exim 4.92) (envelope-from ) id 1wAd1c-0005mE-Ts; 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--00000000000013eb8c064efbe3c9-- From xen-devel-bounces@lists.xenproject.org Thu Apr 09 01:43:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 01:43:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276634.1561993 (Exim 4.92) (envelope-from ) id 1wAeQ9-0000al-4h; Thu, 09 Apr 2026 01:43:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276634.1561993; Thu, 09 Apr 2026 01:43:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAeQ9-0000ae-1s; Thu, 09 Apr 2026 01:43:01 +0000 Received: by outflank-mailman (input) for mailman id 1276634; Thu, 09 Apr 2026 01:43:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAeQ8-0000aY-2z for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 01:43:00 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAeQ6-007il5-9Z for xen-devel@lists.xenproject.org; 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dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775698976; bh=IDbGrUYW1qx3z77VZ3kqZ5LKwaE7kx9+w/skuTHAltM=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=XybisJgRQ3EAAJXHnGoEZDOt4Fk6mszHaP69xkbaVBwYl1b/wU6Hu8qlEhgV6PQRj E4j9fcEXSE/yjjpniPaD3AzRK/DDAVzpODFsyVba15BXImQyvrAp8PSHXffLdOlDVJ dJ1IRR0RwDySXrx64m74/nBRQu+ffvlPFhEncYwuYTndF2/ot6iu9sxZsaWJtRXFRT UUcfrJ+GmZiOmWfgCwCcPGxPTjazub1hHOjXs1mgpraq6D4qaduJ/8Loyyqhv7O7C5 3jWItOzyjRtif4nvTGB6i9zg/rowMPQTxb7nBO46BE7esdxFBsJCCfmpdbSoJOrT14 gi6PaQ/ZB0tqg== Date: Wed, 8 Apr 2026 18:42:54 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: GuoHan Zhao cc: jgross@suse.com, sstabellini@kernel.org, oleksandr_tyshchenko@epam.com, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] xen/manage: unwind partial shutdown watcher setup on error In-Reply-To: <20260407022443.12971-1-zhaoguohan@kylinos.cn> Message-ID: References: <20260407022443.12971-1-zhaoguohan@kylinos.cn> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-c201ff/1775698978-3173A96F-FF6118A3/0/0 X-purgate-type: clean X-purgate-size: 892 On Tue, 7 Apr 2026, zhaoguohan@kylinos.cn wrote: > From: GuoHan Zhao > > setup_shutdown_watcher() registers shutdown_watch first, then the sysrq > watch, and finally publishes the supported feature-* nodes in xenstore. > If sysrq watch registration fails, or xenbus_printf() fails after one or > more feature nodes were created, the function returns immediately without > undoing the earlier setup. > > This leaves the system in a partially initialized state, with registered > watches and/or stale xenstore entries despite the function reporting > failure. > > Unwind the partial setup before returning an error by unregistering any > watches that were already registered and removing feature nodes that were > already published. > > Signed-off-by: GuoHan Zhao Reviewed-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Thu Apr 09 05:51:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 05:51:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276667.1562001 (Exim 4.92) (envelope-from ) id 1wAiHy-00005H-Nf; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <99200edd-3a99-4043-88b7-a7f3ee2c7a44@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775713847-5D3273D8-BA88A76C/0/0 X-purgate-type: clean X-purgate-size: 1628 On 08.04.2026 20:04, Andrew Cooper wrote: > On 08/04/2026 1:12 pm, Jan Beulich wrote: >> With opcode D6h now firmly reserved as another #UD-raising one in 64-bit >> mode, use that instead of the two-byte UD2 for bug frame marking. >> >> While there also make a minor adjustment to the emulator. >> >> Signed-off-by: Jan Beulich > > For the patch itself, Acked-by: Andrew Cooper Thanks. >> --- >> One of the table entries in stub_selftest() uses UD1, yet in not quite >> an appropriate way: The 0x90 following it (presumably meant to be a NOP) >> really is a ModR/M byte, requiring a displacement to follow. Wouldn't we >> better adjust that (e.g. using 0xcc instead)? > > That looks too much like breakpoint padding as opposed to nop padding. > > What about: > > diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c > index a9b6c6b904f5..24440ccd03e3 100644 > --- a/xen/arch/x86/extable.c > +++ b/xen/arch/x86/extable.c > @@ -157,7 +157,7 @@ int __init cf_check stub_selftest(void) >          union stub_exception_token res; >      } tests[] __initconst = { >  #define endbr64 0xf3, 0x0f, 0x1e, 0xfa > -        { .opc = { endbr64, 0x0f, 0xb9, 0x90 }, /* ud1 */ > +        { .opc = { endbr64, 0x0f, 0xb9, 0x00 }, /* ud1 (%rax),%eax */ >            .res.fields.trapnr = X86_EXC_UD }, >          { .opc = { endbr64, 0x90, 0x02, 0x00 }, /* nop; add (%rax),%al */ >            .rax = 0x0123456789abcdef, > > which also brings it in line with the adjacent example? That's also okay, sure. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 05:54:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 05:54:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276675.1562010 (Exim 4.92) (envelope-from ) id 1wAiLh-0000nn-6U; Thu, 09 Apr 2026 05:54:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276675.1562010; Thu, 09 Apr 2026 05:54:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAiLh-0000ng-3Z; Thu, 09 Apr 2026 05:54:41 +0000 Received: by outflank-mailman (input) for mailman id 1276675; Thu, 09 Apr 2026 05:54:39 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAiLf-0000nW-Av for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 05:54:39 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAiLd-007pjO-5J for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 07:54:38 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d73f0e-e002-0a2a0a5209dd-0a2a4504a2d4-36 for ; Thu, 09 Apr 2026 07:54:38 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d73f1e-bb33-0a2a45040019-d155802cf1df-3 for ; Thu, 09 Apr 2026 07:54:38 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488ab2db91aso6830955e9.3 for ; Wed, 08 Apr 2026 22:54:38 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 08 Apr 2026 22:54:37 -0700 (PDT) Message-ID: <518db5e7-bcf0-424d-afce-60c3077cd892@suse.com> Date: Thu, 9 Apr 2026 07:54:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpuidle: split the max_cstate variable To: Marek Marczykowski Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775714078-B2F3E51B-D680C573/0/0 X-purgate-type: clean X-purgate-size: 2138 On 08.04.2026 23:11, Marek Marczykowski wrote: > On Wed, Apr 08, 2026 at 01:34:43PM +0200, Jan Beulich wrote: >> The admin can control the upper bound wanted not only via command line >> option, but also via XEN_SYSCTL_pm_op_set_max_cstate. While decisions how >> to set up the system are okay this way as long as we deem the command line >> option a strict upper bound, what to do during S3 resume should not be >> based on that potentially varying value. Decisions there need to use >> solely the strict upper bound we may have enforced ourselves (or which was >> forced onto us via command line option). >> >> Rather than altering pit_broadcast_is_available(), drop the function >> altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just >> for that to call into acpi/cpu_idle.c again. >> >> Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits") >> Signed-off-by: Jan Beulich > > What should be observable effect, in absence of max_cstate option and > "xenpm set-max-cstate" calls? None. Only if you lower max C-state before S3 to then raise it again afterwards. > The "slow after S3" issue still happens. I > tested this on top of the two other patches: > - [PATCH] x86/HPET: channel handling in hpet_broadcast_resume() > - [PATCH] x86/cpu-policy: set up host policy earlier Right, nothing else was expected. I Cc-ed you because the issue is S3-related (and you are who primarily uses that) and because I noticed the issue here while trying to figure out your actual problems. >> --- >> cpuidle_disable_deep_cstate(), when called from handle_rtc_once(), is >> still somewhat of a problem: Boot time and resume time runs of >> _disable_pit_irq() may still behave differently because of that. > > In the above test, both on boot and resume I got: > (XEN) [ 9.916522] _disable_pit_irq:2649: using_pit: 0, cpu_has_apic: 1 > (XEN) [ 9.921198] _disable_pit_irq:2659: cpuidle_usable_deep_cstate: 1, boot_cpu_has(X86_FEATURE_XEN_ARAT): 1 I don't expect handle_rtc_once() was involved, though? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775717723-22D2796F-486EB4F9/0/0 X-purgate-type: clean X-purgate-size: 1178 On 08.04.2026 17:48, Ross Lagerwall wrote: > On 4/8/26 4:21 PM, Jan Beulich wrote: >> On 01.04.2026 18:35, Ross Lagerwall wrote: >>> A future change to on_selected_cpus() will change the semantics of the >>> wait parameter so that it doesn't wait for remote CPUs to "check in" if >>> wait == 0. Adjust the call here to retain the existing behaviour so it >>> continues to wait for the remote CPUs to VMExit. >> >> Doesn't this go too far though? IOW wouldn't we better make the "wait" >> parameter a tristate then? > > From what I can see, the current wait == 0 behaviour only exists as a > limitation of the implementation: The local CPU needs to wait for all > the remote CPUs to have read "func" and "info" before dropping the lock > to avoid a race condition. > > With that limitation removed, I don't see a valid reason to maintain > this beahviour as an option, though I could be convinced otherwise. Well, the specific case here is where that behavior is wanted. Rather than penalizing that case (by using "wait until complete"), I'm asking to retain prior behavior ("wait until 'checked in'"). Even if (for now) only for this one case. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 07:12:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 07:12:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276700.1562029 (Exim 4.92) (envelope-from ) id 1wAjYy-0003xz-Rd; Thu, 09 Apr 2026 07:12:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276700.1562029; Thu, 09 Apr 2026 07:12:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAjYy-0003xs-OB; Thu, 09 Apr 2026 07:12:28 +0000 Received: by outflank-mailman (input) for mailman id 1276700; Thu, 09 Apr 2026 07:12:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAjYx-0003xm-9I for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 07:12:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAjYw-00A75x-Es for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 09:12:26 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d75149-5cb7-0a2a0a5109dd-0a2a4506d83c-42 for ; Thu, 09 Apr 2026 09:12:26 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7515a-0df0-0a2a45060019-d1558031e9e7-3 for ; Thu, 09 Apr 2026 09:12:26 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488a29e6110so5373175e9.3 for ; Thu, 09 Apr 2026 00:12:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260408163549.135245-1-andrew.cooper3@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775718746-AFD3C3D8-DAB543DA/0/0 X-purgate-type: clean X-purgate-size: 3391 On 08.04.2026 18:35, Andrew Cooper wrote: > AMD CPUs need LKGS depend on NSCB, but this dependency cannot be unconditional > as it will break FRED on Intel CPUs which don't need to enumerate the absence > of a bug. > > The deep dependecy logic is formed of two parts; a deep_features bitmap > indicating which features have dependencies, and deep_deps; the mapping of > feature to dependent features. Given that NSCB is an unconnected root of a > dependency, we can have the row in deep_deps and conditionally exclude it the > deep_features level. > > Rename INIT_DEEP_FEATURES to INIT_ALL_DEEP_FEATURES and add AMD and INTEL > forms too. In both xc_cpuid_apply_policy() and sanitise_featureset(), choose > the appropriate {amd,intel}_deep_features based on vendor. > > Introduce the NSCB <-> LKGS dependency and exclude the NSCB row from > intel_deep_features. This reads as if there was a bi-directional dependency. > --- a/tools/libs/guest/xg_cpuid_x86.c > +++ b/tools/libs/guest/xg_cpuid_x86.c > @@ -650,9 +650,12 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t domid, bool restore, > > if ( featureset ) > { > + static const uint32_t amd_deep_features[] = INIT_AMD_DEEP_FEATURES; > + static const uint32_t intel_deep_features[] = INIT_INTEL_DEEP_FEATURES; Nit: One blank too many each (after '='). > @@ -158,11 +159,21 @@ static void zero_leaves(struct cpuid_leaf *l, > > static void sanitise_featureset(uint32_t *fs) > { > + const uint32_t *deep_features; > /* bitmap_for_each() uses unsigned longs. Extend with zeroes. */ > uint32_t disabled_features[ > ROUNDUP(FSCAPINTS, sizeof(unsigned long)/sizeof(uint32_t))] = {}; > unsigned int i; > > + /* > + * At the time of writing, amd_deep_features contains one extra dependency > + * over intel for a "hardware no longer has this bug" bit. > + */ > + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD|X86_VENDOR_HYGON) ) > + deep_features = amd_deep_features; > + else > + deep_features = intel_deep_features; Aren't there going to be other somewhat similar features which may want marking like this (no matter whether right away they have a dependency)? Deferring the special-casing until a dependency appears is only risking to forget to add them. > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -344,6 +344,12 @@ def crunch_numbers(state): > # The ARCH_CAPS CPUID bit enumerates the availability of the whole register. > ARCH_CAPS: feat_range(RDCL_NO, RDCL_NO + 63), > > + # AMD-only special case. NullSelectorClearsBase is really a "hardware > + # doesn't have this bug any more" bit. All FRED-capable hardware has > + # NSCB properties, so disallow configurations which would cause LGKS > + # to behave unexpectedly. > + NSCB: [LKGS], Along the lines of my reply to your review comments on my LKGS patch, why is LKGS different from other selector loads? Don't we rather need to disallow (perhaps not physically, but verbally) the suppressing of NSCB? And then also for a few other "features", as per above? FDP_EXCP_ONLY and NO_FPU_SEL clearly would be of that kind, and (for possible dependencies) AMD doesn't know of them. Also, nit: "LKGS" (in the comment). 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what varies across architectures > are the attributes passed and hence the wrappers around it. Yet of course > extra checking or special handling may be needed per arch, so introduce a > suitable hook. > > Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monné Just looked at the common and x86 bits, both LGTM. > --- > Declarations (or inline counterparts) aren't being moved around, to avoid > the need to touch source files using the functions. Quite possibly they > want to consistently go into xen/io.h and asm/io.h. > > Of course ioremap.c could also go into lib/. Maybe I'm missing the point, but what's the benefit for it to go into lib/? Is there any realistic scenario where we might have a functional hypervisor build that doesn't require ioremap? Thanks, Roger. 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Thu, 09 Apr 2026 00:54:21 -0700 (PDT) Message-ID: <357c0692-1ed9-4bda-ae9a-729153d7cd93@suse.com> Date: Thu, 9 Apr 2026 09:54:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] make ioremap_attr() common To: Luca Fancellu Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk References: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> <72526f3a-726a-4a1e-8d80-1a336175c1af@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1775721262-76151497-62D24157/0/0 X-purgate-type: clean X-purgate-size: 2562 On 09.04.2026 09:26, Luca Fancellu wrote: > Hi Jan, > >> On 8 Apr 2026, at 13:07, Jan Beulich wrote: >> >> This core backing function is uniform; what varies across architectures >> are the attributes passed and hence the wrappers around it. Yet of course >> extra checking or special handling may be needed per arch, so introduce a >> suitable hook. >> >> Signed-off-by: Jan Beulich >> --- >> Declarations (or inline counterparts) aren't being moved around, to avoid >> the need to touch source files using the functions. Quite possibly they >> want to consistently go into xen/io.h and asm/io.h. >> >> Of course ioremap.c could also go into lib/. >> >> For RISC-V the wrappers likely should become inline functions? >> >> PPC doesn't reference any of the functions just yet, so gets only a >> declaration. >> >> For Arm, a TODO item is deliberately retained, yet seeing the use of >> ioremap_wc() in domain building (which by itself is questionable, see next >> patch) I wonder if that's even feasible as long as we don't have >> memremap() or alike. >> --- >> v2: Use conditional operator in ioremap_attr()'s final return. Re-base and >> leverage that to simplify ioremap_attr() itself. >> >> --- a/xen/arch/arm/include/asm/io.h >> +++ b/xen/arch/arm/include/asm/io.h >> @@ -1,6 +1,8 @@ >> #ifndef _ASM_IO_H >> #define _ASM_IO_H >> >> +#include >> + >> #if defined(CONFIG_ARM_32) >> # include >> #elif defined(CONFIG_ARM_64) >> @@ -9,6 +11,16 @@ >> # error "unknown ARM variant" >> #endif >> >> +#ifdef CONFIG_MPU >> +void __iomem *mpu_ioremap_attr(paddr_t start, size_t len, pte_attr_t flags); >> +#define arch_ioremap_attr mpu_ioremap_attr >> +#else >> +/* >> + * ioremap_attr() should only be used to remap device address ranges. >> + * TODO: Add an arch hook to verify this assumption. >> + */ >> +#endif > > I find a bit strange to have an #else with only a comment, but to be fair I’m not sure where this > comment can be put otherwise. That's the issue: I don't want to lose the comment, but I also didn't see a good place to put it. Having it here means it can be replaced by a single patch hunk, whenever the TODO is going to be addressed. > For the Arm and common part, I’ve also tested on Arm64 MMU, Arm32 MMU, Arm64 MPU on virtual platforms: > > Reviewed-by: Luca Fancellu # arm, common > Tested-by: Luca Fancellu # arm, common Thanks. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 07:58:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 07:58:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276761.1562084 (Exim 4.92) (envelope-from ) id 1wAkHY-0004Bd-Kn; Thu, 09 Apr 2026 07:58:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276761.1562084; Thu, 09 Apr 2026 07:58:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkHY-0004BS-FN; Thu, 09 Apr 2026 07:58:32 +0000 Received: by outflank-mailman (input) for mailman id 1276761; Thu, 09 Apr 2026 07:58:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkHX-0004As-It for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 07:58:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAkHW-004XTq-VN for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 09:58:30 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d75c16-5cb7-0a2a0a5109dd-0a2a450bde08-42 for ; Thu, 09 Apr 2026 09:58:30 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d75c26-bca8-0a2a450b0019-d1558029e0ed-3 for ; Thu, 09 Apr 2026 09:58:30 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so8282835e9.2 for ; Thu, 09 Apr 2026 00:58:30 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 00:58:30 -0700 (PDT) Message-ID: <17abf692-2b49-4f34-b09d-31e6a1741550@suse.com> Date: Thu, 9 Apr 2026 09:58:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] make ioremap_attr() common To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk References: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> <72526f3a-726a-4a1e-8d80-1a336175c1af@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775721510-EED4F2A1-8C47931F/0/0 X-purgate-type: clean X-purgate-size: 1387 On 09.04.2026 09:52, Roger Pau Monné wrote: > On Wed, Apr 08, 2026 at 02:07:23PM +0200, Jan Beulich wrote: >> This core backing function is uniform; what varies across architectures >> are the attributes passed and hence the wrappers around it. Yet of course >> extra checking or special handling may be needed per arch, so introduce a >> suitable hook. >> >> Signed-off-by: Jan Beulich > > Reviewed-by: Roger Pau Monné Thanks. > Just looked at the common and x86 bits, both LGTM. I'll transcribe this into Reviewed-by: Roger Pau Monné # x86, common >> --- >> Declarations (or inline counterparts) aren't being moved around, to avoid >> the need to touch source files using the functions. Quite possibly they >> want to consistently go into xen/io.h and asm/io.h. >> >> Of course ioremap.c could also go into lib/. > > Maybe I'm missing the point, but what's the benefit for it to go into > lib/? Is there any realistic scenario where we might have a > functional hypervisor build that doesn't require ioremap? Well, the difference likely is between "in principle" vs "in practice". In principle a lot of code could really be regarded "library" like. In practice whether to put code in lib/ really matters for stuff which may only be needed in certain configurations. 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Thu, 09 Apr 2026 01:01:26 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 10:01:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] make ioremap_wc() x86 only (for the time being) To: Luca Fancellu Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alistair Francis , Connor Davis , Oleksii Kurochko , Bertrand Marquis , Volodymyr Babchuk References: <145299a0-b25c-4612-82c6-9401a2f88ad2@suse.com> <4291DA48-87D9-491B-83C6-51CCACC0FFE7@arm.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4291DA48-87D9-491B-83C6-51CCACC0FFE7@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775721686-FF746A3D-0A910852/10/73395122804 X-purgate-type: spam X-purgate-size: 1136 On 09.04.2026 09:52, Luca Fancellu wrote: >> On 8 Apr 2026, at 13:09, Jan Beulich wrote: >> >> Its use in domain building is questionable: Already at the point both uses >> were introduced, ioremap_cache() existed. I can't see why kernel and >> initrd would need mapping WC, when at the same time other similar mappings >> (in common/device-tree/) are done WB. >> >> With those uses replaced, neither Arm nor RISC-V have a need for the >> function anymore. >> >> Amends: d8972aa9645f ("xen/arm: kernel: Rework kernel_zimage_load to use the generic copy helper") >> Amends: bb7e6d565d92 ("xen/arm: domain_build: Rework initrd_load to use the generic copy helper") >> Signed-off-by: Jan Beulich >> Reviewed-by: Oleksii Kurochko > > > Reviewed the arm and common part, tested on arm64 mmu, arm32 mmu, arm64 mpu: > > Reviewed-by: Luca Fancellu > Tested-by: Luca Fancellu Thanks, but I guess I'll use the form you sent earlier, with the restricted tags (matching what you say separately). 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This is a scalability bottleneck so to > avoid that: > > 1. Remove the global lock. > 2. Make call_data_struct per-CPU. > 3. Track which CPUs are currently running on_selected_cpus() using a > global CPU mask. This tells CPUs running the interrupt which per-CPU > call_data_structs to look at. > > Since the call data is now per-CPU, skip waiting for CPUs to "check in" > for async calls. Instead, delay it until the next time > on_selected_cpus() is called by which point there should be nothing to > wait for. One concern I have about this approach is loosing the fairness that the usage of the spin lock provided. Without the spinlock, and with the usage of for_each_cpu ( i, &tasks ) to process any pending tasks, it means the tasks from lower CPUs will always get preference over the tasks from higher CPUs, regardless of when they have been queued. Ideally we need some kind of mechanism that can do a FIFO style processing of the pending tasks, otherwise we are introducing a performance penalty to high CPU IDs compared to low ones, and that's likely to get worse as systems get bigger. Thanks, Roger. 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The > >>>>> benchmark has one > >>>>> or more CPUs in Xen calling on_selected_cpus() with between 1 and > >>>>> 64 CPUs in > >>>>> the selected mask. The executed function simply delays for 500 > >>>>> microseconds. > >>>>> > >>>>> The table below shows the % change in execution time of > >>>>> on_selected_cpus(): > >>>>> > >>>>>                     1 thread   2 threads    4 threads > >>>>> 1 CPU in mask     0.02       -35.23       -51.18 > >>>>> 2 CPUs in mask    0.01       -47.20       -69.27 > >>>>> 4 CPUs in mask    -0.02      -42.40       -66.55 > >>>>> 8 CPUs in mask    -0.03      -47.82       -68.39 > >>>>> 16 CPUs in mask   0.12       -41.95       -58.26 > >>>>> 32 CPUs in mask   0.02       -25.43       -39.35 > >>>>> 64 CPUs in mask   0.00       -24.70       -37.83 > >>>>> > >>>>> With 1 thread (i.e. no contention), there is no regression in > >>>>> execution time. > >>>>> With multiple threads, as expected there is a significant > >>>>> improvement in > >>>>> execution time. > >>>>> > >>>>> As a more practical benchmark to simulate host evacuation, I > >>>>> measured the > >>>>> memory dirtying rate across 10 VMs after enabling log dirty (on an > >>>>> AMD system, > >>>>> so without PML). The rate increased by 16% with this patch series, > >>>>> even > >>>>> after the recent deferred TLB flush changes. > >>>> > >>>> Is this a positive thing though? In the context of some related > >>>> work something > >>>> similar was mentioned iirc, accompanied by stating that this is > >>>> actually > >>>> problematic. A guest in log-dirty mode generally wants to be making > >>>> progress, > >>>> but also wants to be throttled enough to limit re-dirtying, such that > >>>> subsequent iterations (in particular the final one) of page contents > >>>> migration won't have to process overly many pages a 2nd time. > >>> > >>> In the context of a real migration, both the process copying the pages > >>> out of the guest and the guest itself will be hitting the TLB flush > >>> lock > >>> so reducing that bottleneck may increase throughput on both sides. > >>> Whether or not the overall migration time increases or decreases > >>> depends > >>> on many factors (number of migrations in parallel, the rate the > >>> guest is > >>> dirtying memory, the line speed of the NIC, whether PML is used, ...) > >>> which is why I measured a more controlled scenario to demonstrate the > >>> change. > >>> > >>> IMO throttling of a guest during a migration should be something > >>> intentional and controlled by userspace policy rather than a side > >>> effect > >>> of some internal global locks. > >> > >> I definitely agree here, but side effects going away may make it > >> necessary to > >> add such explicit throttling. > >> > > > > Explicit throttling is much more important for the already existing > > case of Intel systems with PML. With log dirty enabled, a VM on an Intel > > system can dirty memory an order of magnitude faster than an AMD system > > without PML. > > > > As an aside, for the same test an Intel machine without PML is still a > > lot faster than AMD so there is probably something to improve in this > > area for AMD machines.  > > AMD have PML on the way.  > https://docs.amd.com/v/u/en-US/69208_1.00_AMD64_PML_PUB > > There is a mis-step with how support for Intel's PML is done, meaning > that draining the vCPU's PML buffers is extraordinarily expensive even > when there's no action to take.  (Specifically, the remote VMCS acquire) > > A better option is this:  When logdirty is active, any VMExit will drain > the PML buffer into the logdirty bitmap before processing the main exit > reason.  This way, you drain all the PML buffers by just IPI-ing the > domain dirty mask. Seems like a good and easy to implement optimization. However we are already too fast when using PML in the sense that the toolstack cannot keep up with the rate of dirtied memory :). Thanks, Roger. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1775722419-BF9440B1-192369C3/0/0 X-purgate-type: clean X-purgate-size: 2564 On 08.04.2026 18:58, Andrew Cooper wrote: > On 08/04/2026 1:22 pm, Jan Beulich wrote: >> We will want to use that value for call trace generation, and likely >> also to eliminate the somewhat fragile shadow stack searching done in >> fixup_exception_return(). For those purposes, guest-only entry points do >> not need to record that value. >> >> To keep the saving code simple, record our own SSP that corresponds to >> an exception frame, pointing to the top of the shadow stack counterpart >> of what the CPU has saved on the regular stack. Consuming code can then >> work its way from there. >> >> Signed-off-by: Jan Beulich >> --- >> For PUSH_AND_CLEAR_GPRS and POP_GPRS, putting the new field right next to >> the error code isn't entirely nice; putting it ahead of %r15 would entail >> other changes, though. An option may be to not make SSP handling part of >> the macros in the first place. Thoughts? > > I have a firm dislike for SAVE/RESTORE_ALL, both for their substantial > complexity/inefficiency, and mixing of unrelated tasks. > > I have several series trying to purge them.  I suppose I really ought to > try and finish this off properly. > > While classing SSP as a "register" is probably fine, the ssp= parameter > (and particular it's asymmetric nature) is on the wrong side of the > "complex" argument IMO. > >> For POP_GPRS, does it really matter that it doesn't alter EFLAGS? > > Yes.  The SYSCALL fix for one (reviewed, but waiting on final testing > before I commit). > > Then the VT-x code when swapped to use POP_GPRS. > > > To take a step back, you say that putting it ahead of %r15 would entail > other changes.  What changes? SAVE_ALL's initial ADD, RESTORE_ALL's final SUB, and then the hunt for anything which may simply assume UREGS_r15 to be 0. If UREGS_r were ordered by register number, I would have considered putting it where %rsp nominally would go, but without that putting it somewhere in the middle feels rather arbitrary. > The resulting asm would be far cleaner. I agree. >  It would be an rdssp;push on > one side, and a pop into any register on the other side.  Furthermore, > given that the ssp= doesn't exclude storing it for some user frames, > just store it for all.  It's one push/pop into a hot cacheline, and > makes a substantial reduction in complexity. I'm having significant reservations against that. I use the 0 put there in subsequent patches, to identify absence of that data being available. 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pr=C Message-ID: <464adb13-b702-45cd-a28a-71d3278feb4c@amd.com> Date: Thu, 9 Apr 2026 10:17:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/drivers/char: fix SCIF IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: <6d1996b3d36e4d21e58c0e60876a1976db9a6208.1775667739.git.oleksii_moisieiev@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <6d1996b3d36e4d21e58c0e60876a1976db9a6208.1775667739.git.oleksii_moisieiev@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002325:EE_|SN7PR12MB6910:EE_ X-MS-Office365-Filtering-Correlation-Id: 05999b8d-60b4-449f-4a13-08de96106c79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Eh5ppRJtVBNwkbf3VuuB7HReXuSeA+WjyvlLaJNbP8ztE/aYG9vj1V7vcV1JQrHdTu5Psyo8AUYUzpuuKfSQhaFmEL5oHmJFF3xeU0HoZ6VzXjdkrTGOBJsWOBJ9r44s/lKB4qIyb7rGpy/Dh84xJzSZZFZ0YO8dzgFjC1Bb4No3bDVVyc5jIrtz1K5ZSsbqR6kFA0brV1cBUCEUHNIPiowihKMZhFTu3dKSUxqobGJcX+Uzbl0oitSNuIT/hNlg9pjL7JviIZhwm5VcSpklSB5TGB0FTn9uxbrJM4ZNTWMuMAmA4bwg6O3+Vi2XSaS/AVb2J/mNmzguGmvmEZ+4c3WzbudnyGvu1VjZhYs+9fQxeJWjnS98686xx6t6ZDXxvxcFebPougzIvWhq8oin1vqbccnUxzmer/u3Wne9m9VFDdQ9QOY61q6/9mWsU3bg X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 08:17:21.5383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05999b8d-60b4-449f-4a13-08de96106c79 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002325.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6910 X-purgate-ID: tlsNG-c1860d/1775722646-F5D53497-18B88478/0/0 X-purgate-type: clean X-purgate-size: 3499 On 08/04/2026 19:03, Oleksii Moisieiev wrote: > In scif_uart_init_postirq(), when setup_irq() returns an error the > failure was only logged via dprintk() and execution continued, > unconditionally writing TIE|RIE|REIE into the Serial Control Register > (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, > RX data ready, receive error) with no handler registered to service > them. On platforms where the GIC receives these asserted lines, the > result is either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > The fix adds an early return inside the error branch. The > interrupt-enable write to SCSCR is skipped entirely when no handler is > registered. > > SCIF TX continues to operate correctly after this change. The Xen > serial framework never calls serial_async_transmit() for SCIF, so > port->txbuf is always NULL. This causes __serial_putc() to take the > synchronous finite-capacity path, which polls the SCFSR_TDFE hardware > flag directly and does not depend on the interrupt mechanism. NIT: It would be nice to at least mention that there will be no serial RX without interrupts. > > As a secondary clean-up, the hardware error-flag clearing sequence is > moved to before the setup_irq() call so that error bits accumulated > since init_preirq() are cleared unconditionally, regardless of whether > IRQ registration succeeds. > > Signed-off-by: Oleksii Moisieiev That's a good catch. I can see most of our drivers already use that. Reviewed-by: Michal Orzel That said, I can see that we have exactly the same issue for pl011, cadence and exynos. I can either take your patch as is (no more work for you) and submit the patch fixing remaining drivers or you can send a v2 fixing all at once. It's up to you. ~Michal > --- > > xen/drivers/char/scif-uart.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c > index 888821a3b8..673a2d3800 100644 > --- a/xen/drivers/char/scif-uart.c > +++ b/xen/drivers/char/scif-uart.c > @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct serial_port *port) > uart->irqaction.name = "scif_uart"; > uart->irqaction.dev_id = port; > > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", > - uart->irq); > - > /* Clear all errors */ > if ( scif_readw(uart, params->status_reg) & params->error_mask ) > scif_writew(uart, params->status_reg, ~params->error_mask); > if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) > scif_writew(uart, params->overrun_reg, ~params->overrun_mask); > > + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > + { > + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", > + uart->irq); > + /* > + * If the IRQ handler could not be installed (setup_irq failed), > + * do not enable TX/RX or error interrupts. Serial transmit will > + * fall back to polling mode. > + */ > + return; > + } > + > /* Enable TX/RX and Error Interrupts */ > scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | > params->irq_flags); From xen-devel-bounces@lists.xenproject.org Thu Apr 09 08:26:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 08:26:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276831.1562138 (Exim 4.92) (envelope-from ) id 1wAkiS-0003jb-13; Thu, 09 Apr 2026 08:26:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276831.1562138; Thu, 09 Apr 2026 08:26:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkiR-0003jU-T1; Thu, 09 Apr 2026 08:26:19 +0000 Received: by outflank-mailman (input) for mailman id 1276831; Thu, 09 Apr 2026 08:26:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkiQ-0003jO-Rn for xen-devel@lists.xenproject.org; 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Date: Thu, 9 Apr 2026 10:26:08 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Frediano Ziglio Cc: xen-devel@lists.xenproject.org, Frediano Ziglio , Jan Beulich , Andrew Cooper Subject: Re: [PATCH v3] xen/x86: Check supported features even for PVH dom0 Message-ID: References: <20260408125521.104660-1-frediano.ziglio@cloud.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260408125521.104660-1-frediano.ziglio@cloud.com> X-ClientProxiedBy: MR1P264CA0140.FRAP264.PROD.OUTLOOK.COM (2603:10a6:501:51::6) To CH7PR03MB7860.namprd03.prod.outlook.com (2603:10b6:610:24e::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH7PR03MB7860:EE_|SJ0PR03MB6389:EE_ X-MS-Office365-Filtering-Correlation-Id: daaf1fcb-f962-48bc-c978-08de9611a8f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: bgfhReZHXkS29VXus5HGLEYdfyOgsdg2gRfZZcXZh0V5+CJiqCzCY5sQdtJtnY8iB1YXkwda68HDFDImDsPtlt6LgyiPXYAzxYwy9CElNVvT8XfLp0td5PT1n4vN7jY+KneQf69oJn6bzJWUb+eqx92IKwsHOhrFNbjtDQAqTz1tvTrCS1CULka97cip3O6awEmRO6QpoDXzoaeoP0qIED2nlSYYcK6eMdIGE1YMmj6oClOdQIJxH8ueTPdKJOIeMRXKF4a6AF4zmo+fvKBzcvgtrOQ9DEQBaHLRKsfO6M7V3x8C5fhYkiSgI3+QSszRz/fRHXBNdouWshhD51cwqqAuM+zL9j1bVhazyW3P2r48HTSbxRnQ9cJrwvfuimVMru4INAbwWBJzS5fZPaeJPqA2fX6TGZ88ayaoWJYWy6xAjKMRA51tif8kqlXX0zybtZWkT7QF6MkpimeW2hLtL3ddCkN6agzQMUSwxIxNXc+PYw/nNF2R/qcAfxEpUN1NImqXhhvlEfQ+OYzkU6kjU5TKWAZ8shbzvHpApakUp/ViLoYgN3W/xwag2vBl+oV3+Q3IqBgIuXwoXZZWscEUrGbd1yOw2mkADrXPT16T0T91whLn3AHBVIiBYuti18fETGyvrB+AJfIinT1kBp6qz2Z3xUWqodcTSfQX+W7Ir/BhFYmtusu0l30y1wkt8Sn+dvunaDuDR/804gtyMyvvBSB4QgDiGugdbpR4vplRSTg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH7PR03MB7860.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(366016)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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Factor out a function to check ELF notes and reuse it even > for PVH. > > Signed-off-by: Frediano Ziglio I think you dropped my RB from v2: Reviewed-by: Roger Pau Monné Thanks, Roger. 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Yet of course > extra checking or special handling may be needed per arch, so introduce a > suitable hook. > > Signed-off-by: Jan Beulich > --- RISC-V part LGTM: Reviewed-by: Oleksii Kurochko # riscv I've also tested on my test cases this patch and the next one and it works fine: Tested-by: Oleksii Kurochko # riscv Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 09 08:39:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 08:39:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276853.1562154 (Exim 4.92) (envelope-from ) id 1wAkvQ-0006rS-Gw; Thu, 09 Apr 2026 08:39:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276853.1562154; Thu, 09 Apr 2026 08:39:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkvQ-0006rL-EG; Thu, 09 Apr 2026 08:39:44 +0000 Received: by outflank-mailman (input) for mailman id 1276853; Thu, 09 Apr 2026 08:39:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkvP-0006rF-DT for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 08:39:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAkvO-008mV5-Ih for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:39:42 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d765c3-5cb7-0a2a0a5109dd-0a2a45098192-46 for ; Thu, 09 Apr 2026 10:39:42 +0200 Received: from [209.85.221.41] (helo=mail-wr1-f41.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d765cd-bf79-0a2a45090019-d155dd29ec6d-3 for ; Thu, 09 Apr 2026 10:39:42 +0200 Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-43d5ec211abso169707f8f.0 for ; Thu, 09 Apr 2026 01:39:42 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. 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Switch to 0xc0 which encodes two %eax operands, and is a complete instruction. No practical change. Reported-by: Jan Beulich Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie --- xen/arch/x86/extable.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c index a9b6c6b904f5..e1c8c9fab811 100644 --- a/xen/arch/x86/extable.c +++ b/xen/arch/x86/extable.c @@ -157,7 +157,7 @@ int __init cf_check stub_selftest(void) union stub_exception_token res; } tests[] __initconst = { #define endbr64 0xf3, 0x0f, 0x1e, 0xfa - { .opc = { endbr64, 0x0f, 0xb9, 0x90 }, /* ud1 */ + { .opc = { endbr64, 0x0f, 0xb9, 0xc0 }, /* ud1 %eax,%eax */ .res.fields.trapnr = X86_EXC_UD }, { .opc = { endbr64, 0x90, 0x02, 0x00 }, /* nop; add (%rax),%al */ .rax = 0x0123456789abcdef, -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 08:42:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 08:42:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276861.1562163 (Exim 4.92) (envelope-from ) id 1wAkyA-0008Kp-TU; Thu, 09 Apr 2026 08:42:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276861.1562163; Thu, 09 Apr 2026 08:42:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAkyA-0008Ki-QX; Thu, 09 Apr 2026 08:42:34 +0000 Received: by outflank-mailman (input) for mailman id 1276861; Thu, 09 Apr 2026 08:42:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAky9-0008Ka-Bl for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 08:42:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAky8-00CmoR-HC for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:42:32 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d76671-e002-0a2a0a5209dd-0a2a4501cffa-24 for ; Thu, 09 Apr 2026 10:42:32 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d76678-6fc9-0a2a45010019-d155802dd550-3 for ; Thu, 09 Apr 2026 10:42:32 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-488ba840146so5390095e9.1 for ; Thu, 09 Apr 2026 01:42:32 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7ca7679f-c160-44c2-98ed-f1b1761255d4@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1775724152-14EE3185-049B8097/0/0 X-purgate-type: clean X-purgate-size: 2259 On 08.04.2026 19:53, Andrew Cooper wrote: > On 08/04/2026 1:23 pm, Jan Beulich wrote: >> Shadow stacks contain little more than return addresses, and they in >> particular allow precise call traces also without FRAME_POINTER. > > Do you have an example of what such a backtrace now looks like ? I don't have one to hand, but I'll add an example for v3. >> --- >> While the 'E' for exception frames is probably okay, I'm not overly >> happy with the 'C' (for CET). I would have preferred 'S' (for shadow), >> but we use that character already. >> >> As an alternative to suppressing output for the top level exception >> frame, adding the new code ahead of the 'R' output line (and then also >> ahead of the stack top read) could be considered. >> >> Perhaps having a printk() for the PV entry case is meaningless, for >> - no frame being pushed when entered from CPL=3 (64-bit PV), >> - no entry possible from CPL<3 (32-bit PV disabled when CET is active)? >> In which case the comment probably should just be "Bogus." and the code >> merely be "break;". > > Yes, PV32 doesn't exist when CET-SS is active, and PV64 doesn't push a > frame.  regs->ssp will point to the supervisor token (IDT delivery) or > on the boundary with the regular stack (FRED). Okay, I'll change that then as indicated. >> Quite likely a number of other uses of is_active_kernel_text() also want >> amending with in_stub(). > > There are very few things which can exist on a shadow stack. > > 1) Tokens (supervisor, restore or prev) > 2) Return address > 3) Old-SSP > 4) Old-CS > > Intel recommend not allowing code or stacks to be in the bottom 64k of > the address space to prevent type confusion between Old-CS and the other > values.  Xen matches this expectation, but it might be wise to check for > it explicitly. What exactly do you mean here? Neither is_active_kernel_text() nor in_stub() nor the further "!((val ^ *ptr) >> (PAGE_SHIFT + STACK_ORDER))" (which I only now notice can't be quite right, as val was read from *ptr; I think (unsigned long)ptr is meant instead) would yield true there. If, as per above, in the remaining else we'll have just "break", what would such a separate check be good for? Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 09:19:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 09:19:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276886.1562176 (Exim 4.92) (envelope-from ) id 1wAlXL-0005ER-Nh; Thu, 09 Apr 2026 09:18:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276886.1562176; Thu, 09 Apr 2026 09:18:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAlXL-0005EK-Kf; Thu, 09 Apr 2026 09:18:55 +0000 Received: by outflank-mailman (input) for mailman id 1276886; Thu, 09 Apr 2026 09:18:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAlXK-0005EE-7R for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 09:18:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAlXJ-000xTX-Ea for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 11:18:53 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d76efb-bab6-0a2a0a5309dd-0a2a4507afc6-4 for ; Thu, 09 Apr 2026 11:18:53 +0200 Received: from [209.85.221.48] (helo=mail-wr1-f48.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d76efd-ba2d-0a2a45070019-d155dd30acd6-3 for ; Thu, 09 Apr 2026 11:18:53 +0200 Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-43b983bb07eso368186f8f.0 for ; Thu, 09 Apr 2026 02:18:53 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. 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However, take the opportunity to make the comment more general and less likely to bitrot. It would be a serious vulnerability for operating systems generally if CPL3 could modify GS_SHADOW at all. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie --- xen/arch/x86/domain.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1151997758c6..592530e53bcc 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1952,9 +1952,8 @@ static void load_segments(struct vcpu *n) * changes to bases can also be made with the WR{FS,GS}BASE instructions, when * enabled. * - * Guests however cannot use SWAPGS, so there is no mechanism to modify the - * inactive GS base behind Xen's back. Therefore, Xen's copy of the inactive - * GS base is still accurate, and doesn't need reading back from hardware. + * Guests cannot modify the inactive GS base behind Xen's back. Therefore + * Xen's copy is still accurate and doesn't need reading back. * * Under FRED, hardware automatically swaps GS for us, so SHADOW_GS is the * active GS from the guest's point of view. -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 09:21:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 09:21:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276892.1562185 (Exim 4.92) (envelope-from ) id 1wAlZZ-0006if-2e; Thu, 09 Apr 2026 09:21:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276892.1562185; Thu, 09 Apr 2026 09:21:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAlZY-0006iY-W4; Thu, 09 Apr 2026 09:21:12 +0000 Received: by outflank-mailman (input) for mailman id 1276892; Thu, 09 Apr 2026 09:21:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAlZX-0006iP-Cr for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 09:21:11 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAlZV-008Wwm-7A for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 11:21:10 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d76f85-e002-0a2a0a5209dd-0a2a45088660-8 for ; Thu, 09 Apr 2026 11:21:10 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d76f86-fab6-0a2a45080019-d1558034f076-3 for ; Thu, 09 Apr 2026 11:21:10 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-488d2079582so2577645e9.2 for ; Thu, 09 Apr 2026 02:21:10 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 02:21:09 -0700 (PDT) Message-ID: <2fa2fb41-cb62-4a1b-84cf-822b2f97bc2b@suse.com> Date: Thu, 9 Apr 2026 11:21:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Stewart Hildebrand From: Jan Beulich Subject: [PATCH] x86/APIC: handle overflow in TMICT calculation Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775726470-7694D497-3B324977/0/0 X-purgate-type: clean X-purgate-size: 1595 With an expiry value on the order of 20 hours, and with a bus scale value of 256k (as supplied by qemu), the (signed) multiplication will be UB. As we've checked that the value is positive, we mean unsigned multiplication anyway. Yet let's play safe against even larger expiry and bus scale values, leveraging the compiler builtin that there is for this purpose. While there also drop the stray cast from the actual TMICT write. Fixes: 9062553a0dc1 ("added time and accurate timer support") Fixes: b95beb185810 ("x86: Clean up APIC local timer handling") Reported-by: Stewart Hildebrand Signed-off-by: Jan Beulich --- Sadly neither gcc5 nor gcc15 properly optimize the (effectively) two uses of the 0xffffffffU constant: Both use a 2nd register to load the constant (really 0xfffffffeU unless <= is used) a 2nd time. --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1224,10 +1224,16 @@ int reprogram_timer(s_time_t timeout) } if ( timeout && ((expire = timeout - NOW()) > 0) ) - apic_tmict = min_t(uint64_t, (bus_scale * expire) >> BUS_SCALE_SHIFT, - UINT32_MAX); + { + unsigned long product; - apic_write(APIC_TMICT, (unsigned long)apic_tmict); + apic_tmict = UINT32_MAX; + if ( !__builtin_umull_overflow(bus_scale, expire, &product) && + (product >>= BUS_SCALE_SHIFT) < apic_tmict ) + apic_tmict = product; + } + + apic_write(APIC_TMICT, apic_tmict); return apic_tmict || !timeout; } From xen-devel-bounces@lists.xenproject.org Thu Apr 09 09:40:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 09:40:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276921.1562233 (Exim 4.92) (envelope-from ) id 1wAlro-0001cE-W6; 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As > we've checked that the value is positive, we mean unsigned multiplication > anyway. Yet let's play safe against even larger expiry and bus scale > values, leveraging the compiler builtin that there is for this purpose. > > While there also drop the stray cast from the actual TMICT write. > > Fixes: 9062553a0dc1 ("added time and accurate timer support") > Fixes: b95beb185810 ("x86: Clean up APIC local timer handling") > Reported-by: Stewart Hildebrand > Signed-off-by: Jan Beulich Acked-by: Andrew Cooper > --- > Sadly neither gcc5 nor gcc15 properly optimize the (effectively) two uses > of the 0xffffffffU constant: Both use a 2nd register to load the constant > (really 0xfffffffeU unless <= is used) a 2nd time. > > --- a/xen/arch/x86/apic.c > +++ b/xen/arch/x86/apic.c > @@ -1224,10 +1224,16 @@ int reprogram_timer(s_time_t timeout) > } > > if ( timeout && ((expire = timeout - NOW()) > 0) ) > - apic_tmict = min_t(uint64_t, (bus_scale * expire) >> BUS_SCALE_SHIFT, > - UINT32_MAX); > + { > + unsigned long product; > > - apic_write(APIC_TMICT, (unsigned long)apic_tmict); > + apic_tmict = UINT32_MAX; > + if ( !__builtin_umull_overflow(bus_scale, expire, &product) && > + (product >>= BUS_SCALE_SHIFT) < apic_tmict ) > + apic_tmict = product; > + } > + > + apic_write(APIC_TMICT, apic_tmict); > > return apic_tmict || !timeout; > } This is fine for staging, but be aware it cannot be backported before 4.21 due to the toolchain baseline (and nothing in CI will notice, I don't think.) ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 09 09:50:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 09:50:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276930.1562242 (Exim 4.92) (envelope-from ) id 1wAm1s-0003nh-SP; Thu, 09 Apr 2026 09:50:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276930.1562242; Thu, 09 Apr 2026 09:50:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAm1s-0003na-Po; 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Thu, 9 Apr 2026 09:50:24 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 831229dd307a461e977624eb355b0a9a; Thu, 09 Apr 2026 09:50:24 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775728224; x=1775998224; bh=Xj62McjTPlXGlQsECLY2xvZ8K59wYl8t3c2Hd91Lmco=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=bZC7crDeEsXLBdNXyj4y5/VHp5hkG8hm6JT5tnW6QML7DXjzeEjErbc+7Tdedx63X gZ5taI3Xmu1ClfyMQDb6N9cDXQb2ePjzeNnM3jN48uEk3M1MuWOrFBENMCYGLVEu3q P//TtEzMJxii6XckqMiRUSBbA4HfogPvIOGnTYpnhXLAstGL/HrjmYi2d36mXPa09Q tsNxO27KeVT3QP2MZMGWXCo7NtJ4m8kMKGl9H28q4z4qIp12NfZDLPzxp7FJNfc4gc SOqwG21x9APiOWHjISny1+1wJZ/SnCgPtb5YWfYI9Gp0mO/kByZu2vfV3xXjdtvSwl JehHf5t6dDImw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775728224; x=1775988724; i=teddy.astie@vates.tech; bh=Xj62McjTPlXGlQsECLY2xvZ8K59wYl8t3c2Hd91Lmco=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=oow2TDkoMeO5QTyWvP5BJ/U2WaRNbsgLwQp8u9S7IeYXPb8JNkBQ2iAlM5ZCMwgkK dxfbJMYXF3CTPgHBmxcjx6e1sr+eDoiozLc2X5CvqgK+wPDuTRNlDYsDPmNnT+czuW /oU/T/cquuy0M01xzQ3xrQ2YfMyLSDPXTDUjb/gS4W0DpKDvvPT4Fz/35KWuAWuzGw Czio/9NQ01SzaWEsu9gCU1Wa5dvvzl6M5NftNXTXyq85cjYLp9txPCffDGar31T8Q3 G5zFew9MtH4LKrfGlEYBSmQVT7sJiy37hNi/WV9lpfpzDUZLoycbm6/hpFFhosSZ1v c0feJYdXEv0zA== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH]=20x86/pv:=20Adjust=20the=20save=5Fsegments()=20comment=20regarding=20MSR=5FGS=5FSHADOW?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775728223179 Message-Id: <60de1b7c-f11d-4f32-a84a-16eddc73b5ef@vates.tech> To: "Andrew Cooper" , Xen-devel Cc: "Jan Beulich" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" References: <20260409091848.139077-1-andrew.cooper3@citrix.com> In-Reply-To: <20260409091848.139077-1-andrew.cooper3@citrix.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.831229dd307a461e977624eb355b0a9a?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 09:50:24 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1775728225-BF5460B1-7E0970F1/0/0 X-purgate-type: clean X-purgate-size: 1730 Le 09/04/2026 =C3=A0 11:21, Andrew Cooper a =C3=A9crit=C2=A0: > This is slightly stale mentioning SWAPGS and not LKGS. However, take the > opportunity to make the comment more general and less likely to bitrot. > > It would be a serious vulnerability for operating systems generally if CP= L3 > could modify GS_SHADOW at all. > > No functional change. > > Signed-off-by: Andrew Cooper > --- > CC: Jan Beulich > CC: Roger Pau Monn=C3=A9 > CC: Teddy Astie > --- > xen/arch/x86/domain.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c > index 1151997758c6..592530e53bcc 100644 > --- a/xen/arch/x86/domain.c > +++ b/xen/arch/x86/domain.c > @@ -1952,9 +1952,8 @@ static void load_segments(struct vcpu *n) > * changes to bases can also be made with the WR{FS,GS}BASE instruction= s, when > * enabled. > * > - * Guests however cannot use SWAPGS, so there is no mechanism to modify = the > - * inactive GS base behind Xen's back. Therefore, Xen's copy of the ina= ctive > - * GS base is still accurate, and doesn't need reading back from hardwar= e. > + * Guests cannot modify the inactive GS base behind Xen's back. Therefo= re > + * Xen's copy is still accurate and doesn't need reading back. > * > * Under FRED, hardware automatically swaps GS for us, so SHADOW_GS is = the > * active GS from the guest's point of view. Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:16:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:16:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276940.1562252 (Exim 4.92) (envelope-from ) id 1wAmRN-0007DO-S9; Thu, 09 Apr 2026 10:16:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276940.1562252; Thu, 09 Apr 2026 10:16:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmRN-0007DH-P8; Thu, 09 Apr 2026 10:16:49 +0000 Received: by outflank-mailman (input) for mailman id 1276940; Thu, 09 Apr 2026 10:16:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmRL-0007DB-Pp for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="FadDhAgw7qA4OlbR" Content-Disposition: inline In-Reply-To: <20260408172320.539750-1-thierry.escande@vates.tech> X-purgate-ID: tlsNG-ebf023/1775729806-B273A51B-FEEC0ED7/0/0 X-purgate-type: clean X-purgate-size: 3168 --FadDhAgw7qA4OlbR Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Thu, 9 Apr 2026 12:16:41 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Thierry Escande Cc: xen-devel@lists.xenproject.org, Anthony PERARD , Juergen Gross , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= Subject: Re: [RFC PATCH 0/3] xl: Allow PCI devices to be passthrough'd via Qemu command line On Wed, Apr 08, 2026 at 05:23:39PM +0000, Thierry Escande wrote: > This series adds support for a new 'hotplug' option for PCI devices to be > passthrough'd to guests. >=20 > The current mechanism for device passthrough uses QMP device_add command > to hot-plug PCI devices to the guest Qemu instance. This is an issue for > guests running on Q35 chipset (preliminary support posted at [1]) since t= he > Q35 PCI root bus does not support hotplug. Devices could be hotplugged to > a secondary PCI bus but Xen only support 1 PCI bus for now. >=20 > The 'hotplug' option allows to control how devices are attached to the > guest, either by using the legacy QMP mechanism (this is the default) or = by > passing it directly to the Qemu command line using xen-pci-passthrough > device. >=20 > Example usage in cfg file: > pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] >=20 > Since Qemu -device option accepts parameters in json format, this > patchset adds a new internal function libxl__device_pci_get_qmp_json() th= at > generates the device json object used for both QMP hotplug and command li= ne > passing. > Also, the function libxl_pci_assignable() is made available from libxl.h > for access in libxl_dm.c. I don't know if it's ok to make it public or if > it should stay private. Maybe it should be renamed as > libxl_device_pci_assignable() to match the other PCI device APIs. >=20 > This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running > Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. > Disabling the hotplug mechanism might be made mandatory for Q35 machines > later, once Q35 support is merged upstream. Generally I like the approach, and it looks sensible on the first look. But CI says it fails to build: https://gitlab.com/xen-project/people/marmarek/xen/-/pipelines/2439831766 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --FadDhAgw7qA4OlbR Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnXfIkACgkQ24/THMrX 1yzVtggAko25WLiGketDYodE72dV9YuvzZw0tInQPk3pi2jOkPQqOHb5kfKDaWP6 oH54OtYXWeFKIs6nWcbimJOEdQjIJGo/S/ZXxLUIDodxWnqQYTakG/II3fFBpcUB cS0SwE/eCyrmGJ44++XfYuVvoqHH2aAOsWpDGnO4Yra0wb4c9vf/MCHr11wJO4Ic PSY9Vpf5rmFGXKLCiKEZqSd/Qe3EMo+LJPXk3pmelZaa58KOWh1m+dU6iz34rl/u 3iAeSUFNi3ThazMLvQ9XznZsUZB2GlwBQ3p60CdYpF7VCIYXSYuGpJpM+xTl2+mm SYQCXFr9xQBvaLM5Z0Xwzo2jOTbh9Q== =hZBM -----END PGP SIGNATURE----- --FadDhAgw7qA4OlbR-- From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:31:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:31:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276957.1562261 (Exim 4.92) (envelope-from ) id 1wAmfL-0001vd-23; Thu, 09 Apr 2026 10:31:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276957.1562261; Thu, 09 Apr 2026 10:31:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmfK-0001vW-V8; Thu, 09 Apr 2026 10:31:14 +0000 Received: by outflank-mailman (input) for mailman id 1276957; Thu, 09 Apr 2026 10:31:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wAmfJ-0001vQ-V0 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:31:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAmfF-008nNS-VZ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:31:11 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d77fe8-2eae-0a2a0a5409dd-0a2a450be74e-20 for ; Thu, 09 Apr 2026 12:31:11 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d77fef-bca8-0a2a450b0019-d1558033b594-3 for ; Thu, 09 Apr 2026 12:31:11 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-488b150559bso5652205e9.1 for ; Thu, 09 Apr 2026 03:31:11 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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You really want to settle on whether it is selected unconditionally > or not. Also for the code below, where ... > >> --- a/xen/arch/riscv/Makefile >> +++ b/xen/arch/riscv/Makefile >> @@ -10,7 +10,7 @@ obj-y += irq.o >> obj-y += kernel.o >> obj-y += mm.o >> obj-y += p2m.o >> -obj-y += paging.o >> +obj-$(CONFIG_ARCH_PAGING_MEMPOOL) += paging.o >> obj-y += pt.o >> obj-$(CONFIG_RISCV_64) += riscv64/ >> obj-y += sbi.o > > ... this change and any #ifdef-ary further down aren't needed unless the > select became conditional. (Plus with the change above things likely wouldn't > even build if ARCH_PAGING_MEMPOOL could be off under certain conditions.) I missed if ARCH_PAGING_MEMPOOL=n then p2m.c, at least, will fail to compile so much more things would be needed to be #ifdef-ed. Just for simplicity then I will set CONFIG_ARCH_PAGING_MEMPOOL=y unconditionally and drop all the #ifdef-s related to this config I've added in this patch. > >> --- a/xen/arch/riscv/p2m.c >> +++ b/xen/arch/riscv/p2m.c >> @@ -1568,3 +1568,34 @@ struct page_info *get_page_from_gfn(struct domain *d, unsigned long gfn, >> >> return page; >> } >> + >> +#ifdef CONFIG_ARCH_PAGING_MEMPOOL >> + >> +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) >> +{ >> + unsigned long pages = PFN_DOWN(size); >> + bool preempted = false; >> + int rc; >> + >> + if ( (size & ~PAGE_MASK) || /* Non page-sized request? */ >> + pages != PFN_DOWN(size) ) /* 32-bit overflow? */ >> + return -EINVAL; > > Can't this be had with just > > if ( ((paddr_t)pages << PAGE_SHIFT) != size ) > return -EINVAL; > > (and perhaps utilizing pfn_to_paddr(), even if it's not a PFN we're dealing > with here)? It makes sense, I will apply that for RISC-V. Then for Arm and x86 could be done the same, I can send a separate patch for them. > >> + spin_lock(&d->arch.paging.lock); >> + rc = p2m_set_allocation(d, pages, &preempted); >> + spin_unlock(&d->arch.paging.lock); >> + >> + ASSERT(preempted == (rc == -ERESTART)); > > This actually suggests that (once again) Arm code perhaps shouldn't have been > copied verbatim: There shouldn't be a need for the "preempted" state to be > returned back in two distinct ways. Agree. The preempted argument of p2m_set_allocation() could be switched to a plain 'bool could_preempt', preemption would then be signaled solely via return -ERESTART, and the caller would just check rc, so no local bool preempted in this function and no ASSERT. I'm also thinking that the preempted argument could be dropped entirely, as it seems to exist only to conditionally enable the general_preempt_check() call inside the function. It is skipped only during domain_p2m_set_allocation(), which won't be a significant penalty if general_preempt_check() is called every time. All other callers pass a non-NULL preempted, so general_preempt_check() would always be executed regardless. > >> + return rc; >> +} >> + >> +/* Return the size of the pool, in bytes. */ >> +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) >> +{ >> + *size = (uint64_t)ACCESS_ONCE(d->arch.paging.total_pages) << PAGE_SHIFT; > > As per above, maybe use pfn_to_paddr()? Yes, it could be used to be in sync with a code above. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:38:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:38:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276970.1562270 (Exim 4.92) (envelope-from ) id 1wAmm2-0002kU-PP; Thu, 09 Apr 2026 10:38:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276970.1562270; Thu, 09 Apr 2026 10:38:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmm2-0002kN-Mp; Thu, 09 Apr 2026 10:38:10 +0000 Received: by outflank-mailman (input) for mailman id 1276970; Thu, 09 Apr 2026 10:38:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmm1-0002jk-9c for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:38:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAmm0-0057LG-Lp for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:38:08 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d78180-bab6-0a2a0a5309dd-0a2a4507a80c-48 for ; Thu, 09 Apr 2026 12:38:08 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d78190-ba2d-0a2a45070019-d155802acc77-3 for ; Thu, 09 Apr 2026 12:38:08 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-488971db0fdso7337415e9.0 for ; Thu, 09 Apr 2026 03:38:08 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. 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Smith" Subject: [PATCH] xen/efi: Reduce ifdefary in efi_exit_boot() Date: Thu, 9 Apr 2026 11:38:05 +0100 Message-Id: <20260409103805.176240-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775731088-8955341E-7A655351/0/0 X-purgate-type: clean X-purgate-size: 3596 Use IS_ENABLED() rather than #ifdef to give the compiler visibility into the block, which in turn removes the #ifdef from the varaible block. No functional change. Signed-off-by: Andrew Cooper --- CC: Marek Marczykowski-Górecki CC: Daniel P. Smith Best viewed with git show --ignore-all-space XenServer has been carrying a patch with a typo in this block for a long time, going entirely unnoticed. --- xen/common/efi/boot.c | 47 +++++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index 0ddc7bfd1277..7445f88902cd 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -1335,9 +1335,7 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste EFI_STATUS status; UINTN info_size = 0, map_key; bool retry; -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP unsigned int i; -#endif efi_bs->GetMemoryMap(&info_size, NULL, &map_key, &efi_mdesc_size, &mdesc_ver); @@ -1371,31 +1369,32 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste if ( EFI_ERROR(status) ) PrintErrMesg(L"Cannot exit boot services", status); -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP - for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) + if ( IS_ENABLED(CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP) ) { - EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; + for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) + { + EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; - /* - * Runtime services regions are always mapped here. - * Attributes may be adjusted in efi_init_memory(). - */ - if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || - desc->Type == EfiRuntimeServicesCode || - desc->Type == EfiRuntimeServicesData ) - desc->VirtualStart = desc->PhysicalStart; - else - desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; - } - status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, - mdesc_ver, efi_memmap); - if ( status != EFI_SUCCESS ) - { - printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", - status); - __clear_bit(EFI_RS, &efi_flags); + /* + * Runtime services regions are always mapped here. + * Attributes may be adjusted in efi_init_memory(). + */ + if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || + desc->Type == EfiRuntimeServicesCode || + desc->Type == EfiRuntimeServicesData ) + desc->VirtualStart = desc->PhysicalStart; + else + desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; + } + status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, + mdesc_ver, efi_memmap); + if ( status != EFI_SUCCESS ) + { + printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", + status); + __clear_bit(EFI_RS, &efi_flags); + } } -#endif /* Adjust pointers into EFI. */ efi_ct = (const void *)efi_ct + DIRECTMAP_VIRT_START; -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:41:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:41:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1276983.1562279 (Exim 4.92) (envelope-from ) id 1wAmow-0004Ka-55; Thu, 09 Apr 2026 10:41:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1276983.1562279; Thu, 09 Apr 2026 10:41:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmow-0004KT-2W; Thu, 09 Apr 2026 10:41:10 +0000 Received: by outflank-mailman (input) for mailman id 1276983; Thu, 09 Apr 2026 10:41:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAmou-0004KJ-Tm for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:41:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAmou-00DEVF-9j for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:41:08 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d78240-bab6-0a2a0a5309dd-0a2a450894b6-14 for ; Thu, 09 Apr 2026 12:41:08 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d78244-fab6-0a2a45080019-d155802decb1-3 for ; Thu, 09 Apr 2026 12:41:08 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-488aa77a06eso11387845e9.0 for ; Thu, 09 Apr 2026 03:41:08 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7ca7679f-c160-44c2-98ed-f1b1761255d4@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775731268-F7547497-0AC19B19/0/0 X-purgate-type: clean X-purgate-size: 1199 On 08.04.2026 19:53, Andrew Cooper wrote: > On 08/04/2026 1:23 pm, Jan Beulich wrote: >> Shadow stacks contain little more than return addresses, and they in >> particular allow precise call traces also without FRAME_POINTER. > > Do you have an example of what such a backtrace now looks like ? (XEN) Xen call trace: (XEN) [] R extable.c#search_one_extable+0x70/0x73 (XEN) [] C search_exception_table+0xc2/0x177 (XEN) [] C traps.c#extable_fixup.isra.0+0x18/0x6c (XEN) [] C do_invalid_op+0xab/0x106 (XEN) [] C x86_64/entry.S#handle_exception_saved+0x88/0xf4 (XEN) [] E ffff82d07fffe044 (XEN) [] C stub_selftest+0xd0/0x168 (XEN) [] C setup.c#init_done+0x116/0x15a Note how both the stub entry and stub_selftest() as its caller are present here. The stub entry is missing when FRAME_POINTER=n (albeit we could teach that code to recognize it), while the stub_selftest() entry is missing when FRAME_POINTER=y (and we can't do anything about this unless we wanted to add frame setup to stub generation). Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:53:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:53:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277002.1562288 (Exim 4.92) (envelope-from ) id 1wAn0y-0006KD-9Q; Thu, 09 Apr 2026 10:53:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277002.1562288; Thu, 09 Apr 2026 10:53:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAn0y-0006K6-6f; Thu, 09 Apr 2026 10:53:36 +0000 Received: by outflank-mailman (input) for mailman id 1277002; Thu, 09 Apr 2026 10:53:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAn0x-0006K0-72 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:53:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAn0v-008sFH-18 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:53:34 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d78526-e002-0a2a0a5209dd-0a2a450c9576-18 for ; Thu, 09 Apr 2026 12:53:34 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7852e-f40c-0a2a450c0019-d1558034c8bc-3 for ; Thu, 09 Apr 2026 12:53:34 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-48897fd88ebso7898155e9.2 for ; Thu, 09 Apr 2026 03:53:34 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <35802158-a43e-438d-b20a-8c748819a1f6@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775732014-FE94DA3D-866B9868/0/0 X-purgate-type: clean X-purgate-size: 2236 On 09.04.2026 11:39, Andrew Cooper wrote: > On 09/04/2026 10:21 am, Jan Beulich wrote: >> With an expiry value on the order of 20 hours, and with a bus scale value >> of 256k (as supplied by qemu), the (signed) multiplication will be UB. As >> we've checked that the value is positive, we mean unsigned multiplication >> anyway. Yet let's play safe against even larger expiry and bus scale >> values, leveraging the compiler builtin that there is for this purpose. >> >> While there also drop the stray cast from the actual TMICT write. >> >> Fixes: 9062553a0dc1 ("added time and accurate timer support") >> Fixes: b95beb185810 ("x86: Clean up APIC local timer handling") >> Reported-by: Stewart Hildebrand >> Signed-off-by: Jan Beulich > > Acked-by: Andrew Cooper Thanks. >> --- a/xen/arch/x86/apic.c >> +++ b/xen/arch/x86/apic.c >> @@ -1224,10 +1224,16 @@ int reprogram_timer(s_time_t timeout) >> } >> >> if ( timeout && ((expire = timeout - NOW()) > 0) ) >> - apic_tmict = min_t(uint64_t, (bus_scale * expire) >> BUS_SCALE_SHIFT, >> - UINT32_MAX); >> + { >> + unsigned long product; >> >> - apic_write(APIC_TMICT, (unsigned long)apic_tmict); >> + apic_tmict = UINT32_MAX; >> + if ( !__builtin_umull_overflow(bus_scale, expire, &product) && >> + (product >>= BUS_SCALE_SHIFT) < apic_tmict ) >> + apic_tmict = product; >> + } >> + >> + apic_write(APIC_TMICT, apic_tmict); >> >> return apic_tmict || !timeout; >> } > > This is fine for staging, but be aware it cannot be backported before > 4.21 due to the toolchain baseline (and nothing in CI will notice, I > don't think.) I'm debating with myself whether to replace by an asm() there. (If we expected further uses of those overflow built-ins, we could consider adding non-built- in fallbacks in those older branches. Yet unless something like this was needed in an XSA, it would be solely 4.20 to gain such.) Luckily in this case I think I would notice myself, as by default I'm building the older trees with gcc 4.8.5 and 7.4. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 10:54:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 10:54:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277009.1562296 (Exim 4.92) (envelope-from ) id 1wAn1u-0006oH-Hq; Thu, 09 Apr 2026 10:54:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277009.1562296; Thu, 09 Apr 2026 10:54:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAn1u-0006oA-FB; Thu, 09 Apr 2026 10:54:34 +0000 Received: by outflank-mailman (input) for mailman id 1277009; Thu, 09 Apr 2026 10:54:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAn1s-0006o4-O9 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 10:54:32 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAn1s-00DHYm-3z for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:54:32 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d78565-5cb7-0a2a0a5109dd-0a2a450bd456-14 for ; Thu, 09 Apr 2026 12:54:31 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d78567-bca8-0a2a450b0019-d155dd32c419-3 for ; Thu, 09 Apr 2026 12:54:31 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43cfac48bc7so469267f8f.0 for ; Thu, 09 Apr 2026 03:54:31 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Smith" , Xen-devel References: <20260409103805.176240-1-andrew.cooper3@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260409103805.176240-1-andrew.cooper3@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775732470-75557497-77A4F904/0/0 X-purgate-type: clean X-purgate-size: 3389 On 09.04.2026 12:38, Andrew Cooper wrote: > Use IS_ENABLED() rather than #ifdef to give the compiler visibility into the > block, which in turn removes the #ifdef from the varaible block. Just to mention, if it was just / mainly ... > --- a/xen/common/efi/boot.c > +++ b/xen/common/efi/boot.c > @@ -1335,9 +1335,7 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste > EFI_STATUS status; > UINTN info_size = 0, map_key; > bool retry; > -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP > unsigned int i; > -#endif ... this to be got rid of, we could as well use ... > @@ -1371,31 +1369,32 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste > if ( EFI_ERROR(status) ) > PrintErrMesg(L"Cannot exit boot services", status); > > -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP > - for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) for ( unsigned int i = 0; i < efi_memmap_size; i += efi_mdesc_size ) now. But yes, the typo aspect you mention can be avoided altogether by what you change things to. > + if ( IS_ENABLED(CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP) ) > { > - EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; > + for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) > + { > + EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; > > - /* > - * Runtime services regions are always mapped here. > - * Attributes may be adjusted in efi_init_memory(). > - */ > - if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || > - desc->Type == EfiRuntimeServicesCode || > - desc->Type == EfiRuntimeServicesData ) > - desc->VirtualStart = desc->PhysicalStart; > - else > - desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; > - } > - status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, > - mdesc_ver, efi_memmap); > - if ( status != EFI_SUCCESS ) > - { > - printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", > - status); > - __clear_bit(EFI_RS, &efi_flags); > + /* > + * Runtime services regions are always mapped here. > + * Attributes may be adjusted in efi_init_memory(). > + */ > + if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || > + desc->Type == EfiRuntimeServicesCode || > + desc->Type == EfiRuntimeServicesData ) > + desc->VirtualStart = desc->PhysicalStart; > + else > + desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; > + } > + status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, > + mdesc_ver, efi_memmap); > + if ( status != EFI_SUCCESS ) > + { > + printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", > + status); Could I talk you into switching to printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", status); to make the line at least a little less long? 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Smith" , Xen-devel Subject: Re: [PATCH] xen/efi: Reduce ifdefary in efi_exit_boot() To: Jan Beulich References: <20260409103805.176240-1-andrew.cooper3@citrix.com> <65b04675-abbf-413e-abe7-6cd463913fdd@suse.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: <65b04675-abbf-413e-abe7-6cd463913fdd@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: LO4P265CA0158.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2c7::17) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|LV3PR03MB7707:EE_ X-MS-Office365-Filtering-Correlation-Id: e323b975-093a-4377-dd8e-08de9628c7be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: NA/GUQ9STTYii+bAe2w1ZMyTH3xeR66aC+H0groIZrJuGrCwHSRjuJvDvVT1FANdySLSxA7Uff5OS7r+C3hy3hwpAfiA5qSzIBprV4QbTZiMg7I7OIi+JiK/e3S+sDCLTVJzQ8PqINp3Wor1VSAq2vnkCP0nQB9luZmyxoKzD5YO4vaT52bx1TGrPewDm4JB9+gZeDdjKdK41Fys3/xNnJUzHPEjkDTvRo+F6fu/zaGc2wj5GKcCaT3RlBYSynqGvp2lsDqbLdkCeiSD/Kk1R2Aj8iuOmLhlXyZty1j+49NmhKkvihPvi0K3zanZMlKl4tTrTS5CbeeJg00taCesnAlOoJb4UKHCA5QUmqm4MlXUa4M74xgF2HLnCSfyApsEaw6/Evc3aEPqotRSGThY2AQ8gXh+RrY7oFsN7C2z9GjSbZp2Znt9VFZfepErYIabypz5SbZtvDtoSm2MhY+cRVQ9+Du+4h8+T0fvCucHyd1YMvS62iiLDdgNohqAbtjlzTmviT24nJEUzg+/pByhNAS4874oenff9s7JlxJeoPLHNfySKKwpRnJOQjJK4hlueyImZMr2wel9aJxa1HEwi+wCEg+uLKOeie6PKFXLDm8KwlgAZnRATdISfPnmM8E8swuTRlqd8WBXpvFFM++IBFmpJBBBSgwv9w/vlEnaNtQaJqDpIDDY8aKZ85ozdJCzJn6/iYtseswGaGnbgkt9G7HNtl967Kgy5sgTzgUZe1k= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH8PR03MB8275.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; 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>> UINTN info_size = 0, map_key; >> bool retry; >> -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP >> unsigned int i; >> -#endif > ... this to be got rid of, we could as well use ... > >> @@ -1371,31 +1369,32 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste >> if ( EFI_ERROR(status) ) >> PrintErrMesg(L"Cannot exit boot services", status); >> >> -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP >> - for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) > for ( unsigned int i = 0; i < efi_memmap_size; i += efi_mdesc_size ) > > now. But yes, the typo aspect you mention can be avoided altogether by what > you change things to. I originally had this change in the patch, but it interferes with diff showing (just) an indentation change. I'm not fussed either way. > >> + if ( IS_ENABLED(CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP) ) >> { >> - EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; >> + for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) >> + { >> + EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; >> >> - /* >> - * Runtime services regions are always mapped here. >> - * Attributes may be adjusted in efi_init_memory(). >> - */ >> - if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || >> - desc->Type == EfiRuntimeServicesCode || >> - desc->Type == EfiRuntimeServicesData ) >> - desc->VirtualStart = desc->PhysicalStart; >> - else >> - desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; >> - } >> - status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, >> - mdesc_ver, efi_memmap); >> - if ( status != EFI_SUCCESS ) >> - { >> - printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", >> - status); >> - __clear_bit(EFI_RS, &efi_flags); >> + /* >> + * Runtime services regions are always mapped here. >> + * Attributes may be adjusted in efi_init_memory(). >> + */ >> + if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || >> + desc->Type == EfiRuntimeServicesCode || >> + desc->Type == EfiRuntimeServicesData ) >> + desc->VirtualStart = desc->PhysicalStart; >> + else >> + desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; >> + } >> + status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, >> + mdesc_ver, efi_memmap); >> + if ( status != EFI_SUCCESS ) >> + { >> + printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", >> + status); > Could I talk you into switching to > > printk(XENLOG_ERR > "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", > status); > > to make the line at least a little less long? Ok, but I'm not going to resend just for that. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:22:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:22:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277051.1562324 (Exim 4.92) (envelope-from ) id 1wAnTF-0004Pv-3q; Thu, 09 Apr 2026 11:22:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277051.1562324; Thu, 09 Apr 2026 11:22:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnTF-0004Po-0m; Thu, 09 Apr 2026 11:22:49 +0000 Received: by outflank-mailman (input) for mailman id 1277051; Thu, 09 Apr 2026 11:22:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnTD-0004Pi-Rf for xen-devel@lists.xenproject.org; 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Message-ID: <5d3472ff-77ff-466d-9461-3b33ef0815aa@citrix.com> Date: Thu, 9 Apr 2026 12:22:39 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , "xen-devel@lists.xenproject.org" Subject: Re: [PATCH v2 1/3] x86: record SSP at non-guest entry points To: Jan Beulich References: <868b63e6-c551-49b6-b177-cfadb29a69b1@suse.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: <868b63e6-c551-49b6-b177-cfadb29a69b1@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P123CA0008.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:150::13) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|MW4PR03MB6508:EE_ X-MS-Office365-Filtering-Correlation-Id: 63639e81-4b36-444c-4dbf-08de962a50bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|22082099003|18002099003|56012099003; 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For those purposes, guest-only entry points do >>> not need to record that value. >>> >>> To keep the saving code simple, record our own SSP that corresponds to >>> an exception frame, pointing to the top of the shadow stack counterpart >>> of what the CPU has saved on the regular stack. Consuming code can then >>> work its way from there. >>> >>> Signed-off-by: Jan Beulich >>> --- >>> For PUSH_AND_CLEAR_GPRS and POP_GPRS, putting the new field right next to >>> the error code isn't entirely nice; putting it ahead of %r15 would entail >>> other changes, though. An option may be to not make SSP handling part of >>> the macros in the first place. Thoughts? >> I have a firm dislike for SAVE/RESTORE_ALL, both for their substantial >> complexity/inefficiency, and mixing of unrelated tasks. >> >> I have several series trying to purge them.  I suppose I really ought to >> try and finish this off properly. >> >> While classing SSP as a "register" is probably fine, the ssp= parameter >> (and particular it's asymmetric nature) is on the wrong side of the >> "complex" argument IMO. >> >>> For POP_GPRS, does it really matter that it doesn't alter EFLAGS? >> Yes.  The SYSCALL fix for one (reviewed, but waiting on final testing >> before I commit). >> >> Then the VT-x code when swapped to use POP_GPRS. >> >> >> To take a step back, you say that putting it ahead of %r15 would entail >> other changes.  What changes? > SAVE_ALL's initial ADD, RESTORE_ALL's final SUB, Ok, this problem goes away if they're purged. I guess I should refresh and repost my series. > and then the hunt for > anything which may simply assume UREGS_r15 to be 0. I highly doubt we've got anything like this.  (And even if we do, it wants fixing, not using as an argument against doing this the nicer way.) > If UREGS_r were > ordered by register number, I would have considered putting it where > %rsp nominally would go, but without that putting it somewhere in the > middle feels rather arbitrary. > >> The resulting asm would be far cleaner. > I agree. > >>   It would be an rdssp;push on >> one side, and a pop into any register on the other side.  Furthermore, >> given that the ssp= doesn't exclude storing it for some user frames, >> just store it for all.  It's one push/pop into a hot cacheline, and >> makes a substantial reduction in complexity. > I'm having significant reservations against that. I use the 0 put there > in subsequent patches, to identify absence of that data being available. Well, that's not safe then. You've already got non-zero values there on entry-from-PV because there's no CPL check gating RDSPP the common IDT paths. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:26:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:26:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277065.1562333 (Exim 4.92) (envelope-from ) id 1wAnX4-00053L-Ll; Thu, 09 Apr 2026 11:26:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277065.1562333; Thu, 09 Apr 2026 11:26:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnX4-00053E-Ih; Thu, 09 Apr 2026 11:26:46 +0000 Received: by outflank-mailman (input) for mailman id 1277065; Thu, 09 Apr 2026 11:26:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wAnX3-000536-5A for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 11:26:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAnX2-00DPkc-HG for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 13:26:44 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d78cec-5cb7-0a2a0a5109dd-0a2a450ad6c8-38 for ; Thu, 09 Apr 2026 13:26:44 +0200 Received: from [209.85.208.50] (helo=mail-ed1-f50.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d78cf4-ee98-0a2a450a0019-d155d032b430-3 for ; Thu, 09 Apr 2026 13:26:44 +0200 Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-67010289b73so1072551a12.0 for ; Thu, 09 Apr 2026 04:26:44 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Not directly in this function, but it could be altered, for example, by kernel_image_load() where "info->entry = load_addr" is happening. > >> +{ >> + struct vcpu *v = d->vcpu[0]; >> + struct cpu_user_regs *regs = vcpu_guest_cpu_user_regs(v); >> + >> + BUG_ON(d->vcpu[0] == NULL); > > Why not simply "!v"? It could work. I'll apply that. > > Also, while in the cover letter you state a dependency on another series, > this is somewhat unwieldy here. From the titles there I can't deduce which > of the patches would introduce vcpu_guest_cpu_user_regs(). Yet I would > have wanted to double check that it doesn't de-reference v already. It was already merged. It was part of: xen/riscv: implement vcpu_csr_init() "02b3a1b0e53c" > >> + BUG_ON(v->is_initialised); >> + >> + kernel_load(kinfo); >> + initrd_load(kinfo, copy_to_guest_phys); >> + dtb_load(kinfo, copy_to_guest_phys); > > These all return void, despite this also being used for non-Dom0. Is it > really fatal to a dom0less system if one out of many domains fail to be > built? For a dom0less system, my opinion is that it should not be fatal, it should simply ignore a domain that fails to build and continue with the rest. However, with the current common dom0less code it will just panic(). This is a behavior I would like to change and it is on my TODO list. Regarding the functions returning void, this is because all of them currently call panic() on failure, which I expect will need to change in order to ignore a domain that fails to build in dom0less mode. For the current implementation of the common dom0less code this is fine, but I agree it should be addressed in a separate patch series. Especially when, despite the name, there is a Dom0? For this case, a failure there should indeed be fatal, so panic() is appropriate. > >> + regs->sepc = kinfo->entry; >> + >> + /* Guest boot cpuid = 0 */ >> + regs->a0 = 0; >> + regs->a1 = kinfo->dtb_paddr; >> + >> + for ( unsigned int i = 1; i < d->max_vcpus; i++ ) >> + { >> + if ( vcpu_create(d, i) == NULL ) >> + { >> + printk("Failed to allocate %pd v%d\n", d, i); >> + break; > > And no error is indicated to the caller? No, as generally it is enough to have only one vCPU0 to run domain, so we have to print that something went wrong with allocation of vCPU1...n but it is okay to me to continue domain construction. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:38:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:38:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277080.1562342 (Exim 4.92) (envelope-from ) id 1wAnht-0007SV-F4; Thu, 09 Apr 2026 11:37:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277080.1562342; Thu, 09 Apr 2026 11:37:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnht-0007SO-C8; Thu, 09 Apr 2026 11:37:57 +0000 Received: by outflank-mailman (input) for mailman id 1277080; Thu, 09 Apr 2026 11:37:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnhr-0007SI-Ee for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 11:37:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAnhq-0019io-Mw for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH 0/3] Fix Arm off-by-one bugs Date: Thu, 9 Apr 2026 13:39:31 +0200 Message-ID: <20260409113934.197619-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF00016160:EE_|MN2PR12MB4470:EE_ X-MS-Office365-Filtering-Correlation-Id: 04574b9f-5b69-49d4-b89d-08de962caeb2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700016|82310400026|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: GHZDR7r1U2AzS8RO7cR8TkyW9S0hbiERujGlNqGVEl9cCsv8aW0OBIB2apcLL+VjoQg9o/05mB3/fc/Xjzcqi3v/BtujeCLPjvnVpv35PuIi/Fi+Yn+gM5nrEdEG6VcAMSdf8TCbbVSvTPT4RcUl2ZZ4IuCXQAucRy97chOAEmEWqA5b3rFpvupGFJhKxb5zPzR+O1x2YpHHhokuKFfXSypT1TVnv3LMV5HkFO0jI0f3e4BmSe3saeqmtzdgXvE78XPIRPEqJeqFSmBVA14Hbu0Y6+fr6RyQVfQ6QTSLHwL8Y234izZpwWggpJ7lMPa8yHNxtV6coKV8A+nlw70VCSSCrkh3cSeYt/uKQ4lLwkfZN+rZM5bxdP8jMhQU48zidkyllkWNQCtoFDli5wkxatwpN/NBHeF+6bSNYWQBIy0j5xGsjCVSA3Ip/vNx1t+KzeXMQTPuProsW+7Mf+s0NByTIglF4JJK+FidsEzxN/M1pFHaUByaFIT12Qy3CxwGAj1//+t9WSrVVxDZtgmMT+OZXASuyRAcXGZqi3SH/e4JeQeUi1Is1f7+obivWsC+yEd/y4FeNbiFtj3BPpVjBoCfyOhzZvlkaUi10B5V0II5KDRAucQ9NT3kKynzm6YcAjZ9qQ0b5yWZ0bKiwqmSjuyrIIGHo16jo5sIQCAdiT5GztsOYsO6H/HRFG0qEoY99OY/38XTlKJnOSWk5N4TwO39/TuEG80uQEtN+gXrd9fIEnvV2isybPhCNWcDOmZiUyy9ynmK843dGPtWuaEl+g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700016)(82310400026)(56012099003)(18002099003);DIR:OUT;SFP:1101; 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Michal Orzel (3): xen/arm: Fix off-by-one in iomem_deny_access() calls xen/common: llc-coloring: Fix off-by-one in parse_color_config() xen/arm: gic-v3: Use vsize instead of csize for virtual CPU interface xen/arch/arm/acpi/domain_build.c | 2 +- xen/arch/arm/gic-v2.c | 8 ++++---- xen/arch/arm/gic-v3-its.c | 2 +- xen/arch/arm/gic-v3.c | 10 +++++----- xen/common/llc-coloring.c | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:39:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:39:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277086.1562360 (Exim 4.92) (envelope-from ) id 1wAnjg-0008Ax-4h; Thu, 09 Apr 2026 11:39:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277086.1562360; Thu, 09 Apr 2026 11:39:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnjg-0008Am-20; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=I41Wz6kgb/0DOUu+lYlBPOYvv2CAkwrbJsEJj/f2BGE=; b=4lCLIqE8abZaxsWbw+cxpFIPcWVXYIIYUDfWMSNX/g4XnzgvtxoasX818g4/tyQviDovS9qwEnc/aZWmxwuQxT2isFalZNAqTP9he/RLMXA1SbJU6O21hBunf/eS7ZG+V+yDxWFhFcZ5AxueIqFrQd/xGmavoqA9dUPoS7ucd0k= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/3] xen/arm: Fix off-by-one in iomem_deny_access() calls Date: Thu, 9 Apr 2026 13:39:32 +0200 Message-ID: <20260409113934.197619-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409113934.197619-1-michal.orzel@amd.com> References: <20260409113934.197619-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF00016160:EE_|DM4PR12MB8473:EE_ X-MS-Office365-Filtering-Correlation-Id: c3ac2837-4cd0-4f39-a074-08de962cafc3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|82310400026|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: B7fzeapXP7uNPQipQC2yF11wiOXtjpWmni6t2Rb1E3ivrfhSnck/6fgA9jTGRXLNX1yeRHpny1w9lPn748nNazFE7sZor7fksay6UGG/rnJxKwiy1QZH5dGV5+wATvVXWmA4Iwwg8cv6TaNeqUZM4x6g2sNd7/ZF3y30hyXPRTS4JJw9MRgWg94aE091DdZ0+oGW226QSyoCxtSC2Z7zA1YltUZOo9BbYvOu7SwnBwBvXSEBDov7dJ/inBqj22HoNFNXO262SYLV47KyeqWMSF3GspTy0VOTBHTfAZi01jZ3AleLGddaAcMbJsFbUPoRtsJVJ7pq/e9hpnLvfArsvRVcayxlTMCaDn+wNfk+lezV6tUYyBF4AbYWBruML+jqI+eL5Tr0947WPqu2SPIeHDC3mP5a5DkfM7ktwQ/mjUNn+m3uxRnwYoTbtuwX43bQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:39:40.3429 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3ac2837-4cd0-4f39-a074-08de962cafc3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF00016160.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8473 X-purgate-ID: tlsNG-16d1c6/1775734786-5CD243D8-BBB4CCF6/0/0 X-purgate-type: clean X-purgate-size: 4470 iomem_deny_access() wraps rangeset_remove_range() which takes inclusive endpoints. All call sites in the GIC and ACPI code pass 'mfn + nr' (or 'mfn + 1' for single-page regions) as the end parameter, which causes one extra page beyond each region to be denied. For single-page regions, use 'mfn' as the end (denying exactly one page). For all multi-page regions, use 'mfn + nr - 1'. This matches the correct pattern used elsewhere, e.g. in device.c. Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") Fixes: 66158be465 ("ARM: ITS: Deny hardware domain access to ITS") Fixes: 97e9875646 ("arm/acpi: Permit MMIO access of Xen unused devices for Dom0") Signed-off-by: Michal Orzel --- xen/arch/arm/acpi/domain_build.c | 2 +- xen/arch/arm/gic-v2.c | 8 ++++---- xen/arch/arm/gic-v3-its.c | 2 +- xen/arch/arm/gic-v3.c | 8 ++++---- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/acpi/domain_build.c b/xen/arch/arm/acpi/domain_build.c index 5a117001ef11..249d899c3337 100644 --- a/xen/arch/arm/acpi/domain_build.c +++ b/xen/arch/arm/acpi/domain_build.c @@ -48,7 +48,7 @@ static int __init acpi_iomem_deny_access(struct domain *d) { mfn = spcr->serial_port.address >> PAGE_SHIFT; /* Deny MMIO access for UART */ - rc = iomem_deny_access(d, mfn, mfn + 1); + rc = iomem_deny_access(d, mfn, mfn); if ( rc ) return rc; } diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index b23e72a3d05d..014f9559673b 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -1079,23 +1079,23 @@ static int gicv2_iomem_deny_access(struct domain *d) unsigned long mfn, nr; mfn = dbase >> PAGE_SHIFT; - rc = iomem_deny_access(d, mfn, mfn + 1); + rc = iomem_deny_access(d, mfn, mfn); if ( rc ) return rc; mfn = hbase >> PAGE_SHIFT; - rc = iomem_deny_access(d, mfn, mfn + 1); + rc = iomem_deny_access(d, mfn, mfn); if ( rc ) return rc; mfn = cbase >> PAGE_SHIFT; nr = DIV_ROUND_UP(csize, PAGE_SIZE); - rc = iomem_deny_access(d, mfn, mfn + nr); + rc = iomem_deny_access(d, mfn, mfn + nr - 1); if ( rc ) return rc; mfn = vbase >> PAGE_SHIFT; - return iomem_deny_access(d, mfn, mfn + nr); + return iomem_deny_access(d, mfn, mfn + nr - 1); } #ifdef CONFIG_ACPI diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 9ba068c46fcb..e38aa8711744 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -1009,7 +1009,7 @@ int gicv3_its_deny_access(struct domain *d) { mfn = paddr_to_pfn(its_data->addr); nr = PFN_UP(its_data->size); - rc = iomem_deny_access(d, mfn, mfn + nr); + rc = iomem_deny_access(d, mfn, mfn + nr - 1); if ( rc ) { printk("iomem_deny_access failed for %lx:%lx \r\n", mfn, nr); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bc07f97c16ab..b3e104ea4ad0 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1602,7 +1602,7 @@ static int gicv3_iomem_deny_access(struct domain *d) mfn = dbase >> PAGE_SHIFT; nr = PFN_UP(SZ_64K); - rc = iomem_deny_access(d, mfn, mfn + nr); + rc = iomem_deny_access(d, mfn, mfn + nr - 1); if ( rc ) return rc; @@ -1614,7 +1614,7 @@ static int gicv3_iomem_deny_access(struct domain *d) { mfn = gicv3.rdist_regions[i].base >> PAGE_SHIFT; nr = PFN_UP(gicv3.rdist_regions[i].size); - rc = iomem_deny_access(d, mfn, mfn + nr); + rc = iomem_deny_access(d, mfn, mfn + nr - 1); if ( rc ) return rc; } @@ -1623,7 +1623,7 @@ static int gicv3_iomem_deny_access(struct domain *d) { mfn = cbase >> PAGE_SHIFT; nr = PFN_UP(csize); - rc = iomem_deny_access(d, mfn, mfn + nr); + rc = iomem_deny_access(d, mfn, mfn + nr - 1); if ( rc ) return rc; } @@ -1632,7 +1632,7 @@ static int gicv3_iomem_deny_access(struct domain *d) { mfn = vbase >> PAGE_SHIFT; nr = PFN_UP(csize); - return iomem_deny_access(d, mfn, mfn + nr); + return iomem_deny_access(d, mfn, mfn + nr - 1); } return 0; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:39:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:39:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277087.1562370 (Exim 4.92) (envelope-from ) id 1wAnjh-0008P8-E3; Thu, 09 Apr 2026 11:39:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277087.1562370; Thu, 09 Apr 2026 11:39:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnjh-0008Oz-9R; Thu, 09 Apr 2026 11:39:49 +0000 Received: by outflank-mailman (input) for mailman id 1277087; Thu, 09 Apr 2026 11:39:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnjg-0008Aj-08 for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Andrew Cooper , Anthony PERARD , "Jan Beulich" , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano Stabellini" Subject: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() Date: Thu, 9 Apr 2026 13:39:33 +0200 Message-ID: <20260409113934.197619-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409113934.197619-1-michal.orzel@amd.com> References: <20260409113934.197619-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000205:EE_|DM4PR12MB5772:EE_ X-MS-Office365-Filtering-Correlation-Id: 42b22715-b2c0-485f-dfa5-08de962cb0d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: apyWwzUUUiRAXj8a8GZoQf584U4AYZEOZ2D6vpAOgQ9e/as075hipKPqTYIIsl/R9lnFNwQnMOOSapkeqMdAl/xnJtL9MdrX+AZXkNVmmEtJCSCzhZdHo56unBOyh5vK886PDnKgwUVG46Kp0JbAbC1y27Atizsv5H29X4dxvQkuPZn/nl/b3J/VwPGkzgcZBW8YzLOWokuFKUe9dCmD3ieW9ivefbKrxieRzMvZYFhWeOGVqQbupGT3M7Lj+gpo0Lrr4NF/Lj9uz2rXYpJjC0fyUardpC/dqx2e7Qg07odlYM691aihjV+IwC+rqNkWJbUO89CltEFU+c5S9zg+TTyB/eMMyMysezNrWlR0pHXahIhS5csidCmpNBkX3cLwbchWWxrB9ZXJmi4bldc+BJLK4yHa7NkQ1TrQNlCkmf1XQZUk/PbJDl0V/Pl4FJ+7dTX3DrfRDBj/aGxusE6c++87zzxKC2sbAFFp35+OwJA3PbOE3JttmIUdH68EuGgnEiouOV9HduL5xRvtw/7VlVyK+3a24C7D+64C/hZZciSKVfoy5RwBwh0o2030jdwoxda2lqZ17Y8kboWgQO+y2rEyvN2wcGou9aN8Ejy3KkDuW3fdsasYulCgvoiG4me1JuMIWtMQC4mlhzHRD4Omrxm4qs/bTOoZNlxWKIDHUwRozgog/pb0k3IaomIEojQbqLpfEf7Ftn4nmjR1KYsVn2z7ZjsVBpcxfkbLH6CVc+Uen/ovhU6+I+43GjhBgKVi5QL6pjVCnURdFJv8bgGSJg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: u9lstO0b1NBY+1MmFW473LJuwpjMo0vSq1yrEFiBPn84DfjWx65IBLMdoE/98PiggCN390jEIMPbcXxnXYn07zrmg7FHl+InqxfZ8wCiPSFeE/m2Z3Ml5bQOb3+dh7a9ccUGh/lNrFApo9DbqBe0u+6kakLuSznXvVVwNHkGxfJdP/Ojqd3ceFuOe0lkmF8NzKyZf41PaNDwfvrEOo9Aky7taygi3I/cRfDS0EwiDRrtE7Ymy4ihv1sfakVDoEvNz0HEvKf/GFVfR7YymLITv8ONA+DnC58FzX54GNI2VD58cNfNFb9RN7MzhBYUMWFaTHTq4n5YtLrEhS4M2+DwegrB5pK2fFi0N6t9GMbrpQ5ggkQySR2QBt/NvvqIsJ+5p8aNAPMtoxR62EImY9I1wjy6zBtQ3Mn0SXJiMtRQ5tsm/LQPHs9/nWyuWF3v/zcg X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:39:42.1428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42b22715-b2c0-485f-dfa5-08de962cb0d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000205.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5772 X-purgate-ID: tlsNG-720697/1775734787-46B27CD1-FDD1E078/0/0 X-purgate-type: clean X-purgate-size: 1193 The check uses >= to compare the total number of colors against max_num_colors (which is ARRAY_SIZE of the colors array). This incorrectly rejects input that would exactly fill the array. For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 for dom0 would fail. Change >= to > so that exactly filling the array is permitted. Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") Signed-off-by: Michal Orzel --- xen/common/llc-coloring.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c index eb7c72b24023..30c1594dac9f 100644 --- a/xen/common/llc-coloring.c +++ b/xen/common/llc-coloring.c @@ -78,7 +78,7 @@ static int __init parse_color_config(const char *buf, unsigned int colors[], if ( end >= NR_LLC_COLORS || start > end || (end - start) >= (UINT_MAX - *num_colors) || - (*num_colors + (end - start + 1)) >= max_num_colors ) + (*num_colors + (end - start + 1)) > max_num_colors ) return -EINVAL; /* Colors are range checked in check_colors() */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:39:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:39:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277091.1562378 (Exim 4.92) (envelope-from ) id 1wAnjn-0000It-Lo; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/3] xen/arm: gic-v3: Use vsize instead of csize for virtual CPU interface Date: Thu, 9 Apr 2026 13:39:34 +0200 Message-ID: <20260409113934.197619-4-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409113934.197619-1-michal.orzel@amd.com> References: <20260409113934.197619-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF00016160:EE_|SJ2PR12MB8882:EE_ X-MS-Office365-Filtering-Correlation-Id: ad4b818d-e5c2-4db3-f187-08de962cb212 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|18002099003|22082099003|56012099003; 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Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") Signed-off-by: Michal Orzel --- xen/arch/arm/gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index b3e104ea4ad0..5641ee870f23 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1631,7 +1631,7 @@ static int gicv3_iomem_deny_access(struct domain *d) if ( vbase != INVALID_PADDR ) { mfn = vbase >> PAGE_SHIFT; - nr = PFN_UP(csize); + nr = PFN_UP(vsize); return iomem_deny_access(d, mfn, mfn + nr - 1); } -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:41:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:41:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277120.1562386 (Exim 4.92) (envelope-from ) id 1wAnll-0002VC-7H; Thu, 09 Apr 2026 11:41:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277120.1562386; Thu, 09 Apr 2026 11:41:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnll-0002V5-4a; Thu, 09 Apr 2026 11:41:57 +0000 Received: by outflank-mailman (input) for mailman id 1277120; Thu, 09 Apr 2026 11:41:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAnlk-0002Uz-BA for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 11:41:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAnlj-009MBk-NJ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 13:41:55 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d79081-5cb7-0a2a0a5109dd-0a2a450bedb8-6 for ; Thu, 09 Apr 2026 13:41:55 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d79083-bca8-0a2a450b0019-d155802ee0f7-3 for ; Thu, 09 Apr 2026 13:41:55 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so11428695e9.2 for ; Thu, 09 Apr 2026 04:41:55 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. [78.146.242.105]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488cd1b2799sm71467005e9.6.2026.04.09.04.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 04:41:53 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1775734915; x=1776339715; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=9KaDm/yMBIrw6CzspjElk4N8efh36OMRuJoJnnqxtrc=; b=YEGNt9fgH4RdkQ8uji4Uebdtd+IS5hS4yLGTRNeuQXcqBMoZPosom6lCiXRO5+mniM 0IMCLmW3kO/whA5FR3rirIJCN9Utu1Ycze2XeaFvlPf1uVXBlXY0OgmS/lDLJ9/BxzsH pA2eNaSOyjdapx6CfPRZx0hxOVfIEdIHmB06s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775734915; x=1776339715; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=9KaDm/yMBIrw6CzspjElk4N8efh36OMRuJoJnnqxtrc=; b=nImdkvNJq1nIGHOMQn4v5agMcnTw7URgGjzCeKVJyppzJmL5ep6ivOZVFpDD4l6WrD bxAr52qqzFBqtsr3UhjWNVTBG0pNcDJZWY6v61ODa2rQXoL+gvdw9LPPhlWtLL+1LXqV jmJ3pnFoFcgVEl+sB3lPGeLQnhj8rhFR9BEhWzRDCe5Ll7TdNOfokj7NIqHtjmC7hkfc fuCaac9RnLjPdSdHLLAMNV9eHjBelTmBl4ILmyRjCJ1h0mfU6Gki3xidgw7NltYNfICN CoIzXe98PSiJPNUx+b0k5EVWrQj/0C/TQv1tq052N3rKyDKI+plVVzocUGrQDsi4+eAi MlsA== X-Gm-Message-State: AOJu0Yz/EQbsSW0VpxGOJeUl1bwQPhAFfOJTYWWOMHwNfSFJJkDMl2CF T3OVF7GUxQG3yPHILSiSTDRUh3aIvrhEHtQRcTBP1bkQiGpLjnnH0rYdmjAR9j0FVobVDWvAaxG //nV1 X-Gm-Gg: AeBDiesW+i9/a3zFdwrC/apnFLkx+K856aVjf7ETH2NWkg7TEelR3C7NCE79Kzrbfaa RQNvlgSvbNNFtM9ZK5Xh4vzTRWjLG9+3mwN3+4AaFOEHR5f1cPY1teTZaJfnVmdmZ/mjCeJ92tX jiSr3oQTDs35wSJhetXmDHZxE/nemjiQ0NlCXY4fGYlv9Nxy4Mj9+H92P6Nqy3XRBjNFM7Lfvpk DwAQj8VvrZyHjyzENOPMVz8ngAlWW+JQoEtrxTeUJAdeeZvc+8kVauQsrsBJmOF8GNrEo/X0Ka2 41udaDOpG3k2NT/2QoiWxW9ReDg6jGlag+EpRCbHOib1EnTDXO6bOLtSsK5Vmv3lBdJZZDdlalq 1wu/KYxchSZLBB5IrAoeWCxplJfKtw1wUmK8R/s+01hBs1GPvjHvavj1snISUC1HcjF3SGgrLOU E2jIvk2DzaM21nIiXFXqFjREtH1zMYiltstmb4GOPsFK7TMRZqr8WjW5h8mQIB1oAKHP/4jJAmC PQnyIKgdFM7s1g= X-Received: by 2002:a05:600c:3546:b0:487:5c0:671f with SMTP id 5b1f17b1804b1-488996e8774mr351215065e9.9.1775734913619; Thu, 09 Apr 2026 04:41:53 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH v2] x86: Avoid using .byte for instructions where safe to do so Date: Thu, 9 Apr 2026 12:41:51 +0100 Message-Id: <20260409114151.179408-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775734915-F61C72A1-54C6BD06/0/0 X-purgate-type: clean X-purgate-size: 7378 The new toolchain baseline knows XGETBV, VPXOR and VPOR. For the other cases using .byte, annotate the toolchain minima. No functional change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie v2 * CLZERO, {WR,RD}PKRU can't be named yet. Pull out of previous series as it's somewhat unrelated. The XSAVE cleanup has other prerequiesites before it can move away from .byte. --- xen/arch/x86/arch.mk | 4 +++ xen/arch/x86/include/asm/asm-defns.h | 1 + xen/arch/x86/include/asm/msr.h | 2 ++ xen/arch/x86/include/asm/prot-key.h | 4 +-- xen/arch/x86/include/asm/xstate.h | 3 +-- xen/arch/x86/x86_emulate/0f01.c | 2 +- xen/arch/x86/x86_emulate/x86_emulate.c | 34 ++++++++++++-------------- 7 files changed, 27 insertions(+), 23 deletions(-) diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk index 0b42e6312fac..cd0602a79aaf 100644 --- a/xen/arch/x86/arch.mk +++ b/xen/arch/x86/arch.mk @@ -17,7 +17,11 @@ CFLAGS-$(CONFIG_CC_IS_GCC) += -malign-data=abi $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) $(call cc-option-add,CFLAGS,CC,-Wnested-externs) $(call as-option-add,CFLAGS,CC,".equ \"x\"$(comma)1",-DHAVE_AS_QUOTED_SYM) + +# Binutils >= 2.31, Clang >= 7 $(call as-option-add,CFLAGS,CC,"movdiri %rax$(comma)(%rax)",-DHAVE_AS_MOVDIR) + +# Binutils >= 2.33, Clang >= 9 $(call as-option-add,CFLAGS,CC,"enqcmd (%rax)$(comma)%rax",-DHAVE_AS_ENQCMD) # Check to see whether the assembler supports the .nop directive. diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h index 239dc3af096c..dc9b3ce272fd 100644 --- a/xen/arch/x86/include/asm/asm-defns.h +++ b/xen/arch/x86/include/asm/asm-defns.h @@ -1,5 +1,6 @@ #include +/* binutils >= 2.26 or Clang >= 3.8 */ .macro clzero .byte 0x0f, 0x01, 0xfc .endm diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 941a7612f4ba..1377d156f4e1 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -63,6 +63,8 @@ static inline void wrmsrns(uint32_t msr, uint64_t val) /* * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant CS * prefix to avoid a trailing NOP. + * + * Binutils >= 2.40, Clang >= 16 */ alternative_input(".byte 0x2e; wrmsr", ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS, diff --git a/xen/arch/x86/include/asm/prot-key.h b/xen/arch/x86/include/asm/prot-key.h index 8fb15b5c32e9..e8550e0c9203 100644 --- a/xen/arch/x86/include/asm/prot-key.h +++ b/xen/arch/x86/include/asm/prot-key.h @@ -19,7 +19,7 @@ static inline uint32_t rdpkru(void) { uint32_t pkru; - asm volatile ( ".byte 0x0f,0x01,0xee" + asm volatile ( ".byte 0x0f,0x01,0xee" /* binutils >= 2.26 or Clang >= 3.8 */ : "=a" (pkru) : "c" (0) : "dx" ); return pkru; @@ -27,7 +27,7 @@ static inline uint32_t rdpkru(void) static inline void wrpkru(uint32_t pkru) { - asm volatile ( ".byte 0x0f,0x01,0xef" + asm volatile ( ".byte 0x0f,0x01,0xef" /* binutils >= 2.26 or Clang >= 3.8 */ :: "a" (pkru), "d" (0), "c" (0) ); } diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/xstate.h index c96d75e38b25..0519379edb57 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -118,8 +118,7 @@ static inline uint64_t xgetbv(unsigned int index) uint32_t lo, hi; ASSERT(index); /* get_xcr0() should be used instead. */ - asm volatile ( ".byte 0x0f,0x01,0xd0" /* xgetbv */ - : "=a" (lo), "=d" (hi) : "c" (index) ); + asm volatile ( "xgetbv" : "=a" (lo), "=d" (hi) : "c" (index) ); return lo | ((uint64_t)hi << 32); } diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0f01.c index 4d36c7d289a5..87d338f0c74a 100644 --- a/xen/arch/x86/x86_emulate/0f01.c +++ b/xen/arch/x86/x86_emulate/0f01.c @@ -122,7 +122,7 @@ int x86emul_0f01(struct x86_emulate_state *s, { case vex_none: /* serialize */ host_and_vcpu_must_have(serialize); - asm volatile ( ".byte 0x0f, 0x01, 0xe8" ); + asm volatile ( ".byte 0x0f, 0x01, 0xe8" ); /* Binutils >= 2.34, Clang >= 11 */ break; case vex_f2: /* xsusldtrk */ vcpu_must_have(tsxldtrk); diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c index 11d145e17723..e58735ee9590 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -4748,27 +4748,25 @@ x86_emulate( */ if ( vex.l ) { - /* vpxor %xmmN, %xmmN, %xmmN */ - asm volatile ( ".byte 0xc5,0xf9,0xef,0xc0" ); - asm volatile ( ".byte 0xc5,0xf1,0xef,0xc9" ); - asm volatile ( ".byte 0xc5,0xe9,0xef,0xd2" ); - asm volatile ( ".byte 0xc5,0xe1,0xef,0xdb" ); - asm volatile ( ".byte 0xc5,0xd9,0xef,0xe4" ); - asm volatile ( ".byte 0xc5,0xd1,0xef,0xed" ); - asm volatile ( ".byte 0xc5,0xc9,0xef,0xf6" ); - asm volatile ( ".byte 0xc5,0xc1,0xef,0xff" ); + asm volatile ( "vpxor %xmm0, %xmm0, %xmm0" ); + asm volatile ( "vpxor %xmm1, %xmm1, %xmm1" ); + asm volatile ( "vpxor %xmm2, %xmm2, %xmm2" ); + asm volatile ( "vpxor %xmm3, %xmm3, %xmm3" ); + asm volatile ( "vpxor %xmm4, %xmm4, %xmm4" ); + asm volatile ( "vpxor %xmm5, %xmm5, %xmm5" ); + asm volatile ( "vpxor %xmm6, %xmm6, %xmm6" ); + asm volatile ( "vpxor %xmm7, %xmm7, %xmm7" ); } else { - /* vpor %xmmN, %xmmN, %xmmN */ - asm volatile ( ".byte 0xc5,0xf9,0xeb,0xc0" ); - asm volatile ( ".byte 0xc5,0xf1,0xeb,0xc9" ); - asm volatile ( ".byte 0xc5,0xe9,0xeb,0xd2" ); - asm volatile ( ".byte 0xc5,0xe1,0xeb,0xdb" ); - asm volatile ( ".byte 0xc5,0xd9,0xeb,0xe4" ); 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260401163521.3603665-3-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775735222-1734C2A1-D05DD6E1/0/0 X-purgate-type: clean X-purgate-size: 5209 On 01.04.2026 18:35, Ross Lagerwall wrote: > --- a/xen/common/smp.c > +++ b/xen/common/smp.c > @@ -24,13 +24,15 @@ > /* > * Structure and data for smp_call_function()/on_selected_cpus(). > */ > -static DEFINE_SPINLOCK(call_lock); > -static struct call_data_struct { > +struct call_data_struct { > void (*func) (void *info); > void *info; > int wait; > - cpumask_t selected; > -} call_data; > + cpumask_t selected __cacheline_aligned; The adding of the alignment attribute isn't strictly required here, is it? Can it, with its own justification, be split out? However, wrt what I said in the first reply, putting a full cpumask_t in per-CPU data is even a little worse than having one as a global. Imo this also wants to become cpumask_var_t. Then the attribute wouldn't be quite applicable anymore anyway. > @@ -50,55 +52,84 @@ void on_selected_cpus( > void *info, > int wait) > { > + struct call_data_struct *data; > + unsigned int cpu = smp_processor_id(); > + > ASSERT(local_irq_is_enabled()); > ASSERT(cpumask_subset(selected, &cpu_online_map)); > > - spin_lock(&call_lock); > + if ( cpumask_empty(selected) ) > + return; > + > + data = &this_cpu(call_data); > > - cpumask_copy(&call_data.selected, selected); > + if ( !data->wait ) > + { > + /* Wait for any previous async call to complete */ > + while ( !cpumask_empty(&data->selected) ) > + cpu_relax(); > + > + cpumask_clear_cpu(cpu, &tasks); In the description you say "Track which CPUs are currently running on_selected_cpus()", yet as per this the bit can remain set after the function was left. Which isn't just an issue of describing things correctly; there's also a performance concern: The IPI handler(s) will need to carry out more work than necessary. That's not a lot of work (only the subsequent cpumask_test_cpu() there), but also not nothing. I also think another barrier is needed above here: We may only clear the bit in tasks when the empty ->selected is globally visible. More generally, since the bit in tasks is what everything derives from, barriers are apparently needed around all of its updating / accessing. Which also meant that ... > + } > > - if ( cpumask_empty(&call_data.selected) ) > - goto out; > + data->func = func; > + data->info = info; > + data->wait = wait; > > - call_data.func = func; > - call_data.info = info; > - call_data.wait = wait; > + smp_wmb(); ... besides (as already indicated) this barrier needing to move ... > - smp_send_call_function_mask(&call_data.selected); > + cpumask_copy(&data->selected, selected); ... here, I think that another one is going to be needed ... > - while ( !cpumask_empty(&call_data.selected) ) > - cpu_relax(); > + cpumask_set_cpu(cpu, &tasks); ... here, such that ... > -out: > - spin_unlock(&call_lock); > + smp_send_call_function_mask(&data->selected); ... upon receipt of the IPI the target sees the up-to-date value. > + if ( wait ) > + { > + while ( !cpumask_empty(&data->selected) ) > + cpu_relax(); > + > + cpumask_clear_cpu(cpu, &tasks); > + } > } > > void smp_call_function_interrupt(void) > { > - void (*func)(void *info) = call_data.func; > - void *info = call_data.info; > unsigned int cpu = smp_processor_id(); > - > - if ( !cpumask_test_cpu(cpu, &call_data.selected) ) > - return; > + unsigned int i; > + struct call_data_struct *data; > + void (*func)(void *info); > + void *info; > > irq_enter(); > > - if ( unlikely(!func) ) > - { > - cpumask_clear_cpu(cpu, &call_data.selected); > - } > - else if ( call_data.wait ) > - { > - (*func)(info); > - smp_mb(); > - cpumask_clear_cpu(cpu, &call_data.selected); > - } > - else > + for_each_cpu ( i, &tasks ) > { > - smp_mb(); > - cpumask_clear_cpu(cpu, &call_data.selected); > - (*func)(info); > + data = &per_cpu(call_data, i); > + > + if ( !cpumask_test_cpu(cpu, &data->selected) ) > + continue; > + > + smp_rmb(); > + func = data->func; > + info = data->info; > + > + if ( unlikely(!func) ) > + { > + cpumask_clear_cpu(cpu, &data->selected); > + } > + else if ( data->wait ) > + { > + (*func)(info); > + smp_mb(); > + cpumask_clear_cpu(cpu, &data->selected); > + } > + else > + { > + smp_mb(); > + cpumask_clear_cpu(cpu, &data->selected); > + (*func)(info); I understand you only re-indent this code, but I'm struggling with the purpose of the barrier here. With the smp_rmb() above there are no reads to isolate (data->func and data->info can't change while the bit in data->selected is still set). And there are no earlier writes at all, unless anything done outside of the interrupt handler would matter. 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This > incorrectly rejects input that would exactly fill the array. > > For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 > for dom0 would fail. > > Change >= to > so that exactly filling the array is permitted. > > Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") > Signed-off-by: Michal Orzel > --- > xen/common/llc-coloring.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c > index eb7c72b24023..30c1594dac9f 100644 > --- a/xen/common/llc-coloring.c > +++ b/xen/common/llc-coloring.c > @@ -78,7 +78,7 @@ static int __init parse_color_config(const char *buf, unsigned int colors[], > > if ( end >= NR_LLC_COLORS || start > end || > (end - start) >= (UINT_MAX - *num_colors) || > - (*num_colors + (end - start + 1)) >= max_num_colors ) > + (*num_colors + (end - start + 1)) > max_num_colors ) > return -EINVAL; > > /* Colors are range checked in check_colors() */ This boundary was changed by https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=cba8a584de171c8c4510709c2edc9f1cf86b21ab because it was off-by-one. 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pr=C Message-ID: Date: Thu, 9 Apr 2026 12:49:17 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] xen/arm: Fix off-by-one in iomem_deny_access() calls To: Michal Orzel , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , "Volodymyr Babchuk" References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-2-michal.orzel@amd.com> Content-Language: en-US From: "Halder, Ayan Kumar" In-Reply-To: <20260409113934.197619-2-michal.orzel@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013F:EE_|CY1PR12MB9582:EE_ X-MS-Office365-Filtering-Correlation-Id: 809d6438-0505-438f-6bc4-08de962e094b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: L98HfzrB6gZtyuGSCMGJhjE8IHLpJVTsh86Fo3fVZVDYLlBsm6k7JLyWSQoataJKmyR7K6DDxknQbp9r1arPdBbRSE57mD9BrVrNAzGGH+CM9A6Q8dI3TATZisGha5+jUSVXiPt+1hz4kJKt7z4wZSZLuck8FT5SvChpZNaTOngfuwd72CagkwWVyHMuJBvTG6Q5onzxU/ZteZOKSJXUGLGy4Q7UL/7CbRaNHOaw9w0ajnQnesF5JE86S5NoPFrD032Uj93p/SmOXAnAw7rB42JMtr+oyPPUieUbKaBp9oCruFtAgYZSiAOZ+432jNkABzyji/kjNAsHpG+ChqRkmn6jJ+oofV+YVsZpc1TUKOXuD7L6M/Mgn44bWnQn3ydjJdOWPPCU0eSS87rAK74JeUrO2sBvkIHMAAoVdGPJRnQqMgd8UgK7mlt3k3oYQPG/jth0XUqkAJWDYEBXYtPFzIPVntciqi8Mqu2wYHSjGzMOkm4gOdvPGMeWIx84HV7/PlpZv7W4509VYUo0L5kZw5Pe8VCmhTxOnct7GN7dHHgYp2fMY0D2jS0bjspdVLSVRA7lmqu67Orgocn24mXb6DuYvG2kcucNhzgd4E0XZEVy4CDR5M0PIAcpqmYXrFnosWxOhWVJS5at4TTV3BAFsLYWUf5sasARU4fN/7ZCTVhi/t98o9UvQWn/NJWc9LVj9J+i0mjtVeLLwPZK4ROFhsR1Vddp+F/V8+yz9rmpJDwg4gmWF9nDFuGp3PABsp52Kf5jMe/OAYtP68UVism2Ig== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LNE1NgjSGVQ9xLQm19ZhCEZ3LaDIdJbIMxMJG1Kfx5R4nEt0GyswsdLNwFAFzhoc8wVi1+HdrED+Daex9MgCy0wWs/YYju4LAW5VgroqiCVeqPH0rW1dZL5rO+e0SVNF4x2+HtP5aZm2oNGiA9D2q5IxSbvR2cg+odrN/agJ9QX/DX/HvydXAEO76XAsG874C4627T7Mitq53cxD/6Xv4yjAVVGOVokkIRjNmeuZCtkXoou7yCYKxw4MavtdIHmkicvwqpT3rW1NT7io9Dnw32xGN1qd5NiaV7kCUvcVYfdph284eCWb3XT4SXdRrvt9O9dTCOc+yGQPtGl33T4EL1OqANFooiJO8ga/fXTqVBR/w8ChYyJ5+v4IyknoscIMEODQVXV1X0PRTUsnpNr4upZBnsds6u7jXrbj4JfKf5vp3xCQR4ldY2SThz8B5xQ1 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:49:20.0845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 809d6438-0505-438f-6bc4-08de962e094b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9582 X-purgate-ID: tlsNG-42698a/1775735366-EE3542A1-C5046BC6/0/0 X-purgate-type: clean X-purgate-size: 5438 Hi Michal, Apologies if my review is weird, I have been looking into too much of safety stuff. On 09/04/2026 12:39, Michal Orzel wrote: > iomem_deny_access() wraps rangeset_remove_range() which takes inclusive > endpoints. All call sites in the GIC and ACPI code pass 'mfn + nr' (or > 'mfn + 1' for single-page regions) as the end parameter, which causes > one extra page beyond each region to be denied. > > For single-page regions, use 'mfn' as the end (denying exactly one page). > For all multi-page regions, use 'mfn + nr - 1'. Just reading this and the change below, it seems that the issue was caught while doing some boundary value analysis. In this specific case, it seems the boundary values were set incorrectly. Can you explain a bit more (the boundary/edge cases) in the commit message and give some reference to test (can be even a different repo or something) on how you caught this and verified it to be correct ? We can keep this test somewhere (and tag it to the commit) even if such tests does not make sense to be upstreamed. - Ayan > > This matches the correct pattern used elsewhere, e.g. in device.c. > > Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") > Fixes: 66158be465 ("ARM: ITS: Deny hardware domain access to ITS") > Fixes: 97e9875646 ("arm/acpi: Permit MMIO access of Xen unused devices for Dom0") > Signed-off-by: Michal Orzel > --- > xen/arch/arm/acpi/domain_build.c | 2 +- > xen/arch/arm/gic-v2.c | 8 ++++---- > xen/arch/arm/gic-v3-its.c | 2 +- > xen/arch/arm/gic-v3.c | 8 ++++---- > 4 files changed, 10 insertions(+), 10 deletions(-) > > diff --git a/xen/arch/arm/acpi/domain_build.c b/xen/arch/arm/acpi/domain_build.c > index 5a117001ef11..249d899c3337 100644 > --- a/xen/arch/arm/acpi/domain_build.c > +++ b/xen/arch/arm/acpi/domain_build.c > @@ -48,7 +48,7 @@ static int __init acpi_iomem_deny_access(struct domain *d) > { > mfn = spcr->serial_port.address >> PAGE_SHIFT; > /* Deny MMIO access for UART */ > - rc = iomem_deny_access(d, mfn, mfn + 1); > + rc = iomem_deny_access(d, mfn, mfn); > if ( rc ) > return rc; > } > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > index b23e72a3d05d..014f9559673b 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -1079,23 +1079,23 @@ static int gicv2_iomem_deny_access(struct domain *d) > unsigned long mfn, nr; > > mfn = dbase >> PAGE_SHIFT; > - rc = iomem_deny_access(d, mfn, mfn + 1); > + rc = iomem_deny_access(d, mfn, mfn); > if ( rc ) > return rc; > > mfn = hbase >> PAGE_SHIFT; > - rc = iomem_deny_access(d, mfn, mfn + 1); > + rc = iomem_deny_access(d, mfn, mfn); > if ( rc ) > return rc; > > mfn = cbase >> PAGE_SHIFT; > nr = DIV_ROUND_UP(csize, PAGE_SIZE); > - rc = iomem_deny_access(d, mfn, mfn + nr); > + rc = iomem_deny_access(d, mfn, mfn + nr - 1); > if ( rc ) > return rc; > > mfn = vbase >> PAGE_SHIFT; > - return iomem_deny_access(d, mfn, mfn + nr); > + return iomem_deny_access(d, mfn, mfn + nr - 1); > } > > #ifdef CONFIG_ACPI > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index 9ba068c46fcb..e38aa8711744 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -1009,7 +1009,7 @@ int gicv3_its_deny_access(struct domain *d) > { > mfn = paddr_to_pfn(its_data->addr); > nr = PFN_UP(its_data->size); > - rc = iomem_deny_access(d, mfn, mfn + nr); > + rc = iomem_deny_access(d, mfn, mfn + nr - 1); > if ( rc ) > { > printk("iomem_deny_access failed for %lx:%lx \r\n", mfn, nr); > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index bc07f97c16ab..b3e104ea4ad0 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -1602,7 +1602,7 @@ static int gicv3_iomem_deny_access(struct domain *d) > > mfn = dbase >> PAGE_SHIFT; > nr = PFN_UP(SZ_64K); > - rc = iomem_deny_access(d, mfn, mfn + nr); > + rc = iomem_deny_access(d, mfn, mfn + nr - 1); > if ( rc ) > return rc; > > @@ -1614,7 +1614,7 @@ static int gicv3_iomem_deny_access(struct domain *d) > { > mfn = gicv3.rdist_regions[i].base >> PAGE_SHIFT; > nr = PFN_UP(gicv3.rdist_regions[i].size); > - rc = iomem_deny_access(d, mfn, mfn + nr); > + rc = iomem_deny_access(d, mfn, mfn + nr - 1); > if ( rc ) > return rc; > } > @@ -1623,7 +1623,7 @@ static int gicv3_iomem_deny_access(struct domain *d) > { > mfn = cbase >> PAGE_SHIFT; > nr = PFN_UP(csize); > - rc = iomem_deny_access(d, mfn, mfn + nr); > + rc = iomem_deny_access(d, mfn, mfn + nr - 1); > if ( rc ) > return rc; > } > @@ -1632,7 +1632,7 @@ static int gicv3_iomem_deny_access(struct domain *d) > { > mfn = vbase >> PAGE_SHIFT; > nr = PFN_UP(csize); > - return iomem_deny_access(d, mfn, mfn + nr); > + return iomem_deny_access(d, mfn, mfn + nr - 1); > } > > return 0; From xen-devel-bounces@lists.xenproject.org Thu Apr 09 11:55:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 11:55:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277168.1562423 (Exim 4.92) (envelope-from ) id 1wAnyW-0006aj-W6; Thu, 09 Apr 2026 11:55:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277168.1562423; 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I can spot only the former; instead there is ... Stale comment, I will drop that as vtimer init is called per vCPU. > >> --- a/xen/arch/riscv/domain.c >> +++ b/xen/arch/riscv/domain.c >> @@ -288,6 +288,33 @@ void sync_vcpu_execstate(struct vcpu *v) >> /* Nothing to do -- no lazy switching */ >> } >> >> +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) >> +{ >> + return 0; >> +} >> + >> +int arch_domain_create(struct domain *d, >> + struct xen_domctl_createdomain *config, >> + unsigned int flags) >> +{ >> + int rc = 0; >> + >> + if ( is_idle_domain(d) ) >> + return 0; >> + >> + if ( (rc = p2m_init(d)) != 0) >> + goto fail; >> + >> + d->arch.next_phandle = GUEST_PHANDLE_LAST + 1; > > ... this, which I can't make any sense of. I can't find matching Arm code > either, which might otherwise have helped. There are some cases when we are creating a node for guest DTB we should know which phandles aren't busy (to avoid the case when some nodes have the same phandle) so to track that this struct field was introduced. I will check Arm code as I expect that phandle should be generated somehow on their side too. > >> + return rc; >> + >> + fail: >> + d->is_dying = DOMDYING_dead; >> + arch_domain_destroy(d); > > (At least) for the use here, that other function would better also move out > of stubs.c at the same time (and no longer have unconditional BUG_ON() in it). > >> --- a/xen/arch/riscv/stubs.c >> +++ b/xen/arch/riscv/stubs.c >> @@ -101,14 +101,7 @@ void dump_pageframe_info(struct domain *d) >> BUG_ON("unimplemented"); >> } >> >> -int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) >> -{ >> - BUG_ON("unimplemented"); >> -} >> - >> -int arch_domain_create(struct domain *d, >> - struct xen_domctl_createdomain *config, >> - unsigned int flags) >> +void vcpu_switch_to_aarch64_mode(struct vcpu *v) > > What is this? Surely nothing with this name should exist under riscv/. Good question. I don't know how it appeared here. I will drop it. > >> --- a/xen/include/public/device_tree_defs.h >> +++ b/xen/include/public/device_tree_defs.h >> @@ -14,6 +14,7 @@ >> */ >> #define GUEST_PHANDLE_GIC (65000) >> #define GUEST_PHANDLE_IOMMU (GUEST_PHANDLE_GIC + 1) >> +#define GUEST_PHANDLE_LAST GUEST_PHANDLE_IOMMU > > This, to me, looks like a questionable addition to the public interface. > Yet I'm not a DT person, so I may simply be missing why something like > this might be wanted (and how stable it then would be, long term). I will double check if I have to generate phandle for the node I'm creating for guest DTB. It looks like I am confused something and it could be just dropped. Considering that only RISC-V needs that at the moment (if need it all?) I will put somewhere in riscv/ this definition. Thanks. ~ Oleksii. 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pr=C Message-ID: <83152d2d-aa85-4a06-a73d-25c1d2b06fa8@amd.com> Date: Thu, 9 Apr 2026 12:57:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() To: Michal Orzel , CC: Andrew Cooper , Anthony PERARD , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-3-michal.orzel@amd.com> Content-Language: en-US From: "Halder, Ayan Kumar" In-Reply-To: <20260409113934.197619-3-michal.orzel@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: ayankuma@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|DS0PR12MB7629:EE_ X-MS-Office365-Filtering-Correlation-Id: 6865b28f-f85a-490a-08ca-08de962f1ea6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /JllEm92xPiNdKyPBBP4w3yj+vkfScHjVj9e85sonM/Vpc+Bsth34UHn/amlJPBN3GnNsRtBYfdX2iWpTiMcYY3th4nhX74dP6ik5bgqNcP1Nfx80Di+30BXvaQmDlakEPgF0dY1kRhVt51S4IX6lXq1iprjf53vJRcKPZmDtr71Sx6bhfuSAPxS2XZU9irb5yC7U/5AFWiqu2AjhMwGcfIU0pfBcNEcbPcBL+I10wnezisNwUPSVeRq75aXJfjCblDycsxFtZKyp+yYjKq3OEcNbKy8/LAql1CorCBeqWjjmNx3S0ZhSTWZwk9mDiRvC8i9FxvOf/FAQ3LIpNJ9AF35PQgY8tnKwHKOzcxf2WrF+81ajsM9D5uFvF50GAyKr0mQzh8i5LUd7X7Pa4/Ze2EurD+mbC1SpkwS2+AGhRpkkGMNtFrp6TrHAt4hAJT3 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 11:57:05.4617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6865b28f-f85a-490a-08ca-08de962f1ea6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7629 X-purgate-ID: tlsNG-c201ff/1775735831-2312596F-C0C8FA93/0/0 X-purgate-type: clean X-purgate-size: 462 On 09/04/2026 12:39, Michal Orzel wrote: > The check uses >= to compare the total number of colors against > max_num_colors (which is ARRAY_SIZE of the colors array). This > incorrectly rejects input that would exactly fill the array. This seems related to BVA as well. > > For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 > for dom0 would fail. Why does it fail ? Is it because the max number of colors can be 15. - Ayan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:03:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:03:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277215.1562441 (Exim 4.92) (envelope-from ) id 1wAo6b-0000tV-Aj; Thu, 09 Apr 2026 12:03:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277215.1562441; Thu, 09 Apr 2026 12:03:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAo6b-0000tO-7k; Thu, 09 Apr 2026 12:03:29 +0000 Received: by outflank-mailman (input) for mailman id 1277215; Thu, 09 Apr 2026 12:03:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAo6a-0000tI-Hr for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:03:28 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAo6Y-0097TR-Bu for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 14:03:27 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7958f-5cb7-0a2a0a5109dd-0a2a450ce332-4 for ; Thu, 09 Apr 2026 14:03:27 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7958f-f40c-0a2a450c0019-d1558035a944-3 for ; Thu, 09 Apr 2026 14:03:27 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso10174865e9.1 for ; Thu, 09 Apr 2026 05:03:27 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260409114151.179408-1-andrew.cooper3@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775736207-FE350A3D-294357A1/0/0 X-purgate-type: clean X-purgate-size: 314 On 09.04.2026 13:41, Andrew Cooper wrote: > The new toolchain baseline knows XGETBV, VPXOR and VPOR. > > For the other cases using .byte, annotate the toolchain minima. > > No functional change. > > Signed-off-by: Andrew Cooper Acked-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:13:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:13:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277224.1562451 (Exim 4.92) (envelope-from ) id 1wAoG7-0003Jy-6w; Thu, 09 Apr 2026 12:13:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277224.1562451; Thu, 09 Apr 2026 12:13:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAoG7-0003Jr-34; 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pr=C Message-ID: <0fb39238-2588-4471-aea5-ec8e695adbc6@amd.com> Date: Thu, 9 Apr 2026 13:12:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] xen/arm: gic-v3: Use vsize instead of csize for virtual CPU interface To: Michal Orzel , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , "Volodymyr Babchuk" References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-4-michal.orzel@amd.com> Content-Language: en-US From: "Halder, Ayan Kumar" In-Reply-To: <20260409113934.197619-4-michal.orzel@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|MN0PR12MB5716:EE_ X-MS-Office365-Filtering-Correlation-Id: 454baa88-c36c-49d7-b7ed-08de96315c46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VSfhaKwkcDsKVe+UAKDEvCzlkwluSXolhTWfIgAd4FP98wXz6Dqlcr57369biR8N/d7lMDWKOSgm+0dlHD1ST7TshBoGftFgAuAQAuie4d8B5s6ga8MA9oF9IzxRwWxAEcpIv/ZYVZaG7rJIRj9CSgNUQgDlDMKZw1KXJLsm9SDt7UxGHTAiNnZfdDMNpEW3VO4VTwUa9r+PxrkOA48XjZicFEFkaqUoEL56JwZXpZ80+2KRWRVoLBB0Ie3DD/M18vLUHIQfTnwNo/TF9Ej7FDAWH6Gi2omnwOKIdyUC8j46JIllOL01GZEtdIwN1k5LxKMWRoD0o5sROaJAdcZlT5TZ/DzJdrkZpOI+Fphk0RJVMz1fnYBbnucjzvjSLRM8BpHVXRJgkXg1GOl0Qcq8U0C9chzBYjtJMxL6otvWeLXbRjT/LwmZThjWSCG6E1qq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 12:13:07.8455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 454baa88-c36c-49d7-b7ed-08de96315c46 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5716 X-purgate-ID: tlsNG-d25034/1775736794-FD756A3D-384CEBC3/0/0 X-purgate-type: clean X-purgate-size: 504 On 09/04/2026 12:39, Michal Orzel wrote: > gicv3_iomem_deny_access() incorrectly uses csize (physical CPU > interface size) instead of vsize (virtual CPU interface size) when > calculating the number of pages to deny for the virtual CPU interface > region at vbase. good catch > > Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") > Signed-off-by: Michal Orzel Reviewed-by: Ayan Kumar Halder - Ayan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:22:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:22:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277234.1562459 (Exim 4.92) (envelope-from ) id 1wAoOe-0005MK-Vz; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775737324; x=1776007324; bh=6/LSDButP8uM6JPqcrKxjpaj3SVY0qzt4DP43fBQAec=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=B/T9oqJ5Sw+LuRI0Ne/QIm5RpGZMyK4F7eEdZpWxFWLXKkks7x9l+/UToR87vF+QL E5ncMMa/mXOYrA8ZkBdDuI9Wtczrr8d85MfAHZGE77npUUXgAt41reTynoMEgHyD9J 3ry2NHbMergu4kqd9r1GtIDjINN3dbHCcjxzu2jia5MtY9AyXritMpwKMFBW7u0H1D aCg6Bn/ZbtuSNUfqhi29XtB/lv3nGsYPy4KT2AMB10tXvuKFkVBXEeesuLRMa18Rup Np/SoZjVHB205SzGszm8r9+Q8dJCg4q7qmCd21qlsZlq5vCBYEPr7NIiHMKrl34Q3e 3jZvdAQP2fpvw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775737324; x=1775997824; i=teddy.astie@vates.tech; bh=6/LSDButP8uM6JPqcrKxjpaj3SVY0qzt4DP43fBQAec=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Yg8vnszdQtBIFMQHdBqjHkrTnPCVpqk4TMH5hlQY4KnyReQ/S1CX0b7AEgJu8qbzV eFexKGKGkPnhqY/k7m4wOvB6Cq+suZOysh1Kjgb4YF+oIH0/vFFPEYWHCuf9CQKlPo SROrQEGpjvFpKiwCNbSoShku09SwYuQWR72Qx9OuEtaV+RWM5KowLrxAUq5TxfzmY0 dII+0oEBQb2RH9qc2ITuNFE5sJzJtnZmJkwDnugvaLIzFdgsOUmM5ULi71FB7yX7mO qaVmEBUAFugfFgnqKs3cKp8uu+OMdjpHS/dJR9JBlS+62QvdXlvAxfIZO4X9s1tuKx sUgKeTs5YS4uA== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=20v2]=20x86:=20Avoid=20using=20.byte=20for=20instructions=20where=20safe=20to=20do=20so?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775737320936 Message-Id: To: "Andrew Cooper" , Xen-devel Cc: "Jan Beulich" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" References: <20260409114151.179408-1-andrew.cooper3@citrix.com> In-Reply-To: <20260409114151.179408-1-andrew.cooper3@citrix.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.f245dc9079344828b0ea5d8e3faeb5b4?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 12:22:04 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1775737326-AF5383D8-16B0ED0B/0/0 X-purgate-type: clean X-purgate-size: 8076 Le 09/04/2026 =C3=A0 13:43, Andrew Cooper a =C3=A9crit=C2=A0: > The new toolchain baseline knows XGETBV, VPXOR and VPOR. > > For the other cases using .byte, annotate the toolchain minima. > > No functional change. > > Signed-off-by: Andrew Cooper > --- > CC: Jan Beulich > CC: Roger Pau Monn=C3=A9 > CC: Teddy Astie > > v2 > * CLZERO, {WR,RD}PKRU can't be named yet. > > Pull out of previous series as it's somewhat unrelated. The XSAVE cleanu= p has > other prerequiesites before it can move away from .byte. > --- > xen/arch/x86/arch.mk | 4 +++ > xen/arch/x86/include/asm/asm-defns.h | 1 + > xen/arch/x86/include/asm/msr.h | 2 ++ > xen/arch/x86/include/asm/prot-key.h | 4 +-- > xen/arch/x86/include/asm/xstate.h | 3 +-- > xen/arch/x86/x86_emulate/0f01.c | 2 +- > xen/arch/x86/x86_emulate/x86_emulate.c | 34 ++++++++++++-------------- > 7 files changed, 27 insertions(+), 23 deletions(-) > > diff --git a/xen/arch/x86/arch.mk b/xen/arch/x86/arch.mk > index 0b42e6312fac..cd0602a79aaf 100644 > --- a/xen/arch/x86/arch.mk > +++ b/xen/arch/x86/arch.mk > @@ -17,7 +17,11 @@ CFLAGS-$(CONFIG_CC_IS_GCC) +=3D -malign-data=3Dabi > $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) > $(call cc-option-add,CFLAGS,CC,-Wnested-externs) > $(call as-option-add,CFLAGS,CC,".equ \"x\"$(comma)1",-DHAVE_AS_QUOTED_S= YM) > + > +# Binutils >=3D 2.31, Clang >=3D 7 > $(call as-option-add,CFLAGS,CC,"movdiri %rax$(comma)(%rax)",-DHAVE_AS_M= OVDIR) > + > +# Binutils >=3D 2.33, Clang >=3D 9 > $(call as-option-add,CFLAGS,CC,"enqcmd (%rax)$(comma)%rax",-DHAVE_AS_EN= QCMD) > > # Check to see whether the assembler supports the .nop directive. > diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/= asm/asm-defns.h > index 239dc3af096c..dc9b3ce272fd 100644 > --- a/xen/arch/x86/include/asm/asm-defns.h > +++ b/xen/arch/x86/include/asm/asm-defns.h > @@ -1,5 +1,6 @@ > #include > > +/* binutils >=3D 2.26 or Clang >=3D 3.8 */ > .macro clzero > .byte 0x0f, 0x01, 0xfc > .endm > diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/ms= r.h > index 941a7612f4ba..1377d156f4e1 100644 > --- a/xen/arch/x86/include/asm/msr.h > +++ b/xen/arch/x86/include/asm/msr.h > @@ -63,6 +63,8 @@ static inline void wrmsrns(uint32_t msr, uint64_t val) > /* > * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redunda= nt CS > * prefix to avoid a trailing NOP. > + * > + * Binutils >=3D 2.40, Clang >=3D 16 > */ > alternative_input(".byte 0x2e; wrmsr", > ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS, > diff --git a/xen/arch/x86/include/asm/prot-key.h b/xen/arch/x86/include/a= sm/prot-key.h > index 8fb15b5c32e9..e8550e0c9203 100644 > --- a/xen/arch/x86/include/asm/prot-key.h > +++ b/xen/arch/x86/include/asm/prot-key.h > @@ -19,7 +19,7 @@ static inline uint32_t rdpkru(void) > { > uint32_t pkru; > > - asm volatile ( ".byte 0x0f,0x01,0xee" > + asm volatile ( ".byte 0x0f,0x01,0xee" /* binutils >=3D 2.26 or Clang= >=3D 3.8 */ > : "=3Da" (pkru) : "c" (0) : "dx" ); > > return pkru; > @@ -27,7 +27,7 @@ static inline uint32_t rdpkru(void) > > static inline void wrpkru(uint32_t pkru) > { > - asm volatile ( ".byte 0x0f,0x01,0xef" > + asm volatile ( ".byte 0x0f,0x01,0xef" /* binutils >=3D 2.26 or Clang= >=3D 3.8 */ > :: "a" (pkru), "d" (0), "c" (0) ); > } > > diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm= /xstate.h > index c96d75e38b25..0519379edb57 100644 > --- a/xen/arch/x86/include/asm/xstate.h > +++ b/xen/arch/x86/include/asm/xstate.h > @@ -118,8 +118,7 @@ static inline uint64_t xgetbv(unsigned int index) > uint32_t lo, hi; > > ASSERT(index); /* get_xcr0() should be used instead. */ > - asm volatile ( ".byte 0x0f,0x01,0xd0" /* xgetbv */ > - : "=3Da" (lo), "=3Dd" (hi) : "c" (index) ); > + asm volatile ( "xgetbv" : "=3Da" (lo), "=3Dd" (hi) : "c" (index) ); > > return lo | ((uint64_t)hi << 32); > } > diff --git a/xen/arch/x86/x86_emulate/0f01.c b/xen/arch/x86/x86_emulate/0= f01.c > index 4d36c7d289a5..87d338f0c74a 100644 > --- a/xen/arch/x86/x86_emulate/0f01.c > +++ b/xen/arch/x86/x86_emulate/0f01.c > @@ -122,7 +122,7 @@ int x86emul_0f01(struct x86_emulate_state *s, > { > case vex_none: /* serialize */ > host_and_vcpu_must_have(serialize); > - asm volatile ( ".byte 0x0f, 0x01, 0xe8" ); > + asm volatile ( ".byte 0x0f, 0x01, 0xe8" ); /* Binutils >=3D = 2.34, Clang >=3D 11 */ > break; > case vex_f2: /* xsusldtrk */ > vcpu_must_have(tsxldtrk); > diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_em= ulate/x86_emulate.c > index 11d145e17723..e58735ee9590 100644 > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -4748,27 +4748,25 @@ x86_emulate( > */ > if ( vex.l ) > { > - /* vpxor %xmmN, %xmmN, %xmmN */ > - asm volatile ( ".byte 0xc5,0xf9,0xef,0xc0" ); > - asm volatile ( ".byte 0xc5,0xf1,0xef,0xc9" ); > - asm volatile ( ".byte 0xc5,0xe9,0xef,0xd2" ); > - asm volatile ( ".byte 0xc5,0xe1,0xef,0xdb" ); > - asm volatile ( ".byte 0xc5,0xd9,0xef,0xe4" ); > - asm volatile ( ".byte 0xc5,0xd1,0xef,0xed" ); > - asm volatile ( ".byte 0xc5,0xc9,0xef,0xf6" ); > - asm volatile ( ".byte 0xc5,0xc1,0xef,0xff" ); > + asm volatile ( "vpxor %xmm0, %xmm0, %xmm0" ); > + asm volatile ( "vpxor %xmm1, %xmm1, %xmm1" ); > + asm volatile ( "vpxor %xmm2, %xmm2, %xmm2" ); > + asm volatile ( "vpxor %xmm3, %xmm3, %xmm3" ); > + asm volatile ( "vpxor %xmm4, %xmm4, %xmm4" ); > + asm volatile ( "vpxor %xmm5, %xmm5, %xmm5" ); > + asm volatile ( "vpxor %xmm6, %xmm6, %xmm6" ); > + asm volatile ( "vpxor %xmm7, %xmm7, %xmm7" ); > } > else > { > - /* vpor %xmmN, %xmmN, %xmmN */ > - asm volatile ( ".byte 0xc5,0xf9,0xeb,0xc0" ); > - asm volatile ( ".byte 0xc5,0xf1,0xeb,0xc9" ); > - asm volatile ( ".byte 0xc5,0xe9,0xeb,0xd2" ); > - asm volatile ( ".byte 0xc5,0xe1,0xeb,0xdb" ); > - asm volatile ( ".byte 0xc5,0xd9,0xeb,0xe4" ); > - asm volatile ( ".byte 0xc5,0xd1,0xeb,0xed" ); > - asm volatile ( ".byte 0xc5,0xc9,0xeb,0xf6" ); > - asm volatile ( ".byte 0xc5,0xc1,0xeb,0xff" ); > + asm volatile ( "vpor %xmm0, %xmm0, %xmm0" ); > + asm volatile ( "vpor %xmm1, %xmm1, %xmm1" ); > + asm volatile ( "vpor %xmm2, %xmm2, %xmm2" ); > + asm volatile ( "vpor %xmm3, %xmm3, %xmm3" ); > + asm volatile ( "vpor %xmm4, %xmm4, %xmm4" ); > + asm volatile ( "vpor %xmm5, %xmm5, %xmm5" ); > + asm volatile ( "vpor %xmm6, %xmm6, %xmm6" ); > + asm volatile ( "vpor %xmm7, %xmm7, %xmm7" ); > } > > ASSERT(!state->simd_size); Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:24:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:24:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277241.1562468 (Exim 4.92) (envelope-from ) id 1wAoQa-0005pf-C2; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IIK1ax/KOApDZ7SyrqdNjhr01Xqa31m0UVgSkm/2C8a6deKEc9oNrifPIgrZmB3ctoSUjsM3Ih6siL2V3wD6p1f6pBK6sVy4M/39ihJTAuxHhLJfG3gclpkVWgPKlXFbM1DDuSXtc9J3K08eiMmV0sfRnyiTO0HdUkyhOGJBPfmM8dXa6dRUGUZF9HdTwYvw0AN2dnxwQatuuexE9bgU9fALnPRkt0OQ+AzaoCbF+zWF5fDxCFZ5q6oqiV7CLKk6XyflKNWo5ghoyvTymnUl9GFPoe7blf8uAh9HBUw2qATNb6otV7Msl5zE3qTBW8EfFZ1gk/1USgCx2lkJTRIUcXvmCF18QAN7U10WxnOY8CZaMXowgkU84VqxXcI+Kyic78Ub+1+HGzr/J7gu5ht02qdh7Qh1c16rGKSfoS+P62/UPMNmJPt0TGRp2rVjMrKA X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 12:24:02.6593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b44f09b2-517a-4862-889c-08de9632e29b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B8F.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB10090 X-purgate-ID: tlsNG-d62444/1775737445-B7AFD185-D659E387/0/0 X-purgate-type: clean X-purgate-size: 676 Hi Michal, > On 9 Apr 2026, at 12:39, Michal Orzel wrote: >=20 > The check uses >=3D to compare the total number of colors against > max_num_colors (which is ARRAY_SIZE of the colors array). This > incorrectly rejects input that would exactly fill the array. >=20 > For example, with NR_LLC_COLORS=3D16, specifying 1 color for Xen and 15 > for dom0 would fail. >=20 > Change >=3D to > so that exactly filling the array is permitted. >=20 > Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") > Signed-off-by: Michal Orzel > --- Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:45:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:45:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277263.1562477 (Exim 4.92) (envelope-from ) id 1wAokd-00012I-2A; Thu, 09 Apr 2026 12:44:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277263.1562477; Thu, 09 Apr 2026 12:44:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAokc-00012B-VC; Thu, 09 Apr 2026 12:44:50 +0000 Received: by outflank-mailman (input) for mailman id 1277263; Thu, 09 Apr 2026 12:44:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAokb-000125-GX for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 12:44:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAoka-008ls8-Sg for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 14:44:48 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d79f3b-bab6-0a2a0a5309dd-0a2a450cdd42-8 for ; Thu, 09 Apr 2026 14:44:48 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d79f40-f40c-0a2a450c0019-d1558035b10a-3 for ; Thu, 09 Apr 2026 14:44:48 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4888375f735so8437905e9.3 for ; Thu, 09 Apr 2026 05:44:48 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5d3472ff-77ff-466d-9461-3b33ef0815aa@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775738688-83D43A3D-5353A34B/0/0 X-purgate-type: clean X-purgate-size: 1353 On 09.04.2026 13:22, Andrew Cooper wrote: > On 09/04/2026 9:13 am, Jan Beulich wrote: >> On 08.04.2026 18:58, Andrew Cooper wrote: >>>   It would be an rdssp;push on >>> one side, and a pop into any register on the other side.  Furthermore, >>> given that the ssp= doesn't exclude storing it for some user frames, >>> just store it for all.  It's one push/pop into a hot cacheline, and >>> makes a substantial reduction in complexity. >> I'm having significant reservations against that. I use the 0 put there >> in subsequent patches, to identify absence of that data being available. > > Well, that's not safe then. > > You've already got non-zero values there on entry-from-PV because > there's no CPL check gating RDSPP the common IDT paths. In that case we get safe values (as read from the MSR during the privilege level switch). And wait - no, the latter two patches don't make any such assumptions, I don't think. I may have mis-remembered, or I may have remembered how things were at a very early stage. So really the concern is with RDSSPQ's resource use. This could in principle be as cheap as MOV, but how do I know? (The latency/throughput data I can find doesn't include this insn.) Plus for the purely PV entrypoints I don't see why we would want/need the slightly larger code size that would result. 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Thu, 09 Apr 2026 05:49:01 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 14:48:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() To: Luca Fancellu Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Anthony PERARD , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Michal Orzel References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-3-michal.orzel@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775738942-1195141E-ACA91884/0/0 X-purgate-type: clean X-purgate-size: 1038 On 09.04.2026 14:22, Luca Fancellu wrote: >> On 9 Apr 2026, at 12:39, Michal Orzel wrote: >> >> The check uses >= to compare the total number of colors against >> max_num_colors (which is ARRAY_SIZE of the colors array). This >> incorrectly rejects input that would exactly fill the array. >> >> For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 >> for dom0 would fail. >> >> Change >= to > so that exactly filling the array is permitted. >> >> Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") >> Signed-off-by: Michal Orzel >> --- > > Reviewed-by: Luca Fancellu Did you see Andrew's reply? If that earlier (recent) commit was wrong, I think a 2nd Fixes: tag may be needed here. For now I can't help the impression though that there might have been a re-basing mistake, where that re-base may have wanted to result in this patch dissolving into nothing. Yet of course I'm all ears to learn otherwise. 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pr=C Message-ID: <43995524-5c3e-444c-80a1-849e3e1d9430@amd.com> Date: Thu, 9 Apr 2026 14:53:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() To: Andrew Cooper , CC: Anthony PERARD , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-3-michal.orzel@amd.com> <2ae13059-e0ba-4cf7-bda0-9a21cd428509@citrix.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <2ae13059-e0ba-4cf7-bda0-9a21cd428509@citrix.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB50:EE_|LV3PR12MB9268:EE_ X-MS-Office365-Filtering-Correlation-Id: df2c70e7-85d4-4146-b256-08de9637019a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700016|13003099007|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JLpEPDp0ACAnB6eoeZGoPIloeJjEhvfP4cj1aYGfE6qWRCazgctirOqat1TKi8sTMEacwV1PnRTb5icwbujWgOzI0L/3gAl3sRjdKNeyT5pMTygw86UitcQIe2kC8dw5y6T69TPiFGzctZMdN6L5TpA2CaajW+aTbnyWGfvuPrGur7iozQcvjK0RJYeotUBcySlMWN26vDndSpMh9br3IAWt0KT7MMMdCElOIRxkAprJxy3PDE1pr3NJXr2kqmCgykfqNJVJ8zIikMmwd7v4huwYZOUhzzMPYdTt3DvEzzZgYtVNZNRhrVqtEelXMscYaM4/UIfxapGUODUUEWgemUUnY6bIlKfvjYiu5Qr84O2cfE9k5BBkzAN5qR5c3h0xI3WUzQ2W28USxC8BrmKSD7qCx8i2Sax4xwFoCHdWhRbj3uZf9JU5l/MgBCJs8jUc X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 12:53:32.7026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df2c70e7-85d4-4146-b256-08de9637019a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9268 X-purgate-ID: tlsNG-33051d/1775739223-CA520C9A-E5E3A19F/0/0 X-purgate-type: clean X-purgate-size: 1921 On 09/04/2026 13:47, Andrew Cooper wrote: > On 09/04/2026 12:39 pm, Michal Orzel wrote: >> The check uses >= to compare the total number of colors against >> max_num_colors (which is ARRAY_SIZE of the colors array). This >> incorrectly rejects input that would exactly fill the array. >> >> For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 >> for dom0 would fail. >> >> Change >= to > so that exactly filling the array is permitted. >> >> Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") >> Signed-off-by: Michal Orzel >> --- >> xen/common/llc-coloring.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c >> index eb7c72b24023..30c1594dac9f 100644 >> --- a/xen/common/llc-coloring.c >> +++ b/xen/common/llc-coloring.c >> @@ -78,7 +78,7 @@ static int __init parse_color_config(const char *buf, unsigned int colors[], >> >> if ( end >= NR_LLC_COLORS || start > end || >> (end - start) >= (UINT_MAX - *num_colors) || >> - (*num_colors + (end - start + 1)) >= max_num_colors ) >> + (*num_colors + (end - start + 1)) > max_num_colors ) >> return -EINVAL; >> >> /* Colors are range checked in check_colors() */ > > This boundary was changed by > https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=cba8a584de171c8c4510709c2edc9f1cf86b21ab > because it was off-by-one. > > Are you saying that the analysis in that patch was wrong? I examined the scenario that is a default for dom0 i.e. dom0 gets all the colors by default. This is equivalent to setting dom0-llc-colors=0-15. If I set this, I will get a message: (XEN) parameter "dom0-llc-colors" has invalid value "0-15", rc=-22! I admit that I added wrong example in commit msg. ~Michal > > ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 09 12:53:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 12:53:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277285.1562503 (Exim 4.92) (envelope-from ) id 1wAotN-0003eZ-7y; Thu, 09 Apr 2026 12:53:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277285.1562503; Thu, 09 Apr 2026 12:53:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAotN-0003eS-57; Thu, 09 Apr 2026 12:53:53 +0000 Received: by outflank-mailman (input) for mailman id 1277285; Thu, 09 Apr 2026 12:53:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAotK-0003dV-PV for xen-devel@lists.xenproject.org; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <95fc62d9-cfd4-4b75-a9b0-7e90c9ba1095@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775739534-41311C9A-458187A4/0/0 X-purgate-type: clean X-purgate-size: 3741 On 09.04.2026 13:26, Oleksii Kurochko wrote: > On 3/24/26 10:37 AM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> --- /dev/null >>> +++ b/xen/arch/riscv/domain-build.c >>> @@ -0,0 +1,46 @@ >>> +/* SPDX-License-Identifier: GPL-2.0-or-later */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> +#include >>> + >>> +int __init construct_domain(struct domain *d, struct kernel_info *kinfo) >> >> Are you actually altering what kinfo points to? > > Not directly in this function, but it could be altered, for example, by > kernel_image_load() where "info->entry = load_addr" is happening. Ah, I see. >>> +{ >>> + struct vcpu *v = d->vcpu[0]; >>> + struct cpu_user_regs *regs = vcpu_guest_cpu_user_regs(v); >>> + >>> + BUG_ON(d->vcpu[0] == NULL); >> >> Why not simply "!v"? > > It could work. I'll apply that. > >> >> Also, while in the cover letter you state a dependency on another series, >> this is somewhat unwieldy here. From the titles there I can't deduce which >> of the patches would introduce vcpu_guest_cpu_user_regs(). Yet I would >> have wanted to double check that it doesn't de-reference v already. > > It was already merged. It was part of: > xen/riscv: implement vcpu_csr_init() "02b3a1b0e53c" Oh, indeed. Which makes clear that the BUG_ON() comes too late. >>> + BUG_ON(v->is_initialised); >>> + >>> + kernel_load(kinfo); >>> + initrd_load(kinfo, copy_to_guest_phys); >>> + dtb_load(kinfo, copy_to_guest_phys); >> >> These all return void, despite this also being used for non-Dom0. Is it >> really fatal to a dom0less system if one out of many domains fail to be >> built? > > For a dom0less system, my opinion is that it should not be fatal, it > should simply ignore a domain that fails to build and continue with the > rest. However, with the current common dom0less code it will just > panic(). This is a behavior I would like to change and it is on my TODO > list. > > Regarding the functions returning void, this is because all of them > currently call panic() on failure, which I expect will need to change in > order to ignore a domain that fails to build in dom0less mode. > > For the current implementation of the common dom0less code this is fine, > but I agree it should be addressed in a separate patch series. > > Especially when, despite the name, there is a Dom0? > > For this case, a failure there should indeed be fatal, so panic() is > appropriate. I think you misunderstood. I wasn't referring to the building of Dom0 failing. Was rather emphasizing that when there is a Dom0, failure to create a DomU likely should even less so be fatal, as Dom0 could later rectify the situation. >>> + regs->sepc = kinfo->entry; >>> + >>> + /* Guest boot cpuid = 0 */ >>> + regs->a0 = 0; >>> + regs->a1 = kinfo->dtb_paddr; >>> + >>> + for ( unsigned int i = 1; i < d->max_vcpus; i++ ) >>> + { >>> + if ( vcpu_create(d, i) == NULL ) >>> + { >>> + printk("Failed to allocate %pd v%d\n", d, i); >>> + break; >> >> And no error is indicated to the caller? > > No, as generally it is enough to have only one vCPU0 to run domain, so > we have to print that something went wrong with allocation of vCPU1...n > but it is okay to me to continue domain construction. Hmm, now that I look there, sched_setup_dom0_vcpus() ignores errors and doesn't even emit a log message. Question is why neither Arm nor RISC-V use that function, when we have it. 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This armed all three hardware interrupt lines (TX FIFO empty, >> RX data ready, receive error) with no handler registered to service >> them. On platforms where the GIC receives these asserted lines, the >> result is either repeated spurious-interrupt warnings or an unhandled >> interrupt fault. >> >> The fix adds an early return inside the error branch. The >> interrupt-enable write to SCSCR is skipped entirely when no handler is >> registered. >> >> SCIF TX continues to operate correctly after this change. The Xen >> serial framework never calls serial_async_transmit() for SCIF, so >> port->txbuf is always NULL. This causes __serial_putc() to take the >> synchronous finite-capacity path, which polls the SCFSR_TDFE hardware >> flag directly and does not depend on the interrupt mechanism. > NIT: It would be nice to at least mention that there will be no serial RX > without interrupts. > >> As a secondary clean-up, the hardware error-flag clearing sequence is >> moved to before the setup_irq() call so that error bits accumulated >> since init_preirq() are cleared unconditionally, regardless of whether >> IRQ registration succeeds. >> >> Signed-off-by: Oleksii Moisieiev > That's a good catch. I can see most of our drivers already use that. > Reviewed-by: Michal Orzel > > That said, I can see that we have exactly the same issue for pl011, cadence and > exynos. I can either take your patch as is (no more work for you) and submit the > patch fixing remaining drivers or you can send a v2 fixing all at once. It's up > to you. > > ~Michal > >> --- >> >> xen/drivers/char/scif-uart.c | 16 ++++++++++++---- >> 1 file changed, 12 insertions(+), 4 deletions(-) >> >> diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c >> index 888821a3b8..673a2d3800 100644 >> --- a/xen/drivers/char/scif-uart.c >> +++ b/xen/drivers/char/scif-uart.c >> @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct serial_port *port) >> uart->irqaction.name = "scif_uart"; >> uart->irqaction.dev_id = port; >> >> - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) >> - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", >> - uart->irq); >> - >> /* Clear all errors */ >> if ( scif_readw(uart, params->status_reg) & params->error_mask ) >> scif_writew(uart, params->status_reg, ~params->error_mask); >> if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) >> scif_writew(uart, params->overrun_reg, ~params->overrun_mask); >> >> + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) >> + { >> + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", >> + uart->irq); >> + /* >> + * If the IRQ handler could not be installed (setup_irq failed), >> + * do not enable TX/RX or error interrupts. Serial transmit will >> + * fall back to polling mode. >> + */ >> + return; >> + } >> + >> /* Enable TX/RX and Error Interrupts */ >> scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | >> params->irq_flags); From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:35:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:35:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277358.1562580 (Exim 4.92) (envelope-from ) id 1wApXX-0003l0-H8; Thu, 09 Apr 2026 13:35:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277358.1562580; Thu, 09 Apr 2026 13:35:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApXX-0003ks-E9; Thu, 09 Apr 2026 13:35:23 +0000 Received: by outflank-mailman (input) for mailman id 1277358; Thu, 09 Apr 2026 13:35:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApXW-0003kb-Oo for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uQXojR9KvrLnfYL4saifDFMj4rlf0KRLtGzwaSGuPVS8za6t5UUa25Qqo/OaaiV3UTTxY33EUjHObD78vI9tKGnEf6lOry7f5Gc2YEypeCsIVGp4DMro8kgOdieK/4Uv6oaqtpJtw4AxFoQkDCM7S3ILB4bHVEd6cQCTBrCvCTmUBTjlfC+AbB5W1Yp4b2bJZNFS+Th40kU/HBmqf+beOL/scm8lkEP4MabdkBKBJJ0zr+HxrYzu4F6r/8dvdwa4muVPTCN/HGofnL/XgOoTUGqeDjiNXrJiLN+face0vBol7awzC6eq90hBK5cIBfHpOXIt0Z7/En/EagwSH2PqgqjqsRRHPo7/lrIS/Gf4MKrg0EuV5WDuuek8Iweb8R5wBEvtNcHabMuc+OhK20Fn0DcqzP8t50lSsWCycfTDkHbSRVBkgTVTAxF2hLp+StAS X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 13:35:18.6228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34ed53d0-6ac2-4e92-1e6e-08de963cd749 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E8.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6714 X-purgate-ID: tlsNG-c201ff/1775741722-23D2F96F-72181A4F/0/0 X-purgate-type: clean X-purgate-size: 996 Hi Michal, > On 9 Apr 2026, at 12:39, Michal Orzel wrote: >=20 > iomem_deny_access() wraps rangeset_remove_range() which takes inclusive > endpoints. All call sites in the GIC and ACPI code pass 'mfn + nr' (or > 'mfn + 1' for single-page regions) as the end parameter, which causes > one extra page beyond each region to be denied. >=20 > For single-page regions, use 'mfn' as the end (denying exactly one page). > For all multi-page regions, use 'mfn + nr - 1'. >=20 > This matches the correct pattern used elsewhere, e.g. in device.c. >=20 > Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GI= C regions") > Fixes: 66158be465 ("ARM: ITS: Deny hardware domain access to ITS") > Fixes: 97e9875646 ("arm/acpi: Permit MMIO access of Xen unused devices fo= r Dom0") > Signed-off-by: Michal Orzel > --- >=20 This looks ok to me. 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I'll apply that. >> >>> Also, while in the cover letter you state a dependency on another series, >>> this is somewhat unwieldy here. From the titles there I can't deduce which >>> of the patches would introduce vcpu_guest_cpu_user_regs(). Yet I would >>> have wanted to double check that it doesn't de-reference v already. >> It was already merged. It was part of: >> xen/riscv: implement vcpu_csr_init() "02b3a1b0e53c" > Oh, indeed. Which makes clear that the BUG_ON() comes too late. It makes this BUG_ON() unnessary at all if d->vcpu[0] wasn't created then construct_domain() won't be called for such domain. I will just drop this BUG_ON(). > >>>> + BUG_ON(v->is_initialised); >>>> + >>>> + kernel_load(kinfo); >>>> + initrd_load(kinfo, copy_to_guest_phys); >>>> + dtb_load(kinfo, copy_to_guest_phys); >>> These all return void, despite this also being used for non-Dom0. Is it >>> really fatal to a dom0less system if one out of many domains fail to be >>> built? >> For a dom0less system, my opinion is that it should not be fatal, it >> should simply ignore a domain that fails to build and continue with the >> rest. However, with the current common dom0less code it will just >> panic(). This is a behavior I would like to change and it is on my TODO >> list. >> >> Regarding the functions returning void, this is because all of them >> currently call panic() on failure, which I expect will need to change in >> order to ignore a domain that fails to build in dom0less mode. >> >> For the current implementation of the common dom0less code this is fine, >> but I agree it should be addressed in a separate patch series. >> >> Especially when, despite the name, there is a Dom0? >> >> For this case, a failure there should indeed be fatal, so panic() is >> appropriate. > I think you misunderstood. I wasn't referring to the building of Dom0 > failing. Was rather emphasizing that when there is a Dom0, failure to > create a DomU likely should even less so be fatal, as Dom0 could later > rectify the situation. Oh, okay, then it is really less fatal if DomU creation will fail in the case of Dom0. > >>>> + regs->sepc = kinfo->entry; >>>> + >>>> + /* Guest boot cpuid = 0 */ >>>> + regs->a0 = 0; >>>> + regs->a1 = kinfo->dtb_paddr; >>>> + >>>> + for ( unsigned int i = 1; i < d->max_vcpus; i++ ) >>>> + { >>>> + if ( vcpu_create(d, i) == NULL ) >>>> + { >>>> + printk("Failed to allocate %pd v%d\n", d, i); >>>> + break; >>> And no error is indicated to the caller? >> No, as generally it is enough to have only one vCPU0 to run domain, so >> we have to print that something went wrong with allocation of vCPU1...n >> but it is okay to me to continue domain construction. > Hmm, now that I look there, sched_setup_dom0_vcpus() ignores errors > and doesn't even emit a log message. Question is why neither Arm nor > RISC-V use that function, when we have it. I haven't seen this function, I will re-use it and in separate patch suggest to re-use it for Arm. One thing I think we want to do then is to drop #ifdef x86 around sched_setup_dom0_vcpus() and rename it to sched_setup_dom_vcpus(). And maybe add dprintk()'s to provide some information about which vCPUs were created and which not. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:41:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:41:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277392.1562599 (Exim 4.92) (envelope-from ) id 1wApdK-0006Wi-Bx; Thu, 09 Apr 2026 13:41:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277392.1562599; Thu, 09 Apr 2026 13:41:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApdK-0006Wb-8y; Thu, 09 Apr 2026 13:41:22 +0000 Received: by outflank-mailman (input) for mailman id 1277392; Thu, 09 Apr 2026 13:41:21 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApdI-0006WV-RJ for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 588abf02-8138-40f9-2dc5-08de963ef465 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 13:50:26.5565 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iYjlsjc5YKfVLkPX7juPbDHSlOjkQg2VEhGt9luVc/PKjLxmUVkFcWHyQPb2mcXOSGAfQzEAzknYtx8brKrAvfMxLGuLgw4k97D/wGSSvb4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6132 X-purgate-ID: tlsNG-c1860d/1775742629-74360497-90379B8F/0/0 X-purgate-type: clean X-purgate-size: 2372 In pl011_init_postirq(), two code paths could reach the interrupt-unmask write to IMSC without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IMSC write, unmasking RTI|OEI|BEI|PEI|FEI|TXI|RXI with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IMSC write, arming all hardware interrupt lines with no handler to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure pl011_init_postirq() to use early returns: return immediately when no valid IRQ is provided, and return after logging the error when setup_irq() fails. The interrupt-enable write to IMSC is only reached when IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev --- xen/drivers/char/pl011.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 5f9913367d..918b9d4d4a 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -150,13 +150,18 @@ static void __init pl011_init_postirq(struct serial_p= ort *port) struct pl011 *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq <=3D 0 ) + return; + + uart->irqaction.handler =3D pl011_interrupt; + uart->irqaction.name =3D "pl011"; + uart->irqaction.dev_id =3D port; + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) { - uart->irqaction.handler =3D pl011_interrupt; - uart->irqaction.name =3D "pl011"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); + printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); + /* Do not unmask interrupts if irq handler wasn't set */ + return; } =20 /* Clear pending error interrupts */ --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:50:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:50:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277412.1562609 (Exim 4.92) (envelope-from ) id 1wApmB-00007u-Ag; Thu, 09 Apr 2026 13:50:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277412.1562609; Thu, 09 Apr 2026 13:50:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApmB-00007n-71; Thu, 09 Apr 2026 13:50:31 +0000 Received: by outflank-mailman (input) for mailman id 1277412; Thu, 09 Apr 2026 13:50:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApm9-00007H-4D for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1320194d-9c28-4a15-f0a0-08de963ef3ec X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 13:50:25.7291 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wxnsbkeTOQx/EYtQps4Dm+hVYoYGH9YegnkyaAZG9R2YRyq6xOadhUwDNchrzA5Nlq00z1VgLo1Xyvz4xwxHDn5IZ9NJLXeJSS7ihYV3ge4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6132 X-purgate-ID: tlsNG-c1860d/1775742628-7674E497-1D6CA441/0/0 X-purgate-type: clean X-purgate-size: 1796 This series fixes a common bug pattern found in several Xen UART drivers: when setup_irq() fails during post-IRQ initialization, drivers log the error but continue executing and unconditionally unmask hardware interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Patch 1, originally submitted as a standalone fix in v1, addresses the issue in the SCIF driver and moves the hardware error-flag clearing sequence to before the setup_irq() call so that stale error bits are cleared unconditionally. Patches 2-4 apply the same early-return fix to the pl011, cadence-uart, and exynos4210-uart drivers. The pl011 and cadence-uart drivers additionally had a positive-condition IRQ guard (if uart->irq > 0) that could fall through to the interrupt unmask even when no valid IRQ was provided. Both are restructured to use the early-return idiom. Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description Oleksii Moisieiev (4): xen/drivers/char: fix SCIF IRQ registration failure propagation xen/drivers/char/pl011: fix IRQ registration failure propagation xen/drivers/char/cadence-uart: fix IRQ registration failure propagation xen/drivers/char: fix exynos4210 IRQ registration failure propagation xen/drivers/char/cadence-uart.c | 17 +++++++++++------ xen/drivers/char/exynos4210-uart.c | 4 ++++ xen/drivers/char/pl011.c | 17 +++++++++++------ xen/drivers/char/scif-uart.c | 16 ++++++++++++---- 4 files changed, 38 insertions(+), 16 deletions(-) --=20 2.43.0 base-commit: 2ca756d39f59f834160263fd142ef91c6ca3dd90 branch: amoi_dfmea_scif= From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:50:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:50:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277415.1562625 (Exim 4.92) (envelope-from ) id 1wApmC-0000Pz-62; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f551e331-802a-4b8e-4425-08de963ef4a9 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 13:50:26.9497 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: uwtj2AKzoHIeHY2WJbd197sf1xEFRTqCvUTeRI4LBag/9Ab//IKD6raq3Y9D9+7OU6fJFbVvQWNbxP+C6+CXAGOYIxCcCwuCyuKxfjVkw0o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6132 X-purgate-ID: tlsNG-c1860d/1775742629-F674E497-EB7A424C/0/0 X-purgate-type: clean X-purgate-size: 2266 In cuart_init_postirq(), two code paths could reach the interrupt-enable write to IER without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IER write, enabling the receive data interrupt with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IER write, arming the receive hardware interrupt line with no handler to service it. On platforms where the GIC receives this asserted line, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure cuart_init_postirq() to use early returns in both error paths. Signed-off-by: Oleksii Moisieiev --- xen/drivers/char/cadence-uart.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uar= t.c index b2f379833f..a63dc4adb2 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -72,13 +72,18 @@ static void __init cuart_init_postirq(struct serial_por= t *port) struct cuart *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq <=3D 0 ) + return; + + uart->irqaction.handler =3D cuart_interrupt; + uart->irqaction.name =3D "cadence-uart"; + uart->irqaction.dev_id =3D port; + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) { - uart->irqaction.handler =3D cuart_interrupt; - uart->irqaction.name =3D "cadence-uart"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart= ->irq); + printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->ir= q); + /* Do not unmask interrupts if irq handler wasn't set */ + return; } =20 /* Clear pending error interrupts */ --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:50:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:50:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277416.1562634 (Exim 4.92) (envelope-from ) id 1wApmC-0000b0-Jo; Thu, 09 Apr 2026 13:50:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277416.1562634; Thu, 09 Apr 2026 13:50:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApmC-0000Zo-FZ; Thu, 09 Apr 2026 13:50:32 +0000 Received: by outflank-mailman (input) for mailman id 1277416; Thu, 09 Apr 2026 13:50:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApmA-00007h-Lj for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f7fe5ff6-5a33-4375-4c6e-08de963ef4dc X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 13:50:27.3167 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NTdgNFySvviM6r2x80ywyNq7qBgyjqw2w+GXnnJHc7oo7wEbv0O7pzRMtVI4eFgNxDUQNYxW5XOC0Vp9UFFZn+v+yeSyXRc2swI0CIENuwY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6132 X-purgate-ID: tlsNG-c1860d/1775742629-75358497-AF44ED15/0/0 X-purgate-type: clean X-purgate-size: 1472 In exynos4210_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled receive and transmit interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Add an early return in the setup_irq() error branch so that the interrupt-enable writes to UINTM and UMCON are skipped when IRQ registration fails. Signed-off-by: Oleksii Moisieiev --- xen/drivers/char/exynos4210-uart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos42= 10-uart.c index 58901df554..2e5860ea2b 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -199,8 +199,12 @@ static void __init exynos4210_uart_init_postirq(struct= serial_port *port) uart->irqaction.dev_id =3D port; =20 if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %d\n"= , uart->irq); + /* Don't enable interrupts if irq setup was failed */ + return; + } =20 /* Unmask interrupts */ exynos4210_write(uart, UINTM, ~UINTM_ALLI); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 13:50:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 13:50:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277413.1562614 (Exim 4.92) (envelope-from ) id 1wApmB-0000BK-JP; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 16f0f59e-698a-48f6-cabc-08de963ef43c X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 13:50:26.1973 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: BpFa/9/axK9PnGrP+eIBjYjHjpp0Nd41/OfIGhufHZxZHCn+BEpCUY1W2XulPRRuXua+AZ09irkjz9LMC2/E7pKi3J6bV0BMVLFxrfBeOG8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR03MB6132 X-purgate-ID: tlsNG-c1860d/1775742628-7455F497-4396C1B6/0/0 X-purgate-type: clean X-purgate-size: 3017 In scif_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally writing TIE|RIE|REIE into the Serial Control Register (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, RX data ready, receive error) with no handler registered to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. The fix adds an early return inside the error branch. The interrupt-enable write to SCSCR is skipped entirely when no handler is registered. SCIF TX continues to operate correctly after this change. The Xen serial framework never calls serial_async_transmit() for SCIF, so port->txbuf is always NULL. This causes __serial_putc() to take the synchronous finite-capacity path, which polls the SCFSR_TDFE hardware flag directly and does not depend on the interrupt mechanism. RX wouldn't work if irq wasn't registered. As a secondary clean-up, the hardware error-flag clearing sequence is moved to before the setup_irq() call so that error bits accumulated since init_preirq() are cleared unconditionally, regardless of whether IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev --- Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description xen/drivers/char/scif-uart.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 888821a3b8..673a2d3800 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct seri= al_port *port) uart->irqaction.name =3D "scif_uart"; uart->irqaction.dev_id =3D port; =20 - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", - uart->irq); - /* Clear all errors */ if ( scif_readw(uart, params->status_reg) & params->error_mask ) scif_writew(uart, params->status_reg, ~params->error_mask); if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", + uart->irq); + /* + * If the IRQ handler could not be installed (setup_irq failed), + * do not enable TX/RX or error interrupts. Serial transmit will + * fall back to polling mode. + */ + return; + } + /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | params->irq_flags); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:01:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:01:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277477.1562693 (Exim 4.92) (envelope-from ) id 1wApwy-00055U-2k; Thu, 09 Apr 2026 14:01:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277477.1562693; Thu, 09 Apr 2026 14:01:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApwx-00052q-Su; Thu, 09 Apr 2026 14:01:39 +0000 Received: by outflank-mailman (input) for mailman id 1277477; Thu, 09 Apr 2026 14:01:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApwv-0004Ke-Ig for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e19cb274-e032-43e2-2710-08de964082e5 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 14:01:35.0400 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gVSbm8SQc4MsAT7Akf1xfX/sc/mTAAq+Rm/MnSEU5LnpMTfFzp3Qmnrmjc99Gfg8MyICw16nF87N+greGIDr+w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1PR03MB10891 X-purgate-ID: tlsNG-16d1c6/1775743296-64E4E3D8-0D41CD8F/0/0 X-purgate-type: clean X-purgate-size: 518 Signed-off-by: Mykyta Poturai --- v1->v2: * new patch --- SUPPORT.md | 2 -- 1 file changed, 2 deletions(-) diff --git a/SUPPORT.md b/SUPPORT.md index 8e7ab7cb3e..f4f1458bbb 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -170,8 +170,6 @@ unexpected behavior or issues on some hardware. =20 At least the following features are missing on a PVH dom0: =20 - * PCI SR-IOV. - * Native NMI forwarding (nmi=3Ddom0 command line option). =20 * MCE handling. --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:01:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:01:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277478.1562707 (Exim 4.92) (envelope-from ) id 1wApwz-0005VU-5V; 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Signed-off-by: Stewart Hildebrand Signed-off-by: Mykyta Poturai Reviewed-by: Teddy Astie --- v2->v3: * move declarations to private.h v1->v2: * collect RBs --- xen/drivers/vpci/header.c | 20 +++++++++++--------- xen/drivers/vpci/private.h | 6 ++++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 96995e098b..5d5ba5c016 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -611,9 +611,9 @@ static void cf_check bar_write( pci_conf_write32(pdev->sbdf, reg, val); } =20 -static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, - unsigned int reg, uint32_t val, - void *data) +void cf_check vpci_guest_mem_bar_write(const struct pci_dev *pdev, + unsigned int reg, uint32_t val, + void *data) { struct vpci_bar *bar =3D data; bool hi =3D false; @@ -653,8 +653,8 @@ static void cf_check guest_mem_bar_write(const struct p= ci_dev *pdev, bar->guest_addr =3D guest_addr; } =20 -static uint32_t cf_check guest_mem_bar_read(const struct pci_dev *pdev, - unsigned int reg, void *data) +uint32_t cf_check vpci_guest_mem_bar_read(const struct pci_dev *pdev, + unsigned int reg, void *data) { const struct vpci_bar *bar =3D data; uint32_t reg_val; @@ -826,8 +826,9 @@ int vpci_init_header(struct pci_dev *pdev) bars[i].type =3D VPCI_BAR_MEM64_HI; rc =3D vpci_add_register(pdev->vpci, is_hwdom ? vpci_hw_read32 - : guest_mem_bar_read, - is_hwdom ? bar_write : guest_mem_bar_wr= ite, + : vpci_guest_mem_bar_read, + is_hwdom ? bar_write + : vpci_guest_mem_bar_write, reg, 4, &bars[i]); if ( rc ) goto fail; @@ -885,8 +886,9 @@ int vpci_init_header(struct pci_dev *pdev) bars[i].prefetchable =3D val & PCI_BASE_ADDRESS_MEM_PREFETCH; =20 rc =3D vpci_add_register(pdev->vpci, - is_hwdom ? vpci_hw_read32 : guest_mem_bar_r= ead, - is_hwdom ? bar_write : guest_mem_bar_write, + is_hwdom ? vpci_hw_read32 + : vpci_guest_mem_bar_read, + is_hwdom ? bar_write : vpci_guest_mem_bar_w= rite, reg, 4, &bars[i]); if ( rc ) goto fail; diff --git a/xen/drivers/vpci/private.h b/xen/drivers/vpci/private.h index 6fdf8a20d9..f012fd160d 100644 --- a/xen/drivers/vpci/private.h +++ b/xen/drivers/vpci/private.h @@ -141,6 +141,12 @@ static inline size_t vmsix_table_size(const struct vpc= i *vpci, unsigned int nr) /* Map/unmap the BARs of a vPCI device. */ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_on= ly); 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b=pw1tQiWlj74LD3Dt2PH3dQ8qjSt97RfqAZezhSUGi5AbbMu+hGMSZOmFBtJ2u0Z3jiujlQzdOTPHP0gQ9gCYLU6/Ad8RHTgXorPXv7/X3/Q2jxgq4ELEEvde3IpZe2MOqVlwqYfnGTpsk+VSbEJPYvZf4LvR0jNJa519N9EodYK5CrFFbBnHz9K10L4kk6s3GOSPh+VFuKWclESfzN9PdOwUxHH9/efkyc59YdziVLLQwbh/uIumirT5mBh57w9AodwNV3llbMbm5V4i+nd3ncVoXL8W+2IJPHJz117m9EhGE8hbDf7xUD0YOhQmXrLxLEMzHIwEqzsNrGMlsulvSw== From: Mykyta Poturai To: "xen-devel@lists.xenproject.org" CC: Stewart Hildebrand , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Mykyta Poturai Subject: [PATCH v3 6/7] vpci: add SR-IOV support for DomUs Thread-Topic: [PATCH v3 6/7] vpci: add SR-IOV support for DomUs Thread-Index: AQHcyClgJVtVkM11YECyJKBoUo8yuw== Date: Thu, 9 Apr 2026 14:01:34 +0000 Message-ID: <1aaf1a087ca0003d943d43c55500b3ab84195cf5.1775742115.git.mykyta_poturai@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a5dadb01-ed72-404c-024e-08de964082b3 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 14:01:34.6597 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xc4XkSyo2nbA77++RX3g6Gfgxb1TsxTYBD5Y1tuk7/8+ygXYkkd23AxMny3v0/aJPfPhXQAzg7kbNakZQH6xeg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3PR03MB10964 X-purgate-ID: tlsNG-33051d/1775743296-C9D3CC9A-6EB0357B/0/0 X-purgate-type: clean X-purgate-size: 3434 From: Stewart Hildebrand Emulate guest BAR register values based on PF BAR values for VFs. This allows creating a guest view of the normal BAR registers and emulates the size and properties as it is done during PCI device enumeration by the guest. Expose VID/DID and class/revision to the guest. Note, that VFs ROM BAR is read-only and is all zeros, but VF may provide access to the PFs ROM via emulation and is not implemented. Signed-off-by: Stewart Hildebrand Signed-off-by: Mykyta Poturai --- v2->v3: * don't emulate VID/DID registers * replace ifdef with IS_ENABLED v1->v2: * remove VF register handlers covered by init_header * set guest addr unconditionally --- xen/drivers/vpci/sriov.c | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/xen/drivers/vpci/sriov.c b/xen/drivers/vpci/sriov.c index ec6a7b84d5..b43a2b26d3 100644 --- a/xen/drivers/vpci/sriov.c +++ b/xen/drivers/vpci/sriov.c @@ -211,6 +211,58 @@ int vpci_vf_init_header(struct pci_dev *vf_pdev) sriov_pos =3D pci_find_ext_capability(pf_pdev, PCI_EXT_CAP_ID_SRIOV); ctrl =3D pci_conf_read16(pf_pdev->sbdf, sriov_pos + PCI_SRIOV_CTRL); =20 + if ( IS_ENABLED(CONFIG_HAS_VPCI_GUEST_SUPPORT) && + pf_pdev->domain !=3D vf_pdev->domain ) + { + struct vpci_bar *bars =3D vf_pdev->vpci->header.bars; + + rc =3D vpci_add_register(vf_pdev->vpci, vpci_hw_read16, NULL, + PCI_VENDOR_ID, 2, NULL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(vf_pdev->vpci, vpci_hw_read16, NULL, + PCI_DEVICE_ID, 2, NULL); + if ( rc ) + return rc; + + /* Hardcode multi-function device bit to 0 */ + rc =3D vpci_add_register(vf_pdev->vpci, vpci_read_val, NULL, + PCI_HEADER_TYPE, 1, + (void *)PCI_HEADER_TYPE_NORMAL); + if ( rc ) + return rc; + + rc =3D vpci_add_register(vf_pdev->vpci, vpci_hw_read32, NULL, + PCI_CLASS_REVISION, 4, NULL); + if ( rc ) + return rc; + + for ( unsigned int i =3D 0; i < PCI_SRIOV_NUM_BARS; i++ ) + { + switch ( pf_pdev->vpci->sriov->vf_bars[i].type ) + { + case VPCI_BAR_MEM32: + case VPCI_BAR_MEM64_LO: + case VPCI_BAR_MEM64_HI: + rc =3D vpci_add_register(vf_pdev->vpci, vpci_guest_mem_bar= _read, + vpci_guest_mem_bar_write, + PCI_BASE_ADDRESS_0 + i * 4, 4, &bar= s[i]); + if ( rc ) + return rc; + break; + + default: + rc =3D vpci_add_register(vf_pdev->vpci, vpci_read_val, NUL= L, + PCI_BASE_ADDRESS_0 + i * 4, 4, + (void *)0); + if ( rc ) + return rc; + break; + } + } + } + if ( (pf_pdev->domain =3D=3D vf_pdev->domain) && (ctrl & PCI_SRIOV_CTR= L_MSE) ) { rc =3D vpci_modify_bars(vf_pdev, PCI_COMMAND_MEMORY, false); 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 611f577e-c472-4751-c8e5-08de964081f1 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 14:01:33.4406 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rGfq3kFHgn8zDDulq8LZ5FpblFsvcYG9XHoaSxoc62tW+8PCNJZ8uzTwLig00532d2XDOKt6hyeWPCGuHzLCOA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3PR03MB10964 X-purgate-ID: tlsNG-4011c0/1775743295-BDB550B1-0B871F89/0/0 X-purgate-type: clean X-purgate-size: 13892 From: Mykyta Poturai There is no need to store ranges for each PCI device, as they are only used during the mapping/unmapping process and can be reused for each device. This also allows to avoid the need to allocate and destroy rangesets for each device. Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() macro to free a rangeset and set the pointer to NULL. Amends: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") Signed-off-by: Mykyta Poturai Signed-off-by: Stewart Hildebrand --- v2->v3: * synced with BAR write with memory decoding enabled series[1] * add Amends tag * remove unused variable i due to rebasing over 998060dd9101 ("vPCI: move vpci_init_capabilities() to a separate file") * enclose entire struct vpci_vcpu inside #ifdef __XEN__ * s/bar_mem/mem/ * use ARRAY_SIZE * put init/destroy in functions * only allocate for domains with vPCI and idle domain * replace 'if ( !mem ) continue;' with ASSERT v1->v2 * new patch [1]: https://patchew.org/Xen/20260406191203.97662-1-stewart.hildebrand@amd.= com/ --- xen/common/domain.c | 5 +++ xen/drivers/vpci/header.c | 67 ++++++++++++++------------------------ xen/drivers/vpci/vpci.c | 34 ++++++++++++++++--- xen/include/xen/rangeset.h | 7 ++++ xen/include/xen/vpci.h | 10 ++++-- 5 files changed, 73 insertions(+), 50 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index bb9e210c28..5ef7db8f09 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -455,6 +455,8 @@ static int vcpu_teardown(struct vcpu *v) */ static void vcpu_destroy(struct vcpu *v) { + vpci_vcpu_destroy(v); + free_vcpu_struct(v); } =20 @@ -512,6 +514,9 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int= vcpu_id) if ( arch_vcpu_create(v) !=3D 0 ) goto fail_sched; =20 + if ( vpci_vcpu_init(v) ) + goto fail_sched; + d->vcpu[vcpu_id] =3D v; if ( vcpu_id !=3D 0 ) { diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 5d5ba5c016..5bfb541b6a 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -196,6 +196,7 @@ bool vpci_process_pending(struct vcpu *v) for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; + struct rangeset *mem =3D v->vpci.mem[i]; struct map_data data =3D { .d =3D v->domain, .map =3D v->vpci.cmd & PCI_COMMAND_MEMORY, @@ -203,10 +204,10 @@ bool vpci_process_pending(struct vcpu *v) }; int rc; =20 - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; =20 - rc =3D rangeset_consume_ranges(bar->mem, map_range, &data); + rc =3D rangeset_consume_ranges(mem, map_range, &data); =20 if ( rc =3D=3D -ERESTART ) { @@ -224,8 +225,8 @@ bool vpci_process_pending(struct vcpu *v) =20 /* Clean all the rangesets */ for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) - if ( !rangeset_is_empty(header->bars[i].mem) ) - rangeset_purge(header->bars[i].mem); + if ( !rangeset_is_empty(v->vpci.mem[i]) ) + rangeset_purge(v->vpci.mem[i]); =20 v->vpci.pdev =3D NULL; =20 @@ -260,13 +261,14 @@ static int __init apply_map(struct domain *d, const s= truct pci_dev *pdev, for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; + struct rangeset *mem =3D current->vpci.mem[i]; struct map_data data =3D { .d =3D d, .map =3D true, .bar =3D bar }= ; =20 - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; =20 - while ( (rc =3D rangeset_consume_ranges(bar->mem, map_range, - &data)) =3D=3D -ERESTART ) + while ( (rc =3D rangeset_consume_ranges(mem, map_range, &data)) = =3D=3D + -ERESTART ) { /* * It's safe to drop and reacquire the lock in this context @@ -331,13 +333,13 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; + struct rangeset *mem =3D current->vpci.mem[i]; unsigned long start =3D PFN_DOWN(bar->addr); unsigned long end =3D PFN_DOWN(bar->addr + bar->size - 1); unsigned long start_guest =3D PFN_DOWN(bar->guest_addr); unsigned long end_guest =3D PFN_DOWN(bar->guest_addr + bar->size -= 1); =20 - if ( !bar->mem ) - continue; + ASSERT(mem); =20 if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type !=3D VPCI_BAR_ROM @@ -354,7 +356,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) continue; } =20 - ASSERT(rangeset_is_empty(bar->mem)); + ASSERT(rangeset_is_empty(mem)); =20 /* * Make sure that the guest set address has the same page offset @@ -369,7 +371,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) return -EINVAL; } =20 - rc =3D rangeset_add_range(bar->mem, start_guest, end_guest); + rc =3D rangeset_add_range(mem, start_guest, end_guest); if ( rc ) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", @@ -380,12 +382,12 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) /* Check for overlap with the already setup BAR ranges. */ for ( j =3D 0; j < i; j++ ) { - struct vpci_bar *prev_bar =3D &header->bars[j]; + struct rangeset *prev_mem =3D current->vpci.mem[j]; =20 - if ( rangeset_is_empty(prev_bar->mem) ) + if ( rangeset_is_empty(prev_mem) ) continue; =20 - rc =3D rangeset_remove_range(prev_bar->mem, start_guest, end_g= uest); + rc =3D rangeset_remove_range(prev_mem, start_guest, end_guest)= ; if ( rc ) { gprintk(XENLOG_WARNING, @@ -395,7 +397,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) } } =20 - rc =3D pci_sanitize_bar_memory(bar->mem); + rc =3D pci_sanitize_bar_memory(mem); if ( rc ) { gprintk(XENLOG_WARNING, @@ -412,14 +414,14 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) unsigned long end =3D PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + vmsix_table_size(pdev->vpci, i) - 1); =20 - for ( j =3D 0; j < ARRAY_SIZE(header->bars); j++ ) + for ( j =3D 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) { - const struct vpci_bar *bar =3D &header->bars[j]; + struct rangeset *mem =3D current->vpci.mem[j]; =20 - if ( rangeset_is_empty(bar->mem) ) + if ( rangeset_is_empty(mem) ) continue; =20 - rc =3D rangeset_remove_range(bar->mem, start, end); + rc =3D rangeset_remove_range(mem, start, end); if ( rc ) { gprintk(XENLOG_WARNING, @@ -469,8 +471,9 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) for ( j =3D 0; j < ARRAY_SIZE(header->bars); j++) { const struct vpci_bar *bar =3D &header->bars[j]; + struct rangeset *mem =3D current->vpci.mem[j]; =20 - if ( !rangeset_overlaps_range(bar->mem, start, end) || + if ( !rangeset_overlaps_range(mem, start, end) || /* * If only the ROM enable bit is toggled check ag= ainst * other BARs in the same device for overlaps, bu= t not @@ -481,7 +484,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) bar->type =3D=3D VPCI_BAR_ROM) ) continue; =20 - rc =3D rangeset_remove_range(bar->mem, start, end); + rc =3D rangeset_remove_range(mem, start, end); if ( rc ) { gprintk(XENLOG_WARNING, @@ -734,18 +737,6 @@ static void cf_check rom_write( } } =20 -static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *b= ar, - unsigned int i) -{ - char str[32]; - - snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); - - bar->mem =3D rangeset_new(pdev->domain, str, RANGESETF_no_print); - - return !bar->mem ? -ENOMEM : 0; -} - int vpci_init_header(struct pci_dev *pdev) { uint16_t cmd; @@ -856,10 +847,6 @@ int vpci_init_header(struct pci_dev *pdev) else bars[i].type =3D VPCI_BAR_MEM32; =20 - rc =3D bar_add_rangeset(pdev, &bars[i], i); - if ( rc ) - goto fail; - rc =3D pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, (i =3D=3D num_bars - 1) ? PCI_BAR_LAST : 0); if ( rc < 0 ) @@ -913,12 +900,6 @@ int vpci_init_header(struct pci_dev *pdev) 4, rom); if ( rc ) rom->type =3D VPCI_BAR_EMPTY; - else - { - rc =3D bar_add_rangeset(pdev, rom, num_bars); - if ( rc ) - goto fail; - } } else if ( !is_hwdom ) { diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 0ac9ec8b04..d069ca6d9c 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -24,6 +24,35 @@ =20 #ifdef __XEN__ =20 +void vpci_vcpu_destroy(struct vcpu *v) +{ + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) + return; + + for ( unsigned int i =3D 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) + RANGESET_DESTROY(v->vpci.mem[i]); +} + +int vpci_vcpu_init(struct vcpu *v) +{ + unsigned int i; + + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) + return 0; + + for ( i =3D 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) + { + char str[32]; + + snprintf(str, sizeof(str), "%pv:BAR%u", v, i); + v->vpci.mem[i] =3D rangeset_new(v->domain, str, RANGESETF_no_print= ); + if ( !v->vpci.mem[i] ) + return -ENOMEM; + } + + return 0; +} + #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT static int assign_virtual_sbdf(struct pci_dev *pdev) { @@ -89,8 +118,6 @@ struct vpci_register *vpci_get_register(const struct vpc= i *vpci, =20 void vpci_deassign_device(struct pci_dev *pdev) { - unsigned int i; - ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); =20 if ( !has_vpci(pdev->domain) || !pdev->vpci ) @@ -116,9 +143,6 @@ void vpci_deassign_device(struct pci_dev *pdev) } spin_unlock(&pdev->vpci->lock); =20 - for ( i =3D 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) - rangeset_destroy(pdev->vpci->header.bars[i].mem); - xfree(pdev->vpci); pdev->vpci =3D NULL; } diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index 817505badf..f01e00ec92 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -40,6 +40,13 @@ struct rangeset *rangeset_new( void rangeset_destroy( struct rangeset *r); =20 +/* Destroy a rangeset, and zero the pointer to it. */ +#define RANGESET_DESTROY(r) \ + ({ \ + rangeset_destroy(r); \ + (r) =3D NULL; \ + }) + /* * Set a limit on the number of ranges that may exist in set @r. * NOTE: This must be called while @r is empty. diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 877aa391d1..b55bacbe6e 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -19,6 +19,9 @@ */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) =20 +void vpci_vcpu_destroy(struct vcpu *v); +int vpci_vcpu_init(struct vcpu *v); + /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); =20 @@ -54,7 +57,6 @@ struct vpci { uint64_t guest_addr; uint64_t size; uint64_t resizable_sizes; - struct rangeset *mem; enum { VPCI_BAR_EMPTY, VPCI_BAR_IO, @@ -152,14 +154,15 @@ struct vpci { #endif }; =20 +#ifdef __XEN__ struct vpci_vcpu { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ const struct pci_dev *pdev; + struct rangeset *mem[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; uint16_t cmd; bool rom_only : 1; }; =20 -#ifdef __XEN__ void vpci_dump_msi(void); =20 /* Arch-specific vPCI MSI helpers. */ @@ -204,6 +207,9 @@ bool vpci_ecam_read(pci_sbdf_t sbdf, unsigned int reg, = unsigned int len, #else /* !CONFIG_HAS_VPCI */ struct vpci_vcpu {}; =20 +static inline void vpci_vcpu_destroy(struct vcpu *v) { } +static inline int vpci_vcpu_init(struct vcpu *v) { return 0; } + static inline int vpci_reinit_ext_capabilities(struct pci_dev *pdev) { return 0; --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:01:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:01:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277476.1562687 (Exim 4.92) (envelope-from ) id 1wApwx-0004xi-NG; Thu, 09 Apr 2026 14:01:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277476.1562687; Thu, 09 Apr 2026 14:01:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApwx-0004vJ-Fs; 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b=ctNEyAYDDI7BRjMx7wY67oi4Gdxs/5MpU6Nqf6nJfa4T7isstI1GV4picuuEqM/PcqXyY12IIXPLd9AM0UnPRHrWX7FEvz+pNdeXdvM1n7HhaeKk/QqwBKiLXA4TVEyY8zlrTo/qG8raaBkNRAW8LBwvWlLNynVw8lNmPpPj3Q1vC1lOHmo7zt9ZdzGZZrbrTeW2Nq+ow1Lw3rPm3mrW8rlX9wA5hShcukfNt0ws4vWVZddGgqBhhpTNxZdO9vd6m3EL/8W0EKZByRrme2Y7sSMAQX5Wz+j81uH7bBdkZszLsgq4BfX7tlTfubJqn4XGlZ6s0rDKUPRORoFlh0icNQ== From: Mykyta Poturai To: "xen-devel@lists.xenproject.org" CC: Stewart Hildebrand , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Stefano Stabellini Subject: [PATCH v3 4/7] vpci: allow queueing of mapping operations Thread-Topic: [PATCH v3 4/7] vpci: allow queueing of mapping operations Thread-Index: AQHcyClfiKiYHZL9uEi4zPN+JRCyeQ== Date: Thu, 9 Apr 2026 14:01:33 +0000 Message-ID: <97e3323363ab442ccb21a00d5ed0488b6672870a.1775742115.git.mykyta_poturai@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: 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X-MS-Exchange-CrossTenant-Network-Message-Id: f79b1c04-2a35-405e-ba38-08de96408235 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 14:01:33.9435 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m8FagHfZBkVLGjLgkd2H5Gcl/wqByHWonaQBgqqvHo7Z4tFjCcUSLgou8oy1FS1IVQTONipQp7xr102DnTpHVg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3PR03MB10964 X-purgate-ID: tlsNG-4011c0/1775743296-0E74F0B1-B148B212/0/0 X-purgate-type: clean X-purgate-size: 19628 From: Stewart Hildebrand Introduce vPCI BAR mapping task queue. Store information needed to map/unmap BARs in struct vpci_map_task. Allow queueing of BAR map/unmap operations in a list, thus making it possible to perform multiple p2m operations associated with single PCI device. This is preparatory work for further changes that need to perform multiple unmap/map operations before returning to guest. At the moment, only a single operation will be queued. However, when multiple operations are queued, there is a check in modify_bars() to skip BARs already in the requested state that will no longer be accurate. Remove this check in preparation of upcoming changes. Signed-off-by: Stewart Hildebrand Message-ID: <20260406191203.97662-3-stewart.hildebrand@amd.com> --- v2->v3: * new patch in this series, borrowed from [1] [1]: https://patchew.org/Xen/20260406191203.97662-1-stewart.hildebrand@amd.= com/20260406191203.97662-3-stewart.hildebrand@amd.com/ --- xen/common/domain.c | 5 +- xen/drivers/vpci/header.c | 227 ++++++++++++++++++++++++++----------- xen/drivers/vpci/vpci.c | 28 +---- xen/include/xen/rangeset.h | 7 -- xen/include/xen/vpci.h | 21 ++-- 5 files changed, 179 insertions(+), 109 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index 5ef7db8f09..b1931be987 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -455,8 +455,6 @@ static int vcpu_teardown(struct vcpu *v) */ static void vcpu_destroy(struct vcpu *v) { - vpci_vcpu_destroy(v); - free_vcpu_struct(v); } =20 @@ -514,8 +512,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int= vcpu_id) if ( arch_vcpu_create(v) !=3D 0 ) goto fail_sched; =20 - if ( vpci_vcpu_init(v) ) - goto fail_sched; + vpci_vcpu_init(v); =20 d->vcpu[vcpu_id] =3D v; if ( vcpu_id !=3D 0 ) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index 5bfb541b6a..451cdd3a6f 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 #include =20 @@ -35,7 +36,7 @@ =20 struct map_data { struct domain *d; - const struct vpci_bar *bar; + const struct vpci_bar_map *bar; bool map; }; =20 @@ -174,32 +175,20 @@ static void modify_decoding(const struct pci_dev *pde= v, uint16_t cmd, ASSERT_UNREACHABLE(); } =20 -bool vpci_process_pending(struct vcpu *v) +static int vpci_process_map_task(const struct pci_dev *pdev, + struct vpci_map_task *task) { - const struct pci_dev *pdev =3D v->vpci.pdev; - struct vpci_header *header =3D NULL; unsigned int i; =20 - if ( !pdev ) - return false; - - read_lock(&v->domain->pci_lock); - - if ( !pdev->vpci || (v->domain !=3D pdev->domain) ) - { - v->vpci.pdev =3D NULL; - read_unlock(&v->domain->pci_lock); - return false; - } + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); =20 - header =3D &pdev->vpci->header; - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar =3D &header->bars[i]; - struct rangeset *mem =3D v->vpci.mem[i]; + struct vpci_bar_map *bar =3D &task->bars[i]; + struct rangeset *mem =3D bar->mem; struct map_data data =3D { - .d =3D v->domain, - .map =3D v->vpci.cmd & PCI_COMMAND_MEMORY, + .d =3D pdev->domain, + .map =3D task->cmd & PCI_COMMAND_MEMORY, .bar =3D bar, }; int rc; @@ -210,58 +199,116 @@ bool vpci_process_pending(struct vcpu *v) rc =3D rangeset_consume_ranges(mem, map_range, &data); =20 if ( rc =3D=3D -ERESTART ) - { - read_unlock(&v->domain->pci_lock); - return true; - } + return rc; =20 if ( rc ) { spin_lock(&pdev->vpci->lock); /* Disable memory decoding unconditionally on failure. */ - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, - false); + modify_decoding(pdev, task->cmd & ~PCI_COMMAND_MEMORY, false); spin_unlock(&pdev->vpci->lock); =20 - /* Clean all the rangesets */ - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) - if ( !rangeset_is_empty(v->vpci.mem[i]) ) - rangeset_purge(v->vpci.mem[i]); + if ( !is_hardware_domain(pdev->domain) ) + domain_crash(pdev->domain); + + return rc; + } + } + + spin_lock(&pdev->vpci->lock); + modify_decoding(pdev, task->cmd, task->rom_only); + spin_unlock(&pdev->vpci->lock); + + return 0; +} + +static void destroy_map_task(struct vpci_map_task *task) +{ + unsigned int i; + + if ( !task ) + { + ASSERT_UNREACHABLE(); + return; + } + + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) + rangeset_destroy(task->bars[i].mem); + + xvfree(task); +} + +static void clear_map_queue(struct vcpu *v) +{ + struct vpci_map_task *task; + + while ( (task =3D list_first_entry_or_null(&v->vpci.task_queue, + struct vpci_map_task, + next)) !=3D NULL ) + { + list_del(&task->next); + destroy_map_task(task); + } +} + +bool vpci_process_pending(struct vcpu *v) +{ + const struct pci_dev *pdev =3D v->vpci.pdev; + struct vpci_map_task *task; =20 - v->vpci.pdev =3D NULL; + if ( !pdev ) + return false; =20 + read_lock(&v->domain->pci_lock); + + if ( !pdev->vpci || (v->domain !=3D pdev->domain) ) + { + clear_map_queue(v); + v->vpci.pdev =3D NULL; + read_unlock(&v->domain->pci_lock); + return false; + } + + while ( (task =3D list_first_entry_or_null(&v->vpci.task_queue, + struct vpci_map_task, + next)) !=3D NULL ) + { + int rc =3D vpci_process_map_task(pdev, task); + + if ( rc =3D=3D -ERESTART ) + { read_unlock(&v->domain->pci_lock); + return true; + } =20 - if ( !is_hardware_domain(v->domain) ) - domain_crash(v->domain); + list_del(&task->next); + destroy_map_task(task); =20 - return false; + if ( rc ) + { + clear_map_queue(v); + break; } } v->vpci.pdev =3D NULL; =20 - spin_lock(&pdev->vpci->lock); - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); - spin_unlock(&pdev->vpci->lock); - read_unlock(&v->domain->pci_lock); =20 return false; } =20 static int __init apply_map(struct domain *d, const struct pci_dev *pdev, - uint16_t cmd) + struct vpci_map_task *task) { - struct vpci_header *header =3D &pdev->vpci->header; int rc =3D 0; unsigned int i; =20 ASSERT(rw_is_write_locked(&d->pci_lock)); =20 - for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) { - struct vpci_bar *bar =3D &header->bars[i]; - struct rangeset *mem =3D current->vpci.mem[i]; + struct vpci_bar_map *bar =3D &task->bars[i]; + struct rangeset *mem =3D bar->mem; struct map_data data =3D { .d =3D d, .map =3D true, .bar =3D bar }= ; =20 if ( rangeset_is_empty(mem) ) @@ -281,15 +328,52 @@ static int __init apply_map(struct domain *d, const s= truct pci_dev *pdev, } } if ( !rc ) - modify_decoding(pdev, cmd, false); + modify_decoding(pdev, task->cmd, false); =20 return rc; } =20 -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_o= nly) +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, + uint16_t cmd, bool rom_only) +{ + struct vpci_map_task *task; + unsigned int i; + + task =3D xvzalloc(struct vpci_map_task); + + if ( !task ) + return NULL; + + for ( i =3D 0; i < ARRAY_SIZE(task->bars); i++ ) + { + if ( !MAPPABLE_BAR(&pdev->vpci->header.bars[i]) ) + continue; + + task->bars[i].mem =3D rangeset_new(pdev->domain, NULL, + RANGESETF_no_print); + + if ( !task->bars[i].mem ) + { + destroy_map_task(task); + return NULL; + } + + task->bars[i].addr =3D pdev->vpci->header.bars[i].addr; + task->bars[i].guest_addr =3D pdev->vpci->header.bars[i].guest_addr= ; + } + + task->cmd =3D cmd; + task->rom_only =3D rom_only; + + return task; +} + +static void defer_map(const struct pci_dev *pdev, struct vpci_map_task *ta= sk) { struct vcpu *curr =3D current; =20 + ASSERT(!curr->vpci.pdev || curr->vpci.pdev =3D=3D pdev); + /* * FIXME: when deferring the {un}map the state of the device should no= t * be trusted. For example the enable bit is toggled after the device @@ -297,8 +381,8 @@ static void defer_map(const struct pci_dev *pdev, uint1= 6_t cmd, bool rom_only) * started for the same device if the domain is not well-behaved. */ curr->vpci.pdev =3D pdev; - curr->vpci.cmd =3D cmd; - curr->vpci.rom_only =3D rom_only; + list_add_tail(&task->next, &curr->vpci.task_queue); + /* * Raise a scheduler softirq in order to prevent the guest from resumi= ng * execution with pending mapping operations, to trigger the invocatio= n @@ -313,11 +397,17 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) struct pci_dev *tmp; const struct domain *d; const struct vpci_msix *msix =3D pdev->vpci->msix; + struct vpci_map_task *task; unsigned int i, j; int rc; =20 ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); =20 + task =3D alloc_map_task(pdev, cmd, rom_only); + + if ( !task ) + return -ENOMEM; + /* * Create a rangeset per BAR that represents the current device memory * region and compare it against all the currently active BAR memory @@ -333,19 +423,18 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) for ( i =3D 0; i < ARRAY_SIZE(header->bars); i++ ) { struct vpci_bar *bar =3D &header->bars[i]; - struct rangeset *mem =3D current->vpci.mem[i]; + struct rangeset *mem =3D task->bars[i].mem; unsigned long start =3D PFN_DOWN(bar->addr); unsigned long end =3D PFN_DOWN(bar->addr + bar->size - 1); unsigned long start_guest =3D PFN_DOWN(bar->guest_addr); unsigned long end_guest =3D PFN_DOWN(bar->guest_addr + bar->size -= 1); =20 - ASSERT(mem); + if ( !mem ) + continue; =20 if ( !MAPPABLE_BAR(bar) || (rom_only ? bar->type !=3D VPCI_BAR_ROM - : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) || - /* Skip BARs already in the requested state. */ - bar->enabled =3D=3D !!(cmd & PCI_COMMAND_MEMORY) ) + : (bar->type =3D=3D VPCI_BAR_ROM && !header->rom_en= abled)) ) continue; =20 if ( !pci_check_bar(pdev, _mfn(start), _mfn(end)) ) @@ -368,7 +457,8 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) gprintk(XENLOG_G_WARNING, "%pp: can't map BAR%u - offset mismatch: %#lx vs %#lx\= n", &pdev->sbdf, i, bar->guest_addr, bar->addr); - return -EINVAL; + rc =3D -EINVAL; + goto fail; } =20 rc =3D rangeset_add_range(mem, start_guest, end_guest); @@ -376,13 +466,13 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) { printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", start_guest, end_guest, rc); - return rc; + goto fail; } =20 /* Check for overlap with the already setup BAR ranges. */ for ( j =3D 0; j < i; j++ ) { - struct rangeset *prev_mem =3D current->vpci.mem[j]; + struct rangeset *prev_mem =3D task->bars[j].mem; =20 if ( rangeset_is_empty(prev_mem) ) continue; @@ -393,7 +483,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove overlapping range [%lx, %lx]= : %d\n", &pdev->sbdf, start_guest, end_guest, rc); - return rc; + goto fail; } } =20 @@ -403,7 +493,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to sanitize BAR#%u memory: %d\n", &pdev->sbdf, i, rc); - return rc; + goto fail; } } =20 @@ -414,9 +504,9 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) unsigned long end =3D PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + vmsix_table_size(pdev->vpci, i) - 1); =20 - for ( j =3D 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) + for ( j =3D 0; j < ARRAY_SIZE(task->bars); j++ ) { - struct rangeset *mem =3D current->vpci.mem[j]; + struct rangeset *mem =3D task->bars[j].mem; =20 if ( rangeset_is_empty(mem) ) continue; @@ -427,7 +517,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove MSIX table [%lx, %lx]: %d\n"= , &pdev->sbdf, start, end, rc); - return rc; + goto fail; } } } @@ -471,7 +561,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) for ( j =3D 0; j < ARRAY_SIZE(header->bars); j++) { const struct vpci_bar *bar =3D &header->bars[j]; - struct rangeset *mem =3D current->vpci.mem[j]; + struct rangeset *mem =3D task->bars[j].mem; =20 if ( !rangeset_overlaps_range(mem, start, end) || /* @@ -490,7 +580,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16= _t cmd, bool rom_only) gprintk(XENLOG_WARNING, "%pp: failed to remove [%lx, %lx]: %d\n", &pdev->sbdf, start, end, rc); - return rc; + goto fail; } } } @@ -513,12 +603,19 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint= 16_t cmd, bool rom_only) * will always be to establish mappings and process all the BARs. */ ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); - return apply_map(pdev->domain, pdev, cmd); + rc =3D apply_map(pdev->domain, pdev, task); + destroy_map_task(task); + return rc; } =20 - defer_map(pdev, cmd, rom_only); + defer_map(pdev, task); =20 return 0; + + fail: + destroy_map_task(task); + + return rc; } =20 static void cf_check cmd_write( diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index d069ca6d9c..ce9fb5b357 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -24,33 +24,9 @@ =20 #ifdef __XEN__ =20 -void vpci_vcpu_destroy(struct vcpu *v) +void vpci_vcpu_init(struct vcpu *v) { - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) - return; - - for ( unsigned int i =3D 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) - RANGESET_DESTROY(v->vpci.mem[i]); -} - -int vpci_vcpu_init(struct vcpu *v) -{ - unsigned int i; - - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) - return 0; - - for ( i =3D 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) - { - char str[32]; - - snprintf(str, sizeof(str), "%pv:BAR%u", v, i); - v->vpci.mem[i] =3D rangeset_new(v->domain, str, RANGESETF_no_print= ); - if ( !v->vpci.mem[i] ) - return -ENOMEM; - } - - return 0; + INIT_LIST_HEAD(&v->vpci.task_queue); } =20 #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h index f01e00ec92..817505badf 100644 --- a/xen/include/xen/rangeset.h +++ b/xen/include/xen/rangeset.h @@ -40,13 +40,6 @@ struct rangeset *rangeset_new( void rangeset_destroy( struct rangeset *r); =20 -/* Destroy a rangeset, and zero the pointer to it. */ -#define RANGESET_DESTROY(r) \ - ({ \ - rangeset_destroy(r); \ - (r) =3D NULL; \ - }) - /* * Set a limit on the number of ranges that may exist in set @r. * NOTE: This must be called while @r is empty. diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index b55bacbe6e..e34f7abe6d 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -19,8 +19,7 @@ */ #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) =20 -void vpci_vcpu_destroy(struct vcpu *v); -int vpci_vcpu_init(struct vcpu *v); +void vpci_vcpu_init(struct vcpu *v); =20 /* Assign vPCI to device by adding handlers. */ int __must_check vpci_assign_device(struct pci_dev *pdev); @@ -155,14 +154,23 @@ struct vpci { }; =20 #ifdef __XEN__ -struct vpci_vcpu { +struct vpci_map_task { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ - const struct pci_dev *pdev; - struct rangeset *mem[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; + struct list_head next; + struct vpci_bar_map { + uint64_t addr; + uint64_t guest_addr; + struct rangeset *mem; + } bars[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; uint16_t cmd; bool rom_only : 1; }; =20 +struct vpci_vcpu { + const struct pci_dev *pdev; + struct list_head task_queue; +}; + void vpci_dump_msi(void); =20 /* Arch-specific vPCI MSI helpers. */ @@ -207,8 +215,7 @@ bool vpci_ecam_read(pci_sbdf_t sbdf, unsigned int reg, = unsigned int len, #else /* !CONFIG_HAS_VPCI */ struct vpci_vcpu {}; =20 -static inline void vpci_vcpu_destroy(struct vcpu *v) { } -static inline int vpci_vcpu_init(struct vcpu *v) { return 0; } +static inline void vpci_vcpu_init(struct vcpu *v) { } =20 static inline int vpci_reinit_ext_capabilities(struct pci_dev *pdev) { --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:01:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:01:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277471.1562654 (Exim 4.92) (envelope-from ) id 1wApwv-0004Kq-K4; Thu, 09 Apr 2026 14:01:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277471.1562654; Thu, 09 Apr 2026 14:01:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApwv-0004Kg-HU; Thu, 09 Apr 2026 14:01:37 +0000 Received: by outflank-mailman (input) for mailman id 1277471; Thu, 09 Apr 2026 14:01:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApwu-0004KE-00 for xen-devel@lists.xenproject.org; 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Thu, 9 Apr 2026 14:01:32 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=epam.com header.i="@epam.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:x-ms-exchange-senderadcheck" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=u0Gw3SG0rG+rXP57aIcJs3FSDlAyKTjN3tdfPjprLSCm8zrgPKnXXC6++meAUHL9MiEebo0+340debtDOaQiE/N44/AmJZXwjHldOASTlerpnYDWWj/6Da6HsSaPd2xS9hxEk26F79EqBRbLRxLDfL/p+QzXB0td3FkKaUNxZqVMyoEbqlOlB1wivYi6FnrhKXf/oE+PVNpomT6imBnAXV7nu9S3sjDhC3/0B8gMa3d8zpqt0ixnK3t/XCRP/jz7SYyK7hrAlkr7yLABq1+qx1cGbS8VCJjnOzrQ+vs7lhEGIH017cUXwM0XOuK2GY2bJhOibyRWIddepvBGMqezWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 938b6f27-9ff3-4b7f-7e16-08de96408180 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 14:01:32.5739 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Ia4w88aADiQ0w7lukqEt9lYZ7t0WeJF6yq21Z0LKg2N7fSdTkPVP5/Cbs8XBdhvLGWKbb8LAHV8Hy2wyVipKtw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3PR03MB10964 X-purgate-ID: tlsNG-4011c0/1775743295-BFB450B1-5FA90408/0/0 X-purgate-type: clean X-purgate-size: 3963 From: Stewart Hildebrand Export functions required for SR-IOV support. Signed-off-by: Stewart Hildebrand Signed-off-by: Mykyta Poturai Reviewed-by: Teddy Astie --- v2->v3: * move declaration to private.h v1->v2 * Collect RBs --- xen/drivers/vpci/header.c | 16 +++++++++------- xen/drivers/vpci/private.h | 3 +++ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index a760d8c32f..96995e098b 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -305,7 +305,7 @@ static void defer_map(const struct pci_dev *pdev, uint1= 6_t cmd, bool rom_only) raise_softirq(SCHEDULE_SOFTIRQ); } =20 -static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_= only) +int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_on= ly) { struct vpci_header *header =3D &pdev->vpci->header; struct pci_dev *tmp; @@ -546,7 +546,7 @@ static void cf_check cmd_write( * memory decoding bit has not been changed, so leave everything a= s-is, * hoping the guest will realize and try again. */ - modify_bars(pdev, cmd, false); + vpci_modify_bars(pdev, cmd, false); else pci_conf_write16(pdev->sbdf, reg, cmd); } @@ -714,13 +714,15 @@ static void cf_check rom_write( * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note th= at * this fabricated command is never going to be written to the registe= r. */ - else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true= ) ) + else if ( vpci_modify_bars(pdev, + new_enabled ? PCI_COMMAND_MEMORY : 0, + true) ) /* * No memory has been added or removed from the p2m (because the a= ctual * p2m changes are deferred in defer_map) and the ROM enable bit h= as * not been changed, so leave everything as-is, hoping the guest w= ill * realize and try again. It's important to not update rom->addr i= n the - * unmap case if modify_bars has failed, or future attempts would + * unmap case if vpci_modify_bars has failed, or future attempts w= ould * attempt to unmap the wrong address. */ return; @@ -800,8 +802,8 @@ int vpci_init_header(struct pci_dev *pdev) /* * For DomUs, clear PCI_COMMAND_{MASTER,MEMORY,IO} and other * DomU-controllable bits in PCI_COMMAND. Devices assigned to DomUs wi= ll - * start with memory decoding disabled, and modify_bars() will not be = called - * at the end of this function. + * start with memory decoding disabled, and vpci_modify_bars() will no= t be + * called at the end of this function. */ if ( !is_hwdom ) cmd &=3D ~(PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_INVALIDATE | @@ -926,7 +928,7 @@ int vpci_init_header(struct pci_dev *pdev) goto fail; } =20 - return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0; + return (cmd & PCI_COMMAND_MEMORY) ? vpci_modify_bars(pdev, cmd, false)= : 0; =20 fail: pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd); diff --git a/xen/drivers/vpci/private.h b/xen/drivers/vpci/private.h index 2907f6b40f..6fdf8a20d9 100644 --- a/xen/drivers/vpci/private.h +++ b/xen/drivers/vpci/private.h @@ -138,6 +138,9 @@ static inline size_t vmsix_table_size(const struct vpci= *vpci, unsigned int nr) 8), 8); } =20 +/* Map/unmap the BARs of a vPCI device. */ +int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_on= ly); + #endif /* __XEN__ */ =20 #endif /* VPCI_PRIVATE_H */ --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:01:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:01:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277479.1562726 (Exim 4.92) (envelope-from ) id 1wApx6-0006M1-H0; Thu, 09 Apr 2026 14:01:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277479.1562726; Thu, 09 Apr 2026 14:01:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wApx6-0006LR-Br; Thu, 09 Apr 2026 14:01:48 +0000 Received: by outflank-mailman (input) for mailman id 1277479; Thu, 09 Apr 2026 14:01:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wApx4-0006HP-W3 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 14:01:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wApx4-00CXs8-Br for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 16:01:46 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7b146-e002-0a2a0a5209dd-0a2a45068fc2-38 for ; Thu, 09 Apr 2026 16:01:46 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7b14a-0df0-0a2a45060019-d1558035c4d2-3 for ; Thu, 09 Apr 2026 16:01:46 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-488c2690057so9604115e9.0 for ; Thu, 09 Apr 2026 07:01:46 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Question is why neither Arm nor >> RISC-V use that function, when we have it. > > I haven't seen this function, I will re-use it and in separate patch > suggest to re-use it for Arm. > > One thing I think we want to do then is to drop #ifdef x86 around > sched_setup_dom0_vcpus() and rename it to sched_setup_dom_vcpus(). > And maybe add dprintk()'s to provide some information about which vCPUs > were created and which not. Arm doesn't re-use sched_setup_dom0_vcpus() because it has extra if() inside: for ( i = 1; i < d->max_vcpus; i++ ) { if ( vcpu_create(d, i) == NULL ) { printk("Failed to allocate d%dv%d\n", d->domain_id, i); break; } if ( is_64bit_domain(d) ) vcpu_switch_to_aarch64_mode(d->vcpu[i]); } domain_update_node_affinity(d); sched_setup_dom0_vcpus() still could be re-used but the an extra for() loop will be needed for: if ( is_64bit_domain(d) ) vcpu_switch_to_aarch64_mode(d->vcpu[i]); I think it doesn't then too much sense to re-use sched_setup_dom0_vcpus() for Arm. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:22:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:22:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277577.1562735 (Exim 4.92) (envelope-from ) id 1wAqGz-0004JU-3W; Thu, 09 Apr 2026 14:22:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277577.1562735; Thu, 09 Apr 2026 14:22:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqGz-0004JN-0s; Thu, 09 Apr 2026 14:22:21 +0000 Received: by outflank-mailman (input) for mailman id 1277577; Thu, 09 Apr 2026 14:22:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqGx-0004JH-GO for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 14:22:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAqGw-00227Y-SQ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 16:22:18 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7b60d-5cb7-0a2a0a5109dd-0a2a4502abf2-36 for ; Thu, 09 Apr 2026 16:22:18 +0200 Received: from [136.143.188.51] (helo=sender4-of-o51.zoho.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7b619-42fa-0a2a45020019-888fbc33526d-3 for ; Thu, 09 Apr 2026 16:22:18 +0200 Received: by mx.zohomail.com with SMTPS id 177574452402699.36308080543574; Thu, 9 Apr 2026 07:22:04 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=zoho header.d=apertussolutions.com header.i="dpsmith@apertussolutions.com" header.h="Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Content-Type:Content-Transfer-Encoding" ARC-Seal: i=1; a=rsa-sha256; t=1775744526; cv=none; d=zohomail.com; s=zohoarc; b=BfBSWefW1BhNediGuKRcHVfzOjDXKP7RxuS3imV/ZdAoUttTXSm+MwLL97bnDvBXC44cNyzlSuqEMJpGM8Hzbos2F8tsDe1BQUlGerPaq+qrSKD+FHlUlqZSLaoKcEGzVsDkmh2lJT9MITx05kuwbKvyeHVO3G4AXv8xe6rPN3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775744526; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=imeMNDLn99b+xNdVIDfzn74PuiUbdT5o5oCsPuPIrz4=; b=EzJka3odHO0oCAm+WHEhXLhP1h++cHUJxUQ13beB1Ymq0uu4AFeZWQ3qvNMRj1k5CnWSkap/+zsGqEsvhgTFHuOEw5P42ZXU8Fotxt7FdCAdgzqSLBF3tcdAJDF15kcqGGIGIwLoviBYqCccmObHsYRVZ0pFISc31WYACYkMF3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=apertussolutions.com; spf=pass smtp.mailfrom=dpsmith@apertussolutions.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1775744526; s=zoho; d=apertussolutions.com; i=dpsmith@apertussolutions.com; h=Message-ID:Date:Date:MIME-Version:Subject:Subject:To:To:Cc:Cc:References:From:From:In-Reply-To:Content-Type:Content-Transfer-Encoding:Message-Id:Reply-To; bh=imeMNDLn99b+xNdVIDfzn74PuiUbdT5o5oCsPuPIrz4=; b=Zlo119EeLYAZ9n/6kS+Auk28WE8X9OCjU+iz6sDCJp5Ar+UWC8L9CDwM9mN//F64 3rNtmMxh3KJ3PLOvCEFVmC81cvelrOieFDa/59jdDhZMmjIHfka6SNYHe1RZmdEhiEq 0LZjdnsE1b5+6Nvc/w0FEfRcAm95EIgnhsNmvq3M= Message-ID: <2df92603-ab5e-4990-8a6a-e7a56d952243@apertussolutions.com> Date: Thu, 9 Apr 2026 10:22:02 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/efi: Reduce ifdefary in efi_exit_boot() Content-Language: en-US To: Andrew Cooper , Jan Beulich Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Xen-devel References: <20260409103805.176240-1-andrew.cooper3@citrix.com> <65b04675-abbf-413e-abe7-6cd463913fdd@suse.com> <04b9c465-4940-4a16-8abc-9c3440ab7337@citrix.com> From: "Daniel P. Smith" Autocrypt: addr=dpsmith@apertussolutions.com; keydata= xsJuBFYrueARCACPWL3r2bCSI6TrkIE/aRzj4ksFYPzLkJbWLZGBRlv7HQLvs6i/K4y/b4fs JDq5eL4e9BdfdnZm/b+K+Gweyc0Px2poDWwKVTFFRgxKWq9R7McwNnvuZ4nyXJBVn7PTEn/Z G7D08iZg94ZsnUdeXfgYdJrqmdiWA6iX9u84ARHUtb0K4r5WpLUMcQ8PVmnv1vVrs/3Wy/Rb foxebZNWxgUiSx+d02e3Ad0aEIur1SYXXv71mqKwyi/40CBSHq2jk9eF6zmEhaoFi5+MMMgX X0i+fcBkvmT0N88W4yCtHhHQds+RDbTPLGm8NBVJb7R5zbJmuQX7ADBVuNYIU8hx3dF3AQCm 601w0oZJ0jGOV1vXQgHqZYJGHg5wuImhzhZJCRESIwf+PJxik7TJOgBicko1hUVOxJBZxoe0 x+/SO6tn+s8wKlR1Yxy8gYN9ZRqV2I83JsWZbBXMG1kLzV0SAfk/wq0PAppA1VzrQ3JqXg7T MZ3tFgxvxkYqUP11tO2vrgys+InkZAfjBVMjqXWHokyQPpihUaW0a8mr40w9Qui6DoJj7+Gg DtDWDZ7Zcn2hoyrypuht88rUuh1JuGYD434Q6qwQjUDlY+4lgrUxKdMD8R7JJWt38MNlTWvy rMVscvZUNc7gxcmnFUn41NPSKqzp4DDRbmf37Iz/fL7i01y7IGFTXaYaF3nEACyIUTr/xxi+ MD1FVtEtJncZNkRn7WBcVFGKMAf+NEeaeQdGYQ6mGgk++i/vJZxkrC/a9ZXme7BhWRP485U5 sXpFoGjdpMn4VlC7TFk2qsnJi3yF0pXCKVRy1ukEls8o+4PF2JiKrtkCrWCimB6jxGPIG3lk 3SuKVS/din3RHz+7Sr1lXWFcGYDENmPd/jTwr1A1FiHrSj+u21hnJEHi8eTa9029F1KRfocp ig+k0zUEKmFPDabpanI323O5Tahsy7hwf2WOQwTDLvQ+eqQu40wbb6NocmCNFjtRhNZWGKJS b5GrGDGu/No5U6w73adighEuNcCSNBsLyUe48CE0uTO7eAL6Vd+2k28ezi6XY4Y0mgASJslb NwW54LzSSM0uRGFuaWVsIFAuIFNtaXRoIDxkcHNtaXRoQGFwZXJ0dXNzb2x1dGlvbnMuY29t PsJ6BBMRCAAiBQJWK7ngAhsjBgsJCAcDAgYVCAIJCgsEFgIDAQIeAQIXgAAKCRBTc6WbYpR8 KrQ9AP94+xjtFfJ8gj5c7PVx06Zv9rcmFUqQspZ5wSEkvxOuQQEAg6qEsPYegI7iByLVzNEg 7B7fUG7pqWIfMqFwFghYhQzOwU0EViu54BAIAL6MXXNlrJ5tRUf+KMBtVz1LJQZRt/uxWrCb T06nZjnbp2UcceuYNbISOVHGXTzu38r55YzpkEA8eURQf+5hjtvlrOiHxvpD+Z6WcpV6rrMB kcAKWiZTQihW2HoGgVB3gwG9dCh+n0X5OzliAMiGK2a5iqnIZi3o0SeW6aME94bSkTkuj6/7 OmH9KAzK8UnlhfkoMg3tXW8L6/5CGn2VyrjbB/rcrbIR4mCQ+yCUlocuOjFCJhBd10AG1IcX OXUa/ux+/OAV9S5mkr5Fh3kQxYCTcTRt8RY7+of9RGBk10txi94dXiU2SjPbassvagvu/hEi twNHms8rpkSJIeeq0/cAAwUH/jV3tXpaYubwcL2tkk5ggL9Do+/Yo2WPzXmbp8vDiJPCvSJW rz2NrYkd/RoX+42DGqjfu8Y04F9XehN1zZAFmCDUqBMa4tEJ7kOT1FKJTqzNVcgeKNBGcT7q 27+wsqbAerM4A0X/F/ctjYcKwNtXck1Bmd/T8kiw2IgyeOC+cjyTOSwKJr2gCwZXGi5g+2V8 NhJ8n72ISPnOh5KCMoAJXmCF+SYaJ6hIIFARmnuessCIGw4ylCRIU/TiXK94soilx5aCqb1z ke943EIUts9CmFAHt8cNPYOPRd20pPu4VFNBuT4fv9Ys0iv0XGCEP+sos7/pgJ3gV3pCOric p15jV4PCYQQYEQgACQUCViu54AIbDAAKCRBTc6WbYpR8Khu7AP9NJrBUn94C/3PeNbtQlEGZ NV46Mx5HF0P27lH3sFpNrwD/dVdZ5PCnHQYBZ287ZxVfVr4Zuxjo5yJbRjT93Hl0vMY= In-Reply-To: <04b9c465-4940-4a16-8abc-9c3440ab7337@citrix.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ZohoMailClient: External X-purgate-ID: tlsNG-720697/1775744538-AF52CCD1-5D14FBB5/0/0 X-purgate-type: clean X-purgate-size: 3956 On 4/9/26 07:11, Andrew Cooper wrote: > On 09/04/2026 12:01 pm, Jan Beulich wrote: >> On 09.04.2026 12:38, Andrew Cooper wrote: >>> Use IS_ENABLED() rather than #ifdef to give the compiler visibility into the >>> block, which in turn removes the #ifdef from the varaible block. >> Just to mention, if it was just / mainly ... >> >>> --- a/xen/common/efi/boot.c >>> +++ b/xen/common/efi/boot.c >>> @@ -1335,9 +1335,7 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste >>> EFI_STATUS status; >>> UINTN info_size = 0, map_key; >>> bool retry; >>> -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP >>> unsigned int i; >>> -#endif >> ... this to be got rid of, we could as well use ... >> >>> @@ -1371,31 +1369,32 @@ static void __init efi_exit_boot(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *Syste >>> if ( EFI_ERROR(status) ) >>> PrintErrMesg(L"Cannot exit boot services", status); >>> >>> -#ifdef CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP >>> - for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) >> for ( unsigned int i = 0; i < efi_memmap_size; i += efi_mdesc_size ) >> >> now. But yes, the typo aspect you mention can be avoided altogether by what >> you change things to. > > I originally had this change in the patch, but it interferes with diff > showing (just) an indentation change. > > I'm not fussed either way. > >> >>> + if ( IS_ENABLED(CONFIG_EFI_SET_VIRTUAL_ADDRESS_MAP) ) >>> { >>> - EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; >>> + for ( i = 0; i < efi_memmap_size; i += efi_mdesc_size ) >>> + { >>> + EFI_MEMORY_DESCRIPTOR *desc = efi_memmap + i; >>> >>> - /* >>> - * Runtime services regions are always mapped here. >>> - * Attributes may be adjusted in efi_init_memory(). >>> - */ >>> - if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || >>> - desc->Type == EfiRuntimeServicesCode || >>> - desc->Type == EfiRuntimeServicesData ) >>> - desc->VirtualStart = desc->PhysicalStart; >>> - else >>> - desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; >>> - } >>> - status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, >>> - mdesc_ver, efi_memmap); >>> - if ( status != EFI_SUCCESS ) >>> - { >>> - printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", >>> - status); >>> - __clear_bit(EFI_RS, &efi_flags); >>> + /* >>> + * Runtime services regions are always mapped here. >>> + * Attributes may be adjusted in efi_init_memory(). >>> + */ >>> + if ( (desc->Attribute & EFI_MEMORY_RUNTIME) || >>> + desc->Type == EfiRuntimeServicesCode || >>> + desc->Type == EfiRuntimeServicesData ) >>> + desc->VirtualStart = desc->PhysicalStart; >>> + else >>> + desc->VirtualStart = INVALID_VIRTUAL_ADDRESS; >>> + } >>> + status = efi_rs->SetVirtualAddressMap(efi_memmap_size, efi_mdesc_size, >>> + mdesc_ver, efi_memmap); >>> + if ( status != EFI_SUCCESS ) >>> + { >>> + printk(XENLOG_ERR "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", >>> + status); >> Could I talk you into switching to >> >> printk(XENLOG_ERR >> "EFI: SetVirtualAddressMap() failed (%#lx), disabling runtime services\n", >> status); >> >> to make the line at least a little less long? > > Ok, but I'm not going to resend just for that. > > ~Andrew I'm good with fix up on commit. Acked-by: Daniel P. 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pr=C Message-ID: <685f565a-ca8f-4a76-8b66-6f09614d1ee5@amd.com> Date: Thu, 9 Apr 2026 16:31:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] xen/drivers/char: fix SCIF IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: <276f353ec36258dc545bef581389e60a162988b6.1775742562.git.oleksii_moisieiev@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <276f353ec36258dc545bef581389e60a162988b6.1775742562.git.oleksii_moisieiev@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE4:EE_|PH7PR12MB5927:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a120a0c-3da7-40ce-bde9-08de9644c42d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Xl6p+XHCk/WR/vGnVU5MF/4RiRnVFbQgsvgCOm9wtx1Ovp+Yf6EfrLnEnWUizepRf5p96SAZbUt8SY8U+56rmSoq7QMWQhpy7BuOU5sVpRMagI7149qJqtAfq/jAYIiGgzGPqlGRNaDfqgkbIRDkLNROq+v0S3bHf8bKBa2C2Sm3Dajpp8TFGWy3aON2llN35QKJKgolRm0lil3+BdsKex1+F5dz6YuPLv7Lc30xPI/l18Yv/8iuAjqigjPipiElSgnBe4mHEMAkarWc5LcjUhZpv1YtpOcvEK4KoY+wAfL0e+IIJmO9OozHELLHaSmfx8aaxaqiVGj/ojGFuWQkROPkNj/LQklkgi97n8430G0kGNpeHiKmRYGVomjvZYc5MtBGO3vz+NJLJcHN7ShieBQaK78oKg8IxJ8vdZaWuFD2+iaIjZB5HnTlvY9w5IFc X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 14:32:02.6061 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a120a0c-3da7-40ce-bde9-08de9644c42d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5927 X-purgate-ID: tlsNG-42698a/1775745127-EF9412A1-32AA93AE/0/0 X-purgate-type: clean X-purgate-size: 1504 On 09/04/2026 15:50, Oleksii Moisieiev wrote: > In scif_uart_init_postirq(), when setup_irq() returns an error the > failure was only logged via dprintk() and execution continued, > unconditionally writing TIE|RIE|REIE into the Serial Control Register > (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, > RX data ready, receive error) with no handler registered to service > them. On platforms where the GIC receives these asserted lines, the > result is either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > The fix adds an early return inside the error branch. The > interrupt-enable write to SCSCR is skipped entirely when no handler is > registered. > > SCIF TX continues to operate correctly after this change. The Xen > serial framework never calls serial_async_transmit() for SCIF, so > port->txbuf is always NULL. This causes __serial_putc() to take the > synchronous finite-capacity path, which polls the SCFSR_TDFE hardware > flag directly and does not depend on the interrupt mechanism. RX > wouldn't work if irq wasn't registered. > > As a secondary clean-up, the hardware error-flag clearing sequence is > moved to before the setup_irq() call so that error bits accumulated > since init_preirq() are cleared unconditionally, regardless of whether > IRQ registration succeeds. > > Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:33:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:33:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277597.1562753 (Exim 4.92) (envelope-from ) id 1wAqRg-00077L-EI; Thu, 09 Apr 2026 14:33:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277597.1562753; Thu, 09 Apr 2026 14:33:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqRg-00077E-AY; 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bh=fJUtP/iDO2spTKYHFNGBHi/9Yu5vL6tP0LS3/Jfd7sY=; b=ZaAwhM+QvfZGR6MVeDCyb89dOq0izkpjfwJE23qYZECmRnmzWi3KSp6VME5bR5YIlcF47Saq7in6yFreu13cwFnJcJqUI69Xg96c7UQ2aTl6eAEpADHp/Qy3ye+byMVYpFlm6EXGHPJapAPa5NmEKhf12/J/GRlBw2h4BPhy9uc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Message-ID: Date: Thu, 9 Apr 2026 16:33:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] xen/drivers/char: fix exynos4210 IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: <043b73edeee02b477f210cfd82f0b2940de2ef21.1775742562.git.oleksii_moisieiev@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <043b73edeee02b477f210cfd82f0b2940de2ef21.1775742562.git.oleksii_moisieiev@epam.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gd6mJyucktj4eHkDUEAdY/fRlIq7IerTK19DgamhC7u156I+R9z85EpXqr2kYGJszkCxwNL0a9552VlRaUkWez4eOL3OSmZKn2/jW1cCky0+N8+G1AEfBKA0XzRi+TDx5PDIswcLj7qLbI0R6nZ2mns602Yb3hfFojKRb65L+vC2y8XqPF0WRQ41DjpYx7pP932n9F9i45SqD33ruNAJh0esriVgCbASZyd8bnQztuk/vsulqnOJOslxDY8p4qn3C37gAWLYsEqbudYHc5TfrPQxex1UiNeddDJEOzyDlfnSjXKvOfM0vRPv7j+L+7Wv3lIp2XGpNsE1fcoIPpxnbh63f+oBkhPVaD7wpeZ8t+8RdKUFdeuwb9NRz1sRZMfgL1KliyenSR+g1z7GMnId3h1DSTK6SrXa6NyOmzoS0jo8fRCjMA/AXA9A1ijd3Ihh X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 14:33:17.4635 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc35ecb2-4f0e-4099-8827-08de9644f0da X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8249 X-purgate-ID: tlsNG-d25034/1775745201-FF547A3D-85C9FB0A/0/0 X-purgate-type: clean X-purgate-size: 785 On 09/04/2026 15:50, Oleksii Moisieiev wrote: > In exynos4210_uart_init_postirq(), when setup_irq() returns an error > the failure was only logged via dprintk() and execution continued, > unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled > receive and transmit interrupt lines with no handler registered. On > platforms where the GIC receives these asserted lines, the result is > either repeated spurious-interrupt warnings or an unhandled interrupt > fault. > > Add an early return in the setup_irq() error branch so that the > interrupt-enable writes to UINTM and UMCON are skipped when IRQ > registration fails. > > Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:34:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:34:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277607.1562762 (Exim 4.92) (envelope-from ) id 1wAqT8-0007dz-Oa; Thu, 09 Apr 2026 14:34:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277607.1562762; Thu, 09 Apr 2026 14:34:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqT8-0007ds-Kz; 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bh=jqm/d4wMbEQ/ud4emWG3Tsk3IJS83pXyHnPaPmPqBJQ=; b=S7Sjz39yOU/xOMy8OeOT+lHoCF06UP6mvdFgmZpr3TusnQ+eVrAKu/tnipfODaiCBWXWf5l7cZ2O4cJjZci18Nbati55tuu+BtZaazf+GRuQP+bq1zsosxpR00S6jZ8lxpBoUAzIkObdZ4RUbfgFs5wYfHU27PPgy7KdKePP0AY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Message-ID: <31be1ea4-ac65-43b1-80c0-7e1a8a8723ab@amd.com> Date: Thu, 9 Apr 2026 16:39:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] xen/drivers/char/pl011: fix IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , Volodymyr Babchuk References: <9148b1721adfacf20c5621eb583f6fe87dead767.1775742562.git.oleksii_moisieiev@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <9148b1721adfacf20c5621eb583f6fe87dead767.1775742562.git.oleksii_moisieiev@epam.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: O4zuGNPe09SEC9toV+cmxJQlHUGsDvtOPvimo7y8E+iQvPuHr8wAnCEfYlkOTFDOHQXpJyPfwVTwvTcRySdedoyywfB9M/UTC3dJAhxMQ4kJ8oriFm6mlTQEuBV/quKC+7FsveYZMZKq9+vyNGBghatz1W2R4oif2aTHvnC5X7qbCuVtFFsvSZYakikzN27xregLMr9GLeZe9eoy1ANVMDStRffxkfMYXM3W+aA8KbKsko3JfEx0uNXyt0cgDG/ePrKxfXkqPCTzgwwfdSo6ltD2Do6zdK0gqTwfRx0bKVdV0CxwUDhrXIKluQ0i1dOKi3z01SCr/eF1LhhuNe5L5zz2N+y2syom8ykCMoqLsVnylo7zjiYHUbgQ5K4oeM07xsE2h79umaEwL4D989hAFIlhe+ftLMmjTIoOzSEk6m3irIFkYBUlcolqPUIvXbWq X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2026 14:39:29.0273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95e302cc-b0b1-4729-f312-08de9645ce44 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LVUPR12MB999162 X-purgate-ID: tlsNG-c201ff/1775745571-3252396F-7C0479B2/0/0 X-purgate-type: clean X-purgate-size: 2675 On 09/04/2026 15:50, Oleksii Moisieiev wrote: > In pl011_init_postirq(), two code paths could reach the > interrupt-unmask write to IMSC without a handler being registered: > > - When no valid IRQ number was provided (uart->irq <= 0), the original > positive-condition guard (if uart->irq > 0) skipped the irqaction > setup but still fell through to the IMSC write, unmasking > RTI|OEI|BEI|PEI|FEI|TXI|RXI with no handler installed. > > - When setup_irq() returned an error, only an error message was > printed and execution continued to the IMSC write, arming all > hardware interrupt lines with no handler to service them. On > platforms where the GIC receives these asserted lines, the result > is either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure pl011_init_postirq() to use early returns: return > immediately when no valid IRQ is provided, and return after logging > the error when setup_irq() fails. The interrupt-enable write to IMSC > is only reached when IRQ registration succeeds. > > Signed-off-by: Oleksii Moisieiev > --- > > > > xen/drivers/char/pl011.c | 17 +++++++++++------ > 1 file changed, 11 insertions(+), 6 deletions(-) > > diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c > index 5f9913367d..918b9d4d4a 100644 > --- a/xen/drivers/char/pl011.c > +++ b/xen/drivers/char/pl011.c > @@ -150,13 +150,18 @@ static void __init pl011_init_postirq(struct serial_port *port) > struct pl011 *uart = port->uart; > int rc; > > - if ( uart->irq > 0 ) > + /* Don't unmask interrupts if no valid irq was provided */ > + if ( uart->irq <= 0 ) > + return; > + > + uart->irqaction.handler = pl011_interrupt; > + uart->irqaction.name = "pl011"; > + uart->irqaction.dev_id = port; > + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > { > - uart->irqaction.handler = pl011_interrupt; > - uart->irqaction.name = "pl011"; > - uart->irqaction.dev_id = port; > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); > + printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); > + /* Do not unmask interrupts if irq handler wasn't set */ > + return; > } > > /* Clear pending error interrupts */ I think we should clear pending errors every time. Other than that, the patch is ok. Provided the remark is addressed: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:45:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:45:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277635.1562779 (Exim 4.92) (envelope-from ) id 1wAqdJ-000277-SD; Thu, 09 Apr 2026 14:45:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277635.1562779; Thu, 09 Apr 2026 14:45:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqdJ-000270-Pe; Thu, 09 Apr 2026 14:45:25 +0000 Received: by outflank-mailman (input) for mailman id 1277635; Thu, 09 Apr 2026 14:45:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqdI-00026u-LL for xen-devel@lists.xenproject.org; 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dkim=pass header.s=20201203 header.d=lwn.net header.i="@lwn.net" header.h="From:To:Cc:Subject:In-Reply-To:References:Date" DKIM-Filter: OpenDKIM Filter v2.11.0 ms.lwn.net 33E0F40B2D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lwn.net; s=20201203; t=1775745920; bh=9UjJsJZfwJanCZGABshmZ68foQfId21dwyXnZXsn0Gw=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=M1oTRvPKdFlczPjiNIi/kCOEUebV1SXduyRsOHJpL6K0vbeF7garYUzALbfVlNJ4K vYb5oD+VFS1redUL+alhViqUA7Azlm07SoiQuXZZlwRqT+qrjdv2/ieKdX7WRLJ2ej bU5jiQnxytqPyM5rusfbuut+ov9uLPaL3OscGK1qaclZ8FP160BA7mZiw1TtzfSfI0 wuO00U1Oqh/CUoQ0yrke2WSt2Ab0iRWzeuAfEn//CzU9PUcWjIiVWoYJaqWIouQZsj b+i6lOmTcZVE1487sabU7Vfjgpps3XWTp9w9T3+XQyBQPrCVyMxdsNPjrqVlDN6vSI BWvIqbZO4KlSQ== From: Jonathan Corbet To: Shubham Chakraborty , jgross@suse.com Cc: sstabellini@kernel.org, boris.ostrovsky@oracle.com, linux-doc@vger.kernel.org, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, Shubham Chakraborty Subject: Re: [PATCH v2] docs: sysctl: Add documentation for /proc/sys/xen/ In-Reply-To: <20260304150419.16738-1-chakrabortyshubham66@gmail.com> References: <20260304150419.16738-1-chakrabortyshubham66@gmail.com> Date: Thu, 09 Apr 2026 08:45:19 -0600 Message-ID: <87fr54b3b4.fsf@trenco.lwn.net> MIME-Version: 1.0 Content-Type: text/plain X-purgate-ID: tlsNG-16d1c6/1775745923-AF5383D8-161F3CAB/0/0 X-purgate-type: clean X-purgate-size: 847 Shubham Chakraborty writes: > Add documentation for the Xen hypervisor sysctl controls in > /proc/sys/xen/balloon/. > > Documents the hotplug_unpopulated tunable (available when > CONFIG_XEN_BALLOON_MEMORY_HOTPLUG is enabled) which controls > whether unpopulated memory regions are automatically hotplugged > when the Xen balloon driver needs to reclaim memory. > > The documentation is based on source code analysis of > drivers/xen/balloon.c. > > Signed-off-by: Shubham Chakraborty > --- > Documentation/admin-guide/sysctl/index.rst | 3 ++- > Documentation/admin-guide/sysctl/xen.rst | 31 ++++++++++++++++++++++ > 2 files changed, 33 insertions(+), 1 deletion(-) > create mode 100644 Documentation/admin-guide/sysctl/xen.rst Applied, thanks. jon From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:49:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:49:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277646.1562789 (Exim 4.92) (envelope-from ) id 1wAqgo-0003Jh-CT; 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Additionally, unset > the dt_device_is_protected flag and free no longer needed smmu_master. > > Tested on QEMU with SRIOV series[1] by repeatedly enabling/disabling > VFs. > > [1]: https://patchew.org/Xen/cover.1772806036.git.mykyta._5Fpoturai@epam.com/ > > Signed-off-by: Mykyta Poturai > --- > xen/drivers/passthrough/arm/smmu-v3.c | 59 +++++++++++++++++++++++++++ > xen/include/xen/device_tree.h | 5 +++ > 2 files changed, 64 insertions(+) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index bf153227db..b5b834a7b7 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -1493,6 +1493,64 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct device *dev, > static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, > struct device *dev); > > +static int arm_smmu_remove_device(u8 devfn, struct device *dev) > +{ > + int ret = 0; > + struct arm_smmu_master *master; > + struct iommu_fwspec *fwspec; > + > + fwspec = dev_iommu_fwspec_get(dev); > + if ( !fwspec ) > + return -ENODEV; > + > + master = dev_iommu_priv_get(dev); > + if ( !master ) > + return -ENODEV; > + > +#ifdef CONFIG_HAS_PCI > + if ( dev_is_pci(dev) ) > + { > + struct pci_dev *pdev = dev_to_pci(dev); As Luca has already noticed in a separate email regarding phantom functions: If I understand the code correctly, the iommu_remove_device() loops over PCI phantom functions, calling ops->remove_device() multiple times for the exact same struct device *dev. Because you omitted the phantom function check (which exists in arm_smmu_add_device), the code will process the first phantom function, fall through to out_free, and destroy the master struct. When the iommu_remove_device() subsequently calls remove_device() for the main devfn, dev_iommu_priv_get(dev) will return NULL, and the removal will abort with -ENODEV. Should not we ignore phantom functions at the top of the PCI block, just like in the add_device()? if ( devfn != pdev->devfn ) return 0; > + > + if ( pdev->domain ) > + { > + ret = arm_smmu_deassign_dev(pdev->domain, devfn, dev); > + if ( ret ) > + printk(XENLOG_WARNING "Failed to deassign device %pp from SMMU\n", > + &pdev->sbdf); What worries me is a possible state corruption on deassign failure. If arm_smmu_deassign_dev() fails, the code prints a warning but continues execution here ... > + } > + } > +#endif > + > + if ( !dev_is_pci(dev) ) NIT: I think that you could simplify the PCI/platform device split to avoid evaluating dev_is_pci(dev) twice by using #else block. > + { > + if ( !dt_device_is_protected(dev_to_dt(dev)) ) > + { > + dev_err(dev, "Not added to SMMUv3\n"); > + ret = -ENODEV; > + goto out_free; > + } > + > + if ( master->domain && master->domain->d ) > + { > + ret = arm_smmu_deassign_dev(master->domain->d, 0, dev); > + if ( ret ) > + dev_warn(dev, "Failed to deassign device from SMMU\n"); > + } ... and here. It falls through to the bottom of the function where it frees the master struct. Because you return an error code, the IOMMU framework (specifically in the DT path) will abort the removal. At least, iommu_remove_dt_device() sees the error code and skips freeing the fwspec. But because you freed the master struct, the SMMUv3 driver has lost track of the device, while the common code might think it is still assigned and functional... Should not we bail out immediately and return the error without freeing master or altering the protected state if arm_smmu_deassign_dev() fails? Or am I missing something? > + dt_device_unset_protected(dev_to_dt(dev)); > + } > + > + arm_smmu_disable_pasid(master); > + > + dev_info(dev, "Removed master device (SMMUv3 %s StreamIds %u)\n", > + dev_name(fwspec->iommu_dev), fwspec->num_ids); > + > +out_free: > + xfree(master); > + dev_iommu_priv_set(dev, NULL); > + return ret; > +} > + > static int arm_smmu_add_device(u8 devfn, struct device *dev) > { > int i, ret; > @@ -2867,6 +2925,7 @@ static const struct iommu_ops arm_smmu_iommu_ops = { > .unmap_page = arm_iommu_unmap_page, > .dt_xlate = arm_smmu_dt_xlate, > .add_device = arm_smmu_add_device, > + .remove_device = arm_smmu_remove_device, > }; > > static __init int arm_smmu_dt_init(struct dt_device_node *dev, > diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h > index 06d7643622..1f9608cdcd 100644 > --- a/xen/include/xen/device_tree.h > +++ b/xen/include/xen/device_tree.h > @@ -305,6 +305,11 @@ static inline void dt_device_set_protected(struct dt_device_node *device) > device->is_protected = true; > } > > +static inline void dt_device_unset_protected(struct dt_device_node *device) > +{ > + device->is_protected = false; > +} NIT: Rather than introducing new helper, it might be possible to update the existing helper to take a boolean: e.g., dt_device_set_protected(struct dt_device_node *device, bool protect). But doing this would require updating existing callers, I am not sure if that broader refactoring is necessary, so your current unset approach is acceptable. > + > static inline bool dt_device_is_protected(const struct dt_device_node *device) > { > return device->is_protected; From xen-devel-bounces@lists.xenproject.org Thu Apr 09 14:59:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 14:59:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277662.1562798 (Exim 4.92) (envelope-from ) id 1wAqqn-0005TU-9i; Thu, 09 Apr 2026 14:59:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277662.1562798; Thu, 09 Apr 2026 14:59:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqqn-0005TN-6X; Thu, 09 Apr 2026 14:59:21 +0000 Received: by outflank-mailman (input) for mailman id 1277662; Thu, 09 Apr 2026 14:59:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqqm-0005TH-7A for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 14:59:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAqql-005ubM-JD for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 16:59:19 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7beb3-bab6-0a2a0a5309dd-0a2a45099d8c-18 for ; Thu, 09 Apr 2026 16:59:19 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7bec7-bf79-0a2a45090019-d1558029d13d-3 for ; Thu, 09 Apr 2026 16:59:19 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-488b00ed86fso11048545e9.3 for ; Thu, 09 Apr 2026 07:59:19 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 07:59:18 -0700 (PDT) Message-ID: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Date: Thu, 9 Apr 2026 16:59:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v4 00/16] x86: support AVX10 To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775746759-2F34C152-A3EF381A/0/0 X-purgate-type: clean X-purgate-size: 1598 AVX10.1 is just a re-branding of certain AVX512 (sub)features, i.e. adds no new instructions. Therefore it's mostly relaxation that needs doing. Luckily the 256-bit-only case and an unnecessary restriction on the mask register insns was taken out again, simplifying the actual emulator adjustments quite a bit. AVX10.2 is adding quite a few new insns, support for which is roughly added chapter-wise as the spec has them (perhaps not in the order of the chapters there). While it probably could be re-based ahead, the series in this form depends on the previously submitted "[PATCH v5 0/3] x86/CPUID: leaf pruning" and parts of whatever is left of "[PATCH v9 00/10] x86emul: misc additions". I've tried to be very careful in rebasing ahead of other emulator patches I've been carrying, but almost all testing I've done is with all of those collectively in place. 01: x86/CPUID: enable AVX10 leaf 02: x86emul: support SIMD MOVRS 03: x86emul: support AVX10.2 forms of SM4 insns 04: x86emul: support AVX10.1 05: x86emul/test: use simd_check_avx512*() in main() 06: x86emul/test: drop cpu_has_avx512vl 07: x86emul: AVX10.1 testing 08: x86emul/test: engage AVX512VL via command line option 09: x86/CPUID: enable AVX10.2 sub-leaf 10: x86emul: support AVX10.2 scalar compare insns 11: x86emul: support AVX10.2 partial copy insns 12: x86emul: support AVX10.2 media insns 13: x86emul: support AVX10.2 minmax insns 14: x86emul: support AVX10.2 BFloat16 insns 15: x86emul: support AVX10.2 saturating convert insns 16: x86emul: support other AVX10.2 convert insns Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:00:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:00:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277673.1562807 (Exim 4.92) (envelope-from ) id 1wAqrx-00070n-MB; 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Thu, 09 Apr 2026 08:02:14 -0700 (PDT) Message-ID: <5ed45e7e-6873-4651-9abd-9ece141ed79f@suse.com> Date: Thu, 9 Apr 2026 17:02:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 01/16] x86emul: support SIMD MOVRS From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775746935-C56170B1-63DDE55B/0/0 X-purgate-type: clean X-purgate-size: 4760 As we ignore cachability aspects of insns, they're treated like simple VMOVs. Signed-off-by: Jan Beulich --- SDE: -dmr --- v4: Correct main switch case labels to reference Map5. Switch to using fallthrough pseudo-keyword. Move ahead in series, switching feature dependency to plain AVX10. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -720,6 +720,13 @@ static const struct test vpclmulqdq_all[ INSN(pclmulqdq, 66, 0f3a, 44, vl, q_nb, vl) }; +static const struct test movrs_all[] = { + INSN(movrsb, f2, map5, 6f, vl, b, vl), + INSN(movrsd, f3, map5, 6f, vl, d_nb, vl), + INSN(movrsq, f3, map5, 6f, vl, q_nb, vl), + INSN(movrsw, f2, map5, 6f, vl, w, vl), +}; + static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 }; static const unsigned char vl_128[] = { VL_128 }; static const unsigned char vl_no128[] = { VL_512, VL_256 }; @@ -1071,8 +1078,8 @@ void evex_disp8_test(void *instr, struct emulops.read = read; emulops.write = write; -#define RUN(feat, vl) do { \ - if ( cpu_has_##feat ) \ +#define run(cond, feat, vl) do { \ + if ( cond ) \ { \ printf("%-40s", "Testing " #feat "/" #vl " disp8 handling..."); \ test_group(feat ## _ ## vl, ARRAY_SIZE(feat ## _ ## vl), \ @@ -1081,6 +1088,8 @@ void evex_disp8_test(void *instr, struct } \ } while ( false ) +#define RUN(feat, vl) run(cpu_has_ ## feat, feat, vl) + RUN(avx512f, all); RUN(avx512f, 128); RUN(avx512f, no128); @@ -1111,4 +1120,9 @@ void evex_disp8_test(void *instr, struct RUN(vaes, all); RUN(vpclmulqdq, all); } + + if ( cpu_has_avx10 ) + { + run(ctxt->addr_size == 64 && cpu_has_movrs, movrs, all); + } } --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2124,6 +2124,8 @@ static const struct evex { { { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */ { { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */ { { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */ + { { 0x6f }, 2, T, R, pfx_f3, Wn, Ln }, /* vmovrs{d,q} */ + { { 0x6f }, 2, T, R, pfx_f2, Wn, Ln }, /* vmovrs{b,w} */ { { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */ { { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttph2uqq */ { { 0x78 }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2usi */ --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -209,12 +209,14 @@ void wrpkru(unsigned int val); xcr0_mask(0xe6)) #define cpu_has_cmpccxadd cpu_policy.feat.cmpccxadd #define cpu_has_avx_ifma (cpu_policy.feat.avx_ifma && xcr0_mask(6)) +#define cpu_has_movrs cpu_policy.feat.movrs #define cpu_has_avx_vnni_int8 (cpu_policy.feat.avx_vnni_int8 && \ xcr0_mask(6)) #define cpu_has_avx_ne_convert (cpu_policy.feat.avx_ne_convert && \ xcr0_mask(6)) #define cpu_has_avx_vnni_int16 (cpu_policy.feat.avx_vnni_int16 && \ xcr0_mask(6)) +#define cpu_has_avx10 (cpu_policy.feat.avx10 && xcr0_mask(0xe6)) #define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1) --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -622,6 +622,8 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) #define vcpu_has_user_msr() (ctxt->cpuid->feat.user_msr) +#define vcpu_has_avx10() (ctxt->cpuid->feat.avx10) + #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -7880,6 +7880,17 @@ x86_emulate( op_bytes = 8 << evex.lr; goto simd_zmm; + case X86EMUL_OPC_EVEX_F2(5, 0x6f): /* vmovrs{b,w} mem,[xyz]mm{k} */ + elem_bytes = 1 << evex.w; + fallthrough; + case X86EMUL_OPC_EVEX_F3(5, 0x6f): /* vmovrs{d,q} mem,[xyz]mm{k} */ + generate_exception_if(ea.type != OP_MEM || evex.brs, X86_EXC_UD); + vcpu_must_have(avx10); + vcpu_must_have(movrs); + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_zmm; + case X86EMUL_OPC_EVEX_66(5, 0x78): /* vcvttph2uqq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x79): /* vcvtph2uqq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x7a): /* vcvttph2qq xmm/mem,[xyz]mm{k} */ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:02:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:02:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277689.1562825 (Exim 4.92) (envelope-from ) id 1wAquB-0007vi-8i; Thu, 09 Apr 2026 15:02:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277689.1562825; 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Thu, 09 Apr 2026 08:02:42 -0700 (PDT) Message-ID: <85e5d61e-3a9a-44bd-9c79-37762c6ee2e6@suse.com> Date: Thu, 9 Apr 2026 17:02:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 02/16] x86emul: support AVX10 forms of SM4 insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775746969-41B15C9A-99843D8C/0/0 X-purgate-type: clean X-purgate-size: 3152 Simply clone the VEX-encoded handling to cover the EVEX forms. Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Address v3 TODO. Move ahead in series, switching feature dependency to plain AVX10. Add call to avx512_vlen_check(). v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -727,6 +727,11 @@ static const struct test movrs_all[] = { INSN(movrsw, f2, map5, 6f, vl, w, vl), }; +static const struct test sm4_all[] = { + INSN(sm4key4, f3, 0f38, da, vl, d_nb, vl), + INSN(sm4rnds4, f2, 0f38, da, vl, d_nb, vl), +}; + static const unsigned char vl_all[] = { VL_512, VL_128, VL_256 }; static const unsigned char vl_128[] = { VL_128 }; static const unsigned char vl_no128[] = { VL_512, VL_256 }; @@ -1124,5 +1129,6 @@ void evex_disp8_test(void *instr, struct if ( cpu_has_avx10 ) { run(ctxt->addr_size == 64 && cpu_has_movrs, movrs, all); + run(cpu_has_sm4, sm4, all); } } --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2025,6 +2025,8 @@ static const struct evex { { { 0xcc }, 2, T, R, pfx_66, Wn, L2 }, /* vrsqrt28p{s,d} */ { { 0xcd }, 2, T, R, pfx_66, Wn, LIG }, /* vrsqrt28s{s,d} */ { { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */ + { { 0xda }, 2, T, R, pfx_f3, W0, Ln }, /* vsm4key4 */ + { { 0xda }, 2, T, R, pfx_f2, W0, Ln }, /* vsm4rnds4 */ { { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */ { { 0xdd }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenclast */ { { 0xde }, 2, T, R, pfx_66, WIG, Ln }, /* vaesdec */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -438,7 +438,7 @@ static const struct ext0f38_table { [0xd3] = { .simd_size = simd_other }, [0xd6] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, - [0xda] = { .simd_size = simd_other }, + [0xda] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xdb] = { .simd_size = simd_packed_int, .two_op = 1 }, [0xdc ... 0xdf] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0xe0 ... 0xef] = { .to_mem = 1 }, --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6819,6 +6819,15 @@ x86_emulate( op_bytes = 16 << vex.l; goto simd_0f_ymm; + case X86EMUL_OPC_EVEX_F3(0x0f38, 0xda): /* vsm4key4 [xyz]mm/mem,[xyz]mm,[xyz]mm */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0xda): /* vsm4rnds4 [xyz]mm/mem,[xyz]mm,[xyz]mm */ + vcpu_must_have(avx10); + vcpu_must_have(sm4); + generate_exception_if(evex.w || evex.brs || evex.opmsk, X86_EXC_UD); + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_zmm; + case X86EMUL_OPC_VEX_66(0x0f38, 0xdc): /* vaesenc {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xdd): /* vaesenclast {x,y}mm/mem,{x,y}mm,{x,y}mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0xde): /* vaesdec {x,y}mm/mem,{x,y}mm,{x,y}mm */ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:03:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:03:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277705.1562833 (Exim 4.92) (envelope-from ) id 1wAqvC-000071-Lr; Thu, 09 Apr 2026 15:03:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277705.1562833; Thu, 09 Apr 2026 15:03:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqvC-00006u-JC; Thu, 09 Apr 2026 15:03:54 +0000 Received: by outflank-mailman (input) for mailman id 1277705; Thu, 09 Apr 2026 15:03:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqvA-00006g-HY for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:03:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAqv9-00EBZ8-Pu for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:03:51 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7bfd3-e002-0a2a0a5209dd-0a2a4501d41e-14 for ; Thu, 09 Apr 2026 17:03:51 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7bfd7-6fc9-0a2a45010019-d155802cd531-3 for ; Thu, 09 Apr 2026 17:03:51 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488ba840146so9559615e9.1 for ; Thu, 09 Apr 2026 08:03:51 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 08:03:50 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:03:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 03/16] x86emul: support AVX10.1 From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Oleksii Kurochko , Community Manager References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1775747031-17EFB185-6038C92D/0/0 X-purgate-type: clean X-purgate-size: 50330 This requires relaxing various pre-existing AVX512* checks, as AVX10.1 covers all AVX512* except PF, ER, 4FMAPS, 4VNNIW (support for all of which was removed meanwhile anyway), and VP2INTERSECT. At the same time all vector widths are always supported. Note that visa_check(), replacing host_and_vcpu_must_have() uses, checks only the guest capability: We wouldn't expose AVX512* (nor AVX10) without the hardware supporting it. Similarly in avx512_vlen_check() the original host_and_vcpu_must_have() is reduced just vcpu_must_have(). This also simplifies (resulting) code in the test and fuzzing harnesses, as there the XCR0 checks that are part of cpu_has_avx512* are only needed in local code, not in the emulator itself (where respective checking occurs elsewhere anyway, utilizing emul_test_read_xcr()). While in most cases the changes to x86_emulate() are entirely mechanical, for opmask insns earlier unconditional AVX512F checks are converted into "else" clauses to existing if/else-if ones. To be certain that no uses remain, also drop respective cpu_has_avx512* (except in the test harness) and vcpu_has_avx512*(). Signed-off-by: Jan Beulich --- Probably avx512_vlen_check() should have the avx512_ prefix dropped, now that it also covers AVX10. But if so that wants to be either a prereq or a follow-on patch. visa_check() won't cover AVX10.2 and higher, but probably we will want independent checking logic for that anyway. Spec version 2 still leaves unclear what the xstate components are which would need enabling for AVX10/256. x86emul_get_fpu() is therefore untouched for now. Since it'll be reducing code size, we may want to further convert host_and_vcpu_must_have() to just vcpu_must_have() where appropriate (should be [almost?] everywhere). --- v4: Switch to using fallthrough pseudo-keyword. Drop new _vlen_check() helper again. Re-base. v3: Add ChangeLog entry. v2: Drop use of vsz128 field. Re-base, in particular over dropping of Xeon Phi support. --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,6 +16,7 @@ The format is based on [Keep a Changelog mitigate (by rate-limiting) the system wide impact of an HVM guest misusing atomic instructions. - Support for CPIO microcode in discrete multiboot modules. + - Support for AVX10.1. (Experimental) - On Arm: - Support for guest suspend and resume to/from RAM via vPSCI. --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -200,29 +200,18 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_pqe boot_cpu_has(X86_FEATURE_PQE) #define cpu_has_fpu_sel (!boot_cpu_has(X86_FEATURE_NO_FPU_SEL)) #define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX) -#define cpu_has_avx512f boot_cpu_has(X86_FEATURE_AVX512F) -#define cpu_has_avx512dq boot_cpu_has(X86_FEATURE_AVX512DQ) #define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED) #define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP) -#define cpu_has_avx512_ifma boot_cpu_has(X86_FEATURE_AVX512_IFMA) #define cpu_has_clflushopt boot_cpu_has(X86_FEATURE_CLFLUSHOPT) #define cpu_has_clwb boot_cpu_has(X86_FEATURE_CLWB) -#define cpu_has_avx512cd boot_cpu_has(X86_FEATURE_AVX512CD) #define cpu_has_proc_trace boot_cpu_has(X86_FEATURE_PROC_TRACE) #define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA) -#define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW) -#define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL) /* CPUID level 0x00000007:0.ecx */ -#define cpu_has_avx512_vbmi boot_cpu_has(X86_FEATURE_AVX512_VBMI) #define cpu_has_pku boot_cpu_has(X86_FEATURE_PKU) -#define cpu_has_avx512_vbmi2 boot_cpu_has(X86_FEATURE_AVX512_VBMI2) #define cpu_has_gfni boot_cpu_has(X86_FEATURE_GFNI) #define cpu_has_vaes boot_cpu_has(X86_FEATURE_VAES) #define cpu_has_vpclmulqdq boot_cpu_has(X86_FEATURE_VPCLMULQDQ) -#define cpu_has_avx512_vnni boot_cpu_has(X86_FEATURE_AVX512_VNNI) -#define cpu_has_avx512_bitalg boot_cpu_has(X86_FEATURE_AVX512_BITALG) -#define cpu_has_avx512_vpopcntdq boot_cpu_has(X86_FEATURE_AVX512_VPOPCNTDQ) #define cpu_has_rdpid boot_cpu_has(X86_FEATURE_RDPID) #define cpu_has_movdiri boot_cpu_has(X86_FEATURE_MOVDIRI) #define cpu_has_movdir64b boot_cpu_has(X86_FEATURE_MOVDIR64B) @@ -248,7 +237,6 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE) #define cpu_has_hybrid boot_cpu_has(X86_FEATURE_HYBRID) -#define cpu_has_avx512_fp16 boot_cpu_has(X86_FEATURE_AVX512_FP16) #define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) /* CPUID level 0x00000007:1.eax */ @@ -256,7 +244,6 @@ static inline bool boot_cpu_has(unsigned #define cpu_has_sm3 boot_cpu_has(X86_FEATURE_SM3) #define cpu_has_sm4 boot_cpu_has(X86_FEATURE_SM4) #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) -#define cpu_has_avx512_bf16 boot_cpu_has(X86_FEATURE_AVX512_BF16) #define cpu_has_cmpccxadd boot_cpu_has(X86_FEATURE_CMPCCXADD) #define cpu_has_fred boot_cpu_has(X86_FEATURE_FRED) #define cpu_has_lkgs boot_cpu_has(X86_FEATURE_LKGS) --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -577,26 +577,15 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_invpcid() (ctxt->cpuid->feat.invpcid) #define vcpu_has_rtm() (ctxt->cpuid->feat.rtm) #define vcpu_has_mpx() (ctxt->cpuid->feat.mpx) -#define vcpu_has_avx512f() (ctxt->cpuid->feat.avx512f) -#define vcpu_has_avx512dq() (ctxt->cpuid->feat.avx512dq) #define vcpu_has_rdseed() (ctxt->cpuid->feat.rdseed) #define vcpu_has_adx() (ctxt->cpuid->feat.adx) #define vcpu_has_smap() (ctxt->cpuid->feat.smap) -#define vcpu_has_avx512_ifma() (ctxt->cpuid->feat.avx512_ifma) #define vcpu_has_clflushopt() (ctxt->cpuid->feat.clflushopt) #define vcpu_has_clwb() (ctxt->cpuid->feat.clwb) -#define vcpu_has_avx512cd() (ctxt->cpuid->feat.avx512cd) #define vcpu_has_sha() (ctxt->cpuid->feat.sha) -#define vcpu_has_avx512bw() (ctxt->cpuid->feat.avx512bw) -#define vcpu_has_avx512vl() (ctxt->cpuid->feat.avx512vl) -#define vcpu_has_avx512_vbmi() (ctxt->cpuid->feat.avx512_vbmi) -#define vcpu_has_avx512_vbmi2() (ctxt->cpuid->feat.avx512_vbmi2) #define vcpu_has_gfni() (ctxt->cpuid->feat.gfni) #define vcpu_has_vaes() (ctxt->cpuid->feat.vaes) #define vcpu_has_vpclmulqdq() (ctxt->cpuid->feat.vpclmulqdq) -#define vcpu_has_avx512_vnni() (ctxt->cpuid->feat.avx512_vnni) -#define vcpu_has_avx512_bitalg() (ctxt->cpuid->feat.avx512_bitalg) -#define vcpu_has_avx512_vpopcntdq() (ctxt->cpuid->feat.avx512_vpopcntdq) #define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid) #define vcpu_has_movdiri() (ctxt->cpuid->feat.movdiri) #define vcpu_has_movdir64b() (ctxt->cpuid->feat.movdir64b) @@ -604,12 +593,10 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2intersect) #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) #define vcpu_has_tsxldtrk() (ctxt->cpuid->feat.tsxldtrk) -#define vcpu_has_avx512_fp16() (ctxt->cpuid->feat.avx512_fp16) #define vcpu_has_sha512() (ctxt->cpuid->feat.sha512) #define vcpu_has_sm3() (ctxt->cpuid->feat.sm3) #define vcpu_has_sm4() (ctxt->cpuid->feat.sm4) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) -#define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) #define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1152,6 +1152,10 @@ static unsigned long *decode_vex_gpr( return decode_gpr(regs, ~vex_reg & (mode_64bit() ? 0xf : 7)); } +#define visa_check(subfeat) \ + generate_exception_if(!cp->feat.avx512 ## subfeat && !cp->feat.avx10, \ + X86_EXC_UD) + #define avx512_vlen_check(lig) do { \ switch ( evex.lr ) \ { \ @@ -1161,7 +1165,7 @@ static unsigned long *decode_vex_gpr( break; \ case 0: case 1: \ if ( !(lig) ) \ - host_and_vcpu_must_have(avx512vl); \ + visa_check(vl); \ break; \ } \ } while ( false ) @@ -1396,7 +1400,9 @@ x86_emulate( /* KMOV{W,Q} %k, (%rax) */ stb[0] = 0xc4; stb[1] = 0xe1; - stb[2] = cpu_has_avx512bw ? 0xf8 : 0x78; + stb[2] = cp->feat.avx512bw || cp->feat.avx10 + ? 0xf8 /* L0.NP.W1 - kmovq */ + : 0x78 /* L0.NP.W0 - kmovw */; stb[3] = 0x91; stb[4] = evex.opmsk << 3; insn_bytes = 5; @@ -3423,7 +3429,7 @@ x86_emulate( (ea.type != OP_REG && evex.brs && (evex.pfx & VEX_PREFIX_SCALAR_MASK))), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); simd_zmm: @@ -3479,7 +3485,7 @@ x86_emulate( generate_exception_if((evex.lr || evex.opmsk || evex.brs || evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( (d & DstMask) != DstMem ) d &= ~TwoOp; op_bytes = 8; @@ -3506,7 +3512,7 @@ x86_emulate( generate_exception_if((evex.brs || evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); d |= TwoOp; op_bytes = !(evex.pfx & VEX_PREFIX_DOUBLE_MASK) || evex.lr @@ -3543,7 +3549,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x64): /* vpblendm{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x65): /* vblendmp{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ avx512f_no_sae: - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD); avx512_vlen_check(false); goto simd_zmm; @@ -3623,13 +3629,13 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(5, 0x2a): /* vcvtsi2sh r/m,xmm,xmm */ case X86EMUL_OPC_EVEX_F3(5, 0x7b): /* vcvtusi2sh r/m,xmm,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); /* fall through */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2a): /* vcvtsi2s{s,d} r/m,xmm,xmm */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x7b): /* vcvtusi2s{s,d} r/m,xmm,xmm */ generate_exception_if(evex.opmsk || (ea.type != OP_REG && evex.brs), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3742,7 +3748,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(5, 0x2d): /* vcvtsh2si xmm/mem,reg */ case X86EMUL_OPC_EVEX_F3(5, 0x78): /* vcvttsh2usi xmm/mem,reg */ case X86EMUL_OPC_EVEX_F3(5, 0x79): /* vcvtsh2usi xmm/mem,reg */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); /* fall through */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2c): /* vcvtts{s,d}2si xmm/mem,reg */ CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2d): /* vcvts{s,d}2si xmm/mem,reg */ @@ -3752,7 +3758,7 @@ x86_emulate( evex.opmsk || (ea.type != OP_REG && evex.brs)), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3818,7 +3824,7 @@ x86_emulate( case X86EMUL_OPC_EVEX(5, 0x2e): /* vucomish xmm/m16,xmm */ case X86EMUL_OPC_EVEX(5, 0x2f): /* vcomish xmm/m16,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */ @@ -3827,7 +3833,7 @@ x86_emulate( (ea.type != OP_REG && evex.brs) || evex.w != evex.pfx), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3971,7 +3977,7 @@ x86_emulate( case X86EMUL_OPC_VEX(0x0f, 0x4a): /* kadd{w,q} k,k,k */ if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_VEX(0x0f, 0x41): /* kand{w,q} k,k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x41): /* kand{b,d} k,k,k */ @@ -3987,11 +3993,12 @@ x86_emulate( generate_exception_if(!vex.l, X86_EXC_UD); opmask_basic: if ( vex.w ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); opmask_common: - host_and_vcpu_must_have(avx512f); generate_exception_if(!vex.r || (mode_64bit() && !(vex.reg & 8)) || ea.type != OP_REG, X86_EXC_UD); @@ -4014,13 +4021,14 @@ x86_emulate( generate_exception_if(vex.l || vex.reg != 0xf, X86_EXC_UD); goto opmask_basic; - case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{w,d}{d,q} k,k,k */ + case X86EMUL_OPC_VEX(0x0f, 0x4b): /* kunpck{wd,dq} k,k,k */ generate_exception_if(!vex.l, X86_EXC_UD); - host_and_vcpu_must_have(avx512bw); + visa_check(bw); goto opmask_common; case X86EMUL_OPC_VEX_66(0x0f, 0x4b): /* kunpckbw k,k,k */ generate_exception_if(!vex.l || vex.w, X86_EXC_UD); + visa_check(f); goto opmask_common; #endif /* X86EMUL_NO_SIMD */ @@ -4088,7 +4096,7 @@ x86_emulate( generate_exception_if((evex.w != (evex.pfx & VEX_PREFIX_DOUBLE_MASK) || (ea.type != OP_MEM && evex.brs)), X86_EXC_UD); - host_and_vcpu_must_have(avx512dq); + visa_check(dq); avx512_vlen_check(false); goto simd_zmm; @@ -4127,12 +4135,12 @@ x86_emulate( case X86EMUL_OPC_EVEX_F2(0x0f, 0x7a): /* vcvtudq2ps [xyz]mm/mem,[xyz]mm{k} */ /* vcvtuqq2ps [xyz]mm/mem,{x,y}mm{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else { case X86EMUL_OPC_EVEX(0x0f, 0x78): /* vcvttp{s,d}2udq [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX(0x0f, 0x79): /* vcvtp{s,d}2udq [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); } if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -4349,7 +4357,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x0b): /* vpmulhrsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x1c): /* vpabsb [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x1d): /* vpabsw [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = 1 << (b & 1); goto avx512f_no_sae; @@ -4381,7 +4389,7 @@ x86_emulate( generate_exception_if(b != 0x27 && evex.w != (b & 1), X86_EXC_UD); goto avx512f_no_sae; } - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = 1 << (ext == ext_0f ? b & 1 : evex.w); avx512_vlen_check(false); @@ -4454,7 +4462,7 @@ x86_emulate( dst.bytes = 2; /* fall through */ case X86EMUL_OPC_EVEX_66(5, 0x6e): /* vmovw r/m16,xmm */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f, 0x6e): /* vmov{d,q} r/m,xmm */ @@ -4462,7 +4470,7 @@ x86_emulate( generate_exception_if((evex.lr || evex.opmsk || evex.brs || evex.reg != 0xf || !evex.RX), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); get_fpu(X86EMUL_FPU_zmm); opc = init_evex(stub); @@ -4520,7 +4528,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F2(0x0f, 0x6f): /* vmovdqu{8,16} [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_F2(0x0f, 0x7f): /* vmovdqu{8,16} [xyz]mm,[xyz]mm/mem{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); elem_bytes = 1 << evex.w; goto vmovdqa; @@ -4613,7 +4621,7 @@ x86_emulate( generate_exception_if(evex.w, X86_EXC_UD); else { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); } d = (d & ~SrcMask) | SrcMem | TwoOp; @@ -4861,7 +4869,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f, 0xe6): /* vcvtdq2pd {x,y}mm/mem,[xyz]mm{k} */ /* vcvtqq2pd [xyz]mm/mem,[xyz]mm{k} */ if ( evex.pfx != vex_f3 ) - host_and_vcpu_must_have(avx512f); + visa_check(f); else if ( evex.w ) { case X86EMUL_OPC_EVEX_66(0x0f, 0x78): /* vcvttps2uqq {x,y}mm/mem,[xyz]mm{k} */ @@ -4872,11 +4880,11 @@ x86_emulate( /* vcvttpd2qq [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0x7b): /* vcvtps2qq {x,y}mm/mem,[xyz]mm{k} */ /* vcvtpd2qq [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); } else { - host_and_vcpu_must_have(avx512f); + visa_check(f); /* * While SDM version 085 has explicit wording towards embedded * rounding being ignored, it's still not entirely unambiguous with @@ -4923,7 +4931,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */ generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.brs, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); d |= TwoOp; op_bytes = 8; goto simd_zmm; @@ -4949,19 +4957,21 @@ x86_emulate( case X86EMUL_OPC_VEX(0x0f, 0x90): /* kmov{w,q} k/mem,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x90): /* kmov{b,d} k/mem,k */ generate_exception_if(vex.l || !vex.r, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); if ( vex.w ) { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); op_bytes = 4 << !vex.pfx; } else if ( vex.pfx ) { - host_and_vcpu_must_have(avx512dq); + visa_check(dq); op_bytes = 1; } else + { + visa_check(f); op_bytes = 2; + } get_fpu(X86EMUL_FPU_opmask); @@ -4983,14 +4993,15 @@ x86_emulate( generate_exception_if(vex.l || !vex.r || vex.reg != 0xf || ea.type != OP_REG, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); if ( vex.pfx == vex_f2 ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else { generate_exception_if(vex.w, X86_EXC_UD); if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); } get_fpu(X86EMUL_FPU_opmask); @@ -5022,10 +5033,9 @@ x86_emulate( dst = ea; dst.reg = decode_gpr(&_regs, modrm_reg); - host_and_vcpu_must_have(avx512f); if ( vex.pfx == vex_f2 ) { - host_and_vcpu_must_have(avx512bw); + visa_check(bw); dst.bytes = 4 << (mode_64bit() && vex.w); } else @@ -5033,7 +5043,9 @@ x86_emulate( generate_exception_if(vex.w, X86_EXC_UD); dst.bytes = 4; if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); } get_fpu(X86EMUL_FPU_opmask); @@ -5055,20 +5067,18 @@ x86_emulate( ASSERT(!state->simd_size); break; - case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */ - if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); - /* fall through */ case X86EMUL_OPC_VEX(0x0f, 0x98): /* kortest{w,q} k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x98): /* kortest{b,d} k,k */ + case X86EMUL_OPC_VEX(0x0f, 0x99): /* ktest{w,q} k,k */ case X86EMUL_OPC_VEX_66(0x0f, 0x99): /* ktest{b,d} k,k */ generate_exception_if(vex.l || !vex.r || vex.reg != 0xf || ea.type != OP_REG, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); if ( vex.w ) - host_and_vcpu_must_have(avx512bw); - else if ( vex.pfx ) - host_and_vcpu_must_have(avx512dq); + visa_check(bw); + else if ( vex.pfx || (b & 1) ) + visa_check(dq); + else + visa_check(f); get_fpu(X86EMUL_FPU_opmask); @@ -5355,7 +5365,7 @@ x86_emulate( (evex.pfx & VEX_PREFIX_SCALAR_MASK)) || !evex.r || !evex.R || evex.z), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); simd_imm8_zmm: @@ -5399,9 +5409,9 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x22): /* vpinsr{d,q} $imm8,r/m,xmm,xmm */ generate_exception_if(evex.lr || evex.opmsk || evex.brs, X86_EXC_UD); if ( b & 2 ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); if ( !mode_64bit() ) evex.w = 0; memcpy(mmvalp, &src.val, src.bytes); @@ -5438,7 +5448,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x25): /* vpternlog{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ avx512f_imm8_no_sae: - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD); avx512_vlen_check(false); goto simd_imm8_zmm; @@ -5537,7 +5547,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f, 0xe4): /* vpmulhuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0xea): /* vpminsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f, 0xee): /* vpmaxsw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = b & 0x10 ? 1 : 2; goto avx512f_no_sae; @@ -5762,7 +5772,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x10): /* vpsrlvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x11): /* vpsravw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x12): /* vpsllvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(!evex.w || evex.brs, X86_EXC_UD); elem_bytes = 2; goto avx512f_no_sae; @@ -5772,7 +5782,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f38, 0x20): /* vpmovswb [xyz]mm,{x,y}mm/mem{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x30): /* vpmovzxbw {x,y}mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x30): /* vpmovwb [xyz]mm,{x,y}mm/mem{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); if ( evex.pfx != vex_f3 ) { case X86EMUL_OPC_EVEX_66(0x0f38, 0x21): /* vpmovsxbd xmm/mem,[xyz]mm{k} */ @@ -5820,7 +5830,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x13): /* vcvtph2ps {x,y}mm/mem,[xyz]mm{k} */ generate_exception_if(evex.w || (ea.type != OP_REG && evex.brs), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( !evex.brs ) avx512_vlen_check(false); op_bytes = 8 << evex.lr; @@ -5874,7 +5884,7 @@ x86_emulate( op_bytes = 8; generate_exception_if(evex.brs, X86_EXC_UD); if ( !evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512_broadcast; case X86EMUL_OPC_EVEX_66(0x0f38, 0x1a): /* vbroadcastf32x4 m128,{y,z}mm{k} */ @@ -5884,7 +5894,7 @@ x86_emulate( generate_exception_if(ea.type != OP_MEM || !evex.lr || evex.brs, X86_EXC_UD); if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512_broadcast; case X86EMUL_OPC_VEX_66(0x0f38, 0x20): /* vpmovsxbw xmm/mem,{x,y}mm */ @@ -5909,9 +5919,9 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f38, 0x28): /* vpmovm2{b,w} k,[xyz]mm */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x38): /* vpmovm2{d,q} k,[xyz]mm */ if ( b & 0x10 ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.opmsk || ea.type != OP_REG, X86_EXC_UD); d |= TwoOp; op_bytes = 16 << evex.lr; @@ -5954,7 +5964,7 @@ x86_emulate( fault_suppression = false; /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x44): /* vplzcnt{d,q} [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512cd); + visa_check(cd); goto avx512f_no_sae; case X86EMUL_OPC_VEX_66(0x0f38, 0x2c): /* vmaskmovps mem,{x,y}mm,{x,y}mm */ @@ -6030,7 +6040,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0xba): /* vfmsub231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbc): /* vfnmadd231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbe): /* vfnmsub231p{s,d} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); goto simd_zmm; @@ -6049,7 +6059,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0xbb): /* vfmsub231s{s,d} xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbd): /* vfnmadd231s{s,d} xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xbf): /* vfnmsub231s{s,d} xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -6063,14 +6073,14 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x3a): /* vpminuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x3c): /* vpmaxsb [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x3e): /* vpmaxuw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = b & 2 ?: 1; goto avx512f_no_sae; case X86EMUL_OPC_EVEX_66(0x0f38, 0x40): /* vpmull{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); goto avx512f_no_sae; case X86EMUL_OPC_66(0x0f38, 0xdb): /* aesimc xmm/m128,xmm */ @@ -6110,7 +6120,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x51): /* vpdpbusds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x52): /* vpdpwssd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x53): /* vpdpwssds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vnni); + visa_check(_vnni); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_no_sae; @@ -6122,7 +6132,7 @@ x86_emulate( d |= TwoOp; /* fall through */ case X86EMUL_OPC_EVEX_F3(0x0f38, 0x52): /* vdpbf16ps [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_bf16); + visa_check(_bf16); generate_exception_if(evex.w, X86_EXC_UD); op_bytes = 16 << evex.lr; goto avx512f_no_sae; @@ -6139,7 +6149,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x4d): /* vrcp14s{s,d} xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x4f): /* vrsqrt14s{s,d} xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.brs, X86_EXC_UD); avx512_vlen_check(true); goto simd_zmm; @@ -6148,16 +6158,16 @@ x86_emulate( generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x54): /* vpopcnt{b,w} [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_bitalg); + visa_check(_bitalg); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x66): /* vpblendm{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = 1 << evex.w; goto avx512f_no_sae; case X86EMUL_OPC_EVEX_66(0x0f38, 0x55): /* vpopcnt{d,q} [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vpopcntdq); + visa_check(_vpopcntdq); goto avx512f_no_sae; case X86EMUL_OPC_VEX_66(0x0f38, 0x5a): /* vbroadcasti128 m128,ymm */ @@ -6166,14 +6176,14 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} [xyz]mm,[xyz]mm/mem{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); elem_bytes = 1 << evex.w; /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x88): /* vexpandp{s,d} [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x89): /* vpexpand{d,q} [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8a): /* vcompressp{s,d} [xyz]mm,[xyz]mm/mem{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8b): /* vpcompress{d,q} [xyz]mm,[xyz]mm/mem{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.brs, X86_EXC_UD); avx512_vlen_check(false); /* @@ -6207,7 +6217,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x71): /* vpshldv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x73): /* vpshrdv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); goto avx512f_no_sae; case X86EMUL_OPC_VEX (0x0f38, 0xb0): /* vcvtneoph2ps mem,[xy]mm */ @@ -6227,16 +6237,16 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x7d): /* vpermt2{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x8d): /* vperm{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ if ( !evex.w ) - host_and_vcpu_must_have(avx512_vbmi); + visa_check(_vbmi); else - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); fault_suppression = false; goto avx512f_no_sae; case X86EMUL_OPC_EVEX_66(0x0f38, 0x78): /* vpbroadcastb xmm/m8,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x79): /* vpbroadcastw xmm/m16,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.w || evex.brs, X86_EXC_UD); op_bytes = elem_bytes = 1 << (b & 1); /* See the comment at the avx512_broadcast label. */ @@ -6245,14 +6255,14 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x7a): /* vpbroadcastb r32,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x7b): /* vpbroadcastw r32,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x7c): /* vpbroadcast{d,q} reg,[xyz]mm{k} */ generate_exception_if((ea.type != OP_REG || evex.brs || evex.reg != 0xf || !evex.RX), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); get_fpu(X86EMUL_FPU_zmm); @@ -6321,7 +6331,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0x83): /* vpmultishiftqb [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ generate_exception_if(!evex.w, X86_EXC_UD); - host_and_vcpu_must_have(avx512_vbmi); + visa_check(_vbmi); fault_suppression = false; goto avx512f_no_sae; @@ -6479,8 +6489,8 @@ x86_emulate( evex.reg != 0xf || modrm_reg == state->sib_index), X86_EXC_UD); + visa_check(f); avx512_vlen_check(false); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_zmm); /* Read destination and index registers. */ @@ -6641,8 +6651,8 @@ x86_emulate( evex.reg != 0xf || modrm_reg == state->sib_index), X86_EXC_UD); + visa_check(f); avx512_vlen_check(false); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_zmm); /* Read source and index registers. */ @@ -6758,7 +6768,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f38, 0xb4): /* vpmadd52luq [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xb5): /* vpmadd52huq [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_ifma); + visa_check(_ifma); generate_exception_if(!evex.w, X86_EXC_UD); goto avx512f_no_sae; @@ -7238,7 +7248,7 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x08): /* vrndscaleps $imm8,[xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x09): /* vrndscalepd $imm8,[xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.w != (b & 1), X86_EXC_UD); avx512_vlen_check(b & 2); goto simd_imm8_zmm; @@ -7247,7 +7257,7 @@ x86_emulate( generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX(0x0f3a, 0x08): /* vrndscaleph $imm8,[xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); avx512_vlen_check(b & 2); goto simd_imm8_zmm; @@ -7360,11 +7370,11 @@ x86_emulate( evex.opmsk || evex.brs), X86_EXC_UD); if ( !(b & 2) ) - host_and_vcpu_must_have(avx512bw); + visa_check(bw); else if ( !(b & 1) ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); else - host_and_vcpu_must_have(avx512f); + visa_check(f); get_fpu(X86EMUL_FPU_zmm); opc = init_evex(stub); goto pextr; @@ -7378,7 +7388,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x39): /* vextracti32x4 $imm8,{y,z}mm,xmm/m128{k} */ /* vextracti64x2 $imm8,{y,z}mm,xmm/m128{k} */ if ( evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x23): /* vshuff32x4 $imm8,{y,z}mm/mem,{y,z}mm,{y,z}mm{k} */ @@ -7398,7 +7408,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x3b): /* vextracti32x8 $imm8,zmm,ymm/m256{k} */ /* vextracti64x4 $imm8,zmm,ymm/m256{k} */ if ( !evex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(evex.lr != 2 || evex.brs, X86_EXC_UD); fault_suppression = false; goto avx512f_imm8_no_sae; @@ -7414,7 +7424,7 @@ x86_emulate( generate_exception_if((evex.w || evex.reg != 0xf || !evex.RX || (ea.type != OP_REG && (evex.z || evex.brs))), X86_EXC_UD); - host_and_vcpu_must_have(avx512f); + visa_check(f); avx512_vlen_check(false); opc = init_evex(stub); } @@ -7506,7 +7516,7 @@ x86_emulate( if ( !(b & 0x20) ) goto avx512f_imm8_no_sae; avx512bw_imm: - host_and_vcpu_must_have(avx512bw); + visa_check(bw); generate_exception_if(evex.brs, X86_EXC_UD); elem_bytes = 1 << evex.w; avx512_vlen_check(false); @@ -7545,7 +7555,7 @@ x86_emulate( goto simd_0f_imm8_avx; case X86EMUL_OPC_EVEX_66(0x0f3a, 0x21): /* vinsertps $imm8,xmm/m32,xmm,xmm */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(evex.lr || evex.w || evex.opmsk || evex.brs, X86_EXC_UD); op_bytes = 4; @@ -7553,18 +7563,18 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x50): /* vrangep{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x56): /* vreducep{s,d} $imm8,[xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x26): /* vgetmantp{s,d} $imm8,[xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x54): /* vfixupimmp{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); goto simd_imm8_zmm; case X86EMUL_OPC_EVEX(0x0f3a, 0x26): /* vgetmantph $imm8,[xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x56): /* vreduceph $imm8,[xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7572,11 +7582,11 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x51): /* vranges{s,d} $imm8,xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x57): /* vreduces{s,d} $imm8,xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x27): /* vgetmants{s,d} $imm8,xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x55): /* vfixupimms{s,d} $imm8,xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512f); + visa_check(f); generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -7584,7 +7594,7 @@ x86_emulate( case X86EMUL_OPC_EVEX(0x0f3a, 0x27): /* vgetmantsh $imm8,xmm/mem,xmm,xmm{k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x57): /* vreducesh $imm8,xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( !evex.brs ) avx512_vlen_check(true); @@ -7595,18 +7605,19 @@ x86_emulate( case X86EMUL_OPC_VEX_66(0x0f3a, 0x30): /* kshiftr{b,w} $imm8,k,k */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x32): /* kshiftl{b,w} $imm8,k,k */ if ( !vex.w ) - host_and_vcpu_must_have(avx512dq); + visa_check(dq); + else + visa_check(f); opmask_shift_imm: generate_exception_if(vex.l || !vex.r || vex.reg != 0xf || ea.type != OP_REG, X86_EXC_UD); - host_and_vcpu_must_have(avx512f); get_fpu(X86EMUL_FPU_opmask); op_bytes = 1; /* Any non-zero value will do. */ goto simd_0f_imm8; case X86EMUL_OPC_VEX_66(0x0f3a, 0x31): /* kshiftr{d,q} $imm8,k,k */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x33): /* kshiftl{d,q} $imm8,k,k */ - host_and_vcpu_must_have(avx512bw); + visa_check(bw); goto opmask_shift_imm; case X86EMUL_OPC_66(0x0f3a, 0x44): /* pclmulqdq $imm8,xmm/m128,xmm */ @@ -7747,7 +7758,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(0x0f3a, 0x66): /* vfpclassp{s,d} $imm8,[xyz]mm/mem,k{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x67): /* vfpclasss{s,d} $imm8,xmm/mem,k{k} */ - host_and_vcpu_must_have(avx512dq); + visa_check(dq); generate_exception_if(!evex.r || !evex.R || evex.z, X86_EXC_UD); if ( !(b & 1) ) goto avx512f_imm8_no_sae; @@ -7757,7 +7768,7 @@ x86_emulate( case X86EMUL_OPC_EVEX(0x0f3a, 0x66): /* vfpclassph $imm8,[xyz]mm/mem,k{k} */ case X86EMUL_OPC_EVEX(0x0f3a, 0x67): /* vfpclasssh $imm8,xmm/mem,k{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD); if ( !(b & 1) ) goto avx512f_imm8_no_sae; @@ -7772,14 +7783,14 @@ x86_emulate( /* fall through */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x71): /* vpshld{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f3a, 0x73): /* vpshrd{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_vbmi2); + visa_check(_vbmi2); goto avx512f_imm8_no_sae; case X86EMUL_OPC_EVEX_F3(0x0f3a, 0xc2): /* vcmpsh $imm8,xmm/mem,xmm,k{k} */ generate_exception_if(ea.type != OP_REG && evex.brs, X86_EXC_UD); /* fall through */ case X86EMUL_OPC_EVEX(0x0f3a, 0xc2): /* vcmpph $imm8,[xyz]mm/mem,[xyz]mm,k{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(evex.pfx & VEX_PREFIX_SCALAR_MASK); @@ -7855,13 +7866,13 @@ x86_emulate( CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5d): /* vmin{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5e): /* vdiv{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ CASE_SIMD_SINGLE_FP(_EVEX, 5, 0x5f): /* vmax{p,s}h [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_all_fp; CASE_SIMD_ALL_FP(_EVEX, 5, 0x5a): /* vcvtp{h,d}2p{h,d} [xyz]mm/mem,[xyz]mm{k} */ /* vcvts{h,d}2s{h,d} xmm/mem,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); if ( vex.pfx & VEX_PREFIX_SCALAR_MASK ) d &= ~TwoOp; op_bytes = 2 << (((evex.pfx & VEX_PREFIX_SCALAR_MASK) ? 0 : 1 + evex.lr) + @@ -7872,7 +7883,7 @@ x86_emulate( /* vcvtqq2ph [xyz]mm/mem,xmm{k} */ case X86EMUL_OPC_EVEX_F2(5, 0x7a): /* vcvtudq2ph [xyz]mm/mem,[xy]mm{k} */ /* vcvtuqq2ph [xyz]mm/mem,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); op_bytes = 16 << evex.lr; @@ -7882,7 +7893,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(5, 0x5b): /* vcvttph2dq [xy]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX (5, 0x78): /* vcvttph2udq [xy]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX (5, 0x79): /* vcvtph2udq [xy]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7904,7 +7915,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(5, 0x79): /* vcvtph2uqq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x7a): /* vcvttph2qq xmm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x7b): /* vcvtph2qq xmm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7941,7 +7952,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(6, 0xba): /* vfmsub231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbc): /* vfnmadd231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbe): /* vfnmsub231ph [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); if ( ea.type != OP_REG || !evex.brs ) avx512_vlen_check(false); @@ -7963,7 +7974,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(6, 0xbb): /* vfmsub231sh xmm/m16,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbd): /* vfnmadd231sh xmm/m16,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(6, 0xbf): /* vfnmsub231sh xmm/m16,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || (ea.type != OP_REG && evex.brs), X86_EXC_UD); if ( !evex.brs ) @@ -7972,13 +7983,13 @@ x86_emulate( case X86EMUL_OPC_EVEX_66(6, 0x4c): /* vrcpph [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(6, 0x4e): /* vrsqrtph [xyz]mm/mem,[xyz]mm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_no_sae; case X86EMUL_OPC_EVEX_66(6, 0x4d): /* vrcpsh xmm/m16,xmm,xmm{k} */ case X86EMUL_OPC_EVEX_66(6, 0x4f): /* vrsqrtsh xmm/m16,xmm,xmm{k} */ - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || evex.brs, X86_EXC_UD); avx512_vlen_check(true); goto simd_zmm; @@ -7996,7 +8007,7 @@ x86_emulate( { unsigned int src1 = ~evex.reg; - host_and_vcpu_must_have(avx512_fp16); + visa_check(_fp16); generate_exception_if(evex.w || ((b & 1) && ea.type != OP_REG && evex.brs), X86_EXC_UD); if ( mode_64bit() ) --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -814,7 +814,7 @@ static void __init noinline xstate_check if ( cpu_has_mpx ) check_new_xstate(&s, X86_XCR0_BNDCSR | X86_XCR0_BNDREGS); - if ( cpu_has_avx512f ) + if ( boot_cpu_has(X86_FEATURE_AVX512F) || boot_cpu_has(X86_FEATURE_AVX10) ) check_new_xstate(&s, X86_XCR0_HI_ZMM | X86_XCR0_ZMM | X86_XCR0_OPMASK); /* --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -366,7 +366,7 @@ XEN_CPUFEATURE(PREFETCHI, 15*32 XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructions */ XEN_CPUFEATURE(UIRET_UIF, 15*32+17) /* UIRET updates UIF */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */ -XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector ISA */ +XEN_CPUFEATURE(AVX10, 15*32+19) /*a AVX10 Converged Vector ISA */ XEN_CPUFEATURE(SLSM, 15*32+24) /* Static Lockstep Mode */ /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:04:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:04:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277712.1562843 (Exim 4.92) (envelope-from ) id 1wAqva-0000Wi-4v; Thu, 09 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Thu, 09 Apr 2026 08:04:14 -0700 (PDT) Message-ID: <10c2a780-0f19-496b-a88d-5f01371be091@suse.com> Date: Thu, 9 Apr 2026 17:04:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 04/16] x86emul/test: use simd_check_avx512*() in main() From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775747055-81B54A3D-97BFB3F9/0/0 X-purgate-type: clean X-purgate-size: 10148 In preparation for having these also cover AVX10, use the helper functions in preference of open-coded cpu_has_avx512* for those features that AVX10 includes. Introduce a couple further helper functions where they weren't previously needed. Note that this way simd_check_avx512f_sha_vl() gains an AVX512F check (which is likely benign) and simd_check_avx512bw_gf_vl() gains an AVX512BW check (which was clearly missing). Signed-off-by: Jan Beulich --- v2: Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -167,6 +167,11 @@ static bool simd_check_avx512vbmi_vl(voi return cpu_has_avx512_vbmi && cpu_has_avx512vl; } +static bool simd_check_avx512vbmi2(void) +{ + return cpu_has_avx512_vbmi2; +} + static bool simd_check_sse4_sha(void) { return cpu_has_sha && cpu_has_sse4_2; @@ -179,7 +184,7 @@ static bool simd_check_avx_sha(void) static bool simd_check_avx512f_sha_vl(void) { - return cpu_has_sha && cpu_has_avx512vl; + return cpu_has_sha && simd_check_avx512f_vl(); } static bool simd_check_avx2_vaes(void) @@ -189,13 +194,13 @@ static bool simd_check_avx2_vaes(void) static bool simd_check_avx512bw_vaes(void) { - return cpu_has_aesni && cpu_has_vaes && cpu_has_avx512bw; + return cpu_has_aesni && cpu_has_vaes && simd_check_avx512bw(); } static bool simd_check_avx512bw_vaes_vl(void) { return cpu_has_aesni && cpu_has_vaes && - cpu_has_avx512bw && cpu_has_avx512vl; + simd_check_avx512bw_vl(); } static bool simd_check_avx2_vpclmulqdq(void) @@ -205,22 +210,22 @@ static bool simd_check_avx2_vpclmulqdq(v static bool simd_check_avx512bw_vpclmulqdq(void) { - return cpu_has_vpclmulqdq && cpu_has_avx512bw; + return cpu_has_vpclmulqdq && simd_check_avx512bw(); } static bool simd_check_avx512bw_vpclmulqdq_vl(void) { - return cpu_has_vpclmulqdq && cpu_has_avx512bw && cpu_has_avx512vl; + return cpu_has_vpclmulqdq && simd_check_avx512bw_vl(); } static bool simd_check_avx512vbmi2_vpclmulqdq(void) { - return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq(); + return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq(); } static bool simd_check_avx512vbmi2_vpclmulqdq_vl(void) { - return cpu_has_avx512_vbmi2 && simd_check_avx512bw_vpclmulqdq_vl(); + return simd_check_avx512vbmi2() && simd_check_avx512bw_vpclmulqdq_vl(); } static bool simd_check_sse2_gf(void) @@ -235,12 +240,17 @@ static bool simd_check_avx2_gf(void) static bool simd_check_avx512bw_gf(void) { - return cpu_has_gfni && cpu_has_avx512bw; + return cpu_has_gfni && simd_check_avx512bw(); } static bool simd_check_avx512bw_gf_vl(void) { - return cpu_has_gfni && cpu_has_avx512vl; + return cpu_has_gfni && simd_check_avx512bw_vl(); +} + +static bool simd_check_avx512vnni(void) +{ + return cpu_has_avx512_vnni; } static bool simd_check_avx512fp16(void) @@ -3192,7 +3202,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovq %xmm1,32(%edx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_mem); @@ -3216,7 +3226,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovq 32(%edx),%xmm0..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_from_mem); @@ -3339,7 +3349,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovdqu32 %zmm2,(%ecx){%k1}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovdqu32_to_mem); @@ -3369,7 +3379,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovdqu32 64(%edx),%zmm2{%k2}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovdqu32_from_mem); @@ -3394,7 +3404,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovdqu16 %zmm3,(%ecx){%k1}..."); - if ( stack_exec && cpu_has_avx512bw ) + if ( stack_exec && simd_check_avx512bw() ) { decl_insn(vmovdqu16_to_mem); @@ -3426,7 +3436,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovdqu16 64(%edx),%zmm3{%k2}..."); - if ( stack_exec && cpu_has_avx512bw ) + if ( stack_exec && simd_check_avx512bw() ) { decl_insn(vmovdqu16_from_mem); @@ -3554,7 +3564,7 @@ int main(int argc, char **argv) printf("%-40s", "Testing vmovsd %xmm5,16(%ecx){%k3}..."); memset(res, 0x88, 128); memset(res + 20, 0x77, 8); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovsd_masked_to_mem); @@ -3589,7 +3599,7 @@ int main(int argc, char **argv) } printf("%-40s", "Testing vmovaps (%edx),%zmm7{%k3}{z}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vmovaps_masked_from_mem); @@ -3772,7 +3782,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovd %xmm3,32(%ecx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_to_mem); @@ -3797,7 +3807,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovd 32(%ecx),%xmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_from_mem); @@ -3987,7 +3997,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovd %xmm2,%ebx..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_to_reg); @@ -4013,7 +4023,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovd %ebx,%xmm1..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovd_from_reg); @@ -4115,7 +4125,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing {evex} vmovq %xmm11,32(%ecx)..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_mem2); @@ -4205,7 +4215,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovq %xmm22,%rbx..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovq_to_reg); @@ -4398,7 +4408,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovntdqa 64(%ecx),%zmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vmovntdqa); @@ -4994,7 +5004,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vcvtph2ps 32(%ecx),%zmm7{%k4}..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(evex_vcvtph2ps); decl_insn(evex_vcvtps2ph); @@ -5037,7 +5047,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vfixupimmpd $0,8(%edx){1to8},%zmm3,%zmm4..."); - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vfixupimmpd); static const struct { @@ -5076,7 +5086,7 @@ int main(int argc, char **argv) printf("%-40s", "Testing vfpclasspsz $0x46,64(%edx),%k2..."); - if ( stack_exec && cpu_has_avx512dq ) + if ( stack_exec && simd_check_avx512dq() ) { decl_insn(vfpclassps); @@ -5108,7 +5118,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vfpclassphz $0x46,128(%ecx),%k3..."); - if ( stack_exec && cpu_has_avx512_fp16 ) + if ( stack_exec && simd_check_avx512fp16() ) { decl_insn(vfpclassph); @@ -5151,7 +5161,7 @@ int main(int argc, char **argv) * on the mapping boundaries) that elements controlled by clear mask * bits don't get accessed. */ - if ( stack_exec && cpu_has_avx512f ) + if ( stack_exec && simd_check_avx512f() ) { decl_insn(vpcompressd); decl_insn(vpcompressq); @@ -5253,7 +5263,7 @@ int main(int argc, char **argv) } #if __GNUC__ > 7 /* can't check for __AVX512VBMI2__ here */ - if ( stack_exec && cpu_has_avx512_vbmi2 ) + if ( stack_exec && simd_check_avx512vbmi2() ) { decl_insn(vpcompressb); decl_insn(vpcompressw); @@ -5441,7 +5451,7 @@ int main(int argc, char **argv) } printf("%-40s", "Testing vpdpwssd (%ecx),%{y,z}mmA,%{y,z}mmB..."); - if ( stack_exec && cpu_has_avx512_vnni && cpu_has_avx_vnni ) + if ( stack_exec && simd_check_avx512vnni() && cpu_has_avx_vnni ) { /* Do the same operation two ways and compare the results. */ decl_insn(vpdpwssd_vex1); @@ -5496,7 +5506,7 @@ int main(int argc, char **argv) printf("skipped\n"); printf("%-40s", "Testing vmovsh 8(%ecx),%xmm5..."); - if ( stack_exec && cpu_has_avx512_fp16 ) + if ( stack_exec && simd_check_avx512fp16() ) { decl_insn(vmovsh_from_mem); decl_insn(vmovw_to_gpr); From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:04:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:04:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277722.1562852 (Exim 4.92) (envelope-from ) id 1wAqvw-00013V-BZ; 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Thu, 09 Apr 2026 08:04:38 -0700 (PDT) Message-ID: <36d9ab74-a7e0-4ec3-ae3e-4c9cae6982e5@suse.com> Date: Thu, 9 Apr 2026 17:04:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 05/16] x86emul/test: drop cpu_has_avx512vl From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775747078-ADB3FCD1-543089F8/0/0 X-purgate-type: clean X-purgate-size: 2885 AVX512VL not being a standalone feature anyway, but always needing to be combined with some other AVX512*, replace uses of cpu_has_avx512vl by just the feature bit check. Signed-off-by: Jan Beulich --- v2: Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -1025,7 +1025,8 @@ static void test_group(const struct test { for ( j = 0; j < nr_vl; ++j ) { - if ( vl[0] == VL_512 && vl[j] != VL_512 && !cpu_has_avx512vl ) + if ( vl[0] == VL_512 && vl[j] != VL_512 && + !cpu_policy.feat.avx512vl ) continue; switch ( tests[i].esz ) --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -131,7 +131,7 @@ static bool simd_check_avx512f(void) static bool simd_check_avx512f_vl(void) { - return cpu_has_avx512f && cpu_has_avx512vl; + return cpu_has_avx512f && cpu_policy.feat.avx512vl; } #define simd_check_avx512vl_sg simd_check_avx512f_vl @@ -143,7 +143,7 @@ static bool simd_check_avx512dq(void) static bool simd_check_avx512dq_vl(void) { - return cpu_has_avx512dq && cpu_has_avx512vl; + return cpu_has_avx512dq && cpu_policy.feat.avx512vl; } static bool simd_check_avx512bw(void) @@ -154,7 +154,7 @@ static bool simd_check_avx512bw(void) static bool simd_check_avx512bw_vl(void) { - return cpu_has_avx512bw && cpu_has_avx512vl; + return cpu_has_avx512bw && cpu_policy.feat.avx512vl; } static bool simd_check_avx512vbmi(void) @@ -164,7 +164,7 @@ static bool simd_check_avx512vbmi(void) static bool simd_check_avx512vbmi_vl(void) { - return cpu_has_avx512_vbmi && cpu_has_avx512vl; + return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl; } static bool simd_check_avx512vbmi2(void) @@ -260,7 +260,7 @@ static bool simd_check_avx512fp16(void) static bool simd_check_avx512fp16_vl(void) { - return cpu_has_avx512_fp16 && cpu_has_avx512vl; + return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl; } static void simd_set_regs(struct cpu_user_regs *regs) --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -179,8 +179,6 @@ void wrpkru(unsigned int val); #define cpu_has_sha cpu_policy.feat.sha #define cpu_has_avx512bw (cpu_policy.feat.avx512bw && \ xcr0_mask(0xe6)) -#define cpu_has_avx512vl (cpu_policy.feat.avx512vl && \ - xcr0_mask(0xe6)) #define cpu_has_avx512_vbmi (cpu_policy.feat.avx512_vbmi && \ xcr0_mask(0xe6)) #define cpu_has_avx512_vbmi2 (cpu_policy.feat.avx512_vbmi2 && \ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:05:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:05:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277730.1562861 (Exim 4.92) (envelope-from ) id 1wAqwO-0001an-JP; Thu, 09 Apr 2026 15:05:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277730.1562861; Thu, 09 Apr 2026 15:05:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqwO-0001ag-Fx; Thu, 09 Apr 2026 15:05:08 +0000 Received: by outflank-mailman (input) for mailman id 1277730; Thu, 09 Apr 2026 15:05:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqwN-0001aR-GZ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:05:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAqwM-00EC7x-SZ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:05:06 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7c018-5cb7-0a2a0a5109dd-0a2a450cae3a-42 for ; Thu, 09 Apr 2026 17:05:06 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7c022-f40c-0a2a450c0019-d1558030d92c-3 for ; Thu, 09 Apr 2026 17:05:06 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso9552155e9.3 for ; Thu, 09 Apr 2026 08:05:06 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 08:05:06 -0700 (PDT) Message-ID: <34db5d46-87cf-4449-900e-5b9e6965a52b@suse.com> Date: Thu, 9 Apr 2026 17:05:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 06/16] x86emul: AVX10.1 testing From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775747106-FE151A3D-94C8CACE/0/0 X-purgate-type: clean X-purgate-size: 11728 Re-use respective AVX512 tests, by suitably adjusting the predicate functions. This leaves test names ("Testing ... NN-bit code sequence") somewhat misleading, but I think we can live with that. Note that the AVX512{BW,DQ} opmask tests cannot be run as-is for the AVX10/256 case, as they include 512-bit vector <-> opmask insn tests. Signed-off-by: Jan Beulich --- SDE: -gnr / -gnr256 --- TBD: The testcase.mk change was for AVX10.1/256. It may, however, be worthwhile to keep it. TBD: May want to have separate AVX10 test blobs built, utilizing all of the implied AVX512 sub-features. The AVX512{BW,DQ} opmask tests could of course be cloned (i.e. rebuilt another time with -mavx512vl passed) accordingly, but the coverage gain would be pretty marginal. --- v4: Drop use of vsz fields. Series re-ordering adjustments. Drop stale Phi leftovers. Re-base. v2: Drop SDE 9.27.0 workaround. Re-base over dropping of Xeon Phi support. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -1026,7 +1026,7 @@ static void test_group(const struct test for ( j = 0; j < nr_vl; ++j ) { if ( vl[0] == VL_512 && vl[j] != VL_512 && - !cpu_policy.feat.avx512vl ) + !cpu_policy.feat.avx512vl && !cpu_policy.feat.avx10 ) continue; switch ( tests[i].esz ) @@ -1077,6 +1077,24 @@ static void test_group(const struct test } } +/* AVX512 (sub)features implied by AVX10. */ +#define avx10_has_avx512f cpu_has_avx10 +#define avx10_has_avx512bw cpu_has_avx10 +#define avx10_has_avx512cd cpu_has_avx10 +#define avx10_has_avx512dq cpu_has_avx10 +#define avx10_has_avx512_bf16 cpu_has_avx10 +#define avx10_has_avx512_bitalg cpu_has_avx10 +#define avx10_has_avx512_fp16 cpu_has_avx10 +#define avx10_has_avx512_ifma cpu_has_avx10 +#define avx10_has_avx512_vbmi cpu_has_avx10 +#define avx10_has_avx512_vbmi2 cpu_has_avx10 +#define avx10_has_avx512_vnni cpu_has_avx10 +#define avx10_has_avx512_vpopcntdq cpu_has_avx10 + +/* AVX512 sub-feature(s) /not/ implied by AVX10. */ +#define avx10_has_avx512_vp2intersect false +#define avx10_has_avx512_bmm false + void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt, const struct x86_emulate_ops *ops) { @@ -1094,7 +1112,7 @@ void evex_disp8_test(void *instr, struct } \ } while ( false ) -#define RUN(feat, vl) run(cpu_has_ ## feat, feat, vl) +#define RUN(feat, vl) run(cpu_has_ ## feat || avx10_has_ ## feat, feat, vl) RUN(avx512f, all); RUN(avx512f, 128); @@ -1120,11 +1138,15 @@ void evex_disp8_test(void *instr, struct RUN(avx512_bmm, all); RUN(avx512_bmm, no128); - if ( cpu_has_avx512f ) +#undef RUN + + if ( cpu_has_avx512f || cpu_has_avx10 ) { +#define RUN(feat, vl) run(cpu_has_ ## feat, feat, vl) RUN(gfni, all); RUN(vaes, all); RUN(vpclmulqdq, all); +#undef RUN } if ( cpu_has_avx10 ) --- a/tools/tests/x86_emulator/testcase.mk +++ b/tools/tests/x86_emulator/testcase.mk @@ -7,6 +7,22 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDD CFLAGS += -ffreestanding -nostdinc -I$(XEN_ROOT)/tools/firmware/include CFLAGS += -fno-stack-protector -g0 $($(TESTCASE)-cflags) +ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),) + +cflags-vsz64 := +cflags-vsz32 := -mprefer-vector-width=256 +cflags-vsz16 := -mprefer-vector-width=128 +# Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only) +cflags-vsz := -mprefer-vector-width=128 + +ifneq ($(filter -DVEC_SIZE=%,$($(TESTCASE)-cflags)),) +CFLAGS += $(cflags-vsz$(patsubst -DVEC_SIZE=%,%,$(filter -DVEC_SIZE=%,$($(TESTCASE)-cflags)))) +else +CFLAGS += $(cflags-vsz$(patsubst -DVEC_MAX=%,%,$(filter -DVEC_MAX=%,$($(TESTCASE)-cflags)))) +endif + +endif + LDFLAGS_DIRECT += $(shell { $(LD) -v --warn-rwx-segments; } >/dev/null 2>&1 && echo --no-warn-rwx-segments) .PHONY: all --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -124,52 +124,56 @@ static bool simd_check_avx_pclmul(void) static bool simd_check_avx512f(void) { - return cpu_has_avx512f; + return cpu_has_avx512f || cpu_has_avx10; } #define simd_check_avx512f_opmask simd_check_avx512f #define simd_check_avx512f_sg simd_check_avx512f static bool simd_check_avx512f_vl(void) { - return cpu_has_avx512f && cpu_policy.feat.avx512vl; + return (cpu_has_avx512f && cpu_policy.feat.avx512vl) || + cpu_has_avx10; } #define simd_check_avx512vl_sg simd_check_avx512f_vl static bool simd_check_avx512dq(void) { - return cpu_has_avx512dq; + return cpu_has_avx512dq || cpu_has_avx10; } #define simd_check_avx512dq_opmask simd_check_avx512dq static bool simd_check_avx512dq_vl(void) { - return cpu_has_avx512dq && cpu_policy.feat.avx512vl; + return (cpu_has_avx512dq && cpu_policy.feat.avx512vl) || + cpu_has_avx10; } static bool simd_check_avx512bw(void) { - return cpu_has_avx512bw; + return cpu_has_avx512bw || cpu_has_avx10; } #define simd_check_avx512bw_opmask simd_check_avx512bw static bool simd_check_avx512bw_vl(void) { - return cpu_has_avx512bw && cpu_policy.feat.avx512vl; + return (cpu_has_avx512bw && cpu_policy.feat.avx512vl) || + cpu_has_avx10; } static bool simd_check_avx512vbmi(void) { - return cpu_has_avx512_vbmi; + return cpu_has_avx512_vbmi || cpu_has_avx10; } static bool simd_check_avx512vbmi_vl(void) { - return cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl; + return (cpu_has_avx512_vbmi && cpu_policy.feat.avx512vl) || + cpu_has_avx10; } static bool simd_check_avx512vbmi2(void) { - return cpu_has_avx512_vbmi2; + return cpu_has_avx512_vbmi2 || cpu_has_avx10; } static bool simd_check_sse4_sha(void) @@ -250,17 +254,18 @@ static bool simd_check_avx512bw_gf_vl(vo static bool simd_check_avx512vnni(void) { - return cpu_has_avx512_vnni; + return cpu_has_avx512_vnni || cpu_has_avx10; } static bool simd_check_avx512fp16(void) { - return cpu_has_avx512_fp16; + return cpu_has_avx512_fp16 || cpu_has_avx10; } static bool simd_check_avx512fp16_vl(void) { - return cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl; + return (cpu_has_avx512_fp16 && cpu_policy.feat.avx512vl) || + cpu_has_avx10; } static void simd_set_regs(struct cpu_user_regs *regs) @@ -3238,11 +3243,22 @@ int main(int argc, char **argv) rc = x86_emulate(&ctxt, &emulops); if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovq_from_mem) ) goto fail; - asm ( "vmovq %1, %%xmm1\n\t" - "vpcmpeqq %%zmm0, %%zmm1, %%k0\n" - "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); - if ( rc != 0xff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovq %1, %%xmm1\n\t" + "vpcmpeqq %%zmm0, %%zmm1, %%k0\n" + "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0x00ff ) + goto fail; + } + else + { + asm ( "vmovq %1, %%xmm1\n\t" + "vpcmpeqq %%xmm0, %%xmm1, %%k0\n" + "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0x03 ) + goto fail; + } printf("okay\n"); } else @@ -3820,11 +3836,22 @@ int main(int argc, char **argv) rc = x86_emulate(&ctxt, &emulops); if ( rc != X86EMUL_OKAY || !check_eip(evex_vmovd_from_mem) ) goto fail; - asm ( "vmovd %1, %%xmm0\n\t" - "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t" - "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); - if ( rc != 0xffff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%zmm4, %%zmm0, %%k0\n\t" + "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0xffff ) + goto fail; + } + else + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%xmm4, %%xmm0, %%k0\n\t" + "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0x0f ) + goto fail; + } printf("okay\n"); } else @@ -4037,11 +4064,22 @@ int main(int argc, char **argv) rc = x86_emulate(&ctxt, &emulops); if ( (rc != X86EMUL_OKAY) || !check_eip(evex_vmovd_from_reg) ) goto fail; - asm ( "vmovd %1, %%xmm0\n\t" - "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t" - "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); - if ( rc != 0xffff ) - goto fail; + if ( simd_check_avx512f() ) + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%zmm1, %%zmm0, %%k0\n\t" + "kmovw %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0xffff ) + goto fail; + } + else + { + asm ( "vmovd %1, %%xmm0\n\t" + "vpcmpeqd %%xmm1, %%xmm0, %%k0\n\t" + "kmovb %%k0, %0" : "=r" (rc) : "m" (res[8]) ); + if ( rc != 0x0f ) + goto fail; + } printf("okay\n"); } else @@ -5524,14 +5562,28 @@ int main(int argc, char **argv) rc = x86_emulate(&ctxt, &emulops); if ( (rc != X86EMUL_OKAY) || !check_eip(vmovsh_from_mem) ) goto fail; - asm volatile ( "kmovw %2, %%k1\n\t" - "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t" - "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t" - "kmovw %%k0, %0" - : "=g" (rc) - : "m" (res[2]), "r" (1) ); - if ( rc != 0xffff ) - goto fail; + if ( simd_check_avx512fp16() ) + { + asm volatile ( "kmovw %2, %%k1\n\t" + "vmovdqu16 %1, %%zmm4%{%%k1%}%{z%}\n\t" + "vpcmpeqw %%zmm4, %%zmm5, %%k0\n\t" + "kmovw %%k0, %0" + : "=g" (rc) + : "m" (res[2]), "r" (1) ); + if ( rc != 0xffff ) + goto fail; + } + else + { + asm volatile ( "kmovb %2, %%k1\n\t" + "vmovdqu16 %1, %%xmm4%{%%k1%}%{z%}\n\t" + "vpcmpeqw %%xmm4, %%xmm5, %%k0\n\t" + "kmovb %%k0, %0" + : "=g" (rc) + : "m" (res[2]), "r" (1) ); + if ( rc != 0xff ) + goto fail; + } printf("okay\n"); printf("%-40s", "Testing vmovsh %xmm4,2(%eax){%k3}..."); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -244,7 +244,7 @@ int emul_test_get_fpu( break; case X86EMUL_FPU_opmask: case X86EMUL_FPU_zmm: - if ( cpu_has_avx512f ) + if ( cpu_has_avx512f || cpu_has_avx10 ) break; default: return X86EMUL_UNHANDLEABLE; From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:05:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:05:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277745.1562870 (Exim 4.92) (envelope-from ) id 1wAqwz-0002B3-0q; Thu, 09 Apr 2026 15:05:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277745.1562870; Thu, 09 Apr 2026 15:05:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqwy-0002Aw-Sp; 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Thu, 09 Apr 2026 08:05:41 -0700 (PDT) Message-ID: <26722cdf-707c-486f-93a2-fbfd9d63082e@suse.com> Date: Thu, 9 Apr 2026 17:05:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 07/16] x86emul/test: engage AVX512VL via command line option From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1775747142-B5AED185-EDD14F4A/0/0 X-purgate-type: clean X-purgate-size: 1482 Now that we have machinery in testcase.mk to set vector length dependent flags for AVX512 tests, let's avoid using a pragma to enable AVX512VL insns for the compiler. This way, correct settings are in place from the very beginning of compilation. No change to the generated test blobs, and hence no functional change. Signed-off-by: Jan Beulich --- a/tools/tests/x86_emulator/simd.h +++ b/tools/tests/x86_emulator/simd.h @@ -215,10 +215,6 @@ DECL_OCTET(half); # define __builtin_ia32_shuf_i32x4_512_mask __builtin_ia32_shuf_i32x4_mask # define __builtin_ia32_shuf_i64x2_512_mask __builtin_ia32_shuf_i64x2_mask -# if VEC_SIZE > ELEM_SIZE && (defined(VEC_MAX) ? VEC_MAX : VEC_SIZE) < 64 -# pragma GCC target ( "avx512vl" ) -# endif - # define REN(insn, old, new) \ asm ( ".macro v" #insn #old " o:vararg \n\t" \ "v" #insn #new " \\o \n\t" \ --- a/tools/tests/x86_emulator/testcase.mk +++ b/tools/tests/x86_emulator/testcase.mk @@ -10,8 +10,8 @@ CFLAGS += -fno-stack-protector -g0 $($(T ifneq ($(filter -mavx512%,$($(TESTCASE)-cflags)),) cflags-vsz64 := -cflags-vsz32 := -mprefer-vector-width=256 -cflags-vsz16 := -mprefer-vector-width=128 +cflags-vsz32 := -mavx512vl -mprefer-vector-width=256 +cflags-vsz16 := -mavx512vl -mprefer-vector-width=128 # Scalar tests don't set VEC_SIZE (and VEC_MAX is used by S/G ones only) cflags-vsz := -mprefer-vector-width=128 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:06:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:06:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277753.1562878 (Exim 4.92) (envelope-from ) id 1wAqxT-0002fA-6y; Thu, 09 Apr 2026 15:06:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277753.1562878; Thu, 09 Apr 2026 15:06:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqxT-0002f3-4C; Thu, 09 Apr 2026 15:06:15 +0000 Received: by outflank-mailman (input) for mailman id 1277753; Thu, 09 Apr 2026 15:06:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqxR-0002eT-6N for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:06:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAqxQ-009EAb-IZ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:06:12 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7c05b-e002-0a2a0a5209dd-0a2a45078f46-12 for ; Thu, 09 Apr 2026 17:06:12 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7c064-ba2d-0a2a45070019-d1558029e56b-3 for ; Thu, 09 Apr 2026 17:06:12 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso10677475e9.1 for ; Thu, 09 Apr 2026 08:06:12 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 08:06:11 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:06:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 08/16] x86/CPUID: enable AVX10.2 sub-leaf From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775747172-1294941E-AC730DAA/0/0 X-purgate-type: clean X-purgate-size: 5324 The logic is modeled as closely as possible after that of leaf 7 sub-leaf handling. Signed-off-by: Jan Beulich --- While the "AVX10" infix is necessary everywhere, the "avx10" prefix on the bitfield name is redundant with the containing structure's field name (see "x86emul: support AVX10.2 media insns" for how this looks like in actual use). Do we want to special-case this in gen-cpuid.py? --- v4: New. --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -343,6 +343,7 @@ int libxl_cpuid_parse_config(libxl_cpuid MSR_ENTRY(0x10a, CPUID_REG_EAX), MSR_ENTRY(0x10a, CPUID_REG_EDX), CPUID_ENTRY(0x80000021, NA, CPUID_REG_ECX), + CPUID_ENTRY(0x00000024, 1, CPUID_REG_ECX), #undef MSR_ENTRY #undef CPUID_ENTRY }; --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -38,6 +38,7 @@ static const struct { { "MSR_ARCH_CAPS.lo", "m10Al" }, { "MSR_ARCH_CAPS.hi", "m10Ah" }, { "CPUID 0x80000021.ecx", "e21c" }, + { "CPUID 0x00000024:1.ecx", "24c1" }, }; #define COL_ALIGN "24" --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -547,6 +547,17 @@ void identify_cpu(struct cpuinfo_x86 *c) &c->x86_capability[FEATURESET_Da1], &tmp, &tmp, &tmp); + if (cpu_has(c, X86_FEATURE_AVX10) && c->cpuid_level >= 0x24) { + uint32_t max_subleaf; + + cpuid_count(0x24, 0, &max_subleaf, &tmp, &tmp, &tmp); + if (max_subleaf >= 1) + cpuid_count(0x24, 1, + &tmp, &tmp, + &c->x86_capability[FEATURESET_24c1], + &tmp); + } + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) { val = rdmsr(MSR_ARCH_CAPABILITIES); c->x86_capability[FEATURESET_m10Al] = val; --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -277,6 +277,9 @@ static void recalculate_misc(struct cpu_ p->avx10.raw[0].b &= 0x000700ff; p->avx10.raw[0].c = 0; p->avx10.raw[0].d = 0; + p->avx10.raw[1].a = 0; + p->avx10.raw[1].b = 0; + p->avx10.raw[1].d = 0; if ( !p->feat.avx10 || !p->avx10.version || !p->avx10.vsz512 || !p->avx10.vsz256 || !p->avx10.vsz128 ) { --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -409,6 +409,9 @@ XEN_CPUFEATURE(ITS_NO, 16*32 XEN_CPUFEATURE(TSA_SQ_NO, 18*32+ 1) /*A No Store Queue Transitive Scheduler Attacks */ XEN_CPUFEATURE(TSA_L1_NO, 18*32+ 2) /*A No L1D Transitive Scheduler Attacks */ +/* Intel-defined CPU features, CPUID level 0x00000024:1.ecx, word 19 */ +XEN_CPUFEATURE(AVX10_V1_AUX, 19*32+ 2) /* AVX10 V1 Auxiliary Instructions */ + #endif /* XEN_CPUFEATURE */ /* Clean up from a default include. Close the enum (for C). */ --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -23,6 +23,7 @@ #define FEATURESET_m10Al 16 /* 0x0000010a.eax */ #define FEATURESET_m10Ah 17 /* 0x0000010a.edx */ #define FEATURESET_e21c 18 /* 0x80000021.ecx */ +#define FEATURESET_24c1 19 /* 0x00000024:1.ecx */ struct cpuid_leaf { @@ -64,7 +65,7 @@ const char *x86_cpuid_vendor_to_str(unsi #define CPUID_GUEST_NR_FEAT (2u + 1) #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) -#define CPUID_GUEST_NR_AVX10 (0u + 1) +#define CPUID_GUEST_NR_AVX10 (1u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ @@ -275,6 +276,14 @@ struct cpu_policy bool vsz128:1, vsz256:1, vsz512:1; uint32_t :13; uint32_t /* c */:32, /* d */:32; + + /* Subleaf 1. */ + uint32_t /* a */:32, /* b */:32; + union { + uint32_t _24c1; + struct { DECL_BITFIELD(24c1); }; + }; + uint32_t /* d */:32; }; } avx10; --- a/xen/arch/x86/lib/cpu-policy/cpuid.c +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c @@ -82,6 +82,7 @@ void x86_cpu_policy_to_featureset( fs[FEATURESET_m10Al] = p->arch_caps.lo; fs[FEATURESET_m10Ah] = p->arch_caps.hi; fs[FEATURESET_e21c] = p->extd.e21c; + fs[FEATURESET_24c1] = p->avx10._24c1; } void x86_cpu_featureset_to_policy( @@ -106,6 +107,7 @@ void x86_cpu_featureset_to_policy( p->arch_caps.lo = fs[FEATURESET_m10Al]; p->arch_caps.hi = fs[FEATURESET_m10Ah]; p->extd.e21c = fs[FEATURESET_e21c]; + p->avx10._24c1 = fs[FEATURESET_24c1]; } void x86_cpu_policy_recalc_synth(struct cpu_policy *p) --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -310,6 +310,9 @@ def crunch_numbers(state): AVX512BW: [AVX512_VBMI, AVX512_VBMI2, AVX512_BITALG, AVX512_BF16, AVX512_FP16, AVX512_BMM], + # AVX10 discrete features. + AVX10: [AVX10_V1_AUX], + # Extensions with VEX/EVEX encodings keyed to a separate feature # flag are made dependents of their respective legacy feature. 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Thu, 09 Apr 2026 08:06:41 -0700 (PDT) Message-ID: <71f97a53-2acc-4c4f-811a-ffc9056cfe12@suse.com> Date: Thu, 9 Apr 2026 17:06:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 09/16] x86emul: support AVX10.2 scalar compare insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775747202-5E32F3D8-E46BD14F/0/0 X-purgate-type: clean X-purgate-size: 7442 Simply clone code from their V{,U}COMIS{S,D,H} counterparts. While there drop a redundant EVEX.W check from V{,U}COMISH handling. Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Update encodings to latest spec version. Series re-ordering adjustments. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -81,6 +81,7 @@ enum esz { ESZ_w, ESZ_bw, ESZ_fp16, +#define ESZ_bf16 ESZ_fp16 }; #ifndef __i386__ @@ -720,6 +721,14 @@ static const struct test vpclmulqdq_all[ INSN(pclmulqdq, 66, 0f3a, 44, vl, q_nb, vl) }; +static const struct test avx10_2_all[] = { + INSN(comisbf16, 66, map5, 2f, el, bf16, el), + INSN_SFP(comx, 0f, 2f), + INSN(comxsh, f3, map5, 2f, el, fp16, el), + INSN_SFP(ucomx, 0f, 2e), + INSN(ucomxsh, f3, map5, 2e, el, fp16, el), +}; + static const struct test movrs_all[] = { INSN(movrsb, f2, map5, 6f, vl, b, vl), INSN(movrsd, f3, map5, 6f, vl, d_nb, vl), @@ -1154,4 +1163,6 @@ void evex_disp8_test(void *instr, struct run(ctxt->addr_size == 64 && cpu_has_movrs, movrs, all); run(cpu_has_sm4, sm4, all); } + + run(cpu_has_avx10_2, avx10_2, all); } --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1682,8 +1682,12 @@ static const struct evex { { { 0x2d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvtsd2si */ { { 0x2e }, 2, T, R, pfx_no, W0, LIG }, /* vucomiss */ { { 0x2e }, 2, T, R, pfx_66, W1, LIG }, /* vucomisd */ + { { 0x2e }, 2, T, R, pfx_f2, W1, LIG }, /* vucomxsd */ + { { 0x2e }, 2, T, R, pfx_f3, W0, LIG }, /* vucomxss */ { { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomiss */ { { 0x2f }, 2, T, R, pfx_66, W1, LIG }, /* vcomisd */ + { { 0x2f }, 2, T, R, pfx_f2, W1, LIG }, /* vcomxsd */ + { { 0x2f }, 2, T, R, pfx_f3, W0, LIG }, /* vcomxss */ { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtps */ { { 0x51 }, 2, T, R, pfx_66, W1, Ln }, /* vsqrtpd */ { { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtss */ @@ -2102,7 +2106,10 @@ static const struct evex { { { 0x2c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2si */ { { 0x2d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsh2si */ { { 0x2e }, 2, T, R, pfx_no, W0, LIG }, /* vucomish */ + { { 0x2e }, 2, T, R, pfx_f3, W0, LIG }, /* vucomxsh */ { { 0x2f }, 2, T, R, pfx_no, W0, LIG }, /* vcomish */ + { { 0x2f }, 2, T, R, pfx_66, W0, LIG }, /* vcomisbf16 */ + { { 0x2f }, 2, T, R, pfx_f3, W0, LIG }, /* vcomxsh */ { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtph */ { { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtsh */ { { 0x58 }, 2, T, R, pfx_no, W0, Ln }, /* vaddph */ --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -215,6 +215,8 @@ void wrpkru(unsigned int val); #define cpu_has_avx_vnni_int16 (cpu_policy.feat.avx_vnni_int16 && \ xcr0_mask(6)) #define cpu_has_avx10 (cpu_policy.feat.avx10 && xcr0_mask(0xe6)) +#define cpu_has_avx10_2 (cpu_policy.avx10.version >= 2 && \ + xcr0_mask(0xe6)) #define cpu_has_xgetbv1 (cpu_has_xsave && cpu_policy.xstate.xgetbv1) --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -1515,9 +1515,8 @@ int x86emul_decode(struct x86_emulate_st s->fp16 = true; break; - case 0x2e: case 0x2f: /* v{,u}comish */ - if ( !s->evex.pfx ) - s->fp16 = true; + case 0x2e: case 0x2f: /* v{,u}com{i,x}sh, vcomisbf16 */ + s->fp16 = true; s->simd_size = simd_none; break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -318,7 +318,7 @@ struct x86_emulate_state { bool lock_prefix; bool not_64bit; /* Instruction not available in 64bit. */ bool fpu_ctrl; /* Instruction is an FPU control one. */ - bool fp16; /* Instruction has half-precision FP source operand. */ + bool fp16; /* Instruction has half-precision FP or BF16 source. */ opcode_desc_t desc; union vex vex; union evex evex; @@ -609,10 +609,10 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni_int16() (ctxt->cpuid->feat.avx_vnni_int16) #define vcpu_has_user_msr() (ctxt->cpuid->feat.user_msr) -#define vcpu_has_avx10() (ctxt->cpuid->feat.avx10) +#define vcpu_has_avx10(minor) (ctxt->cpuid->avx10.version >= (minor)) -#define vcpu_must_have(feat) \ - generate_exception_if(!vcpu_has_##feat(), X86_EXC_UD) +#define vcpu_must_have(feat, ...) \ + generate_exception_if(!vcpu_has_##feat(__VA_ARGS__), X86_EXC_UD) #ifdef __XEN__ /* --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -3825,7 +3825,6 @@ x86_emulate( case X86EMUL_OPC_EVEX(5, 0x2e): /* vucomish xmm/m16,xmm */ case X86EMUL_OPC_EVEX(5, 0x2f): /* vcomish xmm/m16,xmm */ visa_check(_fp16); - generate_exception_if(evex.w, X86_EXC_UD); /* fall through */ CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2e): /* vucomis{s,d} xmm/mem,xmm */ CASE_SIMD_PACKED_FP(_EVEX, 0x0f, 0x2f): /* vcomis{s,d} xmm/mem,xmm */ @@ -3834,6 +3833,7 @@ x86_emulate( evex.w != evex.pfx), X86_EXC_UD); visa_check(f); + vcomi_evex: if ( !evex.brs ) avx512_vlen_check(true); get_fpu(X86EMUL_FPU_zmm); @@ -3842,6 +3842,17 @@ x86_emulate( op_bytes = 2 << (!state->fp16 + evex.w); goto vcomi; + CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2e): /* vucomxs{s,d} xmm/mem,xmm */ + CASE_SIMD_SCALAR_FP(_EVEX, 0x0f, 0x2f): /* vcomxs{s,d} xmm/mem,xmm */ + case X86EMUL_OPC_EVEX_F3(5, 0x2e): /* vucomxsh xmm/m16,xmm */ + case X86EMUL_OPC_EVEX_66(5, 0x2f): /* vcomisbf16 xmm/m16,xmm */ + case X86EMUL_OPC_EVEX_F3(5, 0x2f): /* vcomxsh xmm/m16,xmm */ + generate_exception_if((evex.reg != 0xf || !evex.RX || evex.opmsk || + evex.w != (evex.pfx == vex_f2)), + X86_EXC_UD); + vcpu_must_have(avx10, 2); + goto vcomi_evex; + #endif case X86EMUL_OPC(0x0f, 0x30): /* wrmsr */ @@ -6831,7 +6842,7 @@ x86_emulate( case X86EMUL_OPC_EVEX_F3(0x0f38, 0xda): /* vsm4key4 [xyz]mm/mem,[xyz]mm,[xyz]mm */ case X86EMUL_OPC_EVEX_F2(0x0f38, 0xda): /* vsm4rnds4 [xyz]mm/mem,[xyz]mm,[xyz]mm */ - vcpu_must_have(avx10); + vcpu_must_have(avx10, 1); vcpu_must_have(sm4); generate_exception_if(evex.w || evex.brs || evex.opmsk, X86_EXC_UD); avx512_vlen_check(false); @@ -7905,7 +7916,7 @@ x86_emulate( fallthrough; case X86EMUL_OPC_EVEX_F3(5, 0x6f): /* vmovrs{d,q} mem,[xyz]mm{k} */ generate_exception_if(ea.type != OP_MEM || evex.brs, X86_EXC_UD); - vcpu_must_have(avx10); + vcpu_must_have(avx10, 1); vcpu_must_have(movrs); avx512_vlen_check(false); op_bytes = 16 << evex.lr; From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:07:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:07:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277775.1562896 (Exim 4.92) (envelope-from ) id 1wAqyX-0003jS-Rm; Thu, 09 Apr 2026 15:07:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277775.1562896; Thu, 09 Apr 2026 15:07:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAqyX-0003jL-Or; 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Thu, 09 Apr 2026 08:07:18 -0700 (PDT) Message-ID: <4aa12415-2135-4e1c-b5a0-dcc4b01f71fc@suse.com> Date: Thu, 9 Apr 2026 17:07:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 10/16] x86emul: support AVX10.2 partial copy insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; 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Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Series re-ordering adjustments. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -729,6 +729,13 @@ static const struct test avx10_2_all[] = INSN(ucomxsh, f3, map5, 2e, el, fp16, el), }; +static const struct test avx10_2_128[] = { + INSN(movd, f3, 0f, 7e, el, d, el), + INSN(movd, 66, 0f, d6, el, d, el), + INSN(movw, f3, map5, 6e, el, fp16, el), + INSN(movw, f3, map5, 7e, el, fp16, el), +}; + static const struct test movrs_all[] = { INSN(movrsb, f2, map5, 6f, vl, b, vl), INSN(movrsd, f3, map5, 6f, vl, d_nb, vl), @@ -1165,4 +1172,5 @@ void evex_disp8_test(void *instr, struct } run(cpu_has_avx10_2, avx10_2, all); + run(cpu_has_avx10_2, avx10_2, 128); } --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1782,7 +1782,7 @@ static const struct evex { { { 0x7b }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtusi2ss */ { { 0x7b }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvtusi2sd */ { { 0x7e }, 2, T, W, pfx_66, Wn, L0 }, /* vmov{d,q} */ - { { 0x7e }, 2, T, R, pfx_f3, W1, L0 }, /* vmovq */ + { { 0x7e }, 2, T, R, pfx_f3, Wn, L0 }, /* vmov{d,q} */ { { 0x7f }, 2, T, W, pfx_66, Wn, Ln }, /* vmovdqa{32,64} */ { { 0x7f }, 2, T, W, pfx_f3, Wn, Ln }, /* vmovdqu{32,64} */ { { 0x7f }, 2, T, W, pfx_f2, Wn, Ln }, /* vmovdqu{8,16} */ @@ -1799,7 +1799,7 @@ static const struct evex { { { 0xd3 }, 2, T, R, pfx_66, W1, Ln }, /* vpsrlq */ { { 0xd4 }, 2, T, R, pfx_66, W1, Ln }, /* vpaddq */ { { 0xd5 }, 2, T, R, pfx_66, WIG, Ln }, /* vpmullw */ - { { 0xd6 }, 2, T, W, pfx_66, W1, L0 }, /* vmovq */ + { { 0xd6 }, 2, T, W, pfx_66, Wn, L0 }, /* vmov{d,q} */ { { 0xd8 }, 2, T, R, pfx_66, WIG, Ln }, /* vpsubusb */ { { 0xd9 }, 2, T, R, pfx_66, WIG, Ln }, /* vpsubusw */ { { 0xda }, 2, T, R, pfx_66, WIG, Ln }, /* vpminub */ @@ -2133,6 +2133,7 @@ static const struct evex { { { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */ { { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */ { { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */ + { { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */ { { 0x6f }, 2, T, R, pfx_f3, Wn, Ln }, /* vmovrs{d,q} */ { { 0x6f }, 2, T, R, pfx_f2, Wn, Ln }, /* vmovrs{b,w} */ { { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */ @@ -2153,6 +2154,7 @@ static const struct evex { { { 0x7d }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtw2ph */ { { 0x7d }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtuwph */ { { 0x7e }, 2, T, W, pfx_66, WIG, L0 }, /* vmovw */ + { { 0x7e }, 2, T, W, pfx_f3, W0, L0 }, /* vmovw */ }, evex_map6[] = { { { 0x13 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2psx */ { { 0x13 }, 2, T, R, pfx_no, W0, LIG }, /* vcvtsh2ss */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -293,7 +293,7 @@ static const struct twobyte_table { [0xd0] = { DstImplicit|SrcMem|ModRM, simd_other }, [0xd1 ... 0xd3] = { DstImplicit|SrcMem|ModRM, simd_128, 4 }, [0xd4 ... 0xd5] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl }, - [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other, 3 }, + [0xd6] = { DstMem|SrcImplicit|ModRM|Mov, simd_other, d8s_dq }, [0xd7] = { DstReg|SrcImplicit|ModRM|Mov }, [0xd8 ... 0xdf] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl }, [0xe0] = { DstImplicit|SrcMem|ModRM, simd_packed_int, d8s_vl }, @@ -803,7 +803,7 @@ decode_twobyte(struct x86_emulate_state if ( s->vex.pfx == vex_f3 ) /* movq xmm/m64,xmm */ { case X86EMUL_OPC_VEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */ - case X86EMUL_OPC_EVEX_F3(0, 0x7e): /* vmovq xmm/m64,xmm */ + case X86EMUL_OPC_EVEX_F3(0, 0x7e): /* vmov{d,q} xmm/mem,xmm */ s->desc = DstImplicit | SrcMem | TwoOp; s->simd_size = simd_other; /* Avoid the s->desc clobbering of TwoOp below. */ @@ -1416,7 +1416,7 @@ int x86emul_decode(struct x86_emulate_st break; case 0x7e: /* vmovq xmm/m64,xmm needs special casing */ - if ( disp8scale == 2 && s->evex.pfx == vex_f3 ) + if ( disp8scale == 2 && s->evex.pfx == vex_f3 && s->evex.w ) disp8scale = 3; break; @@ -1525,13 +1525,13 @@ int x86emul_decode(struct x86_emulate_st s->fp16 = true; break; - case 0x6e: /* vmovw r/m16, xmm */ + case 0x6e: /* vmovw r/x/m16, xmm */ d = (d & ~SrcMask) | SrcMem16; /* fall through */ - case 0x7e: /* vmovw xmm, r/m16 */ + case 0x7e: /* vmovw xmm, r/x/m16 */ + s->fp16 = true; if ( s->evex.pfx == vex_66 ) - s->fp16 = true; - s->simd_size = simd_none; + s->simd_size = simd_none; break; case 0x78: case 0x79: /* vcvt{,t}ph2u{d,q}q, vcvt{,t}sh2usi */ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -4938,13 +4938,17 @@ x86_emulate( op_bytes = 8; goto simd_0f_int; - case X86EMUL_OPC_EVEX_F3(0x0f, 0x7e): /* vmovq xmm/m64,xmm */ - case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmovq xmm,xmm/m64 */ - generate_exception_if(evex.lr || !evex.w || evex.opmsk || evex.brs, - X86_EXC_UD); - visa_check(f); + case X86EMUL_OPC_EVEX_F3(0x0f, 0x7e): /* vmov{d,q} xmm/mem,xmm */ + case X86EMUL_OPC_EVEX_66(0x0f, 0xd6): /* vmov{d,q} xmm,xmm/mem */ + case X86EMUL_OPC_EVEX_F3(5, 0x6e): /* vmovw xmm/m16,xmm */ + case X86EMUL_OPC_EVEX_F3(5, 0x7e): /* vmovw xmm,xmm/m16 */ + generate_exception_if(evex.lr || evex.opmsk || evex.brs, X86_EXC_UD); + if ( evex.w ) + visa_check(f); + else + vcpu_must_have(avx10, 2); d |= TwoOp; - op_bytes = 8; + op_bytes = 2 << (!state->fp16 + evex.w); goto simd_zmm; #endif /* !X86EMUL_NO_SIMD */ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:07:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:07:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277784.1562906 (Exim 4.92) (envelope-from ) id 1wAqyt-000498-37; Thu, 09 Apr 2026 15:07:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277784.1562906; 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Thu, 09 Apr 2026 08:07:40 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:07:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 11/16] x86emul: support AVX10.2 media insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775747260-8B94141E-E5DE21AF/0/0 X-purgate-type: clean X-purgate-size: 7336 These are all very similar to various existing insns. Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- In evex-disp8.c, should we separately have avx10_v1_aux_all[]? If so, all the convert insns would also need moving/copying there. --- v4: Series re-ordering adjustments. Update to spec version 6. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -725,6 +725,20 @@ static const struct test avx10_2_all[] = INSN(comisbf16, 66, map5, 2f, el, bf16, el), INSN_SFP(comx, 0f, 2f), INSN(comxsh, f3, map5, 2f, el, fp16, el), + INSN(dpphps, , 0f38, 52, vl, d, vl), + INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl), + INSN(pdpbssd, f2, 0f38, 50, vl, d, vl), + INSN(pdpbssds, f2, 0f38, 51, vl, d, vl), + INSN(pdpbsud, f3, 0f38, 50, vl, d, vl), + INSN(pdpbsuds, f3, 0f38, 51, vl, d, vl), + INSN(pdpbuud, , 0f38, 50, vl, d, vl), + INSN(pdpbuuds, , 0f38, 51, vl, d, vl), + INSN(pdpwsud, f3, 0f38, d2, vl, d, vl), + INSN(pdpwsuds, f3, 0f38, d3, vl, d, vl), + INSN(pdpwusd, 66, 0f38, d2, vl, d, vl), + INSN(pdpwusds, 66, 0f38, d3, vl, d, vl), + INSN(pdpwuud, , 0f38, d2, vl, d, vl), + INSN(pdpwuuds, , 0f38, d3, vl, d, vl), INSN_SFP(ucomx, 0f, 2e), INSN(ucomxsh, f3, map5, 2e, el, fp16, el), }; --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1927,8 +1927,15 @@ static const struct evex { { { 0x4d }, 2, T, R, pfx_66, Wn, LIG }, /* vrcp14s{s,d} */ { { 0x4e }, 2, T, R, pfx_66, Wn, Ln }, /* vrsqrt14p{s,d} */ { { 0x4f }, 2, T, R, pfx_66, Wn, LIG }, /* vrsqrt14s{s,d} */ + { { 0x50 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuud */ { { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */ + { { 0x50 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsud */ + { { 0x50 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssd */ + { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpbuuds */ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */ + { { 0x51 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpbsuds */ + { { 0x51 }, 2, T, R, pfx_f2, W0, Ln }, /* vpdpbssds */ + { { 0x52 }, 2, T, R, pfx_no, W0, Ln }, /* vdpphps */ { { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */ { { 0x52 }, 2, T, R, pfx_f3, W0, Ln }, /* vdpbf16ps */ { { 0x52 }, 2, T, R, pfx_f2, W0, L2 }, /* vp4dpwssd */ @@ -2029,6 +2036,12 @@ static const struct evex { { { 0xcc }, 2, T, R, pfx_66, Wn, L2 }, /* vrsqrt28p{s,d} */ { { 0xcd }, 2, T, R, pfx_66, Wn, LIG }, /* vrsqrt28s{s,d} */ { { 0xcf }, 2, T, R, pfx_66, W0, Ln }, /* vgf2p8mulb */ + { { 0xd2 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuud */ + { { 0xd2 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusd */ + { { 0xd2 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsud */ + { { 0xd3 }, 2, T, R, pfx_no, W0, Ln }, /* vpdpwuuds */ + { { 0xd3 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwusds */ + { { 0xd3 }, 2, T, R, pfx_f3, W0, Ln }, /* vpdpwsuds */ { { 0xda }, 2, T, R, pfx_f3, W0, Ln }, /* vsm4key4 */ { { 0xda }, 2, T, R, pfx_f2, W0, Ln }, /* vsm4rnds4 */ { { 0xdc }, 2, T, R, pfx_66, WIG, Ln }, /* vaesenc */ @@ -2075,6 +2088,7 @@ static const struct evex { { { 0x3e }, 3, T, R, pfx_66, Wn, Ln }, /* vpcmpu{b,w} */ { { 0x3f }, 3, T, R, pfx_66, Wn, Ln }, /* vpcmp{b,w} */ { { 0x42 }, 3, T, R, pfx_66, W0, Ln }, /* vdbpsadbw */ + { { 0x42 }, 3, T, R, pfx_f3, W0, Ln }, /* vmpsadbw */ { { 0x43 }, 3, T, R, pfx_66, Wn, L1|L2 }, /* vshufi{32x4,64x2} */ { { 0x44 }, 3, T, R, pfx_66, WIG, Ln }, /* vpclmulqdq */ { { 0x50 }, 3, T, R, pfx_66, Wn, Ln }, /* vrangep{s,d} */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -434,8 +434,8 @@ static const struct ext0f38_table { [0xcb] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xcc ... 0xcd] = { .simd_size = simd_other, .two_op = 1, .d8s = d8s_vl }, [0xcf] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, - [0xd2] = { .simd_size = simd_other }, - [0xd3] = { .simd_size = simd_other }, + [0xd2] = { .simd_size = simd_other, .d8s = d8s_vl }, + [0xd3] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xd6] = { .simd_size = simd_other, .d8s = d8s_vl }, [0xd7] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, [0xda] = { .simd_size = simd_other, .d8s = d8s_vl }, --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6169,6 +6169,30 @@ x86_emulate( avx512_vlen_check(true); goto simd_zmm; + case X86EMUL_OPC_EVEX (0x0f38, 0x50): /* vpdpbuud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F3(0x0f38, 0x50): /* vpdpbsud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x50): /* vpdpbssd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (0x0f38, 0x51): /* vpdpbuuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F3(0x0f38, 0x51): /* vpdpbsuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x51): /* vpdpbssds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (0x0f38, 0xd2): /* vpdpwuud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(0x0f38, 0xd2): /* vpdpwusd [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F3(0x0f38, 0xd2): /* vpdpwsud [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (0x0f38, 0xd3): /* vpdpwuuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(0x0f38, 0xd3): /* vpdpwusds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F3(0x0f38, 0xd3): /* vpdpwsuds [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(evex.w, X86_EXC_UD); + if ( !cp->avx10.avx10_v1_aux ) + vcpu_must_have(avx10, 2); + op_bytes = 16 << evex.lr; + goto avx512f_no_sae; + + case X86EMUL_OPC_EVEX (0x0f38, 0x52): /* vdpphps [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(evex.w, X86_EXC_UD); + vcpu_must_have(avx10, 2); + op_bytes = 16 << evex.lr; + goto avx512f_no_sae; + case X86EMUL_OPC_EVEX_66(0x0f38, 0x8f): /* vpshufbitqmb [xyz]mm/mem,[xyz]mm,k{k} */ generate_exception_if(evex.w || !evex.r || !evex.R || evex.z, X86_EXC_UD); /* fall through */ @@ -7635,6 +7659,14 @@ x86_emulate( visa_check(bw); goto opmask_shift_imm; + case X86EMUL_OPC_EVEX_F3(0x0f3a, 0x42): /* vmpsadbw $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(evex.w || evex.brs, X86_EXC_UD); + vcpu_must_have(avx10, 2); + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + fault_suppression = false; + goto simd_imm8_zmm; + case X86EMUL_OPC_66(0x0f3a, 0x44): /* pclmulqdq $imm8,xmm/m128,xmm */ case X86EMUL_OPC_VEX_66(0x0f3a, 0x44): /* vpclmulqdq $imm8,{x,y}mm/mem,{x,y}mm,{x,y}mm */ host_and_vcpu_must_have(pclmulqdq); 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Thu, 09 Apr 2026 08:09:04 -0700 (PDT) Message-ID: <69eeb7f1-b04e-4c61-90ef-a9e841e6758d@suse.com> Date: Thu, 9 Apr 2026 17:09:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 12/16] x86emul: support AVX10.2 minmax insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775747344-C4E1B0B1-59FCFDF7/0/0 X-purgate-type: clean X-purgate-size: 4819 While they use new major opcodes, they are still pretty similar to various existing insns. Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Update to spec version 3. Switch to using fallthrough pseudo- keyword. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -726,6 +726,11 @@ static const struct test avx10_2_all[] = INSN_SFP(comx, 0f, 2f), INSN(comxsh, f3, map5, 2f, el, fp16, el), INSN(dpphps, , 0f38, 52, vl, d, vl), + INSN(minmax, 66, 0f3a, 52, vl, sd, vl), + INSN(minmax, 66, 0f3a, 53, el, sd, el), + INSN(minmaxbf16, f2, 0f3a, 52, vl, bf16, vl), + INSN(minmaxph, , 0f3a, 52, vl, fp16, vl), + INSN(minmaxsh, , 0f3a, 53, el, fp16, el), INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl), INSN(pdpbssd, f2, 0f38, 50, vl, d, vl), INSN(pdpbssds, f2, 0f38, 51, vl, d, vl), --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2093,6 +2093,11 @@ static const struct evex { { { 0x44 }, 3, T, R, pfx_66, WIG, Ln }, /* vpclmulqdq */ { { 0x50 }, 3, T, R, pfx_66, Wn, Ln }, /* vrangep{s,d} */ { { 0x51 }, 3, T, R, pfx_66, Wn, LIG }, /* vranges{s,d} */ + { { 0x52 }, 3, T, R, pfx_no, W0, Ln }, /* vminmaxph */ + { { 0x52 }, 3, T, R, pfx_66, Wn, Ln }, /* vminmaxp{s,d} */ + { { 0x52 }, 3, T, R, pfx_f2, W0, Ln }, /* vminmaxbf16 */ + { { 0x53 }, 3, T, R, pfx_no, W0, LIG }, /* vminmaxsh */ + { { 0x53 }, 3, T, R, pfx_66, Wn, LIG }, /* vminmaxs{s,d} */ { { 0x54 }, 3, T, R, pfx_66, Wn, Ln }, /* vfixupimmp{s,d} */ { { 0x55 }, 3, T, R, pfx_66, Wn, LIG }, /* vfixumpimms{s,d} */ { { 0x56 }, 3, T, R, pfx_no, W0, Ln }, /* vreduceph */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -500,6 +500,8 @@ static const struct ext0f3a_table { [0x4c] = { .simd_size = simd_packed_int, .four_op = 1 }, [0x50] = { .simd_size = simd_packed_fp, .d8s = d8s_vl }, [0x51] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, + [0x52] = { .simd_size = simd_packed_fp, .d8s = d8s_vl }, + [0x53] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, [0x54] = { .simd_size = simd_packed_fp, .d8s = d8s_vl }, [0x55] = { .simd_size = simd_scalar_vexw, .d8s = d8s_dq }, [0x56] = { .simd_size = simd_packed_fp, .two_op = 1, .d8s = d8s_vl }, @@ -1468,6 +1470,7 @@ int x86emul_decode(struct x86_emulate_st case 0x0a: /* vrndscalesh */ case 0x26: /* vfpclassph */ case 0x27: /* vfpclasssh */ + case 0x53: /* vminmaxsh */ case 0x56: /* vgetmantph */ case 0x57: /* vgetmantsh */ case 0x66: /* vreduceph */ @@ -1476,6 +1479,11 @@ int x86emul_decode(struct x86_emulate_st s->fp16 = true; break; + case 0x52: /* vminmax{ph,bf16} */ + if ( !s->evex.pfx || s->evex.pfx == vex_f2 ) + s->fp16 = true; + break; + case 0xc2: /* vpcmp{p,s}h */ if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) ) s->fp16 = true; --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -7697,6 +7697,21 @@ x86_emulate( generate_exception_if(vex.w, X86_EXC_UD); goto simd_0f_int_imm8; + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x52): /* vminmaxbf16 $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD); + op_bytes = 16 << evex.lr; + fallthrough; + case X86EMUL_OPC_EVEX(0x0f3a, 0x52): /* vminmaxph $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(0x0f3a, 0x53): /* vminmaxsh $imm,xmm/m16,xmm,xmm,xmm{k} */ + generate_exception_if(vex.w, X86_EXC_UD); + fallthrough; + case X86EMUL_OPC_EVEX_66(0x0f3a, 0x52): /* vminmaxp{s,d} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(0x0f3a, 0x53): /* vminmaxs{s,d} $imm8,xmm/mem,xmm,xmm{k} */ + vcpu_must_have(avx10, 2); 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Thu, 09 Apr 2026 08:14:36 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:14:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 13/16] x86emul: support AVX10.2 BFloat16 insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775747677-BEF4B0B1-D7547AAC/0/0 X-purgate-type: clean X-purgate-size: 16443 These are all very similar to various existing insns. VGETEXPPBF16, not living in the expected place, benefits from the respective twobyte_table[] entry already having Mov (aka TwoOp). Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Update to spec version 3. Switch to using fallthrough pseudo- keyword. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -722,15 +722,36 @@ static const struct test vpclmulqdq_all[ }; static const struct test avx10_2_all[] = { + INSN(addbf16, 66, map5, 58, vl, bf16, vl), + INSN(cmpbf16, f2, 0f3a, c2, vl, bf16, vl), INSN(comisbf16, 66, map5, 2f, el, bf16, el), INSN_SFP(comx, 0f, 2f), INSN(comxsh, f3, map5, 2f, el, fp16, el), + INSN(divbf16, 66, map5, 5e, vl, bf16, vl), INSN(dpphps, , 0f38, 52, vl, d, vl), + INSN(fmadd132bf16, , map6, 98, vl, bf16, vl), + INSN(fmadd213bf16, , map6, a8, vl, bf16, vl), + INSN(fmadd231bf16, , map6, b8, vl, bf16, vl), + INSN(fmsub132bf16, , map6, 9a, vl, bf16, vl), + INSN(fmsub213bf16, , map6, aa, vl, bf16, vl), + INSN(fmsub231bf16, , map6, ba, vl, bf16, vl), + INSN(fnmadd132bf16, , map6, 9c, vl, bf16, vl), + INSN(fnmadd213bf16, , map6, ac, vl, bf16, vl), + INSN(fnmadd231bf16, , map6, bc, vl, bf16, vl), + INSN(fnmsub132bf16, , map6, 9e, vl, bf16, vl), + INSN(fnmsub213bf16, , map6, ae, vl, bf16, vl), + INSN(fnmsub231bf16, , map6, be, vl, bf16, vl), + INSN(fpclassbf16, f2, 0f3a, 66, vl, bf16, vl), + INSN(getexpbf16, , map6, 42, vl, bf16, vl), + INSN(getmantbf16, f2, 0f3a, 26, vl, bf16, vl), + INSN(maxbf16, 66, map5, 5f, vl, bf16, vl), + INSN(minbf16, 66, map5, 5d, vl, bf16, vl), INSN(minmax, 66, 0f3a, 52, vl, sd, vl), INSN(minmax, 66, 0f3a, 53, el, sd, el), INSN(minmaxbf16, f2, 0f3a, 52, vl, bf16, vl), INSN(minmaxph, , 0f3a, 52, vl, fp16, vl), INSN(minmaxsh, , 0f3a, 53, el, fp16, el), + INSN(mulbf16, 66, map5, 59, vl, bf16, vl), INSN(mpsadbw, f3, 0f3a, 42, vl, d_nb, vl), INSN(pdpbssd, f2, 0f38, 50, vl, d, vl), INSN(pdpbssds, f2, 0f38, 51, vl, d, vl), @@ -744,6 +765,13 @@ static const struct test avx10_2_all[] = INSN(pdpwusds, 66, 0f38, d3, vl, d, vl), INSN(pdpwuud, , 0f38, d2, vl, d, vl), INSN(pdpwuuds, , 0f38, d3, vl, d, vl), + INSN(rcpph, , map6, 4c, vl, bf16, vl), + INSN(reducebf16, f2, 0f3a, 56, vl, bf16, vl), + INSN(rndscalebf16, f2, 0f3a, 08, vl, bf16, vl), + INSN(rsqrtph, , map6, 4e, vl, bf16, vl), + INSN(scalefbf16, , map6, 2c, vl, bf16, vl), + INSN(sqrtbf16, 66, map5, 51, vl, bf16, vl), + INSN(subbf16, 66, map5, 5c, vl, bf16, vl), INSN_SFP(ucomx, 0f, 2e), INSN(ucomxsh, f3, map5, 2e, el, fp16, el), }; --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2056,6 +2056,7 @@ static const struct evex { { { 0x05 }, 3, T, R, pfx_66, W1, Ln }, /* vpermilpd */ { { 0x08 }, 3, T, R, pfx_no, W0, Ln }, /* vrndscaleph */ { { 0x08 }, 3, T, R, pfx_66, W0, Ln }, /* vrndscaleps */ + { { 0x08 }, 3, T, R, pfx_f2, W0, Ln }, /* vrndscalebf16 */ { { 0x09 }, 3, T, R, pfx_66, W1, Ln }, /* vrndscalepd */ { { 0x0a }, 3, T, R, pfx_no, W0, LIG }, /* vrndscalesh */ { { 0x0a }, 3, T, R, pfx_66, W0, LIG }, /* vrndscaless */ @@ -2079,6 +2080,7 @@ static const struct evex { { { 0x25 }, 3, T, R, pfx_66, Wn, Ln }, /* vpternlog{d,q} */ { { 0x26 }, 3, T, R, pfx_no, W0, Ln }, /* vgetmantph */ { { 0x26 }, 3, T, R, pfx_66, Wn, Ln }, /* vgetmantp{s,d} */ + { { 0x26 }, 3, T, R, pfx_f2, W0, Ln }, /* vgetmantbf16 */ { { 0x27 }, 3, T, R, pfx_no, W0, LIG }, /* vgetmantsh */ { { 0x27 }, 3, T, R, pfx_66, Wn, LIG }, /* vgetmants{s,d} */ { { 0x38 }, 3, T, R, pfx_66, Wn, L1|L2 }, /* vinserti{32x4,64x2} */ @@ -2102,10 +2104,12 @@ static const struct evex { { { 0x55 }, 3, T, R, pfx_66, Wn, LIG }, /* vfixumpimms{s,d} */ { { 0x56 }, 3, T, R, pfx_no, W0, Ln }, /* vreduceph */ { { 0x56 }, 3, T, R, pfx_66, Wn, Ln }, /* vreducep{s,d} */ + { { 0x56 }, 3, T, R, pfx_f2, W0, Ln }, /* vreducebf16 */ { { 0x57 }, 3, T, R, pfx_no, W0, LIG }, /* vreducesh */ { { 0x57 }, 3, T, R, pfx_66, Wn, LIG }, /* vreduces{s,d} */ { { 0x66 }, 3, T, R, pfx_no, W0, Ln }, /* vfpclassph */ { { 0x66 }, 3, T, R, pfx_66, Wn, Ln }, /* vfpclassp{s,d} */ + { { 0x66 }, 3, T, R, pfx_f2, W0, Ln }, /* vfpclassbf16 */ { { 0x67 }, 3, T, R, pfx_no, W0, LIG }, /* vfpclasssh */ { { 0x67 }, 3, T, R, pfx_66, Wn, LIG }, /* vfpclasss{s,d} */ { { 0x70 }, 3, T, R, pfx_66, W1, Ln }, /* vshldw */ @@ -2114,6 +2118,7 @@ static const struct evex { { { 0x73 }, 3, T, R, pfx_66, Wn, Ln }, /* vshrd{d,q} */ { { 0xc2 }, 3, T, R, pfx_no, W0, Ln }, /* vcmpph */ { { 0xc2 }, 3, T, R, pfx_f3, W0, LIG }, /* vcmpsh */ + { { 0xc2 }, 3, T, R, pfx_f2, W0, Ln }, /* vcmpbf16 */ { { 0xce }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineqb */ { { 0xcf }, 3, T, R, pfx_66, W1, Ln }, /* vgf2p8affineinvqb */ }, evex_map5[] = { @@ -2130,10 +2135,13 @@ static const struct evex { { { 0x2f }, 2, T, R, pfx_66, W0, LIG }, /* vcomisbf16 */ { { 0x2f }, 2, T, R, pfx_f3, W0, LIG }, /* vcomxsh */ { { 0x51 }, 2, T, R, pfx_no, W0, Ln }, /* vsqrtph */ + { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vsqrtbf16 */ { { 0x51 }, 2, T, R, pfx_f3, W0, LIG }, /* vsqrtsh */ { { 0x58 }, 2, T, R, pfx_no, W0, Ln }, /* vaddph */ + { { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vaddbf16 */ { { 0x58 }, 2, T, R, pfx_f3, W0, LIG }, /* vaddsh */ { { 0x59 }, 2, T, R, pfx_no, W0, Ln }, /* vmulph */ + { { 0x59 }, 2, T, R, pfx_66, W0, Ln }, /* vmulbf16 */ { { 0x59 }, 2, T, R, pfx_f3, W0, LIG }, /* vmulsh */ { { 0x5a }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2pd */ { { 0x5a }, 2, T, R, pfx_66, W1, Ln }, /* vcvtpd2ph */ @@ -2144,12 +2152,16 @@ static const struct evex { { { 0x5b }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2dq */ { { 0x5b }, 2, T, R, pfx_f3, W0, Ln }, /* vcvttph2dq */ { { 0x5c }, 2, T, R, pfx_no, W0, Ln }, /* vsubph */ + { { 0x5c }, 2, T, R, pfx_66, W0, Ln }, /* vsubbf16 */ { { 0x5c }, 2, T, R, pfx_f3, W0, LIG }, /* vsubsh */ { { 0x5d }, 2, T, R, pfx_no, W0, Ln }, /* vminph */ + { { 0x5d }, 2, T, R, pfx_66, W0, Ln }, /* vminbf16 */ { { 0x5d }, 2, T, R, pfx_f3, W0, LIG }, /* vminsh */ { { 0x5e }, 2, T, R, pfx_no, W0, Ln }, /* vdivph */ + { { 0x5e }, 2, T, R, pfx_66, W0, Ln }, /* vdivbf16 */ { { 0x5e }, 2, T, R, pfx_f3, W0, LIG }, /* vdivsh */ { { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */ + { { 0x5f }, 2, T, R, pfx_66, W0, Ln }, /* vmaxbf16 */ { { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */ { { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */ { { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */ @@ -2177,12 +2189,16 @@ static const struct evex { }, evex_map6[] = { { { 0x13 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtph2psx */ { { 0x13 }, 2, T, R, pfx_no, W0, LIG }, /* vcvtsh2ss */ + { { 0x2c }, 2, T, R, pfx_no, W0, Ln }, /* vscalefbf16 */ { { 0x2c }, 2, T, R, pfx_66, W0, Ln }, /* vscalefph */ { { 0x2d }, 2, T, R, pfx_66, W0, LIG }, /* vscalefsh */ + { { 0x42 }, 2, T, R, pfx_no, W0, Ln }, /* vgetexpbf16 */ { { 0x42 }, 2, T, R, pfx_66, W0, Ln }, /* vgetexpph */ { { 0x43 }, 2, T, R, pfx_66, W0, LIG }, /* vgetexpsh */ + { { 0x4c }, 2, T, R, pfx_no, W0, Ln }, /* vrcpbf16 */ { { 0x4c }, 2, T, R, pfx_66, W0, Ln }, /* vrcpph */ { { 0x4d }, 2, T, R, pfx_66, W0, LIG }, /* vrcpsh */ + { { 0x4e }, 2, T, R, pfx_no, W0, Ln }, /* vrsqrtbf16 */ { { 0x4e }, 2, T, R, pfx_66, W0, Ln }, /* vrsqrtph */ { { 0x4f }, 2, T, R, pfx_66, W0, LIG }, /* vrsqrtsh */ { { 0x56 }, 2, T, R, pfx_f3, W0, Ln }, /* vfmaddcph */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -1466,31 +1466,34 @@ int x86emul_decode(struct x86_emulate_st { switch ( b ) { - case 0x08: /* vrndscaleph */ + case 0x08: /* vrndscale{ph,bf16} */ + case 0x26: /* vfpclass{ph,bf16} */ + case 0x52: /* vminmax{ph,bf16} */ + case 0x56: /* vgetmant{ph,bf16} */ + case 0x66: /* vreduce{ph,bf16} */ + if ( !s->evex.pfx || s->evex.pfx == vex_f2 ) + s->fp16 = true; + break; + case 0x0a: /* vrndscalesh */ - case 0x26: /* vfpclassph */ case 0x27: /* vfpclasssh */ case 0x53: /* vminmaxsh */ - case 0x56: /* vgetmantph */ case 0x57: /* vgetmantsh */ - case 0x66: /* vreduceph */ case 0x67: /* vreducesh */ if ( !s->evex.pfx ) s->fp16 = true; break; - case 0x52: /* vminmax{ph,bf16} */ - if ( !s->evex.pfx || s->evex.pfx == vex_f2 ) - s->fp16 = true; - break; - - case 0xc2: /* vpcmp{p,s}h */ - if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) ) + case 0xc2: /* vpcmp{p,s}h, vcmpbf16 */ + if ( s->evex.pfx != vex_66 ) s->fp16 = true; break; } - disp8scale = decode_disp8scale(ext0f3a_table[b].d8s, s); + if ( s->fp16 && s->evex.pfx == vex_f2 && !s->evex.brs ) + disp8scale = 4 + s->evex.lr; + else + disp8scale = decode_disp8scale(ext0f3a_table[b].d8s, s); } break; @@ -1498,7 +1501,7 @@ int x86emul_decode(struct x86_emulate_st switch ( b ) { default: - if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) ) + if ( s->evex.pfx != vex_f2 ) s->fp16 = true; break; @@ -1528,6 +1531,11 @@ int x86emul_decode(struct x86_emulate_st s->simd_size = simd_none; break; + case 0x5a: /* vcvt{p,s}d2{p,s}h, vcvt{p,s}h2{p,s}d */ + if ( !(s->evex.pfx & VEX_PREFIX_DOUBLE_MASK) ) + s->fp16 = true; + break; + case 0x5b: /* vcvt{d,q}q2ph, vcvt{,t}ph2dq */ if ( s->evex.pfx && s->evex.pfx != vex_f2 ) s->fp16 = true; @@ -1580,6 +1588,14 @@ int x86emul_decode(struct x86_emulate_st disp8scale = 1; break; + case 0x42: /* vgetexpbf16 needs special casing */ + if ( s->evex.pfx == vex_66 ) + { + s->simd_size = simd_packed_fp; + disp8scale = s->evex.brs ? 1 : 4 + s->evex.lr; + } + break; + case 0x5a: /* vcvtph2pd needs special casing */ if ( !s->evex.pfx && !s->evex.brs ) disp8scale -= 2; @@ -1612,7 +1628,7 @@ int x86emul_decode(struct x86_emulate_st switch ( b ) { default: - if ( s->evex.pfx == vex_66 ) + if ( !(s->evex.pfx & VEX_PREFIX_SCALAR_MASK) ) s->fp16 = true; break; @@ -1934,6 +1950,13 @@ int x86emul_decode(struct x86_emulate_st s->op_bytes = 4 >> s->fp16; break; case vex_f2: + if ( s->fp16 ) + { + ASSERT(evex_encoded()); + generate_exception_if(s->evex.w, X86_EXC_UD); + s->op_bytes = 0; + break; + } generate_exception_if(evex_encoded() && !s->evex.w, X86_EXC_UD); s->op_bytes = 8; break; --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -7301,6 +7301,20 @@ x86_emulate( avx512_vlen_check(b & 2); goto simd_imm8_zmm; + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x66): /* vfpclassbf16 $imm8,[xyz]mm/mem,k{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0xc2): /* vcmpbf16 $imm8,[xyz]mm/mem,[xyz]mm,k{k} */ + generate_exception_if(!evex.r || !evex.R || evex.z, X86_EXC_UD); + fallthrough; + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x08): /* vrndscalebf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x26): /* vgetmantbf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f3a, 0x56): /* vreducebf16 $imm8,[xyz]mm/mem,[xyz]mm{k} */ + generate_exception_if(evex.w || (ea.type != OP_MEM && evex.brs), + X86_EXC_UD); + vcpu_must_have(avx10, 2); + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_imm8_zmm; + #endif /* X86EMUL_NO_SIMD */ CASE_SIMD_PACKED_INT(0x0f3a, 0x0f): /* palignr $imm8,{,x}mm/mem,{,x}mm */ @@ -7932,6 +7946,36 @@ x86_emulate( generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_all_fp; + case X86EMUL_OPC_EVEX_66(5, 0x51): /* vsqrtbf16 [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x58): /* vaddbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x59): /* vmulbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x5c): /* vsubbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x5d): /* vminbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x5e): /* vdivbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x5f): /* vmaxbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x2c): /* vscalefbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x42): /* vgetexpbf16 [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x4c): /* vrcpbf16 [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x4e): /* vrsqrtbf16 [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x98): /* vfmadd132bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x9a): /* vfmsub132bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x9c): /* vfnmadd132bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0x9e): /* vfnmsub132bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xa8): /* vfmadd213bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xaa): /* vfmsub213bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xac): /* vfnmadd213bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xae): /* vfnmsub213bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xb8): /* vfmadd231bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xba): /* vfmsub231bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xbc): /* vfnmadd231bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX(6, 0xbe): /* vfnmsub231bf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ + generate_exception_if(evex.w || (ea.type != OP_MEM && evex.brs), + X86_EXC_UD); + vcpu_must_have(avx10, 2); + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_zmm; + CASE_SIMD_ALL_FP(_EVEX, 5, 0x5a): /* vcvtp{h,d}2p{h,d} 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Thu, 09 Apr 2026 08:15:06 -0700 (PDT) Message-ID: <476e3ba2-275f-4fda-bbae-090dee92e089@suse.com> Date: Thu, 9 Apr 2026 17:15:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 14/16] x86emul: support AVX10.2 saturating convert insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775747707-41713C9A-4A26ED8E/0/0 X-purgate-type: clean X-purgate-size: 9105 While the to-byte ones are somewhat different from what has been there (yet then nicely regular from an operands perspective), the others are pretty similar to various existing insns. Signed-off-by: Jan Beulich --- Spec rev 002 says VCVTTNEBF162I{,U}BS, yet that's going to change to VCVTTBF162I{,U}BS. --- SDE: -dmr / -future --- v4: Update to spec version 3. Switch to using fallthrough pseudo- keyword. Series re-ordering adjustments. v3: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -727,6 +727,30 @@ static const struct test avx10_2_all[] = INSN(comisbf16, 66, map5, 2f, el, bf16, el), INSN_SFP(comx, 0f, 2f), INSN(comxsh, f3, map5, 2f, el, fp16, el), + INSN(cvtbf162ibs, f2, map5, 69, vl, bf16, vl), + INSN(cvtbf162iubs, f2, map5, 6b, vl, bf16, vl), + INSN(cvtph2ibs, , map5, 69, vl, fp16, vl), + INSN(cvtph2iubs, , map5, 6b, vl, fp16, vl), + INSN(cvtps2ibs, 66, map5, 69, vl, d, vl), + INSN(cvtps2iubs, 66, map5, 6b, vl, d, vl), + INSN(cvttbf162ibs, f2, map5, 68, vl, bf16, vl), + INSN(cvttbf162iubs, f2, map5, 6a, vl, bf16, vl), + INSN(cvttpd2dqs, , map5, 6d, vl, q, vl), + INSN(cvttpd2qqs, 66, map5, 6d, vl, q, vl), + INSN(cvttpd2udqs, , map5, 6c, vl, q, vl), + INSN(cvttpd2uqqs, 66, map5, 6c, vl, q, vl), + INSN(cvttph2ibs, , map5, 68, vl, fp16, vl), + INSN(cvttph2iubs, , map5, 6a, vl, fp16, vl), + INSN(cvttps2dqs, , map5, 6d, vl, d, vl), + INSN(cvttps2ibs, 66, map5, 68, vl, d, vl), + INSN(cvttps2iubs, 66, map5, 6a, vl, d, vl), + INSN(cvttps2qqs, 66, map5, 6d, vl_2, d, vl), + INSN(cvttps2udqs, , map5, 6c, vl, d, vl), + INSN(cvttps2uqqs, 66, map5, 6c, vl_2, d, vl), + INSN(cvttsd2sis, f2, map5, 6d, el, q, el), + INSN(cvttsd2usis, f2, map5, 6c, el, q, el), + INSN(cvttss2sis, f3, map5, 6d, el, d, el), + INSN(cvttss2usis, f3, map5, 6c, el, d, el), INSN(divbf16, 66, map5, 5e, vl, bf16, vl), INSN(dpphps, , 0f38, 52, vl, d, vl), INSN(fmadd132bf16, , map6, 98, vl, bf16, vl), --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -2163,6 +2163,26 @@ static const struct evex { { { 0x5f }, 2, T, R, pfx_no, W0, Ln }, /* vmaxph */ { { 0x5f }, 2, T, R, pfx_66, W0, Ln }, /* vmaxbf16 */ { { 0x5f }, 2, T, R, pfx_f3, W0, LIG }, /* vmaxsh */ + { { 0x68 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2ibs */ + { { 0x68 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttps2ibs */ + { { 0x68 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvttbf162ibs */ + { { 0x69 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2ibs */ + { { 0x69 }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2ibs */ + { { 0x69 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtbf162ibs */ + { { 0x6a }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2iubs */ + { { 0x6a }, 2, T, R, pfx_66, W0, Ln }, /* vcvttps2iubs */ + { { 0x6a }, 2, T, R, pfx_f2, W0, Ln }, /* vcvttbf162iubs */ + { { 0x6b }, 2, T, R, pfx_no, W0, Ln }, /* vcvtph2iubs */ + { { 0x6b }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2iubs */ + { { 0x6b }, 2, T, R, pfx_f2, W0, Ln }, /* vcvtbf162iubs */ + { { 0x6c }, 2, T, R, pfx_no, Wn, Ln }, /* vcvttp{s,d}2udqs */ + { { 0x6c }, 2, T, R, pfx_66, Wn, Ln }, /* vcvttp{s,d}2uqqs */ + { { 0x6c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttss2usis */ + { { 0x6c }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2usis */ + { { 0x6d }, 2, T, R, pfx_no, Wn, Ln }, /* vcvttp{s,d}2dqs */ + { { 0x6d }, 2, T, R, pfx_66, Wn, Ln }, /* vcvttp{s,d}2qqs */ + { { 0x6d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttss2sis */ + { { 0x6d }, 2, T, R, pfx_f2, Wn, LIG }, /* vcvttsd2sis */ { { 0x6e }, 2, T, R, pfx_66, WIG, L0 }, /* vmovw */ { { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */ { { 0x6f }, 2, T, R, pfx_f3, Wn, Ln }, /* vmovrs{d,q} */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -1541,6 +1541,19 @@ int x86emul_decode(struct x86_emulate_st s->fp16 = true; break; + case 0x68: /* vcvtt{ph,ps,bf16}2ibs */ + case 0x69: /* vcvt{ph,ps,nebf16}2ibs */ + case 0x6a: /* vcvtt{ph,ps,bf16}2iubs */ + case 0x6b: /* vcvt{ph,ps,nebf16}2iubs */ + if ( !s->evex.pfx || s->evex.pfx == vex_f2 ) + s->fp16 = true; + fallthrough; + case 0x6c: /* vcvttp{s,d}2u{d,q}qs, vcvtts{s,d}2usis */ + case 0x6d: /* vcvttp{s,d}2{d,q}qs, vcvtts{s,d}2sis */ + d |= TwoOp; + s->simd_size = simd_other; + break; + case 0x6e: /* vmovw r/x/m16, xmm */ d = (d & ~SrcMask) | SrcMem16; /* fall through */ @@ -1606,6 +1619,14 @@ int x86emul_decode(struct x86_emulate_st --disp8scale; break; + case 0x6c: /* vcvttps2uqqs and vcvts{s,d}2usi need special casing */ + case 0x6d: /* vcvttps2qqs and vcvts{s,d}2si need special casing */ + if ( s->evex.pfx == vex_66 && !s->evex.w && !s->evex.brs ) + --disp8scale; + else if ( s->evex.pfx & VEX_PREFIX_SCALAR_MASK ) + disp8scale = s->evex.pfx & VEX_PREFIX_DOUBLE_MASK ? 3 : 2; + break; + case 0x7a: case 0x7b: /* vcvt{,t}ph2qq need special casing */ if ( s->evex.pfx == vex_66 && !s->evex.brs ) disp8scale = s->evex.brs ? 1 : 2 + s->evex.lr; --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -8006,6 +8006,55 @@ x86_emulate( op_bytes = 8 << evex.lr; goto simd_zmm; + case X86EMUL_OPC_EVEX_F2(5, 0x68): /* vcvttbf162ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(5, 0x69): /* vcvtbf162ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(5, 0x6a): /* vcvttbf162iubs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_F2(5, 0x6b): /* vcvtbf162iubs [xyz]mm/mem,[xyz]mm{k} */ + generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD); + fallthrough; + case X86EMUL_OPC_EVEX (5, 0x68): /* vcvttph2ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x68): /* vcvttps2ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (5, 0x69): /* vcvtph2ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x69): /* vcvtps2ibs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (5, 0x6a): /* vcvttph2iubs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x6a): /* vcvttps2iubs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (5, 0x6b): /* vcvtph2iubs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x6b): /* vcvtps2iubs [xyz]mm/mem,[xyz]mm{k} */ + generate_exception_if(evex.w, X86_EXC_UD); + vcpu_must_have(avx10, 2); + if ( ea.type != OP_REG || !evex.brs ) + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_zmm; + + case X86EMUL_OPC_EVEX (5, 0x6c): /* vcvttps2udqs [xyz]mm/mem,[xyz]mm{k} */ + /* vcvttpd2udqs [xyz]mm/mem,{x,y}mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x6c): /* vcvttps2uqqs {x,y}mm/mem,[xyz]mm{k} */ + /* vcvttpd2uqqs [xyz]mm/mem,[xyz]mm{k} */ + case X86EMUL_OPC_EVEX (5, 0x6d): /* vcvttps2dqs [xyz]mm/mem,[xyz]mm{k} */ + /* vcvttpd2dqs [xyz]mm/mem,{x,y}mm{k} */ + case X86EMUL_OPC_EVEX_66(5, 0x6d): /* vcvttps2qqs {x,y}mm/mem,[xyz]mm{k} */ + /* vcvttpd2qqs [xyz]mm/mem,[xyz]mm{k} */ + vcpu_must_have(avx10, 2); + if ( ea.type != OP_REG || !evex.brs ) + avx512_vlen_check(false); + op_bytes = 8 << ((evex.w || !evex.pfx) + evex.lr); + goto simd_zmm; + + CASE_SIMD_SCALAR_FP(_EVEX, 5, 0x6c): /* vcvtts{s,d}2usis xmm/mem,reg */ + CASE_SIMD_SCALAR_FP(_EVEX, 5, 0x6d): /* vcvtts{s,d}2sis xmm/mem,reg */ + generate_exception_if((evex.reg != 0xf || !evex.RX || !evex.R || + evex.opmsk), + X86_EXC_UD); + vcpu_must_have(avx10, 2); + if ( !evex.brs ) + avx512_vlen_check(true); + else + generate_exception_if(ea.type != OP_REG, X86_EXC_UD); + get_fpu(X86EMUL_FPU_zmm); + opc = init_evex(stub); + goto cvts_2si; + case X86EMUL_OPC_EVEX_F2(5, 0x6f): /* vmovrs{b,w} mem,[xyz]mm{k} */ elem_bytes = 1 << evex.w; fallthrough; From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:15:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:15:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277838.1562942 (Exim 4.92) (envelope-from ) id 1wAr6g-0007hF-Os; Thu, 09 Apr 2026 15:15:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277838.1562942; Thu, 09 Apr 2026 15:15:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAr6g-0007h4-Kj; Thu, 09 Apr 2026 15:15:46 +0000 Received: by outflank-mailman (input) for mailman id 1277838; Thu, 09 Apr 2026 15:15:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAr6f-0007gt-Ay for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:15:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAr6e-001ocu-N3 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:15:44 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7c297-5cb7-0a2a0a5109dd-0a2a4504b52c-26 for ; Thu, 09 Apr 2026 17:15:44 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7c2a0-bb33-0a2a45040019-d1558036a96d-3 for ; Thu, 09 Apr 2026 17:15:44 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso13141645e9.1 for ; Thu, 09 Apr 2026 08:15:44 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 08:15:43 -0700 (PDT) Message-ID: <66f59541-29f1-4bfa-a56e-67e827391ca1@suse.com> Date: Thu, 9 Apr 2026 17:15:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 15/16] x86emul: support other AVX10.2 convert insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Oleksii Kurochko , "community.manager@xenproject.org" References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775747744-33B3051B-4B7489B5/0/0 X-purgate-type: clean X-purgate-size: 10749 Despite most of them being about conversion to BF8/HF8, they are still somewhat similar to various existing convert insns. Signed-off-by: Jan Beulich --- SDE: -dmr / -future --- v4: Update to spec version 3. Switch to using fallthrough pseudo-keyword. Series re-ordering adjustments. Update to spec version 6. Add ChangeLog entry. v3: New. --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,7 +16,7 @@ The format is based on [Keep a Changelog mitigate (by rate-limiting) the system wide impact of an HVM guest misusing atomic instructions. - Support for CPIO microcode in discrete multiboot modules. - - Support for AVX10.1. (Experimental) + - Support for AVX10.2. (Experimental) - On Arm: - Support for guest suspend and resume to/from RAM via vPSCI. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -727,8 +727,22 @@ static const struct test avx10_2_all[] = INSN(comisbf16, 66, map5, 2f, el, bf16, el), INSN_SFP(comx, 0f, 2f), INSN(comxsh, f3, map5, 2f, el, fp16, el), + INSN(cvt2ph2bf8, f2, 0f38, 74, vl, fp16, vl), + INSN(cvt2ph2bf8s, f2, map5, 74, vl, fp16, vl), + INSN(cvt2ph2hf8, f2, map5, 18, vl, fp16, vl), + INSN(cvt2ph2hf8s, f2, map5, 1b, vl, fp16, vl), + INSN(cvt2ps2phx, 66, 0f38, 67, vl, d, vl), + INSN(cvtbiasph2bf8, , 0f38, 74, vl, fp16, vl), + INSN(cvtbiasph2bf8s, , map5, 74, vl, fp16, vl), + INSN(cvtbiasph2hf8, , map5, 18, vl, fp16, vl), + INSN(cvtbiasph2hf8s, , map5, 1b, vl, fp16, vl), + INSN(cvthf82ph, f2, map5, 1e, vl_2, b, vl), INSN(cvtbf162ibs, f2, map5, 69, vl, bf16, vl), INSN(cvtbf162iubs, f2, map5, 6b, vl, bf16, vl), + INSN(cvtph2bf8, f3, 0f38, 74, vl, fp16, vl), + INSN(cvtph2bf8s, f3, map5, 74, vl, fp16, vl), + INSN(cvtph2hf8, f3, map5, 18, vl, fp16, vl), + INSN(cvtph2hf8s, f3, map5, 1b, vl, fp16, vl), INSN(cvtph2ibs, , map5, 69, vl, fp16, vl), INSN(cvtph2iubs, , map5, 6b, vl, fp16, vl), INSN(cvtps2ibs, 66, map5, 69, vl, d, vl), --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1952,6 +1952,7 @@ static const struct evex { { { 0x64 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{d,q} */ { { 0x65 }, 2, T, R, pfx_66, Wn, Ln }, /* vblendmp{s,d} */ { { 0x66 }, 2, T, R, pfx_66, Wn, Ln }, /* vpblendm{b,w} */ + { { 0x67 }, 2, T, R, pfx_66, W0, Ln }, /* vcvt2ps2phx */ { { 0x68 }, 2, T, R, pfx_f2, Wn, Ln }, /* vp2intersect{d,q} */ { { 0x70 }, 2, T, R, pfx_66, W1, Ln }, /* vpshldvw */ { { 0x71 }, 2, T, R, pfx_66, Wn, Ln }, /* vpshldv{d,q} */ @@ -1959,6 +1960,9 @@ static const struct evex { { { 0x72 }, 2, T, R, pfx_f3, W1, Ln }, /* vcvtneps2bf16 */ { { 0x72 }, 2, T, R, pfx_f2, W1, Ln }, /* vcvtne2ps2bf16 */ { { 0x73 }, 2, T, R, pfx_66, Wn, Ln }, /* vpshrdv{d,q} */ + { { 0x74 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2bf8 */ + { { 0x74 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtph2bf8 */ + { { 0x74 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvt2ph2bf8 */ { { 0x75 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2{b,w} */ { { 0x76 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2{d,q} */ { { 0x77 }, 2, T, R, pfx_66, Wn, Ln }, /* vpermi2p{s,d} */ @@ -2124,8 +2128,15 @@ static const struct evex { }, evex_map5[] = { { { 0x10 }, 2, T, R, pfx_f3, W0, LIG }, /* vmovsh */ { { 0x11 }, 2, T, W, pfx_f3, W0, LIG }, /* vmovsh */ + { { 0x18 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2hf8 */ + { { 0x18 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtph2hf8 */ + { { 0x18 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvt2ph2hf8 */ + { { 0x1b }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2hf8s */ + { { 0x1b }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtph2hf8s */ + { { 0x1b }, 2, T, R, pfx_f2, W0, Ln }, /* vcvt2ph2hf8s */ { { 0x1d }, 2, T, R, pfx_66, W0, Ln }, /* vcvtps2phx */ { { 0x1d }, 2, T, R, pfx_no, W0, LIG }, /* vcvtss2sh */ + { { 0x1e }, 2, T, R, pfx_f2, W0, Ln }, /* cvthf82ph */ { { 0x2a }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsi2sh */ { { 0x2c }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2si */ { { 0x2d }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvtsh2si */ @@ -2187,6 +2198,9 @@ static const struct evex { { { 0x6e }, 2, T, R, pfx_f3, W0, L0 }, /* vmovw */ { { 0x6f }, 2, T, R, pfx_f3, Wn, Ln }, /* vmovrs{d,q} */ { { 0x6f }, 2, T, R, pfx_f2, Wn, Ln }, /* vmovrs{b,w} */ + { { 0x74 }, 2, T, R, pfx_no, W0, Ln }, /* vcvtbiasph2bf8s */ + { { 0x74 }, 2, T, R, pfx_f3, W0, Ln }, /* vcvtph2bf8s */ + { { 0x74 }, 2, T, R, pfx_f2, W0, Ln }, /* vcvt2ph2bf8s */ { { 0x78 }, 2, T, R, pfx_no, W0, Ln }, /* vcvttph2udq */ { { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vcvttph2uqq */ { { 0x78 }, 2, T, R, pfx_f3, Wn, LIG }, /* vcvttsh2usi */ --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -378,8 +378,10 @@ static const struct ext0f38_table { [0x62] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_bw }, [0x63] = { .simd_size = simd_packed_int, .to_mem = 1, .two_op = 1, .d8s = d8s_bw }, [0x64 ... 0x66] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, + [0x67] = { .simd_size = simd_other, .d8s = d8s_vl }, [0x68] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, + [0x74] = { .simd_size = simd_other, .d8s = d8s_vl }, [0x75 ... 0x76] = { .simd_size = simd_packed_int, .d8s = d8s_vl }, [0x77] = { .simd_size = simd_packed_fp, .d8s = d8s_vl }, [0x78] = { .simd_size = simd_other, .two_op = 1 }, @@ -1439,6 +1441,15 @@ int x86emul_decode(struct x86_emulate_st s->simd_size = ext0f38_table[b].simd_size; if ( evex_encoded() ) { + switch ( b ) + { + case 0x74: /* cvt{bias,ne,ne2}ph2bf8 */ + s->fp16 = true; + if ( s->evex.pfx != vex_f2 ) + d |= TwoOp; + break; + } + /* * VPMOVUS* are identical to VPMOVS* Disp8-scaling-wise, but * their attributes don't match those of the vex_66 encoded @@ -1586,6 +1597,23 @@ int x86emul_decode(struct x86_emulate_st switch ( b ) { + case 0x18: /* vcvt{bias,ne,ne2}ph2hf8 */ + case 0x1b: /* vcvt{bias,ne,ne2}ph2hf8s */ + case 0x74: /* vcvt{bias,ne,ne2}ph2bf8s */ + s->fp16 = true; + d = DstReg | SrcMem; + if ( s->evex.pfx != vex_f2 ) + d |= TwoOp; + s->simd_size = simd_other; + disp8scale = s->evex.brs ? 1 : 4 + s->evex.lr; + break; + + case 0x1e: /* vcvthf82ph */ + d = DstReg | SrcMem | TwoOp; + s->simd_size = simd_other; + disp8scale = 3 + s->evex.lr; + break; + case 0x78: case 0x79: /* vcvt{,t}ph2u{d,q}q need special casing */ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -6243,6 +6243,30 @@ x86_emulate( } goto simd_zmm; + case X86EMUL_OPC_EVEX (0x0f38, 0x74): /* vcvtbiasph2bf8 [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F3(0x0f38, 0x74): /* vcvtph2bf8 [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x74): /* vcvt2ph2bf8 [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX ( 5, 0x18): /* vcvtbiasph2hf8 [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F3( 5, 0x18): /* vcvtph2hf8 [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F2( 5, 0x18): /* vcvt2ph2hf8 [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX ( 5, 0x1b): /* vcvtbiasph2hf8s [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F3( 5, 0x1b): /* vcvtph2hf8s [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F2( 5, 0x1b): /* vcvt2ph2hf8s [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX ( 5, 0x74): /* vcvtbiasph2bf8s [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F3( 5, 0x74): /* vcvtph2bf8s [xyz]mm,[xyz]mm/mem{k} */ + case X86EMUL_OPC_EVEX_F2( 5, 0x74): /* vcvt2ph2bf8s [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */ + generate_exception_if(ea.type != OP_MEM && evex.brs, X86_EXC_UD); + fault_suppression = false; + fallthrough; + case X86EMUL_OPC_EVEX_66(0x0f38, 0x67): /* vcvt2ps2phx [xyz]mm,[xyz]mm,[xyz]mm/mem{k} */ + generate_exception_if(evex.w, X86_EXC_UD); + if ( !cp->avx10.avx10_v1_aux ) + vcpu_must_have(avx10, 2); + if ( ea.type != OP_REG || !evex.brs ) + avx512_vlen_check(false); + op_bytes = 16 << evex.lr; + goto simd_zmm; + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x68): /* vp2intersect{d,q} [xyz]mm/mem,[xyz]mm,k+1 */ host_and_vcpu_must_have(avx512_vp2intersect); generate_exception_if(evex.opmsk || !evex.r || !evex.R, X86_EXC_UD); @@ -7946,6 +7970,15 @@ x86_emulate( generate_exception_if(evex.w, X86_EXC_UD); goto avx512f_all_fp; + case X86EMUL_OPC_EVEX_F2(5, 0x1e): /* vcvthf82ph [xyz]mm,[xyz]mm/mem{k} */ + generate_exception_if(evex.w || evex.brs, X86_EXC_UD); + if ( !cp->avx10.avx10_v1_aux ) + vcpu_must_have(avx10, 2); + if ( ea.type != OP_REG || !evex.brs ) + avx512_vlen_check(false); + op_bytes = 8 << evex.lr; + goto simd_zmm; + case X86EMUL_OPC_EVEX_66(5, 0x51): /* vsqrtbf16 [xyz]mm/mem,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x58): /* vaddbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(5, 0x59): /* vmulbf16 [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */ --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -410,7 +410,7 @@ XEN_CPUFEATURE(TSA_SQ_NO, 18*32 XEN_CPUFEATURE(TSA_L1_NO, 18*32+ 2) /*A No L1D Transitive Scheduler Attacks */ /* Intel-defined CPU features, CPUID level 0x00000024:1.ecx, word 19 */ -XEN_CPUFEATURE(AVX10_V1_AUX, 19*32+ 2) /* AVX10 V1 Auxiliary Instructions */ +XEN_CPUFEATURE(AVX10_V1_AUX, 19*32+ 2) /*a AVX10 V1 Auxiliary Instructions */ #endif /* XEN_CPUFEATURE */ From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:16:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:16:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277846.1562951 (Exim 4.92) (envelope-from ) id 1wAr7I-0008C7-00; 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bh=u4G5b8BzRpgdq0ECTOrqeR4d4eU9e202pjwonFRVo98=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=wgKkesW0hJ9UoVGORaBS7fiNZwgsq7yyUxbnaIJGtcM6y8uE6z6dfKgHzyLiYE6e6 X/LLB9NeF0pSz2FFpqazGOM7TgVgPz53auTWSkcV6FNCpGpt/9W1B9ExQglfDVQl0v psKCfII148dzkuMKtGubfB+7IbROfOGj0D26eYrsC9a29KyJR1bCKqXdXYc5ALoQKt 3IpEhOiEUzTxE2u0+LRD16PakGiFCrsUPxpf0lFfSoL638fcs7AKZL0VkpavB0WeEQ XSIZDNPJKF6GzXZNknwiqUsVD8K2KF8eORmWkw7NtDVeaRXlBIgwiihbYkuWjQ8qqP 7eDQIDCz7Np3w== From: "Thierry Escande" Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=200/3]=20xl:=20Allow=20PCI=20devices=20to=20be=20passthrough'd=20via=20Qemu=20command=20line?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775747779696 Message-Id: <25920654-0423-49de-8245-ac6212a405cd@vates.tech> To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P.=20Berrang=C3=A9?=" References: <20260408172320.539750-1-thierry.escande@vates.tech> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.ae2112f9b0334547b0aa29321297f94e?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 15:16:20 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1775747782-32B2096F-E28E017E/0/0 X-purgate-type: clean X-purgate-size: 2192 On 4/9/26 12:16, Marek Marczykowski-G=C3=B3recki wrote: > On Wed, Apr 08, 2026 at 05:23:39PM +0000, Thierry Escande wrote: >> This series adds support for a new 'hotplug' option for PCI devices to b= e >> passthrough'd to guests. >> >> The current mechanism for device passthrough uses QMP device_add command >> to hot-plug PCI devices to the guest Qemu instance. This is an issue for >> guests running on Q35 chipset (preliminary support posted at [1]) since = the >> Q35 PCI root bus does not support hotplug. Devices could be hotplugged t= o >> a secondary PCI bus but Xen only support 1 PCI bus for now. >> >> The 'hotplug' option allows to control how devices are attached to the >> guest, either by using the legacy QMP mechanism (this is the default) or= by >> passing it directly to the Qemu command line using xen-pci-passthrough >> device. >> >> Example usage in cfg file: >> pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] >> >> Since Qemu -device option accepts parameters in json format, this >> patchset adds a new internal function libxl__device_pci_get_qmp_json() t= hat >> generates the device json object used for both QMP hotplug and command l= ine >> passing. >> Also, the function libxl_pci_assignable() is made available from libxl.h >> for access in libxl_dm.c. I don't know if it's ok to make it public or i= f >> it should stay private. Maybe it should be renamed as >> libxl_device_pci_assignable() to match the other PCI device APIs. >> >> This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running >> Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. >> Disabling the hotplug mechanism might be made mandatory for Q35 machines >> later, once Q35 support is merged upstream. > > Generally I like the approach, and it looks sensible on the first look. > But CI says it fails to build: > https://gitlab.com/xen-project/people/marmarek/xen/-/pipelines/2439831766 > I completely skipped YAJL support. My bad. I'll send a v2 pretty soon. Regards, Thierry -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:16:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:16:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277852.1562959 (Exim 4.92) (envelope-from ) id 1wAr7g-0000C6-7N; Thu, 09 Apr 2026 15:16:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277852.1562959; Thu, 09 Apr 2026 15:16:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAr7g-0000Bz-4p; Thu, 09 Apr 2026 15:16:48 +0000 Received: by outflank-mailman (input) for mailman id 1277852; Thu, 09 Apr 2026 15:16:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAr7e-0000BP-7z for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:16:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAr7d-00CmTr-KJ for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:16:45 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7c2dc-2eae-0a2a0a5409dd-0a2a4509cfb6-2 for ; Thu, 09 Apr 2026 17:16:45 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7c2dd-bf79-0a2a45090019-d155802ca98a-3 for ; Thu, 09 Apr 2026 17:16:45 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso13160625e9.1 for ; Thu, 09 Apr 2026 08:16:45 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 08:16:44 -0700 (PDT) Message-ID: Date: Thu, 9 Apr 2026 17:16:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 00.9/16] x86/CPUID: enable AVX10 leaf From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775747805-54364152-F06AC54C/0/0 X-purgate-type: clean X-purgate-size: 13690 This requires bumping the number of basic leaves we support. Apart from this the logic is modeled as closely as possible after that of leaf 7 handling. Signed-off-by: Jan Beulich --- The gen-cpuid.py adjustment is merely the minimum needed. It's not really clear to me whether someone turning off e.g. AVX512BW might then also validly expect AVX10 to be turned off. Do we want to synthesize AVX10 in the (max?) policies when all necessary AVX512* features are available, thus allowing migration from an AVX10 host to a suitable non-AVX10 one? The prior vsz bits are now defined as reserved-at-1: No idea yet how to represent this properly. How a toolstack side equivalent (if any) of the init_dom0_cpuid_policy() change would look like is entirely unclear to me. How much should we take from the max policy, and how much should we permit/require the user to specify (and how would the latter look like)? While, as per a comment next to the call site of recalculate_cpuid_policy(), recalculate_*() are supposed to go away when x86_cpu_policies_are_compatible() is complete, some of the checking done in recalculate_misc() really wouldn't below there. We'd need another "is self-consistent" checking function. --- v4: Drop all traces of AVX10/256. Add max_subleaf check to x86_cpu_policies_are_compatible(). Add/adjust vsz checks in recalculate_misc(). In the max policies, synthesize AVX512* when AVX10 is available. v3: Re-base. v2: Add logic to init_dom0_cpuid_policy(). Drop vsz128 field. Re-base. --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -211,7 +211,7 @@ static void recalculate_xstate(struct cp if ( p->feat.mpx ) xstates |= X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; - if ( p->feat.avx512f ) + if ( p->feat.avx512f || p->feat.avx10 ) xstates |= X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM; if ( p->feat.pku ) @@ -272,6 +272,18 @@ static void recalculate_misc(struct cpu_ p->basic.raw[0xc] = EMPTY_LEAF; + zero_leaves(p->basic.raw, 0xe, 0x23); + + p->avx10.raw[0].b &= 0x000700ff; + p->avx10.raw[0].c = 0; + p->avx10.raw[0].d = 0; + if ( !p->feat.avx10 || !p->avx10.version || + !p->avx10.vsz512 || !p->avx10.vsz256 || !p->avx10.vsz128 ) + { + p->feat.avx10 = false; + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); + } + p->extd.e1d &= ~CPUID_COMMON_1D_FEATURES; /* Most of Power/RAS hidden from guests. */ @@ -400,6 +412,7 @@ static void __init guest_common_max_leav { p->basic.max_leaf = ARRAY_SIZE(p->basic.raw) - 1; p->feat.max_subleaf = ARRAY_SIZE(p->feat.raw) - 1; + p->avx10.max_subleaf = ARRAY_SIZE(p->avx10.raw) - 1; p->extd.max_leaf = 0x80000000U + ARRAY_SIZE(p->extd.raw) - 1; } @@ -408,6 +421,7 @@ static void __init guest_common_default_ { p->basic.max_leaf = host_cpu_policy.basic.max_leaf; p->feat.max_subleaf = host_cpu_policy.feat.max_subleaf; + p->avx10.max_subleaf = host_cpu_policy.avx10.max_subleaf; p->extd.max_leaf = host_cpu_policy.extd.max_leaf; } @@ -503,6 +517,28 @@ static void __init guest_common_max_feat * function correctly when migrated here, even if ERMS isn't available. */ __set_bit(X86_FEATURE_ERMS, fs); + + /* + * AVX10 is merely a re-declaration of a combination of AVX512 features. + * Synthesize the latter from the former, when available. Doing it the + * other way around would also require synthesizing the AVX10 CPUID leaf. + */ + if ( test_bit(X86_FEATURE_AVX10, fs) ) + { + __set_bit(X86_FEATURE_AVX512F, fs); + __set_bit(X86_FEATURE_AVX512VL, fs); + __set_bit(X86_FEATURE_AVX512BW, fs); + __set_bit(X86_FEATURE_AVX512DQ, fs); + __set_bit(X86_FEATURE_AVX512_BF16, fs); + __set_bit(X86_FEATURE_AVX512_FP16, fs); + __set_bit(X86_FEATURE_AVX512CD, fs); + __set_bit(X86_FEATURE_AVX512_BITALG, fs); + __set_bit(X86_FEATURE_AVX512_IFMA, fs); + __set_bit(X86_FEATURE_AVX512_VBMI, fs); + __set_bit(X86_FEATURE_AVX512_VBMI2, fs); + __set_bit(X86_FEATURE_AVX512_VNNI, fs); + __set_bit(X86_FEATURE_AVX512_VPOPCNTDQ, fs); + } } static void __init guest_common_default_feature_adjustments(uint32_t *fs) @@ -966,6 +1002,7 @@ void recalculate_cpuid_policy(struct dom p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf); + p->avx10.max_subleaf = min(p->avx10.max_subleaf, max->avx10.max_subleaf); p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff, ((p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) @@ -1012,6 +1049,8 @@ void recalculate_cpuid_policy(struct dom if ( p->basic.max_leaf < XSTATE_CPUID ) __clear_bit(X86_FEATURE_XSAVE, fs); + if ( p->basic.max_leaf < 0x24 ) + __clear_bit(X86_FEATURE_AVX10, fs); sanitise_featureset(fs); @@ -1081,9 +1120,18 @@ void __init init_dom0_cpuid_policy(struc /* Apply dom0-cpuid= command line settings, if provided. */ if ( dom0_cpuid_cmdline ) { + const struct cpu_policy *max = is_pv_domain(d) + ? (IS_ENABLED(CONFIG_PV) ? &pv_max_cpu_policy : NULL) + : (IS_ENABLED(CONFIG_HVM) ? &hvm_max_cpu_policy : NULL); uint32_t fs[FSCAPINTS]; unsigned int i; + if ( !max ) + { + ASSERT_UNREACHABLE(); + return; + } + x86_cpu_policy_to_featureset(p, fs); for ( i = 0; i < ARRAY_SIZE(fs); ++i ) @@ -1093,6 +1141,13 @@ void __init init_dom0_cpuid_policy(struc } x86_cpu_featureset_to_policy(fs, p); + + /* + * Default-off features with their own leaves need those leaves + * re-populated from the max policy. + */ + if ( p->feat.avx10 ) + p->avx10 = max->avx10; } /* @@ -1125,6 +1180,8 @@ static void __init __maybe_unused build_ sizeof(raw_cpu_policy.feat.raw)); BUILD_BUG_ON(sizeof(raw_cpu_policy.xstate) != sizeof(raw_cpu_policy.xstate.raw)); + BUILD_BUG_ON(sizeof(raw_cpu_policy.avx10) != + sizeof(raw_cpu_policy.avx10.raw)); BUILD_BUG_ON(sizeof(raw_cpu_policy.extd) != sizeof(raw_cpu_policy.extd.raw)); } --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -226,6 +226,15 @@ void guest_cpuid(const struct vcpu *v, u *res = array_access_nospec(p->xstate.raw, subleaf); break; + case 0x24: + ASSERT(p->avx10.max_subleaf < ARRAY_SIZE(p->avx10.raw)); + if ( subleaf > min_t(uint32_t, p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1) ) + return; + + *res = array_access_nospec(p->avx10.raw, subleaf); + break; + default: *res = array_access_nospec(p->basic.raw, leaf); break; --- a/xen/arch/x86/lib/cpu-policy/copy-to-buffer.c +++ b/xen/arch/x86/lib/cpu-policy/copy-to-buffer.c @@ -123,6 +123,13 @@ int x86_cpuid_copy_to_buffer(const struc break; } + case 0x24: + for ( subleaf = 0; + subleaf <= MIN(p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1); ++subleaf ) + COPY_LEAF(leaf, subleaf, &p->avx10.raw[subleaf]); + break; + default: COPY_LEAF(leaf, XEN_CPUID_NO_SUBLEAF, &p->basic.raw[leaf]); break; --- a/xen/arch/x86/lib/cpu-policy/copy-from-buffer.c +++ b/xen/arch/x86/lib/cpu-policy/copy-from-buffer.c @@ -108,6 +108,13 @@ int x86_cpuid_copy_from_buffer(struct cp array_access_nospec(p->xstate.raw, data.subleaf) = l; break; + case 0x24: + if ( data.subleaf >= ARRAY_SIZE(p->avx10.raw) ) + goto out_of_range; + + array_access_nospec(p->avx10.raw, data.subleaf) = l; + break; + default: if ( data.subleaf != XEN_CPUID_NO_SUBLEAF ) goto out_of_range; --- a/xen/arch/x86/lib/cpu-policy/cpuid.c +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c @@ -125,6 +125,7 @@ void x86_cpu_policy_fill_native(struct c switch ( i ) { case 0x4: case 0x7: case 0xb: case 0xd: + case 0x24: /* Multi-invocation leaves. Deferred. */ continue; } @@ -218,6 +219,15 @@ void x86_cpu_policy_fill_native(struct c } } + if ( p->basic.max_leaf >= 0x24 ) + { + cpuid_count_leaf(0x24, 0, &p->avx10.raw[0]); + + for ( i = 1; i <= MIN(p->avx10.max_subleaf, + ARRAY_SIZE(p->avx10.raw) - 1); ++i ) + cpuid_count_leaf(0x24, i, &p->avx10.raw[i]); + } + /* Extended leaves. */ cpuid_leaf(0x80000000U, &p->extd.raw[0]); for ( i = 1; i <= MIN(p->extd.max_leaf & 0xffffU, @@ -287,6 +297,9 @@ void x86_cpu_policy_clear_out_of_range_l ARRAY_SIZE(p->xstate.raw) - 1); } + if ( p->basic.max_leaf < 0x24 ) + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); + zero_leaves(p->extd.raw, ((p->extd.max_leaf >> 16) == 0x8000 ? (p->extd.max_leaf & 0xffff) + 1 : 0), @@ -299,6 +312,8 @@ void __init x86_cpu_policy_bound_max_lea min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1); p->feat.max_subleaf = min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1); + p->avx10.max_subleaf = + min_t(uint32_t, p->avx10.max_subleaf, ARRAY_SIZE(p->avx10.raw) - 1); p->extd.max_leaf = 0x80000000U | min_t(uint32_t, p->extd.max_leaf & 0xffff, ARRAY_SIZE(p->extd.raw) - 1); } @@ -326,6 +341,8 @@ void x86_cpu_policy_shrink_max_leaves(st */ p->basic.raw[0xd] = p->xstate.raw[0]; + p->basic.raw[0x24] = p->avx10.raw[0]; + for ( i = p->basic.max_leaf; i; --i ) if ( p->basic.raw[i].a | p->basic.raw[i].b | p->basic.raw[i].c | p->basic.raw[i].d ) --- a/xen/arch/x86/lib/cpu-policy/policy.c +++ b/xen/arch/x86/lib/cpu-policy/policy.c @@ -24,6 +24,10 @@ int x86_cpu_policies_are_compatible(cons if ( guest->feat.max_subleaf > host->feat.max_subleaf ) FAIL_CPUID(7, 0); + if ( guest->avx10.version > host->avx10.version || + guest->avx10.max_subleaf > host->avx10.max_subleaf ) + FAIL_CPUID(0x24, 0); + if ( guest->extd.max_leaf > host->extd.max_leaf ) FAIL_CPUID(0x80000000U, NA); --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -366,6 +366,7 @@ XEN_CPUFEATURE(PREFETCHI, 15*32 XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructions */ XEN_CPUFEATURE(UIRET_UIF, 15*32+17) /* UIRET updates UIF */ XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow Stacks safe to use */ +XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector ISA */ XEN_CPUFEATURE(SLSM, 15*32+24) /* Static Lockstep Mode */ /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ --- a/xen/include/xen/lib/x86/cpu-policy.h +++ b/xen/include/xen/lib/x86/cpu-policy.h @@ -59,11 +59,12 @@ unsigned int x86_cpuid_lookup_vendor(uin */ const char *x86_cpuid_vendor_to_str(unsigned int vendor); -#define CPUID_GUEST_NR_BASIC (0xdu + 1) +#define CPUID_GUEST_NR_BASIC (0x24u + 1) #define CPUID_GUEST_NR_CACHE (5u + 1) #define CPUID_GUEST_NR_FEAT (2u + 1) #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) +#define CPUID_GUEST_NR_AVX10 (0u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ @@ -264,6 +265,19 @@ struct cpu_policy } comp[CPUID_GUEST_NR_XSTATE]; } xstate; + /* Structured AVX10 information leaf: 0x000000024[xx] */ + union { + struct cpuid_leaf raw[CPUID_GUEST_NR_AVX10]; + struct { + /* Subleaf 0. */ + uint32_t max_subleaf; + uint32_t version:8, :8; + bool vsz128:1, vsz256:1, vsz512:1; + uint32_t :13; + uint32_t /* c */:32, /* d */:32; + }; + } avx10; + /* Extended leaves: 0x800000xx */ union { struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD]; --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -294,7 +294,7 @@ def crunch_numbers(state): # enabled. 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Thu, 09 Apr 2026 08:19:18 -0700 (PDT) Message-ID: <03942243-c825-4846-9043-997bffc7daea@suse.com> Date: Thu, 9 Apr 2026 17:19:15 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 00/16] x86: support AVX10 From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775747959-AE725CD1-7A628FE9/0/0 X-purgate-type: clean X-purgate-size: 1886 On 09.04.2026 16:59, Jan Beulich wrote: > AVX10.1 is just a re-branding of certain AVX512 (sub)features, i.e. > adds no new instructions. Therefore it's mostly relaxation that needs > doing. Luckily the 256-bit-only case and an unnecessary restriction on > the mask register insns was taken out again, simplifying the actual > emulator adjustments quite a bit. > > AVX10.2 is adding quite a few new insns, support for which is roughly > added chapter-wise as the spec has them (perhaps not in the order of > the chapters there). > > While it probably could be re-based ahead, the series in this form > depends on the previously submitted "[PATCH v5 0/3] x86/CPUID: leaf > pruning" and parts of whatever is left of "[PATCH v9 00/10] x86emul: > misc additions". > > I've tried to be very careful in rebasing ahead of other emulator > patches I've been carrying, but almost all testing I've done is with > all of those collectively in place. As you may have noticed, I screwed up the numbering. Hence ... > 01: x86/CPUID: enable AVX10 leaf ... this is 00.9, and everything else is off-by-1 (and there's no 16/16). I'm sorry for that. Jan > 02: x86emul: support SIMD MOVRS > 03: x86emul: support AVX10.2 forms of SM4 insns > 04: x86emul: support AVX10.1 > 05: x86emul/test: use simd_check_avx512*() in main() > 06: x86emul/test: drop cpu_has_avx512vl > 07: x86emul: AVX10.1 testing > 08: x86emul/test: engage AVX512VL via command line option > 09: x86/CPUID: enable AVX10.2 sub-leaf > 10: x86emul: support AVX10.2 scalar compare insns > 11: x86emul: support AVX10.2 partial copy insns > 12: x86emul: support AVX10.2 media insns > 13: x86emul: support AVX10.2 minmax insns > 14: x86emul: support AVX10.2 BFloat16 insns > 15: x86emul: support AVX10.2 saturating convert insns > 16: x86emul: support other AVX10.2 convert insns > > Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 09 15:27:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 15:27:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277904.1562988 (Exim 4.92) (envelope-from ) id 1wArHs-0003qT-PE; Thu, 09 Apr 2026 15:27:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277904.1562988; Thu, 09 Apr 2026 15:27:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wArHs-0003qM-Ks; Thu, 09 Apr 2026 15:27:20 +0000 Received: by outflank-mailman (input) for mailman id 1277904; Thu, 09 Apr 2026 15:27:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wArHr-0003qG-AY for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 15:27:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wArHp-009itP-4p for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:27:18 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7c543-e002-0a2a0a5209dd-0a2a4502ce00-28 for ; Thu, 09 Apr 2026 17:27:18 +0200 Received: from [136.143.188.51] (helo=sender4-of-o51.zoho.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7c554-42fa-0a2a45020019-888fbc3352a8-3 for ; Thu, 09 Apr 2026 17:27:17 +0200 Received: by mx.zohomail.com with SMTPS id 1775748428998910.0956839380316; Thu, 9 Apr 2026 08:27:08 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=zoho header.d=apertussolutions.com header.i="dpsmith@apertussolutions.com" header.h="Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Content-Type:Content-Transfer-Encoding" ARC-Seal: i=1; a=rsa-sha256; t=1775748430; cv=none; d=zohomail.com; s=zohoarc; b=Cy8g3lL6lY46PhF/3NGIFoENrtRTDZ0xB4SNaykDRCTBGS8JUa8+GNXLg72fye0eXZ5IVFNXnd0x7yWwuhrrAefcpEXiH1Z5G4XFFGF57+qFk75BkGocN2vm2kl2pXrzlAUUaON/tqJ0lmpt5LwwNQkosObV+8oVyl1bFq7QH/I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775748430; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=6slf66+/mwfKM9Qm1+2ujiAPSu9zDQBkQ60V+Wo3NDI=; b=MPx0lfydDU2NQ3jiYBJgOMdYAvTraStkHuDDwPUU348ELLTzNO0WfuoPEa8myVefu/9W/0+sSxGLvFulSG6/y7+d2ovAygH7J809bNTJ8Hypo1UsqyYXVyGRG6h5PVSvFF1fh4y6BnraNTJv+MYwbuqIsTvb8SPG19kg7/GYaJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=apertussolutions.com; spf=pass smtp.mailfrom=dpsmith@apertussolutions.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1775748430; s=zoho; d=apertussolutions.com; i=dpsmith@apertussolutions.com; h=Message-ID:Date:Date:MIME-Version:Subject:Subject:To:To:Cc:Cc:References:From:From:In-Reply-To:Content-Type:Content-Transfer-Encoding:Message-Id:Reply-To; bh=6slf66+/mwfKM9Qm1+2ujiAPSu9zDQBkQ60V+Wo3NDI=; b=T49IPYZBHA0M9sLtVqPmMZgLSfDYL8zya6UkbczNf8t4qQVCyuqeNPoY8iGVzmbp mvotponcl9RJJMqTw53/nlGAEKYOfTa3tXixn+UmuyTtb5NTIEBWbc5jHAAHefoUiBR zwga38HfRVPR2s1TXE9K9cef3TpOaahcqRM8OcRM= Message-ID: Date: Thu, 9 Apr 2026 11:27:07 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/7] vpci: add SR-IOV support for PVH Dom0 Content-Language: en-US To: Mykyta Poturai , "xen-devel@lists.xenproject.org" Cc: Stewart Hildebrand , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Jason Andryuk References: From: "Daniel P. Smith" Autocrypt: addr=dpsmith@apertussolutions.com; keydata= xsJuBFYrueARCACPWL3r2bCSI6TrkIE/aRzj4ksFYPzLkJbWLZGBRlv7HQLvs6i/K4y/b4fs JDq5eL4e9BdfdnZm/b+K+Gweyc0Px2poDWwKVTFFRgxKWq9R7McwNnvuZ4nyXJBVn7PTEn/Z G7D08iZg94ZsnUdeXfgYdJrqmdiWA6iX9u84ARHUtb0K4r5WpLUMcQ8PVmnv1vVrs/3Wy/Rb foxebZNWxgUiSx+d02e3Ad0aEIur1SYXXv71mqKwyi/40CBSHq2jk9eF6zmEhaoFi5+MMMgX X0i+fcBkvmT0N88W4yCtHhHQds+RDbTPLGm8NBVJb7R5zbJmuQX7ADBVuNYIU8hx3dF3AQCm 601w0oZJ0jGOV1vXQgHqZYJGHg5wuImhzhZJCRESIwf+PJxik7TJOgBicko1hUVOxJBZxoe0 x+/SO6tn+s8wKlR1Yxy8gYN9ZRqV2I83JsWZbBXMG1kLzV0SAfk/wq0PAppA1VzrQ3JqXg7T MZ3tFgxvxkYqUP11tO2vrgys+InkZAfjBVMjqXWHokyQPpihUaW0a8mr40w9Qui6DoJj7+Gg DtDWDZ7Zcn2hoyrypuht88rUuh1JuGYD434Q6qwQjUDlY+4lgrUxKdMD8R7JJWt38MNlTWvy rMVscvZUNc7gxcmnFUn41NPSKqzp4DDRbmf37Iz/fL7i01y7IGFTXaYaF3nEACyIUTr/xxi+ MD1FVtEtJncZNkRn7WBcVFGKMAf+NEeaeQdGYQ6mGgk++i/vJZxkrC/a9ZXme7BhWRP485U5 sXpFoGjdpMn4VlC7TFk2qsnJi3yF0pXCKVRy1ukEls8o+4PF2JiKrtkCrWCimB6jxGPIG3lk 3SuKVS/din3RHz+7Sr1lXWFcGYDENmPd/jTwr1A1FiHrSj+u21hnJEHi8eTa9029F1KRfocp ig+k0zUEKmFPDabpanI323O5Tahsy7hwf2WOQwTDLvQ+eqQu40wbb6NocmCNFjtRhNZWGKJS b5GrGDGu/No5U6w73adighEuNcCSNBsLyUe48CE0uTO7eAL6Vd+2k28ezi6XY4Y0mgASJslb NwW54LzSSM0uRGFuaWVsIFAuIFNtaXRoIDxkcHNtaXRoQGFwZXJ0dXNzb2x1dGlvbnMuY29t PsJ6BBMRCAAiBQJWK7ngAhsjBgsJCAcDAgYVCAIJCgsEFgIDAQIeAQIXgAAKCRBTc6WbYpR8 KrQ9AP94+xjtFfJ8gj5c7PVx06Zv9rcmFUqQspZ5wSEkvxOuQQEAg6qEsPYegI7iByLVzNEg 7B7fUG7pqWIfMqFwFghYhQzOwU0EViu54BAIAL6MXXNlrJ5tRUf+KMBtVz1LJQZRt/uxWrCb T06nZjnbp2UcceuYNbISOVHGXTzu38r55YzpkEA8eURQf+5hjtvlrOiHxvpD+Z6WcpV6rrMB kcAKWiZTQihW2HoGgVB3gwG9dCh+n0X5OzliAMiGK2a5iqnIZi3o0SeW6aME94bSkTkuj6/7 OmH9KAzK8UnlhfkoMg3tXW8L6/5CGn2VyrjbB/rcrbIR4mCQ+yCUlocuOjFCJhBd10AG1IcX OXUa/ux+/OAV9S5mkr5Fh3kQxYCTcTRt8RY7+of9RGBk10txi94dXiU2SjPbassvagvu/hEi twNHms8rpkSJIeeq0/cAAwUH/jV3tXpaYubwcL2tkk5ggL9Do+/Yo2WPzXmbp8vDiJPCvSJW rz2NrYkd/RoX+42DGqjfu8Y04F9XehN1zZAFmCDUqBMa4tEJ7kOT1FKJTqzNVcgeKNBGcT7q 27+wsqbAerM4A0X/F/ctjYcKwNtXck1Bmd/T8kiw2IgyeOC+cjyTOSwKJr2gCwZXGi5g+2V8 NhJ8n72ISPnOh5KCMoAJXmCF+SYaJ6hIIFARmnuessCIGw4ylCRIU/TiXK94soilx5aCqb1z ke943EIUts9CmFAHt8cNPYOPRd20pPu4VFNBuT4fv9Ys0iv0XGCEP+sos7/pgJ3gV3pCOric p15jV4PCYQQYEQgACQUCViu54AIbDAAKCRBTc6WbYpR8Khu7AP9NJrBUn94C/3PeNbtQlEGZ NV46Mx5HF0P27lH3sFpNrwD/dVdZ5PCnHQYBZ287ZxVfVr4Zuxjo5yJbRjT93Hl0vMY= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ZohoMailClient: External X-purgate-ID: tlsNG-720697/1775748438-AFF29CD1-A1C1033B/0/0 X-purgate-type: clean X-purgate-size: 1721 On 4/9/26 10:01, Mykyta Poturai wrote: > From: Stewart Hildebrand > > This code is expected to only be used by privileged domains, > unprivileged domains should not get access to the SR-IOV capability. > > Implement RW handlers for PCI_SRIOV_CTRL register to dynamically > map/unmap VF BARS. Recalculate BAR sizes before mapping VFs to account > for possible changes in the system page size register. Also force VFs to > always use emulated reads for command register, this is needed to > prevent some drivers accidentally unmapping BARs. Discovery of VFs is > done by Dom0, which must register them with Xen. > > Signed-off-by: Roger Pau Monné > Signed-off-by: Stewart Hildebrand > Signed-off-by: Mykyta Poturai > --- > v2->v3: > * rework adding VFs with multiple mapping operations support > * use private.h > * style fixes > * fixup cleanup_sriov > * emulate command register read for VFs > > v1->v2: > * switch to VF discovery by Xen > * fix sequential vpci_modify_bars calls > * move documentation changes to a separate commit > --- I have only cursory read this patch, but it got me thinking, which I'm still in the middle of completing my questions. Figured I will pose it to the community for other's opinions as well. From what I have looked at this far, it is just wiring up the SRIOV under the existing PCI access controls. It's possible to just provide a specific label to the device to differentiate in policy, but I am wondering if there might want to be a further degree of fine-grained access controls over SRIOV devices? V/r, Daniel P. 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Smith" , "xen-devel@lists.xenproject.org" References: <9ac96559ed00257f347bd61b1e074fc3f6ce8a32.1774871881.git.mykyta_poturai@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775748859-8A15541E-A325F571/0/0 X-purgate-type: clean X-purgate-size: 793 On 09.04.2026 16:34, Mykyta Poturai wrote: > On 3/30/26 15:28, Jan Beulich wrote: >> On 30.03.2026 13:59, Mykyta Poturai wrote: >>> --- a/xen/common/Kconfig >>> +++ b/xen/common/Kconfig >>> @@ -638,9 +638,9 @@ config SYSTEM_SUSPEND >>> If unsure, say N. >>> >>> config CPU_HOTPLUG >>> - bool "CPU online/offline support" >>> - depends on X86 >>> - default y >>> + bool "CPU online/offline support" if EXPERT || X86 >> >> Why not just EXPERT? > > Should it be marked as EXPERT on x86? I considered that if the option > was non configurable (always enabled), it should stay enabled by default > and always visible. As you say, it wasn't configurable before. Imo that's a good sign that, at least for starters, we should limit its disabling to experts. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM9PR03MB7526.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6614684a-d48f-45ac-9200-08de965077ca X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 15:55:48.4284 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lS67aZYnXbTk9EexmvHQsh8SI6OWSAwhpme+fh7kFjk/8/qwgT+SSFm57vjKq2oRsVCW59jXlStGogIAAMWxwTY2+w6JksfEcK2U6y63Upc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR03MB8554 X-purgate-ID: tlsNG-4011c0/1775750150-0FD420B1-D8A2D9CA/0/0 X-purgate-type: clean X-purgate-size: 1132 The statement 'return ERR_PTR(-ENOENT);' on the final line of the function 'hypfs_get_entry_rel()' is unreachable because the logic within the infinit= e loop 'for (;;)' provides all possible exit paths for the function. So there is no execution path to exit the loop and reach the final that statement. Remove that statement. This also fixes MISRA C Rule 2.1 which states: "A project shall not contain unreachable code". Signed-off-by: Dmytro Prokopchuk --- Test CI pipeline: https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2440991088 --- xen/common/hypfs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/xen/common/hypfs.c b/xen/common/hypfs.c index cdf4ee0171..fea74d66e1 100644 --- a/xen/common/hypfs.c +++ b/xen/common/hypfs.c @@ -347,8 +347,6 @@ static struct hypfs_entry *hypfs_get_entry_rel(struct h= ypfs_entry_dir *dir, path =3D end + 1; dir =3D container_of(entry, struct hypfs_entry_dir, e); } - - return ERR_PTR(-ENOENT); } =20 static struct hypfs_entry *hypfs_get_entry(const char *path) --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 16:21:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 16:21:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277970.1563035 (Exim 4.92) (envelope-from ) id 1wAs7y-0006an-Gj; Thu, 09 Apr 2026 16:21:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277970.1563035; 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a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775751667; x=1776021667; bh=0UnZsd6VMv3nhahDJTmKjpYZpYAGnJoqucRzautn7QA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=qbefgWiqvZErQ9/ybAH4YbWRSO4lAPnBrUa9n60XJtZ+FaQUBpuwIZGQtJ7wf6jAd 20TesU2SbQbkXhU62M5LdTgbHooW1tgnnR7gwxu26BfYWdhY6aMCADgQgzedyVCZ87 66eKLmn73R33tJZyoTsN0uZiJdZOjKJl+RUuKfNbWbn0H5io3aBCgN+YDWwWFKxQdU tfuefmUyuxSETWquPkU3CiwC2owPqjVYKu45uqaEYjJydRabwHdLB6ltPf3+tDr3Dj tW6PwzhDXhM+d8lIIDRo4y7Q1DYq+x06dbvwP3paBdQq68ySheMhO+KbuCW4/e0bRX x89LfC7f55tSQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775751667; x=1776012167; i=thierry.escande@vates.tech; bh=0UnZsd6VMv3nhahDJTmKjpYZpYAGnJoqucRzautn7QA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=UReoS+ahOd18SgPZmRFWbbfx0xIgFHLHhSfxKjnlXGUAz8e9dg+UGV6vPiv4EVfPC oucDswE963viLI8gwfSxOx70oy6L+EiNoIOxpwH8pGE+FWaSvLPOEK1bRfDVrfCWFQ cePt3vjSVZW1vUH7M+lW2EVq6+j/HyFFPCWZTnToXJ3+G7x8Bo+HbsnllxIcdhsVnZ JmwZJh5cQdd0yA3ROgHTrEW2fcsaxMtTUNMUPVJx+kroQtbbd83VLrzqGBUZyOIJzp nc4MyShmXadcHSABuafEuOlqgfQVF2Stk6VFKI3BgLM5Fdzo6WVP6gNoYqG6ovFcvG 7JinwSTsMZz8A== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v2=202/3]=20libxl:=20Allow=20PCI=20device=20passthrough=20using=20-device=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775751666400 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260409162000.1102680-3-thierry.escande@vates.tech> In-Reply-To: <20260409162000.1102680-1-thierry.escande@vates.tech> References: <20260409162000.1102680-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.2d68c2e86b134086aff945f8d500e260?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 16:21:07 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775751668-AE926CD1-767AF0B8/0/0 X-purgate-type: clean X-purgate-size: 8941 This change makes use of the new option 'hotplug' for host PCI devices passthrough'd to the guest. If hotplug=0 is used in the pci device configuration table, the device will be attached to the guest using the Qemu command line as '-device xen-pci-passthrough,hostaddr=...' The host device configuration is passed to the -device option as a json array, just like it's done for hotplug using QMP. The json array is created by a new internal function libxl__device_pci_get_qmp_json() that is also used by pci_add_qmp_device_add(). Then, instead of sending the 'device_add' command, the device_add callback is called to perform the 'query-pci' check to make sure the passthrough'd device is present. In the same way at shutdown, the device is not removed using QMP and only the pci_remove_done() function is called. As with QMP, the use of the 'hotplug=0' option honors the 'seize' option by adding the PCI device to the assignable list if needed. Example use: pci = [ "00:03.0,seize=1,hotplug=0" ] Signed-off-by: Thierry Escande --- v2: - Add support for YAJL json parser --- tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 80 +++++++++++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 2 + tools/libs/light/libxl_pci.c | 41 ++++++++++++---- 4 files changed, 114 insertions(+), 10 deletions(-) diff --git a/tools/include/libxl.h b/tools/include/libxl.h index 7c098edab6..66fb07ad67 100644 --- a/tools/include/libxl.h +++ b/tools/include/libxl.h @@ -2666,6 +2666,7 @@ int libxl_device_pci_assignable_add(libxl_ctx *ctx, libxl_device_pci *pci, int r int libxl_device_pci_assignable_remove(libxl_ctx *ctx, libxl_device_pci *pci, int rebind); libxl_device_pci *libxl_device_pci_assignable_list(libxl_ctx *ctx, int *num); void libxl_device_pci_assignable_list_free(libxl_device_pci *list, int num); +bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci); /* CPUID handling */ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str); diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c index 511ec76a65..4f4781b36d 100644 --- a/tools/libs/light/libxl_dm.c +++ b/tools/libs/light/libxl_dm.c @@ -1169,6 +1169,86 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, } } } + + if (guest_config->num_pcidevs) { + libxl_ctx *ctx = libxl__gc_owner(gc); + libxl_device_pci *pci; + libxl__json_object *qmp_json; + char *json_str; +#ifdef HAVE_LIBJSONC + json_object *jso; + const char *buf; +#elif defined(HAVE_LIBYAJL) + yajl_gen hand; + /* memory for 'buf' is owned by 'hand' */ + const unsigned char *buf; + libxl_yajl_length len; +#else +# error Missing JSON library +#endif + + for (i = 0; i < guest_config->num_pcidevs; i++) { + pci = &guest_config->pcidevs[i]; + + if (pci->hotplug) + continue; + + if (!libxl_pci_assignable(ctx, pci) && pci->seize) { + rc = libxl_device_pci_assignable_add(ctx, pci, 1); + if (rc) + return rc; + } + + qmp_json = libxl__device_pci_get_qmp_json(gc, pci); + +#ifdef HAVE_LIBJSONC + rc = libxl__json_object_to_json_object(gc, &jso, qmp_json); + if (rc) + return rc; + + buf = json_object_to_json_string_ext(jso, + JSON_C_TO_STRING_PLAIN); + if (!buf) { + json_object_put(jso); + return ERROR_NOMEM; + } +#elif defined(HAVE_LIBYAJL) + hand = libxl_yajl_gen_alloc(NULL); + if (!hand) { + return ERROR_NOMEM; + } +#if HAVE_YAJL_V2 + /* Disable beautify for data sent to QEMU */ + yajl_gen_config(hand, yajl_gen_beautify, 0); +#endif + + rc = libxl__json_object_to_yajl_gen(gc, hand, qmp_json); + if (rc) { + yajl_gen_free(hand); + return rc; + } + + rc = yajl_gen_get_buf(hand, &buf, &len); + if (rc != yajl_gen_status_ok) { + yajl_gen_free(hand); + return rc; + } +#endif + + json_str = libxl__strdup(gc, (const char *)buf); + if (json_str) + flexarray_vappend(dm_args, "-device", json_str, NULL); + +#ifdef HAVE_LIBJSONC + json_object_put(jso); +#elif defined(HAVE_LIBYAJL) + yajl_gen_free(hand); +#endif + + if (!json_str) + return ERROR_NOMEM; + } + } } if (libxl_defbool_val(b_info->u.hvm.nographic) && (!sdl && !vnc)) { diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h index b65e0064b9..06b5a14409 100644 --- a/tools/libs/light/libxl_internal.h +++ b/tools/libs/light/libxl_internal.h @@ -1729,6 +1729,8 @@ _hidden int libxl__device_pci_setdefault(libxl__gc *gc, uint32_t domid, libxl_device_pci *pci, bool hotplug); _hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, const libxl_domain_config *d_config); +_hidden libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci); /* from libxl_dtdev */ diff --git a/tools/libs/light/libxl_pci.c b/tools/libs/light/libxl_pci.c index 49d272d0de..3ef2c43412 100644 --- a/tools/libs/light/libxl_pci.c +++ b/tools/libs/light/libxl_pci.c @@ -1098,16 +1098,10 @@ out: pci_add_dm_done(egc, pas, rc); /* must be last */ } -static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci) { - STATE_AO_GC(pas->aodev->ao); libxl__json_object *args = NULL; - int rc; - - /* Convenience aliases */ - libxl_domid domid = pas->domid; - libxl_device_pci *pci = &pas->pci; - libxl__ev_qmp *const qmp = &pas->qmp; libxl__qmp_param_add_string(gc, &args, "driver", "xen-pci-passthrough"); @@ -1134,11 +1128,30 @@ static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) if (pci->permissive) libxl__qmp_param_add_bool(gc, &args, "permissive", true); + return args; +} + +static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +{ + STATE_AO_GC(pas->aodev->ao); + libxl__json_object *args = NULL; + int rc = 0; + + /* Convenience aliases */ + libxl_domid domid = pas->domid; + libxl_device_pci *pci = &pas->pci; + libxl__ev_qmp *const qmp = &pas->qmp; + + args = libxl__device_pci_get_qmp_json(gc, pci); + qmp->ao = pas->aodev->ao; qmp->domid = domid; qmp->payload_fd = -1; qmp->callback = pci_add_qmp_device_add_cb; - rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + if (pci->hotplug) + rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + else + pci_add_qmp_device_add_cb(egc, qmp, NULL, 0); if (rc) goto out; return; @@ -1509,7 +1522,7 @@ int libxl_device_pci_add(libxl_ctx *ctx, uint32_t domid, return AO_INPROGRESS; } -static bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) +bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) { libxl_device_pci *pcis; int num; @@ -1820,6 +1833,14 @@ static void do_pci_remove(libxl__egc *egc, pci_remove_state *prs) libxl_domain_type type = libxl__domain_type(gc, domid); libxl_device_pci *pci = &prs->pci; int rc, num; + + /* Passthrough'd device has been passed to Qemu command line so there is + * no need to remove it via QMP */ + if (!pci->hotplug) { + pci_remove_done(egc, prs, 0); + return; + } + pcis = libxl_device_pci_list(ctx, domid, &num); if (!pcis) { rc = ERROR_FAIL; -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 16:21:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 16:21:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277969.1563027 (Exim 4.92) (envelope-from ) id 1wAs7v-0006Lp-87; Thu, 09 Apr 2026 16:21:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1277969.1563027; Thu, 09 Apr 2026 16:21:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAs7v-0006Li-4H; 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Thu, 9 Apr 2026 16:21:03 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 79112c74a4eb403bb19f7e2d994d5317; Thu, 09 Apr 2026 16:21:03 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775751663; x=1776021663; bh=Nz9cFB5Mcx1tT5bpJb3P1KzNsuuko5bfszc5bYglBPc=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=LSkNrZLdzHFgCWHDR4OlVLnNFiaF4Kw5htG77yaS9aPysISMCILfP+HQpgYMuEvYA LXbrAMd9LzWzgU3LiRZxyS9uREgEvSjZcZhUrUEcvbr44nvVP44x8oLj8LJ0BgNSpH 4jUmRLObZfWGdmC/LnqP76PYgyvAgXGF6SXMueyJrjXQ1MOl5ir+k2ZpPhjCHIV+oX xjeC813O3PL/JmUlh4YO0Tw1xcpVWYb/gqniBaqDKEGZcZDNMI2EjJfbZeId6qVpO0 US7HpKFXirzpRT4rZKEtCGKNWZZnpUKIp+8WkK3BIqwT3gxpkNkBnJoh4HvR5GGu3O ByWfZv3vw8EAg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775751663; x=1776012163; i=thierry.escande@vates.tech; bh=Nz9cFB5Mcx1tT5bpJb3P1KzNsuuko5bfszc5bYglBPc=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=UhweX3OBt8mayspvrUrkiNjyHDQSwbhUVgmgFC7ItbpcV0Lmz000p0vSXDtH2J3+5 4JnKc0F91sND+7RALcebEHTaAuPn29IFxLu5NQDl2ZudvTnJhYSb01rtixKkjkXSWz rH8OCUXxl4MIOxEwPbjWfmE6qTe3TqANaMaSBX5wfFcUpA7fV8hqprgNB9Orgk/KFV 55BTsseTefHteKUpMVZWH4kcqXa28rzPnAustlvBFXbHLzUPTAzj2NInv4xDig12eD BXQpsRzf/KZNud/mBak3z0iM/3Kd25bvAxlfd/+T+8GI+A3WVotFbvfqAZbBiYHRWE tU+9e4jj7EhKg== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v2=201/3]=20xl:=20Add=20pci=20device=20hotplug=20option?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775751662747 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260409162000.1102680-2-thierry.escande@vates.tech> In-Reply-To: <20260409162000.1102680-1-thierry.escande@vates.tech> References: <20260409162000.1102680-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.79112c74a4eb403bb19f7e2d994d5317?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 16:21:03 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775751665-C481C0B1-8F0CA5CE/0/0 X-purgate-type: clean X-purgate-size: 2915 This option is used to passthrough PCI devices using the Qemu command line (-device driver,...) instead of the QMP hot-plug mechanism. This is needed for Q35 support since its PCI root bus doesn't support hotplugging. If not specified, the default behavior is to use hotplug via QMP. Signed-off-by: Thierry Escande --- v2: no change --- tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 ++ tools/xl/xl_parse.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl index a7893460f0..aca0e93793 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -922,6 +922,7 @@ libxl_device_pci = Struct("device_pci", [ ("seize", bool), ("rdm_policy", libxl_rdm_reserve_policy), ("name", string), + ("hotplug", bool), ]) libxl_device_rdm = Struct("device_rdm", [ diff --git a/tools/libs/util/libxlu_pci.c b/tools/libs/util/libxlu_pci.c index 294482c6d7..f6440c878b 100644 --- a/tools/libs/util/libxlu_pci.c +++ b/tools/libs/util/libxlu_pci.c @@ -192,6 +192,8 @@ int xlu_pci_parse_spec_string(XLU_Config *cfg, libxl_device_pci *pci, name_present = true; pci->name = strdup(val); if (!pci->name) ret = ERROR_NOMEM; + } else if (!strcmp(key, "hotplug")) { + pci->hotplug = atoi(val); } else { XLU__PCI_ERR(cfg, "Unknown PCI_SPEC_STRING option: %s", key); ret = ERROR_INVAL; diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 48c72dce9c..7ea2a76662 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -1361,6 +1361,7 @@ void parse_config_data(const char *config_source, int pci_msitranslate = 0; int pci_permissive = 0; int pci_seize = 0; + int pci_hotplug = 1; int i, e; int num_llc_colors; int num_xs_quota; @@ -1699,6 +1700,9 @@ void parse_config_data(const char *config_source, if (!xlu_cfg_get_long (config, "pci_seize", &l, 0)) pci_seize = l; + if (!xlu_cfg_get_long (config, "pci_hotplug", &l, 0)) + pci_hotplug = l; + if (!xlu_cfg_get_string(config, "rdm", &buf, 0)) { libxl_rdm_reserve rdm; if (!xlu_rdm_parse(config, &rdm, buf)) { @@ -1720,6 +1724,7 @@ void parse_config_data(const char *config_source, pci->power_mgmt = pci_power_mgmt; pci->permissive = pci_permissive; pci->seize = pci_seize; + pci->hotplug = pci_hotplug; /* * Like other pci option, the per-device policy always follows * the global policy by default. -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 16:21:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 16:21:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277968.1563017 (Exim 4.92) (envelope-from ) id 1wAs7r-00068k-05; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775751657; x=1776021657; bh=Qjx6OsI44qGGL/jcmYHV+NmV+OqiXfQQzBrw/BNMPf4=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=HofsryFQHdR+feHc5iaw9Zxa19cuNLhWrnJX31KeOiC0qXOV446YG5+Icjd0Po9dM Z/wAvlqhyXmNtO7zE7ILdIivK7YbJKKNvSg6dYP5xYgekjCiaDGSDbYun6k/n7fYz2 +834G6QEA6oCRkh226IbtZhK5CAr0SLLgjbf5VngNMcgU3bGjArB5qKi22NKWu+Tc+ J10fWO46UQHmLx0690MbRYKBg9PVNmarJMq7A3CoWSfgp3rpsIJb5bK4umfgJCXncL nfLR3om7+OU/xzyUuTyf1A+WcBFwwK0v2abj3oGOWQIijYWjE2UNr3PlmcQ5OJ9Fsc OmODCgkk8Qw4w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775751657; x=1776012157; i=thierry.escande@vates.tech; bh=Qjx6OsI44qGGL/jcmYHV+NmV+OqiXfQQzBrw/BNMPf4=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=urnu/pF++2Gd1Ga/OhMH0WCTMQZLOHoFATGfVsEWDefu5LfPHY26HWdwwAkW2ZfTk geYXYbXcUJcBZzFkZIBKpex/+UkNjTkOA3jlZTZG1X1lgTJbN/9RdvB3YRiEUjyavs LHqwgkGTrlTyKuc+1uDBvFdqkcx+GtApGXOzSoDz2f7+nV3WXL227Blaex6dGB6gRQ oY7p8vgebHaXDALmB79NDVQPpcF2WU7BoT9fxbcc0E7YOxd/z6pZwTRkK9U4QmTueP Kjptqrd7eOgwrq+6WcEwqW42l/Dhe4DtMuLW6LImpOV1krbkxOncC5cBtqVk3XKCfl p6nsnHA2T5wEQ== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v2=200/3]=20xl:=20Allow=20PCI=20devices=20to=20be=20passthrough'd=20via=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775751656801 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260409162000.1102680-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.f49911ee17314b0195681d17125076d7?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 16:20:57 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775751659-81756A3D-CD9AFF73/0/0 X-purgate-type: clean X-purgate-size: 2517 This series adds support for a new 'hotplug' option for PCI devices to be passthrough'd to guests. The current mechanism for device passthrough uses QMP device_add command to hot-plug PCI devices to the guest Qemu instance. This is an issue for guests running on Q35 chipset (preliminary support posted at [1]) since the Q35 PCI root bus does not support hotplug. Devices could be hotplugged to a secondary PCI bus but Xen only support 1 PCI bus for now. The 'hotplug' option allows to control how devices are attached to the guest, either by using the legacy QMP mechanism (this is the default) or by passing it directly to the Qemu command line using xen-pci-passthrough device. Example usage in cfg file: pci = [ "00:03.0,seize=1,hotplug=0" ] Since Qemu -device option accepts parameters in json format, this patchset adds a new internal function libxl__device_pci_get_qmp_json() that generates the device json object used for both QMP hotplug and command line passing. Also, the function libxl_pci_assignable() is made available from libxl.h for access in libxl_dm.c. I don't know if it's ok to make it public or if it should stay private. Maybe it should be renamed as libxl_device_pci_assignable() to match the other PCI device APIs. This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. Disabling the hotplug mechanism might be made mandatory for Q35 machines later, once Q35 support is merged upstream. [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.escande@vates.tech/ Changes in v2: - Add support for YAJL json parser Thierry Escande (3): xl: Add pci device hotplug option libxl: Allow PCI device passthrough using -device Qemu command line docs: provide description for pci hotplug option docs/man/xl-pci-configuration.5.pod | 17 ++++++ docs/man/xl.cfg.5.pod.in | 6 +++ tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 80 +++++++++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 2 + tools/libs/light/libxl_pci.c | 41 +++++++++++---- tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 + tools/xl/xl_parse.c | 5 ++ 9 files changed, 145 insertions(+), 10 deletions(-) -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 16:21:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 16:21:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1277972.1563045 (Exim 4.92) (envelope-from ) id 1wAs82-0006s9-PL; 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bh=aEGweMh3nn2we8a8H+DP/OH/jK1OTcDX5edzheCVTKg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Uj1FqENKAg7IoF81l92a47OI80P0/OeB7Yg+6CMgJEs4O+ZHR+j8wDXA3PD1AWiDU thRbtqACKW6mceDiXYfeP26QdQ13IMbGfyx5vIuNB+L7Donnookv4OBJb8oB+5zCUx 8E6vLX2xPfFoe/sxgldszo3bslDB4owDSGU7Z9HM1B9tEuE4gbuPZIHLMVi+c8wsdi 848XybE4XI9ilb8y3DGcCNFzYAzRn/pZgGmtS/72LONZZ1n6rPOcQDSIZpcdB1zlO9 86x/fss8OIjtxQrwdfvj9QO/pCofltGMPGZFtNnwqy4LDIav5tNxju3nz7mv+qklvF kF3z2YsJT1n7A== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v2=203/3]=20docs:=20provide=20description=20for=20pci=20hotplug=20option?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775751671088 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260409162000.1102680-4-thierry.escande@vates.tech> In-Reply-To: <20260409162000.1102680-1-thierry.escande@vates.tech> References: <20260409162000.1102680-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.739e440ecbe14cfe85700eac099145f7?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260409:md Date: Thu, 09 Apr 2026 16:21:11 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775751673-0DB550B1-350197DB/0/0 X-purgate-type: clean X-purgate-size: 1897 This patch adds description for the 'hotplug' PCI option, allowing devices to be attached to the guest using the legacy QMP hotplug mechanism or by passing them to the Qemu command line using '-device'. Signed-off-by: Thierry Escande --- v2: no change --- docs/man/xl-pci-configuration.5.pod | 17 +++++++++++++++++ docs/man/xl.cfg.5.pod.in | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/docs/man/xl-pci-configuration.5.pod b/docs/man/xl-pci-configuration.5.pod index 0691f06ad3..8b664173cb 100644 --- a/docs/man/xl-pci-configuration.5.pod +++ b/docs/man/xl-pci-configuration.5.pod @@ -166,6 +166,23 @@ dom0 without confirmation. Please use with care. =back +=item B=I + +=over 4 + +=item Description + +Tells L to use QMP hotplug mechanism to attach assignable device to +the guest, or to pass it via Qemu command line using +'B<-device xen-pci-passthrough,...>'. The default is to use the legacy QMP +mechanism. + +=item Default Value + +1 + +=back + =item B=I =over 4 diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 3aac0bc4fb..181aaffa0f 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -1230,6 +1230,12 @@ B<(HVM only)> Changes the default value of B for all PCI devices passed through to this VM. See B above. +=item B + +B<(HVM only)> Changes the default value of B for all PCI +devices passed through to this VM. See L for +more details. + =item B Enable graphics device PCI passthrough. This option makes an assigned -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 09 17:35:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 17:35:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278037.1563053 (Exim 4.92) (envelope-from ) id 1wAtHu-00088i-W7; Thu, 09 Apr 2026 17:35:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278037.1563053; Thu, 09 Apr 2026 17:35:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAtHu-00088b-TU; Thu, 09 Apr 2026 17:35:30 +0000 Received: by outflank-mailman (input) for mailman id 1278037; Thu, 09 Apr 2026 17:35:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAtHs-00088V-Ub for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 17:35:29 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wAtHr-006HS6-U1 for xen-devel@lists.xenproject.org; Thu, 09 Apr 2026 19:35:27 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d7e35d-e002-0a2a0a5209dd-0a2a4508dba6-4 for ; Thu, 09 Apr 2026 19:35:27 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d7e35f-fab6-0a2a45080019-d1558032d454-3 for ; Thu, 09 Apr 2026 19:35:27 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so11306795e9.0 for ; Thu, 09 Apr 2026 10:35:27 -0700 (PDT) Received: from [10.17.80.122] (ll-22.209.223.85.sovam.net.ua. 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Make CPU hotplug and SMT operations >>>> configurable to ease the process. This will also help with introducing >>>> CPU hotplug on Arm, where it needs to be configurable. >>>> >>>> Signed-off-by: Mykyta Poturai >>> >>> Looks largely okay from a technical pov; one nit and one (repeated) remark >>> below. >>> >>>> --- a/xen/arch/x86/sysctl.c >>>> +++ b/xen/arch/x86/sysctl.c >>>> @@ -53,6 +53,11 @@ static long cf_check smt_up_down_helper(void *data) >>>> unsigned int cpu, sibling_mask = boot_cpu_data.x86_num_siblings - 1; >>>> int ret = 0; >>>> >>>> + if ( !IS_ENABLED(CONFIG_CPU_HOTPLUG) ) >>>> + { >>>> + ASSERT_UNREACHABLE(); >>>> + return -EOPNOTSUPP; >>>> + } >>>> opt_smt = up; >>> >>> Another blank line above this one perhaps? >>> >>>> --- a/xen/common/Kconfig >>>> +++ b/xen/common/Kconfig >>>> @@ -637,6 +637,14 @@ config SYSTEM_SUSPEND >>>> >>>> If unsure, say N. >>>> >>>> +config CPU_HOTPLUG >>>> + bool "CPU online/offline support" >>>> + depends on X86 >>>> + default y >>>> + help >>>> + Enable support for bringing CPUs online and offline at runtime. On >>>> + X86 this is required for disabling SMT. >>> >>> The name of this option may need input from others; I'm not quite convinced >>> that this is a good name, as there's no true "hot-plugging" involved here. >>> IOW I fear the present name is misleading. >> >> My first idea was "CONFIG_RUNTIME_CPU_CONTROL" I can switch back to it. > > I could live with that, for at least not being misleading. CPU_ONLINE or > CPU_ONLINE_OFFLINE might be another option, possibly better suited to > later become a dependency (select) of a true CPU_HOTPLUG. As said, input > from others may be helpful. To me, CONFIG_RUNTIME_CPU_CONTROL sounds a little bit vague. Although we are indeed controlling CPUs at runtime, "control" could also mean cpufreq, power management, affinity pinning. I think CONFIG_CPU_ONLINE_OFFLINE is more precise, as it is clear from the name that we are transitioning CPUs between online and offline states. > > Jan > From xen-devel-bounces@lists.xenproject.org Thu Apr 09 17:36:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 17:36:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278046.1563062 (Exim 4.92) (envelope-from ) id 1wAtJ1-00009n-99; Thu, 09 Apr 2026 17:36:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278046.1563062; Thu, 09 Apr 2026 17:36:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAtJ1-00009g-64; Thu, 09 Apr 2026 17:36:39 +0000 Received: by outflank-mailman (input) for mailman id 1278046; Thu, 09 Apr 2026 17:36:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAtJ0-00009a-I5 for xen-devel@lists.xenproject.org; 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Move that if() into the body of the earlier one. > > Signed-off-by: Jan Beulich > > --- a/xen/drivers/passthrough/vtd/intremap.c > +++ b/xen/drivers/passthrough/vtd/intremap.c > @@ -513,13 +513,13 @@ static int msi_msg_to_remap_entry( > > if ( rc ) > return rc; > + > + if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) > + nr = msi_desc->msi.nvec; > } > else > set_hpet_source_id(msi_desc->hpet_id, &new_ire); > > - if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) > - nr = msi_desc->msi.nvec; > - I'm not fully opposed to this, but maybe it would be good to add a small comment to note that HPET never use multi-vector MSI? Thanks, Roger. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM9PR03MB7526.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 567fbb7f-21ca-42d2-d43a-08de965eaa58 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2026 17:37:26.1830 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TZewXxeanjGyaPwdGeDAcR5rQPincpu661NkQO0a6e+qVJ8ykl5AZ+WYSBF4hdh+cX8db0MnlTDo2ss96xj2DLLXJzZLBV2a+JB7kSsakfU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR03MB9870 X-purgate-ID: tlsNG-ef75cf/1775756249-1394141E-B454E631/0/0 X-purgate-type: clean X-purgate-size: 1520 MISRA C Rule 2.1 states: "A project shall not contain unreachable code". In certain build configurations, the function 'altp2m_vcpu_idx()' is define= d as an inline function that contains the 'BUG()' macro. This resulted in a violation because the 'BUG()' macro makes the function non-returning. To ensure compliance with MISRA C Rule 2.1, this patch removes the inline function implementation and its BUG()-based unreachable code. It is replace= d with an unconditional function declaration for 'altp2m_vcpu_idx()'. It reli= es on the compiler's Dead Code Elimination (DCE) to remove the unused function in builds where it is not needed. Signed-off-by: Dmytro Prokopchuk --- Test CI pipeline: https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2441424553 --- xen/include/asm-generic/altp2m.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/alt= p2m.h index 39865a842a..df6b9a9c01 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -15,12 +15,7 @@ static inline bool altp2m_active(const struct domain *d) } =20 /* Alternate p2m VCPU */ -static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) -{ - /* Not implemented on GENERIC, should not be reached. */ - BUG(); - return 0; -} +uint16_t altp2m_vcpu_idx(const struct vcpu *v); =20 #endif /* __ASM_GENERIC_ALTP2M_H */ =20 --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 09 19:04:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 19:04:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278093.1563081 (Exim 4.92) (envelope-from ) id 1wAufz-00034u-OK; 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> } > > +int __init initdom_check_parms( > + const struct domain *d, const struct elf_dom_parms *parms) > +{ > + if ( parms->elf_notes[XEN_ELFNOTE_SUPPORTED_FEATURES].type == XEN_ENT_NONE ) > + return 0; > + > + if ( is_hardware_domain(d) && !test_bit(XENFEAT_dom0, parms->f_supported) ) > + { > + printk("Kernel does not support Dom0 operation\n"); > + return -EINVAL; > + } > + > + return 0; > +} Your v1 structure was better (give or take whitespace mangling). This needs to be a nested pair of if() conditions to not need rewriting when SecureBoot check is added. I'm going to fold this adjustment and commit it, because I need this patch to fix a separate bug in the patchqueue. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 09 21:40:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 09 Apr 2026 21:40:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278150.1563106 (Exim 4.92) (envelope-from ) id 1wAx6g-0004oI-J6; Thu, 09 Apr 2026 21:40:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278150.1563106; Thu, 09 Apr 2026 21:40:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAx6g-0004oB-GL; Thu, 09 Apr 2026 21:40:10 +0000 Received: by outflank-mailman (input) for mailman id 1278150; Thu, 09 Apr 2026 21:29:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wAwvr-0002h1-QT for xen-devel@lists.xenproject.org; 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Thu, 09 Apr 2026 14:28:55 -0700 (PDT) MIME-Version: 1.0 From: Gyujeong Jin Date: Fri, 10 Apr 2026 06:28:43 +0900 X-Gm-Features: AQROBzB07u40_JtQJtBaaMEe18TkugmhZzhmQNiJqWEpx9jZzpL_aZxZ9Cwa980 Message-ID: Subject: [BUG] Potential double-free in Xen dt-overlay attach/remove error path To: xen-devel@lists.xenproject.org Content-Type: multipart/alternative; boundary="00000000000026e311064f0db476" X-purgate-ID: tlsNG-bad1c0/1775770138-55D57152-76FABAA7/0/0 X-purgate-type: clean X-purgate-size: 7794 --00000000000026e311064f0db476 Content-Type: text/plain; charset="UTF-8" Hello Team, I was advised to report this issue in this way because dt-overlay is currently experimental and not security supported. I would like to report a potential memory safety issue in Xen related to the Device Tree overlay handling logic. ------------------------------ Problem Description A double-free / use-after-free condition may occur in the dt-overlay handling path when an overlay attachment fails and the same overlay is later removed. The issue arises because rangeset objects are freed on the failure path of handle_attach_overlay_nodes(), but the corresponding pointers are not cleared. Subsequently, handle_remove_overlay_nodes() may operate on these stale pointers, leading to a second free. Affected Component - Xen ARM - Device Tree overlay subsystem - File: xen/common/device-tree/dt-overlay.c Relevant functions: - handle_attach_overlay_nodes() - handle_remove_overlay_nodes() Impact This issue may lead to: - Double-free of rangeset structures - Use-after-free when accessing stale pointers - Potential hypervisor crash (DoS) - Possible memory corruption depending on allocator behavior Given that this occurs in the hypervisor context, the impact could extend beyond a simple crash under certain conditions. Root Cause The issue originates from inconsistent memory management between the attach failure path and the remove path. In handle_attach_overlay_nodes(), the failure path frees rangeset objects: static long handle_attach_overlay_nodes(...) { ... if ( entry ) { rangeset_destroy(entry->irq_ranges); rangeset_destroy(entry->iomem_ranges); } return rc; } However, the corresponding pointers (entry->irq_ranges and entry->iomem_ranges) are not set to NULL afterward, leaving dangling pointers in the entry structure. Later, in handle_remove_overlay_nodes(), the same fields are used again: static long handle_remove_overlay_nodes(const void *overlay_fdt, uint32_t overlay_fdt_size) { ... rc = remove_nodes(entry); ... rangeset_destroy(entry->irq_ranges); rangeset_destroy(entry->iomem_ranges); ... } static int remove_nodes(const struct overlay_track *tracker) { /* Remove IRQ access. */ if ( tracker->irq_ranges ) { rc = rangeset_consume_ranges(tracker->irq_ranges, irq_remove_cb, d); if ( rc ) return rc; } /* Remove mmio access. */ if ( tracker->iomem_ranges ) { rc = rangeset_consume_ranges(tracker->iomem_ranges, iomem_remove_cb, d); if ( rc ) return rc; } return rc; } Since the pointers were not invalidated after being freed, this leads to: - reuse of freed memory in rangeset_consume_ranges() - double-free in rangeset_destroy() This creates a double-free / use-after-free condition. Environment - Xen: 4.22-dev-517-g500ee5fe0f - Platform: Linux (WSL2 environment) Suggested Fix After calling rangeset_destroy(), the corresponding pointers should be set to NULL to prevent reuse: entry->irq_ranges = NULL; entry->iomem_ranges = NULL; Alternatively, the remove path should defensively check pointer validity. Best regards, Gyujeong Jin (Giunash) --00000000000026e311064f0db476 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Hello Team, I was advised to report this issue in this = way because dt-overlay is currently experimental and not security supported= .

I would like to report a potential memory safety issue in Xen relat= ed to the Device Tree overlay handling logic.

Problem Descriptio= n

A double-free / use-after-free condition may occur in the dt-overl= ay handling path when an overlay attachment fails and the same overlay is l= ater removed.

The issue arises because rangeset objects are freed on = the failure path of handle_attach_overlay_nodes(), but the corresponding po= inters are not cleared. Subsequently, handle_remove_overlay_nodes() may ope= rate on these stale pointers, leading to a second free.

Affected Com= ponent

  • Xen ARM
  • Device Tree overlay subsystem
  • File: xen/common/device-tree/dt-overlay.c

Relevant function= s:

  • handle_attach_overlay_nodes()
    • =
  • handle_remove_overlay_nodes()

I= mpact

This issue may lead to:

  • = Double-free of rangeset structures
  • Use-a= fter-free when accessing stale pointers
  • = Potential hypervisor crash (DoS)
  • Possibl= e memory corruption depending on allocator behavior

Given that = this occurs in the hypervisor context, the impact could extend beyond a sim= ple crash under certain conditions.

Root Cause

The issue orig= inates from inconsistent memory management between the attach failure path = and the remove path.

In handle_attach_overlay_nodes(), the failure pa= th frees rangeset objects:

st=
atic long handle_attach_overlay_nodes(...)
{
    ...

    if ( entry )
    {
        rangeset_destroy(entry->irq_ranges);
        rangeset_destroy(entry->iomem_ranges);
    }

    return rc;
}

However, the corresponding pointers (entry->irq_ranges a= nd entry->iomem_ranges) are not set to NULL afterward, leaving dangling = pointers in the entry structure.

Later, in handle_remove_overlay_node= s(), the same fields are used again:

reuse of freed memory =
in rangeset_consume_ranges()
  • double-free=
 in rangeset_destroy()
    • This creates a double-free / use-after-f=
ree condition.
    Environment
    • Xe=
n: 4.22-dev-517-g500ee5fe0f
    • Platform: Li=
nux (WSL2 environment)
    Suggested Fix
    After calling rang=
eset_destroy(), the corresponding pointers should be set to NULL to prevent=
 reuse:
    entry->irq_ranges =
=3D NULL;
entry->iomem_ranges =3D NULL;

    Alternatively, the remove path should defensively check poi=
nter validity.
    Best regards, Gyujeong Jin (Giunash)
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pr=C Date: Thu, 9 Apr 2026 17:03:11 -0700 From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu CC: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 1/3] xen/arm: Fix off-by-one in iomem_deny_access() calls In-Reply-To: <1D67F18E-0A2E-4A58-8FD7-FC5FD6BE2C6B@arm.com> Message-ID: References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-2-michal.orzel@amd.com> <1D67F18E-0A2E-4A58-8FD7-FC5FD6BE2C6B@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|LV8PR12MB9417:EE_ X-MS-Office365-Filtering-Correlation-Id: 27e2c3a1-95b7-4566-1bdb-08de96948f36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rOTEABFCQW0nzeOqlSDR/Y/Y0tsD04FBtfq5lI9a5nc99oJH484mn0Caul063w2VA2Cwk3XgQVa8S8bmEOq1ekGcMVrPbLyv6G3i+OweZ8Qr9/epOR0E34nBvncGN4fMfjsA0r8GU3sVdNn3bdNU76qRfhxi9vv45HsheanstIxM7ZjeG2BdgWWwNcT5p7reimVKbcaY3Va/Y1485EKZHGSVW7DSipUUvx7Fra4UDZozBRdcnv3TFTyim6JAdZFPCQoqdCt61q184dqrKdJGx0DDGJ2qky8JeX9du3JJN6r94VOd81FoXk1J+ngi2VONsBnMILotJRWzt/PJaOvbF9/xbF/vHQp4q0KgJvW1m+D9LoUW+HXdKBYjvJRZE+XEMsXUKbhiQsH6Oj9TmLdIqDRPcP4rs60vpc6pZACKt/I0N2t0BSY/B6z0HX6p+jlY X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 00:03:13.4326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27e2c3a1-95b7-4566-1bdb-08de96948f36 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9417 X-purgate-ID: tlsNG-ef75cf/1775779405-88F5E41E-077C80BF/0/0 X-purgate-type: clean X-purgate-size: 1113 On Thu, 9 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 9 Apr 2026, at 12:39, Michal Orzel wrote: > > > > iomem_deny_access() wraps rangeset_remove_range() which takes inclusive > > endpoints. All call sites in the GIC and ACPI code pass 'mfn + nr' (or > > 'mfn + 1' for single-page regions) as the end parameter, which causes > > one extra page beyond each region to be denied. > > > > For single-page regions, use 'mfn' as the end (denying exactly one page). > > For all multi-page regions, use 'mfn + nr - 1'. > > > > This matches the correct pattern used elsewhere, e.g. in device.c. > > > > Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") > > Fixes: 66158be465 ("ARM: ITS: Deny hardware domain access to ITS") > > Fixes: 97e9875646 ("arm/acpi: Permit MMIO access of Xen unused devices for Dom0") > > Signed-off-by: Michal Orzel > > --- > > > > This looks ok to me. > > Reviewed-by: Luca Fancellu Reviewed-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Fri Apr 10 00:07:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 00:07:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278216.1563139 (Exim 4.92) (envelope-from ) id 1wAzPh-0005WL-06; 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d=kernel.org; s=k20201202; t=1775779673; bh=J9eE0IfMExM5GO3+0tjrn1qX87H+H2jmgNPBdEUsm3E=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=o9GZDfCdgI9++ImF51a1TRXVTXeEHqwYQrqFAO+QospzWEq1KhcIvx6nR1uIXFOeb 1JVVikRcDMqSQfgGAgMxHLhzo8CJ+UuB8rcuNB3+d8PTsLnT4kRhtcF8uVk/j26jIT r2G5NLJvstF34bgpfHsEJ3ttfGYFqKiNb6wcayR+NsJB7T8R54gQe6KwCEBa/KFQPi zEfvtIG1ZO3iGZcdDnEg2Ru0SzBD6qKfuepzf7AbBD5+1LR4jMuX5GoCuBuYRtrELy gTMA+7xYaimRzOqNKx3bDEF4atLBv+Lv9hJ3Gz1FTa5btywGrwfdSN5uKIibPQ04xU 7ntUkPpdsMpAQ== Date: Thu, 9 Apr 2026 17:07:50 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH 3/3] xen/arm: gic-v3: Use vsize instead of csize for virtual CPU interface In-Reply-To: <995B8A68-0DE0-4FE8-AC80-21E5DE498170@arm.com> Message-ID: References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-4-michal.orzel@amd.com> <995B8A68-0DE0-4FE8-AC80-21E5DE498170@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-42698a/1775779675-175432A1-30903594/0/0 X-purgate-type: clean X-purgate-size: 652 On Thu, 9 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 9 Apr 2026, at 12:39, Michal Orzel wrote: > > > > gicv3_iomem_deny_access() incorrectly uses csize (physical CPU > > interface size) instead of vsize (virtual CPU interface size) when > > calculating the number of pages to deny for the virtual CPU interface > > region at vbase. > > > > Fixes: 8300b3377e ("arm/gic: Add a new callback to deny Dom0 access to GIC regions") > > Signed-off-by: Michal Orzel > > --- > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Fri Apr 10 00:16:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 00:16:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278226.1563150 (Exim 4.92) (envelope-from ) id 1wAzXx-00077d-Pq; Fri, 10 Apr 2026 00:16:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278226.1563150; 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Fri, 10 Apr 2026 02:16:27 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 8055C40664; Fri, 10 Apr 2026 00:16:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48A75C4CEF7; Fri, 10 Apr 2026 00:16:24 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775780185; bh=xAa9ho/qWsXTFCn6t/AyO2PTk8zzuFfmA8Xen8QhGmE=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=McVjr3ZoS28UCtmU7k5Tdgb3gMIt3vJ6kHao/YS66EqzBpA3AYP1wW0EVkMuNB+0G sL77Uu8Pjynejxk7RKAnkRjvqPsv5hQV5SQFRFIc0fh6oxcymzq+ze7sbJRPgE8ujd qQf6tpqd4DMvHwptoY3+sEKouBwnLQUgtrzsUmJu/n+pN0e6b9WPTKTt82NXRX62s0 /QAzbLYedrwzMPGHO01kAxBXWwEH1O4Spb+Xqf63Y3xOBrxx8kVg9mHYTz9jNZFotb +i3jEesda/ZWtF+457xcsOEPiM5DVIekF0GQCVFX1+Q8iDNt86oMAFiSyX69K/8JyH VbWKoImRwAuMA== Date: Thu, 9 Apr 2026 17:16:22 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Dmytro Prokopchuk1 cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: Re: [PATCH] generic/altp2m: address violations of MISRA C Rule 2.1 In-Reply-To: <8b5ca213a097f7b221b06b6173e4621563779a73.1775752149.git.dmytro_prokopchuk1@epam.com> Message-ID: References: <8b5ca213a097f7b221b06b6173e4621563779a73.1775752149.git.dmytro_prokopchuk1@epam.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-ef75cf/1775780187-13D4741E-E2C98BC8/0/0 X-purgate-type: clean X-purgate-size: 1814 On Thu, 9 Apr 2026, Dmytro Prokopchuk1 wrote: > MISRA C Rule 2.1 states: "A project shall not contain unreachable code". > > In certain build configurations, the function 'altp2m_vcpu_idx()' is defined > as an inline function that contains the 'BUG()' macro. This resulted in a > violation because the 'BUG()' macro makes the function non-returning. > > To ensure compliance with MISRA C Rule 2.1, this patch removes the inline > function implementation and its BUG()-based unreachable code. It is replaced > with an unconditional function declaration for 'altp2m_vcpu_idx()'. It relies > on the compiler's Dead Code Elimination (DCE) to remove the unused function > in builds where it is not needed. > > Signed-off-by: Dmytro Prokopchuk > --- > Test CI pipeline: > https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2441424553 > --- > xen/include/asm-generic/altp2m.h | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/altp2m.h > index 39865a842a..df6b9a9c01 100644 > --- a/xen/include/asm-generic/altp2m.h > +++ b/xen/include/asm-generic/altp2m.h > @@ -15,12 +15,7 @@ static inline bool altp2m_active(const struct domain *d) > } > > /* Alternate p2m VCPU */ > -static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) > -{ > - /* Not implemented on GENERIC, should not be reached. */ > - BUG(); > - return 0; > -} > +uint16_t altp2m_vcpu_idx(const struct vcpu *v); The return type being changed to uint16_t is also a fix. It should be mentioned in the commit message. Aside from that: Reviewed-by: Stefano Stabellini > #endif /* __ASM_GENERIC_ALTP2M_H */ > > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Fri Apr 10 00:56:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 00:56:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278241.1563158 (Exim 4.92) (envelope-from ) id 1wB0A9-000408-Hs; Fri, 10 Apr 2026 00:55:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278241.1563158; Fri, 10 Apr 2026 00:55:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB0A9-000401-Eq; Fri, 10 Apr 2026 00:55:57 +0000 Received: by outflank-mailman (input) for mailman id 1278241; Fri, 10 Apr 2026 00:55:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB0A7-0003zv-D3 for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="s166KNew1RMNit10" Content-Disposition: inline In-Reply-To: <20260409162000.1102680-1-thierry.escande@vates.tech> X-purgate-ID: tlsNG-42698a/1775782553-EE9492A1-F40B480D/0/0 X-purgate-type: clean X-purgate-size: 3228 --s166KNew1RMNit10 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 10 Apr 2026 02:55:46 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Thierry Escande Cc: xen-devel@lists.xenproject.org, Anthony PERARD , Juergen Gross , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= Subject: Re: [RFC PATCH v2 0/3] xl: Allow PCI devices to be passthrough'd via Qemu command line On Thu, Apr 09, 2026 at 04:20:57PM +0000, Thierry Escande wrote: > This series adds support for a new 'hotplug' option for PCI devices to be > passthrough'd to guests. >=20 > The current mechanism for device passthrough uses QMP device_add command > to hot-plug PCI devices to the guest Qemu instance. This is an issue for > guests running on Q35 chipset (preliminary support posted at [1]) since t= he > Q35 PCI root bus does not support hotplug. Devices could be hotplugged to > a secondary PCI bus but Xen only support 1 PCI bus for now. >=20 > The 'hotplug' option allows to control how devices are attached to the > guest, either by using the legacy QMP mechanism (this is the default) or = by > passing it directly to the Qemu command line using xen-pci-passthrough > device. >=20 > Example usage in cfg file: > pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] >=20 > Since Qemu -device option accepts parameters in json format, this > patchset adds a new internal function libxl__device_pci_get_qmp_json() th= at > generates the device json object used for both QMP hotplug and command li= ne > passing. > Also, the function libxl_pci_assignable() is made available from libxl.h > for access in libxl_dm.c. I don't know if it's ok to make it public or if > it should stay private. Maybe it should be renamed as > libxl_device_pci_assignable() to match the other PCI device APIs. >=20 > This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running > Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. > Disabling the hotplug mechanism might be made mandatory for Q35 machines > later, once Q35 support is merged upstream. >=20 > [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.esc= ande@vates.tech/ I don't see relevant device option added to the QEMU cmdline: https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/13860278916 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --s166KNew1RMNit10 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnYSpQACgkQ24/THMrX 1ywp+QgAlIu4U3xOIqcswI+Xglm1Big6NccmeqdmX5sknwC6JK5AGVuMWieGBhOb F+QW+jBngPMi8adN3+wHcxUsha4hm5xV8ji9WtioMe4HuMa9erDQ9Sm6vdTUH1lD SQBx6IN0mmFk7/sArRWaFfRlhdGmNp6MadA6pzNMsX6v2ZFK9Lc6tm4m/KyKlqcl vVNS+9fn6B0Fj4aH3RGv+arpOX3dOI5xW1J7tT1HUoG2hFAcye2QxhGDXlLBzcWe BcnRzktEaItarlKxleiohgACVC/NN3q9boiq0LsWvmb0IaviZfrumQ8WzOVqH2hK JYhanOTSAD+RooNtVOsekmRKhnRSlQ== =02cg -----END PGP SIGNATURE----- --s166KNew1RMNit10-- From xen-devel-bounces@lists.xenproject.org Fri Apr 10 01:29:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 01:29:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278256.1563167 (Exim 4.92) (envelope-from ) id 1wB0gU-0007Xy-17; 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pr=C Message-ID: <5f543029-64bc-42af-8fce-31d911800c67@amd.com> Date: Thu, 9 Apr 2026 21:29:10 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/APIC: handle overflow in TMICT calculation To: Jan Beulich , "xen-devel@lists.xenproject.org" CC: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <2fa2fb41-cb62-4a1b-84cf-822b2f97bc2b@suse.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: <2fa2fb41-cb62-4a1b-84cf-822b2f97bc2b@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|PH7PR12MB6587:EE_ X-MS-Office365-Filtering-Correlation-Id: aca8fb2e-46fb-40ae-4776-08de96a0926f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: xXCET1mCsdlOgF9Yka1B/FuAQKqhtvbaVqM3cE2fX/jb1DCeGsb0Twyen0X6+hGDV/3+vni3o5tGUL0hHHnBa4Z9yWRlh73yt4qde3LjRtJkRexO/x3ejKB0ZQSIAa72SZENhQ+9i6B8nORfkyrA59R0pYbPoma9NmKtahh5s//lLW9DhwlYCulPfTunLSUNmwZM2ZrCUkszBEyHGTZHpSdHW2tj2CFEJ6T/DzgVh/Mt0r/PMC1ESnN6boMb/P7G2OkP6gPLF+P7CUrCETrTGPHbYRbFZe6xVErBHbXzmcU1u39PYD+c3QE+TMmLzqpQLRC6qB8fMBdHsAYosfyxKEJLCWzV4aTzuJWlyYXSPPNdnDvsJDvj1u5xMV7IaaGMBkRI1p2s23EeLSyfB+56ey9kpiEXMrmkGKZJOoboEapKE6CmlalRH/kl63IHdpOH0Yt0KTrz1mEqwluJPyJSToihSXvRUdC54OpYqd7s+g++FpjIKYb4xLMLGmgW1+FFU+KgXrPsKutEg/Kf7+ISwUz6B4TZpWZFhX8NXPY5YmOTDUTdOXrMrR5DtNrA5+7GuU8+9FCAtZxmg7OhlbuU0eU05Dn3y7rg7k4jIUoDGCd+MeGqxV87eMA5Pjy45ULyE6Wui+JVR/GQUt4WmiFGWUfSM9C1M1WL9vMIbItlP+yxHVhZjKuAOWjektd3mnHj+vBJYJF5VE0psrsnnnvjWEp+LWYKdfMzgKYXSVigpGMK7FiguINfFcTSYPx7EL1I4Z0FOhG40YnSIRThdU2isw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b8oZYnfzHGnomhZ0mmgS407KCXgpP+cmayM8tJUcGXUiDJ0uCBldda0JSO56Tty15TEMtXa0t1/jfSYPY8snpmlRYSfUkNW58oxUD6TdA9hbWrt9HjF6zWsVEF9V6QUc0a2Vqh4upgkg7aiDYturzd3mT4atEnGyNwXgfIBeSoqPJqwucrR8ahU98Uc86u0halFqpBPH8+LSk55diYGVtGhAIXtw/SSvF79W5MlulBsij9nQpUo/IU2fNJyH+nRI3epwntAZdlS9R5oXyHr3roo+BK7M3jPQRGj1QeVTMmFGXJ2TeL00yxP6EMVNMLqMgIPcXxu/CN/LT859wm+mHgMqb8qK6XJQ5Q+GqPHsdKfXUjRnea5UHjUaXO7u5oC7AuKGL/fkohufjCeDJ2SXkql6UAZlAMSgg6eCmu1pfk1h80HD881jZV2d5jXXQV2g X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 01:29:12.8258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aca8fb2e-46fb-40ae-4776-08de96a0926f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6587 X-purgate-ID: tlsNG-16d1c6/1775784558-5C7213D8-3B2AF377/0/0 X-purgate-type: clean X-purgate-size: 981 On 4/9/26 05:21, Jan Beulich wrote: > With an expiry value on the order of 20 hours, and with a bus scale value If I did my math correctly, I believe 10 hours is sufficient to trigger signed multiplication overflow. 20 hours would result in unsigned multiplication overflow. > of 256k (as supplied by qemu), the (signed) multiplication will be UB. As > we've checked that the value is positive, we mean unsigned multiplication > anyway. Yet let's play safe against even larger expiry and bus scale > values, leveraging the compiler builtin that there is for this purpose. > > While there also drop the stray cast from the actual TMICT write. > > Fixes: 9062553a0dc1 ("added time and accurate timer support") > Fixes: b95beb185810 ("x86: Clean up APIC local timer handling") > Reported-by: Stewart Hildebrand > Signed-off-by: Jan Beulich Tested-by: Stewart Hildebrand Thanks! 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Thu, 09 Apr 2026 22:51:48 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 07:51:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] VT-d: avoid multi-message-MSI check for HPET To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper References: <1903a57a-524e-4e6d-bd47-a87fadda4aa0@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775800308-5FD3C3D8-20A2CC2D/0/0 X-purgate-type: clean X-purgate-size: 1160 On 09.04.2026 19:36, Roger Pau Monné wrote: > On Wed, Apr 01, 2026 at 02:47:48PM +0200, Jan Beulich wrote: >> Having this immediately below a PCI-dev vs HPET conditional is (mildly) >> confusing. Move that if() into the body of the earlier one. >> >> Signed-off-by: Jan Beulich >> >> --- a/xen/drivers/passthrough/vtd/intremap.c >> +++ b/xen/drivers/passthrough/vtd/intremap.c >> @@ -513,13 +513,13 @@ static int msi_msg_to_remap_entry( >> >> if ( rc ) >> return rc; >> + >> + if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) >> + nr = msi_desc->msi.nvec; >> } >> else >> set_hpet_source_id(msi_desc->hpet_id, &new_ire); >> >> - if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) >> - nr = msi_desc->msi.nvec; >> - > > I'm not fully opposed to this, but maybe it would be good to add a > small comment to note that HPET never use multi-vector MSI? That aspect doesn't change - HPET code simply doesn't (and never should) set .type to PCI_CAP_ID_MSI. That field should reflect reality (and HPET, iirc, simply leaves it at 0). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8b5ca213a097f7b221b06b6173e4621563779a73.1775752149.git.dmytro_prokopchuk1@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1775801046-0FD420B1-A499A03F/0/0 X-purgate-type: clean X-purgate-size: 1071 On 09.04.2026 19:37, Dmytro Prokopchuk1 wrote: > MISRA C Rule 2.1 states: "A project shall not contain unreachable code". > > In certain build configurations, Can you give an example where ... > the function 'altp2m_vcpu_idx()' is defined > as an inline function that contains the 'BUG()' macro. This resulted in a > violation because the 'BUG()' macro makes the function non-returning. > > To ensure compliance with MISRA C Rule 2.1, this patch removes the inline > function implementation and its BUG()-based unreachable code. It is replaced > with an unconditional function declaration for 'altp2m_vcpu_idx()'. ... a declaration is needed? The sole non-x86 reference I see is from common/monitor.c, and the sole relevant Kconfig option I can spot is VM_EVENT. When that's off, the file won't be built at all. Further, BUG() and a few more constructs have a dedicated deviation already in place. I don't mind a useless function to be shrunk (or, as per above, perhaps even dropped), but the justification then needs to be different. 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Comparing the masked but unshifted value against GIC_BASER_CACHE_nC, which is an unshifted value, leads to incorrect detection of non-cacheable table mappings. Shift the masked value to properly detect if the BASER backing memory requires flushing. Fixes: 05238012b86 ("ARM: GICv3 ITS: allocate device and collection table") Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- xen/arch/arm/gic-v3-its.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 9ba068c46f..6a46bcc8af 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -496,7 +496,8 @@ retry: } attr = regc & BASER_ATTR_MASK; } - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <= GIC_BASER_CACHE_nC ) clean_and_invalidate_dcache_va_range(buffer, table_size); /* If the host accepted our page size, we are done. */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 06:26:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 06:26:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278339.1563202 (Exim 4.92) (envelope-from ) id 1wB5KJ-0001ud-Vn; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fTd3Ab5xTCOYzNFPoXDvAiDwviSTVDeM9nh54w4op08vw9LnmYJiGhgFI5WXxo4jQvuzRyAiTu1SY8lLrh4OYrnbOIvlTcX+JtZI96kvz7gtEznjK0eyChpGBtcciawclzrp6Zq+3yXIrg/IoIsdgLvhG3nn6Mj835CGL+PMwpugyrDvCm50A+ZYP9ZzvB5geXXa3MHPlGAdGXLxHyeZf5j7+ebaAq4FNrW1KApQL/QWT4UmMAZaw3OeEzzz5kD303AAQ19kGP0y9+3Sl4yQqffRu4lxnjV9afVmiWwS99SIN9uPH5YSjx8+FbSR7nLy+ocTqNRZ4Vr7buy3MrDzFZ2pTGF74Gxmk+qFT6l3sWhtokLo+ceDZsNsHzaDYsEz+1WaKvTGZ60Z4vsoaP/evxuYludCygOdnVTtyOkFz9gOU/4oXnBBemf0PaQ8DVQN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 06:26:35.4370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 378c02db-793d-4ebc-bb5c-08de96ca1d72 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF8423FDA82 X-purgate-ID: tlsNG-ebf023/1775802404-B192151B-7B259140/0/0 X-purgate-type: clean X-purgate-size: 1579 On 09/04/2026 13:49, Halder, Ayan Kumar wrote: > Hi Michal, > > Apologies if my review is weird, I have been looking into too much of > safety stuff. Yes, I know :) > > On 09/04/2026 12:39, Michal Orzel wrote: >> iomem_deny_access() wraps rangeset_remove_range() which takes inclusive >> endpoints. All call sites in the GIC and ACPI code pass 'mfn + nr' (or >> 'mfn + 1' for single-page regions) as the end parameter, which causes >> one extra page beyond each region to be denied. >> >> For single-page regions, use 'mfn' as the end (denying exactly one page). >> For all multi-page regions, use 'mfn + nr - 1'. > > Just reading this and the change below, it seems that the issue was > caught while doing some boundary value analysis. In this specific case, > it seems the boundary values were set incorrectly. > > Can you explain a bit more (the boundary/edge cases) in the commit > message and give some reference to test (can be even a different repo or > something) on how you caught this and verified it to be correct ? > > We can keep this test somewhere (and tag it to the commit) even if such > tests does not make sense to be upstreamed. As much as it looks like an issue found during BVA, the truth is I found it by accident when debugging some issue where rangesets were involved. As always, whenever I see a function with parameters {start, end}, I need to dive deeper to verify whether end is inclusive or not. I also check the call-sites to validate my observations and that's how I found these bugs. ~Michal From xen-devel-bounces@lists.xenproject.org Fri Apr 10 06:31:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 06:31:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278354.1563211 (Exim 4.92) (envelope-from ) id 1wB5Or-0003VQ-I1; Fri, 10 Apr 2026 06:31:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278354.1563211; Fri, 10 Apr 2026 06:31:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB5Or-0003VJ-F4; Fri, 10 Apr 2026 06:31:29 +0000 Received: by outflank-mailman (input) for mailman id 1278354; Fri, 10 Apr 2026 06:31:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB5Op-0003VC-QR for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 06:31:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB5Op-00FvLG-6E for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 08:31:27 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d89934-e002-0a2a0a5209dd-0a2a4505966a-34 for ; Fri, 10 Apr 2026 08:31:27 +0200 Received: from [209.85.221.54] (helo=mail-wr1-f54.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8993e-3760-0a2a45050019-d155dd36a55e-3 for ; Fri, 10 Apr 2026 08:31:26 +0200 Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-43cf5fbacc9so758244f8f.1 for ; Thu, 09 Apr 2026 23:31:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 09 Apr 2026 23:31:26 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 08:31:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [BUG] Potential double-free in Xen dt-overlay attach/remove error path To: xen-devel@lists.xenproject.org References: Content-Language: en-US Cc: Gyujeong Jin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775802686-2292196F-70851A81/0/0 X-purgate-type: clean X-purgate-size: 2610 On 09.04.2026 23:28, Gyujeong Jin wrote: > Hello Team, I was advised to report this issue in this way because > dt-overlay is currently experimental and not security supported. > > I would like to report a potential memory safety issue in Xen related to > the Device Tree overlay handling logic. > ------------------------------ > Problem Description > > A double-free / use-after-free condition may occur in the dt-overlay > handling path when an overlay attachment fails and the same overlay is > later removed. > > The issue arises because rangeset objects are freed on the failure path of > handle_attach_overlay_nodes(), but the corresponding pointers are not > cleared. Subsequently, handle_remove_overlay_nodes() may operate on these > stale pointers, leading to a second free. > Affected Component > > - Xen ARM > - Device Tree overlay subsystem > - File: xen/common/device-tree/dt-overlay.c > > Relevant functions: > > - handle_attach_overlay_nodes() > - handle_remove_overlay_nodes() > > Impact > > This issue may lead to: > > - Double-free of rangeset structures > - Use-after-free when accessing stale pointers > - Potential hypervisor crash (DoS) > - Possible memory corruption depending on allocator behavior > > Given that this occurs in the hypervisor context, the impact could extend > beyond a simple crash under certain conditions. > Root Cause > > The issue originates from inconsistent memory management between the attach > failure path and the remove path. > > In handle_attach_overlay_nodes(), the failure path frees rangeset objects: > > static long handle_attach_overlay_nodes(...) > { > ... > > if ( entry ) > { > rangeset_destroy(entry->irq_ranges); > rangeset_destroy(entry->iomem_ranges); > } > > return rc; > } > > However, the corresponding pointers (entry->irq_ranges and > entry->iomem_ranges) are not set to NULL afterward, leaving dangling > pointers in the entry structure. Further to this, am I overlooking any check preventing an already created pair of rangesets to be replaced by new ones, leaking the original pair? And then there's a Misra issue as well: dt_overlay_domctl() has unreachable code. Anything other than XEN_DOMCTL_DT_OVERLAY_ATTACH is excluded at the top, so the "else" body near the bottom is unreachable. (This in turn makes me wonder: How come there's no "detach"?) Yet then, that's probably pretty meaningless, as there look to be other issues (Misra and general robustness ones) as well. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775803207-C9D3CC9A-C665EEE1/0/0 X-purgate-type: clean X-purgate-size: 790 On 10.04.2026 08:09, Mykola Kvach wrote: > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -496,7 +496,8 @@ retry: > } > attr = regc & BASER_ATTR_MASK; > } > - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) > + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> > + GITS_BASER_INNER_CACHEABILITY_SHIFT) <= GIC_BASER_CACHE_nC ) Are you aware of MASK_EXTR()? This is one of the cases that we have it for. Really all *_SHIFT constants should be purged, as they can be calculated from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the code readable). Further, doesn't gicv3_lpi_set_proptable() have the same issue with GICR_PROPBASER_INNER_CACHEABILITY_MASK? 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Thu, 09 Apr 2026 23:57:41 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 08:57:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() To: Luca Fancellu , Michal Orzel Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Anthony PERARD , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-3-michal.orzel@amd.com> <9A42538E-AB13-488E-9AEF-39CD7E8D3131@arm.com> <6093D2A3-1823-4587-BB81-4593AD060D71@arm.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6093D2A3-1823-4587-BB81-4593AD060D71@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1775804261-EFF462A1-6FB5FD03/0/0 X-purgate-type: clean X-purgate-size: 2537 On 09.04.2026 15:34, Luca Fancellu wrote: >> On 9 Apr 2026, at 13:52, Luca Fancellu wrote: >>> On 9 Apr 2026, at 13:48, Jan Beulich wrote: >>> On 09.04.2026 14:22, Luca Fancellu wrote: >>>>> On 9 Apr 2026, at 12:39, Michal Orzel wrote: >>>>> >>>>> The check uses >= to compare the total number of colors against >>>>> max_num_colors (which is ARRAY_SIZE of the colors array). This >>>>> incorrectly rejects input that would exactly fill the array. >>>>> >>>>> For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 >>>>> for dom0 would fail. >>>>> >>>>> Change >= to > so that exactly filling the array is permitted. >>>>> >>>>> Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") >>>>> Signed-off-by: Michal Orzel >>>>> --- >>>> >>>> Reviewed-by: Luca Fancellu >>> >>> Did you see Andrew's reply? If that earlier (recent) commit was wrong, I >>> think a 2nd Fixes: tag may be needed here. For now I can't help the >>> impression though that there might have been a re-basing mistake, where >>> that re-base may have wanted to result in this patch dissolving into >>> nothing. Yet of course I'm all ears to learn otherwise. >> >> Oh, no I didn’t see that! Thanks for pointing that out, I will have a closer look. > > > I had a closer look, I feel that the patch is ok and commit cba8a584de171c8c4510709c2edc9f1cf86b21ab > was missing this corner case. If anything, that part of the change there was outright wrong (and hence, as said, a 2nd Fixes: tag [actually, see below, simply another one] is needed). With overflow excluded, (*num_colors + (end - start + 1)) > max_num_colors is the same as (*num_colors + (end - start)) >= max_num_colors i.e. the state before that change, isn't it? And yes, now that I look again I think I agree that I screwed up there. Yet then the (imo) better fix would be to undo that change, rather than switching from >= to > . That's one less calculation overall. Michal? Jan > Let’s say max_num_colors = 8 (array capacity), *num_colors = 4 so we stored already 4 entries and the > next parsed range gives start = 4, end = 7: > > (*num_colors + (end - start + 1)) >= max_num_colors will compute as > (4 + (7 - 4 + 1)) >= 8 which will be > 8 >= 8 that will be true and the input will be rejected, instead of being a valid entry. > > Did I miss anything? > > Cheers, > Luca > From xen-devel-bounces@lists.xenproject.org Fri Apr 10 07:04:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 07:04:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278381.1563238 (Exim 4.92) (envelope-from ) id 1wB5up-0000D7-Ay; Fri, 10 Apr 2026 07:04:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278381.1563238; Fri, 10 Apr 2026 07:04:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB5up-0000D0-89; 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bh=wZn7ErxUd+DKabZl6OfftNVf6LgBJtkKHdjlFuA8pTE=; b=39pUHmyaoZG+uBQCSphzg7JYNwTWFz6WDOy4grsF09Un96un68SM6WAeh3Sqy2ALIOmm/uPOxG44aw0UvinBSpJgW1WU3tkbVlRMO5Pmwi1dH6xZqBE7EZUq4l8C08Fm14E3QD2rXaszPWb5+vQ4d1kku0GtMiwpKUY8fcqKn2s= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Message-ID: <3ec5c89b-6429-4bb5-a2b4-585e2feb1685@amd.com> Date: Fri, 10 Apr 2026 09:04:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] xen/common: llc-coloring: Fix off-by-one in parse_color_config() To: Jan Beulich , Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Andrew Cooper" , Anthony PERARD , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260409113934.197619-1-michal.orzel@amd.com> <20260409113934.197619-3-michal.orzel@amd.com> <9A42538E-AB13-488E-9AEF-39CD7E8D3131@arm.com> <6093D2A3-1823-4587-BB81-4593AD060D71@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AsAkDY0EjTIkSg8QRK2LKWMFSjScM1oQOOELzfoK5dHQFbhgpXPJeT6XXNEr5N0mOGcEr1YLiRW6KF6eple6s/UFisEF9azQjLY2jY0ssSgAxGUXnLqmOADHaIavrYjAQSYXGyefJt6flZwXOEPoxyDMhs1ilO5SVVJTh3j9Z//DbTPgq+Nih/1Z8zYnbSnjkhUYS5Y/rKd1G2iyHDTEYoCXs/DFKSBQZmoz8loXUU3h3S2p27JaX3nmXSoxowMuDiL12gDpqM82F53ZotWUDZMUpvnB3pqO/rxbNz0WqWo+iR/ubRJWryFLOV2x8wEzPUoGiIA4O+u5Lg6+eOSdartHJcXsS8SX6plz9zQlYZlVPSkPuYjXKd7Un5drYshcbwO+3DAvfEiwnFEkPgEt8CISqjx5rZond0HZbyhkqADgrQtpbgeH1S6bxs/sqgS6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 07:04:20.3443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d886fee-1334-4249-bd0f-08de96cf6375 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF62A0C9A68 X-purgate-ID: tlsNG-42698a/1775804669-1734C2A1-0F8E0ABF/0/0 X-purgate-type: clean X-purgate-size: 2928 On 10/04/2026 08:57, Jan Beulich wrote: > On 09.04.2026 15:34, Luca Fancellu wrote: >>> On 9 Apr 2026, at 13:52, Luca Fancellu wrote: >>>> On 9 Apr 2026, at 13:48, Jan Beulich wrote: >>>> On 09.04.2026 14:22, Luca Fancellu wrote: >>>>>> On 9 Apr 2026, at 12:39, Michal Orzel wrote: >>>>>> >>>>>> The check uses >= to compare the total number of colors against >>>>>> max_num_colors (which is ARRAY_SIZE of the colors array). This >>>>>> incorrectly rejects input that would exactly fill the array. >>>>>> >>>>>> For example, with NR_LLC_COLORS=16, specifying 1 color for Xen and 15 >>>>>> for dom0 would fail. >>>>>> >>>>>> Change >= to > so that exactly filling the array is permitted. >>>>>> >>>>>> Fixes: 95ef5ddf8a ("xen/arm: add Dom0 cache coloring support") >>>>>> Signed-off-by: Michal Orzel >>>>>> --- >>>>> >>>>> Reviewed-by: Luca Fancellu >>>> >>>> Did you see Andrew's reply? If that earlier (recent) commit was wrong, I >>>> think a 2nd Fixes: tag may be needed here. For now I can't help the >>>> impression though that there might have been a re-basing mistake, where >>>> that re-base may have wanted to result in this patch dissolving into >>>> nothing. Yet of course I'm all ears to learn otherwise. >>> >>> Oh, no I didn’t see that! Thanks for pointing that out, I will have a closer look. >> >> >> I had a closer look, I feel that the patch is ok and commit cba8a584de171c8c4510709c2edc9f1cf86b21ab >> was missing this corner case. > > If anything, that part of the change there was outright wrong (and hence, as > said, a 2nd Fixes: tag [actually, see below, simply another one] is needed). > With overflow excluded, > > (*num_colors + (end - start + 1)) > max_num_colors > > is the same as > > (*num_colors + (end - start)) >= max_num_colors > > i.e. the state before that change, isn't it? > > And yes, now that I look again I think I agree that I screwed up there. Yet > then the (imo) better fix would be to undo that change, rather than switching > from >= to > . That's one less calculation overall. Michal? Yes, I do agree. This patch can be modified to just do: diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c index eb7c72b24023..6dc614739a98 100644 --- a/xen/common/llc-coloring.c +++ b/xen/common/llc-coloring.c @@ -78,7 +78,7 @@ static int __init parse_color_config(const char *buf, unsigned int colors[], if ( end >= NR_LLC_COLORS || start > end || (end - start) >= (UINT_MAX - *num_colors) || - (*num_colors + (end - start + 1)) >= max_num_colors ) + (*num_colors + (end - start)) >= max_num_colors ) return -EINVAL; /* Colors are range checked in check_colors() */ I'll do that later on. ~Michal From xen-devel-bounces@lists.xenproject.org Fri Apr 10 07:08:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 07:08:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278395.1563247 (Exim 4.92) (envelope-from ) id 1wB5yu-0000vB-UX; Fri, 10 Apr 2026 07:08:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278395.1563247; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1775804922-FDF52A3D-C5E95FD2/0/0 X-purgate-type: clean X-purgate-size: 1313 Hi Jan, Thank you for the review. On Fri, Apr 10, 2026 at 9:40=E2=80=AFAM Jan Beulich wro= te: > > On 10.04.2026 08:09, Mykola Kvach wrote: > > --- a/xen/arch/arm/gic-v3-its.c > > +++ b/xen/arch/arm/gic-v3-its.c > > @@ -496,7 +496,8 @@ retry: > > } > > attr =3D regc & BASER_ATTR_MASK; > > } > > - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_CA= CHE_nC ) > > + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> > > + GITS_BASER_INNER_CACHEABILITY_SHIFT) <=3D GIC_BASER_CACHE_nC= ) > > Are you aware of MASK_EXTR()? This is one of the cases that we have it fo= r. > Really all *_SHIFT constants should be purged, as they can be calculated > from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the > code readable). I wasn't aware of this macro, thanks. I will take a look. > > Further, doesn't gicv3_lpi_set_proptable() have the same issue with > GICR_PROPBASER_INNER_CACHEABILITY_MASK? Fortunately, GIC_BASER_NonShareable is equal to zero, so the condition there is not affected. We may want to align that condition for consistency, but I would prefer to keep this patch focused on the actual bug fix and avoid unrelated changes. Best regards, Mykola > > Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 10 07:09:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 07:09:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278403.1563257 (Exim 4.92) (envelope-from ) id 1wB5zy-0001QI-6v; Fri, 10 Apr 2026 07:09:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278403.1563257; Fri, 10 Apr 2026 07:09:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB5zy-0001QB-42; Fri, 10 Apr 2026 07:09:50 +0000 Received: by outflank-mailman (input) for mailman id 1278403; Fri, 10 Apr 2026 07:09:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB5zw-0001Q0-A6 for xen-devel@lists.xenproject.org; Fri, 10 Apr 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Unlike GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable physical Group 1 interrupt signalling, so this write only clears EOImode. The GICv3 power management rules require the physical group enables in the CPU interface to be cleared before the redistributor is driven into ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables Group 1 interrupts on this path, so disable the interface by clearing ICC_IGRPEN1_EL1 instead. This appears to be a copy of the GICv2 pattern where the enable control lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1. Fixes: bc183a0235e ("xen/arm: Add support for GIC v3") Signed-off-by: Mykola Kvach --- xen/arch/arm/gic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bc07f97c16..4f0852be2f 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1028,7 +1028,7 @@ static int gicv3_cpu_init(void) static void gicv3_cpu_disable(void) { - WRITE_SYSREG(0, ICC_CTLR_EL1); + WRITE_SYSREG(0, ICC_IGRPEN1_EL1); isb(); } -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 08:16:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 08:16:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278451.1563275 (Exim 4.92) (envelope-from ) id 1wB72Q-0002mu-LI; Fri, 10 Apr 2026 08:16:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278451.1563275; Fri, 10 Apr 2026 08:16:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB72Q-0002mn-IJ; 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h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=VOv7EPHi8MaWZkoFyDFlMhlUABQGxvolujowi0c2XmN+BcZjr+kdj83+vyYhW2J8/ A0jg8JceNyvTDrhtuOlz/LG4scLt/uk6eJO/MjoKWIeeyyp86tSbAaCzUsI2K2lzNw XEiu7Gf/4HUGRlj+w6pFK1ImapK5n3w6N2kRN//0Kz/1DmlKfK0dRPbSbJkiUyRwXG 4gAXb4p+HUKz8Ih8a+IrWoIpXZ2OYsS4DW/prnas6+VgmAnyOdV4XCypefGxArwff1 7SdYUI+pNrC87FYV5Iufkbuhmx3ZXXJ9TuZ5K3h1pLJ3t8Rrd3d0KISBSwsPXG6Ihl k1dQLshfpM56g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775808983; x=1776069483; i=thierry.escande@vates.tech; bh=ONfxNDiXYC98hlXu/atW+mLoY8BTnDa/ULY8H6DvHW0=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=OTErO7Cv8b/R/QK1XJPs3PPPX4Rnl6L+1ngLhVZWNuVDFm7nBsnEjSYrqtT57A84W mPvQBcYVcEh1EvGHRmussML2YQCTdbmsVA5hlW2y8EvTdhvbIJSzToXJdUNFJcH7Ak a/ZYjwXGeJhJR+FNcQkGlzTgpdJwahP92IDjHssCFmjOomzXrREmotz3Es5HAtK5Y6 vvxyv9KGmsZChRIDRd5TpA7irxIqSApengCu3fQLQqPpzyQDKtcVSdCXWsejOO7d4I /MV1ONsBkR8oy/k9tmpI+y4D5HWRHYSFM2FIWza3/Tu482VMjIKREBnuCUmP4wPwQx bKDn9plJEzWKg== From: "Thierry Escande" Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=20v2=200/3]=20xl:=20Allow=20PCI=20devices=20to=20be=20passthrough'd=20via=20Qemu=20command=20line?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775808981974 Message-Id: To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P.=20Berrang=C3=A9?=" References: <20260409162000.1102680-1-thierry.escande@vates.tech> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.5a7d847fa67b46e4afbeb5fbdefc1df7?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 08:16:22 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1775808984-AE33BCD1-C5EB6E18/0/0 X-purgate-type: clean X-purgate-size: 2310 On 4/10/26 02:55, Marek Marczykowski-G=C3=B3recki wrote: > On Thu, Apr 09, 2026 at 04:20:57PM +0000, Thierry Escande wrote: >> This series adds support for a new 'hotplug' option for PCI devices to b= e >> passthrough'd to guests. >> >> The current mechanism for device passthrough uses QMP device_add command >> to hot-plug PCI devices to the guest Qemu instance. This is an issue for >> guests running on Q35 chipset (preliminary support posted at [1]) since = the >> Q35 PCI root bus does not support hotplug. Devices could be hotplugged t= o >> a secondary PCI bus but Xen only support 1 PCI bus for now. >> >> The 'hotplug' option allows to control how devices are attached to the >> guest, either by using the legacy QMP mechanism (this is the default) or= by >> passing it directly to the Qemu command line using xen-pci-passthrough >> device. >> >> Example usage in cfg file: >> pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] >> >> Since Qemu -device option accepts parameters in json format, this >> patchset adds a new internal function libxl__device_pci_get_qmp_json() t= hat >> generates the device json object used for both QMP hotplug and command l= ine >> passing. >> Also, the function libxl_pci_assignable() is made available from libxl.h >> for access in libxl_dm.c. I don't know if it's ok to make it public or i= f >> it should stay private. Maybe it should be renamed as >> libxl_device_pci_assignable() to match the other PCI device APIs. >> >> This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running >> Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. >> Disabling the hotplug mechanism might be made mandatory for Q35 machines >> later, once Q35 support is merged upstream. >> >> [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.es= cande@vates.tech/ > > I don't see relevant device option added to the QEMU cmdline: > https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/13860278916 > My bad. The code that adds the -device option is not in the correct code block. (bad copy/paste at some point I guess...). v3 on its way. Regards, Thierry -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 08:18:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 08:18:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278460.1563283 (Exim 4.92) (envelope-from ) id 1wB743-0003JX-Vs; Fri, 10 Apr 2026 08:18:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278460.1563283; Fri, 10 Apr 2026 08:18:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB743-0003JO-Sz; Fri, 10 Apr 2026 08:18:07 +0000 Received: by outflank-mailman (input) for mailman id 1278460; Fri, 10 Apr 2026 08:18:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB742-0003JE-FW for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Fri, 10 Apr 2026 10:17:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: gic-v3: disable Group 1 before CPU power-down To: Mykola Kvach , CC: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk References: <1952e52fd60fdd762862e74dbd522fcd7c65284a.1775804338.git.mykola_kvach@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <1952e52fd60fdd762862e74dbd522fcd7c65284a.1775804338.git.mykola_kvach@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017097:EE_|SN7PR12MB8060:EE_ X-MS-Office365-Filtering-Correlation-Id: edc9df11-769d-4aa3-2b1d-08de96d9ad27 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: aWElD4cq2XQxH+zUXy+U3Sw2i2Ori+L49VqgUmWtmEtbhUmLWi+q7lbhLTSuPnMITzPxR6N25TnGKyuUjUmnGBExQGNftDBWPeBk8paogoOwEzgQkv8LVZ2HQetCLzskLhaWbTkHrb1EWnl9KEnFN4uljaiqmkwDObfevAS7srA+Q5lcn9w0tEWMd2tgYk3waDM3nmw3achfvVEVtEpGj8BBRDtZKfd+XB6SqGxEjZ8XZfMg7ya5+03nzqi99yeDVY5ISsSSOYOdiIM+jS1q6zOwdxkswgnve84CsXDhjRXLrbe0S3khLkwnNrReSZz3mpkIdIVD6+JSb3pCiwYnZHkzr4N4wY8CwxsAKoRFAk9xjRSBPUWxlQUaew1zCadZ0bi8oav7l4GIX+tI9p1wwPTprGt1iI79tw924r7aUIWI7PyyVHjhir1XKBhmS65SNXpPRi9sIPpjFu9aM5gx1G6A0KShZmLh0rP0Zo12yDnVZuZnt8Gj+wFWabNktGj983Zz5JF2D03ML7kjfy7Orl69FGLCHL6fUAR9wobWmq/IWOZLivschYK5993ALzkXkxPZThicclAE0HtuYNZs+QIf1qBjOcsjB1tmMpYWynTBV9q91CK8mWmJFLUSZKbcN7XgCk17b27qom70E2r9N555wMde7rP96HMkf6pvvzTvHzZ/w6PFt4NxDwNMZFwTFVRUj9RK0S4qQWLDeblfpcgglSa4+b7ORBBYUvkEUbJsrPL5D7gkv2OptVLcfS4DZegMLJEV/9k9kdPwBSozRA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2Qwx20M8ygfOcDYwjFHKa1ggYIAzl8+5Rn5Tu4dltT8fWt5HgaE/W88UniatfP86TMoSerSShY8m4IIPmfTijZ8K4aEACzQjiJQpm54qCeekudDf1GTDCUW/9Q89YJvpgyJXx214uyIXadM06dNiz5ZVYIoncmmGVbGSPYV6fTjkyMKpfMhDylT3qA+O8XM2/pbr5a+F6FcoKOkRtD2SCF1kogDhugPk2lvabAHdOwiUsro3RWi5fbSJEXw+2iJufjyC1uImtbrbalMhuAxgc3m/z5xJmB1ua7q/29+wgJHOwMa8WQ/9p4PFNwurU/Lg3aQnGXsSW2WKzO4z6OxeI8V1BV4Si5NHUNGgdBJOmmfIU6FHWSYeTOz8zssFgg77v/8lrSPajsBqJqHSTW94EXifGjke05gcNYRK6ssz3BMTqxt4u5/n0CbTUXScaeJt X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 08:17:58.9544 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edc9df11-769d-4aa3-2b1d-08de96d9ad27 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017097.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8060 X-purgate-ID: tlsNG-d62444/1775809085-174FE185-BE0D1C58/0/0 X-purgate-type: clean X-purgate-size: 1035 On 10/04/2026 09:47, Mykola Kvach wrote: > From: Mykola Kvach > > gicv3_cpu_disable() currently writes 0 to ICC_CTLR_EL1. Unlike > GICC_CTLR in the GICv2 path, ICC_CTLR_EL1 does not enable or disable > physical Group 1 interrupt signalling, so this write only clears > EOImode. > > The GICv3 power management rules require the physical group enables in > the CPU interface to be cleared before the redistributor is driven into > ProcessorSleep, otherwise behaviour is UNPREDICTABLE. Xen only enables > Group 1 interrupts on this path, so disable the interface by clearing > ICC_IGRPEN1_EL1 instead. > > This appears to be a copy of the GICv2 pattern where the enable control > lives in CTLR, but for GICv3 the enable moved to ICC_IGRPEN1_EL1. Yes, GICv2 GICC_CTLR combines enable+EOImode in one register. > > Fixes: bc183a0235e ("xen/arm: Add support for GIC v3") > Signed-off-by: Mykola Kvach Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Fri Apr 10 08:38:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 08:38:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278475.1563294 (Exim 4.92) (envelope-from ) id 1wB7Nz-00068S-KI; Fri, 10 Apr 2026 08:38:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278475.1563294; Fri, 10 Apr 2026 08:38:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB7Nz-00068L-GO; Fri, 10 Apr 2026 08:38:43 +0000 Received: by outflank-mailman (input) for mailman id 1278475; Fri, 10 Apr 2026 08:38:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB7Ny-00068F-3H for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Andrew Cooper , Anthony PERARD , "Jan Beulich" , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano Stabellini" , Luca Fancellu Subject: [PATCH v2] xen/common: llc-coloring: Fix off-by-one in parse_color_config() Date: Fri, 10 Apr 2026 10:29:55 +0200 Message-ID: <20260410082955.42038-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|DS2PR12MB9774:EE_ X-MS-Office365-Filtering-Correlation-Id: e7d904e9-ff3a-45d3-e9db-08de96dc8eb8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: FEc2MwxRBTdac6VRFrGas5rU4m730KR6R51FPaoh0cadwL4KlwaYZ1WGCGPtQ3Bem6J+n42NhuQe2Ularmgc+yFkEf5Vzqmwnxwv3JybdI6m7q6lNADG3LXQSLdfvmYVZ5BWKpCv9FLKYK4PyKbTjRKGKZO06G5QNMldtBjkLBToPOKirGfK1RN2Ik+OKXawx33+6MCEh7IBaAW6yy799uLBxOuXF3ydkhIYZ9820VhbvEeUbUJy9QFbsyQUhNKPnlsxqxpPIgfIKKFWQLgkwiapOR6yjUAnFT+3PQpvPjaYs3D1SEZsBhdpgyt/pU5RCA4cSt1Uc7ECiNCKb9EMzbViMHfrRdsR2kiIosySBT4IUJmv+imS7gEm0ldH3rwQJbOXBEeOQOweQsXlMlnWlhibcl5NBlDbg9Fp7M3FZdfU4R3aUY2p2M4OkGPgeT4CDm0ta4xNsY8NOA8YjNGPZePCbChiPzPoNkn03uEIIM0CyhxFPlZsA/T1SEks267YLeuDZ3czfrtdqoPeqZafbbURu5OwBjeGppciPmwFI0ulaWa54ld7LAj5NJnUkGDUSuwtGmU/b9MwzBFt6du5CI1hCaeGoZ5Sm0xMu2sJaxM3MuJXUB0NQ61Hy28c2GqfFyPotOrrCJYNwwzXbZr0tPPPojWzKG0trpppMllsjcVPUV5Zv18ZMuEDZg1tEE5m+7+CbpB/YDpJcZi9T/B9UrLzxJ1nZTyQQw6LjYQJ4IMBWc8vcW1nZ+Nlp4wB2CoYmv3/zal/9Ae60n8sZctZPg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9JGKev1FLc1PR64Zj8v1NINdDJ5uwrxFvA68Tt5DSSGHRjemO72kIuONzl1/2R8AKpWNU6UswVHo5lqbzYd8VBt/TL78iPf20mD7p0U9c9/x9rCQlXkAnK7aXaA0SL+abNB928v53RnjQsRv80uwy//DllNMhGLSLAedAGsFzHBMRrfehpLVnpjFRcu75J5EttCSTOOUG1J2UWZONIdPZDZEacgAnbau8WADGzCk0iVeira2xQBaXKNMszkXI0+3oF73UKVAjcVViZTxzKFg7wIq/e/aBpCKBGVCUSRgsO/NF51WYHyqV8LjZXMPxlcnKj1Awcc+iv1S92op3p5iKjar1uP3Q1pCN/8dEJ7Ir7CzaWKc8l8fd/xDpsXhRLYrBORRD+eRT7FPP9LYJky5ZNjjbDgaSuM++EddXjSbUzjmTQ1Euwe161vGsjz5mqxG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 08:38:36.3841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7d904e9-ff3a-45d3-e9db-08de96dc8eb8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9774 X-purgate-ID: tlsNG-33051d/1775810320-41914C9A-0D5E98A3/0/0 X-purgate-type: clean X-purgate-size: 1439 The check uses (*num_colors + (end - start + 1)) >= max_num_colors, which rejects a configuration where exactly max_num_colors colors are specified. For example, if max_num_colors is 4 and *num_colors is 0, a range "0-3" gives (end - start + 1) = 4, and (0 + 4) >= 4 is true, incorrectly returning -EINVAL. Fix this by switching the overflow condition to the state before commit cba8a584de17 that regressed the behavior (i.e. don't add 1). Fixes: cba8a584de17 ("llc-coloring: improve checking while parsing") Signed-off-by: Michal Orzel Reviewed-by: Luca Fancellu --- Changes in v2: - extract from series - undo the overflow change made by cba8a584de17 --- xen/common/llc-coloring.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/llc-coloring.c b/xen/common/llc-coloring.c index eb7c72b24023..6dc614739a98 100644 --- a/xen/common/llc-coloring.c +++ b/xen/common/llc-coloring.c @@ -78,7 +78,7 @@ static int __init parse_color_config(const char *buf, unsigned int colors[], if ( end >= NR_LLC_COLORS || start > end || (end - start) >= (UINT_MAX - *num_colors) || - (*num_colors + (end - start + 1)) >= max_num_colors ) + (*num_colors + (end - start)) >= max_num_colors ) return -EINVAL; /* Colors are range checked in check_colors() */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 08:55:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 08:55:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278491.1563301 (Exim 4.92) (envelope-from ) id 1wB7e1-0000Sx-UK; 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Use stop_timer() instead of kill_timer() in time_suspend(), so that the set_timer() call in time_resume() successfully re-arms the timer. Otherwise time calibration is no longer scheduled (and executed) after resuming from S3 suspend. Fixes: 6d90db1a2ca1 ("x86: rendezvous-based local time calibration") Reported-by: Marek Marczykowski-Górecki Signed-off-by: Roger Pau Monné --- xen/arch/x86/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index fed30a919d2c..4233ea507d40 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -2728,7 +2728,7 @@ int time_suspend(void) { cmos_utc_offset = -get_wallclock_time(); cmos_utc_offset += get_sec(); - kill_timer(&calibration_timer); + stop_timer(&calibration_timer); /* Sync platform timer stamps. */ platform_time_calibration(); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:01:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:01:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278507.1563311 (Exim 4.92) (envelope-from ) id 1wB7jz-0002Cb-Oj; Fri, 10 Apr 2026 09:01:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278507.1563311; Fri, 10 Apr 2026 09:01:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB7jz-0002CU-LF; Fri, 10 Apr 2026 09:01:27 +0000 Received: by outflank-mailman (input) for mailman id 1278507; Fri, 10 Apr 2026 09:01:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wB7jy-0002C5-Hm for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 09:01:26 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB7jx-00CGcS-U0 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 11:01:25 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8bc61-2eae-0a2a0a5409dd-0a2a450b8386-32 for ; Fri, 10 Apr 2026 11:01:25 +0200 Received: from [209.85.208.48] (helo=mail-ed1-f48.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8bc65-bca8-0a2a450b0019-d155d030e55e-3 for ; Fri, 10 Apr 2026 11:01:25 +0200 Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-670af4fc2f1so57022a12.1 for ; Fri, 10 Apr 2026 02:01:25 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-670706251f0sm415649a12.15.2026.04.10.02.01.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Apr 2026 02:01:23 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:Subject:From:Cc:To:Content-Language:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775811685; x=1776416485; darn=lists.xenproject.org; h=content-transfer-encoding:subject:from:cc:to:content-language :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=MAo25sHibVddpyd9/kKMJyuwa3tRX8JvqBopaTkYYqk=; b=jzIUEF9EmB5GjqH+pM2ukBMrAm/TbIEoPN59lZORCjIRUzEl7CRFCr3ht9NuhNSsq+ 8quYURGj5ghfjdnDH9xer7E7FgIbX0N54wIuZx6wSsBzjLU2fRbKqZUz5K73S5AOXP9C eye01CTdUqWpFqllhiDZ4KBsIJklP435YIpeV8OfL7jZ7NckvtnXCZU3drDpX0igpldi YVfC7FTCzGfHk8469fveI6rrut2slCXtKwfyDYRMDTElwtmIw2vC9d6k4c9Cqpe3RG1G cblkzeF6h9EK35S5bbWINwfZtSufe5y6Pc9wZPfi/i2h2U4MX9bzMG4HSYmqR5keGet/ GbKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775811685; x=1776416485; h=content-transfer-encoding:subject:from:cc:to:content-language :user-agent:mime-version:date:message-id:x-gm-gg:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=MAo25sHibVddpyd9/kKMJyuwa3tRX8JvqBopaTkYYqk=; b=Vupub6VsukFNyIP+LSPQP3dMpl43DZPaBz5kXqkv5p0BaJdgCNOBHktyPomcXUvsut iNbiAWBu7vF1FEiqfWL6Gps7xvAx1oJUi4fPywukkhidnk5c5V9+/WOVr6xEcFLF0h5Q 9U6dVNgJmAChCBI5BnVikxljXRVyMIS8Bhz8R0NyBEbSPeIwKnrEE0i/7vkmtAZiLSVk zJzbyFRBbhmL7yFwj6aGy3wWpfgvAPY5u1wbVErId2eO5cxi+A07yFH7iaKJJ1o6YBXc IxzIhabd9Gt4UoK3HqOSfUytEpdlVVUmJQiAJnBfg+v422ajkb+aT6znpnjHBAlbYCm8 de3w== X-Gm-Message-State: AOJu0YxK25jL5avWYDZEXTSyaidNZL6+4Xgp1cPQaSZijH5edRAlXO+E dB/rxHXtBscgUkGfCO/CC4GFkG2UQaKhW3mj8JoHM1MSmIwg9742a9MPhFaXLQ== X-Gm-Gg: AeBDietFNz3rEjTybz/AjEO2zbvf29lU961RfRN7p9ndRwRuvONZ00+tCrSxLD6bTXt o96g32UBg54spsRRa3TC593EZon7xlLbY9FB1AyL02bb5/zQF4oIQ3pugP+4U6c/adE5p7KzhhM CIhASZEL66IOZvRMBwzOIsYbQrRnK6wYZcAmajbcUHWz35E/hNSIENf9OT8pKSTSzUuAHFZgSP7 zXekRiX3UYWmi3IACIzocIkVx/sScTCRsCgomR650fCM1QkHvzHvk59/XAD4FDlsw/NzJmA3Bab 9nopA3Sy7e9GO+XyMe/QUwYG6ulopqK2owCX6T3HC/h6klYv/O2PjjF17ePr4tRHLOP2Js9ZXwk 7WK8c+K1oeN971cuLX4QIARP+eIB546vpOf40hMRGTN7uprC4gWG2qAOd7C3PEJ3wsP5LtseD95 pNXc8C57YFbbwHuqDTusEoitv8QVBsd5VZa+cgNk18lv6/fVw86EkWLeBZVLjW7PGz88gYlcdpi 7g= X-Received: by 2002:a05:6402:46d6:b0:670:a279:19b7 with SMTP id 4fb4d7f45d1cf-670a2791b27mr409599a12.12.1775811684709; Fri, 10 Apr 2026 02:01:24 -0700 (PDT) Message-ID: <29f456c6-2f6a-4b7d-a70f-9d2d50663b47@gmail.com> Date: Fri, 10 Apr 2026 11:01:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: Xen-devel Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , "Orzel, Michal" From: Oleksii Kurochko Subject: Generation of phandles for guest DTB in dom0less Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775811685-F5DC12A1-91BD72DE/10/73395122804 X-purgate-type: spam X-purgate-size: 2434 Hi all, While working on dom0less guest FDT construction I noticed that fdt_generate_phandle() is "broken" when used to generate phandles for a guest's nodes. The root cause is the way dom0less manages phandle_intc (phandle_gic in Arm terminology): the dummy GIC node already occupies a phandle in pfdt, but fdt_generate_phandle(kinfo->fdt, ...) has no visibility into pfdt and therefore may produce a phandle that collides with phandle_intc. I see three potential approaches to fix this and would like to get the community's feedback before going further. **Option 1: guest_fdt_generate_phandle() wrapper** Introduce a thin wrapper that skips any phandle already reserved by the architecture: int guest_fdt_generate_phandle(const struct kernel_info *kinfo, uint32_t *phandle) { int res; res = fdt_generate_phandle(kinfo->fdt, phandle); if ( *phandle == kinfo->phandle_intc ) (*phandle)++; return res; } The obvious downside is that this is not flexible: every future node added to pfdt would require a corresponding fixup here, which is easy to forget and hard to maintain. **Option 2: Reserve a "first free phandle" field in the arch-specific structure** Add a field to the arch-specific part of struct kernel_info that stores the first phandle number guaranteed not to be used by pfdt. Guest phandle allocation would then start from (and increment) this field, completely avoiding the pfdt phandle space. This is cleaner than Option 1 but requires careful initialisation and documentation to make sure the field is always set before it is consumed. **Option 3: Store a pfdt pointer in struct kernel_info** Add a `pfdt` pointer to struct kernel_info and pass it to fdt_generate_phandle() whenever a guest phandle is needed: fdt_generate_phandle(kinfo->pfdt, ...) Because fdt_generate_phandle() walks the target FDT to find the highest existing phandle and returns the next free one, using pfdt as the source of truth guarantees uniqueness across both pfdt and the guest FDT, without any manual bookkeeping. This feels like the most robust option to me, since it naturally handles any future nodes added to pfdt without requiring changes to the phandle allocation logic. Does anyone see issues with Option 3? Are there other approaches worth considering? Thanks, Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:07:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:07:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278517.1563320 (Exim 4.92) (envelope-from ) id 1wB7pc-0002kk-Bh; Fri, 10 Apr 2026 09:07:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278517.1563320; Fri, 10 Apr 2026 09:07:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB7pc-0002kd-7s; Fri, 10 Apr 2026 09:07:16 +0000 Received: by outflank-mailman (input) for mailman id 1278517; Fri, 10 Apr 2026 09:07:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB7pb-0002kX-3P for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 09:07:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB7pa-00DrTV-FS for xen-devel@lists.xenproject.org; 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>>> } >>> - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) >>> + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> >>> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <= GIC_BASER_CACHE_nC ) >> Are you aware of MASK_EXTR()? This is one of the cases that we have it for. >> Really all *_SHIFT constants should be purged, as they can be calculated >> from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the >> code readable). > I wasn't aware of this macro, thanks. I will take a look. As a general rule of thumb, where you've got a _MASK/_SHIFT pair, you should be using MASK_INSR/EXTR and delete the shift constant. It is is ~half the code (visually), and removes an entire class of errors (mismatched constants). ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:22:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:22:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278537.1563328 (Exim 4.92) (envelope-from ) id 1wB84G-0005et-HW; Fri, 10 Apr 2026 09:22:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278537.1563328; Fri, 10 Apr 2026 09:22:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB84G-0005em-Ew; Fri, 10 Apr 2026 09:22:24 +0000 Received: by outflank-mailman (input) for mailman id 1278537; Fri, 10 Apr 2026 09:22:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB84E-0005eg-Tb for xen-devel@lists.xenproject.org; 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Message-ID: <85f76f74-8554-4000-8c39-623b83944648@citrix.com> Date: Fri, 10 Apr 2026 10:22:15 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , Jan Beulich , Teddy Astie , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Subject: Re: [PATCH] x86/time: do not kill calibration timer on suspend To: Roger Pau Monne , xen-devel@lists.xenproject.org References: <20260410085504.32925-1-roger.pau@citrix.com> Content-Language: en-GB From: Andrew Cooper In-Reply-To: <20260410085504.32925-1-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO4P123CA0260.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:194::13) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|CH4PR03MB7625:EE_ X-MS-Office365-Filtering-Correlation-Id: bd639fab-7e3b-451a-ddfb-08de96e2a9d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024|22082099003|18002099003|56012099003; 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Use stop_timer() instead of > kill_timer() in time_suspend(), so that the set_timer() call in > time_resume() successfully re-arms the timer. Otherwise time calibration > is no longer scheduled (and executed) after resuming from S3 suspend. > > Fixes: 6d90db1a2ca1 ("x86: rendezvous-based local time calibration") > Reported-by: Marek Marczykowski-Górecki > Signed-off-by: Roger Pau Monné > --- > xen/arch/x86/time.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c > index fed30a919d2c..4233ea507d40 100644 > --- a/xen/arch/x86/time.c > +++ b/xen/arch/x86/time.c > @@ -2728,7 +2728,7 @@ int time_suspend(void) > { > cmos_utc_offset = -get_wallclock_time(); > cmos_utc_offset += get_sec(); > - kill_timer(&calibration_timer); > + stop_timer(&calibration_timer); > > /* Sync platform timer stamps. */ > platform_time_calibration(); Reviewed-by: Andrew Cooper This should definitely be stop timer and not kill timer. However, the fact it "stops" drift after S3 really does concern me.  There's clearly a different issue here which this is covering over. The systems which we've been testing on all have ITSC so the TSC doesn't drift.  Whether there's a step or not is a different question (I'd expect firmware to arrange to avoid a step being seen), but a step would not explain our symptoms. Given it's only once a second, can we dump the scale/offset which the rendezvous produced each time? This feels suspiciously like we've gauged the frequency too fast, and are relying on micro-fixes every second to keep time looking normal.  (This is pure speculation; I don't any evidence). ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:25:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:25:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278549.1563339 (Exim 4.92) (envelope-from ) id 1wB87V-0006GF-4M; Fri, 10 Apr 2026 09:25:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278549.1563339; Fri, 10 Apr 2026 09:25:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB87V-0006G8-06; Fri, 10 Apr 2026 09:25:45 +0000 Received: by outflank-mailman (input) for mailman id 1278549; Fri, 10 Apr 2026 09:25:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB87S-0006Fw-UR for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 09:25:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB87S-004RNF-AL for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 11:25:42 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8c20e-bab6-0a2a0a5309dd-0a2a450897e8-22 for ; Fri, 10 Apr 2026 11:25:42 +0200 Received: from [209.85.218.54] (helo=mail-ej1-f54.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8c216-fab6-0a2a45080019-d155da36c558-3 for ; Fri, 10 Apr 2026 11:25:42 +0200 Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-b9d6c8871c7so177355866b.1 for ; Fri, 10 Apr 2026 02:25:42 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775813172; x=1776083172; bh=MN57+wFD3YMSu+hnCyiMaTNNIg+kDpL+iSz3lyloMgY=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=XrES4pPDXzksgmBdmieUdtHN8sQsbJj5U/zSq7eNeArp9prDarQjFYnRGzfRPi5Kc 8hS6TyjTUTOVal2D6ZJhxrK7WK03TgTavVq1kKBvjfD/opN6tffBmIWqHfh52N0n3B yFzIgkCxyMmaRIRU0oKiqi0gElQaZ0dctbaM3iyH3CICyn7LEAl7aINqeIp1GwdVYe QcR7IqwIY1EFw9m99RzeSnvXvCo4DEzCgSxUWQKJVfVduq+nUKtEyF3hc2XtVHL2bb kWuiNVfWAsRu0LvxD/kiAfB3BJESZKIEgWeJhAN6+v9v96tk9tkSQvvpTUiv7gDNfN mVqWZ4iVNQFFg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775813172; x=1776073672; i=teddy.astie@vates.tech; bh=MN57+wFD3YMSu+hnCyiMaTNNIg+kDpL+iSz3lyloMgY=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=t0OteAOWCBimQDuo67L8ZJdOdmYFdhqYVKAD83HzR053udULN6UB1jtUbiw7rjZaN 7lbbew+67tzLXULPJvZshon0yjVxQCnLkUv2D5w8Bk7urQI6KZ0zjE9s0FX8Uv3slL trB+sHMRUOocs7wtJOZtu7QZSIQ0BnNaQYfT1Ln7cY0Mmv6H8q7P5H54EcwmwW15FU yoVS11ozG6M0U40PRWZir0wzITeKB8MAuMTNQDWd2v51ykHqoJmydso69zLwiL7V/W LFOq5CtqaLElKEbsvVVAh+0r3NCEx7YV1UIKM6KXdmv11f5QBsRkcNXdrHTajF8rlw 3caNT0vJmQYSQ== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=20v4=2000.9/16]=20x86/CPUID:=20enable=20AVX10=20leaf?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775813171619 Message-Id: <029ab247-b8a1-4961-80ab-5b13e5c7aa77@vates.tech> To: "Jan Beulich" , xen-devel@lists.xenproject.org Cc: "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.e8385e73c0454e59839060e1a48cc0ce?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 09:26:12 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1775813174-B0B2851B-190ED84D/0/0 X-purgate-type: clean X-purgate-size: 15738 Le 09/04/2026 =C3=A0 17:18, Jan Beulich a =C3=A9crit=C2=A0: > This requires bumping the number of basic leaves we support. Apart from > this the logic is modeled as closely as possible after that of leaf 7 > handling. > > Signed-off-by: Jan Beulich > --- > The gen-cpuid.py adjustment is merely the minimum needed. It's not > really clear to me whether someone turning off e.g. AVX512BW might then > also validly expect AVX10 to be turned off. > AFAIUI, AVX512BW is a dependency of AVX10, as AVX10 implies that the former is available. > Do we want to synthesize AVX10 in the (max?) policies when all necessary > AVX512* features are available, thus allowing migration from an AVX10 > host to a suitable non-AVX10 one? > I guess we want, there is not really a reason to not allow it. Some software may check for AVX10 only, and not check for individual AVX512 bits. > The prior vsz bits are now defined as reserved-at-1: No idea yet how > to represent this properly. > > How a toolstack side equivalent (if any) of the init_dom0_cpuid_policy() > change would look like is entirely unclear to me. How much should we > take from the max policy, and how much should we permit/require the user > to specify (and how would the latter look like)? > > While, as per a comment next to the call site of > recalculate_cpuid_policy(), recalculate_*() are supposed to go away when > x86_cpu_policies_are_compatible() is complete, some of the checking done > in recalculate_misc() really wouldn't below there. We'd need another "is > self-consistent" checking function. > --- > v4: Drop all traces of AVX10/256. Add max_subleaf check to > x86_cpu_policies_are_compatible(). Add/adjust vsz checks in > recalculate_misc(). In the max policies, synthesize AVX512* when > AVX10 is available. > v3: Re-base. > v2: Add logic to init_dom0_cpuid_policy(). Drop vsz128 field. Re-base. > > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -211,7 +211,7 @@ static void recalculate_xstate(struct cp > if ( p->feat.mpx ) > xstates |=3D X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; > > - if ( p->feat.avx512f ) > + if ( p->feat.avx512f || p->feat.avx10 ) In principle, the avx10 check is redundant as avx512f must be set if avx10 is set. > xstates |=3D X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM; > > if ( p->feat.pku ) > @@ -272,6 +272,18 @@ static void recalculate_misc(struct cpu_ > > p->basic.raw[0xc] =3D EMPTY_LEAF; > > + zero_leaves(p->basic.raw, 0xe, 0x23); > + > + p->avx10.raw[0].b &=3D 0x000700ff; > + p->avx10.raw[0].c =3D 0; > + p->avx10.raw[0].d =3D 0; > + if ( !p->feat.avx10 || !p->avx10.version || > + !p->avx10.vsz512 || !p->avx10.vsz256 || !p->avx10.vsz128 ) > + { > + p->feat.avx10 =3D false; > + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); > + } > + > p->extd.e1d &=3D ~CPUID_COMMON_1D_FEATURES; > > /* Most of Power/RAS hidden from guests. */ > @@ -400,6 +412,7 @@ static void __init guest_common_max_leav > { > p->basic.max_leaf =3D ARRAY_SIZE(p->basic.raw) - 1; > p->feat.max_subleaf =3D ARRAY_SIZE(p->feat.raw) - 1; > + p->avx10.max_subleaf =3D ARRAY_SIZE(p->avx10.raw) - 1; > p->extd.max_leaf =3D 0x80000000U + ARRAY_SIZE(p->extd.raw) -= 1; > } > > @@ -408,6 +421,7 @@ static void __init guest_common_default_ > { > p->basic.max_leaf =3D host_cpu_policy.basic.max_leaf; > p->feat.max_subleaf =3D host_cpu_policy.feat.max_subleaf; > + p->avx10.max_subleaf =3D host_cpu_policy.avx10.max_subleaf; > p->extd.max_leaf =3D host_cpu_policy.extd.max_leaf; > } > > @@ -503,6 +517,28 @@ static void __init guest_common_max_feat > * function correctly when migrated here, even if ERMS isn't availa= ble. > */ > __set_bit(X86_FEATURE_ERMS, fs); > + > + /* > + * AVX10 is merely a re-declaration of a combination of AVX512 featu= res. > + * Synthesize the latter from the former, when available. Doing it = the > + * other way around would also require synthesizing the AVX10 CPUID = leaf. > + */ > + if ( test_bit(X86_FEATURE_AVX10, fs) ) > + { > + __set_bit(X86_FEATURE_AVX512F, fs); > + __set_bit(X86_FEATURE_AVX512VL, fs); > + __set_bit(X86_FEATURE_AVX512BW, fs); > + __set_bit(X86_FEATURE_AVX512DQ, fs); > + __set_bit(X86_FEATURE_AVX512_BF16, fs); > + __set_bit(X86_FEATURE_AVX512_FP16, fs); > + __set_bit(X86_FEATURE_AVX512CD, fs); > + __set_bit(X86_FEATURE_AVX512_BITALG, fs); > + __set_bit(X86_FEATURE_AVX512_IFMA, fs); > + __set_bit(X86_FEATURE_AVX512_VBMI, fs); > + __set_bit(X86_FEATURE_AVX512_VBMI2, fs); > + __set_bit(X86_FEATURE_AVX512_VNNI, fs); > + __set_bit(X86_FEATURE_AVX512_VPOPCNTDQ, fs); > + } > } > > static void __init guest_common_default_feature_adjustments(uint32_t *f= s) > @@ -966,6 +1002,7 @@ void recalculate_cpuid_policy(struct dom > > p->basic.max_leaf =3D min(p->basic.max_leaf, max->basic.max_lea= f); > p->feat.max_subleaf =3D min(p->feat.max_subleaf, max->feat.max_subl= eaf); > + p->avx10.max_subleaf =3D min(p->avx10.max_subleaf, max->avx10.max_su= bleaf); > p->extd.max_leaf =3D 0x80000000U | min(p->extd.max_leaf & 0xffff= , > ((p->x86_vendor & (X86_VEND= OR_AMD | > X86_VEND= OR_HYGON)) > @@ -1012,6 +1049,8 @@ void recalculate_cpuid_policy(struct dom > > if ( p->basic.max_leaf < XSTATE_CPUID ) > __clear_bit(X86_FEATURE_XSAVE, fs); > + if ( p->basic.max_leaf < 0x24 ) > + __clear_bit(X86_FEATURE_AVX10, fs); > > sanitise_featureset(fs); > > @@ -1081,9 +1120,18 @@ void __init init_dom0_cpuid_policy(struc > /* Apply dom0-cpuid=3D command line settings, if provided. */ > if ( dom0_cpuid_cmdline ) > { > + const struct cpu_policy *max =3D is_pv_domain(d) > + ? (IS_ENABLED(CONFIG_PV) ? &pv_max_cpu_policy : NULL) > + : (IS_ENABLED(CONFIG_HVM) ? &hvm_max_cpu_policy : NULL); > uint32_t fs[FSCAPINTS]; > unsigned int i; > > + if ( !max ) > + { > + ASSERT_UNREACHABLE(); > + return; > + } > + > x86_cpu_policy_to_featureset(p, fs); > > for ( i =3D 0; i < ARRAY_SIZE(fs); ++i ) > @@ -1093,6 +1141,13 @@ void __init init_dom0_cpuid_policy(struc > } > > x86_cpu_featureset_to_policy(fs, p); > + > + /* > + * Default-off features with their own leaves need those leaves > + * re-populated from the max policy. > + */ > + if ( p->feat.avx10 ) > + p->avx10 =3D max->avx10; > } > > /* > @@ -1125,6 +1180,8 @@ static void __init __maybe_unused build_ > sizeof(raw_cpu_policy.feat.raw)); > BUILD_BUG_ON(sizeof(raw_cpu_policy.xstate) !=3D > sizeof(raw_cpu_policy.xstate.raw)); > + BUILD_BUG_ON(sizeof(raw_cpu_policy.avx10) !=3D > + sizeof(raw_cpu_policy.avx10.raw)); > BUILD_BUG_ON(sizeof(raw_cpu_policy.extd) !=3D > sizeof(raw_cpu_policy.extd.raw)); > } > --- a/xen/arch/x86/cpuid.c > +++ b/xen/arch/x86/cpuid.c > @@ -226,6 +226,15 @@ void guest_cpuid(const struct vcpu *v, u > *res =3D array_access_nospec(p->xstate.raw, subleaf); > break; > > + case 0x24: > + ASSERT(p->avx10.max_subleaf < ARRAY_SIZE(p->avx10.raw)); > + if ( subleaf > min_t(uint32_t, p->avx10.max_subleaf, > + ARRAY_SIZE(p->avx10.raw) - 1) ) > + return; > + > + *res =3D array_access_nospec(p->avx10.raw, subleaf); > + break; > + > default: > *res =3D array_access_nospec(p->basic.raw, leaf); > break; > --- a/xen/arch/x86/lib/cpu-policy/copy-to-buffer.c > +++ b/xen/arch/x86/lib/cpu-policy/copy-to-buffer.c > @@ -123,6 +123,13 @@ int x86_cpuid_copy_to_buffer(const struc > break; > } > > + case 0x24: > + for ( subleaf =3D 0; > + subleaf <=3D MIN(p->avx10.max_subleaf, > + ARRAY_SIZE(p->avx10.raw) - 1); ++sublea= f ) > + COPY_LEAF(leaf, subleaf, &p->avx10.raw[subleaf]); > + break; > + > default: > COPY_LEAF(leaf, XEN_CPUID_NO_SUBLEAF, &p->basic.raw[leaf]); > break; > --- a/xen/arch/x86/lib/cpu-policy/copy-from-buffer.c > +++ b/xen/arch/x86/lib/cpu-policy/copy-from-buffer.c > @@ -108,6 +108,13 @@ int x86_cpuid_copy_from_buffer(struct cp > array_access_nospec(p->xstate.raw, data.subleaf) =3D l; > break; > > + case 0x24: > + if ( data.subleaf >=3D ARRAY_SIZE(p->avx10.raw) ) > + goto out_of_range; > + > + array_access_nospec(p->avx10.raw, data.subleaf) =3D l; > + break; > + > default: > if ( data.subleaf !=3D XEN_CPUID_NO_SUBLEAF ) > goto out_of_range; > --- a/xen/arch/x86/lib/cpu-policy/cpuid.c > +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c > @@ -125,6 +125,7 @@ void x86_cpu_policy_fill_native(struct c > switch ( i ) > { > case 0x4: case 0x7: case 0xb: case 0xd: > + case 0x24: > /* Multi-invocation leaves. Deferred. */ > continue; > } > @@ -218,6 +219,15 @@ void x86_cpu_policy_fill_native(struct c > } > } > > + if ( p->basic.max_leaf >=3D 0x24 ) > + { > + cpuid_count_leaf(0x24, 0, &p->avx10.raw[0]); > + > + for ( i =3D 1; i <=3D MIN(p->avx10.max_subleaf, > + ARRAY_SIZE(p->avx10.raw) - 1); ++i ) > + cpuid_count_leaf(0x24, i, &p->avx10.raw[i]); Do we need to split the 0 iteration out ? I guess we can just start from i =3D 0 instead. > + } > + > /* Extended leaves. */ > cpuid_leaf(0x80000000U, &p->extd.raw[0]); > for ( i =3D 1; i <=3D MIN(p->extd.max_leaf & 0xffffU, > @@ -287,6 +297,9 @@ void x86_cpu_policy_clear_out_of_range_l > ARRAY_SIZE(p->xstate.raw) - 1); > } > > + if ( p->basic.max_leaf < 0x24 ) > + memset(p->avx10.raw, 0, sizeof(p->avx10.raw)); > + > zero_leaves(p->extd.raw, > ((p->extd.max_leaf >> 16) =3D=3D 0x8000 > ? (p->extd.max_leaf & 0xffff) + 1 : 0), > @@ -299,6 +312,8 @@ void __init x86_cpu_policy_bound_max_lea > min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1= ); > p->feat.max_subleaf =3D > min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - = 1); > + p->avx10.max_subleaf =3D > + min_t(uint32_t, p->avx10.max_subleaf, ARRAY_SIZE(p->avx10.raw) -= 1); > p->extd.max_leaf =3D 0x80000000U | min_t(uint32_t, p->extd.max_leaf= & 0xffff, > ARRAY_SIZE(p->extd.raw) - 1)= ; > } > @@ -326,6 +341,8 @@ void x86_cpu_policy_shrink_max_leaves(st > */ > p->basic.raw[0xd] =3D p->xstate.raw[0]; > > + p->basic.raw[0x24] =3D p->avx10.raw[0]; > + > for ( i =3D p->basic.max_leaf; i; --i ) > if ( p->basic.raw[i].a | p->basic.raw[i].b | > p->basic.raw[i].c | p->basic.raw[i].d ) > --- a/xen/arch/x86/lib/cpu-policy/policy.c > +++ b/xen/arch/x86/lib/cpu-policy/policy.c > @@ -24,6 +24,10 @@ int x86_cpu_policies_are_compatible(cons > if ( guest->feat.max_subleaf > host->feat.max_subleaf ) > FAIL_CPUID(7, 0); > > + if ( guest->avx10.version > host->avx10.version || > + guest->avx10.max_subleaf > host->avx10.max_subleaf ) > + FAIL_CPUID(0x24, 0); > + > if ( guest->extd.max_leaf > host->extd.max_leaf ) > FAIL_CPUID(0x80000000U, NA); > > --- a/xen/include/public/arch-x86/cpufeatureset.h > +++ b/xen/include/public/arch-x86/cpufeatureset.h > @@ -366,6 +366,7 @@ XEN_CPUFEATURE(PREFETCHI, 15*32 > XEN_CPUFEATURE(USER_MSR, 15*32+15) /*s U{RD,WR}MSR Instructi= ons */ > XEN_CPUFEATURE(UIRET_UIF, 15*32+17) /* UIRET updates UIF */ > XEN_CPUFEATURE(CET_SSS, 15*32+18) /* CET Supervisor Shadow= Stacks safe to use */ > +XEN_CPUFEATURE(AVX10, 15*32+19) /* AVX10 Converged Vector= ISA */ > XEN_CPUFEATURE(SLSM, 15*32+24) /* Static Lockstep Mode = */ > > /* Intel-defined CPU features, MSR_ARCH_CAPS 0x10a.eax, word 16 */ > --- a/xen/include/xen/lib/x86/cpu-policy.h > +++ b/xen/include/xen/lib/x86/cpu-policy.h > @@ -59,11 +59,12 @@ unsigned int x86_cpuid_lookup_vendor(uin > */ > const char *x86_cpuid_vendor_to_str(unsigned int vendor); > > -#define CPUID_GUEST_NR_BASIC (0xdu + 1) > +#define CPUID_GUEST_NR_BASIC (0x24u + 1) > #define CPUID_GUEST_NR_CACHE (5u + 1) > #define CPUID_GUEST_NR_FEAT (2u + 1) > #define CPUID_GUEST_NR_TOPO (1u + 1) > #define CPUID_GUEST_NR_XSTATE (62u + 1) > +#define CPUID_GUEST_NR_AVX10 (0u + 1) Intel specification now defines AVX10.2 which has a additional leaf (even though the whole leaf is currently marked as "reserved"). > #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) > #define CPUID_GUEST_NR_EXTD_AMD (0x21u + 1) > #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ > @@ -264,6 +265,19 @@ struct cpu_policy > } comp[CPUID_GUEST_NR_XSTATE]; > } xstate; > > + /* Structured AVX10 information leaf: 0x000000024[xx] */ > + union { > + struct cpuid_leaf raw[CPUID_GUEST_NR_AVX10]; > + struct { > + /* Subleaf 0. */ > + uint32_t max_subleaf; > + uint32_t version:8, :8; > + bool vsz128:1, vsz256:1, vsz512:1; > + uint32_t :13; > + uint32_t /* c */:32, /* d */:32; > + }; > + } avx10; > + > /* Extended leaves: 0x800000xx */ > union { > struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD]; > --- a/xen/tools/gen-cpuid.py > +++ b/xen/tools/gen-cpuid.py > @@ -294,7 +294,7 @@ def crunch_numbers(state): > # enabled. Certain later extensions, acting on 256-bit vectors= of > # integers, better depend on AVX2 than AVX. > AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_= INT8, > - AVX_VNNI_INT16, SHA512, SM4], > + AVX_VNNI_INT16, SHA512, SM4, AVX10], > I think we can instead make AVX10 a dependency on AVX512. Especially since > Any processor that enumerates support for Intel AVX10 will also enumerate support for Intel AVX, Intel AVX2, and Intel AVX-512 (see Table 16-2). with AVX-512 depending on AVX2. > # AVX512F is taken to mean hardware support for 512bit register= s > # (which in practice depends on the EVEX prefix to encode) as w= ell > > -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:36:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:36:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278577.1563355 (Exim 4.92) (envelope-from ) id 1wB8I6-0000BO-Ak; Fri, 10 Apr 2026 09:36:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278577.1563355; Fri, 10 Apr 2026 09:36:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8I6-0000BH-7b; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1775813799-3212551B-B8226B98/0/0 X-purgate-type: clean X-purgate-size: 5488 On 3/30/26 14:59, Mykyta Poturai wrote: Hello Mykyta > Move IRQs from dying CPU to the online ones when a CPU is getting > offlined. When onlining, rebalance all IRQs in a round-robin fashion. > Guest-bound IRQs are already handled by scheduler in the process of > moving vCPUs to active pCPUs, so we only need to handle IRQs used by Xen > itself. > > Signed-off-by: Mykyta Poturai > --- > v6->v7: > * replace ifdef with IS_ENABLED > > v5->v6: > * don't do any balancing on boot > * only do balancing when cpu hotplug is enabled > > v4->v5: > * handle CPU onlining as well > * more comments > * fix crash when ESPI is disabled > * don't assume CPU 0 is a boot CPU > * use insigned int for irq number > * remove assumption that all irqs a bound to CPU 0 by default from the > commit message > > v3->v4: > * patch introduced > --- > xen/arch/arm/include/asm/irq.h | 6 ++++ > xen/arch/arm/irq.c | 59 ++++++++++++++++++++++++++++++++++ > xen/arch/arm/smpboot.c | 7 ++++ > 3 files changed, 72 insertions(+) > > diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.h > index 09788dbfeb..3ed55e02c3 100644 > --- a/xen/arch/arm/include/asm/irq.h > +++ b/xen/arch/arm/include/asm/irq.h > @@ -126,6 +126,12 @@ bool irq_type_set_by_domain(const struct domain *d); > void irq_end_none(struct irq_desc *irq); > #define irq_end_none irq_end_none > > +#ifdef CONFIG_CPU_HOTPLUG > +void rebalance_irqs(unsigned int from, bool up); > +#else > +static inline void rebalance_irqs(unsigned int from, bool up) {} > +#endif > + > #endif /* _ASM_HW_IRQ_H */ > /* > * Local variables: > diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c > index 7204bc2b68..447bee428e 100644 > --- a/xen/arch/arm/irq.c > +++ b/xen/arch/arm/irq.c > @@ -158,6 +158,60 @@ static int init_local_irq_data(unsigned int cpu) > return 0; > } > > +#ifdef CONFIG_CPU_HOTPLUG > +static int cpu_next; > + > +static void balance_irq(int irq, unsigned int from, bool up) > +{ > + struct irq_desc *desc = irq_to_desc(irq); > + unsigned long flags; > + > + ASSERT(!cpumask_empty(&cpu_online_map)); > + > + spin_lock_irqsave(&desc->lock, flags); > + if ( likely(!desc->action) ) > + goto out; > + > + if ( likely(test_bit(_IRQ_GUEST, &desc->status) || > + test_bit(_IRQ_MOVE_PENDING, &desc->status)) ) > + goto out; > + > + /* > + * Setting affinity to a mask of multiple CPUs causes the GIC drivers to > + * select one CPU from that mask. If the dying CPU was included in the IRQ's > + * affinity mask, we cannot determine exactly which CPU the interrupt is > + * currently routed to, as GIC drivers lack a concrete get_affinity API. So > + * to be safe we must reroute it to a new, definitely online, CPU. In the > + * case of CPU going down, we move only the interrupt that could reside on > + * it. Otherwise, we rearrange all interrupts in a round-robin fashion. > + */ > + if ( !up && !cpumask_test_cpu(from, desc->affinity) ) > + goto out; > + > + cpu_next = cpumask_cycle(cpu_next, &cpu_online_map); > + irq_set_affinity(desc, cpumask_of(cpu_next)); > + > +out: > + spin_unlock_irqrestore(&desc->lock, flags); > +} > + > +void rebalance_irqs(unsigned int from, bool up) > +{ > + int irq; > + > + if ( cpumask_empty(&cpu_online_map) ) > + return; > + > + for ( irq = NR_LOCAL_IRQS; irq < NR_IRQS; irq++ ) > + balance_irq(irq, from, up); > + > +#ifdef CONFIG_GICV3_ESPI > + for ( irq = ESPI_BASE_INTID; irq < ESPI_MAX_INTID; irq++ ) > + balance_irq(irq, from, up); I think, here we have an inefficient iteration over the ESPI range. Even when CONFIG_GICV3_ESPI=y, the GIC HW might not support ESPIs at runtime. We should probably check if they are present before entering the loop so we do not waste cycles on 1024 unnecessary NULL lookups. Could we use something like ESPI_BASE_INTID + gic_number_espis() to set the loop boundary? What do you think? > +#endif > +} > +#endif /* CONFIG_CPU_HOTPLUG */ > + > static int cpu_callback(struct notifier_block *nfb, unsigned long action, > void *hcpu) > { > @@ -172,6 +226,11 @@ static int cpu_callback(struct notifier_block *nfb, unsigned long action, > printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\n", > cpu); > break; > + case CPU_ONLINE: > + if ( IS_ENABLED(CONFIG_CPU_HOTPLUG) && > + system_state >= SYS_STATE_active ) > + rebalance_irqs(cpu, true); > + break; > } > > return notifier_from_errno(rc); > diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c > index 7f3cfa812e..7d877179c0 100644 > --- a/xen/arch/arm/smpboot.c > +++ b/xen/arch/arm/smpboot.c > @@ -425,6 +425,13 @@ void __cpu_disable(void) > > smp_mb(); > > + /* > + * Now that the interrupts are cleared and the CPU marked as offline, > + * move interrupts out of it > + */ > + if ( IS_ENABLED(CONFIG_CPU_HOTPLUG) ) > + rebalance_irqs(cpu, false); > + > /* Return to caller; eventually the IPI mechanism will unwind and the > * scheduler will drop to the idle loop, which will call stop_cpu(). */ > } From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:38:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 09:38:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278586.1563366 (Exim 4.92) (envelope-from ) id 1wB8Ju-0000rj-Ln; Fri, 10 Apr 2026 09:38:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278586.1563366; Fri, 10 Apr 2026 09:38:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8Ju-0000rc-IE; Fri, 10 Apr 2026 09:38:34 +0000 Received: by outflank-mailman (input) for mailman id 1278586; Fri, 10 Apr 2026 09:38:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8Jt-0000rU-KA for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 09:38:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB8Jt-00BbKX-0C for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 11:38:33 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8c512-e002-0a2a0a5209dd-0a2a450ae7ac-14 for ; Fri, 10 Apr 2026 11:38:32 +0200 Received: from [209.85.218.44] (helo=mail-ej1-f44.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8c518-ee98-0a2a450a0019-d155da2cf11d-3 for ; Fri, 10 Apr 2026 11:38:32 +0200 Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-b9825ba7e8dso260267566b.3 for ; Fri, 10 Apr 2026 02:38:32 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Per IHI0048B.b section 2.3.1, clearing IRQBypDisGrp{0,1} and FIQBypDisGrp{0,1} selects bypass rather than deasserted interrupt outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully disabling the interface. Fix this by reading GICC_CTLR, setting the bypass-disable bits, and clearing both group-enable bits before writing the value back. Keep the existing GICC_CTL_ENABLE definition for the init path and use a separate mask for the shutdown-side group-enable handling. Section 2.3.2 also states that wakeup event signals remain available even when both GIC interrupt signaling and interrupt bypass are disabled, so disabling bypass does not break the power-management use case, i.e. suspend modes. Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") Signed-off-by: Mykola Kvach --- xen/arch/arm/gic-v2.c | 7 ++++++- xen/arch/arm/include/asm/gic.h | 21 +++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index b23e72a3d0..22aa25bad0 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -408,7 +408,12 @@ static void gicv2_cpu_init(void) static void gicv2_cpu_disable(void) { - writel_gicc(0x0, GICC_CTLR); + uint32_t ctlr = readl_gicc(GICC_CTLR); + + ctlr |= GICC_CTL_BYP_DIS_MASK; + ctlr &= ~GICC_CTL_ENABLE_GRP_MASK; + + writel_gicc(ctlr, GICC_CTLR); } static void gicv2_hyp_init(void) diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 8e713aa477..da285adb83 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -102,8 +102,25 @@ #define GICD_TYPE_SEC 0x400 #define GICD_TYPER_DVIS (1U << 18) -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) +/* + * Keep the legacy name for bit[0]. In the Non-secure view of a GICv2 with + * Security Extensions this is the Group 1 enable bit; otherwise it is the + * Group 0. + */ +#define GICC_CTL_ENABLE (0x1 << 0) +/* Bit[1] is the second group-enable bit when separate group enables exist. */ +#define GICC_CTL_ENABLE_GRP1 (0x1 << 1) +#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5) +#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6) +#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7) +#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8) +#define GICC_CTL_EOI (0x1 << 9) + +/* Shutdown clears both possible group-enable bits, regardless of layout. */ +#define GICC_CTL_ENABLE_GRP_MASK (GICC_CTL_ENABLE | GICC_CTL_ENABLE_GRP1) +#define GICC_CTL_BYP_DIS_MASK \ + (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0 | \ + GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1) #define GICC_IA_IRQ 0x03ff #define GICC_IA_CPU_MASK 0x1c00 -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 09:51:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 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X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM1PEPF000252DD.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB9134 X-purgate-ID: tlsNG-ebf023/1775815123-B031451B-1C2ECF3B/0/0 X-purgate-type: clean X-purgate-size: 821 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > In current implementation io_domain is allocated once for each xen > domain as Stage2 translation is common for all devices in same xen > domain. >=20 > Nested stage supports S1 and S2 configuration at the same time. Stage1 > translation will be different for each device as linux kernel will > allocate page-table for each device. >=20 > Alloc io_domain for each device so that each device can have different > Stage-1 and Stage-2 configuration structure. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- Looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:06:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:06:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278627.1563392 (Exim 4.92) (envelope-from ) id 1wB8lF-00061s-99; Fri, 10 Apr 2026 10:06:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278627.1563392; Fri, 10 Apr 2026 10:06:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8lF-00061l-5T; Fri, 10 Apr 2026 10:06:49 +0000 Received: by outflank-mailman (input) for mailman id 1278627; Fri, 10 Apr 2026 10:06:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8lE-00061f-5P for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 10:06:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB8lD-00E48T-D9 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 12:06:47 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8cbb2-bab6-0a2a0a5309dd-0a2a45039446-24 for ; Fri, 10 Apr 2026 12:06:47 +0200 Received: from [162.55.131.47] (helo=support.bugseng.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8cbb7-02b3-0a2a45030019-a237832fa6c2-3 for ; Fri, 10 Apr 2026 12:06:47 +0200 Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) (Authenticated sender: nicola) by support.bugseng.com (Postfix) with ESMTPA id D271D4EE3D1A; Fri, 10 Apr 2026 12:06:46 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: bugseng.com; arc=none smtp.remote-ip=162.55.131.47 ARC-Seal: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; cv=none; t=1775815607; b=MjdY4/JVIuAW9N36xCD3YXm3JotM3V+RfEQt+4MziYEvN3e07ypH3uL2PS6tRREgPlrh eFgNSqpj0cFZszk/EYt3w+spZnkqYb0xtfH4bYb8Al6KRLp0iDn9/G6mgli7yYdyv7Xlx 9n8VMNGEkH/66VjLita3reZoMxBeSUX/ee72S0qQpcayF7QSx+yUBmzqBmEoRwEv4qUsT F9hVA/Ckp6O2BDKpCq15pnPFqc6aNIYCoW77+t34/diJIn7ls71oezMVWks24x/r6L+nE zHfqxZReahftdzo/7YmKBOStHNPBwxH2zm6bKgQ3Pk6WgCgdEBilPocP+7fG9eXiDE3uc f7oGk50b/4p+wvrYevGaQh5MVoS3Vvz6fBUULWsoq40Bn/DXsysE52a+dsqf52huG3f9Q emMM9isp+9Y2uDeeJfYZsF9tvmJSW9xajTXZw/m02EBpsJSY5b5QYZm5kNd2WC5UHEaQx +Wb9Wg+d3Kche3Ig0TRbdpsELuO6JR1DuDDzRAat5NIU5BjUbtVHF2y1ap/P1xyeDFGNG g+wHznknrWKFQ1eMLsRhsaYYYB9SqClBmHRqIO/KNhjUye0SiQ1f8cHOAMStNcKzssRdY lNFpNAzcKujryKs4TxupYSl7dwwcYdzpz48RKGdBpiQ+AZbHyc7Idztyk0XTEZI= ARC-Message-Signature: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; c=relaxed/relaxed; t=1775815607; h=MIME-Version:Date:From:To:Cc:Subject:In-Reply-To:References: Message-ID:X-Sender:Organization:Content-Type: Content-Transfer-Encoding; bh=AthjxD6bIMJJOd71BX/xR7xA5ig717DgsSmNBAcifVk=; b=p6/i966JC5eohSNNJHNMFqvLHODPP0jTYVQ2tMzma/LuQHu3yT3TONHOe+FMD5GqNS2I DycIguteQVprseFuqRXk/7o+JFEWkCZSry+CZu2vdU+8/VHRrIgZQnKWHWohY59EWv9rv FnsjN3Xi8irTxVeLctxsbMB5Apppflv4QwpsmjzN1BjbyFuVWctVY48dlwYbBDEli1AE9 ufSWhHN8Iq38NX7LUMJTi4N0dT//s4fMnAQ5cdqGfKm2HDbIXxTmnxQhrWinml9/GSEKo dn/kHsqNIIdiY2dg4ZJjGv91WVF6mUGEhJ4ui5aGzhiyzZTYJIvEyc3ATBKYKoXykn120 y4kE7imA9xSm7BfHEu4cFUewSVWBGlPnQS/o3/bEJc9la2ueRnKsNOCw6xQCUziwIQFDV jCKQvA20GE4ccrZPg75HV98ba6Oav5Rpjp1gKkj9dFyzFxhRjxU34TyNdfiPCDuuJ1MyF FLambikrRCFlik5WYeSdYY23MF/m2v7+IpGoFAgn6fFzUM0GbmzXkhpKBUntwmA4tXvOB 5FRt2evvljrLp0SwuPUVzRytfpgPPX92FO+8i1zKj/33zE4ZKZfVygl7xsoyRCRNBzsHR 6SIlTCaxeE9LrblsYESUmkiX6jdHiR+e/zZenwqpN98KTO3AAb2wKN4Ybj1wL24= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Fri, 10 Apr 2026 12:06:46 +0200 From: Nicola Vetrini To: Jan Beulich Cc: xen-devel@lists.xenproject.org, Gyujeong Jin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: Re: [BUG] Potential double-free in Xen dt-overlay attach/remove error path In-Reply-To: References: Message-ID: X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1775815607-CB126C9A-4606EAD9/0/0 X-purgate-type: clean X-purgate-size: 3052 On 2026-04-10 08:31, Jan Beulich wrote: > On 09.04.2026 23:28, Gyujeong Jin wrote: >> Hello Team, I was advised to report this issue in this way because >> dt-overlay is currently experimental and not security supported. >> >> I would like to report a potential memory safety issue in Xen related >> to >> the Device Tree overlay handling logic. >> ------------------------------ >> Problem Description >> >> A double-free / use-after-free condition may occur in the dt-overlay >> handling path when an overlay attachment fails and the same overlay is >> later removed. >> >> The issue arises because rangeset objects are freed on the failure >> path of >> handle_attach_overlay_nodes(), but the corresponding pointers are not >> cleared. Subsequently, handle_remove_overlay_nodes() may operate on >> these >> stale pointers, leading to a second free. >> Affected Component >> >> - Xen ARM >> - Device Tree overlay subsystem >> - File: xen/common/device-tree/dt-overlay.c >> >> Relevant functions: >> >> - handle_attach_overlay_nodes() >> - handle_remove_overlay_nodes() >> >> Impact >> >> This issue may lead to: >> >> - Double-free of rangeset structures >> - Use-after-free when accessing stale pointers >> - Potential hypervisor crash (DoS) >> - Possible memory corruption depending on allocator behavior >> >> Given that this occurs in the hypervisor context, the impact could >> extend >> beyond a simple crash under certain conditions. >> Root Cause >> >> The issue originates from inconsistent memory management between the >> attach >> failure path and the remove path. >> >> In handle_attach_overlay_nodes(), the failure path frees rangeset >> objects: >> >> static long handle_attach_overlay_nodes(...) >> { >> ... >> >> if ( entry ) >> { >> rangeset_destroy(entry->irq_ranges); >> rangeset_destroy(entry->iomem_ranges); >> } >> >> return rc; >> } >> >> However, the corresponding pointers (entry->irq_ranges and >> entry->iomem_ranges) are not set to NULL afterward, leaving dangling >> pointers in the entry structure. > > Further to this, am I overlooking any check preventing an already > created > pair of rangesets to be replaced by new ones, leaking the original > pair? > > And then there's a Misra issue as well: dt_overlay_domctl() has > unreachable > code. Anything other than XEN_DOMCTL_DT_OVERLAY_ATTACH is excluded at > the > top, so the "else" body near the bottom is unreachable. (This in turn > makes > me wonder: How come there's no "detach"?) Yet then, that's probably > pretty > meaningless, as there look to be other issues (Misra and general > robustness > ones) as well. > > Jan Is it by any chance enabled in *-allcode analyses? I don't see such reports for unreachable code on ARM64. -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:09:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:09:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278638.1563409 (Exim 4.92) (envelope-from ) id 1wB8nq-0006tl-RH; Fri, 10 Apr 2026 10:09:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278638.1563409; Fri, 10 Apr 2026 10:09:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8nq-0006te-ON; Fri, 10 Apr 2026 10:09:30 +0000 Received: by outflank-mailman (input) for mailman id 1278638; Fri, 10 Apr 2026 10:09:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8no-0006gS-UL for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775815766; x=1776076266; i=teddy.astie@vates.tech; bh=YaD3wL81QOyOKzJ4o6EbQmXAFBu+LZDByU7J9GRr2VA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=C+jlkMHkhSu+DbBrBHyxpW13Q+ol+aW4tc9fELU/auog5ji8n56LLaZO5WKuFxgHz LkFyjXHgdtTsfksjD+bD3mo2Fdh3qcjwvpY+UHZEfrtlij5fo4qlbYvGt7dCqbOcvW hUJVX2CZkjbOdvZFZ9ZH8Rx+bZcbN+0ydLtTJgSZsqSC1gBN4sLnGFg55c61HKgatM mdZiV6MUvcisw8pir1Spr0CJSJAQyIRj5cBVmibS7zsCqMSpkoR3zAlKBIivFmGEQc N3WrzIluLLuXdQE8r/iCJw3VCVkfF+bjtuNK0ioEyLA+o4zyaY7sWfmPpEBSmMg4Fi 3buVDWtoPccBw== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=202/2]=20vtd:=20Replace=20macros=20with=20bitfield?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775815765889 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: <3182da144d0cb998c9ae897b55285b7e408cd972.1775814143.git.teddy.astie@vates.tech> In-Reply-To: <815edfd0db90859a4ce270d833d9d721ff66e31c.1775814143.git.teddy.astie@vates.tech> References: <815edfd0db90859a4ce270d833d9d721ff66e31c.1775814143.git.teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.ed78c97418584d2a93b5e2fa7768da7d?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 10:09:26 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1775815768-F5557497-310C376F/0/0 X-purgate-type: clean X-purgate-size: 18951 Replace macros with bitfield to allow simplyfing the code and be less error prone when manipulating PTEs. It also has the effect of directly exposing the mfn in the pte struct instead of derivating it from the raw pte value using dma_pte_addr(). Signed-off-by: Teddy Astie --- It allows nicer constructs like new.snp = iommu_snoop; instead of if ( iommu_snoop ) dma_set_pte_snp(new); A lot of simplifications could be done afterward when switching the logic from maddrs to mfns i.e remove many maddr-mfn conversions. bloat-o-meter (along with the previous change) add/remove: 0/0 grow/shrink: 7/3 up/down: 227/-45 (182) Function old new delta addr_to_dma_page_maddr 949 1058 +109 vtd_dump_page_table_level 197 233 +36 fill_qpt 1151 1178 +27 print_vtd_entries 486 504 +18 domain_context_mapping_one 2098 2114 +16 intel_iommu_map_page 909 921 +12 intel_iommu_unmap_page 731 740 +9 intel_iommu_lookup_page 185 176 -9 queue_free_pt 442 425 -17 vtd_dump_page_table_level.cold 86 67 -19 Total: Before=18446744073715636162, After=18446744073715636344, chg +0.00% I guess using mfns 'everywhere' would improve the bloat-o-meter picture. xen/drivers/passthrough/vtd/iommu.c | 120 +++++++++++++--------------- xen/drivers/passthrough/vtd/iommu.h | 44 +++++----- xen/drivers/passthrough/vtd/utils.c | 16 ++-- 3 files changed, 85 insertions(+), 95 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index cf97469957..eeebc73d26 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -321,7 +321,7 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, { struct domain_iommu *hd = dom_iommu(domain); int addr_width = agaw_to_width(hd->arch.vtd.agaw); - struct dma_pte *parent, *pte = NULL; + union dma_pte *parent, *pte = NULL; unsigned int level = agaw_to_level(hd->arch.vtd.agaw), offset; u64 pte_maddr = 0; @@ -350,15 +350,15 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, offset = address_level_offset(addr, level); pte = &parent[offset]; - pte_maddr = dma_pte_addr(*pte); - if ( !dma_pte_present(*pte) || (level > 1 && dma_pte_superpage(*pte)) ) + pte_maddr = mfn_to_maddr(pte->mfn); + if ( !dma_pte_present(*pte) || (level > 1 && pte->sp) ) { struct page_info *pg; /* * Higher level tables always set r/w, last level page table * controls read/write. */ - struct dma_pte new_pte = { DMA_PTE_PROT }; + union dma_pte new_pte = { .r = true, .w = true }; if ( !alloc ) { @@ -371,9 +371,8 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, * with the address adjusted to account for the residual of * the walk. */ - pte_maddr = (pte->val & PADDR_MASK) + - (addr & ((1UL << level_to_offset_bits(level)) - 1) & - PAGE_MASK); + pte_maddr = mfn_to_maddr(pte->mfn) + + (addr & ((1UL << level_to_offset_bits(level)) - 1) & PAGE_MASK); if ( !target ) break; } @@ -384,20 +383,20 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, break; pte_maddr = page_to_maddr(pg); - dma_set_pte_addr(new_pte, pte_maddr); + new_pte.mfn = maddr_to_mfn(pte_maddr); if ( dma_pte_present(*pte) ) { - struct dma_pte *split = map_vtd_domain_page(pte_maddr); + union dma_pte *split = map_vtd_domain_page(pte_maddr); unsigned long inc = 1UL << level_to_offset_bits(level - 1); - split[0].val |= pte->val & ~DMA_PTE_CONTIG_MASK; + split[0].raw |= pte->raw & ~DMA_PTE_CONTIG_MASK; if ( inc == PAGE_SIZE ) - split[0].val &= ~DMA_PTE_SP; + split[0].sp = false; for ( offset = 1; offset < PTE_NUM; ++offset ) - split[offset].val |= - (split[offset - 1].val & ~DMA_PTE_CONTIG_MASK) + inc; + split[offset].raw |= + (split[offset - 1].raw & ~DMA_PTE_CONTIG_MASK) + inc; iommu_sync_cache(split, PAGE_SIZE); unmap_vtd_domain_page(split); @@ -408,9 +407,9 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, perfc_incr(iommu_pt_shatters); } - write_atomic(&pte->val, new_pte.val); - iommu_sync_cache(pte, sizeof(struct dma_pte)); - pt_update_contig_markers(&parent->val, + write_atomic(&pte->raw, new_pte.raw); + iommu_sync_cache(pte, sizeof(union dma_pte)); + pt_update_contig_markers(&parent->raw, address_level_offset(addr, level), level, PTE_kind_table); } @@ -418,7 +417,7 @@ static uint64_t addr_to_dma_page_maddr(struct domain *domain, daddr_t addr, if ( --level == target ) { if ( !target ) - pte_maddr = pte->val & PADDR_MASK; + pte_maddr = mfn_to_maddr(pte->mfn); break; } @@ -469,9 +468,9 @@ static paddr_t domain_pgd_maddr(struct domain *d, paddr_t pgd_maddr, agaw != level_to_agaw(nr_pt_levels); agaw-- ) { - const struct dma_pte *p = map_vtd_domain_page(pgd_maddr); + const union dma_pte *p = map_vtd_domain_page(pgd_maddr); - pgd_maddr = dma_pte_addr(*p); + pgd_maddr = mfn_to_maddr(p->mfn); unmap_vtd_domain_page(p); if ( !pgd_maddr ) return 0; @@ -783,13 +782,12 @@ static void queue_free_pt(struct domain_iommu *hd, mfn_t mfn, unsigned int level { if ( level > 1 ) { - struct dma_pte *pt = map_domain_page(mfn); + union dma_pte *pt = map_domain_page(mfn); unsigned int i; for ( i = 0; i < PTE_NUM; ++i ) - if ( dma_pte_present(pt[i]) && !dma_pte_superpage(pt[i]) ) - queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(pt[i])), - level - 1); + if ( dma_pte_present(pt[i]) && !pt[i].sp ) + queue_free_pt(hd, pt[i].mfn, level - 1); unmap_domain_page(pt); } @@ -2074,7 +2072,7 @@ static int __must_check cf_check intel_iommu_map_page( unsigned int *flush_flags) { struct domain_iommu *hd = dom_iommu(d); - struct dma_pte *page, *pte, old, new = {}; + union dma_pte *page, *pte, old, new = {}; u64 pg_maddr; unsigned int level = (IOMMUF_order(flags) / LEVEL_STRIDE) + 1; int rc = 0; @@ -2112,22 +2110,18 @@ static int __must_check cf_check intel_iommu_map_page( return -ENOMEM; } - page = (struct dma_pte *)map_vtd_domain_page(pg_maddr); + page = (union dma_pte *)map_vtd_domain_page(pg_maddr); pte = &page[address_level_offset(dfn_to_daddr(dfn), level)]; old = *pte; - dma_set_pte_addr(new, mfn_to_maddr(mfn)); - dma_set_pte_prot(new, - ((flags & IOMMUF_readable) ? DMA_PTE_READ : 0) | - ((flags & IOMMUF_writable) ? DMA_PTE_WRITE : 0)); - if ( IOMMUF_order(flags) ) - dma_set_pte_superpage(new); - + new.mfn = mfn; + new.r = flags & IOMMUF_readable; + new.w = flags & IOMMUF_writable; + new.sp = IOMMUF_order(flags) > 0; /* Set the SNP on leaf page table if Snoop Control available */ - if ( iommu_snoop ) - dma_set_pte_snp(new); + new.snp = iommu_snoop; - if ( !((old.val ^ new.val) & ~DMA_PTE_CONTIG_MASK) ) + if ( !((old.raw ^ new.raw) & ~DMA_PTE_CONTIG_MASK) ) { spin_unlock(&hd->arch.mapping_lock); unmap_vtd_domain_page(page); @@ -2135,7 +2129,7 @@ static int __must_check cf_check intel_iommu_map_page( } *pte = new; - iommu_sync_cache(pte, sizeof(struct dma_pte)); + iommu_sync_cache(pte, sizeof(union dma_pte)); /* * While the (ab)use of PTE_kind_table here allows to save some work in @@ -2144,7 +2138,7 @@ static int __must_check cf_check intel_iommu_map_page( * based laptop. This also has the intended effect of terminating the * loop when super pages aren't supported anymore at the next level. */ - while ( pt_update_contig_markers(&page->val, + while ( pt_update_contig_markers(&page->raw, address_level_offset(dfn_to_daddr(dfn), level), level, (hd->platform_ops->page_sizes & @@ -2155,8 +2149,8 @@ static int __must_check cf_check intel_iommu_map_page( unmap_vtd_domain_page(page); - new.val &= ~(LEVEL_MASK << level_to_offset_bits(level)); - dma_set_pte_superpage(new); + new.raw &= ~(LEVEL_MASK << level_to_offset_bits(level)); + new.sp = true; pg_maddr = addr_to_dma_page_maddr(d, dfn_to_daddr(dfn), ++level, flush_flags, false); @@ -2180,9 +2174,8 @@ static int __must_check cf_check intel_iommu_map_page( { *flush_flags |= IOMMU_FLUSHF_modified; - if ( IOMMUF_order(flags) && !dma_pte_superpage(old) ) - queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), - IOMMUF_order(flags) / LEVEL_STRIDE); + if ( IOMMUF_order(flags) && !old.sp ) + queue_free_pt(hd, old.mfn, IOMMUF_order(flags) / LEVEL_STRIDE); } return rc; @@ -2193,7 +2186,7 @@ static int __must_check cf_check intel_iommu_unmap_page( { struct domain_iommu *hd = dom_iommu(d); daddr_t addr = dfn_to_daddr(dfn); - struct dma_pte *page = NULL, *pte = NULL, old; + union dma_pte *page = NULL, *pte = NULL, old; uint64_t pg_maddr; unsigned int level = (order / LEVEL_STRIDE) + 1; @@ -2231,10 +2224,10 @@ static int __must_check cf_check intel_iommu_unmap_page( } old = *pte; - dma_clear_pte(*pte); + pte->raw = 0; iommu_sync_cache(pte, sizeof(*pte)); - while ( pt_update_contig_markers(&page->val, + while ( pt_update_contig_markers(&page->raw, address_level_offset(addr, level), level, PTE_kind_null) && ++level < min_pt_levels ) @@ -2248,7 +2241,7 @@ static int __must_check cf_check intel_iommu_unmap_page( page = map_vtd_domain_page(pg_maddr); pte = &page[address_level_offset(addr, level)]; - dma_clear_pte(*pte); + pte->raw = 0; iommu_sync_cache(pte, sizeof(*pte)); *flush_flags |= IOMMU_FLUSHF_all; @@ -2262,9 +2255,8 @@ static int __must_check cf_check intel_iommu_unmap_page( *flush_flags |= IOMMU_FLUSHF_modified; - if ( order && !dma_pte_superpage(old) ) - queue_free_pt(hd, maddr_to_mfn(dma_pte_addr(old)), - order / LEVEL_STRIDE); + if ( order && !old.sp ) + queue_free_pt(hd, old.mfn, order / LEVEL_STRIDE); return 0; } @@ -3055,9 +3047,9 @@ static void cf_check vtd_resume(void) static void vtd_dump_page_table_level(paddr_t pt_maddr, int level, paddr_t gpa, int indent) { - paddr_t address; + daddr_t address; int i; - struct dma_pte *pt_vaddr, *pte; + union dma_pte *pt_vaddr, *pte; int next_level; if ( level < 1 ) @@ -3076,16 +3068,16 @@ static void vtd_dump_page_table_level(paddr_t pt_maddr, int level, paddr_t gpa, continue; address = gpa + offset_level_address(i, level); - if ( next_level && !dma_pte_superpage(*pte) ) - vtd_dump_page_table_level(dma_pte_addr(*pte), next_level, + if ( next_level && !pte->sp ) + vtd_dump_page_table_level(mfn_to_maddr(pte->mfn), next_level, address, indent + 1); else printk("%*sdfn: %08lx mfn: %08lx %c%c\n", indent, "", (unsigned long)(address >> PAGE_SHIFT_4K), - (unsigned long)(dma_pte_addr(*pte) >> PAGE_SHIFT_4K), - dma_pte_read(*pte) ? 'r' : '-', - dma_pte_write(*pte) ? 'w' : '-'); + (unsigned long)(pte->mfn), + pte->r ? 'r' : '-', + pte->w ? 'w' : '-'); } unmap_vtd_domain_page(pt_vaddr); @@ -3101,7 +3093,7 @@ static void cf_check vtd_dump_page_tables(struct domain *d) agaw_to_level(hd->arch.vtd.agaw), 0, 0); } -static int fill_qpt(struct dma_pte *this, unsigned int level, +static int fill_qpt(union dma_pte *this, unsigned int level, struct page_info *pgs[6]) { struct domain_iommu *hd = dom_iommu(dom_io); @@ -3110,7 +3102,7 @@ static int fill_qpt(struct dma_pte *this, unsigned int level, for ( i = 0; !rc && i < PTE_NUM; ++i ) { - struct dma_pte *pte = &this[i], *next; + union dma_pte *pte = &this[i], *next; if ( !dma_pte_present(*pte) ) { @@ -3136,13 +3128,13 @@ static int fill_qpt(struct dma_pte *this, unsigned int level, } } - dma_set_pte_addr(*pte, page_to_maddr(pgs[level])); - dma_set_pte_readable(*pte); - dma_set_pte_writable(*pte); + pte->mfn = page_to_mfn(pgs[level]); + pte->r = true; + pte->w = true; } - else if ( level && !dma_pte_superpage(*pte) ) + else if ( level && !pte->sp ) { - next = map_vtd_domain_page(dma_pte_addr(*pte)); + next = map_vtd_domain_page(mfn_to_maddr(pte->mfn)); rc = fill_qpt(next, level - 1, pgs); unmap_vtd_domain_page(next); } @@ -3212,7 +3204,7 @@ static int cf_check intel_iommu_quarantine_init(struct pci_dev *pdev, if ( !rc && scratch_page ) { - struct dma_pte *root; + union dma_pte *root; struct page_info *pgs[6] = {}; root = map_vtd_domain_page(pdev->arch.vtd.pgd_maddr); diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h index ccb00889d7..7a4534b7fd 100644 --- a/xen/drivers/passthrough/vtd/iommu.h +++ b/xen/drivers/passthrough/vtd/iommu.h @@ -258,31 +258,29 @@ struct context_entry { * 62: reserved * 63: available */ -struct dma_pte { - u64 val; +union dma_pte { + uint64_t raw; + struct { + bool r:1; + bool w:1; + bool :1; /* Ignored */ + unsigned int emt:3; + bool ipat:1; + bool sp:1; + bool a:1; + bool d:1; + bool :1; /* Ignored */ + bool snp:1; + unsigned long mfn:40; + unsigned int pt_contig_mask:4; /* Available */ + unsigned int :6; /* Available */ + bool :1; /* Reserved */ + bool :1; /* Available */ + }; }; -#define DMA_PTE_READ (1) -#define DMA_PTE_WRITE (2) -#define DMA_PTE_PROT (DMA_PTE_READ | DMA_PTE_WRITE) -#define DMA_PTE_SP (1 << 7) -#define DMA_PTE_SNP (1 << 11) + #define DMA_PTE_CONTIG_MASK (0xfULL << PADDR_BITS) -#define dma_clear_pte(p) do {(p).val = 0;} while(0) -#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while(0) -#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while(0) -#define dma_set_pte_superpage(p) do {(p).val |= DMA_PTE_SP;} while(0) -#define dma_set_pte_snp(p) do {(p).val |= DMA_PTE_SNP;} while(0) -#define dma_set_pte_prot(p, prot) do { \ - (p).val = ((p).val & ~DMA_PTE_PROT) | ((prot) & DMA_PTE_PROT); \ - } while (0) -#define dma_pte_prot(p) ((p).val & DMA_PTE_PROT) -#define dma_pte_read(p) (dma_pte_prot(p) & DMA_PTE_READ) -#define dma_pte_write(p) (dma_pte_prot(p) & DMA_PTE_WRITE) -#define dma_pte_addr(p) ((p).val & PADDR_MASK & PAGE_MASK_4K) -#define dma_set_pte_addr(p, addr) do {\ - (p).val |= ((addr) & PADDR_MASK & PAGE_MASK_4K); } while (0) -#define dma_pte_present(p) (((p).val & DMA_PTE_PROT) != 0) -#define dma_pte_superpage(p) (((p).val & DMA_PTE_SP) != 0) +#define dma_pte_present(p) ((p).r || (p).w) /* interrupt remap entry */ struct iremap_entry { diff --git a/xen/drivers/passthrough/vtd/utils.c b/xen/drivers/passthrough/vtd/utils.c index 7c4d032f4f..ac26a1f52d 100644 --- a/xen/drivers/passthrough/vtd/utils.c +++ b/xen/drivers/passthrough/vtd/utils.c @@ -91,8 +91,8 @@ void print_vtd_entries(struct vtd_iommu *iommu, int bus, int devfn, u64 gmfn) { struct context_entry *ctxt_entry; struct root_entry *root_entry; - struct dma_pte pte; - u64 *l, val; + union dma_pte pte, *l; + u64 val; u32 l_index, level; printk("print_vtd_entries: iommu #%u dev %pp gmfn %"PRI_gfn"\n", @@ -142,15 +142,15 @@ void print_vtd_entries(struct vtd_iommu *iommu, int bus, int devfn, u64 gmfn) { l = map_vtd_domain_page(val); l_index = get_level_index(gmfn, level); - pte.val = l[l_index]; + pte = l[l_index]; unmap_vtd_domain_page(l); - printk(" l%u[%03x] = %"PRIx64" %c%c\n", level, l_index, pte.val, - dma_pte_read(pte) ? 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charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775815767-5EF353D8-3686972D/0/0 X-purgate-type: clean X-purgate-size: 1381 `val` comes from `addr_to_dma_page_maddr()` which is a pagetable paddr and doesn't leak the PTE flags in it. Rather than returning entries without any permissions, assume they are always r/w. Fixes: dd93d54fef0b2 ("vtd: add lookup_page method to iommu_ops") Signed-off-by: Teddy Astie --- This doesn't really matter since the lookup ops are not used currently (and not implemented on the AMD side), hence it's not a problem in practice. Perhaps we want to drop the function for the time being, and reintroduce it when it gets useful ? xen/drivers/passthrough/vtd/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 3d6f787b3c..cf97469957 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2293,8 +2293,8 @@ static int cf_check intel_iommu_lookup_page( return -ENOENT; *mfn = maddr_to_mfn(val); - *flags = val & DMA_PTE_READ ? IOMMUF_readable : 0; - *flags |= val & DMA_PTE_WRITE ? IOMMUF_writable : 0; + /* TODO: Populate flags from pte */ + *flags = IOMMUF_readable | IOMMUF_writable; return 0; } -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:11:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:11:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278656.1563418 (Exim 4.92) (envelope-from ) id 1wB8pS-0000Fv-B3; Fri, 10 Apr 2026 10:11:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278656.1563418; Fri, 10 Apr 2026 10:11:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8pS-0000Fn-8C; Fri, 10 Apr 2026 10:11:10 +0000 Received: by outflank-mailman (input) for mailman id 1278656; Fri, 10 Apr 2026 10:11:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8pQ-0000FZ-Ne for xen-devel@lists.xenproject.org; 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Message-ID: <973890d8-aabb-4abe-ac8e-f1e77f4e13dd@citrix.com> Date: Fri, 10 Apr 2026 11:11:00 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , xen-devel@lists.xenproject.org, Gyujeong Jin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: Re: [BUG] Potential double-free in Xen dt-overlay attach/remove error path To: Nicola Vetrini , Jan Beulich References: Content-Language: en-GB From: Andrew Cooper In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: PR3P251CA0011.EURP251.PROD.OUTLOOK.COM (2603:10a6:102:b5::21) To CH8PR03MB8275.namprd03.prod.outlook.com (2603:10b6:610:2b9::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR03MB8275:EE_|CO1PR03MB7867:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f5d11e7-ba96-47ee-38c5-08de96e9797b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|22082099003|56012099003|18002099003; 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Subsequently, handle_remove_overlay_nodes() may operate on >>> these >>> stale pointers, leading to a second free. >>> Affected Component >>> >>>    - Xen ARM >>>    - Device Tree overlay subsystem >>>    - File: xen/common/device-tree/dt-overlay.c >>> >>> Relevant functions: >>> >>>    - handle_attach_overlay_nodes() >>>    - handle_remove_overlay_nodes() >>> >>> Impact >>> >>> This issue may lead to: >>> >>>    - Double-free of rangeset structures >>>    - Use-after-free when accessing stale pointers >>>    - Potential hypervisor crash (DoS) >>>    - Possible memory corruption depending on allocator behavior >>> >>> Given that this occurs in the hypervisor context, the impact could >>> extend >>> beyond a simple crash under certain conditions. >>> Root Cause >>> >>> The issue originates from inconsistent memory management between the >>> attach >>> failure path and the remove path. >>> >>> In handle_attach_overlay_nodes(), the failure path frees rangeset >>> objects: >>> >>> static long handle_attach_overlay_nodes(...) >>> { >>>     ... >>> >>>     if ( entry ) >>>     { >>>         rangeset_destroy(entry->irq_ranges); >>>         rangeset_destroy(entry->iomem_ranges); >>>     } >>> >>>     return rc; >>> } >>> >>> However, the corresponding pointers (entry->irq_ranges and >>> entry->iomem_ranges) are not set to NULL afterward, leaving dangling >>> pointers in the entry structure. >> >> Further to this, am I overlooking any check preventing an already >> created >> pair of rangesets to be replaced by new ones, leaking the original pair? >> >> And then there's a Misra issue as well: dt_overlay_domctl() has >> unreachable >> code. Anything other than XEN_DOMCTL_DT_OVERLAY_ATTACH is excluded at >> the >> top, so the "else" body near the bottom is unreachable. (This in turn >> makes >> me wonder: How come there's no "detach"?) Yet then, that's probably >> pretty >> meaningless, as there look to be other issues (Misra and general >> robustness >> ones) as well. >> >> Jan > > Is it by any chance enabled in *-allcode analyses? I don't see such > reports for unreachable code on ARM64. > eclair-ARM64-allcode:     ...     EXTRA_XEN_CONFIG: |         ...         CONFIG_OVERLAY_DTB=y Seems to be, yes. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:14:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:14:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278668.1563427 (Exim 4.92) (envelope-from ) id 1wB8t0-0000qK-Pq; Fri, 10 Apr 2026 10:14:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278668.1563427; Fri, 10 Apr 2026 10:14:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8t0-0000qD-N7; Fri, 10 Apr 2026 10:14:50 +0000 Received: by outflank-mailman (input) for mailman id 1278668; Fri, 10 Apr 2026 10:14:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB8t0-0000q7-1H for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 10:14:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB8sz-004D7m-A3 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 12:14:49 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8cd8c-bab6-0a2a0a5309dd-0a2a4501cfc8-46 for ; Fri, 10 Apr 2026 12:14:49 +0200 Received: from [209.85.208.48] (helo=mail-ed1-f48.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8cd99-6fc9-0a2a45010019-d155d030b5a6-3 for ; Fri, 10 Apr 2026 12:14:49 +0200 Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-66e8cc747d8so2653607a12.1 for ; Fri, 10 Apr 2026 03:14:49 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------RrhnLUpSH1N9zvQM1H9fBG0T" X-purgate-ID: tlsNG-d62444/1775816089-14EE3185-22168AB3/0/0 X-purgate-type: clean X-purgate-size: 6770 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------RrhnLUpSH1N9zvQM1H9fBG0T Content-Type: multipart/mixed; boundary="------------QKx1hifjZ1Zc54zu9gycsAwb"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" Cc: Dario Faggioli , George Dunlap , Meng Xu Message-ID: <775bc23d-7cd4-43b4-9e5f-0c70204b4262@suse.com> Subject: Re: [PATCH v2] xen/sched: rtds: re-arm repl_timer after timer re-initialization References: <548ea03cc3c3287b1f5dcd101b3c2990ebc08089.1775208527.git.oleksii_moisieiev@epam.com> In-Reply-To: <548ea03cc3c3287b1f5dcd101b3c2990ebc08089.1775208527.git.oleksii_moisieiev@epam.com> --------------QKx1hifjZ1Zc54zu9gycsAwb Content-Type: multipart/mixed; boundary="------------Vdy0cAsM9xS79eMChS80bSy7" --------------Vdy0cAsM9xS79eMChS80bSy7 Content-Type: text/plain; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-670703f5b31sm467810a12.11.2026.04.10.03.24.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Apr 2026 03:24:55 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775816696; x=1776421496; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=GWuwwGgF+Mk5wStqMS+vVyWcPiF3DIKXvNy746Pcy2Y=; b=mIZcXG4TpFeHh4p7muHbP7eUugzqKNgheDDa76C86vO1M7IRPmkE8q9UYd/MeWFz6W egE/xqTFhBRBQ49gO3gD9AMSLDXxE8SzOPqOCBprSWAKsjTkYryp1LuGA8dnHnGWCmBd IOgYTqNYNJ4vUiVDAXkxE8liM75V7qkzHrDNknBl4pZ6IRkI5gZdZYBWpVg0l1SZ8b5s PAy4IyTdE7JoqedTuO5IErz9QRjoSC9u8GL0Dcp7orGwuwUXKaDq+bA3qBER9NxGZLST 0jVd9ghHG9MHfIAajetuyxFkKN6rp+S/Rxd9MrNo0rHKKZ52axBeEcbLkNIKrxP1AUe2 PArA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775816696; x=1776421496; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GWuwwGgF+Mk5wStqMS+vVyWcPiF3DIKXvNy746Pcy2Y=; b=X/dsIF90E3YzrZpz6mIas+FgKEUKdxIRKLgCy7DYkM4ZkLcNBd9EfY0vfzBe2XNbJh MAPx3esfyf1KM9Q1ZTEbKAh89l+8VZ95/FRSWHodXShGlpfziU+LBu///RVFzj8mI/g2 dvNIAWezE48tAoLOxAYbz8NT3vLmjLdgIEhc+199ZyJd3NbPaV1A9IY7vnaL3cgUZsC/ S1BZCkdOfDWfetLrbEijGZe9kU5YTehTu1Z+2tgTUjodq4v1a6ekM3puJt0iqY19c+SV bkF/ad1pFwly7SDZsqs30bszDaa4VrTj6FoXktfeDkf2kThM+E6tWa/nQZwf1mbT2+ML xbyA== X-Forwarded-Encrypted: i=1; AJvYcCWK2Hq31IvZKHmZZhbeolPRafawYdQJGTbdjo0XYE+iNe/H0hVLDfzPTeQuXudgE63M8tB4TFTdqng=@lists.xenproject.org X-Gm-Message-State: AOJu0Yx3Wt2/pwZfK5fnrWp2S0evrjX2VzO2IcNKEUc8DRsQw9DNtgnr 8ezp6GHkR5maH6veRfhgaYCf41E4CIW7et1ehtk105bjaXIv1RfhBE5o X-Gm-Gg: AeBDievr0Hoe+7YDsKgiBA0Dp5qnxVZUy3PEAiAEH/LyEPAuKsWF7se1JEtZd0i8uSM GMgtNmI4z3rTzhAzT91U4r2T2yjJ8tm3kKOIZmXi+js+LBN2EfoK//xpHTSvqjNuzE/zp8qxlV8 5iJ/Pk5KSDInKo8NwPCs5ABwaFitF7gx8sUOMytlIXaHYB/Rw5++fH+GZO19SiZs/mTJsHKqV52 XRKu+3NdFx5evAw7AbLYg0ftXMvSJjEuLs+4fvzwKbhnnylARz/BCGrPz9IpVIz2WPDlHruwYIt EA94dc8Ui98uli5XiGZiir/zx24USC7oESUoPttbmoou7IrojX7RctD+3nA6ulFpMNhcWO8riEv iTbWF9h6524t6SAYJqE7V8YSff9zEUd8pcF3g1qX7ZHXSBoRRFxF3kk1rGOoArJklZLKQzSt+2r OgNpER4zlXpAgfoKcWzjVt0urz/m/o2rBWIAVj6dcb32bTq2ZFcEiE8CxFl7f2EMZ/xa+29h4JE Nc= X-Received: by 2002:a05:6402:505c:b0:66b:b6e2:66e1 with SMTP id 4fb4d7f45d1cf-6707a47e6a3mr895460a12.18.1775816695928; Fri, 10 Apr 2026 03:24:55 -0700 (PDT) Message-ID: Date: Fri, 10 Apr 2026 12:24:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 05/27] xen/riscv: introduce guest riscv,isa string To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <007c0a0243ac7ff1d1ab3faa4ebcdd6fcd14e485.1773157782.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1775816696-8B14D41E-6D76B9D9/10/73395122804 X-purgate-type: spam X-purgate-size: 6460 On 4/1/26 3:49 PM, Jan Beulich wrote: > On 10.03.2026 18:08, Oleksii Kurochko wrote: >> Introduce generation of the riscv,isa string passed to the guest via the >> Device Tree riscv,isa property. > > Title as well as this suggest this is all about guest properties. Then ... > >> The following changes are introduced: >> >> - According to the RISC-V privileged specification, M-mode software controls >> the XLEN value used by S-mode and U-mode. For RV64 harts, the SXL and UXL >> fields of the mstatus register are WARL fields that define the XLEN for >> S-mode and U-mode. >> >> The XLEN value is provided by M-mode software (OpenSBI in the case of Xen) >> via the riscv,isa DT property. Introduce and initialize an xlen variable >> when parsing the host riscv,isa string in riscv_isa_parse_string(). > > ... suddenly talk is of host aspects? (See below as to what "xlen" really > is meant to hold.) I just used it to show that xlen could be different and based on what prev. mode put into one of it register to encode xlen. And the same is applied for guest domains. I will rephrase it in more proper way. > >> --- a/xen/arch/riscv/cpufeature.c >> +++ b/xen/arch/riscv/cpufeature.c >> @@ -38,6 +38,8 @@ struct riscv_isa_ext_data { >> /* Host ISA bitmap */ >> static __ro_after_init DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX); >> >> +static __ro_after_init unsigned int xlen; > > Nit: Attribute between type and identifier please, whenever possible (it > isn't neatly possible in riscv_isa above, due to DECLARE_BITMAP()). > >> @@ -160,6 +162,19 @@ static const struct riscv_isa_ext_data __initconst required_extensions[] = { >> RISCV_ISA_EXT_DATA(svpbmt), >> }; >> >> +static const unsigned int __initconst guest_unsupp_exts[] = { >> + RISCV_ISA_EXT_f, >> + RISCV_ISA_EXT_d, >> + RISCV_ISA_EXT_h, >> + RISCV_ISA_EXT_q, >> + RISCV_ISA_EXT_v, >> +}; > > This could do with a comment clarifying what needs (and what doesn't need) > putting here. My expectation would have been that everything in > riscv_isa_ext[] which shouldn't be exposed to guests should appear here. > Yet then there is V (which riscv_isa_ext[] doesn't have), while e.g. Svade > and Svpbmt (which iirc won't be available to guests right away) aren't > there. > >> +static __ro_after_init DECLARE_BITMAP(guest_unsupp_bmp, RISCV_ISA_EXT_MAX); > > Is the _bmp suffix really needed? riscv_isa, for example, doesn't have it. It makes sense to drop. > >> +#define MAX_GUEST_ISA_STR_LEN 256 >> +char guest_isa_str[MAX_GUEST_ISA_STR_LEN]; > > __ro_after_init? > > Yet then - can this really be a global? Isn't the set of extensions > available to a guest a per-guest property, i.e. a global could at best > represent an upper bound on features? At least, for now I think it is okay just to use global guest riscv,isa for all the domains. From my point of view if Xen doesn't support some extension to be used by guest so then should be responsible to generate proper riscv,isa. It probably make sense to have riscv,isa per guest but then we still will want to parse this passed riscv,isa and check what Xen supports and what not, what looks like a double work a little bit. Probably it is the best one option and if riscv,isa isn't provided then just use that one generated by Xen. > >> @@ -193,6 +208,15 @@ static void __init match_isa_ext(const char *name, const char *name_end, >> !memcmp(name, ext->name, name_end - name) ) >> { >> __set_bit(ext->id, bitmap); >> + >> + if ( riscv_isa_extension_available(guest_unsupp_bmp, ext->id) ) >> + break; >> + >> + if ( ext->id >= RISCV_ISA_EXT_BASE ) >> + safe_strcat(guest_isa_str, "_"); >> + >> + safe_strcat(guest_isa_str, ext->name); > > Shouldn't you check the (kind-of-)return value? (Yet better would be a build- > time check, but I can't think of a way to achieve that.) Yes, it would be nice. But it doesn't clear what should be reaction - just panic() with the message that we don't have enough space to cover all extenstion in riscv,isa or just continue with what was put to guest_isa_str. I think the second option could be fine. > >> @@ -207,13 +231,17 @@ static int __init riscv_isa_parse_string(const char *isa, >> #if defined(CONFIG_RISCV_32) >> if ( isa[2] != '3' && isa[3] != '2' ) >> return -EINVAL; >> + xlen = 32; >> #elif defined(CONFIG_RISCV_64) >> if ( isa[2] != '6' && isa[3] != '4' ) >> return -EINVAL; >> + xlen = 64; >> #else >> # error "unsupported RISC-V bitness" >> #endif > > This can be had with an initializer of "xlen". Then the (kind-of-)variable > could be const unsigned int. Seeing the use below, is the variable > correctly named, though? I.e. shouldn't it be guest_xlen or some such? guest_xlen would be better. > > Independently I expect you will want to support 32-bit guests on 64-bit Xen > at some point, in which case encoding this value into a global string won't > work very well. Yes, then it will be needed to move it to domain-specific structure. I don't know if it makes sense to do now. (depends on what we will decide to do with per-domain riscv,isa or it is fine to go with global one) Btw, it isn't always be possible to have 32-bit guest on 64-bit Xen as when HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa. In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN. > >> + snprintf(guest_isa_str, sizeof(guest_isa_str), "rv%d", xlen); > > %u please with unsigned int. > > This being the only use of the variable (afaics), why is it not function- > scope? With the current implmentation, yes, it should be in function-scope. > >> @@ -487,6 +515,11 @@ void __init riscv_fill_hwcap(void) >> bool all_extns_available = true; >> struct trap_info trap; >> >> + for ( i = 0; i < ARRAY_SIZE(guest_unsupp_exts); i++ ) >> + { >> + __set_bit(guest_unsupp_exts[i], guest_unsupp_bmp); >> + } > > Nit: No need for braces here. And anyway - can't this be had with an > initializer for guest_unsupp_bmp? It could be. I will use an initializer. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:43:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:43:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278698.1563462 (Exim 4.92) (envelope-from ) id 1wB9KC-0005oq-An; Fri, 10 Apr 2026 10:42:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278698.1563462; Fri, 10 Apr 2026 10:42:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB9KC-0005oj-85; Fri, 10 Apr 2026 10:42:56 +0000 Received: by outflank-mailman (input) for mailman id 1278698; Fri, 10 Apr 2026 10:42:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB9KB-0005ob-1g for xen-devel@lists.xenproject.org; Fri, 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xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Teddy Astie Subject: Re: [PATCH] x86/time: do not kill calibration timer on suspend Message-ID: References: <20260410085504.32925-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="tUaYOwkehvKn/XPu" Content-Disposition: inline In-Reply-To: <20260410085504.32925-1-roger.pau@citrix.com> X-purgate-ID: tlsNG-c201ff/1775817846-2372A96F-63941FFC/0/0 X-purgate-type: clean X-purgate-size: 2024 --tUaYOwkehvKn/XPu Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 10 Apr 2026 12:44:02 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Teddy Astie Subject: Re: [PATCH] x86/time: do not kill calibration timer on suspend On Fri, Apr 10, 2026 at 10:55:04AM +0200, Roger Pau Monne wrote: > A killed timer will ignore further set_timer() calls, and hence won't be > re-armed unless it's initialized again. Use stop_timer() instead of > kill_timer() in time_suspend(), so that the set_timer() call in > time_resume() successfully re-arms the timer. Otherwise time calibration > is no longer scheduled (and executed) after resuming from S3 suspend. >=20 > Fixes: 6d90db1a2ca1 ("x86: rendezvous-based local time calibration") > Reported-by: Marek Marczykowski-G=C3=B3recki > Signed-off-by: Roger Pau Monn=C3=A9 I confirm this fixes the issue, thanks! Tested-by: Marek Marczykowski-G=C3=B3recki --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --tUaYOwkehvKn/XPu Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnY1HIACgkQ24/THMrX 1yz9bQf/Y1c6lYD2l1ximaVqJVniKZF0OUUWD2B3gthXifMbXZuL79cUcDetoKGB qu3nSd+PxB7jPKtzRNoE0k3ftwUCzNbrMMKfFk5PxBZ10gMVWmnb9KHeaXLDc3CS l9A0ZiIEob1XtKpYngx08pI1GmT3N5AqQebmkh2DIWqz+W3hEQKjmu3s00bO7cFh Mj35/+i2oBp7Q6nlWM0p4nSlyThSQsTSClG1r2zEEseqtu9p4ySHAxsNbOTmVDHP iCyFbC+j2kw35zx5hSHa9LtXBVA/Xn7Q32e1RbDUGS83Hdv93VQ8O24voAqPeAsc Kji9kA8Tw/JNeP89eRPaytLsnMdxDQ== =dq1v -----END PGP SIGNATURE----- --tUaYOwkehvKn/XPu-- From xen-devel-bounces@lists.xenproject.org Fri Apr 10 10:45:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 10:45:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278717.1563479 (Exim 4.92) (envelope-from ) id 1wB9N2-0006qO-TW; Fri, 10 Apr 2026 10:45:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278717.1563479; Fri, 10 Apr 2026 10:45:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB9N2-0006qH-Ql; Fri, 10 Apr 2026 10:45:52 +0000 Received: by outflank-mailman (input) for mailman id 1278717; Fri, 10 Apr 2026 10:45:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB9N1-0006px-52 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 10:45:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB9Mx-00FJdM-TE for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 12:45:47 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8d4c2-bab6-0a2a0a5309dd-0a2a4502cf70-22 for ; Fri, 10 Apr 2026 12:45:47 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8d4db-42fa-0a2a45020019-d155dd33ec8f-3 for ; Fri, 10 Apr 2026 12:45:47 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43d5ec211abso984317f8f.0 for ; Fri, 10 Apr 2026 03:45:47 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1775817947-AFF29CD1-4DEFFA21/0/0 X-purgate-type: clean X-purgate-size: 1285 On 10.04.2026 09:08, Mykola Kvach wrote: > On Fri, Apr 10, 2026 at 9:40 AM Jan Beulich wrote: >> On 10.04.2026 08:09, Mykola Kvach wrote: >>> --- a/xen/arch/arm/gic-v3-its.c >>> +++ b/xen/arch/arm/gic-v3-its.c >>> @@ -496,7 +496,8 @@ retry: >>> } >>> attr = regc & BASER_ATTR_MASK; >>> } >>> - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) >>> + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> >>> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <= GIC_BASER_CACHE_nC ) >> >> Are you aware of MASK_EXTR()? This is one of the cases that we have it for. >> Really all *_SHIFT constants should be purged, as they can be calculated >> from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the >> code readable). > > I wasn't aware of this macro, thanks. I will take a look. > >> Further, doesn't gicv3_lpi_set_proptable() have the same issue with >> GICR_PROPBASER_INNER_CACHEABILITY_MASK? > > Fortunately, GIC_BASER_NonShareable is equal to zero, so the condition > there is not affected. I fear I don't follow. In if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) where does GIC_BASER_NonShareable come into play? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1775818221-EED4F2A1-620E2A1B/0/0 X-purgate-type: clean X-purgate-size: 1264 On 10.04.2026 12:24, Oleksii Kurochko wrote: > On 4/1/26 3:49 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> +#define MAX_GUEST_ISA_STR_LEN 256 >>> +char guest_isa_str[MAX_GUEST_ISA_STR_LEN]; >> >> __ro_after_init? >> >> Yet then - can this really be a global? Isn't the set of extensions >> available to a guest a per-guest property, i.e. a global could at best >> represent an upper bound on features? > > At least, for now I think it is okay just to use global guest riscv,isa > for all the domains. From my point of view if Xen doesn't support some > extension to be used by guest so then should be responsible to generate > proper riscv,isa. > > It probably make sense to have riscv,isa per guest but then we still > will want to parse this passed riscv,isa and check what Xen supports and > what not, what looks like a double work a little bit. Probably it is the > best one option and if riscv,isa isn't provided then just use that one > generated by Xen. My take is: Have data arrangement be as it wants to be in the end (i.e. here: record what ought to be per guest as per-guest data). All guests using the same value for now is a fair restriction until things have progressed more. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260410082955.42038-1-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775818607-3312596F-917F87C8/0/0 X-purgate-type: clean X-purgate-size: 775 On 10.04.2026 10:29, Michal Orzel wrote: > The check uses (*num_colors + (end - start + 1)) >= max_num_colors, which > rejects a configuration where exactly max_num_colors colors are specified. > For example, if max_num_colors is 4 and *num_colors is 0, a range "0-3" > gives (end - start + 1) = 4, and (0 + 4) >= 4 is true, incorrectly > returning -EINVAL. > > Fix this by switching the overflow condition to the state before commit > cba8a584de17 that regressed the behavior (i.e. don't add 1). > > Fixes: cba8a584de17 ("llc-coloring: improve checking while parsing") > Signed-off-by: Michal Orzel > Reviewed-by: Luca Fancellu I'm sorry for the breakage: Reviewed-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 10 11:01:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 11:01:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278758.1563507 (Exim 4.92) (envelope-from ) id 1wB9bn-0002Vq-K6; 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AJvYcCXjeceSSbyNdtDj1hDIesCFh0PNDJZUNbDwo0qC43c2jnYo/DNTt08Lg4hy40Mts1IVwY4n8YkGVnA=@lists.xenproject.org X-Gm-Message-State: AOJu0Yyg3d1/dA1x58rRrM8t8glVI5jUBn2Cu/aYXM8nsOIyBIaY8PUX odBj4ewUXSBcLPmOj/rABLrxWm724crpBcEX42TKihxgEBLwfH4yzKLgqo9aNkvjyTM1Axl0KOJ QNAcoON8Wz9jc2mkpjpduLMpj1CbUlL8= X-Gm-Gg: AeBDievxXEaIy1JDwuuaDapm6cr5u58ZRvWwl7mvupBjbvQab5IYQdeLK7q77LKROcf r9UOGHT+TWKpFlVLJTfKpDmrBzG7Tyv0OrHDDy1iU6z3zKqT/W1txEIkqZy4OraWHyvPswIEKPA +Itnsboxxoh6kLLHOkdigCBD3DRbTsBY3KHPt4f3YPDVQQzIoIPU9hGcijxp9lnkpbspXGh3DHv Vt6Ww4Pe9AgxWy3JCXjqMugIZQ4Zy03a4KCLraN/kshJpUbGUl8UzLQyevD8Tbjk0Rezkm37Ikn v/tt7g== X-Received: by 2002:a05:651c:503:b0:38c:374f:420d with SMTP id 38308e7fff4ca-38e4bbf4306mr7718891fa.2.1775818864548; Fri, 10 Apr 2026 04:01:04 -0700 (PDT) MIME-Version: 1.0 References: <0c68ca5e-51d3-42ee-aa27-301ffafefc5f@suse.com> <1546f5c9-e270-465d-aa0b-4c4c0ec87c8a@suse.com> In-Reply-To: <1546f5c9-e270-465d-aa0b-4c4c0ec87c8a@suse.com> From: Mykola Kvach Date: Fri, 10 Apr 2026 14:00:52 +0300 X-Gm-Features: AQROBzAKTKxMpShjUBMlXhoA5Zo2soLNnoZXW038yMahzFVpBODqR0SvXpxsQwQ Message-ID: Subject: Re: [PATCH] arm/its: Decode BASER cacheability field before comparing To: Jan Beulich Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Mykyta Poturai , xen-devel@lists.xenproject.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1775818866-76B4C497-A20A4A98/0/0 X-purgate-type: clean X-purgate-size: 1769 On Fri, Apr 10, 2026 at 1:45=E2=80=AFPM Jan Beulich wro= te: > > On 10.04.2026 09:08, Mykola Kvach wrote: > > On Fri, Apr 10, 2026 at 9:40=E2=80=AFAM Jan Beulich = wrote: > >> On 10.04.2026 08:09, Mykola Kvach wrote: > >>> --- a/xen/arch/arm/gic-v3-its.c > >>> +++ b/xen/arch/arm/gic-v3-its.c > >>> @@ -496,7 +496,8 @@ retry: > >>> } > >>> attr =3D regc & BASER_ATTR_MASK; > >>> } > >>> - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_= CACHE_nC ) > >>> + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> > >>> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <=3D GIC_BASER_CACHE_= nC ) > >> > >> Are you aware of MASK_EXTR()? This is one of the cases that we have it= for. > >> Really all *_SHIFT constants should be purged, as they can be calculat= ed > >> from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep = the > >> code readable). > > > > I wasn't aware of this macro, thanks. I will take a look. > > > >> Further, doesn't gicv3_lpi_set_proptable() have the same issue with > >> GICR_PROPBASER_INNER_CACHEABILITY_MASK? > > > > Fortunately, GIC_BASER_NonShareable is equal to zero, so the condition > > there is not affected. > > I fear I don't follow. In > > if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_CA= CHE_nC ) > > where does GIC_BASER_NonShareable come into play? Sorry, I missed that part of your comment; clearly, I haven't had enough coffee yet. You are right: gicv3_lpi_set_proptable() has the exact same issue and needs fixing too. Thanks for catching that. It is interesting that we did not hit this during GICv4 testing. Best regards, Mykola > > Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 10 11:19:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 11:19:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278773.1563516 (Exim 4.92) (envelope-from ) id 1wB9tG-0004YV-03; Fri, 10 Apr 2026 11:19:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278773.1563516; Fri, 10 Apr 2026 11:19:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wB9tF-0004YO-TI; Fri, 10 Apr 2026 11:19:09 +0000 Received: by outflank-mailman (input) for mailman id 1278773; Fri, 10 Apr 2026 11:19:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wB9tE-0004YI-7s for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 11:19:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wB9tD-00FQAC-KJ for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 13:19:07 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8dca2-5cb7-0a2a0a5109dd-0a2a4504de42-10 for ; Fri, 10 Apr 2026 13:19:07 +0200 Received: from [209.85.208.42] (helo=mail-ed1-f42.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8dcab-bb33-0a2a45040019-d155d02ac84f-3 for ; Fri, 10 Apr 2026 13:19:07 +0200 Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-66bf6aa4858so3409052a12.2 for ; Fri, 10 Apr 2026 04:19:07 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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And then domain-build.init.o? Yes, it should be part of patch 02. Made a mistake during splitting. > >> --- a/xen/arch/riscv/domain-build.c >> +++ b/xen/arch/riscv/domain-build.c >> @@ -3,8 +3,10 @@ >> #include >> #include >> #include >> +#include >> #include >> >> +#include >> #include >> #include >> >> @@ -44,3 +46,109 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) >> >> return 0; >> } >> + >> +int __init make_cpus_node(const struct domain *d, void *fdt) >> +{ >> + int res; >> + const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); >> + unsigned int cpu; >> + u32 timebase_frequency; > > uint32_t please. > >> + bool frequency_valid; >> + uint32_t *next_phandle = &((struct domain *)d)->arch.next_phandle; > > No casting away of const, please. > >> + dt_dprintk("Create cpus node\n"); >> + >> + if ( !cpus ) >> + { >> + dprintk(XENLOG_ERR, "Missing /cpus node in the device tree?\n"); >> + return -ENOENT; >> + } >> + >> + frequency_valid = dt_property_read_u32(cpus, "timebase-frequency", >> + &timebase_frequency); >> + >> + res = fdt_begin_node(fdt, "cpus"); >> + if ( res ) >> + return res; >> + >> + res = fdt_property_cell(fdt, "#address-cells", 1); >> + if ( res ) >> + return res; >> + >> + res = fdt_property_cell(fdt, "#size-cells", 0); >> + if ( res ) >> + return res; >> + >> + if ( frequency_valid ) >> + res = fdt_property_cell(fdt, "timebase-frequency", timebase_frequency); > > Handing through a property directly makes me wonder how that's going to > fit with migration. I understand migration may not even be a mid-term > goal, but still. Do you mean if I will set timebase-frequency = X for guest cpu node and then this guest will migrate to h/w where timebase-frequency is Y, so we will have unsynced timebase-frequency? Migration between hosts with differing timebase-frequency would require either (a) restricting migration pools to frequency-matched hosts (for example, KVM checks if timebase-frequency isn't different here: https://elixir.bootlin.com/linux/v6.19.11/source/arch/riscv/kvm/vcpu_timer.c#L200), or (b) trap-and-emulate of time CSR reads to scale the virtual timer. I think so as unlike ARM (which has CNTFRQ_EL0 writable by EL2, letting the hypervisor normalize the frequency it presents), RISC-V has no hypervisor-controlled frequency register. The guest reads timebase-frequency from DT exactly once and trusts it forever. There's no in-guest mechanism to update it post-boot. (at least, I don't see now how to do that based on the spec) > >> + for ( cpu = 0; cpu < d->max_vcpus; cpu++ ) >> + { >> + char buf[64]; >> + uint32_t reg = cpu_to_fdt32(cpu); >> + >> + snprintf(buf, sizeof(buf), "cpu@%u", cpu); >> + res = fdt_begin_node(fdt, buf); >> + if ( res ) >> + return res; >> + >> + res = fdt_property(fdt, "reg", ®, sizeof(reg)); >> + if ( res ) >> + return res; >> + >> + res = fdt_property_string(fdt, "status", "okay"); >> + if ( res ) >> + return res; >> + >> + res = fdt_property_string(fdt, "compatible", "riscv"); >> + if ( res ) >> + return res; >> + >> + BUILD_BUG_ON((sizeof("riscv,") + sizeof_field(struct gstage_mode_desc, name) + 1) >= sizeof(buf)); > > Nit: Overlong line. Also, why +1? The name field has to include a nul, or > else ... Agree, +1 looks wrong here. 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Fri, 10 Apr 2026 04:30:11 -0700 (PDT) MIME-Version: 1.0 References: <0c68ca5e-51d3-42ee-aa27-301ffafefc5f@suse.com> In-Reply-To: <0c68ca5e-51d3-42ee-aa27-301ffafefc5f@suse.com> From: Mykola Kvach Date: Fri, 10 Apr 2026 14:30:00 +0300 X-Gm-Features: AQROBzAqb3s0urNnGDGKB9WoQ_CZeDMbi7wFJPMGzOUuCb32gCBjOYHWMGQEUE0 Message-ID: Subject: Re: [PATCH] arm/its: Decode BASER cacheability field before comparing To: Jan Beulich Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Mykyta Poturai , xen-devel@lists.xenproject.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-bad1c0/1775820612-2E155152-0D8F84F7/0/0 X-purgate-type: clean X-purgate-size: 1147 On Fri, Apr 10, 2026 at 9:40=E2=80=AFAM Jan Beulich wro= te: > > On 10.04.2026 08:09, Mykola Kvach wrote: > > --- a/xen/arch/arm/gic-v3-its.c > > +++ b/xen/arch/arm/gic-v3-its.c > > @@ -496,7 +496,8 @@ retry: > > } > > attr =3D regc & BASER_ATTR_MASK; > > } > > - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_CA= CHE_nC ) > > + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> > > + GITS_BASER_INNER_CACHEABILITY_SHIFT) <=3D GIC_BASER_CACHE_nC= ) > > Are you aware of MASK_EXTR()? This is one of the cases that we have it fo= r. > Really all *_SHIFT constants should be purged, as they can be calculated > from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the > code readable). > > Further, doesn't gicv3_lpi_set_proptable() have the same issue with > GICR_PROPBASER_INNER_CACHEABILITY_MASK? Is it acceptable to include Fixes tags for two different commits in a single patch, or would it be better to split it? Both issues are logically identical, just in different functions. Best regards, Mykola > > Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 10 11:33:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 11:33:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278805.1563533 (Exim 4.92) (envelope-from ) id 1wBA7a-0007tD-G4; Fri, 10 Apr 2026 11:33:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278805.1563533; Fri, 10 Apr 2026 11:33:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBA7a-0007t6-DP; Fri, 10 Apr 2026 11:33:58 +0000 Received: by outflank-mailman (input) for mailman id 1278805; Fri, 10 Apr 2026 11:33:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBA7Y-0007sy-SG for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 11:33:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBA7Y-00FSpf-83 for xen-devel@lists.xenproject.org; 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>>> } >>> - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) >>> + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> >>> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <= GIC_BASER_CACHE_nC ) >> Are you aware of MASK_EXTR()? This is one of the cases that we have it for. >> Really all *_SHIFT constants should be purged, as they can be calculated >> from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep the >> code readable). >> >> Further, doesn't gicv3_lpi_set_proptable() have the same issue with >> GICR_PROPBASER_INNER_CACHEABILITY_MASK? > Is it acceptable to include Fixes tags for two different commits in > a single patch, or would it be better to split it? Both issues are > logically identical, just in different functions. Multiple fixes tags is entirely fine, and we have several examples in fight even now. I'd absolutely recommend one patch with two fixes tags in this case. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 10 11:41:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 11:41:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278817.1563542 (Exim 4.92) (envelope-from ) id 1wBAEc-0001Df-6F; Fri, 10 Apr 2026 11:41:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278817.1563542; Fri, 10 Apr 2026 11:41:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAEc-0001DY-3Z; Fri, 10 Apr 2026 11:41:14 +0000 Received: by outflank-mailman (input) for mailman id 1278817; Fri, 10 Apr 2026 11:41:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAEa-0001DQ-Gr for xen-devel@lists.xenproject.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1775821606-FFB44A3D-45729CFF/0/0 X-purgate-type: clean X-purgate-size: 1586 Hi Andrew, Thank you for the review. On Fri, Apr 10, 2026 at 2:33=E2=80=AFPM Andrew Cooper wrote: > > On 10/04/2026 12:30 pm, Mykola Kvach wrote: > > On Fri, Apr 10, 2026 at 9:40=E2=80=AFAM Jan Beulich = wrote: > >> On 10.04.2026 08:09, Mykola Kvach wrote: > >>> --- a/xen/arch/arm/gic-v3-its.c > >>> +++ b/xen/arch/arm/gic-v3-its.c > >>> @@ -496,7 +496,8 @@ retry: > >>> } > >>> attr =3D regc & BASER_ATTR_MASK; > >>> } > >>> - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_= CACHE_nC ) > >>> + if ( ((regc & GITS_BASER_INNER_CACHEABILITY_MASK) >> > >>> + GITS_BASER_INNER_CACHEABILITY_SHIFT) <=3D GIC_BASER_CACHE_= nC ) > >> Are you aware of MASK_EXTR()? This is one of the cases that we have it= for. > >> Really all *_SHIFT constants should be purged, as they can be calculat= ed > >> from their *_MASK counterparts (leveraging MASK_{EXTR,INSR}() to keep = the > >> code readable). > >> > >> Further, doesn't gicv3_lpi_set_proptable() have the same issue with > >> GICR_PROPBASER_INNER_CACHEABILITY_MASK? > > Is it acceptable to include Fixes tags for two different commits in > > a single patch, or would it be better to split it? Both issues are > > logically identical, just in different functions. > > Multiple fixes tags is entirely fine, and we have several examples in > fight even now. > > I'd absolutely recommend one patch with two fixes tags in this case. Understood, thanks. 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If this node may not > be required, why would the function need providing? Shouldn't the call > site be conditional then? Generally, in DT for RISC-V there is a document which describes timer node (riscv,timer.yaml or sifive,clint.yaml), but the driver (drivers/clocksource/timer-riscv.c:244) is declared with TIMER_OF_DECLARE(riscv_timer, "riscv", ...). It matches the CPU node (compatible "riscv"), not the timer node itself. It then does of_find_compatible_node(NULL, NULL, "riscv,timer") only to read the optional riscv,timer-cannot-wake-cpu flag. But I don't see too much sense at the moment to enable timer-cannot-wake-cpu option. Regarding, sifive,clint.yaml basically it has almost the same as riscv,timer node but also additionally provide some MMIO which are acessible only in M-mode (what isn't the case for virtualization as guest isn't ran in M-mode, otherwise emulation of M-mode register will be needed). So potentially some will want to add riscv,timer node to enable timer-cannot-wake-cpu option, so then some changes additionally should be done in this function. Considering that it isn't needed now and timebase-frequency property is always part of cpu node not a timer one, I think we can go with an empty implementation of make_timer_node(). I can add some extra information to commit message. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 12:00:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 12:00:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278858.1563570 (Exim 4.92) (envelope-from ) id 1wBAXT-0005Rx-Bm; Fri, 10 Apr 2026 12:00:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278858.1563570; Fri, 10 Apr 2026 12:00:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAXT-0005Rq-8n; Fri, 10 Apr 2026 12:00:43 +0000 Received: by outflank-mailman (input) for mailman id 1278858; Fri, 10 Apr 2026 12:00:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAXR-0005Rj-Sc for xen-devel@lists.xenproject.org; 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> + > const struct viommu_desc __read_mostly *cur_viommu; >=20 > +/* Common function for adding to host_iommu_list */ > +void add_to_host_iommu_list(paddr_t addr, paddr_t size, > + const struct dt_device_node *node) > +{ > + struct host_iommu *iommu_data; > + > + iommu_data =3D xzalloc(struct host_iommu); > + if ( !iommu_data ) > + panic("vIOMMU: Cannot allocate memory for host IOMMU data\n"); > + > + iommu_data->addr =3D addr; > + iommu_data->size =3D size; > + iommu_data->dt_node =3D node; > + iommu_data->irq =3D platform_get_irq(node, 0); > + if ( iommu_data->irq < 0 ) > + { > + gdprintk(XENLOG_ERR, > + "vIOMMU: Cannot find a valid IOMMU irq\n"); We need to free iommu_data here > + return; > + } > + > + printk("vIOMMU: Found IOMMU @0x%"PRIx64"\n", addr); > + > + list_add_tail(&iommu_data->entry, &host_iommu_list); > +} > + > int domain_viommu_init(struct domain *d, uint16_t viommu_type) > { > if ( viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthr= ough/arm/vsmmu-v3.c > new file mode 100644 > index 0000000000..6b4009e5ef > --- /dev/null > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -0,0 +1,124 @@ > +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > + > +#include > +#include > +#include > +#include > + > +/* Struct to hold the vIOMMU ops and vIOMMU type */ > +extern const struct viommu_desc __read_mostly *cur_viommu; > + > +struct virt_smmu { > + struct domain *d; > + struct list_head viommu_list; > +}; > + > +static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > + register_t r, void *priv) > +{ > + return IO_HANDLED; > +} > + > +static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, > + register_t *r, void *priv) > +{ > + return IO_HANDLED; If this has to be treated for now as RAZ, being a dummy implementation, I would add *r =3D 0; > +} > + > +static const struct mmio_handler_ops vsmmuv3_mmio_handler =3D { > + .read =3D vsmmuv3_mmio_read, > + .write =3D vsmmuv3_mmio_write, > +}; > + > +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t s= ize) > +{ > + struct virt_smmu *smmu; > + > + smmu =3D xzalloc(struct virt_smmu); > + if ( !smmu ) > + return -ENOMEM; > + > + smmu->d =3D d; > + > + register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); > + > + /* Register the vIOMMU to be able to clean it up later. */ > + list_add_tail(&smmu->viommu_list, &d->arch.viommu_list); > + > + return 0; > +} > + > +int domain_vsmmuv3_init(struct domain *d) > +{ > + int ret; > + INIT_LIST_HEAD(&d->arch.viommu_list); > + > + if ( is_hardware_domain(d) ) > + { > + struct host_iommu *hw_iommu; > + > + list_for_each_entry(hw_iommu, &host_iommu_list, entry) > + { > + ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->siz= e); > + if ( ret ) > + return ret; > + } > + } > + else > + { > + ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3= _SIZE); > + if ( ret ) > + return ret; > + } > + > + return 0; > +} > + > +int vsmmuv3_relinquish_resources(struct domain *d) > +{ > + struct virt_smmu *pos, *temp; > + > + /* Cope with unitialized vIOMMU */ Typo s/unitialized/uninitialized/ Cheers, Luca From xen-devel-bounces@lists.xenproject.org Fri Apr 10 12:02:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 12:02:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278872.1563578 (Exim 4.92) (envelope-from ) id 1wBAZT-0005x6-MR; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <147735e4-cd03-4efa-8981-3f29e15d5e6b@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775822565-32B2096F-9662AE8F/0/0 X-purgate-type: clean X-purgate-size: 1962 On 10.04.2026 13:19, Oleksii Kurochko wrote: > On 4/1/26 4:11 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> @@ -44,3 +46,109 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) >>> >>> return 0; >>> } >>> + >>> +int __init make_cpus_node(const struct domain *d, void *fdt) >>> +{ >>> + int res; >>> + const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); >>> + unsigned int cpu; >>> + u32 timebase_frequency; >> >> uint32_t please. >> >>> + bool frequency_valid; >>> + uint32_t *next_phandle = &((struct domain *)d)->arch.next_phandle; >> >> No casting away of const, please. >> >>> + dt_dprintk("Create cpus node\n"); >>> + >>> + if ( !cpus ) >>> + { >>> + dprintk(XENLOG_ERR, "Missing /cpus node in the device tree?\n"); >>> + return -ENOENT; >>> + } >>> + >>> + frequency_valid = dt_property_read_u32(cpus, "timebase-frequency", >>> + &timebase_frequency); >>> + >>> + res = fdt_begin_node(fdt, "cpus"); >>> + if ( res ) >>> + return res; >>> + >>> + res = fdt_property_cell(fdt, "#address-cells", 1); >>> + if ( res ) >>> + return res; >>> + >>> + res = fdt_property_cell(fdt, "#size-cells", 0); >>> + if ( res ) >>> + return res; >>> + >>> + if ( frequency_valid ) >>> + res = fdt_property_cell(fdt, "timebase-frequency", timebase_frequency); >> >> Handing through a property directly makes me wonder how that's going to >> fit with migration. I understand migration may not even be a mid-term >> goal, but still. > > Do you mean if I will set timebase-frequency = X for guest cpu node and > then this guest will migrate to h/w where timebase-frequency is Y, so we > will have unsynced timebase-frequency? Yes (I wouldn't name it "unsync-ed" though; it'll simply be wrong). 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While we haven't encountered this problem in practice yet, it could occur in the future, so I believe it should be addressed proactively. -- Oleksii. On 10/04/2026 13:14, Jürgen Groß wrote: > On 03.04.26 11:29, Oleksii Moisieiev wrote: >> In RTDS, removing the last eligible pCPU can kill repl_timer. >> When a pCPU is later re-added, rt_switch_sched() reinitializes the >> timer object, but pending entries may already exist in replq. > > Did you experience this behavior? > > I'm asking because I don't see how this could happen. A CPU can't be > removed from a cpupool as long as there are domains in that cpupool. > So how would replq contain entries after the last CPU of the cpupool > has been removed? > > But maybe I'm missing something. > > > Juergen From xen-devel-bounces@lists.xenproject.org Fri Apr 10 12:13:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 12:13:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1278906.1563613 (Exim 4.92) (envelope-from ) id 1wBAjb-0008TO-0H; Fri, 10 Apr 2026 12:13:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1278906.1563613; Fri, 10 Apr 2026 12:13:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAja-0008TH-T3; Fri, 10 Apr 2026 12:13:14 +0000 Received: by outflank-mailman (input) for mailman id 1278906; Fri, 10 Apr 2026 12:13:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBAjZ-0008TB-03 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 12:13:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBAjX-00ESEO-SX for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 14:13:11 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d8e947-e002-0a2a0a5209dd-0a2a450ccd32-46 for ; Fri, 10 Apr 2026 14:13:11 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d8e957-f40c-0a2a450c0019-d1558029c83d-3 for ; Fri, 10 Apr 2026 14:13:11 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-48897fd88ebso20696625e9.2 for ; Fri, 10 Apr 2026 05:13:11 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------oOBVY0dnOumlxyRICmN3vfQ0" X-purgate-ID: tlsNG-d25034/1775823191-A4640A3D-4D2CCA4E/0/0 X-purgate-type: clean X-purgate-size: 8048 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------oOBVY0dnOumlxyRICmN3vfQ0 Content-Type: multipart/mixed; boundary="------------qFia0Z1GqqoxE2WDrzl2PEa3"; protected-headers="v1" From: Juergen Gross To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" Cc: Dario Faggioli , George Dunlap , Meng Xu Message-ID: Subject: Re: [PATCH v2] xen/sched: rtds: re-arm repl_timer after timer re-initialization References: <548ea03cc3c3287b1f5dcd101b3c2990ebc08089.1775208527.git.oleksii_moisieiev@epam.com> <775bc23d-7cd4-43b4-9e5f-0c70204b4262@suse.com> <66b7eaff-f7b9-4737-b32b-ca9ff7b661c1@epam.com> In-Reply-To: <66b7eaff-f7b9-4737-b32b-ca9ff7b661c1@epam.com> --------------qFia0Z1GqqoxE2WDrzl2PEa3 Content-Type: multipart/mixed; boundary="------------YauiT380SO0Jc2HEyVml0zTU" --------------YauiT380SO0Jc2HEyVml0zTU Content-Type: text/plain; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------BJDxGHZT2PMW2qJEFLxj80q0" X-purgate-ID: tlsNG-ebf023/1775823419-B373251B-3DD85F4B/0/0 X-purgate-type: clean X-purgate-size: 7428 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------BJDxGHZT2PMW2qJEFLxj80q0 Content-Type: multipart/mixed; boundary="------------AdfA8aaavdJNlhEHAj0xcyaI"; protected-headers="v1" From: Juergen Gross To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" Cc: Dario Faggioli , George Dunlap , Meng Xu Message-ID: Subject: Re: [PATCH v2] xen/sched: rtds: re-arm repl_timer after timer re-initialization References: <548ea03cc3c3287b1f5dcd101b3c2990ebc08089.1775208527.git.oleksii_moisieiev@epam.com> <775bc23d-7cd4-43b4-9e5f-0c70204b4262@suse.com> <66b7eaff-f7b9-4737-b32b-ca9ff7b661c1@epam.com> In-Reply-To: --------------AdfA8aaavdJNlhEHAj0xcyaI Content-Type: multipart/mixed; boundary="------------0kXZVz591Gx1MQ82njcgoWpa" --------------0kXZVz591Gx1MQ82njcgoWpa Content-Type: text/plain; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <029ab247-b8a1-4961-80ab-5b13e5c7aa77@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1775823887-83D4741E-FDE9E919/0/0 X-purgate-type: clean X-purgate-size: 5108 On 10.04.2026 11:26, Teddy Astie wrote: > Le 09/04/2026 à 17:18, Jan Beulich a écrit : >> This requires bumping the number of basic leaves we support. Apart from >> this the logic is modeled as closely as possible after that of leaf 7 >> handling. >> >> Signed-off-by: Jan Beulich >> --- >> The gen-cpuid.py adjustment is merely the minimum needed. It's not >> really clear to me whether someone turning off e.g. AVX512BW might then >> also validly expect AVX10 to be turned off. > > AFAIUI, AVX512BW is a dependency of AVX10, as AVX10 implies that the > former is available. I'm not convinced it is a "dependency". My understanding is that while Intel may say that all their AVX10 hardware is expected to set all the respective AVX512* bits as well, the spec says e.g. "Intel® AVX-512 instruction families included in Intel® AVX10.1 are shown in Table 3.2." Where "instruction families" doesn't say anything about CPUID bits. So from an abstract spec pov someone wanting to use e.g. VMOVDQU8 will want to check for AVX10 || AVX512BW. >> Do we want to synthesize AVX10 in the (max?) policies when all necessary >> AVX512* features are available, thus allowing migration from an AVX10 >> host to a suitable non-AVX10 one? > > I guess we want, there is not really a reason to not allow it. > > Some software may check for AVX10 only, and not check for individual > AVX512 bits. As per above, such software may be slightly flawed. Synthesizing the AVX10 feature bit also means synthesizing the AVX10 leaf then, for example. This may be somewhat of an issue for migration; I didn't thoroughly think this through yet. >> --- a/xen/arch/x86/cpu-policy.c >> +++ b/xen/arch/x86/cpu-policy.c >> @@ -211,7 +211,7 @@ static void recalculate_xstate(struct cp >> if ( p->feat.mpx ) >> xstates |= X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; >> >> - if ( p->feat.avx512f ) >> + if ( p->feat.avx512f || p->feat.avx10 ) > > In principle, the avx10 check is redundant as avx512f must be set if > avx10 is set. I don't think so; see above discussion of AVX512BW. >> --- a/xen/arch/x86/lib/cpu-policy/cpuid.c >> +++ b/xen/arch/x86/lib/cpu-policy/cpuid.c >> @@ -125,6 +125,7 @@ void x86_cpu_policy_fill_native(struct c >> switch ( i ) >> { >> case 0x4: case 0x7: case 0xb: case 0xd: >> + case 0x24: >> /* Multi-invocation leaves. Deferred. */ >> continue; >> } >> @@ -218,6 +219,15 @@ void x86_cpu_policy_fill_native(struct c >> } >> } >> >> + if ( p->basic.max_leaf >= 0x24 ) >> + { >> + cpuid_count_leaf(0x24, 0, &p->avx10.raw[0]); >> + >> + for ( i = 1; i <= MIN(p->avx10.max_subleaf, >> + ARRAY_SIZE(p->avx10.raw) - 1); ++i ) >> + cpuid_count_leaf(0x24, i, &p->avx10.raw[i]); > > Do we need to split the 0 iteration out ? I guess we can just start from > i = 0 instead. Well, strictly formally p->avx10.max_subleaf is uninitialized on the first loop iteration. Hence comparing against it isn't a good idea. (In practice the field taking whatever value will let i == 0 pass, but still.) What's more important though: I want to keep this in sync with what we to elsewhere in the function. >> --- a/xen/include/xen/lib/x86/cpu-policy.h >> +++ b/xen/include/xen/lib/x86/cpu-policy.h >> @@ -59,11 +59,12 @@ unsigned int x86_cpuid_lookup_vendor(uin >> */ >> const char *x86_cpuid_vendor_to_str(unsigned int vendor); >> >> -#define CPUID_GUEST_NR_BASIC (0xdu + 1) >> +#define CPUID_GUEST_NR_BASIC (0x24u + 1) >> #define CPUID_GUEST_NR_CACHE (5u + 1) >> #define CPUID_GUEST_NR_FEAT (2u + 1) >> #define CPUID_GUEST_NR_TOPO (1u + 1) >> #define CPUID_GUEST_NR_XSTATE (62u + 1) >> +#define CPUID_GUEST_NR_AVX10 (0u + 1) > > Intel specification now defines AVX10.2 which has a additional leaf > (even though the whole leaf is currently marked as "reserved"). See "x86/CPUID: enable AVX10.2 sub-leaf" later in the series. The first part aims at supporting just AVX10.1. >> --- a/xen/tools/gen-cpuid.py >> +++ b/xen/tools/gen-cpuid.py >> @@ -294,7 +294,7 @@ def crunch_numbers(state): >> # enabled. Certain later extensions, acting on 256-bit vectors of >> # integers, better depend on AVX2 than AVX. >> AVX2: [AVX512F, VAES, VPCLMULQDQ, AVX_VNNI, AVX_IFMA, AVX_VNNI_INT8, >> - AVX_VNNI_INT16, SHA512, SM4], >> + AVX_VNNI_INT16, SHA512, SM4, AVX10], >> > > I think we can instead make AVX10 a dependency on AVX512. Especially since > > > Any processor that enumerates support for Intel AVX10 will also > enumerate support for Intel AVX, Intel AVX2, and Intel AVX-512 (see > Table 16-2). > > with AVX-512 depending on AVX2. That's the very statement I refer to at the top. Intel may say this for themselves, but the spec - according to my reading - doesn't mandate this. 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Move that if() into the body of the earlier one. > >> > >> Signed-off-by: Jan Beulich > >> > >> --- a/xen/drivers/passthrough/vtd/intremap.c > >> +++ b/xen/drivers/passthrough/vtd/intremap.c > >> @@ -513,13 +513,13 @@ static int msi_msg_to_remap_entry( > >> > >> if ( rc ) > >> return rc; > >> + > >> + if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) > >> + nr = msi_desc->msi.nvec; > >> } > >> else > >> set_hpet_source_id(msi_desc->hpet_id, &new_ire); > >> > >> - if ( msi_desc->msi_attrib.type == PCI_CAP_ID_MSI ) > >> - nr = msi_desc->msi.nvec; > >> - > > > > I'm not fully opposed to this, but maybe it would be good to add a > > small comment to note that HPET never use multi-vector MSI? > > That aspect doesn't change - HPET code simply doesn't (and never should) > set .type to PCI_CAP_ID_MSI. That field should reflect reality (and HPET, > iirc, simply leaves it at 0). Hm, I see, HPET is a very special case which have been "adjusted" to fit the MSI generation logic. Acked-by: Roger Pau Monné Thanks, Roger. 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pr=C Message-ID: <2ffad2ca-e60d-4cc0-866c-4881544fcc96@amd.com> Date: Fri, 10 Apr 2026 14:58:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [BUG] Potential double-free in Xen dt-overlay attach/remove error path To: Gyujeong Jin , References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CB:EE_|CY1PR12MB9559:EE_ X-MS-Office365-Filtering-Correlation-Id: 539da364-68c7-44cb-26d0-08de9700d80e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: gSS8A32tt3Z4wmcFGYynsOA6noy6QZJclIxRXz4ydSMPnzZaLbAnKE0dtS8YvdF/NZKAzgKAi0ZKeB1oLO+Kgx4pAz/TF7so+U/wnIGrjss6L0JFgVXq6q7P2KlopwFznjBLY2y1ch9m3EMfPwLzcNpPAAF8uTmn0DfzQ8zOxVBxklaCKA6cA3X8mHoR6z4ufkln9aQhiww1A/cbaUCcP0DwbVU4DuwX4ng4lSYShntd1GA4ly6nbtZ6trY7fpaXiF06p6ftZsfXOE2Fts45yAkxJoJKH8mQMB3NoPdM6f0ByFY8LeFP1HKEvVEXnev/c4xKkvZ1dXv4G9gLb9g6h+Kj2ZfyyzJm8/ejKBU68TMhm9aqukaxfkEGvDUQcC15ibMXT6T+XaB49+cCL0OVKZCGO2QvT2Ff6OOcUva9/ksQWlrlUyCEOjKS2ufntS/ZJSnTYGukIaSBTMK/4rLd5VT4/At6TPxXmWeN6QVg7Nro7dAlgNK8/ReGM65tqcZjtb8J28RLLc9mi6/GADU05IRvyj5p82ITRpX6NvsKsbtNhKjoATfX5bMoIIItAAWOGQI0aDLcNHa3Q0k0nu2+TH+waXBwn3fzt5a064BMc+XmXERvy81hgNH2Wj/0BfTBe2MJIys+o2C2S6mTH5NwqYxSeoZIZxYLnUCPOiNxYljmsfv6Jn2sl0LxfT2KQ4SUxxFqa3f9WaWspFEaRo5/SiEnQQmau/DanVS82txwvkPx62viS0V1NRc9WMXhd7q+AKu0bE9kJ6tFF3UQ0tAoXw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LczEvHB06v6vnxUuWzQ7sYwj2hNXvVnh9Og/4nBHEZYaGeKm4RgR1LDtQrmhUDsCL2np3HTRX9SZqPKDfRYgFwT2NMCVYkt8549QHv0OMPiLN0EBWKc5SlaIslr2HhnTlq1HWMrOhEA4yerliXLzVeQupEOMLG8nz8FPYgbe3SJEdo6ODkf+oYjv/ZE0yhi7vG0hkcHY7B3ntZmcb/fvxjZXunlpiZ7NeHcp8Qqu35pl2riBQKVx3eTwlxONpzc3fyHETIeJO9eqN5q9bknREdykgo6It+IdHqUrZQPtUJKl2q7hqM6DD50+RHJ2Lu3we2wMYPt1Cn2INU0Q2zmhophRDA/piah9CQ9AMlcgm1jLXk/bQD+PwKSnmbqrlfExHLzHFf/PFgdtF0j+MrACxkde7Xj0xvSNSyVSFZDWFimXKkb0XL2huW0O1KnpRIFD X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 12:58:21.2957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 539da364-68c7-44cb-26d0-08de9700d80e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9559 X-purgate-ID: tlsNG-4011c0/1775825906-BF5460B1-DF38D3FA/0/0 X-purgate-type: clean X-purgate-size: 3893 Hello, Thanks for the report. I will try to book some time next week to investigate the issues. Our DTBO feature at AMD diverged a bit from the upstream one, so I already planned to do some work here but as always there are tasks of a higher priority. ~Michal On 09/04/2026 23:28, Gyujeong Jin wrote: > > You don't often get email from wlsrbwjd7232@gmail.com. Learn why this is > important > > > Hello Team, I was advised to report this issue in this way because dt-overlay is > currently experimental and not security supported. > > I would like to report a potential memory safety issue in Xen related to the > Device Tree overlay handling logic. > > -------------------------------------------------------------------------------- > > > Problem Description > > A double-free / use-after-free condition may occur in the dt-overlay handling > path when an overlay attachment fails and the same overlay is later removed. > > The issue arises because rangeset objects are freed on the failure path of > handle_attach_overlay_nodes(), but the corresponding pointers are not cleared. > Subsequently, handle_remove_overlay_nodes() may operate on these stale pointers, > leading to a second free. > > > Affected Component > > * Xen ARM > * Device Tree overlay subsystem > * File: xen/common/device-tree/dt-overlay.c > > Relevant functions: > > * handle_attach_overlay_nodes() > * handle_remove_overlay_nodes() > > > Impact > > This issue may lead to: > > * Double-free of rangeset structures > * Use-after-free when accessing stale pointers > * Potential hypervisor crash (DoS) > * Possible memory corruption depending on allocator behavior > > Given that this occurs in the hypervisor context, the impact could extend beyond > a simple crash under certain conditions. > > > Root Cause > > The issue originates from inconsistent memory management between the attach > failure path and the remove path. > > In handle_attach_overlay_nodes(), the failure path frees rangeset objects: > > |static long handle_attach_overlay_nodes(...) { ... if ( entry ) > { rangeset_destroy(entry->irq_ranges); rangeset_destroy(entry->iomem_ranges); } > return rc; } | > > However, the corresponding pointers (entry->irq_ranges and entry->iomem_ranges) > are not set to NULL afterward, leaving dangling pointers in the entry structure. > > Later, in handle_remove_overlay_nodes(), the same fields are used again: > > |static long handle_remove_overlay_nodes(const void *overlay_fdt, uint32_t > overlay_fdt_size) { ... rc = remove_nodes(entry); ... rangeset_destroy(entry- >>irq_ranges); rangeset_destroy(entry->iomem_ranges); ... } static int > remove_nodes(const struct overlay_track *tracker) { /* Remove IRQ access. */ if > ( tracker->irq_ranges ) { rc = rangeset_consume_ranges(tracker->irq_ranges, > irq_remove_cb, d); if ( rc ) return rc; } /* Remove mmio access. */ if > ( tracker->iomem_ranges ) { rc = rangeset_consume_ranges(tracker->iomem_ranges, > iomem_remove_cb, d); if ( rc ) return rc; } return rc; } | > > Since the pointers were not invalidated after being freed, this leads to: > > * reuse of freed memory in rangeset_consume_ranges() > * double-free in rangeset_destroy() > > This creates a double-free / use-after-free condition. > > > Environment > > * Xen: 4.22-dev-517-g500ee5fe0f > * Platform: Linux (WSL2 environment) > > > Suggested Fix > > After calling rangeset_destroy(), the corresponding pointers should be set to > NULL to prevent reuse: > > |entry->irq_ranges = NULL; entry->iomem_ranges = NULL; | > > Alternatively, the remove path should defensively check pointer validity. > > Best regards, Gyujeong Jin (Giunash) > From xen-devel-bounces@lists.xenproject.org Fri Apr 10 13:33:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 13:33:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279096.1563690 (Exim 4.92) (envelope-from ) id 1wBByn-0006Wa-4V; Fri, 10 Apr 2026 13:33:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279096.1563690; Fri, 10 Apr 2026 13:33:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBByn-0006WT-1O; Fri, 10 Apr 2026 13:33:01 +0000 Received: by outflank-mailman (input) for mailman id 1279096; Fri, 10 Apr 2026 13:32:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBByl-0006WN-Bt for xen-devel@lists.xenproject.org; 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I'm using it to provide a node for emulated UART, something like Arm does for VPL011 by calling of make_vpl011_uart_node(). > >> --- >> xen/arch/riscv/Makefile | 1 + >> xen/arch/riscv/dom0less-build.c | 11 +++++++++++ >> 2 files changed, 12 insertions(+) >> create mode 100644 xen/arch/riscv/dom0less-build.c > > Further, on what basis is this function put in this new file, when the > earlier ones live in domain-build.c? Because it is called only for dom0less path, but previous one called from both dom0 and dom0less path. > >> --- a/xen/arch/riscv/Makefile >> +++ b/xen/arch/riscv/Makefile >> @@ -1,5 +1,6 @@ >> obj-y += aplic.o >> obj-y += cpufeature.o >> +obj-y += dom0less-build.o > > obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o> > just like Arm has it? It makes sense. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 14:00:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 14:00:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279129.1563699 (Exim 4.92) (envelope-from ) id 1wBCPK-0002I9-BV; Fri, 10 Apr 2026 14:00:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279129.1563699; Fri, 10 Apr 2026 14:00:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBCPK-0002I2-8d; Fri, 10 Apr 2026 14:00:26 +0000 Received: by outflank-mailman (input) for mailman id 1279129; Fri, 10 Apr 2026 14:00:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBCPI-0002Hw-T6 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 14:00:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBCPI-0095An-8y for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 16:00:24 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d90272-bab6-0a2a0a5309dd-0a2a45028cb4-26 for ; Fri, 10 Apr 2026 16:00:24 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d90278-42fa-0a2a45020019-d1558034e1b6-3 for ; Fri, 10 Apr 2026 16:00:24 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso23410335e9.3 for ; Fri, 10 Apr 2026 07:00:24 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Can't what's intc_make_domu_dt_node() right > now become make_intc_domU_node()? With current implementation no as intc_hw_ops used inside intc_make_domu_dt_node() is declared as static. But I can introduce: enum intc_version intc_hw_version(void) { return intc_hw_ops->info->hw_version; } and the in make_intc_domU_node() just use switch/case to call interrupt controller specific functions. Would it be better? It will also help to ... > >> @@ -41,6 +41,10 @@ struct intc_hw_operations { >> >> /* handle external interrupt */ >> void (*handle_interrupt)(struct cpu_user_regs *regs); >> + >> + /* Create interrupt controller node for domain */ >> + int (*make_dom_dt_node)(const struct kernel_info *kinfo, >> + const struct dt_device_node *intc); > > An __init-only hook is somewhat risky, just to mention it. In IOMMU code > besides struct iommu_ops we have struct iommu_init_ops, just to give an > example of where the same could have been the case. .. not introduce hooks in this structure which won't exist after init. > >> --- a/xen/arch/riscv/intc.c >> +++ b/xen/arch/riscv/intc.c >> @@ -67,3 +67,11 @@ void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) >> intc_set_irq_type(desc, desc->arch.type); >> intc_set_irq_priority(desc, priority); >> } >> + >> +int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) >> +{ >> + if ( intc_hw_ops && intc_hw_ops->make_dom_dt_node ) >> + return intc_hw_ops->make_dom_dt_node(kinfo, intc_hw_ops->info->node); >> + >> + return -ENOSYS; > > How do you justify this choice of return value? This isn't even a hypercall > handler. That make_dom_dt_node() isn't provided by interrupt controller, so isn't supported or as it mentioned in the comment "not implemented in public/errno.h: XEN_ERRNO(ENOSYS, 38) /* Function not implemented */ ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 14:09:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 14:09:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279150.1563707 (Exim 4.92) (envelope-from ) id 1wBCYN-0002zv-5p; Fri, 10 Apr 2026 14:09:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279150.1563707; Fri, 10 Apr 2026 14:09:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBCYN-0002zo-3C; Fri, 10 Apr 2026 14:09:47 +0000 Received: by outflank-mailman (input) for mailman id 1279150; Fri, 10 Apr 2026 14:09:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBCYM-0002zi-G1 for xen-devel@lists.xenproject.org; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4fb7dc0a-9e29-46c0-86d0-f7ef17501a72@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1775830994-AEB333D8-3A23452D/0/0 X-purgate-type: clean X-purgate-size: 2901 On 10.04.2026 16:00, Oleksii Kurochko wrote: > On 4/1/26 4:38 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> --- a/xen/arch/riscv/dom0less-build.c >>> +++ b/xen/arch/riscv/dom0less-build.c >>> @@ -3,6 +3,15 @@ >>> #include >>> #include >>> >>> +#include >>> + >>> +int __init make_intc_domU_node(struct kernel_info *kinfo) >>> +{ >>> + intc_make_domu_dt_node(kinfo); >>> + >>> + return 0; >>> +} >> >> Is this wrapper really needed? Can't what's intc_make_domu_dt_node() right >> now become make_intc_domU_node()? > > With current implementation no as intc_hw_ops used inside > intc_make_domu_dt_node() is declared as static. How does that matter if you simply rename intc_make_domu_dt_node()? > But I can introduce: > > enum intc_version intc_hw_version(void) > { > return intc_hw_ops->info->hw_version; > } > > and the in make_intc_domU_node() just use switch/case to call interrupt > controller specific functions. > > Would it be better? It will also help to ... > >> >>> @@ -41,6 +41,10 @@ struct intc_hw_operations { >>> >>> /* handle external interrupt */ >>> void (*handle_interrupt)(struct cpu_user_regs *regs); >>> + >>> + /* Create interrupt controller node for domain */ >>> + int (*make_dom_dt_node)(const struct kernel_info *kinfo, >>> + const struct dt_device_node *intc); >> >> An __init-only hook is somewhat risky, just to mention it. In IOMMU code >> besides struct iommu_ops we have struct iommu_init_ops, just to give an >> example of where the same could have been the case. > > .. not introduce hooks in this structure which won't exist after init. That would be nice (as already said). >>> --- a/xen/arch/riscv/intc.c >>> +++ b/xen/arch/riscv/intc.c >>> @@ -67,3 +67,11 @@ void intc_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) >>> intc_set_irq_type(desc, desc->arch.type); >>> intc_set_irq_priority(desc, priority); >>> } >>> + >>> +int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) >>> +{ >>> + if ( intc_hw_ops && intc_hw_ops->make_dom_dt_node ) >>> + return intc_hw_ops->make_dom_dt_node(kinfo, intc_hw_ops->info->node); >>> + >>> + return -ENOSYS; >> >> How do you justify this choice of return value? This isn't even a hypercall >> handler. > > That make_dom_dt_node() isn't provided by interrupt controller, so isn't > supported or as it mentioned in the comment "not implemented in > public/errno.h: > XEN_ERRNO(ENOSYS, 38) /* Function not implemented */ "Function" as in "system call function" (normally; for us: "hypercall function"). ENOSYS really has a pretty narrow range of valid uses (according to my reading). EOPNOTSUPP is the more generic alternative. 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> +extern char viommu[]; As far as I can see this one is used only in this header by ... >=20 > /* data structure for each hardware IOMMU */ > struct host_iommu { > @@ -50,6 +51,12 @@ uint16_t viommu_get_type(void); > void add_to_host_iommu_list(paddr_t addr, paddr_t size, > const struct dt_device_node *node); >=20 > +static always_inline bool is_viommu_enabled(void) > +{ > + /* only smmuv3 emulation supported */ > + return !strcmp(viommu, "smmuv3"); > +} this function, it seems cleaner to me if viommu is static inside xen/xen/dr= ivers/passthrough/arm/viommu.c and this one can be defined there as well, so here we will have only the de= claration. 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bh=4VJ9kFlhw+z/hCTPHjAS7qoiehNMI6uP2dnFVadsX98=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=c4iVO3EKMywAXCLcVDfmnTSyDn6d4QWuuKZUDBgrjwPpPPjfZdttf6Aqbc4Z96GOL UXrOlN+nktiO+fKeR3c3sB5ogfmp6iZCatEwrNmVycswLpSZdOtPZWHyv+qFsrqho4 CDDorczrMHpj7qPcCWM2PyfL94N99Dcpmh4q56Rc7qBFP3bo4pRKBXVJtD1ZbmG4dP 6xaOWT+DBQFd7NEu95HA7voF5H7Cs6FSAzbXw9SfZFNSTO58hhXgNkIu1oHTqzIjMJ ozYJ1G94JKLA4P/viDMhVUZKNVBYtYFQnYkKEe+fZRGEOOlwiyt7X8JpJDybbxMiCp i144Qv6Vu+Jzw== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v3=202/3]=20libxl:=20Allow=20PCI=20device=20passthrough=20using=20-device=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775833436555 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260410150333.1533568-3-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-1-thierry.escande@vates.tech> References: <20260410150333.1533568-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.ae297a03d26745569ddf3718bc0d083e?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 15:03:57 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1775833438-FE350A3D-E2F968E1/0/0 X-purgate-type: clean X-purgate-size: 12267 This change makes use of the new option 'hotplug' for host PCI devices passthrough'd to the guest. If hotplug=0 is used in the pci device configuration table, the device will be attached to the guest using the Qemu command line as '-device xen-pci-passthrough,hostaddr=...' The host device configuration is passed to the -device option as a json array, just like it's done for hotplug using QMP. The json array is created by a new internal function libxl__device_pci_get_qmp_json() that is also used by pci_add_qmp_device_add(). Then, instead of sending the 'device_add' command, the device_add callback is called to perform the 'query-pci' check to make sure the passthrough'd device is present. In the same way at shutdown, the device is not removed using QMP and only the pci_remove_done() function is called. As with QMP, the use of the 'hotplug=0' option honors the 'seize' option by adding the PCI device to the assignable list if needed. This mimics what is done in libxl__device_pci_add() with regards to seize option and the assignable PCI device list. This allows to display a proper error message if the device is not assignable before Qemu starts. To do so the function pciback_dev_is_assigned() has been renamed as libxl__pciback_dev_is_assigned() and made available internally, as well as libxl__device_pci_assignable_add(). Also, libxl_pci_assignable() is now exported in libxl.h and renamed as libxl_device_pci_assignable() since its prototype looks like the other libxl_device_pci_*() APIs. Example use: pci = [ "00:03.0,seize=1,hotplug=0" ] Signed-off-by: Thierry Escande --- v2: - Add support for YAJL json parser v3: - Move code block for device command line parameters creation to a correct place. - Better handling of PCI device assignation check to display the correct error message if the device is not assignable. --- tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 85 +++++++++++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 7 +++ tools/libs/light/libxl_pci.c | 57 ++++++++++++++------- 4 files changed, 132 insertions(+), 18 deletions(-) diff --git a/tools/include/libxl.h b/tools/include/libxl.h index 7c098edab6..efd2664a90 100644 --- a/tools/include/libxl.h +++ b/tools/include/libxl.h @@ -2666,6 +2666,7 @@ int libxl_device_pci_assignable_add(libxl_ctx *ctx, libxl_device_pci *pci, int r int libxl_device_pci_assignable_remove(libxl_ctx *ctx, libxl_device_pci *pci, int rebind); libxl_device_pci *libxl_device_pci_assignable_list(libxl_ctx *ctx, int *num); void libxl_device_pci_assignable_list_free(libxl_device_pci *list, int num); +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci); /* CPUID handling */ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str); diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c index 511ec76a65..28e4adbd4f 100644 --- a/tools/libs/light/libxl_dm.c +++ b/tools/libs/light/libxl_dm.c @@ -1798,6 +1798,91 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, break; } + if (guest_config->num_pcidevs) { + libxl_device_pci *pci; + libxl__json_object *qmp_json; + char *json_str; +#ifdef HAVE_LIBJSONC + json_object *jso; + const char *buf; +#elif defined(HAVE_LIBYAJL) + yajl_gen hand; + /* memory for 'buf' is owned by 'hand' */ + const unsigned char *buf; + libxl_yajl_length len; +#else +# error Missing JSON library +#endif + + for (i = 0; i < guest_config->num_pcidevs; i++) { + pci = &guest_config->pcidevs[i]; + + if (pci->hotplug) + continue; + + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pci)) { + rc = libxl__device_pci_assignable_add(gc, pci, 1); + if (rc) + return rc; + } + + if (!libxl_device_pci_assignable(libxl__gc_owner(gc), pci)) { + LOGD(ERROR, guest_domid, "PCI device %x:%x:%x.%x is not assignable", + pci->domain, pci->bus, pci->dev, pci->func); + return ERROR_FAIL; + } + + qmp_json = libxl__device_pci_get_qmp_json(gc, pci); + +#ifdef HAVE_LIBJSONC + rc = libxl__json_object_to_json_object(gc, &jso, qmp_json); + if (rc) + return rc; + + buf = json_object_to_json_string_ext(jso, + JSON_C_TO_STRING_PLAIN); + if (!buf) { + json_object_put(jso); + return ERROR_NOMEM; + } +#elif defined(HAVE_LIBYAJL) + hand = libxl_yajl_gen_alloc(NULL); + if (!hand) { + return ERROR_NOMEM; + } +#if HAVE_YAJL_V2 + /* Disable beautify for data sent to QEMU */ + yajl_gen_config(hand, yajl_gen_beautify, 0); +#endif + + rc = libxl__json_object_to_yajl_gen(gc, hand, qmp_json); + if (rc) { + yajl_gen_free(hand); + return rc; + } + + rc = yajl_gen_get_buf(hand, &buf, &len); + if (rc != yajl_gen_status_ok) { + yajl_gen_free(hand); + return rc; + } +#endif + + json_str = libxl__strdup(gc, (const char *)buf); + if (json_str) + flexarray_vappend(dm_args, "-device", json_str, NULL); + +#ifdef HAVE_LIBJSONC + json_object_put(jso); +#elif defined(HAVE_LIBYAJL) + yajl_gen_free(hand); +#endif + + if (!json_str) + return ERROR_NOMEM; + } + } + if (state->dm_runas) { if (qemu_opts->have_runwith_user) { flexarray_append_pair(dm_args, "-run-with", diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h index b65e0064b9..cab2ab4526 100644 --- a/tools/libs/light/libxl_internal.h +++ b/tools/libs/light/libxl_internal.h @@ -1729,6 +1729,13 @@ _hidden int libxl__device_pci_setdefault(libxl__gc *gc, uint32_t domid, libxl_device_pci *pci, bool hotplug); _hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, const libxl_domain_config *d_config); +_hidden libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci); +_hidden int libxl__pciback_dev_is_assigned(libxl__gc *gc, + libxl_device_pci *pci); +_hidden int libxl__device_pci_assignable_add(libxl__gc *gc, + libxl_device_pci *pci, + int rebind); /* from libxl_dtdev */ diff --git a/tools/libs/light/libxl_pci.c b/tools/libs/light/libxl_pci.c index 49d272d0de..07d005e71d 100644 --- a/tools/libs/light/libxl_pci.c +++ b/tools/libs/light/libxl_pci.c @@ -686,7 +686,7 @@ out: return rc; } -static int pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) +int libxl__pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) { char * spath; int rc; @@ -755,9 +755,9 @@ static int pciback_dev_unassign(libxl__gc *gc, libxl_device_pci *pci) return 0; } -static int libxl__device_pci_assignable_add(libxl__gc *gc, - libxl_device_pci *pci, - int rebind) +int libxl__device_pci_assignable_add(libxl__gc *gc, + libxl_device_pci *pci, + int rebind) { libxl_ctx *ctx = libxl__gc_owner(gc); unsigned dom, bus, dev, func; @@ -798,7 +798,7 @@ static int libxl__device_pci_assignable_add(libxl__gc *gc, } /* Check to see if it's already assigned to pciback */ - rc = pciback_dev_is_assigned(gc, pci); + rc = libxl__pciback_dev_is_assigned(gc, pci); if ( rc < 0 ) { return ERROR_FAIL; } @@ -913,7 +913,7 @@ static int libxl__device_pci_assignable_remove(libxl__gc *gc, } /* Unbind from pciback */ - if ( (rc = pciback_dev_is_assigned(gc, pci)) < 0 ) { + if ( (rc = libxl__pciback_dev_is_assigned(gc, pci)) < 0 ) { return ERROR_FAIL; } else if ( rc ) { pciback_dev_unassign(gc, pci); @@ -1098,16 +1098,10 @@ out: pci_add_dm_done(egc, pas, rc); /* must be last */ } -static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, + libxl_device_pci *pci) { - STATE_AO_GC(pas->aodev->ao); libxl__json_object *args = NULL; - int rc; - - /* Convenience aliases */ - libxl_domid domid = pas->domid; - libxl_device_pci *pci = &pas->pci; - libxl__ev_qmp *const qmp = &pas->qmp; libxl__qmp_param_add_string(gc, &args, "driver", "xen-pci-passthrough"); @@ -1134,11 +1128,30 @@ static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) if (pci->permissive) libxl__qmp_param_add_bool(gc, &args, "permissive", true); + return args; +} + +static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +{ + STATE_AO_GC(pas->aodev->ao); + libxl__json_object *args = NULL; + int rc = 0; + + /* Convenience aliases */ + libxl_domid domid = pas->domid; + libxl_device_pci *pci = &pas->pci; + libxl__ev_qmp *const qmp = &pas->qmp; + + args = libxl__device_pci_get_qmp_json(gc, pci); + qmp->ao = pas->aodev->ao; qmp->domid = domid; qmp->payload_fd = -1; qmp->callback = pci_add_qmp_device_add_cb; - rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + if (pci->hotplug) + rc = libxl__ev_qmp_send(egc, qmp, "device_add", args); + else + pci_add_qmp_device_add_cb(egc, qmp, NULL, 0); if (rc) goto out; return; @@ -1509,7 +1522,7 @@ int libxl_device_pci_add(libxl_ctx *ctx, uint32_t domid, return AO_INPROGRESS; } -static bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) { libxl_device_pci *pcis; int num; @@ -1572,13 +1585,13 @@ void libxl__device_pci_add(libxl__egc *egc, uint32_t domid, rc = libxl__device_pci_setdefault(gc, domid, pci, !starting); if (rc) goto out; - if (pci->seize && !pciback_dev_is_assigned(gc, pci)) { + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pci)) { rc = libxl__device_pci_assignable_add(gc, pci, 1); if ( rc ) goto out; } - if (!libxl_pci_assignable(ctx, pci)) { + if (!libxl_device_pci_assignable(ctx, pci)) { LOGD(ERROR, domid, "PCI device %x:%x:%x.%x is not assignable", pci->domain, pci->bus, pci->dev, pci->func); rc = ERROR_FAIL; @@ -1820,6 +1833,14 @@ static void do_pci_remove(libxl__egc *egc, pci_remove_state *prs) libxl_domain_type type = libxl__domain_type(gc, domid); libxl_device_pci *pci = &prs->pci; int rc, num; + + /* Passthrough'd device has been passed to Qemu command line so there is + * no need to remove it via QMP */ + if (!pci->hotplug) { + pci_remove_done(egc, prs, 0); + return; + } + pcis = libxl_device_pci_list(ctx, domid, &num); if (!pcis) { rc = ERROR_FAIL; -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:04:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:04:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279247.1563753 (Exim 4.92) (envelope-from ) id 1wBDOf-0003iD-QS; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775833425; x=1776103425; bh=9OW/2hjgr5no2WPwd7Dtyhno1ODNPbzpH/8YCAXQ9Vk=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=s3lqZrO17OfxWadpOXgQ4gFi0VDvGEu+MUrgn9B8zRWkQKcQ2kD904g3qGpoladxe xFlJRn8BT/f4VU7RLv8wj/+cnVRTPosN5bC5xXe2RwXaLGXQn/99JJ+VJDHeBnx8oH rD5lUsapNbxTjXpy8XGjevA8wU9SILn6FJpw/qtO9YCDC0hVWdfaY+wgKkLNJ6STq5 AFLmE+rw8ZnqfzFSHwo4kLXwBDD++ohYsfl61Zq3KSImJoWiziaRdg3QX3TlEqoPXi A6zYsxndfQoj49iNh04UMV29H5Np+xgF7QfOhgQ1ab3SHbjiHqdNiX4T+BfMXlImN8 CbvzAr5mLwNSw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775833425; x=1776093925; i=thierry.escande@vates.tech; bh=9OW/2hjgr5no2WPwd7Dtyhno1ODNPbzpH/8YCAXQ9Vk=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=1Nim0Iqpd25JmKGUpuarsrJJiWCzr0aGAti7V45jbykMUP6fQKi7CPcACfp6uxyYx qvZseWXVi4yomQe4aJAVmi1u0SuycfPAxByqXuDUjZlV1mQDzU5MCp5rPzrK95ofdp +ZLH4HESBbp1wM3W8BQ1n16CPbiWnmkHQZLvi/sJvymgOWeKP3TcYu42Uf0UvmFAtt qi1kfIPhSGppd4Qh3mWwRIwARueUkp58THypAQCHKZ6VOajdm7HdlUeCFowF4GdDwR PKYD5ZT9XH0MJ86E/pqVKjL/TFmyKYekIu34s89GXzWq1uTf3iWxek+Egyuok6JrIO +gjwbmz9zX52w== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v3=200/3]=20xl:=20Allow=20PCI=20devices=20to=20be=20passthrough'd=20via=20Qemu=20command=20line?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775833424967 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260410150333.1533568-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.e76f9c812507451585636239d8b3ff11?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 15:03:45 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1775833427-ADB3FCD1-BE51F373/0/0 X-purgate-type: clean X-purgate-size: 2693 This series adds support for a new 'hotplug' option for PCI devices to be passthrough'd to guests. The current mechanism for device passthrough uses QMP device_add command to hot-plug PCI devices to the guest Qemu instance. This is an issue for guests running on Q35 chipset (preliminary support posted at [1]) since the Q35 PCI root bus does not support hotplug. Devices could be hotplugged to a secondary PCI bus but Xen only support 1 PCI bus for now. The 'hotplug' option allows to control how devices are attached to the guest, either by using the legacy QMP mechanism (this is the default) or by passing it directly to the Qemu command line using xen-pci-passthrough device. Example usage in cfg file: pci = [ "00:03.0,seize=1,hotplug=0" ] Since Qemu -device option accepts parameters in json format, this patchset adds a new internal function libxl__device_pci_get_qmp_json() that generates the device json object used for both QMP hotplug and command line passing. Also, to handle the assignable PCI device list, the function libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and is made available from libxl.h for access in libxl_dm.c. 2 other functions are also exported internally: libxl__pciback_dev_is_assigned() and libxl__device_pci_assignable_add(). This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. Disabling the hotplug mechanism might be made mandatory for Q35 machines later, once Q35 support is merged upstream. [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.escande@vates.tech/ Changes in v2: - Add support for YAJL json parser Changes in v3: - Move code block of device command line parameters creation - Better handling of pci device assignation Thierry Escande (3): xl: Add pci device hotplug option libxl: Allow PCI device passthrough using -device Qemu command line docs: provide description for pci hotplug option docs/man/xl-pci-configuration.5.pod | 17 ++++++ docs/man/xl.cfg.5.pod.in | 6 ++ tools/include/libxl.h | 1 + tools/libs/light/libxl_dm.c | 85 +++++++++++++++++++++++++++++ tools/libs/light/libxl_internal.h | 7 +++ tools/libs/light/libxl_pci.c | 57 +++++++++++++------ tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 + tools/xl/xl_parse.c | 5 ++ 9 files changed, 163 insertions(+), 18 deletions(-) -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:04:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:04:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279248.1563761 (Exim 4.92) (envelope-from ) id 1wBDOk-0003w4-4Q; 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Fri, 10 Apr 2026 17:03:52 +0200 Received: from [198.2.187.14] (helo=mail187-14.suw11.mandrillapp.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91157-3760-0a2a45050019-c602bb0e37d9-3 for ; Fri, 10 Apr 2026 17:03:52 +0200 Received: from pmta09.mandrill.prod.suw01.rsglab.com (localhost [127.0.0.1]) by mail187-14.suw11.mandrillapp.com (Mailchimp) with ESMTP id 4fsg6v1yD1z8XS3x7 for ; Fri, 10 Apr 2026 15:03:51 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 1b7cd7e0c2ad488cb44a75c9c4b1170f; Fri, 10 Apr 2026 15:03:51 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="thierry.escande@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1775833431; x=1776103431; bh=ZKqdPVMpXtT8gh10Bvf+Ia+b2oBjvpMt/gEGKWUOgWA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=RUzm0ypYZjsM3tjwMqQz4NY8RCCsHtMq4taK9jd5PbHnE4fDNACX3iodyNqT9E0GG JC+KNLn/3gN0O2zq7Q/f/+dOlYK+OgJa0KvUMkZf+2EG2tQYHeEeo+TrHtAEV34tKn 1CBqFJhXfpTVAQN7So4S53WnSFXZRY3/EvKSO0l5Ev+RC3p78x0KkwiGRaNYOA2VnC tBggTYyI47X9ia6mknJvnFF8ZpBN7DsLmI49maNZ2avy5GJN2hppyAOnmsoFq48mX7 t15nokIppoTzQDTA0SEA+w9wXENzF0zl18CAtettO1JAS6V6taWGa2ZXNDA3Q5NePg QEqfgUXtzclUw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1775833431; x=1776093931; i=thierry.escande@vates.tech; bh=ZKqdPVMpXtT8gh10Bvf+Ia+b2oBjvpMt/gEGKWUOgWA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=RjJqQVaLkMAOrIZEXjjR3KIvv/y7fZaSbBkwtlQX7gXji2yo2x6LtVxKP827PQz0t qlsPnEs/Ih56CkDGdd/jITaHWr/Qp3bl6G3pZPL7W52NVypXVupJSE4+IDJ8xPNlrt KJnFngeOVLU38/xH495ANIhQBrAqk68S409xwDQIs4z+xNzbcufYkWZIn3d7hSNSdg DJIjir1GUbzCegIrCr7NLavlIP53Syw3eFpyPRIrfUIYKajyMGVereUnkCYOy8bxO/ 8LkRdHDVlUt2mat5Q+pHGvIF/dyGPE2jGT7c64SIpoOLiemi1iryycHGMEZq0eWSPL PkETzhOx3xOOg== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v3=201/3]=20xl:=20Add=20pci=20device=20hotplug=20option?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775833430450 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260410150333.1533568-2-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-1-thierry.escande@vates.tech> References: <20260410150333.1533568-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.1b7cd7e0c2ad488cb44a75c9c4b1170f?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 15:03:51 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1775833432-2252396F-A071C152/0/0 X-purgate-type: clean X-purgate-size: 2930 This option is used to passthrough PCI devices using the Qemu command line (-device driver,...) instead of the QMP hot-plug mechanism. This is needed for Q35 support since its PCI root bus doesn't support hotplugging. If not specified, the default behavior is to use hotplug via QMP. Signed-off-by: Thierry Escande --- v2: no change v3: no change --- tools/libs/light/libxl_types.idl | 1 + tools/libs/util/libxlu_pci.c | 2 ++ tools/xl/xl_parse.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl index a7893460f0..aca0e93793 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -922,6 +922,7 @@ libxl_device_pci = Struct("device_pci", [ ("seize", bool), ("rdm_policy", libxl_rdm_reserve_policy), ("name", string), + ("hotplug", bool), ]) libxl_device_rdm = Struct("device_rdm", [ diff --git a/tools/libs/util/libxlu_pci.c b/tools/libs/util/libxlu_pci.c index 294482c6d7..f6440c878b 100644 --- a/tools/libs/util/libxlu_pci.c +++ b/tools/libs/util/libxlu_pci.c @@ -192,6 +192,8 @@ int xlu_pci_parse_spec_string(XLU_Config *cfg, libxl_device_pci *pci, name_present = true; pci->name = strdup(val); if (!pci->name) ret = ERROR_NOMEM; + } else if (!strcmp(key, "hotplug")) { + pci->hotplug = atoi(val); } else { XLU__PCI_ERR(cfg, "Unknown PCI_SPEC_STRING option: %s", key); ret = ERROR_INVAL; diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 48c72dce9c..7ea2a76662 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -1361,6 +1361,7 @@ void parse_config_data(const char *config_source, int pci_msitranslate = 0; int pci_permissive = 0; int pci_seize = 0; + int pci_hotplug = 1; int i, e; int num_llc_colors; int num_xs_quota; @@ -1699,6 +1700,9 @@ void parse_config_data(const char *config_source, if (!xlu_cfg_get_long (config, "pci_seize", &l, 0)) pci_seize = l; + if (!xlu_cfg_get_long (config, "pci_hotplug", &l, 0)) + pci_hotplug = l; + if (!xlu_cfg_get_string(config, "rdm", &buf, 0)) { libxl_rdm_reserve rdm; if (!xlu_rdm_parse(config, &rdm, buf)) { @@ -1720,6 +1724,7 @@ void parse_config_data(const char *config_source, pci->power_mgmt = pci_power_mgmt; pci->permissive = pci_permissive; pci->seize = pci_seize; + pci->hotplug = pci_hotplug; /* * Like other pci option, the per-device policy always follows * the global policy by default. -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:04:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:04:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279252.1563779 (Exim 4.92) (envelope-from ) id 1wBDOy-0004XU-I3; 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bh=jr8KFyjmD49J7UOWjFVMqFhnqGaZw9GrcOVJv0UGtBY=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=K+IAFIljLDaenGDIZpVAj4OhrjiM1gaTMVcA2SB/msyQmbEMyFET8Zrj/yYb2SEhd reKhlmU5aKBlOBjjJgWcKwvycw/8rpk1ICCoyoLDJtytg2ex0tpietLonftNdzF3Y/ /g0+FKSi8kPTlC/iC8NC8m535bC1LPxDJ3vv0hWncBWw2ovCX6fj2y/CnSRg5nzQ45 ER5mrV8L0bGowjqv8SvcZ5k33TyyhSc9/vYzFo1/X9ozVI19jezML4nAkhtW1l1sJu wCRhSO5Yi3CSvc+jUgcg10SmX/YtmnePMDYFvMTmr58cN94h5TrEtZUrgEezpL/aBq QdWWiegHg3iTQ== From: "Thierry Escande" Subject: =?utf-8?Q?[RFC=20PATCH=20v3=203/3]=20docs:=20provide=20description=20for=20pci=20hotplug=20option?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1775833442211 To: xen-devel@lists.xenproject.org Cc: "Thierry Escande" , "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Message-Id: <20260410150333.1533568-4-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-1-thierry.escande@vates.tech> References: <20260410150333.1533568-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.d6430dce3e4b4bb081ddae9aa27b1492?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260410:md Date: Fri, 10 Apr 2026 15:04:05 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1775833446-5714D152-747EFEF2/0/0 X-purgate-type: clean X-purgate-size: 1912 This patch adds description for the 'hotplug' PCI option, allowing devices to be attached to the guest using the legacy QMP hotplug mechanism or by passing them to the Qemu command line using '-device'. Signed-off-by: Thierry Escande --- v2: no change v3: no change --- docs/man/xl-pci-configuration.5.pod | 17 +++++++++++++++++ docs/man/xl.cfg.5.pod.in | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/docs/man/xl-pci-configuration.5.pod b/docs/man/xl-pci-configuration.5.pod index 0691f06ad3..8b664173cb 100644 --- a/docs/man/xl-pci-configuration.5.pod +++ b/docs/man/xl-pci-configuration.5.pod @@ -166,6 +166,23 @@ dom0 without confirmation. Please use with care. =back +=item B=I + +=over 4 + +=item Description + +Tells L to use QMP hotplug mechanism to attach assignable device to +the guest, or to pass it via Qemu command line using +'B<-device xen-pci-passthrough,...>'. The default is to use the legacy QMP +mechanism. + +=item Default Value + +1 + +=back + =item B=I =over 4 diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 3aac0bc4fb..181aaffa0f 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -1230,6 +1230,12 @@ B<(HVM only)> Changes the default value of B for all PCI devices passed through to this VM. See B above. +=item B + +B<(HVM only)> Changes the default value of B for all PCI +devices passed through to this VM. See L for +more details. + =item B Enable graphics device PCI passthrough. This option makes an assigned -- 2.53.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:12:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:12:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279290.1563787 (Exim 4.92) (envelope-from ) id 1wBDWp-00078x-ES; Fri, 10 Apr 2026 15:12:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279290.1563787; Fri, 10 Apr 2026 15:12:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBDWp-00078q-Bm; Fri, 10 Apr 2026 15:12:15 +0000 Received: by outflank-mailman (input) for mailman id 1279290; Fri, 10 Apr 2026 15:12:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBDWn-00078k-Di for xen-devel@lists.xenproject.org; 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Message-ID: Date: Fri, 10 Apr 2026 18:12:08 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/sched: rtds: re-arm repl_timer after timer re-initialization To: Juergen Gross , "xen-devel@lists.xenproject.org" Cc: Dario Faggioli , George Dunlap , Meng Xu References: <548ea03cc3c3287b1f5dcd101b3c2990ebc08089.1775208527.git.oleksii_moisieiev@epam.com> <775bc23d-7cd4-43b4-9e5f-0c70204b4262@suse.com> <66b7eaff-f7b9-4737-b32b-ca9ff7b661c1@epam.com> Content-Language: en-US From: Oleksii Moisieiev In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: WA2P291CA0034.POLP291.PROD.OUTLOOK.COM (2603:10a6:1d0:1f::7) To DU5PR03MB10263.eurprd03.prod.outlook.com (2603:10a6:10:519::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU5PR03MB10263:EE_|AS8PR03MB8420:EE_ X-MS-Office365-Filtering-Correlation-Id: 87978a41-4994-417b-a200-08de9713895a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|56012099003|18002099003|22082099003; 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While we haven't encountered this problem in practice yet, it >>> could occur >>> in the future, so I believe it should be addressed proactively. >> >> For being able to occur in future, the handling of removing a cpu from a >> cpupool would need to be changed. Considering the refusal to remove the >> last cpu from a populated cpupool is on purpose (this avoids leaving a >> domain without any cpu to run on), adding the code as you suggest would >> just be an addition without any benefit. >> >> It isn't doing any harm (other than adding code without purpose), so I >> won't explicitly NAK the patch, but I won't Ack it either. > > One further remark: I would ack the addition of an > ASSERT(list_empty(replq)) > instead of the conditional set_timer() call. > You're right: with the current cpupool semantics, when the timer is re-initialized in this path, replq is expected to be empty. In that case there is nothing to re-arm, and the timer can be programmed later when a new replenishment event is queued. Now I see that it would probably be better to update the cpupool logic to prohibit removing the last pCPU from a cpupool. In that case, this fix — even with the ASSERT — seems to be no longer relevant. I think I'd rather post an update for the cpupool semantics and drop this patch. Or I can send a v3 with the ASSERT if you think that is still reasonable. Thank you for the review! -- Oleksii > > Juergen From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:19:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:19:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279306.1563796 (Exim 4.92) (envelope-from ) id 1wBDdz-00080W-43; Fri, 10 Apr 2026 15:19:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279306.1563796; Fri, 10 Apr 2026 15:19:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBDdz-00080P-1W; Fri, 10 Apr 2026 15:19:39 +0000 Received: by outflank-mailman (input) for mailman id 1279306; Fri, 10 Apr 2026 15:19:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBDdw-00080D-RO for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:19:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBDdw-00DLbO-7I for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:19:36 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d914f5-2eae-0a2a0a5409dd-0a2a4508a860-30 for ; Fri, 10 Apr 2026 17:19:36 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91507-fab6-0a2a45080019-d1558029cdb3-3 for ; Fri, 10 Apr 2026 17:19:36 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-48896199cbaso23188255e9.1 for ; Fri, 10 Apr 2026 08:19:36 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnZFQYFAwAAAAAACgkQsN6d1ii/Ey9G swf/Z10r4UGFu04AWBsmF/wgKwxBR/tFi4t/9wQiaxaDaPSoRURJpQMjVf6/b2Mb4uuawn9qD+A4 +kbnyPhcikwQzD+iTqblnIFgd7GqRD7gTt2nMz3zTp+FhZRyjHRVMVsZvx5oLmndYitET5WObXXK o1R5lbTB1AWfPVzo1r4xAA9DZF1XDln+WUQevn4fAyhkuEFLrGEBfnim0uLhLzSjJuMRMjBZe2NX iV24dzIPJtSZxCdz6DJDQHdcBQoSjgWlS5lTSt4mSZ3Rl6joOS637jHj4y0cz1FuNh/CeLxR7frX nsi/Ln2gISDrF1HqvIwJZpAZDEiQTdbZYcvIK1W8OA== =kNoT -----END PGP SIGNATURE----- --------------WRoAP1gvq8CcDShwNVvfAsI3-- From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:28:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:28:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279341.1563806 (Exim 4.92) (envelope-from ) id 1wBDml-0001Oy-VM; Fri, 10 Apr 2026 15:28:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279341.1563806; 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b=FgiH3513OJvbm3eAC03QI5IF18oYSOXaWSsyqX2Wj3h4maVnc1iKxmPSrCRXtuhlsZnID6ZgKgcdts3TPJSKRnrwNhc67lwxZlZNWZKefK7NbC/Gh63Dh0CKL5ku7DNp1qoHffbEHe59zZVU3cO6Mok+/NiF6kRq79oOKIucXHk= From: Luca Fancellu To: Milan Djokic CC: "xen-devel@lists.xenproject.org" , Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: Re: [PATCH v3 08/23] xen/arm: vsmmuv3: Add support for registers emulation Thread-Topic: [PATCH v3 08/23] xen/arm: vsmmuv3: Add support for registers emulation Thread-Index: AQHcyP6NKmaLb7Af3Um2I3EGy28uyQ== Date: Fri, 10 Apr 2026 15:27:34 +0000 Message-ID: References: <25adb33c4be3932c2d946cf7757c933eb042476c.1774918270.git.milan_djokic@epam.com> In-Reply-To: <25adb33c4be3932c2d946cf7757c933eb042476c.1774918270.git.milan_djokic@epam.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3826.700.81.1.6) Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bJ7kk23aeFiZdra/mzV33Dx5W3Hu/9Z61hdRQKnwuva3+dVVFXghtqeEktwlLbhsSHbL89svdCT+JTMzT7e8qcXBHko8ebQEwZeLHJyR1rZm/NKbmm4NXhk2nbSYstFHhQPXIL4Q2NJO+OC21IdbhjRIKT00TV0QuShgfHDkQ8zppjEtQ5H/exTfwaF9Ja3axX/xSkcQcUDY1+Asn04vB24sv2pyFx0dwYkzojiLM19eUEIjJQhzjyxIsPU5RqXx8K/eoOqEbendubJ0ME+2c/FvV/KgijVBJ+rs9FhxZxViMhGkhVbKin0vSHMiGX1rPTI+InxIIa0U8XiXnrn7HNAsMT/iMEPsEfLbCrQtdRM6x3M/s+f7TSeeviDmxD7gjX2RGoBom0I7MPV0fpI/ljjo9BKtmcelQule+ht98tIPntUhP3wXODruEaaTUoQ8 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2026 15:28:37.9069 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aef32ddc-ac5f-452b-4375-08de9715d664 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF0001E9C5.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MI3PR08MB11908 X-purgate-ID: tlsNG-720697/1775834921-47323CD1-D5034290/0/0 X-purgate-type: clean X-purgate-size: 9194 Hi Milan, > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthr= ough/arm/vsmmu-v3.c > index e36f200ba5..3ae1e62a50 100644 > --- a/xen/drivers/passthrough/arm/vsmmu-v3.c > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c >=20 [...] > static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > register_t r, void *priv) > { > + struct virt_smmu *smmu =3D priv; > + uint64_t reg; > + uint32_t reg32; > + > + switch ( info->gpa & 0xffff ) > + { > + case VREG32(ARM_SMMU_CR0): > + reg32 =3D smmu->cr[0]; > + vreg_reg32_update(®32, r, info); > + smmu->cr[0] =3D reg32; > + smmu->cr0ack =3D reg32 & ~CR0_RESERVED; > + break; > + > + case VREG32(ARM_SMMU_CR1): > + reg32 =3D smmu->cr[1]; > + vreg_reg32_update(®32, r, info); > + smmu->cr[1] =3D reg32; > + break; > + > + case VREG32(ARM_SMMU_CR2): > + reg32 =3D smmu->cr[2]; > + vreg_reg32_update(®32, r, info); > + smmu->cr[2] =3D reg32; > + break; > + > + case VREG64(ARM_SMMU_STRTAB_BASE): > + reg =3D smmu->strtab_base; > + vreg_reg64_update(®, r, info); > + smmu->strtab_base =3D reg; > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): > + reg32 =3D smmu->strtab_base_cfg; > + vreg_reg32_update(®32, r, info); > + smmu->strtab_base_cfg =3D reg32; > + > + smmu->sid_split =3D FIELD_GET(STRTAB_BASE_CFG_SPLIT, reg32); > + smmu->features |=3D STRTAB_BASE_CFG_FMT_2LVL; > + break; > + > + case VREG32(ARM_SMMU_CMDQ_BASE): I think this needs to be VREG64 > + reg =3D smmu->cmdq.q_base; > + vreg_reg64_update(®, r, info); > + smmu->cmdq.q_base =3D reg; > + smmu->cmdq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->cmdq= .q_base); > + if ( smmu->cmdq.max_n_shift > SMMU_CMDQS ) > + smmu->cmdq.max_n_shift =3D SMMU_CMDQS; > + break; > + > + case VREG32(ARM_SMMU_CMDQ_PROD): > + reg32 =3D smmu->cmdq.prod; > + vreg_reg32_update(®32, r, info); > + smmu->cmdq.prod =3D reg32; > + break; > + > + case VREG32(ARM_SMMU_CMDQ_CONS): > + reg32 =3D smmu->cmdq.cons; > + vreg_reg32_update(®32, r, info); > + smmu->cmdq.cons =3D reg32; > + break; > + > + case VREG32(ARM_SMMU_EVTQ_BASE): And also this one VREG64 > + reg =3D smmu->evtq.q_base; > + vreg_reg64_update(®, r, info); > + smmu->evtq.q_base =3D reg; > + smmu->evtq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->evtq= .q_base); > + if ( smmu->cmdq.max_n_shift > SMMU_EVTQS ) > + smmu->cmdq.max_n_shift =3D SMMU_EVTQS; This seems a typo, I think here we want to modify the evtq, not the cmdq? So in case both condition and assignment needs to change. > + break; > + > + case VREG32(ARM_SMMU_EVTQ_PROD): > + reg32 =3D smmu->evtq.prod; > + vreg_reg32_update(®32, r, info); > + smmu->evtq.prod =3D reg32; > + break; > + > + case VREG32(ARM_SMMU_EVTQ_CONS): > + reg32 =3D smmu->evtq.cons; > + vreg_reg32_update(®32, r, info); > + smmu->evtq.cons =3D reg32; > + break; > + > + case VREG32(ARM_SMMU_IRQ_CTRL): > + reg32 =3D smmu->irq_ctrl; > + vreg_reg32_update(®32, r, info); > + smmu->irq_ctrl =3D reg32; > + break; > + > + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): > + reg =3D smmu->gerror_irq_cfg0; > + vreg_reg64_update(®, r, info); > + smmu->gerror_irq_cfg0 =3D reg; > + break; > + > + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): > + reg =3D smmu->evtq_irq_cfg0; > + vreg_reg64_update(®, r, info); > + smmu->evtq_irq_cfg0 =3D reg; > + break; > + > + case VREG32(ARM_SMMU_GERRORN): > + reg =3D smmu->gerrorn; > + vreg_reg64_update(®, r, info); this should be vreg_reg32_update > + smmu->gerrorn =3D reg; > + break; > + > + default: > + printk(XENLOG_G_ERR > + "%pv: vSMMUv3: unhandled write r%d offset %"PRIpaddr"\n", > + v, info->dabt.reg, (unsigned long)info->gpa & 0xffff); > + return IO_ABORT; > + } > + > return IO_HANDLED; > } >=20 > static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, > register_t *r, void *priv) > { > + struct virt_smmu *smmu =3D priv; > + uint64_t reg; > + > + switch ( info->gpa & 0xffff ) > + { > + case VREG32(ARM_SMMU_IDR0): > + reg =3D FIELD_PREP(IDR0_S1P, 1) | FIELD_PREP(IDR0_TTF, 2) | > + FIELD_PREP(IDR0_COHACC, 0) | FIELD_PREP(IDR0_ASID16, 1) | > + FIELD_PREP(IDR0_TTENDIAN, 0) | FIELD_PREP(IDR0_STALL_MODEL, = 1) | > + FIELD_PREP(IDR0_ST_LVL, 1) | FIELD_PREP(IDR0_TERM_MODEL, 1); > + *r =3D vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IDR1): > + reg =3D FIELD_PREP(IDR1_SIDSIZE, SMMU_IDR1_SIDSIZE) | > + FIELD_PREP(IDR1_CMDQS, SMMU_CMDQS) | > + FIELD_PREP(IDR1_EVTQS, SMMU_EVTQS); > + *r =3D vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IDR2): > + goto read_reserved; > + > + case VREG32(ARM_SMMU_IDR3): > + reg =3D FIELD_PREP(IDR3_RIL, 0); > + *r =3D vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IDR4): > + goto read_impl_defined; > + > + case VREG32(ARM_SMMU_IDR5): > + reg =3D FIELD_PREP(IDR5_GRAN4K, 1) | FIELD_PREP(IDR5_GRAN16K, 1= ) | > + FIELD_PREP(IDR5_GRAN64K, 1) | FIELD_PREP(IDR5_OAS, IDR5_OAS_= 48_BIT); > + *r =3D vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IIDR): > + *r =3D vreg_reg32_extract(ARM_SMMU_IIDR_VAL, info); > + break; > + > + case VREG32(ARM_SMMU_CR0): > + *r =3D vreg_reg32_extract(smmu->cr[0], info); > + break; > + > + case VREG32(ARM_SMMU_CR0ACK): > + *r =3D vreg_reg32_extract(smmu->cr0ack, info); > + break; > + > + case VREG32(ARM_SMMU_CR1): > + *r =3D vreg_reg32_extract(smmu->cr[1], info); > + break; > + > + case VREG32(ARM_SMMU_CR2): > + *r =3D vreg_reg32_extract(smmu->cr[2], info); > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE): this needs to be VREG64 I think > + *r =3D vreg_reg64_extract(smmu->strtab_base, info); > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): > + *r =3D vreg_reg32_extract(smmu->strtab_base_cfg, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_BASE): VREG64 > + *r =3D vreg_reg64_extract(smmu->cmdq.q_base, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_PROD): > + *r =3D vreg_reg32_extract(smmu->cmdq.prod, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_CONS): > + *r =3D vreg_reg32_extract(smmu->cmdq.cons, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_BASE): VREG64 > + *r =3D vreg_reg64_extract(smmu->evtq.q_base, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_PROD): > + *r =3D vreg_reg32_extract(smmu->evtq.prod, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_CONS): > + *r =3D vreg_reg32_extract(smmu->evtq.cons, info); > + break; > + > + case VREG32(ARM_SMMU_IRQ_CTRL): > + case VREG32(ARM_SMMU_IRQ_CTRLACK): > + *r =3D vreg_reg32_extract(smmu->irq_ctrl, info); > + break; > + > + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): > + *r =3D vreg_reg64_extract(smmu->gerror_irq_cfg0, info); > + break; > + > + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): > + *r =3D vreg_reg64_extract(smmu->evtq_irq_cfg0, info); > + break; > + > + case VREG32(ARM_SMMU_GERROR): > + *r =3D vreg_reg64_extract(smmu->gerror, info); vreg_reg32_extract > + break; > + > + case VREG32(ARM_SMMU_GERRORN): > + *r =3D vreg_reg64_extract(smmu->gerrorn, info); vreg_reg32_extract > + break; > + > + default: > + printk(XENLOG_G_ERR > + "%pv: vSMMUv3: unhandled read r%d offset %"PRIpaddr"\n", > + v, info->dabt.reg, (unsigned long)info->gpa & 0xffff); > + return IO_ABORT; > + } > + > + return IO_HANDLED; > + > + read_impl_defined: > + printk(XENLOG_G_DEBUG > + "%pv: vSMMUv3: RAZ on implementation defined register offset = %"PRIpaddr"\n", > + v, info->gpa & 0xffff); > + *r =3D 0; > + return IO_HANDLED; > + > + read_reserved: > + printk(XENLOG_G_DEBUG > + "%pv: vSMMUv3: RAZ on reserved register offset %"PRIpaddr"\n"= , > + v, info->gpa & 0xffff); > + *r =3D 0; > return IO_HANDLED; > } Cheers, Luca From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:41:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:41:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279379.1563815 (Exim 4.92) (envelope-from ) id 1wBDyi-0004Le-2X; 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Add support for generating an IMSIC node when >> building the guest DT. >> >> Keep a reference to the host IMSIC DT node and reuse its compatible >> property while constructing the guest-visible node. > > Again raises a migration concern. Presumably a guest would then be able > to migrate only to other hosts with the same compatible property. Right, but I don't think we can do too much and it is the simplest approach just to migrate to hosts with the same compatible property. If you concern is about DTS property then for IMSIC it will be always riscv,imsics according to the RISC-V DT spec. (IIRC, the only other option could be qemu,riscv). Actually, I can just hard code "riscv,imsic" explicitly instead of re-using of host name. If your concern is that we will migrate to a host which doesn't support IMSIC at all then we should or (a) don't migrate to such host or (b) provide an emulation of IMSIC. And option (b) would be terrible from at least performance point of view. >> +static int __init imsic_set_interrupt_extended_prop(struct domain *d, >> + void *fdt) >> +{ >> + uint32_t len = 0, pos = 0, cpu, phandle; > > At least pos and cpu should be of fixed width types. I thought that uint32_t is fixed width type, isn't it? > >> + uint32_t *irq_ext; >> + char buf[64]; > > Move this one into the loop's scope? I will do that. >> + int res; >> + >> + irq_ext = xvzalloc_array(uint32_t, d->max_vcpus * 2); >> + if ( !irq_ext ) >> + return -ENOMEM; >> + >> + for ( cpu = 0; cpu < d->max_vcpus; cpu++ ) >> + { >> + snprintf(buf, sizeof(buf), "/cpus/cpu@%u/interrupt-controller", cpu); >> + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt, buf)); >> + >> + if ( phandle <= 0 ) >> + return phandle; > > <= is odd to use on an unsigned type. Arm, in a similar situation, uses != . Agree, it should be !=. > > Yet then - if 0 is an error indicator, aren't you converting this into a > success indicator for the caller? I read incorrectly the comment of what fdt_get_phandle() returns. so it should be: if ( !phandle ) { res = -ENODEV; goto out; } goto here as xvfree() should be called in this case. > >> + irq_ext[pos++] = cpu_to_be32(phandle); >> + len += sizeof(uint32_t); > > As before, preferably sizeof() to clarify the connection. It's > pretty obvious here, but still. Yet then - do you really need to maintain > "len"? Why not use ... > >> + irq_ext[pos++] = cpu_to_be32(IRQ_S_EXT); >> + len += sizeof(uint32_t); >> + } >> + >> + res = fdt_property(fdt, "interrupts-extended", irq_ext, len); > > ... "d->max_vcpus * 2 * sizeof(*irq_ext)" here? Agree, it could and would be better. > >> + XVFREE(irq_ext); > > This can be just xvfree(), as the variable goes out of scpoe just afterwards > anyway. > >> + return res; >> +} >> + >> +int __init imsic_make_dt_node(const struct kernel_info *kinfo) > > So this function is unused until the next patch. Acceptable as long as Eclair > (or other) scans aren't done for RISC-V, but generally you may want to try to > get used to order patches such that this is avoided. > >> +{ >> + uint32_t len; >> + const void *data = NULL; > > Why the initializer? No, need any more, I had a case before so just missed to clean up properly. > >> + int res = 0; >> + void *fdt = kinfo->fdt; >> + const struct dt_device_node *host_imsic_node = imsic_cfg.host_node; >> + uint32_t *next_phandle = &kinfo->bd.d->arch.next_phandle; >> + >> + res = fdt_begin_node(fdt, host_imsic_node->full_name); >> + if ( res ) >> + return res; >> + >> + data = dt_get_property(host_imsic_node, "compatible", &len); >> + if ( !data ) >> + { >> + printk(XENLOG_ERR "%s: Can't find 'compatible' property\n", >> + host_imsic_node->full_name); >> + >> + return -ENOENT; >> + } > > Move fdt_begin_node() down below here? > >> --- a/xen/arch/riscv/include/asm/imsic.h >> +++ b/xen/arch/riscv/include/asm/imsic.h >> @@ -57,11 +57,16 @@ struct imsic_config { >> /* MSI */ >> const struct imsic_msi *msi; >> >> + /* DT node of IMSIC */ >> + const struct dt_device_node *host_node; > > Does "host" in the name carry much of a meaning? Maybe better dt_node, to > (potentially) distinguish it from a NUMA node which also may need tracking > for an imsic at some point? Maybe, not too much. Lets rename it. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:45:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:45:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279396.1563824 (Exim 4.92) (envelope-from ) id 1wBE2v-0004uJ-IH; Fri, 10 Apr 2026 15:45:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279396.1563824; Fri, 10 Apr 2026 15:45:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBE2v-0004uC-FB; Fri, 10 Apr 2026 15:45:25 +0000 Received: by outflank-mailman (input) for mailman id 1279396; Fri, 10 Apr 2026 15:45:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBE2u-0004u6-8R for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:45:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBE2t-009K4U-KT for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:45:23 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91b00-bab6-0a2a0a5309dd-0a2a4503b300-48 for ; Fri, 10 Apr 2026 17:45:23 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91b13-02b3-0a2a45030019-d1558033d46b-3 for ; Fri, 10 Apr 2026 17:45:23 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so21049325e9.0 for ; Fri, 10 Apr 2026 08:45:23 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d58a8445sm77111195e9.6.2026.04.10.08.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 08:45:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775835923; x=1776440723; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=92qdXREBVwsG+a0SGoPjpWEPYqqewbVtYm4T62FIQ3Y=; b=eL9rg+y53pajxd9Lvfi9yQXdtJchUuCyuXn1DvtbdRnEOe7PgEtPtz6pLlESVcLHPI y1R0uSWUDQi6Ef/KuHM2nAI1DiUcjAQOfVgDedntv/E2UiOE5Qx/b4N2nJf0LZ5cLrbK ja3HPaJ7u+n3XPENjiXIhLm13PmA2l+RzKc/tQBaOFoVXXzu65bVkiDk5XsDXy/ahtIL E4f5UO4swk0qjBkqUyaxRq5OIaqELYVYjEhUGn19CEONcqRJiZ3lC7vv7BLxqyb7u8/3 rZnC/0Xmpvu1f/+icviFbRfDsDYS6IcgMWA0SIdQhTXtOjMy8KjaOt/uQ1eYvj1dQx5M ZSVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775835923; x=1776440723; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=92qdXREBVwsG+a0SGoPjpWEPYqqewbVtYm4T62FIQ3Y=; b=lvLgOYPRH2dHDvxxxj7CYFWCv1ZnSRpAozYnrDtk05Gd1Q8/NpK/z7nGatjMCmwi6C EYeuFE9K6pbgxmK8Ev6bw7YXC+sso7UHPvvzgsaJtaMS1584d5bVUpUlPlsy3uY7cxzd l8GWbmUHjoS+e9FSOtY+pfMGoBT0uDIhITLQaKwbvG2pTzvPYjmOIWE5qysQuNaRHpJm kPoC9ODNqFJtcVXm1hro4NCEq/c0ywDevV5AFpENmhC8/WpibKQDif6Nb+VnxqC1rO2d bfc/ipYJpG4gvxAm31dBtVIjp2yE3wrLvtQiEMt7nug2mOe1ZdhlTuormVblyBA1bSeE tBXg== X-Gm-Message-State: AOJu0YwAtqSWnkdFRkeb8OAXg5RYirMg4UfM1MmDpeizpAAa37+c6aSq 2PCNQVjNAk52xfllxEYcgxmOjaiATlqYkNhPiDrj6wjayiE2a68VHOTm8KJaRQ== X-Gm-Gg: AeBDies/dmz7DqYl1Hwd942MeSQylK34PbygMNuFM0vuHTsmP1JnNFfz/hqDQipsapp 6DOuzaIg91e2IgSC9SFeWCDAn4aDhok7iYLjIyFUAN3S9ngJyVzeGxn9XSE0VPypzftMrNQHr2T alOOnufkHlBERTjKTAZXGRxrmN1Edt85jzbJd8JZ2mK1RGLudR4HpB5+IgJrhj01n6JpJBXq+5x yAdqcLbYwyKKlfeFHMkVnvyl62LkLHEyp5mPKmIY7aTveHYZU30gxdUN0VBVbB1l0w4uJ5z1Ua1 GHxEisAofPVeD/X5BKlo4t0ao7AJ5fyAWOMsD4eXyFGcSXqNOC5PzwjW4KXHkHRsdO31lxZuClK 2x+zwLVovmecKAuRDopcCYAoV2SE8X1c44+Xd8EomexlkCdBVZbh1D4fVZ4g9dAFu6rxjmq0gIU aaLFj+4mqAAnu6EtXAuxoZTvEHwdmBq88S6BBHlYiJGfOZeyH40aAUvnSKrRNDEaEt0A== X-Received: by 2002:a05:600d:d:b0:485:ae14:8191 with SMTP id 5b1f17b1804b1-488d67b8da2mr38326035e9.5.1775835922606; Fri, 10 Apr 2026 08:45:22 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] xen/riscv: allow Xen to use SSTC while hiding it from guests Date: Fri, 10 Apr 2026 17:45:12 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1775835923-41914C9A-FA4B47EF/10/73395122804 X-purgate-type: spam X-purgate-size: 13274 OpenSBI currently does not advertise the SSTC extension via the device tree, so if SSTC support is detected by Xen the riscv_isa bitmap is updated manually. Furthermore, removing the "sstc" string from riscv,isa is not a reliable way to disable SSTC, because OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. Note: clearing RISCV_ISA_EXT_sstc from the DTS riscv,isa property is deferred to a follow-up patch. Also, the corresponding HENVCFG bit is not set so guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. Drop sbi_set_timer() as it is more than enough to have only introduced set_xen_timer(). Drop "SBI v0.2 TIME extension detected" message to avoid confusion which set timer function is really used. Signed-off-by: Oleksii Kurochko --- CI tests: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2437772678 Also, I've manually ran QEMU with SSTC=on/off and built Xen with a newer RISC-V compileer (in comparison with the version used by CI's docker container) to verify CONFIG_CC_HAS_ASM_GOTO_OUTPUT branch inside csr_read_safe(). --- Changes in v3: - Reword print message when SSTC extension is detected. - s/__clear_bit/__set_bit() for the case when SSTC is detected in riscv_fill_hwcap(). Update also the comment above __set_bit(). - Drop BUG_ON()s in vtimer.c. - s/printk/dprintk for the message: SSTC detected... - Drop sbi_set_timer global variable, it is enough just to have set_xen_timer. - As we set bit in riscv_isa bitmap there is no need to use csr_read_safe(CSR_STIMECMP) second time. - Move init of CSR_VSTIMECMP in preinit_xen_time as it looks more correct place. - Update the commit message. --- Changes in v2: - Minor style fixes. - Drop from vcpu_csr_init() setting of SSTC bit in HENVCFG register. Add it back when SSTC for guests will be available. - Add static to set_xen_timer function pointer. - Refactor sstc_set_xen_timer(). - s/csr_allowed_read/csr_read_safe() --- xen/arch/riscv/cpufeature.c | 18 ++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/riscv_encoding.h | 2 + xen/arch/riscv/include/asm/sbi.h | 18 -------- xen/arch/riscv/include/asm/time.h | 3 ++ xen/arch/riscv/sbi.c | 29 ++++++++++--- xen/arch/riscv/time.c | 48 ++++++++++++++------- xen/arch/riscv/vtimer.c | 1 + 8 files changed, 81 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..92235fdfd5ab 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include #include +#include #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_ext[] = { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount = ARRAY_SIZE(required_extensions); bool all_extns_available = true; + unsigned long tmp; riscv_fill_hwcap_from_isa_string(); @@ -495,6 +498,21 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + dprintk(XENLOG_DEBUG, + "SSTC detected; supported for Xen use, but not for guests\n"); + + /* + * As there is no any guarantee that SSTC will be added to riscv,isa + * property by OpenSBI(it doesn't add it now) or whatever ran before + * Xen, it is needed to set this bit manually. + * + * Guest isolation is maintained by not setting ENVCFG_STCE in henvcfg. + */ + __set_bit(RISCV_ISA_EXT_sstc, riscv_isa); + } + for ( i = 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext = required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/include/asm/riscv_encoding.h index dd15731a86fa..d0d60ba15e62 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -396,6 +396,8 @@ #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ #define CSR_HVIEN 0x608 diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/sbi.h index ed7af200288f..1952868e963c 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,7 +13,6 @@ #define ASM__RISCV__SBI_H #include -#include /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -139,23 +138,6 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); -/* - * Programs the clock for next event at (or after) stime_value. stime_value is - * in absolute time. This function must clear the pending timer interrupt bit - * as well. - * - * If the supervisor wishes to clear the timer interrupt without scheduling the - * next timer event, it can either request a timer interrupt infinitely far - * into the future (i.e., (uint64_t)-1), or it can instead mask the timer - * interrupt by clearing sie.STIE CSR bit. - * - * The stime_value parameter represents absolute time measured in ticks. - * - * This SBI call returns 0 upon success or an implementation specific negative - * error code. - */ -extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); - /* * Initialize SBI library * diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h index be3875b9984e..4d68900151a7 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -4,6 +4,7 @@ #include #include +#include #include @@ -26,6 +27,8 @@ static inline cycles_t get_cycles(void) void preinit_xen_time(void); +extern int (* __ro_after_init set_xen_timer)(uint64_t deadline); + #endif /* ASM__RISCV__TIME_H */ /* diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index b4a7ae6940c1..3576e26033a5 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -22,6 +22,7 @@ #include #include +#include static unsigned long __ro_after_init sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; @@ -249,6 +250,21 @@ static int (* __ro_after_init sbi_rfence)(unsigned long fid, unsigned long arg4, unsigned long arg5); +/* + * Programs the clock for next event at (or after) stime_value. stime_value is + * in absolute time. This function must clear the pending timer interrupt bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without scheduling the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific negative + * error code. + */ static int cf_check sbi_set_timer_v02(uint64_t stime_value) { struct sbiret ret; @@ -264,6 +280,10 @@ static int cf_check sbi_set_timer_v02(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } +/* + * Legacy SBI v0.1 SET_TIMER; functionally equivalent to sbi_set_timer_v02 + * from Xen's perspective. + */ static int cf_check sbi_set_timer_v01(uint64_t stime_value) { struct sbiret ret; @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; - int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -360,10 +378,9 @@ int __init sbi_init(void) } if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) - { - sbi_set_timer = sbi_set_timer_v02; - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); - } + set_xen_timer = sbi_set_timer_v02; + else + set_xen_timer = sbi_set_timer_v01; } else panic("Ooops. SBI spec version 0.1 detected. Need to add support"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 7efa76fdbcb1..80f0e9ddae6a 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,12 +7,24 @@ #include #include +#include #include -#include unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write(CSR_STIMECMP, deadline); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_STIMECMPH, deadline >> 32); +#endif + + return 0; +} + +int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks = get_cycles() - boot_clock_cycles; @@ -61,20 +73,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <= now ) return 0; - /* - * TODO: When the SSTC extension is supported, it would be preferable to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementation. - * For example, it is not ideal to panic() if sbi_set_timer() returns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc = sbi_set_timer(deadline)) ) + if ( (rc = set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); /* Enable timer interrupt */ @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) panic("%s: ACPI isn't supported\n", __func__); boot_clock_cycles = get_cycles(); + + /* set_xen_timer must have been set by sbi_init() already */ + ASSERT(set_xen_timer); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) + { + set_xen_timer = sstc_set_xen_timer; + + /* + * A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CSR. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + */ + csr_write(CSR_VSTIMECMP, ULONG_MAX); +#ifdef CONFIG_RISCV_32 + csr_write(CSR_VSTIMECMPH, ULONG_MAX); +#endif + } } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..d5a8dfcb2edb 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include +#include #include static void vtimer_expired(void *data) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279414.1563842 (Exim 4.92) (envelope-from ) id 1wBECQ-00070B-PV; Fri, 10 Apr 2026 15:55:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279414.1563842; Fri, 10 Apr 2026 15:55:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECQ-000702-KQ; Fri, 10 Apr 2026 15:55:14 +0000 Received: by outflank-mailman (input) for mailman id 1279414; Fri, 10 Apr 2026 15:55:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECO-0006mB-Ch for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECM-00Cwd5-71 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:11 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5e-bab6-0a2a0a5309dd-0a2a450abe1c-6 for ; Fri, 10 Apr 2026 17:55:11 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d5f-ee98-0a2a450a0019-d1558033c175-3 for ; Fri, 10 Apr 2026 17:55:11 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4838c15e3cbso19690445e9.3 for ; Fri, 10 Apr 2026 08:55:11 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Fri, 10 Apr 2026 08:55:10 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 01/12] xen/riscv: implement get_page_from_gfn() Date: Fri, 10 Apr 2026 17:54:47 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1775836511-C58140B1-46DD9E41/10/73395122804 X-purgate-type: spam X-purgate-size: 3227 The function is implemented out-of-line rather than as a static inline, to avoid header ordering issues where struct domain is incomplete when asm/p2m.h is included, leading to build failures: In file included from ./arch/riscv/include/asm/domain.h:10, from ./include/xen/domain.h:16, from ./include/xen/sched.h:11, from ./include/xen/event.h:12, from common/cpu.c:3: ./arch/riscv/include/asm/p2m.h: In function 'get_page_from_gfn': ./arch/riscv/include/asm/p2m.h:50:33: error: invalid use of undefined type 'struct domain' 50 | #define p2m_get_hostp2m(d) (&(d)->arch.p2m) | ^~ ./arch/riscv/include/asm/p2m.h:180:38: note: in expansion of macro 'p2m_get_hostp2m' 180 | return p2m_get_page_from_gfn(p2m_get_hostp2m(d), _gfn(gfn), t); | ^~~~~~~~~~~~~~~ make[2]: *** [Rules.mk:253: common/cpu.o] Error 1 make[1]: *** [build.mk:72: common] Error 2 make: *** [Makefile:623: xen] Error 2 Signed-off-by: Oleksii Kurochko --- Changes in v3: - As nothing is called get_page_from_gfn() for system domains, leave only handling of not system domains. --- Changes in v2: - Align implemntation with Arm's get_page_from_gfn(). - Update the first comment about DOMID_XEN to mention that isn't "normal" domain instead of no-autotranslated. - Drop footer after commit message. --- xen/arch/riscv/include/asm/p2m.h | 8 ++------ xen/arch/riscv/p2m.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 60f27f9b347e..54ea67990f06 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -164,12 +164,8 @@ typedef unsigned int p2m_query_t; #define P2M_ALLOC (1u<<0) /* Populate PoD and paged-out entries */ #define P2M_UNSHARE (1u<<1) /* Break CoW sharing */ -static inline struct page_info *get_page_from_gfn( - struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q) -{ - BUG_ON("unimplemented"); - return NULL; -} +struct page_info *get_page_from_gfn(struct domain *d, unsigned long gfn, + p2m_type_t *t, p2m_query_t q); static inline void memory_type_changed(struct domain *d) { diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 89e5db606fc8..d63697c89a1a 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -1534,3 +1534,16 @@ void p2m_handle_vmenter(void) * won't be reused until need_flush is set to true. */ } + +struct page_info *get_page_from_gfn(struct domain *d, unsigned long gfn, + p2m_type_t *t, p2m_query_t q) +{ + /* + * system domains are domains which doesn't have p2m translation tables, + * so they can't use p2m_get_page_from_gfn() and extra care should be + * done for them. + */ + ASSERT(!is_system_domain(d)); + + return p2m_get_page_from_gfn(p2m_get_hostp2m(d), _gfn(gfn), t); +} -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279413.1563833 (Exim 4.92) (envelope-from ) id 1wBECO-0006mJ-Ds; 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Generally it is indepenent patch series from [1] but depends on which patches will go first it could be some merge conflicts. [1] https://lore.kernel.org/xen-devel/eba232ac5a338332ddedc2cb084e0c04ee8744c2.1775835741.git.oleksii.kurochko@gmail.com/T/#u CI tests: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2444698148 --- Changes in v3: - Address the comments from ML. --- Changes in v2: - Address the comments from ML. - Introduce some new patches to make dom0less solution more architecture indepenent from terminology point of view. - Minor fixes. --- Oleksii Kurochko (12): xen/riscv: implement get_page_from_gfn() xen: fix len type for guest copy functions xen/riscv: implement copy_to_guest_phys() xen/dom0less: rename kernel_zimage_probe() to kernel_image_probe() xen/riscv: add kernel loading support xen: move declaration of fw_unreserved_regions() to common header xen: introduce domain-layout.h with common domain_use_host_layout() xen/riscv: rework G-stage mode handling xen: rename p2m_ipa_bits to p2m_gpa_bits xen/riscv: introduce p2m_gpa_bits xen/riscv: add definition of guest RAM banks xen/riscv: enable DOMAIN_BUILD_HELPERS xen/arch/arm/domain_build.c | 1 + xen/arch/arm/guestcopy.c | 6 +- xen/arch/arm/include/asm/domain.h | 14 -- xen/arch/arm/include/asm/guest_access.h | 2 +- xen/arch/arm/include/asm/p2m.h | 2 + xen/arch/arm/include/asm/setup.h | 3 - xen/arch/arm/kernel.c | 48 ++--- xen/arch/arm/vgic-v3.c | 1 + xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 3 + xen/arch/riscv/dom0less-build.c | 30 +++ xen/arch/riscv/guestcopy.c | 116 +++++++++++ xen/arch/riscv/include/asm/config.h | 13 ++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/include/asm/guest-layout.h | 23 +++ xen/arch/riscv/include/asm/guest_access.h | 7 + xen/arch/riscv/include/asm/p2m.h | 29 +-- xen/arch/riscv/kernel.c | 230 ++++++++++++++++++++++ xen/arch/riscv/p2m.c | 141 +++++++++---- xen/arch/riscv/vmid.c | 2 +- xen/common/device-tree/domain-build.c | 3 +- xen/common/device-tree/kernel.c | 2 +- xen/include/public/arch-riscv.h | 5 + xen/include/xen/bootinfo.h | 4 + xen/include/xen/domain-layout.h | 28 +++ xen/include/xen/fdt-domain-build.h | 2 +- xen/include/xen/fdt-kernel.h | 15 +- 27 files changed, 631 insertions(+), 101 deletions(-) create mode 100644 xen/arch/riscv/dom0less-build.c create mode 100644 xen/arch/riscv/guestcopy.c create mode 100644 xen/arch/riscv/include/asm/guest-layout.h create mode 100644 xen/arch/riscv/kernel.c create mode 100644 xen/include/xen/domain-layout.h -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279417.1563860 (Exim 4.92) (envelope-from ) id 1wBECS-0007Rt-8I; Fri, 10 Apr 2026 15:55:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279417.1563860; Fri, 10 Apr 2026 15:55:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECS-0007Rm-3W; Fri, 10 Apr 2026 15:55:16 +0000 Received: by outflank-mailman (input) for mailman id 1279417; Fri, 10 Apr 2026 15:55:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECQ-0006zi-FM for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECP-00DRdD-RY for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:13 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5f-2eae-0a2a0a5409dd-0a2a4506e8bc-12 for ; Fri, 10 Apr 2026 17:55:13 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d61-0df0-0a2a45060019-d1558035b098-3 for ; Fri, 10 Apr 2026 17:55:13 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-483487335c2so24236935e9.2 for ; Fri, 10 Apr 2026 08:55:13 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5b3c597sm78285605e9.12.2026.04.10.08.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 08:55:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775836513; x=1776441313; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SFYf07Rw6EEigOnFsAjQXEHqS/FUbbC2HqDC1ySUOAc=; b=N6OCPPryxPDH7i+Guk+LEXdipKtQX3Sc+ngp9MAxVonaOmZBiy3xMVAs+TfcFSzJfO hQ4oTcZGx/YbJXlzUU5sy2wuwVWIQFUOEL1G3zHWLLCGgW/VvdgoA83NMbAsT19YxXzd lodJW3SfrYsJUtzSICLQWqTAVtGzHu4YYx7vmZMf8Jj6jVD6xuAs4lVk57RuT1HBZ2OD UmG8936YUFyVjbSae40yY90IlOyGJ0Wh7gZnYdMuX22eCo8bbWj7yg7USe8ZvqY7oC9h pWTc2XiH8w/CNmDnqPw9ypQJuLa2ZuiXJ+P1+h5hvPVq4CI4dPhZKoswbJxkzjjNjbBD EWpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775836513; x=1776441313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SFYf07Rw6EEigOnFsAjQXEHqS/FUbbC2HqDC1ySUOAc=; b=Qthazv9dAehQ2XuRWmLRNojclxs2rJMfBkuJ505hFza9KsPcNoOZYs8b/xi+C+Rs34 xSNumr3Y0QJUqH4d0ZImjNddsn8ODFExDWmAqLXZpBDFgsMCt1Mu/QO9+tViXzfMQYwu p5acvo03a49DPC/RqOSTYPBj/9XdOe3ilYTyP+JxEafysLj6RznEltZTKK+4FInjLF9k cS9v64PFGBNJ/kAAJYDqUxL7ioII5QE48HGpveEe13VfwvkH6bmzZbaICdQffLWdc8hB 5ADXDfDmB/DSJaLEZZRQFGgXmdJml9NGPz262IdwINW88WHNaD5JW47yQK3xnEquQvdD S+3Q== X-Gm-Message-State: AOJu0YyEcnJ/acFY8B2AR2VRsUV3WGw/BF2IJ8wK9IjhAFAwEQ33R8KU 1OFUiprNJX6f+efKk0IKtATOBRXSG/puKgJMrIoN23CL/FfJT4je5xCaFozkHA== X-Gm-Gg: AeBDieskIljIoEUIFJtGtskyrFL50/IF/jouza3zJUmNW503GalNyyuIZuV5rLJouwE Jlw+H7zptksKpCW3ffCnSBDj5n2mUmDvZbRARpgxXkk5/vl7PVai4MV1PeqJE7TNoTGjd6Ihx+K MY/QOP2Ysktgo5ffAKPkTHz9IjPi7JaJagD2qPLLtuftj78x/x0BWeEuWNg4dISss+HhQzOzU16 0WlETY1FychPAXoKLAndVq4gRDYIdqzbZowpG6Pr0lMIuqH9ycczUzkndYPn43WXFPrJq1QPuUO cX+mUJcG6wuRX3hhOnQTy9yZ3kTZwip/MZoN8trwByrNLVQFSMiG25tAZMpohJas9EtMZV7Ib+S EPjzty5i+JaxytqMGiTK5HcdEF76GXKQyqyBC18YGsMcd6poZFzgCqV/RErtySGPpxEs6+6YOGO W913ibbR7HYdj32lHhb5aHo1XgzKu7Rr+IBGZWDGdlzIY20VjaMaRayATDAAGYvVEBrg== X-Received: by 2002:a05:600c:45cf:b0:483:8062:b2f with SMTP id 5b1f17b1804b1-488d67b8dddmr46630205e9.6.1775836513001; Fri, 10 Apr 2026 08:55:13 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 03/12] xen/riscv: implement copy_to_guest_phys() Date: Fri, 10 Apr 2026 17:54:49 +0200 Message-ID: <265d9fe7c0ff46c1c969156c889e133593d57fff.1775836193.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1775836513-5FF3D3D8-2F861969/10/73395122804 X-purgate-type: spam X-purgate-size: 6368 Introduce copy_to_guest_phys() for RISC-V, based on the Arm implementation. Add a generic copy_guest() helper for copying to and from guest physical (and potentially virtual addresses in the future), and implement translate_get_page() to translate a guest physical address into a struct page_info via the domain p2m. Compared to the Arm code: - Drop COPY_flush_dcache(), as no such use cases exist on RISC-V. - Do not implement the linear mapping case, which is currently unused. - Use PAGE_OFFSET() to initialize the local offset variable in copy_guest(). Signed-off-by: Oleksii Kurochko --- Changes in v3: - s/if (page == NULL)/if ( !page ). - Drop " - offset" for unmap_domain_page() inside copy_guest() function. unmap_domain_page() is expected to mask (or something similar) the page offset bits. - Change some types for functions as copy_to_guest_phys_cb function pointer prototype was changed too in the prev. commit. --- Changes in v2: - Use BIT() instead of open-coding. - Rename COPY_ipa to COPY_gpa. - Rename COPY_linear to COPY_gva. - Use BUG_ON(linear) instead if (lineer) + BUG_ON. - Rename arg liner to gva for translate_get_page(). - Update translate_get_page() to properly handling write argument. - Return unsigned int for copy_guest() and copy_to_guest_phys() as len function parameter is only 'unsigned int'. - Reformat function arguments for alignment --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/guestcopy.c | 116 ++++++++++++++++++++++ xen/arch/riscv/include/asm/guest_access.h | 7 ++ 3 files changed, 124 insertions(+) create mode 100644 xen/arch/riscv/guestcopy.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 04f02ad89cba..cfc3fdf7d208 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += domain.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += extable.o +obj-y += guestcopy.o obj-y += imsic.o obj-y += intc.o obj-y += irq.o diff --git a/xen/arch/riscv/guestcopy.c b/xen/arch/riscv/guestcopy.c new file mode 100644 index 000000000000..55a2d6597621 --- /dev/null +++ b/xen/arch/riscv/guestcopy.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include + +#define COPY_from_guest 0U +#define COPY_to_guest BIT(0, U) +#define COPY_gpa 0U +#define COPY_gva BIT(1, U) + +typedef union +{ + struct + { + struct vcpu *v; + } gva; + + struct + { + struct domain *d; + } gpa; +} copy_info_t; + +#define GVA_INFO(vcpu) ((copy_info_t) { .gva = { vcpu } }) +#define GPA_INFO(domain) ((copy_info_t) { .gpa = { domain } }) + +static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, + bool gva, bool write) +{ + p2m_type_t p2mt; + struct page_info *page; + + /* + * Not implemented yet. + * + * If gva == true, the operation will likely require a struct vcpu + * rather than just a struct domain. For this reason copy_info_t is + * already passed here instead of only struct domain. + */ + BUG_ON(gva); + + page = get_page_from_gfn(info.gpa.d, paddr_to_pfn(addr), &p2mt, P2M_ALLOC); + + if ( !page ) + return NULL; + + if ( write ? p2mt != p2m_ram_rw : !p2m_is_ram(p2mt) ) + { + put_page(page); + return NULL; + } + + return page; +} + +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, + copy_info_t info, unsigned int flags) +{ + unsigned int offset = PAGE_OFFSET(addr); + + BUILD_BUG_ON((sizeof(addr)) < sizeof(vaddr_t)); + BUILD_BUG_ON((sizeof(addr)) < sizeof(paddr_t)); + + while ( len ) + { + void *p; + unsigned long size = min_t(unsigned long, len, PAGE_SIZE - offset); + struct page_info *page; + + page = translate_get_page(info, addr, flags & COPY_gva, + flags & COPY_to_guest); + if ( !page ) + return len; + + p = __map_domain_page(page); + p += offset; + if ( flags & COPY_to_guest ) + { + /* + * buf will be NULL when the caller request to zero the + * guest memory. + */ + if ( buf ) + memcpy(p, buf, size); + else + memset(p, 0, size); + } + else + memcpy(buf, p, size); + + unmap_domain_page(p); + put_page(page); + len -= size; + buf += size; + addr += size; + + /* + * After the first iteration, guest virtual address is correctly + * aligned to PAGE_SIZE. + */ + offset = 0; + } + + return 0; +} + +unsigned long copy_to_guest_phys(struct domain *d, paddr_t gpa, void *buf, + unsigned long len) +{ + return copy_guest(buf, gpa, len, GPA_INFO(d), + COPY_to_guest | COPY_gpa); +} diff --git a/xen/arch/riscv/include/asm/guest_access.h b/xen/arch/riscv/include/asm/guest_access.h index 7cd51fbbdead..8d679319ded0 100644 --- a/xen/arch/riscv/include/asm/guest_access.h +++ b/xen/arch/riscv/include/asm/guest_access.h @@ -2,6 +2,10 @@ #ifndef ASM__RISCV__GUEST_ACCESS_H #define ASM__RISCV__GUEST_ACCESS_H +#include + +struct domain; + unsigned long raw_copy_to_guest(void *to, const void *from, unsigned len); unsigned long raw_copy_from_guest(void *to, const void *from, unsigned len); unsigned long raw_clear_guest(void *to, unsigned int len); @@ -18,6 +22,9 @@ unsigned long raw_clear_guest(void *to, unsigned int len); #define guest_handle_okay(hnd, nr) (1) #define guest_handle_subrange_okay(hnd, first, last) (1) +unsigned long copy_to_guest_phys(struct domain *d, paddr_t gpa, void *buf, + unsigned long len); + #endif /* ASM__RISCV__GUEST_ACCESS_H */ /* * Local variables: -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279415.1563848 (Exim 4.92) (envelope-from ) id 1wBECR-00073M-1v; Fri, 10 Apr 2026 15:55:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279415.1563848; Fri, 10 Apr 2026 15:55:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECQ-00072l-Sd; Fri, 10 Apr 2026 15:55:14 +0000 Received: by outflank-mailman (input) for mailman id 1279415; Fri, 10 Apr 2026 15:55:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECP-0006xl-DC for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECN-00Cwd5-7o for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:12 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d56-bab6-0a2a0a5309dd-0a2a450cb636-16 for ; Fri, 10 Apr 2026 17:55:12 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d60-f40c-0a2a450c0019-d1558032cce8-3 for ; Fri, 10 Apr 2026 17:55:12 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-488971db0fdso21891455e9.0 for ; Fri, 10 Apr 2026 08:55:12 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5b3c597sm78285605e9.12.2026.04.10.08.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 08:55:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775836512; x=1776441312; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kn185YypiDfOEWixrDVwqtteBm6bdiTVXiEGngdxI1A=; b=WMjkiq7nWY1QPOmYYFMstz0ihWMUut040lCHgRvWX7Tsgbf+SA4XlDOQ42/wqAq9Iu B32nDvUR48VyZ92ve75jF1EoVkvNvuVtnL02crGza3F7k/ZmLmz560aT7qs1FKZua5V5 YujsCIdvEZkLRt0p/gTHvZzPJjQ74ZbkvwbZjDoBpkmpJjXk71TQ5YVpj+LLVt7pDJXh L1S2wKC86vySSdioa07VX+WmyJJw9z87RoaIGBWkbsD5pVsxNwBA1OXn/32H7ARUP0Pn gjt8ahAJzyW6qpmT31XtPYrOQajiPE9uHLJMbrO5M4/iccsVkqbQlNk355q7hxUk3/gl VSaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775836512; x=1776441312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Kn185YypiDfOEWixrDVwqtteBm6bdiTVXiEGngdxI1A=; b=ejsvwEFcLtaUJrlaa9Gx3JOUIB1MyUqDJ51erhVeuY2IMp9yHMC7gu4VBkWMUvgW3q IMU1+7qhD/ZjESqZc4vPQzELTrIIL44YZzb/xREoNWKrTwYWa9irHbJ2DJkFBd3a8qxK HS7Qo5KxRc4Ik7nurrgQW5Ftj7MEfSJT3U9FG49zofEpfXbYD+cAiUpqOmm4b8znB7CM CHDVp6I5F4hT3+dNw3wzSSkju26LaRx0huy7KJlezzm6nzMSUfcgyRtajk/3dD6KRU4N SoWGFgoYz89caXx3P4Fc7aUi8KAdeUwGIFzNYy4FHsW970Hu61+BVFqLAug3B50x4Vch 1bUg== X-Gm-Message-State: AOJu0YxwX8c2vSUslPaS9fZCpO6zBOklusSozm9UpBm2DP4pByEW/Bs5 oNXTsj/ETrY3kV4NSEEvPnv/u+TX/y9O28F5QXEzvgil5NjY0CYG1siRGbY3ag== X-Gm-Gg: AeBDiesf5UjMtT6c04JsHKu4o67YBDjOBWcqT8RcUpBG+sAoB1+xnQB9ezHckSaI/jZ nxh5jjD0/ww0WrpL5lgVziz5qjS5JN2F+3IPU+n7mxAcrOP6lLlWIKxhagg7Pwhj+qNCMahCdnd Ekl7cG9D5n+zg6G/ahavx1nffhAKY8ZSViv02O1xP5n0fJlLjXu2xAF+T6asYqyJjKbshAv9Za6 7OVMGXeQ2xJUVKjaaoO+pQFznqU5Cdxdq5HxhfVKy7EzbHKS23dbCUUtLlrR9XTksFtg1iujHGV pf69ByYtINBTJaLGTJymw7deJda94a0btiiGRyvIVLuZDZSkjkjh3Mb0BIf4VBgrC4xekrLdEb0 BVwHEFJNakIJI445dwcIIBUd3kbgTJtHnC05QiNgHf083e5WBlQszr+apo4+D1b6lZQPGBM1AY1 P3LGS9uZhiwAhe8AFoBw0zlE3yfvSELOFY0A3I0sdvVHGG2kOv/S4FATACA+Tjw9dv9A== X-Received: by 2002:a05:600c:5249:b0:485:7f02:afd5 with SMTP id 5b1f17b1804b1-488d680079bmr45339755e9.13.1775836511858; Fri, 10 Apr 2026 08:55:11 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 02/12] xen: fix len type for guest copy functions Date: Fri, 10 Apr 2026 17:54:48 +0200 Message-ID: <9154aea41a11bc0ba95ad15c217db79d029dd119.1775836193.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775836512-8254FA3D-75CFC99F/10/73395122804 X-purgate-type: spam X-purgate-size: 4947 Widen the len argument of copy_to_guest_phys_flush_dcache() and the copy_to_guest_phys_cb typedef from unsigned int to unsigned long, as the function can be used to copy large blobs such as the initrd which may exceed 4GB. Update the internal copy_guest() len argument to unsigned long accordingly. Change the type for local variable size in copy_guest() to avoid compilation error because of type mismatch. raw_* wrappers above copy_guest() keep returning unsigned long to avoid type narrowing; it is not an issue for raw_*'s len argument to remain 'unsigned int' since the assignment to copy_guest()'s wider unsigned long parameter is safe and there is no raw_* users who are using a value bigger than what can fit into 'unsigned int'. Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in v3: - Correct the declaration of copy_to_guest_phys_cb() instead of return 'unsigned int' to be in sync with len argument, the type of len argument is changed on 'unsigned long' as initrd could be pretty big and also its size is stroed in 'paddr_t' which is 'unsigned long'. - Update copy_guest() prototype to avoid trancation bug for len argument. - Revert prototype changes for raw_* wrappers above copy_guest() as they should keep returning unsigned long to avoid type narrowing; it is not an issue for raw_*'s len argument to remain 'unsigned int' since the assignment to copy_guest()'s wider unsigned long parameter is safe. - Change the type for local variable size in copy_guest() to avoid compilation error because of type mismatch. - Add Reported-by: Jan Beulich --- Changes in v2: - New patch. --- xen/arch/arm/guestcopy.c | 6 +++--- xen/arch/arm/include/asm/guest_access.h | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/guestcopy.c b/xen/arch/arm/guestcopy.c index fdb06422b8e9..ca0f72a80bff 100644 --- a/xen/arch/arm/guestcopy.c +++ b/xen/arch/arm/guestcopy.c @@ -53,7 +53,7 @@ static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, return page; } -static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, copy_info_t info, unsigned int flags) { /* XXX needs to handle faults */ @@ -65,7 +65,7 @@ static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, while ( len ) { void *p; - unsigned int size = min(len, (unsigned int)PAGE_SIZE - offset); + unsigned long size = min_t(unsigned long, len, PAGE_SIZE - offset); struct page_info *page; page = translate_get_page(info, addr, flags & COPY_linear, @@ -136,7 +136,7 @@ unsigned long raw_copy_from_guest(void *to, const void __user *from, unsigned long copy_to_guest_phys_flush_dcache(struct domain *d, paddr_t gpa, void *buf, - unsigned int len) + unsigned long len) { return copy_guest(buf, gpa, len, GPA_INFO(d), COPY_to_guest | COPY_ipa | COPY_flush_dcache); diff --git a/xen/arch/arm/include/asm/guest_access.h b/xen/arch/arm/include/asm/guest_access.h index 18c88b70d7ec..c13cbec55b65 100644 --- a/xen/arch/arm/include/asm/guest_access.h +++ b/xen/arch/arm/include/asm/guest_access.h @@ -14,7 +14,7 @@ unsigned long raw_clear_guest(void *to, unsigned int len); unsigned long copy_to_guest_phys_flush_dcache(struct domain *d, paddr_t gpa, void *buf, - unsigned int len); + unsigned long len); int access_guest_memory_by_gpa(struct domain *d, paddr_t gpa, void *buf, uint32_t size, bool is_write); diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 886a85381651..1d9e77df0eb3 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -47,7 +47,7 @@ static inline int get_allocation_size(paddr_t size) typedef unsigned long (*copy_to_guest_phys_cb)(struct domain *d, paddr_t gpa, void *buf, - unsigned int len); + unsigned long len); void initrd_load(struct kernel_info *kinfo, copy_to_guest_phys_cb cb); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279418.1563868 (Exim 4.92) (envelope-from ) id 1wBECT-0007hP-Ka; Fri, 10 Apr 2026 15:55:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279418.1563868; Fri, 10 Apr 2026 15:55:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECT-0007hE-HA; Fri, 10 Apr 2026 15:55:17 +0000 Received: by outflank-mailman (input) for mailman id 1279418; Fri, 10 Apr 2026 15:55:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECR-0007EN-Iz for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECP-00Cwd5-DQ for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:14 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d56-bab6-0a2a0a5309dd-0a2a450cb636-26 for ; Fri, 10 Apr 2026 17:55:14 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d62-f40c-0a2a450c0019-d155802dc8a2-3 for ; Fri, 10 Apr 2026 17:55:14 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-48897fd88ebso23326085e9.2 for ; Fri, 10 Apr 2026 08:55:14 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5b3c597sm78285605e9.12.2026.04.10.08.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 08:55:13 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775836514; x=1776441314; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sTRi4YH+C2jL1DPdQVnyL1+s27z+ZRb1KNlQ9e7rLKA=; b=s/ADolDC1igUBrDPOfb0FyBbtLgF20pDCtb70tfFOXxjW34DJUjmeIpWcZUCgaQGgh Y5qPFZp4pfhZyNi7/+GCs5Pdu1w3LFm2W9SG/rg6yAPNxQTd6AOHb7RxCuOcbgCIfryk 1k1fCeVRwTzybMTvNOVzzs08ju0cOG/k53w/FqY9KgCNqYF9LPtaT4PhBRvBVPdlpyRC ZDckx2a+gjiHdbhPfbuu4uDywDtuLgvn5fc7SQAN70RKuUde2GreZYLiUWX3EcfuLMWu d9ECxqwsJM1a3tH/QtOxMbmtFc5aIaUCsDy92SGc+UWDKs9VYEWBPCAkUtVXqksZj3go YHqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775836514; x=1776441314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sTRi4YH+C2jL1DPdQVnyL1+s27z+ZRb1KNlQ9e7rLKA=; b=QSmsXq6xlY8fO41BZfN/YyvJ03QAO8P7sd4t80ENciSQxkBUtdX2cfLaw2Ue6VvDpW IJw5AcKy9+XsGA5uf+bTz90uX7fzhxAUMLge8CdtUY+rH5LGi4Ein+hY+F4HT4wESuaZ pqcVr0pMmmx/pJFS68ZSzwW2sDAjVgtAano4C11vQs+IarZj6+hgisFv+kqaNFswumj9 GljOzpmQXCCGSQyCHFWwFSmh0RdrTGGkEsyGSStD/bivqZyCtj2IQph8bjHpa/CjV/+y TKIEbkAwqiOH0rFsR5Z384JgZ2tfgrvQM2yhfoajVvKkxfGnoDzEOBoAgY+LTmbQ24UV QXWw== X-Gm-Message-State: AOJu0YxRgERfs3ZPJ9PfmGhzGap3LbvEgc0VEBz/hxJbVR9dZg6VvcDq nqWjmMUymYKGiaqrEPJYbmpiD62ki7AO0A+IOpuYnkFDFCyLY4DCNLGFbvawqQ== X-Gm-Gg: AeBDieuspLs7cDOb9Xtz6o2VKI1yCFL0cGf9XyulyV4p1MkqiNrp4Cp6UJgh3V9N91T BvXbob6g3Sa+FGYu6cW4tOM5pj2+5laNO8wDOyrZtlCol3lZC+P5ic+Cbj4sT65/yGnTSW8fOys dmtT/ZCZiVVhENJmCerg9TR+P1Efhdr0S2tRo88J4Pyh7fkOShVNezr9/Z4foYknQu14j3IVIiX Y0x+0U+AvVh5IJDRow1lRc+P8Z3MdY+Y2jFlY3Goe4iTTsnyh49mngT9yk+LISZ9gdpne2MjYEM 8QaB7bODFzvzMf2l6xMqwAl8ZbjYrv6855W24T9v/rl0mAoOTBz9buKJ6izfDvuRA4V9Y06ECkq GKyhqE9Z+akUvCipjZousPEae5vmEflJACgzaQAm5sosjwoqx7TTJOzo1TUrNe7VY7BNvR8BJcw bYI3mpfVXF/Mwbzh9DI82ICqzKmd1lRaTsSYSbERrWK2BoRJhHShRDujRTWz3QGrQXREkptOvEv Fjn X-Received: by 2002:a05:600c:34cd:b0:487:575:5e1 with SMTP id 5b1f17b1804b1-488d68c2cb4mr48418635e9.24.1775836514072; Fri, 10 Apr 2026 08:55:14 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 04/12] xen/dom0less: rename kernel_zimage_probe() to kernel_image_probe() Date: Fri, 10 Apr 2026 17:54:50 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1775836514-FF547A3D-4A6AEDB5/10/73395122804 X-purgate-type: spam X-purgate-size: 7698 The helper kernel_zimage_probe() is referenced from common code (xen/common/device-tree/kernel.c), but its name is tied to the zImage format which is specific to Arm (from architectures supported by Xen). Other architectures supported by Xen, such as RISC-V, do not use the zImage format and instead rely on other kernel image types (e.g. Image or compressed Image variants: Image.gz, etc). Using "zimage" in the name is therefore misleading in architecture-independent code. Rename kernel_zimage_probe() to kernel_image_probe() and update the associated structure field from "zimage" to "image" to reflect that the code handles generic kernel images rather than the zImage format specifically. No functional change intended. Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in v3: - Nothing changed. Only rebase. --- Changes in v2: - new patch. --- xen/arch/arm/kernel.c | 48 ++++++++++++++++----------------- xen/common/device-tree/kernel.c | 2 +- xen/include/xen/fdt-kernel.h | 4 +-- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 7544fd50a20f..3c613cdb233f 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -101,8 +101,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) paddr_t load_addr; #ifdef CONFIG_ARM_64 - if ( (info->arch.type == DOMAIN_64BIT) && (info->zimage.start == 0) ) - return mem->bank[0].start + info->zimage.text_offset; + if ( (info->arch.type == DOMAIN_64BIT) && (info->image.start == 0) ) + return mem->bank[0].start + info->image.text_offset; #endif /* @@ -111,19 +111,19 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) * and above 32MiB. Load it as high as possible within these * constraints, while also avoiding the DTB. */ - if ( info->zimage.start == 0 ) + if ( info->image.start == 0 ) { paddr_t load_end; load_end = mem->bank[0].start + mem->bank[0].size; load_end = MIN(mem->bank[0].start + MB(128), load_end); - load_addr = load_end - info->zimage.len; + load_addr = load_end - info->image.len; /* Align to 2MB */ load_addr &= ~((2 << 20) - 1); } else - load_addr = info->zimage.start; + load_addr = info->image.start; return load_addr; } @@ -131,8 +131,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) static void __init kernel_zimage_load(struct kernel_info *info) { paddr_t load_addr = kernel_zimage_place(info); - paddr_t paddr = info->zimage.kernel_addr; - paddr_t len = info->zimage.len; + paddr_t paddr = info->image.kernel_addr; + paddr_t len = info->image.len; void *kernel; int rc; @@ -215,7 +215,7 @@ int __init kernel_uimage_probe(struct kernel_info *info, return -EOPNOTSUPP; } - info->zimage.start = be32_to_cpu(uimage.load); + info->image.start = be32_to_cpu(uimage.load); info->entry = be32_to_cpu(uimage.ep); /* @@ -224,20 +224,20 @@ int __init kernel_uimage_probe(struct kernel_info *info, * independent image. That means Xen is free to load such an image at * any valid address. */ - if ( info->zimage.start == 0 ) + if ( info->image.start == 0 ) printk(XENLOG_INFO "No load address provided. Xen will decide where to load it.\n"); else printk(XENLOG_INFO "Provided load address: %"PRIpaddr" and entry address: %"PRIpaddr"\n", - info->zimage.start, info->entry); + info->image.start, info->entry); /* * If the image supports position independent execution, then user cannot * provide an entry point as Xen will load such an image at any appropriate * memory address. Thus, we need to return error. */ - if ( (info->zimage.start == 0) && (info->entry != 0) ) + if ( (info->image.start == 0) && (info->entry != 0) ) { printk(XENLOG_ERR "Entry point cannot be non zero for PIE image.\n"); @@ -257,13 +257,13 @@ int __init kernel_uimage_probe(struct kernel_info *info, if ( rc ) return rc; - info->zimage.kernel_addr = mod->start; - info->zimage.len = mod->size; + info->image.kernel_addr = mod->start; + info->image.len = mod->size; } else { - info->zimage.kernel_addr = addr + sizeof(uimage); - info->zimage.len = len; + info->image.kernel_addr = addr + sizeof(uimage); + info->image.len = len; } info->load = kernel_zimage_load; @@ -289,7 +289,7 @@ int __init kernel_uimage_probe(struct kernel_info *info, * Thus, Xen uses uimage.load attribute to determine the load address and * zimage.text_offset is ignored. */ - info->zimage.text_offset = 0; + info->image.text_offset = 0; #endif return 0; @@ -338,10 +338,10 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, if ( (end - start) > size ) return -EINVAL; - info->zimage.kernel_addr = addr; - info->zimage.len = end - start; - info->zimage.text_offset = zimage.text_offset; - info->zimage.start = 0; + info->image.kernel_addr = addr; + info->image.len = end - start; + info->image.text_offset = zimage.text_offset; + info->image.start = 0; info->load = kernel_zimage_load; @@ -389,10 +389,10 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, } } - info->zimage.kernel_addr = addr; + info->image.kernel_addr = addr; - info->zimage.start = start; - info->zimage.len = end - start; + info->image.start = start; + info->image.len = end - start; info->load = kernel_zimage_load; @@ -403,7 +403,7 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, return 0; } -int __init kernel_zimage_probe(struct kernel_info *info, paddr_t addr, +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, paddr_t size) { int rc; diff --git a/xen/common/device-tree/kernel.c b/xen/common/device-tree/kernel.c index 28096121a52d..cfa27464f0fc 100644 --- a/xen/common/device-tree/kernel.c +++ b/xen/common/device-tree/kernel.c @@ -235,7 +235,7 @@ int __init kernel_probe(struct kernel_info *info, if ( rc && rc != -EINVAL ) return rc; - rc = kernel_zimage_probe(info, mod->start, mod->size); + rc = kernel_image_probe(info, mod->start, mod->size); return rc; } diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 33a60597bb4d..2af3bd5f0722 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -56,7 +56,7 @@ struct kernel_info { paddr_t text_offset; /* 64-bit Image only */ #endif paddr_t start; /* Must be 0 for 64-bit Image */ - } zimage; + } image; }; #if __has_include() @@ -122,7 +122,7 @@ void kernel_load(struct kernel_info *info); int kernel_decompress(struct boot_module *mod, uint32_t offset); -int kernel_zimage_probe(struct kernel_info *info, paddr_t addr, paddr_t size); +int kernel_image_probe(struct kernel_info *info, paddr_t addr, paddr_t size); /* * uImage isn't really used nowadays thereby leave kernel_uimage_probe() -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279419.1563878 (Exim 4.92) (envelope-from ) id 1wBECU-0007xK-V0; Fri, 10 Apr 2026 15:55:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279419.1563878; Fri, 10 Apr 2026 15:55:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECU-0007wr-R8; Fri, 10 Apr 2026 15:55:18 +0000 Received: by outflank-mailman (input) for mailman id 1279419; Fri, 10 Apr 2026 15:55:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECS-0007Yn-SI for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECS-00Cgsb-89 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:16 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d62-e002-0a2a0a5209dd-0a2a4509a384-2 for ; Fri, 10 Apr 2026 17:55:16 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d64-bf79-0a2a45090019-d155802daca4-3 for ; Fri, 10 Apr 2026 17:55:16 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-488a14c31eeso17203645e9.0 for ; Fri, 10 Apr 2026 08:55:16 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488d5b3c597sm78285605e9.12.2026.04.10.08.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 08:55:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775836515; x=1776441315; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B5ZH7rQJo78iVZbYMuHhA9Tl/XiBD/nIpAdpGmDqucg=; b=nnd6pLLacLLQxFXoQZTBTas/aAPaGs+zWXRWBMHvtIZSL6uMkaKs5KbxepNfEUsyfC hRhvttFifqzWzm5r5j7jxvUSZcdP7peadLcWDo0IZQqDXgEKM/axwiP83RMgp/zIMwU+ ie0yGW/9EMqjRl7TZN/QRCnSkXWIoSp90Fz7vx74zYnHXoJeS+MttWM3DB6h6J6hozOR /WBC6E+LNSJ9W68bApkhejh7yJg+wh4XMCudZVcncs5f2whu2iI4yfv+MNaCfEy6tT7P bPcvbBbmtfAQjI/UcHoFSUQuwBo2Rupt7VW+J5DtGSOHWicv8Vb5uN5R3yXBb2X75OTr xF8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775836515; x=1776441315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=B5ZH7rQJo78iVZbYMuHhA9Tl/XiBD/nIpAdpGmDqucg=; b=i7kl1To89uhG5UBm4jwSBUiYut+pfozoNz3KD4ZgFj+4pKulVlpJ8ySworzf4dEQlt qze5pvPmLn7pqyFsFaReRFPWc8IzpLupKkkEjIBQIkAzhLdGwEyKM7RVvo+vExoxm6L2 N53I3x+gtA0HFtKXR3Hm94h75ZaExpJsj+cbWp9fUmhoWjTRsNYQoaNc4czDGSfA3C5O SIl0VHXp2R5qnuuXWhNz+wZDThHt5RpW7zMlgYACYtzC4VF1BYyWHi1som8p2+C9RUec 0WxFenxQ6bp6JyH34aI5ZHuaRfCZZy1zFH93RDTA0voyVgJ9DziZ9x4I5OBflvLRFMHd Ha/Q== X-Gm-Message-State: AOJu0YxCKrA6JE0CM88VHzANRTKaKiXWVXIvrjrnmf2yVAyiFCZ27kpp T5vucy1y8tmOQIvWOOTKlnRT0aA4ELeUweBo//omoZSzQCFxLAhP4cCip52jBA== X-Gm-Gg: AeBDievn0SMBEvyr7fOYEjCl8mdigIgU1DiHd3xcJ0PnunD+bZxKPOYZ1NgvVoxRfm0 iopLCDcsG6kskPA4nUxCml4fQU/rz8Q7Ur1zmv8nBt82t1U091QwMvurnizgJU6cjg8seOWqmGY mdk68wQrzbimANBYawyPxjZlxSpPpfQvkiNveQmJFc7D+gfakRxXhzAZIBy84tUCP9HD5z85RK4 gjzMQcD4XWQmoxa2UK8/9IqErE3L93NO25eQjL8rEDntlMAtzZ9ql7/FQq3f6Jo/l5Jh3H8m4G5 xbMl+eghclq0PJQcLJyZBGYagUWjaA79oJs2ZFW7ODQnztYDFjVUCFGKWHXraHQxSfYoyt3gkCj K39JXDX6tbzbx2Zp9J4EiqnBVdsdEiGDla9lgdK2j+JRp8QxaGbFBjoTls9lI3WFdV9GDruFKrT hce1+Tl2+wf28bSCMoJM/t+B9bX1GiZZfzs0sJ8ExcHVV0FXMRmABm4sqDQGcyln/TGQ== X-Received: by 2002:a05:600c:8284:b0:488:d228:a133 with SMTP id 5b1f17b1804b1-488d683d280mr45886265e9.14.1775836515301; Fri, 10 Apr 2026 08:55:15 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v3 05/12] xen/riscv: add kernel loading support Date: Fri, 10 Apr 2026 17:54:51 +0200 Message-ID: <29ec8e444792caa925ba92cdc406ef8c0b3bd678.1775836193.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1775836516-57941152-7002F875/10/73395122804 X-purgate-type: spam X-purgate-size: 11722 Introduce support for loading a Linux kernel Image which is got by uncompressing of Image.gz on RISC-V. kernel_image_load() and place_modules() currently call panic() on failure rather than returning an error. This is because the common kernel_load() in common/device-tree/kernel.c does not expect a return code. Handling errors gracefully would require a separate refactor. The implementation is based on the Xen Arm kernel loading code. text_offset is available for both 32-bit and 64-bit Image, so fix that. Signed-off-by: Oleksii Kurochko --- Changes in v3: - s/kernel.o/kernel.init.o. - s/struct kernel_info *info/const struct kernel_info *info for kernel_image_place - s/ioremap_wc/ioremap_cache() inside kernel_image_load(). - s/u/uint. - Drop hard tabs. - Add le{32,64}_to_cpu() when correpondent le endian fields are read. - Update the comment in kernel_image64_probe() about initialization of end of image64. - Introduce image_size to pass to kernel load function total size of kernel it will have at runtime. - Update kernel_image_place() to not put Image always to bank 0. - Update place_modules() function to deal with different banks. - Propage error up the call chain in kernel_image_probe(). --- Changes in v2: - s/zimage/image as RISC-V doesn't support zImages, only Image and Image.{gz,...}. - Update the commit message. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/config.h | 13 ++ xen/arch/riscv/kernel.c | 230 ++++++++++++++++++++++++++++ xen/include/xen/fdt-kernel.h | 11 +- 4 files changed, 253 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/kernel.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index cfc3fdf7d208..eecdcbc76867 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -8,6 +8,7 @@ obj-y += guestcopy.o obj-y += imsic.o obj-y += intc.o obj-y += irq.o +obj-y += kernel.init.o obj-y += mm.o obj-y += p2m.o obj-y += paging.o diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 0613de008b13..fd69057826e1 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -151,6 +151,19 @@ extern unsigned long phys_offset; /* = load_start - XEN_VIRT_START */ #endif +/* + * KERNEL_LOAD_ADDR_ALIGNMENT is defined based on paragraph of + * "Kernel location" of boot.rst: + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location + */ +#if defined(CONFIG_RISCV_32) +#define KERNEL_LOAD_ADDR_ALIGNMENT MB(4) +#elif defined(CONFIG_RISCV_64) +#define KERNEL_LOAD_ADDR_ALIGNMENT MB(2) +#else +#error "Define KERNEL_LOAD_ADDR_ALIGNMENT" +#endif + #endif /* ASM__RISCV__CONFIG_H */ /* * Local variables: diff --git a/xen/arch/riscv/kernel.c b/xen/arch/riscv/kernel.c new file mode 100644 index 000000000000..6d58f3372358 --- /dev/null +++ b/xen/arch/riscv/kernel.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define IMAGE64_MAGIC_V2 0x05435352 /* Magic number 2, le, "RSC\x05" */ + +static void __init place_modules(struct kernel_info *info, paddr_t kernbase, + paddr_t kernend) +{ + const struct boot_module *mod = info->bd.initrd; + const struct membanks *banks = kernel_info_get_mem_const(info); + const paddr_t initrd_len = ROUNDUP(mod ? mod->size : 0, + KERNEL_LOAD_ADDR_ALIGNMENT); + const paddr_t dtb_len = ROUNDUP(fdt_totalsize(info->fdt), + KERNEL_LOAD_ADDR_ALIGNMENT); + const paddr_t modsize = initrd_len + dtb_len; + int bi; + + BUG_ON(modsize < initrd_len); + + /* + * Place modules as high in RAM as possible, scanning banks from + * last to first so that the end of the last bank is preferred. + */ + for ( bi = banks->nr_banks - 1; bi >= 0; bi-- ) + { + const struct membank *bank = &banks->bank[bi]; + const paddr_t bank_end = bank->start + bank->size; + paddr_t modbase; + + if ( modsize > bank->size ) + continue; + + modbase = ROUNDDOWN(bank_end - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); + + if ( modbase < bank->start ) + continue; + + /* + * If the kernel resides in this bank, ensure modules do not + * overlap with it. + */ + if ( (kernbase >= bank->start) && (kernbase < bank_end) && + (modbase < ROUNDUP(kernend, KERNEL_LOAD_ADDR_ALIGNMENT)) && + (modbase + modsize > kernbase) ) + continue; + + info->dtb_paddr = modbase; + info->initrd_paddr = modbase + dtb_len; + + return; + } + + panic("Unable to find suitable location for dtb+initrd\n"); +} + +static paddr_t __init kernel_image_place(struct kernel_info *info) +{ + paddr_t load_addr = INVALID_PADDR; + uint64_t image_size = info->image.image_size ?: info->image.len; + const struct membanks *banks = kernel_info_get_mem_const(info); + unsigned int nr_banks = banks->nr_banks; + unsigned int bi; + + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); + + /* + * At the moment, RISC-V's Linux kernel should be always position + * independent based on "Per-MMU execution" of boot.rst: + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution + * + * But just for the case when RISC-V's Linux kernel isn't position + * independent it is needed to take load address from + * info->image.start. + * + * If `start` is zero, the Image is position independent. + */ + if ( likely(!info->image.start) ) + { + for ( bi = 0; bi != nr_banks; bi++ ) + { + const struct membank *bank = &banks->bank[bi]; + paddr_t bank_start = bank->start; + /* + * According to boot.rst kernel load address should be properly + * aligned: + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location + * + * As Image in this case is PIC we can ignore + * info->image.text_offset. + */ + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); + paddr_t bank_end = bank_start + bank->size; + paddr_t bank_size; + + if ( aligned_start > bank_end ) + continue; + + bank_size = bank_end - aligned_start; + + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); + + if ( image_size <= bank_size ) + { + load_addr = aligned_start; + break; + } + } + } + else + { + load_addr = info->image.start + info->image.text_offset; + + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); + + for ( bi = 0; bi != nr_banks; bi++ ) + { + const struct membank *bank = &banks->bank[bi]; + paddr_t bank_start = bank->start; + paddr_t bank_end = bank_start + bank->size; + + if ( (load_addr >= bank_start) && (load_addr < bank_end) && + (bank_end - load_addr) >= image_size ) + break; + } + } + + if ( bi == nr_banks ) + panic("Failed to place kernel image in any memory bank\n"); + + info->entry = load_addr; + + return load_addr; +} + +static void __init kernel_image_load(struct kernel_info *info) +{ + int rc; + paddr_t load_addr = kernel_image_place(info); + paddr_t paddr = info->image.kernel_addr; + paddr_t len = info->image.len; + paddr_t effective_size = info->image.image_size ?: len; + void *kernel; + + place_modules(info, load_addr, load_addr + effective_size); + + printk("Loading Image from %"PRIpaddr" to %"PRIpaddr"-%"PRIpaddr"\n", + paddr, load_addr, load_addr + effective_size); + + kernel = ioremap_cache(paddr, len); + + if ( !kernel ) + panic("Unable to map kernel\n"); + + /* Move kernel to proper location in guest phys map */ + rc = copy_to_guest_phys(info->bd.d, load_addr, kernel, len); + + if ( rc ) + panic("Unable to copy kernel to proper guest location\n"); + + iounmap(kernel); +} + +/* Check if the image is a 64-bit Image */ +static int __init kernel_image64_probe(struct kernel_info *info, + paddr_t addr, paddr_t size) +{ + /* riscv/boot-image-header.rst */ + struct { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset, little endian */ + uint64_t image_size; /* Effective Image size, little endian */ + uint64_t flags; /* kernel flags, little endian */ + uint32_t version; /* Version of this header */ + uint32_t res1; /* Reserved */ + uint64_t res2; /* Reserved */ + uint64_t magic; /* Deprecated: Magic number, little endian, "RISCV" */ + uint32_t magic2; /* Magic number 2, little endian, "RSC\x05" */ + uint32_t res3; /* Reserved for PE COFF offset */ + } image; + uint64_t effective_size; + + if ( size < sizeof(image) ) + return -EINVAL; + + copy_from_paddr(&image, addr, sizeof(image)); + + /* Magic v1 is deprecated and may be removed. Only use v2 */ + if ( le32_to_cpu(image.magic2) != IMAGE64_MAGIC_V2 ) + return -EINVAL; + + effective_size = le64_to_cpu(image.image_size); + + if ( effective_size && size > effective_size ) + return -EINVAL; + + info->image.kernel_addr = addr; + /* Actual size in the binary file */ + info->image.len = size; + /* Total memory the kernel occupies at runtime */ + info->image.image_size = effective_size; + info->image.text_offset = le64_to_cpu(image.text_offset); + info->image.start = 0; + + info->load = kernel_image_load; + + return 0; +} + +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, + paddr_t size) +{ +#ifdef CONFIG_RISCV_64 + return kernel_image64_probe(info, addr, size); +#else + return -EOPNOTSUPP; +#endif +} diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 2af3bd5f0722..aa977a50f4fc 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -52,8 +52,15 @@ struct kernel_info { struct { paddr_t kernel_addr; paddr_t len; -#if defined(CONFIG_ARM_64) || defined(CONFIG_RISCV_64) - paddr_t text_offset; /* 64-bit Image only */ +#if defined(CONFIG_ARM_64) || defined(CONFIG_RISCV) + /* + * ARM: 64-bit Image only. + * RISC-V: both 32-bit and 64-bit Images. + */ + paddr_t text_offset; +#endif +#if defined(CONFIG_RISCV) + uint64_t image_size; /* Effective size of Image */ #endif paddr_t start; /* Must be 0 for 64-bit Image */ } image; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279420.1563884 (Exim 4.92) (envelope-from ) id 1wBECV-000819-E6; Fri, 10 Apr 2026 15:55:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279420.1563884; Fri, 10 Apr 2026 15:55:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECV-00080C-4q; Fri, 10 Apr 2026 15:55:19 +0000 Received: by outflank-mailman (input) for mailman id 1279420; Fri, 10 Apr 2026 15:55:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECU-0007kD-06 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECT-00DRfX-CL for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:17 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5e-5cb7-0a2a0a5109dd-0a2a450183fa-12 for ; Fri, 10 Apr 2026 17:55:17 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d65-6fc9-0a2a45010019-d1558029c9ce-3 for ; Fri, 10 Apr 2026 17:55:17 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so15800415e9.3 for ; Fri, 10 Apr 2026 08:55:17 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Signed-off-by: Oleksii Kurochko --- Changes in v2-v3: - Nothing changed. Only rebase. --- xen/arch/arm/include/asm/setup.h | 3 --- xen/include/xen/bootinfo.h | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/setup.h index 899e33925ca4..0d29b46ea52b 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -43,9 +43,6 @@ int acpi_make_efi_nodes(void *fdt, struct membank tbl_add[]); void create_dom0(void); void discard_initial_modules(void); -void fw_unreserved_regions(paddr_t s, paddr_t e, - void (*cb)(paddr_t ps, paddr_t pe), - unsigned int first); void init_pdx(void); void setup_mm(void); diff --git a/xen/include/xen/bootinfo.h b/xen/include/xen/bootinfo.h index f834f1957155..dbf492c2e36e 100644 --- a/xen/include/xen/bootinfo.h +++ b/xen/include/xen/bootinfo.h @@ -210,4 +210,8 @@ static inline struct membanks *membanks_xzalloc(unsigned int nr, return banks; } +void fw_unreserved_regions(paddr_t s, paddr_t e, + void (*cb)(paddr_t ps, paddr_t pe), + unsigned int first); + #endif /* XEN_BOOTINFO_H */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279422.1563896 (Exim 4.92) (envelope-from ) id 1wBECX-0008Sj-1Z; Fri, 10 Apr 2026 15:55:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279422.1563896; Fri, 10 Apr 2026 15:55:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECW-0008SG-Qh; Fri, 10 Apr 2026 15:55:20 +0000 Received: by outflank-mailman (input) for mailman id 1279422; Fri, 10 Apr 2026 15:55:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECV-0007xm-6l for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECU-00DRfX-Io for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:18 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5e-5cb7-0a2a0a5109dd-0a2a450183fa-18 for ; Fri, 10 Apr 2026 17:55:18 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d66-6fc9-0a2a45010019-d1558030c4d2-3 for ; Fri, 10 Apr 2026 17:55:18 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-488c2690057so21734005e9.0 for ; Fri, 10 Apr 2026 08:55:18 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Replace the ARM-specific macro in asm/domain.h with a common static inline in a new dedicated header, xen/domain-layout.h. xen/domain.h would be the natural home, but placing it there would require including xen/paging.h (for paging_mode_translate()) and xen/sched.h (for is_hardware_domain()), which would introduce circular dependencies. A separate header that callers opt into avoids this. Adjust the implementation to take paging_mode_translate() into account so it works correctly for all architectures, including x86. Some extra details about implementation [2] and [3]. [1] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602161038120.359097@ubuntu-linux-20-04-desktop/ [2] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602271742400.3148344@ubuntu-linux-20-04-desktop/ [3] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602271750190.3148344@ubuntu-linux-20-04-desktop/ Suggested-by: Stefano Stabellini Signed-off-by: Oleksii Kurochko --- Changes in v3: - Make argument of domain_use_host_layout() const. - Create a separate header to avoid circular heder dependecy and making domain_use_host_layour() as static inline. - Rework domain_use_host_layout() to be protected by paging_mode_translate(). - Update the commit message. --- Changes in v2: - Drop ifdef around defintion of domain_use_host_layout() as it was suggested generic version. It could be returned back when the real use case for it will appear. - Add Suggested-by: and update the commit message. - Make domain_use_host_layout() function instead of macros to avoid ciclular header dependecies. Look at more details in the commit message. --- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/include/asm/domain.h | 14 -------------- xen/arch/arm/vgic-v3.c | 1 + xen/common/device-tree/domain-build.c | 1 + xen/include/xen/domain-layout.h | 28 +++++++++++++++++++++++++++ 5 files changed, 31 insertions(+), 14 deletions(-) create mode 100644 xen/include/xen/domain-layout.h diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6c17a84b2633..60a7cbf915a5 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..f95ad1285e6e 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -30,20 +30,6 @@ enum domain_type { #define is_64bit_domain(d) (0) #endif -/* - * Is the domain using the host memory layout? - * - * Direct-mapped domain will always have the RAM mapped with GFN == MFN. - * To avoid any trouble finding space, it is easier to force using the - * host memory layout. - * - * The hardware domain will use the host layout regardless of - * direct-mapped because some OS may rely on a specific address ranges - * for the devices. - */ -#define domain_use_host_layout(d) (is_domain_direct_mapped(d) || \ - is_hardware_domain(d)) - struct vtimer { struct vcpu *v; int irq; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 77aab5c3c293..77517c303061 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree/domain-build.c index 540627b74e96..e706a6173ba6 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/xen/include/xen/domain-layout.h b/xen/include/xen/domain-layout.h new file mode 100644 index 000000000000..15cbb1813c8a --- /dev/null +++ b/xen/include/xen/domain-layout.h @@ -0,0 +1,28 @@ +#ifndef __XEN_DOMAIN_LAYOUT_H__ +#define __XEN_DOMAIN_LAYOUT_H__ + +#include +#include +#include + +/* + * Is a domain using the host memory layout? + * + * domain_use_host_layout() is always False for PV guests. + * + * Direct-mapped domains (autotranslated domains with memory allocated + * contiguously and mapped 1:1 so that GFN == MFN) are always using the + * host memory layout to avoid address clashes. + * + * The hardware domain will use the host layout (regardless of + * direct-mapped) because some OS may rely on specific address ranges + * for the devices. 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Promote modes[] from a local __initconst variable inside gstage_mode_detect() to a file-scope static const array, and convert max_gstage_mode from an embedded struct (assigned by value) to a global const pointer into modes[]. This allows referencing both the mode identifier and the mode name after init without copying the descriptor. Remove get_max_supported_mode(); its callers now dereference max_gstage_mode->mode directly. Change struct p2m_domain::mode from an embedded gstage_mode_desc to a const pointer into modes[], so each domain shares the descriptor rather than carrying its own copy. Adjust the modes[] entries in three ways: - Use lowercase names without the "x4" suffix (e.g. "sv39" instead of "Sv39x4"). The DT mmu-type binding [1] does not include the suffix, so the name can now be passed directly to the guest without transformation. The suffix is appended only in the diagnostic printk, where it remains informative. - Use "none" for Bare mode (HGATP_MODE_OFF) to match the DT binding. - Change paging_levels to represent the root page-table level index (i.e. total paging levels minus one) rather than the total count. P2M_ROOT_LEVEL() now returns the correct VPN index directly, without requiring callers to subtract one or use hardcoded offsets. Add gstage_mode[8] to xen_arch_domainconfig so the toolstack can request a specific G-stage mode at domain creation time. Introduce find_gstage_mode() to resolve a mode descriptor by name (case-insensitive), capping the result at max_gstage_mode to prevent requesting a mode the hardware does not support. Update p2m_init() to accept a xen_domctl_createdomain pointer and call find_gstage_mode() instead of hardcoding Sv39x4. Add arch_parse_dom0less_node() in a new dom0less-build.c to read the "mmu-type" DT property from a guest domain node and store it in boot_domain::create_cfg.arch.gstage_mode, falling back to maximum supported mode when the property is absent. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v6.19-rc3#n82 Signed-off-by: Oleksii Kurochko --- Changes in v3: - New patch. Was taken from another patch series: https://lore.kernel.org/xen-devel/cover.1773157782.git.oleksii.kurochko@gmail.com/T/#m6eb886bdf718b06b967d1688314b80e7374a8de5 --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/dom0less-build.c | 30 ++++++++ xen/arch/riscv/include/asm/p2m.h | 11 +-- xen/arch/riscv/p2m.c | 113 +++++++++++++++++++++---------- xen/arch/riscv/vmid.c | 2 +- xen/include/public/arch-riscv.h | 5 ++ 6 files changed, 121 insertions(+), 41 deletions(-) create mode 100644 xen/arch/riscv/dom0less-build.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index eecdcbc76867..8f7fd625dddd 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,6 +1,7 @@ obj-y += aplic.o obj-y += cpufeature.o obj-y += domain.o +obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += extable.o diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-build.c new file mode 100644 index 000000000000..11fa184d54be --- /dev/null +++ b/xen/arch/riscv/dom0less-build.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include + +int __init arch_parse_dom0less_node(struct dt_device_node *node, + struct boot_domain *bd) +{ + const char *mmu_type; + + if ( dt_property_read_string(node, "mmu-type", &mmu_type) ) + { + dprintk(XENLOG_WARNING, "mmu-type property is missing in guest domain " + "node. %s will be used as fallback\n", max_gstage_mode->name); + + mmu_type = max_gstage_mode->name; + } + + if ( safe_strcpy(bd->create_cfg.arch.gstage_mode, mmu_type) ) + { + dprintk(XENLOG_ERR, "mmu-type value \"%s\" is too long\n", mmu_type); + + return -EINVAL; + } + + return 0; +} diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 54ea67990f06..b5b6a996baeb 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -13,7 +13,7 @@ #define P2M_ROOT_ORDER (ilog2(GSTAGE_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT) #define P2M_ROOT_PAGES BIT(P2M_ROOT_ORDER, U) -#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode.paging_levels) +#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode->paging_levels) /* * According to the RISC-V spec: @@ -55,6 +55,8 @@ struct gstage_mode_desc { char name[8]; }; +extern const struct gstage_mode_desc *max_gstage_mode; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -68,7 +70,7 @@ struct p2m_domain { /* The root of the p2m tree. May be concatenated */ struct page_info *root; - struct gstage_mode_desc mode; + const struct gstage_mode_desc *mode; /* Back pointer to domain */ struct domain *domain; @@ -215,9 +217,10 @@ static inline bool arch_acquire_resource_check(struct domain *d) } void guest_mm_init(void); -unsigned char get_max_supported_mode(void); -int p2m_init(struct domain *d); +struct xen_domctl_createdomain; + +int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config); static inline void p2m_write_lock(struct p2m_domain *p2m) { diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index d63697c89a1a..b0773083ff53 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -45,12 +45,27 @@ struct p2m_pte_ctx { unsigned int level; /* Paging level at which the PTE resides. */ }; -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { - .mode = HGATP_MODE_OFF, - .paging_levels = 0, - .name = "Bare", +/* Values should be sorted by ->mode in this array */ +static const struct gstage_mode_desc modes[] = { + /* + * Based on the RISC-V spec: + * Bare mode is always supported, regardless of SXLEN. + * When SXLEN=32, the only other valid setting for MODE is Sv32. + * When SXLEN=64, three paged virtual-memory schemes are defined: + * Sv39, Sv48, and Sv57. + */ + { HGATP_MODE_OFF, 0, "none" }, +#ifdef CONFIG_RISCV_32 + { HGATP_MODE_SV32X4, 1, "sv32" }, +#else + { HGATP_MODE_SV39X4, 2, "sv39" }, + { HGATP_MODE_SV48X4, 3, "sv48" }, + { HGATP_MODE_SV57X4, 4, "sv57" }, +#endif }; +const struct gstage_mode_desc * __ro_after_init max_gstage_mode = &modes[0]; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -63,11 +78,6 @@ static inline void p2m_free_metadata_page(struct p2m_domain *p2m, } } -unsigned char get_max_supported_mode(void) -{ - return max_gstage_mode.mode; -} - /* * If anything is changed here, it may also require updates to * p2m_{get,set}_type(). @@ -148,23 +158,6 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn) static void __init gstage_mode_detect(void) { - static const struct gstage_mode_desc modes[] __initconst = { - /* - * Based on the RISC-V spec: - * Bare mode is always supported, regardless of SXLEN. - * When SXLEN=32, the only other valid setting for MODE is Sv32. - * When SXLEN=64, three paged virtual-memory schemes are defined: - * Sv39, Sv48, and Sv57. - */ -#ifdef CONFIG_RISCV_32 - { HGATP_MODE_SV32X4, 2, "Sv32x4" } -#else - { HGATP_MODE_SV39X4, 3, "Sv39x4" }, - { HGATP_MODE_SV48X4, 4, "Sv48x4" }, - { HGATP_MODE_SV57X4, 5, "Sv57x4" }, -#endif - }; - for ( unsigned int mode_idx = ARRAY_SIZE(modes); mode_idx-- > 0; ) { unsigned long mode = modes[mode_idx].mode; @@ -173,16 +166,16 @@ static void __init gstage_mode_detect(void) if ( MASK_EXTR(csr_read(CSR_HGATP), HGATP_MODE_MASK) == mode ) { - max_gstage_mode = modes[mode_idx]; + max_gstage_mode = &modes[mode_idx]; break; } } - if ( max_gstage_mode.mode == HGATP_MODE_OFF ) + if ( max_gstage_mode->mode == HGATP_MODE_OFF ) panic("Xen expects that G-stage won't be Bare mode\n"); - printk("Max supported G-stage mode is %s\n", max_gstage_mode.name); + printk("Max supported G-stage mode is %sx4\n", max_gstage_mode->name); csr_write(CSR_HGATP, 0); @@ -283,7 +276,7 @@ static void clear_and_clean_page(struct page_info *page, bool clean_dcache) unsigned long construct_hgatp(const struct p2m_domain *p2m, uint16_t vmid) { return MASK_INSR(mfn_x(page_to_mfn(p2m->root)), HGATP_PPN_MASK) | - MASK_INSR(p2m->mode.mode, HGATP_MODE_MASK) | + MASK_INSR(p2m->mode->mode, HGATP_MODE_MASK) | MASK_INSR(vmid, HGATP_VMID_MASK); } @@ -331,8 +324,40 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m) return 0; } -int p2m_init(struct domain *d) +static const struct gstage_mode_desc * find_gstage_mode(const char *mmu_type) { + for ( unsigned int mode_idx = 0; mode_idx < ARRAY_SIZE(modes); mode_idx++ ) + { + if ( !strcasecmp(mmu_type, modes[mode_idx].name) ) + { + if ( modes[mode_idx].mode == HGATP_MODE_OFF || + modes[mode_idx].mode > max_gstage_mode->mode ) + break; + + return &modes[mode_idx]; + } + } + + ASSERT(modes[0].mode == HGATP_MODE_OFF); + + dprintk(XENLOG_ERR, "Requested G-stage mode (%s) isn't supported\n", + mmu_type); + + /* + * Return the Bare-mode sentinel. p2m_init() will reject it with + * -EINVAL, producing the appropriate domain-creation failure. + */ + return &modes[0]; +} + +int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) +{ + /* + * TODO: This static is a temporary constraint: all guests must use the + * same MMU mode because p2m_gpa_bits is not yet per-domain. + * Drop this once per-domain p2m_gpa_bits is introduced. + */ + static const struct gstage_mode_desc *m = &modes[0]; struct p2m_domain *p2m = p2m_get_hostp2m(d); /* @@ -341,6 +366,27 @@ int p2m_init(struct domain *d) */ p2m->domain = d; + if ( !config ) + { + dprintk(XENLOG_ERR, "NULL config is passed\n"); + return -EINVAL; + } + + p2m->mode = find_gstage_mode(config->arch.gstage_mode); + + if ( p2m->mode->mode == HGATP_MODE_OFF ) + return -EINVAL; + + if ( m->mode == HGATP_MODE_OFF ) + m = p2m->mode; + + if ( m->mode != p2m->mode->mode ) + { + dprintk(XENLOG_ERR, + "Mode should be the same for all guests at the moment\n"); + return -EINVAL; + } + paging_domain_init(d); rwlock_init(&p2m->lock); @@ -362,11 +408,6 @@ int p2m_init(struct domain *d) # error "Add init of p2m->clean_dcache" #endif - /* TODO: don't hardcode used for a domain g-stage mode. */ - p2m->mode.mode = HGATP_MODE_SV39X4; - p2m->mode.paging_levels = 2; - safe_strcpy(p2m->mode.name, "Sv39x4"); - return 0; } diff --git a/xen/arch/riscv/vmid.c b/xen/arch/riscv/vmid.c index 8fbcd500f24d..11c7e9d6d6c8 100644 --- a/xen/arch/riscv/vmid.c +++ b/xen/arch/riscv/vmid.c @@ -52,7 +52,7 @@ static DEFINE_PER_CPU(struct vmid_data, vmid_data); static unsigned int vmidlen_detect(void) { unsigned int vmid_bits; - unsigned char gstage_mode = get_max_supported_mode(); + unsigned char gstage_mode = max_gstage_mode->mode; /* * According to the RISC-V Privileged Architecture Spec: diff --git a/xen/include/public/arch-riscv.h b/xen/include/public/arch-riscv.h index 360d8e6871ba..5faf8924d926 100644 --- a/xen/include/public/arch-riscv.h +++ b/xen/include/public/arch-riscv.h @@ -56,6 +56,11 @@ typedef struct vcpu_guest_context vcpu_guest_context_t; DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); struct xen_arch_domainconfig { + /* + * G-stage MMU mode for the guest (e.g. "sv39", "sv48", "sv57"). + * Must be set; an empty string is invalid. + */ + char gstage_mode[8]; }; #endif -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279427.1563911 (Exim 4.92) (envelope-from ) id 1wBECY-0000Ps-Tb; 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No functional changes. Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in v3: - Introduce #define p2m_gpa_bits p2m_ipa_bits for Arm instead of renaming of p2m_ipa_bits to p2m_gpa_bits to keep Arm part of changes clearer and keep using Arm-specific terminolgy inside Arm code. --- Changes in v2: - New patch. --- xen/arch/arm/include/asm/p2m.h | 2 ++ xen/common/device-tree/domain-build.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..7957dbd96e57 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -14,6 +14,8 @@ /* Holds the bit size of IPAs in p2m tables. */ extern unsigned int p2m_ipa_bits; +#define p2m_gpa_bits p2m_ipa_bits + #define MAX_VMID_8_BIT (1UL << 8) #define MAX_VMID_16_BIT (1UL << 16) diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree/domain-build.c index e706a6173ba6..30625a33ef08 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -221,7 +221,7 @@ int __init find_unallocated_memory(const struct kernel_info *kinfo, } start = 0; - end = (1ULL << p2m_ipa_bits) - 1; + end = (1ULL << p2m_gpa_bits) - 1; res = rangeset_report_ranges(unalloc_mem, PFN_DOWN(start), PFN_DOWN(end), cb, free_regions); if ( res ) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279431.1563923 (Exim 4.92) (envelope-from ) id 1wBECb-0000vZ-EC; Fri, 10 Apr 2026 15:55:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279431.1563923; Fri, 10 Apr 2026 15:55:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECb-0000vF-9U; Fri, 10 Apr 2026 15:55:25 +0000 Received: by outflank-mailman (input) for mailman id 1279431; Fri, 10 Apr 2026 15:55:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECY-0000Lo-N5 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECY-00Cgsb-32 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:22 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5d-e002-0a2a0a5209dd-0a2a4508b042-30 for ; Fri, 10 Apr 2026 17:55:22 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d69-fab6-0a2a45080019-d155802bccf4-3 for ; Fri, 10 Apr 2026 17:55:22 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-488971db0fdso21894035e9.0 for ; Fri, 10 Apr 2026 08:55:22 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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The variable is initialised to PADDR_BITS and narrowed in p2m_init() to the GPA width of the selected G-stage mode, allowing an external entity (e.g. an IOMMU) to restrict it further if needed. p2m_gpa_bits is a global rather than a per-domain value, which is acceptable for now because all domains are required to use the same G-stage MMU mode, as dom0less common code allocates it per all domains. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Update initialization of p2m_gpa_bits and the comment above. - Rework how p2m_gpa_bits is limited. - Update the commit message. --- Changes in v2: - New patch. --- xen/arch/riscv/include/asm/p2m.h | 10 ++++++++-- xen/arch/riscv/p2m.c | 17 ++++++++++++++++- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index b5b6a996baeb..0d1dace1a0d8 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -32,10 +32,13 @@ */ #define P2M_LEVEL_ORDER(lvl) XEN_PT_LEVEL_ORDER(lvl) -#define P2M_ROOT_EXTRA_BITS(p2m, lvl) (2 * ((lvl) == P2M_ROOT_LEVEL(p2m))) +#define P2M_ROOT_EXTRA_BITS 2 + +#define P2M_LEVEL_EXTRA_BITS(p2m, lvl) \ + (P2M_ROOT_EXTRA_BITS * ((lvl) == P2M_ROOT_LEVEL(p2m))) #define P2M_PAGETABLE_ENTRIES(p2m, lvl) \ - (BIT(PAGETABLE_ORDER + P2M_ROOT_EXTRA_BITS(p2m, lvl), UL)) + (BIT(PAGETABLE_ORDER + P2M_LEVEL_EXTRA_BITS(p2m, lvl), UL)) #define P2M_TABLE_OFFSET(p2m, lvl) (P2M_PAGETABLE_ENTRIES(p2m, lvl) - 1UL) @@ -44,6 +47,9 @@ #define P2M_LEVEL_MASK(p2m, lvl) \ (P2M_TABLE_OFFSET(p2m, lvl) << P2M_GFN_LEVEL_SHIFT(lvl)) +/* Holds the bit size of GPAs in p2m tables */ +extern unsigned int p2m_gpa_bits; + #define paddr_bits PADDR_BITS /* Get host p2m table */ diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index b0773083ff53..1f229e96d740 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -11,6 +11,8 @@ #include #include +#include + #include #include #include @@ -66,6 +68,12 @@ static const struct gstage_mode_desc modes[] = { const struct gstage_mode_desc * __ro_after_init max_gstage_mode = &modes[0]; +/* + * Set to the maximum configured support for GPA bits, so the number of GPA + * bits can be restricted by an external entity (e.g. IOMMU). + */ +unsigned int __ro_after_init p2m_gpa_bits = PADDR_BITS; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -359,6 +367,7 @@ int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) */ static const struct gstage_mode_desc *m = &modes[0]; struct p2m_domain *p2m = p2m_get_hostp2m(d); + unsigned int gpa_bits; /* * "Trivial" initialisation is now complete. Set the backpointer so the @@ -408,6 +417,12 @@ int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) # error "Add init of p2m->clean_dcache" #endif + gpa_bits = P2M_GFN_LEVEL_SHIFT(p2m->mode->paging_levels + 1) + + P2M_ROOT_EXTRA_BITS; + + if ( gpa_bits < p2m_gpa_bits ) + p2m_gpa_bits = gpa_bits; + return 0; } @@ -1345,7 +1360,7 @@ static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, { unsigned int level = P2M_ROOT_LEVEL(p2m); unsigned int gfn_limit_bits = - P2M_LEVEL_ORDER(level + 1) + P2M_ROOT_EXTRA_BITS(p2m, level); + P2M_LEVEL_ORDER(level + 1) + P2M_LEVEL_EXTRA_BITS(p2m, level); pte_t entry, *table; int rc; mfn_t mfn = INVALID_MFN; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279434.1563928 (Exim 4.92) (envelope-from ) id 1wBECc-00011S-1g; Fri, 10 Apr 2026 15:55:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279434.1563928; Fri, 10 Apr 2026 15:55:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECb-00010H-No; Fri, 10 Apr 2026 15:55:25 +0000 Received: by outflank-mailman (input) for mailman id 1279434; Fri, 10 Apr 2026 15:55:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECZ-0000go-Vt for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECZ-00Cgsb-BJ for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:23 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d6a-e002-0a2a0a5209dd-0a2a4507c022-4 for ; Fri, 10 Apr 2026 17:55:23 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d6b-ba2d-0a2a45070019-d155802ac91f-3 for ; Fri, 10 Apr 2026 17:55:23 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so15801995e9.3 for ; Fri, 10 Apr 2026 08:55:23 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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The reason for 2 banks is that there is typically always a use case for low memory under 4 GB, but the bank under 4 GB ends up being small because there are other things under 4 GB it can conflict with (interrupt controller, PCI BARs, etc.). So a second bank is added above that MMIO region (starting at 8 GiB) to provide the remaining RAM; the gap between the two banks also exercises code paths handling discontiguous memory. For Sv32 guests (34-bit GPA, 16 GiB addressable), bank0 provides 2 GB (2–4 GB) and the first 8 GB of bank1 (8–16 GB) is accessible. Extended regions are useful for RISC-V: they could be used to provide a "space" for Linux to map grant mappings. Despite the fact that for every guest MMU mode the GPA could be up to 56 bits wide (except Sv32 whose GPA is 34 bits), the combined size of both banks is limited to 1018 GB as it is more than enough for most use cases. Add inclusion of asm/guest-layout.h to asm/domain.h to make dom0less common code build happy. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Move GUEST_RAM*-related defines to asm/p2m.h instead of public header. --- Changes in v2: - New patch. --- xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/include/asm/guest-layout.h | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest-layout.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h index 6c48bf13111d..6044ce0feee0 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -7,6 +7,7 @@ #include #include +#include #include #include diff --git a/xen/arch/riscv/include/asm/guest-layout.h b/xen/arch/riscv/include/asm/guest-layout.h new file mode 100644 index 000000000000..68d95a09394c --- /dev/null +++ b/xen/arch/riscv/include/asm/guest-layout.h @@ -0,0 +1,23 @@ +#ifndef ASM_RISCV_GUEST_LAYOUT_H +#define ASM_RISCV_GUEST_LAYOUT_H + +#include + +#define GUEST_RAM_BANKS 2 + +/* + * The way to find the extended regions (to be exposed to the guest as unused + * address space) relies on the fact that the regions reserved for the RAM + * below are big enough to also accommodate such regions. + */ +#define GUEST_RAM0_BASE xen_mk_ullong(0x80000000) /* 2GB of low RAM @ 2GB */ +#define GUEST_RAM0_SIZE xen_mk_ullong(0x80000000) + +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016 GB of RAM @ 8GB */ +#define GUEST_RAM1_SIZE xen_mk_ullong(0xFE00000000) + +/* TODO: allocate these all dynamically */ +#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } +#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } + +#endif /* ASM_RISCV_GUEST_LAYOUT_H */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 15:55:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 15:55:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279438.1563932 (Exim 4.92) (envelope-from ) id 1wBECc-000179-P8; Fri, 10 Apr 2026 15:55:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279438.1563932; Fri, 10 Apr 2026 15:55:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBECc-000159-Be; Fri, 10 Apr 2026 15:55:26 +0000 Received: by outflank-mailman (input) for mailman id 1279438; Fri, 10 Apr 2026 15:55:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wBECb-0000sc-2l for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 15:55:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBECa-00Cgsb-Eg for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:55:24 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d91d5d-e002-0a2a0a5209dd-0a2a4508b042-36 for ; Fri, 10 Apr 2026 17:55:24 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d91d6c-fab6-0a2a45080019-d1558036acec-3 for ; Fri, 10 Apr 2026 17:55:24 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488a14c31eeso17205725e9.0 for ; Fri, 10 Apr 2026 08:55:24 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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So enable it. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - Add Acked-by: Jan Beulich . --- Changes in v2: - Move introduction of p2m_ipa_bits to separate patch. - Move to separate patch introduction of guest banks constansts. --- xen/arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index a5e87c1757f7..41426c205292 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -1,5 +1,6 @@ config RISCV def_bool y + select DOMAIN_BUILD_HELPERS select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME select GENERIC_UART_INIT -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 17:02:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 17:02:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279586.1563958 (Exim 4.92) (envelope-from ) id 1wBFFL-00072I-P1; Fri, 10 Apr 2026 17:02:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279586.1563958; Fri, 10 Apr 2026 17:02:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBFFL-00072B-L4; Fri, 10 Apr 2026 17:02:19 +0000 Received: by outflank-mailman (input) for mailman id 1279586; Fri, 10 Apr 2026 16:40:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBEud-0004ce-Ol for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 16:40:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBEud-00GILx-4t for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 18:40:55 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d92808-e002-0a2a0a5209dd-0a2a4509c3b6-20 for ; Fri, 10 Apr 2026 18:40:55 +0200 Received: from [209.85.221.53] (helo=mail-wr1-f53.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d92816-bf79-0a2a45090019-d155dd35e810-3 for ; Fri, 10 Apr 2026 18:40:55 +0200 Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-43cf7683a28so1518543f8f.2 for ; Fri, 10 Apr 2026 09:40:55 -0700 (PDT) Received: from thinkpad-t470s.. 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If any of the steps fail, scheduler entry is cleared in global 'schedulers' array. However, in the current implementation, if verification fails during the first step, the scheduler entry is cleared but verification sequence is not interrupted. This lead to NULL pointer dereference when subsequent required callbacks verified, and possible during the second step. The patch fixes the crashes by adding check inside sched_test_func macro and skipping the call to a global_init if first step did not pass. Signed-off-by: Ruslan Ruslichenko --- xen/common/sched/core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index a57d5dd929..4270c89491 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -3017,7 +3017,7 @@ void __init scheduler_init(void) for ( i = 0; i < NUM_SCHEDULERS; i++) { #define sched_test_func(f) \ - if ( !schedulers[i]->f ) \ + if ( schedulers[i] && !schedulers[i]->f ) \ { \ printk("scheduler %s misses .%s, dropped\n", \ schedulers[i]->opt_name, #f); \ @@ -3034,6 +3034,9 @@ void __init scheduler_init(void) #undef sched_test_func + if ( !schedulers[i] ) + continue; + if ( schedulers[i]->global_init && schedulers[i]->global_init() < 0 ) { printk("scheduler %s failed initialization, dropped\n", -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 17:36:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 17:36:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279641.1563967 (Exim 4.92) (envelope-from ) id 1wBFmO-0002dG-AJ; Fri, 10 Apr 2026 17:36:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279641.1563967; Fri, 10 Apr 2026 17:36:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBFmO-0002d9-6w; Fri, 10 Apr 2026 17:36:28 +0000 Received: by outflank-mailman (input) for mailman id 1279641; Fri, 10 Apr 2026 17:36:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBFmN-0002d3-70 for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 17:36:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBFmM-00FFGg-JH for xen-devel@lists.xenproject.org; Fri, 10 Apr 2026 19:36:26 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69d93503-bab6-0a2a0a5309dd-0a2a45039306-24 for ; Fri, 10 Apr 2026 19:36:26 +0200 Received: from [209.85.208.43] (helo=mail-ed1-f43.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69d9351a-02b3-0a2a45030019-d155d02ba5af-3 for ; Fri, 10 Apr 2026 19:36:26 +0200 Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-66d65646c65so11742a12.1 for ; Fri, 10 Apr 2026 10:36:26 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Comparing the masked but unshifted values against GIC_BASER_CACHE_nC, which is an unshifted enum value, leads to incorrect detection of non-cacheable GITS_CBASER command queue, GITS_BASER tables, and GICR_PROPBASER mappings. Use MASK_EXTR() to decode these cacheability fields before comparing against GIC_BASER_CACHE_nC, so the backing memory is flushed when required. Fixes: 8ed8d21373be ("ARM: GICv3 ITS: map ITS command buffer") Fixes: 05238012b86d ("ARM: GICv3 ITS: allocate device and collection table") Fixes: c9b939863c89 ("ARM: GICv3: allocate LPI pending and property table") Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in v2: - use MASK_EXTR() instead of open-coding the BASER field shift - fix the analogous PROPBASER cacheability comparison in gicv3_lpi_set_proptable() - fix the CBASER command queue cacheability check as well --- xen/arch/arm/gic-v3-its.c | 6 ++++-- xen/arch/arm/gic-v3-lpi.c | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 9ba068c46f..e87465d2ff 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -424,7 +424,8 @@ static void *its_map_cbaser(struct host_its *its) * If the command queue memory is mapped as uncached, we need to flush * it on every access. */ - if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) + if ( MASK_EXTR(reg, GITS_BASER_INNER_CACHEABILITY_MASK) <= + GIC_BASER_CACHE_nC ) { its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); @@ -496,7 +497,8 @@ retry: } attr = regc & BASER_ATTR_MASK; } - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) + if ( MASK_EXTR(regc, GITS_BASER_INNER_CACHEABILITY_MASK) <= + GIC_BASER_CACHE_nC ) clean_and_invalidate_dcache_va_range(buffer, table_size); /* If the host accepted our page size, we are done. */ diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index de5052e5cf..9ee338edc2 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -351,7 +351,8 @@ static int gicv3_lpi_set_proptable(void __iomem * rdist_base) } /* Remember that we have to flush the property table if non-cacheable. */ - if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) + if ( MASK_EXTR(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= + GIC_BASER_CACHE_nC ) { lpi_data.flags |= LPI_PROPTABLE_NEEDS_FLUSHING; /* Update the redistributors knowledge about the attributes. */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 10 17:41:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 17:41:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279658.1563975 (Exim 4.92) (envelope-from ) id 1wBFrR-0004CA-Qz; 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> > boot_clock_cycles = get_cycles(); > + > + /* set_xen_timer must have been set by sbi_init() already */ > + ASSERT(set_xen_timer); > + > + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) > + { > + set_xen_timer = sstc_set_xen_timer; > + > + /* > + * A VS-timer interrupt becomes pending whenever the value of > + * (time + htimedelta) is greater than or equal to vstimecmp CSR. > + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to > + * ULONG_MAX. > + */ > + csr_write(CSR_VSTIMECMP, ULONG_MAX); > +#ifdef CONFIG_RISCV_32 > + csr_write(CSR_VSTIMECMPH, ULONG_MAX); > +#endif You've got this pattern twice in this patch alone, and these aren't the only CSRs which are formed of pairs to get a 64bit value in 32bit mode. Sadly, the numbering isn't consistent for the high constant, but we can let the compiler do most of the hard work for us. #ifdef CONFIG_RISCV_32 # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) #else # define __csr_write32h(csr, val) (void)(csr, val) #endif #define csr_write64(csr, val) ({     uint64_t _v = (val);     csr_write(csr, _v);     __csr_write32h(csr, _v); }) will get you a csr_write64(CSR_FOO, bar) which does the right thing on 32bit mode. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 10 20:18:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 10 Apr 2026 20:18:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1279759.1563984 (Exim 4.92) (envelope-from ) id 1wBIIo-00053q-HY; Fri, 10 Apr 2026 20:18:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1279759.1563984; Fri, 10 Apr 2026 20:18:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBIIo-00053j-Eq; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bR36BRALjcUs3Tls" Content-Disposition: inline In-Reply-To: <20260410150333.1533568-1-thierry.escande@vates.tech> X-purgate-ID: tlsNG-33051d/1775852284-C8530C9A-8A5E50DB/0/0 X-purgate-type: clean X-purgate-size: 4624 --bR36BRALjcUs3Tls Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Fri, 10 Apr 2026 22:17:58 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Thierry Escande Cc: xen-devel@lists.xenproject.org, Anthony PERARD , Juergen Gross , Daniel P =?utf-8?B?LiBCZXJyYW5nw6k=?= Subject: Re: [RFC PATCH v3 0/3] xl: Allow PCI devices to be passthrough'd via Qemu command line On Fri, Apr 10, 2026 at 03:03:45PM +0000, Thierry Escande wrote: > This series adds support for a new 'hotplug' option for PCI devices to be > passthrough'd to guests. >=20 > The current mechanism for device passthrough uses QMP device_add command > to hot-plug PCI devices to the guest Qemu instance. This is an issue for > guests running on Q35 chipset (preliminary support posted at [1]) since t= he > Q35 PCI root bus does not support hotplug. Devices could be hotplugged to > a secondary PCI bus but Xen only support 1 PCI bus for now. >=20 > The 'hotplug' option allows to control how devices are attached to the > guest, either by using the legacy QMP mechanism (this is the default) or = by > passing it directly to the Qemu command line using xen-pci-passthrough > device. >=20 > Example usage in cfg file: > pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] >=20 > Since Qemu -device option accepts parameters in json format, this > patchset adds a new internal function libxl__device_pci_get_qmp_json() th= at > generates the device json object used for both QMP hotplug and command li= ne > passing. >=20 > Also, to handle the assignable PCI device list, the function > libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and is > made available from libxl.h for access in libxl_dm.c. 2 other functions a= re > also exported internally: libxl__pciback_dev_is_assigned() and > libxl__device_pci_assignable_add(). >=20 > This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running > Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. > Disabling the hotplug mechanism might be made mandatory for Q35 machines > later, once Q35 support is merged upstream. >=20 > [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.esc= ande@vates.tech/ Much better now: https://gitlab.com/xen-project/people/marmarek/xen/-/pipelines/2444612680 I get now something like this: libxl: debug: libxl_dm.c:3044:device_model_launch: Domain 1: -device libxl: debug: libxl_dm.c:3044:device_model_launch: Domain 1: {"driver":"xe= n-pci-passthrough","id":"pci-pt-03_00.0","hostaddr":"0000:03:00.0"} So, it works :) > Changes in v2: > - Add support for YAJL json parser >=20 > Changes in v3: > - Move code block of device command line parameters creation > - Better handling of pci device assignation >=20 > Thierry Escande (3): > xl: Add pci device hotplug option > libxl: Allow PCI device passthrough using -device Qemu command line > docs: provide description for pci hotplug option >=20 > docs/man/xl-pci-configuration.5.pod | 17 ++++++ > docs/man/xl.cfg.5.pod.in | 6 ++ > tools/include/libxl.h | 1 + > tools/libs/light/libxl_dm.c | 85 +++++++++++++++++++++++++++++ > tools/libs/light/libxl_internal.h | 7 +++ > tools/libs/light/libxl_pci.c | 57 +++++++++++++------ > tools/libs/light/libxl_types.idl | 1 + > tools/libs/util/libxlu_pci.c | 2 + > tools/xl/xl_parse.c | 5 ++ > 9 files changed, 163 insertions(+), 18 deletions(-) >=20 > --=20 > 2.53.0 >=20 >=20 >=20 > -- > Thierry Escande | Vates XCP-ng Developer >=20 > XCP-ng & Xen Orchestra - Vates solutions >=20 > web: https://vates.tech >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --bR36BRALjcUs3Tls Content-Type: application/pgp-signature; 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charset=US-ASCII X-purgate-ID: tlsNG-d25034/1775858758-FEB4CA3D-40A19CD7/0/0 X-purgate-type: clean X-purgate-size: 2576 On Fri, 10 Apr 2026, Oleksii Kurochko wrote: > Hi all, > > While working on dom0less guest FDT construction I noticed that > fdt_generate_phandle() is "broken" when used to generate phandles for a > guest's nodes. The root cause is the way dom0less manages phandle_intc > (phandle_gic in Arm terminology): the dummy GIC node already occupies a > phandle in pfdt, but fdt_generate_phandle(kinfo->fdt, ...) has no visibility > into pfdt and therefore may produce a phandle that collides with phandle_intc. > > I see three potential approaches to fix this and would like to get the > community's feedback before going further. > > **Option 1: guest_fdt_generate_phandle() wrapper** > > Introduce a thin wrapper that skips any phandle already reserved by the > architecture: > > int guest_fdt_generate_phandle(const struct kernel_info *kinfo, uint32_t > *phandle) > { > int res; > > res = fdt_generate_phandle(kinfo->fdt, phandle); > > if ( *phandle == kinfo->phandle_intc ) > (*phandle)++; > > return res; > } > > The obvious downside is that this is not flexible: every future node added to > pfdt would require a corresponding fixup here, which is easy to forget and > hard to maintain. > > **Option 2: Reserve a "first free phandle" field in the arch-specific > structure** > > Add a field to the arch-specific part of struct kernel_info that stores the > first phandle number guaranteed not to be used by pfdt. Guest phandle > allocation would then start from (and increment) this field, completely > avoiding the pfdt phandle space. > > This is cleaner than Option 1 but requires careful initialisation and > documentation to make sure the field is always set before it is consumed. > > **Option 3: Store a pfdt pointer in struct kernel_info** > > Add a `pfdt` pointer to struct kernel_info and pass it to > fdt_generate_phandle() whenever a guest phandle is needed: > > fdt_generate_phandle(kinfo->pfdt, ...) > > Because fdt_generate_phandle() walks the target FDT to find the highest > existing phandle and returns the next free one, using pfdt as the source of > truth guarantees uniqueness across both pfdt and the guest FDT, without any > manual bookkeeping. > > This feels like the most robust option to me, since it naturally handles any > future nodes added to pfdt without requiring changes to the phandle allocation > logic. > > Does anyone see issues with Option 3? Are there other approaches worth > considering? Option 3 looks decent From xen-devel-bounces@lists.xenproject.org Sun Apr 12 06:22:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 12 Apr 2026 06:22:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280512.1564003 (Exim 4.92) (envelope-from ) id 1wBoCq-0003vg-Uu; Sun, 12 Apr 2026 06:22:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280512.1564003; Sun, 12 Apr 2026 06:22:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBoCq-0003vS-OO; Sun, 12 Apr 2026 06:22:04 +0000 Received: by outflank-mailman (input) for mailman id 1280512; Sun, 12 Apr 2026 06:22:04 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wBoCq-0003vM-9j for xen-devel@lists.xenproject.org; Sun, 12 Apr 2026 06:22:04 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wBoCp-00H2YG-HR for xen-devel@lists.xenproject.org; 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Sun, 12 Apr 2026 06:22:02 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id H0lPIwo622lXRwAAD6G6ig (envelope-from ); Sun, 12 Apr 2026 06:22:02 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1775974922; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H4/EmGHaKtwX8U/Zwd5I44YWhwveUA/5hxSsrtYHhwM=; b=pgVKMgQchlrVfbdt6+ZXr36GRlWGA7G5oY5VHCXndLbIXYN93gfDVzJMdEIdEtVQ3gXG07 ZAJdIsSkcdde63Z6vHPeF8hYi3ngUtALhKadkLfEyK4L/3/rdLYKT+P9zZVZ7DNj+6KKeV napuqvs3RZiBuoY04CLnHGmY02Ml3kg= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1775974922; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=H4/EmGHaKtwX8U/Zwd5I44YWhwveUA/5hxSsrtYHhwM=; b=pgVKMgQchlrVfbdt6+ZXr36GRlWGA7G5oY5VHCXndLbIXYN93gfDVzJMdEIdEtVQ3gXG07 ZAJdIsSkcdde63Z6vHPeF8hYi3ngUtALhKadkLfEyK4L/3/rdLYKT+P9zZVZ7DNj+6KKeV napuqvs3RZiBuoY04CLnHGmY02Ml3kg= From: Juergen Gross To: torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, sstabellini@kernel.org Subject: [GIT PULL] xen: branch for v7.1-rc1 Date: Sun, 12 Apr 2026 08:22:02 +0200 Message-ID: <20260412062202.627248-1-jgross@suse.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[99.99%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,imap1.dmz-prg2.suse.org:helo]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; TO_DN_NONE(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: X-purgate-ID: tlsNG-720697/1775974923-47F29CD1-04F8C777/0/0 X-purgate-type: clean X-purgate-size: 1427 Linus, Please git pull the following tag: git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-7.1-rc1-tag xen: branch for v7.1-rc1 It contains: - a fix of an error path in drivers/xen/manage.c - a fix for the Xen console driver solving a boot hangup when the console backend isn't yet running - a comment fix in the Xen swiotlb driver - a hardening patch for Xen on Arm adding a more thorough validation - a cleanup of the Xen grant table code hiding suspend/resume code for the case if CONFIG_HIBERNATE_CALLBACKS isn't defined Thanks. Juergen arch/arm/xen/enlighten.c | 10 ++++++---- drivers/tty/hvc/hvc_xen.c | 3 +++ drivers/xen/grant-table.c | 3 ++- drivers/xen/manage.c | 20 +++++++++++++++++--- drivers/xen/swiotlb-xen.c | 2 +- include/xen/grant_table.h | 12 ++++++++++++ include/xen/interface/io/console.h | 13 +++++++++++++ 7 files changed, 54 insertions(+), 9 deletions(-) GuoHan Zhao (1): xen/manage: unwind partial shutdown watcher setup on error Jason Andryuk (1): hvc/xen: Check console connection flag Kexin Sun (1): xen/swiotlb: fix stale reference to swiotlb_unmap_page() Pengpeng Hou (2): ARM: xen: validate hypervisor compatible before parsing its version xen/grant-table: guard gnttab_suspend/resume with CONFIG_HIBERNATE_CALLBACKS From xen-devel-bounces@lists.xenproject.org Mon Apr 13 08:44:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 08:44:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280933.1564015 (Exim 4.92) (envelope-from ) id 1wCCtf-0006k7-J8; Mon, 13 Apr 2026 08:43:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280933.1564015; Mon, 13 Apr 2026 08:43:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCCtf-0006k0-Fu; Mon, 13 Apr 2026 08:43:55 +0000 Received: by outflank-mailman (input) for mailman id 1280933; Mon, 13 Apr 2026 08:43:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCCte-0006ju-Jn for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 08:43:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCCtd-00Bb9a-SS for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 10:43:53 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69dcacc7-bab6-0a2a0a5309dd-0a2a450495c4-10 for ; Mon, 13 Apr 2026 10:43:53 +0200 Received: from [209.85.221.49] (helo=mail-wr1-f49.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dcacc9-bb33-0a2a45040019-d155dd31c52f-3 for ; Mon, 13 Apr 2026 10:43:53 +0200 Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-43d572f7437so2632765f8f.1 for ; Mon, 13 Apr 2026 01:43:53 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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No real need, I will drop. > >> + int res = 0; >> + void *fdt = kinfo->fdt; >> + >> + res = imsic_make_dt_node(kinfo); >> + if ( res ) >> + return res; >> + >> + res = fdt_begin_node(fdt, aplic_node->full_name); >> + if (res) > > Nit: Style. > >> + return res; >> + >> + data = dt_get_property(aplic_node, "#interrupt-cells", &len); >> + if ( !data ) >> + { >> + printk("%s: Can't find '#interrupt-cells' property\n", >> + aplic_node->full_name); >> + return -FDT_ERR_XEN(ENOENT); >> + } > > Again, pull this up to be first in the function? Agree, it makes sense to move it up. > >> + res = fdt_property(fdt, "#interrupt-cells", data, len); >> + if ( res ) >> + return res; > > So host properties are again directly handed through to the guest? I am not sure that it can be different from what host has. > Shouldn't the number of interrupts (aiui that's the "number of cells" > here) a guest gets be independent from the host it runs one? The #interrupt-cells property specifies how many 32-bit values (cells) are used to encode a single interrupt specifier when referencing this interrupt controller from another device node. In this APLIC schema, it's fixed at const: 2, meaning every interrupt reference requires exactly two cells — typically: Cell 1 — the interrupt source number (which of the riscv,num-sources wired inputs) Cell 2 — the interrupt type/trigger flags (e.g. edge vs. level, active high/low) So when a device node writes something like interrupts = <42 1>, the interrupt controller knows to interpret that as "source 42, trigger type 1" because #interrupt-cells = <2> told it to consume two cells per specifier. > >> + regs = dt_get_property(aplic_node, "reg", &len); >> + if ( !regs ) >> + { >> + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); >> + return -FDT_ERR_XEN(ENOENT); >> + } >> + >> + res = fdt_property(fdt, "reg", regs, len); >> + if ( res ) >> + return res; >> + >> + data = dt_get_property(aplic_node, "riscv,num-sources", &len); >> + if ( !data ) >> + { >> + printk("%s: Can't find 'riscv,num-sources' property\n", >> + aplic_node->full_name); >> + return -FDT_ERR_XEN(ENOENT); >> + } >> + >> + res = fdt_property(fdt, "riscv,num-sources", data, len); >> + if ( res ) >> + return res; > > Or maybe this is the number of interrupts? This is the total count of hardware interrupt lines wired into this APLIC domain. It could be independent from the host it runs one but looking at the possible range [1,1023] for this property if we will put for a guest lets say 22 but new host support only 20 when we will be in a trouble anyway. It seems like it is another one thing where it will be needed to check that new host has enough number of interrupts and then just deny migration to such host. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 13 08:48:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 08:48:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280945.1564024 (Exim 4.92) (envelope-from ) id 1wCCyT-0007Kg-4w; Mon, 13 Apr 2026 08:48:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280945.1564024; Mon, 13 Apr 2026 08:48:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCCyT-0007KZ-1u; Mon, 13 Apr 2026 08:48:53 +0000 Received: by outflank-mailman (input) for mailman id 1280945; Mon, 13 Apr 2026 08:48:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCCyS-0007KT-FQ for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 08:48:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCCyR-00Bcm9-R8 for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 10:48:51 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69dcadf1-2eae-0a2a0a5409dd-0a2a45048b8c-6 for ; Mon, 13 Apr 2026 10:48:51 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dcadf3-bb33-0a2a45040019-d1558030dd26-3 for ; Mon, 13 Apr 2026 10:48:51 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4887f49ec5aso51009365e9.1 for ; Mon, 13 Apr 2026 01:48:51 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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But on other hand, there are several time used the same construction dt_get_propety() from host aplic node then write this property to guest aplic node, then maybe we want to keep this dt_get_property(aplic_node, "#interrupt-cells", &len); where it is now to have the same visually construction way of guest device tree properties. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 13 08:49:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 08:49:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280953.1564033 (Exim 4.92) (envelope-from ) id 1wCCyu-0007lU-Cc; Mon, 13 Apr 2026 08:49:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280953.1564033; Mon, 13 Apr 2026 08:49:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 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b=SappMDnzg3VDOWsirSnEghBMzgCClHp29eV0PqenPVKs/oORDTbbnvX69NZk2yC1iXPkU697ivw9toOk7V+9wvFWolai4cAdktE2PWKaQj+2JrVfFZhKf2k/7QMdhntwYJ+GqdDRcj2N2Mpv1f5mWG/+XoehpHTNTQpKHuhFq14= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Message-ID: <9cd3e2f1-1b6f-4946-86c2-ff72f34ba138@amd.com> Date: Mon, 13 Apr 2026 11:28:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm/gicv3: Decode cacheability fields before comparing To: Mykola Kvach , CC: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Mykyta Poturai References: <7c20230fcd388ebe398ce19a21a1cd3c2c73d5fa.1775839987.git.mykola_kvach@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <7c20230fcd388ebe398ce19a21a1cd3c2c73d5fa.1775839987.git.mykola_kvach@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|CH0PR12MB8552:EE_ X-MS-Office365-Filtering-Correlation-Id: 934dee65-422f-4468-c043-08de993f0c38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 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CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cotAGUNJafk1rHFX2e+If0Sejl7Eg7cwoCJT0fgCxSJ9D3byp1Ld290NtKbsoz32IhhN0A9pGMpi1LoKbLJq8UI15rWEVsppZCdRmIW15zDUQNsSDzn91uMDC0PUk1eAXhuu6K5qRRyrQ2VGpk+Goiq4iKM7VYwt7wa/Lvhs5/oQy9lQptzExpMxXAqep3iLpq5h0V+AKQp/8Mb+6XLguBgFlnN/UX28W79RQhBnBFpr2IJPqp6hHtu9BnaE39TWA/DuhUUueC7HN3eZsExEP090QEIN+frKCzH23mDvPNYFex7thU5nKTwLYPFEuoZ4uX3fXSw84ETxFspVCyN/y5g/uFQpoqVjCDYPfMXeFu+fxUmj9dMDLKSBfyY5/puPofpgXhnAiHidSBfMCliTckuuDgtYJJCSi/fLFtGTyi4/4KRxey08Ah1eMC0LWVEw X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 09:28:39.9337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 934dee65-422f-4468-c043-08de993f0c38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8552 X-purgate-ID: tlsNG-c201ff/1776072526-3093196F-7FF54ED5/0/0 X-purgate-type: clean X-purgate-size: 3521 On 10/04/2026 19:34, Mykola Kvach wrote: > From: Mykola Kvach > > GITS_BASER_INNER_CACHEABILITY_MASK and > GICR_PROPBASER_INNER_CACHEABILITY_MASK are shifted masks. Comparing the > masked but unshifted values against GIC_BASER_CACHE_nC, which is an > unshifted enum value, leads to incorrect detection of non-cacheable > GITS_CBASER command queue, GITS_BASER tables, and GICR_PROPBASER > mappings. > > Use MASK_EXTR() to decode these cacheability fields before comparing > against GIC_BASER_CACHE_nC, so the backing memory is flushed when > required. > > Fixes: 8ed8d21373be ("ARM: GICv3 ITS: map ITS command buffer") > Fixes: 05238012b86d ("ARM: GICv3 ITS: allocate device and collection table") > Fixes: c9b939863c89 ("ARM: GICv3: allocate LPI pending and property table") > Signed-off-by: Mykyta Poturai > Signed-off-by: Mykola Kvach > --- > Changes in v2: > - use MASK_EXTR() instead of open-coding the BASER field shift > - fix the analogous PROPBASER cacheability comparison in > gicv3_lpi_set_proptable() > - fix the CBASER command queue cacheability check as well > --- > xen/arch/arm/gic-v3-its.c | 6 ++++-- > xen/arch/arm/gic-v3-lpi.c | 3 ++- > 2 files changed, 6 insertions(+), 3 deletions(-) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index 9ba068c46f..e87465d2ff 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -424,7 +424,8 @@ static void *its_map_cbaser(struct host_its *its) > * If the command queue memory is mapped as uncached, we need to flush > * it on every access. > */ > - if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) You don't seem to mention this change. This one does not compare to GIC_BASER_CACHE_nC and checks against 0, which means we are on the safe side. If you still want to change it, then you should also look few lines above where we have: if ( (reg & GITS_BASER_SHAREABILITY_MASK) == 0 ) > + if ( MASK_EXTR(reg, GITS_BASER_INNER_CACHEABILITY_MASK) <= > + GIC_BASER_CACHE_nC ) This is a functional change. Previously we where comparing against 0 and now you compare against <= 1 ~Michal > { > its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; > printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); > @@ -496,7 +497,8 @@ retry: > } > attr = regc & BASER_ATTR_MASK; > } > - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) > + if ( MASK_EXTR(regc, GITS_BASER_INNER_CACHEABILITY_MASK) <= > + GIC_BASER_CACHE_nC ) > clean_and_invalidate_dcache_va_range(buffer, table_size); > > /* If the host accepted our page size, we are done. */ > diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c > index de5052e5cf..9ee338edc2 100644 > --- a/xen/arch/arm/gic-v3-lpi.c > +++ b/xen/arch/arm/gic-v3-lpi.c > @@ -351,7 +351,8 @@ static int gicv3_lpi_set_proptable(void __iomem * rdist_base) > } > > /* Remember that we have to flush the property table if non-cacheable. */ > - if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) > + if ( MASK_EXTR(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK) <= > + GIC_BASER_CACHE_nC ) > { > lpi_data.flags |= LPI_PROPTABLE_NEEDS_FLUSHING; > /* Update the redistributors knowledge about the attributes. */ From xen-devel-bounces@lists.xenproject.org Mon Apr 13 09:32:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 09:32:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280980.1564051 (Exim 4.92) (envelope-from ) id 1wCDet-00061R-OD; Mon, 13 Apr 2026 09:32:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280980.1564051; Mon, 13 Apr 2026 09:32:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCDet-00061K-KU; Mon, 13 Apr 2026 09:32:43 +0000 Received: by outflank-mailman (input) for mailman id 1280980; Mon, 13 Apr 2026 09:32:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCDer-00061E-RM for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 09:32:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCDer-00Bp7w-3c for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 11:32:41 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69dcb834-5cb7-0a2a0a5109dd-0a2a4501df0a-42 for ; Mon, 13 Apr 2026 11:32:41 +0200 Received: from [209.85.221.42] (helo=mail-wr1-f42.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dcb838-6fc9-0a2a45010019-d155dd2aede8-3 for ; Mon, 13 Apr 2026 11:32:41 +0200 Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-43cff5dafc3so3002955f8f.1 for ; Mon, 13 Apr 2026 02:32:41 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Nor can aia_available() be a convenience > wrapper around that call? It's only ... > >> --- /dev/null >> +++ b/xen/arch/riscv/aia.c >> @@ -0,0 +1,25 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +static bool __ro_after_init is_aia_available; > > ... a boolean, yes, but still. My purpose was to have a variable which represent that AIA is initialized properly. Maybe, it makes sense to rename this variable to is_aia_inited. The idea is that in future patches VGEIN will be also initialized in aia_init() and if wasn't initialized properly then just keep is_aia_availabe be set to false and in such case we will have that is_aia_available != riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia). Note that regarding VGEIN it is arguable that it should be initialized as generally it could be that there is no VGEIN what means that h/w assisted guest interrupt files aren't available and s/w one should be used. But s/w guest interrupt files aren't supported. So I mean that with the current implementation if VGEIN isn't initialized I will tell that AIA isn't available what generally isn't quite true. > >> +bool aia_available(void) >> +{ >> + return is_aia_available; >> +} >> + >> +int __init aia_init(void) >> +{ >> + if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) >> + return -ENODEV; >> + >> + is_aia_available = true; >> + >> + return 0; >> +} > > Why the return value, when ... > >> --- a/xen/arch/riscv/intc.c >> +++ b/xen/arch/riscv/intc.c >> @@ -8,6 +8,7 @@ >> #include >> #include >> >> +#include >> #include >> >> static const struct intc_hw_operations *__ro_after_init intc_hw_ops; >> @@ -27,6 +28,8 @@ void __init intc_preinit(void) >> >> void __init intc_init(void) >> { >> + aia_init(); > > ... the sole caller doesn't care? Good point. I think it should return nothing as probably it is just another interrupt controller (PLIC) is going to be used. Also, I thought if aia_init() should be called inside at the start of aplic_preinit(). It looks a little bit incorrect as APLIC is just a part of AIA spec... Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 13 09:42:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 09:42:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1280989.1564059 (Exim 4.92) (envelope-from ) id 1wCDoE-0007ih-J4; Mon, 13 Apr 2026 09:42:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1280989.1564059; Mon, 13 Apr 2026 09:42:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCDoE-0007ia-GE; Mon, 13 Apr 2026 09:42:22 +0000 Received: by outflank-mailman (input) for mailman id 1280989; Mon, 13 Apr 2026 09:42:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCDoD-0007iU-UR for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 09:42:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCDoA-002JN6-T4 for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YU4lJNFs88W/rGQqMzu5Le6WfPbF9BydeU83ygvZwrMCeZYfbiyBldsv/kdu1/+vk4bQHv/Pb5NByUCxujhkyQix7HtZccOhfyJpKIn0o8wJloY/3OV5FzDV8jUmf42+4ovQwpJUKw9Z4AXOpzIXEv/FSIF/x7A3gewE28M/d8PQ+QrzOWwcM8Mo6U/Slu845g546moXriXeDBLXuMs/0aY9rG9PegnOffGOLIBG8821EYdPskqodS4ie5IsKYiUHKOqyQcCJEsvbgqzYWyanXPbhnRLRWBH9/di9SU9VS62IzRe4p/Gcit/Zqnbq6yogoqKOwZmI5K5zwkV+Z8oqRv8Gw1Ev0o9kUn8uJ2UpS0vQHGQjCiWxiE0NNhnjkLANNBwjEOAyxsKfPO7iBQZ1LozMvDfrM3HnEM13locnk43n8cqxXN/ftgPNz8iy96v X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 09:42:11.3047 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 784e2231-9c7d-4e46-3ac3-08de9940efcf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7587 X-purgate-ID: tlsNG-720697/1776073340-AD53CCD1-D31D7DB4/0/0 X-purgate-type: clean X-purgate-size: 4717 On 08/04/2026 15:55, Luca Fancellu wrote: > From: Penny Zheng > > Implement setup_virt_paging for aarch64 MPU systems, taking tare of > stage 2 address translation regime, IPA bits, supported VMID length > configuration and vtcr_el2/vstcr_el2 register programming. > > Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, > related to the supported memory system architecture (PMSA/VMSA) > and check that when MPU is built, the underlying HW is compatible > with PMSA. By default MPU at EL2 and EL1 is required. > > Signed-off-by: Penny Zheng > Signed-off-by: Wei Chen > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye > Signed-off-by: Harry Ramsey > --- > v3: > - Refactor unused code to more relevant commits. > - Add P2M print information > - Formatting issues > - Update commit message > v2: > - Seperate commit into multiple commits > --- > xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- > xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ > xen/arch/arm/include/asm/cpufeature.h | 13 +++- > xen/arch/arm/include/asm/processor.h | 8 +++ > 4 files changed, 101 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c > index b6d8b2777b58..fda512dc7c8f 100644 > --- a/xen/arch/arm/arm64/mpu/p2m.c > +++ b/xen/arch/arm/arm64/mpu/p2m.c > @@ -2,11 +2,89 @@ > > #include > #include > +#include > #include > > void __init setup_virt_paging(void) > { > - BUG_ON("unimplemented"); > + register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); > + register_t vstcr_el2 = READ_SYSREG(VSTCR_EL2); > + > + /* PA size */ > + const unsigned int pa_range_info[] = {32, 36, 40, 42, 44, 48, 52, 0, > + /* Invalid */}; > + > + /* > + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured > + * with IPA bits == PA bits, compare against "pabits". > + */ > + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) > + p2m_ipa_bits = pa_range_info[system_cpuinfo.mm64.pa_range]; > + > + /* > + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identify the > + * memory system configurations supported. In Armv8-R AArch64, the > + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. > + */ > + if ( system_cpuinfo.mm64.msa != MM64_MSA_PMSA_SUPPORT ) > + goto fault; > + > + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b0010. */ > + if ( (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_PMSA_SUPPORT) && > + (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_VMSA_SUPPORT) ) > + goto fault; > + > + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ > + vtcr_el2 &= ~VTCR_MSA; > + > + /* > + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation output > + * address space to access the Secure PA space as Armv8r only implements > + * secure state. > + */ > + vtcr_el2 &= ~VTCR_NSA; > + > + /* > + * cpuinfo sanitization makes sure we support 16bits VMID only if all cores > + * are supporting it. > + * > + * Set the VS bit only if 16 bit VIMD is supported. > + */ > + if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) > + { > + vtcr_el2 |= VTCR_VS; > + max_vmid = MAX_VMID_16_BIT; > + } > + else > + vtcr_el2 &= ~VTCR_VS; This is the last change to vtcr_el2. Why do you put p2m_vmid_allocator_init() in-between this and write to vtcr_el2 register? It looks odd. > + > + p2m_vmid_allocator_init(); > + > + WRITE_SYSREG(vtcr_el2, VTCR_EL2); > + > + /* > + * VSTCR_EL2.SA defines secure stage 2 translation output address space. > + * To make sure that all stage 2 translations for the Secure PA space access > + * the Secure PA space, we keep SA bit as 0. > + * > + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS > + * configuration is checked against stage 1 NS configuration in EL1&0 > + * translation regime for the given address, and generates a fault if they > + * are different, we set SC bit 1. > + */ > + vstcr_el2 &= ~VSTCR_EL2_SA; > + vstcr_el2 |= VSTCR_EL2_SC; > + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); > + > + printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", All these are unsigned, so %u. ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 13 09:50:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 09:50:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281000.1564068 (Exim 4.92) (envelope-from ) id 1wCDvk-00013K-Cn; Mon, 13 Apr 2026 09:50:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281000.1564068; Mon, 13 Apr 2026 09:50:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCDvk-00013D-9t; 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b=S5/g2k1cSG6B1oMTai6KvJ+lKpffExwiNDdn35K4n7FdS+N6jRs9tTwfWdSlTcagHIpinMGdm3yA3BLrbFWSi15ohS+Oi7XF5Cc1YadgVrhyr2mwD3IyY0byDBDDmjCpA/zUz6LZaA45y3rTnaLaPH1G2GGEvX7wTv/x6zHwzdg= From: Luca Fancellu To: Milan Djokic CC: "xen-devel@lists.xenproject.org" , Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: Re: [PATCH v3 10/23] xen/arm: vsmmuv3: Add support for command CMD_CFGI_STE Thread-Topic: [PATCH v3 10/23] xen/arm: vsmmuv3: Add support for command CMD_CFGI_STE Thread-Index: AQHcyyq6FXO6ijWppkGjD9BdYA/62A== Date: Mon, 13 Apr 2026 09:48:49 +0000 Message-ID: <7A296EE6-042F-43B6-A6A8-9BC4408AE605@arm.com> References: <5342a5355191ae3b5b7bfcb86c6494334dda82e6.1774918270.git.milan_djokic@epam.com> In-Reply-To: <5342a5355191ae3b5b7bfcb86c6494334dda82e6.1774918270.git.milan_djokic@epam.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3826.700.81.1.6) Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Tk6ExQUoVq38NSfqM0U0bfaA6OWwBMW2bssWice+chvLk18JcvmvxJbacIETpYX0xK+uXex6iU/jd8Iru+i/SdFm9l+teUjlcoxGyKhw43dQ6N1R77qoLRzntBHEWb2NK27CSSX5T3Nvd1tuV9CNdq5XLm32w5mALMNRMqBtzvIZT3tjIc+9lt/u6OK86O37Ox7cevlw8/LjAc5nQsG0h15fGAlx72frAKJcP5oBT1U6G0v+/ZQhr9WP/JBVcxZxJoqHRoTg7SsScVtrgTJ3RfKpiQF/2aFOuGVUol1Uo7Qpyctxwlz+tS/vzTaXf25cbsL3AdY7TUAF2e1rQUs/4uR/SDFNeGIP9MgZEA3f7ojbV3kvgQ+pVI6TM1yDIhkK+j/TWypLmFzruKkaMf1PhRHVcyneV4Ac6L7eAsSRZHY+BemPcJSK7JCBuE6pSivk X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 09:50:01.6335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83633dbd-c22d-412d-7496-08de9942082f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509E8.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR08MB8916 X-purgate-ID: tlsNG-33051d/1776073805-47B2BC9A-66E415BC/0/0 X-purgate-type: clean X-purgate-size: 6329 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > CMD_CFGI_STE is used to invalidate/validate the STE. Emulated vSMMUv3 > driver in XEN will read the STE from the guest memory space and capture > the Stage-1 configuration required to support nested translation. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/drivers/passthrough/arm/vsmmu-v3.c | 148 +++++++++++++++++++++++++ > 1 file changed, 148 insertions(+) >=20 > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthr= ough/arm/vsmmu-v3.c > index 02fe6a4422..39ed4dc577 100644 > --- a/xen/drivers/passthrough/arm/vsmmu-v3.c > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -45,6 +45,21 @@ extern const struct viommu_desc __read_mostly *cur_vio= mmu; > /* Helper Macros */ > #define smmu_get_cmdq_enabled(x) FIELD_GET(CR0_CMDQEN, x) > #define smmu_cmd_get_command(x) FIELD_GET(CMDQ_0_OP, x) > +#define smmu_cmd_get_sid(x) FIELD_GET(CMDQ_PREFETCH_0_SID, x) Was CMDQ_CFGI_0_SID intended here? we use it in arm_vsmmu_handle_cfgi_ste() > +#define smmu_get_ste_s1cdmax(x) FIELD_GET(STRTAB_STE_0_S1CDMAX, x) > +#define smmu_get_ste_s1fmt(x) FIELD_GET(STRTAB_STE_0_S1FMT, x) > +#define smmu_get_ste_s1stalld(x) FIELD_GET(STRTAB_STE_1_S1STALLD, x) > +#define smmu_get_ste_s1ctxptr(x) FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MAS= K, \ > + FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK= , x)) > + > +/* stage-1 translation configuration */ > +struct arm_vsmmu_s1_trans_cfg { > + paddr_t s1ctxptr; > + uint8_t s1fmt; > + uint8_t s1cdmax; > + bool bypassed; /* translation is bypassed */ > + bool aborted; /* translation is aborted */ > +}; >=20 > /* virtual smmu queue */ > struct arm_vsmmu_queue { > @@ -91,6 +106,138 @@ static void dump_smmu_command(uint64_t *command) > gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n", > smmu_cmd_get_command(command[0]), command[0], command[1]); > } > +static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid, > + uint64_t *ste) > +{ > + paddr_t addr, strtab_base; > + struct domain *d =3D smmu->d; > + uint32_t log2size; > + int strtab_size_shift; > + int ret; > + > + log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base_c= fg); > + > + if ( sid >=3D (1 << MIN(log2size, SMMU_IDR1_SIDSIZE)) ) > + return -EINVAL; > + > + if ( smmu->features & STRTAB_BASE_CFG_FMT_2LVL ) > + { > + int idx, max_l2_ste, span; > + paddr_t l1ptr, l2ptr; > + uint64_t l1std; > + > + strtab_size_shift =3D MAX(5, (int)log2size - smmu->sid_split - 1= + 3); > + strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK & > + ~GENMASK_ULL(strtab_size_shift, 0); > + idx =3D (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS; I think here we should shift by smmu->sid_split instead of STRTAB_SPLIT? > + l1ptr =3D (paddr_t)(strtab_base + idx * sizeof(l1std)); > + > + ret =3D access_guest_memory_by_gpa(d, l1ptr, &l1std, > + sizeof(l1std), false); > + if ( ret ) > + { > + gdprintk(XENLOG_ERR, > + "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); > + return ret; > + } > + > + span =3D FIELD_GET(STRTAB_L1_DESC_SPAN, l1std); > + if ( !span ) > + { > + gdprintk(XENLOG_ERR, "Bad StreamID span\n"); > + return -EINVAL; > + } > + > + max_l2_ste =3D (1 << span) - 1; > + l2ptr =3D FIELD_PREP(STRTAB_L1_DESC_L2PTR_MASK, > + FIELD_GET(STRTAB_L1_DESC_L2PTR_MASK, l1std)); > + idx =3D sid & ((1 << smmu->sid_split) - 1); > + if ( idx > max_l2_ste ) > + { > + gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n", > + idx, max_l2_ste); > + return -EINVAL; > + } > + addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS; > + } > + else > + { > + strtab_size_shift =3D log2size + 5; > + strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK & > + ~GENMASK_ULL(strtab_size_shift, 0); > + addr =3D strtab_base + sid * sizeof(*ste) * STRTAB_STE_DWORDS; > + } > + ret =3D access_guest_memory_by_gpa(d, addr, ste, sizeof(*ste), false= ); > + if ( ret ) > + { > + gdprintk(XENLOG_ERR, > + "Cannot fetch pte at address=3D0x%"PRIx64"\n", addr); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int arm_vsmmu_decode_ste(struct virt_smmu *smmu, uint32_t sid, > + struct arm_vsmmu_s1_trans_cfg *cfg, > + uint64_t *ste) > +{ > + uint64_t val =3D ste[0]; > + > + if ( !(val & STRTAB_STE_0_V) ) > + return -EAGAIN; > + > + switch ( FIELD_GET(STRTAB_STE_0_CFG, val) ) > + { > + case STRTAB_STE_0_CFG_BYPASS: > + cfg->bypassed =3D true; > + return 0; > + case STRTAB_STE_0_CFG_ABORT: > + cfg->aborted =3D true; > + return 0; > + case STRTAB_STE_0_CFG_S1_TRANS: > + break; > + case STRTAB_STE_0_CFG_S2_TRANS: > + gdprintk(XENLOG_ERR, "vSMMUv3 does not support stage 2 yet\n"); > + goto bad_ste; > + default: > + BUG(); /* STE corruption */ This will crash Xen based on the input of the guest, we should print someth= ing and jump to bad_ste instead, in my opinion. > + } > + > + cfg->s1ctxptr =3D smmu_get_ste_s1ctxptr(val); > + cfg->s1fmt =3D smmu_get_ste_s1fmt(val); > + cfg->s1cdmax =3D smmu_get_ste_s1cdmax(val); > + if ( cfg->s1cdmax !=3D 0 ) > + { > + gdprintk(XENLOG_ERR, > + "vSMMUv3 does not support multiple context descriptors\= n"); > + goto bad_ste; > + } > + > + return 0; > + > +bad_ste: NIT: code style, one space before labels Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 09:56:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 09:56:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281010.1564077 (Exim 4.92) (envelope-from ) id 1wCE1L-0001cW-Vc; Mon, 13 Apr 2026 09:55:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281010.1564077; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m4RmwV7Bi+FvYQpplOi6nLyuDLd9ye4V7YDqYv3xXuxr0MCj5aY2KwVrNBqIpxWB71wFwwdTvDsoptMIyCF7ge4oXMjH3l1Mo8LrkOfilzSCwYN5uHCtomTF/Fo4e4v5LmRt8T82Ev5xDN2lsEy+FMR3kj7PFiGyX3zDFbZ+UMB/D/zgZfnppn/ZJfY4ACj5zPbUk61b/u/sQwyBB2z5j5ivo8Lb4Olmjed1CPp+X7/axKZb4+fuVMK6XA/va/u9ouMwu7HRd3TN35IqfF371kkD1CcgtrQVyesMXHNl1wSRa/pV3czMF0DHbaJwzUspQTFLeOE6GAAWPQ9HPwUFicm9kEcQIWQh/fYYj0S4RGFgfQYhLV2Jscr/UloN+HNLkuPx2qaP27yD2M0LB/1atgiiRUm525yZn2J1oU5JKldq12q5Wi+9IAWJp6uKNOlp X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 09:55:48.5921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60c259d6-b6b5-4349-510a-08de9942d6fd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000A7DF.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB10337 X-purgate-ID: tlsNG-720697/1776074153-46B27CD1-4725C3EA/0/0 X-purgate-type: clean X-purgate-size: 3518 Hi Michal, >>=20 >> void __init setup_virt_paging(void) >> { >> - BUG_ON("unimplemented"); >> + register_t vtcr_el2 =3D READ_SYSREG(VTCR_EL2); >> + register_t vstcr_el2 =3D READ_SYSREG(VSTCR_EL2); >> + >> + /* PA size */ >> + const unsigned int pa_range_info[] =3D {32, 36, 40, 42, 44, 48, 52,= 0, >> + /* Invalid */}; >> + >> + /* >> + * Restrict "p2m_ipa_bits" if needed. As P2M table is always config= ured >> + * with IPA bits =3D=3D PA bits, compare against "pabits". >> + */ >> + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) >> + p2m_ipa_bits =3D pa_range_info[system_cpuinfo.mm64.pa_range]; >> + >> + /* >> + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register ide= ntify the >> + * memory system configurations supported. In Armv8-R AArch64, the >> + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. >> + */ >> + if ( system_cpuinfo.mm64.msa !=3D MM64_MSA_PMSA_SUPPORT ) >> + goto fault; >> + >> + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b= 0010. */ >> + if ( (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_PMSA_SUPPORT)= && >> + (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_VMSA_SUPPORT)= ) >> + goto fault; >> + >> + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ >> + vtcr_el2 &=3D ~VTCR_MSA; >> + >> + /* >> + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translati= on output >> + * address space to access the Secure PA space as Armv8r only imple= ments >> + * secure state. >> + */ >> + vtcr_el2 &=3D ~VTCR_NSA; >> + >> + /* >> + * cpuinfo sanitization makes sure we support 16bits VMID only if a= ll cores >> + * are supporting it. >> + * >> + * Set the VS bit only if 16 bit VIMD is supported. >> + */ >> + if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT= ) >> + { >> + vtcr_el2 |=3D VTCR_VS; >> + max_vmid =3D MAX_VMID_16_BIT; >> + } >> + else >> + vtcr_el2 &=3D ~VTCR_VS; > This is the last change to vtcr_el2. Why do you put p2m_vmid_allocator_in= it() > in-between this and write to vtcr_el2 register? It looks odd. ok I can have the write to the register before calling p2m_vmid_allocator_i= nit, in the end what matters is only to call p2m_vmid_allocator_init() after setting ma= x_vmid. >=20 >> + >> + p2m_vmid_allocator_init(); >> + >> + WRITE_SYSREG(vtcr_el2, VTCR_EL2); >> + >> + /* >> + * VSTCR_EL2.SA defines secure stage 2 translation output address s= pace. >> + * To make sure that all stage 2 translations for the Secure PA spa= ce access >> + * the Secure PA space, we keep SA bit as 0. >> + * >> + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 N= S >> + * configuration is checked against stage 1 NS configuration in EL1= &0 >> + * translation regime for the given address, and generates a fault = if they >> + * are different, we set SC bit 1. >> + */ >> + vstcr_el2 &=3D ~VSTCR_EL2_SA; >> + vstcr_el2 |=3D VSTCR_EL2_SC; >> + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); >> + >> + printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", > All these are unsigned, so %u. Oops, blindly copying from MMU code, I realise we have the issue also there Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 10:27:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 10:27:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281031.1564091 (Exim 4.92) (envelope-from ) id 1wCEVy-00068X-EY; Mon, 13 Apr 2026 10:27:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281031.1564091; Mon, 13 Apr 2026 10:27:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCEVy-00068Q-Bg; Mon, 13 Apr 2026 10:27:34 +0000 Received: by outflank-mailman (input) for mailman id 1281031; Mon, 13 Apr 2026 10:27:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCEVx-000673-4F for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: N1CxGByKa1Z8/q3JjoBaBRJ8w0YvEkXJTrP3qrxdYfbgO7i4S/YXtoC11FPSwrqiBH6clbtOlWePDi4k//uZIyOnTRnaiJUCgYagrF0fwotLVYZLfeVFO4GEzVeAzVQ3wk13Py/c8BByJKoMxg5gA3Vtnwc5dOh1I1KfiNgRbnz0orLdKezPOKxYQ7iYBmvAwxZAUaXzAsNZFw0mkf1sGWrmTwxaS6WFfPWLR21KELoPV7BKh3dUKFP+Mva9SdF6jmkNH5qXN08nKg3Qtoh7IxuQuGO6w36A+IrFlz0YVJWyDRsOrczhBXyTcuTLKxiM+9n93HT/w8rkDKMfzeoIAjpq1K3rv6A06v344JLa/ovyLVg3XzrR68WPqm4gwK/joT0bWcOZivY8jppIFgQT2K6VW7j7iju1FAPB/jwL5URoEs2kvbUEwd/jSKpIDWru X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 10:27:24.4187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5e29222-62e6-4b75-4fcb-08de994740fd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A6.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6106 X-purgate-ID: tlsNG-c1860d/1776076052-75557497-BF3F65D6/0/0 X-purgate-type: clean X-purgate-size: 5116 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > Attach the Stage-1 configuration to device STE to support nested > translation for the guests. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/arch/arm/include/asm/iommu.h | 7 +++ > xen/drivers/passthrough/arm/smmu-v3.c | 79 ++++++++++++++++++++++++++ > xen/drivers/passthrough/arm/smmu-v3.h | 1 + > xen/drivers/passthrough/arm/vsmmu-v3.c | 18 ++++++ > xen/include/xen/iommu.h | 6 ++ > 5 files changed, 111 insertions(+) >=20 > diff --git a/xen/arch/arm/include/asm/iommu.h b/xen/arch/arm/include/asm/= iommu.h > index ad15477e24..56bc9314a7 100644 > --- a/xen/arch/arm/include/asm/iommu.h > +++ b/xen/arch/arm/include/asm/iommu.h > @@ -20,6 +20,13 @@ struct arch_iommu > void *priv; > }; >=20 > +struct iommu_guest_config { > + paddr_t s1ctxptr; > + uint8_t config; > + uint8_t s1fmt; > + uint8_t s1cdmax; > +}; > + > const struct iommu_ops *iommu_get_ops(void); > void iommu_set_ops(const struct iommu_ops *ops); >=20 > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthro= ugh/arm/smmu-v3.c > index 87612df21d..cf8f638a49 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -2810,6 +2810,37 @@ static struct arm_smmu_device *arm_smmu_get_by_dev= (const struct device *dev) > return NULL; > } >=20 > +static struct iommu_domain *arm_smmu_get_domain_by_sid(struct domain *d, > + u32 sid) I think this might be wrong, a system can have multiple SMMU and the SID is= unique only on each SMMU, not on the overall platform, I think arm_smmu_attach_guest_co= nfig should pass also the smmu for the selected sid. > +{ > + int i; > + unsigned long flags; > + struct iommu_domain *io_domain; > + struct arm_smmu_domain *smmu_domain; > + struct arm_smmu_master *master; > + struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; > + > + /* > + * Loop through the &xen_domain->contexts to locate a context > + * assigned to this SMMU > + */ > + list_for_each_entry(io_domain, &xen_domain->contexts, list) { > + smmu_domain =3D to_smmu_domain(io_domain); > + > + spin_lock_irqsave(&smmu_domain->devices_lock, flags); > + list_for_each_entry(master, &smmu_domain->devices, domain_head) { > + for (i =3D 0; i < master->num_streams; i++) { > + if (sid !=3D master->streams[i].id) > + continue; > + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); > + return io_domain; > + } > + } > + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); > + } > + return NULL; > +} > + > static struct iommu_domain *arm_smmu_get_domain(struct domain *d, > struct device *dev) > { > @@ -3022,6 +3053,53 @@ static void arm_smmu_iommu_xen_domain_teardown(str= uct domain *d) > xfree(xen_domain); > } >=20 > +static int arm_smmu_attach_guest_config(struct domain *d, u32 sid, > + struct iommu_guest_config *cfg) > +{ > + int ret =3D -EINVAL; > + unsigned long flags; > + struct arm_smmu_master *master; > + struct arm_smmu_domain *smmu_domain; > + struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; > + struct iommu_domain *io_domain =3D arm_smmu_get_domain_by_sid(d, sid); > + > + if (!io_domain) > + return -ENODEV; > + > + smmu_domain =3D to_smmu_domain(io_domain); > + > + spin_lock(&xen_domain->lock); > + > + switch (cfg->config) { > + case ARM_SMMU_DOMAIN_ABORT: > + smmu_domain->abort =3D true; Shold we change also smmu_domain->stage here and ... > + break; > + case ARM_SMMU_DOMAIN_BYPASS: > + smmu_domain->abort =3D false; Here? I see arm_smmu_write_strtab_ent() uses it to select s1_cfg or s2_cfg configuration > + break; > + case ARM_SMMU_DOMAIN_NESTED: > + /* Enable Nested stage translation. */ > + smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED; > + smmu_domain->s1_cfg.s1ctxptr =3D cfg->s1ctxptr; > + smmu_domain->s1_cfg.s1fmt =3D cfg->s1fmt; > + smmu_domain->s1_cfg.s1cdmax =3D cfg->s1cdmax; > + smmu_domain->abort =3D false; > + break; > + default: > + goto out; > + } > + > + spin_lock_irqsave(&smmu_domain->devices_lock, flags); > + list_for_each_entry(master, &smmu_domain->devices, domain_head) > + arm_smmu_install_ste_for_dev(master); > + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); > + > + ret =3D 0; > +out: > + spin_unlock(&xen_domain->lock); > + return ret; > +} > + > static const struct iommu_ops arm_smmu_iommu_ops =3D { > .page_sizes =3D PAGE_SIZE_4K, > .init =3D arm_smmu_iommu_xen_domain_init, > @@ -3034,6 +3112,7 @@ static const struct iommu_ops arm_smmu_iommu_ops = =3D { > .unmap_page =3D arm_iommu_unmap_page, > .dt_xlate =3D arm_smmu_dt_xlate, > .add_device =3D arm_smmu_add_device, > + .attach_guest_config =3D arm_smmu_attach_guest_config > }; >=20 > static __init int arm_smmu_dt_init(struct dt_device_node *dev, Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 10:32:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 10:32:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281039.1564101 (Exim 4.92) (envelope-from ) id 1wCEaT-0007fJ-W6; Mon, 13 Apr 2026 10:32:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281039.1564101; Mon, 13 Apr 2026 10:32:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCEaT-0007fC-SE; Mon, 13 Apr 2026 10:32:13 +0000 Received: by outflank-mailman (input) for mailman id 1281039; Mon, 13 Apr 2026 10:32:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCEaT-0007f6-1L for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <81b7e58f-f004-4632-bc07-00f136d15029@amd.com> Date: Mon, 13 Apr 2026 12:28:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] arm/mpu: implement setup_virt_paging for MPU system To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Penny Zheng" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Wei Chen , Hari Limaye , Harry Ramsey References: <20260408135531.1744388-1-luca.fancellu@arm.com> <20260408135531.1744388-2-luca.fancellu@arm.com> <43fd7fd7-43dc-4c17-8ff6-b58800fd5f46@amd.com> <92DD0227-9023-4824-BB39-56E7F20F2F27@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <92DD0227-9023-4824-BB39-56E7F20F2F27@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFC:EE_|LV3PR12MB9187:EE_ X-MS-Office365-Filtering-Correlation-Id: 726a2388-7237-4b91-0290-08de99475890 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700016|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +c2ksASmmxpBU2Q7eO2SfqKyCEor9Z6MEr7AYWe4ILw1pRXeZxJhUQujf7Ud5TKpydmnCEI6usZfI0g+VAD7TodrPLHzkS5Vcp5hTsGdx2JmL6/UrpnYReOwv2L+X/9ZlSFsGx2Ktm7n7cmyXuHHrJuqJWlyzAvUp2Vu2etrq8mVdF0pYiLDh9v12yNZ3oGxWPdQrhR5pMIufYTWAI9VGwVFS+tQCvtqTXp9CF78UVROGeq/m//wDqAMe66KndMGmwxp3loX2s7HGC3pFk+JerrBtw4PO4xaN91iRKw65ybVVR8uFbtdS/FQcl40IB55/ghv/5D1pEziQkGroUSClAwTXLkznJYcZxPkTHwOrTQWBAHBsAujT8+5R1tuG6ZUMZnrbLqZr6G714tsa9QLFBk/aMsbdKV0OI99ZfEB3pWkByiuj64oZnF/QLd8kBi7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 10:28:04.0353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 726a2388-7237-4b91-0290-08de99475890 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9187 X-purgate-ID: tlsNG-d25034/1776076091-80B5CA3D-3503C446/0/0 X-purgate-type: clean X-purgate-size: 3682 On 13/04/2026 11:54, Luca Fancellu wrote: > Hi Michal, > >>> >>> void __init setup_virt_paging(void) >>> { >>> - BUG_ON("unimplemented"); >>> + register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); >>> + register_t vstcr_el2 = READ_SYSREG(VSTCR_EL2); >>> + >>> + /* PA size */ >>> + const unsigned int pa_range_info[] = {32, 36, 40, 42, 44, 48, 52, 0, >>> + /* Invalid */}; >>> + >>> + /* >>> + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured >>> + * with IPA bits == PA bits, compare against "pabits". >>> + */ >>> + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) >>> + p2m_ipa_bits = pa_range_info[system_cpuinfo.mm64.pa_range]; >>> + >>> + /* >>> + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identify the >>> + * memory system configurations supported. In Armv8-R AArch64, the >>> + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. >>> + */ >>> + if ( system_cpuinfo.mm64.msa != MM64_MSA_PMSA_SUPPORT ) >>> + goto fault; >>> + >>> + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b0010. */ >>> + if ( (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_PMSA_SUPPORT) && >>> + (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_VMSA_SUPPORT) ) >>> + goto fault; >>> + >>> + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ >>> + vtcr_el2 &= ~VTCR_MSA; >>> + >>> + /* >>> + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation output >>> + * address space to access the Secure PA space as Armv8r only implements >>> + * secure state. >>> + */ >>> + vtcr_el2 &= ~VTCR_NSA; >>> + >>> + /* >>> + * cpuinfo sanitization makes sure we support 16bits VMID only if all cores >>> + * are supporting it. >>> + * >>> + * Set the VS bit only if 16 bit VIMD is supported. >>> + */ >>> + if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) >>> + { >>> + vtcr_el2 |= VTCR_VS; >>> + max_vmid = MAX_VMID_16_BIT; >>> + } >>> + else >>> + vtcr_el2 &= ~VTCR_VS; >> This is the last change to vtcr_el2. Why do you put p2m_vmid_allocator_init() >> in-between this and write to vtcr_el2 register? It looks odd. > > ok I can have the write to the register before calling p2m_vmid_allocator_init, in the > end what matters is only to call p2m_vmid_allocator_init() after setting max_vmid. > >> >>> + >>> + p2m_vmid_allocator_init(); >>> + >>> + WRITE_SYSREG(vtcr_el2, VTCR_EL2); >>> + >>> + /* >>> + * VSTCR_EL2.SA defines secure stage 2 translation output address space. >>> + * To make sure that all stage 2 translations for the Secure PA space access >>> + * the Secure PA space, we keep SA bit as 0. >>> + * >>> + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS >>> + * configuration is checked against stage 1 NS configuration in EL1&0 >>> + * translation regime for the given address, and generates a fault if they >>> + * are different, we set SC bit 1. >>> + */ >>> + vstcr_el2 &= ~VSTCR_EL2_SA; >>> + vstcr_el2 |= VSTCR_EL2_SC; >>> + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); >>> + >>> + printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", >> All these are unsigned, so %u. > > Oops, blindly copying from MMU code, I realise we have the issue also there There are many other places in Xen using incorrect printk identifiers but for the new code we should use the correct ones. ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 13 11:07:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 11:07:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281064.1564117 (Exim 4.92) (envelope-from ) id 1wCF8p-0003Vw-Pe; Mon, 13 Apr 2026 11:07:43 +0000 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qx7CM4GUeTJ+yHQCO4Wz5NMdfHnS3Bcg8ShdcYvUV8A=; b=NQDeNJclxd4JwKjO+DWsjxOdDiinN1Kofr4sQPMwRW94Nt4PjDauCSVNBr5VZgPxGVpSOs0tqdW5Cx4viIZrUGRp+Ihn1wJfBRnRDElZ3G+YWJUtPyv5FStiUqmKg6B63+J10dNrAZy2t+2vINRduz1yvyDfQooxHyybAr5FlVw= From: Luca Fancellu To: Milan Djokic CC: "xen-devel@lists.xenproject.org" , Rahul Singh , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: Re: [PATCH v3 14/23] xen/arm: vIOMMU: IOMMU device tree node for dom0 Thread-Topic: [PATCH v3 14/23] xen/arm: vIOMMU: IOMMU device tree node for dom0 Thread-Index: AQHcyzs6VJb6/zH3nkySmP47A5N2jg== Date: Mon, 13 Apr 2026 11:46:56 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3826.700.81.1.6) Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none 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CIP:4.158.2.129;CTRY:GB;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:outbound-uk1.az.dlp.m.darktrace.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(14060799003)(35042699022)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7921uPUzdxEqK+TY6gqH+xya0lla5WoH8Sp7b8EqmeyJOChzO4JG9fTbFkyuPWllxVD9KTBwTM55/U/JqnktJDiWqdP9a9HPeYIrB4dvHXMgCxHRjadZFxmumFcTI8ZYsGGKyGWFIQePwC5Qa+OVhqrRdoVKbX7qWZzMaA8BdHnuEstO4Nb5rwBHDUwGlFCWDVcPT4rNjc5bUstPK/0aPyli7why69usZSiJ+nWgbOG+bVWDtPY2TqjRHQDmNjMFW7JRLnKxdGmjnKDPjK/rEo0TU6VM+sdS6rNWu5e2o+abICdsz+LUBhnVG9ooqpqyxej7qyLXALKZlbxN0RJ0aDQqU2tz0Vjy+ptYGUiFMHoeP88VAa3eldW/SJJ1D4vDHRzknf/RW27xVz0hojxUsCFqFH+bjIJA6zwVUURvq8jRKLvW7JVrtM12dsLVYW4Y X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 11:48:00.2418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f473b6eb-2d01-4bd8-4930-08de9952835e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009529.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9568 X-purgate-ID: tlsNG-d25034/1776080883-A4242A3D-DF43C862/0/0 X-purgate-type: clean X-purgate-size: 1189 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > XEN will create an IOMMU device tree node in the device tree > to enable the dom0 to discover the virtual SMMUv3 during dom0 boot. > IOMMU device tree node will only be created when cmdline option viommu > is enabled. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/arch/arm/domain_build.c | 94 +++++++++++++++++++++++++++++++ > xen/arch/arm/include/asm/viommu.h | 1 + > 2 files changed, 95 insertions(+) >=20 > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 30a4f1fd09..54ae3b5033 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -1440,6 +1440,95 @@ int __init make_timer_node(const struct kernel_inf= o *kinfo) > return res; > } >=20 > +#ifdef CONFIG_ARM_VIRTUAL_IOMMU > +static int make_hwdom_viommu_node(const struct kernel_info *kinfo) __init ? The rest looks ok to me, with that fixed: Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 11:51:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 11:51:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281110.1564152 (Exim 4.92) (envelope-from ) id 1wCFpB-0002qr-S4; Mon, 13 Apr 2026 11:51:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281110.1564152; Mon, 13 Apr 2026 11:51:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCFpB-0002qk-P5; Mon, 13 Apr 2026 11:51:29 +0000 Received: by outflank-mailman (input) for mailman id 1281110; Mon, 13 Apr 2026 11:51:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCFpA-0002qe-6l for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NgMv1DWsCj05U9MwExrDKshHq8vNxCW+EGaZv+/A1DcCxdiAXDHD6ytiYUWvnEmp2M5VR7BCkiLkxuZH5H7Tif2E8vHoSwg9YvXRseKGH6TqYHOup+SaCMtzLQVjSsgJHwGWWXIpJKuHmqi+65r3n/dyK7xc13SOFzOWimmb9hjP7sHXAapnv2ydu4hP+XCdv3sNxuLZdKVhqtETX5hwqIaunBbJkGzgJrQbFsvxBVgyyW55JBt5OXjVkQl8oAeCcSfhjwcEvvnSjmkIMIt2tktR0WjatuWM56iDhsFpz8Xi2lwj7oR3j+nzaACVEjoLGqFuNpQCb/SP8vAqK8Y6iwTCP7+mRXRfx1COBGwftBuLX992eTHg2YZ6eSpHZyW00vAj4+iWaTkYpBbpLlnk6ldWrhXW84c2DWOcWtQFx52cqxFf38g8Q8XZiSZY00mY X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 11:51:21.2345 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b762f554-c274-42c1-cf41-08de9952fb28 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001B4.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9744 X-purgate-ID: tlsNG-42698a/1776081086-EE74A2A1-7F60D61F/0/0 X-purgate-type: clean X-purgate-size: 1482 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > XEN will create an Emulated SMMUv3 device tree node in the device tree > to enable the dom0less domains to discover the virtual SMMUv3 during > boot. Emulated SMMUv3 device tree node will only be created when cmdline > option vsmmuv3 is enabled. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/arch/arm/dom0less-build.c | 53 +++++++++++++++++++++++++++ > xen/include/public/device_tree_defs.h | 1 + > 2 files changed, 54 insertions(+) >=20 > diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.= c > index 067835e5d0..a48edb9568 100644 > --- a/xen/arch/arm/dom0less-build.c > +++ b/xen/arch/arm/dom0less-build.c > @@ -218,10 +218,63 @@ static int __init make_vpl011_uart_node(struct kern= el_info *kinfo) > } > #endif >=20 > +#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3 > +static int __init make_vsmmuv3_node(const struct kernel_info *kinfo) > +{ > + int res; > + char buf[24]; > + __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; > + __be32 *cells; > + void *fdt =3D kinfo->fdt; > + > + snprintf(buf, sizeof(buf), "iommu@%llx", GUEST_VSMMUV3_BASE); PRIx64 ? The rest looks ok to me, with that fixed: Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 13:45:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 13:45:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281152.1564179 (Exim 4.92) (envelope-from ) id 1wCHbD-0007gk-TR; Mon, 13 Apr 2026 13:45:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281152.1564179; Mon, 13 Apr 2026 13:45:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCHbD-0007gd-PD; Mon, 13 Apr 2026 13:45:11 +0000 Received: by outflank-mailman (input) for mailman id 1281152; Mon, 13 Apr 2026 13:45:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fAs/IheV+auxMrH8rqjFGGtBB/B27mD1QFcTXdKHfno=; b=HJjSpxCG4hLGdJ1zNk7TGCGa3kklfSeYvPXNuDfT//GqFecxTsvMPnLoz6ySzIMOPK4R1wUcQZKwgngsQDw0T/UwMf5A37z4rb+dyMsYRp9ybB61X5PcYC/GtFwDENqkuGVlQXMN+4guWh9IfToVhr+8BV74Ul6gFvbhLm5BjBY= From: Luca Fancellu To: Milan Djokic CC: "xen-devel@lists.xenproject.org" , Rahul Singh , Anthony PERARD , Juergen Gross Subject: Re: [PATCH v3 16/23] arm/libxl: vsmmuv3: Emulated SMMUv3 device tree node in libxl Thread-Topic: [PATCH v3 16/23] arm/libxl: vsmmuv3: Emulated SMMUv3 device tree node in libxl Thread-Index: AQHcy0uWtT0jmyy89kG09VrDZ/FQXg== Date: Mon, 13 Apr 2026 13:44:02 +0000 Message-ID: References: <58c7eb798749c8c78935f5a8fc9e0aeff81760bb.1774918270.git.milan_djokic@epam.com> In-Reply-To: <58c7eb798749c8c78935f5a8fc9e0aeff81760bb.1774918270.git.milan_djokic@epam.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: 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3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8338 X-purgate-ID: tlsNG-ef75cf/1776090649-1039741E-BCA8FF7F/0/0 X-purgate-type: clean X-purgate-size: 801 Hi Juergen and Greg, On 2026-04-12 02:22, Juergen Gross wrote: > Linus, > > Please git pull the following tag: > > git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-7.1-rc1-tag > > xen: branch for v7.1-rc1 > - a fix for the Xen console driver solving a boot hangup when the > console backend isn't yet running > > Jason Andryuk (1): > hvc/xen: Check console connection flag Greg included this one in tty-testing as d50dd728ced93a1900ff0be924b6f273baf59fb2, which has been in linux-next for a bit. https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git/commit/?h=tty-testing&id=d50dd728ced93a1900ff0be924b6f273baf59fb2 I just wanted to bring this to your attention so you can decide which way it should go. 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Shouldn't this series > focus on getting basic functionality in place? At the moment, we don't support only APLIC for guest interrupts as it will require trap-and-emulation approach, so just from the start it was decided to go with APLIC+IMSIC (IMSIC here as it only one interrupt controller which exist and support VGEIN stuff at the momemnt) approach and then when it will be needed back to only the case when APLIC is supported. Maybe, it was better to introduce in patch series where a lauching of domain actually happens. Considering that you've already made a review, I prefer then to have this patch part of this patch series. > >> --- a/xen/arch/riscv/aia.c >> +++ b/xen/arch/riscv/aia.c >> @@ -1,11 +1,24 @@ >> /* SPDX-License-Identifier: GPL-2.0-only */ >> >> +#include >> #include >> #include >> #include >> +#include >> +#include >> #include >> +#include >> >> +#include >> #include >> +#include >> +#include >> + >> +/* >> + * Bitmap for each physical cpus to detect which VS (guest) >> + * interrupt file id was used. >> + */ >> +DEFINE_PER_CPU(struct vgein_bmp, vgein_bmp); > > Why can this not be static? All management looks to be in this same file. It could be, it couldn't be before when I have vgein/hgei interrupt handler in traps but after I decided to move it to aia.c, it looks like it is fine to make it static. > >> @@ -14,12 +27,109 @@ bool aia_available(void) >> return is_aia_available; >> } >> >> +int __init vgein_init(unsigned int cpu) > > If this needs invoking once per CPU being brought up, it can't be __init. Yes, it is going to be called inside the secondary CPU bring-up function. __init sections are removed much later, after all CPUs are brought up, so it looks like that at the moment when secondary CPUs are being brought up, __init still exists and can be called. > > Also - static? It isn't static because it will be called inside the secondary CPU bring-up function. > >> +{ >> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); >> + >> + csr_write(CSR_HGEIE, -1UL); >> + vgein->geilen = flsl(csr_read(CSR_HGEIE)); >> + csr_write(CSR_HGEIE, 0); >> + if ( vgein->geilen ) >> + vgein->geilen--; > > I don't understand this. The "len" in "geilen" stands for "length", I suppose, > i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of > bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED > and may be zero. This number is known as GEILEN." This may or may not include > bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is > nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but > that's not unambiguous. But they explicitly wrote that: The least-significant bits are implemented first, apart from bit 0. So bit 0 is explicitly excluded. > > Anyway, may I suggest > > vgein->geilen = flsl(csr_read(CSR_HGEIE) >> 1); > > instead? It would be really better. > >> + BUG_ON(!vgein->geilen); > > You can return (an error, but see the respective remark on the earlier patch), > no need to crash the system. That return may want to come after the printk() > below, though. > >> + printk("cpu%d.geilen=%d\n", cpu, vgein->geilen); > > As before - %u please with unsigned int. > >> + if ( !vgein->bmp ) > > Why would this check be needed? > >> + { >> + vgein->bmp = xvzalloc_array(unsigned long, BITS_TO_LONGS(vgein->geilen)); > > With the determination above, isn't BITS_TO_LONGS(vgein->geilen) == > BITS_PER_LONG in all cases? Surely you don't mean to runtime-allocate > space for a single unsigned long? So I wonder is the dimension used > is wrong. Hm, I can't remember why I did so. You are right there is no any sense to allocate a single unsinged long in runtime... > > If it isn't, dynamically allocating the owners array may be more > useful, as (on RV64) occupies a fixed 512 bytes right now. Agree, it make sense it will be much less memory if to allocate like: vgein->owners = xvzalloc_array(struct vcpu *, vgein->geilen); if ( !vgein->owners ) return -ENOMEM; as maximum value of vgein->geilen is 63. > >> + if ( !vgein->bmp ) >> + return -ENOMEM; >> + } >> + >> + spin_lock_init(&vgein->lock); >> + >> + return 0; >> +} >> + >> int __init aia_init(void) >> { >> + int rc = 0; >> + >> if ( !riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ssaia) ) >> return -ENODEV; >> >> + if ( (rc = vgein_init(0)) ) >> + return rc; >> + >> is_aia_available = true; > > Ah, this answers a question of mine on the earlier patch: This boolean > indicates more than just the extension being available. But why does > the description there not simply say so? How am I as a reviewer supposed > to know? I relised that it is worse to mention that only when saw your reply in the earlier patch, I will update the commit message for convience. > >> - return 0; >> + return rc; >> +} >> + >> +unsigned int vgein_assign(struct vcpu *v) >> +{ >> + unsigned int vgein_id; >> + > > Seemingly undue blank line. > >> + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor); >> + unsigned long *bmp = vgein_bmp->bmp; >> + unsigned long flags; >> + >> + spin_lock_irqsave(&vgein_bmp->lock, flags); >> + vgein_id = bitmap_weight(bmp, vgein_bmp->geilen); > > How can the ID to use be the number of bits which are set? This only works > if all set bits are contiguous at the bottom. Oh, it is really wrong. find_first_zero_bit() should be instead or vgein_id = find_next_zero_bit(bmp, vgein_bmp->geilen + 1, 1); > >> + /* >> + * All vCPU guest interrupt files are used and we don't support a case >> + * when number of vCPU on 1 pCPU is bigger then geilen. >> + */ > > This wants checking in vgein_init() then. CPUs (beyond the boot one) > violating this should not be brought online. It'll be nice. But we can't know how many vCPUs will be ran on pCPU when vgein_init() is executed. > >> + ASSERT(vgein_id < vgein_bmp->geilen); > > What if not bit is available? By asserting, you assume the caller will not > call here when no ID is available. It is just a temporary ASSERT() (as we don't support software guest interrupt files) because in general it is fine if there is no bit available, it will just mean that that no physical hardware guest interrupt file is assigned to the virtual hart, and software-based emulation (a "software file") must be used to handle guest external interrupts. Will it be better to return 0 now here and just don't create a vCPU on ... Yet there is no caller of this function, > so how can one verify whether this assertion is appropriate? ... the caller side when an assignment is expected to be happen? > >> + bitmap_set(bmp, vgein_id, 1); > > __set_bit()? I thought that it will be fine to use for bmp, bitmap_* functions(). __set_bit is what is called inside bitmap_set(). > >> + spin_unlock_irqrestore(&vgein_bmp->lock, flags); >> + >> + /* >> + * The vgein_id shouldn't be zero, as it will indicate that no guest >> + * external interrupt source is selected for VS-level external interrupts >> + * according to RISC-V priviliged spec: >> + * 8.2.1 Hypervisor Status Register (hstatus) in RISC-V priviliged spec: > > Please avoid section numbers in such references. The section of this name > in the version I'm looking at is 21.2.1. > >> + * The VGEIN (Virtual Guest External Interrupt Number) field selects >> + * a guest external interrupt source for VS-level external interrupts. >> + * VGEIN is a WLRL field that must be able to hold values between zero >> + * and the maximum guest external interrupt number (known as GEILEN), >> + * inclusive. >> + * When VGEIN=0, no guest external interrupt source is selected for >> + * VS-level external interrupts. >> + */ >> + vgein_id++; > > Related to my comment regarding GEILEN, this shouldn't be necessary. Keep > bits in their natural positions, and simply avoid using bit 0 (either by > setting it during init and then never clearing it, or by starting the > scan for clear bits at bit 1). > >> +#ifdef VGEIN_DEBUG >> + printk("%s: %pv: vgein_id(%u), xen_cpu%d_bmp=%#lx\n", >> + __func__, v, vgein_id, v->processor, *bmp); >> +#endif >> + >> + vcpu_guest_cpu_user_regs(v)->hstatus &= ~HSTATUS_VGEIN; >> + vcpu_guest_cpu_user_regs(v)->hstatus |= >> + MASK_INSR(vgein_id, HSTATUS_VGEIN); > > When is this function going to be invoked? (As before, not knowing this is > one of the problems with introducing functions with no callers.) vgein_assign() function is going to be invoked during the call of arch_vcpu_create(). I also thought to make vgein_assign() just work with vgein_id and just return vgein_id and fill v->hstatus on the caller side. It looks a little bit cleaner from some point of view. It is still need to return vgein_id as it is needed for IMSIC's guest interrupt file address calculation. > >> + return vgein_id; >> +} >> + >> +void vgein_release(struct vcpu *v, unsigned int vgen_id) >> +{ >> + unsigned long flags; >> + > > Another seemingly stray blank line. > >> + struct vgein_bmp *vgein_bmp = &per_cpu(vgein_bmp, v->processor); >> + >> + spin_lock_irqsave(&vgein_bmp->lock, flags); >> + bitmap_clear(vgein_bmp->bmp, vgen_id - 1, 1); > > __clear_bit()? > The same as with bitmap_set() as ->bmp is bitmap I expect that bitmap_*() functions should be used. But just to avoid extra if() inside bitmap_clear(), I will use __clear_bit(). >> + spin_unlock_irqrestore(&vgein_bmp->lock, flags); >> + >> +#ifdef VGEIN_DEBUG >> + printk("%s: vgein_id(%u), xen_cpu%d_bmp=%#lx\n", >> + __func__, vgen_id, v->processor, *vgein_bmp->bmp); > > I can't spot a difference from the message in vgein_assign(). How is one > to distinguish the two in a log? By function name which is the first argument (__func__). > >> --- a/xen/arch/riscv/include/asm/aia.h >> +++ b/xen/arch/riscv/include/asm/aia.h >> @@ -3,8 +3,26 @@ >> #ifndef ASM__RISCV__AIA_H >> #define ASM__RISCV__AIA_H >> >> +#include >> +#include >> + >> +struct vcpu; >> + >> +struct vgein_bmp { > > What does the _bmp suffix indicate here? There's ... > >> + unsigned long *bmp; > > ... a bitmap field, yes, but ... > >> + spinlock_t lock; >> + struct vcpu *owners[BITS_PER_LONG]; >> + unsigned int geilen; >> +}; > > ... the structure as a whole has quite a bit more. Agree, there is no any sense for _bmp. It would be better to use _ctrl. Also, I will move this struct to aia.c. Then it also make sense to rename vgein_vmp variable just to vgein. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 13 14:42:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 14:42:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281211.1564231 (Exim 4.92) (envelope-from ) id 1wCIUW-0000QU-17; Mon, 13 Apr 2026 14:42:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281211.1564231; Mon, 13 Apr 2026 14:42:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCIUV-0000QK-U7; Mon, 13 Apr 2026 14:42:19 +0000 Received: by outflank-mailman (input) for mailman id 1281211; Mon, 13 Apr 2026 14:42:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCIUU-0000Po-On for xen-devel@lists.xenproject.org; Mon, 13 Apr 2026 14:42:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCIUU-007xxE-44 for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LxdozWUekax1OH07VuZzGCcZhsKAMntzajkXFWaHSaIibLZRlhCyUqZQnL9Nw84Cva0YELLx4RdTpp5AhJh8sgZrQiwdx6rToLkt9jAvlCFnbvqnxteIREYOK4Daq+kUDkRhLl1knljHGEGN8gBZo+nSLz/ZQ9n82RSRQsS3NIiWPvWZEuHP1ARtrfnrZLzQf+gQ/yGXGGhtyY9s5n2ETjd4R5oovPtzuWHzwqe3alUsdS5YLQw2vClCCeHX5o6lf81mk6RNGn4xpzRyiNhiD7QrM1l1bHMZ4Z92eViOYljpwtLWxfhav3GVvtbENLIgX9W0sgWaLzuElovUiPdMKCp1SzohX7AsIWLg+hEOOovTFQ7rEIb1QpKSoNW7B4SLZVvXK11SAFqNs526NUkds9adzn6MBzyRcUyLHWjZxCI1tyOsWHTF1VEg6R6vE7DR X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 14:42:15.4532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27418ce0-b937-43ab-8a2a-08de996adb28 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D09.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7536 X-purgate-ID: tlsNG-16d1c6/1776091337-AD92A3D8-E73AD811/0/0 X-purgate-type: clean X-purgate-size: 513 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > To configure IOMMU in guest for passthrough devices, user will need to > copy the unmodified "iommus" property from host device tree to partial > device tree. To enable the dom0 linux kernel to confiure the IOMMU Typo s/confiure/configure/ The rest looks ok to me with that addressed: Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 14:47:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 14:47:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281230.1564240 (Exim 4.92) (envelope-from ) id 1wCIZf-0001JN-NF; Mon, 13 Apr 2026 14:47:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281230.1564240; Mon, 13 Apr 2026 14:47:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCIZf-0001JG-Jm; Mon, 13 Apr 2026 14:47:39 +0000 Received: by outflank-mailman (input) for mailman id 1281230; Mon, 13 Apr 2026 14:47:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCIZd-0001JA-T7 for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hiR0EYiCY/JOpFiX1EXzwPGW63uES4PyGusw+fhPDg4hqwiZYQbYSEm1zLXo2BZ+BufqykuMjUUi6f2/2cMFHN2CJA59yd7HBwb0UNoUFuBsMJSReejgauWBQhzFZB/DkRw1awlanfIA6/xwlvWhCeDOc4LkPrrjUw0BGkU3GgQhDQHFmg6pJtJKolZm4RrZc4g2uhMVJf+7Mr5uL8ngO/6wcJ/yr7Pe4/1LiuMv8bOAfc0UdWvFK1O9iUSuilYMQQ+hc5H/m/COKQKvH1XRdD7X2FSnl5r8DtJHKbWbHq98+ArLA8LuS3V5QedrO12OBiTserp/35HUoLW0QrLm3nmbGy7lQPAZBIancD0iu5DSR7J2uc0Ik5sdXP3qRQSNzCbyLWy4F7VKxNH1rjeouKeGjBYxZJCVIdGhDZprdNx/iGf/u1ZffxCYspVprMN/ X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2026 14:47:32.7628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcff1009-62e3-4384-45c6-08de996b984a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A65.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB5994 X-purgate-ID: tlsNG-c201ff/1776091656-383E496F-E143179A/0/0 X-purgate-type: clean X-purgate-size: 2742 Hi Milan, > On 31 Mar 2026, at 02:52, Milan Djokic wrote: >=20 > From: Rahul Singh >=20 > To configure IOMMU in guest for passthrough devices, user will need to > copy the unmodified "iommus" property from host device tree to partial > device tree. To enable the dom0 linux kernel to confiure the IOMMU typo s/confiure/configure/ > correctly replace the phandle in partial device tree with virtual > IOMMU phandle when "iommus" property is set. >=20 > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/common/device-tree/dom0less-build.c | 31 ++++++++++++++++++++++++- > 1 file changed, 30 insertions(+), 1 deletion(-) >=20 > diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-= tree/dom0less-build.c > index 840d14419d..4b74d2f705 100644 > --- a/xen/common/device-tree/dom0less-build.c > +++ b/xen/common/device-tree/dom0less-build.c > @@ -318,7 +318,35 @@ static int __init handle_prop_pfdt(struct kernel_inf= o *kinfo, > return ( propoff !=3D -FDT_ERR_NOTFOUND ) ? propoff : 0; > } >=20 > -static int __init scan_pfdt_node(struct kernel_info *kinfo, const void *= pfdt, > +static void modify_pfdt_node(void *pfdt, int nodeoff) > +{ > + int proplen, i, rc; > + const fdt32_t *prop; > + fdt32_t *prop_c; > + > + prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen); > + if ( !prop ) > + return; > + > + prop_c =3D xzalloc_bytes(proplen); we should check if the allocation was ok > + > + for ( i =3D 0; i < proplen / 8; ++i ) > + { > + prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3); > + prop_c[i * 2 + 1] =3D prop[i * 2 + 1]; > + } > + > + rc =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen); > + if ( rc ) > + { > + dprintk(XENLOG_ERR, "Can't set the iommus property in partial FD= T"); > + return; > + } > + > + return; > +} > + > +static int __init scan_pfdt_node(struct kernel_info *kinfo, void *pfdt, > int nodeoff, > uint32_t address_cells, uint32_t size_ce= lls, > bool scan_passthrough_prop) > @@ -344,6 +372,7 @@ static int __init scan_pfdt_node(struct kernel_info *= kinfo, const void *pfdt, > node_next =3D fdt_first_subnode(pfdt, nodeoff); > while ( node_next > 0 ) > { > + modify_pfdt_node(pfdt, node_next); > rc =3D scan_pfdt_node(kinfo, pfdt, node_next, address_cells, size= _cells, > scan_passthrough_prop); > if ( rc ) >=20 Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 13 14:57:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 14:57:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281243.1564248 (Exim 4.92) (envelope-from ) id 1wCIjD-00033Y-IX; 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h=From:Subject:To:Cc:Message-Id:In-Reply-To:Feedback-ID:Date: MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=dx3L7YiDGuM+ep9omsd8lTJHPyNy2aWDPX23M6txrx7GGLh/X4l9myzkLoEnA15w7 9jk+23dvjUqu+RIgURfMU20SJRngQ5eiOkAFxx3jE0dkAPZM17GkFcz0Dp0QNw2Vq5 /WGFrV2AwhwMGu+nGyY9laYg9G1n6FwFHe1H1kzLQmjK4c2A2c8usEhRbOLCpl6e0M e8zhzsLMG4zTkecD6Ff7Brkk1zivTDynDT0lGKKH7cwyihq0MhBZgb3y34hJMlT6aB 97dDKZTyIxUZOGCrjZ7aDe3m0E5xmuh+p+969+Z5iRGc7M/AaMDwheUUmJdL7BrSJ9 VRMAokc8b5uag== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20test-artifacts=20v3=2001/13]=20Add=20Alpine=203.22=20containers?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776092245824 To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Andrew Cooper" , "Stefano Stabellini" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: In-Reply-To: <89e8adefe509165c419b0be7a1fdcd19289c2be7.1774999132.git-series.marmarek@invisiblethingslab.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.28f3e43204da469e876df1a9d9bd776a?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260413:md Date: Mon, 13 Apr 2026 14:57:27 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776092248-B072A51B-5980200C/0/0 X-purgate-type: clean X-purgate-size: 1665 I'm commenting on changes I found in the branch used by the pipeline linked in the cover leter, since there's no copy on the mailing list of the patch :-( (overzealous spam filter). > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > index c698612d5acd..17d25ce0f921 100644 > --- a/.gitlab-ci.yml > +++ b/.gitlab-ci.yml > @@ -40,6 +40,13 @@ alpine-3.18-arm64-rootfs: > variables: > CONTAINER: alpine:3.18-arm64-base > > +alpine-3.22-arm64-rootfs: > + extends: .arm64-artifacts > + script: > + - ./scripts/alpine-rootfs.sh > + variables: > + CONTAINER: alpine:3.18-arm64-base > + Shouldn't this use the 3.22 converner version? > diff --git a/containerize b/containerize > index 38a434ab7075..b3722b465e01 100755 > --- a/containerize > +++ b/containerize > @@ -28,6 +28,10 @@ case "_${CONTAINER}" in > _alpine-3.18-arm64-build) CONTAINER="${BASE}/alpine:3.18-arm64-build" ;; > _alpine-3.18-x86_64-base) CONTAINER="${BASE}/alpine:3.18-x86_64-base" ;; > _alpine-3.18-x86_64-build|_) CONTAINER="${BASE}/alpine:3.18-x86_64-build" ;; > + _alpine-3.22-arm64-base) CONTAINER="${BASE}/alpine:3.22-arm64-base" ;; > + _alpine-3.22-arm64-build) CONTAINER="${BASE}/alpine:3.22-arm64-build" ;; > + _alpine-3.22-x86_64-base) CONTAINER="${BASE}/alpine:3.22-x86_64-base" ;; > + _alpine-3.22-x86_64-build|_) CONTAINER="${BASE}/alpine:3.22-x86_64-build" ;; If you intend to make the x86 3.22 build container the new default, you are going to need to change the 3.18 x86 build container line above. Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 13 15:12:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 13 Apr 2026 15:12:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281255.1564258 (Exim 4.92) (envelope-from ) id 1wCIx6-00061f-Ns; Mon, 13 Apr 2026 15:11:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281255.1564258; Mon, 13 Apr 2026 15:11:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCIx6-00061Y-LE; Mon, 13 Apr 2026 15:11:52 +0000 Received: by outflank-mailman (input) for mailman id 1281255; Mon, 13 Apr 2026 15:11:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 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If you want your features to be included for the release, please make sure they are posted for the first time before Fri Apr 17, 2026. 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17:59:30 -0700 Received: from A6424298.boeing.com (a6424298.nos.boeing.com [10.191.242.201]) by ewa-av-01.mbs.boeing.net (8.15.2/8.15.2/UPSTREAM_RELAY) with ESMTP id 63E0xKU3052426; Mon, 13 Apr 2026 17:59:21 -0700 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=boeing-s1912 header.d=boeing.com header.i="@boeing.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=boeing.com; s=boeing-s1912; t=1776128383; bh=7rRZv4jH4j5UcfT3Vc0EKG1kzDe3IUvMyVRk4LD2oNo=; h=From:To:Cc:Subject:Date:From; b=jtqnKOmjyUOaNazw0e450E7ofcLvt9OZ3PnfW/LsbbZoKcz64p13tA/3fF42bZUV/ 8ubsBSByQEZ1TRKfnMMT35FWLJn8IjfptQmlNip5BvItsqmr9rPikPgQ1wPIsY7kgj 6LjgLMR5vK/DO7I/KfTwOlxTqKt1BNUTvRnrjjTz7CC2WdWsNVcOHuOlSw0nboF0Mo HBJhOSScUKNGabji1VOpKvaC+YphaoWK1aomRq/7NQGFu7v0+N2KNs+yv+YbIM8avk uDqqXv/G3678tSf2umb4jUaomSV1aV/ZLtwj/Ns/dRokHnQrVFgKFmdnfqdHJNUQfy /G8eCr7ZV//ug== From: Joan Bae To: xen-devel@lists.xenproject.org Cc: Joan Bae , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel Subject: [XEN PATCH] xen/common: validate shared memory guest address overlap with guest RAM Date: Tue, 14 Apr 2026 09:59:18 +0900 Message-ID: <59dcd094173791926fff212f3f2b86df50b0dc12.1776060772.git.joan.bae@boeing.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-purgate-ID: tlsNG-c1860d/1776128387-F4F5A497-0FD6B68A/0/0 X-purgate-type: clean X-purgate-size: 3546 Currently, process_shm() does not check whether the guest physical address of a shared memory region overlaps with the domain's allocated RAM banks. Neither process_shm() nor p2m_set_entry() checks for existing mappings, so the RAM mapping is silently overwritten if a user specifies a guest physical address that falls within the guest RAM range. Since construct_domain() loads the kernel after process_shm(), the kernel can end up in shared memory pages. This can cause: - Another domain corrupting the kernel via shared memory write - Silent guest crash with no error message from Xen Add a check in process_shm() to validate that the shared memory guest address range does not overlap with any of the domain's allocated RAM banks. Signed-off-by: Joan Bae --- xen/common/device-tree/static-shmem.c | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/common/device-tree/static-shmem.c b/xen/common/device-tree/static-shmem.c index 4c4cc1b123..b0ae0304a1 100644 --- a/xen/common/device-tree/static-shmem.c +++ b/xen/common/device-tree/static-shmem.c @@ -293,6 +293,31 @@ static bool __init save_map_heap_pages(struct domain *d, struct page_info *pg, return false; } +static bool __init +check_shm_guest_paddr_overlap(struct kernel_info *kinfo, paddr_t gbase, + paddr_t size) +{ + unsigned int i; + const struct membanks *kinfo_mem = kernel_info_get_mem_const(kinfo); + paddr_t gend = gbase + size; + + for ( i = 0; i < kinfo_mem->nr_banks; i++ ) + { + paddr_t bankbase = kinfo_mem->bank[i].start; + paddr_t bankend = bankbase + kinfo_mem->bank[i].size; + + /* Check if shared memory overlaps with guest RAM */ + if ( gbase < bankend && bankbase < gend ) + { + printk("Shared memory guest address 0x%"PRIpaddr" - 0x%"PRIpaddr"" + " overlaps with guest RAM 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", + gbase, gend - 1, bankbase, bankend - 1); + return true; + } + } + + return false; +} + int __init process_shm(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { @@ -355,6 +380,12 @@ int __init process_shm(struct domain *d, struct kernel_info *kinfo, /* guest phys address is after host phys address */ gbase = dt_read_paddr(cells + addr_cells, addr_cells); + if ( check_shm_guest_paddr_overlap(kinfo, gbase, psize) ) + { + printk("%pd: shared memory region overlaps with the guest's RAM range\n", d); + return -EINVAL; + } + if ( is_domain_direct_mapped(d) && (pbase != gbase) ) { printk("%pd: physical address 0x%"PRIpaddr" and guest address 0x%"PRIpaddr" are not direct-mapped.\n", @@ -396,6 +427,12 @@ int __init process_shm(struct domain *d, struct kernel_info *kinfo, /* guest phys address is right at the beginning */ gbase = dt_read_paddr(cells, addr_cells); + if ( check_shm_guest_paddr_overlap(kinfo, gbase, psize) ) + { + printk("%pd: shared memory region overlaps with the guest's RAM range\n", d); + return -EINVAL; + } + if ( !alloc_bank ) { alloc_heap_pages_cb_extra cb_arg = { d, role_str, gbase, -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 01:47:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 01:47:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281385.1564294 (Exim 4.92) (envelope-from ) id 1wCSrY-0003k0-AA; Tue, 14 Apr 2026 01:46:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281385.1564294; Tue, 14 Apr 2026 01:46:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCSrY-0003jt-7L; Tue, 14 Apr 2026 01:46:48 +0000 Received: by outflank-mailman (input) for mailman id 1281385; Tue, 14 Apr 2026 01:46:47 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCSrX-0003jn-8K for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 01:46:47 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCSrV-001QkU-2P; Tue, 14 Apr 2026 01:46:45 +0000 Received: from [116.84.110.196] (helo=[10.158.125.74]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCSrV-001UUQ-14; Tue, 14 Apr 2026 01:46:45 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=hn/ObxAnxTNEf0U8zXIaExFL3p9yj5z4expNS+0guuA=; b=Tr375Fbn7RH6XLG3nob3qGod/x LHEXzMiWx6iB50ckfTXVdif9fO89Fape8rmqBhrtdd19r8nHa9c8UAvsQ6YFcBVUfIDSoweQ3CvL5 QCeaLUvFiYXykgn0lvzIRgqMSijq4MC2EbW1DZEwcY3EGlqGMK/JCjKL2wVK0P6k/yx4=; Message-ID: Date: Tue, 14 Apr 2026 10:46:41 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN PATCH] xen/common: validate shared memory guest address overlap with guest RAM Content-Language: en-GB To: Joan Bae , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel References: <59dcd094173791926fff212f3f2b86df50b0dc12.1776060772.git.joan.bae@boeing.com> From: Julien Grall In-Reply-To: <59dcd094173791926fff212f3f2b86df50b0dc12.1776060772.git.joan.bae@boeing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Joan, Thank you for the patch. On 14/04/2026 09:59, Joan Bae wrote: > Currently, process_shm() does not check whether the guest physical > address of a shared memory region overlaps with the domain's allocated RAM banks. > Neither process_shm() nor p2m_set_entry() checks for existing > mappings, so the RAM mapping is silently overwritten if a user > specifies a guest physical address that falls within the guest RAM > range. Since construct_domain() loads the kernel after process_shm(), > the kernel can end up in shared memory pages. This can cause: > - Another domain corrupting the kernel via shared memory write > - Silent guest crash with no error message from Xen This seems to be solving one specific issue (RAM clashing with shared memory) but I believe this could also happen with other kind of mappings because, as you said, p2m_set_entry() doesn't check any overlap. So I would rather prefer if we solve the problem once and for all. This would mean modifying p2m_set_entry() (or one of its top caller). Although, we would need to be careful to not break memory hypercalls which may rely on overwriting existing mappings. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 02:06:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 02:06:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281393.1564302 (Exim 4.92) (envelope-from ) id 1wCTAE-0006x9-Rj; Tue, 14 Apr 2026 02:06:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281393.1564302; Tue, 14 Apr 2026 02:06:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTAE-0006x2-Ou; Tue, 14 Apr 2026 02:06:06 +0000 Received: by outflank-mailman (input) for mailman id 1281393; Tue, 14 Apr 2026 02:06:05 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTAD-0006ww-5r for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 02:06:05 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCTAC-001RYj-1V; Tue, 14 Apr 2026 02:06:04 +0000 Received: from [116.84.110.196] (helo=[10.158.125.74]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCTAC-001VdL-0b; Tue, 14 Apr 2026 02:06:04 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=XaWnSOD31kbNTVXa8LLDZ78YYn+M2bU6cCp9h8fe9Qg=; b=o275si6sn9VPmUiSTnyq3eITuX P9G8zdKf/2EI8LPde9jZBeoyEkqQIzXpHW0FzDRY1dC5Bj9+pkTrG9GYDrPCU6/XxeBZmGzx8S+Yr hSv9qy4F9+9RaI4la4e4MA/yUPjosKOxFwkc7d8kBFzw9JMBJJl3LYkVDYxLnG1yixyI=; Message-ID: <83786d8b-d57a-4c79-8e8b-7115d4276568@xen.org> Date: Tue, 14 Apr 2026 11:06:00 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: gic-v3: Introduce CONFIG_GICV3_NR_LRS Content-Language: en-GB To: Ayan Kumar Halder , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> From: Julien Grall In-Reply-To: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Ayan, On 18/03/2026 23:09, Ayan Kumar Halder wrote: > One key requirement of Xen functional safety is to reduce the number > of lines of code to be safety certified. Besides, a safety certified > Xen requires a static hardware configuration to be defined. This static > hardware configuration is described as per the test hardware/emulator > hardware configuration against which Xen is verified. > > Introduce GICV3_NR_LRS with the two aims in mind: Out of interest, why is this limited to GICv3? > 1. User should set the number of GICV3 list registers as per the test > hardware so that the unwanted code can be removed using GCC's dead > code elimination or preprocessor's config. We discussed this offline, I am not fully convinced you can rely on dead code elimination to always remove the BUG() in gicv3_ich_read_lr(). If you want to rely on dead code eliminitation, then you will want to call a function which have a prototype defined but not implemented (similar to what we do for bitops with __bad_atomic_read()) which would fail a link time if the compiler didn't remove the code. > 2. By doing #1, one can ensure that there is no untested code due to > unsupported hardware platform and thus there is no safety impact due > to untested code. > > However if the user does not set GICV3_NR_LRS, then it is set to 0. > Thus Xen will fallback to the default scenario (i.e. read the hardware > register to determine the number of LRS). > > 1. In gicv3_save_lrs()/gicv3_restore_lrs(), use the number of list > registers from GICV3_NR_LRS (if defined) instead of gicv3_info.nr_lrs. > This ensures that if the hardware does not support more than 4 LRs > (for example), the code accessing LR 4-15 is never reached. The > compiler can eliminate the unsupported cases as the switch case uses a > constant conditional. > > 2. RAZ/WI for the unsupported LRs. > > Signed-off-by: Ayan Kumar Halder > Signed-off-by: Michal Orzel > --- > Changelog: > > v1 - 1. s/lrs/LRS > 2. Implement RAZ/WI instead of panic > > Few comments which were not addressed > 1. Do "gicv3_info.nr_lrs to LRS" in gicv3_hyp_init() and keep the code > unchanged in gicv3_save_lrs()/gicv3_restore_lrs() -- This prevents the > compiler from doing dead code elimination as the switch condition cannot > be evaluated at compile time. > I am not sure how to get around this issue. > > xen/arch/arm/Kconfig | 9 +++++++++ > xen/arch/arm/gic-v3.c | 14 ++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig > index 2f2b501fda..6540013f97 100644 > --- a/xen/arch/arm/Kconfig > +++ b/xen/arch/arm/Kconfig > @@ -276,6 +276,15 @@ config PCI_PASSTHROUGH > > endmenu > > +config GICV3_NR_LRS > + int "Number of GICv3 Link Registers supported" if EXPERT Supported by who? The hardware? Xen? Asking, because I could forsee an integrator wanted to limit the number of LRs to something smaller than what the HW supports (in a lot of cases, 2 LRs is sufficient). > + depends on GICV3 > + range 0 16 > + default 0 > + help > + Controls the number of Link registers to be accessed. > + Keep it set to 0 to use a value obtained from a hardware register. I still strongly think that if GICV3_NR_LRS is set, then it needs to be checked against the value read by the hardware > + > menu "ARM errata workaround via the alternative framework" > depends on HAS_ALTERNATIVE > > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index bc07f97c16..eaae95eb4d 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -51,6 +51,8 @@ static DEFINE_PER_CPU(void __iomem*, rbase); > #define GICD (gicv3.map_dbase) > #define GICD_RDIST_BASE (this_cpu(rbase)) > #define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K) > +#define LRS (CONFIG_GICV3_NR_LRS ?: \ > + gicv3_info.nr_lrs) IMHO, LRS is a little bit vague. What about MAX_LRS? Or maybe NR_LRS? > > /* > * Saves all 16(Max) LR registers. Though number of LRs implemented > @@ -59,7 +61,7 @@ static DEFINE_PER_CPU(void __iomem*, rbase); > static inline void gicv3_save_lrs(struct vcpu *v) > { > /* Fall through for all the cases */ > - switch ( gicv3_info.nr_lrs ) > + switch ( LRS ) > { > case 16: > v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); > @@ -121,7 +123,7 @@ static inline void gicv3_save_lrs(struct vcpu *v) > static inline void gicv3_restore_lrs(const struct vcpu *v) > { > /* Fall through for all the cases */ > - switch ( gicv3_info.nr_lrs ) > + switch ( LRS ) > { > case 16: > WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); > @@ -178,6 +180,10 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) > > static uint64_t gicv3_ich_read_lr(int lr) > { > + /* RAZ for unsupported LR */ > + if ( lr >= LRS ) > + return 0; > + > switch ( lr ) > { > case 0: return READ_SYSREG_LR(0); > @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) > > static void gicv3_ich_write_lr(int lr, uint64_t val) > { > + /* WI for unsupported LR */ AFAIU, this path is really not meant to happen. So I don't think we want to silently ignore the write as it would mean an interrupt is missing. I think in debug build, we probably want to use ASSERT_UNREACHABLE(). If we want something for production as well, then we could instead use WARN(). Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 02:10:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 02:10:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281401.1564313 (Exim 4.92) (envelope-from ) id 1wCTEe-00006N-D7; Tue, 14 Apr 2026 02:10:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281401.1564313; Tue, 14 Apr 2026 02:10:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTEe-00006G-9M; Tue, 14 Apr 2026 02:10:40 +0000 Received: by outflank-mailman (input) for mailman id 1281401; Tue, 14 Apr 2026 02:10:39 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTEd-00006A-HX for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 02:10:39 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCTEd-001RdR-0p; Tue, 14 Apr 2026 02:10:39 +0000 Received: from [116.84.110.196] (helo=[10.158.125.74]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCTEc-001VmT-30; Tue, 14 Apr 2026 02:10:39 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=bhrcCn6V/kPpvu1fA3POfrorI1qX0VaIDSvPlAcKewI=; b=cKAl92WWPcY+Y6kasF5Qv+bL2N tA2R5REsSc5Wg5nIbuIC6egP+ZVBIAXXKLwHac0B2zWuiQEeqnQncF6D/xxOR3XLZ+VvrJK6W2ALE Bj0WmMoWyKJbAszo2SQd6iMAHy/JZfRADXjiGLOKgvOOa+MePOlMA26l2UV0vj2hHXNo=; Message-ID: <56478969-509d-4527-b136-4498840606e2@xen.org> Date: Tue, 14 Apr 2026 11:10:35 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: gic-v3: Introduce CONFIG_GICV3_NR_LRS Content-Language: en-GB To: Luca Fancellu , Ayan Kumar Halder Cc: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 08/04/2026 23:24, Luca Fancellu wrote: >> @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) >> >> static void gicv3_ich_write_lr(int lr, uint64_t val) >> { >> + /* WI for unsupported LR */ >> + if ( lr >= LRS ) >> + return; >> + >> switch ( lr ) >> { >> case 0: > > Now, since we are using CONFIG_GICV3_NR_LRS or gicv3_info.nr_lrs in gicv3_save_lrs/gicv3_restore_lrs, > there are other part of the codebase using nr_lrs (gic_get_nr_lrs() is one of them), but all the callers of that > function will use the HW nr_lrs and not the CONFIG_GICV3_NR_LRS, so I think some work needs to be done > to align them or there will be mismatches at runtime with possible loss of information. +1. We need a consistent view for the number of LRs. I could also see a use case where the integrator wants to support less LRs than what the HW supports (this doesn't seem to be prevented with this patch). Note, during Xen boot, we may need to zero the LRs which are unused as they may potentially contain active interrupts. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 02:17:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 02:17:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281412.1564321 (Exim 4.92) (envelope-from ) id 1wCTLY-0000pq-4A; Tue, 14 Apr 2026 02:17:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281412.1564321; Tue, 14 Apr 2026 02:17:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTLY-0000pj-1E; Tue, 14 Apr 2026 02:17:48 +0000 Received: by outflank-mailman (input) for mailman id 1281412; Tue, 14 Apr 2026 02:17:46 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTLW-0000pd-6C for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 02:17:46 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCTLV-001RkF-2B; Tue, 14 Apr 2026 02:17:45 +0000 Received: from [116.84.110.196] (helo=[10.158.125.74]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCTLV-001W45-1J; Tue, 14 Apr 2026 02:17:45 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=js5XNSEc24aap/AOxb/rFQf3IpHmT2uTLaA9JtlSpc0=; b=kQ6mYhiE4UbFDKjrAquAjVOavl mwX1laZ5Ny0jlbjvKMJ4CvtK4PFw0ob1gcRx8MTrL7nIaqh+2ftFi0WGzsYh5DBjE0sO9jWK9vt3I rn8lS9JynCRf5UMEBBc6vfR5Gi5HfeGl2YtXgH2l3waHT211GhXiV2TGGAHhHXR6om/4=; Message-ID: <56a7c116-4ecb-4dfc-a7dd-774d53041fe9@xen.org> Date: Tue, 14 Apr 2026 11:17:41 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/23] xen/arm: smmuv3: Add support for stage-1 and nested stage translation Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk References: From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 24/03/2026 07:51, Milan Djokic wrote: > From: Rahul Singh > > Xen SMMUv3 driver only supports stage-2 translation. Add support for > Stage-1 translation that is required to support nested stage > translation. > > In true nested mode, both s1_cfg and s2_cfg will coexist. > Let's remove the union. When nested stage translation is setup, both > s1_cfg and s2_cfg are valid. > > We introduce a new smmu_domain abort field that will be set > upon guest stage-1 configuration passing. If no guest stage-1 > config has been attached, it is ignored when writing the STE. > > arm_smmu_write_strtab_ent() is modified to write both stage > fields in the STE and deal with the abort field. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/drivers/passthrough/arm/smmu-v3.c | 93 +++++++++++++++++++++++---- > xen/drivers/passthrough/arm/smmu-v3.h | 9 +++ > 2 files changed, 91 insertions(+), 11 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index 73cc4ef08f..f9c6837919 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -683,8 +683,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > * 3. Update Config, sync > */ > u64 val = le64_to_cpu(dst[0]); > - bool ste_live = false; > + bool s1_live = false, s2_live = false, ste_live = false; > + bool abort, translate = false; > struct arm_smmu_device *smmu = NULL; > + struct arm_smmu_s1_cfg *s1_cfg = NULL; > struct arm_smmu_s2_cfg *s2_cfg = NULL; > struct arm_smmu_domain *smmu_domain = NULL; > struct arm_smmu_cmdq_ent prefetch_cmd = { > @@ -699,30 +701,54 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > smmu = master->smmu; > } > > - if (smmu_domain) > - s2_cfg = &smmu_domain->s2_cfg; > + if (smmu_domain) { > + switch (smmu_domain->stage) { > + case ARM_SMMU_DOMAIN_NESTED: > + s1_cfg = &smmu_domain->s1_cfg; > + fallthrough; > + case ARM_SMMU_DOMAIN_S2: > + s2_cfg = &smmu_domain->s2_cfg; > + break; > + default: > + break; > + } > + translate = !!s1_cfg || !!s2_cfg; NIT: translate is a bool. So do you actually need the !!? > + } > > if (val & STRTAB_STE_0_V) { > switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { > case STRTAB_STE_0_CFG_BYPASS: > break; > + case STRTAB_STE_0_CFG_S1_TRANS: > + s1_live = true; > + break; > case STRTAB_STE_0_CFG_S2_TRANS: > - ste_live = true; > + s2_live = true; > + break; > + case STRTAB_STE_0_CFG_NESTED: > + s1_live = true; > + s2_live = true; > break; > case STRTAB_STE_0_CFG_ABORT: > - BUG_ON(!disable_bypass); I am not sure I understand why this was removed. Can you clarify? > break; > default: > BUG(); /* STE corruption */ > } > } > > + ste_live = s1_live || s2_live; > + > /* Nuke the existing STE_0 value, as we're going to rewrite it */ > val = STRTAB_STE_0_V; > > /* Bypass/fault */ > - if (!smmu_domain || !(s2_cfg)) { > - if (!smmu_domain && disable_bypass) > + if (!smmu_domain) > + abort = disable_bypass; > + else > + abort = smmu_domain->abort; > + > + if (abort || !translate) { > + if (abort) > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); > else > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); > @@ -740,7 +766,33 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > return; > } > > + if (ste_live) { > + /* First invalidate the live STE */ > + dst[0] = cpu_to_le64(STRTAB_STE_0_CFG_ABORT); > + arm_smmu_sync_ste_for_sid(smmu, sid); > + } > + > + if (s1_cfg) { > + BUG_ON(s1_live); > + dst[1] = cpu_to_le64( > + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | > + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | > + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | > + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | > + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); > + > + if (smmu->features & ARM_SMMU_FEAT_STALLS && > + !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) > + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); > + > + val |= (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) | > + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | > + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | > + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); > + } > + > if (s2_cfg) { > + u64 vttbr = s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK; > u64 strtab = > FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | > FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | > @@ -750,12 +802,19 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | > STRTAB_STE_2_S2R; > > - BUG_ON(ste_live); > + if (s2_live) { > + u64 s2ttb = le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK; > + BUG_ON(s2ttb != vttbr); > + } > + > dst[2] = cpu_to_le64(strtab); > > - dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > + dst[3] = cpu_to_le64(vttbr); > > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); > + } else { > + dst[2] = 0; > + dst[3] = 0; > } > > if (master->ats_enabled) > @@ -1254,6 +1313,15 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, > { > int ret; > struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED && > + (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || > + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) { > + dev_info(smmu_domain->smmu->dev, > + "does not implement two stages\n"); > + return -EINVAL; > + } > > /* Restrict the stage to what we can actually support */ > smmu_domain->stage = ARM_SMMU_DOMAIN_S2; > @@ -2353,11 +2421,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) > break; > } > > + if (reg & IDR0_S1P) > + smmu->features |= ARM_SMMU_FEAT_TRANS_S1; > + > if (reg & IDR0_S2P) > smmu->features |= ARM_SMMU_FEAT_TRANS_S2; > > - if (!(reg & IDR0_S2P)) { > - dev_err(smmu->dev, "no stage-2 translation support!\n"); > + if (!(reg & (IDR0_S1P | IDR0_S2P))) { I believe the behavior is now slightly different. This would not print anything if the SMMU support stage-1 but not stage-2. However, Xen at least need the latter. > + dev_err(smmu->dev, "no translation support!\n"); > return -ENXIO; > } > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h > index ab1f29f6c7..3fb13b7e21 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.h > +++ b/xen/drivers/passthrough/arm/smmu-v3.h > @@ -197,6 +197,7 @@ > #define STRTAB_STE_0_CFG_BYPASS 4 > #define STRTAB_STE_0_CFG_S1_TRANS 5 > #define STRTAB_STE_0_CFG_S2_TRANS 6 > +#define STRTAB_STE_0_CFG_NESTED 7 > > #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) > #define STRTAB_STE_0_S1FMT_LINEAR 0 > @@ -549,6 +550,12 @@ struct arm_smmu_strtab_l1_desc { > dma_addr_t l2ptr_dma; > }; > > +struct arm_smmu_s1_cfg { > + u64 s1ctxptr; > + u8 s1fmt; > + u8 s1cdmax; > +}; > + > struct arm_smmu_s2_cfg { > u16 vmid; > u64 vttbr; > @@ -669,7 +676,9 @@ struct arm_smmu_domain { > atomic_t nr_ats_masters; > > enum arm_smmu_domain_stage stage; > + struct arm_smmu_s1_cfg s1_cfg; > struct arm_smmu_s2_cfg s2_cfg; > + bool abort; I think there might be some padding before s1_cfg. So I wonder whether this would be better be moved before to reduce the size of the structure. > > /* Xen domain associated with this SMMU domain */ > struct domain *d; Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 02:22:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 02:22:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281425.1564329 (Exim 4.92) (envelope-from ) id 1wCTPc-0002OF-LY; Tue, 14 Apr 2026 02:22:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281425.1564329; Tue, 14 Apr 2026 02:22:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTPc-0002O8-J4; Tue, 14 Apr 2026 02:22:00 +0000 Received: by outflank-mailman (input) for mailman id 1281425; Tue, 14 Apr 2026 02:21:59 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCTPb-0002O0-4y for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 02:21:59 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCTPa-001RpZ-0B; Tue, 14 Apr 2026 02:21:58 +0000 Received: from [116.84.110.196] (helo=[10.158.125.74]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCTPZ-001WFu-2S; Tue, 14 Apr 2026 02:21:57 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=/mKi+oHOvJtVh86QkdJWZmXPzkAj7tH9N7+wbcpLyCQ=; b=c1IFRaEjqGaw8efOCAalfg8Fag 7ZXSAog3x4dTqYNAaDoLFm7FhVGohBwKhtMqFlcCLehItr8NNaTI+DQNxXsXqbE2/RAJ5u0Q2UmzL 9pprwm2sutNSOt2vj3HTdN3IoLwL2wdI8FCOCD697ZeI3zof5qBTlHE7y90unyYoE3JM=; Message-ID: Date: Tue, 14 Apr 2026 11:21:52 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 00/23] Add SMMUv3 Stage 1 Support for Xen guests Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Bertrand Marquis , Rahul Singh , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Nick Rosbrook , George Dunlap , Juergen Gross , "Daniel P. Smith" References: From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:51, Milan Djokic wrote: > This patch series provides emulated SMMUv3 support in Xen, enabling stage-1 > translation for the guest OS. > > Stage 1 translation support is required to provide isolation between different > devices within OS. Xen already supports Stage 2 translation but there is no > support for Stage 1 translation. The goal of this work is to support Stage 1 > translation for Xen guests. > > This patch series represents a continuation of work from Rahul Singh: > https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.singh@arm.com/ > Original patch series is aligned with the newest Xen structure, with the addition > of translation layer which provides 1:N vIOMMU->pIOMMU mapping, in order to > support passthrough of the devices attached to different physical IOMMUs. > > We cannot trust the guest OS to control the SMMUv3 hardware directly as > compromised guest OS can corrupt the SMMUv3 configuration and make the system > vulnerable. The guest gets the ownership of the stage 1 page tables and also > owns stage 1 configuration structures. The Xen handles the root configuration > structure (for security reasons), including the stage 2 configuration. > > XEN will emulate the SMMUv3 hardware and expose the virtual SMMUv3 to the > guest. Guest can use the native SMMUv3 driver to configure the stage 1 > translation. When the guest configures the SMMUv3 for Stage 1, XEN will trap > the access and configure hardware. > > SMMUv3 Driver(Guest OS) -> Configure the Stage-1 translation -> > XEN trap access -> XEN SMMUv3 driver configure the HW. > > The final patch series commit provides a design document for the emulated > IOMMU (arm-viommu.rst), which was previously discussed with the maintainers. > Details regarding implementation, future work and security risks are outlined > in this document. > > --- > Changes in v2: > - Updated design and implementation with vIOMMU->pIOMMU mapping layer > - Addressed security risks in the design, provided initial performance > measurements > - Addressed comments from previous version > - Tested on Renesas R-Car platform, initial performance measurements for > stage-1 vs stage-1-less guests > --- > > --- > Changes in v3: > - Bump domctl version, added explicit padding for the new domctl structures > - Remove unnecessary changes according to review comments > - Add "ARM" prefix for vIOMMU Kconfig options, since only ARM architecture is > supported at this point > - Re-generate go code > - Add missing commit sign-off tags Can you please avoid posting new revision in reply-to a previous one? This makes tracking quite difficult on the reviewer side. So I ended up starting to post comments on v2. Please have a look at them. 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Subject: [PATCH] xen/arm64: flushtlb: Optimize ARM64_WORKAROUND_REPEAT_TLBI Date: Tue, 14 Apr 2026 10:11:24 +0200 Message-ID: <20260414081124.48741-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022574:EE_|SJ5PPFD5E8DE351:EE_ X-MS-Office365-Filtering-Correlation-Id: 182f4983-c2c1-467b-24c8-08de99fd74bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|13003099007|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: Vb0imuJC/sTDyw+CSlUnl7zUUfRn36atApgSsOxsRIDdCP/4iPUh2Ms2RmWCAym0Xd6r3GwI3I+ky90sJY/vqu74LcHVnsJUA9lofhoDnkvy3H8JAO0dKfnf4jyR2ZevuED8axlOvB7ARIclBKuORGUMdOND8c5uUkKx9auNNdCfYfvxtpXa+yGoGZngo0+vD6p4kd+LPGxEznPEN0N80Q7V+pHATWbv1jfZgkIRLps4gExp/k7j2uXD3spP0nhHMW2QBrVRh1J/yX4lTrZxD3pwzIb+YqoWZzrlzeh6+9PNFiZhheTTl+QH5CLi25oh/eKI85LARvY97yDIRrpfh2Apgefi8GKwX+VByCVmx8oIyOaKI83Y1cgGC7wsrJH2Zmli+g1e4F1gZCgTyKcYIKyKlAWno7S++YD0vBfo6/L/YL5/IlEkROLyiMWydBA6YzifrAOubuCuWrA+7gh6+uwAKui1Gqk9OdCpYXB9rR8KE8eRAtUrmyi6nGfkxmhRMfEAT3q2phSiyHMn4vIYbKyyeVQOZ3bi83uxLWu76YN7RD3Zv5n99AewG74gNsmVrzjsliZBm4DY/h9zik6EuHpbEdJSyjkLp1YhYuFSTb/qBRE+RWon8UPaoXAcwmFyazrUFYaUtoRbwxRbExcw5zGuBcsoHFF2KH5EnFUdB8v1mGjTL9Rjx1H1LKsJIrE8o812jWKVoAnfsSTqwq0IDWPdyibouJKITC+t047zJPgS6sTyYmBYy6BZ44rkSJCZZMIjy+iaMnG49H1IJjXrzA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(13003099007)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o1kFbWFtiK3xeI1aUlgDvbUumLAYh/h+ajwt3ii+FpIdIjWjilwDpqSyIP1L3m78pyCoF3HMhgh//Ak1pjkfwXODCQ03lLr8iDjBvLhyxz8HU/uXbJkqa4rHzpbh7VjSyaMXh5uRQ4+4WtwjiXTkD+yQAT+EbfAm+8/1yvmYxdEqlfGDP3PAghehknGaAiNqro9dsHxuTRvqmWIYbuktXW3aTiDzsLW4ZEctdaNCyEmrxN/frMIRyujyfP8/E4xIXZ83QA21mhSkg5FajU1ScBOTryrXg9NehFw+qKddKXHs11TTMxuW6opoAhGqUNfR09tOOk2ZSNBRv99PlQLeF9XSqqO92JR7GaKApxey21snfhhE53AmSV8dv+PhrBv6uKGBRW5pbukIhoAUkQgFcswa+dXTU42Tqn52QaFoCH9MHUWYUk03YT61eqKnb1uG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2026 08:11:39.7012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 182f4983-c2c1-467b-24c8-08de99fd74bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFD5E8DE351 X-purgate-ID: tlsNG-c1860d/1776154307-F6151497-20639DC2/0/0 X-purgate-type: clean X-purgate-size: 12302 The ARM64_WORKAROUND_REPEAT_TLBI workaround is used to mitigate several errata where broadcast TLBI;DSB sequences don't provide all the architecturally required synchronization. The workaround performs more work than necessary, and can have significant overhead. This patch optimizes the workaround, as explained below. 1. All relevant errata only affect the ordering and/or completion of memory accesses which have been translated by an invalidated TLB entry. The actual invalidation of TLB entries is unaffected. 2. The existing workaround is applied to both broadcast and local TLB invalidation, whereas for all relevant errata it is only necessary to apply a workaround for broadcast invalidation. 3. The existing workaround replaces every TLBI with a TLBI;DSB;TLBI sequence, whereas for all relevant errata it is only necessary to execute a single additional TLBI;DSB sequence after any number of TLBIs are completed by a DSB. For example, for a sequence of batched TLBIs: TLBI [, ] TLBI [, ] TLBI [, ] DSB ISH ... the existing workaround will expand this to: TLBI [, ] DSB ISH // additional TLBI [, ] // additional TLBI [, ] DSB ISH // additional TLBI [, ] // additional TLBI [, ] DSB ISH // additional TLBI [, ] // additional DSB ISH ... whereas it is sufficient to have: TLBI [, ] TLBI [, ] TLBI [, ] DSB ISH TLBI [, ] // additional DSB ISH // additional Using a single additional TBLI and DSB at the end of the sequence can have significantly lower overhead as each DSB which completes a TLBI must synchronize with other PEs in the system, with potential performance effects both locally and system-wide. 4. The existing workaround repeats each specific TLBI operation, whereas for all relevant errata it is sufficient for the additional TLBI to use *any* operation which will be broadcast, regardless of which translation regime or stage of translation the operation applies to. For example, for a single TLBI: TLBI ALLE2IS DSB ISH ... the existing workaround will expand this to: TLBI ALLE2IS DSB ISH TLBI ALLE2IS // additional DSB ISH // additional ... whereas it is sufficient to have: TLBI ALLE2IS DSB ISH TLBI VALE1IS, XZR // additional DSB ISH // additional As the additional TLBI doesn't have to match a specific earlier TLBI, the additional TLBI can be implemented in separate code, with no memory of the earlier TLBIs. The additional TLBI can also use a cheaper TLBI operation. 5. The existing workaround is applied to both Stage-1 and Stage-2 TLB invalidation, whereas for all relevant errata it is only necessary to apply a workaround for Stage-1 invalidation. Architecturally, TLBI operations which invalidate only Stage-2 information (e.g. IPAS2E1IS) are not required to invalidate TLB entries which combine information from Stage-1 and Stage-2 translation table entries, and consequently may not complete memory accesses translated by those combined entries. In these cases, completion of memory accesses is only guaranteed after subsequent invalidation of Stage-1 information (e.g. VMALLE1IS). Rework the workaround logic as follows: - add TLB_HELPER_LOCAL() to be used for local TLB ops without a workaround, - modify TLB_HELPER() workaround to use tlbi vale2is, xzr as a second TLB, - drop TLB_HELPER_VA(). It's used only by __flush_xen_tlb_one_local which is local and does not need workaround and by __flush_xen_tlb_one. In the latter case, since it's used in a loop, we don't need a workaround in the middle. Add __tlb_repeat_sync with a workaround to be used at the end after DSB and before final ISB, - TLBI VALE2IS passing XZR is used as an additional TLBI. While there is an identity mapping there, it's used very rarely. The performance impact is therefore negligible. If things change in the future, we can revisit the decision. Signed-off-by: Michal Orzel --- Linux counterpart (already merged): https://lore.kernel.org/linux-arm-kernel/20260218164348.2022831-1-mark.rutland@arm.com/ --- xen/arch/arm/include/asm/arm32/flushtlb.h | 3 + xen/arch/arm/include/asm/arm64/flushtlb.h | 108 ++++++++++++++-------- xen/arch/arm/include/asm/flushtlb.h | 1 + 3 files changed, 71 insertions(+), 41 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/flushtlb.h b/xen/arch/arm/include/asm/arm32/flushtlb.h index 61c25a318998..5483be08fbbe 100644 --- a/xen/arch/arm/include/asm/arm32/flushtlb.h +++ b/xen/arch/arm/include/asm/arm32/flushtlb.h @@ -57,6 +57,9 @@ static inline void __flush_xen_tlb_one(vaddr_t va) asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); } +/* Only for ARM64_WORKAROUND_REPEAT_TLBI */ +static inline void __tlb_repeat_sync(void) {} + #endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */ /* * Local variables: diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h index 3b99c11b50d1..1606b26bf28a 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -12,9 +12,14 @@ * ARM64_WORKAROUND_REPEAT_TLBI: * Modification of the translation table for a virtual address might lead to * read-after-read ordering violation. - * The workaround repeats TLBI+DSB ISH operation for all the TLB flush - * operations. While this is strictly not necessary, we don't want to - * take any risk. + * The workaround repeats TLBI+DSB ISH operation for broadcast TLB flush + * operations. The workaround is not needed for local operations. + * + * It is sufficient for the additional TLBI to use *any* operation which will + * be broadcast, regardless of which translation regime or stage of translation + * the operation applies to. TLBI VALE2IS is used passing XZR. While there is + * an identity mapping there, it's only used during suspend/resume, CPU on/off, + * so the impact (performance if any) is negligible. * * For Xen page-tables the ISB will discard any instructions fetched * from the old mappings. @@ -26,69 +31,90 @@ * Note that for local TLB flush, using non-shareable (nsh) is sufficient * (see D5-4929 in ARM DDI 0487H.a). Although, the memory barrier in * for the workaround is left as inner-shareable to match with Linux - * v6.1-rc8. + * v6.19. */ -#define TLB_HELPER(name, tlbop, sh) \ +#define TLB_HELPER_LOCAL(name, tlbop) \ static inline void name(void) \ { \ asm_inline volatile ( \ - "dsb " # sh "st;" \ + "dsb nshst;" \ "tlbi " # tlbop ";" \ - ALTERNATIVE( \ - "nop; nop;", \ - "dsb ish;" \ - "tlbi " # tlbop ";", \ - ARM64_WORKAROUND_REPEAT_TLBI, \ - CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ - "dsb " # sh ";" \ + "dsb nsh;" \ "isb;" \ : : : "memory"); \ } -/* - * FLush TLB by VA. This will likely be used in a loop, so the caller - * is responsible to use the appropriate memory barriers before/after - * the sequence. - * - * See above about the ARM64_WORKAROUND_REPEAT_TLBI sequence. - */ -#define TLB_HELPER_VA(name, tlbop) \ -static inline void name(vaddr_t va) \ -{ \ - asm_inline volatile ( \ - "tlbi " # tlbop ", %0;" \ - ALTERNATIVE( \ - "nop; nop;", \ - "dsb ish;" \ - "tlbi " # tlbop ", %0;", \ - ARM64_WORKAROUND_REPEAT_TLBI, \ - CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ - : : "r" (va >> PAGE_SHIFT) : "memory"); \ +#define TLB_HELPER(name, tlbop) \ +static inline void name(void) \ +{ \ + asm_inline volatile ( \ + "dsb ishst;" \ + "tlbi " # tlbop ";" \ + ALTERNATIVE( \ + "nop; nop;", \ + "dsb ish;" \ + "tlbi vale2is, xzr;", \ + ARM64_WORKAROUND_REPEAT_TLBI, \ + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ + "dsb ish;" \ + "isb;" \ + : : : "memory"); \ } /* Flush local TLBs, current VMID only. */ -TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh) +TLB_HELPER_LOCAL(flush_guest_tlb_local, vmalls12e1) /* Flush innershareable TLBs, current VMID only */ -TLB_HELPER(flush_guest_tlb, vmalls12e1is, ish) +TLB_HELPER(flush_guest_tlb, vmalls12e1is) /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb_local, alle1, nsh) +TLB_HELPER_LOCAL(flush_all_guests_tlb_local, alle1) /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb, alle1is, ish) +TLB_HELPER(flush_all_guests_tlb, alle1is) /* Flush all hypervisor mappings from the TLB of the local processor. */ -TLB_HELPER(flush_xen_tlb_local, alle2, nsh) +TLB_HELPER_LOCAL(flush_xen_tlb_local, alle2) + +#undef TLB_HELPER_LOCAL +#undef TLB_HELPER + +/* + * FLush TLB by VA. This will likely be used in a loop, so the caller + * is responsible to use the appropriate memory barriers before/after + * the sequence. + */ /* Flush TLB of local processor for address va. */ -TLB_HELPER_VA(__flush_xen_tlb_one_local, vae2) +static inline void __flush_xen_tlb_one_local(vaddr_t va) +{ + asm_inline volatile ( + "tlbi vae2, %0" : : "r" (va >> PAGE_SHIFT) : "memory"); +} /* Flush TLB of all processors in the inner-shareable domain for address va. */ -TLB_HELPER_VA(__flush_xen_tlb_one, vae2is) +static inline void __flush_xen_tlb_one(vaddr_t va) +{ + asm_inline volatile ( + "tlbi vae2is, %0" : : "r" (va >> PAGE_SHIFT) : "memory"); +} -#undef TLB_HELPER -#undef TLB_HELPER_VA +/* + * ARM64_WORKAROUND_REPEAT_TLBI: + * For all relevant erratas it is only necessary to execute a single + * additional TLBI;DSB sequence after any number of TLBIs are completed by DSB. + */ +static inline void __tlb_repeat_sync(void) +{ + asm_inline volatile ( + ALTERNATIVE( + "nop; nop;", + "tlbi vale2is, xzr;" + "dsb ish;", + ARM64_WORKAROUND_REPEAT_TLBI, + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) + : : : "memory"); +} #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm/flushtlb.h index e45fb6d97b02..c292c3c00d29 100644 --- a/xen/arch/arm/include/asm/flushtlb.h +++ b/xen/arch/arm/include/asm/flushtlb.h @@ -65,6 +65,7 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, va += PAGE_SIZE; } dsb(ish); /* Ensure the TLB invalidation has completed */ + __tlb_repeat_sync(); isb(); } -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 08:30:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 08:30:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281465.1564352 (Exim 4.92) (envelope-from ) id 1wCZAB-0003zL-KT; Tue, 14 Apr 2026 08:30:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281465.1564352; Tue, 14 Apr 2026 08:30:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZAB-0003zE-HU; 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Tue, 14 Apr 2026 08:30:22 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 13a796e5373942fc88336edd7b0df515; Tue, 14 Apr 2026 08:30:22 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776155422; x=1776425422; bh=twDtVKfWbW1DxGQO9l+h7kZSrEa6BM5hE+mqdHaJ/zE=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=KaW88MzTW1vy5/Qf0DSDs59OcQiKPi3z3A+InpRA57sPzSSRmP5pAWjsGSUrNWGfH nVZ7qrn3hsNsBvkEVZSBExnpZFfuKd89hszJ2hDciAeRfMK3lFut9SomR3A162alwF ksLd4E3k0l3uwXyNtEnlhPp9c4V5WKmZeEvUCuNZH/fA8VJJn7PWio/DZXbaDw3l80 6RwBo1VcY2hI/uUSS6wd0V9w1b7Ngb9jfy/VEcNz1rMKFGPVWvSzRVy1d9p9A6yVTf QoyE43VuJx41sN2uS3ZJ0ktOKXJF7wskFIXxgJLt64Lkxma4IRr18WnRaVsL45P8fu XE4uwAW8h/q4Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776155422; x=1776415922; i=teddy.astie@vates.tech; bh=twDtVKfWbW1DxGQO9l+h7kZSrEa6BM5hE+mqdHaJ/zE=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=hSWSgQbvGThdcMnF5iVnQ2BWc3+iWBOFNXpDVoYkBF+BXDMYOsnpbFrm3M0DjMGpi RtVxKFSE4QiEg5DU2jeVlDxxcXXM5VhZAgRI3IySfLF2ezr1nKbf+YXRyut2F/+gbZ L1xg63sbm0w9osjZBJRjGtuqBMI9WrPSMcJGjbUbp9l9d9zL/rFnTlOKsqFCKIyL1N LYKSDg+eB0em+vkjv1JlcIzzreprTSCovey6/17/yOpNBnTnul2WOT9GCXR95uKpvG /AzmZc0KPVFP/3OykCyD0Bif1y+wUgXwK9s/PSZ7Wpp/5Tu0aqVYYkWiyH5wjg3wRI sVcshIcj/wquQ== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=20v3=201/3]=20xl:=20Add=20pci=20device=20hotplug=20option?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776155421888 Message-Id: <4c058f15-7396-4c06-8886-b77c56dfb14f@vates.tech> To: "Thierry Escande" , xen-devel@lists.xenproject.org Cc: "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" References: <20260410150333.1533568-1-thierry.escande@vates.tech> <20260410150333.1533568-2-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-2-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.13a796e5373942fc88336edd7b0df515?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260414:md Date: Tue, 14 Apr 2026 08:30:22 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1776155424-8BB4041E-2B272237/0/0 X-purgate-type: clean X-purgate-size: 3257 Le 10/04/2026 =C3=A0 17:06, Thierry Escande a =C3=A9crit=C2=A0: > This option is used to passthrough PCI devices using the Qemu command > line (-device driver,...) instead of the QMP hot-plug mechanism. > > This is needed for Q35 support since its PCI root bus doesn't support > hotplugging. > > If not specified, the default behavior is to use hotplug via QMP. > > Signed-off-by: Thierry Escande > --- > v2: no change > v3: no change > --- > tools/libs/light/libxl_types.idl | 1 + > tools/libs/util/libxlu_pci.c | 2 ++ > tools/xl/xl_parse.c | 5 +++++ > 3 files changed, 8 insertions(+) > > diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_ty= pes.idl > index a7893460f0..aca0e93793 100644 > --- a/tools/libs/light/libxl_types.idl > +++ b/tools/libs/light/libxl_types.idl > @@ -922,6 +922,7 @@ libxl_device_pci =3D Struct("device_pci", [ > ("seize", bool), > ("rdm_policy", libxl_rdm_reserve_policy), > ("name", string), > + ("hotplug", bool), > ]) > > libxl_device_rdm =3D Struct("device_rdm", [ > diff --git a/tools/libs/util/libxlu_pci.c b/tools/libs/util/libxlu_pci.c > index 294482c6d7..f6440c878b 100644 > --- a/tools/libs/util/libxlu_pci.c > +++ b/tools/libs/util/libxlu_pci.c > @@ -192,6 +192,8 @@ int xlu_pci_parse_spec_string(XLU_Config *cfg, libxl_= device_pci *pci, > name_present =3D true; > pci->name =3D strdup(val); > if (!pci->name) ret =3D ERROR_NOMEM; > + } else if (!strcmp(key, "hotplug")) { > + pci->hotplug =3D atoi(val); > } else { > XLU__PCI_ERR(cfg, "Unknown PCI_SPEC_STRING option: %s", key= ); > ret =3D ERROR_INVAL; > diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c > index 48c72dce9c..7ea2a76662 100644 > --- a/tools/xl/xl_parse.c > +++ b/tools/xl/xl_parse.c > @@ -1361,6 +1361,7 @@ void parse_config_data(const char *config_source, > int pci_msitranslate =3D 0; > int pci_permissive =3D 0; > int pci_seize =3D 0; > + int pci_hotplug =3D 1; > int i, e; > int num_llc_colors; > int num_xs_quota; > @@ -1699,6 +1700,9 @@ void parse_config_data(const char *config_source, > if (!xlu_cfg_get_long (config, "pci_seize", &l, 0)) > pci_seize =3D l; > > + if (!xlu_cfg_get_long (config, "pci_hotplug", &l, 0)) > + pci_hotplug =3D l; > + > if (!xlu_cfg_get_string(config, "rdm", &buf, 0)) { > libxl_rdm_reserve rdm; > if (!xlu_rdm_parse(config, &rdm, buf)) { > @@ -1720,6 +1724,7 @@ void parse_config_data(const char *config_source, > pci->power_mgmt =3D pci_power_mgmt; > pci->permissive =3D pci_permissive; > pci->seize =3D pci_seize; > + pci->hotplug =3D pci_hotplug; > /* > * Like other pci option, the per-device policy always foll= ows > * the global policy by default. Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:03:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:03:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281480.1564368 (Exim 4.92) (envelope-from ) id 1wCZfZ-0008AM-Aj; Tue, 14 Apr 2026 09:02:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281480.1564368; Tue, 14 Apr 2026 09:02:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZfZ-0008AF-83; Tue, 14 Apr 2026 09:02:53 +0000 Received: by outflank-mailman (input) for mailman id 1281480; Tue, 14 Apr 2026 09:02:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZfY-0008A5-Kd for xen-devel@lists.xenproject.org; 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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776157191; x=1776427191; bh=8jPI6VgNJMTJNIvIHMSppJhg9KypSLlcd8SYkTbpLig=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=T3Zor9C52AcN957CmzdR6gij3hs/UD+/NF4ku8IuVvqx57Zf7jnOmzgsP2X53u7qH hLCh2sFMrnw6YzNHjpD7Yhh0su+I6E/RTKy1vn2Otk7hB8AXn+V5Sb6fsQEFPIT3S1 G9jFD52dQyz2vnEWD9h8FsYtWztDxtdwY1M/Npda2TYo5E0OKR9Aj6FSdXYkG5byzs Do0O6Jc4M6EOZpmDfAHlTm4cG3Qu3C4PyCSS0Xe8+EiC8Qxx+8uIOFiaGYr+0gAQV2 Bg0nSz1dswDyKJOteWkT4I4UBxLvA7/fpBGDFnxURwS1Vz/vhONFAYDm6xlrNSc3Va b9kfdN1be4F1w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776157191; x=1776417691; i=teddy.astie@vates.tech; bh=8jPI6VgNJMTJNIvIHMSppJhg9KypSLlcd8SYkTbpLig=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=ajdXIbbOT8V+fkiigRG3cTwnPBcHYOaUlDxN69Yt1irH5yTFG+HmfzvIlSzNj8myx c2wr1nvttUzE3aDu45CgcekS2FcTOFnJgP8WFtXr0pfKjdWm1jVTUQL5urjxvYHgsV mx/0FywqR2OCIcvpCx6zMlihb8ZyBxAgOQPiLNp8KEknoqPic5uJOYu/IQcqZSJFFx rC4VRmTZuaTi2u8fUdbXgks1RoWnQ7uKVTwFr1uszu38aNOqMLSf9aAFRcu+/siAci vAYu57opIEvk8ZQpR568+PomoaW/u8mKHyo+oBLzjgRB+yhNfPdwE1k6vrpjMsh40X GV0s47gdrDC8w== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=20v3=202/3]=20libxl:=20Allow=20PCI=20device=20passthrough=20using=20-device=20Qemu=20command=20line?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776157191140 Message-Id: To: "Thierry Escande" , xen-devel@lists.xenproject.org Cc: "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" References: <20260410150333.1533568-1-thierry.escande@vates.tech> <20260410150333.1533568-3-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-3-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.b9680d33670344a88a98b650cd451bf3?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260414:md Date: Tue, 14 Apr 2026 08:59:51 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1776157370-8055FA3D-F07BA524/0/0 X-purgate-type: clean X-purgate-size: 13699 Le 10/04/2026 =C3=A0 17:06, Thierry Escande a =C3=A9crit=C2=A0: > This change makes use of the new option 'hotplug' for host PCI devices > passthrough'd to the guest. If hotplug=3D0 is used in the pci device > configuration table, the device will be attached to the guest using the > Qemu command line as '-device xen-pci-passthrough,hostaddr=3D...' > > The host device configuration is passed to the -device option as a json > array, just like it's done for hotplug using QMP. The json array is > created by a new internal function libxl__device_pci_get_qmp_json() that > is also used by pci_add_qmp_device_add(). If (in this specific case) we're not using QMP anymore, I think libxl__device_pci_get_qmp_json should lose the "qmp" qualification. (unless QEMU also considers JSON-formatted command-line paramters as QMP) > > Then, instead of sending the 'device_add' command, the device_add > callback is called to perform the 'query-pci' check to make sure the > passthrough'd device is present. > > In the same way at shutdown, the device is not removed using QMP and > only the pci_remove_done() function is called. > > As with QMP, the use of the 'hotplug=3D0' option honors the 'seize' optio= n > by adding the PCI device to the assignable list if needed. This mimics > what is done in libxl__device_pci_add() with regards to seize option and > the assignable PCI device list. This allows to display a proper error > message if the device is not assignable before Qemu starts. > To do so the function pciback_dev_is_assigned() has been renamed as > libxl__pciback_dev_is_assigned() and made available internally, as well > as libxl__device_pci_assignable_add(). Also, libxl_pci_assignable() is > now exported in libxl.h and renamed as libxl_device_pci_assignable() > since its prototype looks like the other libxl_device_pci_*() APIs. > > Example use: > pci =3D [ "00:03.0,seize=3D1,hotplug=3D0" ] > > Signed-off-by: Thierry Escande > --- > v2: > - Add support for YAJL json parser > > v3: > - Move code block for device command line parameters creation to a > correct place. > - Better handling of PCI device assignation check to display the correct > error message if the device is not assignable. > --- > tools/include/libxl.h | 1 + > tools/libs/light/libxl_dm.c | 85 +++++++++++++++++++++++++++++++ > tools/libs/light/libxl_internal.h | 7 +++ > tools/libs/light/libxl_pci.c | 57 ++++++++++++++------- > 4 files changed, 132 insertions(+), 18 deletions(-) > > diff --git a/tools/include/libxl.h b/tools/include/libxl.h > index 7c098edab6..efd2664a90 100644 > --- a/tools/include/libxl.h > +++ b/tools/include/libxl.h > @@ -2666,6 +2666,7 @@ int libxl_device_pci_assignable_add(libxl_ctx *ctx,= libxl_device_pci *pci, int r > int libxl_device_pci_assignable_remove(libxl_ctx *ctx, libxl_device_pci= *pci, int rebind); > libxl_device_pci *libxl_device_pci_assignable_list(libxl_ctx *ctx, int = *num); > void libxl_device_pci_assignable_list_free(libxl_device_pci *list, int = num); > +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci); > > /* CPUID handling */ > int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char= * str); > diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c > index 511ec76a65..28e4adbd4f 100644 > --- a/tools/libs/light/libxl_dm.c > +++ b/tools/libs/light/libxl_dm.c > @@ -1798,6 +1798,91 @@ static int libxl__build_device_model_args_new(libx= l__gc *gc, > break; > } > > + if (guest_config->num_pcidevs) { > + libxl_device_pci *pci; > + libxl__json_object *qmp_json; > + char *json_str; > +#ifdef HAVE_LIBJSONC > + json_object *jso; > + const char *buf; > +#elif defined(HAVE_LIBYAJL) > + yajl_gen hand; > + /* memory for 'buf' is owned by 'hand' */ > + const unsigned char *buf; > + libxl_yajl_length len; > +#else > +# error Missing JSON library > +#endif > + > + for (i =3D 0; i < guest_config->num_pcidevs; i++) { > + pci =3D &guest_config->pcidevs[i]; > + > + if (pci->hotplug) > + continue; > + > + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pc= i)) { > + rc =3D libxl__device_pci_assignable_add(gc, pci, 1); > + if (rc) > + return rc; > + }> + > + if (!libxl_device_pci_assignable(libxl__gc_owner(gc), pc= i)) { > + LOGD(ERROR, guest_domid, "PCI device %x:%x:%x.%x is = not assignable", > + pci->domain, pci->bus, pci->dev, pci->func); > + return ERROR_FAIL; > + } > + > + qmp_json =3D libxl__device_pci_get_qmp_json(gc, pci); > + > +#ifdef HAVE_LIBJSONC > + rc =3D libxl__json_object_to_json_object(gc, &jso, qmp_j= son); > + if (rc) > + return rc; > + > + buf =3D json_object_to_json_string_ext(jso, > + JSON_C_TO_STRING_PL= AIN); > + if (!buf) { > + json_object_put(jso); > + return ERROR_NOMEM; > + } > +#elif defined(HAVE_LIBYAJL) > + hand =3D libxl_yajl_gen_alloc(NULL); > + if (!hand) { > + return ERROR_NOMEM; > + } > +#if HAVE_YAJL_V2 > + /* Disable beautify for data sent to QEMU */ > + yajl_gen_config(hand, yajl_gen_beautify, 0); > +#endif > + > + rc =3D libxl__json_object_to_yajl_gen(gc, hand, qmp_json= ); > + if (rc) { > + yajl_gen_free(hand); > + return rc; > + } > + > + rc =3D yajl_gen_get_buf(hand, &buf, &len); > + if (rc !=3D yajl_gen_status_ok) { > + yajl_gen_free(hand); > + return rc; > + } > +#endif > + > + json_str =3D libxl__strdup(gc, (const char *)buf); > + if (json_str) > + flexarray_vappend(dm_args, "-device", json_str, NULL= ); > + > +#ifdef HAVE_LIBJSONC > + json_object_put(jso); > +#elif defined(HAVE_LIBYAJL) > + yajl_gen_free(hand); > +#endif > + > + if (!json_str) > + return ERROR_NOMEM; > + } > + } > + > if (state->dm_runas) { > if (qemu_opts->have_runwith_user) { > flexarray_append_pair(dm_args, "-run-with", > diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_i= nternal.h > index b65e0064b9..cab2ab4526 100644 > --- a/tools/libs/light/libxl_internal.h > +++ b/tools/libs/light/libxl_internal.h > @@ -1729,6 +1729,13 @@ _hidden int libxl__device_pci_setdefault(libxl__gc= *gc, uint32_t domid, > libxl_device_pci *pci, bool ho= tplug); > _hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, > const libxl_domain_config *d_co= nfig); > +_hidden libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc= , > + libxl_device_pc= i *pci); > +_hidden int libxl__pciback_dev_is_assigned(libxl__gc *gc, > + libxl_device_pci *pci); > +_hidden int libxl__device_pci_assignable_add(libxl__gc *gc, > + libxl_device_pci *pci, > + int rebind); > > /* from libxl_dtdev */ > > diff --git a/tools/libs/light/libxl_pci.c b/tools/libs/light/libxl_pci.c > index 49d272d0de..07d005e71d 100644 > --- a/tools/libs/light/libxl_pci.c > +++ b/tools/libs/light/libxl_pci.c > @@ -686,7 +686,7 @@ out: > return rc; > } > > -static int pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) > +int libxl__pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) > { > char * spath; > int rc; > @@ -755,9 +755,9 @@ static int pciback_dev_unassign(libxl__gc *gc, libxl_= device_pci *pci) > return 0; > } > > -static int libxl__device_pci_assignable_add(libxl__gc *gc, > - libxl_device_pci *pci, > - int rebind) > +int libxl__device_pci_assignable_add(libxl__gc *gc, > + libxl_device_pci *pci, > + int rebind) > { > libxl_ctx *ctx =3D libxl__gc_owner(gc); > unsigned dom, bus, dev, func; > @@ -798,7 +798,7 @@ static int libxl__device_pci_assignable_add(libxl__gc= *gc, > } > > /* Check to see if it's already assigned to pciback */ > - rc =3D pciback_dev_is_assigned(gc, pci); > + rc =3D libxl__pciback_dev_is_assigned(gc, pci); > if ( rc < 0 ) { > return ERROR_FAIL; > } > @@ -913,7 +913,7 @@ static int libxl__device_pci_assignable_remove(libxl_= _gc *gc, > } > > /* Unbind from pciback */ > - if ( (rc =3D pciback_dev_is_assigned(gc, pci)) < 0 ) { > + if ( (rc =3D libxl__pciback_dev_is_assigned(gc, pci)) < 0 ) { > return ERROR_FAIL; > } else if ( rc ) { > pciback_dev_unassign(gc, pci); > @@ -1098,16 +1098,10 @@ out: > pci_add_dm_done(egc, pas, rc); /* must be last */ > } > > -static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) > +libxl__json_object *libxl__device_pci_get_qmp_json(libxl__gc *gc, > + libxl_device_pci *pci= ) > { > - STATE_AO_GC(pas->aodev->ao); > libxl__json_object *args =3D NULL; > - int rc; > - > - /* Convenience aliases */ > - libxl_domid domid =3D pas->domid; > - libxl_device_pci *pci =3D &pas->pci; > - libxl__ev_qmp *const qmp =3D &pas->qmp; > > libxl__qmp_param_add_string(gc, &args, "driver", > "xen-pci-passthrough"); > @@ -1134,11 +1128,30 @@ static void pci_add_qmp_device_add(libxl__egc *eg= c, pci_add_state *pas) > if (pci->permissive) > libxl__qmp_param_add_bool(gc, &args, "permissive", true); > > + return args; > +} > + > +static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) > +{ > + STATE_AO_GC(pas->aodev->ao); > + libxl__json_object *args =3D NULL; > + int rc =3D 0; > + > + /* Convenience aliases */ > + libxl_domid domid =3D pas->domid; > + libxl_device_pci *pci =3D &pas->pci; > + libxl__ev_qmp *const qmp =3D &pas->qmp; > + > + args =3D libxl__device_pci_get_qmp_json(gc, pci); > + > qmp->ao =3D pas->aodev->ao; > qmp->domid =3D domid; > qmp->payload_fd =3D -1; > qmp->callback =3D pci_add_qmp_device_add_cb; Is it expected to set this callback when !pci->hotplug (given it's the same than the one we call afterward) ? (I don't really know well how works libxl though) > - rc =3D libxl__ev_qmp_send(egc, qmp, "device_add", args); > + if (pci->hotplug) > + rc =3D libxl__ev_qmp_send(egc, qmp, "device_add", args); > + else > + pci_add_qmp_device_add_cb(egc, qmp, NULL, 0); > if (rc) goto out; > return; > > @@ -1509,7 +1522,7 @@ int libxl_device_pci_add(libxl_ctx *ctx, uint32_t d= omid, > return AO_INPROGRESS; > } > > -static bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) > +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) > { > libxl_device_pci *pcis; > int num; > @@ -1572,13 +1585,13 @@ void libxl__device_pci_add(libxl__egc *egc, uint3= 2_t domid, > rc =3D libxl__device_pci_setdefault(gc, domid, pci, !starting); > if (rc) goto out; > > - if (pci->seize && !pciback_dev_is_assigned(gc, pci)) { > + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pci)) { > rc =3D libxl__device_pci_assignable_add(gc, pci, 1); > if ( rc ) > goto out; > } > > - if (!libxl_pci_assignable(ctx, pci)) { > + if (!libxl_device_pci_assignable(ctx, pci)) { > LOGD(ERROR, domid, "PCI device %x:%x:%x.%x is not assignable", > pci->domain, pci->bus, pci->dev, pci->func); > rc =3D ERROR_FAIL; > @@ -1820,6 +1833,14 @@ static void do_pci_remove(libxl__egc *egc, pci_rem= ove_state *prs) > libxl_domain_type type =3D libxl__domain_type(gc, domid); > libxl_device_pci *pci =3D &prs->pci; > int rc, num; > + > + /* Passthrough'd device has been passed to Qemu command line so ther= e is > + * no need to remove it via QMP */ > + if (!pci->hotplug) { > + pci_remove_done(egc, prs, 0); > + return; > + } > + I think you can move the renaming/refactoring part into a separate patch and make the hotplug part separate. > pcis =3D libxl_device_pci_list(ctx, domid, &num); > if (!pcis) { > rc =3D ERROR_FAIL; -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:10:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:10:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281490.1564377 (Exim 4.92) (envelope-from ) id 1wCZmS-0000NP-0A; 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h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=OgneJo8boniEahu6IlKf5jd5eYgxhhqOruTjV/8JO9qa0EFGiwAYdVc7CZwwVhi0z riBDTg1nvXqwP9EPoSkm/cDTdyEq+RunhvjY9JKPRjnawqV4Ee2JVCYyBwmOD1EL58 Grzt7AQxwEJgRlQhAvgoRUzZq8dIdngOshGT9RaapYZFbqgNeNc3lUZ6nSO66wEDmQ GcIrK/Cm/YsbLssEbh9zR8rm2yxqFepYJvFuWIcSGxUHcb/SXkm5Wwu80OzzhrVI+C VbpMmjDR1gIonaD7vY5F57UVw6b2zCybi27sF30UFvSIuWVZ5db5RRH24KnXF2HjBX kvRIcOvUzTwrA== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=20v3=203/3]=20docs:=20provide=20description=20for=20pci=20hotplug=20option?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776157432758 Message-Id: To: "Thierry Escande" , xen-devel@lists.xenproject.org Cc: "Anthony PERARD" , "Juergen Gross" , "=?utf-8?Q?Daniel=20P=20.=20Berrang=C3=A9?=" , "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" References: <20260410150333.1533568-1-thierry.escande@vates.tech> <20260410150333.1533568-4-thierry.escande@vates.tech> In-Reply-To: <20260410150333.1533568-4-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.3bd3658f131248f4abab24c50165b9dc?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260414:md Date: Tue, 14 Apr 2026 09:03:53 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1776157797-449F4CD1-1B01D432/0/0 X-purgate-type: clean X-purgate-size: 2184 Le 10/04/2026 =C3=A0 17:06, Thierry Escande a =C3=A9crit=C2=A0: > This patch adds description for the 'hotplug' PCI option, allowing > devices to be attached to the guest using the legacy QMP hotplug > mechanism or by passing them to the Qemu command line using '-device'. > > Signed-off-by: Thierry Escande > --- > v2: no change > v3: no change > --- > docs/man/xl-pci-configuration.5.pod | 17 +++++++++++++++++ > docs/man/xl.cfg.5.pod.in | 6 ++++++ > 2 files changed, 23 insertions(+) > > diff --git a/docs/man/xl-pci-configuration.5.pod b/docs/man/xl-pci-config= uration.5.pod > index 0691f06ad3..8b664173cb 100644 > --- a/docs/man/xl-pci-configuration.5.pod > +++ b/docs/man/xl-pci-configuration.5.pod > @@ -166,6 +166,23 @@ dom0 without confirmation. Please use with care. > > =3Dback > > +=3Ditem B=3DI > + > +=3Dover 4 > + > +=3Ditem Description > + > +Tells L to use QMP hotplug mechanism to attach assignable device = to > +the guest, or to pass it via Qemu command line using > +'B<-device xen-pci-passthrough,...>'. The default is to use the legacy Q= MP > +mechanism. > + > +=3Ditem Default Value > + > +1 > + > +=3Dback > + > =3Ditem B=3DI > > =3Dover 4 > diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in > index 3aac0bc4fb..181aaffa0f 100644 > --- a/docs/man/xl.cfg.5.pod.in > +++ b/docs/man/xl.cfg.5.pod.in > @@ -1230,6 +1230,12 @@ B<(HVM only)> Changes the default value of B for all PCI > devices passed through to this VM. See B > above. > > +=3Ditem B > + > +B<(HVM only)> Changes the default value of B for all PCI > +devices passed through to this VM. See L for > +more details. > + > =3Ditem B > > Enable graphics device PCI passthrough. This option makes an assigned Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:19:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:19:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281498.1564387 (Exim 4.92) (envelope-from ) id 1wCZuv-00022x-QZ; Tue, 14 Apr 2026 09:18:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281498.1564387; Tue, 14 Apr 2026 09:18:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZuv-00022q-ND; Tue, 14 Apr 2026 09:18:45 +0000 Received: by outflank-mailman (input) for mailman id 1281498; Tue, 14 Apr 2026 09:18:44 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZuu-00022k-7h for xen-devel@lists.xenproject.org; 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Tue, 14 Apr 2026 09:18:36 +0000 (UTC) Received: from redhat.com (headnet01.pony-001.prod.iad2.dc.redhat.com [10.2.32.101]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 603AD195608E; Tue, 14 Apr 2026 09:18:34 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mimecast20190719 header.d=redhat.com header.i="@redhat.com" header.h="From:Reply-To:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1776158321; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OmtXZQeMRh+rctyuoTSEkZL1cxFBhrRFLX3Pl/Sx4gY=; b=iIJKCCw3AccmdxsXljI/a/zzQY6TYsW2MW0mp06h1WARreOc5wQusndsvyWqBL6Oo8cgwT j6xdyJC4h7dvWz66lRjS15asLExcRPalR+axXf+ezndFs2w9WVDL85G3BStP/y78NKg9nv b6VLxhxeiScgPoRVtKYgmzEeQ1eDziY= X-MC-Unique: rTsOmLJ1OXS-Dp8JHnGxGg-1 X-Mimecast-MFC-AGG-ID: rTsOmLJ1OXS-Dp8JHnGxGg_1776158316 Date: Tue, 14 Apr 2026 10:18:30 +0100 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Teddy Astie Cc: Thierry Escande , xen-devel@lists.xenproject.org, Anthony PERARD , Juergen Gross , Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= Subject: Re: [RFC PATCH v3 2/3] libxl: Allow PCI device passthrough using -device Qemu command line Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20260410150333.1533568-1-thierry.escande@vates.tech> <20260410150333.1533568-3-thierry.escande@vates.tech> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/2.2.14 (2025-02-20) X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: xv42_pn1bDFyYsTJpSaxrf8hxdO54BckhQ3lEAUkun8_1776158316 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776158322-B78FC185-67B3D50F/0/0 X-purgate-type: clean X-purgate-size: 1688 On Tue, Apr 14, 2026 at 08:59:52AM +0000, Teddy Astie wrote: > Le 10/04/2026 à 17:06, Thierry Escande a écrit : > > This change makes use of the new option 'hotplug' for host PCI devices > > passthrough'd to the guest. If hotplug=0 is used in the pci device > > configuration table, the device will be attached to the guest using the > > Qemu command line as '-device xen-pci-passthrough,hostaddr=...' > > > > The host device configuration is passed to the -device option as a json > > array, just like it's done for hotplug using QMP. The json array is > > created by a new internal function libxl__device_pci_get_qmp_json() that > > is also used by pci_add_qmp_device_add(). > > If (in this specific case) we're not using QMP anymore, I think > libxl__device_pci_get_qmp_json should lose the "qmp" qualification. > (unless QEMU also considers JSON-formatted command-line paramters as QMP) FWIW, from the QEMU POV, 'QMP' refers to the monitor protocol, whose specification is defined using the 'QAPI' schema language. QEMU is increasing enabling use of JSON on the command line, by having the CLI args parsed using 'QAPI' visitors. In these cases, the 'QAPI' data structures are shared between the command line and QMP in most cases. IOW, in this case, perhaps "qapi_json" is a more accurate name than 'qmp_json' if libxl is returning a JSON doc that represents an object defined using QAPI. With regards, Daniel -- |: https://berrange.com ~~ https://hachyderm.io/@berrange :| |: https://libvirt.org ~~ https://entangle-photo.org :| |: https://pixelfed.art/berrange ~~ https://fstop138.berrange.com :| From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:23:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:23:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281510.1564395 (Exim 4.92) (envelope-from ) id 1wCZz6-0003bs-DQ; Tue, 14 Apr 2026 09:23:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281510.1564395; Tue, 14 Apr 2026 09:23:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZz6-0003bl-AU; Tue, 14 Apr 2026 09:23:04 +0000 Received: by outflank-mailman (input) for mailman id 1281510; Tue, 14 Apr 2026 09:23:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCZz4-0003bf-KI for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 09:23:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCZz4-008mOs-05 for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:23:02 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de076e-e002-0a2a0a5209dd-0a2a450b9aba-44 for ; Tue, 14 Apr 2026 11:23:01 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de0775-bca8-0a2a450b0019-d1558032d943-3 for ; Tue, 14 Apr 2026 11:23:01 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso50445035e9.3 for ; Tue, 14 Apr 2026 02:23:01 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Access to the guest file identifier is protected by a lock. >> >> Initialize this structure during vCPU setup and store it in arch_vcpu. >> The initial state marks the VS-file as software-backed until it becomes >> associated with a physical CPU. >> >> Add helpers to retrieve and update the guest interrupt file identifier. > > Yet again a functions with no callers. They will be called in follow-up patches. > >> --- a/xen/arch/riscv/imsic.c >> +++ b/xen/arch/riscv/imsic.c >> @@ -59,6 +59,29 @@ do { \ >> csr_clear(CSR_SIREG, v); \ >> } while (0) >> >> +unsigned int vcpu_guest_file_id(const struct vcpu *v) >> +{ >> + struct imsic_state *imsic_state = v->arch.imsic_state; >> + unsigned long flags; >> + unsigned int vsfile_id; >> + >> + read_lock_irqsave(&imsic_state->vsfile_lock, flags); >> + vsfile_id = imsic_state->guest_file_id; >> + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); > > What purpose does this locking have? Already ... > >> + return vsfile_id; > > ... here the value can be stale, if indeed there is a chance of races. > Did you perhaps mean to use ACCESS_ONCE() here and where the value is > set? ACCESS_ONCE() isn't guarantee only compiler re-ordering (as basically it is just volatile-related stuff inisde the macros)? Generally, I think that that guest_file_id is needed to be updated only during migration of vCPU from one pCPU to another and I expect that during this migration vCPU isn't active, so no one will want to read imsic_state->guest_file_id. But on the other hand, there is: bool imsic_has_interrupt(const struct vcpu *vcpu) { ... /* * The IMSIC SW-file directly injects interrupt via hvip so * only check for interrupt when IMSIC VS-file is being used. */ read_lock_irqsave(&imsic_state->vsfile_lock, flags); if ( imsic_state->vsfile_pcpu != NR_CPUS ) ret = !!(csr_read(CSR_HGEIP) & BIT(imsic_state->guest_file_id, UL)); read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); ... } which I think could be called in parallel with with migration, so then still lock are needed. > >> @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_node *node, >> return 0; >> } >> >> +int __init vcpu_imsic_init(struct vcpu *v) > > __init for a function involved in setting up a vCPU? Yes, it will be used during creationg of a vCPU. > >> +{ >> + struct imsic_state *imsic_state; >> + >> + /* Allocate IMSIC context */ >> + imsic_state = xvzalloc(struct imsic_state); >> + if ( !imsic_state ) >> + return -ENOMEM; >> + >> + v->arch.imsic_state = imsic_state; >> + >> + /* Setup IMSIC context */ >> + rwlock_init(&imsic_state->vsfile_lock); >> + >> + imsic_state->guest_file_id = imsic_state->vsfile_pcpu = NR_CPUS; > > Iirc Misra dislikes such double assignments, so better avoid them right away. > (As per a comment at the bottom this may need splitting anyway.) > >> --- a/xen/arch/riscv/include/asm/domain.h >> +++ b/xen/arch/riscv/include/asm/domain.h >> @@ -52,6 +52,8 @@ struct arch_vcpu { >> >> struct vtimer vtimer; >> >> + struct imsic_state *imsic_state; > > Just like it's "vtimer", perhaps also "vimsic_state" for both the field > and the struct tag? Makes sense. Lets rename this field and tag. > >> @@ -64,8 +65,20 @@ struct imsic_config { >> spinlock_t lock; >> }; >> >> +struct imsic_state { >> + /* IMSIC VS-file */ >> + rwlock_t vsfile_lock; >> + unsigned int guest_file_id; >> + /* >> + * (vsfile_pcpu >= 0) => h/w IMSIC VS-file >> + * (vsfile_pcpu == NR_CPUS) => s/w IMSIC SW-file >> + */ >> + unsigned long vsfile_pcpu; > > And why unsigned long, when unsigned int will do (as about everywhere else > for CPU numbers)? That'll also shrink the structure size by 8 bytes. Originally, IIRC mhartid register is unsigned long, so potentially we could have amount of pCPU up to what fit into unsigned long. But know I see that AIA limits amount of pCPUs to 16,384 harts. So we could really use unsigned int here. > > As to the comment - as per vcpu_imsic_init() NR_CPUS also has some special > meaning for guest_file_id, yet there's no comment there. How do file ID and > NR_CPUS fit together anyway? Agree, it looks incorrect. I tried to avoid introduction of "#define GIELEN_MAX 64". As an option I can use UINT_MAX as init value for guest_file_id or even better just use 0 as it basically means that SW-file should be used. The idea is that if s/w IMSIC SW-file is used that it doesn't sit on any pCPU, so we should have some marker to show that and NR_CPUS should be fine. As a result guest_file_id should be init-ed with 0 (and it will be by default as xvzalloc() is used for allocation) and ->vsfile_pcpu inits with NR_CPUS. Also, I will add a comment above guest_file_id. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:23:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:23:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281513.1564405 (Exim 4.92) (envelope-from ) id 1wCZzH-0003sz-L2; Tue, 14 Apr 2026 09:23:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281513.1564405; Tue, 14 Apr 2026 09:23:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCZzH-0003ss-H8; Tue, 14 Apr 2026 09:23:15 +0000 Received: by outflank-mailman (input) for mailman id 1281513; Tue, 14 Apr 2026 09:23:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCZzF-0003rq-GW for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 09:23:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCZzE-00ASKL-So for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:23:12 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de0779-2eae-0a2a0a5409dd-0a2a45098dec-38 for ; Tue, 14 Apr 2026 11:23:12 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de077f-bf79-0a2a45090019-a0658309af00-3 for ; Tue, 14 Apr 2026 11:23:12 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id E59EF81A1E35; Tue, 14 Apr 2026 05:22:17 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [PATCH v2] docs: Draft Design Document for NUMA-aware claim sets Date: Tue, 14 Apr 2026 10:21:13 +0100 Message-Id: <9e65c4d4f82ea7a41e9284d58c513dc00e96e7f9.1776158129.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1776158592-5CDF72F2-E07FAA1A/3/8697954094 X-purgate-type: clean.bounce X-purgate-size: 97947 This design extends Xen's memory claim handling to support claim sets spanning multiple NUMA nodes. Roger Pau Monné described it as: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. -- Roger Pau Monné This design implements that model and integrates itself into the Sphinx documentation for the Xen hypervisor below docs/designs. Suggested-by: Jan Beulich Suggested-by: Roger Pau Monné Signed-off-by: Bernhard Kaindl --- Dear reviewers, for convenience, the rendered design document is available here for review: https://bernhard-xen.readthedocs.io/en/claim-sets-v2-design/designs/claims/ The Sphinx site can be built and viewed locally with the following commands: git pull git@gitlab.com:bernhardkaindl/xen.git claim-sets-v2-design make -C docs sphinx-env-build # xdg-open docs/sphinx/html/index.html or start a minimal HTTP server: (cd docs/sphinx/html; python -m http.server) Changes since v1: ----------------- - After consultations, I improved the function names to follow standard naming recommendations and improved the used metaphors. I considered many suggestions, and decided to rename the new functions as follows: * claims_retire_allocation() -> redeem_claims_for_allocation() - Use redeem because it is part of an exchange of claims for memory. * claims_retire_global() -> deduct_global_claims() * claims_retire_nodes() -> deduct_node_claims() - These perform the act of reducung the amount of global/node claims. * claims_retire_node() -> cancel_all_node_claims() - Cancel all node claims when needed when the claims are terminated. - Associated words in the text changed from retire to redeem and deduct. Best regards, Bernhard --- .readthedocs.yaml | 4 +- docs/.gitignore | 1 + docs/Makefile | 12 +- docs/conf.py | 51 +- docs/designs/claims/accounting.rst | 273 ++++++++++ docs/designs/claims/design.rst | 345 ++++++++++++ docs/designs/claims/edge-cases.rst | 24 + docs/designs/claims/history.rst | 82 +++ docs/designs/claims/implementation.rst | 492 ++++++++++++++++++ docs/designs/claims/index.rst | 43 ++ docs/designs/claims/installation.rst | 122 +++++ docs/designs/claims/invariants.mmd | 36 ++ docs/designs/claims/protection.rst | 41 ++ docs/designs/claims/redeeming.rst | 70 +++ docs/designs/claims/usecases.rst | 39 ++ docs/designs/index.rst | 16 + docs/designs/launch/hyperlaunch.rst | 4 +- .../dom/DOMCTL_claim_memory-data.mmd | 43 ++ .../dom/DOMCTL_claim_memory-seqdia.mmd | 23 + .../dom/DOMCTL_claim_memory-workflow.mmd | 23 + docs/guest-guide/dom/DOMCTL_claim_memory.rst | 81 +++ docs/guest-guide/dom/index.rst | 14 + docs/guest-guide/index.rst | 23 + docs/guest-guide/mem/XENMEM_claim_pages.rst | 100 ++++ docs/guest-guide/mem/index.rst | 12 + docs/hypervisor-guide/index.rst | 7 + docs/index.rst | 7 +- 27 files changed, 1978 insertions(+), 10 deletions(-) create mode 100644 docs/designs/claims/accounting.rst create mode 100644 docs/designs/claims/design.rst create mode 100644 docs/designs/claims/edge-cases.rst create mode 100644 docs/designs/claims/history.rst create mode 100644 docs/designs/claims/implementation.rst create mode 100644 docs/designs/claims/index.rst create mode 100644 docs/designs/claims/installation.rst create mode 100644 docs/designs/claims/invariants.mmd create mode 100644 docs/designs/claims/protection.rst create mode 100644 docs/designs/claims/redeeming.rst create mode 100644 docs/designs/claims/usecases.rst create mode 100644 docs/designs/index.rst create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd create mode 100644 docs/guest-guide/dom/DOMCTL_claim_memory.rst create mode 100644 docs/guest-guide/dom/index.rst create mode 100644 docs/guest-guide/mem/XENMEM_claim_pages.rst create mode 100644 docs/guest-guide/mem/index.rst diff --git a/.readthedocs.yaml b/.readthedocs.yaml index d3aff7662ebf..f6dbb4ffa86f 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -12,7 +12,9 @@ build: jobs: post_install: # Instead of needing a separate requirements.txt - - python -m pip install --upgrade --no-cache-dir sphinx-rtd-theme + - > + python -m pip install --upgrade --no-cache-dir sphinx-rtd-theme + sphinxcontrib-mermaid sphinx: configuration: docs/conf.py diff --git a/docs/.gitignore b/docs/.gitignore index c3ce50335ae6..80c3d14ede69 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,3 +1,4 @@ +/.sphinx/ /figs/*.png /html/ /man/xl.cfg.5.pod diff --git a/docs/Makefile b/docs/Makefile index 8e68300e3b44..47e9f366ce7a 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -55,6 +55,16 @@ build: html txt pdf man-pages figs sphinx-html: sphinx-build -b html . sphinx/html +# Sphinx build target that sets up a virtual environment and installs +# dependencies. This is intended for use by developers who want to build +# the Sphinx documentation locally. Keep it the dependencies in sync with +# .readthedocs.yaml. +sphinx-env-build: + if [ ! -d .sphinx ]; then python -m venv .sphinx; fi + . .sphinx/bin/activate && \ + pip install sphinx-rtd-theme sphinxcontrib-mermaid && \ + $(MAKE) sphinx-html + .PHONY: html html: $(DOC_HTML) html/index.html @@ -76,7 +86,7 @@ pdf: $(DOC_PDF) clean: clean-man-pages $(MAKE) -C figs clean rm -rf .word_count *.aux *.dvi *.bbl *.blg *.glo *.idx *~ - rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core + rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core .sphinx rm -rf html txt pdf sphinx/html .PHONY: distclean diff --git a/docs/conf.py b/docs/conf.py index 2fb8bafe6589..97d79a0eb562 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -61,7 +61,48 @@ needs_sphinx = '1.4' # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = [] +extensions = ["sphinx.ext.autosectionlabel"] + +try: + import sphinxcontrib.mermaid + extensions.append("sphinxcontrib.mermaid") +except ImportError: + pass + +def on_build_finished(app, exception): + if exception: + return + try: + import sphinxcontrib.mermaid + except ImportError: + sys.stderr.write(""" + To fix rendering mermaid diagrams, install `sphinxcontrib.mermaid` in + your Python venv. On Debian-based systems, you can install it with:\n + sudo apt install python3-sphinxcontrib-mermaid\n + Alternatively, you can use pipx to install sphinx and the needed + extras in an isolated environment with:\n + pipx install sphinx + pipx inject sphinx sphinxcontrib-mermaid sphinx-rtd-theme\n + Or, use `make -C docs sphinx-env-build` to build the documentation + in a suitable Python environment with all dependencies.\n""") + print("The generated documentation is available at:") + print(f"file://{app.outdir}/index.html") + print("You can also serve it locally with:") + print(f" (cd {app.outdir}; python -m http.server)") + +def setup(app): + app.connect("build-finished", on_build_finished) + + +# Extension options + +# sphinxcontrib.mermaid +mermaid_init_js = """ +mermaid.initialize({ startOnLoad: true }); +""" + +# sphinx.ext.autosectionlabel +autosectionlabel_prefix_document = True # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] @@ -82,7 +123,7 @@ language = 'en' # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. -exclude_patterns = [u'sphinx/output', 'Thumbs.db', '.DS_Store'] +exclude_patterns = [u'sphinx/output', 'Thumbs.db', '.DS_Store', '.sphinx'] # The name of the Pygments (syntax highlighting) style to use. pygments_style = None @@ -99,7 +140,11 @@ highlight_language = 'none' try: import sphinx_rtd_theme html_theme = 'sphinx_rtd_theme' - html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] + # The sphinx_rtd_theme package versions prior to 3.0.0 require the theme + # path to be added to html_theme_path, while newer are warning about it: + # https://sphinx-rtd-theme.readthedocs.io/en/stable/changelog.html#deprecations + if sphinx_rtd_theme.__version__.split('.') < ['3', '0', '0']: + html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] except ImportError: sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n') diff --git a/docs/designs/claims/accounting.rst b/docs/designs/claims/accounting.rst new file mode 100644 index 000000000000..d8efe0cdf24f --- /dev/null +++ b/docs/designs/claims/accounting.rst @@ -0,0 +1,273 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Claims Accounting +----------------- + +.. contents:: Table of Contents + :local: + +.. note:: + Claims accounting state is only updated while holding :c:expr:`heap_lock`. + See :ref:`designs/claims/accounting:Locking of claims accounting` + for details on the locks used to protect claims accounting state. + +This section formalizes the internal state and invariants that Xen must +maintain to ensure correctness. + +For readers following the design in order, the preceding sections are: + +1. :doc:`/designs/claims/design` introduces the overall model and goals. +2. :doc:`/designs/claims/installation` explains how claim sets are installed. +3. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +4. :doc:`/designs/claims/redeeming` explains how claims are redeemed as + allocations succeed. + +Overview +^^^^^^^^ + +.. table:: Table 1: Claims accounting - All accesses, Aggregate state, + and invariants protected by :c:expr:`heap_lock`. + :widths: auto + + ============ ======================================= ======================= + Level Claims must be lower or equal to Available memory + ============ ======================================= ======================= + Node :c:expr:`node_outstanding_claims[node]` :c:expr:`node_avail_pages[node]` + Aggregate state: + + Over all domains: + + SUM(:c:expr:`domain.claims[node]`) + Global :c:expr:`outstanding_claims` = :c:expr:`total_avail_pages` = + Aggregate state: Aggregate state: + + SUM() over all domains: SUM() over all nodes: + + :c:expr:`domain.global_claims` + :c:expr:`node_avail_pages[]` + :c:expr:`domain.node_claims` + + Also, the sum over all nodes: + + :c:expr:`node_outstanding_claims[*]` + Dom global :c:expr:`domain.global_claims` :c:expr:`total_avail_pages` + Dom per-node :c:expr:`domain.claims[node]` :c:expr:`node_avail_pages[node]` + Dom slow tot :c:expr:`domain.global_claims` + :c:expr:`total_avail_pages` + SUM(:c:expr:`domain.claims[node]`) + Aggregate: :c:expr:`domain.node_claims` = + SUM(:c:expr:`domain.claims[node]`) + Domain total :c:expr:`domain.global_claims` :c:expr:`total_avail_pages` + + :c:expr:`domain.node_claims` + Domain mem :c:expr:`domain_tot_pages(domain)` Invariant: must be + - plus :c:expr:`domain.global_claims` lower or equal to + + + plus :c:expr:`domain.node_claims` :c:expr:`domain.max_pages` + ============ ======================================= ======================= + +Claims accounting state +^^^^^^^^^^^^^^^^^^^^^^^ + +When installing claims and redeeming them for allocation, the page allocator +redeems the allocation's claims by deducing the claimed pages from per-node +claims and if not sufficient to cover the allocation, from global claims +as a fallback. See :doc:`redeeming` for details on redeeming claims during +allocation. + +:c:expr:`domain.claims[MAX_NUMNODES]` + The domain's claims for specific NUMA nodes, indexed by node ID. + +:c:expr:`domain.global_claims` + The domain's global claim. + +Aggregate state +^^^^^^^^^^^^^^^ + +Xen also maintains aggregate state for fast checks in allocator hot paths: + +:c:expr:`outstanding_claims`: + The sum of all claims across all domains for global and node claims. + +:c:expr:`node_outstanding_claims[MAX_NUMNODES]`: + The sum of all claims across all domains for specific NUMA nodes, indexed + by node ID, used for efficient checks in the allocator hot paths to ensure + that node claims do not exceed the available memory on the respective node. + +:c:expr:`domain.node_claims`: + The total of the domain's node claims, + equal to the sum of :c:expr:`domain.claims[MAX_NUMNODES]` for all nodes + and used for efficient checks in the allocator. + +:c:expr:`domain_tot_pages(domain)` + The total pages allocated to the domain, used for validating that claims do + not exceed the domain's maximum page limits. This is the sum of the + domain's global claim and node claims, i.e. :c:expr:`domain.global_claims` + + :c:expr:`domain.node_claims`. + +Claims accounting invariants +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Xen must maintain the following invariants: + +- Global claims: + :c:expr:`outstanding_claims` :math:`\le` :c:expr:`total_avail_pages` + +- Node claims: + :c:expr:`node_outstanding_claims[alloc_node]` :math:`\le` + :c:expr:`node_avail_pages[alloc_node]` +- Domain claims: + :c:expr:`domain.global_claims` + :c:expr:`domain.node_claims` + + :c:expr:`domain_tot_pages(domain)` :math:`\le` :c:expr:`domain.max_pages` + + See :doc:`redeeming` for details on the latter invariant. + +Locking of claims accounting +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. c:alias:: domain.page_alloc_lock + +.. c:var:: spinlock_t heap_lock + + Lock for all heap operations including claims. It protects the claims state + and invariants from concurrent updates and ensures that checks in the + allocator hot paths see a consistent view of the claims state. + + If :c:expr:`domain.page_alloc_lock` is needed to check + :c:expr:`domain_tot_pages(domain)` on top of new claims against + :c:expr:`domain.max_pages` for the domain, it needs to be taken + before :c:expr:`heap_lock` for consistent locking order to avoid deadlocks. + +Variables and data structures +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. c:type:: uint8_t nodeid_t + + Type for :term:`NUMA node` IDs. The :c:expr:`memflags` variable of + :c:expr:`xc_populate_physmap()` and related functions for populating + the :term:`physmap` allocates 8 bits in the flags for the node ID, which + limits the theoretical maximum value of ``CONFIG_NR_NUMA_NODES`` at 254, + which is far beyond the current maximum of 64 supported by Xen and should + be sufficient for the foreseeable future. + +.. c:macro:: MAX_NUMNODES + + The maximum number of NUMA nodes supported by Xen. Used for validating + node IDs in the :c:expr:`memory_claim_t` entries of claim sets. + When Xen is built without NUMA support, it is 1. + The default on x86_64 is 64 which is sufficient for current hardware and + allows for efficient storage of e.g. the :c:expr:`node_online_map` for + online nodes and :c:expr:`domain.node_affinity` in a single 64-bit value, + and in the :c:expr:`domain.claims[MAX_NUMNODES]` array. + + ``xen/arch/Kconfig`` limits the maximum number of NUMA nodes to 64. While + Xen can be compiled for up to 254 nodes, configuring machines to split + the installed memory into more than 64 nodes would be unusual. + For example, dual-socket servers, even when using multiple chips per CPU + package should typically be configured for 2 NUMA nodes by default. + +.. c:var:: long total_avail_pages + + Total available pages in the system, including both free and claimed pages. + This is used for validating that global claims do not exceed the total + available memory in the system. + +.. c:var:: long outstanding_claims + + The total global claims across all domains. This is maintained for + efficient checks in the allocator hot paths to ensure the global claims + invariant that total claims do not exceed the total available memory is not + violated. + +.. c:var:: long node_avail_pages[MAX_NUMNODES] + + Available pages for each NUMA node, including both free and claimed pages. + This is used for validating that node claims do not exceed the available + memory on the respective NUMA node. + +.. c:var:: long node_outstanding_claims[MAX_NUMNODES] + + The total claims across all domains for each NUMA node, indexed by node + ID. This is maintained for efficient checks in the allocator hot paths. + +.. c:macro:: domain_tot_pages(domain) + + The total pages allocated to the domain, used for validating that this + allocation and the domain's claims do not exceed :c:expr:`domain.max_pages`. + +.. c:struct:: domain + + .. c:member:: unsigned int global_claims + + The domain's global claim, representing the number of pages claimed + globally for the domain. + + .. c:member:: unsigned int node_claims + + The total of the domain's node claims, equal to the sum of + :c:expr:`claims` for all nodes. + It is maintained for efficient checks in the allocator hot paths + without needing to sum over the per-node claims each time. + + .. c:member:: unsigned int claims[MAX_NUMNODES] + + The domain's claims for each :term:`NUMA node`, indexed by node ID. + + As :c:expr:`domain` is allocated using a dedicated page for each domain, + this allows for efficient and fast storage with direct indexing without + consuming any additional memory for an additional allocation. + + The page allocated for struct :c:expr:`domain` is large enough + to accommodate this array several times, even beyond the current + :c:expr:`MAX_NUMNODES` limit of 64, so it should be sufficient even + for future expansion of the maximum number of supported NUMA nodes + if needed. The allocation has a build-time assertion for safety to + ensure that struct :c:expr:`domain` fits within the allocated page. + + The sum of these claims is stored in :c:expr:`domain.node_claims` + for efficient checks in the allocator hot paths which need to know + the total number of node claims for the :term:`domain`. + + .. c:member:: unsigned int max_pages + + The maximum number of pages the domain is allowed to claim, set at + domain creation time. + + .. c:member:: rspinlock_t page_alloc_lock + + Lock for checking :c:expr:`domain_tot_pages(domain)` on top of new claims + against :c:expr:`domain.max_pages` when installing these new claims. + This is a recursive spinlock to allow for nested calls into the allocator + while holding it, such as when redeeming claims during page allocation. + It is taken before :c:expr:`heap_lock` when installing claims to ensure a + consistent locking order and may not be taken while holding + :c:expr:`heap_lock` to avoid deadlocks. + + .. c:member:: nodemask_t node_affinity + + A :c:expr:`nodemask_t` representing the set of NUMA nodes the domain + is affine to. This is used for efficient checks in the allocator hot + paths to quickly get the set of nodes a domain is affine to for + memory allocation decisions. + +.. c:type:: nodemask_t + + A bitmap representing a set of NUMA nodes, used for status information + like :c:expr:`node_online_map` and the :c:expr:`domain.node_affinity` + and to track which nodes are online and which nodes are in a domain's + node affinity. + +.. c:var:: nodemask_t node_online_map + + A bitmap representing which NUMA nodes are currently online in the system. + This is used for validating that claims are only made for online nodes and + for efficient checks in the allocator hot paths to quickly determine which + nodes are online. Currently, Xen does not support hotplug of NUMA nodes, + so this is set at boot time based on the platform firmware configuration + and does not change at runtime. + +Claims Accounting Diagram +^^^^^^^^^^^^^^^^^^^^^^^^^ + +This diagram illustrates the claims accounting state and the invariants: + +.. mermaid:: invariants.mmd + :caption: Diagram: Claims accounting state and invariants diff --git a/docs/designs/claims/design.rst b/docs/designs/claims/design.rst new file mode 100644 index 000000000000..4e5841590d37 --- /dev/null +++ b/docs/designs/claims/design.rst @@ -0,0 +1,345 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +############# +Claims Design +############# + +.. contents:: Table of Contents + :backlinks: entry + :local: + +************ +Introduction +************ + +Xen's page allocator supports a :term:`claims` API that allows privileged +:term:`domain builders` to reserve an amount of available memory before +:term:`populating` the :term:`guest physical memory` of new :term:`domains` +they are creating, configuring and building. + +These reservations are called :term:`claims`. They ensure that the claimed +memory remains available for the :term:`domains` when allocating it, even +if other :term:`domains` are allocating memory at the same time. + +:term:`Installing claims` is a privileged operation performed by +:term:`domain builders` before they populate the :term:`guest physical memory`. +This prevents other :term:`domains` from allocating memory earmarked +for :term:`domains` under construction. Xen maintains the per-domain +claim state for pages that are claimed but not yet allocated. + +When claim installation succeeds, Xen updates the claim state to reflect +the new targets and protects the claimed memory until it is allocated or +the claim is released. As Xen allocates pages for the domain, claims are +redeemed by reducing the claim state by the size of each allocation. + +************ +Design Goals +************ + +The design's primary goals are: + +1. Allow :term:`domain builders` to claim memory + on multiple :term:`NUMA nodes` using a :term:`claim set` atomically. + +2. Preserve the existing :c:expr:`XENMEM_claim_pages` hypercall command + for compatibility with existing :term:`domain builders` and its legacy + semantics, while introducing a new, unrestricted hypercall command for + new use cases such as NUMA-aware claim sets. + +3. Global claims are supported for compatibility with existing domain builders + and for use cases where a flexible claim that can be satisfied from any node + is desirable, such as on UMA machines or as a fallback for memory that comes + available on any node. This means we cannot remove or replace the legacy + global claim call nor the needed variables maintaining the global claim + state. They are still very much needed: claims are not just for NUMA use + cases, but for :term:`parallel domain builds` in general. + + Only on UMA machines is a global claim the same as a claim on node 0, + but the same is not true for NUMA machines, where global claims can claim + more memory than any single node, and the global claim can be used as a + flexible fallback for claiming memory on any node, which can be useful + when preferred NUMA node(s) should be claimed, but may have insufficient + free memory at the time of claim installation, and the global claim can + ensure that the shortfall is available from any node. + +4. Use fast allocation-time claims protection in the allocator's hot paths + to protect claimed memory from parallel allocations from other domain + builders in case of parallel domain builds, and to protect claimed + memory from allocations from already running domains. + +*************** +Design Overview +*************** + +The legacy :ref:`XENMEM_claim_pages` hypercall is superseded by +:c:expr:`XEN_DOMCTL_claim_memory`. This hypercall installs a :term:`claim set`. +It is an array of :c:expr:`memory_claim_t` entries, where each entry specifies +a page count and a target: either a specific NUMA node ID or a special selector +(for example, a global or flexible claim). + +Like legacy claims, claim sets are validated and installed under +:c:expr:`domain.page_alloc_lock` and :c:expr:`heap_lock`: Either the entire +set is accepted, or the request fails with no side effects. Repeated calls +to install claims replace any existing claims for the domain rather than +accumulating. + +As installing claim sets after allocations is not a supported use case, +the legacy behaviour of subtracting existing allocations from installed +claims is somewhat surprising and counterintuitive, and page exchanges +make incremental per-node tracking of already-allocated pages on a per-node +basis difficult. Therefore, claim sets do not retain the legacy behaviour of +subtracting existing allocations, optionally on a per-node basis, from the +installed claims across the individual claim set entries. + +Summary: + +- Legacy domain builders can continue to use the previous (now deprecated) + :c:expr:`XENMEM_claim_pages` hypercall command to install single-node claims + with the legacy semantics and, aside from improvements or fixes to global + claims in general, observe no changes in their behaviour. +- Updated domain builders can take advantage of claim sets to install + NUMA-aware :term:`claims` on multiple :term:`NUMA nodes` and/or globally + in a single step. + +For readers following the design in order, the next sections cover the +following topics: + +1. :doc:`/designs/claims/installation` explains how claim sets are installed. +2. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +3. :doc:`/designs/claims/redeeming` explains how claims are redeemed as + allocations succeed. +4. :doc:`/designs/claims/accounting` describes the accounting model that + underpins those steps. + +******************** +Key design decisions +******************** + +.. glossary:: + + :c:expr:`node_outstanding_claims[MAX_NUMNODES]` + Tracks the sum of all claims on a node. :c:expr:`get_free_buddy()` checks + it before scanning zones on a node, so claimed memory is protected from + other allocations. + + :c:expr:`redeem_claims_for_allocation()` + When allocating memory for a domain, the page allocator redeems the + matching claims for this allocation, ensuring the domain's total memory + allocation as :c:expr:`domain_tot_pages(domain)` plus its outstanding claims + as :c:expr:`domain.global_claims + domain.node_claims` remain within the + domain's limits, defined by :c:expr:`domain.max_pages`. + See :doc:`redeeming` for details on redeeming claims. + + :c:expr:`domain.global_claims` (formerly :c:expr:`domain.outstanding_claims`) + Support for :term:`global claims` is maintained for two reasons: first, + for compatibility with existing domain builders, and second, for use cases + where a flexible claim that can be satisfied from any node is desirable. + + When the preferred NUMA node(s) for a domain do not have sufficient free + memory to satisfy the domain's memory requirements, global claims provide + a flexible fallback for the memory shortfall from the preferred node(s) that + can be satisfied from any available node. + + In this case, :term:`domain builders` can exploit a combination of passing + the preferred node to :c:expr:`xc_domain_populate_physmap()` and + :term:`NUMA node affinity` to steer allocations towards the preferred NUMA + node(s), while letting the global claim ensure that the shortfall is + available. + + This allows the domain builder to define a set of desired NUMA nodes to + allocate from and even specify which nodes to prefer for an allocation, + but the claim for the shortfall is flexible, not specific to any node. + +********* +Non-goals +********* + +Using per-node allocator data +============================= + +Some data structures could be moved into the per-node allocator data +allocated by `init_node_heap()`, to avoid bouncing those data structures +between nodes, but that would not eliminate the need to take the global +:c:expr:`heap_lock`, which is still needed to protect the allocator's +internal state during allocation and deallocation. + +The synchronisation point for taking the global :c:expr:`heap_lock` is +the main point of contention during allocation, freeing and scrubbing +pages. The overhead of accessing the per-node claims accounting data +is expected to be minimal. + +However, we aim move that data into the per-node allocator data in the +future to reduce the need to bounce those data structures between nodes. + +Legacy behaviours +================= + +Installing claims is a privileged operation performed by domain builders +before they populate guest memory. As such, tracking previous allocations +is not in scope for claims. + +For the following reasons, claim sets do not retain the legacy behaviour +of subtracting existing allocations from installed claims: + +- Xen does not currently maintain a ``d->node_tot_pages[node]`` count, + and the hypercall to exchange extents of memory with new memory makes + such accounting relatively complicated. + +- The legacy behaviour is somewhat surprising and counterintuitive. + Because installing claims after allocations is not a supported use case, + subtracting existing allocations at installation time is unnecessary. + +- Claim sets are a new API and can provide more intuitive semantics + without subtracting existing allocations from installed claims. This + also simplifies the implementation and makes it easier to maintain. + +Versioned hypercall +=================== + +The :term:`domain builders` using the :c:expr:`XEN_DOMCTL_claim_memory` +hypercall also need to use other version-controlled hypercalls which +are wrapped through the :term:`libxenctrl` library. + +Wrapping this call in :term:`libxenctrl` is therefore a practical approach; +otherwise, we would have a mix of version-controlled and unversioned hypercalls, +which could be confusing for API users and for future maintenance. From the +domain builders' viewpoint, it is more consistent to expose the claims +hypercall in the same way as the other calls they use. + +Stable interfaces also have drawbacks: with stable syscalls, Linux needs +to maintain the old interface indefinitely, which can be a maintenance burden +and can limit the ability to make improvements or changes to the interface +in the future. Linux carries many system call successor families, e.g., oldstat, +stat, newstat, stat64, fstatat, statx, with similar examples including openat, +openat2, clone3, dup3, waitid, mmap2, epoll_create1, pselect6 and many more. +Glibc hides that complexity from users by providing a consistent API, but it +still needs to maintain the old system calls for compatibility. + +In contrast, versioned hypercalls allow for more flexibility and evolution of +the API while still providing a clear path to adopt new features. The reserved +fields and reserved bits in the structures of this hypercall allow for many +future extensions without breaking existing callers. + +******** +Glossary +******** + +.. glossary:: + + claims + Reservations of memory for :term:`domains` that are installed by + :term:`domain builders` before :term:`populating` the domain's memory. + Claims ensure that the reserved memory remains available for the + :term:`domains` when allocating it, even if other :term:`domains` are + allocating memory at the same time. + + claim set + An array of :c:expr:`memory_claim_t` entries, each specifying a page count + and a target (either a NUMA node ID or a special value for global claims), + that can be installed atomically for a domain to reserve memory on multiple + NUMA nodes. The chapter on :ref:`designs/claims/installation:claim sets` + provides further information on the structure and semantics of claim sets. + + claim set installation + installing claim sets + installing claims + The process of validating and installing a claim set for a domain under + :c:expr:`domain.page_alloc_lock` and :c:expr:`heap_lock`, ensuring that + either the entire set is accepted and installed, or the request fails with + no side effects. + The chapter on :ref:`designs/claims/installation:claim set installation` + provides further information on the structure and semantics of claim sets. + + domain builders + Privileged entities (such as :term:`toolstacks` in management :term:`domains`) + responsible for constructing and configuring :term:`domains`, including + installing :term:`claims`, :term:`populating` memory, and setting up other + resources before the :term:`domains` are started. + + domains + Virtual machine instances managed by Xen, built by :term:`domain builders`. + + global claims + :term:`claims` that can be satisfied from any NUMA node, required for + compatibility with existing domain builders and for use cases where + strict node-local placement is not required or not possible, such as on + UMA machines or as a fallback for memory that comes available on any node. + + libxenctrl + A library used by :term:`domain builders` running in privileged + :term:`domains` to interact with the hypervisor, including making + hypercalls to install claims and populate memory. + + libxenguest + A library used by :term:`domain builders` running in privileged + :term:`domains` to interact with the hypervisor, including making + hypercalls to install claims and populate memory. + + meminit + The phase of a domain build where the guest's physical memory is populated, + which involves allocating and mapping physical memory for the domain's guest + :term:`physmap`. This should be performed after installing :term:`claims` + to protect the process against parallel allocations of other domain builder + processes in case of parallel domain builds. + + It is implemented in :term:`libxenguest` and optionally installs + :term:`claims` to ensure the claimed memory is reserved before populating + the :term:`physmap` using calls to :c:expr:`xc_domain_populate_physmap()`. + + nodemask + A bitmap representing a set of NUMA nodes, used for status information + like :c:expr:`node_online_map` and the :c:expr:`domain.node_affinity`. + + node + NUMA node + NUMA nodes + A grouping of CPUs and memory in a NUMA architecture. NUMA nodes have + varying access latencies to memory, and NUMA-aware claims allow + :term:`domain builders` to reserve memory on specific NUMA nodes + for performance reasons. Platform firmware configures what constitutes + a NUMA node, and Xen relies on that configuration for NUMA-related features. + + When this design refers to NUMA nodes, it is referring to the NUMA nodes + as defined by the platform firmware and exposed to Xen, initialized at boot + time and not changing at runtime (so far). + + The NUMA node ID is a numeric identifier for a NUMA node, used whenever code + specifies a NUMA node, such as the target of a claim or indexing into arrays + related to NUMA nodes. + + NUMA node IDs start at 0 and are less than :c:expr:`MAX_NUMNODES`. + + Some NUMA nodes may be offline, and the :c:expr:`node_online_map` is used + to track which nodes are online. Currently, Xen does not support hotplug + of NUMA nodes, so the set of online NUMA nodes is determined at boot time + based on the platform firmware configuration and does not change at runtime. + + NUMA node affinity + The preference of a :term:`domain` for a set of NUMA nodes, which can be used + by :term:`domain builders` to guide memory allocation even when not forcing + the buddy allocator to only consider (or prefer) a specific node when + allocating memory, but even a set of preferred NUMA nodes. + + By default, domains have NUMA node auto-affinity, which means their NUMA + node affinity is determined automatically by the hypervisor based on the + CPU affinity of their vCPUs, but it can be disabled and configured. + + guest physical memory + physmap + The mapping of a domain's guest physical memory to the host's + machine address space. The :term:`physmap` defines how the guest's + physical memory corresponds to the actual memory locations on the host. + + populating + The process of allocating and mapping physical memory for a domain's guest + :term:`physmap`, performed by the :term:`domain builders`, preferably after + installing :term:`claims` to protect the process against parallel allocations + of other domain builder processes in case of parallel domain builds. + + toolstacks + Privileged entities (running in privileged :term:`domains`) responsible for + managing :term:`domains`, including building, configuring, and controlling + their lifecycle using :term:`domain builders`. One toolstack may run + multiple :term:`domain builders` in parallel to build multiple :term:`domains` + at the same time. diff --git a/docs/designs/claims/edge-cases.rst b/docs/designs/claims/edge-cases.rst new file mode 100644 index 000000000000..cfb37ef24259 --- /dev/null +++ b/docs/designs/claims/edge-cases.rst @@ -0,0 +1,24 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Handling Edge Cases +------------------- + +Allocations exceeding claims +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +When an allocation exceeds the domain's claims, the allocator must check +whether unclaimed memory can satisfy the remainder of the request before +rejecting the allocation. + +Previously, if a domain's remaining claim did not fully cover a request, +the allocator rejected the allocation even when enough unclaimed memory +existed to satisfy it. + +This forced the :term:`meminit` API to fall back from ``1G`` pages to ``2M`` +and eventually to ``4K`` pages, reducing performance due to higher TLB +pressure and increased page bookkeeping. + +Supporting the use of unclaimed memory to satisfy the remainder of the +request in such cases lets builders continue to use large pages when the +combination of claims and unclaimed memory allows it, possibly improving +runtime performance in such scenarios. diff --git a/docs/designs/claims/history.rst b/docs/designs/claims/history.rst new file mode 100644 index 000000000000..e0b6cddc8d89 --- /dev/null +++ b/docs/designs/claims/history.rst @@ -0,0 +1,82 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +******************* +Development History +******************* + +.. note:: This section provides historical context on the development of + NUMA-aware claims, including previous implementations and feedback received, + to give a better understanding of the design decisions made in the current + implementation. + +The initial `implementation of single-node claims `_ (by Alejandro Vallejo) +introduced node-exact claims, allowing :term:`domain builders` to claim memory +on one :term:`NUMA node`. It passed a NUMA node in the node bits of the +:c:expr:`xen_memory_reservation.mem_flags` +field of the pre-existing claims hypercall :ref:`XENMEM_claim_pages` and, by +adding the flag ``d->claim_node`` and updating it to the passed node, defined +the target of the claim as either the specified NUMA node or global memory. + +.. sidebar:: Feedback and suggestions for multi-node claim sets + + The initial implementations of single-node claims received feedback from the + community, with multiple suggestions to extend the API to support `multi-node + claim sets `_. This feedback highlighted the need for a more flexible + and extensible design that could accommodate claims on multiple NUMA nodes. + +This design was relatively simple and allowed for a quick implementation of +single-node claims, but it had limitations in terms of flexibility and future +extensibility. + +The `v2 series added a hypercall API for multi-node claims `_, opening the +door to future multi-node claim sets and further work in that direction. + +The `v3 series refactored and improved the implementation `_, protecting +claimed memory against parallel allocations by other domain builders. + +Between v3 and v4, `Roger Pau Monné and Andrew Cooper developed and merged +several critical fixes `_ for Xen's overall claims implementation. +These fixes also allowed Roger to improve the implementation for redeeming +claims during domain memory allocation. In turn, this enabled a +fully working implementation that protected claimed memory against parallel +allocations by other domain builders. + +With the `v4 series `_, we submitted the combined work that completed the +fixes for protecting claimed memory on NUMA nodes. The review process indicated +that supporting multiple claim sets would require a `redesign `_ of +claim installation and management, which led to this design document. + +Acknowledgements +---------------- + +The claim sets design builds on the single-node claims implementation +described above and the feedback it generated. The following people +should be acknowledged for their contributions: + +- *Alejandro Vallejo* for initiating the single-node NUMA claims series. +- *Roger Pau Monné* for merging critical fixes and proposing the initial + multi-node claim-sets specification that inspired this design. +- *Andrew Cooper* for integrating and validating the work internally, + helping to stabilise and productise the single-node implementation. +- *Jan Beulich* for providing reviews that led to many improvements. +- *Bernhard Kaindl* for maintaining the single-node series, initiating + the multi-node implementation and authoring this design document. +- *Marcus Granado* and *Edwin Török* for contributing design input, + providing guidance, debugging and testing of single-node implementations. + +.. _fix1: + https://lists.xenproject.org/archives/html/xen-devel/2026-01/msg00164.html + +.. _v1: + https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/ +.. _v1m: + https://lists.xenproject.org/archives/html/xen-devel/2025-06/msg00484.html +.. _v2: + https://lists.xen.org/archives/html/xen-devel/2025-08/msg01076.html +.. _v3: + https://patchew.org/Xen/cover.1757261045.git.bernhard.kaindl@cloud.com/ +.. _v4: + https://lists.xenproject.org/archives/html/xen-devel/2026-02/msg01387.html +.. _v4-03: https://patchwork.kernel.org/project/xen-devel/ + patch/6927e45bf7c2ce56b8849c16a2024edb86034358.1772098423 + .git.bernhard.kaindl@citrix.com/ diff --git a/docs/designs/claims/implementation.rst b/docs/designs/claims/implementation.rst new file mode 100644 index 000000000000..518932599333 --- /dev/null +++ b/docs/designs/claims/implementation.rst @@ -0,0 +1,492 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +##################### +Claims Implementation +##################### + +.. contents:: Table of Contents + :backlinks: entry + :local: + +.. note:: This part describes implementation details of claims and their + interaction with memory allocation in Xen. It covers the functions and + data structures involved in :term:`installing claims`, allocating memory + with :term:`claims`, and handling related edge cases. + +Functions related to the implementation of claims and their interaction +with memory allocation. + +********************** +Installation of claims +********************** + +This section describes the functions and data structures involved +in :term:`installing claims` for domains and the internal functions for +validating and installing claim sets. + +xc_domain_claim_memory() +------------------------ + +.. c:function:: int xc_domain_claim_memory(xc_interface *xch, \ + uint32_t domid, \ + uint32_t nr_claims, \ + memory_claim_t *claims) + + :param xch: The libxenctrl interface to use for the hypercall + :param domid: The ID of the domain for which to install the claim set + :param nr_claims: The number of claims in the claim set + :param claims: The claim set to install for the domain + :type xch: xc_interface * + :type domid: uint32_t + :type nr_claims: uint32_t + :type claims: memory_claim_t * + :returns: 0 on success, or a negative error code on failure. + + Wrapper for :c:expr:`XEN_DOMCTL_claim_memory` to install + :ref:`claim sets ` for a domain. + +domain_set_outstanding_pages() +------------------------------ + +.. c:function:: int domain_set_outstanding_pages(struct domain *d, \ + unsigned long pages) + + :param d: The domain for which to set the outstanding claims + :param pages: The number of pages to claim globally for the domain + :type d: struct domain * + :type pages: unsigned long + :returns: 0 on success, or a negative error code on failure. + + Handles claim installation for :c:expr:`XENMEM_claim_pages` and + :c:expr:`XEN_DOMCTL_claim_memory` with + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` by setting the domain's + :term:`global claims` to the specified number of pages. It calculates + the claims as the requested pages minus the domain's total pages. + When :c:expr:`pages == 0`, it clears the claims of the domain. + +domain_set_node_claims() +------------------------ + +.. c:function:: int domain_set_node_claims(struct domain *d, \ + unsigned int nr_claims, \ + memory_claim_t *claims) + + :param d: The domain for which to set the node claims + :param nr_claims: The number of claims in the claim set + :param claims: The claim set to install for the domain + :type claims: memory_claim_t * + :type d: struct domain * + :type nr_claims: unsigned int + :returns: 0 on success, or a negative error code on failure. + + Handles :term:`installing claim sets`. It performs the validation + of the :term:`claim set` and updates the domain's claims accordingly. + + The function works in four phases: + + 1. Validating claim entries and checking node-local availability + 2. Validating total claims and checking global availability + 3. Resetting any current claims of the domain + 4. Installing the claim set as the domain's claiming state + + Phase 1 checks claim entries for validity and memory availability: + + 1. Target must be :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` or a node. + 2. Each target node may only appear once in the claim set. + 3. For node-local claims, requested pages must not exceed the available + memory on that node after accounting for existing claims. + 4. The explicit padding field must be zero for forward compatibility. + + Phase 2 checks: + + 1. The sum of claims must not exceed globally available memory. + 2. The claims must not exceed the :c:expr:`domain.max_pages` limit. + See :doc:`accounting` and :doc:`redeeming` for the accounting + checks that enforce the domain's :c:expr:`domain.max_pages` limit. + +************************************ +Helper functions for managing claims +************************************ + +- :c:expr:`deduct_global_claims()` to reduce global claims. +- :c:expr:`deduct_node_claims()` to reduce node-local claims. +- :c:expr:`cancel_all_node_claims()` to cancel all node claims of a domain. + +deduct_global_claims() +---------------------- + +.. c:function:: unsigned long deduct_global_claims(struct domain *d, \ + unsigned long \ + pages_to_deduct) + + :param d: The domain for which to deduct the global claims + :param pages_to_deduct: The number of pages to deduct + :type d: struct domain * + :type pages_to_deduct: unsigned long + :returns: The number of pages actually deducted from the global claim. + + This function deducts the specified number of globally claimed pages + and updates the global outstanding totals accordingly. + +deduct_node_claims() +-------------------- + +.. c:function:: unsigned long deduct_node_claims(struct domain *d, \ + nodeid_t node, \ + unsigned long pages_to_deduct) + + :param d: The domain for which to deduct the node claim + :param node: The node for which to deduct the claim + :param pages_to_deduct: The number of pages to deduct from the claim + :type d: struct domain * + :type node: nodeid_t + :type pages_to_deduct: unsigned long + :returns: The number of pages actually deducted from the claim + + This function deducts a specified number of pages from a domain's + claim on a specific node. It limits the deduction to the number of + pages actually claimed by the domain on that node and updates the + node-local claims currently held by the domain on that node, + and it updates the global and node-level claim state accordingly. + +cancel_all_node_claims() +------------------------ + +.. c:function:: void cancel_all_node_claims(struct domain *d) + + :param d: The domain for which to release all node-specific claims. + :type d: struct domain * + + This function is used by + :ref:`designs/claims/implementation:domain_set_outstanding_pages()` + to release all node-specific claims of the domain's claiming state. + +********************** +Allocation with claims +********************** + +The functions below play a key role in allocating memory for domains. + +xc_domain_populate_physmap() +---------------------------- + + .. c:function:: int xc_domain_populate_physmap(xc_interface *xch, \ + uint32_t domid, \ + unsigned long nr_extents, \ + unsigned int extent_order, \ + unsigned int mem_flags, \ + xen_pfn_t *extent_start) + + :param xch: The :term:`libxenctrl` interface + :param domid: The ID of the domain + :param nr_extents: Number of extents + :param extent_order: Order of the extents + :param mem_flags: Allocation flags + :param extent_start: Starting PFN + :type xch: xc_interface * + :type domid: uint32_t + :type nr_extents: unsigned long + :type extent_order: unsigned int + :type mem_flags: unsigned int + :type extent_start: xen_pfn_t * + :returns: 0 on success, or a negative error code on failure. + + This function is a wrapper for the ``XENMEM_populate_physmap`` hypercall, + which is handled by the :c:expr:`populate_physmap()` function in the + hypervisor. It is used by :term:`libxenguest` for populating the + :term:`guest physical memory` of a domain. :term:`domain builders` can + set the :term:`NUMA node affinity` and pass the preferred node to this + function to steer allocations towards the preferred NUMA node(s) and let + :term:`claims` ensure that the memory will be available even in cases + of :term:`parallel domain builds` where multiple domains are being built + at the same time. + + +populate_physmap() +------------------ + +The :term:`meminit` API calls :c:expr:`xc_domain_populate_physmap()` +for populating the :term:`guest physical memory`. It invokes the restartable +``XENMEM_populate_physmap`` hypercall implemented by +:c:expr:`populate_physmap()`. + +.. c:function:: void populate_physmap(struct memop_args *a) + + :param a: Provides status and hypercall restart info + :type a: struct memop_args * + + Allocates memory for building a domain and uses it for populating the + :term:`physmap`. For allocation, it uses + :c:expr:`alloc_domheap_pages()`, which forwards the request to + :c:expr:`alloc_heap_pages()`. + + During domain creation, it adds the ``MEMF_no_scrub`` flag to the request + for populating the :term:`physmap` to optimize domain startup by allowing + the use of unscrubbed pages. + + When that happens, it scrubs the pages as needed using hypercall + continuation to avoid long hypercall latency and watchdog timeouts. + + Domain builders can optimise on-demand scrubbing by running + :term:`physmap` population pinned to the domain's NUMA node, + keeping scrubbing local and avoiding cross-node traffic. + +alloc_heap_pages() +------------------ + +.. c:function:: struct page_info *alloc_heap_pages(unsigned int zone_lo, \ + unsigned int zone_hi, \ + unsigned int order, \ + unsigned int memflags, \ + struct domain *d) + + :param zone_lo: The lowest zone index to consider for allocation + :param zone_hi: The highest zone index to consider for allocation + :param order: The order of the pages to allocate (2^order pages) + :param memflags: Memory allocation flags that may affect the allocation + :param d: The domain for which to allocate memory or NULL + :type zone_lo: unsigned int + :type zone_hi: unsigned int + :type order: unsigned int + :type memflags: unsigned int + :type d: struct domain * + :returns: The allocated page_info structure, or NULL on failure + + This function allocates a contiguous block of pages from the heap. + It checks claims and available memory before attempting the + allocation. On success, it updates relevant counters and redeems + claims as necessary. + + It first checks whether the request can be satisfied given the domain's + claims and available memory using :c:expr:`claims_permit_request()`. + If claims and availability permit the request, it calls + :c:expr:`get_free_buddy()` to find a suitable block of free pages + while respecting node and zone constraints. + + If ``MEMF_no_scrub`` is allowed, it may return unscrubbed pages. When that + happens, :c:expr:`populate_physmap()` scrubs them if needed with hypercall + continuation to avoid long hypercall latency and watchdog timeouts. + + Simplified pseudo-code of its logic: +.. code:: C + + struct page_info *alloc_heap_pages(unsigned int zone_lo, + unsigned int zone_hi, + unsigned int order, + unsigned int memflags, + struct domain *d) { + /* Check whether claims and available memory permit the request. + * `avail_pages` and `claims` are placeholders for the appropriate + * global or node-local availability/counts used by the real code. */ + if (!claims_permit_request(d, avail_pages, claims, memflags, + 1UL << order, NUMA_NO_NODE)) + return NULL; + + /* Find a suitable buddy block. Pass the zone range, order and + * memflags so the helper can apply node and zone selection. */ + pg = get_free_buddy(zone_lo, zone_hi, order, memflags, d); + if (!pg) + return NULL; + + redeem_claims_for_allocation(d, 1UL << order, node_of(pg)); + update_counters_and_stats(d, order); + if (pg_has_dirty_pages(pg)) + scrub_dirty_pages(pg); + return pg; + } + +get_free_buddy() +---------------- + +.. c:function:: struct page_info *get_free_buddy(unsigned int zone_lo, \ + unsigned int zone_hi, \ + unsigned int order, \ + unsigned int memflags, \ + const struct domain *d) + + :param zone_lo: The lowest zone index to consider for allocation + :param zone_hi: The highest zone index to consider for allocation + :param order: The order of the pages to allocate (2^order pages) + :param memflags: Flags for conducting the allocation + :param d: domain to allocate memory for or NULL + :type zone_lo: unsigned int + :type zone_hi: unsigned int + :type order: unsigned int + :type memflags: unsigned int + :type d: struct domain * + :returns: The allocated page_info structure, or NULL on failure + + This function finds a suitable block of free pages in the buddy + allocator while respecting claims and node-level available memory. + + Called by :c:expr:`alloc_heap_pages()` after verifying the request is + permissible, it iterates over nodes and zones to find a buddy block + that satisfies the request. It checks node-local claims before + attempting allocation from a node. + + Using :c:expr:`claims_permit_request()`, it checks whether the node + has enough unclaimed memory to satisfy the request or whether the + domain's claims can permit the request on that node after accounting + for outstanding claims. + + If the node can satisfy the request, it searches for a suitable block + in the specified zones. If found, it returns the block; otherwise it + tries the next node until all online nodes are exhausted. + + Simplified pseudo-code of its logic: +.. code:: C + + /* + * preferred_node_or_next_node() represents the policy to first try the + * preferred/requested node then fall back to other online nodes. + */ + struct page_info *get_free_buddy(unsigned int zone_lo, + unsigned int zone_hi, + unsigned int order, + unsigned int memflags, + const struct domain *d) { + nodeid_t request_node = MEMF_get_node(memflags); + + /* + * Iterate over candidate nodes: start with preferred node (if any), + * then try other online nodes according to the normal placement policy. + */ + while (there are more nodes to try) { + nodeid_t node = preferred_node_or_next_node(request_node); + if (!node_allocatable_request(d, node_avail_pages[node], + node_outstanding_claims[node], + memflags, 1UL << order, node)) + goto try_next_node; + + /* Find a zone on this node with a suitable buddy */ + for (int zone = highest_zone; zone >= lowest_zone; zone--) + for (int j = order; j <= MAX_ORDER; j++) + if ((pg = remove_head(&heap(node, zone, j))) != NULL) + return pg; + try_next_node: + if (request_node != NUMA_NO_NODE && (memflags & MEMF_exact_node)) + return NULL; + /* Fall back to the next node and repeat. */ + } + return NULL; + } + +******************************************* +Helper functions for allocation with claims +******************************************* + +For allocating memory while respecting claims, :c:expr:`alloc_heap_pages()` +and :c:expr:`get_free_buddy()` use :c:expr:`claims_permit_request()` to +check whether the claims permit the request before attempting allocation. + +If permitted, the allocation proceeds, and after success, +:c:expr:`redeem_claims_for_allocation()` redeems the claims for the allocation +based on the domain's claiming state and the node of the allocation. + +See :ref:`designs/claims/design:Key design decisions` for the +rationale behind this design and the accounting checks that enforce +the :c:expr:`domain.max_pages` limit during allocation with claims. + +claims_permit_request() +----------------------- + +.. c:function:: bool claims_permit_request(const struct domain *d, \ + unsigned long avail_pages, \ + unsigned long claims, \ + unsigned int memflags, \ + unsigned long request, \ + nodeid_t node) + + :param d: domain for which to check + :param avail_pages: pages available globally or on node + :param claims: outstanding claims globally or on node + :param memflags: memory allocation flags for the request + :param request: pages requested for allocation + :param node: node of the request or NUMA_NO_NODE for global + :type d: const struct domain * + :type avail_pages: unsigned long + :type claims: unsigned long + :type memflags: unsigned int + :type request: unsigned long + :type node: nodeid_t + :returns: true if claims and available memory permit the request, \ + false otherwise. + + This function checks whether a memory allocation request can be + satisfied given the current state of available memory and outstanding + claims for the domain. It calculates the amount of unclaimed memory + and determines whether it is sufficient to satisfy the request. + + If unclaimed memory is insufficient, it checks if the domain's claims + can cover the shortfall, taking into account whether the request is + node-specific or global. + +redeem_claims_for_allocation() +------------------------------ + +.. c:function:: void redeem_claims_for_allocation(struct domain *d, \ + unsigned long allocation, \ + nodeid_t alloc_node) + + :param d: The domain for which to redeem claims + :param allocation: The number of pages allocated + :param alloc_node: The node on which the allocation was made + :type d: struct domain * + :type allocation: unsigned long + :type alloc_node: nodeid_t + + See :doc:`redeeming` for details on redeeming claims after allocation. + +************************************** +Offlining memory in presence of claims +************************************** + +When offlining pages, Xen must ensure that available memory on a node or +globally does not fall below outstanding claims. If it does, Xen recalls +claims from domains until accounting is valid again. + +This is triggered by privileged domains via the +``XEN_SYSCTL_page_offline_op`` sysctl or by machine-check memory errors. + +Offlining currently allocated pages does not immediately reduce available +memory: pages are marked offlining and become offline only when freed. +Pages marked offlining will not become available again, so this does not +affect claim invariants. + +However, when already free pages are offlined, free memory can drop +below outstanding claims; in that case the offlining process calls +:c:expr:`reserve_offlined_page()` to offline the page. + +It checks whether offlining the page would cause available memory on the +page's node, or globally, to fall below the respective outstanding claims: + +- When + :c:expr:`node_outstanding_claims[offline_node]` exceeds + :c:expr:`node_avail_pages[offline_node]` for the node of the offlined page, + :c:expr:`reserve_offlined_page()` calls :c:expr:`deduct_node_claims()` + to recall claims on that node from domains with claims on the node of the + offlined buddy until the claim accounting of the node is valid again. + +- When total :c:expr:`outstanding_claims` exceeds :c:expr:`total_avail_pages`, + :c:expr:`reserve_offlined_page()` calls :c:expr:`deduct_global_claims()` to + recall global claims from domains with global claims until global accounting + is valid again. + +This can violate claim guarantees, but it is necessary to maintain system +stability when memory must be offlined. + +reserve_offlined_page() +----------------------- + +.. c:function:: int reserve_offlined_page(struct page_info *head) + + :param head: The page being offlined + :type head: struct page_info * + :returns: 0 on success, or a negative error code on failure. + + This function is called during the offlining process to offline pages. + + If offlining a page causes available memory to fall below outstanding + claims, it checks the node and global claim accounting and recalls + claims from domains as necessary to ensure accounting invariants hold + after a buddy is offlined. diff --git a/docs/designs/claims/index.rst b/docs/designs/claims/index.rst new file mode 100644 index 000000000000..2c9ef414b017 --- /dev/null +++ b/docs/designs/claims/index.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +NUMA-aware Claim Sets +===================== + +Design and implementation of NUMA-aware claim sets. + +Status: Draft for review + +This design first introduces the external behaviour of claim sets: how claims +are installed, how they protect allocations, and how they are redeemed. +It then covers the underlying accounting model and implementation details. + +For readers following the design in order, the next sections cover the +following topics: + +1. :doc:`/designs/claims/usecases` describes the use cases for claim sets. +2. :doc:`/designs/claims/history` provides the development's historical context +3. :doc:`/designs/claims/design` introduces the overall model and goals. +4. :doc:`/designs/claims/installation` explains how claim sets are installed. +5. :doc:`/designs/claims/protection` describes how claimed memory is + protected during allocation. +6. :doc:`/designs/claims/redeeming` explains how claims are redeemed as + allocations succeed. +7. :doc:`/designs/claims/accounting` describes the accounting model that + underpins those steps. + +.. toctree:: :caption: Contents + :maxdepth: 2 + + usecases + history + design + installation + protection + redeeming + accounting + implementation + edge-cases + +.. contents:: + :backlinks: entry + :local: diff --git a/docs/designs/claims/installation.rst b/docs/designs/claims/installation.rst new file mode 100644 index 000000000000..29ab43589fe8 --- /dev/null +++ b/docs/designs/claims/installation.rst @@ -0,0 +1,122 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +######################## +Claim Installation Paths +######################## + +********** +Claim sets +********** + +A claim set is an array of :c:expr:`memory_claim_t` entries, each specifying +a page count and a target. Targets are either a NUMA node ID, or one of two +special values: + +.. c:macro:: XEN_DOMCTL_CLAIM_MEMORY_GLOBAL + + Value for the :c:expr:`xen_memory_claim.target` field of a claim set entry + to specify a global claim satisfied from any node, useful when strict + per-node placement is not required or as a fallback for memory that + may be populated on any node. + + These claims are redeemed on allocation only when the allocation node's + claims are exhausted, so they provide a way to claim memory when the + available memory on the allocation nodes is not fully sufficient to + satisfy the domain's needs, but the global pool has sufficient free + memory to cover the shortfall and the domain can tolerate some fallback + to non-preferred nodes without selecting a specific node for the fallback. + + Supported by :c:expr:`XEN_DOMCTL_claim_memory` but not the legacy claim path. + +.. c:macro:: XEN_DOMCTL_CLAIM_MEMORY_LEGACY + + This is a special selector for :c:expr:`xen_memory_claim.target` that can + only be used in a single-entry claim set to indicate that the claim set + should be processed by the legacy claim installation logic. It is not a + valid target for regular claims and is not supported for multi-entry + claim sets and is only used for backward compatibility and is not + intended for use in new code. + +.. note:: The legacy path is deprecated. Use :c:expr:`XEN_DOMCTL_claim_memory` + with :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` for global claims in new + code instead of :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY`. + +.. c:type:: memory_claim_t + + Typedef for :c:expr:`xen_memory_claim`, + the structure for passing claim sets to the hypervisor. + +.. c:struct:: xen_memory_claim + + Underlying structure for passing claim sets to the hypervisor. + + This structure represents an individual claim entry in a claim set. + It specifies the number of pages claimed and the target of the claim, + which can be a specific NUMA node or a special value for global claims. + + The structure includes padding for future expansion, and it is important + to zero-initialise it or use designated initializers to ensure forward + compatibility. Members are as follows: + + .. c:member:: uint64_aligned_t pages + + Number of pages for this claim entry. + + .. c:member:: uint32_t target + + The target of the claim, which can be a specific NUMA node + or a special selector to steer the claim to the global pool + or to invoke the legacy claim path. + Valid values are either a node ID in the range of valid NUMA nodes, or: + + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_GLOBAL` for a global claim, or + :c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` for the legacy claim path. + + .. c:member:: uint32_t pad + + Reserved for future use, must be 0 for forward compatibility. + +.. c:type:: uint64_aligned_t + + 64-bit unsigned integer type with alignment requirements suitable for + representing page counts in the claim structure. + +********************** +Claim set installation +********************** + +Claim set installation is invoked via :c:expr:`XEN_DOMCTL_claim_memory` and +:ref:`designs/claims/implementation:domain_set_node_claims()` implements +the claim set installation logic. + +Claim sets using +:c:expr:`XEN_DOMCTL_CLAIM_MEMORY_LEGACY` are dispatched to +:ref:`designs/claims/implementation:domain_set_outstanding_pages()` +for the legacy claim installation logic. + +See :doc:`accounting` for details on the claims accounting state. + +************************* +Legacy claim installation +************************* + +.. note:: The legacy path is deprecated. + Use :c:expr:`XEN_DOMCTL_claim_memory` for new code. + +Legacy claims are set via the :ref:`XENMEM_claim_pages` command, +implemented by +:ref:`designs/claims/implementation:domain_set_outstanding_pages()` +with the following semantics: + +- The request contains exactly one global claim entry of the form + :c:expr:`xen_memory_claim.target = XEN_DOMCTL_CLAIM_MEMORY_LEGACY`. +- It sets :c:expr:`domain.global_claims` to the requested pages, minus + the domain's total pages, i.e. the pages allocated to the domain so far, + so that the domain's global outstanding claims reflect the shortfall of + allocated pages from claimed pages: + :c:expr:`xen_memory_claim.pages - domain_tot_pages(domain)`. +- Passing :c:expr:`xen_memory_claim.pages == 0` + clears all claims installed for the domain. + +Aside from the edge cases for allocations exceeding claims and +offlining pages, the legacy path is functionally unchanged. diff --git a/docs/designs/claims/invariants.mmd b/docs/designs/claims/invariants.mmd new file mode 100644 index 000000000000..ac9bfba34d49 --- /dev/null +++ b/docs/designs/claims/invariants.mmd @@ -0,0 +1,36 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +%% Claim variables and their Invariants +flowchart TD + +subgraph "Access under the heap_lock only:" + direction TB + Memory_of_Nodes --"  Contribute to  "--> Overall_Memory + Overall_Memory --"  Available to  "--> Memory_of_Domains +end + +subgraph Memory_of_Nodes["Per-node claims and available memory"] + direction LR + per_node_claims -->|"  less or equal to  "| node_avail_pages + per_node_claims["Claims on the node: + node_outstanding_claims[n]"] + node_avail_pages["Available pages on the node: + node_avail_pages[n]"] +end + +subgraph Overall_Memory["Overall claims and available memory"] + direction LR + outstanding -->|"  less or equal to  "| avail_pages + outstanding["Total claims on the host: + outstanding_claims"] + avail_pages["Available pages on the host: + total_avail_pages"] +end + +subgraph Memory_of_Domains["Per-domain claims and available memory"] + direction LR + claims -->|"  less or equal to  "| available_memory_for_domains + claims["Claims of the domain:
    d->claims[n] + d->global_claims"] + available_memory_for_domains["Available pages:
    node_avail_pages[n] + total_avail_pages"] +end \ No newline at end of file diff --git a/docs/designs/claims/protection.rst b/docs/designs/claims/protection.rst new file mode 100644 index 000000000000..2de6097d2c74 --- /dev/null +++ b/docs/designs/claims/protection.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Protection of Claims +-------------------- + +Claimed memory must be protected from unrelated allocations while remaining +available to the claiming domain. + +The allocator performs two checks. + +Global check +^^^^^^^^^^^^ + +``alloc_heap_pages()`` first verifies whether the request fits the global +pool after accounting for claims. The request is permitted when either: + +- Enough unclaimed memory exists globally to satisfy the request. +- The requesting domain's outstanding claims cover the shortfall. + +For this check, the domain's applicable claim is +``d->global_claims + d->node_claims``. The domain therefore receives +credit for its complete claim set, whether reservations are global, +per-node, or both. + +Node check +^^^^^^^^^^ + +After passing the global check, the allocator calls ``get_free_buddy()`` +to find free pages. It loops over the NUMA nodes to find a suitable +node with enough free memory to satisfy the request. + +It performs an additional node-local claims check using the domain's claim +for that node (``d->claims[node]``) to determine whether the node is qualified +to satisfy the request before examining that node's free lists. + +Unless the caller requested an exact node, the allocator loops +over nodes until it finds one where the request can be satisfied +by the unclaimed memory and the node-local claim for that node. + +If no qualifying node is found, the allocator rejects the request +due to insufficient memory. diff --git a/docs/designs/claims/redeeming.rst b/docs/designs/claims/redeeming.rst new file mode 100644 index 000000000000..8d0fa9125aa2 --- /dev/null +++ b/docs/designs/claims/redeeming.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Redeeming Claims +---------------- + +After a successful allocation, +:ref:`designs/claims/implementation:redeem_claims_for_allocation()` +redeems claims up to the size of the allocation in the same critical +region that updates the free-page counters. + +The function performs the following steps to redeem the matching claims +for this allocation, ensuring the domain's total memory allocation as +:c:expr:`domain_tot_pages(domain)` plus its outstanding claims as +:c:expr:`domain.global_claims + domain.node_claims` remain within the +domain's limits, defined by :c:expr:`domain.max_pages`: + +Steps to redeem claims for an allocation +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Step 1: + Redeem claims from :c:expr:`domain.claims[alloc_node]` on the allocation + node, up to the size of that claim. +Step 2: + If the allocation exceeds :c:expr:`domain.claims[alloc_node]`, redeem the + remaining pages from the global fallback claim :c:expr:`domain.global_claims` + (if one exists). +Step 3: + If the allocation exceeds the combination of those claims, redeem the + remaining pages from other per-node claims so that the domain's total + allocation plus claims remain within the domain's :c:expr:`domain.max_pages` + limit. + +Enforcing the :c:expr:`domain.max_pages` limit +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +:c:expr:`domain_tot_pages(domain)` + +:c:expr:`domain.global_claims + domain.node_claims` +must not exceed the :c:expr:`domain.max_pages` limit, otherwise +the domain would exceed its memory entitlement. + +At claim installation time + This check is done by + :c:expr:`domain_set_node_claims()` and + :c:expr:`domain_set_outstanding_pages()`. + +.. :sidebar:: + See :ref:`designs/claims/accounting:Locking of claims accounting` + for the locks used to protect claims accounting state and invariants. + +At memory allocation time + If (unexpectedly) a domain builder ends up allocating memory from + different nodes than it claimed from, the domain's total allocation + plus claims could exceed the domain's :c:expr:`domain.max_pages` + limit, unless the page allocator redeems claims from other nodes + to ensure the sum of the domain's claims and populated pages + remains within the :c:expr:`domain.max_pages` limit. + + :ref:`designs/claims/implementation:redeem_claims_for_allocation()` + cannot reliably check :c:expr:`domain.max_pages` race-free because + :c:expr:`domain.max_pages` is not protected by the :c:expr:`heap_lock` + taken by the page allocator during allocation. + + To check the domain's limits, it would have to take the + :c:expr:`domain.page_alloc_lock` to inspect the domain's + limits and its current allocation. However, taking that lock + while holding the :c:expr:`heap_lock` would invert the locking + order and could lead to deadlocks. + + Therefore, :ref:`designs/claims/implementation:redeem_claims_for_allocation()` + redeems the remaining allocation from other-node claims in Step 3. diff --git a/docs/designs/claims/usecases.rst b/docs/designs/claims/usecases.rst new file mode 100644 index 000000000000..5a618f0d0280 --- /dev/null +++ b/docs/designs/claims/usecases.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +######### +Use Cases +######### + +.. glossary:: + + Parallel :term:`domain builds` + + When many domains need to be created and built, many :term:`domain builders` + compete for the same pools of memory, which can lead to inefficient NUMA + placement of :term:`guest physical memory` and thus suboptimal performance + for the domains. + + NUMA-aware claims can help solve this problem and ensure that memory + is available on the appropriate NUMA nodes. + + Domain builds + + The process of constructing and configuring :term:`domains` by + :term:`domain builders`, which includes installing :term:`claims`, + :term:`populating` memory, and setting up other resources before the + :term:`domains` are started. When multiple :term:`domain builders` can + run in parallel, this is referred to as parallel domain builds, which can + benefit from NUMA-aware claims because the domain builders are competing for + the same pools of memory on the NUMA nodes. + + Boot storms + + It is common for many domains to be booted at the same time, such as during + system startup or when large numbers of domains need to be started. + + Parallel migrations + + Similar to :term:`boot storms`, except that the domains are being migrated + instead of booted, which can happen when other hosts are being drained + for maintenance (host evacuation) or when workloads are being rebalanced + across hosts. diff --git a/docs/designs/index.rst b/docs/designs/index.rst new file mode 100644 index 000000000000..036653303231 --- /dev/null +++ b/docs/designs/index.rst @@ -0,0 +1,16 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Design documents +================ + +Design documents and implementation details for the Xen hypervisor itself. +This is intended for developers working on the Xen hypervisor, +and for those interested in the internal workings of Xen. + +.. toctree:: + :maxdepth: 2 + :numbered: 4 + + launch/hyperlaunch + launch/hyperlaunch-devicetree + claims/index diff --git a/docs/designs/launch/hyperlaunch.rst b/docs/designs/launch/hyperlaunch.rst index 3bed36f97637..aa7c2798a380 100644 --- a/docs/designs/launch/hyperlaunch.rst +++ b/docs/designs/launch/hyperlaunch.rst @@ -2,8 +2,6 @@ Hyperlaunch Design Document ########################### -.. sectnum:: :depth: 4 - This post is a Request for Comment on the included v4 of a design document that describes Hyperlaunch: a new method of launching the Xen hypervisor, relating to dom0less and work from the Hyperlaunch project. We invite discussion of this @@ -13,6 +11,8 @@ Xen Development mailing list. .. contents:: :depth: 3 + :backlinks: entry + :local: Introduction diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd new file mode 100644 index 000000000000..50687392fd20 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-data.mmd @@ -0,0 +1,43 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +classDiagram +class do_domctl["Args passed to do_domctl()"] { + +uint32_t cmd: XEN_DOMCTL_claim_memory + +uint32_t domain: Domain ID + +xen_domctl_claim_memory: Claim set +} +class xen_domctl_claim_memory["Claim set passed to do_domctl()"] { + +memory_claim_t* claims: Claim entries + +uint32_t nr_claims: Number of claim entries + +uint32_t pad: always 0 for future use +} +class memory_claim_t["Claim set: Array of claim entries"] { + +pages: Pages to claim + +node: Claim selector or node + +pad: always 0 for future use +} +class xc_domain_claim_memory["xc_domain_claim_memory()"] { + +xc_interface* xch + +uint32_t domid + +uint32_t nr_claims + +memory_claim_t* claims +} +class global_claimss["Global and Node claim counters"] { + global free = total_avail_pages - outstanding_claims + node free = node_avail_pages[node] - node_outstanding_claims[node] +} +class claim["XEN_DOMCTL_claim_memory"] { + +domain_set_outstanding_pages() + +domain_set_node_claims() +} +class domain["Claim fields in struct domain"] { + +global_claims - Global claims of the domain + +node_claims - Sum of claims on all nodes of the domain + +claims[] - Array of claims on specific nodes +} +xen_domctl_claim_memory o--> memory_claim_t +do_domctl o--> xen_domctl_claim_memory +xc_domain_claim_memory ..> do_domctl: passes
    Claim set +xc_domain_claim_memory ..> claim : calls do_domctl() +claim ..> xen_domctl_claim_memory : reads +claim ..> domain : sets +domain ..> global_claimss : updates outstanding claims diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd new file mode 100644 index 000000000000..05d688c59f13 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-seqdia.mmd @@ -0,0 +1,23 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +sequenceDiagram + +actor DomainBuilder +participant OcamlStub as OCaml stub for
    xc_domain
    claim_memory +participant Libxc as xc_domain
    claim_memory +participant Domctl as XEN_DOMCTL
    claim_memory +#participant DomainLogic as claim_memory +participant Alloc as domain
    set
    outstanding_pages + +DomainBuilder->>OcamlStub: claims +OcamlStub->>OcamlStub: marshall claims -----> OCaml to C +OcamlStub->>Libxc: claims + +Libxc->>Domctl: do_domctl + +Domctl->>Domctl: copy_from_guest(claim) +Domctl->>Domctl: validate claim +Domctl->>Alloc: set
    outstanding_pages +Alloc-->>Domctl: result +Domctl-->>Libxc: rc +Libxc-->>OcamlStub: rc +OcamlStub-->>DomainBuilder: claim_result \ No newline at end of file diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd b/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd new file mode 100644 index 000000000000..372f2bb7a616 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory-workflow.mmd @@ -0,0 +1,23 @@ +%% SPDX-License-Identifier: CC-BY-4.0 +sequenceDiagram + +participant Toolstack +participant Xen +participant NUMA Node memory + +Toolstack->>Xen: XEN_DOMCTL_createdomain +Toolstack->>Xen: XEN_DOMCTL_max_mem(max_pages) + +Toolstack->>Xen: XEN_DOMCTL_claim_memory(pages, node) +Xen->>NUMA Node memory: Claim pages on node +Xen-->>Toolstack: Claim granted + +Toolstack->>Xen: XEN_DOMCTL_set_nodeaffinity(node) + +loop Populate domain memory + Toolstack->>Xen: XENMEM_populate_physmap(memflags:node) + Xen->>NUMA Node memory: alloc from claimed node +end + +Toolstack->>Xen: XEN_DOMCTL_claim_memory(0, NO_NODE) +Xen-->>Toolstack: Remaining claims released diff --git a/docs/guest-guide/dom/DOMCTL_claim_memory.rst b/docs/guest-guide/dom/DOMCTL_claim_memory.rst new file mode 100644 index 000000000000..d435799c57a6 --- /dev/null +++ b/docs/guest-guide/dom/DOMCTL_claim_memory.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +.. c:macro:: XEN_DOMCTL_claim_memory + + Hypercall command for installing claim sets for a domain. + + This hypercall command allows :term:`domain builders` to install a + :term:`claim set` targeting :term:`NUMA nodes` and :term:`global claims`. + + The hypervisor tracks the installed claims for each domain and enforces + them during memory allocation, so that claimed memory is protected from + other allocations and the domain's memory requirements can be met even + when other parallel domain builders are also allocating memory for other + domains in parallel. + + :ref:`designs/claims/installation:Claim set installation` describes + how the Xen hypervisor processes the claim sets installed via this + hypercall command. + +API example using libxenctrl +---------------------------- + +The example below shows how a domain builder can install a claim set and +later replace or clear it. :c:expr:`memory_claim_t` contains padding for future +expansion; zero-initialise the structure or use designated initializers to +ensure forward compatibility. + +.. code-block:: C + + #include + + void example_claims(xc_interface *xch, uint32_t domid) + { + /* Claim 1024 pages on node 0, 1024 pages on node 1, and 1024 global */ + memory_claim_t claims[] = { + {.pages = 1024, .node = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + {.pages = 1024, .node = 0}, + {.pages = 1024, .node = 1} + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(claims), claims); + + /* Replace the claim set with claims on nodes 1, 2, and 3 */ + memory_claim_t claims2[] = { + {.pages = 1024, .node = 1}, + {.pages = 1024, .node = 2}, + {.pages = 1024, .node = 3}, + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(claims2), claims2); + + /* Release any remaining claim once the domain is built */ + memory_claim_t clear[] = { + {.pages = 0, .node = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL} + }; + xc_domain_claim_memory(xch, domid, ARRAY_SIZE(clear), clear); + } + +Call sequence diagram +--------------------- + +The following sequence diagram illustrates the call flow for claiming memory +for a domain using this hypercall command from an OCaml domain builder: + +.. mermaid:: DOMCTL_claim_memory-seqdia.mmd + :caption: Sequence diagram: Call flow for claiming memory for a domain + +Claim workflow +-------------- + +This diagram illustrates a workflow for claiming and populating memory: + +.. mermaid:: DOMCTL_claim_memory-workflow.mmd + :caption: Workflow diagram: Claiming and populating memory for a domain + +Used functions & data structures +-------------------------------- + +This diagram illustrates the key functions and data structures involved in +installing claims via the :c:expr:`XEN_DOMCTL_claim_memory` hypercall command: + +.. mermaid:: DOMCTL_claim_memory-data.mmd + :caption: Diagram: Function and data relationships for installing claims diff --git a/docs/guest-guide/dom/index.rst b/docs/guest-guide/dom/index.rst new file mode 100644 index 000000000000..445ccf599047 --- /dev/null +++ b/docs/guest-guide/dom/index.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Domctl Hypercall +================ + +Through domctl hypercalls, toolstacks in privileged domains can perform +operations related to domain management. This includes operations such as +creating, destroying, and modifying domains, as well as querying domain +information. + +.. toctree:: + :maxdepth: 2 + + DOMCTL_claim_memory diff --git a/docs/guest-guide/index.rst b/docs/guest-guide/index.rst index 5455c67479cf..d9611cd7504d 100644 --- a/docs/guest-guide/index.rst +++ b/docs/guest-guide/index.rst @@ -3,6 +3,29 @@ Guest documentation =================== +Xen exposes a set of hypercalls that allow domains and toolstacks in +privileged contexts (such as Dom0) to request services from the hypervisor. + +Through these hypercalls, privileged domains can perform privileged operations +such as querying system information, memory and domain management, +and enabling inter-domain communication via shared memory and event channels. + +These hypercalls are documented in the following sections, grouped by their +functionality. Each section provides an overview of the hypercalls, their +parameters, and examples of how to use them. + +Hypercall API documentation +--------------------------- + +.. toctree:: + :maxdepth: 2 + + dom/index + mem/index + +Hypercall ABI documentation +--------------------------- + .. toctree:: :maxdepth: 2 diff --git a/docs/guest-guide/mem/XENMEM_claim_pages.rst b/docs/guest-guide/mem/XENMEM_claim_pages.rst new file mode 100644 index 000000000000..1e8a50afc856 --- /dev/null +++ b/docs/guest-guide/mem/XENMEM_claim_pages.rst @@ -0,0 +1,100 @@ +.. SPDX-License-Identifier: CC-BY-4.0 +.. _XENMEM_claim_pages: + +XENMEM_claim_pages +================== + +.. note:: This API is deprecated; + Use :c:expr:`XEN_DOMCTL_claim_memory` for new code. + +.. c:macro:: XENMEM_claim_pages + + Hypercall command for installing legacy claims. + + :ref:`designs/claims/installation:Legacy claim installation` describes + the API for installing legacy claims via this hypercall command. + + It passes a single claim entry to the hypervisor via a + :c:expr:`xen_memory_reservation` structure with the page count in the + :c:expr:`xen_memory_reservation.nr_extents` field and the domain ID + :c:expr:`xen_memory_reservation.domid` field. The claim entry's target is + implicitly global, and the legacy claim path is invoked in the hypervisor + to process the claim: + +.. c:struct:: xen_memory_reservation + + Structure for passing claim requests to the hypervisor via + :ref:`XENMEM_claim_pages` and other memory reservation hypercalls. + + .. code-block:: C + + struct xen_memory_reservation { + xen_pfn_t *extent_start; /* not used for XENMEM_claim_pages */ + xen_ulong_t nr_extents; /* pass page counts to claim */ + unsigned int extent_order; /* must be 0 */ + unsigned int mem_flags; /* XENMEMF flags. */ + domid_t domid; /* domain to apply the claim to */ + }; + typedef struct xen_memory_reservation xen_memory_reservation_t; + + .. c:member:: xen_ulong_t nr_extents + + For :ref:`XENMEM_claim_pages`, the page count to claim. + + .. c:member:: domid_t domid + + Domain ID for the claim. + + .. c:member:: unsigned int mem_flags + + Must be 0 for :ref:`XENMEM_claim_pages`; not used for claims. + + In principle, it supports all the :c:expr:`XENMEMF_*` flags, including + the possibility of passing a single NUMA node ID, but using it to pass + a NUMA node ID is not currently supported by the legacy claim path. + + During review of the NUMA extension of the legacy claim path, it + was used, but the request was made to instead create a new hypercall + which is now :c:expr:`XEN_DOMCTL_claim_memory` with support for claim sets. + + .. c:member:: unsigned int extent_order + .. c:member:: xen_pfn_t *extent_start + + Both are not used for :ref:`XENMEM_claim_pages`, but are used for other + memory reservation hypercalls. + + See :ref:`designs/claims/installation:Legacy claim installation` for details. + +API example using libxenctrl +---------------------------- + +The example below claims pages, populates the domain, +and then clears the claim. + +.. code-block:: C + + #include + + int build_with_claims(xc_interface *xch, uint32_t domid, + unsigned long nr_pages) + { + int ret; + + /* Claim pages for the domain build. */ + ret = xc_domain_claim_pages(xch, domid, nr_pages); + if ( ret < 0 ) + return ret; + + /* Populate the domain's physmap. */ + ret = xc_domain_populate_physmap(xch, domid, /* ... */); + if ( ret < 0 ) + return ret; + + /* Release any remaining claim after populating the domain memory. */ + ret = xc_domain_claim_pages(xch, domid, 0); + if ( ret < 0 ) + return ret; + + /* Unpause the domain to allow it to run. */ + return xc_unpause_domain(xch, domid); + } diff --git a/docs/guest-guide/mem/index.rst b/docs/guest-guide/mem/index.rst new file mode 100644 index 000000000000..086281f082a0 --- /dev/null +++ b/docs/guest-guide/mem/index.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Memctl Hypercall +================ + +The XENMEM hypercall interface allows guests to perform various control +operations related to memory management. + +.. toctree:: + :maxdepth: 2 + + XENMEM_claim_pages diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.rst index 520fe01554ab..904f8daeb79e 100644 --- a/docs/hypervisor-guide/index.rst +++ b/docs/hypervisor-guide/index.rst @@ -3,9 +3,16 @@ Hypervisor documentation ======================== +.. The toctree of the hypervisor design documentation, + providing an overview and links to the various design + documents are added in the `designs` directory and + are referenced using the `designs/index` page here. + (this is a documentation comment which is not rendered) + .. toctree:: :maxdepth: 2 + ../designs/index code-coverage x86/index diff --git a/docs/index.rst b/docs/index.rst index bd87d736b9c3..b6803f6a341e 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -53,17 +53,18 @@ kind of development environment. hypervisor-guide/index misc/ci - Unsorted documents ------------------ Documents in need of some rearranging. +.. The design documentation is added in the `designs` directory + included in the hypervisor guide now. + (this is a documentation comment which is not rendered) + .. toctree:: :maxdepth: 2 - designs/launch/hyperlaunch - designs/launch/hyperlaunch-devicetree misc/xen-makefiles/makefiles misra/index fusa/index -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 09:55:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 09:55:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281554.1564414 (Exim 4.92) (envelope-from ) id 1wCaUD-0008Cp-3p; Tue, 14 Apr 2026 09:55:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281554.1564414; Tue, 14 Apr 2026 09:55:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCaUD-0008Ci-11; Tue, 14 Apr 2026 09:55:13 +0000 Received: by outflank-mailman (input) for mailman id 1281554; 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Tue, 14 Apr 2026 02:55:08 -0700 (PDT) Message-ID: Date: Tue, 14 Apr 2026 12:55:06 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] xen/drivers/char/cadence-uart: fix IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" Cc: Bertrand Marquis , Julien Grall , Michal Orzel , Stefano Stabellini , Volodymyr Babchuk References: Content-Language: en-US From: Oleksandr Tyshchenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776160509-158EC185-A8684F2B/0/0 X-purgate-type: clean X-purgate-size: 2910 On 4/9/26 16:50, Oleksii Moisieiev wrote: Hello Oleksii > In cuart_init_postirq(), two code paths could reach the > interrupt-enable write to IER without a handler being registered: > > - When no valid IRQ number was provided (uart->irq <= 0), the original > positive-condition guard (if uart->irq > 0) skipped the irqaction > setup but still fell through to the IER write, enabling the receive > data interrupt with no handler installed. > > - When setup_irq() returned an error, only an error message was > printed and execution continued to the IER write, arming the > receive hardware interrupt line with no handler to service it. On > platforms where the GIC receives this asserted line, the result is > either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure cuart_init_postirq() to use early returns in both error > paths. > > Signed-off-by: Oleksii Moisieiev > --- > > > > xen/drivers/char/cadence-uart.c | 17 +++++++++++------ > 1 file changed, 11 insertions(+), 6 deletions(-) > > diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uart.c > index b2f379833f..a63dc4adb2 100644 > --- a/xen/drivers/char/cadence-uart.c > +++ b/xen/drivers/char/cadence-uart.c > @@ -72,13 +72,18 @@ static void __init cuart_init_postirq(struct serial_port *port) > struct cuart *uart = port->uart; > int rc; > > - if ( uart->irq > 0 ) > + /* Don't unmask interrupts if no valid irq was provided */ > + if ( uart->irq <= 0 ) But irq field is defined as an unsigned int. By definition, an unsigned int can never be less than zero. > + return; > + > + uart->irqaction.handler = cuart_interrupt; > + uart->irqaction.name = "cadence-uart"; > + uart->irqaction.dev_id = port; > + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > { > - uart->irqaction.handler = cuart_interrupt; > - uart->irqaction.name = "cadence-uart"; > - uart->irqaction.dev_id = port; > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->irq); > + printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->irq); NIT: The format specifier should be %u > + /* Do not unmask interrupts if irq handler wasn't set */ > + return; > } > > /* Clear pending error interrupts */ I notice that with this change, the block that clears pending error interrupts is now skipped if setup_irq() fails or if no valid IRQ is provided. Is this intentional / OK? In "[PATCH v2 1/4] xen/drivers/char: fix SCIF IRQ registration failure propagation", the error status registers are always cleared, even on failure. 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Why would the virtual > one's properties have to match that of the physical one? It is because of how vAPLIC emulation load and store is working. > >> --- /dev/null >> +++ b/xen/arch/riscv/include/asm/vaplic.h >> @@ -0,0 +1,36 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * xen/arch/riscv/vaplic.c >> + * >> + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support >> + * >> + * Copyright (c) Microchip. >> + */ >> + >> +#ifndef ASM__RISCV__VAPLIC_H >> +#define ASM__RISCV__VAPLIC_H >> + >> +#include >> +#include >> + >> +#include >> + >> +struct domain; >> + >> +#define to_vaplic(v) container_of(v, struct vaplic, base) > > I'm confused here, maybe first of all because of the use of v. v is our > common identified for struct vcpu * instances. Using it in a macro like > this one suggests a struct vcpu * needs passing into the macro. Yet from > the two uses of the macro that doesn't look to be the case. v it is stale name when vpalic() was per vCPU. (what looks incorrect as on real h/w APLIC isn't belongs to one pCPU). > > Perhaps best to have a struct domain * passed into here? struct domain * will be better. > >> +struct vaplic_regs { >> + uint32_t domaincfg; >> + uint32_t smsiaddrcfg; >> + uint32_t smsiaddrcfgh; > > The latter two aren't used, and generally I'd expect a h-suffixed field to > exist only for RV32. (The un-suffixed field then would need to be unsigned > long, of course.) It should be a part of another patch. I will drop them for now. > >> +}; >> + >> +struct vaplic { >> + struct vintc base; > > How does "base" fit with the type of the field? The field name base is a idiom for embedding a "base class" struct as the first member, enabling a form of inheritance. Any suggestion how to rename it better? > >> --- a/xen/arch/riscv/intc.c >> +++ b/xen/arch/riscv/intc.c >> @@ -6,6 +6,7 @@ >> #include >> #include >> #include >> +#include >> #include > > Why is this change needed all of the sudden? Incorrect rebase. I will drop that. > >> --- /dev/null >> +++ b/xen/arch/riscv/vaplic.c >> @@ -0,0 +1,74 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * xen/arch/riscv/vaplic.c >> + * >> + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support >> + * >> + * Copyright (c) Microchip. >> + * Copyright (c) Vates >> + */ >> + >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> +#include >> +#include >> + >> +#include "aplic-priv.h" >> + >> +static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >> +{ >> + int rc = 0; >> + >> + rc = vcpu_imsic_init(v); >> + if ( rc ) >> + return rc; >> + >> + imsic_set_guest_file_id(v, vgein_assign(v)); > > And vgein_assign() can't fail? (Rhetorical question - of course it can. That > function shouldn't assert that it can fine a valid ID.) Technically it can't fail (except some bug of course), this function should in general return 0 (when there aren't left h/w IDs) or something > 0 (when there are some h/w IDs). ASSERT() inside it was added only because of ... > > But then - aren't you limiting the number of vCPU-s a host can handle by the > number vgein IDs? ... At the moment, I am limiting because S/W interrutps guest files (IDs) aren't supported. > >> + return rc; >> +} >> + >> +static const struct vintc_ops vaplic_ops = { >> + .vcpu_init = vcpu_vaplic_init, >> +}; >> + >> +static struct vintc * __init vaplic_alloc(void) >> +{ >> + struct vaplic *v = NULL; > > Onve again - why the initializer? In fact, ... > >> + v = xvzalloc(struct vaplic); > > ... this could be the initializer. Sure, I will use it as initializer. > >> + if ( !v ) >> + return NULL; >> + >> + return &v->base; >> +} > > If you returned and ... > >> +int __init domain_vaplic_init(struct domain *d) >> +{ >> + int ret = 0; >> + >> + d->arch.vintc = vaplic_alloc(); > > ... stored struct vaplic *, the slightly odd to_vaplic() macro wouldn't > be needed. vaplic_alloc() return struct vintc *, which is then used by to_vaplic() to get struct vaplic *. > >> + if ( !d->arch.vintc ) >> + { >> + ret = -ENOMEM; >> + goto fail; > > Nit: goto when simply return could be used. > >> + } >> + >> + d->arch.vintc->ops = &vaplic_ops; > > Are other kinds of ops structures going to appear? If not, why the extra > indirection? At the moment, no I don't see any other kinds of ops struct. It was just convenient way to group them and then easier to initialize them - just one assignment instead of addinng a separate line in domain_vaplic_init(). > >> + to_vaplic(d->arch.vintc)->regs.domaincfg = >> + APLIC_DOMAINCFG_IE | APLIC_DOMAINCFG_DM; >> + >> + fail: >> + return ret; >> +} >> + >> +void __init domain_vaplic_deinit(struct domain *d) >> +{ >> + struct vaplic *vaplic = to_vaplic(d->arch.vintc); >> + >> + XVFREE(vaplic); > > If this cleared the struct domain field, then yes. But the way it is, just > xvfree() will suffice. (Re-work following other remarks may want it to > become XVFREE() again, though.) Agree, it could be xvfree() for now. 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Using the kHz based frequency leads to the TSC scaling values possibly not being the same as the ones used by the per CPU cpu_time->tsc_scale field, which introduces skew between the guest and Xen's calculations of the system time. On a 2gHz system, where the frequency is possibly detected as 1999999999Hz (note this is a worse-case scenario), the cpu_khz variable will be set to 1999999kHz, and hence 999Hz cycles will be not accounted for per second. Over a second (the time synchronization period), this leads to a skew of: cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns So far this has gone unnoticed because the time synchronization rendezvous forces the update of the tsc_timestamp and system_time fields in the vCPU time info area, and hence the skew only accumulates up to the rendezvous period. Attempting to remove the rendezvous causes the skew to grow unbounded. Fix by using the native TSC scaling values (as used by Xen) when the guest TSC is not scaled. Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") Signed-off-by: Roger Pau Monné --- I'm worried about the usage of cpu_khz beyond simple printing it for informational purposes. Overall I think it would be safer to store the frequency in Hz, as to avoid losing the least significant digits. In any case, that's a different change. --- xen/arch/x86/time.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index 4233ea507d40..244277c0a921 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1710,17 +1710,25 @@ static void collect_time_info(const struct vcpu *v, else { if ( is_hvm_domain(d) && hvm_tsc_scaling_supported ) - { tsc_stamp = hvm_scale_tsc(d, t->stamp.local_tsc); - u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; - u->tsc_shift = d->arch.vtsc_to_ns.shift; - } else - { tsc_stamp = t->stamp.local_tsc; + + /* + * HVM guests using the native TSC ratio should use the same per-CPU + * scaling factors as Xen. This ensures time keeping is always in sync + * between Xen and the guest. + */ + if ( tsc_stamp == t->stamp.local_tsc ) + { u->tsc_to_system_mul = t->tsc_scale.mul_frac; u->tsc_shift = t->tsc_scale.shift; } + else + { + u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; + u->tsc_shift = d->arch.vtsc_to_ns.shift; + } } u->tsc_timestamp = tsc_stamp; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 10:34:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 10:34:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281574.1564433 (Exim 4.92) (envelope-from ) id 1wCb64-0005Kf-6d; Tue, 14 Apr 2026 10:34:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281574.1564433; Tue, 14 Apr 2026 10:34:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCb64-0005KY-2w; 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First patch fixes the drift, second patch makes the calculation of cpu_khz round up the value for better accuracy. Thanks, Roger. Roger Pau Monne (2): x86/time: use native TSC scaling factors when TSC is not scaled xen/cpu: round up cpu_khz calculations xen/arch/arm/time.c | 4 ++-- xen/arch/riscv/time.c | 2 +- xen/arch/x86/time.c | 20 ++++++++++++++------ 3 files changed, 17 insertions(+), 9 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 10:34:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 10:34:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281577.1564449 (Exim 4.92) (envelope-from ) id 1wCb69-0005ov-Nr; Tue, 14 Apr 2026 10:34:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281577.1564449; Tue, 14 Apr 2026 10:34:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCb69-0005oN-LB; Tue, 14 Apr 2026 10:34:25 +0000 Received: by outflank-mailman (input) for mailman id 1281577; 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Instead use DIV_ROUND_UP() when scaling from Hz to kHz to get as more accurate kHz value. Signed-off-by: Roger Pau Monné --- While the possibly more accurate value is nice, I'm not sure it's actually fixing any functional bug, and hence the lack of "Fixes:" tag. --- xen/arch/arm/time.c | 4 ++-- xen/arch/riscv/time.c | 2 +- xen/arch/x86/time.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index a12912a106a0..9e0c485c77db 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -118,7 +118,7 @@ static void __init preinit_dt_xen_time(void) res = dt_property_read_u32(timer, "clock-frequency", &rate); if ( res ) { - cpu_khz = rate / 1000; + cpu_khz = DIV_ROUND_UP(rate, 1000); validate_timer_frequency(); timer_dt_clock_frequency = rate; } @@ -136,7 +136,7 @@ void __init preinit_xen_time(void) if ( !cpu_khz ) { - cpu_khz = (READ_SYSREG(CNTFRQ_EL0) & CNTFRQ_MASK) / 1000; + cpu_khz = DIV_ROUND_UP(READ_SYSREG(CNTFRQ_EL0) & CNTFRQ_MASK, 1000); validate_timer_frequency(); } diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 7efa76fdbcb1..faca7b70e13a 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -40,7 +40,7 @@ static void __init preinit_dt_xen_time(void) if ( !dt_property_read_u32(timer, "timebase-frequency", &rate) ) panic("Unable to find clock frequency\n"); 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pr=C From: Michal Orzel To: CC: Michal Orzel , Doug Goldstein , Stefano Stabellini , Andrew Cooper Subject: [PATCH] automation: Extend eclair-ARM64-allcode and mark as gating Date: Tue, 14 Apr 2026 13:16:56 +0200 Message-ID: <20260414111656.72939-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615E:EE_|DM4PR12MB6229:EE_ X-MS-Office365-Filtering-Correlation-Id: b530cab0-d318-4f3a-2a35-08de9a175bdd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|18002099003|13003099007|56012099003; X-Microsoft-Antispam-Message-Info: 65jzoNZna+gj+YuDFw/BGp/hO9BjGs5i69RavK5VE1NRTgZMr5g62QeQovNSiypPV4eMZ9+ez2EV181M8jfkm3npc6ynu6L5gjDp2dVMq/BfSFENMl5LPDzpahBfAHrs+Hr4kSSLWSyo4C1ZAhZy1ghCydW454SVlqkiTZSYgODK8WojSosBMVL5mLKcwbBtIMORTRuW+w1SbjwKRTjXHJk42Xtir1SK97hNjN+M1xPDAeJqqGBGkKaptob7ntng5N5cEXL8/xhYU92YRRYkDDqVeCeRKReUM4HQJ3Hf5Qx2h878tPHmIZ9GjpSx5/5sj99GOnoi2u1/eJvIunwSFFBacWJ1RbY7rc9V7oKITw+tQOrsOhxpUojuxCX77kb6liEPinYZtHhblAYYzDYFVdtJPKcgo0hO3URfycqhh/uH/UYaEtXSMxMVjN1hWrb4TNIK/spFSAtR/2blNGPy5nq8rBSBFe1ckCfZeH3qOhDJb16tK6wAnAgp367z0SnRqG9zDMkV00AeIFIXCGybzxKqXyGwNI3PQXG988JUZQjg/E1XxkfWMpjJVuE3c2Qcv4T9aUbodg1K7cOArO9bqeN65mvY7P2snYc63BaBzFP98MrjMOz2fsQ+5ZmwGG132D/T2EzEBvvprRm3FWROoOFecJ5P36sg06K6kf8NP4U/P1sy8NInLIcK0oz7o6eUvZwb/J1lJiu4TY11xJn4EQqqBLjXQh/EgV8F1UbJRTE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(82310400026)(18002099003)(13003099007)(56012099003);DIR:OUT;SFP:1101; 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Given no more regressions for clean rules, mark as gating. Signed-off-by: Michal Orzel --- https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2451527401 --- automation/gitlab-ci/analyze.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/automation/gitlab-ci/analyze.yaml b/automation/gitlab-ci/analyze.yaml index 4e9af9d60224..b3f99f472d9e 100644 --- a/automation/gitlab-ci/analyze.yaml +++ b/automation/gitlab-ci/analyze.yaml @@ -149,7 +149,11 @@ eclair-ARM64-allcode: CONFIG_STACK_PROTECTOR=y CONFIG_UNSUPPORTED=y CONFIG_VM_EVENT=y - allow_failure: true + CONFIG_STATIC_MEMORY=y + CONFIG_STATIC_SHM=y + CONFIG_EARLY_UART_CHOICE_PL011=y + CONFIG_EARLY_UART_BASE_ADDRESS=0x0 + allow_failure: false eclair-ARM64-testing: extends: eclair-ARM64-allcode -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:29:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:29:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281631.1564477 (Exim 4.92) (envelope-from ) id 1wCbxT-0005YJ-6n; Tue, 14 Apr 2026 11:29:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281631.1564477; Tue, 14 Apr 2026 11:29:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCbxT-0005YC-3z; Tue, 14 Apr 2026 11:29:31 +0000 Received: by outflank-mailman (input) for mailman id 1281631; Tue, 14 Apr 2026 11:29:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCbxR-0005Y6-Fg for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:29:29 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCbxQ-002Q05-1S for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:29:28 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de2506-2eae-0a2a0a5409dd-0a2a45019848-32 for ; Tue, 14 Apr 2026 13:29:28 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de2517-6fc9-0a2a45010019-d155802edde2-3 for ; Tue, 14 Apr 2026 13:29:27 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4887f49ec5aso66958685e9.1 for ; Tue, 14 Apr 2026 04:29:27 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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*/ > > Counter question: Why ... > >> +/* >> + * Retrieves the interrupts configuration from a device tree node and maps >> + * those interrupts to the target domain. >> + * >> + * Returns: >> + * < 0 error >> + * 0 success >> + */ >> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >> + bool need_mapping, >> + struct rangeset *irq_ranges); > > ... is this not an inline function, when ... > >> --- a/xen/arch/riscv/intc.c >> +++ b/xen/arch/riscv/intc.c >> @@ -79,3 +79,11 @@ int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) >> >> return -ENOSYS; >> } >> + >> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >> + bool need_mapping, >> + struct rangeset *irq_ranges) >> +{ >> + return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, >> + irq_ranges); >> +} > > ... it's merely a wrapper around an indirect function call? And then the > function isn't used anywhere anyway. It is used by dom0less common code and it is a wrapper because Arm has different implementation and Arm doesn't have map_device_irqs_to_domain() in its virtual interrupt controller operations. > >> --- a/xen/arch/riscv/vaplic.c >> +++ b/xen/arch/riscv/vaplic.c >> @@ -9,6 +9,7 @@ >> */ >> >> #include >> +#include >> #include >> #include >> >> @@ -19,6 +20,113 @@ >> >> #include "aplic-priv.h" >> >> +struct vaplic_priv { >> + /* Contains a legal interrupts for a domain */ >> + uint32_t auth_irq_bmp[APLIC_NUM_REGS]; >> +}; > > With it apparently plural that is correct, the first "a" wants dropping > from the comment. > >> +static bool is_irq_shared_among_domains(const struct domain *d, >> + const unsigned int irq_num) >> +{ >> + struct domain *tmp; > > const > >> + unsigned int reg_num = irq_num / APLIC_NUM_REGS; >> + unsigned int bit_pos = irq_num % APLIC_NUM_REGS; >> + >> + for_each_domain ( tmp ) > > See other uses of the construct for how this needs synchronizing. But looping > over all domains looks pretty inefficient anyway for ... > >> + { >> + uint32_t *auth_irq_bmp; >> + >> + if ( tmp == d ) >> + continue; >> + >> + auth_irq_bmp = tmp->arch.vintc->private; >> + >> + if ( auth_irq_bmp[reg_num] & BIT(bit_pos, U) ) >> + { >> + printk("%s: irq%d is shared between %pd and %pd\n", __func__, >> + irq_num, tmp, d); >> + >> + return true; >> + } > > ... the intended purpose. If IRQs can't be shared, can't you maintain global > state of which ones are in use _somewhere_? Makes sense. I will create a static array inside vaplic_map_device_irqs_to_domain() and maintain global state there. > >> + } >> + >> + return false; >> +} > > This together with ... > >> +int vaplic_map_device_irqs_to_domain(struct domain *d, >> + struct dt_device_node *dev, >> + bool need_mapping, >> + struct rangeset *irq_ranges) >> +{ >> + unsigned int i, nirq; >> + int res, irq; >> + struct dt_raw_irq rirq; >> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >> + unsigned int reg_num; >> + >> + nirq = dt_number_of_irq(dev); >> + >> + /* Give permission and map IRQs */ >> + for ( i = 0; i < nirq; i++ ) >> + { >> + res = dt_device_get_raw_irq(dev, i, &rirq); >> + if ( res ) >> + { >> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >> + i, dt_node_full_name(dev)); >> + return res; >> + } >> + >> + /* >> + * Don't map IRQ that have no physical meaning >> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >> + */ >> + if ( rirq.controller != dt_interrupt_controller ) >> + { >> + dt_dprintk("irq %u not connected to primary controller." >> + "Connected to %s\n", i, >> + dt_node_full_name(rirq.controller)); >> + continue; >> + } >> + >> + irq = platform_get_irq(dev, i); >> + if ( irq < 0 ) >> + { >> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >> + return irq; >> + } >> + >> + res = irq_permit_access(d, irq); >> + if ( res ) >> + { >> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >> + irq); > > This time the other way around: %d please with plain int. (Again at least > once further down.) > >> + return res; >> + } >> + >> + reg_num = irq / APLIC_NUM_REGS; >> + >> + if ( is_irq_shared_among_domains(d, irq) ) >> + { >> + printk("%s: Shared IRQ isn't supported\n", __func__); >> + return -EINVAL; >> + } >> + >> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); > > ... all of this leaves me with the impression that IRQ numbering isn't really > virtualized. IRQs are merely split into groups, one group per domain (and > maybe some unused). How are you going to fit in truly virtual IRQs? What do you mean by truly virtual IRQs? I can't totally agree that the current approach isn't use virtual IRQs, yes, they are 1:1 mapped but on the other side Xen is responsible to give an IRQ number for guest's device and Xen is responsible that guest isn't trying to reach IRQ which not belongs to it. > >> + dt_dprintk(" - IRQ: %u\n", irq); >> + >> + if ( irq_ranges ) >> + { >> + res = rangeset_add_singleton(irq_ranges, irq); >> + if ( res ) >> + return res; >> + } > > What is irq_ranges? IIUC based on Arm code irq_ranges is an optional output accumulator, the caller allocates and passes it in when it needs to track which IRQs were mapped (overlay use case), or passes NULL when that tracking is not needed. I added here as map_device_irqs_to_domain() is called from the common code and so maybe one day someone will decide to pass irq_ranges to this functions. At the moment, for RISC-V it is the only one user of map_device_irqs_to_domain() and it passes NULL. > >> @@ -34,6 +142,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >> >> static const struct vintc_ops vaplic_ops = { >> .vcpu_init = vcpu_vaplic_init, >> + .map_device_irqs_to_domain = vaplic_map_device_irqs_to_domain, >> }; > > What about the inverse function, needed for domain cleanup? I planned to add it when it will be really needed. At the momemnt, I don't have such use cases. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:36:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:36:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281642.1564485 (Exim 4.92) (envelope-from ) id 1wCc4B-00075F-S5; Tue, 14 Apr 2026 11:36:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281642.1564485; Tue, 14 Apr 2026 11:36:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCc4B-000758-PW; Tue, 14 Apr 2026 11:36:27 +0000 Received: by outflank-mailman (input) for mailman id 1281642; Tue, 14 Apr 2026 11:36:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCc49-000752-VE for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:36:26 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCc49-00FyEd-3o for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776166583; x=1776427083; i=ngoc-tu.dinh@vates.tech; bh=xwnl3M2COGDDo2p9tYSk8w95SfMZZ/DdHUWNhVXJjFc=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=mNAGXJrYoNmLRKoPA0DE0SP9PrP70Z6cr04lQrBXUW2E1UszXpBWokEfK7I9552YP wKDLJtk2Wfo3zKWlyDPmVAytcVjLpptFB72N3et9DQsYvSBGGOUaGh+C93iPurml6n Ddn6To9pmNXoL5jWW7QUmTnuT4E+C/KclpXPZnbJ7fhcrX94IpuxTTGiSAysQzAKa6 6kIyTIutb6DWjS7SHoSZfBVv27Jd21OHLdJ6SgsmAv3Mz3+n8eJ1qQRnaZd/3NdMEJ K7pp/jeMFuU9DqTwi44QMiUu4E1DN3zt7ilfHIujPoP+Wv8Hi6lMG7hAO6pwGerYKk FiY8BREJKMgsQ== From: "Tu Dinh" Subject: =?utf-8?Q?Re:=20[PATCH=202/2]=20xen/cpu:=20round=20up=20cpu=5Fkhz=20calculations?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776166581512 Message-Id: To: "Roger Pau Monne" , xen-devel@lists.xenproject.org Cc: "Stefano Stabellini" , "Julien Grall" , "Bertrand Marquis" , "Michal Orzel" , "Volodymyr Babchuk" , "Alistair Francis" , "Connor Davis" , "Oleksii Kurochko" , "Jan Beulich" , "Andrew Cooper" , "Teddy Astie" References: <20260414103327.7420-1-roger.pau@citrix.com> <20260414103327.7420-3-roger.pau@citrix.com> In-Reply-To: <20260414103327.7420-3-roger.pau@citrix.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.257b21c4df744c0ea0670254c1d0c766?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260414:md Date: Tue, 14 Apr 2026 11:36:23 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1776166584-40369C9A-690E3EA6/0/0 X-purgate-type: clean X-purgate-size: 2660 On 14/04/2026 12:36, Roger Pau Monne wrote: > All arches truncate the cpu_khz without taking into account the less > significant digits. Instead use DIV_ROUND_UP() when scaling from Hz to k= Hz > to get as more accurate kHz value. > > Signed-off-by: Roger Pau Monn=C3=A9 Couldn't DIV_ROUND be used here instead for a round-to-closest? > --- > While the possibly more accurate value is nice, I'm not sure it's actuall= y > fixing any functional bug, and hence the lack of "Fixes:" tag. > --- > xen/arch/arm/time.c | 4 ++-- > xen/arch/riscv/time.c | 2 +- > xen/arch/x86/time.c | 2 +- > 3 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index a12912a106a0..9e0c485c77db 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -118,7 +118,7 @@ static void __init preinit_dt_xen_time(void) > res =3D dt_property_read_u32(timer, "clock-frequency", &rate); > if ( res ) > { > - cpu_khz =3D rate / 1000; > + cpu_khz =3D DIV_ROUND_UP(rate, 1000); > validate_timer_frequency(); > timer_dt_clock_frequency =3D rate; > } > @@ -136,7 +136,7 @@ void __init preinit_xen_time(void) > > if ( !cpu_khz ) > { > - cpu_khz =3D (READ_SYSREG(CNTFRQ_EL0) & CNTFRQ_MASK) / 1000; > + cpu_khz =3D DIV_ROUND_UP(READ_SYSREG(CNTFRQ_EL0) & CNTFRQ_MASK, = 1000); > validate_timer_frequency(); > } > > diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c > index 7efa76fdbcb1..faca7b70e13a 100644 > --- a/xen/arch/riscv/time.c > +++ b/xen/arch/riscv/time.c > @@ -40,7 +40,7 @@ static void __init preinit_dt_xen_time(void) > if ( !dt_property_read_u32(timer, "timebase-frequency", &rate) ) > panic("Unable to find clock frequency\n"); > > - cpu_khz =3D rate / 1000; > + cpu_khz =3D DIV_ROUND_UP(rate, 1000); > } > > int reprogram_timer(s_time_t timeout) > diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c > index 244277c0a921..b84414f00d05 100644 > --- a/xen/arch/x86/time.c > +++ b/xen/arch/x86/time.c > @@ -2642,7 +2642,7 @@ void __init early_time_init(void) > set_time_scale(&t->tsc_scale, tmp); > t->stamp.local_tsc =3D boot_tsc_stamp; > > - cpu_khz =3D tmp / 1000; > + cpu_khz =3D DIV_ROUND_UP(tmp, 1000); > printk("Detected %lu.%03lu MHz processor.\n", > cpu_khz / 1000, cpu_khz % 1000); > -- Ngoc Tu Dinh | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:42:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:42:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281653.1564494 (Exim 4.92) (envelope-from ) id 1wCc9r-0000OI-Iz; Tue, 14 Apr 2026 11:42:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281653.1564494; Tue, 14 Apr 2026 11:42:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCc9r-0000OB-G2; Tue, 14 Apr 2026 11:42:19 +0000 Received: by outflank-mailman (input) for mailman id 1281653; Tue, 14 Apr 2026 11:42:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCc9q-0000O5-Pb for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:42:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCc9q-00AwR9-1m for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:42:18 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de280f-5cb7-0a2a0a5109dd-0a2a450ce60a-24 for ; Tue, 14 Apr 2026 13:42:17 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de2819-f40c-0a2a450c0019-d155802bec47-3 for ; Tue, 14 Apr 2026 13:42:17 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-488aa77a06eso91071905e9.0 for ; Tue, 14 Apr 2026 04:42:17 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <2097fefb49fca36f641ddd7d7fb31e796a03619e.1773157782.git.oleksii.kurochko@gmail.com> <072c0f21-a223-46dd-8ea2-f3591c2fd547@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <072c0f21-a223-46dd-8ea2-f3591c2fd547@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776166937-83B44A3D-E7882E6A/10/73395122804 X-purgate-type: spam X-purgate-size: 2544 On 4/2/26 2:51 PM, Jan Beulich wrote: > On 10.03.2026 18:08, Oleksii Kurochko wrote: >> These definitions are required for correct decoding of APLIC MMIO >> accesses and target configuration, and will be used by both the >> physical and virtual APLIC implementations. >> >> No functional change is intended by this patch; it only centralises >> hardware definitions that were previously missing. >> >> Co-developed-by: Romain Caritey >> Signed-off-by: Oleksii Kurochko > > I can commit this as is (with my ack added), but I'd like you to consider > again my remark elsewhere as to ... > >> --- a/xen/arch/riscv/include/asm/aplic.h >> +++ b/xen/arch/riscv/include/asm/aplic.h >> @@ -17,6 +17,11 @@ >> >> #define APLIC_NUM_REGS 32 >> >> +#define APLIC_REG_OFFSET_MASK 0x3FFF >> +#define APLIC_TARGET_IPRIO_MASK 0xFF >> +#define APLIC_TARGET_GUEST_IDX_SHIFT 12 >> +#define APLIC_TARGET_EIID_MASK 0x7FF >> + >> #define APLIC_DOMAINCFG_IE BIT(8, U) >> #define APLIC_DOMAINCFG_DM BIT(2, U) >> >> @@ -27,6 +32,36 @@ >> #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 >> #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 >> >> +#define APLIC_DOMAINCFG 0x0000 >> +#define APLIC_SOURCECFG_BASE 0x0004 >> +#define APLIC_SOURCECFG_LAST 0x0FFC >> + >> +#define APLIC_SMSICFGADDR 0x1BC8 >> +#define APLIC_SMSICFGADDRH 0x1BCC >> + >> +#define APLIC_SETIP_BASE 0x1C00 >> +#define APLIC_SETIP_LAST 0x1C7C >> +#define APLIC_SETIPNUM 0x1CDC >> + >> +#define APLIC_CLRIP_BASE 0x1D00 >> +#define APLIC_CLRIP_LAST 0x1D7C >> +#define APLIC_CLRIPNUM 0x1DDC >> + >> +#define APLIC_SETIE_BASE 0x1E00 >> +#define APLIC_SETIE_LAST 0x1E7C >> +#define APLIC_SETIENUM 0x1EDC >> + >> +#define APLIC_CLRIE_BASE 0x1F00 >> +#define APLIC_CLRIE_LAST 0x1F7C >> +#define APLIC_CLRIENUM 0x1FDC >> + >> +#define APLIC_SETIPNUM_LE 0x2000 >> + >> +#define APLIC_GENMSI 0x3000 >> + >> +#define APLIC_TARGET_BASE 0x3004 >> +#define APLIC_TARGET_LAST 0x3FFC > > ... the case of hex digits vs the need to have L (and hence U) suffixes in > upper case for Misra's sake. Those suffixes are easier to spot as such when > the hex digits use lower case. Then even for un-suffixed numbers lower case > is preferable imo, for overall consistency. I will switch to lower case. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:45:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:45:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281666.1564523 (Exim 4.92) (envelope-from ) id 1wCcCm-00018V-96; Tue, 14 Apr 2026 11:45:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281666.1564523; Tue, 14 Apr 2026 11:45:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcCm-00018O-6T; Tue, 14 Apr 2026 11:45:20 +0000 Received: by outflank-mailman (input) for mailman id 1281666; Tue, 14 Apr 2026 11:45:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCcCl-00018I-7L for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:45:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCcCk-00G083-K6 for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:45:18 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de28c7-5cb7-0a2a0a5109dd-0a2a450a9c24-10 for ; Tue, 14 Apr 2026 13:45:18 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de28ce-ee98-0a2a450a0019-d155802fa8fa-3 for ; Tue, 14 Apr 2026 13:45:18 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-482f454be5bso57861425e9.0 for ; Tue, 14 Apr 2026 04:45:18 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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How can you ... > >> --- a/xen/arch/riscv/vaplic.c >> +++ b/xen/arch/riscv/vaplic.c >> @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >> return 0; >> } >> >> +static int cf_check vaplic_is_access(const struct vcpu *vcpu, >> + const unsigned long addr) >> +{ >> + const struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >> + const struct aplic_priv *priv = vaplic->base.info->private; >> + const paddr_t paddr_end = priv->paddr_start + priv->size; >> + >> + /* check if it is an APLIC access */ >> + if ( priv->paddr_start <= addr && addr < paddr_end ) > > ... use that here? Or asked differently, again: Where's the virtualization, > i.e. the abstraction away from host properties? With the current use case it was easier to choose such approach then provide the full abstraction. > > Furthermore, is it really sufficient to check just the starting address of > an access? Shouldn't the last byte accessed also fall into the range in > question? I think that it is okay, my understanding is that *paddr_end technically is another range. > >> + return 1; >> + >> + return 0; >> +} > > This function looks to want to return bool (and then use true/false). Agree, then it will also need to update function pointer prototype in vintc_ops. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:51:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:51:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281681.1564545 (Exim 4.92) (envelope-from ) id 1wCcIJ-0002yM-0V; Tue, 14 Apr 2026 11:51:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281681.1564545; Tue, 14 Apr 2026 11:51:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcII-0002yF-U7; Tue, 14 Apr 2026 11:51:02 +0000 Received: by outflank-mailman (input) for mailman id 1281681; Tue, 14 Apr 2026 11:51:01 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCcIH-0002y9-AC for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:51:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCcIG-006dsP-Mw for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:51:00 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de2a1d-e002-0a2a0a5209dd-0a2a4506e108-34 for ; Tue, 14 Apr 2026 13:51:00 +0200 Received: from [209.85.221.47] (helo=mail-wr1-f47.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de2a24-0df0-0a2a45060019-d155dd2fe5bf-3 for ; Tue, 14 Apr 2026 13:51:00 +0200 Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-43d43e09de5so3262103f8f.1 for ; Tue, 14 Apr 2026 04:51:00 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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I am totally okay with that. I will do that. Thasnks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 11:56:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 11:56:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281690.1564553 (Exim 4.92) (envelope-from ) id 1wCcNI-0003Wl-Hs; Tue, 14 Apr 2026 11:56:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281690.1564553; Tue, 14 Apr 2026 11:56:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcNI-0003We-F6; Tue, 14 Apr 2026 11:56:12 +0000 Received: by outflank-mailman (input) for mailman id 1281690; Tue, 14 Apr 2026 11:56:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcNH-0003WY-6h for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 11:56:11 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCcNG-005k04-Jk for xen-devel@lists.xenproject.org; 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Instead use DIV_ROUND_UP() when scaling from Hz to kHz > > to get as more accurate kHz value. > > > > Signed-off-by: Roger Pau Monné > > Couldn't DIV_ROUND be used here instead for a round-to-closest? My bad, I got confused with the macro names. Roger. From xen-devel-bounces@lists.xenproject.org Tue Apr 14 12:04:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 12:04:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281701.1564564 (Exim 4.92) (envelope-from ) id 1wCcVh-0005Pl-EP; Tue, 14 Apr 2026 12:04:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281701.1564564; Tue, 14 Apr 2026 12:04:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcVh-0005Pe-Ag; Tue, 14 Apr 2026 12:04:53 +0000 Received: by outflank-mailman (input) for mailman id 1281701; Tue, 14 Apr 2026 12:04:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCcVf-0005PY-Pp for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 12:04:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCcVf-009KLV-6t for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 14:04:51 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de2d5c-2eae-0a2a0a5409dd-0a2a4504c700-36 for ; Tue, 14 Apr 2026 14:04:51 +0200 Received: from [162.55.131.47] (helo=support.bugseng.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de2d62-bb33-0a2a45040019-a237832fa4e2-3 for ; Tue, 14 Apr 2026 14:04:51 +0200 Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) (Authenticated sender: nicola) by support.bugseng.com (Postfix) with ESMTPA id D11C34EE8D50; Tue, 14 Apr 2026 14:04:50 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: bugseng.com; arc=none smtp.remote-ip=162.55.131.47 ARC-Seal: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; cv=none; t=1776168290; b=znbrPan31mdDDHdVtmu6dWk8WqZ1Q4SrB14En764rUvEbfjGN9nQR4hjZPCJtW7aS4Lp eOdge/ytg2jeta356aJOgtQyUhiV9v/Wmgn8V+941EitL73XAQdXUKIanKMmAjlJXTNdd qJPh7raabU55f3pqSF8h7H7oJHem4lR1hBGA217r9cFxYZM4JNgMEdcuHPp/TKj/rtV6A VlVWmHrwt9KAPjwwjXMAa7vhZ+dOP5JXPfdNitjuptDHl0hAYFA0j+SMhUMEYDF7EE4Px xz+TR9q3VTbyFF1uVrGzfoJaJrOlX0mA+lb0/qqSFP771BiYPNutTw5elPwpbZLBoHpvs DL5qQhNa9GUy8WUIqM2iLK5lbS7XyEngFyQJIZjRISZc4N1S19TpJbGWYRMBUAT2ZRqUx B1CzEN9Qq+iKVloRPKxL2vSZ/Ih4DJuplf9OIVorTuTuw+GW2ihwp+dz8cTSSEBeB5KSs kWgRYXWMUZz4UVkAVunowzJZ/1JoroNJ9asFeeZztLoJ4ACpsCt2HfzbUFQJVzO7MvpLR +mBFpWAyNsY7vEiZxyhox86dYBkdl/sCEgjpbqDsoF/kUS9b5I6HDHi32kD9t665e532B SRBSRlc9bZ6woWKDonN2ZpNjCaSpoFVlr8Tq/6zNG1VmsPbYf4KBzzVg1nbFpWc= ARC-Message-Signature: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; c=relaxed/relaxed; t=1776168290; h=MIME-Version:Date:From:To:Cc:Subject:In-Reply-To:References: Message-ID:X-Sender:Organization:Content-Type: Content-Transfer-Encoding; bh=JU4pvPTIQQJuO3ucPW6MqZkZAJcCu5Tx5uiE1Cgg+EM=; b=RmusjHEqebKyWtX0QgrExWGoW2TgaKeU8jWwU9cnyblA4eIF62/ZrAuon0KJfz643s5A JbGNLirFnbMU55jXuYRta1H9108noFriKNuR5pe8uMpOWlEXXBpd48jnpPwf6Zksij8N8 hlV57s6RGqOwKxRDitbYmVt0h4f+njzCUP+S8N8oCH6FaSFrC5/QqOaQnT3jgkHizikiK X8kTpEljpsxQSWdx5fG7tsnuGfCCd0Skmtx/mnjoi+RrVd68wZwAvt8ROth95lvTTQqwX RiP/mXXYJg4hk9FA8rirQgwy47eLM5hsZLWRwbn/nGYQ/Gyj9vctZ0T9hPS2u1/VkJKYk by9u/EjBJvPMXNgl5JJYcNeo1ELRpBavXB7X7bLGWBdgCripRRQ6teO/WpdUczCz+WmN9 sGk0VpnN5ROzJnbh6hhJi+Pa/xbxpyz+5KQqlI+fEJMhUg1dfYhRn54J86a+wx0ZrQWuX 2/XsgaKowePkaXmkohc+0DYNQ7oszUVsFVeBpyiAUDihpYzipfdwTo+1HT4DI4YIiEsy5 0SEH/fqQ4A7oX1XBRztkdc0k0SRj1r0ZRYF8XPWEBRf2NG/t2yIoxFiBkVHxenUabMkXp Qx2X2vWyF5Um3ja7YNgZlHe+vLP/7Rpz8Bcmq8SNZC1gwLvsV185nMJ351xD850= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Tue, 14 Apr 2026 14:04:50 +0200 From: Nicola Vetrini To: Michal Orzel Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini , Andrew Cooper Subject: Re: [PATCH] automation: Extend eclair-ARM64-allcode and mark as gating In-Reply-To: <20260414111656.72939-1-michal.orzel@amd.com> References: <20260414111656.72939-1-michal.orzel@amd.com> Message-ID: <68b7bb7e95e6ae92b976c98af1a7cab9@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776168291-31F2651B-B3ED53E4/0/0 X-purgate-type: clean X-purgate-size: 1352 On 2026-04-14 13:16, Michal Orzel wrote: > Extend the job by enabling static memory, static shared memory and > early > printk features. Given no more regressions for clean rules, mark as > gating. > > Signed-off-by: Michal Orzel > --- > https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2451527401 NIT: pipeline does not seem to be public. Other than that: Reviewed-by: Nicola Vetrini > --- > automation/gitlab-ci/analyze.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/automation/gitlab-ci/analyze.yaml > b/automation/gitlab-ci/analyze.yaml > index 4e9af9d60224..b3f99f472d9e 100644 > --- a/automation/gitlab-ci/analyze.yaml > +++ b/automation/gitlab-ci/analyze.yaml > @@ -149,7 +149,11 @@ eclair-ARM64-allcode: > CONFIG_STACK_PROTECTOR=y > CONFIG_UNSUPPORTED=y > CONFIG_VM_EVENT=y > - allow_failure: true > + CONFIG_STATIC_MEMORY=y > + CONFIG_STATIC_SHM=y > + CONFIG_EARLY_UART_CHOICE_PL011=y > + CONFIG_EARLY_UART_BASE_ADDRESS=0x0 > + allow_failure: false > > eclair-ARM64-testing: > extends: eclair-ARM64-allcode -- Nicola Vetrini, B.Sc. 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pr=C Message-ID: <04a5356f-17ba-4aa0-95c1-045d8efffdb3@amd.com> Date: Tue, 14 Apr 2026 14:32:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] automation: Extend eclair-ARM64-allcode and mark as gating To: Nicola Vetrini CC: , Doug Goldstein , Stefano Stabellini , Andrew Cooper References: <20260414111656.72939-1-michal.orzel@amd.com> <68b7bb7e95e6ae92b976c98af1a7cab9@bugseng.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <68b7bb7e95e6ae92b976c98af1a7cab9@bugseng.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A5:EE_|DS4PR12MB9771:EE_ X-MS-Office365-Filtering-Correlation-Id: f0613454-3692-4d40-f133-08de9a21db75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0EPhpcqlV5Ohk3osjLvOlTf6o0WEWAFECRV8GNvlrRQzPiyD585IZLkPTI+eY1H5n4DLhOdpHyshCnSGZjFWCYeKPApmoV6Dmw3UZilIShmQbas9SccGnOOZ+uPgmx6f3rOdR16qlwZfnPFWBlsmzHVlNylQSxAdHS/V7PP1vyzqje+7N90MITJIOO+Goj6bq5W+KDh2t19oIrLusv9Lkfm/2+gxb3uRTdRuQYORzQ6/IrXUECpwWmkj5MZxe+GLnNdCAZPD5UmkaVP0BC4azz1ytQHq7VkC882HtzT4vdZuS/ddkO7wv2kGY8qpMdieSciFfS8k6mhFsYg11ccf5WBLktjwrT4aYurysGA/vYXLRdQk8fW8+m8pDAAQD3XUn1E4lrZufZzLWad7drGWIAm4C7YxbEH4C53jAPBnP45UcmnvpVPwu98Xr/+ffgKQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2026 12:32:13.9293 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0613454-3692-4d40-f133-08de9a21db75 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9771 X-purgate-ID: tlsNG-720697/1776169938-447CBCD1-74EEC9B1/0/0 X-purgate-type: clean X-purgate-size: 629 On 14/04/2026 14:04, Nicola Vetrini wrote: > On 2026-04-14 13:16, Michal Orzel wrote: >> Extend the job by enabling static memory, static shared memory and >> early >> printk features. Given no more regressions for clean rules, mark as >> gating. >> >> Signed-off-by: Michal Orzel >> --- >> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2451527401 > > NIT: pipeline does not seem to be public. Other than that: Ah yes, my fork is private, so only owners (i.e. committers) can see it. > > Reviewed-by: Nicola Vetrini Thanks. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 14 12:37:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 12:37:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281730.1564613 (Exim 4.92) (envelope-from ) id 1wCd1M-0002Ah-Hq; Tue, 14 Apr 2026 12:37:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281730.1564613; Tue, 14 Apr 2026 12:37:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCd1M-0002Aa-Et; Tue, 14 Apr 2026 12:37:36 +0000 Received: by outflank-mailman (input) for mailman id 1281730; Tue, 14 Apr 2026 12:37:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCd1L-0002AK-18 for xen-devel@lists.xenproject.org; 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Tue, 14 Apr 2026 05:37:32 -0700 (PDT) MIME-Version: 1.0 References: <20260410164039.1000284-1-ruslichenko.r@gmail.com> <358dc4fb-139b-4000-99cb-c9271e90437d@epam.com> In-Reply-To: <358dc4fb-139b-4000-99cb-c9271e90437d@epam.com> From: Ruslan Ruslichenko Date: Tue, 14 Apr 2026 14:37:20 +0200 X-Gm-Features: AQROBzBzEfXsERmTVDGkisvVxFwcHpmRn1YsCRm4l15OcpihPcQdjXdqjOA7-N4 Message-ID: Subject: Re: [PATCH] xen/sched: fix scheduler callback verification on init To: Mykyta Poturai Cc: "xen-devel@lists.xenproject.org" , Volodymyr Babchuk , Ruslan Ruslichenko , Dario Faggioli , Juergen Gross , George Dunlap Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1776170253-41512C9A-91311D73/0/0 X-purgate-type: clean X-purgate-size: 2537 On Tue, Apr 14, 2026 at 1:10=E2=80=AFPM Mykyta Poturai wrote: > > On 4/10/26 19:40, Ruslan Ruslichenko wrote: > > From: Ruslan Ruslichenko > > > > During core scheduler initialization, each registered scheduler > > is sanity tested in two steps: > > > > - it must provide required callbacks (e.g. init, do_schedule). > > - if global_init callback is present, it must succeed. > > > > If any of the steps fail, scheduler entry is cleared in global > > 'schedulers' array. > > > > However, in the current implementation, if verification fails during > > the first step, the scheduler entry is cleared but verification > > sequence is not interrupted. This lead to NULL pointer dereference > > when subsequent required callbacks verified, and possible during > > the second step. > > > > The patch fixes the crashes by adding check inside sched_test_func > > macro and skipping the call to a global_init if first step did not pass= . > > > > Signed-off-by: Ruslan Ruslichenko > > --- > > xen/common/sched/core.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c > > index a57d5dd929..4270c89491 100644 > > --- a/xen/common/sched/core.c > > +++ b/xen/common/sched/core.c > > @@ -3017,7 +3017,7 @@ void __init scheduler_init(void) > > for ( i =3D 0; i < NUM_SCHEDULERS; i++) > > { > > #define sched_test_func(f) \ > > - if ( !schedulers[i]->f ) \ > > + if ( schedulers[i] && !schedulers[i]->f ) \ > > { \ > > printk("scheduler %s misses .%s, dropped\n", \ > > schedulers[i]->opt_name, #f); \ > > schedulers[i] =3D NULL; \ > > Maybe it would be cleaner to just add "continue" here? > Probably, yes. This will also skip unneeded checks after the first missing callback. I will update the patch then. -- BR, Ruslan > > @@ -3034,6 +3034,9 @@ void __init scheduler_init(void) > > > > #undef sched_test_func > > > > + if ( !schedulers[i] ) > > + continue; > > + > > if ( schedulers[i]->global_init && schedulers[i]->global_init= () < 0 ) > > { > > printk("scheduler %s failed initialization, dropped\n", > > -- > Mykyta From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:15:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:15:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281749.1564622 (Exim 4.92) (envelope-from ) id 1wCdbq-0007Er-9l; Tue, 14 Apr 2026 13:15:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281749.1564622; Tue, 14 Apr 2026 13:15:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdbq-0007Ek-77; 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b=QTrq3iH1BqPikEoAyTeqxDTXVmEiJqeYh1MBlB/M896WFeDc38HAXXIU+SDhkAjAAvwFhUrbuh018e/GNDPa0ZDz4Bxo69jXXMiMDdt7yeJN8aHC0Tzf4XplPMlFBxdOEdUl2egLnMDnzCZc1PTShilUpfu5Fq7rq53ORjUGPBJnlsyLws6x+PH8RLNF8UxR3L/Y6tXCsv4TYTyoAHld/Of5o8p/2ZrOn60W4JnN5mWMpA3JwLcxrGqx6bYOQyBonvD78ctqXEUCBDTvtJcXYedz8TGxJiMUkuVQS6dcJ2/OrTnXYTs9Kx6fCRpKfCY/yUUsfFrKu6aYXrlBB6demg== From: Mykyta Poturai To: "xen-devel@lists.xenproject.org" CC: Mykyta Poturai , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Rahul Singh Subject: [PATCH v2] xen/arm: smmuv3: Add support for removing devices Thread-Topic: [PATCH v2] xen/arm: smmuv3: Add support for removing devices Thread-Index: AQHczBC6OGp5DbFlyEyismnWkcVdqA== Date: Tue, 14 Apr 2026 13:15:12 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PAVPR03MB10102:EE_|PA6PR03MB10362:EE_ x-ms-office365-filtering-correlation-id: 4a07abd4-df28-4f4a-e4d1-08de9a27dc8a x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|376014|1800799024|366016|38070700021|56012099003|18002099003; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4a07abd4-df28-4f4a-e4d1-08de9a27dc8a X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Apr 2026 13:15:12.7335 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: zKgu/Bf8Zy2kOPQi/ipex+d2mKen255zwhysMC0MNXo4pEWc8A9uYXhPeiGIuHhJl8yihGjW9i8swKu/hQjHhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA6PR03MB10362 X-purgate-ID: tlsNG-16d1c6/1776172516-6484B3D8-2F745132/0/0 X-purgate-type: clean X-purgate-size: 5618 Allow for removing devices from SMMUv3. arm_smmu_deassign_dev handles most of the work by disabling ATS and zeroing STEs. Additionally, unset the dt_device_is_protected flag and free no longer needed smmu_master. Rework dt_device_set_protected to accept a boolean parameter, update callsites. Tested on QEMU with SRIOV series[1] by repeatedly enabling/disabling VFs. [1]: https://patchew.org/Xen/cover.1772806036.git.mykyta._5Fpoturai@epam.co= m/ Signed-off-by: Mykyta Poturai --- V1-V2: * check for phantom functions * simplify pci/dt device split * improve error handling * don't try to free master for unprotected devices * rework dt_device_set_protected --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 57 +++++++++++++++++++++++- xen/drivers/passthrough/arm/smmu.c | 4 +- xen/include/xen/device_tree.h | 5 ++- 4 files changed, 62 insertions(+), 6 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index fa9ab9cb13..0648f9b407 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1367,7 +1367,7 @@ static int ipmmu_add_device(u8 devfn, struct device *= dev) } =20 /* Let Xen know that the master device is protected by an IOMMU. *= / - dt_device_set_protected(dev_to_dt(dev)); + dt_device_set_protected(dev_to_dt(dev), true); } #ifdef CONFIG_HAS_PCI if ( dev_is_pci(dev) ) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index bf153227db..8e080cd7d0 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1493,6 +1493,60 @@ static int arm_smmu_assign_dev(struct domain *d, u8 = devfn, struct device *dev, static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, struct device *dev); =20 +static int arm_smmu_remove_device(u8 devfn, struct device *dev) +{ + struct arm_smmu_master *master; + struct iommu_fwspec *fwspec; + struct domain *d =3D NULL; + + fwspec =3D dev_iommu_fwspec_get(dev); + if ( !fwspec ) + return -ENODEV; + + master =3D dev_iommu_priv_get(dev); + if ( !master ) + return -ENODEV; + + if ( IS_ENABLED(CONFIG_HAS_PCI) && dev_is_pci(dev) ) + { + struct pci_dev *pdev =3D dev_to_pci(dev); + + /* Ignore calls for phantom functions */ + if ( devfn !=3D pdev->devfn ) + return 0; + + d =3D pdev->domain; + } + else + { + if ( !dt_device_is_protected(dev_to_dt(dev)) ) + { + dev_err(dev, "Not added to SMMUv3\n"); + return -ENODEV; + } + + dt_device_set_protected(dev_to_dt(dev), false); + if ( master->domain && master->domain->d ) + d =3D master->domain->d; + } + + if ( d ) + { + int ret =3D arm_smmu_deassign_dev(d, devfn, dev); + /* This should never fail because we already checked the domain */ + ASSERT(!ret); + } + + arm_smmu_disable_pasid(master); + + dev_info(dev, "Removed master device (SMMUv3 %s StreamIds %u)\n", + dev_name(fwspec->iommu_dev), fwspec->num_ids); + + xfree(master); + dev_iommu_priv_set(dev, NULL); + return 0; +} + static int arm_smmu_add_device(u8 devfn, struct device *dev) { int i, ret; @@ -1571,7 +1625,7 @@ static int arm_smmu_add_device(u8 devfn, struct devic= e *dev) } =20 /* Let Xen know that the master device is protected by an IOMMU. */ - dt_device_set_protected(dev_to_dt(dev)); + dt_device_set_protected(dev_to_dt(dev), true); } =20 dev_info(dev, "Added master device (SMMUv3 %s StreamIds %u)\n", @@ -2867,6 +2921,7 @@ static const struct iommu_ops arm_smmu_iommu_ops =3D = { .unmap_page =3D arm_iommu_unmap_page, .dt_xlate =3D arm_smmu_dt_xlate, .add_device =3D arm_smmu_add_device, + .remove_device =3D arm_smmu_remove_device, }; =20 static __init int arm_smmu_dt_init(struct dt_device_node *dev, diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index d63c901551..4d2f71f152 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -825,7 +825,7 @@ static int arm_smmu_dt_add_device_legacy(struct arm_smm= u_device *smmu, if ( !dev_is_pci(dev) ) { /* Xen: Let Xen know that the device is protected by an SMMU */ - dt_device_set_protected(dev_node); + dt_device_set_protected(dev_node, true); } =20 for (i =3D 0; i < fwspec->num_ids; ++i) { @@ -862,7 +862,7 @@ static int arm_smmu_dt_remove_device_legacy(struct arm_= smmu_device *smmu, =20 if ( !dev_is_pci(dev) ) /* Protected by dt_host_lock and dtdevs_lock as caller holds these locks= . */ - dev_node->is_protected =3D false; + dt_device_set_protected(dev_node, false); =20 kfree(master); return 0; diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 06d7643622..76ae1e674a 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -300,9 +300,10 @@ static inline domid_t dt_device_used_by(const struct d= t_device_node *device) return device->used_by; } =20 -static inline void dt_device_set_protected(struct dt_device_node *device) +static inline void dt_device_set_protected(struct dt_device_node *device, + bool protected) { - device->is_protected =3D true; + device->is_protected =3D protected; } =20 static inline bool dt_device_is_protected(const struct dt_device_node *dev= ice) --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:18:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:18:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281759.1564631 (Exim 4.92) (envelope-from ) id 1wCdeV-0007vS-Of; Tue, 14 Apr 2026 13:18:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281759.1564631; Tue, 14 Apr 2026 13:18:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdeV-0007vL-Lz; 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Tue, 14 Apr 2026 09:17:17 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Juergen Gross , "Daniel P. Smith" , Christian Lindig , David Scott Subject: [PATCH v6 0/7] xen/mm: Introduce NUMA-aware claim sets for domains Date: Tue, 14 Apr 2026 14:15:57 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776172681-BFE7BFF4-F7A99ACD/0/0 X-purgate-type: clean X-purgate-size: 5785 Hi all, This series extends Xen's memory claim handling to support claim sets spanning multiple NUMA nodes. Earlier review raised the concern that claims would need to evolve from a single claim into a multi-node model. Roger Pau Monné described the core requirement well: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. -- Roger Pau Monné This submission implements that model, and its design and code have been validated through the following methods: 1. A suite of host-side integration tests (to be posted shortly), which can be executed on the build host (e.g., on a developer machine) like the PDX tests by Roger Pau Monné (make -C tools/tests/pdx run), as well as the domid and rangeset tests. 2. A comprehensive functional system test suite (with nineteen test cases), included in this v6 submission. These tests are run using automated deployment across various machine types and generations in our labs. 3. A set of high-level functional integration tests and performance tests, executed as part of end-to-end product deployment validation. 4. Validation in a customer's standardised application performance lab to confirm their performance expectations. (This testing was done on predecessor code sharing the same design, with the main difference being that only single-node claims were supported in the previous code base.) The series has been reworked substantially in response to v4 review. Because of that, it is likely best reviewed as a fresh series rather than incrementally. Patch summary: 1. xen/mm: Refactor deducting claims to prepare for functional changes 2. xen/mm: Claims check: Allow free pages to cover a shortfall of claims 3. xen/mm: Optimise getting free page counts per NUMA node 4. xen/mm: Split d->outstanding_pages to global_claims & node_claims 5. xen/mm: Introduce Claim Sets for multiple NUMA nodes 6. tools/ocaml/libs/xc: Add OCaml bindings for NUMA-aware claims 7. tools/tests/mem-claim: Add a test suite for the memory claim API The v2 design document submitted ahead of this series may also help with review. It explains the background, design rationale, and implementation details. Rendered version: https://bernhard-xen.readthedocs.io/en/claim-sets-v2-design/designs/claims Many thanks to everyone who contributed to the earlier work and review, especially Alejandro Vallejo, Jan Beulich, Andrew Cooper, Roger Pau Monné, Marcus Granado, and Edwin Török. Changes since v5: ----------------- - No functional changes for the sum of all commits. (Adding a new function argument was moved to the commit that needs it.) - Added a comprehensive test suite for the new hypercall using the libxenctrl wrapper xc_domain_claim_memory(), based on the test in tools/tests/mem-claim/test-mem-claim.c for the existing hypercall API by Andrew Cooper. - Improved the function names to follow standard naming recommendations. The added functions are renamed as follows: * claims_retire_allocation() -> redeem_claims_for_allocation() - Use "redeem" because it is part of an exchange of claims for memory. * claims_retire_global() -> deduct_global_claims() * claims_retire_nodes() -> deduct_node_claims() - These perform the act of reducing the amount of global/node claims. * claims_retire_node() -> cancel_all_node_claims() - Cancel all node claims when needed when the claims are terminated. * The comments and the design document v2 have been updated accordingly. Thanks, Bernhard Bernhard Kaindl (7): xen/mm: Refactor claim deduction for later functional changes xen/mm: Allow free pages to cover a claims shortfall xen/mm: Optimise getting free page counts per NUMA node xen/mm: Split outstanding claims into global and node totals xen/mm: Introduce NUMA-aware memory claim sets tools/ocaml/libs/xc: Add an OCaml binding for NUMA-aware claims tools/tests/mem-claim: Add a test suite for the memory claim API tools/include/xenctrl.h | 4 + tools/libs/ctrl/xc_domain.c | 38 + tools/ocaml/libs/xc/xenctrl.ml | 11 + tools/ocaml/libs/xc/xenctrl.mli | 11 + tools/ocaml/libs/xc/xenctrl_stubs.c | 47 + tools/tests/mem-claim/.gitignore | 1 + tools/tests/mem-claim/Makefile | 17 +- tools/tests/mem-claim/accounting-1.h | 401 +++++++++ tools/tests/mem-claim/input-phase1.h | 171 ++++ tools/tests/mem-claim/input-phase2.h | 91 ++ tools/tests/mem-claim/libtestclaims.c | 995 ++++++++++++++++++++++ tools/tests/mem-claim/libtestclaims.h | 202 +++++ tools/tests/mem-claim/test-claim-memory.c | 129 +++ xen/common/domctl.c | 56 +- xen/common/page_alloc.c | 374 +++++++- xen/include/public/domctl.h | 32 + xen/include/public/memory.h | 9 + xen/include/xen/mm.h | 3 + xen/include/xen/sched.h | 13 +- xen/xsm/flask/hooks.c | 1 + xen/xsm/flask/policy/access_vectors | 1 + 21 files changed, 2573 insertions(+), 34 deletions(-) create mode 100644 tools/tests/mem-claim/accounting-1.h create mode 100644 tools/tests/mem-claim/input-phase1.h create mode 100644 tools/tests/mem-claim/input-phase2.h create mode 100644 tools/tests/mem-claim/libtestclaims.c create mode 100644 tools/tests/mem-claim/libtestclaims.h create mode 100644 tools/tests/mem-claim/test-claim-memory.c -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:24:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:24:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281788.1564640 (Exim 4.92) (envelope-from ) id 1wCdl6-00014g-E1; Tue, 14 Apr 2026 13:24:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281788.1564640; Tue, 14 Apr 2026 13:24:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdl6-00014Z-B8; Tue, 14 Apr 2026 13:24:52 +0000 Received: by outflank-mailman (input) for mailman id 1281788; Tue, 14 Apr 2026 13:24:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdl5-00014S-Pi for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:24:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdl4-0062r6-GJ for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:24:50 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de4020-e002-0a2a0a5209dd-0a2a4506c2d6-8 for ; Tue, 14 Apr 2026 15:24:50 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de4021-0df0-0a2a45060019-a0658308b188-3 for ; Tue, 14 Apr 2026 15:24:50 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id 85E40424A79F; Tue, 14 Apr 2026 09:24:06 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 1/7] xen/mm: Refactor claim deduction for later functional changes Date: Tue, 14 Apr 2026 14:22:45 +0100 Message-Id: <5302d33e7e896347acc7a8212df4f28ea098e28e.1776172526.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776173090-5E32F3D8-CC5F05F9/0/0 X-purgate-type: clean X-purgate-size: 2424 Refactor claim deduction to make the claims accounting model easier to follow ahead of later functional changes. Three new callers will need to deduct claims, and two of them will also need the number of pages deducted to be returned. No functional change. Signed-off-by: Bernhard Kaindl --- History: Functionally unchanged since v4, only minor cleanups have been applied and: - Updated the function name deduct_global_claims() to follow standard naming. - Moved the other function into another commit as it had no users here. --- xen/common/page_alloc.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index b1edef87124f..80577aa4d50c 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -518,6 +518,19 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages) return d->tot_pages; } +/* Deduct up to the given amount of pages from the global claims of a domain */ +static unsigned long deduct_global_claims(struct domain *d, + unsigned long reduction) +{ + reduction = min(reduction, d->outstanding_pages + 0UL); + ASSERT(reduction <= outstanding_claims); + + outstanding_claims -= reduction; + d->outstanding_pages -= reduction; + + return reduction; +} + int domain_set_outstanding_pages(struct domain *d, unsigned long pages) { int ret = -ENOMEM; @@ -535,8 +548,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { - outstanding_claims -= d->outstanding_pages; - d->outstanding_pages = 0; + deduct_global_claims(d, d->outstanding_pages); ret = 0; goto out; } @@ -1067,11 +1079,7 @@ static struct page_info *alloc_heap_pages( * the domain being destroyed before creation is finished. Losing part * of the claim makes no difference. */ - unsigned long outstanding = min(d->outstanding_pages + 0UL, request); - - BUG_ON(outstanding > outstanding_claims); - outstanding_claims -= outstanding; - d->outstanding_pages -= outstanding; + deduct_global_claims(d, request); } check_low_mem_virq(); -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:25:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:25:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281806.1564648 (Exim 4.92) (envelope-from ) id 1wCdlm-0001Y8-MD; Tue, 14 Apr 2026 13:25:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281806.1564648; Tue, 14 Apr 2026 13:25:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdlm-0001Y1-Iu; Tue, 14 Apr 2026 13:25:34 +0000 Received: by outflank-mailman (input) for mailman id 1281806; Tue, 14 Apr 2026 13:25:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdll-0001Xp-Rp for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:25:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdll-00GLNf-8O for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:25:33 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de403c-2eae-0a2a0a5409dd-0a2a450bb360-46 for ; Tue, 14 Apr 2026 15:25:33 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de404a-bca8-0a2a450b0019-a0658309e5ae-3 for ; Tue, 14 Apr 2026 15:25:32 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id D35F181A5671; Tue, 14 Apr 2026 09:24:36 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 2/7] xen/mm: Allow free pages to cover a claims shortfall Date: Tue, 14 Apr 2026 14:22:46 +0100 Message-Id: <5d1e06a0fcaee4520bf79d58199e447194f84fe8.1776172526.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776173133-ED9512A1-8F1A5C29/0/0 X-purgate-type: clean X-purgate-size: 3086 Allow an allocation to proceed when free, unclaimed memory can cover a claims shortfall. In preparation for NUMA-aware claims, refactor this check into a reusable helper so the same logic can be applied to NUMA nodes. Suggested-by: Jan Beulich Signed-off-by: Bernhard Kaindl --- Changes since v4: Extracted into a dedicated patch and merged the formerly separate functions into one, as suggested by Jan Beulich. Signed-off-by: Bernhard Kaindl --- xen/common/page_alloc.c | 41 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 38 insertions(+), 3 deletions(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 80577aa4d50c..a67839413319 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -868,6 +868,42 @@ static void check_and_stop_scrub(struct page_info *head) } } +/* + * Allow the request when unclaimed pages suffice, or when a refcounted + * domain's outstanding claims cover the shortfall. + */ +static bool claims_permit_request(const struct domain *d, + unsigned long avail_pages, + unsigned long competing_claims, + unsigned int memflags, + unsigned long requested_pages) +{ + unsigned long unclaimed_pages; + + ASSERT(spin_is_locked(&heap_lock)); + ASSERT(avail_pages >= competing_claims); + + /* Start from the free pages not already claimed by other domains. */ + unclaimed_pages = avail_pages - competing_claims; + + /* Allow the request to proceed when unclaimed pages suffice. */ + if ( requested_pages <= unclaimed_pages ) + return true; + + /* + * If unclaimed pages are insufficient, only a refcounted domain allocation + * may use claims to cover the shortfall. + */ + if ( !d || (memflags & MEMF_no_refcount) ) + return false; + + /* + * Allow the request to proceed when combination of unclaimed pages and the + * claims held by the domain cover the shortfall for the requested_pages. + */ + return requested_pages <= unclaimed_pages + d->outstanding_pages; +} + static struct page_info *get_free_buddy(unsigned int zone_lo, unsigned int zone_hi, unsigned int order, unsigned int memflags, @@ -1012,9 +1048,8 @@ static struct page_info *alloc_heap_pages( * Claimed memory is considered unavailable unless the request * is made by a domain with sufficient unclaimed pages. */ - if ( (outstanding_claims + request > total_avail_pages) && - ((memflags & MEMF_no_refcount) || - !d || d->outstanding_pages < request) ) + if ( !claims_permit_request(d, total_avail_pages, outstanding_claims, + memflags, request) ) { spin_unlock(&heap_lock); return NULL; -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:26:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:26:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281823.1564657 (Exim 4.92) (envelope-from ) id 1wCdmm-000246-U2; Tue, 14 Apr 2026 13:26:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281823.1564657; Tue, 14 Apr 2026 13:26:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdmm-00023z-RL; Tue, 14 Apr 2026 13:26:36 +0000 Received: by outflank-mailman (input) for mailman id 1281823; Tue, 14 Apr 2026 13:26:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdml-00023r-K7 for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:26:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdmk-00GLlP-Ve for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:26:35 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de407e-bab6-0a2a0a5309dd-0a2a4506d774-42 for ; Tue, 14 Apr 2026 15:26:34 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de4089-0df0-0a2a45060019-a06583088930-3 for ; Tue, 14 Apr 2026 15:26:34 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id 9FBB6424A7AA; Tue, 14 Apr 2026 09:25:50 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Alejandro Vallejo Subject: [PATCH v6 3/7] xen/mm: Optimise getting free page counts per NUMA node Date: Tue, 14 Apr 2026 14:22:47 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776173194-5DB2B3D8-A3F06007/0/0 X-purgate-type: clean X-purgate-size: 3131 From: Alejandro Vallejo Introduce per-node free page counters to improve the efficiency of avail_node_heap_pages(): - It no longer needs to iterate over all zones in a node. - It is used by the numainfo hypercall and the debug key 'u' to display NUMA information in the printk buffer. - It will also be needed by node-specific claims to determine the number of free pages in a node in the hot path of get_free_buddy() without looping over all zones. No functional change. Signed-off-by: Alejandro Vallejo Signed-off-by: Bernhard Kaindl --- Applied Jan's review: https://lists.xenproject.org/archives/html/xen-devel/2026-03/msg00144.html Changes: - Removed accessor macro - Abandoned conversion to unsigned long --- xen/common/page_alloc.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index a67839413319..28c424072d25 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -485,7 +485,20 @@ static unsigned long node_need_scrub[MAX_NUMNODES]; static unsigned long *avail[MAX_NUMNODES]; static long total_avail_pages; +/* + * Sum of the free pages in all zones of that node. + * Provided via sysctl by NUMA node placement decisions of domain builders and + * for monitoring. It is also logged with debug-key 'u' for NUMA debugging. + */ +static long node_avail_pages[MAX_NUMNODES]; +/* + * The global heap lock, protecting access to the heap and related structures. + * It protects the heap and claims of the buddy allocator and d->*claims. + * The locking order is: d->page_alloc_lock (optional) -> heap_lock + * - Numerous external callers holding d->page_alloc_lock call functions + * taking the heap_lock. Note: Violating it would cause an ABBA deadlock. + */ static DEFINE_SPINLOCK(heap_lock); static long outstanding_claims; /* total outstanding claims by all domains */ @@ -1092,6 +1105,8 @@ static struct page_info *alloc_heap_pages( } } + ASSERT(node_avail_pages[node] >= request); + node_avail_pages[node] -= request; ASSERT(avail[node][zone] >= request); avail[node][zone] -= request; total_avail_pages -= request; @@ -1282,6 +1297,7 @@ static int reserve_offlined_page(struct page_info *head) if ( !page_state_is(cur_head, offlined) ) continue; + node_avail_pages[node]--; avail[node][zone]--; total_avail_pages--; ASSERT(total_avail_pages >= 0); @@ -1606,6 +1622,7 @@ static void free_heap_pages( } } + node_avail_pages[node] += 1 << order; avail[node][zone] += 1 << order; total_avail_pages += 1 << order; if ( need_scrub ) @@ -2873,7 +2890,7 @@ unsigned long avail_domheap_pages_region( unsigned long avail_node_heap_pages(unsigned int nodeid) { - return avail_heap_pages(MEMZONE_XEN, NR_ZONES -1, nodeid); + return node_avail_pages[nodeid]; } -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:27:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:27:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281855.1564667 (Exim 4.92) (envelope-from ) id 1wCdnZ-0002cb-6i; Tue, 14 Apr 2026 13:27:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281855.1564667; Tue, 14 Apr 2026 13:27:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdnZ-0002cU-3r; Tue, 14 Apr 2026 13:27:25 +0000 Received: by outflank-mailman (input) for mailman id 1281855; Tue, 14 Apr 2026 13:27:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdnX-0002cA-SR for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:27:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdnV-006tG8-NV for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:27:23 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de40b9-5cb7-0a2a0a5109dd-0a2a450487f8-14 for ; Tue, 14 Apr 2026 15:27:23 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de40ba-bb33-0a2a45040019-a0658309c394-3 for ; Tue, 14 Apr 2026 15:27:23 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id C4BE581A567F; Tue, 14 Apr 2026 09:26:28 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v6 4/7] xen/mm: Split outstanding claims into global and node totals Date: Tue, 14 Apr 2026 14:22:48 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776173243-3152351B-B3EE361C/0/0 X-purgate-type: clean X-purgate-size: 6513 Replace d->outstanding_pages with d->global_claims and add d->node_claims as the aggregate of the domain's node-specific claims. Keep the allocator hot path efficient and report the combined claims state using the two new fields. No functional change. Signed-off-by: Bernhard Kaindl --- xen/common/domctl.c | 2 +- xen/common/page_alloc.c | 33 ++++++++++++++++----------------- xen/include/xen/sched.h | 7 +++++-- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 93738931c575..2cc5a4ff32fd 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -97,7 +97,7 @@ void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) info->tot_pages = domain_tot_pages(d); info->max_pages = d->max_pages; - info->outstanding_pages = d->outstanding_pages; + info->outstanding_pages = d->global_claims + d->node_claims; #ifdef CONFIG_MEM_SHARING info->shr_pages = atomic_read(&d->shr_pages); #endif diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 28c424072d25..ee4942f93373 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -535,11 +535,11 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages) static unsigned long deduct_global_claims(struct domain *d, unsigned long reduction) { - reduction = min(reduction, d->outstanding_pages + 0UL); + reduction = min(reduction, d->global_claims + 0UL); ASSERT(reduction <= outstanding_claims); outstanding_claims -= reduction; - d->outstanding_pages -= reduction; + d->global_claims -= reduction; return reduction; } @@ -552,8 +552,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* * Two locks are needed here: * - d->page_alloc_lock: protects accesses to d->{tot,max,extra}_pages. - * - heap_lock: protects accesses to d->outstanding_pages, total_avail_pages - * and outstanding_claims. + * - heap_lock: Protects accesses to the claims and avail_pages state. */ nrspin_lock(&d->page_alloc_lock); spin_lock(&heap_lock); @@ -561,13 +560,13 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { - deduct_global_claims(d, d->outstanding_pages); + deduct_global_claims(d, d->global_claims); ret = 0; goto out; } - /* only one active claim per domain please */ - if ( d->outstanding_pages ) + /* Reject updating global claims and we can't update node claims */ + if ( d->global_claims || d->node_claims ) { ret = -EINVAL; goto out; @@ -594,8 +593,8 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) goto out; /* yay, claim fits in available memory, stake the claim, success! */ - d->outstanding_pages = claim; - outstanding_claims += d->outstanding_pages; + d->global_claims = claim; + outstanding_claims += claim; ret = 0; out: @@ -891,7 +890,7 @@ static bool claims_permit_request(const struct domain *d, unsigned int memflags, unsigned long requested_pages) { - unsigned long unclaimed_pages; + unsigned long unclaimed_pages, applicable_claims; ASSERT(spin_is_locked(&heap_lock)); ASSERT(avail_pages >= competing_claims); @@ -910,11 +909,13 @@ static bool claims_permit_request(const struct domain *d, if ( !d || (memflags & MEMF_no_refcount) ) return false; + applicable_claims = d->global_claims; + /* * Allow the request to proceed when combination of unclaimed pages and the * claims held by the domain cover the shortfall for the requested_pages. */ - return requested_pages <= unclaimed_pages + d->outstanding_pages; + return requested_pages <= unclaimed_pages + applicable_claims; } static struct page_info *get_free_buddy(unsigned int zone_lo, @@ -1112,18 +1113,16 @@ static struct page_info *alloc_heap_pages( total_avail_pages -= request; ASSERT(total_avail_pages >= 0); - if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) ) + if ( d && d->global_claims && !(memflags & MEMF_no_refcount) ) { /* * Adjust claims in the same locked region where total_avail_pages is * adjusted, not doing so would lead to a window where the amount of * free memory (avail - claimed) would be incorrect. * - * Note that by adjusting the claimed amount here it's possible for - * pages to fail to be assigned to the claiming domain while already - * having been subtracted from d->outstanding_pages. Such claimed - * amount is then lost, as the pages that fail to be assigned to the - * domain are freed without replenishing the claim. This is fine given + * Note, after redeeming claims for the allocation here, assign_pages() + * could fail. The domain looses The redeemed claims as the not assigned + * pages are freed without replenishing the claim. This is fine given * claims are only to be used during physmap population as part of * domain build, and any failure in assign_pages() there will result in * the domain being destroyed before creation is finished. Losing part diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..2995c99aa34a 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -413,8 +413,11 @@ struct domain unsigned int tot_pages; unsigned int xenheap_pages; /* pages allocated from Xen heap */ - /* Pages claimed but not possessed, protected by global heap_lock. */ - unsigned int outstanding_pages; + + /* All claims are protected by the heap_lock */ + unsigned int global_claims; /* Global Host-level claims */ + unsigned int node_claims; /* Sum of the Node-specific claims */ + unsigned int max_pages; /* maximum value for domain_tot_pages() */ unsigned int extra_pages; /* pages not included in domain_tot_pages() */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:28:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:28:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281881.1564677 (Exim 4.92) (envelope-from ) id 1wCdoJ-0003CD-JE; Tue, 14 Apr 2026 13:28:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281881.1564677; Tue, 14 Apr 2026 13:28:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdoJ-0003C5-FB; Tue, 14 Apr 2026 13:28:11 +0000 Received: by outflank-mailman (input) for mailman id 1281881; Tue, 14 Apr 2026 13:28:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdoH-0003Bv-Q2 for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:28:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdoH-00BM0p-6y for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:28:09 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de40e3-5cb7-0a2a0a5109dd-0a2a4509d356-10 for ; Tue, 14 Apr 2026 15:28:09 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de40e8-bf79-0a2a45090019-a0658309dd12-3 for ; Tue, 14 Apr 2026 15:28:08 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 2D56481A5881; Tue, 14 Apr 2026 09:27:14 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Daniel P. Smith" , Marcus Granado , Alejandro Vallejo Subject: [PATCH v6 5/7] xen/mm: Introduce NUMA-aware memory claim sets Date: Tue, 14 Apr 2026 14:22:49 +0100 Message-Id: <9557995cdab48481b7276443cbae11b00ef03c2e.1776172526.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1776173289-5D1F5152-81BCB725/0/0 X-purgate-type: clean X-purgate-size: 28667 Extend Xen's memory claim handling to support claim sets spanning multiple NUMA nodes. Earlier review raised the concern that claims would need to evolve from a single claim into a multi-node model. Roger Pau Monné described the core requirement well: > Ideally, we would need to introduce a new hypercall that allows > making claims from multiple nodes in a single locked region, > as to ensure success or failure in an atomic way. -- Roger Pau Monné Implement that model. A claim set can contain multiple node-specific claims and an optional global claim for memory that may come from any NUMA node. The new domctl installs the full claim set atomically, and the allocator is updated so that claim checks and claim consumption follow the new semantics. This adds: 1. Installing multi-node claim sets atomically, 2. protecting claimed pages from other claim requests and allocations, 3. redeeming claims for allocations with claims, 4. while keeping the legacy claim interface without functional changes. Suggested-by: Jan Beulich Suggested-by: Marcus Granado Signed-off-by: Alejandro Vallejo Signed-off-by: Roger Pau Monné Signed-off-by: Bernhard Kaindl --- The v2 design document submitted ahead of this series may help with review. It explains the background, design rationale, and implementation details. Rendered version: https://bernhard-xen.readthedocs.io/en/claim-sets-v2-design/designs/claims Many thanks to everyone who contributed to the earlier work and review, especially Alejandro Vallejo, Jan Beulich, Andrew Cooper, Roger Pau Monné, Marcus Granado, and Edwin Török. Thanks, Bernhard --- tools/include/xenctrl.h | 4 + tools/libs/ctrl/xc_domain.c | 38 ++++ xen/common/domctl.c | 54 ++++++ xen/common/page_alloc.c | 277 +++++++++++++++++++++++++++- xen/include/public/domctl.h | 32 ++++ xen/include/public/memory.h | 9 + xen/include/xen/mm.h | 3 + xen/include/xen/sched.h | 6 + xen/xsm/flask/hooks.c | 1 + xen/xsm/flask/policy/access_vectors | 1 + 10 files changed, 420 insertions(+), 5 deletions(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index d5dbf69c8968..a0a9f2143b32 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -2659,6 +2659,10 @@ int xc_domain_set_llc_colors(xc_interface *xch, uint32_t domid, const uint32_t *llc_colors, uint32_t num_llc_colors); +int xc_domain_claim_memory(xc_interface *xch, uint32_t domid, + uint32_t nr_claims, + memory_claim_t *claims); + #if defined(__arm__) || defined(__aarch64__) int xc_dt_overlay(xc_interface *xch, void *overlay_fdt, uint32_t overlay_fdt_size, uint8_t overlay_op); diff --git a/tools/libs/ctrl/xc_domain.c b/tools/libs/ctrl/xc_domain.c index 01c0669c8863..32cd91187d44 100644 --- a/tools/libs/ctrl/xc_domain.c +++ b/tools/libs/ctrl/xc_domain.c @@ -1070,6 +1070,44 @@ int xc_domain_remove_from_physmap(xc_interface *xch, return xc_memory_op(xch, XENMEM_remove_from_physmap, &xrfp, sizeof(xrfp)); } +/* Claim the guest memory for a domain before starting the domain build */ +int xc_domain_claim_memory(xc_interface *xch, + uint32_t domid, + uint32_t nr_claims, + memory_claim_t *claims) +{ + struct xen_domctl domctl = {}; + DECLARE_HYPERCALL_BOUNCE(claims, sizeof(*claims) * nr_claims, + XC_HYPERCALL_BUFFER_BOUNCE_IN); + int ret; + + if ( xc_hypercall_bounce_pre(xch, claims) ) + return -1; + + domctl.cmd = XEN_DOMCTL_claim_memory; + domctl.domain = domid; + domctl.u.claim_memory.nr_claims = nr_claims; + set_xen_guest_handle(domctl.u.claim_memory.claims, claims); + + ret = do_domctl(xch, &domctl); + + xc_hypercall_bounce_post(xch, claims); + + return ret; +} + +/* + * Legacy API for claiming pages, replaced by xc_domain_claim_memory() + * + * Note: This hypercall is deprecated by xc_domain_claim_memory() + * which provides the same claim semantics described above, and thus can be + * used as drop-in replacement and is extended for NUMA-node-specific claims. + * This hypercall should not be used by new code. + * + * See the following documentation pages for more information: + * docs/guest-guide/dom/DOMCTL_claim_memory.rst + * docs/guest-guide/mem/XENMEM_claim_pages.rst + */ int xc_domain_claim_pages(xc_interface *xch, uint32_t domid, unsigned long nr_pages) diff --git a/xen/common/domctl.c b/xen/common/domctl.c index 2cc5a4ff32fd..16d239c75bde 100644 --- a/xen/common/domctl.c +++ b/xen/common/domctl.c @@ -51,6 +51,51 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemask, MAX_NUMNODES); } +/* Claim memory for a domain (or if a claim exists, release the claim) */ +static int claim_memory(struct domain *d, + const struct xen_domctl_claim_memory *uinfo) +{ + memory_claim_t *claims; + int rc = -EFAULT; + + /* alloc_color_heap_page() does not handle claims, reject LLC coloring. */ + if ( llc_coloring_enabled ) + return -EOPNOTSUPP; + + if ( !uinfo->nr_claims || uinfo->pad ) + return -EINVAL; + + /* Only calls for the supported number of nodes + a global claim can pass */ + if ( uinfo->nr_claims > MAX_NUMNODES + 1 ) + return -E2BIG; + + /* + * Under domctl_lock, domain_kill() sets d->is_dying and retires claims. + * If it set, this is in the past and we should reject the claim request. + */ + if ( d->is_dying ) + return -ESRCH; + + claims = xmalloc_array(memory_claim_t, uinfo->nr_claims); + if ( claims == NULL ) + return -ENOMEM; + + if ( copy_from_guest(claims, uinfo->claims, uinfo->nr_claims) ) + goto out; + + rc = -EINVAL; /* Default error code for invalid claim args */ + if ( claims[0].target == XEN_DOMCTL_CLAIM_MEMORY_LEGACY && + uinfo->nr_claims == 1 ) + /* Implement installing a legacy claim for backwards compatibility */ + rc = domain_set_outstanding_pages(d, claims[0].pages); + else + /* domain_install_claim_set() performs validation of the claim set */ + rc = domain_install_claim_set(d, uinfo->nr_claims, claims); + out: + xfree(claims); + return rc; +} + void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) { struct vcpu *v; @@ -865,6 +910,15 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) copyback = true; break; + case XEN_DOMCTL_claim_memory: + /* Use the same XSM hook as XENMEM_claim_pages */ + ret = xsm_claim_pages(XSM_PRIV, d); + if ( ret ) + break; + + ret = claim_memory(d, &op->u.claim_memory); + break; + default: ret = arch_do_domctl(op, d, u_domctl); break; diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index ee4942f93373..6101bd6be9a9 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -502,6 +502,9 @@ static long node_avail_pages[MAX_NUMNODES]; static DEFINE_SPINLOCK(heap_lock); static long outstanding_claims; /* total outstanding claims by all domains */ +/* Sum of the outstanding claims of all domains on that node. */ +static long node_outstanding_claims[MAX_NUMNODES]; + static unsigned long avail_heap_pages( unsigned int zone_lo, unsigned int zone_hi, unsigned int node) { @@ -544,6 +547,164 @@ static unsigned long deduct_global_claims(struct domain *d, return reduction; } +/* Release outstanding claims on a specific node */ +static unsigned long deduct_node_claims(struct domain *d, nodeid_t node, + unsigned long release) +{ + unsigned long consumed = 0; + + /* If the allocation was larger than the claims, do not release beyond it */ + if ( d->claims[node] ) /* Release the claims for this node */ + { + /* Use min_t for clarity to make the comparison type explicit */ + consumed = min_t(unsigned long, release, d->claims[node]); + d->claims[node] -= consumed; + + ASSERT(consumed <= outstanding_claims); + outstanding_claims -= consumed; + + ASSERT(consumed <= node_outstanding_claims[node]); + node_outstanding_claims[node] -= consumed; + + ASSERT(consumed <= d->node_claims); + d->node_claims -= consumed; + } + return consumed; +} + +/* Release all outstanding claims on all online nodes */ +static void cancel_all_node_claims(struct domain *d) +{ + nodeid_t node; + + for_each_online_node ( node ) + { + if ( !d->node_claims ) + return; + deduct_node_claims(d, node, d->claims[node]); + } +} + +/* Validate a claim set and install it if valid. */ +int domain_install_claim_set(struct domain *d, unsigned int nr_claims, + memory_claim_t *claim_set) +{ + nodemask_t nodes; + uint32_t target; + uint64_t pages, tot_pages, max_pages, node_requests = 0, global_request = 0; + bool global_target_seen = false; + int ret = -EINVAL; + + nrspin_lock(&d->page_alloc_lock); + spin_lock(&heap_lock); + + /* + * Phase 1: Check and process the individual claim entries. + * Result: Extracted global claims and the sum of the node-local claims. + */ + nodes_clear(nodes); + for ( int i = 0; i < nr_claims; i++ ) + { + target = claim_set[i].target; + pages = claim_set[i].pages; + if ( claim_set[i].pad ) /* Check before handling global claims */ + goto out; + + if ( target == XEN_DOMCTL_CLAIM_MEMORY_GLOBAL ) + { + if ( global_target_seen ) /* Only one global target allowed */ + goto out; + + global_request = pages; /* Will be checked with the total claims */ + global_target_seen = true; + continue; + } + + if ( target >= MAX_NUMNODES || !node_online(target) ) + { + ret = -ENOENT; /* Node not valid or not online */ + goto out; + } + if ( nodemask_test(target, &nodes) || /* Duplicate node in claim set */ + /* Check for overflow before we add the pages to node_requests */ + pages > ((typeof(d->node_claims))-1) - node_requests ) + goto out; + node_set(target, nodes); + + ASSERT(node_outstanding_claims[target] >= 0 && + node_avail_pages[target] >= node_outstanding_claims[target]); + if ( pages > (uint64_t)(node_avail_pages[target] - + node_outstanding_claims[target]) + + d->claims[target] ) /* current claim deduction */ + { + ret = -ENOMEM; /* Claim exceeds available memory on node */ + goto out; + } + node_requests += pages; /* Will be checked with the total claims */ + } + + max_pages = d->max_pages; + tot_pages = domain_tot_pages(d); + /* + * Check that the total of claims and current pages fits in d->max_pages. + * Subtract sequentially from max_pages instead of adding the claims: + * each subtraction is safe because the prior comparison guarantees + * the subtrahend doesn't exceed the remaining budget. This avoids + * overflow regardless of the type widths of the claims and max_pages, + * as long as the claims are non-negative (which they are, as unsigned) + * and max_pages is not negative, which we check as well here. + */ + if ( global_request > max_pages || + node_requests > max_pages - global_request || + tot_pages > max_pages - global_request - node_requests ) + goto out; /* claims + domain_tot_pages exceeds max_pages: EINVAL */ + + /* States the invariants we are committed to for the next check */ + ASSERT(outstanding_claims >= 0 && total_avail_pages >= outstanding_claims); + /* + * Ensure swapping claims fits into the global unclaimed pages: + * + * Compare the new claims (global_request + node_requests) against the + * available unclaimed memory (total_avail_pages - outstanding_claims) + * plus the domain's current claims (d->global_claims + d->node_claims) + * because they will be deducted when installing the new claim state. + */ + if ( global_request + node_requests > + (uint64_t)(total_avail_pages - outstanding_claims) + d->global_claims + + d->node_claims ) + { + ret = -ENOMEM; + goto out; /* Claim update exceeds available unclaimed memory: ENOMEM */ + } + + /* Phase 3: Remove the old claims before installing the new claims */ + deduct_global_claims(d, d->global_claims); + cancel_all_node_claims(d); + + /* Phase 4: Install new claims: Global claims and overall node claims */ + outstanding_claims += global_request + node_requests; + d->global_claims = global_request; + d->node_claims = node_requests; + + /* Phase 5: Install the individual node claims */ + for ( int i = 0; i < nr_claims; i++ ) + { + target = claim_set[i].target; + pages = claim_set[i].pages; + if ( target >= MAX_NUMNODES ) /* Skip non-node claim targets */ + continue; + + /* Install the node claim and update the node's total claims claims. */ + d->claims[target] = pages; + node_outstanding_claims[target] += pages; + } + ret = 0; +out: + spin_unlock(&heap_lock); + nrspin_unlock(&d->page_alloc_lock); + return ret; +} + int domain_set_outstanding_pages(struct domain *d, unsigned long pages) { int ret = -ENOMEM; @@ -560,6 +721,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) /* pages==0 means "unset" the claim. */ if ( pages == 0 ) { + cancel_all_node_claims(d); deduct_global_claims(d, d->global_claims); ret = 0; goto out; @@ -603,6 +765,85 @@ out: return ret; } +/* + * Redeem the claims to cover a successful allocation. + * + * The claims for an allocation are redeemed in order of specificity: + * + * 1.) Firstly, the claim for the node the allocation was from (if any), + * 2.) Secondly, followed by global claims as a fallback (if any), and + * 3.) Finally, other remaining node claims from other nodes (if any). + * + * This order ensures that the most specific claims are redeemed first, + * and that the global claim is only used as a fallback if the node-specific + * claim is insufficient to cover the allocation or non-existant in case + * the domain doesn't have a claim on the alloc_node. This preserves the + * intent of the claims system to allow domains to reserve memory on + * specific nodes and only use global claims as a fallback when necessary. + * + * Finally, if the domain doesn't have sufficient claims on the alloc_node + * and the global fallback claim doesn't cover the remains of the allocation, + * but as the domain still has other claims, redeem the remaining portion + * of the allocation from those claims. + * + * This final step ensures that the domain's total claims (global + node + * claims) are always redeemed to cover the allocation, which in turn + * prevents domain_tot_pages(d) + d->global_claims + d->node_claims + * from exceeding the domain's d->max_pages limit. + * + * If this final step was not taken, then it would be possible for a domain to + * block off more than its share of system memory as defined by d->max_pages. + * + * Note: We can't reliably check d->max_pages here, at least not under the + * d->page_alloc_lock as taking it here would violate the locking order, + * but we can ensure that the domain's claims are always redeemed to cover + * the allocation, which is sufficient to preserve the intent of d->max_pages + * cap the domain's memory usage and claims to d->max_pages. While we could + * add checking it without lock as a best effort check, a domain builder is + * not supposed to claim memory on one set of nodes and then allocate from + * another set of nodes, so it would not be meaningful to add such a check, + * and the final check covers our bases to handle such misbehaviour anyway. + */ +static void redeem_claims_for_allocation(struct domain *d, + unsigned long pages_to_redeem, + nodeid_t alloc_node) +{ + ASSERT(spin_is_locked(&heap_lock)); + + /* 1.) Redeem the allocation from the alloc_node's claim insofar possible */ + if ( d->claims[alloc_node] ) + { + pages_to_redeem -= deduct_node_claims(d, alloc_node, pages_to_redeem); + if ( pages_to_redeem == 0 ) + return; /* The allocation is fully consumed by alloc_node claim */ + } + + /* 2.) Redeem the unredeemed allocation from the global / fallback claims */ + pages_to_redeem -= deduct_global_claims(d, pages_to_redeem); + + if ( pages_to_redeem == 0 || !d->node_claims ) + return; /* Allocation fully consumed or the domain has no claims left */ + + /* + * 3.) Finally, if the domain doesn't have sufficient claims on alloc_node + * and the global fallback claim didn't cover the remains of the allocation, + * consume the remaining portion of the allocation from the domain's other + * node claims. See the function comment for the details behind this step. + */ + pages_to_redeem = min(pages_to_redeem, d->node_claims + 0UL); + if ( pages_to_redeem ) + { + nodeid_t node; + + for_each_online_node ( node ) + { + pages_to_redeem -= deduct_node_claims(d, node, pages_to_redeem); + if ( pages_to_redeem == 0 ) + break; + } + } +} + #ifdef CONFIG_SYSCTL void get_outstanding_claims(uint64_t *free_pages, uint64_t *outstanding_pages) { @@ -888,7 +1129,7 @@ static bool claims_permit_request(const struct domain *d, unsigned long avail_pages, unsigned long competing_claims, unsigned int memflags, - unsigned long requested_pages) + unsigned long requested_pages, nodeid_t node) { unsigned long unclaimed_pages, applicable_claims; @@ -915,6 +1156,24 @@ static bool claims_permit_request(const struct domain *d, * Allow the request to proceed when combination of unclaimed pages and the * claims held by the domain cover the shortfall for the requested_pages. */ + if ( node == NUMA_NO_NODE ) + /* + * We are checking global claims: For the global claims check, + * we apply the domain's global claims and node claims: The domain + * can use any of its claims to allow the global check to proceed. + * + * get_free_buddy() will repeat this check using a node which + * will check if either the node has enough unclaimed pages + * or the domain enough claims for the node (see below). + */ + applicable_claims = d->node_claims + d->global_claims; + else + /* + * We are checking node-specific claims: For the node-specific claims + * check, we may only apply the domain's claim on that specific node. + */ + applicable_claims = d->claims[node]; + return requested_pages <= unclaimed_pages + applicable_claims; } @@ -967,9 +1226,15 @@ static struct page_info *get_free_buddy(unsigned int zone_lo, */ for ( ; ; ) { + /* Ensure the target node and the claims permit this allocation */ + if ( !claims_permit_request(d, node_avail_pages[node], + node_outstanding_claims[node], memflags, + 1UL << order, node) ) + goto try_next_node; + zone = zone_hi; do { - /* Check if target node can support the allocation. */ + /* Check if this target zone on node can support the allocation. */ if ( !avail[node] || (avail[node][zone] < (1UL << order)) ) continue; @@ -996,6 +1261,8 @@ static struct page_info *get_free_buddy(unsigned int zone_lo, } } while ( zone-- > zone_lo ); /* careful: unsigned zone may wrap */ + try_next_node: + /* If MEMF_exact_node was passed, we may not skip to a different node */ if ( (memflags & MEMF_exact_node) && req_node != NUMA_NO_NODE ) return NULL; @@ -1063,7 +1330,7 @@ static struct page_info *alloc_heap_pages( * is made by a domain with sufficient unclaimed pages. */ if ( !claims_permit_request(d, total_avail_pages, outstanding_claims, - memflags, request) ) + memflags, request, NUMA_NO_NODE) ) { spin_unlock(&heap_lock); return NULL; @@ -1113,7 +1380,7 @@ static struct page_info *alloc_heap_pages( total_avail_pages -= request; ASSERT(total_avail_pages >= 0); - if ( d && d->global_claims && !(memflags & MEMF_no_refcount) ) + if ( d && !(memflags & MEMF_no_refcount) ) { /* * Adjust claims in the same locked region where total_avail_pages is @@ -1128,7 +1395,7 @@ static struct page_info *alloc_heap_pages( * the domain being destroyed before creation is finished. Losing part * of the claim makes no difference. */ - deduct_global_claims(d, request); + redeem_claims_for_allocation(d, request, node); } check_low_mem_virq(); diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..a4f08248e6ee 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -1276,6 +1276,36 @@ struct xen_domctl_get_domain_state { uint64_t unique_id; /* Unique domain identifier. */ }; +struct xen_memory_claim { + uint64_aligned_t pages; /* Number of pages to claim */ + uint32_t target; /* Node and/or claim type like legacy or a global claim */ + uint32_t pad; /* Explicit padding: Reserved, initialize to 0 on input */ +}; +typedef struct xen_memory_claim memory_claim_t; +DEFINE_XEN_GUEST_HANDLE(memory_claim_t); + +/* Special claim targets for the target field of memory_claim_t */ +#define XEN_DOMCTL_CLAIM_MEMORY_LEGACY 0x40000000U /* No node, legacy claim */ +#define XEN_DOMCTL_CLAIM_MEMORY_GLOBAL 0x80000000U /* No node, global claim */ + +/* + * XEN_DOMCTL_claim_memory + * + * Claim memory for a guest domain. It sets aside an amount of memory + * (it is not pre-allocated) for the purpose of satisfying future memory + * allocation requests for building the guest's physical address space. + * Memory can be claimed on a set of nodes, or globally (without node + * affinity), or with legacy behavior. The set of claims is a claim set. See + * docs/guest-guide/dom/DOMCTL_claim_memory.rsti and docs/designs/claims/. + */ +struct xen_domctl_claim_memory { + /* IN: Array of struct xen_memory_claim */ + XEN_GUEST_HANDLE_64(memory_claim_t) claims; + /* IN: Number of claims in the claims array handle. */ + uint32_t nr_claims; + uint32_t pad; /* Explicit padding: Reserved, initialize to 0 on input */ +}; + struct xen_domctl { /* Stable domctl ops: interface_version is required to be 0. */ uint32_t cmd; @@ -1368,6 +1398,7 @@ struct xen_domctl { #define XEN_DOMCTL_gsi_permission 88 #define XEN_DOMCTL_set_llc_colors 89 #define XEN_DOMCTL_get_domain_state 90 /* stable interface */ +#define XEN_DOMCTL_claim_memory 91 #define XEN_DOMCTL_gdbsx_guestmemio 1000 #define XEN_DOMCTL_gdbsx_pausevcpu 1001 #define XEN_DOMCTL_gdbsx_unpausevcpu 1002 @@ -1436,6 +1467,7 @@ struct xen_domctl { #endif struct xen_domctl_set_llc_colors set_llc_colors; struct xen_domctl_get_domain_state get_domain_state; + struct xen_domctl_claim_memory claim_memory; uint8_t pad[128]; } u; }; diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h index bd9fc37b5297..ccec095f8660 100644 --- a/xen/include/public/memory.h +++ b/xen/include/public/memory.h @@ -569,6 +569,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_mem_sharing_op_t); * for 10, only 7 additional pages are claimed. * * Caller must be privileged or the hypercall fails. + * + * Note: This hypercall is deprecated by XEN_DOMCTL_claim_memory + * which provides the same claim semantics described above, and thus can be + * used as drop-in replacement and is extended for NUMA-node-specific claims. + * This hypercall should not be used by new code. + * + * See the following documentation pages for more information: + * docs/guest-guide/dom/DOMCTL_claim_memory.rst + * docs/guest-guide/mem/XENMEM_claim_pages.rst */ #define XENMEM_claim_pages 24 diff --git a/xen/include/xen/mm.h b/xen/include/xen/mm.h index b80bec00c124..b2d6a6f266ba 100644 --- a/xen/include/xen/mm.h +++ b/xen/include/xen/mm.h @@ -69,6 +69,7 @@ #include #include #include +#include #include struct page_info; @@ -131,6 +132,8 @@ int populate_pt_range(unsigned long virt, unsigned long nr_mfns); /* Claim handling */ unsigned long __must_check domain_adjust_tot_pages(struct domain *d, long pages); +int domain_install_claim_set(struct domain *d, unsigned int nr_claims, + memory_claim_t *claims); int domain_set_outstanding_pages(struct domain *d, unsigned long pages); void get_outstanding_claims(uint64_t *free_pages, uint64_t *outstanding_pages); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 2995c99aa34a..d31f4546e3b0 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -417,6 +417,12 @@ struct domain /* All claims are protected by the heap_lock */ unsigned int global_claims; /* Global Host-level claims */ unsigned int node_claims; /* Sum of the Node-specific claims */ + /* + * struct domain is allocated in a dedicated page with more than enough + * spare capacity. It's efficient to use that page to store the + * per-node claims in it instead allocating a separate array for it. + */ + unsigned int claims[MAX_NUMNODES]; /* Array of per-NUMA-node claims */ unsigned int max_pages; /* maximum value for domain_tot_pages() */ unsigned int extra_pages; /* pages not included in domain_tot_pages() */ diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 28522dcbd271..9e999ac1ba73 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -651,6 +651,7 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd, /* These have individual XSM hooks (common/domctl.c) */ case XEN_DOMCTL_getdomaininfo: + case XEN_DOMCTL_claim_memory: case XEN_DOMCTL_scheduler_op: case XEN_DOMCTL_irq_permission: case XEN_DOMCTL_iomem_permission: diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors index bbb9c117ec4a..e7defa117a16 100644 --- a/xen/xsm/flask/policy/access_vectors +++ b/xen/xsm/flask/policy/access_vectors @@ -216,6 +216,7 @@ class domain2 # XEN_DOMCTL_scheduler_op with XEN_DOMCTL_SCHEDOP_putinfo setscheduler # XENMEM_claim_pages +# XEN_DOMCTL_claim_memory setclaim # XEN_DOMCTL_cacheflush cacheflush -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:30:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:30:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281908.1564684 (Exim 4.92) (envelope-from ) id 1wCdqB-0004iq-0a; Tue, 14 Apr 2026 13:30:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281908.1564684; Tue, 14 Apr 2026 13:30:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdqA-0004ij-U1; Tue, 14 Apr 2026 13:30:06 +0000 Received: by outflank-mailman (input) for mailman id 1281908; Tue, 14 Apr 2026 13:30:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdqA-0004fz-CQ for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:30:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdq8-006u0t-43 for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:30:05 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de4158-5cb7-0a2a0a5109dd-0a2a4503b5fa-38 for ; Tue, 14 Apr 2026 15:30:05 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de415c-02b3-0a2a45030019-a0658309dcde-3 for ; Tue, 14 Apr 2026 15:30:05 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id EFBC181A473F; Tue, 14 Apr 2026 09:29:10 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Christian Lindig , David Scott , Anthony PERARD , Christian Lindig , Andrew Cooper Subject: [PATCH v6 6/7] tools/ocaml/libs/xc: Add an OCaml binding for NUMA-aware claims Date: Tue, 14 Apr 2026 14:22:50 +0100 Message-Id: <284b58e46f6e2cb0df3f404da881f40884df5045.1776172526.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776173405-C9136C9A-31D4E234/0/0 X-purgate-type: clean X-purgate-size: 4737 Add an OCaml binding for xc_domain_claim_memory() so the XEN_DOMCTL_claim_memory hypercall can be used from OCaml. This allows OCaml toolstacks to place NUMA-aware memory claims for domains as well as host-wide claims. tools/ocaml/libs/xc/xenctrl.ml/mli: - Add claim record type and domain_claim_memory external. tools/ocaml/libs/xc/xenctrl_stubs.c: - Validate claim count and arguments. - Marshal the OCaml claim array to memory_claim_t[]. - Map node/target of -1 to XEN_DOMCTL_CLAIM_MEMORY_GLOBAL. Acked-by: Christian Lindig Requested-by: Andrew Cooper Signed-off-by: Bernhard Kaindl --- tools/ocaml/libs/xc/xenctrl.ml | 11 +++++++ tools/ocaml/libs/xc/xenctrl.mli | 11 +++++++ tools/ocaml/libs/xc/xenctrl_stubs.c | 47 +++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/tools/ocaml/libs/xc/xenctrl.ml b/tools/ocaml/libs/xc/xenctrl.ml index 97108b9d861a..680cd8ec5449 100644 --- a/tools/ocaml/libs/xc/xenctrl.ml +++ b/tools/ocaml/libs/xc/xenctrl.ml @@ -370,6 +370,17 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool = "stub_xc_domain_test_assign_device" +(* OCaml binding for xc_domain_claim_memory(): Install claim sets for a domain, + target is either a NUMA node or -1 for no node - memory from any node). *) + +type claim = + { + pages: int64; (* Number of pages to claim *) + target: int32; (* Target: NUMA node ID, or -1 for a flexible claim *) + } +external domain_claim_memory: handle -> domid -> claim array -> unit + = "stub_xc_domain_claim_memory" + external version: handle -> version = "stub_xc_version_version" external version_compile_info: handle -> compile_info = "stub_xc_version_compile_info" diff --git a/tools/ocaml/libs/xc/xenctrl.mli b/tools/ocaml/libs/xc/xenctrl.mli index 9fccb2c2c287..8a7c53a09d97 100644 --- a/tools/ocaml/libs/xc/xenctrl.mli +++ b/tools/ocaml/libs/xc/xenctrl.mli @@ -297,6 +297,17 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool = "stub_xc_domain_test_assign_device" +(* OCaml binding for xc_domain_claim_memory(): Install claim sets for a domain, + target is either a NUMA node or -1 for no node - memory from any node). *) + +type claim = + { + pages: int64; (* Number of pages to claim *) + target: int32; (* Target: NUMA node ID, or -1 for a flexible claim *) + } +external domain_claim_memory: handle -> domid -> claim array -> unit + = "stub_xc_domain_claim_memory" + external version : handle -> version = "stub_xc_version_version" external version_compile_info : handle -> compile_info = "stub_xc_version_compile_info" diff --git a/tools/ocaml/libs/xc/xenctrl_stubs.c b/tools/ocaml/libs/xc/xenctrl_stubs.c index c55f73b265b2..90464f718df0 100644 --- a/tools/ocaml/libs/xc/xenctrl_stubs.c +++ b/tools/ocaml/libs/xc/xenctrl_stubs.c @@ -1435,6 +1435,53 @@ CAMLprim value stub_xc_watchdog(value xch_val, value domid, value timeout) CAMLreturn(Val_int(ret)); } +CAMLprim value stub_xc_domain_claim_memory(value xch_val, value domid, + value claims) +{ + CAMLparam3(xch_val, domid, claims); + xc_interface *xch = xch_of_val(xch_val); + mlsize_t nr_claims = Wosize_val(claims); + memory_claim_t *claim; + uint32_t c_domid = (uint32_t)Int_val(domid); + int retval; + + claim = calloc(nr_claims, sizeof(*claim)); + if (claim == NULL && nr_claims != 0) + caml_raise_out_of_memory(); + + for (mlsize_t i = 0; i < nr_claims; i++) { + value claim_rec = Field(claims, i); + int64_t pages = Int64_val(Field(claim_rec, 0)); + int32_t target = Int32_val(Field(claim_rec, 1)); + uint32_t c_target; + + if (pages < 0 || target < -1 ) { + free(claim); + caml_invalid_argument("domain_claim_memory: invalid pages or node"); + } + + if (target == -1) + c_target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL; + else + c_target = (uint32_t)target; + + claim[i] = (memory_claim_t) { + .pages = (uint64_t)pages, .target = c_target + }; + } + + /* May have to wait for the domctl lock, release the OCaml runtime lock. */ + caml_enter_blocking_section(); + retval = xc_domain_claim_memory(xch, c_domid, nr_claims, claim); + caml_leave_blocking_section(); + + free(claim); + if (retval < 0) + failwith_xc(xch); + + CAMLreturn(Val_unit); +} + /* * Local variables: * indent-tabs-mode: t -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 13:30:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 13:30:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281928.1564694 (Exim 4.92) (envelope-from ) id 1wCdqu-0005IH-7f; Tue, 14 Apr 2026 13:30:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281928.1564694; Tue, 14 Apr 2026 13:30:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdqu-0005IA-4v; Tue, 14 Apr 2026 13:30:52 +0000 Received: by outflank-mailman (input) for mailman id 1281928; Tue, 14 Apr 2026 13:30:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCdqt-0005I1-9X for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 13:30:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCdqs-008zP9-MI for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:30:50 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de4188-5cb7-0a2a0a5109dd-0a2a450be768-16 for ; Tue, 14 Apr 2026 15:30:50 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de4189-bca8-0a2a450b0019-a0658309e2d0-3 for ; Tue, 14 Apr 2026 15:30:50 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 3DCE981A473F; Tue, 14 Apr 2026 09:29:56 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH v6 7/7] tools/tests/mem-claim: Add a test suite for the memory claim API Date: Tue, 14 Apr 2026 14:22:51 +0100 Message-Id: <8604d18c252ce142c2f341e2b0016936d159dd7e.1776172526.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776173450-EF14D101-31FB0BB1/0/0 X-purgate-type: clean X-purgate-size: 78485 Add a comprehensive test suite for the xc_domain_claim_memory() API that covers argument validation and the protection semantics of memory claims across domains and NUMA nodes. The suite verifies claim behaviour both globally and per-node, and checks how claims interact with allocations and replacement semantics. Key checks include: - Argument validation and correct errno handling for invalid inputs. - NUMA-aware claim sets, covering node-specific and global targets. - Replacement semantics after allocations (global and node-scoped). - Inter-domain protection and claim movement across NUMA nodes. Signed-off-by: Bernhard Kaindl --- tools/tests/mem-claim/.gitignore | 1 + tools/tests/mem-claim/Makefile | 17 +- tools/tests/mem-claim/accounting-1.h | 401 +++++++++ tools/tests/mem-claim/input-phase1.h | 171 ++++ tools/tests/mem-claim/input-phase2.h | 91 ++ tools/tests/mem-claim/libtestclaims.c | 995 ++++++++++++++++++++++ tools/tests/mem-claim/libtestclaims.h | 202 +++++ tools/tests/mem-claim/test-claim-memory.c | 129 +++ 8 files changed, 2000 insertions(+), 7 deletions(-) create mode 100644 tools/tests/mem-claim/accounting-1.h create mode 100644 tools/tests/mem-claim/input-phase1.h create mode 100644 tools/tests/mem-claim/input-phase2.h create mode 100644 tools/tests/mem-claim/libtestclaims.c create mode 100644 tools/tests/mem-claim/libtestclaims.h create mode 100644 tools/tests/mem-claim/test-claim-memory.c diff --git a/tools/tests/mem-claim/.gitignore b/tools/tests/mem-claim/.gitignore index cfcee00b819b..08365576b22b 100644 --- a/tools/tests/mem-claim/.gitignore +++ b/tools/tests/mem-claim/.gitignore @@ -1 +1,2 @@ test-mem-claim +test-claim-memory diff --git a/tools/tests/mem-claim/Makefile b/tools/tests/mem-claim/Makefile index 76ba3e3c8bef..77decd4b0d05 100644 --- a/tools/tests/mem-claim/Makefile +++ b/tools/tests/mem-claim/Makefile @@ -1,14 +1,16 @@ XEN_ROOT = $(CURDIR)/../../.. include $(XEN_ROOT)/tools/Rules.mk -TARGET := test-mem-claim +TARGETS := test-mem-claim test-claim-memory + +LIB_OBJ := libtestclaims.o .PHONY: all -all: $(TARGET) +all: $(TARGETS) .PHONY: clean clean: - $(RM) -- *.o $(TARGET) $(DEPS_RM) + $(RM) -- *.o $(TARGETS) $(DEPS_RM) .PHONY: distclean distclean: clean @@ -17,11 +19,11 @@ distclean: clean .PHONY: install install: all $(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests - $(INSTALL_PROG) $(TARGET) $(DESTDIR)$(LIBEXEC)/tests + $(INSTALL_PROG) $(TARGETS) $(DESTDIR)$(LIBEXEC)/tests .PHONY: uninstall uninstall: - $(RM) -- $(DESTDIR)$(LIBEXEC)/tests/$(TARGET) + $(RM) -- $(patsubst %,$(DESTDIR)$(LIBEXEC)/tests/%,$(TARGETS)) CFLAGS += $(CFLAGS_xeninclude) CFLAGS += $(CFLAGS_libxenctrl) @@ -32,7 +34,8 @@ LDFLAGS += $(APPEND_LDFLAGS) %.o: Makefile -$(TARGET): test-mem-claim.o - $(CC) -o $@ $< $(LDFLAGS) + +$(TARGETS): %: %.o $(LIB_OBJ) + $(CC) -o $@ $^ $(LDFLAGS) -include $(DEPS_INCLUDE) diff --git a/tools/tests/mem-claim/accounting-1.h b/tools/tests/mem-claim/accounting-1.h new file mode 100644 index 000000000000..70bae2215702 --- /dev/null +++ b/tools/tests/mem-claim/accounting-1.h @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * claim-memory-allocations.h - Test claiming memory and claims protection + * with NUMA-aware claim sets. + * + * Check claiming memory and allocation against claims with NUMA-aware + * claim sets, including: + * + * - Claiming all or nearly all free memory on a node or globally and + * verifying the claim is reflected in physinfo and that memory can + * be allocated against the claim. + * - Exercise xc_domain_claim_memory() with different valid claim sets. + * - Exercise xc_domain_claim_pages() and verify that claims are reflected + * in the outstanding pages in Xen. + */ +#include "libtestclaims.h" + +/* + * A1-1: basic single-node claim is tracked in outstanding pages and released + * when the domain is destroyed. + * + * Smoke test: claims half the primary node's free pages, verifies they + * appear in physinfo.outstanding_pages, then returns. The fixture destroys + * the domain, which releases the claim, and verifies outstanding pages returns + * to the pre-test baseline. + * + * Skipped when NUMA is disabled (num_nodes == 1 and no per-node free pages) or + * when there are fewer than 2 free pages available on the primary node. + */ +static int test_basic_node_claim(struct test_ctx *ctx) +{ + uint64_t pre_existing_claims, free_pages; + memory_claim_t claim; + + /* Get the free memory on the test node */ + ctx->target1 = ctx->env->primary_node; + lib_get_node_free_pages(ctx, ctx->target1, &free_pages, NULL); + + if ( free_pages < 2 ) + return lib_fail( + ctx, "need >= 2 free pages on node %" PRIu64 ", got %" PRIu64, + ctx->target1, free_pages); + + /* + * Leave one page of slack between the claim and the free pages + * so claim does not fail due to a small concurrent allocation. + */ + ctx->alloc_pages = free_pages - 1; + snprintf(ctx->result->params, sizeof(ctx->result->params), + "node=%" PRIu64 " claim_pages=%" PRIu64 " free_pages=%" PRIu64, + ctx->target1, ctx->alloc_pages, free_pages); + + /* + * Capture the baseline after domain creation (domain creation doesn't + * change outstanding pages, so this equals the fixture's baseline). + */ + rc = lib_get_total_claims(ctx, &pre_existing_claims); + if ( rc ) + return rc; + + claim = (memory_claim_t){.pages = ctx->alloc_pages, .target = ctx->target1}; + rc = lib_claim_memory(ctx, ctx->dom_1, 1, &claim, "set basic node claim"); + if ( rc ) + return rc; + + return lib_check_claim( + ctx, pre_existing_claims, ctx->alloc_pages, + "check node claim is reflected in outstanding pages"); + + /* Domain teardown releases claim; fixture verifies baseline is restored. */ +} + +/* + * A1-2: global claim is replaced atomically after an allocation. + * + * Sets an initial global claim, allocates one extent (consuming part of it), + * then sets a smaller replacement claim and verifies the outstanding count + * reflects the new absolute target. + */ +static int test_global_replace_after_alloc(struct test_ctx *ctx) +{ + unsigned long free_pages; + unsigned long initial_pages; + + /* Get the global free memory for sizing the initial claim */ + lib_get_global_free_pages(ctx, &free_pages); + + if ( free_pages < 2 ) + return lib_fail(ctx, "need >= 2 free pages global, got %" PRIu64, + free_pages); + + /* + * This test needs two valid claim targets: an initial larger claim + * and a smaller replacement target after consuming one claimed page. + */ + initial_pages = free_pages; + ctx->alloc_pages = free_pages / 2; + + snprintf(ctx->result->params, sizeof(ctx->result->params), + "alloc_pages=%" PRIu64 " initial=%" PRIu64 " " + "replacement=%" PRIu64 " global_free=%" PRIu64, + ctx->alloc_pages, initial_pages, ctx->alloc_pages, free_pages); + + rc = lib_claim_memory(ctx, ctx->dom_1, 1, /* one claim */ + &(memory_claim_t){ + .pages = initial_pages, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, + }, + "set initial global replacement claim"); + if ( rc ) + return rc; + + lib_set_step(ctx, "Allocate one extent to consume part of claim"); + rc = lib_populate_success(ctx, (lib_populate_args_t){ + .domid = ctx->dom_1, + .nr_extents = 1, + }); + if ( rc ) + return rc; + + rc = lib_claim_memory(ctx, ctx->dom_1, 1, /* one claim */ + &(memory_claim_t){ + .pages = ctx->alloc_pages, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, + }, + "replace global claim with a new absolute target"); + if ( rc ) + return rc; + + return lib_release_all_claims(ctx, ctx->dom_1); +} + +/* + * A1-3: node-specific claim is replaced atomically after an allocation. + * + * Same as C-1 but scoped to the primary NUMA node: + * Sets an initial node claim, allocates one extent (consuming part of it), + * then sets a smaller replacement claim and verifies the outstanding count + * reflects the new absolute target. + */ +static int test_node_replace_after_alloc(struct test_ctx *ctx) +{ + uint64_t free_pages, initial_pages; + + /* Node used for claim sizing, claiming and allocation */ + ctx->target1 = ctx->env->primary_node; + + /* Get the free memory on the test node for sizing the initial claim */ + lib_get_node_free_pages(ctx, ctx->target1, &free_pages, NULL); + if ( free_pages < 2 ) + return lib_skip_test( + ctx, "need >= 2 pages on node %" PRIu64 ", got %" PRIu64, + ctx->target1, free_pages); + /* + * This test needs two valid claim targets: an initial larger claim + * and a smaller replacement target after consuming one claimed page. + * + * Leave one page of slack between the claim and the free pages + * so claim does not fail due to a small concurrent allocation. + */ + initial_pages = free_pages - 1; + ctx->alloc_pages = free_pages / 2; + + /* Logging of test parameters */ + snprintf(ctx->result->params, sizeof(ctx->result->params), + "node=%" PRIu64 " init=%" PRIu64 " replacement=%" PRIu64 + " free=%" PRIu64, + ctx->target1, initial_pages, ctx->alloc_pages, free_pages); + + /* Create the claim with initial_pages */ + rc = lib_claim_memory(ctx, ctx->dom_1, 1, /* one claim */ + &(memory_claim_t){ + .pages = initial_pages, + .target = ctx->target1, + }, + "set initial node-specific replacement claim"); + if ( rc ) + return rc; + + lib_set_step(ctx, "Allocate one extent to consume part of claim"); + rc = + lib_populate_success(ctx, (lib_populate_args_t){ + .domid = ctx->dom_1, + .nr_extents = 1, + .flags = XENMEMF_exact_node(ctx->target1), + }); + if ( rc ) + return rc; + + /* Update the claim with ctx->alloc_pages */ + rc = lib_claim_memory(ctx, ctx->dom_1, 1, /* one claim */ + &(memory_claim_t){ + .pages = ctx->alloc_pages, + .target = ctx->target1, + }, + "replace node claim with a new absolute target"); + if ( rc ) + return rc; + + return lib_release_all_claims(ctx, ctx->dom_1); +} + +/* + * A1-4: legacy xc_domain_claim_pages() global claim is tracked in outstanding + * pages, reduced by an allocation, and released when the domain is destroyed. + */ +static int test_legacy_global_claim(struct test_ctx *ctx) +{ + uint64_t pre_existing_claims, free_pages; + + /* Get the global free memory for sizing the claim */ + lib_get_global_free_pages(ctx, &free_pages); + + ctx->alloc_pages = free_pages / 2; + snprintf(ctx->result->params, sizeof(ctx->result->params), "claim=%" PRIu64, + ctx->alloc_pages); + + rc = lib_get_total_claims(ctx, &pre_existing_claims); + if ( rc ) + return rc; + + rc = lib_claim_pages_legacy(ctx, ctx->dom_1, ctx->alloc_pages, + "set legacy global claim"); + if ( rc ) + return rc; + + rc = lib_check_claim(ctx, pre_existing_claims, ctx->alloc_pages, + "claim is added the outstanding pages"); + if ( rc ) + return rc; + + lib_set_step(ctx, "allocate extents to redeem a part of claim"); + rc = lib_populate_success(ctx, (lib_populate_args_t){ + .domid = ctx->dom_1, + .nr_extents = 10, + }); + if ( rc ) + return rc; + + return lib_check_claim( + ctx, pre_existing_claims, ctx->alloc_pages - 10, + "allocated against claim, outstanding pages reduced"); + /* Teardown releases the claim; fixture verifies baseline is restored. */ +} + +/* + * A1-5: Test blocking allocation with claims and claim movement between nodes. + * + * This test performs a sequence of claims and allocations to verify that claims + * block allocations on the claimed node, that moving a claim to another node + * allows allocation on the original node, and that the new node is now blocked + * by the claim until it is released. + * + * To achieve this, the test creates a helper domain used for allocation + * attempts, then: + * + * Claims most free pages on the primary node, verifies allocation is blocked, + * then moves the claim to the secondary node, verifies the original allocation + * can now succeed on the primary node. + * + * It then verifies allocation is now blocked on the secondary node, + * releases the claim, and verifies the allocation can now succeed on the + * secondary node as well. + * + * Requires at least two online NUMA nodes. + */ +static int test_move_claim_between_nodes(struct test_ctx *ctx) +{ + uint64_t free_src, free_dst, spare_pages = 10; + + if ( !ctx->env->have_secondary_node ) + return lib_skip_test(ctx, "Requires at least two online NUMA nodes."); + + ctx->target1 = ctx->env->primary_node; + ctx->target2 = ctx->env->secondary_node; + + lib_get_node_free_pages(ctx, ctx->target1, &free_src, NULL); + lib_get_node_free_pages(ctx, ctx->target2, &free_dst, NULL); + + if ( free_src < spare_pages + 1 || free_dst < spare_pages + 1 ) + return lib_fail(ctx, "Need more pages, got %" PRIu64 "/%" PRIu64 ".", + free_src, free_dst); + + lib_set_step(ctx, "Claim most memory on source node."); + rc = lib_claim_all_on_node(ctx, ctx->dom_1, ctx->target1, spare_pages); + if ( rc ) + return rc; + + lib_set_step(ctx, "The claim blocks the allocation on the source node."); + rc = + lib_populate_failure(ctx, (lib_populate_args_t){ + .domid = ctx->dom_2, + .nr_extents = spare_pages * 2, + .flags = XENMEMF_exact_node(ctx->target1), + }); + if ( rc ) + return rc; + + lib_set_step(ctx, "Move the claim to most memory on the destination node."); + rc = lib_claim_all_on_node(ctx, ctx->dom_1, ctx->target2, spare_pages); + if ( rc ) + return rc; + + lib_set_step(ctx, "Moved claim no longer blocks allocs on source node."); + rc = + lib_populate_success(ctx, (lib_populate_args_t){ + .domid = ctx->dom_2, + .start = spare_pages * 2, + .nr_extents = spare_pages * 2, + .flags = XENMEMF_exact_node(ctx->target1), + }); + if ( rc ) + return rc; + + lib_set_step(ctx, "Moved claim now blocks allocs on destination node."); + rc = + lib_populate_failure(ctx, (lib_populate_args_t){ + .domid = ctx->dom_2, + .nr_extents = spare_pages * 2, + .flags = XENMEMF_exact_node(ctx->target2), + }); + if ( rc ) + return rc; + + rc = lib_release_all_claims(ctx, ctx->dom_1); + if ( rc ) + return rc; + + lib_set_step(ctx, "Claim released, allocs on destination node succeed."); + rc = + lib_populate_success(ctx, (lib_populate_args_t){ + .domid = ctx->dom_2, + .start = spare_pages * 2, + .nr_extents = spare_pages * 2, + .flags = XENMEMF_exact_node(ctx->target2), + }); + if ( rc ) + return rc; + + return lib_release_all_claims(ctx, ctx->dom_1); +} + +/* + * A1-6: Check that a calling xc_domain_claim_pages(claim_pages = 0) + * resets the claims to the baseline. + */ +static int test_zero_claim_resets_claim(struct test_ctx *ctx) +{ + uint64_t pre_existing_claims; + + rc = lib_get_total_claims(ctx, &pre_existing_claims); + if ( rc ) + return rc; + + /* Make a claim first to move outstanding away from the baseline. */ + rc = lib_claim_pages_legacy(ctx, ctx->dom_1, 8, + "zero claim to reset outstanding to baseline"); + if ( rc ) + return rc; + + /* Now set a zero claim to reset outstanding back to the baseline. */ + rc = lib_claim_pages_legacy(ctx, ctx->dom_1, 0, + "zero claim to reset outstanding to baseline"); + if ( rc ) + return rc; + + return lib_check_claim(ctx, pre_existing_claims, 0, + "check zero claim resets outstanding to baseline"); +} + +/* + * A1-7: Check that a calling xc_domain_claim_memory(claim_pages = 0) + * resets the claims to the baseline. + */ +static int test_zero_claim_memory_resets(struct test_ctx *ctx) +{ + uint64_t pre_existing_claims; + + rc = lib_get_total_claims(ctx, &pre_existing_claims); + if ( rc ) + return rc; + + /* Make a claim first to move outstanding away from the baseline. */ + rc = lib_claim_memory( + ctx, ctx->dom_1, 1, + &(memory_claim_t){.pages = 8, .target = ctx->env->primary_node}, + "make a claim to move outstanding away from baseline"); + if ( rc ) + return rc; + + /* Now set a zero claim to reset outstanding back to the baseline. */ + rc = lib_claim_memory( + ctx, ctx->dom_1, 1, + &(memory_claim_t){.pages = 0, .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + "set a zero claim to reset outstanding to baseline"); + if ( rc ) + return rc; + + return lib_check_claim(ctx, pre_existing_claims, 0, + "check zero claim resets outstanding to baseline"); +} diff --git a/tools/tests/mem-claim/input-phase1.h b/tools/tests/mem-claim/input-phase1.h new file mode 100644 index 000000000000..5a97bb5eeb20 --- /dev/null +++ b/tools/tests/mem-claim/input-phase1.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * input-phase1.h - Test Phase 1 argument validation for memory claims, + * including invalid claim parameters and claiming more pages than are free. + * + * I1-1 - I1-9: invalid claims are rejected with appropriate error codes. + * + * This file contains test cases to validate argument handling when dealing + * with NUMA-aware claim sets. + * + * Tests various invalid claim parameters (non-present node, too many claims, + * node id above UINT8_MAX, pages above INT32_MAX, non-zero pad, zero claim + * count, null claims pointer with non-zero count, and non-null claims pointer + * with zero count) and verify they are rejected with the expected error code. + */ +#include "libtestclaims.h" + +static int test_reject_non_present_node(struct test_ctx *ctx) +{ + memory_claim_t claim = { + .pages = 1, .target = ctx->env->num_nodes, /* Out-of-range node id */ + }; + + ctx->target1 = ctx->env->primary_node; + snprintf(ctx->result->params, sizeof(ctx->result->params), + "node=%u num_nodes=%u", claim.target, ctx->env->num_nodes); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, &claim, ENOENT, + "reject claim on a non-present NUMA node"); +} + +static int test_reject_too_many_claims(struct test_ctx *ctx) +{ + const uint32_t nr_claims = 0x100; /* Xen does not support such nr_claims */ + memory_claim_t claims[nr_claims]; + + ctx->target1 = ctx->env->primary_node; + for ( uint32_t i = 0; i < nr_claims; i++ ) + claims[i] = ((memory_claim_t){ + .pages = 1, + .target = ctx->env->primary_node, + }); + + snprintf(ctx->result->params, sizeof(ctx->result->params), "nr_claims=%u", + nr_claims); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, nr_claims, claims, E2BIG, + "reject claim list larger than the supported maximum"); +} + +static int test_reject_node_gt_uint8_max(struct test_ctx *ctx) +{ + memory_claim_t claim = { + .pages = 1, + .target = UINT8_MAX + 1U, + }; + + ctx->target1 = ctx->env->primary_node; + snprintf(ctx->result->params, sizeof(ctx->result->params), "node=%u", + claim.target); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, &claim, ENOENT, + "reject claim with node id above UINT8_MAX"); +} + +static int test_reject_pages_gt_int32_max(struct test_ctx *ctx) +{ + memory_claim_t claim = { + .pages = INT32_MAX + 1UL, + .target = ctx->env->primary_node, + }; + + ctx->target1 = ctx->env->primary_node; + snprintf(ctx->result->params, sizeof(ctx->result->params), + "pages=%" PRIu64 " node=%u", claim.pages, claim.target); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, &claim, ENOMEM, + "reject claim with pages larger than INT32_MAX"); +} + +static int test_reject_nonzero_pad(struct test_ctx *ctx) +{ + memory_claim_t claim = { + .pages = 1, + .target = ctx->env->primary_node, + .pad = 1, + }; + + ctx->target1 = ctx->env->primary_node; + snprintf(ctx->result->params, sizeof(ctx->result->params), "node=%u pad=%u", + claim.target, claim.pad); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, &claim, EINVAL, + "reject claim with non-zero padding"); +} + +static int test_reject_zero_claim_count(struct test_ctx *ctx) +{ + snprintf(ctx->result->params, sizeof(ctx->result->params), "nr_claims=0"); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 0, NULL, EINVAL, + "reject xc_domain_claim_memory() with nr_claims == 0"); +} + +static int test_null_claims_nonzero_count(struct test_ctx *ctx) +{ + snprintf(ctx->result->params, sizeof(ctx->result->params), + "nr_claims=1 claims=NULL"); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, NULL, EFAULT, + "reject xc_domain_claim_memory() with claims=NULL and nr_claims == 1"); +} + +static int test_zero_count_valid_pointer(struct test_ctx *ctx) +{ + memory_claim_t claim = { + .pages = 1, + .target = ctx->env->primary_node, + }; + + snprintf(ctx->result->params, sizeof(ctx->result->params), + "nr_claims=0 claims=valid node=%u", claim.target); + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 0, &claim, EINVAL, + "reject xc_domain_claim_memory() with !nr_claims but a claims pointer"); +} + +/* + * I1-9: Check both xc_domain_claim_pages() and xc_domain_claim_memory() + * with pages > free pages fail with ENOMEM. + */ +static int test_claim_pages_gt_free_enomem(struct test_ctx *ctx) +{ + uint64_t free_pages; + + /* Get the global free memory for sizing the claim */ + lib_get_global_free_pages(ctx, &free_pages); + ctx->alloc_pages = free_pages + 1; + + snprintf(ctx->result->params, sizeof(ctx->result->params), + "claim=%" PRIu64 " global=%" PRIu64, ctx->alloc_pages, free_pages); + + rc = lib_claim_pages_legacy_failure( + ctx, ctx->dom_1, ctx->alloc_pages, ENOMEM, + "reject xc_domain_claim_pages() with pages > global free page"); + if ( rc ) + return rc; + + rc = lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, + &(memory_claim_t){.pages = ctx->alloc_pages, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + ENOMEM, "reject claim_memory() with pages > global free pages"); + + /* Get the free pages on the primary node and fail to claim more than it */ + lib_get_node_free_pages(ctx, ctx->env->primary_node, &free_pages, NULL); + rc = lib_expect_claim_memory_failure( + ctx, ctx->dom_1, 1, + &(memory_claim_t){.pages = free_pages + 1, + .target = ctx->env->primary_node}, + ENOMEM, "reject claim_memory() with pages > node free pages"); + return rc; +} diff --git a/tools/tests/mem-claim/input-phase2.h b/tools/tests/mem-claim/input-phase2.h new file mode 100644 index 000000000000..d57a7e8a37c0 --- /dev/null +++ b/tools/tests/mem-claim/input-phase2.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * input-phase2.h - Test argument validation for memory claims + * + * This file contains test cases to validate argument handling when dealing + * with NUMA-aware claim sets. + */ +#include "libtestclaims.h" + +static int d2_claim_expect_enomem_global(struct test_ctx *ctx, uint64_t claims) +{ + rc = lib_claim_pages_legacy_failure( + ctx, ctx->dom_2, claims, ENOMEM, + "expect ENOMEM for xc_domain_claim_pages() with claims > spare page"); + if ( rc ) + return rc; + + return lib_expect_claim_memory_failure( + ctx, ctx->dom_2, 1, + /* Request more than the spare to ensure failure */ + &(memory_claim_t){.pages = claims, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + ENOMEM, "expect ENOMEM for claim_memory() with claims > spare pages"); +} + +static int d2_claim_expect_enomem_node(struct test_ctx *ctx, uint64_t claims) +{ + return lib_expect_claim_memory_failure( + ctx, ctx->dom_2, 1, + /* Request more than the spare to ensure failure */ + &(memory_claim_t){.pages = claims, .target = ctx->target1}, ENOMEM, + "expect ENOMEM for claim_memory() with claims > spare pages"); +} + +/* + * I2-1 + * + * Create a legacy global claim for d1 using claim_pages and assert that + * claim calls for d2 that exceed the unclaimed memory fail with ENOMEM. + */ +static int test_claim_pages_causes_enomem(struct test_ctx *ctx) +{ + uint64_t free_pages; + + /* Get the global free memory for sizing the claim */ + lib_get_global_free_pages(ctx, &free_pages); + ctx->alloc_pages = free_pages - SPARE_PAGES; + + snprintf(ctx->result->params, sizeof(ctx->result->params), + "claim=%" PRIu64 " global=%" PRIu64, ctx->alloc_pages, free_pages); + + rc = lib_claim_pages_legacy( + ctx, ctx->dom_1, ctx->alloc_pages, + "dom_1: claim nearly all global memory with claim_pages"); + if ( rc ) + return rc; + + rc = d2_claim_expect_enomem_global(ctx, SPARE_PAGES * 2); + if ( !rc ) + rc = d2_claim_expect_enomem_node(ctx, SPARE_PAGES * 2); + return rc; +} + +/* + * I2-2 + * + * Create a global claim for d1 using claim_memory and assert that + * claim calls for d2 that exceed the unclaimed memory fail with ENOMEM. + */ +static int test_claim_memory_causes_enomem(struct test_ctx *ctx) +{ + if ( lib_claim_all_on_host(ctx, ctx->dom_1, SPARE_PAGES) ) + return -1; + rc = d2_claim_expect_enomem_global(ctx, SPARE_PAGES * 2); + if ( !rc ) + rc = d2_claim_expect_enomem_node(ctx, SPARE_PAGES * 2); + return rc; +} + +/* + * I2-3 + * + * Create a primary-node claim for d1 using claim_memory and assert that + * claim calls for d2 that exceed the unclaimed memory fail with ENOMEM. + */ +static int test_claim_prima_causes_enomem(struct test_ctx *ctx) +{ + if ( lib_claim_all_on_node(ctx, ctx->dom_1, ctx->target1, SPARE_PAGES) ) + return -1; + return d2_claim_expect_enomem_node(ctx, SPARE_PAGES * 2); +} diff --git a/tools/tests/mem-claim/libtestclaims.c b/tools/tests/mem-claim/libtestclaims.c new file mode 100644 index 000000000000..c4c1a63e1856 --- /dev/null +++ b/tools/tests/mem-claim/libtestclaims.c @@ -0,0 +1,995 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Functional system test framework for testing memory claims in Xen. + * + * See test-claim-memory.c for details on a test suite using this framework + * and the verifications it is designed to perform on behalf of a test suite. + * + * Besides providing the test suite with functionality to validate the + * effects of memory claims on the system, such as querying memory state, + * creating and destroying test domains, performing claim operations and + * populating memory, it also provides a consistent way to manage test + * state and record failures with detailed messages that include the + * current step, test parameters, and a snapshot of relevant memory + * state to aid in diagnosing issues when a test fails. + * + * It also provides the framework to select test cases, run them, and + * restore the system to a clean state after tests by destroying test + * domains to release populated memory and claims, even if a test fails + * partway through. + * + * The functions cover: + * + * - Managing the test_ctx structure which holds the test environment, + * configuration, and results. + * + * - Providing helper functions to: + * - Create and destroy domains for testing, which are needed to make claims + * - Query the system's memory state in terms of free pages and outstanding + * claims, which are used for sizing claims and verifying their effects. + * - Perform claim operations and check their effects on the system. + * - Populate memory to test the blocking effects of claims. + * - Record failures with detailed messages that include the current step, + * test parameters, and a snapshot of relevant memory state. + * + * - Cleanup the test environment by destroying domains after tests, ensuring + * that claims are released and the system is left in a clean state even + * if a test fails partway through. + * + * - Providing a consistent way to skip tests when preconditions are not met, + * such as insufficient free memory or lack of multiple NUMA nodes. + * + * - Ensuring that all interactions with Xen are checked for errors, and that + * any failures are reported with detailed diagnostics. + * + * - Test cases should use the provided helper functions to perform all + * operations that interact with Xen or manage test state to ensure + * consistent failure reporting and cleanup. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "libtestclaims.h" + +int rc; +static int step; +static const struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"list", no_argument, NULL, 'l'}, + {"test", required_argument, NULL, 't'}, + {"verbose", no_argument, NULL, 'v'}, + {NULL, 0, NULL, 0 }, +}; + +/* --- diagnostics helpers --- */ + +/* Append formatted text to a buffer, ensuring it is always null-terminated. */ +void lib_appendf(char *buf, size_t size, const char *fmt, ...) +{ + va_list ap; + size_t used = strlen(buf); + + if ( used >= size ) + return; + + va_start(ap, fmt); + vsnprintf(buf + used, size - used, fmt, ap); + va_end(ap); +} + +/* Print debug information if verbose mode is enabled. */ +void lib_debugf(struct test_ctx *ctx, const char *fmt, ...) +{ + va_list ap; + + if ( !ctx->cfg->verbose ) + return; + + fputs(" debug: ", stdout); + + va_start(ap, fmt); + vprintf(fmt, ap); + va_end(ap); + + fputc('\n', stdout); +} + +/* + * Set the current test step description, which is included in failure reports. + * If verbose mode is enabled, also print the step to stdout. + */ +void lib_set_step(struct test_ctx *ctx, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + vsnprintf(ctx->step, sizeof(ctx->step), fmt, ap); + va_end(ap); + + if ( ctx->cfg->verbose ) + printf(" step %d: %s\n", ++step, ctx->step); +} + +/* + * Record a test failure with a formatted message and errno, and include the + * current step, test parameters, and a snapshot of relevant memory state in + * the details. + */ +static void append_snapshot(struct test_ctx *ctx) +{ + xc_physinfo_t physinfo; + unsigned int nodes[2] = {ctx->target1, ctx->target2}; + + xc_physinfo(ctx->env->xch, &physinfo); + ctx_appendf(ctx, + "\n snapshot: free_pages=%" PRIu64 + ", outstanding_pages=%" PRIu64, + physinfo.free_pages, physinfo.outstanding_pages); + + /* Include their free/total pages at the time of failure in the snapshot. */ + for ( size_t i = 0; i < ARRAY_SIZE(nodes); i++ ) + { + unsigned long free_pages, total_pages; + unsigned int node = nodes[i]; + + if ( node == INVALID_NODE ) + continue; + if ( i == 1 && node == nodes[0] ) + continue; + + lib_get_node_free_pages(ctx, node, &free_pages, &total_pages); + ctx_appendf(ctx, "\n snapshot: node%u free=%lu total=%lu", node, + free_pages, total_pages); + } +} + +/* + * Record a test failure with a formatted message and the given errno. + * + * Include the current step, test parameters, and a snapshot of relevant + * memory state in the details. + */ +int lib_fail_with_errno(struct test_ctx *ctx, int errnum, const char *fmt, ...) +{ + va_list ap; + + ctx->result->status = TEST_FAILED; + ctx->result->details[0] = '\0'; + + ctx_appendf(ctx, "step=%s", ctx->step[0] ? ctx->step : "(not set)"); + ctx_appendf(ctx, "\n dom_1=%u dom_2=%u target1=%s target2=%s", + ctx->dom_1, ctx->dom_2, + ctx->target1 == INVALID_NODE ? "n/a" : "set", + ctx->target2 == INVALID_NODE ? "n/a" : "set"); + + if ( ctx->target1 != INVALID_NODE ) + ctx_appendf(ctx, " (%" PRIu64 ")", ctx->target1); + if ( ctx->target2 != INVALID_NODE ) + ctx_appendf(ctx, " (%" PRIu64 ")", ctx->target2); + + ctx_appendf(ctx, "\n alloc_pages=%lu", ctx->alloc_pages); + + ctx_appendf(ctx, "\n cause: "); + va_start(ap, fmt); + vsnprintf(ctx->result->details + strlen(ctx->result->details), + sizeof(ctx->result->details) - strlen(ctx->result->details), fmt, + ap); + va_end(ap); + + if ( errnum ) + ctx_appendf(ctx, "\n errno=%d (%s)", errnum, strerror(errnum)); + + append_snapshot(ctx); + return -1; +} + +/* + * Record a test failure with a formatted message and the current errno. + * + * Calls lib_fail_with_errno() to do the actual recording, passing the current + * errno. + */ +int lib_fail(struct test_ctx *ctx, const char *fmt, ...) +{ + va_list ap; + int saved_errno = errno; + char message[1024]; + + va_start(ap, fmt); + vsnprintf(message, sizeof(message), fmt, ap); + va_end(ap); + + return lib_fail_with_errno(ctx, saved_errno, "%s", message); +} + +/* + * Record that a test was skipped with a formatted message. + * + * Include the message in the details to explain why the test was skipped. + */ +int lib_skip_test(struct test_ctx *ctx, const char *fmt, ...) +{ + va_list ap; + + ctx->result->status = TEST_SKIPPED; + ctx->result->details[0] = '\0'; + + va_start(ap, fmt); + vsnprintf(ctx->result->details, sizeof(ctx->result->details), fmt, ap); + va_end(ap); + + return 1; +} + +/* --- memory-state queries --- */ + +/* Get the number of free and total pages for a specific NUMA node. */ +int lib_get_node_free_pages(struct test_ctx *ctx, unsigned int node, + uint64_t *free_pages, uint64_t *total_pages) +{ + struct test_env *env = ctx->env; + + if ( node >= env->num_nodes ) /* Check node validity */ + return lib_fail(ctx, "Invalid node %u/%u", node, env->num_nodes); + + if ( xc_numainfo(env->xch, &env->num_nodes, env->meminfo, NULL) ) + return lib_fail(ctx, "xc_numainfo failed to get node memory info"); + + *free_pages = env->meminfo[node].memfree / XC_PAGE_SIZE; + if ( total_pages ) + *total_pages = env->meminfo[node].memsize / XC_PAGE_SIZE; + return 0; +} + +/* Get the total number of free pages available across all nodes. */ +int lib_get_global_free_pages(struct test_ctx *ctx, uint64_t *free_pages) +{ + struct test_env *env = ctx->env; + uint64_t free_bytes; + + if ( xc_availheap(env->xch, 0, 0, -1, &free_bytes) ) + return lib_fail(ctx, "xc_availheap failed to get global pages"); + + *free_pages = free_bytes / XC_PAGE_SIZE; + return 0; +} + +/* Get the current number of outstanding pages. */ +int lib_get_total_claims(struct test_ctx *ctx, + uint64_t *outstanding_pages_global) +{ + xc_physinfo_t physinfo; + + if ( xc_physinfo(ctx->env->xch, &physinfo) ) + return lib_fail(ctx, "xc_physinfo failed to get outstanding pages"); + *outstanding_pages_global = physinfo.outstanding_pages; + return 0; +} + +/* --- claim check operations --- */ + +/* Check the current outstanding pages against the expected value. */ +int lib_check_claim(struct test_ctx *ctx, uint64_t baseline_outstanding, + uint64_t expected_delta, const char *reason) +{ + xc_physinfo_t physinfo; + uint64_t expected = baseline_outstanding + expected_delta; + + lib_set_step(ctx, "%s", reason); + if ( xc_physinfo(ctx->env->xch, &physinfo) ) + return lib_fail(ctx, "xc_physinfo failed to get outstanding pages"); + + if ( physinfo.outstanding_pages != expected ) + return lib_fail_with_errno( + ctx, 0, "expected outstanding_pages=%" PRIu64 ", got %" PRIu64, + expected, physinfo.outstanding_pages); + return 0; +} + +/* --- domain lifecycle --- */ + +/* + * Create a domain with the specified configuration and label. + * Record a failure if the creation or maxmem setting fails. + * + * On success, the new domain ID is stored in *domid. + */ +int lib_create_domain(struct test_ctx *ctx, uint32_t *domid, const char *label) +{ + struct xen_domctl_createdomain create = ctx->env->create_template; + + lib_set_step(ctx, "create %s domain", label); + *domid = DOMID_INVALID; + if ( xc_domain_create(ctx->env->xch, domid, &create) ) + return lib_fail(ctx, "xc_domain_create(%s) failed", label); + + lib_set_step(ctx, "set maxmem for %s domain", label); + if ( xc_domain_setmaxmem(ctx->env->xch, *domid, -1) ) + { + lib_destroy_domain(ctx, domid, label); + return lib_fail(ctx, "xc_domain_setmaxmem(%s) failed", label); + } + + return 0; +} + +/* + * Destroy the specified domain, if it is valid. + * Add the destroy step with the given label to the current test description. + * Record a failure if the destroy operation fails. + * + * This should be called during test cleanup to ensure domains are destroyed + * and claims are released even if a test fails partway through. + */ +int lib_destroy_domain(struct test_ctx *ctx, uint32_t *domid, const char *label) +{ + if ( *domid == DOMID_INVALID ) + return 0; + + lib_set_step(ctx, "destroy %s domain", label); + rc = xc_domain_destroy(ctx->env->xch, *domid); + *domid = DOMID_INVALID; + if ( rc ) + { + if ( ctx->result->status == TEST_FAILED ) + { + ctx_appendf(ctx, + "\n cleanup: xc_domain_destroy(%s) failed: %d (%s)", + label, errno, strerror(errno)); + return -1; + } + + return lib_fail(ctx, "xc_domain_destroy(%s) failed", label); + } + + return 0; +} + +/* --- claim operations --- */ + +/* + * Attempt to claim memory with the specified parameters. + * Record the failure if the claim operation fails. + */ +int lib_claim_memory(struct test_ctx *ctx, uint32_t domid, uint32_t nr_claims, + memory_claim_t *claims, const char *reason) +{ + lib_set_step(ctx, "%s", reason); + rc = xc_domain_claim_memory(ctx->env->xch, domid, nr_claims, claims); + if ( rc ) + { + uint64_t outstanding_pages, node_free, total_pages; + + lib_get_node_free_pages(ctx, ctx->target1, &node_free, &total_pages); + lib_get_total_claims(ctx, &outstanding_pages); + + return lib_fail(ctx, + "xc_domain_claim_memory failed: node=%" PRIu64 + "\n total_outstanding: %" PRIu64 + "\n total_pages: %" PRIu64 + "\n node free_pages: %" PRIu64, + ctx->target1, outstanding_pages, total_pages, + node_free); + } + return rc; +} + +/* + * Attempt to claim memory with the specified parameters, expecting it to fail + * with the specified errno. Record a failure if it does not fail as expected. + */ +int lib_expect_claim_memory_failure(struct test_ctx *ctx, uint32_t domid, + uint32_t nr_claims, memory_claim_t *claims, + int expected_errno, const char *reason) +{ + lib_set_step(ctx, "%s", reason); + rc = xc_domain_claim_memory(ctx->env->xch, domid, nr_claims, claims); + if ( rc == -1 && errno == expected_errno ) + return 0; + + return lib_fail_with_errno(ctx, errno, + "expected xc_domain_claim_memory() to fail with " + "errno=%d (%s), got rc=%d", + expected_errno, strerror(expected_errno), rc); +} + +/* + * Release all claims for the specified domain by setting a global claim with + * zero pages. Record the failure if the claim release operation fails. + */ +int lib_release_all_claims(struct test_ctx *ctx, uint32_t domid) +{ + memory_claim_t claim = { + .pages = 0, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, + }; + + lib_set_step(ctx, "release all claims with global zero claim"); + rc = xc_domain_claim_memory(ctx->env->xch, domid, 1, &claim); + if ( rc ) + return lib_fail(ctx, "xc_domain_claim_memory(..., global=0) failed"); + return 0; +} + +/* + * Claim all available memory on the host except for a specified number + * of pages to spare. Record the failure if the claim operation fails. + */ +int lib_claim_all_on_host(struct test_ctx *ctx, uint32_t domid, + unsigned int spare) +{ + unsigned long free_pages; + unsigned long claim_pages = 0; + + lib_set_step(ctx, "claim all except %u pages on host", spare); + lib_get_global_free_pages(ctx, &free_pages); + if ( free_pages <= spare ) + return lib_fail(ctx, "Not enough free pages @ host, spare=%u, free=%lu", + spare, free_pages); + + claim_pages += free_pages - spare; + snprintf(ctx->result->params, sizeof(ctx->result->params), + "claim all pages except %u pages on host claim=%lu free=%lu", + spare, claim_pages, free_pages); + return lib_claim_memory( + ctx, domid, 1, + &(memory_claim_t){.pages = claim_pages, + .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL}, + ctx->result->params); +} + +/* + * Claim all available memory on the specified node except for a specified + * number of pages to spare. Record the failure if the claim operation fails. + * + * This is used to set up a claim that exhausts the free memory on a specific + * node, which is needed to test the behavior of claims that target specific + * nodes and the global claim accounting that tracks them. The spare pages are + * needed to ensure that the claim can be successfully installed and leave some + * free pages on the node leave a little breathing room for other allocations + * and not cause the test to fail because of a minor fluctuation in free memory + * that causes unexpected differences in the expected vs actual page counts. + * + * This function also checks that the delta of global outstanding claims before + * and after the claim matches the expected delta based on the number of pages + * claimed, accounting for any existing claims the domain had before making the + * claim, since these existing claims are already part of the global outstanding + * claims, so we need to account for them in the expected delta when we check + * the global delta after the claim. + * + * It also checks that the domain's outstanding claims after the claim matches + * the number of pages claimed, ensuring that the claim was correctly installed. + */ +int lib_claim_all_on_node(struct test_ctx *ctx, uint32_t domid, + unsigned int node, unsigned int spare) +{ + uint64_t global_before, global_after, free_pages, claim_pages = 0; + uint64_t dom_claims_before; + xc_domaininfo_t info; + + lib_set_step(ctx, "claim all except %u pages on node %u", spare, node); + lib_get_node_free_pages(ctx, node, &free_pages, NULL); + if ( free_pages <= spare ) + return lib_fail(ctx, "Not enough pages @ node %u, spare=%u, free=%lu", + node, spare, free_pages); + + claim_pages += free_pages - spare; + snprintf(ctx->result->params, sizeof(ctx->result->params), + "claim all pages except %u pages on node %u claim=%lu free=%lu", + spare, node, claim_pages, free_pages); + + /* + * Get the domain's outstanding claims before making the claim to check the + * delta after the claim: If the domain had existing claims, these claims + * are already part of the global outstanding claims, so we need to account + * for them when we check the global delta after the claim to ensure it + * matches the expected delta. + */ + if ( xc_domain_getinfo_single(ctx->env->xch, domid, &info) ) + return lib_fail(ctx, "xc_domain_getinfo failed to get domain claims"); + dom_claims_before = info.outstanding_pages; + + /* + * Get the global outstanding claims before making the claim to check the + * delta after the claim. + */ + lib_get_total_claims(ctx, &global_before); + rc = lib_claim_memory( + ctx, domid, 1, &(memory_claim_t){.pages = claim_pages, .target = node}, + ctx->result->params); + if ( rc ) + return rc; + lib_get_total_claims(ctx, &global_after); + + if ( xc_domain_getinfo_single(ctx->env->xch, domid, &info) ) + return lib_fail(ctx, "xc_domain_getinfo failed to get domain claims"); + + if ( info.outstanding_pages != claim_pages ) + return lib_fail(ctx, "unexpected claims installation: exp=%lu, got=%lu", + claim_pages, info.outstanding_pages); + + if ( global_after - global_before != claim_pages - dom_claims_before ) + return lib_fail(ctx, "unexp. global delta @ node %u: exp=%lu, got=%lu", + node, claim_pages, global_before - global_after); + return 0; +} + +/* + * Attempt to claim memory with the legacy xc_domain_claim_pages() API. + * Record the failure if the claim operation fails. + */ +int lib_claim_pages_legacy(struct test_ctx *ctx, uint32_t domid, + unsigned long nr_pages, const char *reason) +{ + lib_set_step(ctx, "%s", reason); + rc = xc_domain_claim_pages(ctx->env->xch, domid, nr_pages); + if ( rc ) + return lib_fail(ctx, "xc_domain_claim_pages(%lu) failed", nr_pages); + return 0; +} + +/* + * Attempt to claim memory with the legacy xc_domain_claim_pages() API. + * Expect it to fail with the specified errno. + * Record a failure on success or if it fails with an unexpected errno. + */ +int lib_claim_pages_legacy_failure(struct test_ctx *ctx, uint32_t domid, + unsigned long request, int expected_errno, + const char *reason) +{ + uint64_t outstanding_claims, free_pages; + + /* + * Sanity check: Check that there are not enough free pages for installing + * the claim, as this is the only condition under which the claim install + * is expected to fail with ENOMEM. If this fails, the previous actions + * of the test did not properly set up the expected conditions for the + * claim to fail, so we record this as the cause of failure. + */ + lib_get_total_claims(ctx, &outstanding_claims); + lib_get_global_free_pages(ctx, &free_pages); + if ( request < free_pages - outstanding_claims ) + return lib_fail(ctx, + "too many unclaimed pages to expect ENOMEM: " + "request=%lu, free=%" PRIu64 " - claims=%" PRIu64 + "=%" PRIu64, + request, free_pages, outstanding_claims, + free_pages - outstanding_claims); + lib_set_step(ctx, "%s", reason); + rc = xc_domain_claim_pages(ctx->env->xch, domid, request); + if ( rc == -1 && errno == expected_errno ) + return 0; + + return lib_fail_with_errno(ctx, errno, + "expected xc_domain_claim_pages() to fail " + "with errno=%d(%s), got rc=%d", + expected_errno, strerror(expected_errno), rc); +} + +/* --- physmap population --- */ + +/* + * Private helper function to populate extents at the specified GPFN + * with the xc_domain_populate_physmap() API, and return the result code. + * + * Tests may use its callers lib_populate_success() or lib_populate_failure() + * which record the failure the actual result did not match the expectation. + */ +static int lib_populate_physmap(struct test_ctx *ctx, lib_populate_args_t args) +{ + xen_pfn_t *frames; + + frames = calloc(args.nr_extents, sizeof(*frames)); + if ( !frames ) + return lib_fail(ctx, "calloc(%lu) failed", args.nr_extents); + + for ( unsigned long i = 0; i < args.nr_extents; i++ ) + frames[i] = args.start + i; + + errno = 0; + rc = xc_domain_populate_physmap_exact(ctx->env->xch, args.domid, + args.nr_extents, args.order, + args.flags, frames); + free(frames); + return rc; +} + +/* + * Populate extents at the specified GPFN with checking if it + * succeeded. Record the failure with diagnostics if it did not. + */ +int lib_populate_success(struct test_ctx *ctx, lib_populate_args_t args) +{ + rc = lib_populate_physmap(ctx, args); + if ( rc ) + return lib_fail(ctx, "expected populate to succeed for node %u", + XENMEMF_get_node(args.flags)); + return 0; +} + +/* + * Attempt to populate extents at the specified GPFN with checking if it + * failed. Record a failure with diagnostics if it did not fail as expected. + */ +int lib_populate_failure(struct test_ctx *ctx, lib_populate_args_t args) +{ + rc = lib_populate_physmap(ctx, args); + if ( rc == 0 ) + return lib_fail_with_errno( + ctx, 0, "expected exact-node populate to fail for node %u", + XENMEMF_get_node(args.flags)); + return 0; +} + +/* --- test runner --- */ + +static double timespec_diff_ms(const struct timespec *start, + const struct timespec *end) +{ + double sec = (double)(end->tv_sec - start->tv_sec); + double nsec = (double)(end->tv_nsec - start->tv_nsec); + + return sec * 1000.0 + nsec / 1e6; +} + +static void usage(FILE *stream, const char *prog) +{ + fprintf(stream, + "Usage: %s [OPTIONS]\n\n" + "Options:\n" + " -l, --list List available test IDs and exit\n" + " -t, --test ID Run only the specified test ID (repeatable)\n" + " -v, --verbose Print per-step progress\n" + " -h, --help Show this help text\n", + prog); +} + +int lib_print_available_tests(const struct test_case *cases, size_t num_cases) +{ + puts("Available tests:"); + for ( size_t i = 0; i < num_cases; i++ ) + printf(" %s %s\n", cases[i].id, cases[i].name); + return 0; +} + +/* + * Parse command-line arguments to configure the test run. + * It populates the runtime_config struct with the parsed configuration, + * including test IDs and the verbose flag. + * + * It supports filtering tests by test ID and enabling verbose output. + * If --list is specified, prints available tests and exits. + * By default, all tests will be run with concise output. + * If cfg.list_only is set, the caller should exit after this function returns. + * + * Returns 0 on success, or 1 on failure (invalid arguments) + */ +int lib_parse_args(int argc, char *argv[], struct runtime_config *cfg) +{ + int opt; + + while ( (opt = getopt_long(argc, argv, "hlt:v", long_options, NULL)) != -1 ) + { + switch ( opt ) + { + case 'h': + usage(stdout, argv[0]); + case 'l': + cfg->list_only = true; + break; + + case 't': + if ( cfg->nr_selected_ids >= ARRAY_SIZE(cfg->selected_ids) ) + errx(1, "too many --test selectors (max %zu)", + ARRAY_SIZE(cfg->selected_ids)); + cfg->selected_ids[cfg->nr_selected_ids++] = optarg; + break; + + case 'v': + cfg->verbose = true; + break; + + default: + usage(stderr, argv[0]); + return 1; + } + } + + if ( cfg->list_only ) + return 0; + + printf("========= testcase program: %s ==========\n", argv[0]); + if ( cfg->nr_selected_ids ) + { + printf("Selected %zu test(s):\n", cfg->nr_selected_ids); + for ( size_t i = 0; i < cfg->nr_selected_ids; i++ ) + printf(" %s\n", cfg->selected_ids[i]); + } + return 0; +} + +/* + * Run a single test case, capturing results and ensuring cleanup. + * + * Outstanding claims are tracked baseline_outstanding are are checked + * to be reset to the baseline at the end of the test, ensuring that all + * claims are released after each test case. + * + * Returns 0 on success, or -1 on failure with result details populated. + */ +int lib_run_one_test(struct test_env *env, const struct runtime_config *cfg, + const struct test_case *test, struct test_result *result) +{ + struct test_ctx ctx = { + .env = env, + .cfg = cfg, + .result = result, + .dom_1 = DOMID_INVALID, + .dom_2 = DOMID_INVALID, + .target1 = env->primary_node, + .target2 = INVALID_NODE, + .alloc_pages = 0, + .step = "", + }; + uint64_t baseline_outstanding; + struct timespec start, end; + + if ( env->num_nodes >= 2 ) + ctx.target2 = env->secondary_node; + + result->test = test; + result->status = TEST_PASSED; + result->params[0] = '\0'; + result->details[0] = '\0'; + result->duration_ms = 0.0; + + /* + * Fixture: capture baseline, create the primary domain, run the test + * body, then always destroy any remaining test domains and verify + * outstanding pages returned to baseline. + */ + rc = lib_get_total_claims(&ctx, &baseline_outstanding); + if ( rc ) + goto out; + + rc = lib_create_domain(&ctx, &ctx.dom_1, "primary"); + if ( rc ) + goto out; + + rc = lib_create_domain(&ctx, &ctx.dom_2, "secondary"); + if ( rc ) + goto out; + + clock_gettime(CLOCK_MONOTONIC, &start); + + errno = 0; + rc = test->test(&ctx); /* Run the test body */ + + clock_gettime(CLOCK_MONOTONIC, &end); + result->duration_ms = timespec_diff_ms(&start, &end); + + if ( rc > 0 && result->status == TEST_SKIPPED ) + rc = 0; + +out: + /* Cleanup test domains without affecting the return code if rc != 0 */ + if ( lib_destroy_domain(&ctx, &ctx.dom_2, "helper") && !rc ) + rc = -1; + + if ( lib_destroy_domain(&ctx, &ctx.dom_1, "primary") && !rc ) + rc = -1; + + if ( !rc && + lib_check_claim(&ctx, baseline_outstanding, 0, + "check cleanup restored baseline claimed pages") ) + rc = -1; + + if ( rc < 0 ) + result->status = TEST_FAILED; + + return rc; +} + +/* + * Run all test cases, filtering based on the runtime configuration, and print + * results to stdout. Each test case is run with lib_run_one_test() which + * captures detailed diagnostics on failure. + */ +void lib_run_tests(struct test_env *env, char *argv0, + const struct runtime_config *cfg, + const struct test_case *test_cases, + unsigned int num_test_cases, struct test_result *results) +{ + for ( size_t i = 0; i < num_test_cases; i++ ) + { + struct test_result *result = &results[i]; + + if ( !test_is_selected(cfg, &test_cases[i]) ) + continue; + + lib_run_one_test(env, cfg, &test_cases[i], result); + + /* Print a summary: test, result, including parameters and duration. */ + printf("%s::%s [%s] %s (%.2f ms)\n", argv0, result->test->id, + result->params[0] ? result->params : "default", + status_name(result->status), result->duration_ms); + + if ( result->status == TEST_FAILED || result->status == TEST_SKIPPED ) + printf(" %s\n", result->details); + } +} + +/* + * Print a concise summary of test results, including counts of passed, failed, + * and skipped tests, and details for any failures or skips. + */ +int lib_summary(const struct test_result *results, unsigned int num_results) +{ + unsigned int passed = 0, failed = 0, skipped = 0; + + puts("================== short test summary info ================="); + for ( size_t i = 0; i < num_results; i++ ) + { + if ( !results[i].test ) + continue; + + printf("%s %s %s\n", status_name(results[i].status), + results[i].test->id, results[i].test->name); + + switch ( results[i].status ) + { + case TEST_PASSED: + passed++; + break; + case TEST_FAILED: + failed++; + printf(" %s\n", results[i].details); + break; + case TEST_SKIPPED: + skipped++; + printf(" %s\n", results[i].details); + break; + } + } + printf("============ %u passed, %u failed, %u skipped ============\n", + passed, failed, skipped); + return failed; +} + +/* Update the create_template structure based on the host's capabilities */ +static void fixup_create_template(struct xen_domctl_createdomain *create, + const xc_physinfo_t *physinfo) +{ +#if defined(__x86_64__) || defined(__i386__) + if ( !(physinfo->capabilities & XEN_SYSCTL_PHYSCAP_hap) ) + create->flags &= ~XEN_DOMCTL_CDF_hap; + + if ( !(physinfo->capabilities & + (XEN_SYSCTL_PHYSCAP_hap | XEN_SYSCTL_PHYSCAP_shadow)) || + !(physinfo->capabilities & XEN_SYSCTL_PHYSCAP_hvm) ) + { + create->flags &= ~XEN_DOMCTL_CDF_hvm; + create->arch.emulation_flags = 0; + } +#else + (void)physinfo; +#endif +} + +/* + * Initialise the test environment by opening the Xen control interface, + * querying the number of NUMA nodes, and populating memory information. + * Returns 0 on success, or -1 on failure with errno set. + */ +int lib_initialise_test_env(struct test_env *env) +{ + xc_physinfo_t physinfo; + + env->xch = xc_interface_open(NULL, NULL, 0); + if ( !env->xch ) + err(1, "xc_interface_open"); + + /* + * Get the number of nodes to allocate xc_meminfo_t structures for. + * If NUMA is disabled, this will return one node, so we can still + * run tests that don't require > 1 NUMA node on non-NUMA hosts. + */ + xc_numainfo(env->xch, &env->num_nodes, NULL, NULL); + + /* Allocate memory for xc_meminfo_t structures */ + env->meminfo = calloc(env->num_nodes, sizeof(*env->meminfo)); + if ( !env->meminfo ) + err(1, "calloc"); + + /* Populate meminfo structures with current data */ + xc_numainfo(env->xch, &env->num_nodes, env->meminfo, NULL); + xc_physinfo(env->xch, &physinfo); + + /* Initialise the create_template structure */ + env->create_template = (struct xen_domctl_createdomain){ + .flags = XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap, + .max_vcpus = 1, + .max_grant_frames = 1, + .grant_opts = XEN_DOMCTL_GRANT_version(1), +#if defined(__x86_64__) || defined(__i386__) + .arch = { .emulation_flags = XEN_X86_EMU_LAPIC, }, +#endif + }; + /* Update the create_template structure based on the host's capabilities */ + fixup_create_template(&env->create_template, &physinfo); + + env->primary_node = 0; + env->secondary_node = 0; + env->have_secondary_node = false; + + /* + * Pick the node with the most free memory as the primary node, and if + * there's a second node, pick the one with the next most free memory as + * the secondary. + */ + for ( unsigned int i = 1; i < env->num_nodes; i++ ) + { + if ( env->meminfo[i].memfree > env->meminfo[env->primary_node].memfree ) + { + env->secondary_node = env->primary_node; + env->primary_node = i; + env->have_secondary_node = true; + } + else if ( !env->have_secondary_node || + env->meminfo[i].memfree > + env->meminfo[env->secondary_node].memfree ) + { + env->secondary_node = i; + env->have_secondary_node = true; + } + } + + if ( env->num_nodes < 2 ) + env->have_secondary_node = false; + else if ( env->secondary_node == env->primary_node ) + { + for ( unsigned int i = 0; i < env->num_nodes; i++ ) + { + if ( i != env->primary_node ) + { + env->secondary_node = i; + env->have_secondary_node = true; + break; + } + } + } + + return 0; +} + +/* Free allocated memory and close the Xen control interface */ +void lib_release_test_env(struct test_env *env) +{ + free(env->meminfo); + env->meminfo = NULL; + + if ( env->xch ) + { + xc_interface_close(env->xch); + env->xch = NULL; + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/mem-claim/libtestclaims.h b/tools/tests/mem-claim/libtestclaims.h new file mode 100644 index 000000000000..66aa6bc2da10 --- /dev/null +++ b/tools/tests/mem-claim/libtestclaims.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header file for the functional system test framework + * testing for memory claims in the Xen hypervisor. + * + * This header declares the interface for the test framework implemented + * in libtestclaims.c. + * + * It includes the definitions of the test environment, test context, and + * helper functions for performing memory claim operations, querying memory + * state, managing test domains, and recording test results. + */ +#ifndef _LIBTEST_MEM_CLAIMS_ +#define _LIBTEST_MEM_CLAIMS_ + +#include +#include +#include +#include + +#include + +#define MAX_SELECTED_TESTS 32 +#define INVALID_NODE UINT_MAX +#define SPARE_PAGES 200 + +struct test_env { + xc_interface *xch; + struct xen_domctl_createdomain create_template; + unsigned int num_nodes; + unsigned int primary_node; + unsigned int secondary_node; + bool have_secondary_node; + xc_meminfo_t *meminfo; +}; + +struct runtime_config { + const char *selected_ids[MAX_SELECTED_TESTS]; + size_t nr_selected_ids; + bool list_only; + bool verbose; +}; + +enum test_status { + TEST_PASSED, + TEST_FAILED, + TEST_SKIPPED, +}; + +struct test_case; + +struct test_result { + const struct test_case *test; + enum test_status status; + char params[256]; + char details[4096]; + double duration_ms; +}; + +struct test_ctx { + struct test_env *env; + const struct runtime_config *cfg; + struct test_result *result; + uint32_t dom_1; + uint32_t dom_2; + uint64_t target1; + uint64_t target2; + uint64_t alloc_pages; + char step[160]; +}; + +struct lib_populate_physmap_args { + uint32_t domid; + xen_pfn_t start; + unsigned long nr_extents; + unsigned int order; + unsigned int flags; +}; +typedef struct lib_populate_physmap_args lib_populate_args_t; + +/* + * test_fn_t: the test body. Called after the fixture has created + * ctx->domid and captured a baseline outstanding-pages count. Tests needing + * extra domains should create and destroy them explicitly. + * Returns 0 on pass, -1 on fail, 1 on skip. + */ +typedef int (*test_fn_t)(struct test_ctx *ctx); + +struct test_case { + const char *id; + const char *name; + test_fn_t test; +}; + +/* --- diagnostics helpers --- */ +void lib_appendf(char *buf, size_t size, const char *fmt, ...) +__attribute__((format(printf, 3, 4))); + +/* Append a formatted string to ctx->result->details. */ +#define ctx_appendf(ctx, ...) \ + lib_appendf((ctx)->result->details, sizeof((ctx)->result->details), \ + __VA_ARGS__) +void lib_debugf(struct test_ctx *ctx, const char *fmt, ...) +__attribute__((format(printf, 2, 3))); +void lib_set_step(struct test_ctx *ctx, const char *fmt, ...) +__attribute__((format(printf, 2, 3))); +int lib_fail_with_errno(struct test_ctx *ctx, int errnum, const char *fmt, ...) +__attribute__((format(printf, 3, 4))); +int lib_fail(struct test_ctx *ctx, const char *fmt, ...) +__attribute__((format(printf, 2, 3))); +int lib_skip_test(struct test_ctx *ctx, const char *fmt, ...) +__attribute__((format(printf, 2, 3))); + +/* --- memory-state queries --- */ +int lib_get_node_free_pages(struct test_ctx *ctx, unsigned int node, + unsigned long *free_pages, + unsigned long *total_pages); +int lib_get_global_free_pages(struct test_ctx *ctx, unsigned long *free_pages); +int lib_get_total_claims(struct test_ctx *ctx, + uint64_t *outstanding_pages_global); +int lib_check_claim(struct test_ctx *ctx, uint64_t baseline_outstanding, + uint64_t expected_delta, const char *reason); + +/* --- domain lifecycle --- */ +int lib_create_domain(struct test_ctx *ctx, uint32_t *domid, const char *label); +int lib_destroy_domain(struct test_ctx *ctx, uint32_t *domid, + const char *label); + +/* --- claim operations --- */ +int lib_claim_memory(struct test_ctx *ctx, uint32_t domid, uint32_t nr_claims, + memory_claim_t *claims, const char *reason); +int lib_expect_claim_memory_failure(struct test_ctx *ctx, uint32_t domid, + uint32_t nr_claims, memory_claim_t *claims, + int expected_errno, const char *reason); +int lib_release_all_claims(struct test_ctx *ctx, uint32_t domid); +int lib_claim_pages_legacy(struct test_ctx *ctx, uint32_t domid, + unsigned long nr_pages, const char *reason); +int lib_claim_pages_legacy_failure(struct test_ctx *ctx, uint32_t domid, + unsigned long nr_pages, int expected_errno, + const char *reason); +int lib_claim_all_on_host(struct test_ctx *ctx, uint32_t domid, + unsigned int spare); +int lib_claim_all_on_node(struct test_ctx *ctx, uint32_t domid, uint32_t node, + uint32_t spare); + +/* --- physmap --- */ +int lib_populate_success(struct test_ctx *ctx, lib_populate_args_t args); +int lib_populate_failure(struct test_ctx *ctx, lib_populate_args_t args); + +/* --- test runner --- */ +int lib_print_available_tests(const struct test_case *cases, size_t num_cases); +int lib_parse_args(int argc, char *argv[], struct runtime_config *cfg); +int lib_run_one_test(struct test_env *env, const struct runtime_config *cfg, + const struct test_case *test, struct test_result *result); +void lib_run_tests(struct test_env *env, char *argv0, + const struct runtime_config *cfg, + const struct test_case *test_cases, + unsigned int num_test_cases, struct test_result *results); +int lib_summary(const struct test_result *results, unsigned int num_results); +int lib_initialise_test_env(struct test_env *env); +void lib_release_test_env(struct test_env *env); +unsigned long lib_default_alloc_pages(unsigned long free_pages); + +extern int rc; + +static inline const char *status_name(enum test_status status) +{ + switch ( status ) + { + case TEST_PASSED: + return "PASSED"; + case TEST_FAILED: + return "FAILED"; + case TEST_SKIPPED: + return "SKIPPED"; + } + return "UNKNOWN"; +} + +static inline bool test_is_selected(const struct runtime_config *cfg, + const struct test_case *test) +{ + if ( !cfg->nr_selected_ids ) + return true; + + for ( size_t i = 0; i < cfg->nr_selected_ids; i++ ) + if ( !strcmp(cfg->selected_ids[i], test->id) ) + return true; + return false; +} + +#endif /* _LIBTEST_MEM_CLAIMS_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/mem-claim/test-claim-memory.c b/tools/tests/mem-claim/test-claim-memory.c new file mode 100644 index 000000000000..4ea94515ed22 --- /dev/null +++ b/tools/tests/mem-claim/test-claim-memory.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Functional system test suite for testing memory claims in Xen. + * + * It is designed to test the xc_domain_claim_memory() API and + * to reconfirm the xc_domain_claim_pages() API and interacts + * with the running Xen hypervisor in Dom0 using libxenctrl. + * + * The verifications performed by the test cases include: + * + * - Validating that claims can be successfully made with valid parameters + * and that they have the expected effects on the system's memory state, + * such as increasing the number of outstanding claimed pages. + * + * - Validating that invalid claim attempts are rejected with the expected + * error codes, such as EINVAL for invalid parameters or ENOMEM when + * claiming more pages than are free. + * + * - Validating the effects of memory claims on the system, such as blocking + * effects when claiming more pages than are free or left unclaimed by + * other domains, and the guarantees provided by claims such as reserved + * claimed pages not being allocated to other domains. + * + * For the need to perform these verifications, the test cases interact + * with the Xen hypervisor to query the system's memory state, create and + * destroy test domains, perform claim operations, and populate memory to + * test the blocking effects of claims. + * + * As the act of testing the blocking effects of claims involves allocating + * memory from the system, other operations that interact with the system's + * memory state should be avoided or kept to a minimum during the test run + * to avoid interference with the test results. + * + * During these interactions, the test cases record successes and failures + * with detailed messages that include the current step, test parameters, + * and a snapshot of relevant memory state to aid in diagnosing issues + * when a test fails. + * + * The test suite also ensures that domains are destroyed after tests to + * clean up claims and leave the system in a clean state, even if a test + * fails partway through. + * + * Some test cases that require multiple NUMA nodes can be skipped if the + * system does not have a 2nd NUMA node, allowing the test suite to be run + * on single-node systems as well. + * + * It is designed to run on a quiet system as it stakes claims on the system's + * memory and verifies their effects, by allocating against the running system + * Xen hypervisor in Dom0 using libxenctrl. + */ +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "libtestclaims.h" +#include "accounting-1.h" +#include "input-phase1.h" +#include "input-phase2.h" + +/* Short helper to declare test cases more concisely. */ +#define CASE(ID, NAME, FN) \ + { \ + .id = (ID), .name = (NAME), .test = (FN) \ + } + +/* + * List of test cases. lib_run_tests() iterates over this list to run tests. + * + * Tests are identified by their id (e.g. "A1-1") and have a descriptive name + * and a function pointer to the test implementation. + */ +static const struct test_case cases[] = { + CASE("A1-1", "basic_node_claim", test_basic_node_claim), + CASE("A1-2", "global_replace_after_alloc", test_global_replace_after_alloc), + CASE("A1-3", "node_replace_after_alloc", test_node_replace_after_alloc), + CASE("A1-4", "legacy_global_claim", test_legacy_global_claim), + CASE("A1-5", "move_claim_between_nodes", test_move_claim_between_nodes), + CASE("A1-6", "zero_claim_resets_claim", test_zero_claim_resets_claim), + CASE("A1-7", "zero_claim_memory_reset", test_zero_claim_memory_resets), + CASE("I1-1", "reject_non_present_node", test_reject_non_present_node), + CASE("I1-2", "reject_too_many_claims", test_reject_too_many_claims), + CASE("I1-3", "reject_node_gt_uint8_max", test_reject_node_gt_uint8_max), + CASE("I1-4", "reject_pages_gt_int32_max", test_reject_pages_gt_int32_max), + CASE("I1-5", "reject_nonzero_pad", test_reject_nonzero_pad), + CASE("I1-6", "reject_zero_claim_count", test_reject_zero_claim_count), + CASE("I1-7", "null_claims_nonzero_count", test_null_claims_nonzero_count), + CASE("I1-8", "zero_count_with_pointer", test_zero_count_valid_pointer), + CASE("I1-9", "claim_pages_gt_free_enomem", test_claim_pages_gt_free_enomem), + CASE("I2-1", "claim_pages_causes_enomem", test_claim_pages_causes_enomem), + CASE("I2-2", "claim_memory_causes_enomem", test_claim_memory_causes_enomem), + CASE("I2-3", "claim_prima_causes_enomem", test_claim_prima_causes_enomem), +}; + +/* Test entry point */ +int main(int argc, char **argv) +{ + struct test_result results[ARRAY_SIZE(cases)] = {}; + struct runtime_config cfg = {}; + struct test_env env = {}; + int retval; + + retval = lib_parse_args(argc, argv, &cfg); + if ( cfg.list_only ) + return lib_print_available_tests(cases, ARRAY_SIZE(cases)); + if ( !retval ) + { + lib_initialise_test_env(&env); + lib_run_tests(&env, argv[0], &cfg, cases, ARRAY_SIZE(cases), results); + retval = lib_summary(results, ARRAY_SIZE(results)); + lib_release_test_env(&env); + } + return retval ? EXIT_FAILURE : EXIT_SUCCESS; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 14 14:02:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 14:02:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1281998.1564703 (Exim 4.92) (envelope-from ) id 1wCeKm-00015A-K7; Tue, 14 Apr 2026 14:01:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1281998.1564703; Tue, 14 Apr 2026 14:01:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCeKm-000153-GI; Tue, 14 Apr 2026 14:01:44 +0000 Received: by outflank-mailman (input) for mailman id 1281998; Tue, 14 Apr 2026 14:01:43 +0000 Received: from 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X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Message-ID: Date: Tue, 14 Apr 2026 17:09:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm64: flushtlb: Optimize ARM64_WORKAROUND_REPEAT_TLBI To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Volodymyr Babchuk , Mark Rutland References: <20260414081124.48741-1-michal.orzel@amd.com> <5098DD0F-9FA9-469B-BAAA-2CA0C1382FA0@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <5098DD0F-9FA9-469B-BAAA-2CA0C1382FA0@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit 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CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(22082099003)(18002099003)(56012099003)(18096099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tOstmmu6fGaep4AqO0vOXrVCJwjtgVUuvBfuQyHIh2PqRyaRb+0mcZ0i3KIWjFkzZBF6u6VQtd3Cd2NkhuKJA/+ej3yzVnGiDSzO//CydM7zhR9aCEmXkbGrrXIV3vPHlJBhI+ps0Akpiw6/IIr8t0TcoIoo5AaLoN52OfEVBTiwA9xVV5vorPVMtAqHT66UTKZQ67xtSTGj8DozHaJPZ+Q2zw8KJtmev58eNIytWLMMDbekjdkbKIfE4YwLWnCQ+Sx/huO9TbS2flDZbavINinM1cPqZA2bWPJ7X7aoWO3ytReqRFZTUnTRyHGBjulzRnlcC7VaIpbQwPDtOSF6BSfjEcyKPp0AVcCy39Gho+11TSq4jNdy8cjL6joNKfOclDW51OqH9ZUBvI0l0+71RTSpbCmgE2m2b5q1ON8PQfm+Pr2WtEljYTCpV2496CxO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2026 15:09:05.9423 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3274379-0224-4e0b-968f-08de9a37c57b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4474 X-purgate-ID: tlsNG-d62444/1776179352-B727DFF4-01CA152A/0/0 X-purgate-type: clean X-purgate-size: 13844 On 14/04/2026 16:00, Luca Fancellu wrote: > Hi Michal, > >> On 14 Apr 2026, at 09:11, Michal Orzel wrote: >> >> The ARM64_WORKAROUND_REPEAT_TLBI workaround is used to mitigate several >> errata where broadcast TLBI;DSB sequences don't provide all the >> architecturally required synchronization. The workaround performs more >> work than necessary, and can have significant overhead. This patch >> optimizes the workaround, as explained below. >> >> 1. All relevant errata only affect the ordering and/or completion of >> memory accesses which have been translated by an invalidated TLB >> entry. The actual invalidation of TLB entries is unaffected. >> >> 2. The existing workaround is applied to both broadcast and local TLB >> invalidation, whereas for all relevant errata it is only necessary to >> apply a workaround for broadcast invalidation. >> >> 3. The existing workaround replaces every TLBI with a TLBI;DSB;TLBI >> sequence, whereas for all relevant errata it is only necessary to >> execute a single additional TLBI;DSB sequence after any number of >> TLBIs are completed by a DSB. >> >> For example, for a sequence of batched TLBIs: >> >> TLBI [, ] >> TLBI [, ] >> TLBI [, ] >> DSB ISH >> >> ... the existing workaround will expand this to: >> >> TLBI [, ] >> DSB ISH // additional >> TLBI [, ] // additional >> TLBI [, ] >> DSB ISH // additional >> TLBI [, ] // additional >> TLBI [, ] >> DSB ISH // additional >> TLBI [, ] // additional >> DSB ISH >> >> ... whereas it is sufficient to have: >> >> TLBI [, ] >> TLBI [, ] >> TLBI [, ] >> DSB ISH >> TLBI [, ] // additional >> DSB ISH // additional >> >> Using a single additional TBLI and DSB at the end of the sequence can > > NIT: Typo s/TBLI/TLBI > >> have significantly lower overhead as each DSB which completes a TLBI >> must synchronize with other PEs in the system, with potential >> performance effects both locally and system-wide. >> >> 4. The existing workaround repeats each specific TLBI operation, whereas >> for all relevant errata it is sufficient for the additional TLBI to >> use *any* operation which will be broadcast, regardless of which >> translation regime or stage of translation the operation applies to. >> >> For example, for a single TLBI: >> >> TLBI ALLE2IS >> DSB ISH >> >> ... the existing workaround will expand this to: >> >> TLBI ALLE2IS >> DSB ISH >> TLBI ALLE2IS // additional >> DSB ISH // additional >> >> ... whereas it is sufficient to have: >> >> TLBI ALLE2IS >> DSB ISH >> TLBI VALE1IS, XZR // additional >> DSB ISH // additional >> >> As the additional TLBI doesn't have to match a specific earlier TLBI, >> the additional TLBI can be implemented in separate code, with no >> memory of the earlier TLBIs. The additional TLBI can also use a >> cheaper TLBI operation. >> >> 5. The existing workaround is applied to both Stage-1 and Stage-2 TLB >> invalidation, whereas for all relevant errata it is only necessary to >> apply a workaround for Stage-1 invalidation. >> >> Architecturally, TLBI operations which invalidate only Stage-2 >> information (e.g. IPAS2E1IS) are not required to invalidate TLB >> entries which combine information from Stage-1 and Stage-2 >> translation table entries, and consequently may not complete memory >> accesses translated by those combined entries. In these cases, >> completion of memory accesses is only guaranteed after subsequent >> invalidation of Stage-1 information (e.g. VMALLE1IS). >> >> Rework the workaround logic as follows: >> - add TLB_HELPER_LOCAL() to be used for local TLB ops without a >> workaround, >> - modify TLB_HELPER() workaround to use tlbi vale2is, xzr as a second >> TLB, > > TLBI ? > >> - drop TLB_HELPER_VA(). It's used only by __flush_xen_tlb_one_local >> which is local and does not need workaround and by >> __flush_xen_tlb_one. In the latter case, since it's used in a loop, >> we don't need a workaround in the middle. Add __tlb_repeat_sync with >> a workaround to be used at the end after DSB and before final ISB, >> - TLBI VALE2IS passing XZR is used as an additional TLBI. While there is >> an identity mapping there, it's used very rarely. The performance >> impact is therefore negligible. If things change in the future, we >> can revisit the decision. >> >> Signed-off-by: Michal Orzel >> --- >> Linux counterpart (already merged): >> https://lore.kernel.org/linux-arm-kernel/20260218164348.2022831-1-mark.rutland@arm.com/ >> --- >> xen/arch/arm/include/asm/arm32/flushtlb.h | 3 + >> xen/arch/arm/include/asm/arm64/flushtlb.h | 108 ++++++++++++++-------- >> xen/arch/arm/include/asm/flushtlb.h | 1 + >> 3 files changed, 71 insertions(+), 41 deletions(-) >> >> diff --git a/xen/arch/arm/include/asm/arm32/flushtlb.h b/xen/arch/arm/include/asm/arm32/flushtlb.h >> index 61c25a318998..5483be08fbbe 100644 >> --- a/xen/arch/arm/include/asm/arm32/flushtlb.h >> +++ b/xen/arch/arm/include/asm/arm32/flushtlb.h >> @@ -57,6 +57,9 @@ static inline void __flush_xen_tlb_one(vaddr_t va) >> asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); >> } >> >> +/* Only for ARM64_WORKAROUND_REPEAT_TLBI */ >> +static inline void __tlb_repeat_sync(void) {} >> + >> #endif /* __ASM_ARM_ARM32_FLUSHTLB_H__ */ >> /* >> * Local variables: >> diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h >> index 3b99c11b50d1..1606b26bf28a 100644 >> --- a/xen/arch/arm/include/asm/arm64/flushtlb.h >> +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h >> @@ -12,9 +12,14 @@ >> * ARM64_WORKAROUND_REPEAT_TLBI: >> * Modification of the translation table for a virtual address might lead to >> * read-after-read ordering violation. >> - * The workaround repeats TLBI+DSB ISH operation for all the TLB flush >> - * operations. While this is strictly not necessary, we don't want to >> - * take any risk. >> + * The workaround repeats TLBI+DSB ISH operation for broadcast TLB flush >> + * operations. The workaround is not needed for local operations. >> + * >> + * It is sufficient for the additional TLBI to use *any* operation which will >> + * be broadcast, regardless of which translation regime or stage of translation >> + * the operation applies to. TLBI VALE2IS is used passing XZR. While there is >> + * an identity mapping there, it's only used during suspend/resume, CPU on/off, >> + * so the impact (performance if any) is negligible. >> * >> * For Xen page-tables the ISB will discard any instructions fetched >> * from the old mappings. >> @@ -26,69 +31,90 @@ >> * Note that for local TLB flush, using non-shareable (nsh) is sufficient >> * (see D5-4929 in ARM DDI 0487H.a). Although, the memory barrier in >> * for the workaround is left as inner-shareable to match with Linux >> - * v6.1-rc8. >> + * v6.19. >> */ >> -#define TLB_HELPER(name, tlbop, sh) \ >> +#define TLB_HELPER_LOCAL(name, tlbop) \ >> static inline void name(void) \ >> { \ >> asm_inline volatile ( \ >> - "dsb " # sh "st;" \ >> + "dsb nshst;" \ >> "tlbi " # tlbop ";" \ >> - ALTERNATIVE( \ >> - "nop; nop;", \ >> - "dsb ish;" \ >> - "tlbi " # tlbop ";", \ >> - ARM64_WORKAROUND_REPEAT_TLBI, \ >> - CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ >> - "dsb " # sh ";" \ >> + "dsb nsh;" \ >> "isb;" \ >> : : : "memory"); \ >> } >> >> -/* >> - * FLush TLB by VA. This will likely be used in a loop, so the caller >> - * is responsible to use the appropriate memory barriers before/after >> - * the sequence. >> - * >> - * See above about the ARM64_WORKAROUND_REPEAT_TLBI sequence. >> - */ >> -#define TLB_HELPER_VA(name, tlbop) \ >> -static inline void name(vaddr_t va) \ >> -{ \ >> - asm_inline volatile ( \ >> - "tlbi " # tlbop ", %0;" \ >> - ALTERNATIVE( \ >> - "nop; nop;", \ >> - "dsb ish;" \ >> - "tlbi " # tlbop ", %0;", \ >> - ARM64_WORKAROUND_REPEAT_TLBI, \ >> - CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ >> - : : "r" (va >> PAGE_SHIFT) : "memory"); \ >> +#define TLB_HELPER(name, tlbop) \ >> +static inline void name(void) \ >> +{ \ >> + asm_inline volatile ( \ >> + "dsb ishst;" \ >> + "tlbi " # tlbop ";" \ >> + ALTERNATIVE( \ >> + "nop; nop;", \ >> + "dsb ish;" \ >> + "tlbi vale2is, xzr;", \ >> + ARM64_WORKAROUND_REPEAT_TLBI, \ >> + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ >> + "dsb ish;" \ >> + "isb;" \ >> + : : : "memory"); \ >> } >> >> /* Flush local TLBs, current VMID only. */ >> -TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh) >> +TLB_HELPER_LOCAL(flush_guest_tlb_local, vmalls12e1) >> >> /* Flush innershareable TLBs, current VMID only */ >> -TLB_HELPER(flush_guest_tlb, vmalls12e1is, ish) >> +TLB_HELPER(flush_guest_tlb, vmalls12e1is) >> >> /* Flush local TLBs, all VMIDs, non-hypervisor mode */ >> -TLB_HELPER(flush_all_guests_tlb_local, alle1, nsh) >> +TLB_HELPER_LOCAL(flush_all_guests_tlb_local, alle1) >> >> /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ >> -TLB_HELPER(flush_all_guests_tlb, alle1is, ish) >> +TLB_HELPER(flush_all_guests_tlb, alle1is) >> >> /* Flush all hypervisor mappings from the TLB of the local processor. */ >> -TLB_HELPER(flush_xen_tlb_local, alle2, nsh) >> +TLB_HELPER_LOCAL(flush_xen_tlb_local, alle2) >> + >> +#undef TLB_HELPER_LOCAL >> +#undef TLB_HELPER >> + >> +/* >> + * FLush TLB by VA. This will likely be used in a loop, so the caller >> + * is responsible to use the appropriate memory barriers before/after >> + * the sequence. >> + */ >> >> /* Flush TLB of local processor for address va. */ >> -TLB_HELPER_VA(__flush_xen_tlb_one_local, vae2) >> +static inline void __flush_xen_tlb_one_local(vaddr_t va) >> +{ >> + asm_inline volatile ( >> + "tlbi vae2, %0" : : "r" (va >> PAGE_SHIFT) : "memory"); >> +} >> >> /* Flush TLB of all processors in the inner-shareable domain for address va. */ >> -TLB_HELPER_VA(__flush_xen_tlb_one, vae2is) >> +static inline void __flush_xen_tlb_one(vaddr_t va) >> +{ >> + asm_inline volatile ( >> + "tlbi vae2is, %0" : : "r" (va >> PAGE_SHIFT) : "memory"); >> +} >> >> -#undef TLB_HELPER >> -#undef TLB_HELPER_VA >> +/* >> + * ARM64_WORKAROUND_REPEAT_TLBI: >> + * For all relevant erratas it is only necessary to execute a single >> + * additional TLBI;DSB sequence after any number of TLBIs are completed by DSB. >> + */ >> +static inline void __tlb_repeat_sync(void) >> +{ >> + asm_inline volatile ( >> + ALTERNATIVE( >> + "nop; nop;", >> + "tlbi vale2is, xzr;" >> + "dsb ish;", >> + ARM64_WORKAROUND_REPEAT_TLBI, >> + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) >> + : : : "memory"); >> +} >> >> #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ >> /* >> diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm/flushtlb.h >> index e45fb6d97b02..c292c3c00d29 100644 >> --- a/xen/arch/arm/include/asm/flushtlb.h >> +++ b/xen/arch/arm/include/asm/flushtlb.h >> @@ -65,6 +65,7 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, >> va += PAGE_SIZE; >> } >> dsb(ish); /* Ensure the TLB invalidation has completed */ >> + __tlb_repeat_sync(); > > More a question here rather than a comment, shall we have a comment on top > of this stating that it’s deliberate to have it before the isb? > Or developer should infer it from the code and from git blame? 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To understand it fully, you still need to read the complete message to get a full picture, so I don't think that adding a commit with one sentence improves the situation. > >> isb(); >> } >> >> -- >> 2.43.0 >> >> > > With these fixed: The NITs can be fixed on commit provided no other remarks from other maintainers, specifically @Julien. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 14 15:17:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 15:17:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282025.1564722 (Exim 4.92) (envelope-from ) id 1wCfWN-0001oa-6I; Tue, 14 Apr 2026 15:17:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282025.1564722; Tue, 14 Apr 2026 15:17:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCfWN-0001oT-2R; Tue, 14 Apr 2026 15:17:47 +0000 Received: by outflank-mailman (input) for mailman id 1282025; Tue, 14 Apr 2026 15:17:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCfWL-0001oN-Gd for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 15:17:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCfWK-00GyXU-9N for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 17:17:44 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de5a8d-e002-0a2a0a5209dd-0a2a4507c124-24 for ; Tue, 14 Apr 2026 17:17:44 +0200 Received: from [52.101.46.23] (helo=CO1PR03CU002.outbound.protection.outlook.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de5a96-ba2d-0a2a45070019-34652e17cb91-3 for ; Tue, 14 Apr 2026 17:17:43 +0200 Received: from LV3PR03MB7707.namprd03.prod.outlook.com (2603:10b6:408:28b::21) by CH0PR03MB6068.namprd03.prod.outlook.com (2603:10b6:610:bf::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.48; Tue, 14 Apr 2026 15:17:36 +0000 Received: from LV3PR03MB7707.namprd03.prod.outlook.com ([fe80::97e8:ef9c:9031:e2bf]) by LV3PR03MB7707.namprd03.prod.outlook.com ([fe80::97e8:ef9c:9031:e2bf%6]) with mapi id 15.20.9769.046; Tue, 14 Apr 2026 15:17:36 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=citrix.com header.i="@citrix.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:x-ms-exchange-senderadcheck" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=UJa63nQ03rQ1ZJTYobZsogUzbIpx+EondWqH4Bec3pcCtz4P4SX+I3Kzax8VKiO9ltbMt451MtjvE/zlSHXYF+YojF69tZOSO1eiGrL1tn8PpAxgLHrLYpnHZ/nNjw92L/zWgRdCkZLSvhKUB/DenD71LLtHbe01TwglAv0C66rb/vYCZhfmfARb+JsXnHAsqURW7HYZs/TyEmB1BrszlPMqNS8N5hp4VNMPxsBNu48rBCRWuFu8C1lZ23cF+Ix2rFuc1J0v9UGCV/K9WbVwvf9q//bxGCctGd+cWxkvaLr4YgaB7IozU8THBEZ2rjzM66i7Wod8t3Q8+Bm9LTVWaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=keQrFtT9dt5ZDdhDEWvYWBjAYAxqqgcuTssWiEsqDlA=; b=rJkjXr3G7mVd6a41emhNx26+KWoRoHoKi4AP8xysX9LcPRxcR1WS3tg1n/yZHGskO25OxDz5pEFLtYhDThq2PIWi2FPPR0DnlPp4ukWmuLdF+8XF+DN03gnmfA1kKH+qq+PrzBXOFObWFBW784wmLYXPP8ZlVyDELXwK4fXpB/1dxf6VEw6ufitVP7W2xsn9iwUjiwcB9iZf/zU3Hvq9HpEYje8+4rp7D9fPfGsugxTfjZaZgpQEWWtf3wtLb9eQK4wzuBxFy1zB/84kdSwO5rUs0bneWf11ThHgi818eQRRK+Q26Bo5VT6WY3ifCQ/xOK6dKbeMaLjGMityl4zUNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=keQrFtT9dt5ZDdhDEWvYWBjAYAxqqgcuTssWiEsqDlA=; b=icj9r5onP9krSxqdkoxnUG1CoLloS3f81fSgsjHl5FTFcvla8N1F39CDPG2Smy3azY9CqM1q1A05ucaDw3Zek3Ge2w8y+NJPI9mWVS2HgVfMZNey+fLAdmZ7KAFWlMD6LydUPSjdNqRkhlwmXSLDQat3djwsNGUvRuRlEL/Lhak= From: Bernhard Kaindl To: Jan Beulich CC: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Roger Pau Monne , Stefano Stabellini , "Daniel P. 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43d63e46a85sm42868094f8f.24.2026.04.14.09.04.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Apr 2026 09:04:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776182679; x=1776787479; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=a+aMCWayM4ixlHJG7UsZh7nEeBfMdvI1oSjCQGXA9E8=; b=PwqBXoIMuRMDZWBtfoq6F7tin3ryMWQpJB5PWnvAZ+5CvL7YQGMCzFtlWxjsS1vX4f jZbIVobbxEr3HwfBkKCNujgM0V3hrt10rfjavEd1cZqQnuIMw5UG5XiKuaAG+Q9IxDxy fzLY67mFzH48k+cEf5RxC1Q5o9gyN1ku9g/YPYADFA5xXefATlc1hDqzB/hNUVfmcMx6 Njb9ukMnwddr/JJTp0QoQLe+IkW/kFnmPHG4RCoUYyZsF9EdDHf11A8djaDZodDGF0u0 U0/fzbx8H4dDvR3KiD2Wq4NF83JeNd6KbCUihaGorX4RXyuBNnB5e3fOLtgzSBIbj/Ll p+9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776182679; x=1776787479; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=a+aMCWayM4ixlHJG7UsZh7nEeBfMdvI1oSjCQGXA9E8=; b=qebUlvGH0ZF9VHQ9BFwCvbjRrDK9O3/NvucGwqeNMEKImIZeb8FTmPOB67hT3EZVyP lzJq8megPq728xWQarR6P0Z7RIVcQnZbpuJixuTKcfCDENseISrqz4qT3X5zYNeY0ofl hh5t7FMUPA8Rv7xdOTWvGghJM2pFlNq3AhQdZV2BsnhvFyLN2h04BuKgvSjoY9DZhSB6 V5S49Jx2RBsjDLt5vKSmkpLBuIB3YcKZ2RCgVw8RvKWJM7Nv7gn7kH8oTgnr+3Bbd1s8 f6eu/+gU7LG3mw994WWfYk1tvwPAFi3CaDuPrFZ2+x7Jnxmpro86AmJfdsr4bUnmvQw3 k0oQ== X-Forwarded-Encrypted: i=1; AFNElJ/hrNSC0SmxJ3FRbyb/4BTwI2Uo+jyMkomp7DARhaeisJR5YFigs6PVzoLk9TxB45JuHpRA//2VNj4=@lists.xenproject.org X-Gm-Message-State: AOJu0Yzd7bFSlrdNgJGFW0OgoquKksTdaGVfo+EcoXuhkBWzfaq4Gb5k 6CAPh0kZirKiR/JLTe1D2GGOWdbT8eqC4h7U6EQHTVtSA6YWICTYoqkC X-Gm-Gg: AeBDieue5HfY1GCE5XGmecJBLKq0WL2Rwca3xWadDDHHG9SnPldgSuOpX+50ZKjprLS dc1WhjcwUMMLWK77sOYHyblpwt8toKkK/Wn6F5/AybbCwK+Ozcbs+WPD1niZ8vof69r6p3TGbz/ XT2zmL6xWYEYm8l3YX1xVT0aCB/IqpU+3yMBDw887yzhvUVRnPt6Jl6BEMtiypQtPYnWPGctmsP OLzryXWJwFsW2RDS00uFb8konnXaerpl0eZrM9aOAGoENpD309lgD49HPLOI2QO+0oUuL2yXQtN n9n3X5QBqUkD/IC9y6f8nOF5DzyS4ZENgIEqe0sUXZfJthhaiN5a5ckgTLOfM6jQk6CrvZ5OAl4 LTz9Kgw3LI0rp4E7TZaEG/yHrWTaVPX1IaMHiS4jF550BDwh/zbMYdcnjkuRveu3Ic1CsVv9w3G yP/MeSORiV01CeL7rw1ObwlezlEQAgYDAZ4j3mdU/psOe5xAxo5yXnsrJjv1US24BySWyVqxVc1 kAgbFkKpVOQ5w== X-Received: by 2002:a05:600c:4a12:b0:488:aac9:7a31 with SMTP id 5b1f17b1804b1-488cd23f39fmr201037065e9.0.1776182678527; Tue, 14 Apr 2026 09:04:38 -0700 (PDT) Message-ID: <76ea5954-89cd-47a4-872a-239bbc08b785@gmail.com> Date: Tue, 14 Apr 2026 18:04:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 19/27] xen/riscv: emulate guest writes to virtual APLIC MMIO To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <2bff40f5-2eef-4e72-8191-b3442607e0e4@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <2bff40f5-2eef-4e72-8191-b3442607e0e4@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776182679-ACD30CD1-EDAE375D/10/73395122804 X-purgate-type: spam X-purgate-size: 12136 On 4/2/26 4:18 PM, Jan Beulich wrote: > On 10.03.2026 18:08, Oleksii Kurochko wrote: >> --- a/xen/arch/riscv/vaplic.c >> +++ b/xen/arch/riscv/vaplic.c >> @@ -20,6 +20,16 @@ >> >> #include "aplic-priv.h" >> >> +#define APLIC_REG_GET(addr, offset) \ >> + readl((void *)((vaddr_t)(addr) + offset)) >> +#define APLIC_REG_SET(addr, offset, value) \ >> + writel(value, (void *)((vaddr_t)(addr) + offset)) > > Why is addr properly parenthesized, but offset isn't? Overlooked that. Will fix. > >> +#define AUTH_IRQ_BIT(irqnum) (auth_irq_bmp[(irqnum) / APLIC_NUM_REGS] & \ >> + BIT((irqnum) % APLIC_NUM_REGS, U)) >> + >> +#define regval_to_irqn(reg_val) ((reg_val) / sizeof(uint32_t)) > > I'm trying to make sense of the division here, but I think the main issue > is with naming: It's not a "register value" which is passed into here, but > a register index (offset from a range's base register). register index would be clearer. I will rename s/regval/regindx. > >> @@ -127,6 +137,164 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >> return 0; >> } >> >> +static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t *iprio) >> +{ >> + *iprio &= APLIC_TARGET_IPRIO_MASK; >> + *iprio |= (hart_id << APLIC_TARGET_HART_IDX_SHIFT); >> +} >> + >> +static void vaplic_update_target(const struct imsic_config *imsic, >> + const int guest_id, >> + const unsigned long hart_id, uint32_t *value) >> +{ >> + unsigned long group_index; >> + unsigned int hhxw = imsic->group_index_bits; >> + unsigned int lhxw = imsic->hart_index_bits; >> + unsigned int hhxs = imsic->group_index_shift - IMSIC_MMIO_PAGE_SHIFT * 2; >> + unsigned long base_ppn = imsic->msi[hart_id].base_addr >> IMSIC_MMIO_PAGE_SHIFT; >> + >> + group_index = (base_ppn >> (hhxs + 12)) & (BIT(hhxw, UL) - 1); > > And there's no constant available to make this literal 12 more descriptive? As it was used in aplic_set_irq_affinity() - IMSIC_MMIO_PAGE_SHIFT could be used here. > >> + *value &= APLIC_TARGET_EIID_MASK; >> + *value |= guest_id << APLIC_TARGET_GUEST_IDX_SHIFT; >> + *value |= hart_id << APLIC_TARGET_HART_IDX_SHIFT; >> + *value |= group_index << (lhxw + APLIC_TARGET_HART_IDX_SHIFT) ; >> +} > > Both functions returning void right now, why would they need to return their > result via indirection? No specific reason. Do you think it would be better just to return value instead? I am okay to rework that. > >> +#define CALC_REG_VALUE(base) \ >> +{ \ >> + uint32_t index; \ >> + uint32_t tmp_val; \ > > Combine these two, or have the variables have initializers? > >> + index = regval_to_irqn(offset - base); \ > > There's no "offset" declared or passed into here, nor ... > >> + tmp_val = APLIC_REG_GET(priv->regs, aplic_addr) & ~auth_irq_bmp[index]; \ > > ... "priv", nor ... > >> + value &= auth_irq_bmp[index]; \ >> + value |= tmp_val; \ > > ... "value". It may remain like this, but then it wants putting inside the > sole function that uses it, and be #undef-ed at the end of the function. > >> +} > > Please wrap in do/while(0), for use sites to be required to have semicolons > (and hence look like normal statements). Or make it a statement expression > properly returning the calculated value. I will put the following inside the function + undef at the end: #define CALC_REG_VALUE(base) do { \ \ uint32_t index = regindx_to_irqn(offset - (base)); \ uint32_t tmp_val = APLIC_REG_GET(priv->regs, aplic_addr) & \ ~auth_irq_bmp[index]; \ value &= auth_irq_bmp[index]; \ value |= tmp_val; \ } while ( 0 ) > >> +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, >> + unsigned long addr, uint32_t value) >> +{ >> + struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >> + struct aplic_priv *priv = vaplic->base.info->private; >> + uint32_t offset = addr & APLIC_REG_OFFSET_MASK; > > See ./CODING_STYLE as to uses of fixed-width types. > >> + unsigned long aplic_addr = addr - priv->paddr_start; >> + const uint32_t *auth_irq_bmp = vcpu->domain->arch.vintc->private; >> + >> + switch ( offset ) >> + { >> + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: > > And (taking this just as example) any misaligned accesses falling in this range > are fine? Do you mean something like 0x1C02 instead of 0x1C00 or 0x1C04? If yes, then I don't think. I will add the following between switch(): if ( offset & 3 ) { gdprintk(XENLOG_WARNING, "Misaligned APLIC access at offset %#x\n", offset); return -EINVAL; } > >> + CALC_REG_VALUE(APLIC_SETIP_BASE); >> + break; >> + >> + case APLIC_CLRIP_BASE ... APLIC_CLRIP_LAST: >> + CALC_REG_VALUE(APLIC_CLRIP_BASE); >> + break; >> + >> + case APLIC_SETIE_BASE ... APLIC_SETIE_LAST: >> + CALC_REG_VALUE(APLIC_SETIE_BASE); >> + break; >> + >> + case APLIC_CLRIE_BASE ... APLIC_CLRIE_LAST: >> + CALC_REG_VALUE(APLIC_CLRIE_BASE); >> + break; >> + >> + case APLIC_SOURCECFG_BASE ... APLIC_SOURCECFG_LAST: >> + /* We don't suppert delagation, so bit10 if sourcecfg should be 0 */ >> + ASSERT(!(value & BIT(10, U))); > > And that bit doesn't have a proper #define? No, at the moment, I will add: #define APLIC_SOURCECFG_D BIT(10, U) to aplic.h. > >> + /* >> + * As sourcecfg register starts from 1: >> + * 0x0000 domaincfg >> + * 0x0004 sourcecfg[1] >> + * 0x0008 sourcecfg[2] >> + * ... >> + * 0x0FFC sourcecfg[1023] >> + * It is necessary to calculate an interrupt number by substracting > > Nit: subtracting > >> + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. >> + */ >> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) >> + /* interrupt not enabled, ignore it */ > > Throughout the series: Please adhere to ./CODING_STYLE. > >> + return 0; >> + >> + break; > > And any value is okay to write? No, it should be in a range [APLIC_SOURCECFG_SM_INACTIVE,APLIC_SOURCECFG_SM_LEVEL_LOW]. I will add the check before break: if ( value > APLIC_SOURCECFG_SM_LEVEL_LOW ) { gdprintk(XENLOG_WARNING, "value(%u) is incorrect for sourcecfg register\n", value); value = APLIC_SOURCECFG_SM_INACTIVE; } > >> + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: >> + struct vcpu *target_vcpu = NULL; >> + >> + /* >> + * Look at vaplic_emulate_load() for explanation why >> + * APLIC_GENMSI is substracted. >> + */ > > There's no vaplic_emulate_load() - how can I go look there? It is introduced in the next patch. > > Also same typo again as above. > >> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) >> + /* interrupt not enabled, ignore it */ >> + return 0; >> + >> + for ( int i = 0; i < vcpu->domain->max_vcpus; i++ ) > > unsigned int > >> + { >> + struct vcpu *v = vcpu->domain->vcpu[i]; >> + >> + if ( v->vcpu_id == (value >> APLIC_TARGET_HART_IDX_SHIFT) ) >> + { >> + target_vcpu = v; >> + break; >> + } >> + } >> + >> + ASSERT(target_vcpu); > > What guarantees the pointer to be non-NULL? The incoming value can be > arbitrary, afaict. I didn't understand your point. It is just checking that target_vcpu has been found. If after for() loop the value of target_vcpu is still NULL then something wrong in Xen. > >> + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) >> + { >> + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor), >> + &value); >> + } >> + else >> + vaplic_update_target(priv->imsic_cfg, >> + vcpu_guest_file_id(target_vcpu), >> + cpuid_to_hartid(target_vcpu->processor), >> + &value); > > I'm struggling with the naming here: When DM is clear, a function with "dm" > in the name is called. it means direct (delivery) mode. Maybe it is better to put dm at the end of the function name? Or it is just better to change it to something else? > > For the latter one, unless other uses are intended speaking against that, > instead of the middle two arguments simply pass target_vcpu? Good point. I will update the function accordingly. > > Also please omit the braces consistently from both branches. > >> + break; >> + >> + case APLIC_SETIPNUM: >> + case APLIC_SETIPNUM_LE: > > What about APLIC_SETIPNUM_BE? > >> + case APLIC_CLRIPNUM: >> + case APLIC_SETIENUM: >> + case APLIC_CLRIENUM: >> + if ( AUTH_IRQ_BIT(value) ) >> + break; > > Aren't you easily overrunning auth_irq_bmp[] here? It makes sense to add instead: if ( !value || value >= APLIC_NUM_REGS * APLIC_NUM_REGS || !AUTH_IRQ_BIT(value) ) return 0; break; > >> + return 0; >> + >> + case APLIC_DOMAINCFG: >> + /* >> + * TODO: >> + * The domaincfg register has this format: >> + * bits 31:24 read-only 0x80 >> + * bit 8 IE >> + * bit 7 read-only 0 >> + * bit 2 DM (WARL) >> + * bit 0 BE (WARL) >> + * >> + * The most interesting bit for us is IE(Interrupt Enable) bit. >> + * At the moment, at least, Linux doesn't use domaincfg.IE bit to >> + * disable interrupts globally, but if one day someone will use it >> + * then extra actions should be done. >> + */ >> + >> + printk_once("%s: Nothing to do, domaincfg is set by aplic during " >> + "initialization in Xen\n", __func__); > > As per the comment it's not "nothing to do", but your choice to ignore writes > even if they may be relevant. I will change "Nothing to do" to "Ignore writes to". > >> + return 0; >> + >> + default: >> + panic("%s: unsupported register offset: %#x\n", __func__, offset); > > Crashing the host for the guest doing something odd? It's odd that the function > only ever returns 0 anyway - it could simply return an error here (if the > itention is to not ignore such writes). But maybe it is a legal offset and we really want to support it? Even if I will return just error then a caller site will want to do something with this error -> for example, kill domain or panic() again. Maybe panic is to much and just domain should be crashed here: default: gdprintk(XENLOG_WARNING, "Unhandled APLIC write at offset %#x (value %#x)\n", offset, value); domain_crash(vcpu->domain); return 0; ? > > As it's not clear what values other than zero such a function may return, I > also can't comment on its (and the hook's) return type (may want to be bool > instead of int). Maybe, it makes sense to switch to bool. As I mentioned above I'm returning -EINVAL in some cases. But it could be really just return 1 instead. Here: if ( offset & 3 ) { gdprintk(XENLOG_WARNING, "Misaligned APLIC access at offset %#x\n", offset); return -EINVAL; } Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:08:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:08:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282070.1564739 (Exim 4.92) (envelope-from ) id 1wCk3q-0002Jy-Dh; Tue, 14 Apr 2026 20:08:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282070.1564739; Tue, 14 Apr 2026 20:08:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCk3q-0002Jq-8y; Tue, 14 Apr 2026 20:08:38 +0000 Received: by outflank-mailman (input) for mailman id 1282070; Tue, 14 Apr 2026 20:08:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCk3o-0002JR-Ls for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:08:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCk3l-007whr-UN for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 22:08:35 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69de9ea0-5cb7-0a2a0a5109dd-0a2a4502e8ea-32 for ; Tue, 14 Apr 2026 22:08:35 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69de9ec1-42fa-0a2a45020019-aceafc1fe558-3 for ; Tue, 14 Apr 2026 22:08:34 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id C64D1416F8; Tue, 14 Apr 2026 20:08:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4206FC19425; Tue, 14 Apr 2026 20:08:32 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776197312; bh=yjVCZ3a0MrQZ9xudQupVJGsRXbJe5XDuXlr+v1hQPS8=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=r2fSS6EPlkY+jyQLBgtliy+sf1NAR9PIAYSdJhLd/2rPvH7J2Zlc34WQr6g8V3A2l Ndwx7RIDMsSqmF2/VCY5dgM+c4RRvSudqZzdmu3LU9leWblj+MAYIQPHSH2iaL6H6V BY6ZPV5017q9iKPxBkq/BaN8VmmKM26b8Kk8sSRg8C2zgrhINye9giYyvRnzOCePMv Ue9YDENRDV8GTI5tVtvrPO7Qyoe9TJ2IZlm62pxaEG33Mozgr/jrzcj1i2Jr8NT+Xa MD2J+gFFhNyiP4lP7Xt8AaZkgq1dp56DeFf0kCIWpnJRoJs1tVG2VDyjZMjICkdhvu C4bYDyONnvOjw== Date: Tue, 14 Apr 2026 13:08:22 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Roger Pau Monne cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Teddy Astie , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: Re: [PATCH 0/2] time: fix time accounting for x86 HVM guests In-Reply-To: <20260414103327.7420-1-roger.pau@citrix.com> Message-ID: References: <20260414103327.7420-1-roger.pau@citrix.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-720697/1776197314-AE524CD1-A6F09630/0/0 X-purgate-type: clean X-purgate-size: 625 On Tue, 14 Apr 2026, Roger Pau Monne wrote: > Hello, > > When not emulating the TSC the guest time value calculated by using the > vCPU time info page in HVM mode would drift between time synchronization > intervals. First patch fixes the drift, second patch makes the > calculation of cpu_khz round up the value for better accuracy. > > Thanks, Roger. > > Roger Pau Monne (2): > x86/time: use native TSC scaling factors when TSC is not scaled > xen/cpu: round up cpu_khz calculations Thanks Roger, this fixed an outstanding bug I was seeing! Tested-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282080.1564758 (Exim 4.92) (envelope-from ) id 1wCkJF-0005Dc-Qt; Tue, 14 Apr 2026 20:24:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282080.1564758; Tue, 14 Apr 2026 20:24:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJF-0005DV-Mw; Tue, 14 Apr 2026 20:24:33 +0000 Received: by outflank-mailman (input) for mailman id 1282080; Tue, 14 Apr 2026 20:24:33 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJF-0005CU-8n for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:33 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJE-001nT3-26; Tue, 14 Apr 2026 20:24:32 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJE-0036wi-1I; Tue, 14 Apr 2026 20:24:32 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=hvfc6WY0pbSdLS2SJLE1D/glK/FsO9Y9J36uU8Z+6EY=; b=5VltWaQYTRHArNRQXpNj+qjEJJ HbSV/AXBfcZhwczUsUmhAv7f6ST+rdx1obUA1X9sc86DgII0rLppdPQRiAsUeQ5z57oKg1ABmJrmi p79pLpggf2RT4ei+vc/G88LWPiU4OdOBwgA1lUFJKB9sGIy+tIRtFs4ZL4JOnag1Dg5A=; Message-ID: <8cb4ca97-e605-4416-b532-a8df4816a0ee@xen.org> Date: Tue, 14 Apr 2026 15:15:38 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/23] xen/arm: vIOMMU: add generic vIOMMU framework Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > This patch adds basic framework for vIOMMU. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/arch/arm/dom0less-build.c | 2 + > xen/arch/arm/domain.c | 33 +++++++++++++ > xen/arch/arm/domain_build.c | 2 + > xen/arch/arm/include/asm/viommu.h | 70 ++++++++++++++++++++++++++++ > xen/drivers/passthrough/Kconfig | 5 ++ > xen/drivers/passthrough/arm/Makefile | 1 + > xen/drivers/passthrough/arm/viommu.c | 48 +++++++++++++++++++ > xen/include/public/arch-arm.h | 5 ++ > xen/include/public/domctl.h | 4 +- > 9 files changed, 168 insertions(+), 2 deletions(-) > create mode 100644 xen/arch/arm/include/asm/viommu.h > create mode 100644 xen/drivers/passthrough/arm/viommu.c > > diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c > index 4181c10538..067835e5d0 100644 > --- a/xen/arch/arm/dom0less-build.c > +++ b/xen/arch/arm/dom0less-build.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -317,6 +318,7 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node, > uint32_t val; > > d_cfg->arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE; > + d_cfg->arch.viommu_type = viommu_get_type(); > d_cfg->flags |= XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap; > > if ( domu_dt_sci_parse(node, d_cfg) ) > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index 94b9858ad2..241f87386b 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > #include > > #include "vpci.h" > @@ -550,6 +551,14 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) > return -EINVAL; > } > > + /* Check config structure padding */ > + if ( config->arch.pad ) > + { > + dprintk(XENLOG_INFO, > + "Invalid input config, padding must be zero\n"); > + return -EINVAL; > + } > + > /* Check feature flags */ > if ( sve_vl_bits > 0 ) > { > @@ -626,6 +635,21 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) > return -EINVAL; > } > > + if ( !(config->flags & XEN_DOMCTL_CDF_iommu) && > + config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > + { > + dprintk(XENLOG_INFO, > + "vIOMMU requested while iommu not enabled for domain\n"); > + return -EINVAL; > + } > + > + if ( config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > + { > + dprintk(XENLOG_INFO, > + "vIOMMU type requested not supported by the platform or Xen\n"); > + return -EINVAL; > + } > + > return sci_domain_sanitise_config(config); > } > > @@ -721,6 +745,9 @@ int arch_domain_create(struct domain *d, > if ( (rc = sci_domain_init(d, config)) != 0 ) > goto fail; > > + if ( (rc = domain_viommu_init(d, config->arch.viommu_type)) != 0 ) > + goto fail; > + > return 0; > > fail: > @@ -965,6 +992,7 @@ enum { > PROG_pci = 1, > PROG_sci, > PROG_tee, > + PROG_viommu, I am not entirely sure about the position. Is the intention to relinquish the viommu state *after* the devices are detached? If so, it would be better to move this call just after 'PROG_pci' and add a comment indicating the dependency. > PROG_xen, > PROG_page, > PROG_mapping, > @@ -1021,6 +1049,11 @@ int domain_relinquish_resources(struct domain *d) > if (ret ) > return ret; > > + PROGRESS(viommu): > + ret = viommu_relinquish_resources(d); > + if (ret ) > + return ret; > + > PROGRESS(xen): > ret = relinquish_memory(d, &d->xenpage_list); > if ( ret ) > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index e8795745dd..a51563ee3d 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -35,6 +35,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -1946,6 +1947,7 @@ void __init create_dom0(void) > dom0_cfg.arch.nr_spis = vgic_def_nr_spis(); > dom0_cfg.arch.tee_type = tee_get_type(); > dom0_cfg.max_vcpus = dom0_max_vcpus(); > + dom0_cfg.arch.viommu_type = viommu_get_type(); > > if ( iommu_enabled ) > dom0_cfg.flags |= XEN_DOMCTL_CDF_iommu; > diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/viommu.h > new file mode 100644 > index 0000000000..4598f543b8 > --- /dev/null > +++ b/xen/arch/arm/include/asm/viommu.h > @@ -0,0 +1,70 @@ > +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > +#ifndef __ARCH_ARM_VIOMMU_H__ > +#define __ARCH_ARM_VIOMMU_H__ > + > +#ifdef CONFIG_ARM_VIRTUAL_IOMMU > + > +#include > +#include > +#include > + > +struct viommu_ops { > + /* > + * Called during domain construction if toolstack requests to enable > + * vIOMMU support. > + */ > + int (*domain_init)(struct domain *d); > + > + /* > + * Called during domain destruction to free resources used by vIOMMU. > + */ > + int (*relinquish_resources)(struct domain *d); > +}; > + > +struct viommu_desc { > + /* vIOMMU domains init/free operations described above. */ > + const struct viommu_ops *ops; > + > + /* > + * ID of vIOMMU. Corresponds to xen_arch_domainconfig.viommu_type. > + * Should be one of XEN_DOMCTL_CONFIG_VIOMMU_xxx > + */ > + uint16_t viommu_type; Below, you define viommu_type as 'uint8_t'. So shouldn't this also be 'uint8_t'? > +}; > + > +int domain_viommu_init(struct domain *d, uint16_t viommu_type); > +int viommu_relinquish_resources(struct domain *d); > +uint16_t viommu_get_type(void); > + > +#else > + > +static inline uint8_t viommu_get_type(void) > +{ > + return XEN_DOMCTL_CONFIG_VIOMMU_NONE; > +} > + > +static inline int domain_viommu_init(struct domain *d, uint16_t viommu_type) > +{ > + if ( likely(viommu_type == XEN_DOMCTL_CONFIG_VIOMMU_NONE) ) > + return 0; > + > + return -ENODEV; > +} > + > +static inline int viommu_relinquish_resources(struct domain *d) > +{ > + return 0; > +} > + > +#endif /* CONFIG_ARM_VIRTUAL_IOMMU */ > + > +#endif /* __ARCH_ARM_VIOMMU_H__ */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kconfig > index b413c33a4c..3c174bc87b 100644 > --- a/xen/drivers/passthrough/Kconfig > +++ b/xen/drivers/passthrough/Kconfig > @@ -35,6 +35,11 @@ config IPMMU_VMSA > (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports stage 2 > translation table format and is able to use CPU's P2M table as is. > > +config ARM_VIRTUAL_IOMMU > + bool "Virtual IOMMU Support (UNSUPPORTED)" if UNSUPPORTED > + help > + Support virtual IOMMU infrastructure to implement vIOMMU. > + > endif > > config AMD_IOMMU > diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough/arm/Makefile > index c5fb3b58a5..c3783188e3 100644 > --- a/xen/drivers/passthrough/arm/Makefile > +++ b/xen/drivers/passthrough/arm/Makefile > @@ -2,3 +2,4 @@ obj-y += iommu.o iommu_helpers.o iommu_fwspec.o > obj-$(CONFIG_ARM_SMMU) += smmu.o > obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o > obj-$(CONFIG_ARM_SMMU_V3) += smmu-v3.o > +obj-$(CONFIG_ARM_VIRTUAL_IOMMU) += viommu.o > diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough/arm/viommu.c > new file mode 100644 > index 0000000000..7ab6061e34 > --- /dev/null > +++ b/xen/drivers/passthrough/arm/viommu.c > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > + > +#include > +#include > +#include > + > +#include > + > +const struct viommu_desc __read_mostly *cur_viommu; You don't seem to define 'cur_viommmu' in the header. So shouldn't this be 'static'? Also, AFAICT, 'cur_viommu' would be set only once at boot. So rather than using __read_mostly, you probably want to use '__ro_after_init'. > + > +int domain_viommu_init(struct domain *d, uint16_t viommu_type) > +{ > + if ( viommu_type == XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > + return 0; > + > + if ( !cur_viommu ) > + return -ENODEV; > + > + if ( cur_viommu->viommu_type != viommu_type ) > + return -EINVAL; > + > + return cur_viommu->ops->domain_init(d); > +} > + > +int viommu_relinquish_resources(struct domain *d) > +{ > + if ( !cur_viommu ) > + return 0; > + > + return cur_viommu->ops->relinquish_resources(d); > +} > + > +uint16_t viommu_get_type(void) > +{ > + if ( !cur_viommu ) > + return XEN_DOMCTL_CONFIG_VIOMMU_NONE; > + > + return cur_viommu->viommu_type; > +} > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index cd563cf706..d4953d40fd 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -330,6 +330,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); > #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 > #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 > > +#define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 > + > struct xen_arch_domainconfig { > /* IN/OUT */ > uint8_t gic_version; > @@ -355,6 +357,9 @@ struct xen_arch_domainconfig { > uint32_t clock_frequency; > /* IN */ > uint8_t arm_sci_type; > + /* IN */ > + uint8_t viommu_type; > + uint16_t pad; > }; > #endif /* __XEN__ || __XEN_TOOLS__ */ > > diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h > index 8f6708c0a7..23124547f3 100644 > --- a/xen/include/public/domctl.h > +++ b/xen/include/public/domctl.h > @@ -30,9 +30,9 @@ > * fields) don't require a change of the version. > * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! > * > - * Last version bump: Xen 4.19 > + * Last version bump: Xen 4.22 > */ > -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 > +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 > > /* > * NB. xen_domctl.domain is an IN/OUT parameter for this operation. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282079.1564748 (Exim 4.92) (envelope-from ) id 1wCkJD-0004zD-Jo; Tue, 14 Apr 2026 20:24:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282079.1564748; Tue, 14 Apr 2026 20:24:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJD-0004z6-Gs; Tue, 14 Apr 2026 20:24:31 +0000 Received: by outflank-mailman (input) for mailman id 1282079; Tue, 14 Apr 2026 20:24:29 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJB-0004z0-SP for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:29 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJB-001nSu-0Z; Tue, 14 Apr 2026 20:24:29 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJA-0036wi-36; Tue, 14 Apr 2026 20:24:29 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=JVdik3zfubZEJqj2xS+6s9d1Kw5jWMMJH4KgQvL21Oc=; b=YAcauW58vGNSbNj9xQqUAK1Z3q LBQn16esHGukWatzeK1GO5mLpcW6f6PO7lNyqhkNKoK2OB6xO0/EF10kaCknxL6x/X80dGVNS3koe 1BFMeHqpKygjAu4eJ8nfF8gQjNFvzgjVo9BGTIqt0XNsou4PGPCzgR+ue0mrwxiLulDo=; Message-ID: Date: Tue, 14 Apr 2026 15:06:42 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/23] xen/arm: smmuv3: Alloc io_domain for each device Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk References: <78e4f2e2c68cdb75aa1c0dd7e8b456c03aa2fe6f.1774918270.git.milan_djokic@epam.com> From: Julien Grall In-Reply-To: <78e4f2e2c68cdb75aa1c0dd7e8b456c03aa2fe6f.1774918270.git.milan_djokic@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > In current implementation io_domain is allocated once for each xen > domain as Stage2 translation is common for all devices in same xen > domain. > > Nested stage supports S1 and S2 configuration at the same time. Stage1 > translation will be different for each device as linux kernel will > allocate page-table for each device. > > Alloc io_domain for each device so that each device can have different > Stage-1 and Stage-2 configuration structure. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/drivers/passthrough/arm/smmu-v3.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index f9c6837919..19e55b6c9b 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -2809,11 +2809,13 @@ static struct arm_smmu_device *arm_smmu_get_by_dev(const struct device *dev) > static struct iommu_domain *arm_smmu_get_domain(struct domain *d, > struct device *dev) > { > + unsigned long flags; In Xen, we are trying to limit the scope of local variables. AFAICT, this is only used within the loop below. So this can be defined later. Same ... > struct iommu_domain *io_domain; > struct arm_smmu_domain *smmu_domain; > struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > struct arm_smmu_xen_domain *xen_domain = dom_iommu(d)->arch.priv; > struct arm_smmu_device *smmu = arm_smmu_get_by_dev(fwspec->iommu_dev); > + struct arm_smmu_master *master; ... here. Also, AFAICT, ``master`` is not meant ot be modified. So shouldn't this be 'const'? Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282082.1564766 (Exim 4.92) (envelope-from ) id 1wCkJK-0005T7-5J; Tue, 14 Apr 2026 20:24:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282082.1564766; Tue, 14 Apr 2026 20:24:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJK-0005Sy-2E; Tue, 14 Apr 2026 20:24:38 +0000 Received: by outflank-mailman (input) for mailman id 1282082; Tue, 14 Apr 2026 20:24:37 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJJ-0005SC-9G for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:37 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJI-001nTE-26; Tue, 14 Apr 2026 20:24:36 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJI-0036wi-1c; Tue, 14 Apr 2026 20:24:36 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=AHmYUvmIYyfh5dRdTCNsTASPX/XO0DclUvr2J8d1xqM=; b=lThJrqOcegsEXtTr6iPEIVDwSl AIg2Z01fKfPv9R6h+0nvE+Cj/4hW0RxrG3E1JeP947CLaXQlWpdNAX5hGFNY4VxRAvG6XhxGF4w+f W2zSDQI3bZq6zlaNb6f87neV/GjdgB2IGr/J7yRCdAIOVrQ93yVnwsuh/zqL5b1eHn+I=; Message-ID: Date: Tue, 14 Apr 2026 15:19:07 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/23] xen/arm: vIOMMU: add generic vIOMMU framework Content-Language: en-GB To: Luca Fancellu , Milan Djokic , Andrew Cooper Cc: "xen-devel@lists.xenproject.org" , Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <93490E9C-4D22-4EAB-965E-B20DA8189C60@arm.com> From: Julien Grall In-Reply-To: <93490E9C-4D22-4EAB-965E-B20DA8189C60@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/04/2026 19:41, Luca Fancellu wrote: > Hi Milan, > >> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c >> index 94b9858ad2..241f87386b 100644 >> --- a/xen/arch/arm/domain.c >> +++ b/xen/arch/arm/domain.c >> @@ -28,6 +28,7 @@ >> #include >> #include >> #include >> +#include >> #include >> >> #include "vpci.h" >> @@ -550,6 +551,14 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) >> return -EINVAL; >> } >> >> + /* Check config structure padding */ >> + if ( config->arch.pad ) >> + { >> + dprintk(XENLOG_INFO, >> + "Invalid input config, padding must be zero\n"); >> + return -EINVAL; >> + } >> + > > This feels ok but unrelated to the patch In general, we want to have padding explictly define and zeroed. I wouldn't mind if this is kept in this patch but this would need to be mentioned in the commit message. > , but also the text maybe should be something like “Invalid domain configuration during domain creation\n”. > >> /* Check feature flags */ >> if ( sve_vl_bits > 0 ) >> { >> @@ -626,6 +635,21 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) >> return -EINVAL; >> } >> >> + if ( !(config->flags & XEN_DOMCTL_CDF_iommu) && >> + config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE ) >> + { >> + dprintk(XENLOG_INFO, >> + "vIOMMU requested while iommu not enabled for domain\n"); >> + return -EINVAL; >> + } >> + >> + if ( config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE ) >> + { >> + dprintk(XENLOG_INFO, >> + "vIOMMU type requested not supported by the platform or Xen\n"); >> + return -EINVAL; >> + } >> + >> return sci_domain_sanitise_config(config); >> } >> >> @@ -721,6 +745,9 @@ int arch_domain_create(struct domain *d, >> if ( (rc = sci_domain_init(d, config)) != 0 ) >> goto fail; >> >> + if ( (rc = domain_viommu_init(d, config->arch.viommu_type)) != 0 ) >> + goto fail; >> + >> return 0; >> >> fail: >> @@ -965,6 +992,7 @@ enum { >> PROG_pci = 1, >> PROG_sci, >> PROG_tee, >> + PROG_viommu, >> PROG_xen, >> PROG_page, >> PROG_mapping, >> @@ -1021,6 +1049,11 @@ int domain_relinquish_resources(struct domain *d) >> if (ret ) >> return ret; >> >> + PROGRESS(viommu): >> + ret = viommu_relinquish_resources(d); >> + if (ret ) >> + return ret; >> + >> PROGRESS(xen): >> ret = relinquish_memory(d, &d->xenpage_list); >> if ( ret ) >> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c >> index e8795745dd..a51563ee3d 100644 >> --- a/xen/arch/arm/domain_build.c >> +++ b/xen/arch/arm/domain_build.c >> @@ -35,6 +35,7 @@ >> #include >> #include >> #include >> +#include > > NIT: In my local branch I’ve rebased this on top of new staging > >> >> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h >> index cd563cf706..d4953d40fd 100644 >> --- a/xen/include/public/arch-arm.h >> +++ b/xen/include/public/arch-arm.h >> @@ -330,6 +330,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); >> #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 >> #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 >> >> +#define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 >> + >> struct xen_arch_domainconfig { >> /* IN/OUT */ >> uint8_t gic_version; >> @@ -355,6 +357,9 @@ struct xen_arch_domainconfig { >> uint32_t clock_frequency; >> /* IN */ >> uint8_t arm_sci_type; >> + /* IN */ >> + uint8_t viommu_type; >> + uint16_t pad; > > Having the padding explicit feels ok to me, but I would rely on maintainer > choice. See above. To expand what I wrote, if we don't define the padding explicitly and then check against zero, then we can't re-use them without breaking the ABI. So... > >> }; >> #endif /* __XEN__ || __XEN_TOOLS__ */ >> >> diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h >> index 8f6708c0a7..23124547f3 100644 >> --- a/xen/include/public/domctl.h >> +++ b/xen/include/public/domctl.h >> @@ -30,9 +30,9 @@ >> * fields) don't require a change of the version. >> * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! >> * >> - * Last version bump: Xen 4.19 >> + * Last version bump: Xen 4.22 >> */ >> -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 >> +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 > > I don’t think the changes in this patch are breaking the ABI, so this should not be bumped; > said so, I would rely on @Andrew or another maintainer for this ... this is needed because older toolstack may not zero the field. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282083.1564776 (Exim 4.92) (envelope-from ) id 1wCkJS-0005od-E7; Tue, 14 Apr 2026 20:24:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282083.1564776; Tue, 14 Apr 2026 20:24:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJS-0005oQ-9W; Tue, 14 Apr 2026 20:24:46 +0000 Received: by outflank-mailman (input) for mailman id 1282083; Tue, 14 Apr 2026 20:24:44 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJQ-0005mB-Nd for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:44 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJQ-001nTb-1F; Tue, 14 Apr 2026 20:24:44 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJQ-0036wi-0F; Tue, 14 Apr 2026 20:24:44 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=y9Jy5pZT/zSrlNnVBifWKpQNbFOCzie1g4ZvyNRLRHY=; b=qE6DT/azrqQnsOwGlseeR9+lKy jB8R93UfI8s5smLGSC5n65lXfAKmdZ8uOiZMfcKqYbUkrnp2QN7JfVZ8ijL6dBxkPpDL2jz8gJdCQ 0CSrpri/qlWvjdxHhQj/u+1XemFdJ2TD416WpBvzeluY1SQX4U77PUq6fzrEYLmKwuBY=; Message-ID: <1dcec397-a265-4972-8f2c-fd10c6e0b6ad@xen.org> Date: Tue, 14 Apr 2026 16:09:33 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/23] xen/arm: vsmmuv3: Add dummy support for virtual SMMUv3 for guests Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <97aa20fdcec324bb58c6869ddcba5fcf29bf75b3.1774918270.git.milan_djokic@epam.com> From: Julien Grall In-Reply-To: <97aa20fdcec324bb58c6869ddcba5fcf29bf75b3.1774918270.git.milan_djokic@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > domain_viommu_init() will be called during domain creation and will add > the dummy trap handler for virtual IOMMUs for guests. > > A host IOMMU list will be created when host IOMMU devices are probed > and this list will be used to create the IOMMU device tree node for > dom0. For dom0, 1-1 mapping will be established between vIOMMU in dom0 > and physical IOMMU. > > For domUs, the 1-N mapping will be established between domU and physical > IOMMUs. A new area has been reserved in the arm guest physical map at > which the emulated vIOMMU node is created in the device tree. > > Also set the vIOMMU type to vSMMUv3 to enable vIOMMU framework to call > vSMMUv3 domain creation/destroy functions. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/arch/arm/domain.c | 3 +- > xen/arch/arm/include/asm/domain.h | 4 + > xen/arch/arm/include/asm/viommu.h | 20 ++++ > xen/drivers/passthrough/Kconfig | 8 ++ > xen/drivers/passthrough/arm/Makefile | 1 + > xen/drivers/passthrough/arm/smmu-v3.c | 7 ++ > xen/drivers/passthrough/arm/viommu.c | 30 ++++++ > xen/drivers/passthrough/arm/vsmmu-v3.c | 124 +++++++++++++++++++++++++ > xen/drivers/passthrough/arm/vsmmu-v3.h | 20 ++++ > xen/include/public/arch-arm.h | 7 +- > 10 files changed, 222 insertions(+), 2 deletions(-) > create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.c > create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.h > > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index 241f87386b..b982d79b3b 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -643,7 +643,8 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) > return -EINVAL; > } > > - if ( config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > + if ( config->arch.viommu_type != XEN_DOMCTL_CONFIG_VIOMMU_NONE && > + config->arch.viommu_type != viommu_get_type() ) > { > dprintk(XENLOG_INFO, > "vIOMMU type requested not supported by the platform or Xen\n"); > diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h > index 758ad807e4..61108d0068 100644 > --- a/xen/arch/arm/include/asm/domain.h > +++ b/xen/arch/arm/include/asm/domain.h > @@ -126,6 +126,10 @@ struct arch_domain > void *sci_data; > #endif > > +#ifdef CONFIG_ARM_VIRTUAL_IOMMU > + struct list_head viommu_list; /* List of virtual IOMMUs */ > +#endif > + > } __cacheline_aligned; > > struct arch_vcpu > diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/viommu.h > index 4598f543b8..2a6742de73 100644 > --- a/xen/arch/arm/include/asm/viommu.h > +++ b/xen/arch/arm/include/asm/viommu.h > @@ -5,9 +5,21 @@ > #ifdef CONFIG_ARM_VIRTUAL_IOMMU > > #include > +#include > #include > #include > > +extern struct list_head host_iommu_list; > + > +/* data structure for each hardware IOMMU */ > +struct host_iommu { > + struct list_head entry; > + const struct dt_device_node *dt_node; > + paddr_t addr; > + paddr_t size; > + uint32_t irq; You don't seem to use ``irq`` in this patch. What is this meant to be used for? > +}; > + > struct viommu_ops { > /* > * Called during domain construction if toolstack requests to enable > @@ -35,6 +47,8 @@ struct viommu_desc { > int domain_viommu_init(struct domain *d, uint16_t viommu_type); > int viommu_relinquish_resources(struct domain *d); > uint16_t viommu_get_type(void); > +void add_to_host_iommu_list(paddr_t addr, paddr_t size, > + const struct dt_device_node *node); > > #else > > @@ -56,6 +70,12 @@ static inline int viommu_relinquish_resources(struct domain *d) > return 0; > } > > +static inline void add_to_host_iommu_list(paddr_t addr, paddr_t size, > + const struct dt_device_node *node) > +{ > + return; > +} > + > #endif /* CONFIG_ARM_VIRTUAL_IOMMU */ > > #endif /* __ARCH_ARM_VIOMMU_H__ */ > diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kconfig > index 3c174bc87b..9c48e7415e 100644 > --- a/xen/drivers/passthrough/Kconfig > +++ b/xen/drivers/passthrough/Kconfig > @@ -40,6 +40,14 @@ config ARM_VIRTUAL_IOMMU > help > Support virtual IOMMU infrastructure to implement vIOMMU. > > +config VIRTUAL_ARM_SMMU_V3 > + bool "ARM Ltd. Virtual SMMUv3 Support (UNSUPPORTED)" > + depends on ARM_SMMU_V3 && ARM_VIRTUAL_IOMMU > + help > + Support for implementations of the virtual ARM System MMU architecture > + version 3. Virtual SMMUv3 is unsupported feature and should not be used > + in production. > + > endif > > config AMD_IOMMU > diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough/arm/Makefile > index c3783188e3..c8f0a5f802 100644 > --- a/xen/drivers/passthrough/arm/Makefile > +++ b/xen/drivers/passthrough/arm/Makefile > @@ -3,3 +3,4 @@ obj-$(CONFIG_ARM_SMMU) += smmu.o > obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o > obj-$(CONFIG_ARM_SMMU_V3) += smmu-v3.o > obj-$(CONFIG_ARM_VIRTUAL_IOMMU) += viommu.o > +obj-$(CONFIG_VIRTUAL_ARM_SMMU_V3) += vsmmu-v3.o > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index 19e55b6c9b..87612df21d 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -93,6 +93,7 @@ > #include > > #include "smmu-v3.h" > +#include "vsmmu-v3.h" > > #define ARM_SMMU_VTCR_SH_IS 3 > #define ARM_SMMU_VTCR_RGN_WBWA 1 > @@ -2727,6 +2728,9 @@ static int __init arm_smmu_device_probe(struct platform_device *pdev) > list_add(&smmu->devices, &arm_smmu_devices); > spin_unlock(&arm_smmu_devices_lock); > > + /* Add to host IOMMU list to initialize vIOMMU for dom0 */ The indentation looks odd. Is this correctly aligned? > + add_to_host_iommu_list(ioaddr, iosize, dev_to_dt(pdev)); > + > return 0; > > > @@ -3058,6 +3062,9 @@ static __init int arm_smmu_dt_init(struct dt_device_node *dev, > > platform_features &= smmu->features; > > + /* Set vIOMMU type to SMMUv3 */ > + vsmmuv3_set_type(); > + > return 0; > } > > diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough/arm/viommu.c > index 7ab6061e34..53ae46349a 100644 > --- a/xen/drivers/passthrough/arm/viommu.c > +++ b/xen/drivers/passthrough/arm/viommu.c > @@ -2,12 +2,42 @@ > > #include > #include > +#include > #include > > #include > > +/* List of all host IOMMUs */ > +LIST_HEAD(host_iommu_list); I don't quite follow why this is part of the common code. That said, why do we need to register the host IOMMU? Wouldn't it be simpler to go through the list of pIOMMU in the vSMMU v3 implementation? > + > const struct viommu_desc __read_mostly *cur_viommu; > > +/* Common function for adding to host_iommu_list */ > +void add_to_host_iommu_list(paddr_t addr, paddr_t size, > + const struct dt_device_node *node) Is this supposed to only be called during __init? If so, this will help to justify the ... > +{ > + struct host_iommu *iommu_data; > + > + iommu_data = xzalloc(struct host_iommu); > + if ( !iommu_data ) > + panic("vIOMMU: Cannot allocate memory for host IOMMU data\n"); ... panic(). If not, then this function needs to return an error. > + > + iommu_data->addr = addr; > + iommu_data->size = size; > + iommu_data->dt_node = node; > + iommu_data->irq = platform_get_irq(node, 0); > + if ( iommu_data->irq < 0 ) > + { > + gdprintk(XENLOG_ERR, > + "vIOMMU: Cannot find a valid IOMMU irq\n"); Shouldn't you free the allocated memory? That said, why is it ok to ignore the vIOMMU in this case? > + return; > + } > + > + printk("vIOMMU: Found IOMMU @0x%"PRIx64"\n", addr); > + > + list_add_tail(&iommu_data->entry, &host_iommu_list); > +} > + > int domain_viommu_init(struct domain *d, uint16_t viommu_type) > { > if ( viommu_type == XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrough/arm/vsmmu-v3.c > new file mode 100644 > index 0000000000..6b4009e5ef > --- /dev/null > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -0,0 +1,124 @@ > +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > + > +#include > +#include > +#include > +#include > + > +/* Struct to hold the vIOMMU ops and vIOMMU type */ > +extern const struct viommu_desc __read_mostly *cur_viommu; Why is this defined in the C file? Shouldn't this be defined in ``viomum.h``? That said, looking at the use, I think we want to introduce a helper to set the cur_viommu and not export ``cur_viommu``. > + > +struct virt_smmu { > + struct domain *d; > + struct list_head viommu_list; > +}; > + > +static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > + register_t r, void *priv) > +{ > + return IO_HANDLED; > +} > + > +static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, > + register_t *r, void *priv) > +{ > + return IO_HANDLED; > +} I undertand that both helpers are meant to be updated in a later patch. However, I think it makes quite difficult to know whether the code is complete by the end of the series. I would strongly recommend adding 'BUG_ON("unimplemented");' so we can easily grep whether there is anything missing by the end. > + > +static const struct mmio_handler_ops vsmmuv3_mmio_handler = { > + .read = vsmmuv3_mmio_read, > + .write = vsmmuv3_mmio_write, > +}; > + > +static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t size) > +{ > + struct virt_smmu *smmu; > + > + smmu = xzalloc(struct virt_smmu); > + if ( !smmu ) > + return -ENOMEM; > + > + smmu->d = d; > + > + register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); I can't seem to find a place where the number of handler supported is incremented (see domain_io_init()) for the vIOMMU. Are you sure we always have enough space today? > + > + /* Register the vIOMMU to be able to clean it up later. */ > + list_add_tail(&smmu->viommu_list, &d->arch.viommu_list); > + > + return 0; > +} > + > +int domain_vsmmuv3_init(struct domain *d) > +{ > + int ret; Coding style: newline missing. > + INIT_LIST_HEAD(&d->arch.viommu_list); > + > + if ( is_hardware_domain(d) ) > + { > + struct host_iommu *hw_iommu; > + > + list_for_each_entry(hw_iommu, &host_iommu_list, entry) > + { > + ret = vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size); > + if ( ret ) > + return ret; > + } > + } > + else > + { > + ret = vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_SIZE); > + if ( ret ) > + return ret; > + } > + > + return 0; > +} > + > +int vsmmuv3_relinquish_resources(struct domain *d) > +{ > + struct virt_smmu *pos, *temp; > + > + /* Cope with unitialized vIOMMU */ > + if ( list_head_is_null(&d->arch.viommu_list) ) > + return 0; > + > + list_for_each_entry_safe(pos, temp, &d->arch.viommu_list, viommu_list ) > + { > + list_del(&pos->viommu_list); > + xfree(pos); > + } > + > + return 0; > +} > + > +static const struct viommu_ops vsmmuv3_ops = { > + .domain_init = domain_vsmmuv3_init, > + .relinquish_resources = vsmmuv3_relinquish_resources, > +}; > + > +static const struct viommu_desc vsmmuv3_desc = { > + .ops = &vsmmuv3_ops, > + .viommu_type = XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3, > +}; > + > +void __init vsmmuv3_set_type(void) > +{ > + const struct viommu_desc *desc = &vsmmuv3_desc; > + > + if ( cur_viommu && (cur_viommu != desc) ) > + { > + printk("WARNING: Cannot set vIOMMU, already set to a different value\n"); > + return; > + } > + > + cur_viommu = desc; > +} > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.h b/xen/drivers/passthrough/arm/vsmmu-v3.h > new file mode 100644 > index 0000000000..e11f85b431 > --- /dev/null > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.h > @@ -0,0 +1,20 @@ > +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > +#ifndef __ARCH_ARM_VSMMU_V3_H__ > +#define __ARCH_ARM_VSMMU_V3_H__ > + > +#include > + > +#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3 > + > +void vsmmuv3_set_type(void); > + > +#else > + > +static inline void vsmmuv3_set_type(void) > +{ > + return; > +} > + > +#endif /* CONFIG_VIRTUAL_ARM_SMMU_V3 */ > + > +#endif /* __ARCH_ARM_VSMMU_V3_H__ */ > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index d4953d40fd..ebac02ed63 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -330,7 +330,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); > #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 > #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 > > -#define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 > +#define XEN_DOMCTL_CONFIG_VIOMMU_NONE 0 I am generally against trying to align values because this is just introducing unnecessary churn in the code. > +#define XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 1 > > struct xen_arch_domainconfig { > /* IN/OUT */ > @@ -456,6 +457,10 @@ typedef uint64_t xen_callback_t; > #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ > #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) > > +/* vsmmuv3 ITS mappings */ What is ITS stand for in this context? > +#define GUEST_VSMMUV3_BASE xen_mk_ullong(0x04040000) > +#define GUEST_VSMMUV3_SIZE xen_mk_ullong(0x00040000) If I am not mistaken, you are reserving 256KiB. However, looking at the SMMU spec (section 6.1, ARM IHI 0070 H.a), the minimum is 128 KiB. Are you intending to expose additional features? > + > /* > * 256 MB is reserved for VPCI configuration space based on calculation > * 256 buses x 32 devices x 8 functions x 4 KB = 256 MB Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282087.1564784 (Exim 4.92) (envelope-from ) id 1wCkJT-00063O-Kp; Tue, 14 Apr 2026 20:24:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282087.1564784; Tue, 14 Apr 2026 20:24:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJT-00063D-Gw; Tue, 14 Apr 2026 20:24:47 +0000 Received: by outflank-mailman (input) for mailman id 1282087; Tue, 14 Apr 2026 20:24:46 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJS-0005oE-5y for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:46 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJM-001nTQ-1v; Tue, 14 Apr 2026 20:24:40 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJM-0036wi-1G; Tue, 14 Apr 2026 20:24:40 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=hM9fqT/J7mb5lZTQsjxgjpy1ycoQF+7u90mM95CalWM=; b=Dm8u9zuf+yTX0fLInCjfU/PmV2 DqZjhx7HaqZmEJBzDsqTredSOH9YuXb9UOuAyQRViXz6wUbLiBanG6nc5zSQMvN8TZ9nZE0Ha2SK6 Rfulx3dPGtjWGTZfd/GD4+d6twJM02AXsbULOg07kJPVDCoLqYBus/IJnx4tXzk8rmPM=; Message-ID: <75f9ccb1-e7e8-419c-9359-7779c5662a02@xen.org> Date: Tue, 14 Apr 2026 15:26:14 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 02/27] xen/riscv: Implement construct_domain() Content-Language: en-GB To: Oleksii Kurochko , Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <3a86599284108e6f2a27488a03145f8dd1b71def.1773157782.git.oleksii.kurochko@gmail.com> <95fc62d9-cfd4-4b75-a9b0-7e90c9ba1095@gmail.com> <2926ad08-39c8-4559-bb40-7231c69d9a65@gmail.com> From: Julien Grall In-Reply-To: <2926ad08-39c8-4559-bb40-7231c69d9a65@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 09/04/2026 22:39, Oleksii Kurochko wrote: >>>>> +    BUG_ON(v->is_initialised); >>>>> + >>>>> +    kernel_load(kinfo); >>>>> +    initrd_load(kinfo, copy_to_guest_phys); >>>>> +    dtb_load(kinfo, copy_to_guest_phys); >>>> These all return void, despite this also being used for non-Dom0. Is it >>>> really fatal to a dom0less system if one out of many domains fail to be >>>> built? >>> For a dom0less system, my opinion is that it should not be fatal, it >>> should simply ignore a domain that fails to build and continue with the >>> rest. However, with the current common dom0less code it will just >>> panic(). This is a behavior I would like to change and it is on my TODO >>> list. >>> >>> Regarding the functions returning void, this is because all of them >>> currently call panic() on failure, which I expect will need to change in >>> order to ignore a domain that fails to build in dom0less mode. >>> >>> For the current implementation of the common dom0less code this is fine, >>> but I agree it should be addressed in a separate patch series. >>> >>>    Especially when, despite the name, there is a Dom0? >>> >>> For this case, a failure there should indeed be fatal, so panic() is >>> appropriate. >> I think you misunderstood. I wasn't referring to the building of Dom0 >> failing. Was rather emphasizing that when there is a Dom0, failure to >> create a DomU likely should even less so be fatal, as Dom0 could later >> rectify the situation. > > Oh, okay, then it is really less fatal if DomU creation will fail in the > case of Dom0. I am not sure I agree with this statement. The goal of dom0less is to not have a dom0 at all. So there is no way to rectify after the fact. At least on Arm, we took the stance that boot failures are fatal because this is a clear signal that something went wrong. It may be more difficult to notice if you continue to boot. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282089.1564793 (Exim 4.92) (envelope-from ) id 1wCkJV-0006KB-SR; Tue, 14 Apr 2026 20:24:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282089.1564793; Tue, 14 Apr 2026 20:24:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJV-0006K0-OO; Tue, 14 Apr 2026 20:24:49 +0000 Received: by outflank-mailman (input) for mailman id 1282089; Tue, 14 Apr 2026 20:24:48 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJU-0006Ev-EY for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:48 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJT-001nTl-2o; Tue, 14 Apr 2026 20:24:47 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJT-0036wi-2K; Tue, 14 Apr 2026 20:24:47 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=9YaZxjoKz18ZaT0K7IsqTa9f9VS7PwBgIblFZCsgu/c=; b=3vV5BhkS3eXiLHMLnktLSgq4hK /y4zHUPJ9mEJevevpbBBm8Aze90H9YZAv87xN8sf0V9jpMaYEa59jOa/OrTBvR1+ioXnK06wKd9xW szSCbYPlIT/RmsCQ6HvJi0/ydaR7vl92rMitSjsCowkvCWeXBTbWsbIaSaCK/RppOo9Y=; Message-ID: <4d00797b-fe24-43d6-9ada-42426bcdab30@xen.org> Date: Tue, 14 Apr 2026 16:18:11 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/23] xen/arm: vIOMMU: Add cmdline boot option "viommu = " Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <5d86efa38ca99439153822fa19064bda6843fdc2.1774918270.git.milan_djokic@epam.com> From: Julien Grall In-Reply-To: <5d86efa38ca99439153822fa19064bda6843fdc2.1774918270.git.milan_djokic@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > Add cmdline boot option "viommu = " to enable or disable the > virtual iommu support for guests on ARM (only viommu="smmuv3" supported > for now). In Xen terminology, 'guests' refers to domUs. IOW, this doesn't include dom0. Is this what you meant? If so, how would you enable it for dom0? That said, is there any particular reason why this can't be automatically enabled based on the SMMUv3 discovered? > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > docs/misc/xen-command-line.pandoc | 9 +++++++++ > xen/arch/arm/include/asm/viommu.h | 12 ++++++++++++ > xen/drivers/passthrough/arm/viommu.c | 11 +++++++++++ > xen/drivers/passthrough/arm/vsmmu-v3.c | 3 +++ > 4 files changed, 35 insertions(+) > > diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc > index 6c77129732..6531c2355c 100644 > --- a/docs/misc/xen-command-line.pandoc > +++ b/docs/misc/xen-command-line.pandoc > @@ -2850,6 +2850,15 @@ The optional `keep` parameter causes Xen to continue using the vga > console even after dom0 has been started. The default behaviour is to > relinquish control to dom0. > > +### viommu (arm) > +> `= ` > + > +> Default: `` > + > +Flag to enable or disable support for the virtual IOMMU for guests. Disabled by > +default. Enable by specifying target IOMMU type (if supported). Only "smmuv3" > +IOMMU emulation supported at this point. > + > ### viridian-spinlock-retry-count (x86) > > `= ` > > diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/viommu.h > index 2a6742de73..ed338fe0ec 100644 > --- a/xen/arch/arm/include/asm/viommu.h > +++ b/xen/arch/arm/include/asm/viommu.h > @@ -10,6 +10,7 @@ > #include > > extern struct list_head host_iommu_list; > +extern char viommu[]; > > /* data structure for each hardware IOMMU */ > struct host_iommu { > @@ -50,6 +51,12 @@ uint16_t viommu_get_type(void); > void add_to_host_iommu_list(paddr_t addr, paddr_t size, > const struct dt_device_node *node); > > +static always_inline bool is_viommu_enabled(void) Regardless what Luca wrote, why do we need to force "always_inline"? > +{ > + /* only smmuv3 emulation supported */ > + return !strcmp(viommu, "smmuv3"); > +} > + > #else > > static inline uint8_t viommu_get_type(void) > @@ -76,6 +83,11 @@ static inline void add_to_host_iommu_list(paddr_t addr, paddr_t size, > return; > } > > +static always_inline bool is_viommu_enabled(void) > +{ > + return false; > +} > + > #endif /* CONFIG_ARM_VIRTUAL_IOMMU */ > > #endif /* __ARCH_ARM_VIOMMU_H__ */ > diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough/arm/viommu.c > index 53ae46349a..5f5892fbb2 100644 > --- a/xen/drivers/passthrough/arm/viommu.c > +++ b/xen/drivers/passthrough/arm/viommu.c > @@ -3,6 +3,7 @@ > #include > #include > #include > +#include > #include > > #include > @@ -38,8 +39,18 @@ void add_to_host_iommu_list(paddr_t addr, paddr_t size, > list_add_tail(&iommu_data->entry, &host_iommu_list); > } > > +/* By default viommu is disabled. > + * If enabled, 'viommu' param indicates type (smmuv3 is only supported type atm) > + */ > +char __read_mostly viommu[10] = ""; > +string_param("viommu", viommu); > + > int domain_viommu_init(struct domain *d, uint16_t viommu_type) > { > + /* Enable viommu when it has been enabled explicitly (viommu="smmuv3"). */ > + if ( !is_viommu_enabled() ) > + return 0;> + > if ( viommu_type == XEN_DOMCTL_CONFIG_VIOMMU_NONE ) > return 0; > > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrough/arm/vsmmu-v3.c > index 6b4009e5ef..e36f200ba5 100644 > --- a/xen/drivers/passthrough/arm/vsmmu-v3.c > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -105,6 +105,9 @@ void __init vsmmuv3_set_type(void) > { > const struct viommu_desc *desc = &vsmmuv3_desc; > > + if ( !is_viommu_enabled() ) This is likely going to go wrong in the future if we add support for other vIOMMU in the future. If we decide to continue using the command line option (see above), you would want want an helper to return the selected emulation and check against SMMUv3 here. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282092.1564801 (Exim 4.92) (envelope-from ) id 1wCkJY-0006ef-8D; Tue, 14 Apr 2026 20:24:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282092.1564801; Tue, 14 Apr 2026 20:24:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJY-0006eQ-4k; Tue, 14 Apr 2026 20:24:52 +0000 Received: by outflank-mailman (input) for mailman id 1282092; Tue, 14 Apr 2026 20:24:50 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJW-0006Xg-RI for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:50 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJW-001nTv-1X; Tue, 14 Apr 2026 20:24:50 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJW-0036wi-16; Tue, 14 Apr 2026 20:24:50 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=QFBLfe5i/9JqZBRgUFAj7nWhiJfRTY56kNhSbwiwTQk=; b=0S9RfB0x6qrJPSFDae9jphUcrr nyjl6xNGf4BS8hZvn7h05Fc1npFScMmKPEJLlg7f+PJdnIN45iYenX5xFcJbo/VaEFimam6Du+hPc Zq8clk9jv2X3Otb/auFuSMV6psCOjfTd6Nw6t7MPo4JZH65g6UBN/wKN5zq3wjeTYuVo=; Message-ID: <6d1806aa-b009-407a-9a7a-476f9f4deb70@xen.org> Date: Tue, 14 Apr 2026 17:10:37 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 08/23] xen/arm: vsmmuv3: Add support for registers emulation Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: <25adb33c4be3932c2d946cf7757c933eb042476c.1774918270.git.milan_djokic@epam.com> From: Julien Grall In-Reply-To: <25adb33c4be3932c2d946cf7757c933eb042476c.1774918270.git.milan_djokic@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > Add initial support for various emulated registers for virtual SMMUv3 > for guests and also add support for virtual cmdq and eventq. > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/drivers/passthrough/arm/smmu-v3.h | 6 + > xen/drivers/passthrough/arm/vsmmu-v3.c | 286 +++++++++++++++++++++++++ > 2 files changed, 292 insertions(+) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h > index 3fb13b7e21..fab4fd5a26 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.h > +++ b/xen/drivers/passthrough/arm/smmu-v3.h > @@ -60,6 +60,12 @@ > #define IDR5_VAX GENMASK(11, 10) > #define IDR5_VAX_52_BIT 1 > > +#define ARM_SMMU_IIDR 0x18 > +#define IIDR_PRODUCTID GENMASK(31, 20) > +#define IIDR_VARIANT GENMASK(19, 16) > +#define IIDR_REVISION GENMASK(15, 12) > +#define IIDR_IMPLEMENTER GENMASK(11, 0) > + > #define ARM_SMMU_CR0 0x20 > #define CR0_ATSCHK (1 << 4) > #define CR0_CMDQEN (1 << 3) > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrough/arm/vsmmu-v3.c > index e36f200ba5..3ae1e62a50 100644 > --- a/xen/drivers/passthrough/arm/vsmmu-v3.c > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -3,25 +3,307 @@ > #include > #include > #include > +#include vgic-emul.h is intended to only be used in the vGIC code. I am fine if you want to use it in vsmmu-v3.c but it needs to be renamed. Maybe to vdev-emul.h. > #include > +#include > + > +#include "smmu-v3.h" > + > +/* Register Definition */ > +#define ARM_SMMU_IDR2 0x8 > +#define ARM_SMMU_IDR3 0xc > +#define ARM_SMMU_IDR4 0x10 > +#define IDR0_TERM_MODEL (1 << 26) > +#define IDR3_RIL (1 << 10) > +#define CR0_RESERVED 0xFFFFFC20 AFAIU, this is covering all the bits defined by the SMMU spec. But some of them are optional. Does this mean we will expose those optional features? > +#define SMMU_IDR1_SIDSIZE 16 > +#define SMMU_CMDQS 19 Can you add some details how you decided the size of the command and ... > +#define SMMU_EVTQS 19 ... even queues? > +#define DWORDS_BYTES 8 > +#define ARM_SMMU_IIDR_VAL 0x12 I am not sure which implementer this is referring to. But how do you plan to handle errata? Are we sure they can always be handled by Xen? > > /* Struct to hold the vIOMMU ops and vIOMMU type */ > extern const struct viommu_desc __read_mostly *cur_viommu; > > +/* virtual smmu queue */ > +struct arm_vsmmu_queue { > + uint64_t q_base; /* base register */ > + uint32_t prod; > + uint32_t cons; > + uint8_t ent_size; > + uint8_t max_n_shift; > +}; > + > struct virt_smmu { > struct domain *d; > struct list_head viommu_list; > + uint8_t sid_split; > + uint32_t features; > + uint32_t cr[3]; > + uint32_t cr0ack; > + uint32_t gerror; > + uint32_t gerrorn; > + uint32_t strtab_base_cfg; > + uint64_t strtab_base; > + uint32_t irq_ctrl; > + uint64_t gerror_irq_cfg0; > + uint64_t evtq_irq_cfg0; > + struct arm_vsmmu_queue evtq, cmdq; > }; > > static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > register_t r, void *priv) > { > + struct virt_smmu *smmu = priv; > + uint64_t reg; > + uint32_t reg32; Looking at this helper and the read one, I am bit surprised there is no lock taken nor we check the access size. Can you explain why? For instance, we should not allow 64-bit access on 32-bit register. The rest of the size (8-bit and 16-bit) is IMP DEFINED so it may be easier just not allow them. > + > + switch ( info->gpa & 0xffff ) > + { > + case VREG32(ARM_SMMU_CR0): > + reg32 = smmu->cr[0];> + vreg_reg32_update(®32, r, info); > + smmu->cr[0] = reg32; > + smmu->cr0ack = reg32 & ~CR0_RESERVED; > + break; > + > + case VREG32(ARM_SMMU_CR1): > + reg32 = smmu->cr[1]; > + vreg_reg32_update(®32, r, info); > + smmu->cr[1] = reg32; > + break; > + > + case VREG32(ARM_SMMU_CR2): > + reg32 = smmu->cr[2]; > + vreg_reg32_update(®32, r, info); > + smmu->cr[2] = reg32; > + break; > + > + case VREG64(ARM_SMMU_STRTAB_BASE): Looking at the SMMU spec (6.3.24 in ARM IHI 0070 H.a), the behavior of writing to the register is constrained unpredictable before SMMUv3.2, but after it should be ignored if SMMU_CR0.SMMUEN == 1. So this implementation would not be valid for SMMUv3.2 and later. For convenience it would be best to just ignore the write (which is also valid for SMMUv3.1 and ealier). > + reg = smmu->strtab_base; > + vreg_reg64_update(®, r, info); > + smmu->strtab_base = reg; > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): Similar to above, there are some conditions when this field can be written (see 6.3.25). > + reg32 = smmu->strtab_base_cfg; > + vreg_reg32_update(®32, r, info); > + smmu->strtab_base_cfg = reg32; > + > + smmu->sid_split = FIELD_GET(STRTAB_BASE_CFG_SPLIT, reg32); The information for sid_split is already stored in ``smmu->strtab_base_cfg``. So why do we need to store it differently? > + smmu->features |= STRTAB_BASE_CFG_FMT_2LVL; I haven't checked the rest of the code yet. But from the name, I would assume it indicates whether 2-level stream table is supported. From my understanding of the specification, this is selectable by the guest OS. So why is this unconditionally set? > + break; > + > + case VREG32(ARM_SMMU_CMDQ_BASE): Similar to above, there are some condition when this field is RO. > + reg = smmu->cmdq.q_base; > + vreg_reg64_update(®, r, info); > + smmu->cmdq.q_base = reg; > + smmu->cmdq.max_n_shift = FIELD_GET(Q_BASE_LOG2SIZE, smmu->cmdq.q_base); > + if ( smmu->cmdq.max_n_shift > SMMU_CMDQS ) > + smmu->cmdq.max_n_shift = SMMU_CMDQS; > + break; > + > + case VREG32(ARM_SMMU_CMDQ_PROD): > + reg32 = smmu->cmdq.prod; > + vreg_reg32_update(®32, r, info); > + smmu->cmdq.prod = reg32; AFAIU, this implementation is not yet complete. If so, it would be good to mark it as such with a comment of BUG_ON("Not yet implemented"). Same for everywhere in this file and the rest of the series. > + break; > + > + case VREG32(ARM_SMMU_CMDQ_CONS): > + reg32 = smmu->cmdq.cons; > + vreg_reg32_update(®32, r, info); > + smmu->cmdq.cons = reg32; > + break; > + > + case VREG32(ARM_SMMU_EVTQ_BASE): > + reg = smmu->evtq.q_base; > + vreg_reg64_update(®, r, info); > + smmu->evtq.q_base = reg; > + smmu->evtq.max_n_shift = FIELD_GET(Q_BASE_LOG2SIZE, smmu->evtq.q_base); > + if ( smmu->cmdq.max_n_shift > SMMU_EVTQS ) > + smmu->cmdq.max_n_shift = SMMU_EVTQS; > + break; > + > + case VREG32(ARM_SMMU_EVTQ_PROD): > + reg32 = smmu->evtq.prod; > + vreg_reg32_update(®32, r, info); > + smmu->evtq.prod = reg32; > + break; > + > + case VREG32(ARM_SMMU_EVTQ_CONS): > + reg32 = smmu->evtq.cons; > + vreg_reg32_update(®32, r, info); > + smmu->evtq.cons = reg32; > + break; > + > + case VREG32(ARM_SMMU_IRQ_CTRL): > + reg32 = smmu->irq_ctrl; > + vreg_reg32_update(®32, r, info); > + smmu->irq_ctrl = reg32; > + break; > + > + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): > + reg = smmu->gerror_irq_cfg0; > + vreg_reg64_update(®, r, info); > + smmu->gerror_irq_cfg0 = reg; > + break; > + > + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): > + reg = smmu->evtq_irq_cfg0; > + vreg_reg64_update(®, r, info); > + smmu->evtq_irq_cfg0 = reg; > + break; > + > + case VREG32(ARM_SMMU_GERRORN): > + reg = smmu->gerrorn; > + vreg_reg64_update(®, r, info); > + smmu->gerrorn = reg; > + break; > + > + default: > + printk(XENLOG_G_ERR > + "%pv: vSMMUv3: unhandled write r%d offset %"PRIpaddr"\n", NIT: The vIOMMU is per-domain so it is sufficient to print "%pd". > + v, info->dabt.reg, (unsigned long)info->gpa & 0xffff); > + return IO_ABORT; Per section 6 of the SMMU: " For all pages except Page 1, undefined register locations are RES0. For Page 1, access to undefined/Reserved register locations is CONSTRAINED UNPREDICTABLE and an implementation has one of the following behaviors: [...] " Here you seem to implement page0 so the default case should be write ignore and therefore IO_HANDLED should be returned. BTW, you don't seem to handle page1. Is this going to be handled later on? > + } > + > return IO_HANDLED; > } > > static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info, > register_t *r, void *priv) > { > + struct virt_smmu *smmu = priv; > + uint64_t reg; > + > + switch ( info->gpa & 0xffff ) > + { > + case VREG32(ARM_SMMU_IDR0): > + reg = FIELD_PREP(IDR0_S1P, 1) | FIELD_PREP(IDR0_TTF, 2) | As the page-table will be used by the HW, shouldn't TTF reflect what the HW supports? This would allow the vIOMMU to work for 32-bit domains. > + FIELD_PREP(IDR0_COHACC, 0) | FIELD_PREP(IDR0_ASID16, 1) | Here you set COHACC to 0 which means the guest OS will have to clean the cache every time. This is safe everywhere, but it will have an impact on performance. I am not asking to allow COHACC when the HW supports it, but I think a TODO would be worth. For ASID16, shouldn't the value be based on the HW? As an aside, I guess we don't allow BTM because we only expose a single vSMMU? > + FIELD_PREP(IDR0_TTENDIAN, 0) | FIELD_PREP(IDR0_STALL_MODEL, 1) | For TTENDIAN, it is the same as above. For STALL_MODEL, I think 1 is ok. > + FIELD_PREP(IDR0_ST_LVL, 1) | FIELD_PREP(IDR0_TERM_MODEL, 1); Overall, it feels the value set in IDR0 and IDR1 (below) needs some comment. > + *r = vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IDR1): > + reg = FIELD_PREP(IDR1_SIDSIZE, SMMU_IDR1_SIDSIZE) | > + FIELD_PREP(IDR1_CMDQS, SMMU_CMDQS) | > + FIELD_PREP(IDR1_EVTQS, SMMU_EVTQS); > + *r = vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IDR2): > + goto read_reserved; > + > + case VREG32(ARM_SMMU_IDR3): > + reg = FIELD_PREP(IDR3_RIL, 0); I am not sure why we explicitely need to set RIL but not the other fields? > + *r = vreg_reg32_extract(reg, info);> + break; > + > + case VREG32(ARM_SMMU_IDR4): > + goto read_impl_defined; > + > + case VREG32(ARM_SMMU_IDR5): > + reg = FIELD_PREP(IDR5_GRAN4K, 1) | FIELD_PREP(IDR5_GRAN16K, 1) | > + FIELD_PREP(IDR5_GRAN64K, 1) | FIELD_PREP(IDR5_OAS, IDR5_OAS_48_BIT); Similar to the other fields in IDR0, isn't this based on what the HW supports? > + *r = vreg_reg32_extract(reg, info); > + break; > + > + case VREG32(ARM_SMMU_IIDR): > + *r = vreg_reg32_extract(ARM_SMMU_IIDR_VAL, info); > + break; > + > + case VREG32(ARM_SMMU_CR0): > + *r = vreg_reg32_extract(smmu->cr[0], info); > + break; > + > + case VREG32(ARM_SMMU_CR0ACK): > + *r = vreg_reg32_extract(smmu->cr0ack, info); > + break; > + > + case VREG32(ARM_SMMU_CR1): > + *r = vreg_reg32_extract(smmu->cr[1], info); > + break; > + > + case VREG32(ARM_SMMU_CR2): > + *r = vreg_reg32_extract(smmu->cr[2], info); > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE): > + *r = vreg_reg64_extract(smmu->strtab_base, info); > + break; > + > + case VREG32(ARM_SMMU_STRTAB_BASE_CFG): > + *r = vreg_reg32_extract(smmu->strtab_base_cfg, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_BASE): > + *r = vreg_reg64_extract(smmu->cmdq.q_base, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_PROD): > + *r = vreg_reg32_extract(smmu->cmdq.prod, info); > + break; > + > + case VREG32(ARM_SMMU_CMDQ_CONS): > + *r = vreg_reg32_extract(smmu->cmdq.cons, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_BASE): > + *r = vreg_reg64_extract(smmu->evtq.q_base, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_PROD): > + *r = vreg_reg32_extract(smmu->evtq.prod, info); > + break; > + > + case VREG32(ARM_SMMU_EVTQ_CONS): > + *r = vreg_reg32_extract(smmu->evtq.cons, info); > + break; > + > + case VREG32(ARM_SMMU_IRQ_CTRL): > + case VREG32(ARM_SMMU_IRQ_CTRLACK): > + *r = vreg_reg32_extract(smmu->irq_ctrl, info); > + break; > + > + case VREG64(ARM_SMMU_GERROR_IRQ_CFG0): > + *r = vreg_reg64_extract(smmu->gerror_irq_cfg0, info); > + break; > + > + case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0): > + *r = vreg_reg64_extract(smmu->evtq_irq_cfg0, info); > + break; > + > + case VREG32(ARM_SMMU_GERROR): > + *r = vreg_reg64_extract(smmu->gerror, info); > + break; > + > + case VREG32(ARM_SMMU_GERRORN): > + *r = vreg_reg64_extract(smmu->gerrorn, info); > + break; > + > + default: > + printk(XENLOG_G_ERR > + "%pv: vSMMUv3: unhandled read r%d offset %"PRIpaddr"\n", > + v, info->dabt.reg, (unsigned long)info->gpa & 0xffff); > + return IO_ABORT; > + } > + > + return IO_HANDLED; > + > + read_impl_defined: > + printk(XENLOG_G_DEBUG > + "%pv: vSMMUv3: RAZ on implementation defined register offset %"PRIpaddr"\n", > + v, info->gpa & 0xffff); > + *r = 0; > + return IO_HANDLED; > + > + read_reserved: > + printk(XENLOG_G_DEBUG > + "%pv: vSMMUv3: RAZ on reserved register offset %"PRIpaddr"\n", > + v, info->gpa & 0xffff); > + *r = 0; > return IO_HANDLED; > } > > @@ -39,6 +321,10 @@ static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t size) > return -ENOMEM; > > smmu->d = d; > + smmu->cmdq.q_base = FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_CMDQS); > + smmu->cmdq.ent_size = CMDQ_ENT_DWORDS * DWORDS_BYTES; > + smmu->evtq.q_base = FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS); > + smmu->evtq.ent_size = EVTQ_ENT_DWORDS * DWORDS_BYTES; I understand why we initialize ent_size. But I am not sure to understand why we need to initialize q_base. Can you clarify? > > register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); > Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 14 20:24:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 14 Apr 2026 20:24:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282096.1564811 (Exim 4.92) (envelope-from ) id 1wCkJa-0006y1-I6; Tue, 14 Apr 2026 20:24:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282096.1564811; Tue, 14 Apr 2026 20:24:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJa-0006x3-Dq; Tue, 14 Apr 2026 20:24:54 +0000 Received: by outflank-mailman (input) for mailman id 1282096; Tue, 14 Apr 2026 20:24:53 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCkJZ-0006tP-Ba for xen-devel@lists.xenproject.org; Tue, 14 Apr 2026 20:24:53 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCkJZ-001nU6-00; Tue, 14 Apr 2026 20:24:53 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCkJY-0036wi-2l; Tue, 14 Apr 2026 20:24:52 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=09cHly2BqHYGkH46vKnOx07jfMK6IV594uDYR5Bmswg=; b=dYthwWWTRu8t31JD9TpxyWNo7w QY+H99Bw3+5QPpBIWWOA3jlT+6y4HdchpYCCrbLgI465eaik4BAfQhHRZl0qpHiDjt/YLovGusv5G 0Am67lhsAW2Oeox2scP6A3dTT728WvBpdv9HozZRPc4cuIQVA3TwGj2tl05n1ks3DDI0=; Message-ID: <5aa739f7-dba0-42bf-beb3-594c53fdb868@xen.org> Date: Tue, 14 Apr 2026 17:18:19 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/23] xen/arm: vsmmuv3: Add support for cmdqueue handling Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Milan, On 31/03/2026 10:52, Milan Djokic wrote: > From: Rahul Singh > > Add support for virtual cmdqueue handling for guests This commit message is quite light. There are quite a few pitfalss with the command queue because it can be long running which require some explaining on the plan to handle it. If this is delayed for later, then it would be useful to document in the code what's missing so it is easier to know whether the vSMMUv3 implementation can be security supported (I assume this will be the goal). > > Signed-off-by: Rahul Singh > Signed-off-by: Milan Djokic > --- > xen/drivers/passthrough/arm/vsmmu-v3.c | 101 +++++++++++++++++++++++++ > 1 file changed, 101 insertions(+) > > diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrough/arm/vsmmu-v3.c > index 3ae1e62a50..02fe6a4422 100644 > --- a/xen/drivers/passthrough/arm/vsmmu-v3.c > +++ b/xen/drivers/passthrough/arm/vsmmu-v3.c > @@ -1,5 +1,6 @@ > /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ > > +#include > #include > #include > #include > @@ -25,6 +26,26 @@ > /* Struct to hold the vIOMMU ops and vIOMMU type */ > extern const struct viommu_desc __read_mostly *cur_viommu; > > +/* SMMUv3 command definitions */ > +#define CMDQ_OP_PREFETCH_CFG 0x1 > +#define CMDQ_OP_CFGI_STE 0x3 > +#define CMDQ_OP_CFGI_ALL 0x4 > +#define CMDQ_OP_CFGI_CD 0x5 > +#define CMDQ_OP_CFGI_CD_ALL 0x6 > +#define CMDQ_OP_TLBI_NH_ASID 0x11 > +#define CMDQ_OP_TLBI_NH_VA 0x12 > +#define CMDQ_OP_TLBI_NSNH_ALL 0x30 > +#define CMDQ_OP_CMD_SYNC 0x46 > + > +/* Queue Handling */ > +#define Q_BASE(q) ((q)->q_base & Q_BASE_ADDR_MASK) > +#define Q_CONS_ENT(q) (Q_BASE(q) + Q_IDX(q, (q)->cons) * (q)->ent_size) > +#define Q_PROD_ENT(q) (Q_BASE(q) + Q_IDX(q, (q)->prod) * (q)->ent_size) > + > +/* Helper Macros */ > +#define smmu_get_cmdq_enabled(x) FIELD_GET(CR0_CMDQEN, x) > +#define smmu_cmd_get_command(x) FIELD_GET(CMDQ_0_OP, x) > + > /* virtual smmu queue */ > struct arm_vsmmu_queue { > uint64_t q_base; /* base register */ > @@ -49,8 +70,80 @@ struct virt_smmu { > uint64_t gerror_irq_cfg0; > uint64_t evtq_irq_cfg0; > struct arm_vsmmu_queue evtq, cmdq; > + spinlock_t cmd_queue_lock; > }; > > +/* Queue manipulation functions */ > +static bool queue_empty(struct arm_vsmmu_queue *q) > +{ > + return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && > + Q_WRP(q, q->prod) == Q_WRP(q, q->cons); > +} > + > +static void queue_inc_cons(struct arm_vsmmu_queue *q) > +{ > + uint32_t cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; > + q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); > +} > + > +static void dump_smmu_command(uint64_t *command) > +{ > + gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n", > + smmu_cmd_get_command(command[0]), command[0], command[1]); I would consider using gprintk() because this could be useful even in non-production build. > +} > +static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu) > +{ > + struct arm_vsmmu_queue *q = &smmu->cmdq; > + struct domain *d = smmu->d; > + uint64_t command[CMDQ_ENT_DWORDS]; > + paddr_t addr; > + > + if ( !smmu_get_cmdq_enabled(smmu->cr[0]) ) > + return 0; > + > + while ( !queue_empty(q) ) > + {> + int ret; > + > + addr = Q_CONS_ENT(q); > + ret = access_guest_memory_by_gpa(d, addr, command, > + sizeof(command), false); > + if ( ret ) > + return ret; > + > + switch ( smmu_cmd_get_command(command[0]) ) > + { > + case CMDQ_OP_CFGI_STE: > + break; > + case CMDQ_OP_PREFETCH_CFG: > + case CMDQ_OP_CFGI_CD: > + case CMDQ_OP_CFGI_CD_ALL: > + case CMDQ_OP_CFGI_ALL: > + case CMDQ_OP_CMD_SYNC: Is this empty because there is nothing to do? Or is this empty because they are not yet implemented? > + break; > + case CMDQ_OP_TLBI_NH_ASID: > + case CMDQ_OP_TLBI_NSNH_ALL: > + case CMDQ_OP_TLBI_NH_VA: > + if ( !iommu_iotlb_flush_all(smmu->d, 1) ) This is quite a bigger hammer when the guest may only want to flush the S1 TLB for a single device. I am ok for now, but it would be good to add a TODO for optimizing it. > + break; > + default: > + gdprintk(XENLOG_ERR, "vSMMUv3: unhandled command\n"); > + dump_smmu_command(command); > + break; > + } > + > + if ( ret ) > + { > + gdprintk(XENLOG_ERR, > + "vSMMUv3: command error %d while handling command\n", > + ret); > + dump_smmu_command(command); > + } > + queue_inc_cons(q); > + } > + return 0; > +} > + > static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > register_t r, void *priv) > { > @@ -104,9 +197,15 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info, > break; > > case VREG32(ARM_SMMU_CMDQ_PROD): > + spin_lock(&smmu->cmd_queue_lock); > reg32 = smmu->cmdq.prod; > vreg_reg32_update(®32, r, info); > smmu->cmdq.prod = reg32; > + > + if ( arm_vsmmu_handle_cmds(smmu) ) > + gdprintk(XENLOG_ERR, "error handling vSMMUv3 commands\n"); > + > + spin_unlock(&smmu->cmd_queue_lock); > break; > > case VREG32(ARM_SMMU_CMDQ_CONS): > @@ -326,6 +425,8 @@ static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t size) > smmu->evtq.q_base = FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS); > smmu->evtq.ent_size = EVTQ_ENT_DWORDS * DWORDS_BYTES; > > + spin_lock_init(&smmu->cmd_queue_lock); > + > register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu); > > /* Register the vIOMMU to be able to clean it up later. */ Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Apr 15 02:21:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 02:21:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282156.1564820 (Exim 4.92) (envelope-from ) id 1wCpsh-0002q2-Si; Wed, 15 Apr 2026 02:21:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282156.1564820; Wed, 15 Apr 2026 02:21:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCpsh-0002pu-Nu; Wed, 15 Apr 2026 02:21:31 +0000 Received: by outflank-mailman (input) for mailman id 1282156; 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Or asked differently, again: Where's the >> virtualization, >> i.e. the abstraction away from host properties? > > With the current use case it was easier to choose such approach then > provide the full abstraction. BUt specifically here even with the current approach there is no too much sense to check MMIO of real APLIC. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 15 07:50:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 07:50:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282199.1564850 (Exim 4.92) (envelope-from ) id 1wCv0k-0007uU-4G; Wed, 15 Apr 2026 07:50:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282199.1564850; Wed, 15 Apr 2026 07:50:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCv0k-0007uN-1k; Wed, 15 Apr 2026 07:50:10 +0000 Received: by outflank-mailman (input) for mailman id 1282199; Wed, 15 Apr 2026 07:50:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCv0i-0007uH-4O for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 07:50:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCv0f-009SHF-CZ for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 09:50:06 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69df432e-5cb7-0a2a0a5109dd-0a2a450286d2-6 for ; Wed, 15 Apr 2026 09:50:06 +0200 Received: from [209.85.221.41] (helo=mail-wr1-f41.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69df432e-42fa-0a2a45020019-d155dd29a8bc-3 for ; Wed, 15 Apr 2026 09:50:06 +0200 Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-43d70c30767so2014780f8f.0 for ; Wed, 15 Apr 2026 00:50:06 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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As arch_domain_destroy() is stub at the moment, domain_vintc_deinit() isn't called. > >> @@ -87,3 +88,42 @@ int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >> return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, >> irq_ranges); >> } >> + >> +int __init domain_vintc_init(struct domain *d) > > The __init here and below is questionable again. This function is called during construction domain only, what happen when __init section exists. So it is okay to have __init here. Any use cases where it isn't true? It could be wrong for domain_vintc_deinit() as it could be called when __init section was freed. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 15 08:44:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 08:44:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282222.1564859 (Exim 4.92) (envelope-from ) id 1wCvrR-0006K9-95; Wed, 15 Apr 2026 08:44:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282222.1564859; Wed, 15 Apr 2026 08:44:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCvrR-0006K2-69; Wed, 15 Apr 2026 08:44:37 +0000 Received: by outflank-mailman (input) for mailman id 1282222; Wed, 15 Apr 2026 08:44:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCvrP-0006Jw-Fl for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OXkKdlGRfDshscfP" Content-Disposition: inline In-Reply-To: <20260414103327.7420-1-roger.pau@citrix.com> X-purgate-ID: tlsNG-ef75cf/1776242674-8AF4E41E-890966F3/0/0 X-purgate-type: clean X-purgate-size: 2192 --OXkKdlGRfDshscfP Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 15 Apr 2026 10:44:28 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Teddy Astie , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Alistair Francis , Connor Davis , Oleksii Kurochko Subject: Re: [PATCH 0/2] time: fix time accounting for x86 HVM guests On Tue, Apr 14, 2026 at 12:33:25PM +0200, Roger Pau Monne wrote: > Hello, >=20 > When not emulating the TSC the guest time value calculated by using the > vCPU time info page in HVM mode would drift between time synchronization > intervals. First patch fixes the drift, second patch makes the > calculation of cpu_khz round up the value for better accuracy. I confirm with with those patches, and without the other fix ("x86/time: do not kill calibration timer on suspend") the post-S3 issue is also gone! Tested-by: Marek Marczykowski-G=C3=B3recki --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --OXkKdlGRfDshscfP Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnfT+wACgkQ24/THMrX 1yzkOwf+MKW7KLhSeEiOfUGFN213ssCRXJNceF+o9Jd63DzpnbvLZgLl/jpu7oPb tBsuKDdTGi3UlVaPCvspWLxE1PEo8xRNa7WJXt+7TXstdvtbegP/iDyPtRd7o5Z2 pdWTjbfCkSNLCKjMaTUar/QahBwDxzF554j7qcd17ocY6UzopuPmfl4bo2EGp84a BWBiqncXwDQIEqDby7C8uShEpm5nEzXH9IpfSSfKItxMulh6x0ZPHR89YxDxaQhw 1+I6RIaeC9sY8kO8TGaiQXLyKqXzZLPkW76S/+WYiBDLySm5s8Eewny9bJu6G09V +aOvgZxUjFUZFE7wv7gFWBVWM0HO7g== =Ci4O -----END PGP SIGNATURE----- --OXkKdlGRfDshscfP-- From xen-devel-bounces@lists.xenproject.org Wed Apr 15 10:00:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 10:00:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282240.1564868 (Exim 4.92) (envelope-from ) id 1wCx2d-0007Uw-4c; Wed, 15 Apr 2026 10:00:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282240.1564868; Wed, 15 Apr 2026 10:00:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCx2d-0007Up-0l; Wed, 15 Apr 2026 10:00:15 +0000 Received: by outflank-mailman (input) for mailman id 1282240; Wed, 15 Apr 2026 10:00:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCx2c-0007Uj-4d for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 10:00:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCx2b-00CaMR-H5 for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 12:00:13 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69df61aa-bab6-0a2a0a5309dd-0a2a4505d82c-14 for ; Wed, 15 Apr 2026 12:00:13 +0200 Received: from [209.85.221.46] (helo=mail-wr1-f46.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69df61ad-3760-0a2a45050019-d155dd2ec1cf-3 for ; Wed, 15 Apr 2026 12:00:13 +0200 Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-43d04fc3bf2so3916226f8f.3 for ; Wed, 15 Apr 2026 03:00:13 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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These currently perform no >> additional work but allow the generic dom0less code to build and run >> on RISC-V. >> >> Introduce max_init_domid as a runtime variable rather than a constant >> so that it can be updated during dom0less domain creation. >> >> Provide missing helpers and definitions required by the domain >> construction code, > > I'm wondering about the splitting among patches: There's half a dozen > (effectively stub) functions which are added here, and then there is > the single init_vuart() which was split out into the earlier patch. > What's the pattern behind this, i.e. why isn't init_vuart() also > being added here? If it'll be more convenient I am okay to merge prev. patch with the current one. init_vuart() is in a separate patch as it has some useful functionality inside and thereby it will be more convenient to review. > >> including domain bitness helpers and the >> p2m_set_allocation() prototype. >> >> Additionally define the guest magic memory region in the public >> RISC-V interface. >> >> Signed-off-by: Oleksii Kurochko >> --- >> Open questions: >> - Shouldn't declaration/defintion of max_init_domid move to common code >> instead of having it for each architecture separately? If yes, then what >> would be the best place. > > What would you use to decide whether the declaration or #define is > needed? (Plausible headers to put it can surely be found: console.h, > domain.h, and perhaps more.) I thought about to wrap that with CONFIG_DOM0LESS_BOOT as the declaration is needed only for this case, for all other cases it is just #define. Or as an option we could always use declaration all the time. It won't increase size of Xen too much or decrease performance because of variable access. > >> --- a/xen/arch/riscv/include/asm/domain.h >> +++ b/xen/arch/riscv/include/asm/domain.h >> @@ -20,6 +20,14 @@ struct hvm_domain >> uint64_t params[HVM_NR_PARAMS]; >> }; >> >> +#ifdef CONFIG_RISCV_64 >> +#define is_32bit_domain(d) (0) >> +#define is_64bit_domain(d) (1) >> +#else >> +#define is_32bit_domain(d) (1) >> +#define is_64bit_domain(d) (0) >> +#endif > > First, please use true/false. Then, while I agree with the RV32 part, 32-bit > guests surely will need to be an option on a 64-bit hypervisor. Imo you'd > better introduced a field in struct arch_domain to carry that information > (or to derive it from) right away. That wouldn't be set to non-zero for the > time being, i.e. that same constant-true/false would still result. > > Otherwise I don't see why you use #ifdef; you could then have things > simpler as > > #define is_32bit_domain(d) IS_ENABLED(CONFIG_RISCV_32) > #define is_64bit_domain(d) IS_ENABLED(CONFIG_RISCV_64) > > (but I specifically don't recommend going this route). I will introduce a type in struct arch_domain then. > >> --- a/xen/include/public/arch-riscv.h >> +++ b/xen/include/public/arch-riscv.h >> @@ -58,6 +58,9 @@ typedef uint64_t xen_ulong_t; >> #define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE } >> #define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE } >> >> +#define GUEST_MAGIC_BASE xen_mk_ullong(0x39000000) >> +#define GUEST_MAGIC_SIZE xen_mk_ullong(0x01000000) > > What is this, and why does it need putting in the public interface? In other patch series such related things will live in asm/guest-layout.h. It will be moved there after rebase on top of that patch series. It is needed now only for common dom0less code compilation as at the moment we don't use xenstore pages for dom0less. But generally it is region which is used to allocate "magic pages" -special pages that facilitate communication between the guest and the Xen hypervisor such as Console, XenStore pages etc. I have in my TODO to understand how to remove requirement to have this fixed region from dom0less common code. Plus > how come the numbers are exactly the same as what Arm uses? It could be different. But this region is free for RISC-V too so it is fine to re-use. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 15 10:28:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 10:28:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282253.1564876 (Exim 4.92) (envelope-from ) id 1wCxUF-000262-Ag; Wed, 15 Apr 2026 10:28:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282253.1564876; Wed, 15 Apr 2026 10:28:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCxUF-00025v-86; Wed, 15 Apr 2026 10:28:47 +0000 Received: by outflank-mailman (input) for mailman id 1282253; Wed, 15 Apr 2026 10:28:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wCxUD-00025W-RH for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 10:28:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCxUC-005mFT-Df for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 12:28:44 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69df6856-e002-0a2a0a5209dd-0a2a45088a96-26 for ; Wed, 15 Apr 2026 12:28:44 +0200 Received: from [209.85.221.41] (helo=mail-wr1-f41.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69df685c-fab6-0a2a45080019-d155dd29b0c7-3 for ; Wed, 15 Apr 2026 12:28:44 +0200 Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-43cf8fe9c2aso4132735f8f.2 for ; Wed, 15 Apr 2026 03:28:44 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Instead add __read_mostly, like > Arm has it? Then I expect it will fail to compile as setup.c should contain only __init data. So the we have to remove or __read_mostly or put max_init_domid to different file. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282282.1564919 (Exim 4.92) (envelope-from ) id 1wCyYg-0002vK-B9; Wed, 15 Apr 2026 11:37:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282282.1564919; Wed, 15 Apr 2026 11:37:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyYg-0002uj-1q; Wed, 15 Apr 2026 11:37:26 +0000 Received: by outflank-mailman (input) for mailman id 1282282; Wed, 15 Apr 2026 11:37:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyYe-0002dH-Li for xen-devel@lists.xenproject.org; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: [PATCH 4/6] xen/dt-overlay: fix silent success in dt_overlay_remove_node Date: Wed, 15 Apr 2026 13:36:58 +0200 Message-ID: <20260415113700.107915-5-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415113700.107915-1-michal.orzel@amd.com> References: <20260415113700.107915-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|CH3PR12MB8510:EE_ X-MS-Office365-Filtering-Correlation-Id: e6a0a1e9-c4d6-4cfd-656d-08de9ae35982 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 93CgH3e2sS/b2ZGNQk5HLUMslz1U3svMNW24DSv+ZyTldX8rcOdDCBVPywxARZ3WkIqFxatrGRzTd8JjN8//Rs9hBtvhoAgyRgxP6DIYJj6wwIZ33yT/+s4LD/jUDDNqAKxQWewm1pz17IkPyKYduMgmbMG6798AuDqBgZoLjUPkq+UzYFaJQY8lCMUOKIhovOKhl93J3p5aFXqkdzdz74waqTXj3pOxgnyCwjhmUsrRKGU7qk6vYBuFpENz3wBcsZQoICkdQ0FeiEJBC7FTeuq+9hryJcDJcA/4ikfUonCT9iDRIan4S5Muu50QNk/Sfhl2Vn2VjMfRo67lMlAxfigGgb1Qs/Q8VGMmMzjILD2hXNyEo+M2ZA9fvctLi0X+exs2puHyxfVGOqJ0rYaaJ1FtX/kQO7oI9AKw8QPKqtsW19ceYTgG9Egv5Wjz4v/g2P7nR6p/ui70u2CVXBIBvsIEUOrerztocIHFkXvld+L3KvVIoKOZV17x3vKo9RHMGiLNZpHY9r+BlnTRyYdTMEdqEg2Ek2mMPUEZ6y8OjGMgSvc+hsZy5NoJEyWXd/Tb7DemHtbsz2w2leVgXNH7+N2GFNsrcG06mXB38TMF+teHHQYKeo85rmM8cAeZNBBGrrZ/C6f9d08LYzbvCp6QWOmCGUBAKgZG5wYx9wkrM2XGf7LTkO8Tcmokyba7ScPKzf6+94T+k6MbmYXbKnPTOZXBiAchoSwrZ90IwyuzeVDoZWm850qMmo7PqvTpOKVHV5ajPFTfHZUNeuM3zM1GNw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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The loop simply exits without matching and falls through to "return 0", making the caller believe the node was successfully removed. Return -ENODEV after the loop when no match is found, and change the found-path from break to an explicit return 0 so the two outcomes are distinct. Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functionalities") Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index 0eed1532a10d..d3d4669718ac 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -125,11 +125,11 @@ static int dt_overlay_remove_node(struct dt_device_node *device_node) else np->allnext = np->allnext->allnext; - break; + return 0; } } - return 0; + return -ENODEV; } static int dt_overlay_add_node(struct dt_device_node *device_node, -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282278.1564886 (Exim 4.92) (envelope-from ) id 1wCyYc-0002D7-3t; Wed, 15 Apr 2026 11:37:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282278.1564886; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: B8V9olcV4lLe2Q9RJIU9ty4ecc7K3jrXDqk2Ktumxy3wO98G5dSZEXYARcm488HgYjxG033BBD6lFRCz/iNV0pMNAqEcoibM0m15GZ/9JD8owpKJ8AjokgaPXy/QmPZQiwXamGV6/5mG4pbotNGiUQjit/P0WLD4GOe3rBf8u95OaqltBjWvlfdgLIQGarcb8YmV/xtHT4sQXKbv8wfGAXFicIHZmKi5djeK/hLCmVEDSmwx3V9RwT97kP37Api88XMWhMvfYg8oYc5dsM3hVDYf3y8Bc+LY65SkGI2J5BLBwwzzfOMW8V7ycGMEtNTQFWuQjPJlVC9xZNhQK9c8eVcMxTkZ5RtbsGZb/aYizY3gqCrZl/ylbYagF0A61Yw+KyKjCDNAVDdTIblGmzeMFSvkSrtJR4Slsy85Bg5tnMZWQNNrjsOv+qAb6iU0WqwJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 11:37:12.3696 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 906a3078-f6b9-4451-71cc-08de9ae3560b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E80.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6789 X-purgate-ID: tlsNG-d25034/1776253038-FD756A3D-E1C80DDB/0/0 X-purgate-type: clean X-purgate-size: 1409 I don't like the state this feature is in right now. While the feature, even in Linux is quite fragile, I investigated quite a lot of corner cases and many issues are present due to the fact that we support a weird combination of ADD/REMOVE + ATTACH without DETACH. Focusing on fixing issues and implementing DETACH is not an easy task now. REMOVE handles things that should really be done by DETACH. I think that the best move forward would be to strip the REMOVE operation from the dt-overlay subsystem (I would preserve ABI). This would eliminate the buggy, incomplete teardown code and leave a clean ADD+ATTACH surface to later build DETACH and a proper REMOVE on top of. Thoughts? The removal of REMOVE could be done in this release, not to carry on the buggy code. I tested this series with the AMD SW/HW stack. Michal Orzel (6): xen/dt-overlay: fix double-free of rangesets on attach failure xen/dt-overlay: fix rangeset leak and dead code in domctl path xen/dt-overlay: check overlay size before memcmp in tracker lookup xen/dt-overlay: fix silent success in dt_overlay_remove_node xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info xen/dt-overlay: attach resources for child nodes in overlay xen/common/device-tree/dt-overlay.c | 120 ++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 15 deletions(-) -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282279.1564890 (Exim 4.92) (envelope-from ) id 1wCyYc-0002GC-Ad; Wed, 15 Apr 2026 11:37:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282279.1564890; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HcZupUjCihrhH4fumGKyczgJktfm1ndcrphTiFO0/vw=; b=uyGGa5fOADXzEn8OZWcudjuuIBd3hc72vx5piG7laL4bkxiUIJQSciwRe9U+hPRxe3L1xczBYPqiKYq0ETJ93y7n4N2nGJeGNNOPcJOwMLg/aUer4AXiGAhpBFo5F7m4FfhIVvmgJJbQh/76X7OLIO2r2tj67z4sCHIJrjdyhkk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Gyujeong Jin Subject: [PATCH 1/6] xen/dt-overlay: fix double-free of rangesets on attach failure Date: Wed, 15 Apr 2026 13:36:55 +0200 Message-ID: <20260415113700.107915-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415113700.107915-1-michal.orzel@amd.com> References: <20260415113700.107915-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E80:EE_|CH3PR12MB9729:EE_ X-MS-Office365-Filtering-Correlation-Id: d43d5f58-3a0a-4e4d-6356-08de9ae35720 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|22082099003|56012099003|18002099003; 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A subsequent handle_remove_overlay_nodes() for the same overlay will call rangeset_consume_ranges() on freed memory followed by a second rangeset_destroy(), resulting in use-after-free and double-free. NULL the pointers after rangeset_destroy() so that remove_nodes() and handle_remove_overlay_nodes() skip the stale entries. Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains") Reported-by: Gyujeong Jin Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index d184186c015e..6fa07dbf42a5 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -910,7 +910,9 @@ static long handle_attach_overlay_nodes(struct domain *d, if ( entry ) { rangeset_destroy(entry->irq_ranges); + entry->irq_ranges = NULL; rangeset_destroy(entry->iomem_ranges); + entry->iomem_ranges = NULL; } return rc; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282280.1564905 (Exim 4.92) (envelope-from ) id 1wCyYe-0002dI-Ih; Wed, 15 Apr 2026 11:37:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282280.1564905; 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If the input is larger, memcmp reads past the stored allocation. If smaller, a prefix match could falsely succeed. Compare fdt_totalsize() of the stored overlay against overlay_fdt_size first. Both values are validated by check_overlay_fdt() at their respective entry points, so no additional field in overlay_track is needed. Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functionalities") Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index 3853e6e347fe..0eed1532a10d 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -379,7 +379,8 @@ find_track_entry_from_tracker(const void *overlay_fdt, */ list_for_each_entry_safe( entry, temp, &overlay_tracker, entry ) { - if ( memcmp(entry->overlay_fdt, overlay_fdt, overlay_fdt_size) == 0 ) + if ( (fdt_totalsize(entry->overlay_fdt) == overlay_fdt_size) && + !memcmp(entry->overlay_fdt, overlay_fdt, overlay_fdt_size) ) { found_entry = true; break; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282284.1564931 (Exim 4.92) (envelope-from ) id 1wCyYh-0003KL-HR; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info Date: Wed, 15 Apr 2026 13:36:59 +0200 Message-ID: <20260415113700.107915-6-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415113700.107915-1-michal.orzel@amd.com> References: <20260415113700.107915-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E7D:EE_|BL4PR12MB9484:EE_ X-MS-Office365-Filtering-Correlation-Id: a3562573-1ea7-4114-f66a-08de9ae35ada X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|18002099003|56012099003; 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This fails for overlays using phandle-based targeting (target = <&label>) because DTC compiles these as unresolved fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to manually modify the dtbo (even for hwdom) to switch from target to target-phandle by manually inspecting also the host DTB. Introduce overlay_get_target_path() which directly handles the two targeting cases that occur before fixup resolution: - target-path: the string property is returned directly. - target = <&label>: the label is found in the overlay's __fixups__ node, then resolved to a path via the base DTB's __symbols__ node. Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 65 ++++++++++++++++++++++++++--- 1 file changed, 59 insertions(+), 6 deletions(-) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index d3d4669718ac..a0dee7edb7e5 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -286,6 +286,63 @@ static unsigned int overlay_node_count(const void *overlay_fdt) return num_overlay_nodes; } +/* + * Resolve the target path for an overlay fragment. + * + * This is called before fdt_overlay_apply(), so phandle-based targets + * (target = <&label>) are still unresolved (compiled as 0xffffffff by DTC). + * Handle the two cases that actually occur: + * - target-path property: the path string is used directly, + * - target = <&label>: the label is looked up in the overlay's __fixups__ + * node, then resolved to a path via the base DTB's __symbols__ node. + * + * Returns a pointer into the FDT on success, NULL on failure. + */ +static const char *overlay_get_target_path(const void *fdt, const void *fdto, + int fragment) +{ + const char *path, *fragment_name; + int fixups_off, symbols_off, property; + int fragment_name_len; + + /* Try target-path first (string-based targeting) */ + path = fdt_getprop(fdto, fragment, "target-path", NULL); + if ( path ) + return path; + + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ + fixups_off = fdt_path_offset(fdto, "/__fixups__"); + if ( fixups_off < 0 ) + return NULL; + + symbols_off = fdt_path_offset(fdt, "/__symbols__"); + if ( symbols_off < 0 ) + return NULL; + + fragment_name = fdt_get_name(fdto, fragment, &fragment_name_len); + if ( !fragment_name ) + return NULL; + + fdt_for_each_property_offset(property, fdto, fixups_off) + { + const char *val, *label, *p; + int val_len; + + val = fdt_getprop_by_offset(fdto, property, &label, &val_len); + if ( !val ) + continue; + + /* Match entries of the form "/:target:0" */ + for ( p = val; p < (val + val_len); p += (strlen(p) + 1) ) + if ( p[0] == '/' && + !strncmp(p + 1, fragment_name, fragment_name_len) && + !strcmp(p + 1 + fragment_name_len, ":target:0") ) + return fdt_getprop(fdt, symbols_off, label, NULL); + } + + return NULL; +} + /* * overlay_get_nodes_info gets full name with path for all the nodes which * are in one level of __overlay__ tag. This is useful when checking node for @@ -298,7 +355,6 @@ static int overlay_get_nodes_info(const void *fdto, char **nodes_full_path) fdt_for_each_subnode(fragment, fdto, 0) { - int target; int overlay; int subnode; const char *target_path; @@ -307,11 +363,8 @@ static int overlay_get_nodes_info(const void *fdto, char **nodes_full_path) if ( overlay < 0 ) continue; - target = fdt_overlay_target_offset(device_tree_flattened, fdto, - fragment, &target_path); - if ( target < 0 ) - return target; - + target_path = overlay_get_target_path(device_tree_flattened, fdto, + fragment); if ( target_path == NULL ) return -EINVAL; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:37:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:37:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282286.1564940 (Exim 4.92) (envelope-from ) id 1wCyYk-0003f8-W4; Wed, 15 Apr 2026 11:37:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282286.1564940; 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Child nodes that have their own reg, interrupts, or iommus properties are never processed, so their IRQs are not routed, MMIO regions are not mapped, and IOMMU setup is skipped. Introduce handle_device_and_children() which recursively walks the subtree rooted at each overlay node and calls handle_device() on every descendant, ensuring all resources in the overlay are properly attached. Note that the attach error path has a pre-existing bug: on partial failure, the tracking rangesets are destroyed without first revoking the IRQ/MMIO permissions and IOMMU assignments that were already granted by the successful handle_device() calls. Add a TODO comment to flag this. Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 34 +++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index a0dee7edb7e5..b837f1112188 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -894,6 +894,30 @@ static long handle_add_overlay_nodes(void *overlay_fdt, return rc; } +static int handle_device_and_children(struct domain *d, + struct dt_device_node *dev, + p2m_type_t p2mt, + struct rangeset *iomem_ranges, + struct rangeset *irq_ranges) +{ + int rc; + struct dt_device_node *child; + + rc = handle_device(d, dev, p2mt, iomem_ranges, irq_ranges); + if ( rc ) + return rc; + + dt_for_each_child_node(dev, child) + { + rc = handle_device_and_children(d, child, p2mt, + iomem_ranges, irq_ranges); + if ( rc ) + return rc; + } + + return 0; +} + static long handle_attach_overlay_nodes(struct domain *d, const void *overlay_fdt, uint32_t overlay_fdt_size) @@ -951,8 +975,9 @@ static long handle_attach_overlay_nodes(struct domain *d, } write_lock(&dt_host_lock); - rc = handle_device(d, overlay_node, p2m_mmio_direct_c, - entry->iomem_ranges, entry->irq_ranges); + rc = handle_device_and_children(d, overlay_node, p2m_mmio_direct_c, + entry->iomem_ranges, + entry->irq_ranges); write_unlock(&dt_host_lock); if ( rc ) { @@ -968,6 +993,11 @@ static long handle_attach_overlay_nodes(struct domain *d, out: spin_unlock(&overlay_lock); + /* + * TODO: IRQ/MMIO permissions and IOMMU assignments granted by + * handle_device() before the failure are not revoked here. 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Jan Beulich Subject: [PATCH 2/6] xen/dt-overlay: fix rangeset leak and dead code in domctl path Date: Wed, 15 Apr 2026 13:36:56 +0200 Message-ID: <20260415113700.107915-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260415113700.107915-1-michal.orzel@amd.com> References: <20260415113700.107915-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E80:EE_|LV2PR12MB5824:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a18a0f7-b228-4b80-4af8-08de9ae357a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|22082099003|18002099003|56012099003; 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A repeated attach for the same overlay leaks the original pair. Reject the operation with -EEXIST if rangesets are already present. Also, dt_overlay_domctl() early-returns -EOPNOTSUPP for any operation other than ATTACH, making the if/else at the bottom unreachable. Remove the dead branch. Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains") Reported-by: Jan Beulich Signed-off-by: Michal Orzel --- xen/common/device-tree/dt-overlay.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index 6fa07dbf42a5..3853e6e347fe 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -861,6 +861,13 @@ static long handle_attach_overlay_nodes(struct domain *d, goto out; } + if ( entry->irq_ranges || entry->iomem_ranges ) + { + printk(XENLOG_ERR "Overlay is already attached\n"); + spin_unlock(&overlay_lock); + return -EEXIST; + } + entry->irq_ranges = rangeset_new(d, "Overlays: Interrupts", 0); if (entry->irq_ranges == NULL) { @@ -991,10 +998,7 @@ long dt_overlay_domctl(struct domain *d, struct xen_domctl_dt_overlay *op) return -EFAULT; } - if ( op->overlay_op == XEN_DOMCTL_DT_OVERLAY_ATTACH ) - ret = handle_attach_overlay_nodes(d, overlay_fdt, op->overlay_fdt_size); - else - ret = -EOPNOTSUPP; + ret = handle_attach_overlay_nodes(d, overlay_fdt, op->overlay_fdt_size); xfree(overlay_fdt); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:49:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:49:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282343.1564950 (Exim 4.92) (envelope-from ) id 1wCyk0-0007Cj-VK; Wed, 15 Apr 2026 11:49:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282343.1564950; Wed, 15 Apr 2026 11:49:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyk0-0007Cc-Rj; Wed, 15 Apr 2026 11:49:08 +0000 Received: by outflank-mailman (input) for mailman id 1282343; Wed, 15 Apr 2026 11:49:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyjz-0007CW-LF for xen-devel@lists.xenproject.org; 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Wed, 15 Apr 2026 04:49:04 -0700 (PDT) MIME-Version: 1.0 References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-2-michal.orzel@amd.com> In-Reply-To: <20260415113700.107915-2-michal.orzel@amd.com> From: Gyujeong Jin Date: Wed, 15 Apr 2026 20:48:53 +0900 X-Gm-Features: AQROBzDZ2_suPqDuYVx4ON47qTbGVxvMFSHBd9Ap8npzwo9pDkzE10NRof6f6hE Message-ID: Subject: Re: [PATCH 1/6] xen/dt-overlay: fix double-free of rangesets on attach failure To: Michal Orzel Cc: xen-devel@lists.xenproject.org, Stefano Stabellini , Julien Grall , Bertrand Marquis Content-Type: multipart/alternative; boundary="0000000000007995ca064f7e4d7f" X-purgate-ID: tlsNG-42698a/1776253746-F43D62A1-F419A566/0/0 X-purgate-type: clean X-purgate-size: 4671 --0000000000007995ca064f7e4d7f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks for your efforts. I=E2=80=99ve seen some advisories that received cve here. https://xenbits.xen.org/xsa/ Can I receive a cve for this report? Thanks. 2026=EB=85=84 4=EC=9B=94 15=EC=9D=BC (=EC=88=98) 20:37, Michal Orzel =EB=8B=98=EC=9D=B4 =EC=9E=91=EC=84=B1: > handle_attach_overlay_nodes() destroys the IRQ and IOMEM rangesets on > failure but leaves the pointers dangling in the tracker entry. A > subsequent handle_remove_overlay_nodes() for the same overlay will call > rangeset_consume_ranges() on freed memory followed by a second > rangeset_destroy(), resulting in use-after-free and double-free. > > NULL the pointers after rangeset_destroy() so that remove_nodes() and > handle_remove_overlay_nodes() skip the stale entries. > > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device > attachment to domains") > Reported-by: Gyujeong Jin > Signed-off-by: Michal Orzel > --- > xen/common/device-tree/dt-overlay.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/xen/common/device-tree/dt-overlay.c > b/xen/common/device-tree/dt-overlay.c > index d184186c015e..6fa07dbf42a5 100644 > --- a/xen/common/device-tree/dt-overlay.c > +++ b/xen/common/device-tree/dt-overlay.c > @@ -910,7 +910,9 @@ static long handle_attach_overlay_nodes(struct domain > *d, > if ( entry ) > { > rangeset_destroy(entry->irq_ranges); > + entry->irq_ranges =3D NULL; > rangeset_destroy(entry->iomem_ranges); > + entry->iomem_ranges =3D NULL; > } > > return rc; > -- > 2.43.0 > > --0000000000007995ca064f7e4d7f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
    Thanks for your efforts.

    I=E2=80=99ve seen some advisories that received cve here= .
    Can I receive a cve for this rep= ort?

    Thanks.
    <= br>
    2026=EB=85=84 4=EC=9B=94 15=EC=9D=BC (=EC=88=98) 20:37, Mic= hal Orzel <michal.orzel@amd.com<= /a>>=EB=8B=98=EC=9D=B4 =EC=9E=91=EC=84=B1:
    han= dle_attach_overlay_nodes() destroys the IRQ and IOMEM rangesets on
    failure but leaves the pointers dangling in the tracker entry. A
    subsequent handle_remove_overlay_nodes() for the same overlay will call
    rangeset_consume_ranges() on freed memory followed by a second
    rangeset_destroy(), resulting in use-after-free and double-free.

    NULL the pointers after rangeset_destroy() so that remove_nodes() and
    handle_remove_overlay_nodes() skip the stale entries.

    Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device at= tachment to domains")
    Reported-by: Gyujeong Jin <    wlsrbwjd7232@gmail.com>
    Signed-off-by: Michal Orzel <michal.orzel@amd.com>
    ---
    =C2=A0xen/common/device-tree/dt-overlay.c | 2 ++
    =C2=A01 file changed, 2 insertions(+)

    diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/d= t-overlay.c
    index d184186c015e..6fa07dbf42a5 100644
    --- a/xen/common/device-tree/dt-overlay.c
    +++ b/xen/common/device-tree/dt-overlay.c
    @@ -910,7 +910,9 @@ static long handle_attach_overlay_nodes(struct domain *= d,
    =C2=A0 =C2=A0 =C2=A0if ( entry )
    =C2=A0 =C2=A0 =C2=A0{
    =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rangeset_destroy(entry->irq_ranges); +=C2=A0 =C2=A0 =C2=A0 =C2=A0 entry->irq_ranges =3D NULL;
    =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rangeset_destroy(entry->iomem_ranges);=
    +=C2=A0 =C2=A0 =C2=A0 =C2=A0 entry->iomem_ranges =3D NULL;
    =C2=A0 =C2=A0 =C2=A0}

    =C2=A0 =C2=A0 =C2=A0return rc;
    --
    2.43.0

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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="anthony.perard@vates.tech" header.h="From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776253839; x=1776523839; bh=GCGte0Z3A7kTvS18fV4wo3myVXmVNIE4719dmtr62Y0=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Q4V7IjTnk/JsoSc9/BAmAURWO4Wr3bjPXoyLls88u3V52eVPlhVITGvL7+HCbag4d 85mtUVb+J8rmlhlmI8J+hQQQ66dHhZvBjf/DR2vwx+MWRbyhSO6+0tHqFubo8zL3XR kofeiLBgrOaBwWCyc10J+y4gg3wMztkHqFW1f9DmkZET+GfKR6uUnmMeMlPMQhQAUV QTZdrmSWtzpPa4GdWi6vMPRB7Y6X4CL1p2q3uCl2DSaiZexK+o3Eoflp2fOUf23Ruq lnXIn1iamPre9E413bhzTrJ15zb/sMWKO0dHptbSrzeiPcCtH1hMRm5TRkWdpKQ9fl YIXZC6f0Zs8HQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776253839; x=1776514339; i=anthony.perard@vates.tech; bh=GCGte0Z3A7kTvS18fV4wo3myVXmVNIE4719dmtr62Y0=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Ge0N67Uck/NbUZCNCkXqNqIUFYS9H6/unHpl2eDXICYaL0+1SEj06Iqi+ebkzei03 sUKipL9XVtgU13D1YjNx9e7JqDOXCsWkBubByYfAQc/8AzWo0h/J11Wb0OOVXB6n2E h4OrMLFjzfOvsKmbIFlCv1wOi4e5TOu70LneY16FZSl2v++gtJ+ioOiQbGYMC/ku9X ahp3IujpHyUvaXEKXp5P1k1H+EAtBkquJCewOI9rgnR4jsPiRTc5t76vg8UutUfUpR sdlNxR/ruSFVtTfD6ByQkO1pFlntplhhXY9nmDHXtEPOSeUpDcCe/1ehWCgi4g4GUe Z6Qv4wGaC7erQ== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20test-artifacts=20v3=2003/13]=20Add=20debian=20rootfs=20artifact?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776253838063 To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Andrew Cooper" , "Stefano Stabellini" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: References: In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.b04eb2f46eaf41bd866880f8e9a735d4?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 11:50:39 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776254111-B052B51B-E85556CC/0/0 X-purgate-type: clean X-purgate-size: 1415 I'm commenting on changes I found in the branch used by the pipeline linked in the cover leter, since there's no copy on the mailing list of the patch :-( (overzealous spam filter). > diff --git a/scripts/debian-rootfs.sh b/scripts/debian-rootfs.sh > new file mode 100755 > index 000000000000..7cb8a96e39c0 > --- /dev/null > +++ b/scripts/debian-rootfs.sh ... > +PKGS=( > + # System > + bridge-utils > + dropbear > + udev > + systemd-sysv > + iproute2 > + inetutils-ping > + util-linux > + cpio Is `cpio` going to be used in dom0? The alpine rootfs don't have it. > +# don't need persistent logging, avoid journal flush service > +rmdir var/log/journal I think this would better be done with: cat >> /etc/systemd/journald.conf.d/storage.conf < +# Create rootfs > +cd / > +{ > + PATHS="bin etc home init lib lib64 mnt opt root sbin srv tmp usr var" > + find $PATHS -print0 > + echo -ne "dev\0proc\0run\0sys\0" > +} | cpio -0 -H newc -o | gzip > "${COPYDIR}/rootfs.cpio.gz" You should add "-R0:0" to the `cpio` command, like we do for the alpine rootfs. Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 11:58:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 11:58:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282361.1564966 (Exim 4.92) (envelope-from ) id 1wCyt6-0000nD-Ts; Wed, 15 Apr 2026 11:58:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282361.1564966; Wed, 15 Apr 2026 11:58:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyt6-0000n6-RJ; Wed, 15 Apr 2026 11:58:32 +0000 Received: by outflank-mailman (input) for mailman id 1282361; Wed, 15 Apr 2026 11:58:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCyt5-0000n0-M1 for xen-devel@lists.xenproject.org; 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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776254182; x=1776524182; bh=WIWJlCYAKOt0EHTWZdN0VepA2MSlrAv0igbJ3uBehFg=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=FQRaEMZspkHw0E7oZGKsLJ+X6cyXylXGT60UsrNzgQ06REGJXpWYIJInvadwoJ/UC h3AfB4Omyb/RLVFOuV84MiQIO5bmNjIsuE8kQ/E1kNvw1m3bNCdXgQWqJ1V7kenffr b/I08Cz1VOhLFVQQgoWYBWNxfrN80J7nde1xnqoYyi1zmAOBQYtoKKn4BRL9YW2k0E CH/Mipav0KPQFFVUmprEi1DFnoGlp/PTxpPHcnNfVr74xJwRgE+3AZsIjW6d4RbK83 sm0cajmE+0fVYA1PfiEAm95tkk9BbvDHeU6njmXYRdgye70gx0YhCQ5DzAvDfoP/Hx LwSNbijU1roig== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776254182; x=1776514682; i=teddy.astie@vates.tech; bh=WIWJlCYAKOt0EHTWZdN0VepA2MSlrAv0igbJ3uBehFg=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=nfuSHcvY9Vpz4mWWc1r0kBUVcj772WAxm6nlGXzTIr7OlX64m0/76nn4JDzs26LvT WGQgVt5Jt5vWuetfAQlEoQDOcDFYF4PW1tSd/g7k/wobvkltMWYvDunBYpcBwFR9Ps dJ5hUIxof/4AL1hfLFe8Z1aCdcSz/kGmcVhGGL/i9rydsCdTC0ZGPx+ib9bhC/axAT eSYuo9LTRnIcS0m/TpTnih2QLUbMIIGSPro6w2j+IPoGGi7AHDZTkf25/yfXM3Ehv1 4DtwumLfdVBTVQg6YqmRPWqKkVuy5aOvkyOhUILxUciZPDwhw4tOMp63mEH3aAkLX/ tYTg8AlzKv1yA== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=201/6]=20xen/dt-overlay:=20fix=20double-free=20of=20rangesets=20on=20attach=20failure?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776254181615 Message-Id: <29f94a8b-1c5d-42b6-9887-4303ddf58bd0@vates.tech> To: "Gyujeong Jin" , "Michal Orzel" Cc: xen-devel@lists.xenproject.org, "Stefano Stabellini" , "Julien Grall" , "Bertrand Marquis" References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-2-michal.orzel@amd.com> In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.9c3c2a7e817948e4aa5e830b2a7d3782?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 11:56:22 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1776254310-BED4A0B1-88B86905/0/0 X-purgate-type: clean X-purgate-size: 2554 Le 15/04/2026 =C3=A0 13:51, Gyujeong Jin a =C3=A9crit=C2=A0: > Thanks for your efforts. > > I=E2=80=99ve seen some advisories that received cve here. > https://xenbits.xen.org/xsa/ > > Can I receive a cve for this report? > > Thanks. > Device-tree overlay is marked as "Experimental", hence it's not Security supported so no XSA would be issued, even if it it has security implications for the feature. I don't know regarding individual CVEs though. > 2026=EB=85=84 4=EC=9B=94 15=EC=9D=BC (=EC=88=98) 20:37, Michal Orzel >=EB=8B=98=EC=9D=B4 =EC=9E=91=EC=84=B1: > > handle_attach_overlay_nodes() destroys the IRQ and IOMEM rangesets on > failure but leaves the pointers dangling in the tracker entry. A > subsequent handle_remove_overlay_nodes() for the same overlay will ca= ll > rangeset_consume_ranges() on freed memory followed by a second > rangeset_destroy(), resulting in use-after-free and double-free. > > NULL the pointers after rangeset_destroy() so that remove_nodes() and > handle_remove_overlay_nodes() skip the stale entries. > > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device > attachment to domains") > Reported-by: Gyujeong Jin > > Signed-off-by: Michal Orzel > > --- > =C2=A0xen/common/device-tree/dt-overlay.c | 2 ++ > =C2=A01 file changed, 2 insertions(+) > > diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/ > device-tree/dt-overlay.c > index d184186c015e..6fa07dbf42a5 100644 > --- a/xen/common/device-tree/dt-overlay.c > +++ b/xen/common/device-tree/dt-overlay.c > @@ -910,7 +910,9 @@ static long handle_attach_overlay_nodes(struct > domain *d, > =C2=A0 =C2=A0 =C2=A0if ( entry ) > =C2=A0 =C2=A0 =C2=A0{ > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rangeset_destroy(entry->irq_ranges= ); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 entry->irq_ranges =3D NULL; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rangeset_destroy(entry->iomem_rang= es); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 entry->iomem_ranges =3D NULL; > =C2=A0 =C2=A0 =C2=A0} > > =C2=A0 =C2=A0 =C2=A0return rc; > -- > 2.43.0 > Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 12:14:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 12:14:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282378.1564975 (Exim 4.92) (envelope-from ) id 1wCz8Z-000457-8n; Wed, 15 Apr 2026 12:14:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282378.1564975; Wed, 15 Apr 2026 12:14:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCz8Z-000450-69; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1776255269-FE350A3D-D26C1ADC/0/0 X-purgate-type: clean X-purgate-size: 480 On Wed, Apr 01, 2026 at 01:21:54AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > +linux-6.12.60-x86_64: > + extends: .x86_64-artifacts > + script: ./scripts/build-linux.sh "6.12.60" I've got: $ ./scripts/build-linux.sh "6.12.60" LINUX_VERSION must be set Linux version want's to be in a env variable, not an argument. Cheers, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 12:22:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 12:22:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282390.1564985 (Exim 4.92) (envelope-from ) id 1wCzGW-0005tz-1I; Wed, 15 Apr 2026 12:22:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282390.1564985; Wed, 15 Apr 2026 12:22:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCzGV-0005ts-Up; Wed, 15 Apr 2026 12:22:43 +0000 Received: by outflank-mailman (input) for mailman id 1282390; Wed, 15 Apr 2026 12:22:43 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCzGV-0005tm-0d for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 12:22:43 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wCzGU-003DMY-06; Wed, 15 Apr 2026 12:22:42 +0000 Received: from [2a02:8012:3a1:0:6452:fdce:8dbd:9a39] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wCzGT-0042rr-2b; Wed, 15 Apr 2026 12:22:41 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=9OxsrBbnph6Lh14GYqegueMdJ+lWozdPjhaBtj9/v4o=; b=3VCHho85Y2SnHT8OuFc2Xm8zE9 +9vVQkndkQRQOSFJnu/nVe2y5NvQmvJ7gbQfngTmlDmWm0pQDYXKbwPRnnODzu5a25LVM7E1j/rBM 4Gb9qfF+CKOTje041BSgxj5U+ehoCQqXCICXK//x4BLj7mT5segt0FumlDmYsTdp6a4M=; Message-ID: Date: Wed, 15 Apr 2026 13:22:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] xen/dt-overlay: fix double-free of rangesets on attach failure Content-Language: en-GB To: Gyujeong Jin , Michal Orzel Cc: xen-devel@lists.xenproject.org, Stefano Stabellini , Bertrand Marquis References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-2-michal.orzel@amd.com> From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Gyujeong, On 15/04/2026 12:48, Gyujeong Jin wrote: > Thanks for your efforts. > > I’ve seen some advisories that received cve here. > https://xenbits.xen.org/xsa/ > > Can I receive a cve for this report? Thank you for the original report. The security team doesn't issue any CVE when there is no associated XSA. Best regards, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Apr 15 12:27:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 12:27:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282398.1564994 (Exim 4.92) (envelope-from ) id 1wCzKt-0006SH-HG; Wed, 15 Apr 2026 12:27:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282398.1564994; Wed, 15 Apr 2026 12:27:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCzKt-0006SA-EO; Wed, 15 Apr 2026 12:27:15 +0000 Received: by outflank-mailman (input) for mailman id 1282398; Wed, 15 Apr 2026 12:27:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wCzKr-0006RJ-SF for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 12:27:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wCzKr-00EsDN-75 for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="iJT/IRkUW/TDFo7l" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-33051d/1776256033-C9F3DC9A-3F6303B4/0/0 X-purgate-type: clean X-purgate-size: 1770 --iJT/IRkUW/TDFo7l Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 15 Apr 2026 14:27:07 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Anthony PERARD Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH test-artifacts v3 04/13] Add linux-6.12.79-x86_64 On Wed, Apr 15, 2026 at 11:56:53AM +0000, Anthony PERARD wrote: > On Wed, Apr 01, 2026 at 01:21:54AM +0200, Marek Marczykowski-G=C3=B3recki= wrote: > > +linux-6.12.60-x86_64: > > + extends: .x86_64-artifacts > > + script: ./scripts/build-linux.sh "6.12.60" >=20 > I've got: > $ ./scripts/build-linux.sh "6.12.60" > LINUX_VERSION must be set >=20 > Linux version want's to be in a env variable, not an argument. Oh, that's patch ordering, after 07/13 it's in argument. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --iJT/IRkUW/TDFo7l Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnfhBsACgkQ24/THMrX 1yxNBggAhN+2TOjqGxS0TnA50h0e8lluW0NoRmeoNP4Uo3veszjA1kJ6f2d4zeAE r6yXCJ7u8Gsa5D9VUtEqZuz2/Xsm9CLG8bhYr5GTTsu81dPbSHx8BMDXah4DyxMc 88LR1GpCPOwxqp/FZUvw3zAytWIPF4K8NDlbC9rgt+9up4TmhEVPgj9nDcatvGlQ peMDlDJ4XEfQtnP8K9huImW2meIGmXoqfkzbMHeVzsOTw0IZ/vPFfuOxr0iosCFq bjM0OYxA2EmzdNWdVtxB3JCNUVCL0VHD8lCpJbIBxTUMHY68Ct+yP8bLvxiu3Uww hATaPwIGJ3ekY62H/TSSri6J1r7N5w== =XsGF -----END PGP SIGNATURE----- --iJT/IRkUW/TDFo7l-- From xen-devel-bounces@lists.xenproject.org Wed Apr 15 12:31:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 12:31:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282408.1565004 (Exim 4.92) (envelope-from ) id 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=?utf-8?Q?Re:=20[PATCH=20test-artifacts=20v3=2007/13]=20Support=20building=20arbitrary=20Linux=20branch/tag/commit?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259063364 To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Andrew Cooper" , "Stefano Stabellini" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: References: In-Reply-To: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.fd547845742743ca86a5e54dbe50272d?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:17:44 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1776259066-3072A51B-3BF21ADD/0/0 X-purgate-type: clean X-purgate-size: 1552 On Wed, Apr 01, 2026 at 01:21:57AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > index 58f7571f5366..62b2a24e7faf 100644 > --- a/.gitlab-ci.yml > +++ b/.gitlab-ci.yml > @@ -49,9 +53,13 @@ alpine-3.22-arm64-rootfs: > > linux-6.6.86-arm64: > extends: .arm64-artifacts > - script: ./scripts/build-linux.sh > - variables: > - LINUX_VERSION: 6.6.86 > + script: ./scripts/build-linux.sh "6.6.86" Is it crazy to think we could grab the linux version from the job name? :-D linux-6.6.86-arm64: script: - linux_version=3D"$CI_JOB_NAME" - linux_version=3D"${linux_version#linux-}" - linux_version=3D"${linux_version%%-*}" - ./scripts/build-linux.sh "$linux_version" That would avoid having a job building a version of linux that is different than the expected one, which can happen easly when duplicating an existing job for building a new version of linux. > diff --git a/scripts/build-linux.sh b/scripts/build-linux.sh > index cf0e744bd232..882bac2189a6 100755 > --- a/scripts/build-linux.sh > +++ b/scripts/build-linux.sh > @@ -1,5 +1,8 @@ > #!/usr/bin/env bash > > +LINUX_VERSION=3D"$1" > +LINUX_GIT_URL=3D"$2" > + > if test -z "${LINUX_VERSION}" With LINUX_VERSION been set just before, this test doesn't make sense anymore, or the error message is wrong. > then > >&2 echo "LINUX_VERSION must be set"; exit 1 Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:32:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:32:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282447.1565020 (Exim 4.92) (envelope-from ) id 1wD0Lp-0008UO-DY; Wed, 15 Apr 2026 13:32:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282447.1565020; Wed, 15 Apr 2026 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h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=aewLOIUc21gakTYdJKuHjfeDFOm3ibWen26ACcWO78RBFuXCYlAaocdFPenc56U8T UsMH9fXjPDtKuvSiPrvyzmlXCpgsRi81mAu7lPxPl+Tp88Sg08b4Y4KpqR/Ukrvtav JrxaNgimXczfB6bbpaajTnMUSs7DT96FcG+TEorDqKye7Qk2b2IrlkgVJodVhdL6rS KlNux50R7fFsQhZ7BSDY7c0ai9tDLP+2ph7uTykQ0savGllAhYoDsRiSu/HjQQfMF/ BhY7X3BQN3Ez8sI8ov30Xdz/896wzIqVbwLDEtqLGlaIKX3Bmdx6C7jf67Qh0oE/2O 4Us0B80lMQMLw== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=201/7]=20vmx:=20Introduce=20vcpu=20single=20context=20VPID=20invalidation?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259933722 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: <50c96e2306538eb7cd28ddfcb21163c628fae0a4.1776259594.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.1a795d0610064f5681462d6652086e28?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:14 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776259936-FF547A3D-0EE0BC28/0/0 X-purgate-type: clean X-purgate-size: 1506 Introduce vpid_sync_vcpu_context to do a single-context invalidation on the vpid attached to the vcpu as a alternative to per-gva and all-context invlidations. Signed-off-by: Teddy Astie --- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h index da04752e17..3524cb3536 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -452,6 +452,27 @@ static inline void ept_sync_all(void) void ept_sync_domain(struct p2m_domain *p2m); +static inline void vpid_sync_vcpu_context(const struct vcpu *v) +{ + int type = INVVPID_SINGLE_CONTEXT; + + /* + * If single context invalidation is not supported, we escalate to + * use all context invalidation. + */ + if ( likely(cpu_has_vmx_vpid_invvpid_single_context) ) + goto execute_invvpid; + + /* + * If single context invalidation is not supported, we escalate to + * use all context invalidation. + */ + type = INVVPID_ALL_CONTEXT; + +execute_invvpid: + __invvpid(type, v->arch.hvm.n1asid.asid, 0); +} + static inline void vpid_sync_vcpu_gva(struct vcpu *v, unsigned long gva) { int type = INVVPID_INDIVIDUAL_ADDR; -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:32:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:32:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282448.1565029 (Exim 4.92) (envelope-from ) id 1wD0Lr-0000Gj-Ko; Wed, 15 Apr 2026 13:32:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282448.1565029; Wed, 15 Apr 2026 13:32:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0Lr-0000Gc-Hv; Wed, 15 Apr 2026 13:32:19 +0000 Received: by outflank-mailman (input) for mailman id 1282448; Wed, 15 Apr 2026 13:32:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0Lq-0000GL-Or for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259936; x=1776520436; i=teddy.astie@vates.tech; bh=V1xNEuLkT/UoGYapzOaT2ccLIg+S5oeSeb8h+8Yriq0=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=QqmXDzKPu0zPeEW63cqKXrsHH/05zS9IyAZVmh4ynlQ6NM3HoYbDH7vKPhF2b2hO6 JbAUd+ssbjHpS4jvZ/kGHPnhzeEqmuYLRZV/EjofnYLBwFXgUbQlhaBjTruq5mu4Zz BaX4mk+Uqlg5OmcorAOMDhndUvYIpKeg9HyKrUgDbA5UDr1YKJUandjrSuayg2SILl KQu6g0R7buUUn92ddGU3a/luHF2d+YmAqbd8csK/b5AqoMjMqxA3Eemi1zjKoN/WgE M+JTHsWMg0L4ESL+tSBQ9cUyl73F4HzvrJBoyuc+VQ7XSkAeGjrGcChoQR/RkMM5e3 4GlwhHOp9Bbww== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=202/7]=20common:=20Track=20latest=20pCPU=20that=20ran=20the=20vCPU?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259935319 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Jason Andryuk" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" Message-Id: In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.2f204a884a51440aa20c387e5f905bb7?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:16 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776259938-B5E6BFF4-9814C635/0/0 X-purgate-type: clean X-purgate-size: 3524 Track on which pCPU each vCPU of a domain ran. This will be used to know whether a TLB flush is required or not when the vCPU is migrated on another pCPU. Signed-off-by: Teddy Astie --- I wonder if there is a way to move curr->domain->latest_vcpu[cpu] = curr->vcpu_id into a (at least more) common code ? xen/arch/x86/hvm/svm/svm.c | 3 +++ xen/arch/x86/hvm/vmx/vmx.c | 3 +++ xen/common/domain.c | 8 ++++++++ xen/include/xen/sched.h | 4 ++++ 4 files changed, 18 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index ced6166847..58e927ae04 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -967,6 +967,7 @@ void asmlinkage svm_vmenter_helper(void) const struct cpu_user_regs *regs = guest_cpu_user_regs(); struct vcpu *curr = current; struct vmcb_struct *vmcb = curr->arch.hvm.svm.vmcb; + unsigned int cpu = smp_processor_id(); ASSERT(hvmemul_cache_disabled(curr)); @@ -977,6 +978,8 @@ void asmlinkage svm_vmenter_helper(void) svm_sync_vmcb(curr, vmcb_needs_vmsave); + curr->domain->latest_vcpu[cpu] = curr->vcpu_id; + vmcb->rax = regs->rax; vmcb->rip = regs->rip; vmcb->rsp = regs->rsp; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 269ca56433..ec0a790336 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4934,6 +4934,7 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) u32 new_asid, old_asid; struct hvm_vcpu_asid *p_asid; bool need_flush; + unsigned int cpu = smp_processor_id(); ASSERT(hvmemul_cache_disabled(curr)); @@ -4977,6 +4978,8 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( unlikely(need_flush) ) vpid_sync_all(); + currd->latest_vcpu[cpu] = curr->vcpu_id; + if ( paging_mode_hap(curr->domain) ) { struct ept_data *ept = &p2m_get_hostp2m(currd)->ept; diff --git a/xen/common/domain.c b/xen/common/domain.c index bb9e210c28..7867166411 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -758,6 +758,7 @@ static void _domain_destroy(struct domain *d) rangeset_domain_destroy(d); free_cpumask_var(d->dirty_cpumask); + xfree(d->latest_vcpu); xsm_free_security_domain(d); @@ -992,6 +993,13 @@ struct domain *domain_create(domid_t domid, if ( !zalloc_cpumask_var(&d->dirty_cpumask) ) goto fail; + err = -ENOMEM; + d->latest_vcpu = xmalloc_array(int, nr_cpu_ids); + if ( !d->latest_vcpu ) + goto fail; + for (unsigned int i = 0; i < nr_cpu_ids; i++) + d->latest_vcpu[i] = -1; + rangeset_domain_initialise(d); if ( is_idle_domain(d) ) diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c..4b8ae21b51 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -567,6 +567,10 @@ struct domain /* Bitmask of CPUs which are holding onto this domain's state. */ cpumask_var_t dirty_cpumask; + /* Mapping of the latest vCPU that ran on a specific CPU + * (-1 if the vCPU hasn't ran yet) */ + int *latest_vcpu; + struct arch_domain arch; void *ssid; /* sHype security subject identifier */ -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:32:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:32:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282449.1565039 (Exim 4.92) (envelope-from ) id 1wD0Lw-0000XS-S6; Wed, 15 Apr 2026 13:32:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282449.1565039; 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a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776259940; x=1776529940; bh=6GgW9zqjU7eafFgo+aMF5dqgD8VnWAi/yFVJIMHbHCg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=M/DcqyVjR/cY6vyn1nwNEyOdFK41VqfPRkEf8M2hmsDIRAFT8OsZ/mMoK9FpeSdCu M4XM5s9vYiVDx7WOixvesMgEEsvJ3iEWNPEn8LAFoUvH2eXy28TGFtJyDiRmxjmaJI SiuAe+e61IuADQEmQc7TtAUGSyoWO+z2PWz9EnR4XLHjdFDSx0He8zcdVD/pBV7o7u 8+VgCnCQ02WSqJn81P0c7+zRQPJHTKn89PACppphLIRwwDjroL3TQAK/icmlLEDrLU Fnf1ZH+nWfbnPhD57jfaC4XnPr4ndRFz/NHFxKgtH1tuMFJFsWyNL/69Mnh7wLBxJb bgxaTo/QXk82w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259940; x=1776520440; i=teddy.astie@vates.tech; bh=6GgW9zqjU7eafFgo+aMF5dqgD8VnWAi/yFVJIMHbHCg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=jithJSCaP3cYKzWK9+hoC7D6Nl4asINeWNx5+ssXORJ6d6cfKP2b9rHme4Nl1PnnW zRsj6HYHAFchkQNHVhBL22Tj+TvmyC/+2/dpX2GEf9anFD1N6HqtMmrxAsTsCpSKFG S5Oedq0nfY7ebLatQHsX2xq/HN0jr2qskwpSJp2Roc60xhwCF/KZJxta2skzvJU6TN YUgrgDzLBKUpcT9GBtQodtK4jG8C1EtfU0LoolYWoIrj6rQAaMSpWhQFPO2J7HogEh 4FIcUXORTsJLaUF5Lucy6JUMInZAe+bb/1rZ00JOBqX4zl9koGel8mEonC6I05kDVI DpWuXF/w4DvLw== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=204/7]=20x86:=20Set=20v->needs=5Ftlb=5Fflush=20when=20needed?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259938505 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Jason Andryuk" , "Tim Deegan" Message-Id: <3415abe736e46b3f36ccb045aa5144a371774fba.1776259594.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.549f1328209a4bf6a574e4c88ba3cd82?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:20 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776259942-5FB3B3D8-53BADBDA/0/0 X-purgate-type: clean X-purgate-size: 7788 Sets v->needs_tlb_flush in where a tlb flush is expected to be scheduled on the vCPU. Signed-off-by: Teddy Astie --- The goal here is to avoid too much noise in [1], hence it currently cohexists with hvm_asid_flush_vcpu(), but [1] will drop hvm_asid_flush_vcpu() and only keep needs_tlb_flush. [1] x86/hvm: Transition to needs_tlb_flush logic, use per-domain ASID xen/arch/x86/flushtlb.c | 4 ++++ xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 1 + xen/arch/x86/hvm/svm/svm.c | 5 +++++ xen/arch/x86/hvm/vmx/vmcs.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 3 +++ xen/arch/x86/hvm/vmx/vvmx.c | 1 + xen/arch/x86/mm/p2m.c | 4 ++++ xen/arch/x86/mm/paging.c | 1 + xen/arch/x86/mm/shadow/multi.c | 1 + 10 files changed, 22 insertions(+) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index 23721bb52c..8ee2385bba 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -324,7 +324,11 @@ unsigned int guest_flush_tlb_flags(const struct domain *d) void guest_flush_tlb_mask(const struct domain *d, const cpumask_t *mask) { unsigned int flags = guest_flush_tlb_flags(d); + struct vcpu *v; if ( flags ) flush_mask(mask, flags); + + for_each_vcpu(d, v) + v->needs_tlb_flush = true; } diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index f3aae158e9..3bc1d321cc 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2657,6 +2657,7 @@ static int cf_check hvmemul_tlb_op( if ( x86emul_invpcid_type(aux) != X86_INVPCID_INDIV_ADDR ) { hvm_asid_flush_vcpu(current); + current->needs_tlb_flush = true; break; } aux = x86emul_invpcid_pcid(aux); diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4a81afce02..0f0b0e242f 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1613,6 +1613,7 @@ int hvm_vcpu_initialise(struct vcpu *v) struct domain *d = v->domain; hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; spin_lock_init(&v->arch.hvm.tm_lock); INIT_LIST_HEAD(&v->arch.hvm.tm_list); diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 58e927ae04..64c08432fd 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -138,6 +138,8 @@ static void cf_check svm_update_guest_cr( { if ( !(flags & HVM_UPDATE_GUEST_CR3_NOFLUSH) ) hvm_asid_flush_vcpu(v); + + v->needs_tlb_flush = true; } else if ( nestedhvm_vmswitch_in_progress(v) ) ; /* CR3 switches during VMRUN/VMEXIT do not flush the TLB. */ @@ -944,6 +946,7 @@ static void noreturn cf_check svm_do_resume(void) hvm_migrate_pirqs(v); /* Migrating to another ASID domain. Request a new ASID. */ hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; } if ( !vcpu_guestmode && !vlapic_hw_disabled(vlapic) ) @@ -2306,6 +2309,8 @@ static void cf_check svm_invlpg(struct vcpu *v, unsigned long linear) { /* Safe fallback. Take a new ASID. */ hvm_asid_flush_vcpu(v); + /* Schedule a tlb flush on the VCPU. */ + v->needs_tlb_flush = true; } static bool cf_check svm_get_pending_event( diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 8e52ef4d49..4efe13e07f 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1904,6 +1904,7 @@ void cf_check vmx_do_resume(void) v->arch.hvm.vmx.hostenv_migrated = 1; hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; } debug_state = v->domain->debugger_attached diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index ec0a790336..0e4f9f9c3d 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1511,6 +1511,7 @@ static void cf_check vmx_handle_cd(struct vcpu *v, unsigned long value) wbinvd(); /* flush possibly polluted cache */ hvm_asid_flush_vcpu(v); /* invalidate memory type cached in TLB */ + v->needs_tlb_flush = true; /* invalidate memory type cached in TLB */ v->arch.hvm.vmx.cache_mode = CACHE_MODE_NO_FILL; } else @@ -1520,6 +1521,7 @@ static void cf_check vmx_handle_cd(struct vcpu *v, unsigned long value) if ( !is_iommu_enabled(v->domain) || iommu_snoop ) vmx_clear_msr_intercept(v, MSR_IA32_CR_PAT, VMX_MSR_RW); hvm_asid_flush_vcpu(v); /* no need to flush cache */ + v->needs_tlb_flush = true; } } } @@ -1872,6 +1874,7 @@ static void cf_check vmx_update_guest_cr( if ( !(flags & HVM_UPDATE_GUEST_CR3_NOFLUSH) ) hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; break; default: diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index e4cdfe55c1..16d6f1d61b 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1254,6 +1254,7 @@ static void virtual_vmentry(struct cpu_user_regs *regs) if ( nvmx->guest_vpid != new_vpid ) { hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(v).nv_n2asid); + v->needs_tlb_flush = true; nvmx->guest_vpid = new_vpid; } } diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index fddecdf978..910623ac93 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1439,6 +1440,7 @@ p2m_flush(struct vcpu *v, struct p2m_domain *p2m) vcpu_nestedhvm(v).nv_p2m = NULL; p2m_flush_table(p2m); hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; } void @@ -1498,6 +1500,7 @@ static void assign_np2m(struct vcpu *v, struct p2m_domain *p2m) static void nvcpu_flush(struct vcpu *v) { hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; vcpu_nestedhvm(v).stale_np2m = true; } @@ -1618,6 +1621,7 @@ void np2m_schedule(int dir) { /* This vCPU's np2m was flushed while it was not runnable */ hvm_asid_flush_core(); + curr->needs_tlb_flush = true; vcpu_nestedhvm(curr).nv_p2m = NULL; } else diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index 2396f81ad5..b0b3bef753 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -939,6 +939,7 @@ void paging_update_nestedmode(struct vcpu *v) /* TODO: shadow-on-shadow */ v->arch.paging.nestedmode = NULL; hvm_asid_flush_vcpu(v); + v->needs_tlb_flush = true; } int __init paging_set_allocation(struct domain *d, unsigned int pages, diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 80cd3299fa..2df2842138 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -3165,6 +3165,7 @@ sh_update_linear_entries(struct vcpu *v) * without this change, it would fetch the wrong value due to a stale TLB. */ sh_flush_local(d); + v->needs_tlb_flush = true; } static pagetable_t cf_check sh_update_cr3(struct vcpu *v, bool noflush) -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:32:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:32:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282455.1565048 (Exim 4.92) (envelope-from ) id 1wD0M4-0000sY-7m; Wed, 15 Apr 2026 13:32:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282455.1565048; Wed, 15 Apr 2026 13:32:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0M4-0000sN-4B; Wed, 15 Apr 2026 13:32:32 +0000 Received: by outflank-mailman (input) for mailman id 1282455; Wed, 15 Apr 2026 13:32:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0M2-0000q7-1H for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259947; x=1776520447; i=teddy.astie@vates.tech; bh=V9h2LeDrWd+hcIIUXMFjjufE73oFJ5PXheM8EpWf9EU=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=WwAN6xK8C6OYy2JJXwfERhI1QDvdeUeYmm4R4jTvlKcEPXC9vjywJaOz10d+arYAw KnCa/eA9SXQopN62WYN9ZlN8aI4nbFGUfoejCpMfznKIrfFvhZTWQUfz0m3lksaqSY rBlNjmpqpPDgUw72eEuOlbCOfEvD/TRt/qyxSftwZPfP98LFmphJMeLWf03jWGfRlL E21GraGfuDGd7tjweHj53QOq25/C+M0B8v1rf76nhAbcE9nisIUHWWcPq8nQ27gFTu m3FYYXZJFBWGGSIZKrTKCHJaue1vDELCnaXx9OjXnJHDdaQpuB+6i/GGVfL345yAQ9 HoMBybpFl9MPw== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=206/7]=20x86/hvm:=20Transition=20to=20needs=5Ftlb=5Fflush=20logic,=20use=20per-domain=20ASID?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259945929 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" , "Jason Andryuk" , "Tim Deegan" Message-Id: <2775da1be0c767a2dc7fcdf5caaf43278da2ab74.1776259594.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.23fe8188e6a9447487e3112d66dc3e1a?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:27 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776259949-77348497-BD68DE05/0/0 X-purgate-type: clean X-purgate-size: 42911 Change the ASID model where all vCPU of a domain share the same ASID as required by AMD SEV and broadcast TLB flushing features (AMD INVLPGB). ASID 1 is reserved as a placeholder for "no domain ASID", and used when either ASID are not supported or no more ASID is available for use. In this case, we always flush the TLB when from and to such domain's vCPU. Moreover, centralize the TLB flushing logic to use needs_tlb_flush, if a full TLB flush needs to be performed for the vCPU, either through SVM tlb_control or VMX invvpid before entering the guest. As a result, drop ASID tickling logic, which is now redundant with the needs_tlb_flush mechanism introduced previously. Also take the opportunity to drop some now unused helpers now that FLUSH_HVM_ASID_CORE is dropped. Signed-off-by: Teddy Astie --- Nested virt makes some aspects tricky and is hard to reason about, especially since there are 2 ASID in such case and complex TLB flushing logic. docs/misc/xen-command-line.pandoc | 2 +- xen/arch/x86/flushtlb.c | 18 +-- xen/arch/x86/hvm/asid.c | 169 +++++++++++-------------- xen/arch/x86/hvm/emulate.c | 1 - xen/arch/x86/hvm/hvm.c | 24 +++- xen/arch/x86/hvm/nestedhvm.c | 7 +- xen/arch/x86/hvm/svm/asid.c | 67 +++++++--- xen/arch/x86/hvm/svm/nestedsvm.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 31 +++-- xen/arch/x86/hvm/svm/svm.h | 4 - xen/arch/x86/hvm/vmx/vmcs.c | 5 +- xen/arch/x86/hvm/vmx/vmx.c | 64 +++++----- xen/arch/x86/hvm/vmx/vvmx.c | 3 +- xen/arch/x86/include/asm/flushtlb.h | 7 - xen/arch/x86/include/asm/hvm/asid.h | 26 ++-- xen/arch/x86/include/asm/hvm/domain.h | 1 + xen/arch/x86/include/asm/hvm/hvm.h | 15 +-- xen/arch/x86/include/asm/hvm/svm.h | 5 + xen/arch/x86/include/asm/hvm/vcpu.h | 10 +- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 4 +- xen/arch/x86/mm/hap/hap.c | 9 +- xen/arch/x86/mm/p2m.c | 3 - xen/arch/x86/mm/paging.c | 1 - xen/arch/x86/mm/shadow/multi.c | 11 +- 24 files changed, 228 insertions(+), 261 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 6c77129732..099b718df9 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -208,7 +208,7 @@ to appropriate auditing by Xen. Argo is disabled by default. > Default: `true` Permit Xen to use Address Space Identifiers. This is an optimisation which -tags the TLB entries with an ID per vcpu. This allows for guest TLB flushes +tags the TLB entries with an ID per domain. This allows for guest TLB flushes to be performed without the overhead of a complete TLB flush. ### async-show-all (x86) diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index 8ee2385bba..f60d2df8fd 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -117,7 +118,6 @@ void switch_cr3_cr4(unsigned long cr3, unsigned long cr4) if ( tlb_clk_enabled ) t = pre_flush(); - hvm_flush_guest_tlbs(); old_cr4 = read_cr4(); ASSERT(!(old_cr4 & X86_CR4_PCIDE) || !(old_cr4 & X86_CR4_PGE)); @@ -221,9 +221,6 @@ unsigned int flush_area_local(const void *va, unsigned int flags) do_tlb_flush(); } - if ( flags & FLUSH_HVM_ASID_CORE ) - hvm_flush_guest_tlbs(); - if ( flags & (FLUSH_CACHE_EVICT | FLUSH_CACHE_WRITEBACK) ) { const struct cpuinfo_x86 *c = ¤t_cpu_data; @@ -313,21 +310,12 @@ void cache_writeback(const void *addr, unsigned int size) asm volatile ("sfence" ::: "memory"); } -unsigned int guest_flush_tlb_flags(const struct domain *d) -{ - bool shadow = paging_mode_shadow(d); - bool asid = is_hvm_domain(d) && (cpu_has_svm || shadow); - - return (shadow ? FLUSH_TLB : 0) | (asid ? FLUSH_HVM_ASID_CORE : 0); -} - void guest_flush_tlb_mask(const struct domain *d, const cpumask_t *mask) { - unsigned int flags = guest_flush_tlb_flags(d); struct vcpu *v; - if ( flags ) - flush_mask(mask, flags); + if ( paging_mode_shadow(d) ) + flush_tlb_mask(mask); for_each_vcpu(d, v) v->needs_tlb_flush = true; diff --git a/xen/arch/x86/hvm/asid.c b/xen/arch/x86/hvm/asid.c index 935cae3901..1a21125161 100644 --- a/xen/arch/x86/hvm/asid.c +++ b/xen/arch/x86/hvm/asid.c @@ -5,138 +5,115 @@ * Copyright (c) 2009, Citrix Systems, Inc. */ +#include #include #include #include -#include -#include -#include +#include +#include + +#include #include /* Xen command-line option to enable ASIDs */ static bool __read_mostly opt_asid_enabled = true; boolean_param("asid", opt_asid_enabled); +bool __read_mostly asid_enabled = false; +static unsigned long __ro_after_init *asid_bitmap; +static unsigned long __ro_after_init asid_count; +static DEFINE_SPINLOCK(asid_lock); + /* - * ASIDs partition the physical TLB. In the current implementation ASIDs are - * introduced to reduce the number of TLB flushes. Each time the guest's - * virtual address space changes (e.g. due to an INVLPG, MOV-TO-{CR3, CR4} - * operation), instead of flushing the TLB, a new ASID is assigned. This - * reduces the number of TLB flushes to at most 1/#ASIDs. The biggest - * advantage is that hot parts of the hypervisor's code and data retain in - * the TLB. - * * Sketch of the Implementation: + * ASIDs are assigned uniquely per domain and doesn't change during the lifecycle of the + * domain. Once vcpus are initialized and are up, we assign the same ASID to all vcpus + * of that domain at the first VMRUN. In order to process a TLB flush on a vcpu, we set + * needs_tlb_flush to schedule a TLB flush for the next VMRUN (e.g using tlb control + * field of VMCB). * - * ASIDs are a CPU-local resource. As preemption of ASIDs is not possible, - * ASIDs are assigned in a round-robin scheme. To minimize the overhead of - * ASID invalidation, at the time of a TLB flush, ASIDs are tagged with a - * 64-bit generation. Only on a generation overflow the code needs to - * invalidate all ASID information stored at the VCPUs with are run on the - * specific physical processor. This overflow appears after about 2^80 - * host processor cycles, so we do not optimize this case, but simply disable - * ASID useage to retain correctness. + * We reserve ASID=1 as being the ASID used when none other is available (or with asid + * use disabled). Multiples domains may use this ASID, thus we need to systematically + * flush the TLB for this one when switching between vCPUs with ASID=1. */ -/* Per-CPU ASID management. */ -struct hvm_asid_data { - uint64_t core_asid_generation; - uint32_t next_asid; - uint32_t max_asid; - bool disabled; -}; - -static DEFINE_PER_CPU(struct hvm_asid_data, hvm_asid_data); - -void hvm_asid_init(unsigned int nasids) +int __init hvm_asid_init(unsigned long nasids) { - static int8_t __ro_after_init g_disabled = -1; - struct hvm_asid_data *data = &this_cpu(hvm_asid_data); + ASSERT(nasids); - data->max_asid = nasids - 1; - data->disabled = !opt_asid_enabled || (nasids <= 1); + asid_count = nasids; + asid_enabled = opt_asid_enabled && (nasids > 1); - if ( g_disabled < 0 ) - { - g_disabled = data->disabled; - printk("HVM: ASIDs %sabled\n", data->disabled ? "dis" : "en"); - } - else if ( g_disabled != data->disabled ) - printk("HVM: CPU%u: ASIDs %sabled\n", smp_processor_id(), - data->disabled ? "dis" : "en"); + asid_bitmap = xvzalloc_array(unsigned long, BITS_TO_LONGS(asid_count + 1)); + if ( !asid_bitmap ) + return -ENOMEM; - /* Zero indicates 'invalid generation', so we start the count at one. */ - data->core_asid_generation = 1; + printk("HVM: ASIDs %sabled (count=%lu)\n", asid_enabled ? "en" : "dis", asid_count); - /* Zero indicates 'ASIDs disabled', so we start the count at one. */ - data->next_asid = 1; -} + /* ASID 0 and 1 are reserved, mark it as permanently used */ + set_bit(0, asid_bitmap); + set_bit(1, asid_bitmap); -void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid) -{ - write_atomic(&asid->generation, 0); + return 0; } -void hvm_asid_flush_vcpu(struct vcpu *v) +int hvm_asid_alloc(struct hvm_asid *asid) { - hvm_asid_flush_vcpu_asid(&v->arch.hvm.n1asid); - hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(v).nv_n2asid); -} + unsigned long new_asid; -void hvm_asid_flush_core(void) -{ - struct hvm_asid_data *data = &this_cpu(hvm_asid_data); + if ( !asid_enabled ) + { + asid->asid = 1; + return 0; + } - if ( data->disabled ) - return; + spin_lock(&asid_lock); + new_asid = find_first_zero_bit(asid_bitmap, asid_count); + if ( new_asid > asid_count ) + return -ENOSPC; - if ( likely(++data->core_asid_generation != 0) ) - return; + set_bit(new_asid, asid_bitmap); - /* - * ASID generations are 64 bit. Overflow of generations never happens. - * For safety, we simply disable ASIDs, so correctness is established; it - * only runs a bit slower. - */ - printk("HVM: ASID generation overrun. Disabling ASIDs.\n"); - data->disabled = 1; + asid->asid = new_asid; + spin_unlock(&asid_lock); + return 0; } -bool hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid) +int hvm_asid_alloc_range(struct hvm_asid *asid, unsigned long min, unsigned long max) { - struct hvm_asid_data *data = &this_cpu(hvm_asid_data); + unsigned long new_asid; + + if ( WARN_ON(min >= asid_count) ) + return -EINVAL; - /* On erratum #170 systems we must flush the TLB. - * Generation overruns are taken here, too. */ - if ( data->disabled ) - goto disabled; + if ( !asid_enabled ) + return -EOPNOTSUPP; - /* Test if VCPU has valid ASID. */ - if ( read_atomic(&asid->generation) == data->core_asid_generation ) - return 0; + spin_lock(&asid_lock); + new_asid = find_next_zero_bit(asid_bitmap, asid_count, min); + if ( new_asid > max || new_asid > asid_count ) + return -ENOSPC; - /* If there are no free ASIDs, need to go to a new generation */ - if ( unlikely(data->next_asid > data->max_asid) ) - { - hvm_asid_flush_core(); - data->next_asid = 1; - if ( data->disabled ) - goto disabled; - } + set_bit(new_asid, asid_bitmap); - /* Now guaranteed to be a free ASID. */ - asid->asid = data->next_asid++; - write_atomic(&asid->generation, data->core_asid_generation); + asid->asid = new_asid; + spin_unlock(&asid_lock); + return 0; +} - /* - * When we assign ASID 1, flush all TLB entries as we are starting a new - * generation, and all old ASID allocations are now stale. - */ - return (asid->asid == 1); +void hvm_asid_free(struct hvm_asid *asid) +{ + ASSERT( asid->asid ); - disabled: - asid->asid = 0; - return 0; + if ( !asid_enabled || asid->asid == 1 ) + return; + + ASSERT( asid->asid < asid_count ); + + spin_lock(&asid_lock); + WARN_ON(!test_bit(asid->asid, asid_bitmap)); + clear_bit(asid->asid, asid_bitmap); + spin_unlock(&asid_lock); } /* diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 3bc1d321cc..efdf236df1 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2656,7 +2656,6 @@ static int cf_check hvmemul_tlb_op( case x86emul_invpcid: if ( x86emul_invpcid_type(aux) != X86_INVPCID_INDIV_ADDR ) { - hvm_asid_flush_vcpu(current); current->needs_tlb_flush = true; break; } diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 0f0b0e242f..2ab625d6e0 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -520,11 +520,13 @@ static bool hvm_get_pending_event(struct vcpu *v, struct x86_event *info) void hvm_do_resume(struct vcpu *v) { + struct domain *currd = v->domain;; + check_wakeup_from_wait(); pt_restore_timer(v); - if ( has_vpci(v->domain) && vpci_process_pending(v) ) + if ( has_vpci(currd) && vpci_process_pending(v) ) { raise_softirq(SCHEDULE_SOFTIRQ); return; @@ -559,6 +561,13 @@ void hvm_do_resume(struct vcpu *v) v->arch.monitor.next_interrupt_enabled = false; } } + + if ( unlikely(currd->arch.hvm.asid.asid == 1) ) + /* + * As ASID=1 may be shared across multiples domains, we can't easily track the + * state of the TLB, we always flush the TLB before resuming this vCPU. + */ + v->needs_tlb_flush = true; } static int cf_check hvm_print_line( @@ -714,6 +723,10 @@ int hvm_domain_initialise(struct domain *d, if ( rc ) goto fail2; + rc = hvm_asid_alloc(&d->arch.hvm.asid); + if ( rc ) + goto fail2; + rc = alternative_call(hvm_funcs.domain_initialise, d); if ( rc != 0 ) goto fail2; @@ -794,7 +807,7 @@ void hvm_domain_destroy(struct domain *d) list_del(&ioport->list); xfree(ioport); } - + hvm_asid_free(&d->arch.hvm.asid); destroy_vpci_mmcfg(d); } @@ -1612,7 +1625,6 @@ int hvm_vcpu_initialise(struct vcpu *v) int rc; struct domain *d = v->domain; - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; spin_lock_init(&v->arch.hvm.tm_lock); @@ -4085,6 +4097,11 @@ static void hvm_s3_resume(struct domain *d) } } +int hvm_flush_tlb(const unsigned long *vcpu_bitmap) +{ + return current->domain->arch.paging.flush_tlb(vcpu_bitmap); +} + static int hvmop_flush_tlb_all(void) { if ( !is_hvm_domain(current->domain) ) @@ -5464,4 +5481,3 @@ int hvm_copy_context_and_params(struct domain *dst, struct domain *src) * indent-tabs-mode: nil * End: */ - diff --git a/xen/arch/x86/hvm/nestedhvm.c b/xen/arch/x86/hvm/nestedhvm.c index bddd77d810..61e866b771 100644 --- a/xen/arch/x86/hvm/nestedhvm.c +++ b/xen/arch/x86/hvm/nestedhvm.c @@ -12,6 +12,7 @@ #include #include /* for local_event_delivery_(en|dis)able */ #include /* for paging_mode_hap() */ +#include static unsigned long *shadow_io_bitmap[3]; @@ -36,13 +37,11 @@ nestedhvm_vcpu_reset(struct vcpu *v) hvm_unmap_guest_frame(nv->nv_vvmcx, 1); nv->nv_vvmcx = NULL; nv->nv_vvmcxaddr = INVALID_PADDR; - nv->nv_flushp2m = 0; + nv->nv_flushp2m = true; nv->nv_p2m = NULL; nv->stale_np2m = false; nv->np2m_generation = 0; - hvm_asid_flush_vcpu_asid(&nv->nv_n2asid); - alternative_vcall(hvm_funcs.nhvm_vcpu_reset, v); /* vcpu is in host mode */ @@ -86,7 +85,7 @@ static void cf_check nestedhvm_flushtlb_ipi(void *info) * This is cheaper than flush_tlb_local() and has * the same desired effect. */ - hvm_asid_flush_core(); + WARN_ON(hvm_flush_tlb(NULL)); vcpu_nestedhvm(v).nv_p2m = NULL; vcpu_nestedhvm(v).stale_np2m = true; } diff --git a/xen/arch/x86/hvm/svm/asid.c b/xen/arch/x86/hvm/svm/asid.c index 53aa5d0512..44d2138895 100644 --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -1,39 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * asid.c: handling ASIDs in SVM. + * asid.c: handling ASIDs/VPIDs. * Copyright (c) 2007, Advanced Micro Devices, Inc. */ +#include + #include #include #include +#include #include "svm.h" #include "vmcb.h" -void svm_asid_init(const struct cpuinfo_x86 *c) +void __init svm_asid_init(void) { - unsigned int nasids = 0; + unsigned int cpu, nasids = cpuid_ebx(0x8000000aU); + + if ( !nasids ) + nasids = 1; - /* Check for erratum #170, and leave ASIDs disabled if it's present. */ - if ( !cpu_has_amd_erratum(c, AMD_ERRATUM_170) ) - nasids = cpuid_ebx(0x8000000aU); + for_each_present_cpu(cpu) + { + /* Check for erratum #170, and leave ASIDs disabled if it's present. */ + if ( cpu_has_amd_erratum(&cpu_data[cpu], AMD_ERRATUM_170) ) + { + printk(XENLOG_WARNING "Disabling ASID due to errata 170 on CPU%u\n", cpu); + nasids = 1; + } + } - hvm_asid_init(nasids); + BUG_ON(hvm_asid_init(nasids)); } /* - * Called directly before VMRUN. Checks if the VCPU needs a new ASID, - * assigns it, and if required, issues required TLB flushes. + * Called directly at the first VMRUN/VMENTER of a vcpu to assign the ASID/VPID. */ -void svm_asid_handle_vmrun(void) +void svm_vcpu_assign_asid(struct vcpu *v) { - struct vcpu *curr = current; - struct vmcb_struct *vmcb = curr->arch.hvm.svm.vmcb; - struct hvm_vcpu_asid *p_asid = - nestedhvm_vcpu_in_guestmode(curr) - ? &vcpu_nestedhvm(curr).nv_n2asid : &curr->arch.hvm.n1asid; - bool need_flush = hvm_asid_handle_vmenter(p_asid); + struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb; + struct hvm_asid *p_asid = &v->domain->arch.hvm.asid; /* ASID 0 indicates that ASIDs are disabled. */ if ( p_asid->asid == 0 ) @@ -44,11 +51,31 @@ void svm_asid_handle_vmrun(void) return; } - if ( vmcb_get_asid(vmcb) != p_asid->asid ) - vmcb_set_asid(vmcb, p_asid->asid); + /* In case ASIDs are disabled, as ASID = 0 is reserved, guest can use 1 instead. */ + vmcb_set_asid(vmcb, asid_enabled ? p_asid->asid : 1); +} + +/* Call to make a TLB flush at the next VMRUN. */ +void svm_vcpu_set_tlb_control(struct vcpu *v) +{ + struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb; + + /* + * If the vcpu is already running, the tlb control flag may not be + * processed and will be cleared at the next VMEXIT, which will undo + * what we are trying to do. + */ + WARN_ON(v != current && v->is_running); + + vmcb->tlb_control = + cpu_has_svm_flushbyasid ? TLB_CTRL_FLUSH_ASID : TLB_CTRL_FLUSH_ALL; +} + +void svm_vcpu_clear_tlb_control(struct vcpu *v) +{ + struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb; - /* We can't rely on TLB_CTRL_FLUSH_ASID as all ASIDs are stale here. */ - vmcb->tlb_control = need_flush ? TLB_CTRL_FLUSH_ALL : TLB_CTRL_NO_FLUSH; + vmcb->tlb_control = TLB_CTRL_NO_FLUSH; } /* diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c index ef6fa5d23b..d9a84f9388 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -5,6 +5,7 @@ * */ +#include #include #include #include @@ -638,7 +639,6 @@ nsvm_vcpu_vmentry(struct vcpu *v, struct cpu_user_regs *regs, if ( svm->ns_asid != vmcb_get_asid(ns_vmcb)) { nv->nv_flushp2m = 1; - hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(v).nv_n2asid); svm->ns_asid = vmcb_get_asid(ns_vmcb); } diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 8714fb18ec..ba22acb8a6 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -137,16 +138,18 @@ static void cf_check svm_update_guest_cr( if ( !nestedhvm_enabled(v->domain) ) { if ( !(flags & HVM_UPDATE_GUEST_CR3_NOFLUSH) ) - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; } else if ( nestedhvm_vmswitch_in_progress(v) ) ; /* CR3 switches during VMRUN/VMEXIT do not flush the TLB. */ else if ( !(flags & HVM_UPDATE_GUEST_CR3_NOFLUSH) ) - hvm_asid_flush_vcpu_asid( - nestedhvm_vcpu_in_guestmode(v) - ? &vcpu_nestedhvm(v).nv_n2asid : &v->arch.hvm.n1asid); + { + if (nestedhvm_vcpu_in_guestmode(v)) + vcpu_nestedhvm(v).nv_flushp2m = true; + else + v->needs_tlb_flush = true; + } break; case 4: value = HVM_CR4_HOST_MASK; @@ -944,8 +947,6 @@ static void noreturn cf_check svm_do_resume(void) v->arch.hvm.svm.launch_core = smp_processor_id(); hvm_migrate_timers(v); hvm_migrate_pirqs(v); - /* Migrating to another ASID domain. Request a new ASID. */ - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; } @@ -974,8 +975,6 @@ void asmlinkage svm_vmenter_helper(void) ASSERT(hvmemul_cache_disabled(curr)); - svm_asid_handle_vmrun(); - TRACE_TIME(TRC_HVM_VMENTRY | (nestedhvm_vcpu_in_guestmode(curr) ? TRC_HVM_NESTEDFLAG : 0)); @@ -991,6 +990,9 @@ void asmlinkage svm_vmenter_helper(void) curr->domain->latest_vcpu[cpu] = curr->vcpu_id; + if ( test_and_clear_bool(curr->needs_tlb_flush) ) + svm_vcpu_set_tlb_control(curr); + vmcb->rax = regs->rax; vmcb->rip = regs->rip; vmcb->rsp = regs->rsp; @@ -1111,6 +1113,8 @@ static int cf_check svm_vcpu_initialise(struct vcpu *v) return rc; } + svm_vcpu_assign_asid(v); + return 0; } @@ -1536,9 +1540,6 @@ static int _svm_cpu_up(bool bsp) /* check for erratum 383 */ svm_init_erratum_383(c); - /* Initialize core's ASID handling. */ - svm_asid_init(c); - /* Initialize OSVW bits to be used by guests */ svm_host_osvw_init(); @@ -2293,7 +2294,7 @@ static void svm_invlpga_intercept( { svm_invlpga(linear, (asid == 0) - ? v->arch.hvm.n1asid.asid + ? v->domain->arch.hvm.asid.asid : vcpu_nestedhvm(v).nv_n2asid.asid); } @@ -2315,8 +2316,6 @@ static bool cf_check is_invlpg( static void cf_check svm_invlpg(struct vcpu *v, unsigned long linear) { - /* Safe fallback. Take a new ASID. */ - hvm_asid_flush_vcpu(v); /* Schedule a tlb flush on the VCPU. */ v->needs_tlb_flush = true; } @@ -2486,6 +2485,8 @@ const struct hvm_function_table * __init start_svm(void) svm_function_table.caps.hap_superpage_2mb = true; svm_function_table.caps.hap_superpage_1gb = cpu_has_page1gb; + svm_asid_init(); + return &svm_function_table; } @@ -2542,6 +2543,8 @@ void asmlinkage svm_vmexit_handler(void) (vlapic_get_reg(vlapic, APIC_TASKPRI) & 0x0F)); } + svm_vcpu_clear_tlb_control(v); + exit_reason = vmcb->exitcode; if ( hvm_long_mode_active(v) ) diff --git a/xen/arch/x86/hvm/svm/svm.h b/xen/arch/x86/hvm/svm/svm.h index cfa411ad5a..901354e914 100644 --- a/xen/arch/x86/hvm/svm/svm.h +++ b/xen/arch/x86/hvm/svm/svm.h @@ -12,12 +12,8 @@ #include struct cpu_user_regs; -struct cpuinfo_x86; struct vcpu; -void svm_asid_init(const struct cpuinfo_x86 *c); -void svm_asid_handle_vmrun(void); - unsigned long *svm_msrbit(unsigned long *msr_bitmap, uint32_t msr); void __update_guest_eip(struct cpu_user_regs *regs, unsigned int inst_len); diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index 4efe13e07f..88808e26e7 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -778,8 +779,6 @@ static int _vmx_cpu_up(bool bsp) this_cpu(vmxon) = 1; - hvm_asid_init(cpu_has_vmx_vpid ? (1u << VMCS_VPID_WIDTH) : 0); - if ( cpu_has_vmx_ept ) ept_sync_all(); @@ -1903,7 +1902,6 @@ void cf_check vmx_do_resume(void) */ v->arch.hvm.vmx.hostenv_migrated = 1; - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; } @@ -2117,7 +2115,6 @@ void vmcs_dump_vcpu(struct vcpu *v) (SECONDARY_EXEC_ENABLE_VPID | SECONDARY_EXEC_ENABLE_VM_FUNCTIONS) ) printk("Virtual processor ID = 0x%04x VMfunc controls = %016lx\n", vmr16(VIRTUAL_PROCESSOR_ID), vmr(VM_FUNCTION_CONTROL)); - vmx_vmcs_exit(v); } diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index dceff2f221..15989cf136 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -834,6 +835,18 @@ static void cf_check vmx_cpuid_policy_changed(struct vcpu *v) vmx_update_secondary_exec_control(v); } + if ( asid_enabled ) + { + v->arch.hvm.vmx.secondary_exec_control |= SECONDARY_EXEC_ENABLE_VPID; + vmx_update_secondary_exec_control(v); + } + else + { + v->arch.hvm.vmx.secondary_exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; + vmx_update_secondary_exec_control(v); + } + + /* * We can safely pass MSR_SPEC_CTRL through to the guest, even if STIBP * isn't enumerated in hardware, as SPEC_CTRL_STIBP is ignored. @@ -1510,7 +1523,6 @@ static void cf_check vmx_handle_cd(struct vcpu *v, unsigned long value) vmx_set_msr_intercept(v, MSR_IA32_CR_PAT, VMX_MSR_RW); wbinvd(); /* flush possibly polluted cache */ - hvm_asid_flush_vcpu(v); /* invalidate memory type cached in TLB */ v->needs_tlb_flush = true; /* invalidate memory type cached in TLB */ v->arch.hvm.vmx.cache_mode = CACHE_MODE_NO_FILL; } @@ -1520,7 +1532,6 @@ static void cf_check vmx_handle_cd(struct vcpu *v, unsigned long value) vmx_set_guest_pat(v, *pat); if ( !is_iommu_enabled(v->domain) || iommu_snoop ) vmx_clear_msr_intercept(v, MSR_IA32_CR_PAT, VMX_MSR_RW); - hvm_asid_flush_vcpu(v); /* no need to flush cache */ v->needs_tlb_flush = true; } } @@ -1873,7 +1884,6 @@ static void cf_check vmx_update_guest_cr( __vmwrite(GUEST_CR3, v->arch.hvm.hw_cr[3]); if ( !(flags & HVM_UPDATE_GUEST_CR3_NOFLUSH) ) - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; break; @@ -3171,6 +3181,8 @@ const struct hvm_function_table * __init start_vmx(void) lbr_tsx_fixup_check(); ler_to_fixup_check(); + BUG_ON(hvm_asid_init(cpu_has_vmx_vpid ? (1u << VMCS_VPID_WIDTH) : 1)); + return &vmx_function_table; } @@ -4934,9 +4946,7 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) { struct vcpu *curr = current; struct domain *currd = curr->domain; - u32 new_asid, old_asid; - struct hvm_vcpu_asid *p_asid; - bool need_flush; + struct hvm_asid *p_asid; unsigned int cpu = smp_processor_id(); ASSERT(hvmemul_cache_disabled(curr)); @@ -4948,38 +4958,16 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( curr->domain->arch.hvm.pi_ops.vcpu_block ) vmx_pi_do_resume(curr); - if ( !cpu_has_vmx_vpid ) + if ( !asid_enabled ) goto out; if ( nestedhvm_vcpu_in_guestmode(curr) ) p_asid = &vcpu_nestedhvm(curr).nv_n2asid; else - p_asid = &curr->arch.hvm.n1asid; + p_asid = &currd->arch.hvm.asid; - old_asid = p_asid->asid; - need_flush = hvm_asid_handle_vmenter(p_asid); - new_asid = p_asid->asid; + __vmwrite(VIRTUAL_PROCESSOR_ID, p_asid->asid); - if ( unlikely(new_asid != old_asid) ) - { - __vmwrite(VIRTUAL_PROCESSOR_ID, new_asid); - if ( !old_asid && new_asid ) - { - /* VPID was disabled: now enabled. */ - curr->arch.hvm.vmx.secondary_exec_control |= - SECONDARY_EXEC_ENABLE_VPID; - vmx_update_secondary_exec_control(curr); - } - else if ( old_asid && !new_asid ) - { - /* VPID was enabled: now disabled. */ - curr->arch.hvm.vmx.secondary_exec_control &= - ~SECONDARY_EXEC_ENABLE_VPID; - vmx_update_secondary_exec_control(curr); - } - } - if ( unlikely(need_flush) ) - vpid_sync_all(); /** * Check if we were the latest vCPU of this domain that ran on this pCPU. * Flush the TLB if it is not, as the TLB entries are the ones from the previous @@ -4993,16 +4981,21 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( paging_mode_hap(curr->domain) ) { struct ept_data *ept = &p2m_get_hostp2m(currd)->ept; - unsigned int cpu = smp_processor_id(); unsigned int inv = 0; /* None => Single => All */ struct ept_data *single = NULL; /* Single eptp, iff inv == 1 */ + if ( test_and_clear_bool(curr->needs_tlb_flush) ) + { + inv = 1; + single = ept; + } + if ( cpumask_test_cpu(cpu, ept->invalidate) ) { cpumask_clear_cpu(cpu, ept->invalidate); /* Automatically invalidate all contexts if nested. */ - inv += 1 + nestedhvm_enabled(currd); + inv = 1 + nestedhvm_enabled(currd); single = ept; } @@ -5031,6 +5024,11 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) __invept(inv == 1 ? INVEPT_SINGLE_CONTEXT : INVEPT_ALL_CONTEXT, inv == 1 ? single->eptp : 0); } + else /* Shadow paging */ + { + if ( test_and_clear_bool(curr->needs_tlb_flush) ) + vpid_sync_vcpu_context(curr); + } out: if ( unlikely(curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_MASK) ) diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 16d6f1d61b..7314aa5633 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1253,7 +1253,6 @@ static void virtual_vmentry(struct cpu_user_regs *regs) if ( nvmx->guest_vpid != new_vpid ) { - hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(v).nv_n2asid); v->needs_tlb_flush = true; nvmx->guest_vpid = new_vpid; } @@ -2053,7 +2052,7 @@ static int nvmx_handle_invvpid(struct cpu_user_regs *regs) case INVVPID_INDIVIDUAL_ADDR: case INVVPID_SINGLE_CONTEXT: case INVVPID_ALL_CONTEXT: - hvm_asid_flush_vcpu_asid(&vcpu_nestedhvm(current).nv_n2asid); + hvm_flush_tlb(NULL); break; default: vmfail(regs, VMX_INSN_INVEPT_INVVPID_INVALID_OP); diff --git a/xen/arch/x86/include/asm/flushtlb.h b/xen/arch/x86/include/asm/flushtlb.h index 7bcbca2b7f..d8167aca18 100644 --- a/xen/arch/x86/include/asm/flushtlb.h +++ b/xen/arch/x86/include/asm/flushtlb.h @@ -125,12 +125,6 @@ void switch_cr3_cr4(unsigned long cr3, unsigned long cr4); #define FLUSH_VCPU_STATE 0x1000 /* Flush the per-cpu root page table */ #define FLUSH_ROOT_PGTBL 0x2000 -#if CONFIG_HVM - /* Flush all HVM guests linear TLB (using ASID/VPID) */ -#define FLUSH_HVM_ASID_CORE 0x4000 -#else -#define FLUSH_HVM_ASID_CORE 0 -#endif #if defined(CONFIG_PV) || defined(CONFIG_SHADOW_PAGING) /* * Adding this to the flags passed to flush_area_mask will prevent using the @@ -190,7 +184,6 @@ void flush_area_mask(const cpumask_t *mask, const void *va, static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache) {} -unsigned int guest_flush_tlb_flags(const struct domain *d); void guest_flush_tlb_mask(const struct domain *d, const cpumask_t *mask); #endif /* __FLUSHTLB_H__ */ diff --git a/xen/arch/x86/include/asm/hvm/asid.h b/xen/arch/x86/include/asm/hvm/asid.h index 25ba57e768..13ea357f70 100644 --- a/xen/arch/x86/include/asm/hvm/asid.h +++ b/xen/arch/x86/include/asm/hvm/asid.h @@ -8,25 +8,21 @@ #ifndef __ASM_X86_HVM_ASID_H__ #define __ASM_X86_HVM_ASID_H__ +#include +#include -struct vcpu; -struct hvm_vcpu_asid; +struct hvm_asid { + uint32_t asid; +}; -/* Initialise ASID management for the current physical CPU. */ -void hvm_asid_init(unsigned int nasids); +extern bool asid_enabled; -/* Invalidate a particular ASID allocation: forces re-allocation. */ -void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid); +/* Initialise ASID management distributed across all CPUs. */ +int hvm_asid_init(unsigned long nasids); -/* Invalidate all ASID allocations for specified VCPU: forces re-allocation. */ -void hvm_asid_flush_vcpu(struct vcpu *v); - -/* Flush all ASIDs on this processor core. */ -void hvm_asid_flush_core(void); - -/* Called before entry to guest context. Checks ASID allocation, returns a - * boolean indicating whether all ASIDs must be flushed. */ -bool hvm_asid_handle_vmenter(struct hvm_vcpu_asid *asid); +int hvm_asid_alloc(struct hvm_asid *asid); +int hvm_asid_alloc_range(struct hvm_asid *asid, unsigned long min, unsigned long max); +void hvm_asid_free(struct hvm_asid *asid); #endif /* __ASM_X86_HVM_ASID_H__ */ diff --git a/xen/arch/x86/include/asm/hvm/domain.h b/xen/arch/x86/include/asm/hvm/domain.h index abf9bc448d..03fe6c8f7b 100644 --- a/xen/arch/x86/include/asm/hvm/domain.h +++ b/xen/arch/x86/include/asm/hvm/domain.h @@ -139,6 +139,7 @@ struct hvm_domain { } write_map; struct hvm_pi_ops pi_ops; + struct hvm_asid asid; union { struct vmx_domain vmx; diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index e7c1364802..935d9e7548 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -274,6 +274,8 @@ int hvm_domain_initialise(struct domain *d, void hvm_domain_relinquish_resources(struct domain *d); void hvm_domain_destroy(struct domain *d); +int hvm_flush_tlb(const unsigned long *vcpu_bitmap); + int hvm_vcpu_initialise(struct vcpu *v); void hvm_vcpu_destroy(struct vcpu *v); void hvm_vcpu_down(struct vcpu *v); @@ -497,17 +499,6 @@ static inline void hvm_set_tsc_offset(struct vcpu *v, uint64_t offset) alternative_vcall(hvm_funcs.set_tsc_offset, v, offset); } -/* - * Called to ensure than all guest-specific mappings in a tagged TLB are - * flushed; does *not* flush Xen's TLB entries, and on processors without a - * tagged TLB it will be a noop. - */ -static inline void hvm_flush_guest_tlbs(void) -{ - if ( hvm_enabled ) - hvm_asid_flush_core(); -} - static inline unsigned int hvm_get_cpl(struct vcpu *v) { @@ -901,8 +892,6 @@ static inline int hvm_cpu_up(void) static inline void hvm_cpu_down(void) {} -static inline void hvm_flush_guest_tlbs(void) {} - static inline void hvm_invlpg(const struct vcpu *v, unsigned long linear) { ASSERT_UNREACHABLE(); diff --git a/xen/arch/x86/include/asm/hvm/svm.h b/xen/arch/x86/include/asm/hvm/svm.h index a35a61273b..1877bb149a 100644 --- a/xen/arch/x86/include/asm/hvm/svm.h +++ b/xen/arch/x86/include/asm/hvm/svm.h @@ -9,6 +9,11 @@ #ifndef __ASM_X86_HVM_SVM_H__ #define __ASM_X86_HVM_SVM_H__ +void svm_asid_init(void); +void svm_vcpu_assign_asid(struct vcpu *v); +void svm_vcpu_set_tlb_control(struct vcpu *v); +void svm_vcpu_clear_tlb_control(struct vcpu *v); + /* * PV context switch helpers. Prefetching the VMCB area itself has been shown * to be useful for performance. diff --git a/xen/arch/x86/include/asm/hvm/vcpu.h b/xen/arch/x86/include/asm/hvm/vcpu.h index 836138a4a6..7472cdd0f2 100644 --- a/xen/arch/x86/include/asm/hvm/vcpu.h +++ b/xen/arch/x86/include/asm/hvm/vcpu.h @@ -9,6 +9,7 @@ #define __ASM_X86_HVM_VCPU_H__ #include +#include #include #include #include @@ -16,11 +17,6 @@ #include #include -struct hvm_vcpu_asid { - uint64_t generation; - uint32_t asid; -}; - struct hvm_vcpu_io { /* * HVM emulation: @@ -78,7 +74,7 @@ struct nestedvcpu { bool stale_np2m; /* True when p2m_base in VMCx02 is no longer valid */ uint64_t np2m_generation; - struct hvm_vcpu_asid nv_n2asid; + struct hvm_asid nv_n2asid; bool nv_vmentry_pending; bool nv_vmexit_pending; @@ -142,8 +138,6 @@ struct hvm_vcpu { /* (MFN) hypervisor page table */ pagetable_t monitor_table; - struct hvm_vcpu_asid n1asid; - u64 msr_tsc_adjust; union { diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h index 3524cb3536..4f307ae123 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h @@ -470,7 +470,7 @@ static inline void vpid_sync_vcpu_context(const struct vcpu *v) type = INVVPID_ALL_CONTEXT; execute_invvpid: - __invvpid(type, v->arch.hvm.n1asid.asid, 0); + __invvpid(type, v->domain->arch.hvm.asid.asid, 0); } static inline void vpid_sync_vcpu_gva(struct vcpu *v, unsigned long gva) @@ -494,7 +494,7 @@ static inline void vpid_sync_vcpu_gva(struct vcpu *v, unsigned long gva) type = INVVPID_ALL_CONTEXT; execute_invvpid: - __invvpid(type, v->arch.hvm.n1asid.asid, (u64)gva); + __invvpid(type, v->domain->arch.hvm.asid.asid, (u64)gva); } static inline void vpid_sync_all(void) diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5..156734d3e0 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -750,18 +751,16 @@ static bool cf_check flush_tlb(const unsigned long *vcpu_bitmap) if ( !flush_vcpu(v, vcpu_bitmap) ) continue; - hvm_asid_flush_vcpu(v); - cpu = read_atomic(&v->dirty_cpu); if ( cpu != this_cpu && is_vcpu_dirty_cpu(cpu) && v->is_running ) __cpumask_set_cpu(cpu, mask); } + guest_flush_tlb_mask(d, mask); + /* * Trigger a vmexit on all pCPUs with dirty vCPU state in order to force an - * ASID/VPID change and hence accomplish a guest TLB flush. Note that vCPUs - * not currently running will already be flushed when scheduled because of - * the ASID tickle done in the loop above. + * ASID/VPID flush and hence accomplish a guest TLB flush. */ on_selected_cpus(mask, NULL, NULL, 0); diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index 910623ac93..6eb6035f09 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -1439,7 +1439,6 @@ p2m_flush(struct vcpu *v, struct p2m_domain *p2m) ASSERT(v->domain == p2m->domain); vcpu_nestedhvm(v).nv_p2m = NULL; p2m_flush_table(p2m); - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; } @@ -1499,7 +1498,6 @@ static void assign_np2m(struct vcpu *v, struct p2m_domain *p2m) static void nvcpu_flush(struct vcpu *v) { - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; vcpu_nestedhvm(v).stale_np2m = true; } @@ -1620,7 +1618,6 @@ void np2m_schedule(int dir) if ( !np2m_valid ) { /* This vCPU's np2m was flushed while it was not runnable */ - hvm_asid_flush_core(); curr->needs_tlb_flush = true; vcpu_nestedhvm(curr).nv_p2m = NULL; } diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index b0b3bef753..af5584a777 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -938,7 +938,6 @@ void paging_update_nestedmode(struct vcpu *v) else /* TODO: shadow-on-shadow */ v->arch.paging.nestedmode = NULL; - hvm_asid_flush_vcpu(v); v->needs_tlb_flush = true; } diff --git a/xen/arch/x86/mm/shadow/multi.c b/xen/arch/x86/mm/shadow/multi.c index 2df2842138..0eef92bc5b 100644 --- a/xen/arch/x86/mm/shadow/multi.c +++ b/xen/arch/x86/mm/shadow/multi.c @@ -81,12 +81,6 @@ const char *const fetch_type_names[] = { static pagetable_t cf_check sh_update_cr3(struct vcpu *v, bool noflush); -/* Helper to perform a local TLB flush. */ -static void sh_flush_local(const struct domain *d) -{ - flush_local(guest_flush_tlb_flags(d)); -} - #if GUEST_PAGING_LEVELS >= 4 && defined(CONFIG_PV32) #define ASSERT_VALID_L2(t) \ ASSERT((t) == SH_type_l2_shadow || (t) == SH_type_l2h_shadow) @@ -2947,7 +2941,8 @@ static bool cf_check sh_invlpg(struct vcpu *v, unsigned long linear) if ( mfn_to_page(sl1mfn)->u.sh.type == SH_type_fl1_shadow ) { - sh_flush_local(v->domain); + flush_tlb_local(); + v->needs_tlb_flush = true; return false; } @@ -3164,7 +3159,7 @@ sh_update_linear_entries(struct vcpu *v) * linear pagetable to read a top-level shadow page table entry. But, * without this change, it would fetch the wrong value due to a stale TLB. */ - sh_flush_local(d); + flush_tlb_local(); v->needs_tlb_flush = true; } -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:32:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:32:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282456.1565053 (Exim 4.92) (envelope-from ) id 1wD0M4-0000yz-MS; Wed, 15 Apr 2026 13:32:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282456.1565053; Wed, 15 Apr 2026 13:32:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0M4-0000xS-Ix; Wed, 15 Apr 2026 13:32:32 +0000 Received: by outflank-mailman (input) for mailman id 1282456; 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charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776259950-75358497-AD69C7F1/0/0 X-purgate-type: clean X-purgate-size: 1837 To avoid clobbering all ASIDs that are below SEV-enabled guest maximum, we want to allocate if possible all ASID over a "prefered minimum" and fallback to below otherwise. Signed-off-by: Teddy Astie --- xen/arch/x86/hvm/asid.c | 8 ++++++++ xen/arch/x86/include/asm/hvm/asid.h | 1 + 2 files changed, 9 insertions(+) diff --git a/xen/arch/x86/hvm/asid.c b/xen/arch/x86/hvm/asid.c index 1a21125161..4ad3200c96 100644 --- a/xen/arch/x86/hvm/asid.c +++ b/xen/arch/x86/hvm/asid.c @@ -22,6 +22,9 @@ boolean_param("asid", opt_asid_enabled); bool __read_mostly asid_enabled = false; static unsigned long __ro_after_init *asid_bitmap; static unsigned long __ro_after_init asid_count; + +/* Default minimum ASID to use */ +unsigned long __read_mostly asid_default_min = 0; static DEFINE_SPINLOCK(asid_lock); /* @@ -67,6 +70,11 @@ int hvm_asid_alloc(struct hvm_asid *asid) return 0; } + /* Try to allocate above default minimum */ + if ( asid_default_min && + !hvm_asid_alloc_range(asid, asid_default_min, asid_count) ) + return 0; + spin_lock(&asid_lock); new_asid = find_first_zero_bit(asid_bitmap, asid_count); if ( new_asid > asid_count ) diff --git a/xen/arch/x86/include/asm/hvm/asid.h b/xen/arch/x86/include/asm/hvm/asid.h index 13ea357f70..e989ebbe8c 100644 --- a/xen/arch/x86/include/asm/hvm/asid.h +++ b/xen/arch/x86/include/asm/hvm/asid.h @@ -16,6 +16,7 @@ struct hvm_asid { }; extern bool asid_enabled; +extern unsigned long asid_default_min; /* Initialise ASID management distributed across all CPUs. */ int hvm_asid_init(unsigned long nasids); -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:44:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:44:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282498.1565066 (Exim 4.92) (envelope-from ) id 1wD0Xz-0003zB-IC; Wed, 15 Apr 2026 13:44:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282498.1565066; Wed, 15 Apr 2026 13:44:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0Xz-0003z4-FK; Wed, 15 Apr 2026 13:44:51 +0000 Received: by outflank-mailman (input) for mailman id 1282498; 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b=CWJLQsjDywmikCmPwll4k9l6BwkfqwAt6BJJFPzVZAz4589wppITxJHKQfLrZGGQR WWzeRGjmG7kZJX4KxqRrUAGyGOXf1/9wmsWM/yOaFEclCowfP9K8Si4BuEWcHYeBJR PeJ0IyHfDJywxuXkWa2JO49x0xxvomd+LENjRwN2VjF4De3wsFwChBnRyP9td2PJKc GfrsydVmdCsYurKff8+wvuWg+uPJFhkq5NrTDR+IymbjlIaXJVG80miFp1BAbO/UhH C8+wF5cB/DwhgqeB9sz7idR42eVvNFD245i+R/yHDVQeeTcVOMtwxrDnotE7HRqaoY wVAmQd9mLRwtA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776260687; x=1776521187; i=anthony.perard@vates.tech; bh=//hAjML2pP2vneo2Hm8FFXS2YtyAc4eA0WjPQ7ENl3I=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=kcKALmQok2Xxm7U9tuhtxZ/rLyqDfvZQddaWVbquy75KG6gu3m/gbVslYV2oGzmyH eNqANYyJU8cVP6VVVviMp1yctYFPuOIJZyRHNQ7wZaWmyjp+ys2VPCjG3O/VwgLzKy 5b1zno7bm7bZrZGdAvqAbzQ3/9uHsapJ05mLnJRZgKUSq7HIIt7wapYTkb0D6lCk/r zINaGxiwUCP78RM4bAvVUB4W465lq8s3HFwx+CtabRXWbzLs843TQmPQn0WQ5CnBYo Bu3eNUzK2Ttfcmd21pUbAQvX1WoI+70qASashqf9n+uk1Sybs7+BtVaQ9AYoURfhd+ M1ubXx4nYv9PQ== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20test-artifacts=20v3=2009/13]=20Add=20trigger-test=20job,=20to=20run=20test=20on=20a=20Linux=20built=20from=20a=20branch/tag?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776260686233 To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Andrew Cooper" , "Stefano Stabellini" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" Message-Id: References: <9893108225500bb841a39918942bc9267e62b6af.1774999132.git-series.marmarek@invisiblethingslab.com> In-Reply-To: <9893108225500bb841a39918942bc9267e62b6af.1774999132.git-series.marmarek@invisiblethingslab.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.603041154a0e46c9bf79c06074e1b14a?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:44:47 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1776260688-BFF430B1-0B40947B/0/0 X-purgate-type: clean X-purgate-size: 2617 On Wed, Apr 01, 2026 at 01:21:59AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > When scheduling pipeline in test-artifacts repo, it can get also > TEST_TRIGGER_REPO and TEST_TRIGGER_BRANCH variables, to trigger relevant > pipeline to test just built artifacts. > Pass ARTIFACTS_REPO+ARTIFACTS_BRANCH to the child pipeline to ensure it > fetches artifacts from the right job. > For example, to build linux-next and test Xen staging on it, the > pipeline could be triggered with: > > LINUX_GIT_URL=3Dhttps://git.kernel.org/pub/scm/linux/kernel/git/next/= linux-next.git > LINUX_GIT_VERSION=3Dmaster > TEST_TRIGGER_REPO=3Dxen-project/hardware/xen > TEST_TRIGGER_BRANCH=3Dstaging > > The triggered xen test pipeline will skip most build jobs. > > Signed-off-by: Marek Marczykowski-G=C3=B3recki > --- You might want to add that this depends on two patch for the xen repo, for the trigger to do the expected tests: CI: make test-artifacts repo/branch/job customizable ci: introduce BUILD_FOR_TESTS_ONLY > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > index 62b2a24e7faf..9d90a8f57ff8 100644 > --- a/.gitlab-ci.yml > +++ b/.gitlab-ci.yml > @@ -105,3 +110,18 @@ linux-git-x86_64: > microcode-x86: > extends: .x86_64-artifacts > script: ./scripts/x86-microcode.sh > + > +trigger-test: > + stage: deploy > + trigger: > + project: $TEST_TRIGGER_REPO > + branch: $TEST_TRIGGER_BRANCH > + strategy: mirror > + variables: > + ARTIFACTS_REPO: $CI_PROJECT_PATH > + ARTIFACTS_BRANCH: $CI_COMMIT_REF_NAME > + LINUX_JOB_X86_64: linux-git-x86_64 > + LINUX_JOB_ARM64: linux-git-arm64 > + BUILD_FOR_TESTS_ONLY: 1 Can we add this? inherit: variables: false Otherwise, as I understand, the triggered pipeline will also use the global variables, like TEST_TRIGGER_REPO, LINUX_GIT_VERSION, ... Or I could be wrong because we don't set a default value and the are only manual/scheduled pipeline variable. https://docs.gitlab.com/ci/yaml/#trigger > CI/CD variables defined in a top-level variables section (globally) or > in the trigger job are forwarded to the downstream pipeline as trigger > variables. https://docs.gitlab.com/ci/pipelines/downstream_pipelines/#prevent-default-= variables-from-being-passed I'm not sure if the inherit:variables:false is needed, so: Reviewed-by: Anthony PERARD Thanks, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:54:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:54:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282510.1565083 (Exim 4.92) (envelope-from ) id 1wD0hM-0005zL-GV; Wed, 15 Apr 2026 13:54:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282510.1565083; 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a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776259937; x=1776529937; bh=cDN1jWQB46rVs3zOCKAJTcEcv7n7xu0idZzLK6Twz+k=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=b7YKXzwBRqXevTTdluknHhPQVsV4/0GoTs6tYB6Fl1/uxvl6Il6b+bvwDmz9w4DKS 1ASvxd8tvRDh7cED8IQQci6fjhrNwua4ceUfLUM2pgU/fn2GHfIVaqJ3CcMbA7OJdW BeN/oB+VMZf4Ti008he9IbImrciNxrTbbgbhcZBSFOccWu4MpLgCdrjXuzxiKOyzfY 8U6HdKOwesVOGC8/Pdw3nHkTT4N4l7S2M/M8ypcTGKnMNkKvtbiyEXd8MIAJ3OBbSU zjnUAAZcXrnZOGxgaIZYMARWpKZyRHXhmmOWdLIdynJVaJJGcFWk+5/7E2JT09klrq ZkLTRqhpZKv9Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259937; x=1776520437; i=teddy.astie@vates.tech; bh=cDN1jWQB46rVs3zOCKAJTcEcv7n7xu0idZzLK6Twz+k=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=KOXLsXqTIZ85Ipkyr+nrJkb5ifofsFfgCVQK8WLLIfkdBHiwZNLwzRy2Jas7SZx+p ZcH2lCfnXHQbV95qHbyn6H1jYqgHgefHdykZDPl2UUsoEnsnezHTh0MR22Hz2S+UAp YcJUeC9PLgawjOn3Zbkl2MyUtjzT5yXfAgAI6U788QAv/Z0a7n9bxh/7/SqIJShNT7 lqM4S8si0zgj1+XiMePpZLjZ36qgfPiwGY+yuq7EKfcAwEr0CYU+1ntzeIfCWDJUkb hmlmigMNhcXdun8dQXzWudpPoMmzebfazBzI2qgeE1UTAsb2gzftQp9CaJMeujZYxy KjFAUVnNyuFAg== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=203/7]=20common:=20Introduce=20needs=5Ftlb=5Fflush=20vcpu=20field?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259936778 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Dario Faggioli" , "Juergen Gross" , "George Dunlap" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" Message-Id: <76d570a1b444a0bf2308389d9ed8bef8878b0c96.1776259594.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.58b0a3bb1a944e24a0083559f9875d46?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:17 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776261270-B112D51B-F48AC452/0/0 X-purgate-type: clean X-purgate-size: 1892 This field is meant to be used to schedule a TLB flush on the vCPU before waking it up. This field can be set from another vCPU at any time. Schedule a TLB flush when the vCPU is migrated to another CPU. This is needed as the vCPU-related TLB entries may be out of sync with what happened on another core. Currently, no architecture use this mechanism, but it is meant to be used as a way to schedule a TLB flush on the vCPU. Signed-off-by: Teddy Astie --- xen/common/sched/core.c | 5 +++++ xen/include/xen/sched.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index a57d5dd929..f8e615b3af 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -1188,7 +1188,12 @@ static void sched_unit_migrate_finish(struct sched_unit *unit) /* Wake on new CPU. */ for_each_sched_unit_vcpu ( unit, v ) + { + if ( old_cpu != new_cpu ) + /* Migrating to another CPU needs TLB flush */ + v->needs_tlb_flush = true; vcpu_wake(v); + } } static bool sched_check_affinity_broken(const struct sched_unit *unit) diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 4b8ae21b51..a26c571015 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -224,6 +224,8 @@ struct vcpu bool defer_shutdown; /* VCPU is paused following shutdown request (d->is_shutting_down)? */ bool paused_for_shutdown; + /* VCPU needs its TLB flushed before waking. */ + bool needs_tlb_flush; /* VCPU need affinity restored */ uint8_t affinity_broken; #define VCPU_AFFINITY_OVERRIDE 0x01 -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:54:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:54:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282509.1565075 (Exim 4.92) (envelope-from ) id 1wD0hL-0005mS-B3; Wed, 15 Apr 2026 13:54:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282509.1565075; Wed, 15 Apr 2026 13:54:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0hL-0005mK-7b; Wed, 15 Apr 2026 13:54:31 +0000 Received: by outflank-mailman (input) for mailman id 1282509; Wed, 15 Apr 2026 13:54:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD0hK-0005m8-3y for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259933; x=1776520433; i=teddy.astie@vates.tech; bh=eaNab+1rc2BcfVbepkQ2ytNtOfdi2ILkULRqAk1y38E=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=PnmTODKgc//LggMKpqMw7iWTR+myzszTu9LlC5KJMvO5XDNPczQVz/NPFPmBM97Ba S2XIWqVyYx/EIboX9hEEWxE9vkHLx5liJUQxSa/ZDGE1vFsXYW34f3Hgu2MszunPeF Edai2/ZYM8PELE5eDpO0hDmhCYCusgSGyjTLSDDzEzZZhkkMBPBOTx/wRsCvLyqUXC UdkGtNBtbEpx0pT2ERzKJiDxdvV3xinsbGlWp3E1sbHJ0Pr+dBWpnZdY9c5ceweT8H a8xuG3xbqIH+b0bkVZwL+zWfw31VyCgIY+xI4vVR6VsLfPP3+AeX2iBvkGa0AEj/+7 9voKYG15MGCuw== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=200/7]=20x86:=20Use=20a=20single=20fixed=20ASID=20per=20domain?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259931711 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Jason Andryuk" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Dario Faggioli" , "Juergen Gross" , "George Dunlap" , "Tim Deegan" Message-Id: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.7a1d26ad580a45489050d865f5dd3455?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:13 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776261269-5E12E3D8-65004FE7/0/0 X-purgate-type: clean X-purgate-size: 4934 (ASID can be replaced with VPID for Intel) This patch series is a reorganized version of [1] though, it share the same goal. Not a lot of logic remain from v1/v2 [2] and the patch series is structured quite differently to v3 [1]. Currently in Xen. In order to perform a TLB flush for a guest, we just increment the ASID, which has the same effect as flushing the TLB. When we run out of ASID, we flush the entire TLB and start over. This is done per pCPU, thus the ASID management is done on a per-pCPU basis. However, AMD SEV requires the ASID to be configured in advance and be unique per domain as it bound to the encryption key used for the domain. This patch series propose a new ASID model where a fixed single ASID is attributed to the domain, thus all vCPU share such ASID. Moreover, the TLB for a vCPU is always flushed in these conditions : * the vCPU is migrated to another pCPU (remote pCPU TLB may be out of sync or lack flushes made previously) * a different vCPU of the same domain previously ran on this pCPU (TLB entries comes from the previous vCPU, which may have a different CR3) Albeit related to a SEV vulnerability, [4] gives more justifications on the needs of these rules for correctness. It is also important for making hypervisor-side guest broadcast TLB flushing realistic, as a single fixed ASID per domain allows a broacast TLB flush to use such ASID as target. Moreover, AMD programmer manual also explicitely require this for correctly virtualizing INVLPGB in guests (through 090h:7 ("Enable INVLPGB/TLBSYNC.") in VMCB) : > A guest that executes a legal INVLPGB that is not intercepted will have the requested > ASID field replaced by the current ASID and the valid ASID bit set before doing the > broadcast invalidation. Because of its broadcast nature, the ASID field must be global > and all processors must allocate the same ASID to the same Guest for proper operation. > Hypervisors that do not support a global ASID must intercept the Guest usage of INVLPGB, > if enabled, for proper behavior. In order to avoid making ASID management too complex, transition to only using a fixed ASID per domain. If no ASID is available (e.g out of ASID or ASID usage is diabled), we use ASID=1 as a placeholder (which is still a valid ASID), and always flush the TLB on context switch if the vcpu is using ASID=1. Also add a way to specify a prefered minimum ASID, it is meant to be used later on to avoid clobbering the low ASID space of SEV-ES and favor allocating ASIDs over that space. [1] x86/hvm: Introduce Xen-wide ASID allocator https://lore.kernel.org/xen-devel/cover.1750770621.git.teddy.astie@vates.tech/ [2] x86/hvm: Introduce Xen-wide ASID allocator https://lore.kernel.org/xen-devel/cover.1723574652.git.vaishali.thakkar@vates.tech/ [4] TLB Poisoning Attacks on AMD Secure Encrypted Virtualization https://dl.acm.org/doi/epdf/10.1145/3485832.3485876 Teddy Astie (7): vmx: Introduce vcpu single context VPID invalidation common: Track latest pCPU that ran the vCPU common: Introduce needs_tlb_flush vcpu field x86: Set v->needs_tlb_flush when needed x86/hvm: Flush TLB on vCPU overlaps on the same pCPU x86/hvm: Transition to needs_tlb_flush logic, use per-domain ASID hvm: Allow specifying a prefered asid minimum docs/misc/xen-command-line.pandoc | 2 +- xen/arch/x86/flushtlb.c | 22 +-- xen/arch/x86/hvm/asid.c | 177 +++++++++++-------------- xen/arch/x86/hvm/emulate.c | 2 +- xen/arch/x86/hvm/hvm.c | 25 +++- xen/arch/x86/hvm/nestedhvm.c | 7 +- xen/arch/x86/hvm/svm/asid.c | 67 +++++++--- xen/arch/x86/hvm/svm/nestedsvm.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 47 +++++-- xen/arch/x86/hvm/svm/svm.h | 4 - xen/arch/x86/hvm/vmx/vmcs.c | 6 +- xen/arch/x86/hvm/vmx/vmx.c | 77 ++++++----- xen/arch/x86/hvm/vmx/vvmx.c | 4 +- xen/arch/x86/include/asm/flushtlb.h | 7 - xen/arch/x86/include/asm/hvm/asid.h | 27 ++-- xen/arch/x86/include/asm/hvm/domain.h | 1 + xen/arch/x86/include/asm/hvm/hvm.h | 15 +-- xen/arch/x86/include/asm/hvm/svm.h | 5 + xen/arch/x86/include/asm/hvm/vcpu.h | 10 +- xen/arch/x86/include/asm/hvm/vmx/vmx.h | 23 +++- xen/arch/x86/mm/hap/hap.c | 9 +- xen/arch/x86/mm/p2m.c | 7 +- xen/arch/x86/mm/paging.c | 2 +- xen/arch/x86/mm/shadow/multi.c | 12 +- xen/common/domain.c | 8 ++ xen/common/sched/core.c | 5 + xen/include/xen/sched.h | 6 + 27 files changed, 319 insertions(+), 260 deletions(-) -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:54:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:54:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282512.1565094 (Exim 4.92) (envelope-from ) id 1wD0hR-0006HS-TD; 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dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776259942; x=1776529942; bh=BuRU+2TlBcBTTb5Q+25wdwHHW2PQBda97rbEBk2HBMg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=apafzCn1D7dkgCAP+0AjQlCovSuawJ7U/aO/D63ik+eRQX5BuBCfKkFM0hys+l4MS yCt7cCc2xU91kZ48za/Eu+Rn3C7g8CtdCiJ+xDH64IcWxSSMNYIpfTh7cmYy4dx6sv nuoB4tDfEYzJakMU6ziW2flgBRMnIVA08FWOcLEGgQJeNAxs88j78lJHJrwv/LTOzu 09LdE9FaEi6u5x+a0MEfU9b9d19PrkUrG6y2msQalKXtW7VJq2iffuGWM2VIzHCiuT 5u+OUB1dTUZ06cd1sggMHedQF7NabDHv/rAhdSba94ppi8ZGMiGAHHNsdzS93+QctT GDh1mcioHVj0Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776259942; x=1776520442; i=teddy.astie@vates.tech; bh=BuRU+2TlBcBTTb5Q+25wdwHHW2PQBda97rbEBk2HBMg=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=hI2Bdf1HB2413BPp4DlZ3xzYuvIoZXqhgjQwJTZT95WWdYYyvv1uTmZrqBSxwG/kV gbi9lsO0BQLwyIJHb00h2ces0yaBJhWBuL5CZhc5X/s94EHKXF87eo2Pv2vlzwOJQ4 1sWyBN4sdrsibmP2RnQyaSX/1V0364bh+XG2+ZtAvmvJyOl4QusgTISD1Hsq7q29um 4HnSZu1I5qN6AJRSmdjR+0N5PvU0Y+gOzDtmw/FIai6aKYW8vOjrxiIhjYCvtBj+37 gxRIl/8BP10jHRKB/0soWoYwi9PCDO+cKdDvp8Ilwz+RIiml/H7UuvEJznFP4Yifgl irKu+6nyNL52A== From: "Teddy Astie" Subject: =?utf-8?Q?[RFC=20PATCH=205/7]=20x86/hvm:=20Flush=20TLB=20on=20vCPU=20overlaps=20on=20the=20same=20pCPU?= X-Mailer: git-send-email 2.52.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776259941217 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Jason Andryuk" Message-Id: In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.4a8938bac7ba4f1da0b2eca74ce48353?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260415:md Date: Wed, 15 Apr 2026 13:32:22 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776261276-0FF430B1-C81FA595/0/0 X-purgate-type: clean X-purgate-size: 2201 When using the same ASID/VPID for all vCPU of a domain, we need to make sure that when context switching between 2 vCPUs of the same domain on the same pCPU don't miss a TLB flush, as they may be using different CR3. Flush the TLB if the latest vCPU that ran on this core differ to the one we're currently on. Signed-off-by: Teddy Astie --- Would it be preferable to move it to common code (or shared logic for x86). xen/arch/x86/hvm/svm/svm.c | 8 ++++++++ xen/arch/x86/hvm/vmx/vmx.c | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 64c08432fd..8714fb18ec 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -981,6 +981,14 @@ void asmlinkage svm_vmenter_helper(void) svm_sync_vmcb(curr, vmcb_needs_vmsave); + /** + * Check if we were the latest vCPU of this domain that ran on this pCPU. + * Flush the TLB if it is not, as the TLB entries are the ones from the previous + * vCPU. vCPU migration from a CPU to another always imply a TLB flush. + */ + if ( curr->domain->latest_vcpu[cpu] != curr->vcpu_id ) + curr->needs_tlb_flush = true; + curr->domain->latest_vcpu[cpu] = curr->vcpu_id; vmcb->rax = regs->rax; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0e4f9f9c3d..dceff2f221 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4980,6 +4980,13 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( unlikely(need_flush) ) vpid_sync_all(); + /** + * Check if we were the latest vCPU of this domain that ran on this pCPU. + * Flush the TLB if it is not, as the TLB entries are the ones from the previous + * vCPU. vCPU migration from a CPU to another always imply a TLB flush. + */ + if ( currd->latest_vcpu[cpu] != curr->vcpu_id ) + curr->needs_tlb_flush = true; currd->latest_vcpu[cpu] = curr->vcpu_id; -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Wed Apr 15 13:55:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 13:55:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282537.1565102 (Exim 4.92) (envelope-from ) id 1wD0iE-0007FR-55; Wed, 15 Apr 2026 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A > subsequent handle_remove_overlay_nodes() for the same overlay will call > rangeset_consume_ranges() on freed memory followed by a second > rangeset_destroy(), resulting in use-after-free and double-free. >=20 > NULL the pointers after rangeset_destroy() so that remove_nodes() and > handle_remove_overlay_nodes() skip the stale entries. >=20 > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attac= hment to domains") > Reported-by: Gyujeong Jin > Signed-off-by: Michal Orzel > --- Looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 14:51:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 14:51:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282584.1565145 (Exim 4.92) (envelope-from ) id 1wD1aK-0000Jn-Uu; Wed, 15 Apr 2026 14:51:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282584.1565145; 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With Xen swiotlb, devices may use per-device coherent DMA memory, such as reserved-memory regions described by 'shared-dma-pool', which are assigned to dev->dma_mem. These regions may be marked no-map in DT and therefore are not part of the kernel linear map. In such cases, pfn_valid() still returns true, but phys_to_virt() is not valid and cache maintenance via arch_sync_dma_* will fault. Prevent this by excluding devices with a private DMA memory pool (dev->dma_mem) from the arch_sync_dma_* fast path, and always fall back to xen_dma_sync_* for those devices to avoid invalid phys_to_virt() conversions for no-map DMA memory while preserving the existing fast path for normal, linear-mapped RAM. Signed-off-by: Peng Fan --- drivers/xen/swiotlb-xen.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c index 2cbf2b588f5b20cfbf9e83a8339dc22092c9559a..b1445df99d9a8f1d18a83b8c413bada6e5579209 100644 --- a/drivers/xen/swiotlb-xen.c +++ b/drivers/xen/swiotlb-xen.c @@ -195,6 +195,11 @@ xen_swiotlb_free_coherent(struct device *dev, size_t size, void *vaddr, } #endif /* CONFIG_X86 */ +static inline bool dev_has_private_dma_pool(struct device *dev) +{ + return dev && dev->dma_mem; +} + /* * Map a single buffer of the indicated size for DMA in streaming mode. The * physical address to use is returned. @@ -262,7 +267,8 @@ static dma_addr_t xen_swiotlb_map_phys(struct device *dev, phys_addr_t phys, done: if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr)))) { + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr))) && + !dev_has_private_dma_pool(dev)) { arch_sync_dma_for_device(phys, size, dir); arch_sync_dma_flush(); } else { @@ -289,7 +295,8 @@ static void xen_swiotlb_unmap_phys(struct device *hwdev, dma_addr_t dev_addr, BUG_ON(dir == DMA_NONE); if (!dev_is_dma_coherent(hwdev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { - if (pfn_valid(PFN_DOWN(dma_to_phys(hwdev, dev_addr)))) { + if (pfn_valid(PFN_DOWN(dma_to_phys(hwdev, dev_addr))) && + !dev_has_private_dma_pool(hwdev)) { arch_sync_dma_for_cpu(paddr, size, dir); arch_sync_dma_flush(); } else { @@ -312,7 +319,8 @@ xen_swiotlb_sync_single_for_cpu(struct device *dev, dma_addr_t dma_addr, struct io_tlb_pool *pool; if (!dev_is_dma_coherent(dev)) { - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr)))) { + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr))) && + !dev_has_private_dma_pool(dev)) { arch_sync_dma_for_cpu(paddr, size, dir); arch_sync_dma_flush(); } else { @@ -337,7 +345,8 @@ xen_swiotlb_sync_single_for_device(struct device *dev, dma_addr_t dma_addr, __swiotlb_sync_single_for_device(dev, paddr, size, dir, pool); if (!dev_is_dma_coherent(dev)) { - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr)))) { + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr))) && + !dev_has_private_dma_pool(dev)) { arch_sync_dma_for_device(paddr, size, dir); arch_sync_dma_flush(); } else { --- base-commit: 66672af7a095d89f082c5327f3b15bc2f93d558e change-id: 20260415-xen-swiotlb-34a198b6c1d6 Best regards, -- Peng Fan From xen-devel-bounces@lists.xenproject.org Wed Apr 15 15:07:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 15:07:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282600.1565162 (Exim 4.92) (envelope-from ) id 1wD1pc-0002ZH-FS; Wed, 15 Apr 2026 15:07:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282600.1565162; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WGNzcKgl3sx57pMnvKRQmgMV6S3leysZQVVN/FFY8NMR16Pm54cLpe2x/+JTXtL5cBIVO3Q4WbHGsVXAY7jWMQk7iQ6GhlDomn2rgqMkbksGsLpMJiMGCv7cagrhXO4WUrE8elqtv/520oVK43drXgMvMJ99prXImS7Hnko/V8pOiWzemJyezs3vTtE9FZ9JeTtmzbJfRjtBJNSWcdsfVRpSMbUFPw3C8Zg8xttj16PYaczDpPgg2inFbuYkqnOHi1fWgJUtP1BifmPA6AAiAS0nDn3h03Z+nYb3wQuH8C/qpfSr66qGa+5B+HKCR9NzN3kleaPoNFzEFhWrL2XXHFCqNoudvMzqrVkm0LQmf5L7ESbxAKnZwgYGfL/E4TGzULkvn90Vepcrdlbm5kJoIswUl0xVUTLloMUp6IM0SJO9hUDnSYOOoSkjsg/cjc+2 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 15:06:57.2634 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cba028a4-ced4-44ea-d482-08de9b00a333 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00025F9B.EURPRD83.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB11398 X-purgate-ID: tlsNG-d62444/1776265625-B6C7CFF4-628C6E80/0/0 X-purgate-type: clean X-purgate-size: 829 Hi Michal, > On 15 Apr 2026, at 12:36, Michal Orzel wrote: >=20 > handle_attach_overlay_nodes() unconditionally creates new rangesets > without checking whether they already exist from a prior attach. A > repeated attach for the same overlay leaks the original pair. Reject the > operation with -EEXIST if rangesets are already present. >=20 > Also, dt_overlay_domctl() early-returns -EOPNOTSUPP for any operation > other than ATTACH, making the if/else at the bottom unreachable. Remove > the dead branch. >=20 > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attac= hment to domains") > Reported-by: Jan Beulich > Signed-off-by: Michal Orzel > --- Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 15:08:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 15:08:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282613.1565171 (Exim 4.92) (envelope-from ) id 1wD1r4-0003NJ-SX; Wed, 15 Apr 2026 15:08:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282613.1565171; Wed, 15 Apr 2026 15:08:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD1r4-0003NC-PD; Wed, 15 Apr 2026 15:08:38 +0000 Received: by outflank-mailman (input) for mailman id 1282613; Wed, 15 Apr 2026 15:08:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD1r2-0003N4-T6 for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KUka7StHsfWCBQzJuEPq63YWbjgnQ+bLSKCRyCc8SkADLKjW1JErYkx2wHQR8V2qXTXozcSFoe4UTMn4b4Zeek5v1G5amOuovg4AGfHx/LS8ph73MFQ4Tn1GWpYIi0qR5o2LiC6/HtAlpVae99BGD8tf3wpFuMW5/FcTCDAv0oBu8WyS7p50g0QYmTxMYlw8sBbKMaTOtxYcOpsxMGS47aFlybqGeeXMH/H4ba2E6YsSeTTZc6i09k9ZAy0rH0O197Q+9TVm80GTYNRm4HNrmTCGrKyfbQ+rwQNBTWEa4z0FHK9TcbzeIZzr8K+kI9vpZZqUSha4vMNtvrAy17RKmzkvrs+V0PA932vhYS0cz1ZPV++CGyHdle0TBtW5EQ/k4eU2SnFRf0FnNuKAEzKDkl7x7XSqY27eHcUixwHgvqmG9Q0dg4gCfjeKWqjpfVOV X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 15:08:32.5815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6ab5b90-8480-4678-0aa7-08de9b00dc05 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FE.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9599 X-purgate-ID: tlsNG-720697/1776265716-4C9F4CD1-EB663FD4/0/0 X-purgate-type: clean X-purgate-size: 852 Hi Michal, > On 15 Apr 2026, at 12:36, Michal Orzel wrote: >=20 > find_track_entry_from_tracker() compares overlay_fdt_size bytes of the > stored overlay against the input without verifying that the stored > overlay is at least that large. If the input is larger, memcmp reads > past the stored allocation. If smaller, a prefix match could falsely > succeed. >=20 > Compare fdt_totalsize() of the stored overlay against overlay_fdt_size > first. Both values are validated by check_overlay_fdt() at their > respective entry points, so no additional field in overlay_track is > needed. >=20 > Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functio= nalities") > Signed-off-by: Michal Orzel > --- Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 15:10:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 15:10:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282622.1565179 (Exim 4.92) (envelope-from ) id 1wD1sV-0004qs-6m; Wed, 15 Apr 2026 15:10:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282622.1565179; Wed, 15 Apr 2026 15:10:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD1sV-0004ql-3z; Wed, 15 Apr 2026 15:10:07 +0000 Received: by outflank-mailman (input) for mailman id 1282622; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wE5hhejPz/YuWNqjdJhH1/auktcjaP6+6eaaPvOGswtbDEzpC01bJAdCuhZqhkG4YKHpbSOgectcL/53I2vIWOSuW1DdnLsii2R/BVMcXmMQxovagGRw2h9RC3ORSz42p5yr3w20HOLqZClBLyxe6qYe9D/B0zH9NmfWqesDwFvCkPaWImYQ+tqNDfLFtS0SB/P+CHtvgTyIMvt/BHL95N4fSMy/xjjMAzFMr+Ckj9GLaZuXe2mWuMDiBCgOrIzVkJsDSpBWomsGkWvuw48xOR15M45XbFilWw2h3UdqPm1CBekbZ40APscHoaLcZnzwpWnMP6gBWL3383l5sJBli7kXw9lMHVhDuQwILzExz+vmZTpYE/yiYUQSPQMOxkaMDoU8Gx3VZLFnu8pyIk+zlHwLsS+PMXs9pggOpRIjzjkkGAiIZ8PKK6ucHWRNhSQh X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 15:10:00.3837 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d58bb97-4278-4dfe-c3f9-08de9b01105a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D0A.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6464 X-purgate-ID: tlsNG-16d1c6/1776265804-AFB3B3D8-6092D58F/0/0 X-purgate-type: clean X-purgate-size: 760 Hi Michal, > On 15 Apr 2026, at 12:36, Michal Orzel wrote: >=20 > dt_overlay_remove_node() silently returns 0 when the target node is not > found in the parent's sibling list. The loop simply exits without > matching and falls through to "return 0", making the caller believe the > node was successfully removed. >=20 > Return -ENODEV after the loop when no match is found, and change the > found-path from break to an explicit return 0 so the two outcomes are > distinct. >=20 > Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functio= nalities") > Signed-off-by: Michal Orzel > --- Looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 15:37:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 15:37:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282643.1565189 (Exim 4.92) (envelope-from ) id 1wD2Io-00089t-9P; Wed, 15 Apr 2026 15:37:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282643.1565189; Wed, 15 Apr 2026 15:37:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD2Io-00089m-6X; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nCq/u2LFqRsswlbdHi83VeHeTxfRNRNTg65EbGHz6utUMMaDit9givSV28zjpgUgm+4ZG6COjMnBTurmf5nQ4HXgV7nX8SBZqeXbHH1OmlFyxfDlQa/ZNaFeAcUGzD5Z2dEEmzjtezC12DsrdslVmM6vPum8m3tj/ujQpZ6vOlfv39TGqulykw3lD1+F9HXCs3k5/CDS21wNK7L3MP5hq2kpkCwyIOxxJ7sGISztjImffMow+JlDYY6d2PqSIzi0RUVqZ3ezXYEq7myKeS+cWEXF53CNS6e+CrZoSvvEv25Db59QElYGBAdkZ9Xd3TsCHX151EPb4NyEWQfyVWm39fNkmdlaJo7kvnIhVq7L5xGAP+ihS7JM0iRHMIIVrJaWBY5DkmoQKaiwEaLYkO1Ko5ESSaz5ngpYWVJ4WbT3X5q/BZNUSSeg3oHAg8G7nRr1 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 15:37:09.6349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb2436c4-433a-4763-9a3d-08de9b04db77 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF00039231.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB10974 X-purgate-ID: tlsNG-bad1c0/1776267436-5674A152-07F72940/0/0 X-purgate-type: clean X-purgate-size: 5099 Hi Michal, > On 15 Apr 2026, at 12:36, Michal Orzel wrote: >=20 > overlay_get_nodes_info() is called before fdt_overlay_apply() to extract > target paths from the overlay. This fails for overlays using phandle-base= d > targeting (target =3D <&label>) because DTC compiles these as unresolved > fixups (target =3D <0xffffffff>), causing fdt_overlay_target_offset() to > return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to > manually modify the dtbo (even for hwdom) to switch from target to > target-phandle by manually inspecting also the host DTB. >=20 > Introduce overlay_get_target_path() which directly handles the two > targeting cases that occur before fixup resolution: > - target-path: the string property is returned directly. > - target =3D <&label>: the label is found in the overlay's __fixups__ > node, then resolved to a path via the base DTB's __symbols__ node. >=20 > Signed-off-by: Michal Orzel > --- > xen/common/device-tree/dt-overlay.c | 65 ++++++++++++++++++++++++++--- > 1 file changed, 59 insertions(+), 6 deletions(-) >=20 > diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree= /dt-overlay.c > index d3d4669718ac..a0dee7edb7e5 100644 > --- a/xen/common/device-tree/dt-overlay.c > +++ b/xen/common/device-tree/dt-overlay.c > @@ -286,6 +286,63 @@ static unsigned int overlay_node_count(const void *o= verlay_fdt) > return num_overlay_nodes; > } >=20 > +/* > + * Resolve the target path for an overlay fragment. > + * > + * This is called before fdt_overlay_apply(), so phandle-based targets > + * (target =3D <&label>) are still unresolved (compiled as 0xffffffff by= DTC). > + * Handle the two cases that actually occur: > + * - target-path property: the path string is used directly, > + * - target =3D <&label>: the label is looked up in the overlay's __fix= ups__ > + * node, then resolved to a path via the base DTB's __symbols__ node. > + * > + * Returns a pointer into the FDT on success, NULL on failure. > + */ > +static const char *overlay_get_target_path(const void *fdt, const void *= fdto, > + int fragment) > +{ > + const char *path, *fragment_name; > + int fixups_off, symbols_off, property; > + int fragment_name_len; > + > + /* Try target-path first (string-based targeting) */ > + path =3D fdt_getprop(fdto, fragment, "target-path", NULL); > + if ( path ) > + return path; > + > + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ > + fixups_off =3D fdt_path_offset(fdto, "/__fixups__"); > + if ( fixups_off < 0 ) > + return NULL; > + > + symbols_off =3D fdt_path_offset(fdt, "/__symbols__"); > + if ( symbols_off < 0 ) > + return NULL; > + > + fragment_name =3D fdt_get_name(fdto, fragment, &fragment_name_len); > + if ( !fragment_name ) > + return NULL; > + > + fdt_for_each_property_offset(property, fdto, fixups_off) > + { > + const char *val, *label, *p; > + int val_len; > + > + val =3D fdt_getprop_by_offset(fdto, property, &label, &val_len); > + if ( !val ) > + continue; > + > + /* Match entries of the form "/:target:0" */ > + for ( p =3D val; p < (val + val_len); p +=3D (strlen(p) + 1) ) what guarantees us that p will be null terminated, if a malformed overlay is passed this strlen can read past the string, we can use strnlen having a= s upper bound a counter=3Dval_len? decreasing counter each iteration. Or do you think it can never happen? > + if ( p[0] =3D=3D '/' && > + !strncmp(p + 1, fragment_name, fragment_name_len) && > + !strcmp(p + 1 + fragment_name_len, ":target:0") ) > + return fdt_getprop(fdt, symbols_off, label, NULL); > + } > + > + return NULL; > +} > + > /* > * overlay_get_nodes_info gets full name with path for all the nodes whic= h > * are in one level of __overlay__ tag. This is useful when checking node= for > @@ -298,7 +355,6 @@ static int overlay_get_nodes_info(const void *fdto, c= har **nodes_full_path) >=20 > fdt_for_each_subnode(fragment, fdto, 0) > { > - int target; > int overlay; > int subnode; > const char *target_path; > @@ -307,11 +363,8 @@ static int overlay_get_nodes_info(const void *fdto, = char **nodes_full_path) > if ( overlay < 0 ) > continue; >=20 > - target =3D fdt_overlay_target_offset(device_tree_flattened, fdto= , > - fragment, &target_path); > - if ( target < 0 ) > - return target; > - > + target_path =3D overlay_get_target_path(device_tree_flattened, f= dto, > + fragment); > if ( target_path =3D=3D NULL ) > return -EINVAL; >=20 > --=20 > 2.43.0 >=20 >=20 Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 15:57:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 15:57:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282653.1565197 (Exim 4.92) (envelope-from ) id 1wD2c3-0002lN-Qo; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: crVFjz3jy1+BY9v6wqWUaqUqOV19YFVKz2IxTZLI5DaSM75n7w394A1bpfKdbO6NwFZxd0FyON2KwhGHvhAw9dAbd415LSJ9RQab+t5aEObhBe4MIllg7josHLj2aK48JtJ01FQ/jxMphu74n2zLg95au+BFuf2NUQwLHCdU4NQ4IVkWanrJGlboS+cH8gQLK01eVdUp7/bfwm2Oi1cCOzgqCYxrIDk5IveHrftmGAjlxawOVhkxIXLKtwlkTpYL2cg2DCtNa1dhZF/1CtcA9HlX+DcWfQ6dhr/l6raErG4mKYUxTy6Yrv7sVI9S0dW4lsqbCwpJPDvND5BVNf6ZRQmXhmjTd+ScD9bhW/k85Uj4X2nqR7WRxNaqrXyMck3lR7Duw4z0dvcx/TZ65jG2m2D4OTa6iPpSVVvriCTf1BHkxZsL0Ms8y/pipmxbHTZN X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 15:57:00.5559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7e0988e-fe14-42d7-3609-08de9b07a14d X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF0000004A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB10152 X-purgate-ID: tlsNG-d25034/1776268629-80D5BA3D-FDB42907/0/0 X-purgate-type: clean X-purgate-size: 1105 Hi Michal, > On 15 Apr 2026, at 12:37, Michal Orzel wrote: >=20 > handle_attach_overlay_nodes() only calls handle_device() on the > top-level overlay nodes tracked in entry->nodes_address[]. Child nodes > that have their own reg, interrupts, or iommus properties are never > processed, so their IRQs are not routed, MMIO regions are not mapped, > and IOMMU setup is skipped. >=20 > Introduce handle_device_and_children() which recursively walks the > subtree rooted at each overlay node and calls handle_device() on every > descendant, ensuring all resources in the overlay are properly attached. >=20 > Note that the attach error path has a pre-existing bug: on partial > failure, the tracking rangesets are destroyed without first revoking the > IRQ/MMIO permissions and IOMMU assignments that were already granted by > the successful handle_device() calls. Add a TODO comment to flag this. >=20 > Signed-off-by: Michal Orzel > --- >=20 Looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:40:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:40:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282686.1565208 (Exim 4.92) (envelope-from ) id 1wD4E2-0000GT-MY; Wed, 15 Apr 2026 17:40:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282686.1565208; Wed, 15 Apr 2026 17:40:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4E2-0000GK-I8; Wed, 15 Apr 2026 17:40:30 +0000 Received: by outflank-mailman (input) for mailman id 1282686; Wed, 15 Apr 2026 17:40:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4E1-0000GE-JY for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="CaGGDZKULuvCeH9e" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-c201ff/1776274827-2292196F-228500A5/0/0 X-purgate-type: clean X-purgate-size: 4409 --CaGGDZKULuvCeH9e Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 15 Apr 2026 19:40:19 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Anthony PERARD Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH test-artifacts v3 09/13] Add trigger-test job, to run test on a Linux built from a branch/tag On Wed, Apr 15, 2026 at 01:44:47PM +0000, Anthony PERARD wrote: > On Wed, Apr 01, 2026 at 01:21:59AM +0200, Marek Marczykowski-G=C3=B3recki= wrote: > > When scheduling pipeline in test-artifacts repo, it can get also > > TEST_TRIGGER_REPO and TEST_TRIGGER_BRANCH variables, to trigger relevant > > pipeline to test just built artifacts. > > Pass ARTIFACTS_REPO+ARTIFACTS_BRANCH to the child pipeline to ensure it > > fetches artifacts from the right job. > > For example, to build linux-next and test Xen staging on it, the > > pipeline could be triggered with: > > > > LINUX_GIT_URL=3Dhttps://git.kernel.org/pub/scm/linux/kernel/git/nex= t/linux-next.git > > LINUX_GIT_VERSION=3Dmaster > > TEST_TRIGGER_REPO=3Dxen-project/hardware/xen > > TEST_TRIGGER_BRANCH=3Dstaging > > > > The triggered xen test pipeline will skip most build jobs. > > > > Signed-off-by: Marek Marczykowski-G=C3=B3recki > > --- >=20 > You might want to add that this depends on two patch for the xen repo, > for the trigger to do the expected tests: > CI: make test-artifacts repo/branch/job customizable > ci: introduce BUILD_FOR_TESTS_ONLY >=20 > > diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml > > index 62b2a24e7faf..9d90a8f57ff8 100644 > > --- a/.gitlab-ci.yml > > +++ b/.gitlab-ci.yml > > @@ -105,3 +110,18 @@ linux-git-x86_64: > > microcode-x86: > > extends: .x86_64-artifacts > > script: ./scripts/x86-microcode.sh > > + > > +trigger-test: > > + stage: deploy > > + trigger: > > + project: $TEST_TRIGGER_REPO > > + branch: $TEST_TRIGGER_BRANCH > > + strategy: mirror > > + variables: > > + ARTIFACTS_REPO: $CI_PROJECT_PATH > > + ARTIFACTS_BRANCH: $CI_COMMIT_REF_NAME > > + LINUX_JOB_X86_64: linux-git-x86_64 > > + LINUX_JOB_ARM64: linux-git-arm64 > > + BUILD_FOR_TESTS_ONLY: 1 >=20 > Can we add this? > inherit: > variables: false >=20 > Otherwise, as I understand, the triggered pipeline will also use the > global variables, like TEST_TRIGGER_REPO, LINUX_GIT_VERSION, ... Or I > could be wrong because we don't set a default value and the are only > manual/scheduled pipeline variable. >=20 > https://docs.gitlab.com/ci/yaml/#trigger > > CI/CD variables defined in a top-level variables section (globally) or > > in the trigger job are forwarded to the downstream pipeline as trigger > > variables. >=20 > https://docs.gitlab.com/ci/pipelines/downstream_pipelines/#prevent-defaul= t-variables-from-being-passed Hm, yes, inherit:variables:false might be needed if we'd want to avoid passing those variables. But, TBH I'm not sure if we want to avoid that - it might be useful at some point to get LINUX_GIT_VERSION there, for example.=20 > I'm not sure if the inherit:variables:false is needed, so: > Reviewed-by: Anthony PERARD >=20 > Thanks, >=20 >=20 > -- > Anthony Perard | Vates XCP-ng Developer >=20 > XCP-ng & Xen Orchestra - Vates solutions >=20 > web: https://vates.tech >=20 >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --CaGGDZKULuvCeH9e Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmnfzYMACgkQ24/THMrX 1yx8Xwf/XSWAbi0mIjPs1NEu6gFMy2T5CYBtFs5hZkffz7lLVAKUbS5PHBLsMBKh 98gCov1nT1b9ZYVhEB/0fDjhMF4LyQNOhD/flAkcBR/iLSaz9jftt9u0qdeXRBjx FBTSxsLT4NvthLgUB+hcFJfGY2/2IWsznVTLkg58UnLnCEiLyie7ovMbHTRgvN2H C+a5+4YrnCEU6XdLRDSYmMEhcgmZZQKybGZgy7i8+68zrJT85CL33yElh4W0jhja 1mFVrOYHz4ZlHVti4HYF8TILSF5ck8L3mmW9NHiL2VQ1ZEz6YTiBmGgOHUL/CJYF A/VFCVCHiAM4UJM24XtD6TE+mzLigw== =qeFz -----END PGP SIGNATURE----- --CaGGDZKULuvCeH9e-- From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:46:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:46:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282694.1565216 (Exim 4.92) (envelope-from ) id 1wD4JG-0000pD-7o; Wed, 15 Apr 2026 17:45:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282694.1565216; Wed, 15 Apr 2026 17:45:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4JG-0000p6-4M; Wed, 15 Apr 2026 17:45:54 +0000 Received: by outflank-mailman (input) for mailman id 1282694; Wed, 15 Apr 2026 17:45:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4JF-0000oy-CK for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 17:45:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wD4JE-00Dvab-Ly for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 19:45:52 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69dfceaf-2eae-0a2a0a5409dd-0a2a4505d5e0-30 for ; Wed, 15 Apr 2026 19:45:52 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dfcecf-3760-0a2a45050019-a06583098b08-3 for ; Wed, 15 Apr 2026 19:45:52 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 7B8CB81C0CF2; Wed, 15 Apr 2026 13:44:57 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 0/4] xen/mm: Host-side unit/integration test framework for page_alloc.c Date: Wed, 15 Apr 2026 18:34:55 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1776275152-21B3896F-8A0D6962/0/0 X-purgate-type: clean X-purgate-size: 4597 Hi all, This patch series adds a host-side unit and integration test framework for the Xen page allocator in xen/common/page_alloc.c. Using this framework, it also adds a host-side integration test suite for memory claims, including NUMA-aware claim sets. This test suite complements the functional system tests submitted as part of the NUMA-aware claims v6 series yesterday. The purpose is to verify the behaviour of the page allocator when multi-node claim sets are present in situations that are easier to create and validate in isolation, with full control over a synthetic Xen heap state and visibility into the claim state of domains as claims are made and redeemed through heap allocation. This series depends on the NUMA claims v6 series, which introduced NUMA-aware claim sets which I submitted yesterday: [PATCH v6 0/7] xen/mm: Introduce NUMA-aware claim sets for domains https://lists.xen.org/archives/html/xen-devel/2026-04/msg00587.html https://patchwork.kernel.org/project/xen-devel/list/?series=1081139 Its design is described in this design document submitted yesterday: [PATCH v2] docs: Draft Design Document for NUMA-aware claim sets https://lists.xen.org/archives/html/xen-devel/2026-04/msg00569.html https://patchwork.kernel.org/project/xen-devel/list/?series=1081047 Patch summary: 1. tools/tests/alloc: Add test framework for xen/common/page_alloc.c 2. tools/tests/alloc: Add integration tests for claims and claim sets 3. tools/tests/alloc: Add tests for offlining with claims present 4. xen/mm: Fix recalling claims when offlining pages if needed Thanks, Bernhard Kaindl --- PS: The bug fixed in the last commit of this series affects global outstanding claims as implemented in current Xen master as well. However, this only arises when Xen offlines pages. Page offlining code in current Xen still has known limitations, particularly when offlining pages from larger buddies, and should be avoided in the interest of heap integrity. That said, this test framework makes it possible to run targeted test cases on a synthetic Xen heap and observe logged changes to the heap during page offlining. That should make further offlining fixes easier to validate, both by checking the test results and by inspecting the resulting heap state. If you are interested in that, the next series will add a test suite for offlining pages using this test framework. That should make it possible to observe the effects of the bugs and the corresponding fixes on any machine able to compile Xen source code. Bernhard Kaindl (4): tools/tests/alloc: Unit and Integration Test Framework for page_alloc.c tools/tests/alloc: Add integration test suite for memory claims tools/tests/alloc: Add tests for offlining with claims present xen/mm: Recall claims when offlining pages if needed tools/tests/Makefile | 1 + tools/tests/alloc/.gitignore | 6 + tools/tests/alloc/Makefile | 141 ++++++ tools/tests/alloc/README.rst | 31 ++ tools/tests/alloc/check-asserts.h | 347 +++++++++++++++ tools/tests/alloc/harness.h | 69 +++ tools/tests/alloc/hypervisor-macros.h | 101 +++++ tools/tests/alloc/libtest-page_alloc.h | 356 +++++++++++++++ tools/tests/alloc/mock-page_list.h | 307 +++++++++++++ tools/tests/alloc/page_alloc-wrapper.h | 465 ++++++++++++++++++++ tools/tests/alloc/page_alloc_shim.h | 433 ++++++++++++++++++ tools/tests/alloc/test-claims_basic.c | 230 ++++++++++ tools/tests/alloc/test-claims_numa_redeem.c | 201 +++++++++ tools/tests/alloc/test-offlining-claims.c | 102 +++++ xen/common/page_alloc.c | 42 ++ 15 files changed, 2832 insertions(+) create mode 100644 tools/tests/alloc/.gitignore create mode 100644 tools/tests/alloc/Makefile create mode 100644 tools/tests/alloc/README.rst create mode 100644 tools/tests/alloc/check-asserts.h create mode 100644 tools/tests/alloc/harness.h create mode 100644 tools/tests/alloc/hypervisor-macros.h create mode 100644 tools/tests/alloc/libtest-page_alloc.h create mode 100644 tools/tests/alloc/mock-page_list.h create mode 100644 tools/tests/alloc/page_alloc-wrapper.h create mode 100644 tools/tests/alloc/page_alloc_shim.h create mode 100644 tools/tests/alloc/test-claims_basic.c create mode 100644 tools/tests/alloc/test-claims_numa_redeem.c create mode 100644 tools/tests/alloc/test-offlining-claims.c -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:47:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:47:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282720.1565225 (Exim 4.92) (envelope-from ) id 1wD4Kp-0001TK-Hb; Wed, 15 Apr 2026 17:47:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282720.1565225; Wed, 15 Apr 2026 17:47:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Kp-0001TD-EP; Wed, 15 Apr 2026 17:47:31 +0000 Received: by outflank-mailman (input) for mailman id 1282720; Wed, 15 Apr 2026 17:47:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Ko-0001Ns-4b for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 17:47:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wD4Kn-00DXB0-Hb for xen-devel@lists.xenproject.org; Wed, 15 Apr 2026 19:47:29 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69dfcf20-e002-0a2a0a5209dd-0a2a4506aab4-18 for ; Wed, 15 Apr 2026 19:47:29 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dfcf30-0df0-0a2a45060019-a0658309e5ce-3 for ; Wed, 15 Apr 2026 19:47:29 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 80CA481C0DDB; Wed, 15 Apr 2026 13:46:34 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH 1/4] tools/tests/alloc: Unit and Integration Test Framework for page_alloc.c Date: Wed, 15 Apr 2026 18:34:56 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776275249-5E530078-FE305C64/0/0 X-purgate-type: clean X-purgate-size: 91660 Add a test framefork for unit and integration test suites testing the Xen page allocator module xen/common/page_alloc.c in isolation. It enables test suites to verify the behaviour of the page allocator in situations that are easier to create and validate in isolation, with full control over a synthetic Xen heap state and visibility into the allocator and domain state. Signed-off-by: Bernhard Kaindl --- tools/tests/Makefile | 1 + tools/tests/alloc/.gitignore | 6 + tools/tests/alloc/Makefile | 141 ++++++++ tools/tests/alloc/README.rst | 31 ++ tools/tests/alloc/check-asserts.h | 347 ++++++++++++++++++ tools/tests/alloc/harness.h | 69 ++++ tools/tests/alloc/hypervisor-macros.h | 101 ++++++ tools/tests/alloc/libtest-page_alloc.h | 356 +++++++++++++++++++ tools/tests/alloc/mock-page_list.h | 307 ++++++++++++++++ tools/tests/alloc/page_alloc-wrapper.h | 465 +++++++++++++++++++++++++ tools/tests/alloc/page_alloc_shim.h | 433 +++++++++++++++++++++++ 11 files changed, 2257 insertions(+) create mode 100644 tools/tests/alloc/.gitignore create mode 100644 tools/tests/alloc/Makefile create mode 100644 tools/tests/alloc/README.rst create mode 100644 tools/tests/alloc/check-asserts.h create mode 100644 tools/tests/alloc/harness.h create mode 100644 tools/tests/alloc/hypervisor-macros.h create mode 100644 tools/tests/alloc/libtest-page_alloc.h create mode 100644 tools/tests/alloc/mock-page_list.h create mode 100644 tools/tests/alloc/page_alloc-wrapper.h create mode 100644 tools/tests/alloc/page_alloc_shim.h diff --git a/tools/tests/Makefile b/tools/tests/Makefile index 6477a4386dda..ca3de4c7b54a 100644 --- a/tools/tests/Makefile +++ b/tools/tests/Makefile @@ -2,6 +2,7 @@ XEN_ROOT = $(CURDIR)/../.. include $(XEN_ROOT)/tools/Rules.mk SUBDIRS-y := +SUBDIRS-y += alloc SUBDIRS-y += domid SUBDIRS-y += mem-claim SUBDIRS-y += paging-mempool diff --git a/tools/tests/alloc/.gitignore b/tools/tests/alloc/.gitignore new file mode 100644 index 000000000000..9f77c5879772 --- /dev/null +++ b/tools/tests/alloc/.gitignore @@ -0,0 +1,6 @@ +/test-claims_basic +/test-claims_numa_install +/test-claims_numa_redeem +/test-online_page +/test-offlining-claims +/test-reserve_offline_page diff --git a/tools/tests/alloc/Makefile b/tools/tests/alloc/Makefile new file mode 100644 index 000000000000..f5724aa3f699 --- /dev/null +++ b/tools/tests/alloc/Makefile @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Makefile for tools/tests/alloc + +XEN_ROOT := $(abspath $(CURDIR)/../../..) +include $(XEN_ROOT)/tools/Rules.mk +RELDIR := $(subst $(XEN_ROOT)/,,$(CURDIR)) + +TEST_SOURCES := $(notdir $(wildcard test-*.c)) +TARGETS := $(TEST_SOURCES:.c=) + +.PHONY: all +all: $(TARGETS) + +define RUN_TESTS + @echo "Build configuration:" + @echo "CC=$(CC)" + @echo "CFLAGS='$(CFLAGS)'" + @for test in $? ; do \ + echo;echo "$(RELDIR): RUN_TESTS: $$test...";echo; \ + ./$$test ; EXIT_CODE=$$? ; \ + if [ $$EXIT_CODE -ne 0 ]; then \ + echo "Test $$test failed with exit code $$EXIT_CODE"; \ + exit 1; \ + fi; \ + done + @echo + @echo "Tests executed successfully:" + @for test in $? ; do \ + echo " - $$test"; \ + done +endef + +# Run the tests if possible, otherwise print a warning and skip them. +.PHONY: run +# Determine if the tests can be run on the build host. If CC and HOSTCC +# are the same, we can run the tests directly. If they differ, we check +# if binfmt-support and qemu-binfmt are available to run the tests under +# using binfmt-misc using qemu-user-static. +ifeq ($(CC),$(HOSTCC)) + TESTS_RUNNABLE=yes +else + BINFMT_SUPP := $(if $(wildcard /etc/init.d/binfmt-support),1,0) + QEMU_BINFMT := $(if $(wildcard /usr/libexec/qemu-binfmt),1,0) + ifeq ($(BINFMT_SUPP)$(QEMU_BINFMT),11) + # Running static binaries doesn't need extra setup besides qemu-binfmt + CFLAGS += -static + TESTS_RUNNABLE=yes + else + TESTS_RUNNABLE=no + endif +endif + +run: $(TARGETS) +ifeq ($(TESTS_RUNNABLE),yes) + $(RUN_TESTS) +else + $(warning HOSTCC != CC, and qemu-binfmt not detected, skipping alloc tests) +endif + +# Run the tests binfmt-misc set up +BINFMT_SUPP := $(if $(wildcard /etc/init.d/binfmt-support),1,0) +QEMU_BINFMT := $(if $(wildcard /usr/libexec/qemu-binfmt),1,0) +.PHONY: run-tests +run-tests: $(TARGETS) +ifeq ($(CC),$(HOSTCC)) + $(RUN_TESTS) +else ifeq ($(BINFMT_SUPP)$(QEMU_BINFMT),11) + $(RUN_TESTS) +else + $(warning Note: binfmt-support or qemu-user not found, skipping run-tests) +endif + +# +# Build and run the tests for multiple architectures, +# skipping if the appropriate cross-compiler is not found. +# The default XEN_TARGET_ARCH is always built and tested as well. +# This is gcc-specific, but can be adapted for other toolchains. +# +ARCHS := arm64-aarch64-linux-gnu arm32-arm-linux-gnueabihf +ARCHS += x86_32-i686-linux-gnu x86_64-x86_64-linux-gnu +ARCHS += ppc64-powerpc64le-linux-gnu riscv64-riscv64-linux-gnu +.PHONY: run-archs +run-archs: $(TARGETS) +ifneq ($(CC),gcc) + $(warning run-archs target is only supported with CC=gcc for now, skipping) +else + @set -e;PASSES=;SKIPPED_ARCHS=; \ + MAKEFLAGS="$$MAKEFLAGS --no-print-directory"; \ + + for t in $(ARCHS); do \ + A=$${t%%-*}; C=$${t#*-}; \ + [ $$A != $(XEN_TARGET_ARCH) ] || continue; \ + if ! type "$${C}-gcc" >/dev/null 2>&1; then \ + echo " $${C}-gcc not found, skipping $${A}"; \ + SKIPPED_ARCHS="$${SKIPPED_ARCHS} $${A}"; continue; \ + fi; \ + if [ $${A} = $(XEN_TARGET_ARCH) ]; then C=$(CROSS_COMPILE); fi; \ + make XEN_TARGET_ARCH="$${A}" CROSS_COMPILE=$$C- clean run-tests; \ + PASSES="$${PASSES} $${A}"; \ + done;\ + echo "$@ successful for:$${PASSES} $(XEN_TARGET_ARCH)";\ + [ -z "$${SKIPPED_ARCHS}" ] || echo "Skipped architectures:$${SKIPPED_ARCHS}" +endif + +.PHONY: clean +.NOTPARALLEL: clean +clean: + $(RM) -- *.o $(TARGETS) $(DEPS_RM) + +.PHONY: distclean +distclean: clean + $(RM) -- *~ + +.PHONY: install +install: all + $(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests + $(INSTALL_PROG) $(TARGETS) $(DESTDIR)$(LIBEXEC)/tests + +.PHONY: uninstall +uninstall: + $(RM) -- $(patsubst %,$(DESTDIR)$(LIBEXEC)/tests/%,$(TARGETS)) + +# CFLAGS for building the tests +XEN_INCLUDE_ARCH := $(subst x86_64,x86,$(XEN_COMPILE_ARCH)) +CFLAGS += -D__XEN_TOOLS__ +CFLAGS += $(APPEND_CFLAGS) +CFLAGS += -I$(XEN_ROOT)/xen/include +CFLAGS += -I$(XEN_ROOT)/xen/arch/$(XEN_INCLUDE_ARCH)/include +CFLAGS += $(CFLAGS_xeninclude) + +# Enable sanitizers to catch memory errors and undefined behavior in the code +# for x86_64. Other architectures do not support -fstatic with it. +ifeq ($(XEN_TARGET_ARCH),x86_64) +CFLAGS += -fsanitize=address -fsanitize=undefined -fno-common +endif + +# Build rules for the tests +$(TARGETS): %: %.o $(LIB_OBJ) + $(CC) -o $@ $^ $(LDFLAGS) $(CPPFLAGS) $(CFLAGS) $(APPEND_CFLAGS) + +-include $(DEPS_INCLUDE) diff --git a/tools/tests/alloc/README.rst b/tools/tests/alloc/README.rst new file mode 100644 index 000000000000..3ed362598bb3 --- /dev/null +++ b/tools/tests/alloc/README.rst @@ -0,0 +1,31 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Unit and Integration test suite for the page allocator +====================================================== + +The tests in ``tools/tests/alloc`` contain unit tests for the +Xen page allocator in ``xen/common/page_alloc.c`` and are +built as standalone executables. + +They are not intended to be run in a Xen environment, but rather to test +the allocator logic in isolation and can be run on any compatible host +system at build time and do not use any installed libraries or require +any special setup or dependencies beyond the standard C library. + +The tests use a shim as a substitute for Xen hypervisor code that would +conflict with running the page allocator as a host executable, and they +use helper functions to initialize and assert the status of the data +structures of the allocator such as the page lists and zones. + +The tests can be run with the ``run`` target of the ``Makefile``, which +will execute all the test executables and report their results unless +you override the TARGETS variable to run a specific test: + +.. code:: shell + + make -C tools/tests/alloc clean all run \ + TARGETS=test-reserve_offline_page-uma + +To add a new test, simply create a new C file with a name starting with +``test-``, implement the test logic, and it will be automatically included +in the build and run targets by default. diff --git a/tools/tests/alloc/check-asserts.h b/tools/tests/alloc/check-asserts.h new file mode 100644 index 000000000000..04a254c0999d --- /dev/null +++ b/tools/tests/alloc/check-asserts.h @@ -0,0 +1,347 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header-only library for check assertions in unit tests. + * + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef _CHECK_ASSERTS_H_ +#define _CHECK_ASSERTS_H_ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_NUMA +#define CONFIG_NUMA 0 +#endif +#define __used __attribute__((__used__)) + +/** ## Global state for the test framework and assertions */ + +/** Set when assertions are expected to fail */ +static bool testcase_assert_expected_to_fail = false; +/** Set when verbose assertions are enabled */ +static bool testcase_assert_verbose_assertions = true; +/** + * The current function for verbose assertions, used to avoid repeating the + * function name in the logs for multiple assertions within the same function. + */ +static const char *testcase_assert_current_func = NULL; +/** The current indentation level for verbose assertions */ +static int testcase_assert_verbose_indent_level = 0; +/** Failed checks since the last call call to EXPECTED_TO_FAIL_BEGIN() */ +static int testcase_assert_expected_failures = 0; +/** Failed checks within EXPECTED_TO_FAIL_BEGIN()/END() in this test case */ +static int testcase_assert_expected_failures_total = 0; +/** Successful assertions in this test case */ +static int testcase_assert_successful_assert_total = 0; +#define assert_failed_str "Assertion failed: " + +/** ## Assertion macros and helpers */ + +/** Check a condition and log the result with context. */ +#define CHECK(condition, fmt, ...) \ + testcase_assert(condition, __FILE__, __LINE__, __func__, fmt, \ + ##__VA_ARGS__) + +/** If the condition is false, treat it as a test assertion failure */ +#define ASSERT(x) \ + testcase_assert(x, __FILE__, __LINE__, __func__, assert_failed_str #x) + +/** If the condition is true, treat it as a bug, used in Xen hypervisor code */ +#define BUG_ON(x) \ + testcase_assert(!(x), __FILE__, __LINE__, __func__, "BUG_ON: " #x) + +/** Assert that the code is unreachable */ +#define ASSERT_UNREACHABLE() assert(false) + +/** ## Helpers for expected assertion failures */ + +/** Marks the beginning of a block where assertions are expected to fail */ +#define EXPECTED_TO_FAIL_BEGIN() (testcase_assert_expected_to_fail = true) +/** Marks the end of a block where assertions are expected to fail */ +#define EXPECTED_TO_FAIL_END(c) testcase_assert_check_expected_failures(c) + +/** Checks the number of expected failures against the actual count */ +static void __used testcase_assert_check_expected_failures(int expected) +{ + if ( testcase_assert_expected_failures != expected ) + { + fprintf(stderr, "Test assertion expected %d failures, but got %d\n", + expected, testcase_assert_expected_failures); + abort(); + } + testcase_assert_expected_to_fail = false; + testcase_assert_expected_failures = 0; + testcase_assert_expected_failures_total += expected; +} + +/** ## Test case management and reporting */ + +/** Function pointer used for initializing a test case */ +static void (*testcase_init_func)(const char *, int); + +/** Set up the function pointer for initializing a test case */ +static void __used setup_testcase_init_func(void (*init_fn)(const char *, int)) +{ + testcase_init_func = init_fn; +} + +/** + * Assert a condition within a test case + * + * This function is the core of the assertion mechanism for test cases. + * It checks a given condition and handles both expected and unexpected + * assertion failures. + * + * If the assertion is expected to fail, it logs the failure and increments + * the expected failure count. If the assertion is not expected to fail but + * does, it logs the failure and aborts the test. If the assertion passes, + * it increments the successful assertion count and optionally logs the + * successful assertion if verbose assertions are enabled. + * + * Args: + * condition (bool): The condition to check. If false, the assertion fails. + * file (const char *): The file where the assertion is located, for logging. + * line (int): The source line of the assertion, for logging. + * func (const char *): The function name where the assertion is located. + * fmt (const char *): A printf format string with context for the assertion. + * ...: Additional arguments for the format string. + */ +static void testcase_assert(bool condition, const char *file, int line, + const char *func, const char *fmt, ...) +{ + va_list ap; + const char *relpath = file; + + while ( (file = strstr(relpath, "../")) ) + relpath += 3; + + va_start(ap, fmt); + if ( testcase_assert_expected_to_fail ) + { + fprintf(stderr, "\n- Test assertion %s at %s:%d:\n ", + condition ? "unexpectedly passed" : "expectedly failed", + relpath, line); + vfprintf(stderr, fmt, ap); + va_end(ap); + fprintf(stderr, "\n"); + + if ( condition ) + abort(); /* Unexpected pass, treat as test failure */ + else + testcase_assert_expected_failures++; /* update for the report */ + return; + } + if ( !condition ) + { + fprintf(stderr, "Test assertion failed at %s:%d: ", relpath, line); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + abort(); + } + testcase_assert_successful_assert_total++; + if ( testcase_assert_verbose_assertions ) + { + /* As the assertion didn't actually fail, remove the prefix */ + if ( strncmp(fmt, assert_failed_str, strlen(assert_failed_str)) == 0 ) + fmt += strlen(assert_failed_str); + + if ( strcmp(fmt, "ret == 0") == 0 ) + return; + + for ( int i = 0; i < testcase_assert_verbose_indent_level; i++ ) + printf(" "); + + printf("%s:%d: ", relpath, line); + + /* + * Skip logging the passed function if it was already logged for the + * current function, or the source or the function starts with test. + */ + if ( (testcase_assert_current_func == NULL || + strcmp(testcase_assert_current_func, func)) && + (strncmp(relpath, "test-", strlen("test-")) && + strncmp(func, "test_", strlen("test_"))) ) + printf("%s(): ", func); + + if ( strncmp(fmt, "BUG_ON:", strlen("BUG_ON:")) ) + printf("ASSERT("); + + vprintf(fmt, ap); + va_end(ap); + + if ( strncmp(fmt, "BUG_ON:", strlen("BUG_ON:")) ) + printf(")"); + + printf("\n"); + } +} + +/** Structure to represent a test case and its results for reporting */ +struct testcase { + /** Human-readable name of the test case */ + const char *name; + /** Test ID */ + const char *tid; + /** Integer argument for the test case */ + int intarg; + /** Function pointer to the test case function */ + void (*func)(int); + /** Number of assertions passed */ + int passed_asserts; + /** Number of expected failures occurred */ + int expected_failures; +} testcases[40]; +/** Pointer to the current test case being executed, for tracking results */ +struct testcase *current_testcase = testcases; + +static void print_testcase_report(struct testcase *tc) +{ + printf("- %-5s %-34s %2d: %3d assertions passed", tc->tid, tc->name, + tc->intarg, tc->passed_asserts); + if ( tc->expected_failures ) + printf(" (%2d XFAIL)", tc->expected_failures); + printf("\n"); +} + +/** + * Execute the given test function and record the number of assertions + * passed and expected failures for the test report. The test function + * is expected to use the CHECK, ASSERT, and BUG_ON macros for assertions, + * and can use EXPECTED_TO_FAIL_BEGIN and EXPECTED_TO_FAIL_END to mark + * assertions that are expected to fail for testing negative scenarios. + * + * The test function is also passed an integer argument that can be used + * to specify different scenarios or parameters for the test. + * + * The test report will include the name of the test case, the integer + * argument, the number of assertions passed, and the number of expected + * failures. The test report is printed after the test function completes, + * and a summary report is printed after all test cases have been executed. + * + * The test function can also use the verbose assertion mode to print + * additional context for each assertion, which can be helpful for debugging + * test failures and understanding the test flow. + * + * Args: + * case_func (void (*)(int)): + * The test function to execute, which takes an int argument. + * int_arg (int): An argument to pass to the test function, which can be used + * to specify different scenarios or parameters for the test. + * tid (const char *): + * A test id; string identifier for the test case. + * case_name (const char *): + * A human-readable name for the test case, used for reporting. + */ +static void run_testcase(void (*case_func)(int), int int_arg, const char *tid, + const char *case_name) +{ + printf("\nTest Case: %s...\n", case_name); + current_testcase->name = case_name; + current_testcase->func = case_func; + current_testcase->intarg = int_arg; + current_testcase->tid = tid; + current_testcase->passed_asserts = 0; + current_testcase->expected_failures = 0; + + /* + * Call the testcase initialization function if it is set, which can be + * used to reset global state or set up specific scenarios for the test. + * + * For example, the page allocator tests use this to reset the state of the + * synthetic page structures and the heap before each test case. + */ + if ( testcase_init_func && int_arg >= 0 ) + testcase_init_func(case_name, int_arg); + + case_func(int_arg); + + current_testcase->passed_asserts = testcase_assert_successful_assert_total; + current_testcase->expected_failures = + testcase_assert_expected_failures_total; + + testcase_assert_successful_assert_total = 0; + testcase_assert_expected_failures_total = 0; + + printf("\nResults:\n"); + print_testcase_report(current_testcase); + current_testcase++; +} +#define RUN_TESTCASE(tid, func, arg) run_testcase(func, arg, #tid, #func) + +/** + * Provide a report of all test cases executed and their results, + * including the total number of assertions passed and expected failures. + */ +static int testcase_print_summary(const char *argv0) +{ + struct utsname uts; + int total_asserts = 0, expected_failures = 0; + + fprintf(stderr, "\nTest Report:\n"); + + current_testcase = testcases; + for ( size_t i = 0; i < ARRAY_SIZE(testcases) && current_testcase->func; + i++ ) + { + print_testcase_report(current_testcase); + total_asserts += current_testcase->passed_asserts; + expected_failures += current_testcase->expected_failures; + current_testcase++; + } + current_testcase->tid = "Total"; + current_testcase->name = ""; + current_testcase->passed_asserts = total_asserts; + current_testcase->expected_failures = expected_failures; + current_testcase->intarg = current_testcase - testcases; + print_testcase_report(current_testcase); + + uname(&uts); + printf("\nTest suite %s for %s completed.\n", argv0, uts.machine); + return 0; +} + +static const char *parse_args(int argc, char *argv[], const char *topic) +{ + const char *program_name = argv[0]; + struct utsname uts; + + if ( argc != 1 ) + { + fprintf(stderr, "Usage: %s\n", argv[0]); + return NULL; + } + program_name = strrchr(program_name, '/'); + if ( program_name ) + program_name++; + else + program_name = argv[0]; + + uname(&uts); + printf("Suite : %s\n", program_name); + printf("Topic : %s\n", topic); + printf("Config: CONFIG_NUMA %s\n", + config_enabled(CONFIG_NUMA) ? "enabled" : "disabled"); +#ifndef __clang__ + printf("Target: gcc %s/%s\n", __VERSION__, uts.machine); +#else + printf("Target: %s/%s\n", __VERSION__, uts.machine); +#endif + return program_name; +} + +#endif /* _CHECK_ASSERTS_H_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/alloc/harness.h b/tools/tests/alloc/harness.h new file mode 100644 index 000000000000..946c796c5475 --- /dev/null +++ b/tools/tests/alloc/harness.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common test harness for page allocation unit tests. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#ifndef _TEST_HARNESS_ +#define _TEST_HARNESS_ + +#include +#include +#include +#include +#include + +/* Enable debug mode to enable additional checks */ +#define CONFIG_DEBUG + +/* Define common macros which are compatible with the test context */ +#include "hypervisor-macros.h" + +/* Provide the common check_asserts library for test assertions */ +#include "check-asserts.h" + +/* Common Xen types for the test context */ +typedef uint8_t u8; +typedef uint64_t paddr_t; +typedef unsigned long cpumask_t; +typedef long long s_time_t; +typedef bool spinlock_t; + +/* + * The original implementation of reserve_offlined_page() causes the GCC + * and clang AddressSanitizer (ASAN) to report stack-buffer-overflow + * when the test_merge_tail_pair test case is run with ASAN enabled, + * when test verifies the state of the free lists in the heap. + * + * It finds several list pointer errors in the heap state and one of the + * appears to trigger ASAN's stack-buffer-overflow detection on x86_64. + * + * To temporarily work around this issue, we detect if ASAN is enabled + * and in order to be able skip the ASSERT_LIST_EQUAL verification step + * in the test case that triggers the ASAN error, while still allowing + * the rest of the test case to run and verify all execution with ASAN. + */ +/* clang-format off */ +#if defined(__has_feature) +/* Clang uses __has_feature to detect AddressSanitizer */ +# if __has_feature(address_sanitizer) +# define ASAN_ENABLED 1 +# endif +/* GCC uses __SANITIZE_ADDRESS__ to detect AddressSanitizer */ +#elif defined(__SANITIZE_ADDRESS__) +# define ASAN_ENABLED 1 +#else +# define ASAN_ENABLED 0 +#endif +/* clang-format on */ +#endif /* _TEST_HARNESS_H_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/alloc/hypervisor-macros.h b/tools/tests/alloc/hypervisor-macros.h new file mode 100644 index 000000000000..0d35bd9a806c --- /dev/null +++ b/tools/tests/alloc/hypervisor-macros.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common macros and definitions for building host-side unit tests + * the Xen hypervisor. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#ifndef _TEST_ALLOC_XEN_MACROS_ +#define _TEST_ALLOC_XEN_MACROS_ + +/* + * In Xen, STATIC_IF(x) and config_enabled(x) are defined in kconfig.h + * which we cannot include, so we need to define the necessary macros. + */ +#define STATIC_IF(option) static_if(option) +#define static_if(value) _static_if(__ARG_PLACEHOLDER_##value) +#define _static_if(arg1_or_junk) ___config_enabled(arg1_or_junk static, ) +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) + +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0) + +#define ___config_enabled(__ignored, val, ...) val + +/* + * We include common-macros.h to reuse the Xen-tools macros, which are + * not necessarily the same as the Xen hypervisor macros, but are close + * enough for the test context. + */ +#include + +/* + * Define the header guards of the Xen headers that the Xen hypervisor + * variants of the definitions in common-macros.h and bitops.h to prevent + * conflicting definitions from those headers that prevent clean compilation. + */ +#define __XEN_CONST_H__ +#define __MACROS_H__ + +/* + * We also define the Xen hypervisor macros that are used by page_alloc.c + * but not defined by common-macros.h, but needed to build hypervisor code + * in the test context, such as IS_ALIGNED() and the ffsl/flsl macros. + */ +#define IS_ALIGNED(x, a) (!((x) & ((a) - 1))) + +/* + * Inclde the Xen-tools bitops.h to reuse the bitops from the tools side. + * They are not necessarily the same as the Xen hypervisor bitops, but are + * close enough for the test context. + */ +#include +/* + * Afer including the Xen-tools bitops.h, we need to redefine the ffsl and flsl + * macros to match the behavior of the Xen hypervisor's ffsl and flsl, which + * return unsigned int and are relevant for signed/unsigned conversion checking + * and type hints in the test context. + * And we need to undefine conflicting macros defined by xen-tools headers. + */ +#undef BITS_PER_LONG +#undef __LITTLE_ENDIAN +#undef __BIG_ENDIAN +/* Xen ffsl returns 1-based position of lowest set bit as unsigned int */ +#undef ffsl /* tools/include/xen-tools/bitops.h returns signed int */ +#define ffsl(x) ((unsigned int)__builtin_ffsl(x)) +/* Xen flsl returns 1-based position of highest set bit as unsigned int */ +#define flsl(x) ((unsigned int)((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0)) + +/* Common assertion and logging macros */ +#define BUG() assert(false) +#define domain_crash(d) ((void)(d)) +#define PRI_mfn "lu" +#define PRI_stime "lld" +#define printk printf +#define dprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define gdprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define gprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define panic(fmt, ...) \ + do \ + { \ + fprintf(stderr, fmt, ##__VA_ARGS__); \ + abort(); \ + } while ( 0 ) + +/* Support including xen/sections.h and other function attributes */ +#define __initdata +#define __init __used +#define __initcall(f) static int __used (*f##_ptr)(void) = (f) + +#endif /* _TEST_ALLOC_XEN_MACROS_ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/alloc/libtest-page_alloc.h b/tools/tests/alloc/libtest-page_alloc.h new file mode 100644 index 000000000000..5654152cd48a --- /dev/null +++ b/tools/tests/alloc/libtest-page_alloc.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Test framework for testing the memory-allocation functionality + * of xen/common/page_alloc.c, consisting of: + * + * 1. A header-only shim for page_alloc.c to provide the necessary + * definitions and helpers to allow the test framework to include + * the real page_alloc.c directly into its translation unit. + * + * 2. A set of mocks for the Xen types and functions used by page_alloc.c, + * sufficient to support the test scenarios in tools/tests/alloc. + * + * This includes mocks for NUMA topology, designed to allow the test + * scenarios to manipulate the state of the allocator and verify its + * behavior in a way that is consistent with how page_alloc.c acts when + * used by the running Xen hypervisor, while being self-contained and + * suitable for unit and integration testing. + * + * 3. A tiny wrapper which includes the real page_alloc.c for testing. + * + * It disables a few of the -Wextra warnings enabled by the test + * framework that are not yet fixed in page_alloc.c, such as some + * sign-compare warnings and unused parameter warnings in its code. + * + * 4. A library for NUMA heap initialisation, and asserting the heap status. + * + * This library provides functions to prepare the state of the memory + * allocator for the test scenarios, such as: + * + * a. Initializing the heap before each test case, creating NUMA nodes, + * and adding pages to the heap in specific states, such as free, + * allocated, marked to be offlined or already offlined. + * + * b. Verifying the state of the heap and the page_info structures after + * test actions, such as checking that pages are allocated or freed + * as expected, that the state of the page_info structures is consistent + * with the expected state. + * + * 5. Test case lifecycle management, such as initializing the test context + * before each test case, printing the outcome of each test case, + * tracking the number of assertions, logging assertions with file + * and line information, and printing a summary report at the end. + * + * 6. A Makefile for discovering, compiling, running the test cases, + * and reporting results which test cases were run. + * + * The Makefile is designed to allow running individual test cases + * or the entire test suite for all supported CPU architectures, if + * so desired. + * + * It is also responsible for compiling the tests with address sanitizer + * (ASAN) enabled to catch memory errors in the page allocator code + * and the test code, especially when manipulating the state of the + * page_info structures inside the test scenarios. + * + * Copyright (C) 2026 Cloud Software Group + */ +#include +#include +#include + +/* Enable -Wextra warnings as errors to catch e.g. sign-compare issues */ +#pragma GCC diagnostic error "-Wextra" + +/* Support for printing the status of pages for debugging */ +struct page_info; +static void print_page_info(struct page_info *pos); +static void print_page_count_info(unsigned long count_info); + +#define TEST_USES_PAGE_ALLOC_SHIM +#include "page_alloc_shim.h" + +/* Include the real page_alloc.c for testing */ + +#include "page_alloc-wrapper.h" + +static const unsigned int node = 0; +static const unsigned int node0 = 0; +static const unsigned int node1 = 1; +static const unsigned int order0 = 0; +static const unsigned int order1 = 1; +static const unsigned int order2 = 2; +static const unsigned int order3 = 3; + +/** + * Functions for setting up test scenarios with a clean allocator state, + * and for building synthetic buddy trees with the expected page_info state. + */ + +/* Set up a bare minimum NUMA node topology. */ +static void init_numa_node_data(unsigned int start_mfn) +{ + (void)start_mfn; +#ifdef CONFIG_NUMA + /* + * For simplicity, we assign each CPU to its own node, and set each + * node's cpumask to contain just that CPU. + * + * If needed, we could easily modify this setup to have multiple CPUs + * per node by adjusting the cpu_to_node assignments and node_to_cpumask + * values accordingly. + * + * The test scenarios in this suite do not currently require multiple + * CPUs per node, but we could extend them to do so if desired. + * + * This is just a default setup that the test scenarios can rely on, + * and they are free to modify the cpu_to_node and node_to_cpumask + * values as needed for their specific test cases. + */ + for ( unsigned int i = 0; i < NR_CPUS; i++ ) + cpu_to_node[i] = i; + + /* Each node has a single CPU in its cpumask for simplicity */ + for ( unsigned int i = 0; i < MAX_NUMNODES; i++ ) + node_to_cpumask[i] = (1UL << i); + + /* Initialize node data structures */ + for ( unsigned int i = 0; i < MAX_NUMNODES; i++ ) + { + /* Each node has 8 pages for testing for now */ + node_data[i].node_start_pfn = start_mfn + (i * 8); + node_data[i].node_present_pages = 8UL; + node_data[i].node_spanned_pages = 8UL; + } + + /* + * Set up memnodemap so that mfn_to_nid() correctly resolves MFN + * ranges to NUMA nodes: with memnode_shift=3 each memnodemap entry + * covers 8 MFNs (2^3), matching the 8-page-per-node layout above. + * Entry i maps MFNs [i*8 .. (i+1)*8 - 1] to node i. + */ + memnode_shift = 3; + for ( unsigned int i = 0; i < 64; i++ ) + memnodemap[i] = (nodeid_t)i; +#endif /* CONFIG_NUMA */ +} + +static void init_dummy_domains(void); +/** + * Reset all page_alloc translation-unit globals that these tests observe. + * + * The test program includes xen/common/page_alloc.c directly, so its + * file-scope variables become global variables of this translation unit. + * + * Each test must start from a clean page allocator state, with a clean heap, + * clean availability counters, and empty offlined and broken lists. + */ +static void reset_page_alloc_state(const char *caller_func, int start_mfn) +{ + unsigned int zone; + unsigned int order; + + printf("\n%s: start_mfn = %u\n", caller_func, start_mfn); + + /* Clear the test page table used for synthetic page_info objects. */ + memset(frame_table, 0, sizeof(frame_table)); + + /* Clear the backing storage used by the imported allocator globals. */ + memset(test_heap_storage, 0, sizeof(test_heap_storage)); + memset(test_avail_storage, 0, sizeof(test_avail_storage)); + + /* Clear the shim-owned singleton objects used by helper macros. */ + memset(&test_dummy_domain1, 0, sizeof(test_dummy_domain1)); + memset(&test_dummy_domain2, 0, sizeof(test_dummy_domain2)); + memset(&test_current_vcpu, 0, sizeof(test_current_vcpu)); + + /* Reinitialise the global page lists manipulated by the allocator. */ + INIT_PAGE_LIST_HEAD(&page_offlined_list); + INIT_PAGE_LIST_HEAD(&page_broken_list); + INIT_PAGE_LIST_HEAD(&test_page_list); + + init_numa_node_data(start_mfn); /* Only used for NUMA-enabled builds */ + + /* Reinitialise every per-zone, per-order free-list bucket. */ + for ( nodeid_t node = 0; node < MAX_NUMNODES; node++ ) + { + _heap[node] = &test_heap_storage[node]; + avail[node] = test_avail_storage[node]; + node_avail_pages[node] = 0; + for ( zone = 0; zone < NR_ZONES; zone++ ) + for ( order = 0; order <= MAX_ORDER; order++ ) + INIT_PAGE_LIST_HEAD(&heap(node, zone, order)); + } + + total_avail_pages = 0; + outstanding_claims = 0; + /* + * The valid MFN range for the test context is configured to cover only + * the test frame table, so that any attempts by page_alloc.c to prevent + * functions in page_alloc.c is only manipulating the intended test + * state and not accessing uninitialized memory or going out of bounds. + * + * Set up the initial range of valid pages for mfn_valid() used by + * free_heap_pages() as condition if there are successors/predecessors + * to merge pages with. Unless successors/predecessors are initialized + * to be free, it should forgoe merging and just add the provided page + * as-is to the heap, but to prevent it looking up uninitialised memory, + * we set the valid MFN range to cover the frame_table only. + */ + first_valid_mfn = start_mfn; + max_page = sizeof(frame_table) / sizeof(frame_table[0]); + assert(first_valid_mfn < max_page); + + init_dummy_domains(); +} + +static void init_dummy_domains(void) +{ + nodemask_t dom_node_affinity; + struct domain *dom; + int dom_id = 1; /* Start domain IDs from 1 for clarity in logs */ + + /* Provide a current vcpu/domain pair for code paths that inspect it. */ + test_current_vcpu.domain = &test_dummy_domain1; + + /* Provide the dummy domains for tests that need some domains */ + domain_list = &test_dummy_domain1; + test_dummy_domain1.next_in_list = &test_dummy_domain2; + + nodes_clear(dom_node_affinity); + node_set(node0, dom_node_affinity); + node_set(node1, dom_node_affinity); + + for_each_domain ( dom ) + { + dom->node_affinity = dom_node_affinity; + dom->max_pages = MAX_PAGES; + dom->domain_id = dom_id++; + } +} + +/* Initialize the page allocator tests */ +static void __used init_page_alloc_tests(void) +{ + /* Define the function above as the testcase initialization function */ + setup_testcase_init_func(reset_page_alloc_state); +} + +/** + * Populate a page descriptor with the minimal state needed by + * reserve_offlined_page(). + * + * Tests build synthetic buddy trees by placing a small set of + * page_info objects into allocator free lists. This helper + * keeps that setup consistent across scenarios. + * + * Args: + * page (struct page_info *): Pointer to the page_info to be initialised. + * order (unsigned int): The order to set in the page_info's order field + * state (unsigned long): The state bits to set in the page's count_info + * field, e.g. PGC_state_inuse for pages to be + * added to the heap, or PGC_state_offlined for + * pages to be added to the offlined list. + */ +static void init_test_page(struct page_info *page, unsigned int order, + unsigned long state) +{ + mfn_t mfn = page_to_mfn(page); + + if ( mfn < first_valid_mfn && mfn > 0 && mfn < max_page ) + first_valid_mfn = mfn; + + if ( mfn >= max_page && mfn < ARRAY_SIZE(frame_table) ) + max_page = mfn + 1; + + CHECK(mfn_valid(mfn), "mfn %lu valid: %lu-%lu", mfn, first_valid_mfn, + max_page); + + memset(page, 0, sizeof(*page)); + + /* Model the page as a free buddy head of the requested order. */ + page->v.free.order = order; + + /* Default to no tracked dirty subrange and no active scrubbing. */ + page->u.free.first_dirty = INVALID_DIRTY_IDX; + page->u.free.scrub_state = BUDDY_NOT_SCRUBBING; + + /* Install the requested allocator state bits for this synthetic page. */ + page->count_info = state; +} + +/** + * Initialize the given pages as a buddy of the requested order, + * with the first page as the buddy head and the rest as subpages + * of it, and add the intialised buddy to the heap. + * + * This helper is intended to be used by test scenarios to set up + * the heap with buddies of the expected order and state for testing + * operations that manipulate the heap, such as reserve_offlined_page() + * and free_heap_pages(), and to ensure that the heap state is consistent + * with the page_info state after those operations. + * + * The buddy is added to the heap using free_heap_pages() which + * models the expected usage of the heap and ensures that the + * heap structures are updated correctly according to the logic + * of the allocator, which may change over time. + * + * For example, if the logic for merging buddies or tracking claims changes, + * using free_heap_pages() ensures that the test setup will be correct even + * after such changes, and that the test scenarios will be testing the real + * behaviour of the allocator rather than an idealised version of it. + * + * Args: + * pages (struct page_info *): Pointer to the first page_info in an array. + * order (unsigned int): The order of the buddy to be created. + * caller (const char *): The name of the calling function for context. + * Returns: + * The zone of the added buddy, which can be useful for test scenarios that + * need to know the zone of the buddy for further operations or assertions. + */ +static zone_t __used page_list_add_buddy(struct page_info *pages, + unsigned int order, const char *caller) +{ + size_t i, num_pages = 1U << order; + bool verbose_asserts_save = testcase_assert_verbose_assertions; + + /* Avoid logging spinlocks and verbose assertions during initialization */ + testcase_assert_verbose_assertions = false; + + /* + * Initialize the first page as the head of the buddy with the given order. + * All pages are initialized as in-use as this is the API expected by + * free_heap_pages() when it adds a buddy to the heap(). This model is + * consistent with the way the boot allocator and online_page() handle + * page initialization as well as the normal way for used pages to be freed. + */ + init_test_page(&pages[0], order, PGC_state_inuse); + + /* Add the subpages of the buddy as order-0 buddies to the heap */ + for ( i = 1; i < num_pages; i++ ) + init_test_page(&pages[i], order0, PGC_state_inuse); + + /* + * Add the created buddy to the heap. This uses the same code path as + * freeing used pages and is consistent with the way the boot allocator + * and online_page() handle page initialization. Using free_heap_pages() + * has the additional benefit of ensuring that the heap structures are + * consistent even if the internal logic of the heap management changes. + * + * For example, implementing NUMA claims adds new per-node claims counters + * and logic to free_heap_pages(), so using it here ensures that the test + * setup will be correct even after such changes. + */ + printf("%s: Adding buddy of order %u at MFN %lu to the heap.\n", caller, + order, page_to_mfn(&pages[0])); + + testcase_assert_verbose_assertions = false; + + free_heap_pages(&pages[0], order, false); + + testcase_assert_verbose_assertions = verbose_asserts_save; + return page_to_zone(&pages[0]); +} + +#define test_page_list_add_buddy(pages, order) \ + page_list_add_buddy(pages, order, __func__) diff --git a/tools/tests/alloc/mock-page_list.h b/tools/tests/alloc/mock-page_list.h new file mode 100644 index 000000000000..92a0f7c53042 --- /dev/null +++ b/tools/tests/alloc/mock-page_list.h @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mock page list implementation for testing page allocator functions. + * + * This mock implementation provides a simplified version of the page list + * structures and functions used by the page allocator, allowing unit tests + * to be written without relying on the full Xen environment. + * + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef _MOCK_PAGE_LIST_H_ +#define _MOCK_PAGE_LIST_H_ + +#include +#include +#include + +#include "harness.h" /* Provides the generic Xen defintitions needed */ + +/* + * Wrapper around xen/config.h for common Xen definitions for the test context + */ +#define __XEN_KCONFIG_H +#undef __nonnull +#undef offsetof +#include +/* Xen code adds cf_check as an attribute macro to functions we don't call */ +#undef cf_check +#define cf_check __used + +#define MAX_ORDER 20 + +/* + * The page_info structures in the frame table are manipulated directly + * by page_alloc.c, so they must be defined in a way that is consistent + * with how page_alloc.c uses them, while being self-contained and suitable + * for unit testing. + * + * The test scenarios can then manipulate the state of these page_info + * structures to set up test conditions and verify the behavior of the + * allocator in a way that is consistent with how it acts when used by + * the running hypervisor. + */ +struct page_info { + unsigned long count_info; /* PGC_state_inuse and other flags/counters */ + union { + /* When the page is in use, u.inuse.type_info is used for status */ + struct { + unsigned long type_info; + } inuse; + /* + * When the page is free, u.free is used for buddy management. + * + * Using BUILD_BUG_ON(sizeof(var->u) != sizeof(long)), page_alloc + * enforces that the u.free struct is exactly the size of a long. + * 32-bit architectures need to use bitfields to fit the fields + * in a long, while 64-bit architectures can use normal fields. + */ + union { + struct { + unsigned int first_dirty : MAX_ORDER + 1; +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + bool need_tlbflush : 1; + unsigned long scrub_state : 2; +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + }; + unsigned long val; + } free; + } u; + union { + struct { + unsigned int order; +#define PFN_ORDER(pg) ((pg)->v.free.order) + } free; + unsigned long type_info; + } v; + uint32_t tlbflush_timestamp; + struct domain *owner; + struct page_info *list_next; + struct page_info *list_prev; +}; + +struct page_list_head { + struct page_info *head; + struct page_info *tail; + unsigned int count; +}; +#define PAGE_LIST_HEAD(name) struct page_list_head name = {NULL, NULL, 0} + +static inline void test_page_list_init(struct page_list_head *list) +{ + list->head = NULL; + list->tail = NULL; + list->count = 0; +} +#define INIT_PAGE_LIST_HEAD(l) test_page_list_init(l) + +/* Used by page_alloc.c */ +#define page_list_for_each_safe(pos, tmp, list) \ + for ( (pos) = page_list_first(list), \ + (tmp) = (pos) ? (pos)->list_next : NULL; \ + (pos) != NULL; \ + (pos) = (tmp), (tmp) = (pos) ? (pos)->list_next : NULL ) + +typedef unsigned long mfn_t; +static struct page_list_head test_page_list; + +#define page_to_list(d, pg) (&test_page_list) +#define page_list_add(pg, list) test_page_list_add((pg), (list)) +#define page_list_add_tail(pg, list) test_page_list_add_tail((pg), (list)) +#define page_list_del(pg, list) test_page_list_del((pg), (list)) +#define page_list_empty(list) ((list)->head == NULL) +#define page_list_first(list) ((list)->head) +#define page_list_last(list) ((list)->tail) +#define page_list_remove_head(list) test_page_list_remove_head((list)) + +static inline void test_page_list_add_common(struct page_info *pg, + struct page_list_head *list, + bool at_tail) +{ + pg->list_next = NULL; + pg->list_prev = NULL; + + if ( list->head == NULL ) + { + list->head = pg; + list->tail = pg; + } + else if ( at_tail ) + { + pg->list_prev = list->tail; + list->tail->list_next = pg; + list->tail = pg; + } + else + { + pg->list_next = list->head; + list->head->list_prev = pg; + list->head = pg; + } + + list->count++; +} + +#define test_page_list_add(pg, list) test_page_list_add_common(pg, list, false) +#define test_page_list_add_tail(pg, list) \ + test_page_list_add_common(pg, list, true) + +static inline void test_page_list_del(struct page_info *pg, + struct page_list_head *list) +{ + if ( pg->list_prev ) + pg->list_prev->list_next = pg->list_next; + else + list->head = pg->list_next; + + if ( pg->list_next ) + pg->list_next->list_prev = pg->list_prev; + else + list->tail = pg->list_prev; + + pg->list_next = NULL; + pg->list_prev = NULL; + + ASSERT(list->count > 0); + list->count--; +} + +static inline struct page_info * +test_page_list_remove_head(struct page_list_head *list) +{ + struct page_info *pg = list->head; + + if ( pg ) + test_page_list_del(pg, list); + + return pg; +} + +/* + * The frame table is the foundation for the buddy allocator algorithm + * implemented by page_alloc.c, and the test scenarios manipulate the + * state of the page_info structures in the frame table to set up test + * conditions and verify the behavior of the allocator. + * + * The frame table is indexed by MFN as required by the buddy allocator + * algorithm in page_alloc.c, so the translation functions between page_info + * pointers and MFNs are defined to allow page_alloc.c to manipulate the + * page_info structures in the test frame table using MFN-based translations. + */ +extern struct page_info frame_table[]; +#define page_to_mfn(pg) ((mfn_t)((pg) - &frame_table[0])) +#define mfn_to_page(mfn) (&frame_table[(mfn)]) +#define mfn_valid(mfn) (mfn >= first_valid_mfn && mfn < max_page) +#define maddr_to_page(pa) (CHECK(false, "Not implemented")) + +/* + * Helper functions to print the state of the heap and offlined pages + * for reference while asserting consistency of the heap and offlined + * page state. + * + * These functions are called at various points in the test scenarios + * to validate that the internal state of the allocator is consistent + * with expectations. + */ + +/* Architecture-specific page state defines */ +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x##UL << PG_shift(idx)) +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) +#define PGC_allocated PG_mask(1, 1) +#define PGC_xen_heap PG_mask(1, 2) +#define _PGC_need_scrub PG_shift(4) +#define PGC_need_scrub PG_mask(1, 4) +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info & PGC_state) == PGC_state_##st) +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +struct PGC_flag_names { + unsigned long flag; + const char *name; +} PGC_flag_names[] = { + {.flag = PGC_need_scrub, "PGC_need_scrub"}, + {.flag = PGC_extra, "PGC_extra" }, + {.flag = PGC_broken, "PGC_broken" }, + {.flag = PGC_xen_heap, "PGC_xen_heap" }, +}; + +static const char *pgc_state_name(unsigned long count_info) +{ + switch ( count_info & PGC_state ) + { + case PGC_state_inuse: + return "PGC_state_inuse"; + case PGC_state_offlining: + return "PGC_state_offlining"; + case PGC_state_offlined: + return "PGC_state_offlined"; + case PGC_state_free: + return "PGC_state_free"; + default: + assert("Invalid page state" && false); + } +} + +/* Print the count_info flags of a page_info for reference */ +static void print_page_count_info(unsigned long count_info) +{ + printf(" flags: %s", pgc_state_name(count_info)); + for ( size_t i = 0; i < ARRAY_SIZE(PGC_flag_names); i++ ) + if ( count_info & PGC_flag_names[i].flag ) + printf(" %s", PGC_flag_names[i].name); + puts(""); +} + +/* Print the state of a single page for reference */ +static void print_page_info(struct page_info *pos) +{ + printf(" mfn %lu: order %u, first_dirty %x\n", page_to_mfn(pos), + PFN_ORDER(pos), pos->u.free.first_dirty); + print_page_count_info(pos->count_info); +} + +/* Print and assert the state of an offlined page.*/ +static void print_and_assert_offlined_page(struct page_info *pos) +{ + print_page_info(pos); + /* + * The order of offlined pages must always be 0 because pages are only + * offlined as standalone pages. Higher-order pages on the offline lists + * are not supported by reserve_offlined_page() and online_page(). + */ + CHECK(PFN_ORDER(pos) == 0, "All offlined pages must have order 0"); + + /* + * Check the first_dirty index of offlined pages: Current code does + * not use first_dirty for offlined pages as it only points to the + * first dirty subpage within a buddy on the heap, and offlined pages + * are not on the heap. As it is not used, current code sets it to + * INVALID_DIRTY_IDX when offlining a page, so just confirm that. + * + * PS: Their scrubbing state is tracked by count_info & PG_need_scrub. + * In case an offlined page is onlined, the onlining code will be + * responsible to set first_dirty based on the scrubbing state. + */ + if ( pos->u.free.first_dirty != INVALID_DIRTY_IDX ) + { + printf("WARNING: offlined page at MFN %lu has first_dirty %x but " + "expected INVALID_DIRTY_IDX\n", + page_to_mfn(pos), pos->u.free.first_dirty); + ASSERT(pos->u.free.first_dirty == INVALID_DIRTY_IDX); + } +} + +#endif /* _MOCK_PAGE_LIST_H_ */ \ No newline at end of file diff --git a/tools/tests/alloc/page_alloc-wrapper.h b/tools/tests/alloc/page_alloc-wrapper.h new file mode 100644 index 000000000000..ce1889e3aa37 --- /dev/null +++ b/tools/tests/alloc/page_alloc-wrapper.h @@ -0,0 +1,465 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Test framework for testing Xen's memory-allocation functionality. + * + * This file wraps xen/common/page_alloc.c for the test framework. + * + * Context: + * + * The test framework includes the real page_alloc.c directly into its + * translation unit, along with mocks for the Xen types and functions + * used by page_alloc.c, and a library for NUMA heap initialisation + * and asserting the heap status. + * + * This file serves as the wrapper around page_alloc.c, providing the + * necessary definitions and helpers to allow the test framework to + * include the real page_alloc.c directly into its translation unit. + * + * It also provides wrapper functions for key page_alloc.c functions like + * mark_page_offline() and offline_page() to allow the test scenarios to + * log the actions being taken and the outcomes observed when these functions + * are called, which is important for understanding the behavior of the + * allocator during the test scenarios and for debugging any issues that arise. + * + * Copyright (C) 2026 Cloud Software Group + */ +#include +#include + +#define TEST_USES_PAGE_ALLOC_SHIM +#include "page_alloc_shim.h" + +/* Include the real page_alloc.c for testing */ + +#pragma GCC diagnostic push +/* TODO: We should fix the remaining sign-compare warnings in page_alloc.c */ +#pragma GCC diagnostic ignored "-Wsign-compare" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#include "../../xen/common/page_alloc.c" +#pragma GCC diagnostic pop + +/* Allows the logging spinlock/unlock mocks to identify the heap lock */ +static spinlock_t *heap_lock_ptr = &heap_lock; + +/* + * Global state for the test page allocator shim and helpers. + * + * This includes the heap storage and availability counters that the test + * scenarios manipulate, as well as the domain list and a bug counter for + * the test program to track any unexpected conditions encountered in the + * test helpers. + */ +#ifndef PAGES_PER_ZONE +#define PAGES_PER_ZONE 8 +#endif + +#ifndef MAX_PAGES +#define MAX_PAGES (MAX_NUMNODES * NR_ZONES * PAGES_PER_ZONE) +#endif + +/* + * The test frame table serves as the backing storage for the page_info + * structures used in the test scenarios, and the page_info structures + * are indexed by MFN for easy translation between page_info pointers and + * MFNs in the test helpers and assertions. + * + * The frame table is the foundation for the buddy allocator algorithm + * implemented by page_alloc.c, and the test scenarios manipulate the + * state of the page_info structures in the frame table to set up test + * conditions and verify the behavior of the allocator. + */ +struct page_info frame_table[MAX_PAGES]; + +/* Provide a test pages pointer for the test scenarios */ +static struct page_info *test_pages = frame_table; + +/* + * Global state for the test page allocator shim and helpers. + * + * This includes the heap storage and availability counters that the test + * scenarios manipulate, as well as the domain list and a bug counter for + * the test program to track any unexpected conditions encountered in the + * test helpers. + */ +static heap_by_zone_and_order_t test_heap_storage[MAX_NUMNODES]; +static unsigned long test_avail_storage[MAX_NUMNODES][NR_ZONES]; +struct domain *domain_list; +typedef size_t zone_t; + +static int __used test_domain_install_claim_set(struct domain *d, + unsigned int nr_claims, + memory_claim_t *claim_set) +{ + bool save_verbose_asserts = testcase_assert_verbose_assertions; + char target_str[16]; + + /* Avoid logging verbose logging while marking a page offline */ + testcase_assert_verbose_assertions = false; + + printf("%s => Installing claim set for domain %u:\n", __func__, + d->domain_id); + for ( unsigned int i = 0; i < nr_claims; i++ ) + { + switch ( claim_set[i].target ) + { + case XEN_DOMCTL_CLAIM_MEMORY_GLOBAL: + snprintf(target_str, sizeof(target_str), "GLOBAL"); + break; + case XEN_DOMCTL_CLAIM_MEMORY_LEGACY: + snprintf(target_str, sizeof(target_str), "LEGACY"); + break; + default: + snprintf(target_str, sizeof(target_str), "NODE %u", + claim_set[i].target); + break; + } + printf(" Claim %u: pages=%lu, target=%s\n", i, claim_set[i].pages, + target_str); + } + + int ret = domain_install_claim_set(d, nr_claims, claim_set); + printf("%s <= domain_install_claim_set() returned %d\n", __func__, ret); + testcase_assert_verbose_assertions = save_verbose_asserts; + return ret; +} +#define domain_install_claim_set(d, nr_claims, claim_set) \ + test_domain_install_claim_set(d, nr_claims, claim_set) + +static unsigned long __used test_mark_page_offline(struct page_info *page, + int flag, + const char *caller_func) +{ + bool save_verbose_asserts = testcase_assert_verbose_assertions; + + /* Avoid logging verbose logging while marking a page offline */ + testcase_assert_verbose_assertions = false; + + printf("%s => Marking page at MFN %lu as %s.\n", caller_func, + page_to_mfn(page), flag ? "broken" : "offlined"); + + mark_page_offline(page, flag); + + testcase_assert_verbose_assertions = save_verbose_asserts; + return 0; +} +#define mark_page_offline(pg, flag) test_mark_page_offline(pg, flag, __func__) + +static const char *offline_state_name(uint32_t offline_status) +{ + switch ( offline_status ) + { + case PG_OFFLINE_FAILED: + return "PG_OFFLINE_FAILED"; + case PG_OFFLINE_PENDING: + return "PG_OFFLINE_PENDING"; + case PG_OFFLINE_OFFLINED: + return "PG_OFFLINE_OFFLINED"; + case PG_OFFLINE_AGAIN: + return "PG_OFFLINE_AGAIN"; + default: + return "PG_OFFLINE_UNKNOWN_STATUS"; + } +} + +static int __used test_offline_page(mfn_t mfn, int broken, uint32_t *status) +{ + bool save_verbose_asserts = testcase_assert_verbose_assertions; + + testcase_assert_verbose_assertions = false; + printf("%s => Offlining page at MFN %lu with broken=%d\n", __func__, mfn, + broken); + + int ret = offline_page(mfn, broken, status); + + printf("%s <= offline_page() returned %d, status=0x%x (%s)\n", __func__, + ret, *status, offline_state_name(*status)); + testcase_assert_verbose_assertions = save_verbose_asserts; + return 0; +} +#define offline_page(mfn, broken, status) test_offline_page(mfn, broken, status) + +static int __used test_set_outstanding_pages(struct domain *dom, + unsigned long pages, + const char *caller_func) +{ + bool save_verbose_asserts = testcase_assert_verbose_assertions; + + /* Avoid logging verbose logging while setting outstanding claims */ + testcase_assert_verbose_assertions = false; + printf("%s => domain_set_outstanding_pages(dom=%u, pages=%lu)\n", + caller_func, dom->domain_id, pages); + + int ret = domain_set_outstanding_pages(dom, pages); + + printf("%s <= domain_set_outstanding_pages() = %d\n", caller_func, ret); + testcase_assert_current_func = NULL; + testcase_assert_verbose_assertions = save_verbose_asserts; + return ret; +} +#define domain_set_outstanding_pages(dom, pages) \ + test_set_outstanding_pages(dom, pages, __func__) + +static struct page_info *__used test_alloc_domheap(struct domain *dom, + unsigned int order, + unsigned int memflags, + const char *caller_func) +{ + bool save_verbose_asserts = testcase_assert_verbose_assertions; + + /* Avoid logging verbose logging while allocating domheap pages */ + testcase_assert_verbose_assertions = false; + printf("%s => alloc_domheap_pages(dom=%u, order=%u, memflags=%x)\n", + caller_func, dom->domain_id, order, memflags); + testcase_assert_current_func = "alloc_domheap_pages"; + testcase_assert_verbose_indent_level++; + struct page_info *pg = alloc_domheap_pages(dom, order, memflags); + testcase_assert_verbose_indent_level--; + testcase_assert_current_func = NULL; + + testcase_assert_verbose_assertions = save_verbose_asserts; + return pg; +} +#define alloc_domheap_pages(dom, order, memflags) \ + test_alloc_domheap(dom, order, memflags, __func__) + +#ifdef CONFIG_SYSCTL +/* Helper for just getting the number of free pages for ASSERTs */ +static uint64_t __used free_pages(void) +{ + uint64_t free_pages, total_claims; + bool verbose_asserts_save = testcase_assert_verbose_assertions; + + /* Avoid logging spinlock actions while getting the free page count */ + testcase_assert_verbose_assertions = false; + get_outstanding_claims(&free_pages, &total_claims); + testcase_assert_verbose_assertions = verbose_asserts_save; + return free_pages; +} +#define FREE_PAGES free_pages() + +/* Helper for just getting the total number of claimed pages for ASSERTs */ +static uint64_t __used total_claims(void) +{ + uint64_t free_pages, total_claims; + bool verbose_asserts_save = testcase_assert_verbose_assertions; + + /* Avoid logging spinlock actions while getting the total claims */ + testcase_assert_verbose_assertions = false; + get_outstanding_claims(&free_pages, &total_claims); + testcase_assert_verbose_assertions = verbose_asserts_save; + return total_claims; +} +#define TOTAL_CLAIMS total_claims() + +#define DOM_GLOBAL_CLAIMS(d) ((d)->global_claims) +#define DOM_NODE_CLAIMS(d, n) ((d)->claims[n]) + +#endif /* CONFIG_SYSCTL */ + +static void print_order_list(nodeid_t node, zone_t zone, size_t order) +{ + struct page_info *pos = page_list_first(&heap(node, zone, order)); + + if ( pos ) + printf(" Heap for zone %zu, order %zu:\n", zone, order); + + while ( pos ) + { + size_t page_order = PFN_ORDER(pos); + + print_page_info(pos); + /* Print the subpages of the buddy head */ + for ( size_t sub_pg = 1; sub_pg < (1U << page_order); sub_pg++ ) + { + struct page_info *sub_pos = pos + sub_pg; + + printf(" "); + print_page_info(sub_pos); + /* Assert the subpages of a buddy to have order-0. */ + ASSERT(PFN_ORDER(sub_pos) == 0); + } + /* Assert that the page_order matches the heap order. */ + if ( page_order != order ) + { + printf("ERROR:mfn %lu has order %zu but expected %zu " + "based on heap position\n", + page_to_mfn(pos), page_order, order); + ASSERT(page_order == order); + } + pos = pos->list_next; + } +} + +#define CHECK_BUDDY(pages, fmt, ...) \ + check_buddy(pages, __FILE__, __LINE__, fmt, ##__VA_ARGS__) + +/* Function to print the order and first_dirty of each page for debugging. */ +static void check_buddy(struct page_info *pages, const char *file, int line, + const char *fmt, ...) +{ + size_t size = 1U << PFN_ORDER(pages); + bool verbose_asserts_save = testcase_assert_verbose_assertions; + va_list args; + + if ( fmt ) /* Print the given message for context in the logs.*/ + { + va_start(args, fmt); + printf(" %s:%d: ", file, line); + vprintf(fmt, args); + puts(":"); + va_end(args); + } + else + printf(" %s:%d: %s():\n", file, line, __func__); + + /* Avoid logging internal assertions while logging the free list status */ + testcase_assert_verbose_assertions = false; + + /* + * Inside pages, first_dirty must (if not INVALID_DIRTY_IDX) index the + * (first) page itself or a subpage within the page's range (<= 2^order). + */ + for ( size_t i = 0; i < size; i++ ) + { + unsigned long first_dirty = pages[i].u.free.first_dirty; + unsigned int tail_offset = (1U << PFN_ORDER(&pages[i])) - 1; + + if ( first_dirty != INVALID_DIRTY_IDX && first_dirty > tail_offset ) + { + printf("page at index %zu has first_dirty %lx but expected <= %u " + "based on its order\n", + i, first_dirty, tail_offset); + ASSERT(pages[i].u.free.first_dirty == tail_offset); + } + } + + /* Traverse the offlined list, print and assert errors in it. */ + struct page_info *pos = page_list_first(&page_offlined_list); + if ( pos ) + puts(" Offlined list:"); + while ( pos ) + { + print_and_assert_offlined_page(pos); + pos = pos->list_next; + } + + /* Traverse the broken list, print and assert errors in it. */ + pos = page_list_first(&page_broken_list); + if ( pos ) + puts(" Broken list:"); + while ( pos ) + { + print_and_assert_offlined_page(pos); + pos = pos->list_next; + } + + /* + * Traverse the _heap[node] for each order and zone and print and assert + * the order and first_dirty of each page for each heap for debugging. + * + * This is to help verify that the heap structure is consistent with the + * page_info order fields after operations that manipulate both, such as + * reserve_offlined_page(). + */ + for ( nodeid_t node = 0; node < MAX_NUMNODES; node++ ) + for ( size_t order = 0; order <= MAX_ORDER; order++ ) + for ( size_t zone = 0; zone < NR_ZONES; zone++ ) + print_order_list(node, zone, order); + testcase_assert_verbose_assertions = verbose_asserts_save; +} + +/* + * Failure reporting helper that prints the provided message, the test + * caller context and a native backtrace before aborting. + */ +static void fail_with_ctx(const char *caller_file, const char *caller_func, + int caller_line, const char *fmt, ...) +{ + va_list ap; + + fprintf(stderr, "\n- %s: Assertion failed: ", caller_func); + va_start(ap, fmt); + testcase_assert(false, caller_file, caller_line, caller_func, fmt, ap); + vfprintf(stderr, fmt, ap); + va_end(ap); +} + +/* + * Assert that a page_list matches the provided sequence of page pointers. + * + * The public helper below is a macro so call sites can provide a simple list + * of page pointers while the implementation works over an ordinary array. + */ +static void __used assert_list_eq_array(struct page_list_head *list, + struct page_info *const expected[], + unsigned int nr_expected, + const char *call_file, + const char *caller_func, + int caller_line) +{ + struct page_info *pos; + int fails_before = testcase_assert_expected_failures; + unsigned int index = 0; + + if ( list->count != nr_expected ) + fail_with_ctx(call_file, caller_func, caller_line, + "list count mismatch: expected %u, got %u", nr_expected, + list->count); + + if ( nr_expected == 0 ) + { + if ( page_list_first(list) != NULL ) + fail_with_ctx(call_file, caller_func, caller_line, + "expected empty list but head != NULL"); + else + testcase_assert_successful_assert_total++; + return; + } + + if ( page_list_first(list) != expected[0] ) + fail_with_ctx(call_file, caller_func, caller_line, + "list head mismatch: expected %p, got %p", expected[0], + page_list_first(list)); + + for ( pos = page_list_first(list); pos; pos = pos->list_next, index++ ) + { + if ( index >= nr_expected ) + fail_with_ctx(call_file, caller_func, caller_line, + "list contains more elements than expected"); + + if ( pos != expected[index] ) + fail_with_ctx(call_file, caller_func, caller_line, + "element %u mismatch: expected %p, got %p", index, + expected[index], pos); + + if ( pos->list_prev != (index ? expected[index - 1] : NULL) ) + fail_with_ctx(call_file, caller_func, caller_line, + "list_prev mismatch at index %u", index); + + if ( pos->list_next != + (index + 1 < nr_expected ? expected[index + 1] : NULL) ) + fail_with_ctx(call_file, caller_func, caller_line, + "list_next mismatch at index %u", index); + } + + if ( index != nr_expected ) + fail_with_ctx( + call_file, caller_func, caller_line, + "list element count consumed mismatch: expected %u, got %u", + nr_expected, index); + + if ( testcase_assert_expected_failures == fails_before ) + testcase_assert_successful_assert_total++; +} + +/** Assert that a page_list matches the provided sequence of page pointers. */ +#define ASSERT_LIST_EQUAL(list, ...) \ + do \ + { \ + struct page_info *const expected[] = {__VA_ARGS__}; \ + assert_list_eq_array((list), expected, ARRAY_SIZE(expected), \ + __FILE__, \ + __func__, __LINE__); \ + } while ( 0 ) +/** Assert that a page_list is empty. */ +#define ASSERT_LIST_EMPTY(list) ASSERT(page_list_empty(list)) diff --git a/tools/tests/alloc/page_alloc_shim.h b/tools/tests/alloc/page_alloc_shim.h new file mode 100644 index 000000000000..74459b6dda61 --- /dev/null +++ b/tools/tests/alloc/page_alloc_shim.h @@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Header-only shim for unit testing functions in xen/common/page_alloc.c. + * + * This header provides the necessary definitions and helpers to allow: + * + * 1) the test program to include the real page_alloc.c directly into its + * translation unit, and + * + * 2) the test scenarios to manipulate the allocator state and verify its + * behavior in a way that is consistent with the real page_alloc.c, while + * being self-contained and suitable for unit testing. + * + * The test page allocator shim provides the necessary definitions for the + * page_info structure and the translation functions between page_info + * pointers and MFNs, so that page_alloc.c can manipulate the page_info + * structures in the test frame table and verify its behavior in a way + * that is consistent with how page_alloc.c acts when used by the running + * hypervisor, while being self-contained and suitable for unit testing. + * + * Shim definitions for Xen types and functions used by page_alloc.c. + * + * This shim is intended to be included directly in the test program + * or header-only library for testing a specific scenario, included + * by the test program, for unit testing functions in common/page_alloc.c. + * + * It provides stubs (minimal definitions for Xen types and functions) + * used by page_alloc.c, sufficient to support the test scenarios in + * tools/tests/alloc. + * + * It is not intended to be complete or accurate for general use in + * other test contexts or as a general-purpose shim for page_alloc.c. + * + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef _TEST_ALLOC_PAGE_ALLOC_SHIM_ +#define _TEST_ALLOC_PAGE_ALLOC_SHIM_ + +/*. + * Guard against language servers and linters picking up this header in + * the wrong context. + * + * This header is only intended to be used in the test program for unit + * testing functions in xen/common/page_alloc.c, and test programs define + * TEST_USES_PAGE_ALLOC_SHIM to enable the definitions in this header. + */ +#ifndef TEST_USES_PAGE_ALLOC_SHIM +#warning "This header is only for use in page_alloc.c unit tests." +#else +/* + * Inside the intended test context, provide mocks and stub definitions. + */ + +/* Configure the included headers for the test context */ +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 64 +#endif + +#if defined(CONFIG_NUMA) && !defined(CONFIG_NR_NUMA_NODES) +#define CONFIG_NR_NUMA_NODES 64 +#endif + +#define CONFIG_SCRUB_DEBUG + +/* Provide struct page_info and related Xen definitions */ +#include "mock-page_list.h" + +/* Include the common check_asserts library for test assertions */ +#include "check-asserts.h" + +/* + * We add the Xen headers to the include path so page_alloc.c can + * resolve its #include directives without having to replicate all + * headers as actual files in the test tree: + * + * We define the header guards of those files to prevent unwanted + * definitions from those headers that conflict with the test harness. + */ +#define XEN_SOFTIRQ_H +#define XEN__XVMALLOC_H +#define _LINUX_INIT_H +#define _XEN_PARAM_H +#define __LIB_H__ /* C runtime library, only for the hypervisor */ +#define __LINUX_NODEMASK_H +#define __FLUSHTLB_H__ +#define __SCHED_H__ +#define __SPINLOCK_H__ +#define __TYPES_H__ /* Conflicts with the compiler-provided types */ +#define __VM_EVENT_H__ +#define __X86_PAGE_H__ +#define __XEN_CPUMASK_H +#define __XEN_EVENT_H__ +#define __XEN_FRAME_NUM_H__ +#define __XEN_IRQ_H__ +#define __XEN_MM_H__ +#define __XEN_PDX_H__ + +#include +#include +#include + +/* Include xen/numa.h with stubs and unused parameter warnings disabled */ +#define cpumask_clear_cpu(cpu, mask) ((void)(cpu), (void)(mask)) +#define mfn_to_pdx(mfn) ((unsigned long)(mfn)) +#pragma GCC diagnostic push +#ifndef CONFIG_NUMA +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif +#include +#pragma GCC diagnostic pop + +/* Flexible definition to support 32- and 64-bit architectures */ +#undef PADDR_BITS +#define PADDR_BITS (BITS_PER_LONG - PAGE_SHIFT) +#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) +#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define INVALID_MFN_INITIALIZER (~0UL) + +typedef unsigned long nodemask_t; + +struct domain { + spinlock_t page_alloc_lock; + nodemask_t node_affinity; + nodeid_t last_alloc_node; + domid_t domain_id; + unsigned int tot_pages; + unsigned int max_pages; + unsigned int extra_pages; + unsigned int global_claims; + unsigned int node_claims; + unsigned int claims[MAX_NUMNODES]; + unsigned int xenheap_pages; + bool is_dying; + struct domain *next_in_list; +}; +extern struct domain *domain_list; + +struct vcpu { + struct domain *domain; +}; + +/* + * Provide two domains for the test context, so that test helpers can + * call allocator functions that require domain context and verify behavior + * that depends on domain state, such as claims accounting and page allocation + * for specific domains. + */ +static struct domain test_dummy_domain1; +static struct domain test_dummy_domain2; +static struct domain __used *dom1 = &test_dummy_domain1; +static struct domain __used *dom2 = &test_dummy_domain2; + +/* To provide a current vcpu/domain pair for code paths that inspect it. */ +static unsigned char test_dummy_storage[PAGE_SIZE]; +static struct vcpu test_current_vcpu; +static struct vcpu *current = &test_current_vcpu; +static cpumask_t cpu_online_map = ~0UL; + +#define for_each_domain(_d) \ + for ( (_d) = domain_list; (_d) != NULL; (_d) = (_d)->next_in_list ) +#define for_each_online_node(i) for ( (i) = 0; (i) < MAX_NUMNODES; ++(i) ) +#define for_each_cpu(i, mask) for ( (i) = 0; (i) < 1; ++(i) ) + +/* dom_cow is a domain pointer used by the memory sharing code */ +#ifdef CONFIG_MEM_SHARING +static struct domain *dom_cow; +#else +#define dom_cow NULL +#endif + +/* + * Logging spinlock for the test context + */ +static spinlock_t *heap_lock_ptr; + +/* Helper function to track spinlock actions for additional context */ +static void print_spinlock(const char *action, spinlock_t *lock, + const char *file, int line, const char *func) +{ + const char *relpath = file; + + if ( !testcase_assert_verbose_assertions ) + return; + + while ( (file = strstr(relpath, "../")) ) + relpath += 3; + + for ( int i = 0; i < testcase_assert_verbose_indent_level; i++ ) + printf(" "); + + /* Print the path first:*/ + if ( testcase_assert_current_func == NULL || + strcmp(testcase_assert_current_func, func) != 0 ) + printf("%s:%d: %s(): ", relpath, line, func); + else + printf("%s:%d: ", relpath, line); + + if ( lock == heap_lock_ptr ) + printf("heap_lock %s\n", action); + else if ( domain_list && lock == &test_dummy_domain1.page_alloc_lock ) + printf("dom1->page_alloc_lock %s\n", action); + else if ( domain_list && lock == &test_dummy_domain2.page_alloc_lock ) + printf("dom2->page_alloc_lock %s\n", action); + else + printf("unknown lock %p %s\n", (void *)lock, action); +} + +/* + * If testcase_assert_verbose_assertions is enabled, the spinlock + * functions print the spinlock being acquired or released along with + * the file and line number of the assertion that triggered it. + * This can be helpful for debugging test failures and understanding + * the sequence of events leading up to the failure. + */ +#define spin_lock(l) \ + (print_spinlock("acquired", l, __FILE__, __LINE__, __func__), (void)(l)) +#define spin_unlock(l) \ + (print_spinlock("released", l, __FILE__, __LINE__, __func__), (void)(l)) +#define spin_lock_cb(l, cb, data) spin_lock(l) +#define spin_lock_kick() ((void)0) +#define nrspin_lock(l) spin_lock(l) +#define nrspin_unlock(l) spin_unlock(l) +#define rspin_lock(l) spin_lock(l) +#define rspin_unlock(l) spin_unlock(l) +#define DEFINE_SPINLOCK(l) spinlock_t l +/* + * For the test context, we assume all locks are always held to avoid having + * to manage lock state in the test helpers. This allows the test helpers + * to call allocator functions that require locks to be held without needing + * to acquire those locks, which simplifies the test code and focuses on + * exercising the allocator logic under test. + * + * Invariants that would normally be protected by locks must still be upheld + * by the test helpers, but the test helpers can assume they have exclusive + * access to the allocator state and do not need to worry about concurrency. + */ +#define spin_is_locked(l) true +#define rspin_is_locked(l) true + +/* memflags: */ +#define _MEMF_no_refcount 0 +#define MEMF_no_refcount (1U << _MEMF_no_refcount) +#define _MEMF_populate_on_demand 1 +#define MEMF_populate_on_demand (1U << _MEMF_populate_on_demand) +#define _MEMF_keep_scrub 2 +#define MEMF_keep_scrub (1U << _MEMF_keep_scrub) +#define _MEMF_no_dma 3 +#define MEMF_no_dma (1U << _MEMF_no_dma) +#define _MEMF_exact_node 4 +#define MEMF_exact_node (1U << _MEMF_exact_node) +#define _MEMF_no_owner 5 +#define MEMF_no_owner (1U << _MEMF_no_owner) +#define _MEMF_no_tlbflush 6 +#define MEMF_no_tlbflush (1U << _MEMF_no_tlbflush) +#define _MEMF_no_icache_flush 7 +#define MEMF_no_icache_flush (1U << _MEMF_no_icache_flush) +#define _MEMF_no_scrub 8 +#define MEMF_no_scrub (1U << _MEMF_no_scrub) +#define _MEMF_node 16 +#define MEMF_node_mask ((1U << (8 * sizeof(nodeid_t))) - 1) +#define MEMF_node(n) ((((n) + 1)&MEMF_node_mask) << _MEMF_node) +#define MEMF_get_node(f) ((((f) >> _MEMF_node) - 1)&MEMF_node_mask) +#define _MEMF_bits 24 +#define MEMF_bits(n) ((n) << _MEMF_bits) + +#define string_param(name, var) +#define custom_param(name, fn) +#define size_param(name, var) +#define boolean_param(name, func) +#define integer_param(name, var) +#define ACCESS_ONCE(x) (x) +#define cmpxchg(ptr, oldv, newv) \ + ({ \ + *(ptr) = (newv); \ + (oldv); \ + }) + +#define is_xen_heap_page(pg) false +#define page_to_virt(pg) ((void *)(pg)) +#define virt_to_page(v) ((struct page_info *)(v)) +#define mfn_to_virt(mfn) ((void *)&test_dummy_storage) +#define __mfn_to_virt(mfn) mfn_to_virt(mfn) +#define _mfn(x) ((mfn_t)(x)) +#define mfn_x(x) ((unsigned long)(x)) +#define mfn_add(mfn, nr) ((mfn) + (nr)) +#define mfn_min(a, b) ((a) < (b) ? (a) : (b)) + +/* + * NUMA stubs for unit testing NUMA-aware page allocator logic. + * + * nodemask_test() and node_set() implement real bit operations so that + * domain_install_claim_set() can correctly detect duplicate node entries + * in a claim set. mfn_to_pdx() is defined before xen/numa.h is included. + */ + +static nodemask_t node_online_map = ~0UL; +#define num_online_nodes() MAX_NUMNODES +#define node_online(node) ((node) < MAX_NUMNODES) +#define nodes_intersects(a, b) ((a) & (b)) +#define nodes_and(dst, a, b) ((dst) = (a) & (b)) +#define nodes_andnot(dst, a, b) ((dst) = (a) & ~(b)) +#define nodes_clear(dst) ((dst) = 0) +#define nodemask_test(node, mask) ((*(mask) >> (node)) & 1UL) +#define node_set(node, mask) ((mask) |= (1UL << (node))) +#define node_clear(node, mask) ((void)(mask)) +#define node_test_and_set(node, mask) false +#define first_node(mask) 0U +#define next_node(node, mask) MAX_NUMNODES +#define cycle_node(node, mask) 0U + +#ifdef CONFIG_NUMA +#define __node_distance(a, b) 0 +nodeid_t cpu_to_node[NR_CPUS]; +cpumask_t node_to_cpumask[MAX_NUMNODES]; +struct node_data node_data[MAX_NUMNODES]; +unsigned int memnode_shift; + +static typeof(*memnodemap) _memnodemap[64]; +nodeid_t *memnodemap = _memnodemap; +unsigned long memnodemapsize = sizeof(_memnodemap); +#endif /* CONFIG_NUMA */ + +/* + * Stub definitions for Xen functions and macros used by page_alloc.c, + * sufficient to support the test scenarios in tools/tests/alloc. + * + * These are not intended to be complete or accurate for general use + * in other test contexts or as a general-purpose shim for page_alloc.c. + */ +#define rcu_lock_domain(id) (&test_dummy_domain1) +#define rcu_lock_domain_by_any_id(id) (&test_dummy_domain1) +#define NOW() 0LL +#define SYS_STATE_active 1 +#define system_state 0 +#define cpu_online(cpu) ((cpu) == 0) +#define smp_processor_id() 0U +#define smp_wmb() ((void)0) +#define cpumask_empty(mask) true +#define cpumask_clear(mask) ((void)(mask)) +#define cpumask_and(dst, a, b) ((void)(dst), (void)(a), (void)(b)) +#define cpumask_or(dst, a, b) ((void)(dst), (void)(a), (void)(b)) +#define cpumask_copy(dst, src) ((void)(dst), (void)(src)) +#define cpumask_first(mask) 0U +#define cpumask_intersects(a, b) false +#define cpumask_weight(mask) 1 +#define __cpumask_set_cpu(cpu, mask) ((void)(cpu), (void)(mask)) +#define page_get_owner(pg) ((pg)->owner) +#define page_set_owner(pg, d) ((pg)->owner = (d)) +#define page_get_owner_and_reference(pg) ((pg)->owner) +#define page_set_tlbflush_timestamp(pg) ((pg)->tlbflush_timestamp = 0) +#define set_gpfn_from_mfn(mfn, gpfn) ((void)0) +#define page_is_offlinable(mfn) true +#define is_xen_fixed_mfn(mfn) false +#define filtered_flush_tlb_mask(ts) ((void)(ts)) +#define accumulate_tlbflush(need, pg, ts) ((void)(need), (void)(pg), (void)(ts)) +#define flush_page_to_ram(mfn, icache) ((void)(mfn), (void)(icache)) +#define scrub_page_hot(ptr) clear_page_hot(ptr) +#define scrub_page_cold(ptr) clear_page_cold(ptr) +#define send_global_virq(virq) ((void)(virq)) +#define softirq_pending(cpu) false +#define process_pending_softirqs() ((void)0) +#define on_selected_cpus(msk, f, data, w) ((void)0) +#define cpu_relax() ((void)0) +#define xmalloc(type) calloc(1, sizeof(type)) +#define xmalloc_array(type, nr) calloc((nr), sizeof(type)) +#define xvzalloc_array(type, nr) calloc((nr), sizeof(type)) +#define xvmalloc_array(type, nr) calloc((nr), sizeof(type)) +#define get_order_from_pages(nr) 0U +#define get_order_from_bytes(bytes) 0U +#define arch_mfns_in_directmap(mfn, nr) true +#define maddr_to_mfn(pa) ((mfn_t)paddr_to_pfn(pa)) + +#define ASSERT_ALLOC_CONTEXT() ((void)0) +#define arch_free_heap_page(d, pg) ((void)(d), (void)(pg)) +#define get_knownalive_domain(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, bits) (bits) +#define mem_paging_enabled(d) false +#define put_domain(d) ((void)(d)) +#define clear_page_hot(ptr) memset((ptr), 0, PAGE_SIZE) +#define clear_page_cold(ptr) memset((ptr), 0, PAGE_SIZE) +#define unmap_domain_page(ptr) ((void)(ptr)) +#define put_page(pg) ((void)(pg)) + +void *alloc_xenheap_pages(unsigned int order, unsigned int memflags); +void init_domheap_pages(paddr_t ps, paddr_t pe); +struct page_info *alloc_domheap_pages(struct domain *d, unsigned int order, + unsigned int memflags); + +/* Additional stubs for test support */ + +unsigned int arch_get_dma_bitsize(void) +{ + return 32U; +} + +/* Return number of pages currently posessed by the domain */ +static inline unsigned int domain_tot_pages(const struct domain *d) +{ + assert(d->extra_pages <= d->tot_pages); + return d->tot_pages - d->extra_pages; +} + +/* LLC (Last Level Cache) coloring support stubs */ +#define llc_coloring_enabled false +unsigned int get_max_nr_llc_colors(void) +{ + return 1U; +} +unsigned int page_to_llc_color(const struct page_info *pg) +{ + (void)pg; + return 0U; +} + +#define parse_bool(s, e) (-1) /* Not parsed, use the default */ + +void __init register_keyhandler(unsigned char key, keyhandler_fn_t *fn, + const char *desc, bool diagnostic) +{ + (void)key; + (void)fn; + (void)desc; + (void)diagnostic; +} + +unsigned long simple_strtoul(const char *cp, const char **endp, + unsigned int base) +{ + return strtoul(cp, (char **)endp, base); +} + +#endif /* TEST_USES_PAGE_ALLOC_SHIM */ +#endif /* _TEST_ALLOC_PAGE_ALLOC_SHIM_ */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:48:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:48:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282742.1565233 (Exim 4.92) (envelope-from ) id 1wD4Lg-00021r-Uo; Wed, 15 Apr 2026 17:48:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282742.1565233; Wed, 15 Apr 2026 17:48:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Lg-00021k-SA; Wed, 15 Apr 2026 17:48:24 +0000 Received: by outflank-mailman (input) for mailman id 1282742; Wed, 15 Apr 2026 17:48:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Lf-00021e-0r for xen-devel@lists.xenproject.org; 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none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH 2/4] tools/tests/alloc: Add integration test suite for memory claims Date: Wed, 15 Apr 2026 18:34:57 +0100 Message-Id: <355d67b11c88695bec517a16d88b696a96ed0e5f.1776273656.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776275302-1734C2A1-D9852D6D/0/0 X-purgate-type: clean X-purgate-size: 18715 Add a host-side integration test suite for memory claims, including NUMA-aware claim sets. This complements the functional system tests submitted as part of the NUMA-aware claims series. It verifies the behaviour of the page allocator when multi-node claim sets are present in situations that are easier to create and validate in isolation, with full control over a synthetic Xen heap state and visibility into the claim state of domains as claims are made and redeemed through heap allocation. The included tests cover a range of claim-related scenarios to ensure that the Xen page allocator behaves as expected. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-claims_basic.c | 230 ++++++++++++++++++++ tools/tests/alloc/test-claims_numa_redeem.c | 201 +++++++++++++++++ 2 files changed, 431 insertions(+) create mode 100644 tools/tests/alloc/test-claims_basic.c create mode 100644 tools/tests/alloc/test-claims_numa_redeem.c diff --git a/tools/tests/alloc/test-claims_basic.c b/tools/tests/alloc/test-claims_basic.c new file mode 100644 index 000000000000..f81e75876d30 --- /dev/null +++ b/tools/tests/alloc/test-claims_basic.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Unit tests for memory claims in xen/common/page_alloc.c. + * + * Copyright (C) 2026 Cloud Software Group + */ + +/* Enable sysctl support in page_alloc.c for testing get_outstanding_claims() */ +#define CONFIG_NUMA 1 +#define CONFIG_SYSCTL 1 +#include "libtest-page_alloc.h" + +/* + * Wrapper for domain_install_claim_set() with the function signature as + * domain_set_outstanding_pages() to test both domain_install_claim_set() + * and domain_set_outstanding_pages() by using a function pointer for + * setting claims to check feature parity and consistent behavior. + */ + +int test_set_global_claims(struct domain *d, unsigned long pages) +{ + memory_claim_t claim_set[] = { + {.target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, .pages = pages}, + }; + return domain_install_claim_set(d, ARRAY_SIZE(claim_set), claim_set); +} +typedef int (*set_global_claims)(struct domain *d, unsigned long pages); + +/* + * Function pointer to test both domain_install_claim_set() and + * domain_set_outstanding_pages() interchangeably in the test + * scenarios for feature parity and consistent behaviour. + */ +set_global_claims install_global_claims = test_set_global_claims; + +/* + * Test that memory claims are consumed correctly during allocations. + */ +static void test_alloc_domheap_consumes_claims(int start_mfn) +{ + unsigned long avail_pages_zone; + int zone, ret; + struct page_info *pages = test_pages + start_mfn, *allocated; + + /* + * PREPARE + */ + + /* Create a buddy of order 2 (4 pages) and add it to the heap. */ + zone = test_page_list_add_buddy(pages, order2); + + /* Verify the initial state of the heap */ + ASSERT_LIST_EQUAL(&heap(node, zone, order2), pages); + ASSERT(page_list_empty(&heap(node, zone, order1))); + ASSERT(page_list_empty(&heap(node, zone, order0))); + CHECK_BUDDY(pages, "Order-2 buddy prepared on the heap"); + + /* + * ACT 1 + */ + + /* Claim 3 out of the 4 pages for the dummy domain */ + ret = test_set_global_claims(dom1, 3); + ASSERT(ret == 0); + + /* Allocate an order-1 page for the dummy domain */ + allocated = alloc_domheap_pages(dom1, order1, 0); + CHECK(allocated == &pages[2], "Expect allocation start at 3rd page"); + + /* + * ASSERT 1 + * + * The allocation is expected to split the order-2 buddy and allocate + * an order-1 chunk from it, leaving the remaining order-1 chunk as a free + * available pages, and the claim should have been consumed accordingly. + */ + + /* Verify the state of the heap after allocation */ + ASSERT(page_list_empty(&heap(node, zone, order2))); + ASSERT(page_list_empty(&heap(node, zone, order0))); + /* The remaining order-1 chunk should be the first page */ + ASSERT_LIST_EQUAL(&heap(node, zone, order1), pages); + CHECK_BUDDY(pages, "Buddy after order-1 allocation"); + + /* Verify the state of the aggregate counters */ + CHECK(TOTAL_CLAIMS == 1, "Expect 1 claims left after allocation"); + CHECK(FREE_PAGES == 2, "Expect 2 available after allocation"); + CHECK(avail_heap_pages(zone, zone, node) == 2, "Expect 2 in zone"); + + /* + * ACT 2 + */ + + /* Allocate one of the two remaining order-0 pages for the dummy domain */ + allocated = alloc_domheap_pages(dom1, order0, 0); + CHECK(allocated == &pages[1], "alloc_domheap_pages returned the 2nd page"); + + /* + * ASSERT 2 + * + * The allocation is expected to split the remaining order-1 + * buddy and allocate an order-0 page from it, leaving the + * remaining order-0 page as a free available page, and the + * claim should have been consumed accordingly. + */ + + /* Verify the state of the heap after allocation */ + ASSERT(page_list_empty(&heap(node, zone, order2))); + ASSERT(page_list_empty(&heap(node, zone, order1))); + /* The remaining order-0 page should be the only free page we've left */ + ASSERT_LIST_EQUAL(&heap(node, zone, order0), pages); + + /* Verify the state of the aggregate counters */ + CHECK(TOTAL_CLAIMS == 0, "Expect all claims consumed after allocation"); + CHECK(FREE_PAGES == 1, "Expect one free page after allocation"); + + avail_pages_zone = avail_heap_pages(zone, zone, node); + CHECK(avail_pages_zone == 1, "Expect one page in zone after allocation"); + + /* + * PREPARE 3 + */ + + /* Claim all free memory from another domain to block allocations */ + ret = test_set_global_claims(dom2, FREE_PAGES); + ASSERT(ret == 0); + + /* + * ACT 3 + */ + + /* Claim more than dom1 already has fails with ENOMEM (claimed by dom2) */ + ret = test_set_global_claims(dom1, domain_tot_pages(dom1) + 1); + CHECK(ret == -ENOMEM, "dom 1 claim +1 fails due to insufficient pages"); + + /* Claim more than dom1's d->max_pages fails with EINVAL */ + ret = test_set_global_claims(dom1, dom1->max_pages + 1); + CHECK(ret == -EINVAL, "dom 1 claim fails due to exceeding max_pages"); + + /* Attempt to allocate an order-0 page with a foreign claim present */ + allocated = alloc_domheap_pages(dom1, order0, 0); + CHECK(allocated == NULL, "dom 1 alloc fails b/c domain 2's claim"); + + /* + * ASSERT 3 + */ + + /* Verify the state of the heap after failed allocation (no changes) */ + ASSERT(page_list_empty(&heap(node, zone, order2))); + ASSERT(page_list_empty(&heap(node, zone, order1))); + /* Due to the foreign claim, the remaining page should still be free */ + ASSERT_LIST_EQUAL(&heap(node, zone, order0), pages); + + /* Verify the state of the aggregate counters (no changes expected) */ + CHECK(TOTAL_CLAIMS == 1, "Expect domain 2's claim to be still present"); + CHECK(FREE_PAGES == 1, "Expect one free page after failed alloc"); + + avail_pages_zone = avail_heap_pages(zone, zone, node); + CHECK(avail_pages_zone == 1, "Expect one page in zone after allocation"); +} + +/* + * Test that memory claims are consumed correctly during allocations. + */ +static void test_cancel_claims(int start_mfn) +{ + struct page_info *page = test_pages + start_mfn; + unsigned long claims; + + /* Create a buddy of order 2 (4 pages) and add it to the heap. */ + test_page_list_add_buddy(page, order2); + claims = FREE_PAGES / 2; + /* Claim half of the free pages for dom1 */ + ASSERT(test_set_global_claims(dom1, claims) == 0); + ASSERT(TOTAL_CLAIMS == claims); + + /* + * Act: Cancel the claims for the dummy domain and verify that the + * claim counts are updated and the free pages are available again. + */ + + /* Act + Assert 2: Claim all free pages for dom2, should fail */ + ASSERT(test_set_global_claims(dom2, FREE_PAGES) == -ENOMEM); + ASSERT(TOTAL_CLAIMS == claims); + + /* Act + Assert 1: Cancel all claims for dom1 */ + ASSERT(test_set_global_claims(dom1, 0) == 0); + ASSERT(TOTAL_CLAIMS == 0); + + /* Act + Assert 2: Claim all free pages for dom2, should work */ + ASSERT(test_set_global_claims(dom2, FREE_PAGES) == 0); + ASSERT(TOTAL_CLAIMS == FREE_PAGES); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test legacy claims with allocation from the heap"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + + /* Use domain_set_outstanding_pages() for staking claims */ + install_global_claims = domain_set_outstanding_pages; + RUN_TESTCASE(ADCL, test_alloc_domheap_consumes_claims, 0); + + /* + * Use test_set_global_claims() which is a wrapper around + * domain_install_claim_set() to check ensure consistent + * behavior with domain_set_outstanding_pages(). + */ + install_global_claims = test_set_global_claims; + RUN_TESTCASE(ADCG, test_alloc_domheap_consumes_claims, 4); + + RUN_TESTCASE(TCCL, test_cancel_claims, 0); + + testcase_print_summary(program_name); + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/alloc/test-claims_numa_redeem.c b/tools/tests/alloc/test-claims_numa_redeem.c new file mode 100644 index 000000000000..61bec12be1c0 --- /dev/null +++ b/tools/tests/alloc/test-claims_numa_redeem.c @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Integration tests for redeeming NUMA memory claim set as implemented + * in xen/common/page_alloc.c's redeem_claims_for_allocation() and + * related functions. + * + * redeem_claims_for_allocation() is exercised indirectly through + * alloc_domheap_pages() which is the primary interface for allocating + * pages from a domain's heap. + * + * By means of domain_install_claim_set(), a claim set with global and + * per-NUMA-node claims is installed for a dummy domain, and then + * allocations with NUMA node affinity are performed to verify that the + * appropriate claims are redeemed (same-node first, global fallback next, + * then other nodes to not exceed page limits). The test also verifies that + * aggregate counters are updated correctly after each allocation. + * + * The test verifies that when a domain has a claim set installed with + * global and per-NUMA-node claims, allocations that specify NUMA node + * affinity will redeem the appropriate claims (same-node first, global + * fallback claim next, then other nodes to not exceed page limits). + * It also verifies that the aggregate claim counters are updated + * correctly after each allocation. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#define CONFIG_NUMA 1 +#define CONFIG_SYSCTL 1 +#include "libtest-page_alloc.h" + +/* + * Test redeeming NUMA memory claims in exchange for allocations, + * and the redeemed claims are correctly reflected in the domain's + * claim state and the aggregate claim counters. + */ +static void test_claims_numa_install(int start_mfn) +{ + unsigned long avail_pages_zone; + int zone, ret; + struct page_info *pages = test_pages + start_mfn, *allocated; + + /* + * PREPARE + */ + + /* + * Node 1's pages start at the pfn set by init_numa_node_data(): + * node_data[node1].node_start_pfn = start_mfn + 8 (8 MFNs per node with + * memnode_shift=3). The order-2 buddy (4 pages) placed there satisfies + * the 2-page node1 claim and provides enough total pages for the + * 2 global + 2 node0 + 2 node1 = 6-page claim set (2 + 4 = 6 total). + */ + struct page_info *pages_node1 = + test_pages + node_data[node1].node_start_pfn; + + /* Create an order-1 buddy (2 pages) for node 0 and add it to the heap. */ + zone = test_page_list_add_buddy(pages, order1); + + /* Verify the initial state of node 0's heap. */ + ASSERT_LIST_EQUAL(&heap(node0, zone, order1), pages); + ASSERT(page_list_empty(&heap(node0, zone, order0))); + CHECK_BUDDY(pages, "Order-1 buddy on node 0 prepared"); + + /* Create an order-2 buddy (4 pages) for node 1 and add it to the heap. */ + test_page_list_add_buddy(pages_node1, order2); + CHECK_BUDDY(pages_node1, "Order-2 buddy on node 1 prepared"); + + /* + * ACT 1 + */ + + /* Install a claim set with global + per-NUMA-node claims. */ + memory_claim_t claim_set[] = { + {.target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, .pages = 2}, + {.target = node0, .pages = 2}, + {.target = node1, .pages = 2}, + }; + ret = domain_install_claim_set(dom1, ARRAY_SIZE(claim_set), claim_set); + CHECK(ret == 0, "domain_install_claim_set should succeed: %d", ret); + + /* Assert dom1's claims */ + CHECK(TOTAL_CLAIMS == 6, "Expect 6 total claims after installation"); + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 having 2 global claims after installation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 2, + "Expect dom1 having 2 claims for node0 after installation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 2, + "Expect dom1 having 2 claims for node1 after installation"); + + /* Allocate an order-0 page from node 0 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node0)); + CHECK(allocated != NULL, "alloc_domheap_pages should succeed"); + + /* + * ASSERT 1 + * + * The order-0 allocation from node 0 splits the node 0 order-1 buddy: + * - The lower half (pages[0]) stays on node 0's order-0 heap. + * - The upper half (pages[1]) is returned as the allocated page. + * One node 0 claim is consumed by the allocation. + */ + CHECK_BUDDY(pages, "Buddy after order-0 allocation"); + /* Verify the state of node 0's heap after allocation. */ + ASSERT(page_list_empty(&heap(node0, zone, order2))); + ASSERT(page_list_empty(&heap(node0, zone, order1))); + /* The lower half (pages[0]) remains as the sole order-0 buddy on node 0. */ + ASSERT_LIST_EQUAL(&heap(node0, zone, order0), pages); + + avail_pages_zone = avail_heap_pages(zone, zone, node0); + CHECK(avail_pages_zone == 1, "Expect one page in node0 after allocation"); + + /* Verify the state of the aggregate counters after allocation. */ + CHECK(TOTAL_CLAIMS == 5, "Expect 5 total claims left after allocation"); + CHECK(FREE_PAGES == 5, "Expect 5 free pages left after allocation"); + + /* Assert dom1's claims after the allocation from node0 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 still having 2 global claims after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 2, + "Expect dom1 still having 2 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 still having 2 global claims after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 1, + "Expect dom1 having 1 claim for node1 after allocation"); + + /* Allocate an order-1 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order1, MEMF_node(node1)); + CHECK(allocated != NULL, "order-1 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 1, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 0, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 0, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 0, + "Expect dom1 having 0 claims for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test legacy claims with allocation from the heap"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + /* + * Use test_set_global_claims() which is a wrapper around + * domain_install_claim_set() to check ensure consistent + * behavior with domain_set_outstanding_pages(). + */ + RUN_TESTCASE(CNI0, test_claims_numa_install, 0); + + testcase_print_summary(program_name); + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:49:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:49:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282759.1565244 (Exim 4.92) (envelope-from ) id 1wD4Ms-0002Xy-8X; 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Wed, 15 Apr 2026 19:49:36 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69dfcfaf-ee98-0a2a450a0019-a0658309cb08-3 for ; Wed, 15 Apr 2026 19:49:36 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 063EE81BB9DF; Wed, 15 Apr 2026 13:48:41 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH 3/4] tools/tests/alloc: Add tests for offlining with claims present Date: Wed, 15 Apr 2026 18:34:58 +0100 Message-Id: <84f126a27ba8035601777e8cdb0d5d0a6a337c51.1776273656.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776275376-C461F0B1-D5967C0C/0/0 X-purgate-type: clean X-purgate-size: 4750 Add an integration test for offlining pages with outstanding claims. The test offlines two pages, with the second offline operation recalling one claim to prevent over-claiming beyond the available memory. Due to missing checks in the offlining code, there are expected failures which will be fixed in a test-driven manner. Run this test with both global claims and node-local claims. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-offlining-claims.c | 106 ++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 tools/tests/alloc/test-offlining-claims.c diff --git a/tools/tests/alloc/test-offlining-claims.c b/tools/tests/alloc/test-offlining-claims.c new file mode 100644 index 000000000000..d22d270ceeb4 --- /dev/null +++ b/tools/tests/alloc/test-offlining-claims.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Integration test for offlining pages with outstanding claims in page_alloc.c. + * + * Copyright (C) 2026 Cloud Software Group + */ + +/* Enable sysctl support in page_alloc.c for testing get_outstanding_claims() */ +#define CONFIG_SYSCTL +#define CONFIG_NUMA +#include "libtest-page_alloc.h" + +/* + * Claim 3 of 4 pages globally, offline two pages, and the 2nd offline should + * recall one claim to prevent over-claiming beyond the available memory. + * + * As part of offline_page(), reserve_offlined_page() should recall the + * needed claims to not exceed the number of pages that are are remaining. + */ +static void test_offlining_with_global_claims(int mfn) +{ + struct page_info *page = test_pages + mfn; + uint32_t status = 0; + memory_claim_t claims[1] = { + {.pages = 3, .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL} + }; + + /* PREPARE */ + test_page_list_add_buddy(page, order2); /* Add a buddy with 4 free pages*/ + ASSERT(domain_install_claim_set(dom1, ARRAY_SIZE(claims), claims) == 0); + offline_page(mfn + 3, 0, &status); /* Offline the 1st page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + CHECK(TOTAL_CLAIMS == 3, "Still 3 claims before offlining the 2nd page"); + + /* ACT */ + /* Offlining the 2nd page must reduce the free pages and claims to 2 */ + status = 0; + offline_page(mfn + 1, 0, &status); /* Offline the 2nd page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + + /* ASSERT */ + CHECK_BUDDY(page, "After offlining the 2nd page"); + CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); + EXPECTED_TO_FAIL_BEGIN(); + CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); + EXPECTED_TO_FAIL_END(1); +} + + +/* + * Claim 3 of 4 pages on node0, offline two pages, and the 2nd offline should + * recall one claim to prevent over-claiming beyond the available memory. + * + * As part of offline_page(), reserve_offlined_page() should recall the + * needed claims to not exceed the number of pages that are are remaining. + */ +static void test_offlining_with_node_claims(int mfn) +{ + struct page_info *page = test_pages + mfn; + uint32_t status = 0; + memory_claim_t claims[1] = { {.pages = 3, .target = node0} }; + + /* PREPARE */ + test_page_list_add_buddy(page, order2); /* Add a buddy with 4 free pages*/ + ASSERT(domain_install_claim_set(dom1, ARRAY_SIZE(claims), claims) == 0); + ASSERT(offline_page(mfn + 3, 0, &status) == 0); /* Offline the 1st page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + CHECK(TOTAL_CLAIMS == 3, "Still 3 claims before offlining the 2nd page"); + + /* ACT */ + /* Offlining the 2nd page must reduce the free pages and claims to 2 */ + ASSERT(offline_page(mfn + 1, 0, &status) == 0); /* Offline the 2nd page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + + /* ASSERT */ + CHECK_BUDDY(page, "After offlining the 2nd page"); + CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); + EXPECTED_TO_FAIL_BEGIN(); + CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); + EXPECTED_TO_FAIL_END(1); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test offlining with memory claims"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + + RUN_TESTCASE(OWGC, test_offlining_with_global_claims, 0); + RUN_TESTCASE(OWNC, test_offlining_with_node_claims, 0); + + return testcase_print_summary(program_name); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:50:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:50:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282779.1565251 (Exim 4.92) (envelope-from ) id 1wD4Nf-00041i-FZ; Wed, 15 Apr 2026 17:50:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282779.1565251; Wed, 15 Apr 2026 17:50:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Nf-00041a-Ch; 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Wed, 15 Apr 2026 13:49:41 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 4/4] xen/mm: Recall claims when offlining pages if needed Date: Wed, 15 Apr 2026 18:34:59 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776275426-7694D497-AB44D8E1/0/0 X-purgate-type: clean X-purgate-size: 4038 Fix a bug where offlining pages could cause an unsigned underflow in total_avail_pages - outstanding_claims, leading to incorrect claim behavior. This issue arises when outstanding claims are close to the total available pages. It occurse when domain_set_outstanding_claims() and domain_install_claim_set effectively do this: unsigned long avail_pages = total_avail_pages - outstanding_claims; When this unsigned subtraction underflows, staking claims can succeed even when there is insufficient unclaimed memory for the new claim. This leads to a state where claims always succeed, regardless of actual memory availability. To prevent this, recall claims when offlining pages if needed to maintain equilibrium between `total_avail_pages` and outstanding claims for global and for per-NUMA-node claims. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-offlining-claims.c | 4 --- xen/common/page_alloc.c | 42 +++++++++++++++++++++++ 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/tools/tests/alloc/test-offlining-claims.c b/tools/tests/alloc/test-offlining-claims.c index d22d270ceeb4..0844c792e740 100644 --- a/tools/tests/alloc/test-offlining-claims.c +++ b/tools/tests/alloc/test-offlining-claims.c @@ -41,9 +41,7 @@ static void test_offlining_with_global_claims(int mfn) /* ASSERT */ CHECK_BUDDY(page, "After offlining the 2nd page"); CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); - EXPECTED_TO_FAIL_BEGIN(); CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); - EXPECTED_TO_FAIL_END(1); } @@ -75,9 +73,7 @@ static void test_offlining_with_node_claims(int mfn) /* ASSERT */ CHECK_BUDDY(page, "After offlining the 2nd page"); CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); - EXPECTED_TO_FAIL_BEGIN(); CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); - EXPECTED_TO_FAIL_END(1); } int main(int argc, char *argv[]) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 6101bd6be9a9..adedf6fae590 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -1575,6 +1575,48 @@ static int reserve_offlined_page(struct page_info *head) count++; } + if ( count ) + { + long recall_pages; + struct domain *d; + + /* Ensure that claims on the node are in line with its free memory. */ + recall_pages = node_outstanding_claims[node] - node_avail_pages[node]; + if ( recall_pages > 0 ) + /* + * node_avail_pages slipped below node_outstanding_claims. + * We need to recall claimed pages until the amount of claimed + * memory is in line with the amount of available memory again. + */ + for_each_domain ( d ) + { + if ( d->claims[node] ) + { + recall_pages -= deduct_node_claims(d, node, recall_pages); + if ( recall_pages <= 0 ) + break; + } + } + + /* Ensure that outstanding claims are in line with available memory. */ + recall_pages = outstanding_claims - total_avail_pages; + if ( recall_pages > 0 ) + /* + * total_avail_pages slipped below outstanding_claims. + * We need to recall claimed pages until the amount of claimed + * memory is in line with the amount of available memory again. + */ + for_each_domain ( d ) + { + if ( d->global_claims ) + { + recall_pages -= deduct_global_claims(d, recall_pages); + if ( recall_pages <= 0 ) + break; + } + } + } + return count; } -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 15 17:59:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 17:59:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282833.1565262 (Exim 4.92) (envelope-from ) id 1wD4Wc-0004tY-Dn; Wed, 15 Apr 2026 17:59:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1282833.1565262; Wed, 15 Apr 2026 17:59:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wD4Wc-0004tR-9g; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="iO2MMPZnQIZUJ200" Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-c1860d/1776275980-F5358497-608B4827/0/0 X-purgate-type: clean X-purgate-size: 4493 --iO2MMPZnQIZUJ200 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 15 Apr 2026 19:59:34 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Anthony PERARD Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?utf-8?B?TW9ubsOp?= Subject: Re: [PATCH test-artifacts v3 03/13] Add debian rootfs artifact On Wed, Apr 15, 2026 at 11:50:38AM +0000, Anthony PERARD wrote: > I'm commenting on changes I found in the branch used by the pipeline > linked in the cover leter, since there's no copy on the mailing list of > the patch :-( (overzealous spam filter). >=20 > > diff --git a/scripts/debian-rootfs.sh b/scripts/debian-rootfs.sh > > new file mode 100755 > > index 000000000000..7cb8a96e39c0 > > --- /dev/null > > +++ b/scripts/debian-rootfs.sh > ... > > +PKGS=3D( > > + # System > > + bridge-utils > > + dropbear > > + udev > > + systemd-sysv > > + iproute2 > > + inetutils-ping > > + util-linux > > + cpio >=20 > Is `cpio` going to be used in dom0? The alpine rootfs don't have it. Alpine does have it, via busybox. That said, I don't see it used in any current test. > > +# don't need persistent logging, avoid journal flush service > > +rmdir var/log/journal >=20 > I think this would better be done with: >=20 > cat >> /etc/systemd/journald.conf.d/storage.conf < [Journal] > Storage=3Dvolatile > EOF >=20 > because I think systemd intend to change the behavior in future release, > and we are more explicit with a config file. +1=20 > > +# Create rootfs > > +cd / > > +{ > > + PATHS=3D"bin etc home init lib lib64 mnt opt root sbin srv tmp usr= var" > > + find $PATHS -print0 > > + echo -ne "dev\0proc\0run\0sys\0" > > +} | cpio -0 -H newc -o | gzip > "${COPYDIR}/rootfs.cpio.gz" >=20 > You should add "-R0:0" to the `cpio` command, like we do for the alpine > rootfs. Hm, I'm not sure if that's a good idea. There are a few intentionally non-root files in Debian. Right now that is: -rw-r----- 1 root 42 496 Apr 1 01:08 etc/gshadow -rw-r----- 1 root 42 564 Apr 1 01:08 etc/shadow -rw-r----- 1 root 42 444 Apr 1 01:08 etc/gshadow- -rw-r----- 1 root 42 565 Apr 1 01:08 etc/shadow- -rwxr-sr-x 1 root 42 31256 Apr 19 2025 usr/bin/expiry -rwxr-sr-x 1 root 42 113848 Apr 19 2025 usr/bin/chage -rwsr-xr-- 1 root printadm 51272 Mar 8 2025 usr/lib/dbus-1.0/dbu= s-daemon-launch-helper -rwxr-sr-x 1 root 42 43256 Jun 29 2025 usr/sbin/unix_chkpwd drwxr-xr-x 2 systemd- systemd- 0 Apr 1 01:08 var/lib/systemd/netw= ork drwxr-xr-x 2 42 root 0 Apr 1 01:07 var/lib/apt/lists/au= xfiles drwx------ 2 42 root 0 Apr 1 01:07 var/lib/apt/lists/pa= rtial drwxrwsr-x 2 root mem 0 Sep 8 2025 var/mail -rw-rw-r-- 1 root 43 0 Sep 8 2025 var/log/wtmp -rw-rw-r-- 1 root 43 0 Sep 8 2025 var/log/lastlog -rw-rw---- 1 root 43 0 Sep 8 2025 var/log/btmp -rw-r----- 1 root adm 31508 Apr 1 01:08 var/log/apt/term.log drwx------ 2 42 root 0 Apr 1 01:08 var/cache/apt/archiv= es/partial While it _might_ not explode right now if we reset it to root, it may cause issues in the future (for example APT likes to run downloads as unprivileged user, with write access only to /var/lib/apt/lists/partial). --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --iO2MMPZnQIZUJ200 Content-Type: application/pgp-signature; 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Thu, 16 Apr 2026 00:39:02 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id B2D6443EE4; Wed, 15 Apr 2026 22:39:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 913CFC19424; Wed, 15 Apr 2026 22:39:00 +0000 (UTC) Received: from [10.30.226.235] (localhost [IPv6:::1]) by aws-us-west-2-korg-oddjob-rhel9-1.codeaurora.org (Postfix) with ESMTP id 02E1F380A963; Wed, 15 Apr 2026 22:38:31 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Subject:From:In-Reply-To:References:Date:To:Cc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776292740; bh=u4aKVvdutaNNPEDn+NYqz5QpfufNxXnKjBN8Ribs3ZQ=; h=Subject:From:In-Reply-To:References:Date:To:Cc:From; b=IT48Gtjyce80EYKaU8/WL2Tpivb8lzW34m5HhRTrKjRR2+v327S0Kil1B7g/V9a7x vuK1vNkL1Rzxgpg1vJldi5e2aAtfFaplU2pSEup/Z62cbLQcxz6hkkHzpxCiJh9cvT B4BZV0ouNttUSlBHmKiSxa2IUE1Sy/22rxiQDoUeV1fQ9QoFBr/yx06POw8vhWL8qu U8D/MX5fgodYbLjMSWOiMYU9Xp1XrdEL2ik0Bke8OGZ/usse/zBsh1bXsyfJaJ1Xo5 IlmcdwzDTc/r0oUmAnv4FihOlHflZJTSnobqO8Ecfh7ERqXWoHAW25SM0OUXoQzcmr MpA4467VzqfoA== Subject: Re: [GIT PULL] xen: branch for v7.1-rc1 From: pr-tracker-bot@kernel.org In-Reply-To: <20260412062202.627248-1-jgross@suse.com> References: <20260412062202.627248-1-jgross@suse.com> X-PR-Tracked-List-Id: Xen developer discussion X-PR-Tracked-Message-Id: <20260412062202.627248-1-jgross@suse.com> X-PR-Tracked-Remote: git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-7.1-rc1-tag X-PR-Tracked-Commit-Id: 3f100dd61ad4ee7c1fb6a44775a928dcdba7515b X-PR-Merge-Tree: torvalds/linux.git X-PR-Merge-Refname: refs/heads/master X-PR-Merge-Commit-Id: 83964553e8a94217edf961994ea0ca722d297447 Message-Id: <177629270956.2482053.15639149570997116080.pr-tracker-bot@kernel.org> Date: Wed, 15 Apr 2026 22:38:29 +0000 To: Juergen Gross Cc: torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, sstabellini@kernel.org X-purgate-ID: tlsNG-bad1c0/1776292742-54B58152-9B4BF6EB/0/0 X-purgate-type: clean X-purgate-size: 362 The pull request you sent on Sun, 12 Apr 2026 08:22:02 +0200: > git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-7.1-rc1-tag has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/83964553e8a94217edf961994ea0ca722d297447 Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html From xen-devel-bounces@lists.xenproject.org Wed Apr 15 23:27:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 15 Apr 2026 23:27:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1282922.1565279 (Exim 4.92) (envelope-from ) id 1wD9e9-0003ZU-GK; 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Or is using dma_buf_pin() unsafe if one does not know the exporter? For context, Xen grant tables do not support revocation. One can ask the guest to unmap the grants, but if the guest doesn't obey the only recourse is to ungracefully kill it. They also do not support page faults, so the pages must be pinned. Right now, grant tables don't support PCI BAR mappings, but that's fixable. How badly is this going to break with dGPU VRAM, if at all? I know that AMDGPU has a fallback when the BAR isn't mappable. What about other drivers? Supporting page faults the way KVM does is going to be extremely hard, so pinned mappings and DMA transfers are vastly preferable. --=20 Sincerely, Demi Marie Obenour (she/her/hers) --------------Ta5juJgfI0DZ27VwkVPMBljQ Content-Type: application/pgp-keys; name="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Disposition: attachment; filename="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Description: OpenPGP public key Content-Transfer-Encoding: quoted-printable -----BEGIN PGP PUBLIC KEY BLOCK----- xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49y B+l2nipdaq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYf bWpr/si88QKgyGSVZ7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/ UorR+FaSuVwT7rqzGrTlscnTDlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7M MPCJwI8JpPlBedRpe9tfVyfu3euTPLPxwcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9H zx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR6h3nBc3eyuZ+q62HS1pJ5EvU T1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl5FMWo8TCniHynNXs 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WXMO5iFc62D0zkaFOiN06kstBj4BEeo2X0iOYBaX9Jgud50K/jFPqTcZlMI7Xtv/vJ+C2eZ1UH1 Gy4oh8w9J4vWK+OFkOiVamOTlLxqnED0Ivd4hDpL4vpqQ6QgrfAVUjzxd X-Received: by 2002:a05:6a00:3924:b0:82c:77cd:50e8 with SMTP id d2e1a72fcca58-82f0c30f593mr23470678b3a.27.1776309999733; Wed, 15 Apr 2026 20:26:39 -0700 (PDT) X-Received: by 2002:a05:6a00:3924:b0:82c:77cd:50e8 with SMTP id d2e1a72fcca58-82f0c30f593mr23470629b3a.27.1776309999089; Wed, 15 Apr 2026 20:26:39 -0700 (PDT) Message-ID: <555b2695-1feb-482b-aec2-d6f3f2b2ef0e@oss.qualcomm.com> Date: Thu, 16 Apr 2026 08:56:24 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 3/3] of: Respect #{iommu,msi}-cells in maps To: Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Saravana Kannan , Richard Zhu , Lucas Stach , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Prakash Gupta , Vikash Garodia Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Charan Teja Kalla References: <20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com> <20260408-parse_iommu_cells-v13-3-fa921e92661b@oss.qualcomm.com> Content-Language: en-US From: Vijayanand Jitta In-Reply-To: <20260408-parse_iommu_cells-v13-3-fa921e92661b@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 6O7hIPU-KsNlEwkCnCKDetfjLj9HUHBU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE2MDAyOSBTYWx0ZWRfX1dbmOrPr6IHL xhT7bbt8Wy+vx7CLhftFT6xSqiHtwqsfjL/h0paqvJKvmXWH1Wi6B5YBNpgFaCXVt6vMQjW1JXI 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definitions=2026-04-16_01,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604160029 X-purgate-ID: tlsNG-d62444/1776310003-B6C7CFF4-926DCFCE/0/0 X-purgate-type: clean X-purgate-size: 12762 On 4/8/2026 3:33 PM, Vijayanand Jitta wrote: > From: Robin Murphy > > So far our parsing of {iommu,msi}-map properties has always blindly > assumed that the output specifiers will always have exactly 1 cell. > This typically does happen to be the case, but is not actually enforced > (and the PCI msi-map binding even explicitly states support for 0 or 1 > cells) - as a result we've now ended up with dodgy DTs out in the field > which depend on this behaviour to map a 1-cell specifier for a 2-cell > provider, despite that being bogus per the bindings themselves. > > Since there is some potential use in being able to map at least single > input IDs to multi-cell output specifiers (and properly support 0-cell > outputs as well), add support for properly parsing and using the target > nodes' #cells values, albeit with the unfortunate complication of still > having to work around expectations of the old behaviour too. > > Since there are multi-cell output specifiers, the callers of of_map_id() > may need to get the exact cell output value for further processing. > Update of_map_id() to set args_count in the output to reflect the actual > number of output specifier cells. > > Signed-off-by: Robin Murphy > Signed-off-by: Charan Teja Kalla > Signed-off-by: Vijayanand Jitta > --- > drivers/of/base.c | 157 +++++++++++++++++++++++++++++++++++++++++------------ > include/linux/of.h | 6 +- > 2 files changed, 125 insertions(+), 38 deletions(-) > > diff --git a/drivers/of/base.c b/drivers/of/base.c > index b3d002015192..2554e4f1a181 100644 > --- a/drivers/of/base.c > +++ b/drivers/of/base.c > @@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu) > return cache_level; > } > > +/* > + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while > + * specifying only 1 cell. Fortunately they all consist of value '1' > + * as the 2nd cell entry with the same target, so check for that pattern. > + * > + * Example: > + * IOMMU node: > + * #iommu-cells = <2>; > + * > + * Device node: > + * iommu-map = <0x0000 &smmu 0x0000 0x1>, > + * <0x0100 &smmu 0x0100 0x1>; > + */ > +static bool of_check_bad_map(const __be32 *map, int len) > +{ > + __be32 phandle = map[1]; > + > + if (len % 4) > + return false; > + for (int i = 0; i < len; i += 4) { > + if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1)) > + return false; > + } > + return true; > +} > + > /** > * of_map_id - Translate an ID through a downstream mapping. > * @np: root complex device node. > * @id: device ID to map. > * @map_name: property name of the map to use. > + * @cells_name: property name of target specifier cells. > * @map_mask_name: optional property name of the mask to use. > * @filter_np: optional device node to filter matches by, or NULL to match any. > * If non-NULL, only map entries targeting this node will be matched. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] will contain the translated ID. If a map entry was > - * matched, @arg->np will be set to the target node with a reference > - * held that the caller must release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * as defined by @cells_name in the target node, and > + * @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np will be set > + * to the target node with a reference held that the caller must release > + * with of_node_put(). > * > * Given a device ID, look up the appropriate implementation-defined > * platform ID and/or the target device which receives transactions on that > @@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu) > * Return: 0 on success or a standard error code on failure. > */ > int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, struct of_phandle_args *arg) > { > u32 map_mask, masked_id; > - int map_len; > + int map_bytes, map_len, offset = 0; > + bool bad_map = false; > const __be32 *map = NULL; > > if (!np || !map_name || !arg) > return -EINVAL; > > - map = of_get_property(np, map_name, &map_len); > + map = of_get_property(np, map_name, &map_bytes); > if (!map) { > if (filter_np) > return -ENODEV; > @@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id, > return 0; > } > > - if (!map_len || map_len % (4 * sizeof(*map))) { > - pr_err("%pOF: Error: Bad %s length: %d\n", np, > - map_name, map_len); > - return -EINVAL; > - } > + if (map_bytes % sizeof(*map)) > + goto err_map_len; > + map_len = map_bytes / sizeof(*map); > > /* The default is to select all bits. */ > map_mask = 0xffffffff; > @@ -2153,39 +2183,84 @@ int of_map_id(const struct device_node *np, u32 id, > of_property_read_u32(np, map_mask_name, &map_mask); > > masked_id = map_mask & id; > - for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { > + > + while (offset < map_len) { > struct device_node *phandle_node; > - u32 id_base = be32_to_cpup(map + 0); > - u32 phandle = be32_to_cpup(map + 1); > - u32 out_base = be32_to_cpup(map + 2); > - u32 id_len = be32_to_cpup(map + 3); > + u32 id_base, phandle, id_len, id_off, cells = 0; > + const __be32 *out_base; > + > + if (map_len - offset < 2) > + goto err_map_len; > + > + id_base = be32_to_cpup(map + offset); > > if (id_base & ~map_mask) { > - pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", > - np, map_name, map_name, > - map_mask, id_base); > + pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n", > + np, map_name, map_mask_name, map_mask, id_base); > return -EFAULT; > } > > - if (masked_id < id_base || masked_id >= id_base + id_len) > - continue; > - > + phandle = be32_to_cpup(map + offset + 1); > phandle_node = of_find_node_by_phandle(phandle); > if (!phandle_node) > return -ENODEV; > > + if (bad_map) { > + cells = 1; > + } else if (of_property_read_u32(phandle_node, cells_name, &cells)) { > + pr_err("%pOF: missing %s property\n", phandle_node, cells_name); > + of_node_put(phandle_node); > + return -EINVAL; > + } > + > + if (map_len - offset < 3 + cells) { > + of_node_put(phandle_node); > + goto err_map_len; > + } > + > + if (offset == 0 && cells == 2) { > + bad_map = of_check_bad_map(map, map_len); > + if (bad_map) { > + pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n", > + np, map_name, cells_name); > + cells = 1; > + } > + } > + > + out_base = map + offset + 2; > + offset += 3 + cells; > + > + id_len = be32_to_cpup(map + offset - 1); > + if (id_len > 1 && cells > 1) { > + /* > + * With 1 output cell we reasonably assume its value > + * has a linear relationship to the input; with more, > + * we'd need help from the provider to know what to do. > + */ > + pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n", > + np, map_name, id_len, cells); > + of_node_put(phandle_node); > + return -EINVAL; > + } > + id_off = masked_id - id_base; > + if (masked_id < id_base || id_off >= id_len) { > + of_node_put(phandle_node); > + continue; > + } > + > if (filter_np && filter_np != phandle_node) { > of_node_put(phandle_node); > continue; > } > > arg->np = phandle_node; > - arg->args[0] = masked_id - id_base + out_base; > - arg->args_count = 1; > + for (int i = 0; i < cells; i++) > + arg->args[i] = id_off + be32_to_cpu(out_base[i]); > + arg->args_count = cells; > > pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", > - np, map_name, map_mask, id_base, out_base, > - id_len, id, masked_id - id_base + out_base); > + np, map_name, map_mask, id_base, be32_to_cpup(out_base), > + id_len, id, id_off + be32_to_cpup(out_base)); > return 0; > } > > @@ -2196,6 +2271,10 @@ int of_map_id(const struct device_node *np, u32 id, > arg->args[0] = id; > arg->args_count = 1; > return 0; > + > +err_map_len: > + pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes); > + return -EINVAL; > } > EXPORT_SYMBOL_GPL(of_map_id); > > @@ -2205,18 +2284,21 @@ EXPORT_SYMBOL_GPL(of_map_id); > * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform > * stream/device ID) used as the lookup key in the iommu-map table. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] contains the translated ID. If a map entry was matched, > - * @arg->np holds a reference to the target node that the caller must > - * release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * and @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np holds a > + * reference to the target node that the caller must release with > + * of_node_put(). > * > - * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". > + * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells", > + * and "iommu-map-mask". > * > * Return: 0 on success or a standard error code on failure. > */ > int of_map_iommu_id(const struct device_node *np, u32 id, > struct of_phandle_args *arg) > { > - return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); > + return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg); > } > EXPORT_SYMBOL_GPL(of_map_iommu_id); > > @@ -2229,17 +2311,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); > * to match any. If non-NULL, only map entries targeting this node will > * be matched. > * @arg: pointer to a &struct of_phandle_args for the result. On success, > - * @arg->args[0] contains the translated ID. If a map entry was matched, > - * @arg->np holds a reference to the target node that the caller must > - * release with of_node_put(). > + * @arg->args_count will be set to the number of output specifier cells > + * and @arg->args[0..args_count-1] will contain the translated output > + * specifier values. If a map entry was matched, @arg->np holds a > + * reference to the target node that the caller must release with > + * of_node_put(). > * > - * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". > + * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells", > + * and "msi-map-mask". > * > * Return: 0 on success or a standard error code on failure. > */ > int of_map_msi_id(const struct device_node *np, u32 id, > const struct device_node *filter_np, struct of_phandle_args *arg) > { > - return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); > + return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg); > } > EXPORT_SYMBOL_GPL(of_map_msi_id); > diff --git a/include/linux/of.h b/include/linux/of.h > index 8548cd9eb4f1..51ac8539f2c3 100644 > --- a/include/linux/of.h > +++ b/include/linux/of.h > @@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur); > bool of_console_check(const struct device_node *dn, char *name, int index); > > int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, struct of_phandle_args *arg); > > int of_map_iommu_id(const struct device_node *np, u32 id, > @@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag > } > > static inline int of_map_id(const struct device_node *np, u32 id, > - const char *map_name, const char *map_mask_name, > + const char *map_name, const char *cells_name, > + const char *map_mask_name, > const struct device_node *filter_np, > struct of_phandle_args *arg) > { > Gentle ping. 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Smith" , "xen-devel@lists.xenproject.org" References: <7d439bb1-7381-4fa4-af79-423e8c7fafb1@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776321963-40F6FC9A-A3BCF9AC/0/0 X-purgate-type: clean X-purgate-size: 2913 On 14.04.2026 17:17, Bernhard Kaindl wrote: > Jan Beulich wrote: >>> --- a/xen/common/domain.c >>> +++ b/xen/common/domain.c > [...] >>> +int claim_memory(struct domain *d, [...] >> >> static in domctl.c? Otherwise with Penny's work to make domctl optional this >> would be unreachable code. > > Thanks, done: Moved it to domctl.c to be not compiled without MGMT_HYPERCALLS in v5/v6. > >>> + if ( uinfo->pad || uinfo->nr_claims != 1 || d->is_dying ) >>> + return -EINVAL; >> >> As already alluded to in reply to patch 03, I can't help the impression that >> usage of this sub-op with multiple entries would we quite different (i.e. it >> would be not only the implementation in Xen that changes). I'm therefore >> pretty uncertain whether taking it with this restriction is going to make >> much sense. > > I submitted this sub-op to support multiple entries with v5/v6 now. > > In v5/v6 these checks are updated to support multiple claims in the claim set. > For clarity, I renamed the .node of the individual claim entries to .target: > > The target of a claim entry can also be a selector for a global claim > or a legacy claim and the field have many bits for future use. > > This wasn't needed but I think it's clearer that the claim entry specifies a > target which is where the claim entry is aimed at, it's not just only a node. > >> + if ( claim.node == XEN_DOMCTL_CLAIM_MEMORY_NO_NODE ) >>> + claim.node = NUMA_NO_NODE; >> >> What about the incoming claim.node being NUMA_NO_NODE? Imo the range checking >> the previous patch adds to domain_set_outstanding_pages() wants to move here, >> at which point the function's new parameter could be properly nodeid_t. > > nodeid_t and NUMA_NO_NODE have (judging by the existing implementation) are not > exposed in the public API to the control domain. > > This separation is probably a good thing because it allows to change Xen internals > like nodeit_t and NUMA_NO_NODE if so desired without changing the public API. > > NUMA_NO_NODE is defined as 0xFF and nodeid_t is u8. But that is just an > implementation detail of the Hypervisor itself. If needed, we could change > the implementation like this series could do, if wanted. You spell it all out here, but then you don't draw the conclusion that I was aiming at: If someone passes in 0xff, that _should not_ be mistaken for NUMA_NO_NODE. Hence for the time being you simply need to reject 0xff if you don't want to expose "no specific node" exactly that way in the ABI. And indeed ... > The public struct xen_sysctl_numainfo and xen_sysctl_physinfo define num_nodes, > nr_nodes and max_node_id as uint32_t, for example. For type consistency, I opted > to define this public API as uint32_t as well and not expose internal types/values. ... the proper representation there would then likely be 0xffffffff. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776322167-8274EA3D-3973FB81/0/0 X-purgate-type: clean X-purgate-size: 2619 On 15.04.2026 16:51, Mykyta Poturai wrote: > On 3/30/26 15:32, Jan Beulich wrote: >> On 30.03.2026 13:59, Mykyta Poturai wrote: >>> With CPU hotplug sysctls implemented on Arm it becomes useful to have a >>> tool for calling them. >>> >>> According to the commit history it seems that putting hptool under >>> config MIGRATE was a measure to fix IA64 build. As IA64 is no longer >>> supported it can now be brought back. So build it unconditionally. >>> >>> Signed-off-by: Mykyta Poturai >>> --- >>> v6->v7: >>> * no changes >>> >>> v5->v6: >>> * don't change order in Makefile >>> >>> v4->v5: >>> * make hptool always build >>> >>> v3->v4: >>> * no changes >>> >>> v2->v3: >>> * no changes >>> >>> v1->v2: >>> * switch to configure from legacy config >>> --- >>> tools/libs/guest/Makefile.common | 2 +- >>> tools/misc/Makefile | 2 +- >>> 2 files changed, 2 insertions(+), 2 deletions(-) >>> >>> diff --git a/tools/libs/guest/Makefile.common b/tools/libs/guest/Makefile.common >>> index b928a4a246..03dfcee7fa 100644 >>> --- a/tools/libs/guest/Makefile.common >>> +++ b/tools/libs/guest/Makefile.common >>> @@ -7,6 +7,7 @@ OBJS-y += xg_private.o >>> OBJS-y += xg_domain.o >>> OBJS-y += xg_suspend.o >>> OBJS-y += xg_resume.o >>> +OBJS-y += xg_offline_page.o >>> ifeq ($(CONFIG_MIGRATE),y) >>> OBJS-y += xg_sr_common.o >>> OBJS-$(CONFIG_X86) += xg_sr_common_x86.o >>> @@ -17,7 +18,6 @@ OBJS-$(CONFIG_X86) += xg_sr_save_x86_pv.o >>> OBJS-$(CONFIG_X86) += xg_sr_save_x86_hvm.o >>> OBJS-y += xg_sr_restore.o >>> OBJS-y += xg_sr_save.o >>> -OBJS-y += xg_offline_page.o >>> else >>> OBJS-y += xg_nomigrate.o >>> endif >> >> This looks wrong to me. There are x86-specifics in that file, which shouldn't >> be built on Arm. And the name of the file also doesn't indicate any relation >> to CPU management. > > xen-hptool requires xg_offline_page as it has both CPU and memory > hotplug commands. Without building xg_offline_page it fails with > > xen-hptool: symbol lookup error: xen-hptool: undefined symbol: > xc_mark_page_offline, version libxenguest_4.22.0 > > when trying to do memory ops. > > Is it an acceptable behavior? I don't think so, no. The tool wouldn't, aiui, load at all then if built with "bindnow" enabled. > If so I guess we can build xg_offline page only on x86. We still need to, imo. But the tool still needs to be usable no matter how specifically it is built. It should avoid referencing xg_offline_page.c functions when built for non-x86. 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pr=C Message-ID: <1ab0c888-e890-490e-adad-938222f31a62@amd.com> Date: Thu, 16 Apr 2026 09:33:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-6-michal.orzel@amd.com> <519E2133-12B9-4E51-A7A5-FDBADF82159E@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <519E2133-12B9-4E51-A7A5-FDBADF82159E@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1B:EE_|DS0PR12MB8295:EE_ X-MS-Office365-Filtering-Correlation-Id: 4190388a-c2b8-4a1e-1eb1-08de9b8a70d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fytqQGQRQIUwAaucP0Y+Qwm3iJbZCM848GD13rubk9pKasYvDnuEgqCPtincLSz9lm3Fb/Y9qIIENVZpZUGEwv0iFADfVLr6VUKX7td2nzzhIAWVDVIyPWNnzmujOBKfZ9gh2YZM6GUn4JeyDw+0KCnMY55PcDKosvswomVNkLwRZv8YrD8Rofx9qlPn4dfoS47BTOdZCe8KFAJNetgdlRSydXRZtZzybsClghvFoG5vkqqkxAUXtOjQp8hOn4KRknxYYtczVqS/900FC42WNATmS8gdrOU6hnDoEUPyNe4F5KMpHqqHcp1tIoR4wegHpi08weShiDwM85pDx/x6DjumP7qvsgQ5Mi0GidpKx9CcEhyrDMZwvKPKc9KfcisghPi4/RGtpVfjiVzOKXKXR7vK+PYO3+JBllqkj0k6FoudO1A5Lds9xULymg8l9+0B X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2026 07:33:23.2323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4190388a-c2b8-4a1e-1eb1-08de9b8a70d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8295 X-purgate-ID: tlsNG-d25034/1776324809-FF149A3D-B64F0B10/0/0 X-purgate-type: clean X-purgate-size: 4122 On 15/04/2026 17:36, Luca Fancellu wrote: > Hi Michal, > >> On 15 Apr 2026, at 12:36, Michal Orzel wrote: >> >> overlay_get_nodes_info() is called before fdt_overlay_apply() to extract >> target paths from the overlay. This fails for overlays using phandle-based >> targeting (target = <&label>) because DTC compiles these as unresolved >> fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to >> return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to >> manually modify the dtbo (even for hwdom) to switch from target to >> target-phandle by manually inspecting also the host DTB. >> >> Introduce overlay_get_target_path() which directly handles the two >> targeting cases that occur before fixup resolution: >> - target-path: the string property is returned directly. >> - target = <&label>: the label is found in the overlay's __fixups__ >> node, then resolved to a path via the base DTB's __symbols__ node. >> >> Signed-off-by: Michal Orzel >> --- >> xen/common/device-tree/dt-overlay.c | 65 ++++++++++++++++++++++++++--- >> 1 file changed, 59 insertions(+), 6 deletions(-) >> >> diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c >> index d3d4669718ac..a0dee7edb7e5 100644 >> --- a/xen/common/device-tree/dt-overlay.c >> +++ b/xen/common/device-tree/dt-overlay.c >> @@ -286,6 +286,63 @@ static unsigned int overlay_node_count(const void *overlay_fdt) >> return num_overlay_nodes; >> } >> >> +/* >> + * Resolve the target path for an overlay fragment. >> + * >> + * This is called before fdt_overlay_apply(), so phandle-based targets >> + * (target = <&label>) are still unresolved (compiled as 0xffffffff by DTC). >> + * Handle the two cases that actually occur: >> + * - target-path property: the path string is used directly, >> + * - target = <&label>: the label is looked up in the overlay's __fixups__ >> + * node, then resolved to a path via the base DTB's __symbols__ node. >> + * >> + * Returns a pointer into the FDT on success, NULL on failure. >> + */ >> +static const char *overlay_get_target_path(const void *fdt, const void *fdto, >> + int fragment) >> +{ >> + const char *path, *fragment_name; >> + int fixups_off, symbols_off, property; >> + int fragment_name_len; >> + >> + /* Try target-path first (string-based targeting) */ >> + path = fdt_getprop(fdto, fragment, "target-path", NULL); >> + if ( path ) >> + return path; >> + >> + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ >> + fixups_off = fdt_path_offset(fdto, "/__fixups__"); >> + if ( fixups_off < 0 ) >> + return NULL; >> + >> + symbols_off = fdt_path_offset(fdt, "/__symbols__"); >> + if ( symbols_off < 0 ) >> + return NULL; >> + >> + fragment_name = fdt_get_name(fdto, fragment, &fragment_name_len); >> + if ( !fragment_name ) >> + return NULL; >> + >> + fdt_for_each_property_offset(property, fdto, fixups_off) >> + { >> + const char *val, *label, *p; >> + int val_len; >> + >> + val = fdt_getprop_by_offset(fdto, property, &label, &val_len); >> + if ( !val ) >> + continue; >> + >> + /* Match entries of the form "/:target:0" */ >> + for ( p = val; p < (val + val_len); p += (strlen(p) + 1) ) > > what guarantees us that p will be null terminated, if a malformed overlay > is passed this strlen can read past the string, we can use strnlen having as > upper bound a counter=val_len? decreasing counter each iteration. > > Or do you think it can never happen? In theory it can happen, in practice this is something not usually taken into account. But we can surely stay on the defensive side and do a single check right after fdt_getprop_by_offset to catch not-NUL terminated stringlist: if ( !val || !val_len || val[val_len - 1] != '\0' ) In case of no other remarks, I'd do that on commit. ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 16 07:39:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 07:39:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283015.1565324 (Exim 4.92) (envelope-from ) id 1wDHK4-0006wg-7K; Thu, 16 Apr 2026 07:39:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283015.1565324; Thu, 16 Apr 2026 07:39:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHK4-0006wZ-4l; Thu, 16 Apr 2026 07:39:36 +0000 Received: by outflank-mailman (input) for mailman id 1283015; Thu, 16 Apr 2026 07:39:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHK3-0006wT-8I for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 07:39:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDHK2-00HTU7-H9 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 09:39:34 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e09235-bab6-0a2a0a5309dd-0a2a450c94be-4 for ; Thu, 16 Apr 2026 09:39:34 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.0) (envelope-from ) id 69e09236-f40c-0a2a450c0019-d155802cb838-3 for ; Thu, 16 Apr 2026 09:39:34 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so101700285e9.2 for ; Thu, 16 Apr 2026 00:39:34 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776325174-81D53A3D-AA714608/0/0 X-purgate-type: clean X-purgate-size: 1935 On 15.04.2026 19:34, Bernhard Kaindl wrote: > Add a test framefork for unit and integration test suites testing > the Xen page allocator module xen/common/page_alloc.c in isolation. > > It enables test suites to verify the behaviour of the page allocator > in situations that are easier to create and validate in isolation, > with full control over a synthetic Xen heap state and visibility > into the allocator and domain state. > > Signed-off-by: Bernhard Kaindl Just two remarks (nits?) for now: > --- > tools/tests/Makefile | 1 + > tools/tests/alloc/.gitignore | 6 + > tools/tests/alloc/Makefile | 141 ++++++++ > tools/tests/alloc/README.rst | 31 ++ > tools/tests/alloc/check-asserts.h | 347 ++++++++++++++++++ > tools/tests/alloc/harness.h | 69 ++++ > tools/tests/alloc/hypervisor-macros.h | 101 ++++++ > tools/tests/alloc/libtest-page_alloc.h | 356 +++++++++++++++++++ > tools/tests/alloc/mock-page_list.h | 307 ++++++++++++++++ > tools/tests/alloc/page_alloc-wrapper.h | 465 +++++++++++++++++++++++++ > tools/tests/alloc/page_alloc_shim.h | 433 +++++++++++++++++++++++ > 11 files changed, 2257 insertions(+) This is a lot of new code. > create mode 100644 tools/tests/alloc/.gitignore > create mode 100644 tools/tests/alloc/Makefile > create mode 100644 tools/tests/alloc/README.rst > create mode 100644 tools/tests/alloc/check-asserts.h > create mode 100644 tools/tests/alloc/harness.h > create mode 100644 tools/tests/alloc/hypervisor-macros.h > create mode 100644 tools/tests/alloc/libtest-page_alloc.h > create mode 100644 tools/tests/alloc/mock-page_list.h > create mode 100644 tools/tests/alloc/page_alloc-wrapper.h > create mode 100644 tools/tests/alloc/page_alloc_shim.h No underscores please in new files' names when dashes will do. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776325827-82969161-BA3636A7/0/0 X-purgate-type: clean X-purgate-size: 1738 On 10.04.2026 19:41, Andrew Cooper wrote: > On 10/04/2026 4:45 pm, Oleksii Kurochko wrote: >> diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c >> index 7efa76fdbcb1..80f0e9ddae6a 100644 >> --- a/xen/arch/riscv/time.c >> +++ b/xen/arch/riscv/time.c >> @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) >> panic("%s: ACPI isn't supported\n", __func__); >> >> boot_clock_cycles = get_cycles(); >> + >> + /* set_xen_timer must have been set by sbi_init() already */ >> + ASSERT(set_xen_timer); >> + >> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >> + { >> + set_xen_timer = sstc_set_xen_timer; >> + >> + /* >> + * A VS-timer interrupt becomes pending whenever the value of >> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >> + * ULONG_MAX. >> + */ >> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >> +#ifdef CONFIG_RISCV_32 >> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >> +#endif > > You've got this pattern twice in this patch alone, and these aren't the > only CSRs which are formed of pairs to get a 64bit value in 32bit mode. > > Sadly, the numbering isn't consistent for the high constant, but we can > let the compiler do most of the hard work for us. > > #ifdef CONFIG_RISCV_32 > # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) > #else > # define __csr_write32h(csr, val) (void)(csr, val) Just to mention: Since the comma is an operator here (not a lexical element separating function arguments), more parenthesization may be needed for Misra's sake. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260414103327.7420-3-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776326145-B6265FF4-04142350/0/0 X-purgate-type: clean X-purgate-size: 730 On 14.04.2026 12:33, Roger Pau Monne wrote: > All arches truncate the cpu_khz without taking into account the less > significant digits. Instead use DIV_ROUND_UP() when scaling from Hz to kHz > to get as more accurate kHz value. > > Signed-off-by: Roger Pau Monné > --- > While the possibly more accurate value is nice, I'm not sure it's actually > fixing any functional bug, and hence the lack of "Fixes:" tag. With, as suggested by Tu, DIV_ROUND() used instead (which then statistically indeed is an improvement in accuracy) Reviewed-by: Jan Beulich As it's only statistically, nevertheless there is a risk of (perceived) regressions, just to mention it. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260410164039.1000284-1-ruslichenko.r@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776326437-E23D8443-AB5D4AF8/0/0 X-purgate-type: clean X-purgate-size: 1001 On 10.04.2026 18:40, Ruslan Ruslichenko wrote: > From: Ruslan Ruslichenko > > During core scheduler initialization, each registered scheduler > is sanity tested in two steps: > > - it must provide required callbacks (e.g. init, do_schedule). > - if global_init callback is present, it must succeed. > > If any of the steps fail, scheduler entry is cleared in global > 'schedulers' array. > > However, in the current implementation, if verification fails during > the first step, the scheduler entry is cleared but verification > sequence is not interrupted. This lead to NULL pointer dereference > when subsequent required callbacks verified, and possible during > the second step. > > The patch fixes the crashes by adding check inside sched_test_func > macro and skipping the call to a global_init if first step did not pass. > > Signed-off-by: Ruslan Ruslichenko This likely also wants a Fixes: tag. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 08:14:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 08:14:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283066.1565361 (Exim 4.92) (envelope-from ) id 1wDHs7-00060n-QS; Thu, 16 Apr 2026 08:14:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283066.1565361; Thu, 16 Apr 2026 08:14:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHs7-00060g-MM; Thu, 16 Apr 2026 08:14:47 +0000 Received: by outflank-mailman (input) for mailman id 1283066; Thu, 16 Apr 2026 08:14:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHs6-00060a-O5 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 08:14:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDHs5-004zU6-Eb for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 10:14:45 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e09a70-bab6-0a2a0a5309dd-0a2a4507d11c-26 for ; Thu, 16 Apr 2026 10:14:45 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e09a75-229c-0a2a45070019-d1558031c0eb-3 for ; Thu, 16 Apr 2026 10:14:45 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488a9033b2cso92682475e9.2 for ; Thu, 16 Apr 2026 01:14:45 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Thu, 16 Apr 2026 01:14:44 -0700 (PDT) Message-ID: <3f832c12-5a02-418d-b420-23ed3cf798db@suse.com> Date: Thu, 16 Apr 2026 10:14:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hypfs: remove unreachable statement in the 'hypfs_get_entry_rel()' To: Dmytro Prokopchuk1 , Juergen Gross Cc: "xen-devel@lists.xenproject.org" References: <341811ced2943fb79d0235c27781c564c7bdaf02.1775749146.git.dmytro_prokopchuk1@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <341811ced2943fb79d0235c27781c564c7bdaf02.1775749146.git.dmytro_prokopchuk1@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776327285-AE573C48-5BD032FD/0/0 X-purgate-type: clean X-purgate-size: 631 On 09.04.2026 17:55, Dmytro Prokopchuk1 wrote: > --- a/xen/common/hypfs.c > +++ b/xen/common/hypfs.c > @@ -347,8 +347,6 @@ static struct hypfs_entry *hypfs_get_entry_rel(struct hypfs_entry_dir *dir, > path = end + 1; > dir = container_of(entry, struct hypfs_entry_dir, e); > } > - > - return ERR_PTR(-ENOENT); > } How certain are we that no supported compiler in any mode of compilation might issue a diagnostic for the then missing "return" at the end of a function returning non-void? Imo we might be better off adding ASSERT_UNREACHABLE() and keeping the "return" that's there. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 08:21:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 08:21:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283076.1565369 (Exim 4.92) (envelope-from ) id 1wDHyR-0007ni-I1; Thu, 16 Apr 2026 08:21:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283076.1565369; Thu, 16 Apr 2026 08:21:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHyR-0007nb-EL; Thu, 16 Apr 2026 08:21:19 +0000 Received: by outflank-mailman (input) for mailman id 1283076; Thu, 16 Apr 2026 08:21:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDHyQ-0007nT-OQ for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 08:21:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDHyQ-008q4O-1e for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 10:21:18 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e09bf5-5cb7-0a2a0a5109dd-0a2a450cbb94-14 for ; Thu, 16 Apr 2026 10:21:17 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e09bfd-62f1-0a2a450c0019-d1558034d048-3 for ; Thu, 16 Apr 2026 10:21:17 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-488e1a8ac40so71944765e9.2 for ; Thu, 16 Apr 2026 01:21:17 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <815edfd0db90859a4ce270d833d9d721ff66e31c.1775814143.git.teddy.astie@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776327677-F5A00CF5-A136CAC7/0/0 X-purgate-type: clean X-purgate-size: 402 On 10.04.2026 12:09, Teddy Astie wrote: > `val` comes from `addr_to_dma_page_maddr()` which is a pagetable > paddr and doesn't leak the PTE flags in it. Did you read the comment ahead of the function, in particular the part about the caller passing 0 for "target"? > Rather than returning entries without any permissions, assume they > are always r/w. This wouldn't be any better. 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nfok6GtyZbB92DO23LCWQJIQ0G1lbsbdtCxjgOCANBI=; b=TC4HqGeB6Zdib09QwW0Qxpc4/df0QU2RMhJWFZp0GIOQP4LiDIDG3sZ1ck2LG3yUsDr/A7hmxo4NLwr9ZsrzRRMAAtwg/Dqn7fpQrLfxNmjHaNmTizd8PVNHG9XVHUgS30/BHbV+CqeKK1/eIZqt2UrQyUJWda1s/REJIBGe32A= From: Luca Fancellu To: "Orzel, Michal" CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info Thread-Topic: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info Thread-Index: AQHczMxJn1pwTu5+sUmN2MgYtFAQK7XgQWaAgAELlQCAAA1zAA== Date: Thu, 16 Apr 2026 08:21:55 +0000 Message-ID: <6E811F82-6F9F-4894-B2A3-03AA166E78F4@arm.com> References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-6-michal.orzel@amd.com> <519E2133-12B9-4E51-A7A5-FDBADF82159E@arm.com> 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an overlay fragment. >>> + * >>> + * This is called before fdt_overlay_apply(), so phandle-based targets >>> + * (target =3D <&label>) are still unresolved (compiled as 0xffffffff = by DTC). >>> + * Handle the two cases that actually occur: >>> + * - target-path property: the path string is used directly, >>> + * - target =3D <&label>: the label is looked up in the overlay's __f= ixups__ >>> + * node, then resolved to a path via the base DTB's __symbols__ nod= e. >>> + * >>> + * Returns a pointer into the FDT on success, NULL on failure. >>> + */ >>> +static const char *overlay_get_target_path(const void *fdt, const void= *fdto, >>> + int fragment) >>> +{ >>> + const char *path, *fragment_name; >>> + int fixups_off, symbols_off, property; >>> + int fragment_name_len; >>> + >>> + /* Try target-path first (string-based targeting) */ >>> + path =3D fdt_getprop(fdto, fragment, "target-path", NULL); >>> + if ( path ) >>> + return path; >>> + >>> + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ >>> + fixups_off =3D fdt_path_offset(fdto, "/__fixups__"); >>> + if ( fixups_off < 0 ) >>> + return NULL; >>> + >>> + symbols_off =3D fdt_path_offset(fdt, "/__symbols__"); >>> + if ( symbols_off < 0 ) >>> + return NULL; >>> + >>> + fragment_name =3D fdt_get_name(fdto, fragment, &fragment_name_len)= ; >>> + if ( !fragment_name ) >>> + return NULL; >>> + >>> + fdt_for_each_property_offset(property, fdto, fixups_off) >>> + { >>> + const char *val, *label, *p; >>> + int val_len; >>> + >>> + val =3D fdt_getprop_by_offset(fdto, property, &label, &val_len= ); >>> + if ( !val ) >>> + continue; >>> + >>> + /* Match entries of the form "/:target:0" */ >>> + for ( p =3D val; p < (val + val_len); p +=3D (strlen(p) + 1) ) >>=20 >> what guarantees us that p will be null terminated, if a malformed overla= y >> is passed this strlen can read past the string, we can use strnlen havin= g as >> upper bound a counter=3Dval_len? decreasing counter each iteration. >>=20 >> Or do you think it can never happen? > In theory it can happen, in practice this is something not usually taken = into > account. But we can surely stay on the defensive side and do a single che= ck > right after fdt_getprop_by_offset to catch not-NUL terminated stringlist: > if ( !val || !val_len || val[val_len - 1] !=3D '\0' ) Ok, do we also want to print a warning in case of malformed properties inst= ead of ignoring and continue? >=20 > In case of no other remarks, I'd do that on commit. >=20 > ~Michal >=20 Cheers, Luca From xen-devel-bounces@lists.xenproject.org Thu Apr 16 08:27:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 08:27:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283106.1565396 (Exim 4.92) (envelope-from ) id 1wDI40-0000zF-Mu; Thu, 16 Apr 2026 08:27:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283106.1565396; Thu, 16 Apr 2026 08:27:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDI40-0000z8-JL; Thu, 16 Apr 2026 08:27:04 +0000 Received: by outflank-mailman (input) for mailman id 1283106; Thu, 16 Apr 2026 08:27:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDI3y-0000z2-Lr for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 08:27:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDI3x-0005GT-Fn for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 10:27:01 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e09d4b-e002-0a2a0a5209dd-0a2a450bdfbc-36 for ; Thu, 16 Apr 2026 10:27:01 +0200 Received: from [209.85.221.46] (helo=mail-wr1-f46.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e09d55-212f-0a2a450b0019-d155dd2ed1db-3 for ; Thu, 16 Apr 2026 10:27:01 +0200 Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-43cfde3c3f3so7810373f8f.3 for ; Thu, 16 Apr 2026 01:27:01 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <96829f0b-faac-4100-8c30-c93ac9459600@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776328021-0576AF3B-5A7CBCDD/0/0 X-purgate-type: clean X-purgate-size: 3293 On 16.04.2026 10:22, Mykyta Poturai wrote: > On 4/16/26 09:49, Jan Beulich wrote: >> On 15.04.2026 16:51, Mykyta Poturai wrote: >>> On 3/30/26 15:32, Jan Beulich wrote: >>>> On 30.03.2026 13:59, Mykyta Poturai wrote: >>>>> With CPU hotplug sysctls implemented on Arm it becomes useful to have a >>>>> tool for calling them. >>>>> >>>>> According to the commit history it seems that putting hptool under >>>>> config MIGRATE was a measure to fix IA64 build. As IA64 is no longer >>>>> supported it can now be brought back. So build it unconditionally. >>>>> >>>>> Signed-off-by: Mykyta Poturai >>>>> --- >>>>> v6->v7: >>>>> * no changes >>>>> >>>>> v5->v6: >>>>> * don't change order in Makefile >>>>> >>>>> v4->v5: >>>>> * make hptool always build >>>>> >>>>> v3->v4: >>>>> * no changes >>>>> >>>>> v2->v3: >>>>> * no changes >>>>> >>>>> v1->v2: >>>>> * switch to configure from legacy config >>>>> --- >>>>> tools/libs/guest/Makefile.common | 2 +- >>>>> tools/misc/Makefile | 2 +- >>>>> 2 files changed, 2 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/tools/libs/guest/Makefile.common b/tools/libs/guest/Makefile.common >>>>> index b928a4a246..03dfcee7fa 100644 >>>>> --- a/tools/libs/guest/Makefile.common >>>>> +++ b/tools/libs/guest/Makefile.common >>>>> @@ -7,6 +7,7 @@ OBJS-y += xg_private.o >>>>> OBJS-y += xg_domain.o >>>>> OBJS-y += xg_suspend.o >>>>> OBJS-y += xg_resume.o >>>>> +OBJS-y += xg_offline_page.o >>>>> ifeq ($(CONFIG_MIGRATE),y) >>>>> OBJS-y += xg_sr_common.o >>>>> OBJS-$(CONFIG_X86) += xg_sr_common_x86.o >>>>> @@ -17,7 +18,6 @@ OBJS-$(CONFIG_X86) += xg_sr_save_x86_pv.o >>>>> OBJS-$(CONFIG_X86) += xg_sr_save_x86_hvm.o >>>>> OBJS-y += xg_sr_restore.o >>>>> OBJS-y += xg_sr_save.o >>>>> -OBJS-y += xg_offline_page.o >>>>> else >>>>> OBJS-y += xg_nomigrate.o >>>>> endif >>>> >>>> This looks wrong to me. There are x86-specifics in that file, which shouldn't >>>> be built on Arm. And the name of the file also doesn't indicate any relation >>>> to CPU management. >>> >>> xen-hptool requires xg_offline_page as it has both CPU and memory >>> hotplug commands. Without building xg_offline_page it fails with >>> >>> xen-hptool: symbol lookup error: xen-hptool: undefined symbol: >>> xc_mark_page_offline, version libxenguest_4.22.0 >>> >>> when trying to do memory ops. >>> >>> Is it an acceptable behavior? >> >> I don't think so, no. The tool wouldn't, aiui, load at all then if built with >> "bindnow" enabled. >> >>> If so I guess we can build xg_offline page only on x86. >> >> We still need to, imo. But the tool still needs to be usable no matter how >> specifically it is built. It should avoid referencing xg_offline_page.c >> functions when built for non-x86. > > As I understand, the usage of arch-specific compile time checks is > heavily discouraged in tools. So I don’t think it would be approved by > tools maintainers. Do we really need to omit this file if memory ops are > already getting blocked by Xen on Arm anyway? Nothing I can answer in a way that's definitive for your purpose. As you say, the final word here is with Anthony. I've voiced my opinion. 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pr=C Message-ID: Date: Thu, 16 Apr 2026 10:36:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-6-michal.orzel@amd.com> <519E2133-12B9-4E51-A7A5-FDBADF82159E@arm.com> <1ab0c888-e890-490e-adad-938222f31a62@amd.com> <6E811F82-6F9F-4894-B2A3-03AA166E78F4@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <6E811F82-6F9F-4894-B2A3-03AA166E78F4@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|PH7PR12MB7284:EE_ X-MS-Office365-Filtering-Correlation-Id: d0b97038-3789-49e1-f76d-08de9b9352df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: i9RQCQvfIUnRLFg89tNkaAJDB88wzxga/Syl6zgZQuAVu6LO3OT3GUM9JdInS56YdzI/tuulcdy6C+VIz0wKmc1Ww1bUW4xOUYqmSqyC6PA9uBtXVTZzAJsi1YTJSTJXbmeewWOHoVsDowwWKHzw2mPaFEv9Cn2ZPlyPP3FwkNLTjZ2QSrKj/myuiHBEZZXTfJXDeAdjw21yYTftKgxN9X1pCRaFEIWXvhiqQH21Z69y36jtRjpQaY3nLVLUlglB55G+O8c2fHvILUHbjAAmpQ3PhqHWPxG+BCHp9yc6Ngap1CGP6L9A0MBT2Vd6aL6Uk8ktaOBBv4K0Y3AFe6NM7NUmF0qvawhRONstSBcNRv7YvBVPc9FF+yZD3HgEnCLvYeKYfh/XJH6qHWiY0Jb/vkoiIPJdnt/WQkNPRZtchma0i8LntrygVf0aPInabkEZ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2026 08:36:58.5228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0b97038-3789-49e1-f76d-08de9b9352df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7284 X-purgate-ID: tlsNG-ef75cf/1776328625-AD56BC48-363EA4E8/0/0 X-purgate-type: clean X-purgate-size: 3257 On 16/04/2026 10:21, Luca Fancellu wrote: >>>> >>>> diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c >>>> index d3d4669718ac..a0dee7edb7e5 100644 >>>> --- a/xen/common/device-tree/dt-overlay.c >>>> +++ b/xen/common/device-tree/dt-overlay.c >>>> @@ -286,6 +286,63 @@ static unsigned int overlay_node_count(const void *overlay_fdt) >>>> return num_overlay_nodes; >>>> } >>>> >>>> +/* >>>> + * Resolve the target path for an overlay fragment. >>>> + * >>>> + * This is called before fdt_overlay_apply(), so phandle-based targets >>>> + * (target = <&label>) are still unresolved (compiled as 0xffffffff by DTC). >>>> + * Handle the two cases that actually occur: >>>> + * - target-path property: the path string is used directly, >>>> + * - target = <&label>: the label is looked up in the overlay's __fixups__ >>>> + * node, then resolved to a path via the base DTB's __symbols__ node. >>>> + * >>>> + * Returns a pointer into the FDT on success, NULL on failure. >>>> + */ >>>> +static const char *overlay_get_target_path(const void *fdt, const void *fdto, >>>> + int fragment) >>>> +{ >>>> + const char *path, *fragment_name; >>>> + int fixups_off, symbols_off, property; >>>> + int fragment_name_len; >>>> + >>>> + /* Try target-path first (string-based targeting) */ >>>> + path = fdt_getprop(fdto, fragment, "target-path", NULL); >>>> + if ( path ) >>>> + return path; >>>> + >>>> + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ >>>> + fixups_off = fdt_path_offset(fdto, "/__fixups__"); >>>> + if ( fixups_off < 0 ) >>>> + return NULL; >>>> + >>>> + symbols_off = fdt_path_offset(fdt, "/__symbols__"); >>>> + if ( symbols_off < 0 ) >>>> + return NULL; >>>> + >>>> + fragment_name = fdt_get_name(fdto, fragment, &fragment_name_len); >>>> + if ( !fragment_name ) >>>> + return NULL; >>>> + >>>> + fdt_for_each_property_offset(property, fdto, fixups_off) >>>> + { >>>> + const char *val, *label, *p; >>>> + int val_len; >>>> + >>>> + val = fdt_getprop_by_offset(fdto, property, &label, &val_len); >>>> + if ( !val ) >>>> + continue; >>>> + >>>> + /* Match entries of the form "/:target:0" */ >>>> + for ( p = val; p < (val + val_len); p += (strlen(p) + 1) ) >>> >>> what guarantees us that p will be null terminated, if a malformed overlay >>> is passed this strlen can read past the string, we can use strnlen having as >>> upper bound a counter=val_len? decreasing counter each iteration. >>> >>> Or do you think it can never happen? >> In theory it can happen, in practice this is something not usually taken into >> account. But we can surely stay on the defensive side and do a single check >> right after fdt_getprop_by_offset to catch not-NUL terminated stringlist: >> if ( !val || !val_len || val[val_len - 1] != '\0' ) > > Ok, do we also want to print a warning in case of malformed properties instead > of ignoring and continue? That's really a matter of taste. I would not do it unless you really want to. ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 16 08:38:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 08:38:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283128.1565414 (Exim 4.92) (envelope-from ) id 1wDIF7-0003bD-Rw; Thu, 16 Apr 2026 08:38:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283128.1565414; Thu, 16 Apr 2026 08:38:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDIF7-0003b6-Oe; Thu, 16 Apr 2026 08:38:33 +0000 Received: by outflank-mailman (input) for mailman id 1283128; Thu, 16 Apr 2026 08:38:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDIF6-0003ay-PP for xen-devel@lists.xenproject.org; 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It doesn't need setting immediately. Except for > the (possible) channel put in legacy mode we don't do so during boot > either. > > Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an > all-zero message (when the passed in CPU mask has no online CPUs). Nothing > would later call msi_compose_msg() / hpet_msi_write(), and hence nothing > would later produce a well-formed message template in > hpet_events[].msi.msg. > > Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") > Reported-by: Marek Marczykowski-Górecki > Signed-off-by: Jan Beulich > Tested-by: Marek Marczykowski-Górecki Acked-by: Roger Pau Monné I think you can adjust the now redundant irq_to_desc() to use dist as Teddy noted? Thanks, Roger. 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Thu, 16 Apr 2026 01:43:16 -0700 (PDT) Message-ID: <89b32645-fd5d-4ebc-a3e3-224cdeab11c2@suse.com> Date: Thu, 16 Apr 2026 10:43:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/HPET: channel handling in hpet_broadcast_resume() To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Teddy Astie , Marek Marczykowski References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1776328997-AD364C48-CACC9A40/0/0 X-purgate-type: clean X-purgate-size: 1219 On 16.04.2026 10:38, Roger Pau Monné wrote: > On Tue, Apr 07, 2026 at 03:33:12PM +0200, Jan Beulich wrote: >> The per-channel ENABLE bit is to solely be driven by hpet_enable_channel() >> and hpet_msi_{,un}mask(). It doesn't need setting immediately. Except for >> the (possible) channel put in legacy mode we don't do so during boot >> either. >> >> Instead reset ->arch.cpu_mask, to avoid msi_compose_msg() yielding an >> all-zero message (when the passed in CPU mask has no online CPUs). Nothing >> would later call msi_compose_msg() / hpet_msi_write(), and hence nothing >> would later produce a well-formed message template in >> hpet_events[].msi.msg. >> >> Fixes: 15aa6c67486c ("amd iommu: use base platform MSI implementation") >> Reported-by: Marek Marczykowski-Górecki >> Signed-off-by: Jan Beulich >> Tested-by: Marek Marczykowski-Górecki > > Acked-by: Roger Pau Monné Thanks. > I think you can adjust the now redundant irq_to_desc() to use dist as > Teddy noted? Yes, I've already done so locally. I didn't think I would need to send a v2 just for this. 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h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=y6CN+Lr0oFqVaPOBFQnGm6DPeoettk7DJttH910jPZlsqylT+haSa534CXmj8LAyH 8RWqjaztWlzD0fj2inTc28WUCWb450FQx0Yn4MB9A/2EfjFrqceGqIqy6PkZ2VPGFp 7t0WCsDDGbUj4ms1HiYVWkO9LbU4BwxWnewUVcbne7+XoQow6Ekw6nKKIVk4dOdmRI zS7+jYXrvOEUMOoIql+RuMbaVOibtxA2ka44kJM6kFghIzorcOl8uB9nKDsJwfGkBA +xsvuFitNNibeHpc41haRZwE9h9C3buzKxvwI/JXHwZBwDxV2XBKbff3FoWyNT7vUC RsusymWYW85pQ== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=201/2]=20vtd:=20Drop=20dead=20check=20for=20permissions=20in=20lookup=5Fpage?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776330928805 Message-Id: <70023321-c799-456f-920f-af7a7344de34@vates.tech> To: "Jan Beulich" Cc: "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , xen-devel@lists.xenproject.org References: <815edfd0db90859a4ce270d833d9d721ff66e31c.1775814143.git.teddy.astie@vates.tech> <4f9e6615-b9ab-4c2e-9345-100e73eebbb3@suse.com> In-Reply-To: <4f9e6615-b9ab-4c2e-9345-100e73eebbb3@suse.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.82e43376dfb5406f84713a8671625188?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260416:md Date: Thu, 16 Apr 2026 09:15:29 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1776330931-469768B7-8E67D747/0/0 X-purgate-type: clean X-purgate-size: 1144 Le 16/04/2026 =C3=A0 10:23, Jan Beulich a =C3=A9crit=C2=A0: > On 10.04.2026 12:09, Teddy Astie wrote: >> `val` comes from `addr_to_dma_page_maddr()` which is a pagetable >> paddr and doesn't leak the PTE flags in it. > > Did you read the comment ahead of the function, in particular the part ab= out > the caller passing 0 for "target"? > Ah ok, the "full PTE contents below PADDR_BITS limit" also includes the R/W flags, but only in that case. While I'm on it, there is a corner case here where "full PTE content" is also at the same time a error condition of this function (if PTE mfn =3D=3D= 0, we have val < PAGE_SIZE; yet the mapping exists), but that's not the problem this patch is fixing. >> Rather than returning entries without any permissions, assume they >> are always r/w. > > This wouldn't be any better. > Not having any permission could confuse the caller that there are no mappings. But it depends mostly on the callers which don't exist yet. > Jan > Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 16 09:57:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 09:57:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283177.1565450 (Exim 4.92) (envelope-from ) id 1wDJTH-0007Qf-60; Thu, 16 Apr 2026 09:57:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283177.1565450; Thu, 16 Apr 2026 09:57:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDJTH-0007QY-2z; Thu, 16 Apr 2026 09:57:15 +0000 Received: by outflank-mailman (input) for mailman id 1283177; Thu, 16 Apr 2026 09:57:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDJTG-0007QS-0g for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 09:57:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDJTE-005Qct-Lj for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 11:57:12 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0b278-e002-0a2a0a5209dd-0a2a450797b0-2 for ; Thu, 16 Apr 2026 11:57:12 +0200 Received: from [209.85.221.49] (helo=mail-wr1-f49.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0b278-229c-0a2a45070019-d155dd31d8c0-3 for ; Thu, 16 Apr 2026 11:57:12 +0200 Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-43cfce3a195so4773139f8f.2 for ; Thu, 16 Apr 2026 02:57:12 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <70023321-c799-456f-920f-af7a7344de34@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1776333432-15A59C48-634A5507/0/0 X-purgate-type: clean X-purgate-size: 839 On 16.04.2026 11:15, Teddy Astie wrote: > Le 16/04/2026 à 10:23, Jan Beulich a écrit : >> On 10.04.2026 12:09, Teddy Astie wrote: >>> `val` comes from `addr_to_dma_page_maddr()` which is a pagetable >>> paddr and doesn't leak the PTE flags in it. >> >> Did you read the comment ahead of the function, in particular the part about >> the caller passing 0 for "target"? >> > > Ah ok, the "full PTE contents below PADDR_BITS limit" also includes the > R/W flags, but only in that case. > > While I'm on it, there is a corner case here where "full PTE content" is > also at the same time a error condition of this function (if PTE mfn == > 0, we have val < PAGE_SIZE; yet the mapping exists), but that's not the > problem this patch is fixing. Not PTE will have MFN == 0. On x86 at least, MFN 0 is special. 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Or is > using dma_buf_pin() unsafe if one does not know the exporter? Neither. dma_buf_pin() makes sure that the importer doesn't get any invalidation notifications because the exporter moves the backing store of the buffer around for memory management. But what is still possible is that the exporter is hot removed, in which case the importer should basically terminate it's DMA operation as soon as possible. GPU drivers usually reject pin requests to VRAM from DMA-buf importers when that isn't restricted by cgroups for example, because that can otherwise easily result in a deny of service. Amdgpu only recently started to allow pinning into VRAM to support RDMA without ODP (I think it was ODP, but could be that I mixed up the RDMA three letter code for that feature). > For context, Xen grant tables do not support revocation. One can ask > the guest to unmap the grants, but if the guest doesn't obey the only > recourse is to ungracefully kill it. They also do not support page > faults, so the pages must be pinned. Right now, grant tables don't > support PCI BAR mappings, but that's fixable. That sounds like an use case for the DMA-buf pin interface. > How badly is this going to break with dGPU VRAM, if at all? I know > that AMDGPU has a fallback when the BAR isn't mappable. What about > other drivers? Supporting page faults the way KVM does is going to > be extremely hard, so pinned mappings and DMA transfers are vastly > preferable. Well if you only want to share a fixed amount of VRAM then that is pretty much ok. But when the client VM can trigger pinning on demand without any limitation you can pretty easily have deny of service against the host. That is usually a rather bad idea. Regards, Christian. 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Short circuit the pause if possible. */ - if ( paging_mode_shadow(d) || !using_vmx() ) + if ( paging_mode_shadow(d) || !using_vmx() || !v || vmx_unrestricted_guest(v) ) { d->arch.hvm.params[index] = value; break; -- 2.52.0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 16 11:28:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 11:28:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283232.1565513 (Exim 4.92) (envelope-from ) id 1wDKtH-0003wA-Gs; Thu, 16 Apr 2026 11:28:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283232.1565513; Thu, 16 Apr 2026 11:28:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDKtH-0003w3-DK; Thu, 16 Apr 2026 11:28:11 +0000 Received: by outflank-mailman (input) for mailman id 1283232; Thu, 16 Apr 2026 11:28:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDKtF-0003vx-UW for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 11:28:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDKtF-00GUzC-BR for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 13:28:09 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0c7c6-2eae-0a2a0a5409dd-0a2a450b8dc4-20 for ; Thu, 16 Apr 2026 13:28:09 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0c7c9-212f-0a2a450b0019-d1558033f048-3 for ; Thu, 16 Apr 2026 13:28:09 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-488d2079582so73450555e9.2 for ; Thu, 16 Apr 2026 04:28:09 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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AFNElJ9QPuzU2IocFuzg/cQOr0TM+kn/nkFrsIRGTTcs5JTecT7iB9MHKj+KLxbcYB6M6CsqQ7XVMDpAlnI=@lists.xenproject.org X-Gm-Message-State: AOJu0YwxUn6OxuVJB5DMA92RNI32AWZ7x9bDvf/+Cidin+DZCYTtTc+f rEoHCQRY4HjJTcDzqR/a5HRNZcPT4A1pqZrmjZzqGglCbJx1z16t2/W2eJddVQL8Eg== X-Gm-Gg: AeBDieuqd2lWxKQUK4M/pqM/Plg6/iYEn8wT4N5Jg3fXjyrf716svCjX3lM6f5FM+3q 9yfeok6rbpc1QFR6/mI6w07HxPlmGGZ3i2j4grPPX7OAG445YxiAlCfknCVO3uiWqw6bHwKCEFT bsT+/3BE7Eb3JQaSxCRL1yFE+PHQMRhGjlGTQaU3mKZinlCDS1MP+qXZt0Cz56rYkTUA/GPQKNq PXPyOXhTYUe7uGbd7csjwYJZrfJCIfngylUVoYVs8faGihvaQDtzG9ehMmBCLH7Z+o90kU0kdJy txuftoGd0uNLkyYLVLcygP+tJFVN9owwHhNWhI2HDSFLqkBLmvVIRuuDPWxGdrdnXj7yUPJYtJB 8srr4nx8QljKcIg3CeflJyrX6KmfLNo3ARlmTM0144Ywx92NwGQYTPzo+c5DEQE3jjJZDG8ix6G Jnb0DDn7Z6xq7pILkzC53YT/9Js7XPg14VBe04Q6Fptmyhd90PcrQGkpnXfoQUG44WrKyOgQ6DW Q+jX4QZ0uWVduZeSt6ITU65bQ== X-Received: by 2002:a05:600c:a306:b0:480:20f1:7aa6 with SMTP id 5b1f17b1804b1-488d68607e8mr251217955e9.21.1776338888579; Thu, 16 Apr 2026 04:28:08 -0700 (PDT) Message-ID: Date: Thu, 16 Apr 2026 13:28:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] x86/time: use native TSC scaling factors when TSC is not scaled To: Roger Pau Monne Cc: Andrew Cooper , Teddy Astie , xen-devel@lists.xenproject.org References: <20260414103327.7420-1-roger.pau@citrix.com> <20260414103327.7420-2-roger.pau@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260414103327.7420-2-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776338889-7D165F3B-2FF5CC75/0/0 X-purgate-type: clean X-purgate-size: 3325 On 14.04.2026 12:33, Roger Pau Monne wrote: > When running HVM guest in native TSC mode avoid using the recalculated vTSC > scaling factors based on the cpu_khz value. Using the kHz based frequency > leads to the TSC scaling values possibly not being the same as the ones > used by the per CPU cpu_time->tsc_scale field, which introduces skew > between the guest and Xen's calculations of the system time. > > On a 2gHz system, where the frequency is possibly detected as 1999999999Hz > (note this is a worse-case scenario), the cpu_khz variable will be set to > 1999999kHz, and hence 999Hz cycles will be not accounted for per second. > Over a second (the time synchronization period), this leads to a skew of: > > cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns > > So far this has gone unnoticed because the time synchronization rendezvous > forces the update of the tsc_timestamp and system_time fields in the vCPU > time info area, and hence the skew only accumulates up to the rendezvous > period. Attempting to remove the rendezvous causes the skew to grow > unbounded. > > Fix by using the native TSC scaling values (as used by Xen) when the guest > TSC is not scaled. > > Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") > Signed-off-by: Roger Pau Monné > --- > I'm worried about the usage of cpu_khz beyond simple printing it for > informational purposes. Overall I think it would be safer to store the > frequency in Hz, as to avoid losing the least significant digits. > > In any case, that's a different change. I'm not quite sure - improving accuracy is of course a good thing, but will we ever be able to do any such calculations error free, when already the detected frequency isn't exactly precise? > --- a/xen/arch/x86/time.c > +++ b/xen/arch/x86/time.c > @@ -1710,17 +1710,25 @@ static void collect_time_info(const struct vcpu *v, > else > { > if ( is_hvm_domain(d) && hvm_tsc_scaling_supported ) > - { > tsc_stamp = hvm_scale_tsc(d, t->stamp.local_tsc); This is a potentially imprecise calculation. How likely is it that its result will indeed ... > - u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; > - u->tsc_shift = d->arch.vtsc_to_ns.shift; > - } > else > - { > tsc_stamp = t->stamp.local_tsc; > + > + /* > + * HVM guests using the native TSC ratio should use the same per-CPU > + * scaling factors as Xen. This ensures time keeping is always in sync > + * between Xen and the guest. > + */ > + if ( tsc_stamp == t->stamp.local_tsc ) ... exactly match t->stamp.local_tsc? Don't we possibly need a (small) error margin? (In which case of course the next question would be: How to establish such a margin?) Jan > + { > u->tsc_to_system_mul = t->tsc_scale.mul_frac; > u->tsc_shift = t->tsc_scale.shift; > } > + else > + { > + u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; > + u->tsc_shift = d->arch.vtsc_to_ns.shift; > + } > } > > u->tsc_timestamp = tsc_stamp; From xen-devel-bounces@lists.xenproject.org Thu Apr 16 11:34:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 11:34:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283247.1565522 (Exim 4.92) (envelope-from ) id 1wDKzg-0005WO-99; Thu, 16 Apr 2026 11:34:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283247.1565522; Thu, 16 Apr 2026 11:34:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDKzg-0005WH-6F; Thu, 16 Apr 2026 11:34:48 +0000 Received: by outflank-mailman (input) for mailman id 1283247; Thu, 16 Apr 2026 11:34:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDKze-0005WB-8n for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 11:34:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDKzd-009YzA-Lx for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 13:34:45 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0c951-2eae-0a2a0a5409dd-0a2a4509adcc-12 for ; Thu, 16 Apr 2026 13:34:45 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0c955-2497-0a2a45090019-d1558034dddb-3 for ; Thu, 16 Apr 2026 13:34:45 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4887f49ec5aso95174345e9.1 for ; Thu, 16 Apr 2026 04:34:45 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776339285-9377AA53-4F344BFD/0/0 X-purgate-type: clean X-purgate-size: 405 On 10.04.2026 17:45, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/riscv_encoding.h > +++ b/xen/arch/riscv/include/asm/riscv_encoding.h > @@ -396,6 +396,8 @@ > #define CSR_VSTVAL 0x243 > #define CSR_VSIP 0x244 > #define CSR_VSATP 0x280 > +#define CSR_VSTIMECMP 0x24d > +#define CSR_VSTIMECMPH 0x25d This list looks to be sorted numerically, which you now break. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776339773-91079D75-497DC4A3/0/0 X-purgate-type: clean X-purgate-size: 1873 On 10.04.2026 17:40, Oleksii Kurochko wrote: > On 4/1/26 5:05 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> Guests using the IMSIC interrupt controller require a corresponding >>> Device Tree description. Add support for generating an IMSIC node when >>> building the guest DT. >>> >>> Keep a reference to the host IMSIC DT node and reuse its compatible >>> property while constructing the guest-visible node. >> >> Again raises a migration concern. Presumably a guest would then be able >> to migrate only to other hosts with the same compatible property. > > Right, but I don't think we can do too much and it is the simplest > approach just to migrate to hosts with the same compatible property. > > If you concern is about DTS property then for IMSIC it will be always > riscv,imsics according to the RISC-V DT spec. (IIRC, the only other > option could be qemu,riscv). Actually, I can just hard code > "riscv,imsic" explicitly instead of re-using of host name. > > If your concern is that we will migrate to a host which doesn't support > IMSIC at all then we should or (a) don't migrate to such host or (b) > provide an emulation of IMSIC. And option (b) would be terrible from at > least performance point of view. That would all be only a secondary concern - in an IMSIC is needed right now, so be it. My primary concern is with inheriting the host IMSIC's properties. >>> +static int __init imsic_set_interrupt_extended_prop(struct domain *d, >>> + void *fdt) >>> +{ >>> + uint32_t len = 0, pos = 0, cpu, phandle; >> >> At least pos and cpu should be of fixed width types. > > I thought that uint32_t is fixed width type, isn't it? Oh, of course. Problem being: I meant "shouldn't". More generally, see ./CODING_STYLE. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9fd04b0f-3b04-4f1e-ac63-de0fca57d466@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776340184-2A17E3FF-EF4555FE/0/0 X-purgate-type: clean X-purgate-size: 2712 On 13.04.2026 10:43, Oleksii Kurochko wrote: > On 4/1/26 5:16 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> + res = fdt_property(fdt, "#interrupt-cells", data, len); >>> + if ( res ) >>> + return res; >> >> So host properties are again directly handed through to the guest? > > I am not sure that it can be different from what host has. > >> Shouldn't the number of interrupts (aiui that's the "number of cells" >> here) a guest gets be independent from the host it runs one? > > The #interrupt-cells property specifies how many 32-bit values (cells) > are used to encode a single interrupt specifier when referencing this > interrupt controller from another device node. > In this APLIC schema, it's fixed at const: 2, meaning every interrupt > reference requires exactly two cells — typically: > > Cell 1 — the interrupt source number (which of the riscv,num-sources > wired inputs) > Cell 2 — the interrupt type/trigger flags (e.g. edge vs. level, active > high/low) So what if #interrupt-cells is 3 in the DT Xen is handed? If Xen can cope, should that value really also be handed through to guests? >>> + regs = dt_get_property(aplic_node, "reg", &len); >>> + if ( !regs ) >>> + { >>> + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); >>> + return -FDT_ERR_XEN(ENOENT); >>> + } >>> + >>> + res = fdt_property(fdt, "reg", regs, len); >>> + if ( res ) >>> + return res; >>> + >>> + data = dt_get_property(aplic_node, "riscv,num-sources", &len); >>> + if ( !data ) >>> + { >>> + printk("%s: Can't find 'riscv,num-sources' property\n", >>> + aplic_node->full_name); >>> + return -FDT_ERR_XEN(ENOENT); >>> + } >>> + >>> + res = fdt_property(fdt, "riscv,num-sources", data, len); >>> + if ( res ) >>> + return res; >> >> Or maybe this is the number of interrupts? > > This is the total count of hardware interrupt lines wired into this > APLIC domain. > > It could be independent from the host it runs one but looking at the > possible range [1,1023] for this property if we will put for a guest > lets say 22 but new host support only 20 when we will be in a trouble > anyway. Correct. But if you had some hosts with 1024 and some with 256, how would you bring up a guest on the former to later be able to migrate it to one of the latter when guests inherit the count from the host? > It seems like it is another one thing where it will be needed to check > that new host has enough number of interrupts and then just deny > migration to such host. Yes. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776341183-CFB7DD75-76376763/0/0 X-purgate-type: clean X-purgate-size: 2345 On 13.04.2026 11:32, Oleksii Kurochko wrote: > On 4/2/26 11:00 AM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> aia_init() is going to contain all the stuff related to AIA initialization. >>> At the moment, it is just Check if SSAIA extension is available and if yes >>> set is_aia_available to true. >> >> And (future) users of aia_available() can't directly call >> riscv_isa_extension_available()? Nor can aia_available() be a convenience >> wrapper around that call? It's only ... >> >>> --- /dev/null >>> +++ b/xen/arch/riscv/aia.c >>> @@ -0,0 +1,25 @@ >>> +/* SPDX-License-Identifier: GPL-2.0-only */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +static bool __ro_after_init is_aia_available; >> >> ... a boolean, yes, but still. > > My purpose was to have a variable which represent that AIA is > initialized properly. Maybe, it makes sense to rename this variable to > is_aia_inited. I'm generally having trouble with the non-word "inited". How about "aia_usable"? Fits ... > The idea is that in future patches VGEIN will be also initialized in > aia_init() and if wasn't initialized properly then just keep > is_aia_availabe be set to false and in such case we will have that > is_aia_available != riscv_isa_extension_available(NULL, > RISCV_ISA_EXT_ssaia). ... this as well. And ... > Note that regarding VGEIN it is arguable that it should be initialized > as generally it could be that there is no VGEIN what means that h/w > assisted guest interrupt files aren't available and s/w one should be > used. But s/w guest interrupt files aren't supported. > So I mean that with the current implementation if VGEIN isn't > initialized I will tell that AIA isn't available what generally isn't > quite true. ... this. Question of course if what aia_usable (or whatever its name) being set to false means to Xen's own operation. If Xen would still work okay (without being able to create guests), perhaps the name may want to be "aia_guest_usable" or some such. I.e. as I said on a number of occasions: A variable wants to be named to accurately express its purpose, without the name growing excessively long. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4b977410-8d24-41c3-9c83-7d95637ddea3@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1776342100-07175F3B-2B6E47E3/0/0 X-purgate-type: clean X-purgate-size: 5759 On 13.04.2026 16:42, Oleksii Kurochko wrote: > On 4/2/26 12:03 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> AIA provides a hardware-accelerated mechanism for delivering external >>> interrupts to domains via "guest interrupt files" located in IMSIC. >>> A single physical hart can implement multiple such files (up to GEILEN), >>> allowing several virtual harts to receive interrupts directly from hardware >> >> Isn't use of such an optimization coming prematurely? Shouldn't this series >> focus on getting basic functionality in place? > > At the moment, we don't support only APLIC for guest interrupts as it > will require trap-and-emulation approach, so just from the start it was > decided to go with APLIC+IMSIC (IMSIC here as it only one interrupt > controller which exist and support VGEIN stuff at the momemnt) approach > and then when it will be needed back to only the case when APLIC is > supported. > > Maybe, it was better to introduce in patch series where a lauching of > domain actually happens. > > Considering that you've already made a review, I prefer then to have > this patch part of this patch series. That's okay, but then please take my remark as an indication that once again the patch description makes implications on what the reader knows (without it being written down anywhere I'm aware of). >>> @@ -14,12 +27,109 @@ bool aia_available(void) >>> return is_aia_available; >>> } >>> >>> +int __init vgein_init(unsigned int cpu) >> >> If this needs invoking once per CPU being brought up, it can't be __init. > > Yes, it is going to be called inside the secondary CPU bring-up function. > > __init sections are removed much later, after all CPUs are brought up, > so it looks like that at the moment when secondary CPUs are being > brought up, __init still exists and can be called. No. And I said so before. See XEN_SYSCTL_cpu_hotplug (and ignore it having "hotplug" in the name, but merely consider that you can take CPUs offline at runtime, and later bring them online again). >> Also - static? > > It isn't static because it will be called inside the secondary CPU > bring-up function. As it doesn't need calling from the outside for the boot CPU, it's not obvious why it would need calling from the outside for secondary ones. >>> +{ >>> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); >>> + >>> + csr_write(CSR_HGEIE, -1UL); >>> + vgein->geilen = flsl(csr_read(CSR_HGEIE)); >>> + csr_write(CSR_HGEIE, 0); >>> + if ( vgein->geilen ) >>> + vgein->geilen--; >> >> I don't understand this. The "len" in "geilen" stands for "length", I suppose, >> i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of >> bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED >> and may be zero. This number is known as GEILEN." This may or may not include >> bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is >> nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but >> that's not unambiguous. > > But they explicitly wrote that: The least-significant bits are > implemented first, apart from bit 0. So bit 0 is explicitly excluded. Fine, but not including it in anything named *LEN feels - as said - ambiguous. >>> + /* >>> + * All vCPU guest interrupt files are used and we don't support a case >>> + * when number of vCPU on 1 pCPU is bigger then geilen. >>> + */ >> >> This wants checking in vgein_init() then. CPUs (beyond the boot one) >> violating this should not be brought online. > > It'll be nice. But we can't know how many vCPUs will be ran on pCPU when > vgein_init() is executed. I don't understand: How does it matter how many vCPU-s will exist later on (and will run wherever)? >>> + ASSERT(vgein_id < vgein_bmp->geilen); >> >> What if not bit is available? By asserting, you assume the caller will not >> call here when no ID is available. > > It is just a temporary ASSERT() (as we don't support software guest > interrupt files) because in general it is fine if there is no bit > available, it will just mean that that no physical hardware guest > interrupt file is assigned to the virtual hart, and software-based > emulation (a "software file") must be used to handle guest external > interrupts. > > Will it be better to return 0 now here and just don't create a vCPU > on ... > > Yet there is no caller of this function, >> so how can one verify whether this assertion is appropriate? > > ... the caller side when an assignment is expected to be happen? Yes, you want to return errors for cases you can't handle. You wan to assert on internal state only, not on anything controlled by a caller outside of the hypervisor. >>> + bitmap_set(bmp, vgein_id, 1); >> >> __set_bit()? > > I thought that it will be fine to use for bmp, bitmap_* functions(). > __set_bit is what is called inside bitmap_set(). Sure, but why make things look complicated? We use __set_bit() and friends all over the place on bitmaps. bitmap_*() exist for the less trivial cases. >>> + spin_unlock_irqrestore(&vgein_bmp->lock, flags); >>> + >>> +#ifdef VGEIN_DEBUG >>> + printk("%s: vgein_id(%u), xen_cpu%d_bmp=%#lx\n", >>> + __func__, vgen_id, v->processor, *vgein_bmp->bmp); >> >> I can't spot a difference from the message in vgein_assign(). How is one >> to distinguish the two in a log? > > By function name which is the first argument (__func__). My general take is that in gprintk() use of __func__ may be okay, but hardly anywhere else. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 12:31:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 12:31:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283322.1565586 (Exim 4.92) (envelope-from ) id 1wDLsF-0007OI-9t; Thu, 16 Apr 2026 12:31:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283322.1565586; Thu, 16 Apr 2026 12:31:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDLsF-0007OB-6i; Thu, 16 Apr 2026 12:31:11 +0000 Received: by outflank-mailman (input) for mailman id 1283322; Thu, 16 Apr 2026 12:31:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDLsD-0007Nz-CT for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 12:31:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDLsC-005oDU-M4 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:31:08 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0d682-2eae-0a2a0a5409dd-0a2a450b9d60-40 for ; Thu, 16 Apr 2026 14:31:08 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0d68c-212f-0a2a450b0019-d1558036d4f5-3 for ; Thu, 16 Apr 2026 14:31:08 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4852a9c6309so73374805e9.0 for ; Thu, 16 Apr 2026 05:31:08 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2f555a8b-d058-41ca-80f8-ce3dc08edfbe@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1776342668-7E772F3B-9D956A63/0/0 X-purgate-type: clean X-purgate-size: 3751 On 14.04.2026 11:22, Oleksii Kurochko wrote: > On 4/2/26 1:31 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> Each vCPU interacting with the IMSIC requires state to track the >>> associated guest interrupt file and its backing context. >>> >>> Introduce a per-vCPU structure to hold IMSIC-related state, including >>> the guest interrupt file identifier and the CPU providing the backing >>> VS-file. Access to the guest file identifier is protected by a lock. >>> >>> Initialize this structure during vCPU setup and store it in arch_vcpu. >>> The initial state marks the VS-file as software-backed until it becomes >>> associated with a physical CPU. >>> >>> Add helpers to retrieve and update the guest interrupt file identifier. >> >> Yet again a functions with no callers. > > They will be called in follow-up patches. In which case please provide some minimal information on the intended use. >>> --- a/xen/arch/riscv/imsic.c >>> +++ b/xen/arch/riscv/imsic.c >>> @@ -59,6 +59,29 @@ do { \ >>> csr_clear(CSR_SIREG, v); \ >>> } while (0) >>> >>> +unsigned int vcpu_guest_file_id(const struct vcpu *v) >>> +{ >>> + struct imsic_state *imsic_state = v->arch.imsic_state; >>> + unsigned long flags; >>> + unsigned int vsfile_id; >>> + >>> + read_lock_irqsave(&imsic_state->vsfile_lock, flags); >>> + vsfile_id = imsic_state->guest_file_id; >>> + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); >> >> What purpose does this locking have? Already ... >> >>> + return vsfile_id; >> >> ... here the value can be stale, if indeed there is a chance of races. >> Did you perhaps mean to use ACCESS_ONCE() here and where the value is >> set? > > ACCESS_ONCE() isn't guarantee only compiler re-ordering (as basically it > is just volatile-related stuff inisde the macros)? > > Generally, I think that that guest_file_id is needed to be updated only > during migration of vCPU from one pCPU to another and I expect that > during this migration vCPU isn't active, so no one will want to read > imsic_state->guest_file_id. But on the other hand, there is: > bool imsic_has_interrupt(const struct vcpu *vcpu) > { > ... > /* > * The IMSIC SW-file directly injects interrupt via hvip so > * only check for interrupt when IMSIC VS-file is being used. > */ > > read_lock_irqsave(&imsic_state->vsfile_lock, flags); > if ( imsic_state->vsfile_pcpu != NR_CPUS ) > ret = !!(csr_read(CSR_HGEIP) & BIT(imsic_state->guest_file_id, > UL)); > read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); > ... > } > which I think could be called in parallel with with migration, so then > still lock are needed. None of this addresses my pointing out that the returned value will be stale by the point the caller gets to look at it. Which in turn raises said question about the use of a lock. If you read imsic_state->guest_file_id atomically (i.e. excluding tearing of reads), the value seen / used will be stale as with the lock in use. Unless of course there's yet another aspect hidden somewhere in what is not being explained. >>> @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_node *node, >>> return 0; >>> } >>> >>> +int __init vcpu_imsic_init(struct vcpu *v) >> >> __init for a function involved in setting up a vCPU? > > Yes, it will be used during creationg of a vCPU. And vCPU-s can be created post-boot, can't they? (Outside of dom0less of course, but imo you really don't want to tie each and every function to dom0less being the primary goal right now.) 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2f555a8b-d058-41ca-80f8-ce3dc08edfbe@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776342670-45B6F8B7-D94EC8C3/0/0 X-purgate-type: clean X-purgate-size: 3751 On 14.04.2026 11:22, Oleksii Kurochko wrote: > On 4/2/26 1:31 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> Each vCPU interacting with the IMSIC requires state to track the >>> associated guest interrupt file and its backing context. >>> >>> Introduce a per-vCPU structure to hold IMSIC-related state, including >>> the guest interrupt file identifier and the CPU providing the backing >>> VS-file. Access to the guest file identifier is protected by a lock. >>> >>> Initialize this structure during vCPU setup and store it in arch_vcpu. >>> The initial state marks the VS-file as software-backed until it becomes >>> associated with a physical CPU. >>> >>> Add helpers to retrieve and update the guest interrupt file identifier. >> >> Yet again a functions with no callers. > > They will be called in follow-up patches. In which case please provide some minimal information on the intended use. >>> --- a/xen/arch/riscv/imsic.c >>> +++ b/xen/arch/riscv/imsic.c >>> @@ -59,6 +59,29 @@ do { \ >>> csr_clear(CSR_SIREG, v); \ >>> } while (0) >>> >>> +unsigned int vcpu_guest_file_id(const struct vcpu *v) >>> +{ >>> + struct imsic_state *imsic_state = v->arch.imsic_state; >>> + unsigned long flags; >>> + unsigned int vsfile_id; >>> + >>> + read_lock_irqsave(&imsic_state->vsfile_lock, flags); >>> + vsfile_id = imsic_state->guest_file_id; >>> + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); >> >> What purpose does this locking have? Already ... >> >>> + return vsfile_id; >> >> ... here the value can be stale, if indeed there is a chance of races. >> Did you perhaps mean to use ACCESS_ONCE() here and where the value is >> set? > > ACCESS_ONCE() isn't guarantee only compiler re-ordering (as basically it > is just volatile-related stuff inisde the macros)? > > Generally, I think that that guest_file_id is needed to be updated only > during migration of vCPU from one pCPU to another and I expect that > during this migration vCPU isn't active, so no one will want to read > imsic_state->guest_file_id. But on the other hand, there is: > bool imsic_has_interrupt(const struct vcpu *vcpu) > { > ... > /* > * The IMSIC SW-file directly injects interrupt via hvip so > * only check for interrupt when IMSIC VS-file is being used. > */ > > read_lock_irqsave(&imsic_state->vsfile_lock, flags); > if ( imsic_state->vsfile_pcpu != NR_CPUS ) > ret = !!(csr_read(CSR_HGEIP) & BIT(imsic_state->guest_file_id, > UL)); > read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); > ... > } > which I think could be called in parallel with with migration, so then > still lock are needed. None of this addresses my pointing out that the returned value will be stale by the point the caller gets to look at it. Which in turn raises said question about the use of a lock. If you read imsic_state->guest_file_id atomically (i.e. excluding tearing of reads), the value seen / used will be stale as with the lock in use. Unless of course there's yet another aspect hidden somewhere in what is not being explained. >>> @@ -315,6 +338,25 @@ static int imsic_parse_node(const struct dt_device_node *node, >>> return 0; >>> } >>> >>> +int __init vcpu_imsic_init(struct vcpu *v) >> >> __init for a function involved in setting up a vCPU? > > Yes, it will be used during creationg of a vCPU. And vCPU-s can be created post-boot, can't they? (Outside of dom0less of course, but imo you really don't want to tie each and every function to dom0less being the primary goal right now.) Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 12:42:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 12:42:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283353.1565604 (Exim 4.92) (envelope-from ) id 1wDM3O-0001Pp-OP; Thu, 16 Apr 2026 12:42:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283353.1565604; Thu, 16 Apr 2026 12:42:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDM3O-0001Pi-Lm; Thu, 16 Apr 2026 12:42:42 +0000 Received: by outflank-mailman (input) for mailman id 1283353; Thu, 16 Apr 2026 12:42:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDM3M-0001Pc-Vi for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 12:42:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDM3L-0010mU-Sq for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:42:39 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0d930-bab6-0a2a0a5309dd-0a2a450ae2d8-38 for ; Thu, 16 Apr 2026 14:42:39 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0d93f-56b3-0a2a450a0019-d1558031b1f4-3 for ; Thu, 16 Apr 2026 14:42:39 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4888375f735so79319245e9.3 for ; Thu, 16 Apr 2026 05:42:39 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776343359-445648B7-8D279A63/0/0 X-purgate-type: clean X-purgate-size: 4284 On 14.04.2026 12:27, Oleksii Kurochko wrote: > On 4/2/26 1:58 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> @@ -47,6 +48,19 @@ struct intc_hw_operations { >>> const struct dt_device_node *intc); >>> }; >>> + >>> +struct vintc { >>> + const struct intc_info *info; >> >> Isn't this referencing a physical INTC's structure? Why would the virtual >> one's properties have to match that of the physical one? > > It is because of how vAPLIC emulation load and store is working. Thank you very much. This fully explains things, the more that of course emulation of loads and stores comes earlier in this series. Oleksii, really, please. >>> +struct vaplic { >>> + struct vintc base; >> >> How does "base" fit with the type of the field? > > The field name base is a idiom for embedding a "base class" struct as > the first member, enabling a form of inheritance. > > Any suggestion how to rename it better? vintc? >>> --- /dev/null >>> +++ b/xen/arch/riscv/vaplic.c >>> @@ -0,0 +1,74 @@ >>> +/* SPDX-License-Identifier: MIT */ >>> +/* >>> + * xen/arch/riscv/vaplic.c >>> + * >>> + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support >>> + * >>> + * Copyright (c) Microchip. >>> + * Copyright (c) Vates >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include "aplic-priv.h" >>> + >>> +static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >>> +{ >>> + int rc = 0; >>> + >>> + rc = vcpu_imsic_init(v); >>> + if ( rc ) >>> + return rc; >>> + >>> + imsic_set_guest_file_id(v, vgein_assign(v)); >> >> And vgein_assign() can't fail? (Rhetorical question - of course it can. That >> function shouldn't assert that it can fine a valid ID.) > > Technically it can't fail (except some bug of course), this function > should in general return 0 (when there aren't left h/w IDs) Which is "failure". > or something > 0 (when there are some h/w IDs). Which is "success". > ASSERT() inside it was added only > because of ... > >> But then - aren't you limiting the number of vCPU-s a host can handle by the >> number vgein IDs? > > ... At the moment, I am limiting because S/W interrutps guest files > (IDs) aren't supported. As before - return error codes when errors occur. >>> +static struct vintc * __init vaplic_alloc(void) >>> +{ >>> + struct vaplic *v = NULL; >> >> Onve again - why the initializer? In fact, ... >> >>> + v = xvzalloc(struct vaplic); >> >> ... this could be the initializer. > > Sure, I will use it as initializer. > >> >>> + if ( !v ) >>> + return NULL; >>> + >>> + return &v->base; >>> +} >> >> If you returned and ... >> >>> +int __init domain_vaplic_init(struct domain *d) >>> +{ >>> + int ret = 0; >>> + >>> + d->arch.vintc = vaplic_alloc(); >> >> ... stored struct vaplic *, the slightly odd to_vaplic() macro wouldn't >> be needed. > > vaplic_alloc() return struct vintc *, Which is what I'm putting under question. Why would a function of this name return anything else than struct vaplic *? > which is then used by to_vaplic() > to get struct vaplic *. And which is what I'm saying can be avoided. >>> + if ( !d->arch.vintc ) >>> + { >>> + ret = -ENOMEM; >>> + goto fail; >> >> Nit: goto when simply return could be used. >> >>> + } >>> + >>> + d->arch.vintc->ops = &vaplic_ops; >> >> Are other kinds of ops structures going to appear? If not, why the extra >> indirection? > > At the moment, no I don't see any other kinds of ops struct. It was just > convenient way to group them and then easier to initialize them - just > one assignment instead of addinng a separate line in domain_vaplic_init(). Maybe I wasn't as clear as I should have been: Why the indirection when it doesn't abstract anything? I.e. why the "ops" field in the first place, when everyone could access the global (until such time that abstraction becomes necessary)? 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Thu, 16 Apr 2026 05:51:32 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Mykola Kvach Date: Thu, 16 Apr 2026 15:51:19 +0300 X-Gm-Features: AQROBzCXb_sn7BntMTwyQVG-72fbLmBAK4nVwRUIbr_john-FM3-bB9YxeaMzNo Message-ID: Subject: PING: Re: [PATCH v8 00/13] Add initial Xen Suspend-to-RAM support on ARM64 To: Xen-devel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1776343894-2BF7EC48-1967113E/0/0 X-purgate-type: clean X-purgate-size: 5859 Hi all, A gentle ping on this series. It's been a couple of weeks since v8 was post= ed. Please let me know if there are any further comments or if anything else is needed from my side to move this forward. Thanks! Best regards, Mykola On Thu, Apr 2, 2026 at 1:47=E2=80=AFPM Mykola Kvach wrote: > > From: Mykola Kvach > > This is part 2 of version 8 of the ARM Xen system suspend/resume patch > series, based on earlier work by Mirela Simonovic and Mykyta Poturai. > > The first part is in mainline. > > NOTE: Most of the code is guarded by CONFIG_SYSTEM_SUSPEND, which can > currently only be selected when UNSUPPORTED is set, and thus the > functionality is neither enabled by default nor even built. > > This version is ported to Xen master and includes extensive improvements > based on reviewer feedback. The patch series restructures code to improve > robustness, maintainability, and implements system Suspend-to-RAM support > on ARM64 hardware/control domains. > > Key updates in this series: > - Introduced architecture-specific suspend/resume infrastructure > - Integrated GICv2/GICv3 suspend and resume, including memory-backed con= text > save/restore with error handling > - Added time and IRQ suspend/resume hooks, ensuring correct timer/interr= upt > state across suspend cycles > - Implemented proper PSCI SYSTEM_SUSPEND invocation and version checks > - Improved state management and recovery in error cases during suspend/r= esume > - Added support for IPMMU-VMSA/SMMUv3 context save/restore > - Added support for GICv3 eSPI registers context save/restore > - Added support for ITS registers context save/restore > --- > > TODOs: > - Enable "xl suspend" support on ARM > - Add suspend/resume CI test for ARM (QEMU if feasible) > - PCI suspend ? > --- > > Detailed changelogs can be found in each patch. > > Changes in v8: > - Rebased to latest master and refreshed the series accordingly. > - Added a new GICv3 patch to tolerate retained redistributor LPI state > across CPU_OFF/CPU_ON. > - GICv2 suspend now disables the CPU interface and distributor before > saving state. > - GICv3 suspend/resume fixes the redistributor base used for LPI state. > - ITS and SMMUv3 suspend/resume paths were tightened, with safer > restore/rollback handling and stricter fatal-error handling. > - System suspend now checks that all domains are already in > SHUTDOWN_suspend before proceeding, and renames the hardware-domain > suspend capability/helper for clearer semantics. > - Fixed alignment/cleanup issues in the low-level suspend/resume code. > > Changes in v7: > - Timer helper renamed/clarified; virtual/hyper/phys handling documented. > - GICv2 uses one context block; restore saved CTLR; panic on alloc failur= e. > - GICv3/eSPI/ITS always suspend/resume; restore LPI/eSPI; rdist timeout. > - IPMMU suspend context allocated before PCI setup. > - System suspend: control domain drives host suspend. > - Dropped v6 IRQ descriptor restore patches; use setup_irq and re-registe= r > local IRQs on resume instead. > > For earlier changelogs, please refer to the previous cover letters. > > Mirela Simonovic (6): > xen/arm: Add suspend and resume timer helpers > xen/arm: gic-v2: Implement GIC suspend/resume functions > xen/arm: Resume memory management on Xen resume > xen/arm: Save/restore context on suspend/resume > xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface) > xen/arm: Add support for system suspend triggered by hardware domain > > Mykola Kvach (6): > xen/arm: gic-v3: tolerate retained redistributor LPI state across > CPU_OFF > xen/arm: gic-v3: Implement GICv3 suspend/resume functions > xen/arm: gic-v3: add ITS suspend/resume support > xen/arm: tee: keep init_tee_secondary() for hotplug and resume > xen/arm: ffa: fix notification SRI across CPU hotplug/suspend > arm/smmu-v3: add suspend/resume handlers > > Oleksandr Tyshchenko (1): > iommu/ipmmu-vmsa: Implement suspend/resume callbacks > > xen/arch/arm/Kconfig | 2 + > xen/arch/arm/Makefile | 1 + > xen/arch/arm/arm64/head.S | 112 ++++++++ > xen/arch/arm/gic-v2.c | 132 +++++++++ > xen/arch/arm/gic-v3-its.c | 126 +++++++- > xen/arch/arm/gic-v3-lpi.c | 80 +++++- > xen/arch/arm/gic-v3.c | 349 ++++++++++++++++++++++- > xen/arch/arm/gic.c | 29 ++ > xen/arch/arm/include/asm/gic.h | 12 + > xen/arch/arm/include/asm/gic_v3_defs.h | 1 + > xen/arch/arm/include/asm/gic_v3_its.h | 24 ++ > xen/arch/arm/include/asm/mm.h | 2 + > xen/arch/arm/include/asm/psci.h | 1 + > xen/arch/arm/include/asm/suspend.h | 31 ++ > xen/arch/arm/include/asm/time.h | 5 + > xen/arch/arm/mmu/smpboot.c | 2 +- > xen/arch/arm/psci.c | 23 +- > xen/arch/arm/suspend.c | 195 +++++++++++++ > xen/arch/arm/tee/ffa_notif.c | 63 +++- > xen/arch/arm/tee/tee.c | 2 +- > xen/arch/arm/time.c | 44 ++- > xen/arch/arm/vpsci.c | 12 +- > xen/common/Kconfig | 3 + > xen/common/domain.c | 7 +- > xen/drivers/passthrough/arm/ipmmu-vmsa.c | 305 +++++++++++++++++++- > xen/drivers/passthrough/arm/smmu-v3.c | 172 ++++++++--- > xen/drivers/passthrough/arm/smmu.c | 10 + > xen/include/xen/list.h | 14 + > 28 files changed, 1670 insertions(+), 89 deletions(-) > create mode 100644 xen/arch/arm/suspend.c > > -- > 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 12:51:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 12:51:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283373.1565624 (Exim 4.92) (envelope-from ) id 1wDMCC-0003Wl-Vr; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776343906-BDE6BFF4-7F7E20B3/0/0 X-purgate-type: clean X-purgate-size: 6916 On 14.04.2026 13:29, Oleksii Kurochko wrote: > On 4/2/26 2:22 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> --- a/xen/arch/riscv/include/asm/setup.h >>> +++ b/xen/arch/riscv/include/asm/setup.h >>> @@ -5,6 +5,10 @@ >>> >>> #include >>> >>> +struct domain; >>> +struct dt_device_node; >>> +struct rangeset; >>> + >>> #define max_init_domid (0) >>> >>> void setup_mm(void); >>> @@ -13,6 +17,19 @@ void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len); >>> >>> void init_csr_masks(void); >>> >>> +/* TODO: move somewhere to common header? */ >> >> Counter question: Why ... >> >>> +/* >>> + * Retrieves the interrupts configuration from a device tree node and maps >>> + * those interrupts to the target domain. >>> + * >>> + * Returns: >>> + * < 0 error >>> + * 0 success >>> + */ >>> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >>> + bool need_mapping, >>> + struct rangeset *irq_ranges); >> >> ... is this not an inline function, when ... >> >>> --- a/xen/arch/riscv/intc.c >>> +++ b/xen/arch/riscv/intc.c >>> @@ -79,3 +79,11 @@ int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) >>> >>> return -ENOSYS; >>> } >>> + >>> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >>> + bool need_mapping, >>> + struct rangeset *irq_ranges) >>> +{ >>> + return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, >>> + irq_ranges); >>> +} >> >> ... it's merely a wrapper around an indirect function call? And then the >> function isn't used anywhere anyway. > > It is used by dom0less common code and it is a wrapper because Arm has > different implementation and Arm doesn't have > map_device_irqs_to_domain() in its virtual interrupt controller operations. But the question wasn't why this is a wrapper, but why this wrapper isn't an inline function. >>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>> + struct dt_device_node *dev, >>> + bool need_mapping, >>> + struct rangeset *irq_ranges) >>> +{ >>> + unsigned int i, nirq; >>> + int res, irq; >>> + struct dt_raw_irq rirq; >>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>> + unsigned int reg_num; >>> + >>> + nirq = dt_number_of_irq(dev); >>> + >>> + /* Give permission and map IRQs */ >>> + for ( i = 0; i < nirq; i++ ) >>> + { >>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>> + if ( res ) >>> + { >>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>> + i, dt_node_full_name(dev)); >>> + return res; >>> + } >>> + >>> + /* >>> + * Don't map IRQ that have no physical meaning >>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>> + */ >>> + if ( rirq.controller != dt_interrupt_controller ) >>> + { >>> + dt_dprintk("irq %u not connected to primary controller." >>> + "Connected to %s\n", i, >>> + dt_node_full_name(rirq.controller)); >>> + continue; >>> + } >>> + >>> + irq = platform_get_irq(dev, i); >>> + if ( irq < 0 ) >>> + { >>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>> + return irq; >>> + } >>> + >>> + res = irq_permit_access(d, irq); >>> + if ( res ) >>> + { >>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>> + irq); >> >> This time the other way around: %d please with plain int. (Again at least >> once further down.) >> >>> + return res; >>> + } >>> + >>> + reg_num = irq / APLIC_NUM_REGS; >>> + >>> + if ( is_irq_shared_among_domains(d, irq) ) >>> + { >>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>> + return -EINVAL; >>> + } >>> + >>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >> >> ... all of this leaves me with the impression that IRQ numbering isn't really >> virtualized. IRQs are merely split into groups, one group per domain (and >> maybe some unused). How are you going to fit in truly virtual IRQs? > > What do you mean by truly virtual IRQs? Ones where no aspects are represented by any piece of hardware. > I can't totally agree that the current approach isn't use virtual IRQs, > yes, they are 1:1 mapped but on the other side Xen is responsible to > give an IRQ number for guest's device and Xen is responsible that guest > isn't trying to reach IRQ which not belongs to it. In a non-virtualized environment I expect IRQs are going to be "sparse" (i.e. with perhaps large blocks of items used elsewhere). If you had proper translation of IRQ numbers, the same could be true for your guests. >>> + dt_dprintk(" - IRQ: %u\n", irq); >>> + >>> + if ( irq_ranges ) >>> + { >>> + res = rangeset_add_singleton(irq_ranges, irq); >>> + if ( res ) >>> + return res; >>> + } >> >> What is irq_ranges? > > IIUC based on Arm code irq_ranges is an optional output accumulator, the > caller allocates and passes it in when it needs to track which IRQs were > mapped (overlay use case), or passes NULL when that tracking is not needed. > > I added here as map_device_irqs_to_domain() is called from the common > code and so maybe one day someone will decide to pass irq_ranges to this > functions. At the moment, for RISC-V it is the only one user of > map_device_irqs_to_domain() and it passes NULL. Simply assert then that it's NULL? >>> @@ -34,6 +142,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >>> >>> static const struct vintc_ops vaplic_ops = { >>> .vcpu_init = vcpu_vaplic_init, >>> + .map_device_irqs_to_domain = vaplic_map_device_irqs_to_domain, >>> }; >> >> What about the inverse function, needed for domain cleanup? > > I planned to add it when it will be really needed. At the momemnt, I > don't have such use cases. I.e. if any domain needs re-starting, the entire system needs rebooting? Recall that "dom0less" is slightly misleading a name, as it only allows there to not be a Dom0. One can be there, and hence re-starting a crashed domain ought to be possible. For that, you need to correctly clean up after the crashed one. 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Using the kHz based frequency > > leads to the TSC scaling values possibly not being the same as the ones > > used by the per CPU cpu_time->tsc_scale field, which introduces skew > > between the guest and Xen's calculations of the system time. > > > > On a 2gHz system, where the frequency is possibly detected as 1999999999Hz > > (note this is a worse-case scenario), the cpu_khz variable will be set to > > 1999999kHz, and hence 999Hz cycles will be not accounted for per second. > > Over a second (the time synchronization period), this leads to a skew of: > > > > cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns > > > > So far this has gone unnoticed because the time synchronization rendezvous > > forces the update of the tsc_timestamp and system_time fields in the vCPU > > time info area, and hence the skew only accumulates up to the rendezvous > > period. Attempting to remove the rendezvous causes the skew to grow > > unbounded. > > > > Fix by using the native TSC scaling values (as used by Xen) when the guest > > TSC is not scaled. > > > > Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") > > Signed-off-by: Roger Pau Monné > > --- > > I'm worried about the usage of cpu_khz beyond simple printing it for > > informational purposes. Overall I think it would be safer to store the > > frequency in Hz, as to avoid losing the least significant digits. > > > > In any case, that's a different change. > > I'm not quite sure - improving accuracy is of course a good thing, but will > we ever be able to do any such calculations error free, when already the > detected frequency isn't exactly precise? > > > --- a/xen/arch/x86/time.c > > +++ b/xen/arch/x86/time.c > > @@ -1710,17 +1710,25 @@ static void collect_time_info(const struct vcpu *v, > > else > > { > > if ( is_hvm_domain(d) && hvm_tsc_scaling_supported ) > > - { > > tsc_stamp = hvm_scale_tsc(d, t->stamp.local_tsc); > > This is a potentially imprecise calculation. How likely is it that its result > will indeed ... > > > - u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; > > - u->tsc_shift = d->arch.vtsc_to_ns.shift; > > - } > > else > > - { > > tsc_stamp = t->stamp.local_tsc; > > + > > + /* > > + * HVM guests using the native TSC ratio should use the same per-CPU > > + * scaling factors as Xen. This ensures time keeping is always in sync > > + * between Xen and the guest. > > + */ > > + if ( tsc_stamp == t->stamp.local_tsc ) > > ... exactly match t->stamp.local_tsc? Don't we possibly need a (small) error > margin? (In which case of course the next question would be: How to establish > such a margin?) hvm_scale_tsc() has: if ( ratio == hvm_default_tsc_scaling_ratio ) return tsc; So when using no scaling the input value is the output value, and hence tsc_stamp will match exactly t->stamp.local_tsc. Thanks, Roger. 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Thu, 16 Apr 2026 05:52:22 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Mykola Kvach Date: Thu, 16 Apr 2026 15:52:10 +0300 X-Gm-Features: AQROBzDkRt956UJ9HFqIUZus6pPyZV4x_qUHalERlz9C-lnc7Gr6C1oaVR71_7I Message-ID: Subject: PING: Re: [PATCH v8 00/13] Add initial Xen Suspend-to-RAM support on ARM64 To: Xen-devel Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Jens Wiklander , Rahul Singh Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1776343944-48FD6938-1C72C8A1/0/0 X-purgate-type: clean X-purgate-size: 5859 Hi all, A gentle ping on this series. It's been a couple of weeks since v8 was post= ed. Please let me know if there are any further comments or if anything else is needed from my side to move this forward. Thanks! Best regards, Mykola On Thu, Apr 2, 2026 at 1:47=E2=80=AFPM Mykola Kvach wrote: > > From: Mykola Kvach > > This is part 2 of version 8 of the ARM Xen system suspend/resume patch > series, based on earlier work by Mirela Simonovic and Mykyta Poturai. > > The first part is in mainline. > > NOTE: Most of the code is guarded by CONFIG_SYSTEM_SUSPEND, which can > currently only be selected when UNSUPPORTED is set, and thus the > functionality is neither enabled by default nor even built. > > This version is ported to Xen master and includes extensive improvements > based on reviewer feedback. The patch series restructures code to improve > robustness, maintainability, and implements system Suspend-to-RAM support > on ARM64 hardware/control domains. > > Key updates in this series: > - Introduced architecture-specific suspend/resume infrastructure > - Integrated GICv2/GICv3 suspend and resume, including memory-backed con= text > save/restore with error handling > - Added time and IRQ suspend/resume hooks, ensuring correct timer/interr= upt > state across suspend cycles > - Implemented proper PSCI SYSTEM_SUSPEND invocation and version checks > - Improved state management and recovery in error cases during suspend/r= esume > - Added support for IPMMU-VMSA/SMMUv3 context save/restore > - Added support for GICv3 eSPI registers context save/restore > - Added support for ITS registers context save/restore > --- > > TODOs: > - Enable "xl suspend" support on ARM > - Add suspend/resume CI test for ARM (QEMU if feasible) > - PCI suspend ? > --- > > Detailed changelogs can be found in each patch. > > Changes in v8: > - Rebased to latest master and refreshed the series accordingly. > - Added a new GICv3 patch to tolerate retained redistributor LPI state > across CPU_OFF/CPU_ON. > - GICv2 suspend now disables the CPU interface and distributor before > saving state. > - GICv3 suspend/resume fixes the redistributor base used for LPI state. > - ITS and SMMUv3 suspend/resume paths were tightened, with safer > restore/rollback handling and stricter fatal-error handling. > - System suspend now checks that all domains are already in > SHUTDOWN_suspend before proceeding, and renames the hardware-domain > suspend capability/helper for clearer semantics. > - Fixed alignment/cleanup issues in the low-level suspend/resume code. > > Changes in v7: > - Timer helper renamed/clarified; virtual/hyper/phys handling documented. > - GICv2 uses one context block; restore saved CTLR; panic on alloc failur= e. > - GICv3/eSPI/ITS always suspend/resume; restore LPI/eSPI; rdist timeout. > - IPMMU suspend context allocated before PCI setup. > - System suspend: control domain drives host suspend. > - Dropped v6 IRQ descriptor restore patches; use setup_irq and re-registe= r > local IRQs on resume instead. > > For earlier changelogs, please refer to the previous cover letters. > > Mirela Simonovic (6): > xen/arm: Add suspend and resume timer helpers > xen/arm: gic-v2: Implement GIC suspend/resume functions > xen/arm: Resume memory management on Xen resume > xen/arm: Save/restore context on suspend/resume > xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface) > xen/arm: Add support for system suspend triggered by hardware domain > > Mykola Kvach (6): > xen/arm: gic-v3: tolerate retained redistributor LPI state across > CPU_OFF > xen/arm: gic-v3: Implement GICv3 suspend/resume functions > xen/arm: gic-v3: add ITS suspend/resume support > xen/arm: tee: keep init_tee_secondary() for hotplug and resume > xen/arm: ffa: fix notification SRI across CPU hotplug/suspend > arm/smmu-v3: add suspend/resume handlers > > Oleksandr Tyshchenko (1): > iommu/ipmmu-vmsa: Implement suspend/resume callbacks > > xen/arch/arm/Kconfig | 2 + > xen/arch/arm/Makefile | 1 + > xen/arch/arm/arm64/head.S | 112 ++++++++ > xen/arch/arm/gic-v2.c | 132 +++++++++ > xen/arch/arm/gic-v3-its.c | 126 +++++++- > xen/arch/arm/gic-v3-lpi.c | 80 +++++- > xen/arch/arm/gic-v3.c | 349 ++++++++++++++++++++++- > xen/arch/arm/gic.c | 29 ++ > xen/arch/arm/include/asm/gic.h | 12 + > xen/arch/arm/include/asm/gic_v3_defs.h | 1 + > xen/arch/arm/include/asm/gic_v3_its.h | 24 ++ > xen/arch/arm/include/asm/mm.h | 2 + > xen/arch/arm/include/asm/psci.h | 1 + > xen/arch/arm/include/asm/suspend.h | 31 ++ > xen/arch/arm/include/asm/time.h | 5 + > xen/arch/arm/mmu/smpboot.c | 2 +- > xen/arch/arm/psci.c | 23 +- > xen/arch/arm/suspend.c | 195 +++++++++++++ > xen/arch/arm/tee/ffa_notif.c | 63 +++- > xen/arch/arm/tee/tee.c | 2 +- > xen/arch/arm/time.c | 44 ++- > xen/arch/arm/vpsci.c | 12 +- > xen/common/Kconfig | 3 + > xen/common/domain.c | 7 +- > xen/drivers/passthrough/arm/ipmmu-vmsa.c | 305 +++++++++++++++++++- > xen/drivers/passthrough/arm/smmu-v3.c | 172 ++++++++--- > xen/drivers/passthrough/arm/smmu.c | 10 + > xen/include/xen/list.h | 14 + > 28 files changed, 1670 insertions(+), 89 deletions(-) > create mode 100644 xen/arch/arm/suspend.c > > -- > 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 12:57:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 12:57:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283415.1565651 (Exim 4.92) (envelope-from ) id 1wDMHS-0005Oe-1q; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776344231-BD66FFF4-307BC43C/0/0 X-purgate-type: clean X-purgate-size: 3685 On 16.04.2026 14:51, Roger Pau Monné wrote: > On Thu, Apr 16, 2026 at 01:28:11PM +0200, Jan Beulich wrote: >> On 14.04.2026 12:33, Roger Pau Monne wrote: >>> When running HVM guest in native TSC mode avoid using the recalculated vTSC >>> scaling factors based on the cpu_khz value. Using the kHz based frequency >>> leads to the TSC scaling values possibly not being the same as the ones >>> used by the per CPU cpu_time->tsc_scale field, which introduces skew >>> between the guest and Xen's calculations of the system time. >>> >>> On a 2gHz system, where the frequency is possibly detected as 1999999999Hz >>> (note this is a worse-case scenario), the cpu_khz variable will be set to >>> 1999999kHz, and hence 999Hz cycles will be not accounted for per second. >>> Over a second (the time synchronization period), this leads to a skew of: >>> >>> cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns >>> >>> So far this has gone unnoticed because the time synchronization rendezvous >>> forces the update of the tsc_timestamp and system_time fields in the vCPU >>> time info area, and hence the skew only accumulates up to the rendezvous >>> period. Attempting to remove the rendezvous causes the skew to grow >>> unbounded. >>> >>> Fix by using the native TSC scaling values (as used by Xen) when the guest >>> TSC is not scaled. >>> >>> Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") >>> Signed-off-by: Roger Pau Monné >>> --- >>> I'm worried about the usage of cpu_khz beyond simple printing it for >>> informational purposes. Overall I think it would be safer to store the >>> frequency in Hz, as to avoid losing the least significant digits. >>> >>> In any case, that's a different change. >> >> I'm not quite sure - improving accuracy is of course a good thing, but will >> we ever be able to do any such calculations error free, when already the >> detected frequency isn't exactly precise? >> >>> --- a/xen/arch/x86/time.c >>> +++ b/xen/arch/x86/time.c >>> @@ -1710,17 +1710,25 @@ static void collect_time_info(const struct vcpu *v, >>> else >>> { >>> if ( is_hvm_domain(d) && hvm_tsc_scaling_supported ) >>> - { >>> tsc_stamp = hvm_scale_tsc(d, t->stamp.local_tsc); >> >> This is a potentially imprecise calculation. How likely is it that its result >> will indeed ... >> >>> - u->tsc_to_system_mul = d->arch.vtsc_to_ns.mul_frac; >>> - u->tsc_shift = d->arch.vtsc_to_ns.shift; >>> - } >>> else >>> - { >>> tsc_stamp = t->stamp.local_tsc; >>> + >>> + /* >>> + * HVM guests using the native TSC ratio should use the same per-CPU >>> + * scaling factors as Xen. This ensures time keeping is always in sync >>> + * between Xen and the guest. >>> + */ >>> + if ( tsc_stamp == t->stamp.local_tsc ) >> >> ... exactly match t->stamp.local_tsc? Don't we possibly need a (small) error >> margin? (In which case of course the next question would be: How to establish >> such a margin?) > > hvm_scale_tsc() has: > > if ( ratio == hvm_default_tsc_scaling_ratio ) > return tsc; > > So when using no scaling the input value is the output value, and > hence tsc_stamp will match exactly t->stamp.local_tsc. Ouch. I did look at the function, but managed to have all my attention drawn to the asm() there. I'm sorry for the noise. As it's strictly an improvement: Reviewed-by: Jan Beulich The other, earlier remark remains applicable, though. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 13:01:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 13:01:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283428.1565659 (Exim 4.92) (envelope-from ) id 1wDMLW-0007JZ-FZ; Thu, 16 Apr 2026 13:01:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283428.1565659; Thu, 16 Apr 2026 13:01:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDMLW-0007JS-Cg; Thu, 16 Apr 2026 13:01:26 +0000 Received: by outflank-mailman (input) for mailman id 1283428; Thu, 16 Apr 2026 13:01:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDMLU-0007JM-MP for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 13:01:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDMLU-00GVtf-33 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 15:01:24 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0dda3-2eae-0a2a0a5409dd-0a2a4503e926-6 for ; Thu, 16 Apr 2026 15:01:23 +0200 Received: from [209.85.128.45] (helo=mail-wm1-f45.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0dda3-672d-0a2a45030019-d155802dc16e-3 for ; Thu, 16 Apr 2026 15:01:23 +0200 Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4838c15e3cbso75329655e9.3 for ; Thu, 16 Apr 2026 06:01:23 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776344483-A0975938-154E628A/0/0 X-purgate-type: clean X-purgate-size: 1901 On 14.04.2026 13:45, Oleksii Kurochko wrote: > On 4/2/26 3:10 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> --- a/xen/arch/riscv/aplic.c >>> +++ b/xen/arch/riscv/aplic.c >>> @@ -38,6 +38,7 @@ static struct aplic_priv aplic = { >>> >>> static struct intc_info __ro_after_init aplic_info = { >>> .hw_version = INTC_APLIC, >>> + .private = &aplic, >> >> Isn't this the host instance again? How can you ... >> >>> --- a/xen/arch/riscv/vaplic.c >>> +++ b/xen/arch/riscv/vaplic.c >>> @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >>> return 0; >>> } >>> >>> +static int cf_check vaplic_is_access(const struct vcpu *vcpu, >>> + const unsigned long addr) >>> +{ >>> + const struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>> + const struct aplic_priv *priv = vaplic->base.info->private; >>> + const paddr_t paddr_end = priv->paddr_start + priv->size; >>> + >>> + /* check if it is an APLIC access */ >>> + if ( priv->paddr_start <= addr && addr < paddr_end ) >> >> ... use that here? Or asked differently, again: Where's the virtualization, >> i.e. the abstraction away from host properties? > > With the current use case it was easier to choose such approach then > provide the full abstraction. > >> Furthermore, is it really sufficient to check just the starting address of >> an access? Shouldn't the last byte accessed also fall into the range in >> question? > > I think that it is okay, my understanding is that *paddr_end technically > is another range. Of course it is. But a multi-byte access crossing the paddr_end boundary isn't purely an APLIC one. You can reject such for simplicity, but I'm unconvinced that you can claim you will be able to correctly handle it without proper merging. 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Using the kHz based frequency > > leads to the TSC scaling values possibly not being the same as the ones > > used by the per CPU cpu_time->tsc_scale field, which introduces skew > > between the guest and Xen's calculations of the system time. > > > > On a 2gHz system, where the frequency is possibly detected as 1999999999Hz > > (note this is a worse-case scenario), the cpu_khz variable will be set to > > 1999999kHz, and hence 999Hz cycles will be not accounted for per second. > > Over a second (the time synchronization period), this leads to a skew of: > > > > cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns > > > > So far this has gone unnoticed because the time synchronization rendezvous > > forces the update of the tsc_timestamp and system_time fields in the vCPU > > time info area, and hence the skew only accumulates up to the rendezvous > > period. Attempting to remove the rendezvous causes the skew to grow > > unbounded. > > > > Fix by using the native TSC scaling values (as used by Xen) when the guest > > TSC is not scaled. > > > > Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") > > Signed-off-by: Roger Pau Monné > > --- > > I'm worried about the usage of cpu_khz beyond simple printing it for > > informational purposes. Overall I think it would be safer to store the > > frequency in Hz, as to avoid losing the least significant digits. > > > > In any case, that's a different change. > > I'm not quite sure - improving accuracy is of course a good thing, but will > we ever be able to do any such calculations error free, when already the > detected frequency isn't exactly precise? I think getting them fully accurate is not strictly required. The specific issue here was that the guest was supposedly running with the native TSC frequency, but the vCPU time info scaling factors where (slightly) different from the ones using natively by Xen, hence resulting in a time skew. When the guest runs with a different TSC frequency Xen already accounts for it properly, and hence there's no skew. However, as noted in the next patch, I don't really see the benefit of storing the frequency in kHz instead of using plain Hz. Thanks, Roger. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <76ea5954-89cd-47a4-872a-239bbc08b785@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776345562-28D73938-A21EBDAF/0/0 X-purgate-type: clean X-purgate-size: 8861 On 14.04.2026 18:04, Oleksii Kurochko wrote: > On 4/2/26 4:18 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> @@ -127,6 +137,164 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >>> return 0; >>> } >>> >>> +static void vaplic_dm_update_target(const unsigned long hart_id, uint32_t *iprio) >>> +{ >>> + *iprio &= APLIC_TARGET_IPRIO_MASK; >>> + *iprio |= (hart_id << APLIC_TARGET_HART_IDX_SHIFT); >>> +} >>> + >>> +static void vaplic_update_target(const struct imsic_config *imsic, >>> + const int guest_id, >>> + const unsigned long hart_id, uint32_t *value) >>> +{ >>> + unsigned long group_index; >>> + unsigned int hhxw = imsic->group_index_bits; >>> + unsigned int lhxw = imsic->hart_index_bits; >>> + unsigned int hhxs = imsic->group_index_shift - IMSIC_MMIO_PAGE_SHIFT * 2; >>> + unsigned long base_ppn = imsic->msi[hart_id].base_addr >> IMSIC_MMIO_PAGE_SHIFT; >>> + >>> + group_index = (base_ppn >> (hhxs + 12)) & (BIT(hhxw, UL) - 1); >> >> And there's no constant available to make this literal 12 more descriptive? > > As it was used in aplic_set_irq_affinity() - IMSIC_MMIO_PAGE_SHIFT could > be used here. > >> >>> + *value &= APLIC_TARGET_EIID_MASK; >>> + *value |= guest_id << APLIC_TARGET_GUEST_IDX_SHIFT; >>> + *value |= hart_id << APLIC_TARGET_HART_IDX_SHIFT; >>> + *value |= group_index << (lhxw + APLIC_TARGET_HART_IDX_SHIFT) ; >>> +} >> >> Both functions returning void right now, why would they need to return their >> result via indirection? > > No specific reason. Do you think it would be better just to return value > instead? I am okay to rework that. Rule of thumb is: Use return value in preference to indirection when the returned value isn't needed for some other purpose. >>> +#define CALC_REG_VALUE(base) \ >>> +{ \ >>> + uint32_t index; \ >>> + uint32_t tmp_val; \ >> >> Combine these two, or have the variables have initializers? >> >>> + index = regval_to_irqn(offset - base); \ >> >> There's no "offset" declared or passed into here, nor ... >> >>> + tmp_val = APLIC_REG_GET(priv->regs, aplic_addr) & ~auth_irq_bmp[index]; \ >> >> ... "priv", nor ... >> >>> + value &= auth_irq_bmp[index]; \ >>> + value |= tmp_val; \ >> >> ... "value". It may remain like this, but then it wants putting inside the >> sole function that uses it, and be #undef-ed at the end of the function. >> >>> +} >> >> Please wrap in do/while(0), for use sites to be required to have semicolons >> (and hence look like normal statements). Or make it a statement expression >> properly returning the calculated value. > > I will put the following inside the function + undef at the end: > > #define CALC_REG_VALUE(base) do { \ > \ Nit: Why this extra line? >>> +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, >>> + unsigned long addr, uint32_t value) >>> +{ >>> + struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>> + struct aplic_priv *priv = vaplic->base.info->private; >>> + uint32_t offset = addr & APLIC_REG_OFFSET_MASK; >> >> See ./CODING_STYLE as to uses of fixed-width types. >> >>> + unsigned long aplic_addr = addr - priv->paddr_start; >>> + const uint32_t *auth_irq_bmp = vcpu->domain->arch.vintc->private; >>> + >>> + switch ( offset ) >>> + { >>> + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: >> >> And (taking this just as example) any misaligned accesses falling in this range >> are fine? > > Do you mean something like 0x1C02 instead of 0x1C00 or 0x1C04? Yes. >>> + /* >>> + * As sourcecfg register starts from 1: >>> + * 0x0000 domaincfg >>> + * 0x0004 sourcecfg[1] >>> + * 0x0008 sourcecfg[2] >>> + * ... >>> + * 0x0FFC sourcecfg[1023] >>> + * It is necessary to calculate an interrupt number by substracting >> >> Nit: subtracting >> >>> + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. >>> + */ >>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) >>> + /* interrupt not enabled, ignore it */ >> >> Throughout the series: Please adhere to ./CODING_STYLE. >> >>> + return 0; >>> + >>> + break; >> >> And any value is okay to write? > > No, it should be in a range > [APLIC_SOURCECFG_SM_INACTIVE,APLIC_SOURCECFG_SM_LEVEL_LOW]. > > I will add the check before break: > if ( value > APLIC_SOURCECFG_SM_LEVEL_LOW ) > { > gdprintk(XENLOG_WARNING, > "value(%u) is incorrect for sourcecfg register\n", > value); > value = APLIC_SOURCECFG_SM_INACTIVE; > } And why would writing APLIC_SOURCECFG_SM_INACTIVE be any better, when that's not what the guest wanted? Simply ignore such writes, unless the spec mandates specific behavior for out-of-range avlues? >>> + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: >>> + struct vcpu *target_vcpu = NULL; >>> + >>> + /* >>> + * Look at vaplic_emulate_load() for explanation why >>> + * APLIC_GENMSI is substracted. >>> + */ >> >> There's no vaplic_emulate_load() - how can I go look there? > > It is introduced in the next patch. As before - it should be possible to review patch series strictly sequentially. Further, what if this patch gets committed, and the other gets delayed by several months? >>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) >>> + /* interrupt not enabled, ignore it */ >>> + return 0; >>> + >>> + for ( int i = 0; i < vcpu->domain->max_vcpus; i++ ) >> >> unsigned int >> >>> + { >>> + struct vcpu *v = vcpu->domain->vcpu[i]; >>> + >>> + if ( v->vcpu_id == (value >> APLIC_TARGET_HART_IDX_SHIFT) ) >>> + { >>> + target_vcpu = v; >>> + break; >>> + } >>> + } >>> + >>> + ASSERT(target_vcpu); >> >> What guarantees the pointer to be non-NULL? The incoming value can be >> arbitrary, afaict. > > I didn't understand your point. It is just checking that target_vcpu has > been found. If after for() loop the value of target_vcpu is still NULL > then something wrong in Xen. If that's true, then the assertion is fine to have. I can't help the impression though that a guest could pick a value such that you can't possibly find the target vCPU. Asserting on guest controlled input is not okay, as was said several times before. >>> + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) >>> + { >>> + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor), >>> + &value); >>> + } >>> + else >>> + vaplic_update_target(priv->imsic_cfg, >>> + vcpu_guest_file_id(target_vcpu), >>> + cpuid_to_hartid(target_vcpu->processor), >>> + &value); >> >> I'm struggling with the naming here: When DM is clear, a function with "dm" >> in the name is called. > > it means direct (delivery) mode. Maybe it is better to put dm at the end > of the function name? Or it is just better to change it to something else? Without a better understanding of what is wanted, all I can say is that calling something with "dm" in its name when the condition says it's not "dm" is confusing. >>> + default: >>> + panic("%s: unsupported register offset: %#x\n", __func__, offset); >> >> Crashing the host for the guest doing something odd? It's odd that the function >> only ever returns 0 anyway - it could simply return an error here (if the >> itention is to not ignore such writes). > > But maybe it is a legal offset and we really want to support it? Still not a reason to crash the entire host? > Even if I will return just error then a caller site will want to do > something with this error -> for example, kill domain or panic() again. > Maybe panic is to much and just domain should be crashed here: > > default: > gdprintk(XENLOG_WARNING, > "Unhandled APLIC write at offset %#x (value %#x)\n", > offset, value); > domain_crash(vcpu->domain); > return 0; > ? This would already be better. You shouldn't use gdprintk() with domain_crash() though. Please take a look at domain_crash()'s definition - you'll then see what to do, I suppose. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776345662-7DB68F3B-71A57B2E/0/0 X-purgate-type: clean X-purgate-size: 2679 On 16.04.2026 15:13, Roger Pau Monné wrote: > On Thu, Apr 16, 2026 at 01:28:11PM +0200, Jan Beulich wrote: >> On 14.04.2026 12:33, Roger Pau Monne wrote: >>> When running HVM guest in native TSC mode avoid using the recalculated vTSC >>> scaling factors based on the cpu_khz value. Using the kHz based frequency >>> leads to the TSC scaling values possibly not being the same as the ones >>> used by the per CPU cpu_time->tsc_scale field, which introduces skew >>> between the guest and Xen's calculations of the system time. >>> >>> On a 2gHz system, where the frequency is possibly detected as 1999999999Hz >>> (note this is a worse-case scenario), the cpu_khz variable will be set to >>> 1999999kHz, and hence 999Hz cycles will be not accounted for per second. >>> Over a second (the time synchronization period), this leads to a skew of: >>> >>> cycles * 1 / (Hz freq) = 999 / 1999999999 = 499,5ns >>> >>> So far this has gone unnoticed because the time synchronization rendezvous >>> forces the update of the tsc_timestamp and system_time fields in the vCPU >>> time info area, and hence the skew only accumulates up to the rendezvous >>> period. Attempting to remove the rendezvous causes the skew to grow >>> unbounded. >>> >>> Fix by using the native TSC scaling values (as used by Xen) when the guest >>> TSC is not scaled. >>> >>> Fixes: eab8a90be723 ("x86/time: scale host TSC in pvclock properly") >>> Signed-off-by: Roger Pau Monné >>> --- >>> I'm worried about the usage of cpu_khz beyond simple printing it for >>> informational purposes. Overall I think it would be safer to store the >>> frequency in Hz, as to avoid losing the least significant digits. >>> >>> In any case, that's a different change. >> >> I'm not quite sure - improving accuracy is of course a good thing, but will >> we ever be able to do any such calculations error free, when already the >> detected frequency isn't exactly precise? > > I think getting them fully accurate is not strictly required. The > specific issue here was that the guest was supposedly running with the > native TSC frequency, but the vCPU time info scaling factors where > (slightly) different from the ones using natively by Xen, hence resulting in a > time skew. > > When the guest runs with a different TSC frequency Xen already > accounts for it properly, and hence there's no skew. As "properly" isn't "accurate", I expect there'll still be some skew. > However, as noted in the next patch, I don't really see the benefit of > storing the frequency in kHz instead of using plain Hz. That would reduce the error, yes. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6f4b3a0b-8c13-4c54-afa1-2893aa967254@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776345781-291763FF-7BF149C4/0/0 X-purgate-type: clean X-purgate-size: 872 On 15.04.2026 09:50, Oleksii Kurochko wrote: > On 4/2/26 4:58 PM, Jan Beulich wrote: >> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>> @@ -87,3 +88,42 @@ int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >>> return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, >>> irq_ranges); >>> } >>> + >>> +int __init domain_vintc_init(struct domain *d) >> >> The __init here and below is questionable again. > > This function is called during construction domain only, what happen > when __init section exists. So it is okay to have __init here. > > Any use cases where it isn't true? See my earlier reply. Imo it is wrong for you to tailor the code to dom0less-only operation, with no domains ever created (or destroyed) at runtime. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776348785-80979161-D1FD231B/0/0 X-purgate-type: clean X-purgate-size: 1142 On 15.04.2026 12:00, Oleksii Kurochko wrote: > On 4/7/26 4:11 PM, Jan Beulich wrote: >> On 10.03.2026 18:09, Oleksii Kurochko wrote: >>> --- >>> Open questions: >>> - Shouldn't declaration/defintion of max_init_domid move to common code >>> instead of having it for each architecture separately? If yes, then what >>> would be the best place. >> >> What would you use to decide whether the declaration or #define is >> needed? (Plausible headers to put it can surely be found: console.h, >> domain.h, and perhaps more.) > > I thought about to wrap that with CONFIG_DOM0LESS_BOOT as the > declaration is needed only for this case, for all other cases it is just > #define. > > Or as an option we could always use declaration all the time. It won't > increase size of Xen too much or decrease performance because of > variable access. Just to mention - unless coming with very good justification, I for one am opposed to using variables for compile-time constants. We avoid doing so in a number of situations, so deliberately introducing a case to the contrary would at least feel inconsistent. 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AFNElJ8MTPhcxvBS/36cnHcaqqDeJNNyxLBC012rvpqzIZsIjQa6pHO1idfVh4B3fo7Fn2QHDw2/g3Xer2A=@lists.xenproject.org X-Gm-Message-State: AOJu0YzNsC0zwvOPNmeRZst78WwnBbjfguLzmTndrvtOdREGL19DB/Hs OAnjNH0eq9Prony/iZf4icdNZl42fCz7m/o0r8WG8/kvUTEfIN9vlEn5IxXHD/rOZw== X-Gm-Gg: AeBDieumL8HEgDKSUcSFbBkDZx+sQ4XHDRS2NBfuQx38b2+0Db2UqTu/fzJEMuUIOd7 c34OzG3iAK+kc3mCvT9pbjmxhJ4dc9A5b3AFiWEm5Lh5Lt/WhAbhtooINjDU0gTSsQXhnL+O6aJ L68lTT+a6kH7UuZV3vGlAut3CFJYvfa18nwS8gXJIT5YP7uV/Ecs5+hIYUsJY1Yt25TkFkMLBpG eMUZMI53yLS9ZI6ucDj2zoHmu2R+oPpkiBeGLAF0sDEkHXcsRKoh4af5uXLySEy7PPVboSqN3nB ivoatTfpKoooftG9WIVFm2T4fUvhePRqFVH3kLNcxysx2hD+tg2IUEqScmMXRVQI66onk5g6YYb HkFPVhBP5e5GGspDP6ZpfRLC3SE1V0s0nb2RV4qwCLKQOFYJVnAD3Qltjj6eVBbCnBCaXy6H0jy ZV5ArDDiAjWfvpA6E14uvPEL9+vowrQ9+w0jqfl9/HA+c/7STr2e8768IaReVap9D34fg72/DAk Zb+AFfqvMe3MGYVfCIqI5hZ9gz4Ccgbjy3K X-Received: by 2002:a5d:5304:0:b0:43d:7783:c67e with SMTP id ffacd0b85a97d-43d7783c7f7mr17590939f8f.36.1776348918446; Thu, 16 Apr 2026 07:15:18 -0700 (PDT) Message-ID: Date: Thu, 16 Apr 2026 16:15:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 27/27] xen/riscv: add initial dom0less infrastructure support To: Oleksii Kurochko Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <79c69067-4771-40df-a52b-8b552cd92a00@suse.com> <7032dd40-f1fe-4d34-b559-6f2eb853bf5b@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7032dd40-f1fe-4d34-b559-6f2eb853bf5b@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776348919-6DB6CCF5-0DE00C2F/0/0 X-purgate-type: clean X-purgate-size: 788 On 15.04.2026 12:28, Oleksii Kurochko wrote: > On 4/7/26 4:11 PM, Jan Beulich wrote: >>> --- a/xen/arch/riscv/setup.c >>> +++ b/xen/arch/riscv/setup.c >>> @@ -32,6 +32,8 @@ >>> #include >>> #include >>> >>> +domid_t max_init_domid = 0; >> The initializer isn't of much use, is it? Instead add __read_mostly, like >> Arm has it? > > Then I expect it will fail to compile as setup.c should contain only > __init data. But that's true no matter whether you have __read_mostly there or no section placement attribute at all. > So the we have to remove or __read_mostly or put max_init_domid to > different file. If it can't be __initdata (or alike), any data item needs to live outside of any file compiled into *.init.o. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:21:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:21:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283530.1565740 (Exim 4.92) (envelope-from ) id 1wDNak-0005Jw-RQ; Thu, 16 Apr 2026 14:21:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283530.1565740; Thu, 16 Apr 2026 14:21:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNak-0005Jl-Nv; Thu, 16 Apr 2026 14:21:14 +0000 Received: by outflank-mailman (input) for mailman id 1283530; Thu, 16 Apr 2026 14:21:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDNaj-00052Y-4L for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:21:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDNai-00EKYV-HA for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:21:12 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0f052-2eae-0a2a0a5409dd-0a2a4509bd4e-30 for ; Thu, 16 Apr 2026 16:21:12 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0f058-2497-0a2a45090019-d155802cb11a-3 for ; Thu, 16 Apr 2026 16:21:12 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4888375f735so80629695e9.3 for ; Thu, 16 Apr 2026 07:21:12 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Align prototype with what other make_*_node() are passed. 2. A follow-up RISC-V patch will call get_next_free_phandle() inside make_cpus_node(), requiring mutable access to kinfo->free_phandle. Signed-off-by: Oleksii Kurochko --- xen/arch/arm/domain_build.c | 5 +++-- xen/common/device-tree/dom0less-build.c | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 60a7cbf915a5..6740da3d324b 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1164,7 +1164,7 @@ int __init make_psci_node(void *fdt) return res; } -int __init make_cpus_node(const struct domain *d, void *fdt) +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) { int res; const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); @@ -1178,6 +1178,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) /* Keep the compiler happy with -Og */ bool clock_valid = false; uint64_t mpidr_aff; + void *fdt = kinfo; dt_dprintk("Create cpus node\n"); @@ -1626,7 +1627,7 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo, if ( res ) return res; - res = make_cpus_node(d, kinfo->fdt); + res = make_cpus_node(d, kinfo); if ( res ) return res; diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 9205f01f0a49..64b12d6aec62 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -535,7 +535,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - ret = make_cpus_node(d, kinfo->fdt); + ret = make_cpus_node(d, kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 220ae46ddbe1..2349baba3427 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -25,7 +25,7 @@ int construct_domain(struct domain *d, struct kernel_info *kinfo); int construct_hwdom(struct kernel_info *kinfo, const struct dt_device_node *node); int make_chosen_node(const struct kernel_info *kinfo); -int make_cpus_node(const struct domain *d, void *fdt); +int make_cpus_node(const struct domain *d, struct kernel_info *kinfo); int make_hypervisor_node(struct domain *d, const struct kernel_info *kinfo, int addrcells, int sizecells); int make_memory_node(const struct kernel_info *kinfo, int addrcells, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:21:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:21:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283531.1565749 (Exim 4.92) (envelope-from ) id 1wDNam-0005YJ-28; Thu, 16 Apr 2026 14:21:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283531.1565749; Thu, 16 Apr 2026 14:21:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNal-0005Y8-Um; Thu, 16 Apr 2026 14:21:15 +0000 Received: by outflank-mailman (input) for mailman id 1283531; Thu, 16 Apr 2026 14:21:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDNak-0005Iy-K6 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:21:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDNak-00GoVN-0I for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:21:14 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0f053-bab6-0a2a0a5309dd-0a2a450b9f54-24 for ; Thu, 16 Apr 2026 16:21:13 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0f059-212f-0a2a450b0019-d1558036e46a-3 for ; Thu, 16 Apr 2026 16:21:13 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488ad135063so77998165e9.0 for ; Thu, 16 Apr 2026 07:21:13 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488f096d110sm59803515e9.11.2026.04.16.07.21.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 07:21:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776349273; x=1776954073; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OlLqvIvTkFRs8hkQkfaNXDqEZXGwCjef7xkJAk72j/M=; b=oETgS9gbScgugEcQwyFfwNnN5WAfaaEyIsu8B+SdEfdI9cuKmqU5P9onAs7alfgQ13 MPPAdjlZB4JKHct64LQcFkCZjGs00n+HsIHx0gZAdlxLltweVY174lAJB/nbktH0b2H+ 3MPLjMY6FOWv///ky3M+2R5qEN+d860rg+HCBL6yj43Y19kHsO5OgKnaO+n69f+PS2TF 6GHOdFEpihK63T+jwKSeL+CAMo4hQOQGGtZV2Nx1v5TNRwptMU+9nvWLG/JpllKu4VFS AxQbvUARaA73grIagj//7vyBErupjbNSkVkxibbAb4+S3m1n+Yz3LvCVLVhqaQn7LLMa tUcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776349273; x=1776954073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=OlLqvIvTkFRs8hkQkfaNXDqEZXGwCjef7xkJAk72j/M=; b=HZlsEoJjoQagRmbVNuiM6VZzAb4C1q+MvkOacgZz0z9qDq/3xN9g062Wp9Eys9ko4t mpOZl/M+6k2tqbsU+lL7EFdAig20ocD7X6+ZqOnXCZfiIs+smKeeB2XjjXKKwsd4xYlS BjZ6kmM8dD8ZXtK4TY1RAM2T0Kxg2vF3P7gg5kK7zCk5QF7j9cLuGz5iLI809ZHq8CxD +MwY6Q6O9qvloNhKqryjF19j1hfr3JISHzJoGEXZIvEd+MS1YNmNyATUyXAM3jYxbCuA BEeJXpoeXmaNjXIQw7BUKXOoTaMLuSIBfWpeSiukReSJnBZnZpuesJW/UngaXW2rd+GB nDSw== X-Gm-Message-State: AOJu0Yya36pDGKnJ1fMoZPVfyOpx65SumsN8gZ+0xDYnyytrmF+vAIJB yiBCKBBkBx/t6xcIfcnSua7CXO28VXe9QxuufXRHOPT1l1YBwNYqXPuJb9RHVA== X-Gm-Gg: AeBDiesU98CBWRI0bJ7JkcxZdgWKcOqzM+yQDHehCqmmQX43e18g8/TzxeLv/weo5/I HyplA1oK14Ck3vvLh30LYQSIDTnudI2JZlb3UcIZpRhrCVM99vlwSN7JQbkJoq2pM3ouqcw5xp6 dvhTH3zjfP5IlcJHOs37eXb8PSiYLBRzyBMp4gFElr+plkgKsn9p2jRbeHu1zE504oGT+P8Lmak 3al0Oecy/BiAW0WZpAV19bn3Y5tRbqJaeh76kI6wDj3raXw3o3kKJf18OqFdKKz/KNWrjjs+eoQ KxPh9ogG+PGdQUNT/6gNH4bg3m6FdKOPm8XM2TKF5CjkIHtDZp9dTsXe63KzLEDhog47GYGyWOl DnBQpyptVxxycJFGLaR4S5gYU9qAfFS/vJwZn5MsX0HwqcFcp0peuIMv5avlhGU7GWIFJmbfHKH 3kHuAjpywB+yjcFnUiODq51UQyr3RLr5TsDNX7HvhAQ3CK9UIL7gkNkCrdn0FQnCAmSKbm/+BL7 Lqz X-Received: by 2002:a05:600c:3f0a:b0:488:afb5:6a21 with SMTP id 5b1f17b1804b1-488d68764b0mr362614505e9.15.1776349272848; Thu, 16 Apr 2026 07:21:12 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v1 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE Date: Thu, 16 Apr 2026 16:21:00 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776349273-06573F3B-97F78B3A/10/73395122804 X-purgate-type: spam X-purgate-size: 10470 As domain type is part of common code now there is no any reason to have architecture-specific set_domain_type() functions so it is dropped. The CONFIG_ARM_64 guard in xen/arch/arm/domain_build.c is intentionally left unchanged: it is ARM-specific code, and ARM_64 selects HAS_DOMAIN_TYPE, so the semantics are identical. x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. For x86_32 it is fine to follow generic is_{32,64}_bit_domain() implementations. Generally it probably would be better to introduce CONFIG_32BIT and use it to define is_{32,64}bit_domain() as if one day CONFIG_128BIT will be introduced is_{32,64}bit_domain() will be defined incorrectly but considering that CONFIG_64BIT is maximum supported bitness it is fine to define in this way. Signed-off-by: Oleksii Kurochko --- xen/arch/Kconfig | 3 +++ xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 ++-- xen/arch/arm/dom0less-build.c | 14 -------------- xen/arch/arm/domain_build.c | 8 ++++---- xen/arch/arm/include/asm/domain.h | 12 ------------ xen/arch/arm/include/asm/kernel.h | 4 ---- xen/arch/arm/kernel.c | 10 +++++----- xen/common/device-tree/dom0less-build.c | 5 ++++- xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++++++++ xen/include/xen/fdt-kernel.h | 5 +++++ xen/include/xen/sched.h | 4 ++++ 13 files changed, 41 insertions(+), 44 deletions(-) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index f9230bfaf872..6c53149f7ee1 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -1,6 +1,9 @@ config 64BIT bool +config HAS_DOMAIN_TYPE + bool + config PHYS_ADDR_T_32 bool diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..79622b46a10d 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -7,6 +7,7 @@ config ARM_64 def_bool y depends on !ARM_32 select 64BIT + select HAS_DOMAIN_TYPE select HAS_FAST_MULTIPLY select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c index 8720d126c97d..9e9a29eb1e78 100644 --- a/xen/arch/arm/arm64/domctl.c +++ b/xen/arch/arm/arm64/domctl.c @@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type) return -EINVAL; if ( domain_tot_pages(d) != 0 ) return -EBUSY; - if ( d->arch.type == type ) + if ( d->type == type ) return 0; - d->arch.type = type; + d->type = type; if ( is_64bit_domain(d) ) for_each_vcpu(d, v) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f73c65e5151 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) return 0; } -/* TODO: make arch.type generic ? */ -#ifdef CONFIG_ARM_64 -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* type must be set before allocate memory */ - d->arch.type = kinfo->arch.type; -} -#else -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* Nothing to do */ -} -#endif - int __init init_vuart(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6740da3d324b..2fd89b3a1345 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1178,7 +1178,7 @@ int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) /* Keep the compiler happy with -Og */ bool clock_valid = false; uint64_t mpidr_aff; - void *fdt = kinfo; + void *fdt = kinfo->fdt; dt_dprintk("Create cpus node\n"); @@ -1774,13 +1774,13 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) #ifdef CONFIG_ARM_64 /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) + if ( !(cpu_has_el1_32) && kinfo->type == DOMAIN_32BIT ) { printk("Platform does not support 32-bit domain\n"); return -EINVAL; } - if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) ) + if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) ) { printk("SVE is not available for 32-bit domain\n"); return -EINVAL; @@ -1896,7 +1896,7 @@ int __init construct_hwdom(struct kernel_info *kinfo, #ifdef CONFIG_ARM_64 /* type must be set before allocate_memory */ - d->arch.type = kinfo->arch.type; + d->type = kinfo->type; #endif find_gnttab_region(d, kinfo); if ( is_domain_direct_mapped(d) ) diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index f95ad1285e6e..2d4c1bdecb66 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -18,18 +18,6 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; -#ifdef CONFIG_ARM_64 -enum domain_type { - DOMAIN_32BIT, - DOMAIN_64BIT, -}; -#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT) -#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT) -#else -#define is_32bit_domain(d) (1) -#define is_64bit_domain(d) (0) -#endif - struct vtimer { struct vcpu *v; int irq; diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h index 7c3b7fde5b64..21f4273fa1b5 100644 --- a/xen/arch/arm/include/asm/kernel.h +++ b/xen/arch/arm/include/asm/kernel.h @@ -10,10 +10,6 @@ struct arch_kernel_info { -#ifdef CONFIG_ARM_64 - enum domain_type type; -#endif - /* Enable pl011 emulation */ bool vpl011; }; diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 3c613cdb233f..bc9aad3f5f45 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -101,7 +101,7 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) paddr_t load_addr; #ifdef CONFIG_ARM_64 - if ( (info->arch.type == DOMAIN_64BIT) && (info->image.start == 0) ) + if ( (info->type == DOMAIN_64BIT) && (info->image.start == 0) ) return mem->bank[0].start + info->image.text_offset; #endif @@ -272,10 +272,10 @@ int __init kernel_uimage_probe(struct kernel_info *info, switch ( uimage.arch ) { case IH_ARCH_ARM: - info->arch.type = DOMAIN_32BIT; + info->type = DOMAIN_32BIT; break; case IH_ARCH_ARM64: - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; break; default: printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch); @@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, info->load = kernel_zimage_load; - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; return 0; } @@ -397,7 +397,7 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, info->load = kernel_zimage_load; #ifdef CONFIG_ARM_64 - info->arch.type = DOMAIN_32BIT; + info->type = DOMAIN_32BIT; #endif return 0; diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 64b12d6aec62..418282a6a549 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -809,7 +809,10 @@ static int __init construct_domU(struct kernel_info *kinfo, if ( rc < 0 ) return rc; - set_domain_type(d, kinfo); +#ifdef CONFIG_HAS_DOMAIN_TYPE + /* type must be set before allocate memory */ + d->type = kinfo->type; +#endif if ( is_hardware_domain(d) ) { diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h index faaf660424b2..4118dec76c0a 100644 --- a/xen/include/xen/dom0less-build.h +++ b/xen/include/xen/dom0less-build.h @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, int make_intc_domU_node(struct kernel_info *kinfo); int make_arch_nodes(struct kernel_info *kinfo); -void set_domain_type(struct domain *d, struct kernel_info *kinfo); - int init_intc_phandle(struct kernel_info *kinfo, const char *name, const int node_next, const void *pfdt); diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 93c0fd00c1d7..5951e7e6928f 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -13,6 +13,19 @@ struct guest_area { void *map; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE +enum domain_type { + DOMAIN_32BIT, + DOMAIN_64BIT, +}; +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) +#elif !defined(CONFIG_64BIT) +/* On 32-bit-only platforms all domains are 32-bit. */ +#define is_32bit_domain(d) (true) +#define is_64bit_domain(d) (false) +#endif + #include typedef union { diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 3527934b2a00..2c9bf4d4ef4f 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -9,6 +9,7 @@ #include #include +#include #include #if __has_include() @@ -69,6 +70,10 @@ struct kernel_info { } image; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + #if __has_include() struct arch_kernel_info arch; #endif diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..4314bd195457 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -668,6 +668,10 @@ struct domain struct page_info *pending_scrub; unsigned int pending_scrub_order; unsigned int pending_scrub_index; + +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif } __aligned(PAGE_SIZE); static inline struct page_list_head *page_to_list( -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:21:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:21:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283529.1565732 (Exim 4.92) (envelope-from ) id 1wDNaj-000564-H3; Thu, 16 Apr 2026 14:21:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283529.1565732; Thu, 16 Apr 2026 14:21:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNaj-00055x-D5; Thu, 16 Apr 2026 14:21:13 +0000 Received: by outflank-mailman (input) for mailman id 1283529; Thu, 16 Apr 2026 14:21:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDNai-0004sq-Bm for xen-devel@lists.xenproject.org; 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When a partial FDT (pfdt) is provided, special care is needed during initialization of free_phandle, as the pfdt may already contain a dummy interrupt controller node with a phandle assigned to it. free_phandle must therefore be initialized to one past the highest phandle already present in the pfdt, to avoid collisions. Since free_phandle may be needed for the very first guest node generated, domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). The new call site also aligns better with the existing comment stating that domain_handle_dtb_boot_module() must be called before the rest of the device tree is generated. Introduce get_next_free_phandle() to ensure that phandles allocated for guest nodes do not overlap the Xen-reserved phandle range. This helper will be used by subsequent patches (by RISC-V at the moment). Signed-off-by: Oleksii Kurochko --- xen/common/device-tree/dom0less-build.c | 44 ++++++++++++++++++------- xen/include/xen/fdt-domain-build.h | 6 ++++ xen/include/xen/fdt-kernel.h | 3 ++ 3 files changed, 41 insertions(+), 12 deletions(-) diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 840d14419da2..9205f01f0a49 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, if ( res < 0 ) goto out; + /* + * Find the highest phandle in the partial FDT so free_phandle starts + * above it, avoiding collisions with pfdt's own phandle assignments. + */ + res = fdt_generate_phandle(pfdt, &kinfo->free_phandle); + if ( res ) + { + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; + goto out; + } + + if ( kinfo->free_phandle >= GUEST_PHANDLE_GIC ) + { + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); + res = -EOVERFLOW; + goto out; + } + for ( node_next = fdt_first_subnode(pfdt, 0); node_next > 0; node_next = fdt_next_subnode(pfdt, node_next) ) @@ -459,6 +477,8 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); kinfo->phandle_intc = GUEST_PHANDLE_GIC; + kinfo->free_phandle = 1; + BUILD_BUG_ON(GUEST_PHANDLE_GIC == 1); #ifdef CONFIG_GRANT_TABLE kinfo->gnttab_start = GUEST_GNTTAB_BASE; @@ -499,6 +519,18 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; + /* + * domain_handle_dtb_boot_module() must be called before the rest of the + * device tree is generated because it sets phandle_intc and free_phandle, + * which subsequent node generation depends on. + */ + if ( kinfo->dtb ) + { + ret = domain_handle_dtb_boot_module(d, kinfo); + if ( ret ) + goto err; + } + ret = make_chosen_node(kinfo); if ( ret ) goto err; @@ -516,18 +548,6 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - /* - * domain_handle_dtb_boot_module has to be called before the rest of - * the device tree is generated because it depends on the value of - * the field phandle_intc. - */ - if ( kinfo->dtb ) - { - ret = domain_handle_dtb_boot_module(d, kinfo); - if ( ret ) - goto err; - } - ret = make_intc_domU_node(kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 1d9e77df0eb3..220ae46ddbe1 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -63,6 +63,12 @@ int find_unallocated_memory(const struct kernel_info *kinfo, unsigned long e_gfn, void *data)); +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ +static inline uint32_t get_next_free_phandle(struct kernel_info *kinfo) +{ + return kinfo->free_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->free_phandle++; +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index aa977a50f4fc..3527934b2a00 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -44,6 +44,9 @@ struct kernel_info { /* Interrupt controller phandle */ uint32_t phandle_intc; + /* Next free phandle available for assigning to guest device nodes */ + uint32_t free_phandle; + /* loader to use for this kernel */ void (*load)(struct kernel_info *info); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:21:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:21:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283528.1565723 (Exim 4.92) (envelope-from ) id 1wDNai-0004sy-AP; Thu, 16 Apr 2026 14:21:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283528.1565723; Thu, 16 Apr 2026 14:21:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNai-0004sr-64; Thu, 16 Apr 2026 14:21:12 +0000 Received: by outflank-mailman (input) for mailman id 1283528; Thu, 16 Apr 2026 14:21:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDNag-0004sk-RF for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:21:11 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDNag-00EKYV-81 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:21:10 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0f052-2eae-0a2a0a5409dd-0a2a4509bd4e-18 for ; Thu, 16 Apr 2026 16:21:10 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0f056-2497-0a2a45090019-d155802cb0f6-3 for ; Thu, 16 Apr 2026 16:21:10 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-483487335c2so88860995e9.2 for ; Thu, 16 Apr 2026 07:21:10 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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For example, on the RISC-V side in make_cpus_node() [1] it is necessary to know which phandle number is unused to use it for device tree node generation. Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandles for imsic and riscv,cpu-intc are generated in this example not by get_next_free_phandle(), that is why they have such big numbers. For non-RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC is an interrupt controller that provides MSI and connects to each CPU. So (based on the DTS above) for APLIC, kinfo->phandle_intc is reused, which will also be re-used for the device node's interrupt property. For all others, I just introduced GUEST_PHANDLE_LAST [2] and used it for generation [3]. But I expect that it could be useful for other architectures too so I just moved it to common and re-use pfdt to understand what the maximum used phandle is. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt [2] https://lore.kernel.org/xen-devel/ccd6d21b224b478c88ca5f2fdd2d1dd507671510.1773157782.git.oleksii.kurochko@gmail.com/ [3] https://lore.kernel.org/xen-devel/fd64b8526a23e9d7775b9b48c5a933b0673c4fba.1773157782.git.oleksii.kurochko@gmail.com/ ************************************* Another thing introduced in this patch series is moving domain type to common code as several architectures (ARM and RISC-V for now) use them and it looks pretty architecture-independent. Also, is_64bit_domain() is used by dom0less common code, so I found it useful also to move is_{32,64}bit_domain macros to common code. ************************************* And the last thing is changing the prototype of make_cpus_node() to be aligned with other make_*_node() and since RISC-V will need access to the free_phandle field (even if it will be moved to kinfo->arch.free_phandle) and for the reason that this ->free_phandle is updated in make_*_node(), the kinfo argument is passed as non-const. CI tests: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2457632124 Oleksii Kurochko (3): xen/dom0less: introduce free_phandle in struct kernel_info xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() xen: introduce CONFIG_HAS_DOMAIN_TYPE xen/arch/Kconfig | 3 ++ xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 +- xen/arch/arm/dom0less-build.c | 14 ------- xen/arch/arm/domain_build.c | 11 +++--- xen/arch/arm/include/asm/domain.h | 12 ------ xen/arch/arm/include/asm/kernel.h | 4 -- xen/arch/arm/kernel.c | 10 ++--- xen/common/device-tree/dom0less-build.c | 51 ++++++++++++++++++------- xen/include/xen/dom0less-build.h | 2 - xen/include/xen/domain.h | 13 +++++++ xen/include/xen/fdt-domain-build.h | 8 +++- xen/include/xen/fdt-kernel.h | 8 ++++ xen/include/xen/sched.h | 4 ++ 14 files changed, 86 insertions(+), 59 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:26:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:26:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283570.1565759 (Exim 4.92) (envelope-from ) id 1wDNfS-0006y5-Ie; Thu, 16 Apr 2026 14:26:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283570.1565759; Thu, 16 Apr 2026 14:26:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNfS-0006xy-Eg; Thu, 16 Apr 2026 14:26:06 +0000 Received: by outflank-mailman (input) for mailman id 1283570; Thu, 16 Apr 2026 14:26:04 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNfQ-0006xc-Ef for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:26:04 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDNfO-00EUyY-9o for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:26:03 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0f160-bab6-0a2a0a5309dd-0a2a4502b5fc-48 for ; Thu, 16 Apr 2026 16:26:03 +0200 Received: from [209.85.221.43] (helo=mail-wr1-f43.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0f17b-af86-0a2a45020019-d155dd2ba87b-3 for ; Thu, 16 Apr 2026 16:26:03 +0200 Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-43d70c30767so436657f8f.0 for ; Thu, 16 Apr 2026 07:26:03 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776349563-81772161-99629E44/0/0 X-purgate-type: clean X-purgate-size: 1823 On 06.04.2026 21:11, Stewart Hildebrand wrote: > From: Mykyta Poturai > > There is no need to store ranges for each PCI device, as they are only > used during the mapping/unmapping process and can be reused for each > device. This also allows to avoid the need to allocate and destroy > rangesets for each device. > > Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform > (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() > macro to free a rangeset and set the pointer to NULL. I'm struggling some with this description. On a typical system I might expect far more vCPU-s to be there than there are PCI devices. In which case "There is no need to ..." and "This also allows to avoid ..." feels like an attempt to mislead readers: We may end up with bigger memory footprint, when my reading of the description suggests you're trying to hint at a reduction. > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -455,6 +455,8 @@ static int vcpu_teardown(struct vcpu *v) > */ > static void vcpu_destroy(struct vcpu *v) > { > + vpci_vcpu_destroy(v); > + > free_vcpu_struct(v); > } Can't the resources be released much earlier, somewhere during domain_relinquish_resources()? > --- a/xen/include/xen/rangeset.h > +++ b/xen/include/xen/rangeset.h > @@ -40,6 +40,13 @@ struct rangeset *rangeset_new( > void rangeset_destroy( > struct rangeset *r); > > +/* Destroy a rangeset, and zero the pointer to it. */ > +#define RANGESET_DESTROY(r) \ > + ({ \ > + rangeset_destroy(r); \ > + (r) = NULL; \ > + }) Please note the subtle but important difference (in ordering of operations) from e.g. XFREE() or FREE_XENHEAP_PAGES(). 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Thu, 16 Apr 2026 07:32:51 -0700 (PDT) Message-ID: <29c2a896-59b4-4804-ade4-362f65ffadfc@suse.com> Date: Thu, 16 Apr 2026 16:32:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= From: Jan Beulich Subject: [PATCH] xvmalloc: adjust XVFREE() ordering Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; 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Amends: 9102fcd9579f ("mm: introduce xvmalloc() et al and use for grant table allocations") Signed-off-by: Jan Beulich --- a/xen/include/xen/xvmalloc.h +++ b/xen/include/xen/xvmalloc.h @@ -71,8 +71,9 @@ void *_xvrealloc(void *va, size_t size, /* Free an allocation, and zero the pointer to it. */ #define XVFREE(p) do { \ - xvfree(p); \ + void *_ptr_ = (p); \ (p) = NULL; \ + xvfree(_ptr_); \ } while ( false ) static inline void *_xvmalloc_array( From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:40:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:40:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283598.1565776 (Exim 4.92) (envelope-from ) id 1wDNsu-0001TQ-Vd; Thu, 16 Apr 2026 14:40:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283598.1565776; Thu, 16 Apr 2026 14:40:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDNsu-0001TJ-Sk; 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Thanks, Roger. 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Thu, 16 Apr 2026 07:50:40 -0700 (PDT) Message-ID: <58dd3393-02a8-418a-8a8a-7d8f0256fb3c@suse.com> Date: Thu, 16 Apr 2026 16:50:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xvmalloc: adjust XVFREE() ordering To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel References: <29c2a896-59b4-4804-ade4-362f65ffadfc@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776351041-C2F72DB1-2A5C894C/0/0 X-purgate-type: clean X-purgate-size: 832 On 16.04.2026 16:39, Roger Pau Monné wrote: > On Thu, Apr 16, 2026 at 04:32:54PM +0200, Jan Beulich wrote: >> What c4f427ec879e ("xen: Swap order of actions in the FREE*() macros") did >> should have been done right away when XVFREE() was introduced. >> >> Amends: 9102fcd9579f ("mm: introduce xvmalloc() et al and use for grant table allocations") >> Signed-off-by: Jan Beulich > > Acked-by: Roger Pau Monné Thanks. > No intention to stir controversy, but I feel like this should better > use the Fixes tag, as it's not an omission or similar, but code fix. I would have used Fixes: if I was able to spot a use where the difference would actually matter in existing code. I can switch, but in the absence thereof I deemed Amends: (marginally) more precise. Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:54:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:54:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283621.1565794 (Exim 4.92) (envelope-from ) id 1wDO6T-0004rH-Ax; Thu, 16 Apr 2026 14:54:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283621.1565794; Thu, 16 Apr 2026 14:54:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDO6T-0004rA-74; Thu, 16 Apr 2026 14:54:01 +0000 Received: by outflank-mailman (input) for mailman id 1283621; Thu, 16 Apr 2026 14:53:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDO6R-0004r4-KE for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:53:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDO6R-00Dgea-0w for xen-devel@lists.xenproject.org; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1776351238-CF77FD75-8A070105/0/0 X-purgate-type: clean X-purgate-size: 1429 On Wed, Apr 01, 2026 at 01:22:03AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > diff --git a/scripts/alpine-rootfs.sh b/scripts/alpine-rootfs.sh > index f649550d80ab..0afae48cfa6b 100755 > --- a/scripts/alpine-rootfs.sh > +++ b/scripts/alpine-rootfs.sh > @@ -72,6 +74,7 @@ rc-update add loopback sysinit > rc-update add bootmisc boot > rc-update add devfs sysinit > rc-update add dmesg sysinit > +rc-update add dropbear boot > rc-update add hostname boot > rc-update add hwclock boot > rc-update add hwdrivers sysinit > @@ -84,7 +87,9 @@ echo "ttyS0" >> /etc/securetty > echo "hvc0" >> /etc/securetty > echo "ttyS0::respawn:/sbin/getty -L ttyS0 115200 vt100" >> /etc/inittab > echo "hvc0::respawn:/sbin/getty -L hvc0 115200 vt100" >> /etc/inittab > +echo "DROPBEAR_OPTS=3D\"-R\"" >> /etc/conf.d/dropbear Is this useful somehow? Because the service that start dropbear will generate the ssh_host keys before starting dropbear. > echo "rc_verbose=3Dyes" >> /etc/rc.conf > +touch /etc/network/interfaces That the kind of command that I don't understand what it is for on a first look ... But looks like it just to allow the "networking" service to start without error if the test didn't configure networking via this file. A comment would be nice, here or in the commit message. Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 16 14:59:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 14:59:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283636.1565803 (Exim 4.92) (envelope-from ) id 1wDOC9-0005lb-25; Thu, 16 Apr 2026 14:59:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283636.1565803; Thu, 16 Apr 2026 14:59:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOC8-0005lU-VR; Thu, 16 Apr 2026 14:59:52 +0000 Received: by outflank-mailman (input) for mailman id 1283636; Thu, 16 Apr 2026 14:59:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOC7-0005lO-JQ for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 14:59:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDOC6-00DhQc-Gp for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:59:50 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0f94a-2eae-0a2a0a5409dd-0a2a450acf44-40 for ; Thu, 16 Apr 2026 16:59:50 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0f966-56b3-0a2a450a0019-d1558031dc29-3 for ; Thu, 16 Apr 2026 16:59:50 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488ba6366a7so97261205e9.0 for ; Thu, 16 Apr 2026 07:59:50 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260406191203.97662-3-stewart.hildebrand@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776351590-CF3738B7-2D1D27E1/0/0 X-purgate-type: clean X-purgate-size: 2205 On 06.04.2026 21:11, Stewart Hildebrand wrote: > Introduce vPCI BAR mapping task queue. Store information needed to > map/unmap BARs in struct vpci_map_task. Allow queueing of BAR map/unmap > operations in a list, thus making it possible to perform multiple p2m > operations associated with single PCI device. > > This is preparatory work for further changes that need to perform > multiple unmap/map operations before returning to guest. > > At the moment, only a single operation will be queued. However, when > multiple operations are queued, there is a check in modify_bars() to > skip BARs already in the requested state that will no longer be > accurate. Remove this check in preparation of upcoming changes. > > Signed-off-by: Stewart Hildebrand > --- > apply_map() and vpci_process_map_task() are very similar. Should we try > to combine them into a single function? > > I concede that the dynamic allocation/deallocation of struct > vpci_map_task is not ideal. However, to support SR-IOV, there will be a > need to queue many mapping operations (one per VF), and statically > pre-allocating that much would seem wasteful. Only the hardware and/or > control domain would need to queue many operations, and only when > configuring SR-IOV. The address ranges are pretty regular though across the VFs, so I wonder whether getting away with less than one instance per VF (perhaps one per PF) wouldn't be possible by adjusting what data is being put into the "task" structure. > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -19,8 +19,7 @@ > */ > #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) > > -void vpci_vcpu_destroy(struct vcpu *v); > -int vpci_vcpu_init(struct vcpu *v); > +void vpci_vcpu_init(struct vcpu *v); > > /* Assign vPCI to device by adding handlers. */ > int __must_check vpci_assign_device(struct pci_dev *pdev); > @@ -155,14 +154,23 @@ struct vpci { > }; > > #ifdef __XEN__ > -struct vpci_vcpu { > +struct vpci_map_task { > /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ This comment needs adjusting then, too, doesn't it? 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I can switch, but in the absence > thereof I deemed Amends: (marginally) more precise. It's speculative defence in depth. Zeroing the pointer in memory before freeing the block is strictly better than the other way around. For the local CPU it prevents speculative use-after-free (the store queue is always in program order), and whether it does this for remote CPUs depends on how strong the platform memory ordering is. This all came from the Ghostrace paper. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 16 15:16:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 15:16:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283668.1565829 (Exim 4.92) (envelope-from ) id 1wDORy-0000tt-Jk; Thu, 16 Apr 2026 15:16:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283668.1565829; Thu, 16 Apr 2026 15:16:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDORy-0000tm-Gr; Thu, 16 Apr 2026 15:16:14 +0000 Received: by outflank-mailman (input) for mailman id 1283668; Thu, 16 Apr 2026 15:16:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDORx-0000tg-BC for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 15:16:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDORw-00EVg7-Nj for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 17:16:12 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e0fd15-5cb7-0a2a0a5109dd-0a2a45048d66-44 for ; Thu, 16 Apr 2026 17:16:12 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e0fd3c-1dec-0a2a45040019-d155dd32c93e-3 for ; Thu, 16 Apr 2026 17:16:12 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43cfd1f9fd1so5210761f8f.3 for ; Thu, 16 Apr 2026 08:16:12 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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I will sort them. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 16 15:29:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 15:29:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283691.1565838 (Exim 4.92) (envelope-from ) id 1wDOek-0003BE-R7; Thu, 16 Apr 2026 15:29:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283691.1565838; Thu, 16 Apr 2026 15:29:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOek-0003B7-OD; Thu, 16 Apr 2026 15:29:26 +0000 Received: by outflank-mailman (input) for mailman id 1283691; Thu, 16 Apr 2026 15:29:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOej-0003B1-LT for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 15:29:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDOej-006Y9f-2A for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 17:29:25 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e10048-2eae-0a2a0a5409dd-0a2a45038ef4-28 for ; Thu, 16 Apr 2026 17:29:24 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e10054-672d-0a2a45030019-d155802ba96e-3 for ; Thu, 16 Apr 2026 17:29:24 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso7701785e9.1 for ; Thu, 16 Apr 2026 08:29:24 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260406191203.97662-2-stewart.hildebrand@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776353364-A177E938-74D125C5/0/0 X-purgate-type: clean X-purgate-size: 1944 On 06.04.2026 21:11, Stewart Hildebrand wrote: > From: Mykyta Poturai > > There is no need to store ranges for each PCI device, as they are only > used during the mapping/unmapping process and can be reused for each > device. This also allows to avoid the need to allocate and destroy > rangesets for each device. > > Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform > (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() > macro to free a rangeset and set the pointer to NULL. > > Amends: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") > Signed-off-by: Mykyta Poturai > Signed-off-by: Stewart Hildebrand > --- > It seems a bit awkward to introduce various vpci vcpu alloc/dealloc > functions here only to undo most of it in the next patch. Thoughts on > folding the next patch into this one? > > v3->v4: > * no change There are some complexities here due to the patch being part of two series. Once Mykyta re-submits the SR-IOV series, we'll have two (likely diverging) v4-s. Already here ... > v2->v3: > * new patch in this series, borrowed from [1] > * add Amends tag > * remove unused variable i due to rebasing over 998060dd9101 ("vPCI: > move vpci_init_capabilities() to a separate file") > * enclose entire struct vpci_vcpu inside #ifdef __XEN__ > * s/bar_mem/mem/ > * use ARRAY_SIZE > * put init/destroy in functions > * only allocate for domains with vPCI and idle domain > * replace 'if ( !mem ) continue;' with ASSERT ... the v3 there has one more item on this ChangeLog list ("* synced with BAR write with memory decoding enabled series[1]"), albeit maybe (now that I read it again) this merely is the counterpart of the first bullet point here. It would be clearer if there the other series' title was supplied verbatim and in quotes. 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776353830-47B7F8B7-7A702960/10/73395122804 X-purgate-type: spam X-purgate-size: 1943 On 4/16/26 9:50 AM, Jan Beulich wrote: > On 10.04.2026 19:41, Andrew Cooper wrote: >> On 10/04/2026 4:45 pm, Oleksii Kurochko wrote: >>> diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c >>> index 7efa76fdbcb1..80f0e9ddae6a 100644 >>> --- a/xen/arch/riscv/time.c >>> +++ b/xen/arch/riscv/time.c >>> @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) >>> panic("%s: ACPI isn't supported\n", __func__); >>> >>> boot_clock_cycles = get_cycles(); >>> + >>> + /* set_xen_timer must have been set by sbi_init() already */ >>> + ASSERT(set_xen_timer); >>> + >>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >>> + { >>> + set_xen_timer = sstc_set_xen_timer; >>> + >>> + /* >>> + * A VS-timer interrupt becomes pending whenever the value of >>> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >>> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >>> + * ULONG_MAX. >>> + */ >>> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >>> +#ifdef CONFIG_RISCV_32 >>> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >>> +#endif >> >> You've got this pattern twice in this patch alone, and these aren't the >> only CSRs which are formed of pairs to get a 64bit value in 32bit mode. >> >> Sadly, the numbering isn't consistent for the high constant, but we can >> let the compiler do most of the hard work for us. >> >> #ifdef CONFIG_RISCV_32 >> # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) >> #else >> # define __csr_write32h(csr, val) (void)(csr, val) > > Just to mention: Since the comma is an operator here (not a lexical element > separating function arguments), more parenthesization may be needed for > Misra's sake. I will define it in the next way: # define __csr_write32h(csr, val) (void)((csr), (val)) Thanks ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 16 15:45:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 15:45:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283716.1565856 (Exim 4.92) (envelope-from ) id 1wDOtq-0006YU-AN; Thu, 16 Apr 2026 15:45:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283716.1565856; Thu, 16 Apr 2026 15:45:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOtq-0006YN-7G; Thu, 16 Apr 2026 15:45:02 +0000 Received: by outflank-mailman (input) for mailman id 1283716; Thu, 16 Apr 2026 15:45:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDOtn-0006YH-VN for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 15:45:00 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDOtn-00AMxm-CN for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 17:44:59 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e103f6-2eae-0a2a0a5409dd-0a2a45099750-8 for ; Thu, 16 Apr 2026 17:44:59 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e103fb-2497-0a2a45090019-d1558033a5d5-3 for ; Thu, 16 Apr 2026 17:44:59 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-488b8efed61so9204695e9.1 for ; Thu, 16 Apr 2026 08:44:59 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776354299-92F76A53-60F5083A/0/0 X-purgate-type: clean X-purgate-size: 2133 On 16.04.2026 17:37, Oleksii Kurochko wrote: > > > On 4/16/26 9:50 AM, Jan Beulich wrote: >> On 10.04.2026 19:41, Andrew Cooper wrote: >>> On 10/04/2026 4:45 pm, Oleksii Kurochko wrote: >>>> diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c >>>> index 7efa76fdbcb1..80f0e9ddae6a 100644 >>>> --- a/xen/arch/riscv/time.c >>>> +++ b/xen/arch/riscv/time.c >>>> @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) >>>> panic("%s: ACPI isn't supported\n", __func__); >>>> >>>> boot_clock_cycles = get_cycles(); >>>> + >>>> + /* set_xen_timer must have been set by sbi_init() already */ >>>> + ASSERT(set_xen_timer); >>>> + >>>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >>>> + { >>>> + set_xen_timer = sstc_set_xen_timer; >>>> + >>>> + /* >>>> + * A VS-timer interrupt becomes pending whenever the value of >>>> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >>>> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >>>> + * ULONG_MAX. >>>> + */ >>>> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >>>> +#ifdef CONFIG_RISCV_32 >>>> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >>>> +#endif >>> >>> You've got this pattern twice in this patch alone, and these aren't the >>> only CSRs which are formed of pairs to get a 64bit value in 32bit mode. >>> >>> Sadly, the numbering isn't consistent for the high constant, but we can >>> let the compiler do most of the hard work for us. >>> >>> #ifdef CONFIG_RISCV_32 >>> # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) >>> #else >>> # define __csr_write32h(csr, val) (void)(csr, val) >> >> Just to mention: Since the comma is an operator here (not a lexical element >> separating function arguments), more parenthesization may be needed for >> Misra's sake. > > I will define it in the next way: > > # define __csr_write32h(csr, val) (void)((csr), (val)) Actually, yet more parentheses are needed: # define __csr_write32h(csr, val) ((void)((csr), (val))) Jan From xen-devel-bounces@lists.xenproject.org Thu Apr 16 15:49:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 15:49:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283724.1565866 (Exim 4.92) (envelope-from ) id 1wDOxw-0007Qd-Qo; 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AFNElJ9xGmYiwsTyT+nqf2PznRLdWpZcLxGJ8dOCXOxv90Q5pDN0J4O64awWwJZMLLoe17Ri9ez0Qor61zg=@lists.xenproject.org X-Gm-Message-State: AOJu0YxyszP7R8YZsy6mSrQ/dklyHWKBfubH7POJgj9zd8wb7+Fzp7NL hpOGqmzY6v26qEygGayYcCUkltPLH6ckp2e9Gsym6+8wNvJ2YUyP4PJM X-Gm-Gg: AeBDieudkgI0qd2ocCNMgFKwaBC96KR7+G0nMLrF01BlMal2dirnRRHqFcGaDHPNLPL H1U9vpARSehxswkZ+Ap7xHR4e8zT8MbYuRcD/U6BoB7Z/3KcO3MLYPE6ORfA2y3CDE5YluaeYSU qJ/HC0leaj5a1FAq+BWpOD0i38gFA9C5GCIPLq8F24cIXGmUsbykQKCDzodWcxT79r8earv7T0F uYZRuAayo5/RMFQNv5FleIdR7V+XWkhlCwJJOXTW/oXGljiMGCZK7BWmxrMr7OuHoAxKAbnbzc6 xeEORePnQm1s/dgh5T07vbsybc81VvPlc4VqHOfjoDkCEhYCkMxKksxC+KYJudjPcVoQxqToVvl SU6TLy5ZRas2m2xZLEasMnTZzOfrG2M+TrEw1pa5RsCl5NQdsEXLeN3DNObrViSIkN3ubg+RGUO frYRlghs1tZ/Jd57rtUBIE7RXpuBrs3V9gwEUOp95/sJMvyFc7AtS9ufL/IR88zREMYDgAH58GA TAwtps0zF81DhNY4yIJBELE X-Received: by 2002:a05:600c:c0da:b0:488:936a:6220 with SMTP id 5b1f17b1804b1-488d685b577mr310909935e9.21.1776354554067; Thu, 16 Apr 2026 08:49:14 -0700 (PDT) Message-ID: <5de7ede4-b14f-4a36-b06b-12bf768b52a8@gmail.com> Date: Thu, 16 Apr 2026 17:49:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/riscv: allow Xen to use SSTC while hiding it from guests To: Jan Beulich , Andrew Cooper Cc: Romain Caritey , Alistair Francis , Connor Davis , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <9eb6c6d9-8e1c-40f6-a44b-579df213bda0@citrix.com> <3c8cba0b-8d9c-4656-b70e-f5c65017aecc@gmail.com> <9579ca3e-e98b-4d76-81bf-0f2e0df5a990@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <9579ca3e-e98b-4d76-81bf-0f2e0df5a990@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776354554-2A9623FF-00904EBD/10/73395122804 X-purgate-type: spam X-purgate-size: 2623 On 4/16/26 5:45 PM, Jan Beulich wrote: > On 16.04.2026 17:37, Oleksii Kurochko wrote: >> >> >> On 4/16/26 9:50 AM, Jan Beulich wrote: >>> On 10.04.2026 19:41, Andrew Cooper wrote: >>>> On 10/04/2026 4:45 pm, Oleksii Kurochko wrote: >>>>> diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c >>>>> index 7efa76fdbcb1..80f0e9ddae6a 100644 >>>>> --- a/xen/arch/riscv/time.c >>>>> +++ b/xen/arch/riscv/time.c >>>>> @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) >>>>> panic("%s: ACPI isn't supported\n", __func__); >>>>> >>>>> boot_clock_cycles = get_cycles(); >>>>> + >>>>> + /* set_xen_timer must have been set by sbi_init() already */ >>>>> + ASSERT(set_xen_timer); >>>>> + >>>>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >>>>> + { >>>>> + set_xen_timer = sstc_set_xen_timer; >>>>> + >>>>> + /* >>>>> + * A VS-timer interrupt becomes pending whenever the value of >>>>> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >>>>> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >>>>> + * ULONG_MAX. >>>>> + */ >>>>> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >>>>> +#ifdef CONFIG_RISCV_32 >>>>> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >>>>> +#endif >>>> >>>> You've got this pattern twice in this patch alone, and these aren't the >>>> only CSRs which are formed of pairs to get a 64bit value in 32bit mode. >>>> >>>> Sadly, the numbering isn't consistent for the high constant, but we can >>>> let the compiler do most of the hard work for us. >>>> >>>> #ifdef CONFIG_RISCV_32 >>>> # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) >>>> #else >>>> # define __csr_write32h(csr, val) (void)(csr, val) >>> >>> Just to mention: Since the comma is an operator here (not a lexical element >>> separating function arguments), more parenthesization may be needed for >>> Misra's sake. >> >> I will define it in the next way: >> >> # define __csr_write32h(csr, val) (void)((csr), (val)) > > Actually, yet more parentheses are needed: > > # define __csr_write32h(csr, val) ((void)((csr), (val))) It seems like (void) should be for (csr) and (val), so it should be: # define __csr_write32h(csr, val) ((void)(csr), (void)(val)) Otherwise the following compilation error occurs. ./arch/riscv/include/asm/csr.h:38:48: error: left-hand operand of comma expression has no effect [-Werror=unused-value] 38 | # define __csr_write32h(csr, val) ((void)((csr), (val))) ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 16 15:50:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 15:50:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283737.1565873 (Exim 4.92) (envelope-from ) id 1wDOyz-0000VA-4v; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1776354619-7D56BF3B-926FE146/0/0 X-purgate-type: clean X-purgate-size: 940 On Wed, Apr 01, 2026 at 01:24:51AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > Allow choosing which artifacts branch and job to use for Linux. This > allows running the same tests for different Linux versions, without > duplicating a lot of yaml sections. > > Similarly, make the repo path itself configurable too. The main purpose > is to ensure the test pipeline triggered from any repo will fetch linux > artifact from the right repo. But with a minor change of using that > variable for rootfs and microcode artifacts too, it allows testing > test-artifacts repo changes without needing to modify gitlab-ci.yml in > xen.git at all. > > Signed-off-by: Marek Marczykowski-G=C3=B3recki Reviewed-by: Anthony PERARD Thanks, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Thu Apr 16 16:08:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 16 Apr 2026 16:08:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283752.1565882 (Exim 4.92) (envelope-from ) id 1wDPFt-0003Sa-Ev; Thu, 16 Apr 2026 16:07:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1283752.1565882; Thu, 16 Apr 2026 16:07:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDPFt-0003ST-CO; Thu, 16 Apr 2026 16:07:49 +0000 Received: by outflank-mailman (input) for mailman id 1283752; Thu, 16 Apr 2026 16:07:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDPFr-0003SN-J9 for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 16:07:47 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDPFq-006PCN-WD for xen-devel@lists.xenproject.org; Thu, 16 Apr 2026 18:07:47 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e10952-bab6-0a2a0a5309dd-0a2a450880d4-0 for ; Thu, 16 Apr 2026 18:07:46 +0200 Received: from [209.85.221.47] (helo=mail-wr1-f47.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e10951-63b5-0a2a45080019-d155dd2fb96f-3 for ; Thu, 16 Apr 2026 18:07:46 +0200 Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-43d7605ec91so4275500f8f.3 for ; Thu, 16 Apr 2026 09:07:46 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5de7ede4-b14f-4a36-b06b-12bf768b52a8@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776355666-38766DB1-8608CF0D/0/0 X-purgate-type: clean X-purgate-size: 2879 On 16.04.2026 17:49, Oleksii Kurochko wrote: > > > On 4/16/26 5:45 PM, Jan Beulich wrote: >> On 16.04.2026 17:37, Oleksii Kurochko wrote: >>> >>> >>> On 4/16/26 9:50 AM, Jan Beulich wrote: >>>> On 10.04.2026 19:41, Andrew Cooper wrote: >>>>> On 10/04/2026 4:45 pm, Oleksii Kurochko wrote: >>>>>> diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c >>>>>> index 7efa76fdbcb1..80f0e9ddae6a 100644 >>>>>> --- a/xen/arch/riscv/time.c >>>>>> +++ b/xen/arch/riscv/time.c >>>>>> @@ -91,4 +90,23 @@ void __init preinit_xen_time(void) >>>>>> panic("%s: ACPI isn't supported\n", __func__); >>>>>> >>>>>> boot_clock_cycles = get_cycles(); >>>>>> + >>>>>> + /* set_xen_timer must have been set by sbi_init() already */ >>>>>> + ASSERT(set_xen_timer); >>>>>> + >>>>>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >>>>>> + { >>>>>> + set_xen_timer = sstc_set_xen_timer; >>>>>> + >>>>>> + /* >>>>>> + * A VS-timer interrupt becomes pending whenever the value of >>>>>> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >>>>>> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >>>>>> + * ULONG_MAX. >>>>>> + */ >>>>>> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >>>>>> +#ifdef CONFIG_RISCV_32 >>>>>> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >>>>>> +#endif >>>>> >>>>> You've got this pattern twice in this patch alone, and these aren't the >>>>> only CSRs which are formed of pairs to get a 64bit value in 32bit mode. >>>>> >>>>> Sadly, the numbering isn't consistent for the high constant, but we can >>>>> let the compiler do most of the hard work for us. >>>>> >>>>> #ifdef CONFIG_RISCV_32 >>>>> # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) >>>>> #else >>>>> # define __csr_write32h(csr, val) (void)(csr, val) >>>> >>>> Just to mention: Since the comma is an operator here (not a lexical element >>>> separating function arguments), more parenthesization may be needed for >>>> Misra's sake. >>> >>> I will define it in the next way: >>> >>> # define __csr_write32h(csr, val) (void)((csr), (val)) >> >> Actually, yet more parentheses are needed: >> >> # define __csr_write32h(csr, val) ((void)((csr), (val))) > > It seems like (void) should be for (csr) and (val), so it should be: > > # define __csr_write32h(csr, val) ((void)(csr), (void)(val)) > > Otherwise the following compilation error occurs. > > ./arch/riscv/include/asm/csr.h:38:48: error: left-hand operand of comma > expression has no effect [-Werror=unused-value] > 38 | # define __csr_write32h(csr, val) ((void)((csr), (val))) I was indeed wondering, but I did assume Andrew had checked his suggestion. Then again maybe it was only meant as an outline anyway. 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>>>>>>> >>>>>>> boot_clock_cycles = get_cycles(); >>>>>>> + >>>>>>> + /* set_xen_timer must have been set by sbi_init() already */ >>>>>>> + ASSERT(set_xen_timer); >>>>>>> + >>>>>>> + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) >>>>>>> + { >>>>>>> + set_xen_timer = sstc_set_xen_timer; >>>>>>> + >>>>>>> + /* >>>>>>> + * A VS-timer interrupt becomes pending whenever the value of >>>>>>> + * (time + htimedelta) is greater than or equal to vstimecmp CSR. >>>>>>> + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to >>>>>>> + * ULONG_MAX. >>>>>>> + */ >>>>>>> + csr_write(CSR_VSTIMECMP, ULONG_MAX); >>>>>>> +#ifdef CONFIG_RISCV_32 >>>>>>> + csr_write(CSR_VSTIMECMPH, ULONG_MAX); >>>>>>> +#endif >>>>>> You've got this pattern twice in this patch alone, and these aren't the >>>>>> only CSRs which are formed of pairs to get a 64bit value in 32bit mode. >>>>>> >>>>>> Sadly, the numbering isn't consistent for the high constant, but we can >>>>>> let the compiler do most of the hard work for us. >>>>>> >>>>>> #ifdef CONFIG_RISCV_32 >>>>>> # define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) >>>>>> #else >>>>>> # define __csr_write32h(csr, val) (void)(csr, val) >>>>> Just to mention: Since the comma is an operator here (not a lexical element >>>>> separating function arguments), more parenthesization may be needed for >>>>> Misra's sake. >>>> I will define it in the next way: >>>> >>>> # define __csr_write32h(csr, val) (void)((csr), (val)) >>> Actually, yet more parentheses are needed: >>> >>> # define __csr_write32h(csr, val) ((void)((csr), (val))) >> It seems like (void) should be for (csr) and (val), so it should be: >> >> # define __csr_write32h(csr, val) ((void)(csr), (void)(val)) >> >> Otherwise the following compilation error occurs. >> >> ./arch/riscv/include/asm/csr.h:38:48: error: left-hand operand of comma >> expression has no effect [-Werror=unused-value] >> 38 | # define __csr_write32h(csr, val) ((void)((csr), (val))) > I was indeed wondering, but I did assume Andrew had checked his suggestion. > Then again maybe it was only meant as an outline anyway. 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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1776355932-E13A0443-09EAAD9B/0/0 X-purgate-type: clean X-purgate-size: 845 On Wed, Apr 01, 2026 at 01:24:52AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build= .yaml > index b69bad9202c2..f4e277780311 100644 > --- a/automation/gitlab-ci/build.yaml > +++ b/automation/gitlab-ci/build.yaml > @@ -496,6 +520,7 @@ debian-bookworm-gcc-cppcheck: > > debian-bookworm-gcc-arm32-cppcheck: > extends: .gcc-arm32-cross-build > + <<: *build-test This jobs doesn't looks like it's used by any tests. The other looks probables, and I could start a pipeline, so no tests are missing the new rule. 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To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------fKtr6APMKplfqUUUg4ENHwUG" X-purgate-ID: tlsNG-4011c0/1776356039-46B778B7-9E7EA6AD/0/0 X-purgate-type: clean X-purgate-size: 15541 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------fKtr6APMKplfqUUUg4ENHwUG Content-Type: multipart/mixed; boundary="------------FoCuIYfAKM7AmMdOnB0smfE5"; protected-headers="v1" Message-ID: Date: Thu, 16 Apr 2026 12:13:34 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: --------------FoCuIYfAKM7AmMdOnB0smfE5 Content-Type: multipart/mixed; boundary="------------OSrLV2efYOWdGoySTNAye0Q0" --------------OSrLV2efYOWdGoySTNAye0Q0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/16/26 05:57, Christian K=C3=B6nig wrote: > On 4/16/26 01:27, Demi Marie Obenour wrote: >> Is it safe to assume that if a dmabuf exporter cannot handle >> non-revocable, pinned importers, it will fail the import? Or is >> using dma_buf_pin() unsafe if one does not know the exporter? >=20 > Neither. >=20 > dma_buf_pin() makes sure that the importer doesn't get any invalidation= notifications because the exporter moves the backing store of the buffer= around for memory management. >=20 > But what is still possible is that the exporter is hot removed, in whic= h case the importer should basically terminate it's DMA operation as soon= as possible. >=20 > GPU drivers usually reject pin requests to VRAM from DMA-buf importers = when that isn't restricted by cgroups for example, because that can other= wise easily result in a deny of service. >=20 > Amdgpu only recently started to allow pinning into VRAM to support RDMA= without ODP (I think it was ODP, but could be that I mixed up the RDMA t= hree letter code for that feature). >=20 >> For context, Xen grant tables do not support revocation. One can ask >> the guest to unmap the grants, but if the guest doesn't obey the only >> recourse is to ungracefully kill it. They also do not support page >> faults, so the pages must be pinned. Right now, grant tables don't >> support PCI BAR mappings, but that's fixable. >=20 > That sounds like an use case for the DMA-buf pin interface. >=20 >> How badly is this going to break with dGPU VRAM, if at all? I know >> that AMDGPU has a fallback when the BAR isn't mappable. What about >> other drivers? Supporting page faults the way KVM does is going to >> be extremely hard, so pinned mappings and DMA transfers are vastly >> preferable. >=20 > Well if you only want to share a fixed amount of VRAM then that is pret= ty much ok. >=20 > But when the client VM can trigger pinning on demand without any limita= tion you can pretty easily have deny of service against the host. That is= usually a rather bad idea. Is there a reasonable way to choose such an amount? Unless I am mistaken, client workloads are highly non-uniform: a single game or compute job might well use more VRAM than every other program on the system combined. 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Smith" , "xen-devel@lists.xenproject.org" Subject: RE: [PATCH v4 05/10] xen/domain: Add DOMCTL handler for claiming memory with NUMA awareness Thread-Topic: [PATCH v4 05/10] xen/domain: Add DOMCTL handler for claiming memory with NUMA awareness Thread-Index: AQHcpy8NKyz6wh/Wrk6CsdW/rK3ShrWf2LiAgAAdICCAQZUugIABBMnw Date: Thu, 16 Apr 2026 23:48:38 +0000 Message-ID: References: <7d439bb1-7381-4fa4-af79-423e8c7fafb1@suse.com> <589b36fe-946d-4a34-8227-a4dc558db304@suse.com> In-Reply-To: <589b36fe-946d-4a34-8227-a4dc558db304@suse.com> Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: LV3PR03MB7707:EE_|SA0PR03MB5658:EE_ x-ms-office365-filtering-correlation-id: 5c07b66d-2220-4ba5-a77a-08de9c12aec0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|366016|1800799024|376014|22082099003|38070700021|56012099003|18002099003; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fb6e16b3sm14578345e9.0.2026.04.17.00.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 00:24:34 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776410676; x=1777015476; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=g2D/0gDX5iLGL2+CnfFG8EhHTMrOO2S+Kr3prVGAwic=; b=EWegANMuLgHZV5O8e0zlpWF28wXmzK3/RaZvu0WiRsSBmjtokJO/OZrsjTb6uoG3YD ScjAfsCki45PD/8QPF6oVieEDn7zcEATGQWqkG7t00g9cWbk4roYUwMlR+E0BZOdafuC /p05OZxFnaYZVAM00TOrX+dKBYQ56hoKL7GFTJmef8Xf/SZNck+fEeFj8jg4CclovJbO A0B9xLqVdevWLHNyw2+5TZSztcSlNMNMFxDCrp3IGkvSSGnvW6VFuUtqEfHMs0EXlb1W E5wdcF/q/uavhUBHL+RE6HzAzOZTKZTPjuQSBd4Jnqy9HD7ynv8GqAS4iv1nWQlaLuSx UJHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776410676; x=1777015476; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=g2D/0gDX5iLGL2+CnfFG8EhHTMrOO2S+Kr3prVGAwic=; b=QVPWTxB3Uv7VjCkzXh5rXpqEVGuLhHHl4g+s27MhVF8wbLJFm47vZW7P8S2zab4WJO WHsbQZ2FaVdOvAy/CV3LGpaK6e66n2Guhuor24B3sh7DPWlXDNxNJ1Vwsy/D/gbqdchk EoCxHeZAf2+YaC8tq5mJAMt+HMZM/O0h6QGfYVPJXR3Ng9Xe90ta27k2g2U3XFT+6NJI w/8wpNVX+yHHglzFLrNGyAXI5ttP8DYyAsfZz3DYKlgfhJF+HpsDmsuqcNds+MZPnh9Q rfb/ZuNqR5FTxLk8iWOi1hxvXEH3MWK4PFE/1pp+pHHAmlavNe5CQr4TDfPTJiPYycWW CWrg== X-Gm-Message-State: AOJu0YyFaTw+e7tq2VlJw7gcoZhR/WOwAJPmmX1n/BpAbJP5mQPVKUHO 4AYO62bDOruOhjmZMJGnIXKNXcNwpcBMsy2yuKVXEzJ6NQkFOFMWZfF7JqYFNA== X-Gm-Gg: AeBDiesbmvV7n8oblEVbdjg6dlOUten3U7ZH79tzSJdYbsk7H7n2ZPBZpAdtF3rBl6f hAVk+qJ5G4Aaori8BiQszfR7aj3aGT483TD51i3iNt9OzrKhImoVUU5Oiaq2ngckCGx1aB7YPNL RBH93EkTdwLfKlKWZe2zjQ7ujSjBzhJnEtDpBxE93c9sfoHUILUBIOZ4Q29szkjKhZOygE9ZKt9 S1ecC6Y1uNi4LBvpEn68YjExrrLQBALe/2csGAU7o88LiW0Zs1qjfnBC/VvkF9WD+2P3AE6WkrY 9XUAXUqrXy35Qn98ygBjelmnHzwoWYkA5E+r12Qxh6yAQcVt0OQhiX9WQMxhywJBL2l00f1DvTn SAjhS3PMXdvl7t/DBYK/sEd7mKhrrMnl6oOJIBzsSM7O01IjuLD+wZAfzQ1Zv6ywlIY+l6LFRiO uWwnl5GW3fLOrvaPfs+T4RwOEQ/enfCMH2kVxYeVdD7TnqhATF4dj0NU5C3pXMp/syyLrMLljxj T7whYj7g5kIX5M= X-Received: by 2002:a05:600c:5246:b0:487:219e:42d with SMTP id 5b1f17b1804b1-488fb750a1dmr22851325e9.11.1776410675594; Fri, 17 Apr 2026 00:24:35 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4] xen/riscv: allow Xen to use SSTC while hiding it from guests Date: Fri, 17 Apr 2026 09:24:26 +0200 Message-ID: <5285075f24cd2a2c5566b2a7724198d34aab51c5.1776354739.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1776410676-42B70A53-66B3954F/10/73395122804 X-purgate-type: spam X-purgate-size: 13888 OpenSBI currently does not advertise the SSTC extension via the device tree, so if SSTC support is detected by Xen the riscv_isa bitmap is updated manually. Furthermore, removing the "sstc" string from riscv,isa is not a reliable way to disable SSTC, because OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. Note: clearing RISCV_ISA_EXT_sstc from the DTS riscv,isa property is deferred to a follow-up patch. Also, the corresponding HENVCFG bit is not set so guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. Drop sbi_set_timer() as it is more than enough to have only introduced set_xen_timer(). Drop "SBI v0.2 TIME extension detected" message to avoid confusion which set timer function is really used. Signed-off-by: Oleksii Kurochko ---- Changes in v4: - Introduce csr_write64() and __csr_write32h(). - Sort numericaly definitions of CSR_VSTIMECMP{H}. --- Changes in v3: - Reword print message when SSTC extension is detected. - s/__clear_bit/__set_bit() for the case when SSTC is detected in riscv_fill_hwcap(). Update also the comment above __set_bit(). - Drop BUG_ON()s in vtimer.c. - s/printk/dprintk for the message: SSTC detected... - Drop sbi_set_timer global variable, it is enough just to have set_xen_timer. - As we set bit in riscv_isa bitmap there is no need to use csr_read_safe(CSR_STIMECMP) second time. - Move init of CSR_VSTIMECMP in preinit_xen_time as it looks more correct place. - Update the commit message. --- Changes in v2: - Minor style fixes. - Drop from vcpu_csr_init() setting of SSTC bit in HENVCFG register. Add it back when SSTC for guests will be available. - Add static to set_xen_timer function pointer. - Refactor sstc_set_xen_timer(). - s/csr_allowed_read/csr_read_safe() --- xen/arch/riscv/cpufeature.c | 18 +++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/csr.h | 14 +++++++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + xen/arch/riscv/include/asm/sbi.h | 18 --------- xen/arch/riscv/include/asm/time.h | 3 ++ xen/arch/riscv/sbi.c | 29 +++++++++++--- xen/arch/riscv/time.c | 42 +++++++++++++-------- xen/arch/riscv/vtimer.c | 1 + 9 files changed, 89 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..92235fdfd5ab 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include #include +#include #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_ext[] = { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount = ARRAY_SIZE(required_extensions); bool all_extns_available = true; + unsigned long tmp; riscv_fill_hwcap_from_isa_string(); @@ -495,6 +498,21 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + dprintk(XENLOG_DEBUG, + "SSTC detected; supported for Xen use, but not for guests\n"); + + /* + * As there is no any guarantee that SSTC will be added to riscv,isa + * property by OpenSBI(it doesn't add it now) or whatever ran before + * Xen, it is needed to set this bit manually. + * + * Guest isolation is maintained by not setting ENVCFG_STCE in henvcfg. + */ + __set_bit(RISCV_ISA_EXT_sstc, riscv_isa); + } + for ( i = 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext = required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h index 27d4b7942f6b..9dc5f8767508 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -32,6 +32,20 @@ : "memory" ); \ }) +#ifdef CONFIG_RISCV_32 +# define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) +#else +# define __csr_write32h(csr, val) ((void)(csr), (void)(val)) +#endif + +#define csr_write64(csr, val) \ +({ \ + uint64_t _v = (val); \ + \ + csr_write(csr, _v); \ + __csr_write32h(csr, _v); \ +}) + #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/include/asm/riscv_encoding.h index dd15731a86fa..03e186bcdb8c 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -395,6 +395,8 @@ #define CSR_VSCAUSE 0x242 #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d #define CSR_VSATP 0x280 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/sbi.h index ed7af200288f..1952868e963c 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,7 +13,6 @@ #define ASM__RISCV__SBI_H #include -#include /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -139,23 +138,6 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); -/* - * Programs the clock for next event at (or after) stime_value. stime_value is - * in absolute time. This function must clear the pending timer interrupt bit - * as well. - * - * If the supervisor wishes to clear the timer interrupt without scheduling the - * next timer event, it can either request a timer interrupt infinitely far - * into the future (i.e., (uint64_t)-1), or it can instead mask the timer - * interrupt by clearing sie.STIE CSR bit. - * - * The stime_value parameter represents absolute time measured in ticks. - * - * This SBI call returns 0 upon success or an implementation specific negative - * error code. - */ -extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); - /* * Initialize SBI library * diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h index be3875b9984e..4d68900151a7 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -4,6 +4,7 @@ #include #include +#include #include @@ -26,6 +27,8 @@ static inline cycles_t get_cycles(void) void preinit_xen_time(void); +extern int (* __ro_after_init set_xen_timer)(uint64_t deadline); + #endif /* ASM__RISCV__TIME_H */ /* diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index b4a7ae6940c1..3576e26033a5 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -22,6 +22,7 @@ #include #include +#include static unsigned long __ro_after_init sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; @@ -249,6 +250,21 @@ static int (* __ro_after_init sbi_rfence)(unsigned long fid, unsigned long arg4, unsigned long arg5); +/* + * Programs the clock for next event at (or after) stime_value. stime_value is + * in absolute time. This function must clear the pending timer interrupt bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without scheduling the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific negative + * error code. + */ static int cf_check sbi_set_timer_v02(uint64_t stime_value) { struct sbiret ret; @@ -264,6 +280,10 @@ static int cf_check sbi_set_timer_v02(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } +/* + * Legacy SBI v0.1 SET_TIMER; functionally equivalent to sbi_set_timer_v02 + * from Xen's perspective. + */ static int cf_check sbi_set_timer_v01(uint64_t stime_value) { struct sbiret ret; @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; - int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -360,10 +378,9 @@ int __init sbi_init(void) } if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) - { - sbi_set_timer = sbi_set_timer_v02; - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); - } + set_xen_timer = sbi_set_timer_v02; + else + set_xen_timer = sbi_set_timer_v01; } else panic("Ooops. SBI spec version 0.1 detected. Need to add support"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 698ab49d1292..8769709e5227 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,12 +7,21 @@ #include #include +#include #include -#include unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write64(CSR_STIMECMP, deadline); + + return 0; +} + +int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks = get_cycles() - boot_clock_cycles; @@ -61,20 +70,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <= now ) return 0; - /* - * TODO: When the SSTC extension is supported, it would be preferable to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementation. - * For example, it is not ideal to panic() if sbi_set_timer() returns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc = sbi_set_timer(deadline)) ) + if ( (rc = set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); /* Enable timer interrupt */ @@ -91,4 +87,20 @@ void __init preinit_xen_time(void) panic("%s: ACPI isn't supported\n", __func__); boot_clock_cycles = get_cycles(); + + /* set_xen_timer must have been set by sbi_init() already */ + ASSERT(set_xen_timer); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) + { + set_xen_timer = sstc_set_xen_timer; + + /* + * A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CSR. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + */ + csr_write64(CSR_STIMECMP, ULONG_MAX); + } } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..d5a8dfcb2edb 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include +#include #include static void vtimer_expired(void *data) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 07:54:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 07:54:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1283992.1565948 (Exim 4.92) (envelope-from ) id 1wDe1e-0006FA-0m; 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Or is >>> using dma_buf_pin() unsafe if one does not know the exporter? >> >> Neither. >> >> dma_buf_pin() makes sure that the importer doesn't get any invalidation notifications because the exporter moves the backing store of the buffer around for memory management. >> >> But what is still possible is that the exporter is hot removed, in which case the importer should basically terminate it's DMA operation as soon as possible. >> >> GPU drivers usually reject pin requests to VRAM from DMA-buf importers when that isn't restricted by cgroups for example, because that can otherwise easily result in a deny of service. >> >> Amdgpu only recently started to allow pinning into VRAM to support RDMA without ODP (I think it was ODP, but could be that I mixed up the RDMA three letter code for that feature). >> >>> For context, Xen grant tables do not support revocation. One can ask >>> the guest to unmap the grants, but if the guest doesn't obey the only >>> recourse is to ungracefully kill it. They also do not support page >>> faults, so the pages must be pinned. Right now, grant tables don't >>> support PCI BAR mappings, but that's fixable. >> >> That sounds like an use case for the DMA-buf pin interface. >> >>> How badly is this going to break with dGPU VRAM, if at all? I know >>> that AMDGPU has a fallback when the BAR isn't mappable. What about >>> other drivers? Supporting page faults the way KVM does is going to >>> be extremely hard, so pinned mappings and DMA transfers are vastly >>> preferable. >> >> Well if you only want to share a fixed amount of VRAM then that is pretty much ok. >> >> But when the client VM can trigger pinning on demand without any limitation you can pretty easily have deny of service against the host. That is usually a rather bad idea. > > Is there a reasonable way to choose such an amount? Not really. > Unless I am > mistaken, client workloads are highly non-uniform: a single game or > compute job might well use more VRAM than every other program on the > system combined. Yeah, perfectly correct. > Are these workloads impossible to make work well with pinning? No, as long as you don't know the workload beforehand, e.g. when you define the limit. I mean that's why basically everybody avoids pinning and assigning fixed amounts of resources. Even if you can make it work technically pinning usually results in a rather bad end user experience. Regards, Christian. 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Add support for generating an IMSIC node when >>>> building the guest DT. >>>> >>>> Keep a reference to the host IMSIC DT node and reuse its compatible >>>> property while constructing the guest-visible node. >>> >>> Again raises a migration concern. Presumably a guest would then be able >>> to migrate only to other hosts with the same compatible property. >> >> Right, but I don't think we can do too much and it is the simplest >> approach just to migrate to hosts with the same compatible property. >> >> If you concern is about DTS property then for IMSIC it will be always >> riscv,imsics according to the RISC-V DT spec. (IIRC, the only other >> option could be qemu,riscv). Actually, I can just hard code >> "riscv,imsic" explicitly instead of re-using of host name. >> >> If your concern is that we will migrate to a host which doesn't support >> IMSIC at all then we should or (a) don't migrate to such host or (b) >> provide an emulation of IMSIC. And option (b) would be terrible from at >> least performance point of view. > > That would all be only a secondary concern - in an IMSIC is needed right > now, so be it. My primary concern is with inheriting the host IMSIC's > properties. Could we do really something better? At the moment, the following properties are inhereted: node name -> not an issue at all, it is just a name of the node and generally doesn't matter what it is in the matter of DTB generation as phandle number of this node will be used as pointer to this node, not the name. If it would be better I can hard code just "imsic". compatible -> also, not a big issue. According to current DT RISC-V bindings it could be just "riscv,imsic". But then I have the question what if one day someone will come up with own implementation of IMSIC then "riscv,own-imsic" will be in host DTB and so I expect that guest DTB should have it as this h/w expects to use specifically OWN-IMSIC driver. So it seems okay to copy compatible from host DTB. Yes, if migration will happen where just "riscv,imsic" is supported then it can't be easily migrated to such h/w and its okay. But generally I expect that compatible will always riscv,imsic. riscv,num-ids -> generally, it could be any number from [63, 2047], but it seems like there is no any sense if put a value bigger then guest-num-ids=min(riscv,num-ids, riscv,num-guest-ids) for guest as h/w can't support more then that. At the same time I don't see too much sense to tell a guest that it supports less then guest-num-ids. What is the problem to give a guest a maximum that IMSIC could provide? With migration, of course, it will be an issue if new host will support different number of riscv,num-ids but I don't know what we can do better then just avoid migration to such hosts if old-num-ids > new-num-ids without significant performance drop. As an summary it is okay IMO to re-use these host properties. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 08:27:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 08:27:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284033.1565971 (Exim 4.92) (envelope-from ) id 1wDeY1-00033D-7L; Fri, 17 Apr 2026 08:27:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284033.1565971; Fri, 17 Apr 2026 08:27:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDeY1-000336-4O; Fri, 17 Apr 2026 08:27:33 +0000 Received: by outflank-mailman (input) for mailman id 1284033; Fri, 17 Apr 2026 08:27:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDeXz-000330-Qs for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776414449; x=1776674949; i=anthony.perard@vates.tech; bh=p3fjiuwfEK2kqAivumZFHwViDj4gbcyHBsUQ9+3dGDE=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=grGijPalEVVQxzdMg/cygjHALXHktuZCyhczeyuf2UxHNbm7twhF2DFJ5DcMW/7DU Jz2EdMUXbDIKBshw4SEPfW+cB6uCraDECTWTzT+ycOxzK0rH8SQ06zYx4O6tSOorxZ t8K21fL0M1bbzWfk85HItnDXPHXKuGDayvA4pPTbOqk1ZVeSE05GmDoAOahzlyfuYr FEs4BRoD+qr4oE7BeN7Y3sc6NVAUzCSI1RXznNd5vRzMGo4YC01BSYsxaOxWcsE9lN XnNxJhHHZbHeZ4rT/dExzU3YrOOX9YWges8Dbpa90dz/cgMUOuv9/w4Abyhqll/U+V rrLP/7Vf9exPQ== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20v7]=20xen/domain:=20introduce=20DOMID=5FANY?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776414444332 To: dmukhin@ford.com Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org Message-Id: References: <20260408234046.1314021-1-dmukhin@ford.com> In-Reply-To: <20260408234046.1314021-1-dmukhin@ford.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.d79241642dce4e9989a7f4075f540953?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260417:md Date: Fri, 17 Apr 2026 08:27:29 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776414451-29D7B938-2A7DF26C/0/0 X-purgate-type: clean X-purgate-size: 788 On Wed, Apr 08, 2026 at 04:40:46PM -0700, dmukhin@ford.com wrote: > From: Denis Mukhin > > Add a new symbol DOMID_ANY to improve the readability of the code. > > Update all relevant domid_alloc() call sites and harden the domid_alloc() > input value check. > > Also, fix problem with passing invalid domain IDs in > XEN_DOMCTL_createdomain: turns out libxl__domain_make() (toolstack) > uses 0xffff as domain ID. > > Amends: 2d5065060710 ("xen/domain: unify domain ID allocation") > Signed-off-by: Denis Mukhin Reviewed-by: Anthony PERARD And I believe stefano's review would still apply, right? Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 17 08:57:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 08:57:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284050.1565980 (Exim 4.92) (envelope-from ) id 1wDf1B-0006vY-D1; Fri, 17 Apr 2026 08:57:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284050.1565980; Fri, 17 Apr 2026 08:57:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDf1B-0006vR-AC; Fri, 17 Apr 2026 08:57:41 +0000 Received: by outflank-mailman (input) for mailman id 1284050; Fri, 17 Apr 2026 08:57:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDf1A-0006vL-0n for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776416257; x=1776676757; i=anthony.perard@vates.tech; bh=DW2l/jc+ZEcxNJuiNNbXqKEtvirgVWtkF8VjCPX3hh4=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Gp5wfOtHgiSAk3yA568oHC1o4YiofkHKaBTYC4a8Fm4bZOdaCqjYbvLwARcHVIfWO EHlEJ/siS/wDnIZfF5N+SNEJnJYI0kyC7y7eyQztz1yA96LQOcDaXzV1EJPkNZ7lMe 4+LJxrOWz0fO6Rvj5hmIozJuiXdezTbVnEGLxtnnZHrLT4CTeJeVsLmYi0O8du8JB/ P4mCSbhZncXC7F/AHeXqAS2oAjmucE3g56K5CR7bg+tkHjk7Hozotws+Ldz4C4JRW4 P8OUnZwU5vJp9DPPyd02pQFpqY4M1dk+yEpCsiMhiJ38AFxAr6Hvi7fBaj1HkaGmKY k+eDKFZeJ4twA== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20v10]=20xenpm:=20Add=20get-core-temp=20subcommand?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776416256345 To: "Teddy Astie" Cc: xen-devel@lists.xenproject.org, "Oleksii Kurochko" , "Community Manager" Message-Id: References: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> In-Reply-To: <22bcde2914c0303b2c594485542af19d2952e782.1775570823.git.teddy.astie@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.5bc42f588c204b238698d215908a218c?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260417:md Date: Fri, 17 Apr 2026 08:57:37 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1776416259-B3762161-4279913A/0/0 X-purgate-type: clean X-purgate-size: 774 On Tue, Apr 07, 2026 at 02:10:37PM +0000, Teddy Astie wrote: > + for ( cpu =3D 0; cpu < max_cpu_nr; cpu +=3D physinfo.threads_per_cor= e ) > + { > + if ( fetch_dts_temp(xc_handle, cpu, false, &temp) ) > + { > + fprintf(stderr, "[CPU%d] Unable to fetch temperature (%d - %= s)\n", > + cpu, errno, strerror(errno)); > + continue; > + } > + A trailing whitespace was introduced here since v9. > + has_data =3D true; > + printf("CPU%d: %d=C2=B0C\n", cpu, temp); > + } Beside that, patch looks good to me now: Reviewed-by: Anthony PERARD Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 17 09:01:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 09:01:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284062.1565988 (Exim 4.92) (envelope-from ) id 1wDf53-0008SO-Vz; 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>> >> I am not sure that it can be different from what host has. >> >>> Shouldn't the number of interrupts (aiui that's the "number of cells" >>> here) a guest gets be independent from the host it runs one? >> >> The #interrupt-cells property specifies how many 32-bit values (cells) >> are used to encode a single interrupt specifier when referencing this >> interrupt controller from another device node. >> In this APLIC schema, it's fixed at const: 2, meaning every interrupt >> reference requires exactly two cells — typically: >> >> Cell 1 — the interrupt source number (which of the riscv,num-sources >> wired inputs) >> Cell 2 — the interrupt type/trigger flags (e.g. edge vs. level, active >> high/low) > > So what if #interrupt-cells is 3 in the DT Xen is handed? If Xen can > cope, should that value really also be handed through to guests? I would say that it depends on what cell 3 will represent. But likely it will be needed to hand it to the guest. > >>>> + regs = dt_get_property(aplic_node, "reg", &len); >>>> + if ( !regs ) >>>> + { >>>> + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); >>>> + return -FDT_ERR_XEN(ENOENT); >>>> + } >>>> + >>>> + res = fdt_property(fdt, "reg", regs, len); >>>> + if ( res ) >>>> + return res; >>>> + >>>> + data = dt_get_property(aplic_node, "riscv,num-sources", &len); >>>> + if ( !data ) >>>> + { >>>> + printk("%s: Can't find 'riscv,num-sources' property\n", >>>> + aplic_node->full_name); >>>> + return -FDT_ERR_XEN(ENOENT); >>>> + } >>>> + >>>> + res = fdt_property(fdt, "riscv,num-sources", data, len); >>>> + if ( res ) >>>> + return res; >>> >>> Or maybe this is the number of interrupts? >> >> This is the total count of hardware interrupt lines wired into this >> APLIC domain. >> >> It could be independent from the host it runs one but looking at the >> possible range [1,1023] for this property if we will put for a guest >> lets say 22 but new host support only 20 when we will be in a trouble >> anyway. > > Correct. But if you had some hosts with 1024 and some with 256, how > would you bring up a guest on the former to later be able to migrate > it to one of the latter when guests inherit the count from the host? It will be impossible to do that without emulation, so I expect it will be easier to simply forbid migration to such a host. Basically, it is just a game of numbers. We could try to estimate how many interrupts are needed for the guest, or for simplicity use some hard-coded number (say 128 or 256, something “pretty small”). Will it resolve the migration issue? Partially yes, but not fully, as there could always be cases where the new host’s number of sources is lower than our hard-coded “small guest value.” So having a smaller value will likely help on average and will allow to support more h/w migration to which could happen, but the migration issue will still be present. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 09:11:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 09:11:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284076.1565998 (Exim 4.92) (envelope-from ) id 1wDfEi-0001qy-0G; Fri, 17 Apr 2026 09:11:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284076.1565998; Fri, 17 Apr 2026 09:11:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDfEh-0001qr-TQ; Fri, 17 Apr 2026 09:11:39 +0000 Received: by outflank-mailman (input) for mailman id 1284076; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YyzHTxFnjxjJN0nWg+DGsr86lgb1ay66CJY/qx6Sc5/jagFxYibOmqtOYtR8n5ERyLmULrW+7sCC5u1mojpe0QVWnzo/ZtPNtOxC7fl3f097glCkX/XCwHGUXaFS9q+ny93UUA94s2N2QDZEfhICjuGgiywKJEWxK+bKxjfI7vF88DRTP2dxU23vynHNHxF/kNOyD+nnYWOjE5PUgj7vixiBwmyLCuzjCes+KDeg8d88WjPmULZQ4X56p66diLyiwUwc1VZMm2zwv4gSfMOjbtAYAojTQqPiyreUjgMkrOpbFuHaaneGAqM984GEOLqApOK7RK2ANJR728x1C3PtHBft+qP27bGfbLJn0MmgzmRo9BxI16cOvA2XpIfx2s4R6ds1ns3cj9fY05eokWaQiaZa8KsVzRL7BOEQWQf2GclhFHRyFYE4vmFWkEEVDUUv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2026 09:11:31.1443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 665f9581-10c9-4707-1bd9-08de9c6150a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV5PR12MB9802 X-purgate-ID: tlsNG-16d1c6/1776417098-50158D75-DFCA6778/0/0 X-purgate-type: clean X-purgate-size: 9600 Refactor setup_frametable_mappings() into init_frametable(), modeled after x86's implementation. Instead of mapping one contiguous frametable covering ram_start to ram_end (including holes), iterate the pdx_group_valid bitmap to allocate and map frametable memory only for valid PDX groups, skipping gaps in the physical address space. At the moment we don't really take into account pdx_group_valid bitmap. This reduces memory consumption on systems with sparse RAM layouts by not allocating frametable entries for non-existent memory regions. A file-local pdx_to_page() override is needed because the generic macro in xen/include/xen/pdx.h does not account for ARM's non-zero frametable_base_pdx. Update the MPU implementation to match the new init_frametable() signature. Since MPU has no virtual address translation (ma == va), hole-skipping is not possible and the frametable remains a single contiguous allocation. Signed-off-by: Michal Orzel --- We've been using this approach at AMD for a while now. Without this we would not be able to boot some of our boards that have huge holes in the PA space, so I consider this patch a great improvement. Two things to consider as a follow-up in the future: - change generic pdx_to_page, page_to_pdx to take into account offset that on x86 is zero but on other arches it is not. The page list code is for now unaffected because the offset cancels out, - use the same on RISCV. --- xen/arch/arm/arm32/mmu/mm.c | 3 +- xen/arch/arm/include/asm/mm.h | 4 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/mm.c | 77 ++++++++++++++++++++++++----------- xen/arch/arm/mpu/mm.c | 23 ++++++----- 5 files changed, 70 insertions(+), 39 deletions(-) diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c index 5e4766ddcf65..0b595baa11b3 100644 --- a/xen/arch/arm/arm32/mmu/mm.c +++ b/xen/arch/arm/arm32/mmu/mm.c @@ -178,8 +178,7 @@ void __init setup_mm(void) setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages); - /* Frame table covers all of RAM region, including holes */ - setup_frametable_mappings(ram_start, ram_end); + init_frametable(ram_start); /* * The allocators may need to use map_domain_page() (such as for diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 72a692862420..2eb8465aa904 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -196,8 +196,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr); extern void remove_early_mappings(void); /* Prepare the memory subystem to bring-up the given secondary CPU */ extern int prepare_secondary_mm(int cpu); -/* Map a frame table to cover physical addresses ps through pe */ -extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); +/* Map a frame table */ +void init_frametable(paddr_t ram_start); /* Helper function to setup memory management */ void setup_mm_helper(void); /* map a physical range in virtual memory */ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6df8b616e464..e6b651956927 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -62,7 +62,7 @@ void __init setup_mm(void) setup_mm_helper(); - setup_frametable_mappings(ram_start, ram_end); + init_frametable(ram_start); init_staticmem_pages(); init_sharedmem_pages(); diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c index 6604f3bf4e6a..4b4da349c16c 100644 --- a/xen/arch/arm/mmu/mm.c +++ b/xen/arch/arm/mmu/mm.c @@ -8,16 +8,37 @@ #include #include -/* Map a frame table to cover physical addresses ps through pe */ -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) +#undef pdx_to_page +#define pdx_to_page(pdx) gcc11_wrap(frame_table + ((pdx) - frametable_base_pdx)) + +static void __init +init_frametable_chunk(unsigned long pdx_s, unsigned long pdx_e) { - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) - - mfn_to_pdx(maddr_to_mfn(ps)) + 1; - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); - mfn_t base_mfn; - const unsigned long mapping_size = frametable_size < MB(32) ? MB(2) - : MB(32); + unsigned long nr_pdxs = pdx_e - pdx_s; + unsigned long chunk_size = nr_pdxs * sizeof(struct page_info); + const unsigned long mapping_size = chunk_size < MB(32) ? MB(2) : MB(32); + unsigned long virt; int rc; + mfn_t base_mfn; + + /* Round up to 2M or 32M boundary, as appropriate. */ + chunk_size = ROUNDUP(chunk_size, mapping_size); + base_mfn = alloc_boot_pages(chunk_size >> PAGE_SHIFT, 32 << (20 - 12)); + + virt = (unsigned long)pdx_to_page(pdx_s); + rc = map_pages_to_xen(virt, base_mfn, chunk_size >> PAGE_SHIFT, + PAGE_HYPERVISOR_RW | _PAGE_BLOCK); + if ( rc ) + panic("Unable to setup the frametable mappings\n"); + + memset(pdx_to_page(pdx_s), 0, nr_pdxs * sizeof(struct page_info)); + memset(pdx_to_page(pdx_e), -1, + chunk_size - nr_pdxs * sizeof(struct page_info)); +} + +void __init init_frametable(paddr_t ram_start) +{ + unsigned int sidx, nidx, max_idx; /* * The size of paddr_t should be sufficient for the complete range of @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); - if ( frametable_size > FRAMETABLE_SIZE ) - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", - ps, pe); + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); - /* Round up to 2M or 32M boundary, as appropriate. */ - frametable_size = ROUNDUP(frametable_size, mapping_size); - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); + /* + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of + * PAGE_SIZE by construction. + */ + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, - frametable_size >> PAGE_SHIFT, - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); - if ( rc ) - panic("Unable to setup the frametable mappings.\n"); + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) + panic("Frametable too small\n"); + + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) + { + unsigned int eidx; + + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); + + if ( nidx >= max_idx ) + break; + + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); + } - memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info)); - memset(&frame_table[nr_pdxs], -1, - frametable_size - (nr_pdxs * sizeof(struct page_info))); + init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx); } /* diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index aff88bd3a9c1..9c568831c128 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned int attributes) return 0; } -/* Map a frame table to cover physical addresses ps through pe */ -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) +/* + * Allocate a contiguous frame table covering ram_start through max_pdx. + * Unlike the MMU version, MPU cannot skip holes because there is no virtual + * address translation (ma == va). + */ +void __init init_frametable(paddr_t ram_start) { + unsigned long nr_pdxs, frametable_size; mfn_t base_mfn; - paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE); - paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE); - - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) - - mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1; - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); /* * The size of paddr_t should be sufficient for the complete range of @@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); + nr_pdxs = max_pdx - frametable_base_pdx; + frametable_size = nr_pdxs * sizeof(struct page_info); + if ( frametable_size > FRAMETABLE_SIZE ) - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", - ps, pe); + panic("Frametable too small\n"); - frametable_base_pdx = paddr_to_pdx(aligned_ps); frametable_size = ROUNDUP(frametable_size, PAGE_SIZE); base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 09:12:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 09:12:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284085.1566006 (Exim 4.92) (envelope-from ) id 1wDfFK-0002Kr-92; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Luca Fancellu Subject: [PATCH] device-tree: Improve hwdom memory allocation for DMA Date: Fri, 17 Apr 2026 11:11:55 +0200 Message-ID: <20260417091155.39653-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|BL3PR12MB6572:EE_ X-MS-Office365-Filtering-Correlation-Id: afb89aad-3684-4fff-6c01-08de9c6166f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: FDjdiMBzpJuv3LAF2f3WMi1e+LE42zrgYf8RDJP9oK7voHOrV8dNnV1aV3cn5qseI+YhpbA+0Xuq1IkD1eAUhy9pVlJxg/o3O4x0Ink+ArxrfVHver4wuwH6DME4MyWc1vkcs1/NDhll9frYvgsFdoQLdBbUGn3Dd0lD7obm2A4L5c51l4kGkUDkehPN1XHe587yVbpfRNU4e/kX/IAklOI+ZHV8CBXEly5fJVloPTId45df2nKQkMj+XVw5RA6QZBNiMu0+6MNmjcCiEi9RbIRFWRsP4tpRWx0wgbNFkg+NJ2y4qCl0OjNNVawBzQciWoC14eBw5zJsPGoO7q7fBLm/ZgZ1/3obn6Xp4a2hBd+SMfnf9CRWHqb2BHjrSk11Hz9ykbWJT+lYsF9MEyUyiJiVsZNIv9Kxgq8nJDesyN5RUZG7XVIBMK8+AooHWIEdvnhfG3LdFk0HEk4VGWc4bHbSz6H7AuA8M9PnS3tojSi1o3q1REeECANYEuzVbVrSUhzffSmoHlyyu6IH3KS/UKCPFhLOiUz0v3mocJVsS9ee21/mTlUc48vCE0HYEpuud4YLUc45XhWmW7uuQgnbUUnRBNSq8zpqN35IahhPTpKhpFKxFU4R+pY8H0FvlzrwR86kGAeM3yMVb76aQ4AwzsWUgoFVTTZFzKBY91kd/9Yb/fMSj2Zww7bsyFch5TUS+dJ/7Espw17fXVmOz3/pE0VEXEtUNbrqJzkiQZ/lkSlke7FDvzYs2Z80e7bIcvU9s+9n9+AJj2wnNDJSceEXRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(18002099003)(56012099003);DIR:OUT;SFP:1101; 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The previous code sorted these regions by descending size, which usually causes high-address memory to be allocated first. All allocated memory could reside above 4 GB leaving DMA non-functional for devices with limited addressing capabilities. Improve the handling as follows: - Sort free regions by ascending address instead of descending size, so low-memory banks are allocated first, - Skip banks smaller than 128 MB (or the total remaining allocation, whichever is less) until the first bank is placed, ensuring place_modules() has enough contiguous space, - Extract the hardware domain allocation path into its own function (allocate_hwdom_memory) for clarity. Signed-off-by: Michal Orzel --- xen/common/device-tree/domain-build.c | 152 ++++++++++++++++---------- 1 file changed, 96 insertions(+), 56 deletions(-) diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree/domain-build.c index 540627b74e96..c51520ebadf9 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -133,9 +133,9 @@ static int __init add_hwdom_free_regions(unsigned long s_gfn, e += 1; size = (e - start) & ~(SZ_2M - 1); - /* Find the insert position (descending order). */ - for ( i = 0; i < free_regions->nr_banks ; i++ ) - if ( size > free_regions->bank[i].size ) + /* Find the insert position (ascending address order). */ + for ( i = 0; i < free_regions->nr_banks; i++ ) + if ( start < free_regions->bank[i].start ) break; /* Move the other banks to make space. */ @@ -234,82 +234,123 @@ out: return res; } -void __init allocate_memory(struct domain *d, struct kernel_info *kinfo) +/* + * Allocate memory for the hardware domain using the host memory layout, when + * the domain is not direct mapped. The only case for this is when LLC coloring + * is enabled. + * + * Banks are sorted by ascending address from add_hwdom_free_regions(), so + * low memory banks are naturally allocated first (if any). This allows the + * hardware domain to have memory reachable by devices with limited DMA address + * capabilities (e.g. 32-bit DMA). + * + * The first bank allocated must be large enough for place_modules() to fit + * the kernel, DTB and initrd. + */ +static bool __init allocate_hwdom_memory(struct kernel_info *kinfo) { + const paddr_t min_bank_size = + min_t(paddr_t, kinfo->unassigned_mem, MB(128)); struct membanks *mem = kernel_info_get_mem(kinfo); - unsigned int i, nr_banks = GUEST_RAM_BANKS; - struct membanks *hwdom_free_mem = NULL; - - printk(XENLOG_INFO "Allocating mappings totalling %ldMB for %pd:\n", - /* Don't want format this as PRIpaddr (16 digit hex) */ - (unsigned long)(kinfo->unassigned_mem >> 20), d); + unsigned int i, nr_banks; + struct membanks *hwdom_free_mem; + struct membanks *gnttab = + IS_ENABLED(CONFIG_GRANT_TABLE) + ? membanks_xzalloc(1, MEMORY) + : NULL; - mem->nr_banks = 0; /* - * Use host memory layout for hwdom. Only case for this is when LLC coloring - * is enabled. + * Exclude the following regions: + * 1) Remove reserved memory + * 2) Grant table assigned to hwdom */ - if ( is_hardware_domain(d) ) - { - struct membanks *gnttab = - IS_ENABLED(CONFIG_GRANT_TABLE) - ? membanks_xzalloc(1, MEMORY) - : NULL; - /* - * Exclude the following regions: - * 1) Remove reserved memory - * 2) Grant table assigned to hwdom - */ - const struct membanks *mem_banks[] = { - bootinfo_get_reserved_mem(), - gnttab, - }; + const struct membanks *mem_banks[] = { + bootinfo_get_reserved_mem(), + gnttab, + }; #ifdef CONFIG_GRANT_TABLE - if ( !gnttab ) - goto fail; + if ( !gnttab ) + return false; - gnttab->nr_banks = 1; - gnttab->bank[0].start = kinfo->gnttab_start; - gnttab->bank[0].size = kinfo->gnttab_size; + gnttab->nr_banks = 1; + gnttab->bank[0].start = kinfo->gnttab_start; + gnttab->bank[0].size = kinfo->gnttab_size; #endif - hwdom_free_mem = membanks_xzalloc(NR_MEM_BANKS, MEMORY); - if ( !hwdom_free_mem ) - goto fail; - - if ( find_unallocated_memory(kinfo, mem_banks, ARRAY_SIZE(mem_banks), - hwdom_free_mem, add_hwdom_free_regions) ) - goto fail; + hwdom_free_mem = membanks_xzalloc(NR_MEM_BANKS, MEMORY); + if ( !hwdom_free_mem ) + { + xfree(gnttab); + return false; + } - nr_banks = hwdom_free_mem->nr_banks; + if ( find_unallocated_memory(kinfo, mem_banks, ARRAY_SIZE(mem_banks), + hwdom_free_mem, add_hwdom_free_regions) ) + { xfree(gnttab); + xfree(hwdom_free_mem); + return false; } - for ( i = 0; kinfo->unassigned_mem > 0 && nr_banks > 0; i++, nr_banks-- ) + xfree(gnttab); + nr_banks = hwdom_free_mem->nr_banks; + + for ( i = 0; (kinfo->unassigned_mem > 0) && (i < nr_banks); i++ ) { - paddr_t bank_start, bank_size; + paddr_t bank_size; + + /* + * The first bank must be large enough for place_modules() to + * fit the kernel, DTB and initrd. Skip small regions to avoid + * ending up with a tiny first bank. + */ + if ( !mem->nr_banks && (hwdom_free_mem->bank[i].size < min_bank_size) ) + continue; - if ( is_hardware_domain(d) ) + bank_size = MIN(hwdom_free_mem->bank[i].size, kinfo->unassigned_mem); + if ( !allocate_bank_memory(kinfo, + gaddr_to_gfn(hwdom_free_mem->bank[i].start), + bank_size) ) { - bank_start = hwdom_free_mem->bank[i].start; - bank_size = hwdom_free_mem->bank[i].size; + xfree(hwdom_free_mem); + return false; } - else + } + + xfree(hwdom_free_mem); + return true; +} + +void __init allocate_memory(struct domain *d, struct kernel_info *kinfo) +{ + struct membanks *mem = kernel_info_get_mem(kinfo); + unsigned int i; + + printk(XENLOG_INFO "Allocating mappings totalling %ldMB for %pd:\n", + /* Don't want format this as PRIpaddr (16 digit hex) */ + (unsigned long)(kinfo->unassigned_mem >> 20), d); + + mem->nr_banks = 0; + + if ( is_hardware_domain(d) ) + { + if ( !allocate_hwdom_memory(kinfo) ) + goto fail; + } + else + { + for ( i = 0; kinfo->unassigned_mem > 0 && i < GUEST_RAM_BANKS; i++ ) { const uint64_t bankbase[] = GUEST_RAM_BANK_BASES; const uint64_t banksize[] = GUEST_RAM_BANK_SIZES; + paddr_t bank_size; - if ( i >= GUEST_RAM_BANKS ) + bank_size = MIN(banksize[i], kinfo->unassigned_mem); + if ( !allocate_bank_memory(kinfo, gaddr_to_gfn(bankbase[i]), + bank_size) ) goto fail; - - bank_start = bankbase[i]; - bank_size = banksize[i]; } - - bank_size = MIN(bank_size, kinfo->unassigned_mem); - if ( !allocate_bank_memory(kinfo, gaddr_to_gfn(bank_start), bank_size) ) - goto fail; } if ( kinfo->unassigned_mem ) @@ -326,7 +367,6 @@ void __init allocate_memory(struct domain *d, struct kernel_info *kinfo) (unsigned long)(mem->bank[i].size >> 20)); } - xfree(hwdom_free_mem); return; fail: -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 09:38:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 09:38:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284113.1566017 (Exim 4.92) (envelope-from ) id 1wDfeD-0005WW-9r; Fri, 17 Apr 2026 09:38:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284113.1566017; Fri, 17 Apr 2026 09:38:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDfeD-0005WP-6I; Fri, 17 Apr 2026 09:38:01 +0000 Received: by outflank-mailman (input) for mailman id 1284113; Fri, 17 Apr 2026 09:37:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDfeB-0005WJ-Ss for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 09:37:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDfeB-008dQl-9K for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 11:37:59 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e1ff6d-2eae-0a2a0a5409dd-0a2a4504a354-34 for ; Fri, 17 Apr 2026 11:37:59 +0200 Received: from [209.85.221.43] (helo=mail-wr1-f43.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e1ff77-1dec-0a2a45040019-d155dd2ba5aa-3 for ; Fri, 17 Apr 2026 11:37:59 +0200 Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-43d7a5e77b1so329061f8f.1 for ; Fri, 17 Apr 2026 02:37:59 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Nor can aia_available() be a convenience >>> wrapper around that call? It's only ... >>> >>>> --- /dev/null >>>> +++ b/xen/arch/riscv/aia.c >>>> @@ -0,0 +1,25 @@ >>>> +/* SPDX-License-Identifier: GPL-2.0-only */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include >>>> + >>>> +static bool __ro_after_init is_aia_available; >>> >>> ... a boolean, yes, but still. >> >> My purpose was to have a variable which represent that AIA is >> initialized properly. Maybe, it makes sense to rename this variable to >> is_aia_inited. > > I'm generally having trouble with the non-word "inited". How about > "aia_usable"? Fits ... > >> The idea is that in future patches VGEIN will be also initialized in >> aia_init() and if wasn't initialized properly then just keep >> is_aia_availabe be set to false and in such case we will have that >> is_aia_available != riscv_isa_extension_available(NULL, >> RISCV_ISA_EXT_ssaia). > > ... this as well. And ... > >> Note that regarding VGEIN it is arguable that it should be initialized >> as generally it could be that there is no VGEIN what means that h/w >> assisted guest interrupt files aren't available and s/w one should be >> used. But s/w guest interrupt files aren't supported. >> So I mean that with the current implementation if VGEIN isn't >> initialized I will tell that AIA isn't available what generally isn't >> quite true. > > ... this. Question of course if what aia_usable (or whatever its name) > being set to false means to Xen's own operation. If Xen would still work > okay (without being able to create guests), perhaps the name may want to > be "aia_guest_usable" or some such. I.e. as I said on a number of > occasions: A variable wants to be named to accurately express its > purpose, without the name growing excessively long. aia_usable sounds good to me. It covers also the case if AIA isn't expected to be used as h/w uses non-AIA-compliant interrupt controller, for example, PLIC. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 10:55:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 10:55:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284140.1566029 (Exim 4.92) (envelope-from ) id 1wDgqi-0006g2-Kk; Fri, 17 Apr 2026 10:55:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284140.1566029; Fri, 17 Apr 2026 10:55:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDgqi-0006fv-HE; Fri, 17 Apr 2026 10:55:00 +0000 Received: by outflank-mailman (input) for mailman id 1284140; Fri, 17 Apr 2026 10:54:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDgqh-0006fp-6c for xen-devel@lists.xenproject.org; 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This manifested itself as a page fault while scrubbing RAM during boot. Xen failed to mark its location as reserved in the E820 because the last 2 MiB superpage overlapped a reserved region which meant the memory was given to the allocator despite being RO. Fixes: 4fb075201f54 ("x86/mkelf32: pad load segment to 2Mb boundary") Signed-off-by: Ross Lagerwall --- xen/arch/x86/boot/mkelf32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/boot/mkelf32.c b/xen/arch/x86/boot/mkelf32.c index 373ba4ddd593..469d1ba0af41 100644 --- a/xen/arch/x86/boot/mkelf32.c +++ b/xen/arch/x86/boot/mkelf32.c @@ -345,7 +345,7 @@ int main(int argc, char **argv) * the Xen image using 2M pages. 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Do you have the relevant snippet of the E820? AIUI, you're saying that Xen was placed immediately below an E820 reserved region (a valid layout at 1M alignment), where said region was inside the 2M-aligned boundary that Xen was expecting. But I don't quite follow what happened next.  Where does read-only-ness come into it? > > Fixes: 4fb075201f54 ("x86/mkelf32: pad load segment to 2Mb boundary") > Signed-off-by: Ross Lagerwall For the patch itself, Reviewed-by: Andrew Cooper but likely to want a tweak to the commit message. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 17 11:34:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 11:34:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284178.1566047 (Exim 4.92) (envelope-from ) id 1wDhTE-0003ql-Tj; Fri, 17 Apr 2026 11:34:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284178.1566047; Fri, 17 Apr 2026 11:34:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDhTE-0003qe-R2; Fri, 17 Apr 2026 11:34:48 +0000 Received: by outflank-mailman (input) for mailman id 1284178; Fri, 17 Apr 2026 11:34:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDhTD-0003qY-Ea for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 11:34:47 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDhTC-0091Be-Ro for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:34:46 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e21ad1-e002-0a2a0a5209dd-0a2a4509c1de-20 for ; Fri, 17 Apr 2026 13:34:46 +0200 Received: from [209.85.167.54] (helo=mail-lf1-f54.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e21ad6-2497-0a2a45090019-d155a736b9cd-3 for ; Fri, 17 Apr 2026 13:34:46 +0200 Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-5a3cee3a271so654970e87.3 for ; Fri, 17 Apr 2026 04:34:46 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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See XEN_SYSCTL_cpu_hotplug (and ignore it having > "hotplug" in the name, but merely consider that you can take CPUs offline > at runtime, and later bring them online again). Thanks, now it makes sense to drop __init. > >>> Also - static? >> >> It isn't static because it will be called inside the secondary CPU >> bring-up function. > > As it doesn't need calling from the outside for the boot CPU, it's not > obvious why it would need calling from the outside for secondary ones. I think I am confused here by what do you mean by "calling from the outside". It should be called during boot or secondary CPU initialization (if AIA is used), right? Then considering that VGEIN-related stuff is connected to AIA then vgein_init() is expected to live in aia.c and considering that it wants to be called by secondary CPU boot code it can't be static. I have a feeling that I misunderstood your statement... > >>>> +{ >>>> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); >>>> + >>>> + csr_write(CSR_HGEIE, -1UL); >>>> + vgein->geilen = flsl(csr_read(CSR_HGEIE)); >>>> + csr_write(CSR_HGEIE, 0); >>>> + if ( vgein->geilen ) >>>> + vgein->geilen--; >>> >>> I don't understand this. The "len" in "geilen" stands for "length", I suppose, >>> i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of >>> bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED >>> and may be zero. This number is known as GEILEN." This may or may not include >>> bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is >>> nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but >>> that's not unambiguous. >> >> But they explicitly wrote that: The least-significant bits are >> implemented first, apart from bit 0. So bit 0 is explicitly excluded. > > Fine, but not including it in anything named *LEN feels - as said - ambiguous. Agree, it is. I just tried to follow the spec naming here. But I am okay to rename it to max_gein, for example. > >>>> + /* >>>> + * All vCPU guest interrupt files are used and we don't support a case >>>> + * when number of vCPU on 1 pCPU is bigger then geilen. >>>> + */ >>> >>> This wants checking in vgein_init() then. CPUs (beyond the boot one) >>> violating this should not be brought online. >> >> It'll be nice. But we can't know how many vCPUs will be ran on pCPU when >> vgein_init() is executed. > > I don't understand: How does it matter how many vCPU-s will exist later on > (and will run wherever)? IIUC, you want to check what is mentioned in the comment in vcpu_init(). The comment says that it is checking that number of vCPU on one pCPU isn't bigger then geilen. To check that we have to know an amount of vCPU potentially will be ran on pCPU. For me it is enough to have that vgein->geilen isn't 0 as this case isn't supported now. > >>>> + ASSERT(vgein_id < vgein_bmp->geilen); >>> >>> What if not bit is available? By asserting, you assume the caller will not >>> call here when no ID is available. >> >> It is just a temporary ASSERT() (as we don't support software guest >> interrupt files) because in general it is fine if there is no bit >> available, it will just mean that that no physical hardware guest >> interrupt file is assigned to the virtual hart, and software-based >> emulation (a "software file") must be used to handle guest external >> interrupts. >> >> Will it be better to return 0 now here and just don't create a vCPU >> on ... >> >> Yet there is no caller of this function, >>> so how can one verify whether this assertion is appropriate? >> >> ... the caller side when an assignment is expected to be happen? > > Yes, you want to return errors for cases you can't handle. You wan to > assert on internal state only, not on anything controlled by a caller > outside of the hypervisor. I will return then just vgein_id = 0 (as it is what should be returned when s/w guest interrupt files are supported) and handle that on the caller side. And symmetrically I will add 'if ( !vgein_id ) return' to vgein_release() as nothing should be done in vgein bitmap in this case. ~ Oleksii ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 11:56:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 11:56:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284195.1566057 (Exim 4.92) (envelope-from ) id 1wDhoK-0006eh-K7; Fri, 17 Apr 2026 11:56:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284195.1566057; Fri, 17 Apr 2026 11:56:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDhoK-0006eY-F6; Fri, 17 Apr 2026 11:56:36 +0000 Received: by outflank-mailman (input) for mailman id 1284195; Fri, 17 Apr 2026 11:56:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDhoI-0006eS-Mm for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fmJHCDHuj0I2EK+QF9HWE3ksnDBgpclet8sc0zuFsMINNI+UEjlmmMuzA8Dr+r8qq4SNQUQUuVlP4X1R1Hqibe2LGbrTIxdfqORdaVEXUPan6rLXwojcDll+6uQ6mTK4H7X0m0G9j05ijNWudk9IrrqQ8e9tOb0uZGxQ85GYXsE9boyCKF+iN41ChvV1vtDWG9NxbCzo2WPajAgm5H2ZRUFlD7iJoILOQjHtaw2A9+CDi7Ombc34gHv2WU8ZMRnqHFIuvL5siwzw8cXWBexC43OsPWPzI6xyJ7sDqXs8HZ5BsQQUwuQbk6Nl4m1Y+KrD7XsD3WAAAgdzYWkJSA0vMmk6kRpgsInKAobJzgb8pHjONssQVYLEWhGkgqq7XBgvWE/Dd8/WB1rWrgkW2gCdtVVssnZHLUxYJpSwzOSxAVxu26EoHUBtlVLp/J9OqjeE X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2026 11:56:26.3064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56309858-cc2b-49c0-93d6-08de9c785aa7 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000197.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB10898 X-purgate-ID: tlsNG-ebf023/1776426993-30E443FF-9A178883/0/0 X-purgate-type: clean X-purgate-size: 10780 HI Michal, > On 17 Apr 2026, at 10:11, Michal Orzel wrote: >=20 > Refactor setup_frametable_mappings() into init_frametable(), modeled > after x86's implementation. Instead of mapping one contiguous frametable > covering ram_start to ram_end (including holes), iterate the > pdx_group_valid bitmap to allocate and map frametable memory only for > valid PDX groups, skipping gaps in the physical address space. At the > moment we don't really take into account pdx_group_valid bitmap. >=20 > This reduces memory consumption on systems with sparse RAM layouts by > not allocating frametable entries for non-existent memory regions. >=20 > A file-local pdx_to_page() override is needed because the generic macro > in xen/include/xen/pdx.h does not account for ARM's non-zero > frametable_base_pdx. >=20 > Update the MPU implementation to match the new init_frametable() > signature. Since MPU has no virtual address translation (ma =3D=3D va), > hole-skipping is not possible and the frametable remains a single > contiguous allocation. >=20 > Signed-off-by: Michal Orzel > --- > We've been using this approach at AMD for a while now. Without this we wo= uld not > be able to boot some of our boards that have huge holes in the PA space, = so I > consider this patch a great improvement. >=20 > Two things to consider as a follow-up in the future: > - change generic pdx_to_page, page_to_pdx to take into account offset tha= t > on x86 is zero but on other arches it is not. The page list code is > for now unaffected because the offset cancels out, > - use the same on RISCV. > --- > xen/arch/arm/arm32/mmu/mm.c | 3 +- > xen/arch/arm/include/asm/mm.h | 4 +- > xen/arch/arm/mm.c | 2 +- > xen/arch/arm/mmu/mm.c | 77 ++++++++++++++++++++++++----------- > xen/arch/arm/mpu/mm.c | 23 ++++++----- > 5 files changed, 70 insertions(+), 39 deletions(-) >=20 > diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c > index 5e4766ddcf65..0b595baa11b3 100644 > --- a/xen/arch/arm/arm32/mmu/mm.c > +++ b/xen/arch/arm/arm32/mmu/mm.c > @@ -178,8 +178,7 @@ void __init setup_mm(void) >=20 > setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages); >=20 > - /* Frame table covers all of RAM region, including holes */ > - setup_frametable_mappings(ram_start, ram_end); > + init_frametable(ram_start); >=20 > /* > * The allocators may need to use map_domain_page() (such as for > diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.= h > index 72a692862420..2eb8465aa904 100644 > --- a/xen/arch/arm/include/asm/mm.h > +++ b/xen/arch/arm/include/asm/mm.h > @@ -196,8 +196,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr); > extern void remove_early_mappings(void); > /* Prepare the memory subystem to bring-up the given secondary CPU */ > extern int prepare_secondary_mm(int cpu); > -/* Map a frame table to cover physical addresses ps through pe */ > -extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); > +/* Map a frame table */ NIT: Would /* Initialize the frame table */ fit better the new helper descr= iption? > +void init_frametable(paddr_t ram_start); > /* Helper function to setup memory management */ > void setup_mm_helper(void); > /* map a physical range in virtual memory */ > diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c > index 6df8b616e464..e6b651956927 100644 > --- a/xen/arch/arm/mm.c > +++ b/xen/arch/arm/mm.c > @@ -62,7 +62,7 @@ void __init setup_mm(void) >=20 > setup_mm_helper(); >=20 > - setup_frametable_mappings(ram_start, ram_end); > + init_frametable(ram_start); >=20 > init_staticmem_pages(); > init_sharedmem_pages(); > diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c > index 6604f3bf4e6a..4b4da349c16c 100644 > --- a/xen/arch/arm/mmu/mm.c > +++ b/xen/arch/arm/mmu/mm.c > @@ -8,16 +8,37 @@ > #include > #include >=20 > -/* Map a frame table to cover physical addresses ps through pe */ > -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) > +#undef pdx_to_page > +#define pdx_to_page(pdx) gcc11_wrap(frame_table + ((pdx) - frametable_ba= se_pdx)) > + > +static void __init > +init_frametable_chunk(unsigned long pdx_s, unsigned long pdx_e) > { > - unsigned long nr_pdxs =3D mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) = - > - mfn_to_pdx(maddr_to_mfn(ps)) + 1; > - unsigned long frametable_size =3D nr_pdxs * sizeof(struct page_info)= ; > - mfn_t base_mfn; > - const unsigned long mapping_size =3D frametable_size < MB(32) ? MB(2= ) > - : MB(32)= ; > + unsigned long nr_pdxs =3D pdx_e - pdx_s; > + unsigned long chunk_size =3D nr_pdxs * sizeof(struct page_info); > + const unsigned long mapping_size =3D chunk_size < MB(32) ? MB(2) : M= B(32); > + unsigned long virt; > int rc; > + mfn_t base_mfn; > + > + /* Round up to 2M or 32M boundary, as appropriate. */ > + chunk_size =3D ROUNDUP(chunk_size, mapping_size); > + base_mfn =3D alloc_boot_pages(chunk_size >> PAGE_SHIFT, 32 << (20 - = 12)); > + > + virt =3D (unsigned long)pdx_to_page(pdx_s); > + rc =3D map_pages_to_xen(virt, base_mfn, chunk_size >> PAGE_SHIFT, > + PAGE_HYPERVISOR_RW | _PAGE_BLOCK); > + if ( rc ) > + panic("Unable to setup the frametable mappings\n"); > + > + memset(pdx_to_page(pdx_s), 0, nr_pdxs * sizeof(struct page_info)); > + memset(pdx_to_page(pdx_e), -1, > + chunk_size - nr_pdxs * sizeof(struct page_info)); > +} > + > +void __init init_frametable(paddr_t ram_start) > +{ > + unsigned int sidx, nidx, max_idx; >=20 > /* > * The size of paddr_t should be sufficient for the complete range of > @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, pad= dr_t pe) > BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); > BUILD_BUG_ON(sizeof(struct page_info) !=3D PAGE_INFO_SIZE); >=20 > - if ( frametable_size > FRAMETABLE_SIZE ) > - panic("The frametable cannot cover the physical region %#"PRIpad= dr" - %#"PRIpaddr"\n", > - ps, pe); > + max_idx =3D DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); > + frametable_base_pdx =3D mfn_to_pdx(maddr_to_mfn(ram_start)); >=20 > - frametable_base_pdx =3D mfn_to_pdx(maddr_to_mfn(ps)); > - /* Round up to 2M or 32M boundary, as appropriate. */ > - frametable_size =3D ROUNDUP(frametable_size, mapping_size); > - base_mfn =3D alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20= -12)); > + /* > + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned > + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees th= is > + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple = of > + * PAGE_SIZE by construction. > + */ > + frametable_base_pdx =3D ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COU= NT); We are now rounding down frametable_base_pdx which before this patch it was= the start of the ram, but in xen/xen/arch/arm/include/asm/mm.h, mfn_valid(mfn) is using frametabl= e_base_pdx to check for mfn validity, this means that we could pass an mfn before the start of the = ram and if __mfn_valid is happy, we are getting a regression. Can this happen or am I missing something? >=20 > - rc =3D map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, > - frametable_size >> PAGE_SHIFT, > - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); > - if ( rc ) > - panic("Unable to setup the frametable mappings.\n"); > + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) > + panic("Frametable too small\n"); > + > + for ( sidx =3D (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx =3D n= idx ) > + { > + unsigned int eidx; > + > + eidx =3D find_next_zero_bit(pdx_group_valid, max_idx, sidx); > + nidx =3D find_next_bit(pdx_group_valid, max_idx, eidx); > + > + if ( nidx >=3D max_idx ) > + break; > + > + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_C= OUNT); > + } >=20 > - memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info)); > - memset(&frame_table[nr_pdxs], -1, > - frametable_size - (nr_pdxs * sizeof(struct page_info))); > + init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx); > } >=20 > /* > diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c > index aff88bd3a9c1..9c568831c128 100644 > --- a/xen/arch/arm/mpu/mm.c > +++ b/xen/arch/arm/mpu/mm.c > @@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned = int attributes) > return 0; > } >=20 > -/* Map a frame table to cover physical addresses ps through pe */ > -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) > +/* > + * Allocate a contiguous frame table covering ram_start through max_pdx. > + * Unlike the MMU version, MPU cannot skip holes because there is no vir= tual > + * address translation (ma =3D=3D va). > + */ > +void __init init_frametable(paddr_t ram_start) > { > + unsigned long nr_pdxs, frametable_size; > mfn_t base_mfn; > - paddr_t aligned_ps =3D ROUNDUP(ps, PAGE_SIZE); > - paddr_t aligned_pe =3D ROUNDDOWN(pe, PAGE_SIZE); > - > - unsigned long nr_pdxs =3D mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe= ), -1)) - > - mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1; > - unsigned long frametable_size =3D nr_pdxs * sizeof(struct page_info)= ; >=20 > /* > * The size of paddr_t should be sufficient for the complete range of > @@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, p= addr_t pe) > BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); > BUILD_BUG_ON(sizeof(struct page_info) !=3D PAGE_INFO_SIZE); >=20 > + frametable_base_pdx =3D mfn_to_pdx(maddr_to_mfn(ram_start)); > + nr_pdxs =3D max_pdx - frametable_base_pdx; > + frametable_size =3D nr_pdxs * sizeof(struct page_info); > + > if ( frametable_size > FRAMETABLE_SIZE ) > - panic("The frametable cannot cover the physical region %#"PRIpad= dr" - %#"PRIpaddr"\n", > - ps, pe); > + panic("Frametable too small\n"); >=20 > - frametable_base_pdx =3D paddr_to_pdx(aligned_ps); > frametable_size =3D ROUNDUP(frametable_size, PAGE_SIZE); >=20 > base_mfn =3D alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1); > --=20 > 2.43.0 >=20 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 11:57:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 11:57:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284202.1566066 (Exim 4.92) (envelope-from ) id 1wDhol-00072N-VW; Fri, 17 Apr 2026 11:57:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284202.1566066; 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Instead of mapping one contiguous frametable > covering ram_start to ram_end (including holes), iterate the > pdx_group_valid bitmap to allocate and map frametable memory only for > valid PDX groups, skipping gaps in the physical address space. At the > moment we don't really take into account pdx_group_valid bitmap. > > This reduces memory consumption on systems with sparse RAM layouts by > not allocating frametable entries for non-existent memory regions. > > A file-local pdx_to_page() override is needed because the generic macro > in xen/include/xen/pdx.h does not account for ARM's non-zero > frametable_base_pdx. > > Update the MPU implementation to match the new init_frametable() > signature. Since MPU has no virtual address translation (ma == va), > hole-skipping is not possible and the frametable remains a single > contiguous allocation. > > Signed-off-by: Michal Orzel > --- > We've been using this approach at AMD for a while now. Without this we would not > be able to boot some of our boards that have huge holes in the PA space, so I > consider this patch a great improvement. > > Two things to consider as a follow-up in the future: > - change generic pdx_to_page, page_to_pdx to take into account offset that > on x86 is zero but on other arches it is not. The page list code is > for now unaffected because the offset cancels out, > - use the same on RISCV. PPC also has frametable_base_pdx and a TODO saying "make this work".  The header file however is horribly tangled and needs some work. What I think we want is to include early (if it exists), and allow it the option to define frametable_base_pdx, but with a common fallback making it 0. I think we also want to split out xen/pdx-{mask,offset}.h each taking their respective chunk of the giant comment.  Possibly pdx-none.h too.  This separates the unrelated algorithms, and puts their definitions next to the comment explaining how it works. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:00:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:00:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284247.1566079 (Exim 4.92) (envelope-from ) id 1wDioC-0007X6-KC; Fri, 17 Apr 2026 13:00:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284247.1566079; Fri, 17 Apr 2026 13:00:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDioC-0007Wz-Fn; Fri, 17 Apr 2026 13:00:32 +0000 Received: by outflank-mailman (input) for mailman id 1284247; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5Q1fkmpiTnC2OAcVts4qa7+3EC553sFxD++5VROxj4it8HNZro1+uZRB9gPsLcaAYiIdcD3fqv4dKXLSwwZbOEZCmKHIdRtZl6wSYAmk1NVa6+KIt2OLoQg08FjYeRnr2IoU6l3i8Ln0mYchdO6FkUJ3gE6GLlHKQsyB6HOU9xpfpOzId2jxvuKQIPNvYrAgaUUMTo7AA0SC930mXUKV2nxeGNU2UrkS6bT0ggv5W2wuzeLmIPUPyUkcp//i6bNQyhsyyZBL8HGgSvOSINhBBntQEuYQ1A1iqVzocC+OW56033yIPnALDaN67iZbMej+hlPx7ALeCQtNEbzgQoxsnSqx8B7Qkq0HIH/yrlOyxmrefrQjqqJMTJyP8yf77a+UNqYjzYean3WVaaIq+7F3/8qr3HklAAr285HLJFlVKet94esCzSQM8nguVKpjGBWh X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2026 13:00:22.1435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0ba5cc8-05a6-4f5e-af4d-08de9c8148f3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004684.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7859 X-purgate-ID: tlsNG-16d1c6/1776430829-90E7CD75-ABF76D70/0/0 X-purgate-type: clean X-purgate-size: 11206 On 17/04/2026 13:55, Luca Fancellu wrote: > HI Michal, > >> On 17 Apr 2026, at 10:11, Michal Orzel wrote: >> >> Refactor setup_frametable_mappings() into init_frametable(), modeled >> after x86's implementation. Instead of mapping one contiguous frametable >> covering ram_start to ram_end (including holes), iterate the >> pdx_group_valid bitmap to allocate and map frametable memory only for >> valid PDX groups, skipping gaps in the physical address space. At the >> moment we don't really take into account pdx_group_valid bitmap. >> >> This reduces memory consumption on systems with sparse RAM layouts by >> not allocating frametable entries for non-existent memory regions. >> >> A file-local pdx_to_page() override is needed because the generic macro >> in xen/include/xen/pdx.h does not account for ARM's non-zero >> frametable_base_pdx. >> >> Update the MPU implementation to match the new init_frametable() >> signature. Since MPU has no virtual address translation (ma == va), >> hole-skipping is not possible and the frametable remains a single >> contiguous allocation. >> >> Signed-off-by: Michal Orzel >> --- >> We've been using this approach at AMD for a while now. Without this we would not >> be able to boot some of our boards that have huge holes in the PA space, so I >> consider this patch a great improvement. >> >> Two things to consider as a follow-up in the future: >> - change generic pdx_to_page, page_to_pdx to take into account offset that >> on x86 is zero but on other arches it is not. The page list code is >> for now unaffected because the offset cancels out, >> - use the same on RISCV. >> --- >> xen/arch/arm/arm32/mmu/mm.c | 3 +- >> xen/arch/arm/include/asm/mm.h | 4 +- >> xen/arch/arm/mm.c | 2 +- >> xen/arch/arm/mmu/mm.c | 77 ++++++++++++++++++++++++----------- >> xen/arch/arm/mpu/mm.c | 23 ++++++----- >> 5 files changed, 70 insertions(+), 39 deletions(-) >> >> diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c >> index 5e4766ddcf65..0b595baa11b3 100644 >> --- a/xen/arch/arm/arm32/mmu/mm.c >> +++ b/xen/arch/arm/arm32/mmu/mm.c >> @@ -178,8 +178,7 @@ void __init setup_mm(void) >> >> setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages); >> >> - /* Frame table covers all of RAM region, including holes */ >> - setup_frametable_mappings(ram_start, ram_end); >> + init_frametable(ram_start); >> >> /* >> * The allocators may need to use map_domain_page() (such as for >> diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h >> index 72a692862420..2eb8465aa904 100644 >> --- a/xen/arch/arm/include/asm/mm.h >> +++ b/xen/arch/arm/include/asm/mm.h >> @@ -196,8 +196,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr); >> extern void remove_early_mappings(void); >> /* Prepare the memory subystem to bring-up the given secondary CPU */ >> extern int prepare_secondary_mm(int cpu); >> -/* Map a frame table to cover physical addresses ps through pe */ >> -extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); >> +/* Map a frame table */ > > NIT: Would /* Initialize the frame table */ fit better the new helper description? > >> +void init_frametable(paddr_t ram_start); >> /* Helper function to setup memory management */ >> void setup_mm_helper(void); >> /* map a physical range in virtual memory */ >> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c >> index 6df8b616e464..e6b651956927 100644 >> --- a/xen/arch/arm/mm.c >> +++ b/xen/arch/arm/mm.c >> @@ -62,7 +62,7 @@ void __init setup_mm(void) >> >> setup_mm_helper(); >> >> - setup_frametable_mappings(ram_start, ram_end); >> + init_frametable(ram_start); >> >> init_staticmem_pages(); >> init_sharedmem_pages(); >> diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c >> index 6604f3bf4e6a..4b4da349c16c 100644 >> --- a/xen/arch/arm/mmu/mm.c >> +++ b/xen/arch/arm/mmu/mm.c >> @@ -8,16 +8,37 @@ >> #include >> #include >> >> -/* Map a frame table to cover physical addresses ps through pe */ >> -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >> +#undef pdx_to_page >> +#define pdx_to_page(pdx) gcc11_wrap(frame_table + ((pdx) - frametable_base_pdx)) >> + >> +static void __init >> +init_frametable_chunk(unsigned long pdx_s, unsigned long pdx_e) >> { >> - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) - >> - mfn_to_pdx(maddr_to_mfn(ps)) + 1; >> - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); >> - mfn_t base_mfn; >> - const unsigned long mapping_size = frametable_size < MB(32) ? MB(2) >> - : MB(32); >> + unsigned long nr_pdxs = pdx_e - pdx_s; >> + unsigned long chunk_size = nr_pdxs * sizeof(struct page_info); >> + const unsigned long mapping_size = chunk_size < MB(32) ? MB(2) : MB(32); >> + unsigned long virt; >> int rc; >> + mfn_t base_mfn; >> + >> + /* Round up to 2M or 32M boundary, as appropriate. */ >> + chunk_size = ROUNDUP(chunk_size, mapping_size); >> + base_mfn = alloc_boot_pages(chunk_size >> PAGE_SHIFT, 32 << (20 - 12)); >> + >> + virt = (unsigned long)pdx_to_page(pdx_s); >> + rc = map_pages_to_xen(virt, base_mfn, chunk_size >> PAGE_SHIFT, >> + PAGE_HYPERVISOR_RW | _PAGE_BLOCK); >> + if ( rc ) >> + panic("Unable to setup the frametable mappings\n"); >> + >> + memset(pdx_to_page(pdx_s), 0, nr_pdxs * sizeof(struct page_info)); >> + memset(pdx_to_page(pdx_e), -1, >> + chunk_size - nr_pdxs * sizeof(struct page_info)); >> +} >> + >> +void __init init_frametable(paddr_t ram_start) >> +{ >> + unsigned int sidx, nidx, max_idx; >> >> /* >> * The size of paddr_t should be sufficient for the complete range of >> @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >> >> - if ( frametable_size > FRAMETABLE_SIZE ) >> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >> - ps, pe); >> + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); >> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >> >> - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); >> - /* Round up to 2M or 32M boundary, as appropriate. */ >> - frametable_size = ROUNDUP(frametable_size, mapping_size); >> - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); >> + /* >> + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned >> + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this >> + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of >> + * PAGE_SIZE by construction. >> + */ >> + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); > > We are now rounding down frametable_base_pdx which before this patch it was the start of the ram, > but in xen/xen/arch/arm/include/asm/mm.h, mfn_valid(mfn) is using frametable_base_pdx to check for > mfn validity, this means that we could pass an mfn before the start of the ram and if __mfn_valid is happy, > we are getting a regression. > > Can this happen or am I missing something? mfn_valid() can indeed return true for an MFN below ram_start that falls in the same PDX group, but this is safe. init_frametable_chunk() maps and zeroes the frametable for that range, so mfn_to_page() won't fault. The zeroed page_info has count_info == 0 and no owner, so any get_page() call on it will fail — the page is effectively inert. ~Michal > >> >> - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, >> - frametable_size >> PAGE_SHIFT, >> - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); >> - if ( rc ) >> - panic("Unable to setup the frametable mappings.\n"); >> + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) >> + panic("Frametable too small\n"); >> + >> + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) >> + { >> + unsigned int eidx; >> + >> + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); >> + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); >> + >> + if ( nidx >= max_idx ) >> + break; >> + >> + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); >> + } >> >> - memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info)); >> - memset(&frame_table[nr_pdxs], -1, >> - frametable_size - (nr_pdxs * sizeof(struct page_info))); >> + init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx); >> } >> >> /* >> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c >> index aff88bd3a9c1..9c568831c128 100644 >> --- a/xen/arch/arm/mpu/mm.c >> +++ b/xen/arch/arm/mpu/mm.c >> @@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned int attributes) >> return 0; >> } >> >> -/* Map a frame table to cover physical addresses ps through pe */ >> -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >> +/* >> + * Allocate a contiguous frame table covering ram_start through max_pdx. >> + * Unlike the MMU version, MPU cannot skip holes because there is no virtual >> + * address translation (ma == va). >> + */ >> +void __init init_frametable(paddr_t ram_start) >> { >> + unsigned long nr_pdxs, frametable_size; >> mfn_t base_mfn; >> - paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE); >> - paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE); >> - >> - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) - >> - mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1; >> - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); >> >> /* >> * The size of paddr_t should be sufficient for the complete range of >> @@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >> >> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >> + nr_pdxs = max_pdx - frametable_base_pdx; >> + frametable_size = nr_pdxs * sizeof(struct page_info); >> + >> if ( frametable_size > FRAMETABLE_SIZE ) >> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >> - ps, pe); >> + panic("Frametable too small\n"); >> >> - frametable_base_pdx = paddr_to_pdx(aligned_ps); >> frametable_size = ROUNDUP(frametable_size, PAGE_SIZE); >> >> base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1); >> -- >> 2.43.0 >> > From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:25:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:25:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284265.1566092 (Exim 4.92) (envelope-from ) id 1wDjCB-0001vB-I7; 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Where does read-only-ness > come into it? > Relevant E820: (XEN) [00000063469ff02c] [000000003f2df000, 000000003f31efff] (ACPI NVS) (XEN) [00000063519dc9f2] [000000003f31f000, 000000004cfebfff] (usable) (XEN) [000000635c504aff] [000000004cfec000, 000000004d07bfff] (ACPI data) (XEN) [00000063677372dc] [000000004d07c000, 000000004d09bfff] (ACPI NVS) With a load size of 0x900000 (padded to a 1 MiB boundary), Xen was placed at 4c600000-4cefffff. In __start_xen(), there is a call... reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)); ... which tries to reserve the region 4c600000-4cffffff (size 0x1000000), padded to a 2 MiB boundary since it is using superpages. reserve_e820_ram() doesn't reserve anything because the request doesn't fall within a single RAM region. Therefore, the pages get treated as normal RAM and will get scrubbed later. However, __start_xen() also calls modify_xen_mappings() to mark all of .text and .rodata as RO in the direct map so when it actually tries to scrub it it gets a page fault instead (which is I suppose slightly better than just zeroing Xen's .text). Ross From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:26:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:26:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284277.1566100 (Exim 4.92) (envelope-from ) id 1wDjCx-0002Qu-U7; Fri, 17 Apr 2026 13:26:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284277.1566100; Fri, 17 Apr 2026 13:26:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjCx-0002Qn-QH; Fri, 17 Apr 2026 13:26:07 +0000 Received: by outflank-mailman (input) for mailman id 1284277; Fri, 17 Apr 2026 13:26:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjCw-0002Qe-QQ for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:26:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjCw-00H0yR-7H for xen-devel@lists.xenproject.org; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776432364; x=1776692864; i=anthony.perard@vates.tech; bh=yOS4SBQdL2rVMR1pZqlGorF4AN8726MhdosMKOtMbH0=; h=From:Subject:To:Cc:Message-Id:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=ECA3TNpbYK+4N/9untMWWtu71c5vGpcavM2ExBtT8HY1ze5Y1bVGB/wFnQxmwRzy+ iVYyuASm48va9HtubGrLetJmcm+kDViwMYdHeLkRn4rFrrh9ELaZgBc9E5B0LmL0FW Xxtp9zmN7TtZnCPvad++KaQw+dRg/DpABYCiZLlRzJbeR25sHSBnPcz+0KghOmD595 MNe8JG/oVICwVOJW22dm6fSYjPvCka5eoZCowv2aclCgaJtrc/Q01mli0O5Wt5hv4+ x/QV3erV9fEndKIOFS9jGeChyB+hud63Pb+XnoMp5Cd/gPLp3uxITPll5G1T9bLIkO IUxmAEroNEYaQ== From: "Anthony PERARD" Subject: =?utf-8?Q?Re:=20[PATCH=20v2=205/6]=20CI:=20setup=20SSH=20key?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776432357951 To: "=?utf-8?Q?Marek=20Marczykowski-G=C3=B3recki?=" Cc: xen-devel@lists.xenproject.org, "Stefano Stabellini" , "Andrew Cooper" , "Doug Goldstein" Message-Id: References: <5d11a521db04134f8917c990a494ba8ce44548b9.1774999414.git-series.marmarek@invisiblethingslab.com> In-Reply-To: <5d11a521db04134f8917c990a494ba8ce44548b9.1774999414.git-series.marmarek@invisiblethingslab.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.13888a4284754813a4320b3d89ce7d09?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260417:md Date: Fri, 17 Apr 2026 13:26:04 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-bad1c0/1776432366-48AAEA53-A369B1EC/0/0 X-purgate-type: clean X-purgate-size: 506 On Wed, Apr 01, 2026 at 01:24:54AM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > Generate fresh key for a job, and add its public part to dom0's > authorized_keys file. > This allows the test controller to use SSH without any password prompt. > > Signed-off-by: Marek Marczykowski-G=C3=B3recki Reviewed-by: Anthony PERARD Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284299.1566113 (Exim 4.92) (envelope-from ) id 1wDjRf-0005Hh-8t; Fri, 17 Apr 2026 13:41:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284299.1566113; Fri, 17 Apr 2026 13:41:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRf-0005Ha-4O; Fri, 17 Apr 2026 13:41:19 +0000 Received: by outflank-mailman (input) for mailman id 1284299; Fri, 17 Apr 2026 13:41:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRd-0005HU-JA for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:41:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjRb-000EA5-ES for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:41:17 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e2386d-bab6-0a2a0a5309dd-0a2a4508a240-30 for ; Fri, 17 Apr 2026 15:41:16 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e2387b-63b5-0a2a45080019-d98c6eac9954-1 for ; Fri, 17 Apr 2026 15:41:16 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC87F1E5E; Fri, 17 Apr 2026 06:41:09 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 243C43F7D8; Fri, 17 Apr 2026 06:41:13 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433275; bh=RHC4oaKNm/5AmZippxNTl48kACDWHDvNsCq3bToP1H4=; h=From:To:Cc:Subject:Date:From; b=ZKVfybHq2pOH0Lh5Fam0EdXoo48OCe1c3z1MOY7QWGLCd8CmyVnz99owK7B27BdZd F9F/wlpLjWUmHssZXp3DX8NERyzG2lM3ImQFuw1uMsIa/V1KA2afJAxsyagrBWMf86 QwDZ8lOjkMi354eJAlLrBi1UvIEDXCH9K0RNNonI= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 0/6] xen/arm: ffa: Harden notifications and enable VM-to-VM delivery Date: Fri, 17 Apr 2026 15:40:48 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776433276-C2368DB1-4A54B146/0/0 X-purgate-type: clean X-purgate-size: 2387 This series hardens FF-A notification handling in the Arm FF-A mediator and completes local delivery for non-secure VM-to-VM notifications. Hardening and state handling (Patches 1-4): 1) Fix notification pending interrupt delivery when vcpu0 is offline by reusing a common global NPI injection helper. 2) Replace the single hypervisor notification boolean with a protected HYP bitmap and keep bitmap lifecycle tied to the cached endpoint ID. 3) Tighten notification parameter validation so malformed BIND, UNBIND, GET, and SET requests are rejected consistently before reaching cached state or the SPMC. 4) Preserve the secure pending indication until secure notifications are retrieved, protect the secure pending latch with notif_lock, serialize SPMC INFO_GET polling, and keep INFO_GET return width consistent with the caller. Local VM notification delivery (Patches 5-6): 1) Track non-secure VM notification bindings locally, promote pending state to a per-bit bitmap, and validate BIND/UNBIND requests against that state. 2) Deliver non-secure VM-to-VM notifications locally, track whether a local NPI is already armed, and only advertise notification support when firmware capabilities or CONFIG_FFA_VM_TO_VM actually provide it. Backward compatibility: v1.0/v1.1 guests remain compatible. Valid guest-visible notification behavior is preserved; the series only tightens malformed-request handling and enables local non-secure VM-to-VM delivery when CONFIG_FFA_VM_TO_VM is enabled. Gitlab branch with patches: https://gitlab.com/xen-project/people/bmarquis/xen-ffa/-/tree/vm-notif/v1?ref_type=heads CI pass result: https://gitlab.com/xen-project/people/bmarquis/xen-ffa/-/pipelines/2460589353 Bertrand Marquis (6): xen/arm: ffa: Fix NPI injection when vcpu0 is offline xen/arm: ffa: Track hypervisor notifications in a bitmap xen/arm: ffa: Tighten notification parameter validation xen/arm: ffa: Preserve secure notification state when polling SPMC xen/arm: ffa: Track VM notification bindings locally xen/arm: ffa: Deliver VM-to-VM notifications locally xen/arch/arm/tee/ffa.c | 24 +- xen/arch/arm/tee/ffa_notif.c | 407 +++++++++++++++++++++++++++------ xen/arch/arm/tee/ffa_private.h | 29 ++- 3 files changed, 385 insertions(+), 75 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284300.1566123 (Exim 4.92) (envelope-from ) id 1wDjRr-0005Xi-G5; Fri, 17 Apr 2026 13:41:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284300.1566123; Fri, 17 Apr 2026 13:41:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRr-0005Xb-C4; Fri, 17 Apr 2026 13:41:31 +0000 Received: by outflank-mailman (input) for mailman id 1284300; Fri, 17 Apr 2026 13:41:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRq-0005XG-DB for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:41:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjRp-000Ejb-QG for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:41:29 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23869-5cb7-0a2a0a5109dd-0a2a450688f0-46 for ; Fri, 17 Apr 2026 15:41:29 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e23888-7371-0a2a45060019-d98c6eacc488-1 for ; Fri, 17 Apr 2026 15:41:29 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BFB2E1E5E; Fri, 17 Apr 2026 06:41:22 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 164583F7D8; Fri, 17 Apr 2026 06:41:26 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433288; bh=2EBHRYe3a9Iu2Tcg1hgwEsSiL6lkKJcFnxNSP9Ue5No=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VdYJxFcLI4jsdEtYZSOcScludKGT5YwwMuMO0TwaaXWi1Hgkxt892Fotc+CN25Arq uRpUQYMjXbKpDSE5fOBcWIAD9XE8w9J02CloxF0T26Qh7gFylIzux2q+Ro2n5PIvfA P811XWtiGYC16BhHODf+4AbWTwWhWzSMWGbofGO0= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 1/6] xen/arm: ffa: Fix NPI injection when vcpu0 is offline Date: Fri, 17 Apr 2026 15:40:49 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776433289-52369D75-B7400893/0/0 X-purgate-type: clean X-purgate-size: 3302 RX-buffer-full notifications currently inject the notification pending interrupt through vcpu0 only. Secure notification delivery already walks the domain's online vCPUs, but the RX-buffer-full path does not. When vcpu0 is offline, the notification remains pending and the guest never receives it. Extract the common notification injection path and reuse it from ffa_raise_rx_buffer_full(). The shared helper delivers the global notification to the first online vCPU and keeps the existing ratelimited debug message when none are online. Functional impact: RX-buffer-full notifications are delivered even when vcpu0 is offline. Fixes: 3935c705688e ("xen/arm: ffa: Add buffer full notification support") Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa_notif.c | 45 ++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 186e72641237..07bc5cb3a430 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -19,6 +19,29 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; +static void inject_notif_pending(struct domain *d) +{ + struct vcpu *v; + + /* + * Since we're only delivering global notification, always + * deliver to the first online vCPU. It doesn't matter + * which we chose, as long as it's available. + */ + for_each_vcpu(d, v) + { + if ( is_vcpu_online(v) ) + { + vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); + return; + } + } + + if ( printk_ratelimit() ) + printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", + d); +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -190,7 +213,7 @@ void ffa_raise_rx_buffer_full(struct domain *d) ACCESS_ONCE(ctx->notif.buff_full_pending) = true; if ( !test_and_set_bool(ctx->notif.vm_pending) ) - vgic_inject_irq(d, d->vcpu[0], GUEST_FFA_NOTIF_PEND_INTR_ID, true); + inject_notif_pending(d); } #endif @@ -238,7 +261,6 @@ static void notif_vm_pend_intr(uint16_t vm_id) { struct ffa_ctx *ctx; struct domain *d; - struct vcpu *v; /* * vm_id == 0 means a notifications pending for Xen itself, but @@ -277,24 +299,7 @@ static void notif_vm_pend_intr(uint16_t vm_id) * it. */ ACCESS_ONCE(ctx->notif.secure_pending) = true; - - /* - * Since we're only delivering global notification, always - * deliver to the first online vCPU. It doesn't matter - * which we chose, as long as it's available. - */ - for_each_vcpu(d, v) - { - if ( is_vcpu_online(v) ) - { - vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, - true); - break; - } - } - if ( !v && printk_ratelimit() ) - printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", - d); + inject_notif_pending(d); out_unlock: rcu_unlock_domain(d); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284302.1566131 (Exim 4.92) (envelope-from ) id 1wDjRs-0005lk-Lj; Fri, 17 Apr 2026 13:41:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284302.1566131; Fri, 17 Apr 2026 13:41:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRs-0005ld-J0; Fri, 17 Apr 2026 13:41:32 +0000 Received: by outflank-mailman (input) for mailman id 1284302; Fri, 17 Apr 2026 13:41:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRr-0005cp-T0 for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:41:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjRr-000Ejb-9z for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:41:31 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23878-5cb7-0a2a0a5109dd-0a2a450a8746-26 for ; Fri, 17 Apr 2026 15:41:31 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e2388a-56b3-0a2a450a0019-d98c6eacc2a8-1 for ; Fri, 17 Apr 2026 15:41:31 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 845031516; Fri, 17 Apr 2026 06:41:24 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D5E8A3F7D8; Fri, 17 Apr 2026 06:41:28 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433290; bh=caqGVxvnjz0bVK6Ez9rNrj5k4WIzyoABx5lWZ62MqVc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=F/9rK41YnPUbCvUBHCt5U0B3AIRzfayyu4D5MvWYWuc5xGXma+MxvpDDLffQHSAt1 B7Bg4iM3FAywj4XwhUbq14JxtRUZZPfPf8yYJSbdp5KP+U5YjXRuj29S8szj7wmgER JoceslpxERiNOPD+UNgMD4dmFI7ngoNnufOaX6AY= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 2/6] xen/arm: ffa: Track hypervisor notifications in a bitmap Date: Fri, 17 Apr 2026 15:40:50 +0200 Message-ID: <7053b8c14bbe50cc855dad0a82cde2bb10153d2b.1776266307.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776433291-CEB778B7-F8329588/0/0 X-purgate-type: clean X-purgate-size: 4902 Hypervisor notifications are currently tracked with a dedicated buff_full_pending boolean. That state only represents a single HYP notification bit and keeps HYP bitmap handling tied to single-purpose bookkeeping. Replace the boolean with a hypervisor notification bitmap protected by notif_lock. INFO_GET reports pending when the bitmap is non-zero, GET returns and clears the HYP bitmap under the lock, and RX-buffer-full sets FFA_NOTIF_RX_BUFFER_FULL in the bitmap instead of updating separate state. Initialize and clear the bitmap during domain lifecycle handling, and use ctx->ffa_id for bitmap create and destroy so the notification state stays tied to the cached FF-A endpoint ID. No functional changes. Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa_notif.c | 46 ++++++++++++++++++++++++++-------- xen/arch/arm/tee/ffa_private.h | 9 +++++-- 2 files changed, 43 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 07bc5cb3a430..d15119409a25 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -94,8 +94,15 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) notif_pending = test_and_clear_bool(ctx->notif.secure_pending); if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + { notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); + spin_lock(&ctx->notif.notif_lock); + if ( ctx->notif.hyp_pending ) + notif_pending = true; + spin_unlock(&ctx->notif.notif_lock); + } + if ( notif_pending ) { /* A pending global notification for the guest */ @@ -174,12 +181,17 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) w6 = resp.a6; } - if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && - flags & FFA_NOTIF_FLAG_BITMAP_HYP && - test_and_clear_bool(ctx->notif.buff_full_pending) ) + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { - ACCESS_ONCE(ctx->notif.vm_pending) = false; - w7 = FFA_NOTIF_RX_BUFFER_FULL; + spin_lock(&ctx->notif.notif_lock); + + if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pending ) + { + w7 = ctx->notif.hyp_pending; + ctx->notif.hyp_pending = 0; + } + + spin_unlock(&ctx->notif.notif_lock); } ffa_set_regs(regs, FFA_SUCCESS_32, 0, w2, w3, w4, w5, w6, w7); @@ -207,12 +219,17 @@ int32_t ffa_handle_notification_set(struct cpu_user_regs *regs) void ffa_raise_rx_buffer_full(struct domain *d) { struct ffa_ctx *ctx = d->arch.tee; + uint32_t prev_bitmap; if ( !ctx ) return; - ACCESS_ONCE(ctx->notif.buff_full_pending) = true; - if ( !test_and_set_bool(ctx->notif.vm_pending) ) + spin_lock(&ctx->notif.notif_lock); + prev_bitmap = ctx->notif.hyp_pending; + ctx->notif.hyp_pending |= FFA_NOTIF_RX_BUFFER_FULL; + spin_unlock(&ctx->notif.notif_lock); + + if ( !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) ) inject_notif_pending(d); } #endif @@ -426,12 +443,15 @@ void ffa_notif_init(void) int ffa_notif_domain_init(struct domain *d) { + struct ffa_ctx *ctx = d->arch.tee; int32_t res; + spin_lock_init(&ctx->notif.notif_lock); + ctx->notif.hyp_pending = 0; + if ( fw_notif_enabled ) { - - res = ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_vcpus); + res = ffa_notification_bitmap_create(ctx->ffa_id, d->max_vcpus); if ( res ) return -ENOMEM; } @@ -441,10 +461,16 @@ int ffa_notif_domain_init(struct domain *d) void ffa_notif_domain_destroy(struct domain *d) { + struct ffa_ctx *ctx = d->arch.tee; + + spin_lock(&ctx->notif.notif_lock); + ctx->notif.hyp_pending = 0; + spin_unlock(&ctx->notif.notif_lock); + /* * Call bitmap_destroy even if bitmap create failed as the SPMC will * return a DENIED error that we will ignore. */ if ( fw_notif_enabled ) - ffa_notification_bitmap_destroy(ffa_get_vm_id(d)); + ffa_notification_bitmap_destroy(ctx->ffa_id); } diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index c291f32b56ff..5693772481ed 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -340,9 +340,14 @@ struct ffa_ctx_notif { bool vm_pending; /* - * True if domain has buffer full notification pending + * Lock protecting the hypervisor-managed notification state. */ - bool buff_full_pending; + spinlock_t notif_lock; + + /* + * Bitmap of pending hypervisor notifications (for HYP bitmap queries). + */ + uint32_t hyp_pending; }; struct ffa_ctx { -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284305.1566140 (Exim 4.92) (envelope-from ) id 1wDjRv-00062z-Uu; Fri, 17 Apr 2026 13:41:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284305.1566140; Fri, 17 Apr 2026 13:41:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRv-00062s-R5; Fri, 17 Apr 2026 13:41:35 +0000 Received: by outflank-mailman (input) for mailman id 1284305; Fri, 17 Apr 2026 13:41:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRu-0005zq-6m for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:41:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjRt-009kb3-Jo for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:41:33 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23874-e002-0a2a0a5209dd-0a2a4504d544-46 for ; Fri, 17 Apr 2026 15:41:33 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e2388c-1dec-0a2a45040019-d98c6eacd9ca-1 for ; Fri, 17 Apr 2026 15:41:32 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 47521152B; Fri, 17 Apr 2026 06:41:26 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D90C3F7D8; Fri, 17 Apr 2026 06:41:30 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433292; bh=GpMN53OmsGMUNWxbJRMSEFaE53+mcg2MmZqtr/Lo+zY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ucGQGoVsedG3vqsRL/HuomCA0Jz5/3TnwHbqBxEWVCowvK4bG1Xo/y+ovBDsdFWfW rBTnupjUo8k5NpYtaJM/9xf8eDMCYTsLR9ajQX7S2poaQAWt+gaNSbPsLuTeYulTVW SRcArxibT/wa8kwDgYF7hKelE08jkMfcUyucIY9o= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 3/6] xen/arm: ffa: Tighten notification parameter validation Date: Fri, 17 Apr 2026 15:40:51 +0200 Message-ID: <1036add9199c6304eb649854024c74dd0f0192cc.1776266307.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776433293-300413FF-D93CA36A/0/0 X-purgate-type: clean X-purgate-size: 5853 The notification handlers still validate overlapping subsets of their inputs. BIND, UNBIND, and SET each decode caller and destination IDs locally, GET still accepts a non-zero receiver vCPU ID and reserved flag bits, and SET still accepts non-zero NS-virtual flags. BIND also treats unsupported non-zero flag encodings as a supported-feature failure instead of as malformed input. Add ffa_notif_parse_params() and use it to centralize the common caller/destination and non-zero bitmap checks for BIND, UNBIND, and SET. Also reject malformed GET and SET requests locally before touching cached state or forwarding anything to the SPMC. Keep BIND limited to global notifications and reject unsupported non-zero flag encodings with INVALID_PARAMETERS. - add a shared parameter parser for notification caller/destination validation - wire BIND and UNBIND through the shared parser and reject unsupported bind flag encodings with INVALID_PARAMETERS - reject non-zero receiver vCPU and reserved flag bits in FFA_NOTIFICATION_GET - reject non-zero flags in the NS-virtual FFA_NOTIFICATION_SET path Functional impact: malformed notification requests are rejected consistently earlier in the mediator. Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa_notif.c | 61 +++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index d15119409a25..491db3b04df5 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -42,21 +42,40 @@ static void inject_notif_pending(struct domain *d) d); } +static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller_id, + uint16_t dest_id, uint32_t bitmap_lo, + uint32_t bitmap_hi) +{ + if ( caller_id != dom_id || dest_id == dom_id || !dest_id ) + return FFA_RET_INVALID_PARAMETERS; + + if ( !bitmap_lo && !bitmap_hi ) + return FFA_RET_INVALID_PARAMETERS; + + return FFA_RET_OK; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; + struct ffa_ctx *ctx = d->arch.tee; + int32_t ret; uint32_t src_dst = get_user_reg(regs, 1); uint32_t flags = get_user_reg(regs, 2); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst & GENMASK(15, 0); + uint16_t dest_id = src_dst >> 16; - if ( (src_dst & GENMASK(15, 0)) != ffa_get_vm_id(d) ) + if ( flags ) /* Only global notifications are supported */ return FFA_RET_INVALID_PARAMETERS; - if ( flags ) /* Only global notifications are supported */ - return FFA_RET_DENIED; + ret = ffa_notif_parse_params(ctx->ffa_id, caller_id, dest_id, bitmap_lo, + bitmap_hi); + if ( ret ) + return ret; - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, bitmap_lo, bitmap_hi); @@ -66,16 +85,22 @@ int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) { struct domain *d = current->domain; + struct ffa_ctx *ctx = d->arch.tee; + int32_t ret; uint32_t src_dst = get_user_reg(regs, 1); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst & GENMASK(15, 0); + uint16_t dest_id = src_dst >> 16; - if ( (src_dst & GENMASK(15, 0)) != ffa_get_vm_id(d) ) - return FFA_RET_INVALID_PARAMETERS; + ret = ffa_notif_parse_params(ctx->ffa_id, caller_id, dest_id, bitmap_lo, + bitmap_hi); + if ( ret ) + return ret; - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, + bitmap_hi); return FFA_RET_NOT_SUPPORTED; } @@ -142,6 +167,12 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) return; } + if ( recv >> 16 || (flags & GENMASK(31, 4)) ) + { + ffa_set_regs_error(regs, FFA_RET_INVALID_PARAMETERS); + return; + } + if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | FFA_NOTIF_FLAG_BITMAP_SPM )) ) { @@ -204,11 +235,19 @@ int32_t ffa_handle_notification_set(struct cpu_user_regs *regs) uint32_t flags = get_user_reg(regs, 2); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst >> 16; + uint16_t dest_id = src_dst & GENMASK(15, 0); + int32_t ret; + + ret = ffa_notif_parse_params(ffa_get_vm_id(d), caller_id, dest_id, + bitmap_lo, bitmap_hi); + if ( ret ) + return ret; - if ( (src_dst >> 16) != ffa_get_vm_id(d) ) + if ( flags ) return FFA_RET_INVALID_PARAMETERS; - if ( FFA_ID_IS_SECURE(src_dst & GENMASK(15, 0)) && fw_notif_enabled ) + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo, bitmap_hi); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284306.1566149 (Exim 4.92) (envelope-from ) id 1wDjRx-0006I3-9Y; Fri, 17 Apr 2026 13:41:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284306.1566149; Fri, 17 Apr 2026 13:41:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRx-0006Hw-5i; Fri, 17 Apr 2026 13:41:37 +0000 Received: by outflank-mailman (input) for mailman id 1284306; Fri, 17 Apr 2026 13:41:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRv-000617-Dt for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:41:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjRu-009kb3-Qj for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:41:34 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e2387d-e002-0a2a0a5209dd-0a2a4501dbf6-44 for ; Fri, 17 Apr 2026 15:41:34 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e2388e-c1f2-0a2a45010019-d98c6eacc4ba-1 for ; Fri, 17 Apr 2026 15:41:34 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B3C01516; Fri, 17 Apr 2026 06:41:28 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5D90F3F7D8; Fri, 17 Apr 2026 06:41:32 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433293; bh=muz5M8Iqgy9eYpjCmc9pZ8VEHmiBcMu4FfUho63d0M0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZTB9GDnC8dlk4AuK5JEPg+WSaTmt+qDuvHT6F6NOx2Z/7Af49FmybLRpf2vLCeJ+ ZfyhuzZXZe5xRicWkcQ64iNe5zjxp0Y/XgX38wJJYkQm1RyTIJpE5/nSVgBcMVQzfH 99YaNfJX4D5swFgq217QsO69bfIdG3TBCLtW+vmU= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 4/6] xen/arm: ffa: Preserve secure notification state when polling SPMC Date: Fri, 17 Apr 2026 15:40:52 +0200 Message-ID: <5b9ce4a4a3927ce2287ec4db7f864174f53b8f17.1776266307.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776433294-B5468FF4-67EDDF68/0/0 X-purgate-type: clean X-purgate-size: 7136 Secure pending state is latched when the SPMC raises the schedule receiver interrupt, but Xen currently clears that latch too aggressively. Guest FFA_NOTIFICATION_INFO_GET consumes secure_pending even though it only reports pending state, and secure FFA_NOTIFICATION_GET only clears the latch when both SP and SPM bitmaps are requested together. This can drop a pending indication before the receiver retrieves secure notifications, or keep INFO_GET reporting stale secure pending state after a successful GET. Keep secure_pending as a latched indication until secure notifications are actually retrieved. Guest FFA_NOTIFICATION_INFO_GET now reports the latched state without clearing it, while a successful secure FFA_NOTIFICATION_GET clears the latch regardless of which secure bitmap flags were requested. Also protect secure_pending with notif_lock, serialize SPMC INFO_GET polling behind notif_info_lock, and preserve the caller-visible INFO_GET success width. Functional impact: guest INFO_GET preserves the secure pending indication until secure notifications are retrieved, and successful secure GET clears the guest-visible pending latch. Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa_notif.c | 54 +++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 19 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 491db3b04df5..fff00ca2baec 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -18,6 +18,7 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; +static DEFINE_SPINLOCK(notif_info_lock); static void inject_notif_pending(struct domain *d) { @@ -109,6 +110,7 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) { struct domain *d = current->domain; struct ffa_ctx *ctx = d->arch.tee; + uint32_t fid = get_user_reg(regs, 0); bool notif_pending; if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) @@ -117,7 +119,10 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) return; } - notif_pending = test_and_clear_bool(ctx->notif.secure_pending); + spin_lock(&ctx->notif.notif_lock); + notif_pending = ctx->notif.secure_pending; + spin_unlock(&ctx->notif.notif_lock); + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); @@ -131,7 +136,9 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) if ( notif_pending ) { /* A pending global notification for the guest */ - ffa_set_regs(regs, FFA_SUCCESS_64, 0, + ffa_set_regs(regs, + smccc_is_conv_64(fid) ? FFA_SUCCESS_64 : FFA_SUCCESS_32, + 0, 1U << FFA_NOTIF_INFO_GET_ID_COUNT_SHIFT, ffa_get_vm_id(d), 0, 0, 0, 0); } @@ -154,6 +161,8 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) uint32_t w5 = 0; uint32_t w6 = 0; uint32_t w7 = 0; + uint32_t secure_flags = flags & ( FFA_NOTIF_FLAG_BITMAP_SP | + FFA_NOTIF_FLAG_BITMAP_SPM ); if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) { @@ -173,27 +182,16 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) return; } - if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | - FFA_NOTIF_FLAG_BITMAP_SPM )) ) + if ( fw_notif_enabled && secure_flags ) { struct arm_smccc_1_2_regs arg = { .a0 = FFA_NOTIFICATION_GET, .a1 = recv, - .a2 = flags & ( FFA_NOTIF_FLAG_BITMAP_SP | - FFA_NOTIF_FLAG_BITMAP_SPM ), + .a2 = secure_flags, }; struct arm_smccc_1_2_regs resp; int32_t e; - /* - * Clear secure pending if both FFA_NOTIF_FLAG_BITMAP_SP and - * FFA_NOTIF_FLAG_BITMAP_SPM are set since secure world can't have - * any more pending notifications. - */ - if ( ( flags & FFA_NOTIF_FLAG_BITMAP_SP ) && - ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) ) - ACCESS_ONCE(ctx->notif.secure_pending) = false; - arm_smccc_1_2_smc(&arg, &resp); e = ffa_get_ret_code(&resp); if ( e ) @@ -210,6 +208,10 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) if ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) w6 = resp.a6; + + spin_lock(&ctx->notif.notif_lock); + ctx->notif.secure_pending = false; + spin_unlock(&ctx->notif.notif_lock); } if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) @@ -354,7 +356,10 @@ static void notif_vm_pend_intr(uint16_t vm_id) * guarantees that the data structure isn't freed while we're accessing * it. */ - ACCESS_ONCE(ctx->notif.secure_pending) = true; + spin_lock(&ctx->notif.notif_lock); + ctx->notif.secure_pending = true; + spin_unlock(&ctx->notif.notif_lock); + inject_notif_pending(d); out_unlock: @@ -373,11 +378,18 @@ static void notif_sri_action(void *unused) unsigned int n; int32_t res; - do { + if ( !fw_notif_enabled ) + return; + + spin_lock(¬if_info_lock); + + do + { arm_smccc_1_2_smc(&arg, &resp); res = ffa_get_ret_code(&resp); if ( res ) { + spin_unlock(¬if_info_lock); if ( res != FFA_RET_NO_DATA && printk_ratelimit() ) printk(XENLOG_WARNING "ffa: notification info get failed: error %d\n", res); @@ -391,7 +403,7 @@ static void notif_sri_action(void *unused) id_pos = 0; for ( n = 0; n < list_count; n++ ) { - unsigned int count = ((ids_count >> 2 * n) & 0x3) + 1; + unsigned int count = ((ids_count >> (2 * n)) & 0x3) + 1; uint16_t vm_id = get_id_from_resp(&resp, id_pos); notif_vm_pend_intr(vm_id); @@ -399,7 +411,9 @@ static void notif_sri_action(void *unused) id_pos += count; } - } while (resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG); + } while ( resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG ); + + spin_unlock(¬if_info_lock); } static DECLARE_TASKLET(notif_sri_tasklet, notif_sri_action, NULL); @@ -486,6 +500,7 @@ int ffa_notif_domain_init(struct domain *d) int32_t res; spin_lock_init(&ctx->notif.notif_lock); + ctx->notif.secure_pending = false; ctx->notif.hyp_pending = 0; if ( fw_notif_enabled ) @@ -503,6 +518,7 @@ void ffa_notif_domain_destroy(struct domain *d) struct ffa_ctx *ctx = d->arch.tee; spin_lock(&ctx->notif.notif_lock); + ctx->notif.secure_pending = false; ctx->notif.hyp_pending = 0; spin_unlock(&ctx->notif.notif_lock); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284307.1566158 (Exim 4.92) (envelope-from ) id 1wDjRz-0006ZC-I0; Fri, 17 Apr 2026 13:41:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284307.1566158; Fri, 17 Apr 2026 13:41:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRz-0006Yt-DK; Fri, 17 Apr 2026 13:41:39 +0000 Received: by outflank-mailman (input) for mailman id 1284307; Fri, 17 Apr 2026 13:41:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRx-0006Hl-97 for xen-devel@lists.xenproject.org; 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dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433295; bh=K0L3j6rOuFbocNT0G1KNMjoLTTA4P4wveYKXWHNkbsg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B/bQ7sOWm1dxec2RmlYkfebzmi/bx9ZcepiAYslRbJWBW4zioVi1baQfMBdZdGO9e iOsX8RZScJAHJVd/WiJyZMZhoIsRS3//jupKt4dEtgK+DTvoPK9HMnh1zAV9Ezl8AA M3k7OdCTx034h/uFsaB+kER/aYVcEChWw2C1lEcU= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 5/6] xen/arm: ffa: Track VM notification bindings locally Date: Fri, 17 Apr 2026 15:40:53 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1776433296-F620CCF5-86443AD2/0/0 X-purgate-type: clean X-purgate-size: 7406 VM-to-VM notifications need receiver-side bind state so Xen can validate which sender owns each notification bit. Non-secure BIND and UNBIND requests currently have no local state and cannot enforce that contract. Add per-bit VM notification binding state to struct ffa_ctx_notif and use it to handle non-secure BIND and UNBIND requests when CONFIG_FFA_VM_TO_VM is enabled. The update helper validates the whole request under notif_lock before mutating anything, denies bind or unbind when a bit is pending, rejects rebinding to a different sender, and keeps rebinding to the same sender idempotent. Promote vm_pending to a bitmap so the bind logic can reason per notification ID, use that bitmap directly when reporting pending state, and initialize and clear the new VM notification state during domain init and teardown. Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, Xen tracks VM notification bindings locally and validates non-secure bind and unbind requests against that state. Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa_notif.c | 97 ++++++++++++++++++++++++++++++---- xen/arch/arm/tee/ffa_private.h | 15 ++++-- 2 files changed, 99 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index fff00ca2baec..4def701f0130 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -56,6 +56,54 @@ static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller_id, return FFA_RET_OK; } +static int32_t ffa_notif_update_vm_binding(struct ffa_ctx *ctx, + uint16_t dest_id, uint64_t bitmap, + bool bind) +{ + unsigned int id; + int32_t ret = FFA_RET_OK; + + spin_lock(&ctx->notif.notif_lock); + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( !(bitmap & BIT(id, ULL)) ) + continue; + + if ( ctx->notif.vm_pending & BIT(id, ULL) ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + + if ( bind ) + { + if ( ctx->notif.vm_bind[id] != 0 && + ctx->notif.vm_bind[id] != dest_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + else if ( ctx->notif.vm_bind[id] != dest_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( bitmap & BIT(id, ULL) ) + ctx->notif.vm_bind[id] = bind ? dest_id : 0; + } + +out_unlock: + spin_unlock(&ctx->notif.notif_lock); + + return ret; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -76,11 +124,21 @@ int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) if ( ret ) return ret; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, - bitmap_lo, bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, + bitmap_lo, bitmap_hi); - return FFA_RET_NOT_SUPPORTED; + return FFA_RET_NOT_SUPPORTED; + } + + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + return FFA_RET_NOT_SUPPORTED; + + return ffa_notif_update_vm_binding(ctx, dest_id, + ((uint64_t)bitmap_hi << 32) | bitmap_lo, + true); } int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) @@ -99,11 +157,21 @@ int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) if ( ret ) return ret; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, + bitmap_lo, bitmap_hi); - return FFA_RET_NOT_SUPPORTED; + return FFA_RET_NOT_SUPPORTED; + } + + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + return FFA_RET_NOT_SUPPORTED; + + return ffa_notif_update_vm_binding(ctx, dest_id, + ((uint64_t)bitmap_hi << 32) | bitmap_lo, + false); } void ffa_handle_notification_info_get(struct cpu_user_regs *regs) @@ -125,9 +193,10 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { - notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); - spin_lock(&ctx->notif.notif_lock); + if ( ctx->notif.vm_pending ) + notif_pending = true; + if ( ctx->notif.hyp_pending ) notif_pending = true; spin_unlock(&ctx->notif.notif_lock); @@ -497,10 +566,14 @@ void ffa_notif_init(void) int ffa_notif_domain_init(struct domain *d) { struct ffa_ctx *ctx = d->arch.tee; + unsigned int i; int32_t res; spin_lock_init(&ctx->notif.notif_lock); ctx->notif.secure_pending = false; + ctx->notif.vm_pending = 0; + for ( i = 0; i < FFA_NUM_VM_NOTIF; i++ ) + ctx->notif.vm_bind[i] = 0; ctx->notif.hyp_pending = 0; if ( fw_notif_enabled ) @@ -516,9 +589,13 @@ int ffa_notif_domain_init(struct domain *d) void ffa_notif_domain_destroy(struct domain *d) { struct ffa_ctx *ctx = d->arch.tee; + unsigned int i; spin_lock(&ctx->notif.notif_lock); ctx->notif.secure_pending = false; + ctx->notif.vm_pending = 0; + for ( i = 0; i < FFA_NUM_VM_NOTIF; i++ ) + ctx->notif.vm_bind[i] = 0; ctx->notif.hyp_pending = 0; spin_unlock(&ctx->notif.notif_lock); diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index 5693772481ed..6d83afb3d00a 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -236,6 +236,11 @@ #define FFA_NOTIF_INFO_GET_ID_COUNT_MASK 0x1F #define FFA_NOTIF_RX_BUFFER_FULL BIT(0, U) +#define FFA_NUM_VM_NOTIF 64U + +#if FFA_NUM_VM_NOTIF > 64 +#error "FFA_NUM_VM_NOTIF must be <= 64" +#endif /* Feature IDs used with FFA_FEATURES */ #define FFA_FEATURE_NOTIF_PEND_INTR 0x1U @@ -334,10 +339,14 @@ struct ffa_ctx_notif { bool secure_pending; /* - * True if domain is reported by FFA_NOTIFICATION_INFO_GET to have - * pending notifications from VMs (including framework ones). + * Bitmap of pending notifications from VMs (including framework ones). + */ + uint64_t vm_pending; + + /* + * Source endpoint bound to each VM notification ID (0 means unbound). */ - bool vm_pending; + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; /* * Lock protecting the hypervisor-managed notification state. -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:41:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:41:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284310.1566162 (Exim 4.92) (envelope-from ) id 1wDjRz-0006cF-Rn; Fri, 17 Apr 2026 13:41:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284310.1566162; Fri, 17 Apr 2026 13:41:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjRz-0006b5-Lc; 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Fri, 17 Apr 2026 06:41:31 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.89.170]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D6D373F7D8; Fri, 17 Apr 2026 06:41:35 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776433297; bh=cZZGPI6vYtUzakFAvu0YBSmNdIu2H7Rzaign3ej2VlA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y1XalVlal1hWmaJVNRfQYNZEX63Jd6p5Jf9DVO7ivurdKHvPxODE93GmrQBpPyrXJ OjFOR1PtxYL6A0kjZi4T+J7W8qdXR8ejrNDRuD3yPJcJiPxo/NdQw8yIZ1tM/sLTsI bzCi6GUXv+iF0ls9DWhFLcmdMLQFkRYjyYCyo+jY= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH 6/6] xen/arm: ffa: Deliver VM-to-VM notifications locally Date: Fri, 17 Apr 2026 15:40:54 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776433298-2BB6C938-83D67431/0/0 X-purgate-type: clean X-purgate-size: 12215 VM notification binding and pending tracking exist for non-secure endpoints, but FFA_NOTIFICATION_SET still only forwards secure destinations to the SPMC. Non-secure VMs therefore cannot receive notifications from other VMs. Local NPI delivery also needs explicit re-arm tracking so repeated raises are not lost while the interrupt is already pending. Add a local VM notification delivery path for non-secure destinations. notification_set_vm() resolves the destination endpoint, verifies that every requested bit is bound to the sender, sets the receiver's vm_pending bitmap under notif_lock, and raises an NPI only when the receiver transitions from no local pending notifications to some. Track whether a local NPI is already armed with notif_irq_raised, clear that state once both VM and hypervisor pending bitmaps are drained, and roll back newly-added VM pending bits if no destination vCPU is online. Also expose firmware notification availability so FFA_FEATURES only advertises notification support when it is actually provided by the firmware or by CONFIG_FFA_VM_TO_VM. Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, non-secure FFA_NOTIFICATION_SET delivers VM-to-VM notifications locally and keeps NPI delivery reliable across repeated raises. Signed-off-by: Bertrand Marquis --- xen/arch/arm/tee/ffa.c | 24 +++++-- xen/arch/arm/tee/ffa_notif.c | 126 +++++++++++++++++++++++++++++++-- xen/arch/arm/tee/ffa_private.h | 11 ++- 3 files changed, 147 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c index 1fe33f26454a..7fe021049cba 100644 --- a/xen/arch/arm/tee/ffa.c +++ b/xen/arch/arm/tee/ffa.c @@ -39,8 +39,13 @@ * o FFA_MSG_SEND_DIRECT_REQ: * - only supported from a VM to an SP * o FFA_NOTIFICATION_*: + * - only supported when firmware notifications are enabled or VM-to-VM + * support is built in * - only supports global notifications, that is, per vCPU notifications - * are not supported + * are not supported and secure per-vCPU notification information is + * not forwarded + * - the source endpoint ID reported for a notification may no longer + * exist by the time the receiver consumes it * - doesn't support signalling the secondary scheduler of pending * notification for secure partitions * - doesn't support notifications for Xen itself @@ -245,6 +250,8 @@ static void handle_features(struct cpu_user_regs *regs) uint32_t a1 = get_user_reg(regs, 1); struct domain *d = current->domain; struct ffa_ctx *ctx = d->arch.tee; + bool notif_supported = IS_ENABLED(CONFIG_FFA_VM_TO_VM) || + ffa_notif_fw_enabled(); /* * FFA_FEATURES defines w2 as input properties only for specific @@ -343,10 +350,16 @@ static void handle_features(struct cpu_user_regs *regs) break; case FFA_FEATURE_NOTIF_PEND_INTR: - ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; case FFA_FEATURE_SCHEDULE_RECV_INTR: - ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; case FFA_PARTITION_INFO_GET_REGS: if ( ACCESS_ONCE(ctx->guest_vers) >= FFA_VERSION_1_2 ) @@ -361,7 +374,10 @@ static void handle_features(struct cpu_user_regs *regs) case FFA_NOTIFICATION_SET: case FFA_NOTIFICATION_INFO_GET_32: case FFA_NOTIFICATION_INFO_GET_64: - ffa_set_regs_success(regs, 0, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, 0, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; default: ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 4def701f0130..e77321244926 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -20,7 +20,12 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; static DEFINE_SPINLOCK(notif_info_lock); -static void inject_notif_pending(struct domain *d) +bool ffa_notif_fw_enabled(void) +{ + return fw_notif_enabled; +} + +static bool inject_notif_pending(struct domain *d) { struct vcpu *v; @@ -34,13 +39,15 @@ static void inject_notif_pending(struct domain *d) if ( is_vcpu_online(v) ) { vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); - return; + return true; } } if ( printk_ratelimit() ) printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", d); + + return false; } static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller_id, @@ -104,6 +111,73 @@ out_unlock: return ret; } +/* + * Deliver a VM-to-VM notification. ctx->notif.notif_lock protects + * vm_bind/vm_pending so callers must not hold it already. + */ +static int32_t notification_set_vm(uint16_t dst_id, uint16_t src_id, + uint32_t flags, uint64_t bitmap) +{ + struct domain *dst_d; + struct ffa_ctx *dst_ctx; + unsigned int id; + int32_t ret; + uint64_t prev_bitmap = 0; + uint64_t new_bitmap; + bool inject = false; + + if ( flags ) + return FFA_RET_INVALID_PARAMETERS; + + ret = ffa_endpoint_domain_lookup(dst_id, &dst_d, &dst_ctx); + if ( ret ) + return ret; + + ret = FFA_RET_OK; + + spin_lock(&dst_ctx->notif.notif_lock); + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( !(bitmap & BIT(id, ULL)) ) + continue; + + if ( dst_ctx->notif.vm_bind[id] != src_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + + prev_bitmap = dst_ctx->notif.vm_pending; + dst_ctx->notif.vm_pending |= bitmap; + if ( !dst_ctx->notif.notif_irq_raised && + (dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) ) + { + dst_ctx->notif.notif_irq_raised = true; + inject = true; + } + +out_unlock: + spin_unlock(&dst_ctx->notif.notif_lock); + + new_bitmap = bitmap & ~prev_bitmap; + if ( ret == FFA_RET_OK && inject && new_bitmap && + !inject_notif_pending(dst_d) ) + { + spin_lock(&dst_ctx->notif.notif_lock); + dst_ctx->notif.vm_pending &= ~new_bitmap; + if ( !(dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) ) + dst_ctx->notif.notif_irq_raised = false; + spin_unlock(&dst_ctx->notif.notif_lock); + ret = FFA_RET_DENIED; + } + + rcu_unlock_domain(dst_d); + + return ret; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -285,6 +359,8 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { + bool pending; + spin_lock(&ctx->notif.notif_lock); if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pending ) @@ -293,6 +369,18 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) ctx->notif.hyp_pending = 0; } + if ( (flags & FFA_NOTIF_FLAG_BITMAP_VM) && ctx->notif.vm_pending ) + { + w4 = (uint32_t)(ctx->notif.vm_pending & GENMASK(31, 0)); + w5 = (uint32_t)((ctx->notif.vm_pending >> 32) & GENMASK(31, 0)); + ctx->notif.vm_pending = 0; + } + + pending = (ctx->notif.hyp_pending != 0) || + (ctx->notif.vm_pending != 0); + if ( !pending ) + ctx->notif.notif_irq_raised = false; + spin_unlock(&ctx->notif.notif_lock); } @@ -318,9 +406,17 @@ int32_t ffa_handle_notification_set(struct cpu_user_regs *regs) if ( flags ) return FFA_RET_INVALID_PARAMETERS; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, + bitmap_lo, bitmap_hi); + } + else if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + { + return notification_set_vm(dest_id, caller_id, flags, + ((uint64_t)bitmap_hi << 32) | bitmap_lo); + } return FFA_RET_NOT_SUPPORTED; } @@ -330,6 +426,7 @@ void ffa_raise_rx_buffer_full(struct domain *d) { struct ffa_ctx *ctx = d->arch.tee; uint32_t prev_bitmap; + bool inject = false; if ( !ctx ) return; @@ -337,10 +434,23 @@ void ffa_raise_rx_buffer_full(struct domain *d) spin_lock(&ctx->notif.notif_lock); prev_bitmap = ctx->notif.hyp_pending; ctx->notif.hyp_pending |= FFA_NOTIF_RX_BUFFER_FULL; + if ( !ctx->notif.notif_irq_raised && + (ctx->notif.vm_pending || ctx->notif.hyp_pending) ) + { + ctx->notif.notif_irq_raised = true; + inject = true; + } spin_unlock(&ctx->notif.notif_lock); - if ( !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) ) - inject_notif_pending(d); + if ( inject && !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) && + !inject_notif_pending(d) ) + { + spin_lock(&ctx->notif.notif_lock); + ctx->notif.hyp_pending &= ~FFA_NOTIF_RX_BUFFER_FULL; + if ( !(ctx->notif.vm_pending || ctx->notif.hyp_pending) ) + ctx->notif.notif_irq_raised = false; + spin_unlock(&ctx->notif.notif_lock); + } } #endif @@ -572,6 +682,7 @@ int ffa_notif_domain_init(struct domain *d) spin_lock_init(&ctx->notif.notif_lock); ctx->notif.secure_pending = false; ctx->notif.vm_pending = 0; + ctx->notif.notif_irq_raised = false; for ( i = 0; i < FFA_NUM_VM_NOTIF; i++ ) ctx->notif.vm_bind[i] = 0; ctx->notif.hyp_pending = 0; @@ -594,6 +705,7 @@ void ffa_notif_domain_destroy(struct domain *d) spin_lock(&ctx->notif.notif_lock); ctx->notif.secure_pending = false; ctx->notif.vm_pending = 0; + ctx->notif.notif_irq_raised = false; for ( i = 0; i < FFA_NUM_VM_NOTIF; i++ ) ctx->notif.vm_bind[i] = 0; ctx->notif.hyp_pending = 0; diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index 6d83afb3d00a..5bb19bd11dd0 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -344,13 +344,17 @@ struct ffa_ctx_notif { uint64_t vm_pending; /* - * Source endpoint bound to each VM notification ID (0 means unbound). + * Tracks whether an NPI has been raised for local pending notifications. + * Protected by notif_lock. */ - uint16_t vm_bind[FFA_NUM_VM_NOTIF]; + bool notif_irq_raised; /* - * Lock protecting the hypervisor-managed notification state. + * Source endpoint bound to each VM notification ID (0 means unbound). */ + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; + + /* Lock protecting local notification state. */ spinlock_t notif_lock; /* @@ -493,6 +497,7 @@ void ffa_notif_init(void); void ffa_notif_init_interrupt(void); int ffa_notif_domain_init(struct domain *d); void ffa_notif_domain_destroy(struct domain *d); +bool ffa_notif_fw_enabled(void); int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs); int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:48:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:48:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284370.1566176 (Exim 4.92) (envelope-from ) id 1wDjYA-0000jx-Qg; Fri, 17 Apr 2026 13:48:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284370.1566176; Fri, 17 Apr 2026 13:48:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjYA-0000jq-Mk; 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Already ... >>> >>>> + return vsfile_id; >>> >>> ... here the value can be stale, if indeed there is a chance of races. >>> Did you perhaps mean to use ACCESS_ONCE() here and where the value is >>> set? >> >> ACCESS_ONCE() isn't guarantee only compiler re-ordering (as basically it >> is just volatile-related stuff inisde the macros)? >> >> Generally, I think that that guest_file_id is needed to be updated only >> during migration of vCPU from one pCPU to another and I expect that >> during this migration vCPU isn't active, so no one will want to read >> imsic_state->guest_file_id. But on the other hand, there is: >> bool imsic_has_interrupt(const struct vcpu *vcpu) >> { >> ... >> /* >> * The IMSIC SW-file directly injects interrupt via hvip so >> * only check for interrupt when IMSIC VS-file is being used. >> */ >> >> read_lock_irqsave(&imsic_state->vsfile_lock, flags); >> if ( imsic_state->vsfile_pcpu != NR_CPUS ) >> ret = !!(csr_read(CSR_HGEIP) & BIT(imsic_state->guest_file_id, >> UL)); >> read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); >> ... >> } >> which I think could be called in parallel with with migration, so then >> still lock are needed. > > None of this addresses my pointing out that the returned value will be > stale by the point the caller gets to look at it. Yes, I agree that lock in vcpu_guest_file_id() is useless and it should be on the caller side and used for the whole IMSIC state access. But ... > Which in turn raises > said question about the use of a lock. If you read > imsic_state->guest_file_id atomically (i.e. excluding tearing of reads), > the value seen / used will be stale as with the lock in use. Unless of > course there's yet another aspect hidden somewhere in what is not being > explained. ... I am not sure that I get this part. If I am somewhere in migration code where I took write lock to update imsic state (and of course ->guest_file_id as part of it) then if someone else in parallel calls imsic_has_interrupt() then it won't enter critical section where ->guest_file_id is trying to be read so no stale ->guest_file_id will be read. Then does it make sense to use ACCESS_ONCE() during read and write of ->guest_file_id in such use cases? ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 13:50:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 13:50:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284384.1566185 (Exim 4.92) (envelope-from ) id 1wDjaq-0002E7-6Y; Fri, 17 Apr 2026 13:50:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284384.1566185; Fri, 17 Apr 2026 13:50:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjaq-0002E0-2q; Fri, 17 Apr 2026 13:50:48 +0000 Received: by outflank-mailman (input) for mailman id 1284384; Fri, 17 Apr 2026 13:50:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjao-0002Dr-Hk for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 13:50:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjan-0051ot-R4 for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 15:50:45 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23a9d-5cb7-0a2a0a5109dd-0a2a450998da-46 for ; Fri, 17 Apr 2026 15:50:45 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e23ab5-2497-0a2a45090019-d155802fd0ff-3 for ; Fri, 17 Apr 2026 15:50:45 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-488e1a8ac40so9890065e9.2 for ; Fri, 17 Apr 2026 06:50:45 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776433845-410B3A53-9299B9C3/0/0 X-purgate-type: clean X-purgate-size: 3405 On 17.04.2026 10:10, Oleksii Kurochko wrote: > On 4/16/26 1:42 PM, Jan Beulich wrote: >> On 10.04.2026 17:40, Oleksii Kurochko wrote: >>> On 4/1/26 5:05 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> Guests using the IMSIC interrupt controller require a corresponding >>>>> Device Tree description. Add support for generating an IMSIC node when >>>>> building the guest DT. >>>>> >>>>> Keep a reference to the host IMSIC DT node and reuse its compatible >>>>> property while constructing the guest-visible node. >>>> >>>> Again raises a migration concern. Presumably a guest would then be able >>>> to migrate only to other hosts with the same compatible property. >>> >>> Right, but I don't think we can do too much and it is the simplest >>> approach just to migrate to hosts with the same compatible property. >>> >>> If you concern is about DTS property then for IMSIC it will be always >>> riscv,imsics according to the RISC-V DT spec. (IIRC, the only other >>> option could be qemu,riscv). Actually, I can just hard code >>> "riscv,imsic" explicitly instead of re-using of host name. >>> >>> If your concern is that we will migrate to a host which doesn't support >>> IMSIC at all then we should or (a) don't migrate to such host or (b) >>> provide an emulation of IMSIC. And option (b) would be terrible from at >>> least performance point of view. >> >> That would all be only a secondary concern - in an IMSIC is needed right >> now, so be it. My primary concern is with inheriting the host IMSIC's >> properties. > Could we do really something better? > > At the moment, the following properties are inhereted: > node name -> not an issue at all, it is just a name of the node and > generally doesn't matter what it is in the matter of DTB generation as > phandle number of this node will be used as pointer to this node, not > the name. If it would be better I can hard code just "imsic". > > compatible -> also, not a big issue. According to current DT RISC-V > bindings it could be just "riscv,imsic". But then I have the question > what if one day someone will come up with own implementation of IMSIC > then "riscv,own-imsic" will be in host DTB and so I expect that guest > DTB should have it as this h/w expects to use specifically OWN-IMSIC > driver. So it seems okay to copy compatible from host DTB. Yes, if > migration will happen where just "riscv,imsic" is supported then it > can't be easily migrated to such h/w and its okay. But generally I > expect that compatible will always riscv,imsic. > > riscv,num-ids -> generally, it could be any number from [63, 2047], but > it seems like there is no any sense if put a value bigger then > guest-num-ids=min(riscv,num-ids, riscv,num-guest-ids) for guest as h/w > can't support more then that. At the same time I don't see too much > sense to tell a guest that it supports less then guest-num-ids. What is > the problem to give a guest a maximum that IMSIC could provide? With > migration, of course, it will be an issue if new host will support > different number of riscv,num-ids but I don't know what we can do better > then just avoid migration to such hosts if old-num-ids > new-num-ids > without significant performance drop. This is exactly why an admin may want to limit what a guest gets to see / use. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776434028-815848B7-CE70404B/0/0 X-purgate-type: clean X-purgate-size: 3812 On 17.04.2026 11:01, Oleksii Kurochko wrote: > > > On 4/16/26 1:49 PM, Jan Beulich wrote: >> On 13.04.2026 10:43, Oleksii Kurochko wrote: >>> On 4/1/26 5:16 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> + res = fdt_property(fdt, "#interrupt-cells", data, len); >>>>> + if ( res ) >>>>> + return res; >>>> >>>> So host properties are again directly handed through to the guest? >>> >>> I am not sure that it can be different from what host has. >>> >>>> Shouldn't the number of interrupts (aiui that's the "number of cells" >>>> here) a guest gets be independent from the host it runs one? >>> >>> The #interrupt-cells property specifies how many 32-bit values (cells) >>> are used to encode a single interrupt specifier when referencing this >>> interrupt controller from another device node. >>> In this APLIC schema, it's fixed at const: 2, meaning every interrupt >>> reference requires exactly two cells — typically: >>> >>> Cell 1 — the interrupt source number (which of the riscv,num-sources >>> wired inputs) >>> Cell 2 — the interrupt type/trigger flags (e.g. edge vs. level, active >>> high/low) >> >> So what if #interrupt-cells is 3 in the DT Xen is handed? If Xen can >> cope, should that value really also be handed through to guests? > > I would say that it depends on what cell 3 will represent. But likely it > will be needed to hand it to the guest. > >> >>>>> + regs = dt_get_property(aplic_node, "reg", &len); >>>>> + if ( !regs ) >>>>> + { >>>>> + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); >>>>> + return -FDT_ERR_XEN(ENOENT); >>>>> + } >>>>> + >>>>> + res = fdt_property(fdt, "reg", regs, len); >>>>> + if ( res ) >>>>> + return res; >>>>> + >>>>> + data = dt_get_property(aplic_node, "riscv,num-sources", &len); >>>>> + if ( !data ) >>>>> + { >>>>> + printk("%s: Can't find 'riscv,num-sources' property\n", >>>>> + aplic_node->full_name); >>>>> + return -FDT_ERR_XEN(ENOENT); >>>>> + } >>>>> + >>>>> + res = fdt_property(fdt, "riscv,num-sources", data, len); >>>>> + if ( res ) >>>>> + return res; >>>> >>>> Or maybe this is the number of interrupts? >>> >>> This is the total count of hardware interrupt lines wired into this >>> APLIC domain. >>> >>> It could be independent from the host it runs one but looking at the >>> possible range [1,1023] for this property if we will put for a guest >>> lets say 22 but new host support only 20 when we will be in a trouble >>> anyway. >> >> Correct. But if you had some hosts with 1024 and some with 256, how >> would you bring up a guest on the former to later be able to migrate >> it to one of the latter when guests inherit the count from the host? > > It will be impossible to do that without emulation, It's not quite clear to me why this would be. > so I expect it will > be easier to simply forbid migration to such a host. > > Basically, it is just a game of numbers. We could try to estimate how > many interrupts are needed for the guest, or for simplicity use some > hard-coded number (say 128 or 256, something “pretty small”). Will it > resolve the migration issue? Partially yes, but not fully, as there > could always be cases where the new host’s number of sources is lower > than our hard-coded “small guest value.” So having a smaller value will > likely help on average and will allow to support more h/w migration to > which could happen, but the migration issue will still be present. An admin, knowing the capabilities of all hosts in a pool, can suitably limit guests intended to move among hosts. No migration issue at all. Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 17 14:02:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 14:02:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284407.1566202 (Exim 4.92) (envelope-from ) id 1wDjlS-0004nl-Ce; Fri, 17 Apr 2026 14:01:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284407.1566202; Fri, 17 Apr 2026 14:01:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjlS-0004ne-A3; Fri, 17 Apr 2026 14:01:46 +0000 Received: by outflank-mailman (input) for mailman id 1284407; Fri, 17 Apr 2026 14:01:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDjlR-0004nY-EX for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 14:01:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjlN-0053g5-O5 for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 16:01:41 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23d42-5cb7-0a2a0a5109dd-0a2a450ae8d2-8 for ; Fri, 17 Apr 2026 16:01:41 +0200 Received: from [209.85.208.182] (helo=mail-lj1-f182.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e23d45-56b3-0a2a450a0019-d155d0b6c85e-3 for ; Fri, 17 Apr 2026 16:01:41 +0200 Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-38e936caafeso7222371fa.2 for ; Fri, 17 Apr 2026 07:01:41 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Add support for generating an IMSIC node when >>>>>> building the guest DT. >>>>>> >>>>>> Keep a reference to the host IMSIC DT node and reuse its compatible >>>>>> property while constructing the guest-visible node. >>>>> >>>>> Again raises a migration concern. Presumably a guest would then be able >>>>> to migrate only to other hosts with the same compatible property. >>>> >>>> Right, but I don't think we can do too much and it is the simplest >>>> approach just to migrate to hosts with the same compatible property. >>>> >>>> If you concern is about DTS property then for IMSIC it will be always >>>> riscv,imsics according to the RISC-V DT spec. (IIRC, the only other >>>> option could be qemu,riscv). Actually, I can just hard code >>>> "riscv,imsic" explicitly instead of re-using of host name. >>>> >>>> If your concern is that we will migrate to a host which doesn't support >>>> IMSIC at all then we should or (a) don't migrate to such host or (b) >>>> provide an emulation of IMSIC. And option (b) would be terrible from at >>>> least performance point of view. >>> >>> That would all be only a secondary concern - in an IMSIC is needed right >>> now, so be it. My primary concern is with inheriting the host IMSIC's >>> properties. >> Could we do really something better? >> >> At the moment, the following properties are inhereted: >> node name -> not an issue at all, it is just a name of the node and >> generally doesn't matter what it is in the matter of DTB generation as >> phandle number of this node will be used as pointer to this node, not >> the name. If it would be better I can hard code just "imsic". >> >> compatible -> also, not a big issue. According to current DT RISC-V >> bindings it could be just "riscv,imsic". But then I have the question >> what if one day someone will come up with own implementation of IMSIC >> then "riscv,own-imsic" will be in host DTB and so I expect that guest >> DTB should have it as this h/w expects to use specifically OWN-IMSIC >> driver. So it seems okay to copy compatible from host DTB. Yes, if >> migration will happen where just "riscv,imsic" is supported then it >> can't be easily migrated to such h/w and its okay. But generally I >> expect that compatible will always riscv,imsic. >> >> riscv,num-ids -> generally, it could be any number from [63, 2047], but >> it seems like there is no any sense if put a value bigger then >> guest-num-ids=min(riscv,num-ids, riscv,num-guest-ids) for guest as h/w >> can't support more then that. At the same time I don't see too much >> sense to tell a guest that it supports less then guest-num-ids. What is >> the problem to give a guest a maximum that IMSIC could provide? With >> migration, of course, it will be an issue if new host will support >> different number of riscv,num-ids but I don't know what we can do better >> then just avoid migration to such hosts if old-num-ids > new-num-ids >> without significant performance drop. > > This is exactly why an admin may want to limit what a guest gets to > see / use. Would it be better then provide a separate define for riscv, num-ids and use it here? Maybe here it makes sense to re-use already provided by DT binding property: riscv,num-guest-ids: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 63 maximum: 2047 description: Number of interrupt identities are supported by IMSIC guest interrupt file. When not specified it is assumed to be same as specified by the riscv,num-ids property. And if riscv,num-guest-ids the use some predefined in define value? Does it make sense then provide the similar defines for compatible and node name or for that properties it would be okay to re-use what host DTB IMSIC node provides? ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 14:07:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 14:07:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284419.1566213 (Exim 4.92) (envelope-from ) id 1wDjqn-0005OV-0I; Fri, 17 Apr 2026 14:07:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284419.1566213; Fri, 17 Apr 2026 14:07:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjqm-0005OO-S0; Fri, 17 Apr 2026 14:07:16 +0000 Received: by outflank-mailman (input) for mailman id 1284419; Fri, 17 Apr 2026 14:07:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjql-0005NW-Nx for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 14:07:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjql-00DUuq-07 for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 16:07:15 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23e8f-bab6-0a2a0a5309dd-0a2a4503da90-30 for ; Fri, 17 Apr 2026 16:07:14 +0200 Received: from [209.85.221.45] (helo=mail-wr1-f45.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e23e92-672d-0a2a45030019-d155dd2db8a2-3 for ; Fri, 17 Apr 2026 16:07:14 +0200 Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-43d76dd4ee8so636988f8f.2 for ; Fri, 17 Apr 2026 07:07:14 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776434834-2BF6A938-EBD60914/0/0 X-purgate-type: clean X-purgate-size: 4282 On 17.04.2026 13:34, Oleksii Kurochko wrote: > On 4/16/26 2:21 PM, Jan Beulich wrote: >> On 13.04.2026 16:42, Oleksii Kurochko wrote: >>> On 4/2/26 12:03 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> @@ -14,12 +27,109 @@ bool aia_available(void) >>>>> return is_aia_available; >>>>> } >>>>> >>>>> +int __init vgein_init(unsigned int cpu) >>>> >>>> If this needs invoking once per CPU being brought up, it can't be __init. >>> >>> Yes, it is going to be called inside the secondary CPU bring-up function. >>> >>> __init sections are removed much later, after all CPUs are brought up, >>> so it looks like that at the moment when secondary CPUs are being >>> brought up, __init still exists and can be called. >> >> No. And I said so before. See XEN_SYSCTL_cpu_hotplug (and ignore it having >> "hotplug" in the name, but merely consider that you can take CPUs offline >> at runtime, and later bring them online again). > > Thanks, now it makes sense to drop __init. > >>>> Also - static? >>> >>> It isn't static because it will be called inside the secondary CPU >>> bring-up function. >> >> As it doesn't need calling from the outside for the boot CPU, it's not >> obvious why it would need calling from the outside for secondary ones. > > I think I am confused here by what do you mean by "calling from the > outside". As in "from another translation unit". > It should be called during boot or secondary CPU initialization (if AIA > is used), right? > Then considering that VGEIN-related stuff is connected to AIA then > vgein_init() is expected to live in aia.c and considering that it wants > to be called by secondary CPU boot code it can't be static. Putting my question differently: Why is there a difference here between boot CPU and secondary CPUs. My (general) expectation would be that either the function wants calling from outside of aia.c in all cases, or it could be static (now and later). >>>>> +{ >>>>> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); >>>>> + >>>>> + csr_write(CSR_HGEIE, -1UL); >>>>> + vgein->geilen = flsl(csr_read(CSR_HGEIE)); >>>>> + csr_write(CSR_HGEIE, 0); >>>>> + if ( vgein->geilen ) >>>>> + vgein->geilen--; >>>> >>>> I don't understand this. The "len" in "geilen" stands for "length", I suppose, >>>> i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of >>>> bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED >>>> and may be zero. This number is known as GEILEN." This may or may not include >>>> bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is >>>> nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but >>>> that's not unambiguous. >>> >>> But they explicitly wrote that: The least-significant bits are >>> implemented first, apart from bit 0. So bit 0 is explicitly excluded. >> >> Fine, but not including it in anything named *LEN feels - as said - ambiguous. > > Agree, it is. I just tried to follow the spec naming here. But I am okay > to rename it to max_gein, for example. Perhaps better stick to spec naming, but consider adding a clarifying comment. >>>>> + /* >>>>> + * All vCPU guest interrupt files are used and we don't support a case >>>>> + * when number of vCPU on 1 pCPU is bigger then geilen. >>>>> + */ >>>> >>>> This wants checking in vgein_init() then. CPUs (beyond the boot one) >>>> violating this should not be brought online. >>> >>> It'll be nice. But we can't know how many vCPUs will be ran on pCPU when >>> vgein_init() is executed. >> >> I don't understand: How does it matter how many vCPU-s will exist later on >> (and will run wherever)? > > IIUC, you want to check what is mentioned in the comment in vcpu_init(). > The comment says that it is checking that number of vCPU on one pCPU > isn't bigger then geilen. To check that we have to know an amount of > vCPU potentially will be ran on pCPU. Well, not quite. I don't understand at all why the number of vCPU-s in a system would be limited by any pCPU property. I don't think we have any such constraint on x86, for example. Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 17 14:12:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 14:12:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284430.1566220 (Exim 4.92) (envelope-from ) id 1wDjvi-0007BJ-Gi; Fri, 17 Apr 2026 14:12:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284430.1566220; Fri, 17 Apr 2026 14:12:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjvi-0007BC-E5; Fri, 17 Apr 2026 14:12:22 +0000 Received: by outflank-mailman (input) for mailman id 1284430; Fri, 17 Apr 2026 14:12:21 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDjvh-0007Al-2z for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 14:12:21 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDjvg-009qSb-CV for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 16:12:20 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e23fbb-2eae-0a2a0a5409dd-0a2a4504e340-18 for ; Fri, 17 Apr 2026 16:12:20 +0200 Received: from [209.85.221.45] (helo=mail-wr1-f45.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e23f4b-1dec-0a2a45040019-d155dd2dec04-3 for ; Fri, 17 Apr 2026 16:10:20 +0200 Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-43d74086e5bso668191f8f.0 for ; Fri, 17 Apr 2026 07:10:20 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776435020-2997A3FF-ED467573/0/0 X-purgate-type: clean X-purgate-size: 4600 On 17.04.2026 16:01, Oleksii Kurochko wrote: > > > On 4/17/26 3:50 PM, Jan Beulich wrote: >> On 17.04.2026 10:10, Oleksii Kurochko wrote: >>> On 4/16/26 1:42 PM, Jan Beulich wrote: >>>> On 10.04.2026 17:40, Oleksii Kurochko wrote: >>>>> On 4/1/26 5:05 PM, Jan Beulich wrote: >>>>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>>>> Guests using the IMSIC interrupt controller require a corresponding >>>>>>> Device Tree description. Add support for generating an IMSIC node when >>>>>>> building the guest DT. >>>>>>> >>>>>>> Keep a reference to the host IMSIC DT node and reuse its compatible >>>>>>> property while constructing the guest-visible node. >>>>>> >>>>>> Again raises a migration concern. Presumably a guest would then be able >>>>>> to migrate only to other hosts with the same compatible property. >>>>> >>>>> Right, but I don't think we can do too much and it is the simplest >>>>> approach just to migrate to hosts with the same compatible property. >>>>> >>>>> If you concern is about DTS property then for IMSIC it will be always >>>>> riscv,imsics according to the RISC-V DT spec. (IIRC, the only other >>>>> option could be qemu,riscv). Actually, I can just hard code >>>>> "riscv,imsic" explicitly instead of re-using of host name. >>>>> >>>>> If your concern is that we will migrate to a host which doesn't support >>>>> IMSIC at all then we should or (a) don't migrate to such host or (b) >>>>> provide an emulation of IMSIC. And option (b) would be terrible from at >>>>> least performance point of view. >>>> >>>> That would all be only a secondary concern - in an IMSIC is needed right >>>> now, so be it. My primary concern is with inheriting the host IMSIC's >>>> properties. >>> Could we do really something better? >>> >>> At the moment, the following properties are inhereted: >>> node name -> not an issue at all, it is just a name of the node and >>> generally doesn't matter what it is in the matter of DTB generation as >>> phandle number of this node will be used as pointer to this node, not >>> the name. If it would be better I can hard code just "imsic". >>> >>> compatible -> also, not a big issue. According to current DT RISC-V >>> bindings it could be just "riscv,imsic". But then I have the question >>> what if one day someone will come up with own implementation of IMSIC >>> then "riscv,own-imsic" will be in host DTB and so I expect that guest >>> DTB should have it as this h/w expects to use specifically OWN-IMSIC >>> driver. So it seems okay to copy compatible from host DTB. Yes, if >>> migration will happen where just "riscv,imsic" is supported then it >>> can't be easily migrated to such h/w and its okay. But generally I >>> expect that compatible will always riscv,imsic. >>> >>> riscv,num-ids -> generally, it could be any number from [63, 2047], but >>> it seems like there is no any sense if put a value bigger then >>> guest-num-ids=min(riscv,num-ids, riscv,num-guest-ids) for guest as h/w >>> can't support more then that. At the same time I don't see too much >>> sense to tell a guest that it supports less then guest-num-ids. What is >>> the problem to give a guest a maximum that IMSIC could provide? With >>> migration, of course, it will be an issue if new host will support >>> different number of riscv,num-ids but I don't know what we can do better >>> then just avoid migration to such hosts if old-num-ids > new-num-ids >>> without significant performance drop. >> >> This is exactly why an admin may want to limit what a guest gets to >> see / use. > > Would it be better then provide a separate define for riscv, num-ids and > use it here? Maybe here it makes sense to re-use already provided by DT > binding property: > riscv,num-guest-ids: > $ref: /schemas/types.yaml#/definitions/uint32 > minimum: 63 > maximum: 2047 > description: > Number of interrupt identities are supported by IMSIC guest > interrupt > file. When not specified it is assumed to be same as specified by the > riscv,num-ids property. > And if riscv,num-guest-ids the use some predefined in define value? > > Does it make sense then provide the similar defines for compatible and > node name or for that properties it would be okay to re-use what host > DTB IMSIC node provides? I fear I can't answer this. I'm not knowledgeable enough on DT. To me, guest properties are (originally) specified by a guest config file. How that maps to DT (in particular in the dom0less case) I don't really know. Jan From xen-devel-bounces@lists.xenproject.org Fri Apr 17 14:27:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 14:27:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284446.1566229 (Exim 4.92) (envelope-from ) id 1wDkAA-0000j6-QB; Fri, 17 Apr 2026 14:27:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284446.1566229; Fri, 17 Apr 2026 14:27:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDkAA-0000iz-NV; Fri, 17 Apr 2026 14:27:18 +0000 Received: by outflank-mailman (input) for mailman id 1284446; Fri, 17 Apr 2026 14:27:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wDkA8-0000it-Nq for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 14:27:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDkA8-0057ZA-4a for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 16:27:16 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e2433c-5cb7-0a2a0a5109dd-0a2a4502a9d0-4 for ; Fri, 17 Apr 2026 16:27:16 +0200 Received: from [209.85.167.50] (helo=mail-lf1-f50.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e24343-af86-0a2a45020019-d155a732cc4c-3 for ; Fri, 17 Apr 2026 16:27:16 +0200 Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-59dea72099eso724393e87.0 for ; Fri, 17 Apr 2026 07:27:15 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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>>>> >>>> I am not sure that it can be different from what host has. >>>> >>>>> Shouldn't the number of interrupts (aiui that's the "number of cells" >>>>> here) a guest gets be independent from the host it runs one? >>>> >>>> The #interrupt-cells property specifies how many 32-bit values (cells) >>>> are used to encode a single interrupt specifier when referencing this >>>> interrupt controller from another device node. >>>> In this APLIC schema, it's fixed at const: 2, meaning every interrupt >>>> reference requires exactly two cells — typically: >>>> >>>> Cell 1 — the interrupt source number (which of the riscv,num-sources >>>> wired inputs) >>>> Cell 2 — the interrupt type/trigger flags (e.g. edge vs. level, active >>>> high/low) >>> >>> So what if #interrupt-cells is 3 in the DT Xen is handed? If Xen can >>> cope, should that value really also be handed through to guests? >> >> I would say that it depends on what cell 3 will represent. But likely it >> will be needed to hand it to the guest. >> >>> >>>>>> + regs = dt_get_property(aplic_node, "reg", &len); >>>>>> + if ( !regs ) >>>>>> + { >>>>>> + printk("%s: Can't find 'reg' property\n", aplic_node->full_name); >>>>>> + return -FDT_ERR_XEN(ENOENT); >>>>>> + } >>>>>> + >>>>>> + res = fdt_property(fdt, "reg", regs, len); >>>>>> + if ( res ) >>>>>> + return res; >>>>>> + >>>>>> + data = dt_get_property(aplic_node, "riscv,num-sources", &len); >>>>>> + if ( !data ) >>>>>> + { >>>>>> + printk("%s: Can't find 'riscv,num-sources' property\n", >>>>>> + aplic_node->full_name); >>>>>> + return -FDT_ERR_XEN(ENOENT); >>>>>> + } >>>>>> + >>>>>> + res = fdt_property(fdt, "riscv,num-sources", data, len); >>>>>> + if ( res ) >>>>>> + return res; >>>>> >>>>> Or maybe this is the number of interrupts? >>>> >>>> This is the total count of hardware interrupt lines wired into this >>>> APLIC domain. >>>> >>>> It could be independent from the host it runs one but looking at the >>>> possible range [1,1023] for this property if we will put for a guest >>>> lets say 22 but new host support only 20 when we will be in a trouble >>>> anyway. >>> >>> Correct. But if you had some hosts with 1024 and some with 256, how >>> would you bring up a guest on the former to later be able to migrate >>> it to one of the latter when guests inherit the count from the host? >> >> It will be impossible to do that without emulation, > > It's not quite clear to me why this would be. if migration happens from the host with 256 to the host with 1024 the some interrupt remapping/multiplixing might be needed. But I am not consider this as a good option... > >> so I expect it will >> be easier to simply forbid migration to such a host. >> >> Basically, it is just a game of numbers. We could try to estimate how >> many interrupts are needed for the guest, or for simplicity use some >> hard-coded number (say 128 or 256, something “pretty small”). Will it >> resolve the migration issue? Partially yes, but not fully, as there >> could always be cases where the new host’s number of sources is lower >> than our hard-coded “small guest value.” So having a smaller value will >> likely help on average and will allow to support more h/w migration to >> which could happen, but the migration issue will still be present. > > An admin, knowing the capabilities of all hosts in a pool, can suitably > limit guests intended to move among hosts. No migration issue at all. ... this one option is much better. I will introduce define for now in vaplic.h header or maybe just inside this function to hard-code this amount of interrupts supported by guest vAPLIC for now. But in future it make sense to introduce property in host APLIC node something like riscv,num-guest-sources as IMSIC has for interrupt identites (riscv,num-guest-ids). ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 17 14:36:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 14:36:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284460.1566238 (Exim 4.92) (envelope-from ) id 1wDkIl-0002R8-KV; Fri, 17 Apr 2026 14:36:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284460.1566238; Fri, 17 Apr 2026 14:36:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDkIl-0002R1-Hw; Fri, 17 Apr 2026 14:36:11 +0000 Received: by outflank-mailman (input) for mailman id 1284460; Fri, 17 Apr 2026 14:36:10 +0000 Received: from mx.expurgate.net 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=?utf-8?B?cnA0OERWQ0toUmNrN3VOR0J5ZUVLdE12b05VU1JVWCtCYnRaZFVCL2lrSEE2?= =?utf-8?B?TnVQOFdmWGUxTFhNNjR6ZHJ3V3l3cVZnUXhpTjNsS0VtQkRMRUVkNG9IRCtC?= =?utf-8?B?ZHpSN05hcDg4SG94N2hJREhPRkNiVXNHUHpxUDFTWlFQT1hicFJwSFRsdFJs?= =?utf-8?B?SlBvQ3lFNzlYaHVIcFJQR0pnY0d0cGxzL1pPbFRSMHJ3b3BKOVBkbk1NYTh2?= =?utf-8?Q?WXJ85qEMBBCQMEwA=3D?= X-OriginatorOrg: citrix.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2067b450-23a0-4ff5-d034-08de9c8ea6ca X-MS-Exchange-CrossTenant-AuthSource: CH8PR03MB8275.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2026 14:36:03.2345 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: XCwsYolyjoukCDnKFbDuy61vINPm8fDWjJT/V30bUXNNQEqccc5sVFfKckNi7VLkumFGTQ30Kmq7oktVsvBkO9BMb1OwyBAWmC9CBH6Wzjk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR03MB5699 X-purgate-ID: tlsNG-16d1c6/1776436569-9087DD75-2E9D85A1/0/0 X-purgate-type: clean X-purgate-size: 2779 On 17/04/2026 2:25 pm, Ross Lagerwall wrote: > On 4/17/26 12:03 PM, Andrew Cooper wrote: >> On 17/04/2026 11:54 am, Ross Lagerwall wrote: >>> Fix the code which tries to pad the load segment to 2 MiB but only pads >>> it to a 1 MiB boundary. >>> >>> This manifested itself as a page fault while scrubbing RAM during boot. >>> Xen failed to mark its location as reserved in the E820 because the >>> last >>> 2 MiB superpage overlapped a reserved region which meant the memory was >>> given to the allocator despite being RO. >> >> Do you have the relevant snippet of the E820? >> >> AIUI, you're saying that Xen was placed immediately below an E820 >> reserved region (a valid layout at 1M alignment), where said region was >> inside the 2M-aligned boundary that Xen was expecting. >> >> But I don't quite follow what happened next.  Where does read-only-ness >> come into it? >> > > Relevant E820: > > (XEN) [00000063469ff02c]  [000000003f2df000, 000000003f31efff] (ACPI NVS) > (XEN) [00000063519dc9f2]  [000000003f31f000, 000000004cfebfff] (usable) > (XEN) [000000635c504aff]  [000000004cfec000, 000000004d07bfff] (ACPI > data) > (XEN) [00000063677372dc]  [000000004d07c000, 000000004d09bfff] (ACPI NVS) > > With a load size of 0x900000 (padded to a 1 MiB boundary), Xen was > placed at > 4c600000-4cefffff. > > In __start_xen(), there is a call... > > reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)); > > ... which tries to reserve the region 4c600000-4cffffff (size 0x1000000), > padded to a 2 MiB boundary since it is using superpages. > > reserve_e820_ram() doesn't reserve anything because the request > doesn't fall > within a single RAM region. Therefore, the pages get treated as normal > RAM and > will get scrubbed later. However, __start_xen() also calls > modify_xen_mappings() to mark all of .text and .rodata as RO in the > direct map > so when it actually tries to scrub it it gets a page fault instead > (which is I > suppose slightly better than just zeroing Xen's .text). Oh, well I'm glad that I fought to adjust the directmap perms.  This is exactly the kind of thing I was looking to catch. reserve_e820_ram() failing here is also catastrophic; the bootscrub can be bypassed with a cmdline parameter. Either way, can I suggest the following adjustment to the commit message: This manifested itself as a page fault while scrubbing RAM during boot.  Xen failed to mark itself as reserved in the E820 (due to spanning multiple regions), but did restrict the permissions in the directmap.  All of Xen is then handed to physical memory manager as available for use, and scrubbing hit the directmap protections. ? I can fix on commit if you're happy. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 17 16:08:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 16:08:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284524.1566248 (Exim 4.92) (envelope-from ) id 1wDlkA-0005Qg-UQ; Fri, 17 Apr 2026 16:08:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284524.1566248; Fri, 17 Apr 2026 16:08:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDlkA-0005QY-Ov; Fri, 17 Apr 2026 16:08:34 +0000 Received: by outflank-mailman (input) for mailman id 1284524; Fri, 17 Apr 2026 16:08:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDlk9-0005QS-U2 for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 16:08:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDlk8-005LZt-FB for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 18:08:32 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e25afb-e002-0a2a0a5209dd-0a2a4506ca6c-14 for ; Fri, 17 Apr 2026 18:08:32 +0200 Received: from [209.85.221.53] (helo=mail-wr1-f53.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e25b00-7371-0a2a45060019-d155dd35ac33-3 for ; Fri, 17 Apr 2026 18:08:32 +0200 Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-43d70b3e159so437036f8f.0 for ; Fri, 17 Apr 2026 09:08:32 -0700 (PDT) Received: from localhost.localdomain (host-78-146-242-105.as13285.net. [78.146.242.105]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4cb1176sm6088485f8f.3.2026.04.17.09.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 09:08:30 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1776442111; x=1777046911; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=f5xH1RkeuahuDZVxF9D4w7AKkT9fwbSs/UOLRMa4N9s=; b=Z4aj56QgCVar9GZNu7tOqQQnkGwTzjM41+iWlegpM4sl72SCAQtXpa9Fd5xvuDzJnH AGdYS3f75kyD/V7wGkquKBCma+m9zvG5Yjkf6SCk5BeY7/9olswZ6UIHFwjUul8mv2Ii T9YimTaRIqMBtltaCY5qc4qXsU36f/mo54I38= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776442111; x=1777046911; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=f5xH1RkeuahuDZVxF9D4w7AKkT9fwbSs/UOLRMa4N9s=; b=CrZYNPhehiP92+si/BtPqzL45IOix1wNyzo0aSFjQbbLbUB15H1N2XWQQ9lv7XCxY5 JmD2rp5MSpG7LMyh5rC+FvvCYJLEd0zrEupYsP03uawasxtZM/9g84ibEGZ4RB0kTlos f1mt2rhLi+7gxz/qR/rrnQCw54MopEaIAS42rUeUjJMHMpyjvrXfVtDB6mly6LEEhB17 bPCCv7a65T/B0bN9azOqSm+T/fU2rdBs7M005WiV6hFqJMhDOpLPk2XHkeWSt8aM/lN6 OdLAQhcYt9XCkyCjTnaluTS/QwUeYqtZ2MLC8NCUgVuxjD7AfKnb6d2JVokjkcNbauFA 6gCQ== X-Gm-Message-State: AOJu0Yy/JSK2gEoYcj6gdsAG+8tfRxaciA/k/sWUSqTWA29CWgiVdKnB 7uEtZ6NMH0ziBC5Td0g29Yw+8MEcJVsEPNoM5vyzMkRiuOS186LlGpHZPKABOb0D014xs+koFy9 gd4SopRc+Kg== X-Gm-Gg: AeBDieuUx89Ng4rOfxczYELKJ4FkFx2JnbnLJMxwIrXbro69D6NyNNe9H4T8hRMtJt8 WBdis6JZRyku/Ul0CyKO+mVN3zhJDECTTMH0tjj7oQ7IXgq4Ydh+kUd0U5nQ5npDoYNQ44dP2mw oVQ2O1J72s0LgYIV80nvjXnLpE50rebIFE8CqPIWHn23clCYmcZVAeW7VlLPVK6eDqjyDVRU2qD FCP9mqVllE3YLYHiRWBYo4b/yzRsILkwJMtkfGUo6YkemKB7JLFgSbTOrpnFz7MK7S94OkWiWlU 46PxS0f1Z211XU2U3HShqyzntCra/ls1+zwrNNwK1y2W7IznbCVJbmW43UzV4cpluwRqhlndVUy pZ3WSo4gylDy6aCCsSPwkl8Dp4OP/CQ21ZTOgoPlI+g7OqjMp82liY5U8qYCr4AU1W0TG47xD7L 4yh0OBWklnydsgr1Z7+cNbM9jALOcfdPOLAf6gN5nu0Y9wZMm+HhkqNvpomqS9rUGvtmDlDUpbB yhUV1rmU0GgES4= X-Received: by 2002:a05:6000:2f8a:b0:43d:9bb5:bda5 with SMTP id ffacd0b85a97d-43fe3e0ae25mr5397155f8f.40.1776442111193; Fri, 17 Apr 2026 09:08:31 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Ross Lagerwall , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH] x86/boot: Force error checking for reserve_e820_ram() Date: Fri, 17 Apr 2026 17:08:28 +0100 Message-Id: <20260417160828.526063-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776442112-53B7DD75-4F7A7549/0/0 X-purgate-type: clean X-purgate-size: 3917 Failing to mark Xen as Reserved in the E820 is catastrophic; RAM regions get handed to the physical memory allocator for general use. Similarly, failure to mark the boot modules as reserved is not going to result in a working system. Mark reserve_e820_ram() as __must_check, and panic() on failure. To avoid opencoding the range in every caller, print a general failure message in reserve_e820_ram(). Reported-by: Ross Lagerwall Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie Slightly RFC; only compile tested so far. There's no obvious fixes tag. This has been many variations of broken since forever. --- xen/arch/x86/e820.c | 8 +++++++- xen/arch/x86/include/asm/e820.h | 2 +- xen/arch/x86/setup.c | 11 +++++++---- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c index 872208ab3722..f09a01f0c50a 100644 --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -670,7 +670,13 @@ int __init e820_change_range_type( /* Set E820_RAM area (@s,@e) as RESERVED in specified e820 map. */ int __init reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e) { - return e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); + int res = e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); + + if ( !res ) + printk("Failed to convert E820 RAM %"PRIx64"-%"PRIx64" to RESERVED\n", + s, e); + + return res; } unsigned long __init init_e820(const char *str, struct e820map *raw) diff --git a/xen/arch/x86/include/asm/e820.h b/xen/arch/x86/include/asm/e820.h index 8e7644f8870b..a86d60ce3e77 100644 --- a/xen/arch/x86/include/asm/e820.h +++ b/xen/arch/x86/include/asm/e820.h @@ -25,7 +25,7 @@ struct e820map { extern int sanitize_e820_map(struct e820entry *biosmap, unsigned int *pnr_map); extern int e820_all_mapped(u64 start, u64 end, unsigned type); -extern int reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); +extern int __must_check reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); extern int e820_change_range_type( struct e820map *map, uint64_t s, uint64_t e, uint32_t orig_type, uint32_t new_type); diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d041cbd5f6f1..9c1f1eafa0d7 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1639,7 +1639,8 @@ void asmlinkage __init noreturn __start_xen(void) { uint64_t s = bi->mods[i].start, l = bi->mods[i].size; - reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)); + if ( !reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)) ) + panic("Failed to reserve boot module %u in E820\n", i); } if ( !xen_phys_start ) @@ -1652,11 +1653,13 @@ void asmlinkage __init noreturn __start_xen(void) /* This needs to remain in sync with remove_xen_ranges(). */ if ( efi_boot_mem_unused(&eb_start, &eb_end) ) { - reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)); - reserve_e820_ram(&boot_e820, __pa(eb_end), __pa(__2M_rwdata_end)); + if ( !reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)) || + !reserve_e820_ram(&boot_e820, __pa(eb_end), __pa(__2M_rwdata_end)) ) + panic("Failed to reserve Xen in E820\n"); } else - reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)); + if ( reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)) ) + panic("Failed to reserve Xen in E820\n"); /* Late kexec reservation (dynamic start address). */ kexec_reserve_area(); base-commit: 986707b461eb56d75f55581dd1c8e2633f814795 -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Fri Apr 17 16:26:16 2026 Return-path: Envelope-to: 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=?utf-8?B?TGZpZWlTQUJoaFYzaElvNGNoZDBTL1NRVmVCdTdLN1pIcjB5clNBU3NVQU5q?= =?utf-8?Q?qs1cIIPn0Mg0EDbw=3D?= X-OriginatorOrg: citrix.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e5fca16-56c7-44e1-ed31-08de9c9e046d X-MS-Exchange-CrossTenant-AuthSource: CH8PR03MB8274.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2026 16:26:02.7946 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AZIY6s0Q9CFOCEb//Eq02MOzjgUKgt8BIJ2HD/HAhdYjNLcCOAVjRV3M0Uv1G1X1CEYISPT0D6xIdf6NVn9oXn2UaZFEvm2ksYFJgQGUsM0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV4PR03MB8281 X-purgate-ID: tlsNG-d62444/1776443166-B5A69FF4-CEE15A28/0/0 X-purgate-type: clean X-purgate-size: 2894 On 4/17/26 3:35 PM, Andrew Cooper wrote: > On 17/04/2026 2:25 pm, Ross Lagerwall wrote: >> On 4/17/26 12:03 PM, Andrew Cooper wrote: >>> On 17/04/2026 11:54 am, Ross Lagerwall wrote: >>>> Fix the code which tries to pad the load segment to 2 MiB but only pads >>>> it to a 1 MiB boundary. >>>> >>>> This manifested itself as a page fault while scrubbing RAM during boot. >>>> Xen failed to mark its location as reserved in the E820 because the >>>> last >>>> 2 MiB superpage overlapped a reserved region which meant the memory was >>>> given to the allocator despite being RO. >>> >>> Do you have the relevant snippet of the E820? >>> >>> AIUI, you're saying that Xen was placed immediately below an E820 >>> reserved region (a valid layout at 1M alignment), where said region was >>> inside the 2M-aligned boundary that Xen was expecting. >>> >>> But I don't quite follow what happened next.  Where does read-only-ness >>> come into it? >>> >> >> Relevant E820: >> >> (XEN) [00000063469ff02c]  [000000003f2df000, 000000003f31efff] (ACPI NVS) >> (XEN) [00000063519dc9f2]  [000000003f31f000, 000000004cfebfff] (usable) >> (XEN) [000000635c504aff]  [000000004cfec000, 000000004d07bfff] (ACPI >> data) >> (XEN) [00000063677372dc]  [000000004d07c000, 000000004d09bfff] (ACPI NVS) >> >> With a load size of 0x900000 (padded to a 1 MiB boundary), Xen was >> placed at >> 4c600000-4cefffff. >> >> In __start_xen(), there is a call... >> >> reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)); >> >> ... which tries to reserve the region 4c600000-4cffffff (size 0x1000000), >> padded to a 2 MiB boundary since it is using superpages. >> >> reserve_e820_ram() doesn't reserve anything because the request >> doesn't fall >> within a single RAM region. Therefore, the pages get treated as normal >> RAM and >> will get scrubbed later. However, __start_xen() also calls >> modify_xen_mappings() to mark all of .text and .rodata as RO in the >> direct map >> so when it actually tries to scrub it it gets a page fault instead >> (which is I >> suppose slightly better than just zeroing Xen's .text). > > Oh, well I'm glad that I fought to adjust the directmap perms.  This is > exactly the kind of thing I was looking to catch. > > reserve_e820_ram() failing here is also catastrophic; the bootscrub can > be bypassed with a cmdline parameter. > > Either way, can I suggest the following adjustment to the commit message: > > This manifested itself as a page fault while scrubbing RAM during boot. > Xen failed to mark itself as reserved in the E820 (due to spanning > multiple regions), but did restrict the permissions in the directmap. > All of Xen is then handed to physical memory manager as available for > use, and scrubbing hit the directmap protections. > > ? Sure, fine with me. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CtLvE4RacGmVpg8gOvDV8JUO4ULJRNtAd5z6yJb/2p0=; b=fZ/cBloBanlYNb/cgzYe2u/sjmFw+reMDWjijvW87EQ5J0tEVj7TfuusJDyLMUbDTVXOHoW2twJzsFi4LNAyaJg3242zOC6AjAlUpi9kzJigwKmu9vYEFaqL1EWTdObX+RkMWABjowWYusCnkIS60XO0QDEHG1JAWcR4vsMD6xU= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com; Message-ID: <85625a6f-8d04-4863-8f74-461c9a85464f@citrix.com> Date: Fri, 17 Apr 2026 17:27:46 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/boot: Force error checking for reserve_e820_ram() To: Andrew Cooper , Xen-devel Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <20260417160828.526063-1-andrew.cooper3@citrix.com> Content-Language: en-US From: Ross Lagerwall In-Reply-To: <20260417160828.526063-1-andrew.cooper3@citrix.com> Content-Type: text/plain; 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RAM regions get > handed to the physical memory allocator for general use. Similarly, failure > to mark the boot modules as reserved is not going to result in a working > system. > > Mark reserve_e820_ram() as __must_check, and panic() on failure. To avoid > opencoding the range in every caller, print a general failure message in > reserve_e820_ram(). > > Reported-by: Ross Lagerwall > Signed-off-by: Andrew Cooper > --- > CC: Jan Beulich > CC: Roger Pau Monné > CC: Teddy Astie > > Slightly RFC; only compile tested so far. > > There's no obvious fixes tag. This has been many variations of broken since > forever. > --- > xen/arch/x86/e820.c | 8 +++++++- > xen/arch/x86/include/asm/e820.h | 2 +- > xen/arch/x86/setup.c | 11 +++++++---- > 3 files changed, 15 insertions(+), 6 deletions(-) > > diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c > index 872208ab3722..f09a01f0c50a 100644 > --- a/xen/arch/x86/e820.c > +++ b/xen/arch/x86/e820.c > @@ -670,7 +670,13 @@ int __init e820_change_range_type( > /* Set E820_RAM area (@s,@e) as RESERVED in specified e820 map. */ > int __init reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e) > { > - return e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); > + int res = e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); > + > + if ( !res ) > + printk("Failed to convert E820 RAM %"PRIx64"-%"PRIx64" to RESERVED\n", > + s, e); > + > + return res; > } > > unsigned long __init init_e820(const char *str, struct e820map *raw) > diff --git a/xen/arch/x86/include/asm/e820.h b/xen/arch/x86/include/asm/e820.h > index 8e7644f8870b..a86d60ce3e77 100644 > --- a/xen/arch/x86/include/asm/e820.h > +++ b/xen/arch/x86/include/asm/e820.h > @@ -25,7 +25,7 @@ struct e820map { > > extern int sanitize_e820_map(struct e820entry *biosmap, unsigned int *pnr_map); > extern int e820_all_mapped(u64 start, u64 end, unsigned type); > -extern int reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); > +extern int __must_check reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); > extern int e820_change_range_type( > struct e820map *map, uint64_t s, uint64_t e, > uint32_t orig_type, uint32_t new_type); > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c > index d041cbd5f6f1..9c1f1eafa0d7 100644 > --- a/xen/arch/x86/setup.c > +++ b/xen/arch/x86/setup.c > @@ -1639,7 +1639,8 @@ void asmlinkage __init noreturn __start_xen(void) > { > uint64_t s = bi->mods[i].start, l = bi->mods[i].size; > > - reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)); > + if ( !reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)) ) > + panic("Failed to reserve boot module %u in E820\n", i); > } > > if ( !xen_phys_start ) > @@ -1652,11 +1653,13 @@ void asmlinkage __init noreturn __start_xen(void) > /* This needs to remain in sync with remove_xen_ranges(). */ > if ( efi_boot_mem_unused(&eb_start, &eb_end) ) > { > - reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)); > - reserve_e820_ram(&boot_e820, __pa(eb_end), __pa(__2M_rwdata_end)); > + if ( !reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)) || > + !reserve_e820_ram(&boot_e820, __pa(eb_end), __pa(__2M_rwdata_end)) ) > + panic("Failed to reserve Xen in E820\n"); > } > else > - reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)); > + if ( reserve_e820_ram(&boot_e820, __pa(_stext), __pa(__2M_rwdata_end)) ) > + panic("Failed to reserve Xen in E820\n"); > This condition is inverted. Otherwise this looks like a sensible change. Ross From xen-devel-bounces@lists.xenproject.org Fri Apr 17 17:02:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 17:02:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284580.1566281 (Exim 4.92) (envelope-from ) id 1wDmaE-0005Nt-IL; Fri, 17 Apr 2026 17:02:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284580.1566281; Fri, 17 Apr 2026 17:02:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDmaE-0005Ne-B4; Fri, 17 Apr 2026 17:02:22 +0000 Received: by outflank-mailman (input) for mailman id 1284580; Fri, 17 Apr 2026 17:02:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDmaC-0005Jz-9o; Fri, 17 Apr 2026 17:02:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDmaB-000jIW-MX; Fri, 17 Apr 2026 19:02:19 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e2678f-bab6-0a2a0a5309dd-0a2a4509cc8a-30 for ; Fri, 17 Apr 2026 19:02:19 +0200 Received: from [104.130.215.37] (helo=mail.xenproject.org) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e2679a-2497-0a2a45090019-6882d725c690-3 for ; Fri, 17 Apr 2026 19:02:19 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wDma4-006TOt-20; Fri, 17 Apr 2026 17:02:12 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wDma4-007har-1n; Fri, 17 Apr 2026 17:02:12 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 488 v1 - x86: Floating Point Divider State Sampling Message-Id: Date: Fri, 17 Apr 2026 17:02:12 +0000 X-purgate-ID: tlsNG-bad1c0/1776445339-93979A53-BBDDC461/0/0 X-purgate-type: clean X-purgate-size: 17345 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory XSA-488 x86: Floating Point Divider State Sampling ISSUE DESCRIPTION ================= Researchers from the CISPA Helmholtz Center for Information Security have discovered Floating Point Divider State Sampling. It is detailed in a paper titled "TREVEX: A Black-Box Detection Framework For Data-Flow Transient Execution Vulnerabilities" For more information, see: https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7053.html https://roots.ec/blog/fpdss/ IMPACT ====== An attacker might be able to infer data belonging to other contexts, including data belonging to other guests. VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Only AMD Fam17h CPUs (Zen1 microarchitecture) are believed to be vulnerable. Other AMD CPUs and CPUs from other manufacturers are not known to be affected. MITIGATION ========== There are no mitigations. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa488.patch xen-unstable - Xen 4.21.x xsa488-4.20.patch Xen 4.20.x - Xen 4.19.x xsa488-4.18.patch Xen 4.18.x xsa488-4.17.patch Xen 4.17.x $ sha256sum xsa488* 3dde61413eb75cb65fbd20b58165f673f9f4610804ec532ff0bf3c3f469454c1 xsa488.patch 7822abb0ed5a5f8e2b8697db41d46e030fd69bf8ca8cb965022484b287d9ea26 xsa488-4.17.patch 6668f9d1433863522b8554dc324f57efcfcf3e00c9261c0ee5c2db17f63bccd6 xsa488-4.18.patch 275c35d05951c4583056904869183972b9699549f0ec59f946faa92d5cef4b21 xsa488-4.20.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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RAM >> regions get >> handed to the physical memory allocator for general use.  Similarly, >> failure >> to mark the boot modules as reserved is not going to result in a working >> system. >> >> Mark reserve_e820_ram() as __must_check, and panic() on failure.  To >> avoid >> opencoding the range in every caller, print a general failure message in >> reserve_e820_ram(). >> >> Reported-by: Ross Lagerwall >> Signed-off-by: Andrew Cooper >> --- >> CC: Jan Beulich >> CC: Roger Pau Monné >> CC: Teddy Astie >> >> Slightly RFC; only compile tested so far. >> >> There's no obvious fixes tag.  This has been many variations of >> broken since >> forever. >> --- >>   xen/arch/x86/e820.c             |  8 +++++++- >>   xen/arch/x86/include/asm/e820.h |  2 +- >>   xen/arch/x86/setup.c            | 11 +++++++---- >>   3 files changed, 15 insertions(+), 6 deletions(-) >> >> diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c >> index 872208ab3722..f09a01f0c50a 100644 >> --- a/xen/arch/x86/e820.c >> +++ b/xen/arch/x86/e820.c >> @@ -670,7 +670,13 @@ int __init e820_change_range_type( >>   /* Set E820_RAM area (@s,@e) as RESERVED in specified e820 map. */ >>   int __init reserve_e820_ram(struct e820map *map, uint64_t s, >> uint64_t e) >>   { >> -    return e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); >> +    int res = e820_change_range_type(map, s, e, E820_RAM, >> E820_RESERVED); >> + >> +    if ( !res ) >> +        printk("Failed to convert E820 RAM %"PRIx64"-%"PRIx64" to >> RESERVED\n", >> +               s, e); >> + >> +    return res; >>   } >>     unsigned long __init init_e820(const char *str, struct e820map *raw) >> diff --git a/xen/arch/x86/include/asm/e820.h >> b/xen/arch/x86/include/asm/e820.h >> index 8e7644f8870b..a86d60ce3e77 100644 >> --- a/xen/arch/x86/include/asm/e820.h >> +++ b/xen/arch/x86/include/asm/e820.h >> @@ -25,7 +25,7 @@ struct e820map { >>     extern int sanitize_e820_map(struct e820entry *biosmap, unsigned >> int *pnr_map); >>   extern int e820_all_mapped(u64 start, u64 end, unsigned type); >> -extern int reserve_e820_ram(struct e820map *map, uint64_t s, >> uint64_t e); >> +extern int __must_check reserve_e820_ram(struct e820map *map, >> uint64_t s, uint64_t e); >>   extern int e820_change_range_type( >>       struct e820map *map, uint64_t s, uint64_t e, >>       uint32_t orig_type, uint32_t new_type); >> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c >> index d041cbd5f6f1..9c1f1eafa0d7 100644 >> --- a/xen/arch/x86/setup.c >> +++ b/xen/arch/x86/setup.c >> @@ -1639,7 +1639,8 @@ void asmlinkage __init noreturn __start_xen(void) >>       { >>           uint64_t s = bi->mods[i].start, l = bi->mods[i].size; >>   -        reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)); >> +        if ( !reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)) ) >> +            panic("Failed to reserve boot module %u in E820\n", i); >>       } >>         if ( !xen_phys_start ) >> @@ -1652,11 +1653,13 @@ void asmlinkage __init noreturn >> __start_xen(void) >>       /* This needs to remain in sync with remove_xen_ranges(). */ >>       if ( efi_boot_mem_unused(&eb_start, &eb_end) ) >>       { >> -        reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)); >> -        reserve_e820_ram(&boot_e820, __pa(eb_end), >> __pa(__2M_rwdata_end)); >> +        if ( !reserve_e820_ram(&boot_e820, __pa(_stext), >> __pa(eb_start)) || >> +             !reserve_e820_ram(&boot_e820, __pa(eb_end), >> __pa(__2M_rwdata_end)) ) >> +            panic("Failed to reserve Xen in E820\n"); >>       } >>       else >> -        reserve_e820_ram(&boot_e820, __pa(_stext), >> __pa(__2M_rwdata_end)); >> +        if ( reserve_e820_ram(&boot_e820, __pa(_stext), >> __pa(__2M_rwdata_end)) ) >> +            panic("Failed to reserve Xen in E820\n"); >>   > > This condition is inverted. > Otherwise this looks like a sensible change. Oops, yes.  Fixed. This is a horrible function of type int but returning a boolean success.  Still, I'm not altering the error scheme in the same patch as this fix. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 17 19:36:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 17 Apr 2026 19:36:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284744.1566364 (Exim 4.92) (envelope-from ) id 1wDoz4-0000FV-Qp; Fri, 17 Apr 2026 19:36:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284744.1566364; Fri, 17 Apr 2026 19:36:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDoz4-0000FO-NJ; Fri, 17 Apr 2026 19:36:10 +0000 Received: by outflank-mailman (input) for mailman id 1284744; Fri, 17 Apr 2026 19:36:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDoz4-0000FI-2M for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 19:36:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wDoz3-00ED1J-1G for xen-devel@lists.xenproject.org; Fri, 17 Apr 2026 21:36:09 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e28b84-bab6-0a2a0a5309dd-0a2a4507e504-28 for ; Fri, 17 Apr 2026 21:36:08 +0200 Received: from [74.125.224.53] (helo=mail-yx1-f53.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e28ba7-229c-0a2a45070019-4a7de035b0a7-3 for ; Fri, 17 Apr 2026 21:36:08 +0200 Received: by mail-yx1-f53.google.com with SMTP id 956f58d0204a3-650775f427eso1231578d50.2 for ; Fri, 17 Apr 2026 12:36:08 -0700 (PDT) Received: from [10.138.34.110] (h69-131-150-119.cncrtn.broadband.dynamic.tds.net. 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To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------bs68b4yFFH9Al3ffdKH6its7" X-purgate-ID: tlsNG-ef75cf/1776454568-16062C48-1020CBC4/0/0 X-purgate-type: clean X-purgate-size: 17112 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------bs68b4yFFH9Al3ffdKH6its7 Content-Type: multipart/mixed; boundary="------------QazVX00TBm0dCevWLQ1sUV0h"; protected-headers="v1" Message-ID: <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> Date: Fri, 17 Apr 2026 15:35:51 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> --------------QazVX00TBm0dCevWLQ1sUV0h Content-Type: multipart/mixed; boundary="------------D7OcFUkheM5tnXkSpl0qNROw" --------------D7OcFUkheM5tnXkSpl0qNROw Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/17/26 03:53, Christian K=C3=B6nig wrote: > On 4/16/26 18:13, Demi Marie Obenour wrote: >> On 4/16/26 05:57, Christian K=C3=B6nig wrote: >>> On 4/16/26 01:27, Demi Marie Obenour wrote: >>>> Is it safe to assume that if a dmabuf exporter cannot handle >>>> non-revocable, pinned importers, it will fail the import? Or is >>>> using dma_buf_pin() unsafe if one does not know the exporter? >>> >>> Neither. >>> >>> dma_buf_pin() makes sure that the importer doesn't get any invalidati= on notifications because the exporter moves the backing store of the buff= er around for memory management. >>> >>> But what is still possible is that the exporter is hot removed, in wh= ich case the importer should basically terminate it's DMA operation as so= on as possible. >>> >>> GPU drivers usually reject pin requests to VRAM from DMA-buf importer= s when that isn't restricted by cgroups for example, because that can oth= erwise easily result in a deny of service. >>> >>> Amdgpu only recently started to allow pinning into VRAM to support RD= MA without ODP (I think it was ODP, but could be that I mixed up the RDMA= three letter code for that feature). >>> >>>> For context, Xen grant tables do not support revocation. One can as= k >>>> the guest to unmap the grants, but if the guest doesn't obey the onl= y >>>> recourse is to ungracefully kill it. They also do not support page >>>> faults, so the pages must be pinned. Right now, grant tables don't >>>> support PCI BAR mappings, but that's fixable. >>> >>> That sounds like an use case for the DMA-buf pin interface. >>> >>>> How badly is this going to break with dGPU VRAM, if at all? I know >>>> that AMDGPU has a fallback when the BAR isn't mappable. What about >>>> other drivers? Supporting page faults the way KVM does is going to >>>> be extremely hard, so pinned mappings and DMA transfers are vastly >>>> preferable. >>> >>> Well if you only want to share a fixed amount of VRAM then that is pr= etty much ok. >>> >>> But when the client VM can trigger pinning on demand without any limi= tation you can pretty easily have deny of service against the host. That = is usually a rather bad idea. >> >> Is there a reasonable way to choose such an amount? >=20 > Not really. >=20 >> Unless I am >> mistaken, client workloads are highly non-uniform: a single game or >> compute job might well use more VRAM than every other program on the >> system combined. >=20 > Yeah, perfectly correct. >=20 >> Are these workloads impossible to make work well with pinning? >=20 > No, as long as you don't know the workload beforehand, e.g. when you de= fine the limit. >=20 > I mean that's why basically everybody avoids pinning and assigning fixe= d amounts of resources. >=20 > Even if you can make it work technically pinning usually results in a r= ather bad end user experience. >=20 > Regards, > Christian. Do drivers and programs assume that they can access VRAM from the CPU? Are any of the following reasonable options? 1. Change the guest kernel to only map (and thus pin) a small subset of VRAM at any given time. If unmapped VRAM is accessed the guest traps the page fault, evicts an old VRAM mapping, and creates a new one. =20 2. Pretend that resizable BAR is not enabled, so the guest doesn't think it can map much of VRAM at once. If resizable BAR is enabled on the host, it might be possible to split the large BAR mapping in a lot of ways. Or does Xen really need to allow the host to handle guest page faults? That adds a huge amount of complexity to trusted and security-critical parts of the system, so it really is a last resort. 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CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oFs7CYHSCcAJSZghCkOGs16KWeK3oiXxZEjLwjMkXxtwESgusFDnznyTn0CI68zeP5BjzIyrp2wg7CNtsMJgjYbfs8arD3OWoawbA/+SJl9TwqwwHM0STNGoXoxbYeuRrISzCge20oV5D/0zCHNG+/WH73xIEqiDt9P+5ytZksHcwvvYlbjjWmcrG+Kx0swHonZIirg+6/WUhhlkr3hkyudnpTYpDutgcrdkk+/B4jG6BYw1WzOLLV66T+QA63LHj6vgzamGsdqZ12pyg/PQipsjKIqFsgO/wm5Wijf0iAjGzDOpc0f4UxtGnjuNSDIHh2QqzNo/hT7mQ83w0lXhgmg1NCJXwNxQJkcT8LQGwvywXdPdO7x6e+mJAa+ZzoSHto2FD9U4pIcCi2kjCxTiIukmrwIUx20vzJ6ZB4genjZtKIV2J5wUhKobocKm4tF/ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2026 07:06:38.5029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b826b96-e9d0-441a-22ae-08de9d190919 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4413 X-purgate-ID: tlsNG-16d1c6/1776496004-CF57ED75-522C5CFB/0/0 X-purgate-type: clean X-purgate-size: 6048 On 08/04/2026 15:24, Luca Fancellu wrote: > Hi Ayan, Hi Luca, > >> On 18 Mar 2026, at 14:09, Ayan Kumar Halder wrote: >> >> One key requirement of Xen functional safety is to reduce the number >> of lines of code to be safety certified. Besides, a safety certified >> Xen requires a static hardware configuration to be defined. This static >> hardware configuration is described as per the test hardware/emulator >> hardware configuration against which Xen is verified. >> >> Introduce GICV3_NR_LRS with the two aims in mind: >> 1. User should set the number of GICV3 list registers as per the test >> hardware so that the unwanted code can be removed using GCC's dead >> code elimination or preprocessor's config. >> 2. By doing #1, one can ensure that there is no untested code due to >> unsupported hardware platform and thus there is no safety impact due >> to untested code. >> >> However if the user does not set GICV3_NR_LRS, then it is set to 0. >> Thus Xen will fallback to the default scenario (i.e. read the hardware >> register to determine the number of LRS). >> >> 1. In gicv3_save_lrs()/gicv3_restore_lrs(), use the number of list >> registers from GICV3_NR_LRS (if defined) instead of gicv3_info.nr_lrs. >> This ensures that if the hardware does not support more than 4 LRs >> (for example), the code accessing LR 4-15 is never reached. The >> compiler can eliminate the unsupported cases as the switch case uses a >> constant conditional. >> >> 2. RAZ/WI for the unsupported LRs. >> >> Signed-off-by: Ayan Kumar Halder >> Signed-off-by: Michal Orzel >> --- >> Changelog: >> >> v1 - 1. s/lrs/LRS >> 2. Implement RAZ/WI instead of panic >> >> Few comments which were not addressed >> 1. Do "gicv3_info.nr_lrs to LRS" in gicv3_hyp_init() and keep the code >> unchanged in gicv3_save_lrs()/gicv3_restore_lrs() -- This prevents the >> compiler from doing dead code elimination as the switch condition cannot >> be evaluated at compile time. >> I am not sure how to get around this issue. >> >> xen/arch/arm/Kconfig | 9 +++++++++ >> xen/arch/arm/gic-v3.c | 14 ++++++++++++-- >> 2 files changed, 21 insertions(+), 2 deletions(-) >> >> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig >> index 2f2b501fda..6540013f97 100644 >> --- a/xen/arch/arm/Kconfig >> +++ b/xen/arch/arm/Kconfig >> @@ -276,6 +276,15 @@ config PCI_PASSTHROUGH >> >> endmenu >> >> +config GICV3_NR_LRS >> + int "Number of GICv3 Link Registers supported" if EXPERT >> + depends on GICV3 >> + range 0 16 > 16 is the maximum supported since ICH_VTR_EL2.ListRegs is 4 bits [1], > however how are we handling the case when GICV3_NR_LRS is greater > than the supported number of LR registers? > > Shall we check that in gicv3_hyp_init()? My intention is that when user sets GICV3_NR_LRS , it overwrites the value obtained from reading the hardware. IOW, I was thinking of something like gicv3_info.nr_lrs = GICV3_NR_LRS But you have a valid point that what will happen if the user sets GICV3_NR_LRS to value greater than that supported by the hardware. I think we should print a warning in that case. This was suggested by Julien in v1, but I missed that. > >> + default 0 >> + help >> + Controls the number of Link registers to be accessed. >> + Keep it set to 0 to use a value obtained from a hardware register. >> + >> menu "ARM errata workaround via the alternative framework" >> depends on HAS_ALTERNATIVE >> >> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c >> index bc07f97c16..eaae95eb4d 100644 >> --- a/xen/arch/arm/gic-v3.c >> +++ b/xen/arch/arm/gic-v3.c >> @@ -51,6 +51,8 @@ static DEFINE_PER_CPU(void __iomem*, rbase); >> #define GICD (gicv3.map_dbase) >> #define GICD_RDIST_BASE (this_cpu(rbase)) >> #define GICD_RDIST_SGI_BASE (GICD_RDIST_BASE + SZ_64K) >> +#define LRS (CONFIG_GICV3_NR_LRS ?: \ >> + gicv3_info.nr_lrs) >> >> /* >> * Saves all 16(Max) LR registers. Though number of LRs implemented >> @@ -59,7 +61,7 @@ static DEFINE_PER_CPU(void __iomem*, rbase); >> static inline void gicv3_save_lrs(struct vcpu *v) >> { >> /* Fall through for all the cases */ >> - switch ( gicv3_info.nr_lrs ) >> + switch ( LRS ) >> { >> case 16: >> v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); >> @@ -121,7 +123,7 @@ static inline void gicv3_save_lrs(struct vcpu *v) >> static inline void gicv3_restore_lrs(const struct vcpu *v) >> { >> /* Fall through for all the cases */ >> - switch ( gicv3_info.nr_lrs ) >> + switch ( LRS ) >> { >> case 16: >> WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); >> @@ -178,6 +180,10 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) >> >> static uint64_t gicv3_ich_read_lr(int lr) >> { >> + /* RAZ for unsupported LR */ >> + if ( lr >= LRS ) >> + return 0; >> + >> switch ( lr ) >> { >> case 0: return READ_SYSREG_LR(0); >> @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) >> >> static void gicv3_ich_write_lr(int lr, uint64_t val) >> { >> + /* WI for unsupported LR */ >> + if ( lr >= LRS ) >> + return; >> + >> switch ( lr ) >> { >> case 0: > Now, since we are using CONFIG_GICV3_NR_LRS or gicv3_info.nr_lrs in gicv3_save_lrs/gicv3_restore_lrs, > there are other part of the codebase using nr_lrs (gic_get_nr_lrs() is one of them), but all the callers of that > function will use the HW nr_lrs and not the CONFIG_GICV3_NR_LRS, so I think some work needs to be done > to align them or there will be mismatches at runtime with possible loss of information. I will fix that. - Ayan > > > [1] https://developer.arm.com/documentation/111179/2025-09_ASL1/AArch64-Registers/ICH-VTR-EL2--Interrupt-Controller-VGIC-Type-Register > > Cheers, > Luca > > From xen-devel-bounces@lists.xenproject.org Sat Apr 18 07:13:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 18 Apr 2026 07:13:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284834.1566381 (Exim 4.92) (envelope-from ) id 1wDzrt-0004bj-Rp; Sat, 18 Apr 2026 07:13:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284834.1566381; Sat, 18 Apr 2026 07:13:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDzrt-0004bc-P0; Sat, 18 Apr 2026 07:13:29 +0000 Received: by outflank-mailman (input) for mailman id 1284834; Sat, 18 Apr 2026 07:13:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wDzrs-0004bW-Tu for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <360f731d-5902-4578-b6cd-7cc438b1d998@amd.com> Date: Sat, 18 Apr 2026 08:13:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: gic-v3: Introduce CONFIG_GICV3_NR_LRS To: Julien Grall , Luca Fancellu , Ayan Kumar Halder , Ayan Kumar Halder CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" References: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> <56478969-509d-4527-b136-4498840606e2@xen.org> Content-Language: en-US From: "Halder, Ayan Kumar" In-Reply-To: <56478969-509d-4527-b136-4498840606e2@xen.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|LV2PR12MB5944:EE_ X-MS-Office365-Filtering-Correlation-Id: cd6f4f51-ccff-495c-57cb-08de9d19f9d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|18002099003|56012099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hwC6Sip7xxN4zXKRqh9Y53wacGyBttqVW8Ik9SNoU69LYbZvnqNyX6YLygIj4aqdh7fMXM8+BjHcWSqRBdPsD2eL0saqNFcvIn5IU4ilTdf3RNbFsEpK0lgHT1RiCGti2TBMUk7JiJjXhkAX7iJDc/DS6rLI6WS23PoSMnyGHQ6qrbbboJZp1pu5nVoD3qNHtBoeRYuIejz4F0u7n8Kz1grb/odn42LD8P2vAwIwNQ04Id053SD8NvycdLF5g8+D2fHTaxOTbQLnBT5kuFtessMQTg11RvbFXqlahp2lqWf+Y3uLOVxiL+ptUu1QS3JRnEIezR8VulbvMRN/bUc0pXxtZUcZJkTFNuNO6tZHRnjjKk8B6LchhC+DcHPQ9yWOrxSuk+IkGdZplTZYw8Iob6+RVLAW/SbtDAdhYYP+e5RbiuYnlWsdSP101V8GOLde X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2026 07:13:22.3760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd6f4f51-ccff-495c-57cb-08de9d19f9d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5944 X-purgate-ID: tlsNG-4011c0/1776496407-47B7F8B7-F21EC398/0/0 X-purgate-type: clean X-purgate-size: 1622 On 14/04/2026 03:10, Julien Grall wrote: > Hi, Hi Julien, > > On 08/04/2026 23:24, Luca Fancellu wrote: >>> @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) >>> >>> static void gicv3_ich_write_lr(int lr, uint64_t val) >>> { >>> +    /* WI for unsupported LR */ >>> +    if ( lr >= LRS ) >>> +        return; >>> + >>>      switch ( lr ) >>>      { >>>      case 0: >> >> Now, since we are using CONFIG_GICV3_NR_LRS or gicv3_info.nr_lrs in >> gicv3_save_lrs/gicv3_restore_lrs, >> there are other part of the codebase using nr_lrs (gic_get_nr_lrs() >> is one of them), but all the callers of that >> function will use the HW nr_lrs and not the CONFIG_GICV3_NR_LRS, so I >> think some work needs to be done >> to align them or there will be mismatches at runtime with possible >> loss of information. > > +1. We need a consistent view for the number of LRs. I could also see > a use case where the integrator wants to support less LRs than what > the HW supports (this doesn't seem to be prevented with this patch). This scenario is ok. In this case, we should use the value provided by the GICV3_NR_LRS. I don't think this should be something we want to prevent. Or I might be missing something ? The issue is with the opposite situation. If GICV3_NR_LRS is greater than what the hardware supports, we should print a warning. And let Xen use the value GICV3_NR_LRS. > > Note, during Xen boot, we may need to zero the LRs which are unused as > they may potentially contain active interrupts. Ack. - Ayan > > Cheers, > From xen-devel-bounces@lists.xenproject.org Sat Apr 18 07:28:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 18 Apr 2026 07:28:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1284842.1566391 (Exim 4.92) (envelope-from ) id 1wE06j-0006Ml-3k; Sat, 18 Apr 2026 07:28:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1284842.1566391; Sat, 18 Apr 2026 07:28:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wE06j-0006Me-0m; Sat, 18 Apr 2026 07:28:49 +0000 Received: by outflank-mailman (input) for mailman id 1284842; Sat, 18 Apr 2026 07:28:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wE06i-0006MY-0L for xen-devel@lists.xenproject.org; Sat, 18 Apr 2026 07:28:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wE06g-00BkpQ-Rz for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Sat, 18 Apr 2026 08:28:23 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: gic-v3: Introduce CONFIG_GICV3_NR_LRS To: Julien Grall , Ayan Kumar Halder , CC: Stefano Stabellini , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" References: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> <83786d8b-d57a-4c79-8e8b-7115d4276568@xen.org> Content-Language: en-US From: "Halder, Ayan Kumar" In-Reply-To: <83786d8b-d57a-4c79-8e8b-7115d4276568@xen.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|DM4PR12MB6182:EE_ X-MS-Office365-Filtering-Correlation-Id: ae28e254-f83c-4825-c84e-08de9d1c1cea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: Ad0P3/IGZesYojPP1NZWa0YcxcYzkX5mIoUDGDdCxBvmIOnG4vsUdp+8lPv9Cj+ggBCkuwlkAm4TttU/8OctpV4pikajbUEzOVTMk60NScSsA2ya3vUXjtVH/2zxAEuCxe+A9jkUDYr7uLLne53jlfbYw+qMJBalDO1+hpILoM00hvPKw/KybQ6X906gEAWqFhAhDVJyu0YVHs3Tqqc/jzTz03CiIgUvrF+jc7vsMOB3HBd3OL4pHbuLJSORnXa+0etW4wg4F/Hmz50jNwzMiqtM19+JaHJHiaXUEgnd3mSEjtdS6llmB/xrnRhq6ZJo2UCI08cs8lgqeimKIR0JPM9VWu2jU18iSMFv/M/JT2/Sff0JV6MIKtl0x3Rtbkx9aHFGkJgzyyU9VZghX1APhha/tWGZUWUPSzSJY3FZ6+bb9ZXXt08xFnbMHDieTqcHqvA/oqks23twy6K8Ro+NgdEO2KXJ/ll4z26Rubuu2W3KfIIbdDhujkW2oNY9K44NPzur8pKvyHhenT25M2bIbsWu/U3pEvSRnyV1oJnxnl+3YLUA36C11ATdFngnfaafG6gw/TMkd3HJPZ5ueOAer7IIAouJqh0WG06DNDk/A7rmweZO14Di4SA7QWHgkwjOoYVjs5wbmGcdsDoKQRMF7gKWT+5Rum/F1MEooHcoJYGlzyMbKPXQ1bcTQBF4JxgkM7zknbBPt5/L0VKlK1ekKc5/pvER0Apk49etw+tzNbbH0+VhN5+RfyRPrpI/+txEx6QEv5IlJuJ89ZIn7LkRjw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RuV1bVi4lqXlFMQ+uYGOyhCpR+K4n2bgN32lkSZ5vGiQv6czBLxXxLPaHv0HwELxNHZB/orB+mMMT/5aavIxnjJIHPXlFJk9WdHUlgXvw85/46FB+BJglIjHrYbBMWA0NTFE98WbdtI0TipzLNODqGa8vumTn874/9SiY0QsdJg8udHmXbKR1HyZsGFUoWlGwpART0/oVcj6HkNSQk62DFBXmkqMC+LyBQe0dgmBajTm1qLt93g6exntfV5BicOXWE+H9b9xWul5kZTZ4vzFU0zAP7HSLL355WwvvUrvMVb/NtN0S/iYnAi4sF2SHfch5wSI3r+2WIxhhVMtG9qhv85yvaO24jrEymzQ3npQ0uyo//Nhm7IFOKaDOgasvKhfA/zGMMUOKxLCGJpVm5yo4Q9P6yrcCNeJf78djHbuguE/ee8Sezub39Op/I0kU34u X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2026 07:28:40.2151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae28e254-f83c-4825-c84e-08de9d1c1cea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6182 X-purgate-ID: tlsNG-bad1c0/1776497326-484A9A53-1DDB3538/0/0 X-purgate-type: clean X-purgate-size: 7195 On 14/04/2026 03:06, Julien Grall wrote: > Hi Ayan, Hi Julien, > > On 18/03/2026 23:09, Ayan Kumar Halder wrote: >> One key requirement of Xen functional safety is to reduce the number >> of lines of code to be safety certified. Besides, a safety certified >> Xen requires a static hardware configuration to be defined. This static >> hardware configuration is described as per the test hardware/emulator >> hardware configuration against which Xen is verified. >> >> Introduce GICV3_NR_LRS with the two aims in mind: > > Out of interest, why is this limited to GICv3? This was just my starting point of investigation. My intention is to have as much as a static defined hardware configuration, so that the code that cannot be tested on the hardware can be eliminated by one of the many ways (DCE, Kconfig or actual code removal). The advantage of having a static defined configuration is that the system integrator will have the full control on how to configure Xen for a specific hardware platform. And we try to reduce as much as possible any code that cannot be used due to hardware limitations. > >> 1. User should set the number of GICV3 list registers as per the test >> hardware so that the unwanted code can be removed using GCC's dead >> code elimination or preprocessor's config. > > We discussed this offline, I am not fully convinced you can rely on > dead code elimination to always remove the BUG() in > gicv3_ich_read_lr(). If you want to rely on dead code eliminitation, > then you will want to call a function which have a prototype defined > but not implemented (similar to what we do for bitops with > __bad_atomic_read()) which would fail a link time if the compiler > didn't remove the code. If you are ok, we can break this into 2 patches 1. Introduce GICV3_NR_LRS and make sure it is used consistently in the code. IOW, it should address the comments that Luca and you provided. 2. Implement a way for compiler to do DCE based on GICV3_NR_LRS. > >> 2. By doing #1, one can ensure that there is no untested code due to >> unsupported hardware platform and thus there is no safety impact due >> to untested code. >> >> However if the user does not set GICV3_NR_LRS, then it is set to 0. >> Thus Xen will fallback to the default scenario (i.e. read the hardware >> register to determine the number of LRS). >> >> 1. In gicv3_save_lrs()/gicv3_restore_lrs(), use the number of list >> registers from GICV3_NR_LRS (if defined) instead of gicv3_info.nr_lrs. >> This ensures that if the hardware does not support more than 4 LRs >> (for example), the code accessing LR 4-15 is never reached. The >> compiler can eliminate the unsupported cases as the switch case uses a >> constant conditional. >> >> 2. RAZ/WI for the unsupported LRs. >> >> Signed-off-by: Ayan Kumar Halder >> Signed-off-by: Michal Orzel >> --- >> Changelog: >> >> v1 - 1. s/lrs/LRS >> 2. Implement RAZ/WI instead of panic >> >> Few comments which were not addressed >> 1. Do "gicv3_info.nr_lrs to LRS" in gicv3_hyp_init() and keep the code >> unchanged in gicv3_save_lrs()/gicv3_restore_lrs() -- This prevents the >> compiler from doing dead code elimination as the switch condition cannot >> be evaluated at compile time. >> I am not sure how to get around this issue. >> >>   xen/arch/arm/Kconfig  |  9 +++++++++ >>   xen/arch/arm/gic-v3.c | 14 ++++++++++++-- >>   2 files changed, 21 insertions(+), 2 deletions(-) >> >> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig >> index 2f2b501fda..6540013f97 100644 >> --- a/xen/arch/arm/Kconfig >> +++ b/xen/arch/arm/Kconfig >> @@ -276,6 +276,15 @@ config PCI_PASSTHROUGH >>     endmenu >>   +config GICV3_NR_LRS >> +    int "Number of GICv3 Link Registers supported" if EXPERT > > Supported by who? The hardware? Xen? Asking, because I could forsee an > integrator wanted to limit the number of LRs to something smaller than > what the HW supports (in a lot of cases, 2 LRs is sufficient). Ack  ... "Number of GICv3 Link Registers used" if EXPERT So it implies a decision to be taken by the system integrator. Does it sound ok ? > >> +    depends on GICV3 >> +    range 0 16 >> +    default 0 >> +    help >> +      Controls the number of Link registers to be accessed. >> +      Keep it set to 0 to use a value obtained from a hardware >> register. > > I still strongly think that if GICV3_NR_LRS is set, then it needs to > be checked against the value read by the hardware Ack. > >> + >>   menu "ARM errata workaround via the alternative framework" >>       depends on HAS_ALTERNATIVE >>   diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c >> index bc07f97c16..eaae95eb4d 100644 >> --- a/xen/arch/arm/gic-v3.c >> +++ b/xen/arch/arm/gic-v3.c >> @@ -51,6 +51,8 @@ static DEFINE_PER_CPU(void __iomem*, rbase); >>   #define GICD                   (gicv3.map_dbase) >>   #define GICD_RDIST_BASE        (this_cpu(rbase)) >>   #define GICD_RDIST_SGI_BASE    (GICD_RDIST_BASE + SZ_64K) >> +#define LRS                    (CONFIG_GICV3_NR_LRS ?: \ >> +                                gicv3_info.nr_lrs) > > IMHO, LRS is a little bit vague. What about MAX_LRS? Or maybe NR_LRS? NR_LRS . > >>     /* >>    * Saves all 16(Max) LR registers. Though number of LRs implemented >> @@ -59,7 +61,7 @@ static DEFINE_PER_CPU(void __iomem*, rbase); >>   static inline void gicv3_save_lrs(struct vcpu *v) >>   { >>       /* Fall through for all the cases */ >> -    switch ( gicv3_info.nr_lrs ) >> +    switch ( LRS ) >>       { >>       case 16: >>           v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); >> @@ -121,7 +123,7 @@ static inline void gicv3_save_lrs(struct vcpu *v) >>   static inline void gicv3_restore_lrs(const struct vcpu *v) >>   { >>       /* Fall through for all the cases */ >> -    switch ( gicv3_info.nr_lrs ) >> +    switch ( LRS ) >>       { >>       case 16: >>           WRITE_SYSREG_LR(v->arch.gic.v3.lr[15], 15); >> @@ -178,6 +180,10 @@ static inline void gicv3_restore_lrs(const >> struct vcpu *v) >>     static uint64_t gicv3_ich_read_lr(int lr) >>   { >> +    /* RAZ for unsupported LR */ >> +    if ( lr >= LRS ) >> +        return 0; >> + >>       switch ( lr ) >>       { >>       case 0: return READ_SYSREG_LR(0); >> @@ -203,6 +209,10 @@ static uint64_t gicv3_ich_read_lr(int lr) >>     static void gicv3_ich_write_lr(int lr, uint64_t val) >>   { >> +    /* WI for unsupported LR */ > > AFAIU, this path is really not meant to happen. So I don't think we > want to silently ignore the write as it would mean an interrupt is > missing. I think in debug build, we probably want to use > ASSERT_UNREACHABLE(). If we want something for production as well, > then we could instead use WARN(). Ack. I will use WARN(). - Ayan > > Cheers, > From xen-devel-bounces@lists.xenproject.org Sat Apr 18 17:11:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sat, 18 Apr 2026 17:11:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285096.1566400 (Exim 4.92) (envelope-from ) id 1wE9CT-00029F-Nz; Sat, 18 Apr 2026 17:11:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285096.1566400; Sat, 18 Apr 2026 17:11:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wE9CT-000296-IW; Sat, 18 Apr 2026 17:11:21 +0000 Received: by outflank-mailman (input) for mailman id 1285096; Sat, 18 Apr 2026 17:11:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wE9CR-000290-Sb for xen-devel@lists.xenproject.org; Sat, 18 Apr 2026 17:11:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wE9CR-007yPY-9U for xen-devel@lists.xenproject.org; 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This is the clean backport without >> any changes. >> >> When handling faults from the event or PRI queue, we need to find the >> struct device associated with a SID. Add a rb_tree to keep track of >> SIDs. >> >> Acked-by: Jonathan Cameron >> Reviewed-by: Eric Auger >> Reviewed-by: Keqian Zhu >> Signed-off-by: Jean-Philippe Brucker >> Acked-by: Will Deacon >> Link: https://lore.kernel.org/r/20210401154718.307519-8-jean-philippe@linaro.org >> Signed-off-by: Joerg Roedel >> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cdf315f907d4 >> Signed-off-by: Rahul Singh >> Signed-off-by: Milan Djokic >> --- > > I think that by only backporting this one we are introducing a regression for which > we don’t allow anymore duplicated stream id, have a look on this linux commit > that is fixing it: b00d24997a11c10d3e420614f0873b83ce358a34. > I will backport the logic from this commit also > P.s. I was able to apply only until patch 3, I think this serie needs a rebase, do you have > an updated branch or can you point me to the staging SHA to build it? (hope it’s not too far > from now) > Yes, sorry for that, it's conflicting with the couple of recently merged commits, rebased for the new version. > Cheers, > Luca > > Best regards, Milan From xen-devel-bounces@lists.xenproject.org Sun Apr 19 17:35:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 19 Apr 2026 17:35:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285344.1566418 (Exim 4.92) (envelope-from ) id 1wEW31-0000Nq-Jw; Sun, 19 Apr 2026 17:35:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285344.1566418; Sun, 19 Apr 2026 17:35:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEW31-0000Nj-GU; Sun, 19 Apr 2026 17:35:07 +0000 Received: by outflank-mailman (input) for mailman id 1285344; Sun, 19 Apr 2026 17:35:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEW30-0000Nd-OB for xen-devel@lists.xenproject.org; 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Message-ID: <87a04781-5765-43b6-8b21-cb993609bd91@epam.com> Date: Sun, 19 Apr 2026 19:34:59 +0200 User-Agent: Mozilla Thunderbird From: Milan Djokic Subject: Re: [PATCH v2 02/23] xen/arm: smmuv3: Add support for stage-1 and nested stage translation To: Julien Grall , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk References: <56a7c116-4ecb-4dfc-a7dd-774d53041fe9@xen.org> Content-Language: en-US In-Reply-To: <56a7c116-4ecb-4dfc-a7dd-774d53041fe9@xen.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: VI1P190CA0050.EURP190.PROD.OUTLOOK.COM (2603:10a6:800:1bb::15) To AS2PR03MB9587.eurprd03.prod.outlook.com (2603:10a6:20b:595::7) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS2PR03MB9587:EE_|DB4PR03MB9433:EE_ X-MS-Office365-Filtering-Correlation-Id: 13be872a-5731-4bcd-aaec-08de9e39fbeb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|56012099003|22082099003|18002099003; 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Add support for >> Stage-1 translation that is required to support nested stage >> translation. >> >> In true nested mode, both s1_cfg and s2_cfg will coexist. >> Let's remove the union. When nested stage translation is setup, both >> s1_cfg and s2_cfg are valid. >> >> We introduce a new smmu_domain abort field that will be set >> upon guest stage-1 configuration passing. If no guest stage-1 >> config has been attached, it is ignored when writing the STE. >> >> arm_smmu_write_strtab_ent() is modified to write both stage >> fields in the STE and deal with the abort field. >> >> Signed-off-by: Rahul Singh >> Signed-off-by: Milan Djokic >> --- >> xen/drivers/passthrough/arm/smmu-v3.c | 93 +++++++++++++++++++++++---- >> xen/drivers/passthrough/arm/smmu-v3.h | 9 +++ >> 2 files changed, 91 insertions(+), 11 deletions(-) >> >> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c >> index 73cc4ef08f..f9c6837919 100644 >> --- a/xen/drivers/passthrough/arm/smmu-v3.c >> +++ b/xen/drivers/passthrough/arm/smmu-v3.c >> @@ -683,8 +683,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, >> * 3. Update Config, sync >> */ >> u64 val = le64_to_cpu(dst[0]); >> - bool ste_live = false; >> + bool s1_live = false, s2_live = false, ste_live = false; >> + bool abort, translate = false; >> struct arm_smmu_device *smmu = NULL; >> + struct arm_smmu_s1_cfg *s1_cfg = NULL; >> struct arm_smmu_s2_cfg *s2_cfg = NULL; >> struct arm_smmu_domain *smmu_domain = NULL; >> struct arm_smmu_cmdq_ent prefetch_cmd = { >> @@ -699,30 +701,54 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, >> smmu = master->smmu; >> } >> >> - if (smmu_domain) >> - s2_cfg = &smmu_domain->s2_cfg; >> + if (smmu_domain) { >> + switch (smmu_domain->stage) { >> + case ARM_SMMU_DOMAIN_NESTED: >> + s1_cfg = &smmu_domain->s1_cfg; >> + fallthrough; >> + case ARM_SMMU_DOMAIN_S2: >> + s2_cfg = &smmu_domain->s2_cfg; >> + break; >> + default: >> + break; >> + } >> + translate = !!s1_cfg || !!s2_cfg; > > NIT: translate is a bool. So do you actually need the !!? > No, !! is not necessary here, will fix this. >> + } >> >> if (val & STRTAB_STE_0_V) { >> switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { >> case STRTAB_STE_0_CFG_BYPASS: >> break; >> + case STRTAB_STE_0_CFG_S1_TRANS: >> + s1_live = true; >> + break; >> case STRTAB_STE_0_CFG_S2_TRANS: >> - ste_live = true; >> + s2_live = true; >> + break; >> + case STRTAB_STE_0_CFG_NESTED: >> + s1_live = true; >> + s2_live = true; >> break; >> case STRTAB_STE_0_CFG_ABORT: >> - BUG_ON(!disable_bypass); > > I am not sure I understand why this was removed. Can you clarify? > Yes. With the stage-1 support, abort is controlled per guest smmu configuration, so abort state is valid and not controlled by the global disable_bypass, but with per-config smmu_domain->abort field instead. >> break; >> default: >> BUG(); /* STE corruption */ >> } >> } >> >> + ste_live = s1_live || s2_live; >> + >> /* Nuke the existing STE_0 value, as we're going to rewrite it */ >> val = STRTAB_STE_0_V; >> >> /* Bypass/fault */ >> - if (!smmu_domain || !(s2_cfg)) { >> - if (!smmu_domain && disable_bypass) >> + if (!smmu_domain) >> + abort = disable_bypass; >> + else >> + abort = smmu_domain->abort; >> + >> + if (abort || !translate) { >> + if (abort) >> val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); >> else >> val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); >> @@ -740,7 +766,33 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, >> return; >> } >> >> + if (ste_live) { >> + /* First invalidate the live STE */ >> + dst[0] = cpu_to_le64(STRTAB_STE_0_CFG_ABORT); >> + arm_smmu_sync_ste_for_sid(smmu, sid); >> + } >> + >> + if (s1_cfg) { >> + BUG_ON(s1_live); >> + dst[1] = cpu_to_le64( >> + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | >> + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | >> + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | >> + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | >> + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); >> + >> + if (smmu->features & ARM_SMMU_FEAT_STALLS && >> + !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) >> + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); >> + >> + val |= (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) | >> + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | >> + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | >> + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); >> + } >> + >> if (s2_cfg) { >> + u64 vttbr = s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK; >> u64 strtab = >> FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | >> FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | >> @@ -750,12 +802,19 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, >> STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | >> STRTAB_STE_2_S2R; >> >> - BUG_ON(ste_live); >> + if (s2_live) { >> + u64 s2ttb = le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK; >> + BUG_ON(s2ttb != vttbr); >> + } >> + >> dst[2] = cpu_to_le64(strtab); >> >> - dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); >> + dst[3] = cpu_to_le64(vttbr); >> >> val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); >> + } else { >> + dst[2] = 0; >> + dst[3] = 0; >> } >> >> if (master->ats_enabled) >> @@ -1254,6 +1313,15 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, >> { >> int ret; >> struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); >> + struct arm_smmu_device *smmu = smmu_domain->smmu; >> + >> + if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED && >> + (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || >> + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) { >> + dev_info(smmu_domain->smmu->dev, >> + "does not implement two stages\n"); >> + return -EINVAL; >> + } >> >> /* Restrict the stage to what we can actually support */ >> smmu_domain->stage = ARM_SMMU_DOMAIN_S2; >> @@ -2353,11 +2421,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) >> break; >> } >> >> + if (reg & IDR0_S1P) >> + smmu->features |= ARM_SMMU_FEAT_TRANS_S1; >> + >> if (reg & IDR0_S2P) >> smmu->features |= ARM_SMMU_FEAT_TRANS_S2; >> >> - if (!(reg & IDR0_S2P)) { >> - dev_err(smmu->dev, "no stage-2 translation support!\n"); >> + if (!(reg & (IDR0_S1P | IDR0_S2P))) { > > I believe the behavior is now slightly different. This would not print > anything if the SMMU support stage-1 but not stage-2. However, Xen at > least need the latter. > The original idea was to also allow stage-1-only support. But I'm not sure if stage-1-only usecase is useful or even valid for Xen.. I will update the patch series with the missing parts for stage-1-only support, pointed out by Luca, but the question remains if this is needed at all. If not, I can revert to original state where stage-2 was always required. >> + dev_err(smmu->dev, "no translation support!\n"); >> return -ENXIO; >> } >> >> diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h >> index ab1f29f6c7..3fb13b7e21 100644 >> --- a/xen/drivers/passthrough/arm/smmu-v3.h >> +++ b/xen/drivers/passthrough/arm/smmu-v3.h >> @@ -197,6 +197,7 @@ >> #define STRTAB_STE_0_CFG_BYPASS 4 >> #define STRTAB_STE_0_CFG_S1_TRANS 5 >> #define STRTAB_STE_0_CFG_S2_TRANS 6 >> +#define STRTAB_STE_0_CFG_NESTED 7 >> >> #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) >> #define STRTAB_STE_0_S1FMT_LINEAR 0 >> @@ -549,6 +550,12 @@ struct arm_smmu_strtab_l1_desc { >> dma_addr_t l2ptr_dma; >> }; >> >> +struct arm_smmu_s1_cfg { >> + u64 s1ctxptr; >> + u8 s1fmt; >> + u8 s1cdmax; >> +}; >> + >> struct arm_smmu_s2_cfg { >> u16 vmid; >> u64 vttbr; >> @@ -669,7 +676,9 @@ struct arm_smmu_domain { >> atomic_t nr_ats_masters; >> >> enum arm_smmu_domain_stage stage; >> + struct arm_smmu_s1_cfg s1_cfg; >> struct arm_smmu_s2_cfg s2_cfg; >> + bool abort; > > I think there might be some padding before s1_cfg. So I wonder whether > this would be better be moved before to reduce the size of the structure. > Will do so. >> >> /* Xen domain associated with this SMMU domain */ >> struct domain *d; > > Cheers, > Best regards, Milan From xen-devel-bounces@lists.xenproject.org Sun Apr 19 17:55:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 19 Apr 2026 17:55:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285362.1566427 (Exim 4.92) (envelope-from ) id 1wEWMt-0003Tr-8h; Sun, 19 Apr 2026 17:55:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285362.1566427; Sun, 19 Apr 2026 17:55:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEWMt-0003Tk-5z; Sun, 19 Apr 2026 17:55:39 +0000 Received: by outflank-mailman (input) for mailman id 1285362; Sun, 19 Apr 2026 17:55:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEWMr-0003Te-SW for xen-devel@lists.xenproject.org; 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>> } >> >> + if (ste_live) { >> + /* First invalidate the live STE */ >> + dst[0] = cpu_to_le64(STRTAB_STE_0_CFG_ABORT); >> + arm_smmu_sync_ste_for_sid(smmu, sid); >> + } >> + >> + if (s1_cfg) { >> + BUG_ON(s1_live); > > I think this is wrong, if a guest issues another s1 update on the same sid, this will crash Xen, I think > that we’ve already invalidated the live status so this one should be removed > Yes, this is a leftover. I will remove this assertion. >> + dst[1] = cpu_to_le64( >> + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | >> + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | >> + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | >> + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | >> + FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1)); >> + >> + if (smmu->features & ARM_SMMU_FEAT_STALLS && >> + !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) >> + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); >> + >> + val |= (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) | >> + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | >> + FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) | >> + FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt); >> + } >> + >> if (s2_cfg) { >> + u64 vttbr = s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK; >> u64 strtab = >> FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | >> FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | >> @@ -750,12 +802,19 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, >> STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | >> STRTAB_STE_2_S2R; >> >> - BUG_ON(ste_live); >> + if (s2_live) { >> + u64 s2ttb = le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK; >> + BUG_ON(s2ttb != vttbr); >> + } >> + >> dst[2] = cpu_to_le64(strtab); >> >> - dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); >> + dst[3] = cpu_to_le64(vttbr); >> >> val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); >> + } else { >> + dst[2] = 0; >> + dst[3] = 0; >> } >> >> if (master->ats_enabled) >> @@ -1254,6 +1313,15 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, >> { >> int ret; >> struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); >> + struct arm_smmu_device *smmu = smmu_domain->smmu; >> + >> + if (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED && >> + (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || >> + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) { >> + dev_info(smmu_domain->smmu->dev, >> + "does not implement two stages\n"); >> + return -EINVAL; >> + } >> >> /* Restrict the stage to what we can actually support */ >> smmu_domain->stage = ARM_SMMU_DOMAIN_S2; > > Here we set stage 2 as default, but in arm_smmu_device_hw_probe() we’ve > deleted the check for S2 required, so if we have an HW with only S1 the probe will > succeed but we will wrongly set here S2, so I would keep ... > Yes, handling of stage-1-only scenario is not correct, missing in ste and guest config handling also. I will update this in the new version. Following comments from Julien on the same topic, I'm wondering if it's valid to provide stage-1-only support in Xen? >> @@ -2353,11 +2421,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) >> break; >> } >> >> + if (reg & IDR0_S1P) >> + smmu->features |= ARM_SMMU_FEAT_TRANS_S1; >> + >> if (reg & IDR0_S2P) >> smmu->features |= ARM_SMMU_FEAT_TRANS_S2; >> >> - if (!(reg & IDR0_S2P)) { >> - dev_err(smmu->dev, "no stage-2 translation support!\n"); > > this change, rearranged in the way that is sensible with the new logic. > >> + if (!(reg & (IDR0_S1P | IDR0_S2P))) { >> + dev_err(smmu->dev, "no translation support!\n"); >> return -ENXIO; >> } >> > Best regards, Milan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 07:26:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 07:26:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285417.1566452 (Exim 4.92) (envelope-from ) id 1wEj1e-00051Y-7D; Mon, 20 Apr 2026 07:26:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285417.1566452; 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bh=uB6k0kOtErN3VP+hR2720UAh2VmSDTlX3y1KH48oS/8=; b=VtdM4A8sGo+0TW5J98po2Ld8wQ0IxhESd9FBpfgzZGPHn7Ji67JgmKGNYnpnnR4R/0cggLynAEkm7X412+cs1YUo74jcVMSTCaAqgKG/A1Zlqnx5EHtQtL2aVoeYHB2W3wfZ12/djsuhxtyjLpgw9SC9ZvzPvuL3VnyQWU5AJMM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Message-ID: <6188df37-47f1-4b46-8b4a-56316221b86c@amd.com> Date: Mon, 20 Apr 2026 09:26:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] xen/dom0less: introduce free_phandle in struct kernel_info To: Oleksii Kurochko , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , Andrew Cooper , Anthony PERARD , "Jan Beulich" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <58f59a071f6329acac610688a6c25b67b30e5b92.1776340422.git.oleksii.kurochko@gmail.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <58f59a071f6329acac610688a6c25b67b30e5b92.1776340422.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4SGbQQfUlrx86HlcGTKQmrQ1huBt5CPltNXYCP3HOdKqqWin0zLB9spXWSoNcAWygACiUkxi5PTaQg4zMQ/AqxrKBYSz1Y2zstR0/m9Rz34UBbZjcKPtLjIlm9gdSEM4j1o3lhUzGtbosDgMScIoEe2z0/BtTS8kq7nkqB8acMQ7vST/IjbVpL2+fl9mo1ZmeOnfQCPzUKt9L9f0jLfDjcUZenSaHdCyRVmxj7ei8fxhT7ktyKQNt0uzse3quHCjqBRNiR/J8sBS0MxiLA3YFxfG06tnMtJsEpTKjb956BAg4fgDVylDIvRoHytwa3BDi+qBl82gkJhMqNYCYQHyZKcAwlTprZ3Dz46SXNSRSxuzIr9rX6z7wwI5HmKSSgrgvB4htAAHlZ9ibYH7vl5A1zPYocPcbz04WiX2Vl+dynVp0OOD7CChjJTSW5pJcY+A X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 07:26:25.8592 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 872c1d12-84d8-4cf1-9f02-08de9eae21a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB999086 X-purgate-ID: tlsNG-720697/1776669990-880D7161-8A467684/0/0 X-purgate-type: clean X-purgate-size: 1440 On 16/04/2026 16:20, Oleksii Kurochko wrote: > There are cases where it is necessary to know the next available phandle > number in order to generate phandles for guest device nodes. > > When a partial FDT (pfdt) is provided, special care is needed during > initialization of free_phandle, as the pfdt may already contain a dummy > interrupt controller node with a phandle assigned to it. free_phandle > must therefore be initialized to one past the highest phandle already > present in the pfdt, to avoid collisions. > > Since free_phandle may be needed for the very first guest node generated, I would prefer next_phandle rather than free_phandle given that it always holds the *next* phandle to be allocated. Free is implied. > domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). > The new call site also aligns better with the existing comment stating > that domain_handle_dtb_boot_module() must be called before the rest of > the device tree is generated. > > Introduce get_next_free_phandle() to ensure that phandles allocated for The name is a bit confusing. It reads as "get the next one after the current free phandle" but it actually returns the current value of free_phandle and post increments it. Let's call it alloc_phandle(). This will also make it clear to use the return value of this function instead of directly kinfo value. Other than that, all good. ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 20 07:29:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 07:29:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285428.1566461 (Exim 4.92) (envelope-from ) id 1wEj4q-0005YK-Ku; Mon, 20 Apr 2026 07:29:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285428.1566461; Mon, 20 Apr 2026 07:29:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEj4q-0005YD-Hh; Mon, 20 Apr 2026 07:29:52 +0000 Received: by outflank-mailman (input) for mailman id 1285428; Mon, 20 Apr 2026 07:29:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEj4p-0005Y7-Pc for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 07:29:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEj4o-00GP9O-Rp for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Mon, 20 Apr 2026 09:29:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() To: Oleksii Kurochko , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , "Volodymyr Babchuk" , Andrew Cooper , Anthony PERARD , "Jan Beulich" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006001:EE_|DM3PR12MB9416:EE_ X-MS-Office365-Filtering-Correlation-Id: 24bc89bd-01e6-4bb4-36a6-08de9eae97f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PBO32GGPdqKiYc16vhuXRMRCkIl0R2LTqnCjG7yvd4tf/ZZkWBHJXTMqyxD4JKKyr41y1qlSXeL9AycDStMgoGU8Kp0fNWSlKh8wNQDy0ISR5Ojqpwcgld++TK9y2RtxzAOad/cuPhbOlE+naaojlEqfe4eZFyA9EnCznywU8b1wilOmDioi50alr9DgbIQ8LTLD2i/YnwO5Xu2j80q7nSSQApROpL0ojdMlbjrfVdsn43aWqiulxkw8pBIRQCrM98jI2UJFGBZRMl0c6Yj52iojGNw3fdqac+bRIfw7JwCAbUW1u0egcuK7S1PyY5op9dxSj4NJFqkknp0RLy0oxjWGj/WJCejXyFaOE1V+QJoA4yMA64dr9nCfLVJudy80AjgLsGI1kLikU7X3w3lmtu+IV4baqldCwU4YOMgifzybOFlI9HE7m4PXS2iwW1tN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 07:29:44.3658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24bc89bd-01e6-4bb4-36a6-08de9eae97f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006001.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9416 X-purgate-ID: tlsNG-4011c0/1776670190-4596E8B7-C1DE077D/10/73395122804 X-purgate-type: spam X-purgate-size: 1455 On 16/04/2026 16:20, Oleksii Kurochko wrote: > There are two reasons of this change: > 1. Align prototype with what other make_*_node() are passed. > 2. A follow-up RISC-V patch will call get_next_free_phandle() inside > make_cpus_node(), requiring mutable access to kinfo->free_phandle. > > Signed-off-by: Oleksii Kurochko > --- > xen/arch/arm/domain_build.c | 5 +++-- > xen/common/device-tree/dom0less-build.c | 2 +- > xen/include/xen/fdt-domain-build.h | 2 +- > 3 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 60a7cbf915a5..6740da3d324b 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -1164,7 +1164,7 @@ int __init make_psci_node(void *fdt) > return res; > } > > -int __init make_cpus_node(const struct domain *d, void *fdt) > +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) > { > int res; > const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); > @@ -1178,6 +1178,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) > /* Keep the compiler happy with -Og */ > bool clock_valid = false; > uint64_t mpidr_aff; > + void *fdt = kinfo; You're assigning kinfo to fdt pointer which is a bug. Instead, you should do: void *fdt = kinfo->fdt ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 20 07:52:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 07:52:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285442.1566469 (Exim 4.92) (envelope-from ) id 1wEjQm-0000yE-Ew; Mon, 20 Apr 2026 07:52:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285442.1566469; Mon, 20 Apr 2026 07:52:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEjQm-0000y7-CE; Mon, 20 Apr 2026 07:52:32 +0000 Received: by outflank-mailman (input) for mailman id 1285442; Mon, 20 Apr 2026 07:52:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEjQl-0000y1-EJ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 07:52:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEjQk-002hnS-Ns for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 09:52:30 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e5db3e-5cb7-0a2a0a5109dd-0a2a45038604-0 for ; Mon, 20 Apr 2026 09:52:30 +0200 Received: from [209.85.208.175] (helo=mail-lj1-f175.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e5db3e-672d-0a2a45030019-d155d0afa877-3 for ; Mon, 20 Apr 2026 09:52:30 +0200 Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-38dd9f0fdc6so39349401fa.0 for ; Mon, 20 Apr 2026 00:52:30 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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See XEN_SYSCTL_cpu_hotplug (and ignore it having >>> "hotplug" in the name, but merely consider that you can take CPUs offline >>> at runtime, and later bring them online again). >> >> Thanks, now it makes sense to drop __init. >> >>>>> Also - static? >>>> >>>> It isn't static because it will be called inside the secondary CPU >>>> bring-up function. >>> >>> As it doesn't need calling from the outside for the boot CPU, it's not >>> obvious why it would need calling from the outside for secondary ones. >> >> I think I am confused here by what do you mean by "calling from the >> outside". > > As in "from another translation unit". > >> It should be called during boot or secondary CPU initialization (if AIA >> is used), right? >> Then considering that VGEIN-related stuff is connected to AIA then >> vgein_init() is expected to live in aia.c and considering that it wants >> to be called by secondary CPU boot code it can't be static. > > Putting my question differently: Why is there a difference here between > boot CPU and secondary CPUs. My (general) expectation would be that either > the function wants calling from outside of aia.c in all cases, or it could > be static (now and later). Generally, if update prototype of aia_init() to receive cpuid argument then it will be enough to make vgein_init() static and then all others will call aia_init(). The only reason why I tried to have vgein_init() non-static is that in the case of secondary CPU there is no need to call second time anything (at least, now) from aia_init() or re-init is_aia_usable variable. But I can agree that probably it would be better to make vgein_init() static now and then use aia_init() everywhere it is needed just for the case that if something new will be added what should be called for boot and secondary CPU won't be missed to call properly. And I think it is fine just re-init is_aia_usable without any additional synchronization. As an option I could check at the start if is_aia_usable is initialized by checking if it is true and if it is then just call vgein_init() for that cpuid. Would it be better? > >>>>>> +{ >>>>>> + struct vgein_bmp *vgein = &per_cpu(vgein_bmp, cpu); >>>>>> + >>>>>> + csr_write(CSR_HGEIE, -1UL); >>>>>> + vgein->geilen = flsl(csr_read(CSR_HGEIE)); >>>>>> + csr_write(CSR_HGEIE, 0); >>>>>> + if ( vgein->geilen ) >>>>>> + vgein->geilen--; >>>>> >>>>> I don't understand this. The "len" in "geilen" stands for "length", I suppose, >>>>> i.e. the number of bits. Hmm, the spec itself is inconsistent: "The number of >>>>> bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED >>>>> and may be zero. This number is known as GEILEN." This may or may not include >>>>> bit 0 (which is implemented, but r/o zero). Then saying "Hence, if GEILEN is >>>>> nonzero, bits GEILEN:1 shall be writable in ..." suggests 0 isn't included, but >>>>> that's not unambiguous. >>>> >>>> But they explicitly wrote that: The least-significant bits are >>>> implemented first, apart from bit 0. So bit 0 is explicitly excluded. >>> >>> Fine, but not including it in anything named *LEN feels - as said - ambiguous. >> >> Agree, it is. I just tried to follow the spec naming here. But I am okay >> to rename it to max_gein, for example. > > Perhaps better stick to spec naming, but consider adding a clarifying comment. I will add then above geilen field in vgein_bmp struct the comment: The least-significant bits are implemented first, apart from bit 0 > >>>>>> + /* >>>>>> + * All vCPU guest interrupt files are used and we don't support a case >>>>>> + * when number of vCPU on 1 pCPU is bigger then geilen. >>>>>> + */ >>>>> >>>>> This wants checking in vgein_init() then. CPUs (beyond the boot one) >>>>> violating this should not be brought online. >>>> >>>> It'll be nice. But we can't know how many vCPUs will be ran on pCPU when >>>> vgein_init() is executed. >>> >>> I don't understand: How does it matter how many vCPU-s will exist later on >>> (and will run wherever)? >> >> IIUC, you want to check what is mentioned in the comment in vcpu_init(). >> The comment says that it is checking that number of vCPU on one pCPU >> isn't bigger then geilen. To check that we have to know an amount of >> vCPU potentially will be ran on pCPU. > > Well, not quite. I don't understand at all why the number of vCPU-s in > a system would be limited by any pCPU property. I don't think we have > any such constraint on x86, for example. Then I will just drop this comment and correspondent ASSERT() and just return vgein_id in the case when there is no available h/w VGEINs to mark that h/w should use s/w guest interrupt files: if ( vgein_id > vgein->geilen ) vgein_id = 0; else __set_bit(vgein_id, bmp); ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 07:57:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 07:57:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285453.1566478 (Exim 4.92) (envelope-from ) id 1wEjV3-0001Ul-VQ; Mon, 20 Apr 2026 07:56:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285453.1566478; Mon, 20 Apr 2026 07:56:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEjV3-0001Ue-Sf; Mon, 20 Apr 2026 07:56:57 +0000 Received: by outflank-mailman (input) for mailman id 1285453; Mon, 20 Apr 2026 07:56:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEjV2-0001UY-6g for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 07:56:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEjV1-00GVMR-J5 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 09:56:55 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e5dc2f-e002-0a2a0a5209dd-0a2a450b9c36-46 for ; Mon, 20 Apr 2026 09:56:55 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e5dc47-212f-0a2a450b0019-d155802ad96b-3 for ; Mon, 20 Apr 2026 09:56:55 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso23034965e9.3 for ; Mon, 20 Apr 2026 00:56:55 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1776671815-252B9F3B-5157A77A/0/0 X-purgate-type: clean X-purgate-size: 2022 On 17.04.2026 09:24, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/csr.h > +++ b/xen/arch/riscv/include/asm/csr.h > @@ -32,6 +32,20 @@ > : "memory" ); \ > }) > > +#ifdef CONFIG_RISCV_32 > +# define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) > +#else > +# define __csr_write32h(csr, val) ((void)(csr), (void)(val)) In order to be able to spot issues in 64-bit builds, how about # define __csr_write32h(csr, val) ((void)csr ## H, (void)(val)) ? Apart from this, no matter that it was Andrew to suggest this, I'd like to (once again) point out that identifiers starting with two underscores are reserved. I don't see why a single underscore wouldn't do here. Or alternatively csr__write32h(). > @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) > return sbi_err_map_xen_errno(ret.error); > } > > -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; > - > int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, > size_t size) > { > @@ -360,10 +378,9 @@ int __init sbi_init(void) > } > > if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) > - { > - sbi_set_timer = sbi_set_timer_v02; > - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); > - } > + set_xen_timer = sbi_set_timer_v02; > + else > + set_xen_timer = sbi_set_timer_v01; > } Sadly this isn't quite equivalent to sbi_set_timer having had an initializer. I would have wanted to suggest to use a constructor function, but we call init_constructors() even later than do_initcalls() on both Arm and x86 (we don't call the latter at all on RISC-V so far). Might it be necessary to introduce sbi_early_init(), called very early during boot? Else how do you guarantee no accidental use of the variable before it is first set? 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RAM >>> regions get >>> handed to the physical memory allocator for general use. Similarly, >>> failure >>> to mark the boot modules as reserved is not going to result in a working >>> system. >>> >>> Mark reserve_e820_ram() as __must_check, and panic() on failure. To >>> avoid >>> opencoding the range in every caller, print a general failure message in >>> reserve_e820_ram(). >>> >>> Reported-by: Ross Lagerwall >>> Signed-off-by: Andrew Cooper >>> --- >>> CC: Jan Beulich >>> CC: Roger Pau Monné >>> CC: Teddy Astie >>> >>> Slightly RFC; only compile tested so far. >>> >>> There's no obvious fixes tag. This has been many variations of >>> broken since >>> forever. >>> --- >>> xen/arch/x86/e820.c | 8 +++++++- >>> xen/arch/x86/include/asm/e820.h | 2 +- >>> xen/arch/x86/setup.c | 11 +++++++---- >>> 3 files changed, 15 insertions(+), 6 deletions(-) >>> >>> diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c >>> index 872208ab3722..f09a01f0c50a 100644 >>> --- a/xen/arch/x86/e820.c >>> +++ b/xen/arch/x86/e820.c >>> @@ -670,7 +670,13 @@ int __init e820_change_range_type( >>> /* Set E820_RAM area (@s,@e) as RESERVED in specified e820 map. */ >>> int __init reserve_e820_ram(struct e820map *map, uint64_t s, >>> uint64_t e) >>> { >>> - return e820_change_range_type(map, s, e, E820_RAM, E820_RESERVED); >>> + int res = e820_change_range_type(map, s, e, E820_RAM, >>> E820_RESERVED); >>> + >>> + if ( !res ) >>> + printk("Failed to convert E820 RAM %"PRIx64"-%"PRIx64" to >>> RESERVED\n", >>> + s, e); >>> + >>> + return res; >>> } >>> unsigned long __init init_e820(const char *str, struct e820map *raw) >>> diff --git a/xen/arch/x86/include/asm/e820.h >>> b/xen/arch/x86/include/asm/e820.h >>> index 8e7644f8870b..a86d60ce3e77 100644 >>> --- a/xen/arch/x86/include/asm/e820.h >>> +++ b/xen/arch/x86/include/asm/e820.h >>> @@ -25,7 +25,7 @@ struct e820map { >>> extern int sanitize_e820_map(struct e820entry *biosmap, unsigned >>> int *pnr_map); >>> extern int e820_all_mapped(u64 start, u64 end, unsigned type); >>> -extern int reserve_e820_ram(struct e820map *map, uint64_t s, >>> uint64_t e); >>> +extern int __must_check reserve_e820_ram(struct e820map *map, >>> uint64_t s, uint64_t e); >>> extern int e820_change_range_type( >>> struct e820map *map, uint64_t s, uint64_t e, >>> uint32_t orig_type, uint32_t new_type); >>> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c >>> index d041cbd5f6f1..9c1f1eafa0d7 100644 >>> --- a/xen/arch/x86/setup.c >>> +++ b/xen/arch/x86/setup.c >>> @@ -1639,7 +1639,8 @@ void asmlinkage __init noreturn __start_xen(void) >>> { >>> uint64_t s = bi->mods[i].start, l = bi->mods[i].size; >>> - reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)); >>> + if ( !reserve_e820_ram(&boot_e820, s, s + PAGE_ALIGN(l)) ) >>> + panic("Failed to reserve boot module %u in E820\n", i); i is an int, so it should be %d. >>> } >>> if ( !xen_phys_start ) >>> @@ -1652,11 +1653,13 @@ void asmlinkage __init noreturn >>> __start_xen(void) >>> /* This needs to remain in sync with remove_xen_ranges(). */ >>> if ( efi_boot_mem_unused(&eb_start, &eb_end) ) >>> { >>> - reserve_e820_ram(&boot_e820, __pa(_stext), __pa(eb_start)); >>> - reserve_e820_ram(&boot_e820, __pa(eb_end), >>> __pa(__2M_rwdata_end)); >>> + if ( !reserve_e820_ram(&boot_e820, __pa(_stext), >>> __pa(eb_start)) || >>> + !reserve_e820_ram(&boot_e820, __pa(eb_end), >>> __pa(__2M_rwdata_end)) ) >>> + panic("Failed to reserve Xen in E820\n"); >>> } >>> else >>> - reserve_e820_ram(&boot_e820, __pa(_stext), >>> __pa(__2M_rwdata_end)); >>> + if ( reserve_e820_ram(&boot_e820, __pa(_stext), >>> __pa(__2M_rwdata_end)) ) >>> + panic("Failed to reserve Xen in E820\n"); >>> >> >> This condition is inverted. >> Otherwise this looks like a sensible change. > > Oops, yes. Fixed. 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pr=C Message-ID: Date: Mon, 20 Apr 2026 10:03:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE To: Oleksii Kurochko , CC: Andrew Cooper , Anthony PERARD , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013C:EE_|MN2PR12MB4373:EE_ X-MS-Office365-Filtering-Correlation-Id: f1d14d4b-91f7-4e0c-e619-08de9eb351aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: IQnBV7ABC6c9rdhJJGhVmAMoeX0Ra1iqEp/bawHvRtSW8xoZIJae9rZiqesCyfGSNj07jq2H+2GFzVM1EWi92hBPL3Ia5sQ6zZa0ui1HImTifIsHmYcWran+S49aOFKOeWaiDiiLEPVUNAQlgZVbtmPxtQ7nCMTAVEN5Zcv83lBYZlC+gPVnfAnb95oGQoJKqe5GtMxnyDzBFPLIEph5YVvm2Ar/I+kussna0bOUek1GOi3frISwTYPJjFranbml45PYAGknvAAPgqSfyDj4BBMuL5HNPlVnv4Aj0FYhT+T9dxoF6kDOTDBB7Stv1vft1DPIUGYR6OIQUQjEYlLGLzKNgDDR3uT+n1aPxWNu/B0wYlwkReL2vQ7Uj4w1S6RfGaZtUdPKV6YGbU17kxZGlDDRUbFPwsXAUAhWkRMB7Zgs+wsJUEC7zq93ft0cyAjxFMuymYi9cKKx12gGEHVEy0FrIlNX9uiqgaLxJ/W6Ohj9PBTbO2u7w02SdSnPLhrEWa6dGW7ZRHcgCy1eUAnIoiNtsYp9hwfDd3PC/OVCdKYXAr4qShCb626a+nzWaDrNvV5jChG3zkzNbCGiT2Ped2p7VgN56vpg2zTnbArFN1oYeE9Av81vmzQ/VPP4+WbBtIy1nzxTBBnhG8nSrpyFQ3vqP2mmNrn1Lp+eMY6pMnARyw6sygAagI7B6i6bslE4jD9AkhBmQBNMPzDNYuimTHZjx1UQHGeqIDXoH3YyBjxvYr9D2YfbWsTgsdc/L5HUUVwcpakICyAQeR6yXhZHfA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(7416014)(82310400026)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Lde9OLG+sI3dwkXERktZb775qX2h0x/fojbvNbfFMbBko9ZL1Nxm+/2AqNJRLor9W8rH2ngE9Hh69mDE3NA3jIAafzxxSlRQjYKnQVsSWr1uRmDUwcSLiDD4qE8c4PvyN1UMGA4Ibi/iPKDZlsCWmKbu850MvQo0hJG32gDmPHEOe3vYeV6XgTPnIvsXhx/HsQItfTCe1aa+zMdqNRD4orrF8WZSLyeoQvOz2gonfM89z2AufXX/qZkL/1JBL2ZUN+fgA5ecISKwmVCPo8T5quvW08bVBaPldhXTL/kkUwPzI7kP/2z2iak8KsR2GMbfI2mrvNJefaM0SnPlbnVWQW8+TjZzOk/ZwjRbsJFGxZ+NYICtvsx6O2k4esLvr2xSO9u+stlls+DKqB01bm9x+fVgXq2pCR6AKUoZJrck/dDNdUH4wB7MtJecGcL7haMj X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 08:03:33.9149 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1d14d4b-91f7-4e0c-e619-08de9eb351aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4373 X-purgate-ID: tlsNG-d25034/1776672226-6E776CF5-E6B9C4FC/10/73395122804 X-purgate-type: spam X-purgate-size: 4711 On 16/04/2026 16:21, Oleksii Kurochko wrote: > As domain type is part of common code now there is no any reason > to have architecture-specific set_domain_type() functions so > it is dropped. > > The CONFIG_ARM_64 guard in xen/arch/arm/domain_build.c is intentionally > left unchanged: it is ARM-specific code, and ARM_64 selects > HAS_DOMAIN_TYPE, so the semantics are identical. > > x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as > x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. For x86_32 > it is fine to follow generic is_{32,64}_bit_domain() implementations. I thought x86_32 Xen no longer builds. This means the fallback is only for arm32. > > Generally it probably would be better to introduce CONFIG_32BIT > and use it to define is_{32,64}bit_domain() as if one day > CONFIG_128BIT will be introduced is_{32,64}bit_domain() will be > defined incorrectly but considering that CONFIG_64BIT is maximum > supported bitness it is fine to define in this way. > > Signed-off-by: Oleksii Kurochko > --- > xen/arch/Kconfig | 3 +++ > xen/arch/arm/Kconfig | 1 + > xen/arch/arm/arm64/domctl.c | 4 ++-- > xen/arch/arm/dom0less-build.c | 14 -------------- > xen/arch/arm/domain_build.c | 8 ++++---- > xen/arch/arm/include/asm/domain.h | 12 ------------ > xen/arch/arm/include/asm/kernel.h | 4 ---- > xen/arch/arm/kernel.c | 10 +++++----- > xen/common/device-tree/dom0less-build.c | 5 ++++- > xen/include/xen/dom0less-build.h | 2 -- > xen/include/xen/domain.h | 13 +++++++++++++ > xen/include/xen/fdt-kernel.h | 5 +++++ > xen/include/xen/sched.h | 4 ++++ > 13 files changed, 41 insertions(+), 44 deletions(-) > > diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig > index f9230bfaf872..6c53149f7ee1 100644 > --- a/xen/arch/Kconfig > +++ b/xen/arch/Kconfig > @@ -1,6 +1,9 @@ > config 64BIT > bool > > +config HAS_DOMAIN_TYPE > + bool > + > config PHYS_ADDR_T_32 > bool > > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig > index 2f2b501fdac4..79622b46a10d 100644 > --- a/xen/arch/arm/Kconfig > +++ b/xen/arch/arm/Kconfig > @@ -7,6 +7,7 @@ config ARM_64 > def_bool y > depends on !ARM_32 > select 64BIT > + select HAS_DOMAIN_TYPE > select HAS_FAST_MULTIPLY > select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH > > diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c > index 8720d126c97d..9e9a29eb1e78 100644 > --- a/xen/arch/arm/arm64/domctl.c > +++ b/xen/arch/arm/arm64/domctl.c > @@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type) > return -EINVAL; > if ( domain_tot_pages(d) != 0 ) > return -EBUSY; > - if ( d->arch.type == type ) > + if ( d->type == type ) > return 0; > > - d->arch.type = type; > + d->type = type; > > if ( is_64bit_domain(d) ) > for_each_vcpu(d, v) > diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c > index 4181c105389a..6f73c65e5151 100644 > --- a/xen/arch/arm/dom0less-build.c > +++ b/xen/arch/arm/dom0less-build.c > @@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) > return 0; > } > > -/* TODO: make arch.type generic ? */ > -#ifdef CONFIG_ARM_64 > -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) > -{ > - /* type must be set before allocate memory */ > - d->arch.type = kinfo->arch.type; > -} > -#else > -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) > -{ > - /* Nothing to do */ > -} > -#endif > - > int __init init_vuart(struct domain *d, struct kernel_info *kinfo, > const struct dt_device_node *node) > { > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 6740da3d324b..2fd89b3a1345 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -1178,7 +1178,7 @@ int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) > /* Keep the compiler happy with -Og */ > bool clock_valid = false; > uint64_t mpidr_aff; > - void *fdt = kinfo; > + void *fdt = kinfo->fdt; Here you are fixing a regression introduced in patch 2/3. I'm ok with this patch. but since you touch common code too you need to wait for other's opinion. For now, provided you fix the commit msg and regression remark: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 20 08:22:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 08:22:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285499.1566506 (Exim 4.92) (envelope-from ) id 1wEjtV-0007Bp-CX; Mon, 20 Apr 2026 08:22:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285499.1566506; Mon, 20 Apr 2026 08:22:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEjtV-0007Bi-8u; Mon, 20 Apr 2026 08:22:13 +0000 Received: by outflank-mailman (input) for mailman id 1285499; Mon, 20 Apr 2026 08:22:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEjtU-0007Bc-36 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 08:22:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEjtT-009ubX-G0 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 10:22:11 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e5e230-e002-0a2a0a5209dd-0a2a45019e0c-20 for ; Mon, 20 Apr 2026 10:22:11 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e5e233-c1f2-0a2a45010019-d155802fe5ac-3 for ; Mon, 20 Apr 2026 10:22:11 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso26705885e9.1 for ; Mon, 20 Apr 2026 01:22:11 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776673331-BE066FF4-DF5F8203/0/0 X-purgate-type: clean X-purgate-size: 4504 On 16.04.2026 16:21, Oleksii Kurochko wrote: > As domain type is part of common code now there is no any reason > to have architecture-specific set_domain_type() functions so > it is dropped. > > The CONFIG_ARM_64 guard in xen/arch/arm/domain_build.c is intentionally > left unchanged: it is ARM-specific code, and ARM_64 selects > HAS_DOMAIN_TYPE, so the semantics are identical. Still I think it would better be updated, for consistency's sake. > x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as > x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. For x86_32 > it is fine to follow generic is_{32,64}_bit_domain() implementations. As Michal has also alluded to, the use of x86_32 here needs some further qualification, as Xen hasn't been possible to be built for that target for many years. Quite possibly you mean guest type there, but then it's unclear why you would restrict the explanation to 32-bit guests. > Generally it probably would be better to introduce CONFIG_32BIT > and use it to define is_{32,64}bit_domain() as if one day > CONFIG_128BIT will be introduced is_{32,64}bit_domain() will be > defined incorrectly but considering that CONFIG_64BIT is maximum > supported bitness it is fine to define in this way. Many things will need adjustment for a future CONFIG_128BIT. Imo this kind of statement doesn't belong in a patch description; it could be a post-commit-message remark. > --- a/xen/arch/Kconfig > +++ b/xen/arch/Kconfig > @@ -1,6 +1,9 @@ > config 64BIT > bool > > +config HAS_DOMAIN_TYPE > + bool > + > config PHYS_ADDR_T_32 > bool Why here rather than where the bulk of the other HAS_* are? > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -1178,7 +1178,7 @@ int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) > /* Keep the compiler happy with -Og */ > bool clock_valid = false; > uint64_t mpidr_aff; > - void *fdt = kinfo; > + void *fdt = kinfo->fdt; > > dt_dprintk("Create cpus node\n"); > > @@ -1774,13 +1774,13 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) > > #ifdef CONFIG_ARM_64 > /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ > - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) > + if ( !(cpu_has_el1_32) && kinfo->type == DOMAIN_32BIT ) I'm not an Arm maintainer; if I was, I'd ask for the stray parentheses to be dropped on this occasion. > @@ -1896,7 +1896,7 @@ int __init construct_hwdom(struct kernel_info *kinfo, > > #ifdef CONFIG_ARM_64 > /* type must be set before allocate_memory */ > - d->arch.type = kinfo->arch.type; > + d->type = kinfo->type; > #endif I wonder why this doesn't use set_domain_type() (see also below). > --- a/xen/common/device-tree/dom0less-build.c > +++ b/xen/common/device-tree/dom0less-build.c > @@ -809,7 +809,10 @@ static int __init construct_domU(struct kernel_info *kinfo, > if ( rc < 0 ) > return rc; > > - set_domain_type(d, kinfo); > +#ifdef CONFIG_HAS_DOMAIN_TYPE > + /* type must be set before allocate memory */ Nit: Comment style. > + d->type = kinfo->type; > +#endif Imo it would be preferable to retain set_domain_type(), to avoid #ifdef-ary here and in construct_hwdom(). Of course its implementation would need to move. Couldn't it be ... > --- a/xen/include/xen/dom0less-build.h > +++ b/xen/include/xen/dom0less-build.h > @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, > int make_intc_domU_node(struct kernel_info *kinfo); > int make_arch_nodes(struct kernel_info *kinfo); > > -void set_domain_type(struct domain *d, struct kernel_info *kinfo); ... an inline function here? > --- a/xen/include/xen/sched.h > +++ b/xen/include/xen/sched.h > @@ -668,6 +668,10 @@ struct domain > struct page_info *pending_scrub; > unsigned int pending_scrub_order; > unsigned int pending_scrub_index; > + > +#ifdef CONFIG_HAS_DOMAIN_TYPE > + enum domain_type type; > +#endif > } __aligned(PAGE_SIZE); I'm not quite happy with all new fields getting put at the bottom, when better options may exist. If the enum was a packed one, it could go next to domain_id (where 16 bits of padding presently exist). The five *_pages fields also have a padding field following them (unless MEM_SHARING != MEM_PAGING). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9bee01f5-8275-4d8e-b217-1b2d2f8fa2e8@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776673771-49AB6A53-A2047AD8/0/0 X-purgate-type: clean X-purgate-size: 3587 On 17.04.2026 15:47, Oleksii Kurochko wrote: > On 4/16/26 2:31 PM, Jan Beulich wrote: >> On 14.04.2026 11:22, Oleksii Kurochko wrote: >>> On 4/2/26 1:31 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> --- a/xen/arch/riscv/imsic.c >>>>> +++ b/xen/arch/riscv/imsic.c >>>>> @@ -59,6 +59,29 @@ do { \ >>>>> csr_clear(CSR_SIREG, v); \ >>>>> } while (0) >>>>> >>>>> +unsigned int vcpu_guest_file_id(const struct vcpu *v) >>>>> +{ >>>>> + struct imsic_state *imsic_state = v->arch.imsic_state; >>>>> + unsigned long flags; >>>>> + unsigned int vsfile_id; >>>>> + >>>>> + read_lock_irqsave(&imsic_state->vsfile_lock, flags); >>>>> + vsfile_id = imsic_state->guest_file_id; >>>>> + read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); >>>> >>>> What purpose does this locking have? Already ... >>>> >>>>> + return vsfile_id; >>>> >>>> ... here the value can be stale, if indeed there is a chance of races. >>>> Did you perhaps mean to use ACCESS_ONCE() here and where the value is >>>> set? >>> >>> ACCESS_ONCE() isn't guarantee only compiler re-ordering (as basically it >>> is just volatile-related stuff inisde the macros)? >>> >>> Generally, I think that that guest_file_id is needed to be updated only >>> during migration of vCPU from one pCPU to another and I expect that >>> during this migration vCPU isn't active, so no one will want to read >>> imsic_state->guest_file_id. But on the other hand, there is: >>> bool imsic_has_interrupt(const struct vcpu *vcpu) >>> { >>> ... >>> /* >>> * The IMSIC SW-file directly injects interrupt via hvip so >>> * only check for interrupt when IMSIC VS-file is being used. >>> */ >>> >>> read_lock_irqsave(&imsic_state->vsfile_lock, flags); >>> if ( imsic_state->vsfile_pcpu != NR_CPUS ) >>> ret = !!(csr_read(CSR_HGEIP) & BIT(imsic_state->guest_file_id, >>> UL)); >>> read_unlock_irqrestore(&imsic_state->vsfile_lock, flags); >>> ... >>> } >>> which I think could be called in parallel with with migration, so then >>> still lock are needed. >> >> None of this addresses my pointing out that the returned value will be >> stale by the point the caller gets to look at it. > > Yes, I agree that lock in vcpu_guest_file_id() is useless and it should > be on the caller side and used for the whole IMSIC state access. But ... > >> Which in turn raises >> said question about the use of a lock. If you read >> imsic_state->guest_file_id atomically (i.e. excluding tearing of reads), >> the value seen / used will be stale as with the lock in use. Unless of >> course there's yet another aspect hidden somewhere in what is not being >> explained. > > ... I am not sure that I get this part. > > If I am somewhere in migration code where I took write lock to update > imsic state (and of course ->guest_file_id as part of it) then if > someone else in parallel calls imsic_has_interrupt() then it won't enter > critical section where ->guest_file_id is trying to be read so no stale > ->guest_file_id will be read. Well, hence why I said "Unless of course there's yet another aspect hidden somewhere in what is not being explained." If I don't know the full picture, I can't very well judge whether a lock is needed, or whether ... > Then does it make sense to use ACCESS_ONCE() during read and write of > ->guest_file_id in such use cases? ... ACCESS_ONCE() would be enough. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776674074-BDC64FF4-DDF4E661/0/0 X-purgate-type: clean X-purgate-size: 634 On 17.04.2026 18:08, Andrew Cooper wrote: > --- a/xen/arch/x86/include/asm/e820.h > +++ b/xen/arch/x86/include/asm/e820.h > @@ -25,7 +25,7 @@ struct e820map { > > extern int sanitize_e820_map(struct e820entry *biosmap, unsigned int *pnr_map); > extern int e820_all_mapped(u64 start, u64 end, unsigned type); > -extern int reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); > +extern int __must_check reserve_e820_ram(struct e820map *map, uint64_t s, uint64_t e); Nit: This line has grown too long now. With this and the adjustments Ross has asked for: Reviewed-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 08:38:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 08:38:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285529.1566532 (Exim 4.92) (envelope-from ) id 1wEk9C-0001jh-4D; Mon, 20 Apr 2026 08:38:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285529.1566532; Mon, 20 Apr 2026 08:38:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEk9C-0001ja-1K; Mon, 20 Apr 2026 08:38:26 +0000 Received: by outflank-mailman (input) for mailman id 1285529; Mon, 20 Apr 2026 08:38:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEk9A-0001jU-Fz for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Mon, 20 Apr 2026 10:38:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown To: Mykola Kvach , CC: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk References: <459cf46204e86ed3a2ffd79ae649b1a2051f5204.1775812563.git.mykola_kvach@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <459cf46204e86ed3a2ffd79ae649b1a2051f5204.1775812563.git.mykola_kvach@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|MW4PR12MB7264:EE_ X-MS-Office365-Filtering-Correlation-Id: 1beb2688-3f32-4537-3918-08de9eb82be0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: U7+4oM2FxHntrTOTJUu9FSyeS0rWeGhfay1SMOFUpYJC3HgUhlSwV2BX4bRybnLClu6LSCV5Lo2pJp4QDgrS0xJo6lkXc1KZ6+L0QiAYwdUXORlCuJOM2i6B6sX/XRqwR2TEEIXNiUMYUzZxmfZOul0Ocjv84PDDLO6pDj5Z4WIJ3piIUn6DCewUcZ+gOq3PPoeIMcRn20xT55J/3d24gaymZ9s42F5pSWSfa47oxJlrRw+QeOpzPdYIgJRQRsdvpJoonZqPXPhwaKxR2L4XKC8jDR/vCXL+QZ4IZWKXVeG+/xiZ9FFE8DIM710CVVgpJE+IV4OgQKGHNZbaocFeYl6NvehVA/QkJ8grIn4+MLNnOTtUC/P+1vYM4rvVFyY/pWqWLc2IixSLmVj7y7Yh36CjmXjdCZh5G2sw5ywVhPTrS+xdy8zMcKMjxZzgsJ44Cm/tt8qp1XWHH5q5h7Rhj4Cj9ggWLNQOJx5duMa+qwd2C0hfVz1IdI8BS252BQ8dtHar2edYNrEWTKMHpCFZ8RF/xcFEPW+v3eN/0na92LqhKCATulnRT2X/+aBhWowBmAy43VCWsn4saFf1QtbsHukVwWSi2qH1PoH0mmjMlGjxcD9qQiHUzHhtaM0MzV84xop4pKU67GWEEAPHz+1RbT2oX6xBn1QKbDyEXfVqpzfipxrIEtxoqQ30vv5D5v+2CtHbxgH9+0MdrrOISEqpRglznkMgd+EjAYPgkjjIDBAtYF/GseYZFEvE6AJWohYj5a5oV/g2ayPIom8kmETbLQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(82310400026)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; 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On 10/04/2026 11:36, Mykola Kvach wrote: > From: Mykola Kvach > > The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. > > Per IHI0048B.b section 2.3.1, clearing IRQBypDisGrp{0,1} and > FIQBypDisGrp{0,1} selects bypass rather than deasserted interrupt > outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 > show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs > instead of fully disabling the interface. > > Fix this by reading GICC_CTLR, setting the bypass-disable bits, and > clearing both group-enable bits before writing the value back. Keep the > existing GICC_CTL_ENABLE definition for the init path and use a separate > mask for the shutdown-side group-enable handling. IIUC we don't need to worry about not setting the bypass-disable bits in cpu init (we only set group 0 and EOI) because they are relevant only when the bit 0 is disabled i.e. the path this patch changes? > > Section 2.3.2 also states that wakeup event signals remain available > even when both GIC interrupt signaling and interrupt bypass are > disabled, so disabling bypass does not break the power-management use > case, i.e. suspend modes. > > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > Signed-off-by: Mykola Kvach Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 20 08:49:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 08:49:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285539.1566541 (Exim 4.92) (envelope-from ) id 1wEkK9-0003VN-1U; Mon, 20 Apr 2026 08:49:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285539.1566541; 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Yes, and that is actually really important for performance. That's why Alex and I came up with the idea of using the resize able BAR feature to access all of VRAM on modern GPUs. There are a couple of hacks which have been implemented over the years for exotic platforms were MMIO/VRAM access was problematic. For example on a page fault you use a GPU DMA engine to copy the VRAM buffer into system memory, make the CPU memory access and then copy it back again on demand at the next command submission. But all of those hacks are basically just prove of concepts and result in completely unusable performance. > Are any of the following reasonable options? > > 1. Change the guest kernel to only map (and thus pin) a small subset > of VRAM at any given time. If unmapped VRAM is accessed the guest > traps the page fault, evicts an old VRAM mapping, and creates a > new one. Yeah, that could potentially work. This is basically what we do on the host kernel driver when we can't resize the BAR for some reason. In that use case VRAM buffers are shuffled in and out of the CPU accessible window of VRAM on demand. > 2. Pretend that resizable BAR is not enabled, so the guest doesn't > think it can map much of VRAM at once. If resizable BAR is enabled > on the host, it might be possible to split the large BAR mapping > in a lot of ways. That won't work. The userspace parts of the driver stack don't care how large the BAR to access VRAM with the CPU is. The expectation is that the kernel driver makes thing CPU accessible as needed in the page fault handler. It is still a good idea for your solution #1 to give the amount of "pin-able" VRAM to the userspace stack as CPU visible VRAM limit so that test cases and applications try to lower their usage of VRAM, e.g. use system memory bounce buffers when possible. > Or does Xen really need to allow the host to handle guest page faults? > That adds a huge amount of complexity to trusted and security-critical > parts of the system, so it really is a last resort. Putting the > complexity in to the guest virtio-GPU driver is vastly preferable if > it can be made to work well. Well the nested page fault handling KVM offers has proven to be extremely useful. So when XEN can't do this it is clearly lacking an important feature. But I have one question: When XEN has a problem handling faults from the guest on the host then how does that work for system memory mappings? There is really no difference between VRAM and system memory in the handling for the GPU driver stack. Regards, Christian. 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776677909; x=1776938409; i=julian.vetter@vates.tech; bh=QE5mUC97O9np+hjQ/d+sTOK0LSQ1Hp/wQ2SjgL069Qk=; h=From:Subject:To:Cc:Message-Id:Feedback-ID:Date:MIME-Version: Content-Type:Content-Transfer-Encoding:CC:Date:Subject:From; b=MuNphuZzYgliH+3rPVvCBNynLpLIH9FzUO0S2pkiQEn1iHVNuI/AFsVUpk/iQxn2e LfSIJnCnxuh+6VQAiWfVRhoOTEHCTaXYzEJRGM+ORNa0N6HmiIRE6ayXImrq5r7fxc r6G+wuoDxftfM7faO3qklULSN8d7NQoUrtTO5Hn6LTVbLxxX1HkAjEie4lqWzs740m tX3rDWgCh57uVQL4mJi2SWEael0DHeiw1PpeUXwOSBfLrFgUs5HAHgkDOffgfJrGv8 ne1BgGZ672vcPiqKiDrI4SpIDH7Vp1q/TGrhCdMdfCXIvOTkl9TUyzkloEk3x2G3MS d4o1Cs4Vz20jg== From: "Julian Vetter" Subject: =?utf-8?Q?[PATCH=20v6=200/3]=20Support=20multiple=20ioreq=20pages?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776677908510 To: xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Julian Vetter" Message-Id: <20260420093820.825969-1-julian.vetter@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.2562406edfd4437cb382af627caa7011?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 09:38:29 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776677911-80C788B7-73BFD4C6/0/0 X-purgate-type: clean X-purgate-size: 1241 Hello Jan, thank you again for your thorough feedback. I have addressed your comments. I just have one remaining issue. For the temporary MFNs array I now use a static array, i.e., mfns[IOREQ_NR_PAGES_MAX], with a IOREQ_NR_PAGES_MAX = DIV_ROUND_UP(HVM_MAX_VCPUS, PAGE_SIZE / sizeof(ioreq_t)). Is this appropriate? Or should I leave the HVM_MAX_VCPUS out of this and instead use a fixed constant value? Also for now I haven't taken the path to permanently store the MFNs as you suggested. I'm not sure, but I don't think it's really necessary. Since this array will rarely exceed the size of 2 or 3. Signed-off-by: Julian Vetter --- Julian Vetter (3): ioreq: switch ioreq page allocation to vmap ioreq: Indent ioreq_server_alloc_mfn() body one level deeper x86/ioreq: Extend ioreq server to support multiple ioreq pages xen/arch/x86/hvm/ioreq.c | 63 ++++++++++++++++--- xen/common/ioreq.c | 127 ++++++++++++++++++++++++++------------- xen/include/xen/ioreq.h | 13 +++- 3 files changed, 151 insertions(+), 52 deletions(-) -- 2.53.0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 09:38:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 09:38:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285559.1566561 (Exim 4.92) (envelope-from ) id 1wEl5P-0001Qy-PL; Mon, 20 Apr 2026 09:38:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285559.1566561; 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Mon, 20 Apr 2026 11:38:33 +0200 Received: from mta004-md-usw2.delv.a.intuit.com (localhost [127.0.0.1]) by mail137-11.atl71.mandrillapp.com (Mailchimp) with ESMTP id 4fzgQv3Wr5zDRT7yQ for ; Mon, 20 Apr 2026 09:38:31 +0000 (UTC) Received: from [37.26.189.201] by mandrillapp.com id 52cc267a23d34b12b2a72cd81a0c3c36; Mon, 20 Apr 2026 09:38:31 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="julian.vetter@vates.tech" header.h="From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776677911; x=1776947911; bh=gSN+dG6DEEzuWv6g//ewPcup5z/eGaDyrl5RwIr2Dy4=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=BQ+eryZrCpEcJoM3E9l+lkBeQzs8Xp8zfqBe/TEfywfJFmnMU95BYvr44mIIb4ajO YR3ONlllI3vTjxGUmCB5lHiVUyaG68fQvZKEOtAam//COjgAZcm8btxHVapng8Iktq pWhT/IxNGiFMLuBNNP7eKPZBRp9HuacLGiCLAKCYsFY0MtNFeH0Q2wFy+I5j1B4ZuL 2gGIp18EG+HeQ9BY3yVzaoXVIZbDEB1IuMc+ZOcJp54qW6Dk6MOsqVI2/E9aVqzBUn UKh2kvA9CINu/PvyTLsqcLExVECbDj4E3vcIOszjs6OSgxm0/iRb7qGe34Wx/ZC5aS rsLct+WyO3TWw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776677911; x=1776938411; i=julian.vetter@vates.tech; bh=gSN+dG6DEEzuWv6g//ewPcup5z/eGaDyrl5RwIr2Dy4=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Pd8dOW1Xn9C5vBAXW2NBwKw9bIiJU3AMDc80V2pFkPxST9r+Bwh4Kzdv/oeWPgGx6 8te7ePDA0cD7EQpk8zg5/J+fVvkje9l5KiGqoUQNwFI+zv4Tgiu9sXyqdSoR8QVdar MMeZMrvUhXe4dHsWicCuNZvPOlhkwu1kUOKO0P2di4qUJuJYFfIBq7eMeGfJ+3C+y9 inJRBV2TwURIbm7tRfK9UV2K1E+NBl8GjJ+IAiDFSjobxjQGGJVuT15yq7bX+dnlcx jEOMmJhiCDGybPk/VYSDb4jghGJeIgggiKDFTUBtaB2bcvp77QC77oOhONbsh5MErG jkA8MHCLIM4MA== From: "Julian Vetter" Subject: =?utf-8?Q?[PATCH=20v6=201/3]=20ioreq:=20switch=20ioreq=20page=20allocation=20to=20vmap?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776677910519 To: xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Julian Vetter" Message-Id: <20260420093820.825969-2-julian.vetter@vates.tech> In-Reply-To: <20260420093820.825969-1-julian.vetter@vates.tech> References: <20260420093820.825969-1-julian.vetter@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.52cc267a23d34b12b2a72cd81a0c3c36?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 09:38:31 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776677913-E1FDA443-9C96E951/0/0 X-purgate-type: clean X-purgate-size: 8541 Switch the Xen-side ioreq page mapping from prepare_ring_for_helper() / map_domain_page_global() to explicit vmap(), to ensure vmap_to_page() can recover the struct page_info * uniformly during teardown. This is a prerequisite for multi-page ioreq support: the non-buf ioreq region will need to span multiple pages for domains with more vCPUs than fit in a single page, and vmap() is the natural interface for contiguous multi-page Xen VA mappings. In non-debug builds map_domain_page_global() uses the directmap for low MFNs rather than vmap(), so this change has a small overhead in the common case. Debug builds already used vmap() indirectly. With both paths using vmap(), vmap_to_page() can recover the struct page_info * uniformly, so drop the 'page' field from struct ioreq_page and update all callers accordingly. Signed-off-by: Julian Vetter --- Changes in v6: - Updated commit message to clearly specify why these changes are made - Added comment to say that this is {prepare,destroy}_ring_for_helper() just using vmap_to_page() + v{map,unmap}() - Kept proper ordering in ioreq_server_free_mfn(), first clearing the va pointer before unmapping --- xen/arch/x86/hvm/ioreq.c | 55 +++++++++++++++++++++++++++++++++------- xen/common/ioreq.c | 34 +++++++++++++------------ xen/include/xen/ioreq.h | 1 - 3 files changed, 64 insertions(+), 26 deletions(-) diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index a5fa97e149..3cabec141c 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -128,8 +129,13 @@ static void hvm_unmap_ioreq_gfn(struct ioreq_server *s, bool buf) if ( gfn_eq(iorp->gfn, INVALID_GFN) ) return; - destroy_ring_for_helper(&iorp->va, iorp->page); - iorp->page = NULL; + /* Equivalent to destroy_ring_for_helper(), using vmap_to_page(). */ + if ( iorp->va ) + { + put_page_and_type(vmap_to_page(iorp->va)); + vunmap(iorp->va); + iorp->va = NULL; + } hvm_free_ioreq_gfn(s, iorp->gfn); iorp->gfn = INVALID_GFN; @@ -139,9 +145,12 @@ static int hvm_map_ioreq_gfn(struct ioreq_server *s, bool buf) { struct domain *d = s->target; struct ioreq_page *iorp = buf ? &s->bufioreq : &s->ioreq; + struct page_info *page; + p2m_type_t p2mt; + mfn_t mfn; int rc; - if ( iorp->page ) + if ( iorp->va ) { /* * If a page has already been allocated (which will happen on @@ -162,12 +171,40 @@ static int hvm_map_ioreq_gfn(struct ioreq_server *s, bool buf) if ( gfn_eq(iorp->gfn, INVALID_GFN) ) return -ENOMEM; - rc = prepare_ring_for_helper(d, gfn_x(iorp->gfn), &iorp->page, - &iorp->va); - + /* + * Equivalent to prepare_ring_for_helper() using vmap(). Using vmap() + * rather than map_domain_page_global() ensures vmap_to_page() can + * recover the struct page_info * uniformly at teardown, which is + * needed to support multi-page ioreq mappings (see nr_ioreq_pages()). + */ + rc = check_get_page_from_gfn(d, iorp->gfn, false, &p2mt, &page); if ( rc ) - hvm_unmap_ioreq_gfn(s, buf); + { + if ( rc == -EAGAIN ) + rc = -ENOENT; + goto fail; + } + + if ( !get_page_type(page, PGT_writable_page) ) + { + put_page(page); + rc = -EINVAL; + goto fail; + } + + mfn = page_to_mfn(page); + iorp->va = vmap(&mfn, 1); + if ( !iorp->va ) + { + put_page_and_type(page); + rc = -ENOMEM; + goto fail; + } + + return 0; + fail: + hvm_unmap_ioreq_gfn(s, buf); return rc; } @@ -179,7 +216,7 @@ static void hvm_remove_ioreq_gfn(struct ioreq_server *s, bool buf) if ( gfn_eq(iorp->gfn, INVALID_GFN) ) return; - if ( p2m_remove_page(d, iorp->gfn, page_to_mfn(iorp->page), 0) ) + if ( p2m_remove_page(d, iorp->gfn, vmap_to_mfn(iorp->va), 0) ) domain_crash(d); clear_page(iorp->va); } @@ -195,7 +232,7 @@ static int hvm_add_ioreq_gfn(struct ioreq_server *s, bool buf) clear_page(iorp->va); - rc = p2m_add_page(d, iorp->gfn, page_to_mfn(iorp->page), 0, p2m_ram_rw); + rc = p2m_add_page(d, iorp->gfn, vmap_to_mfn(iorp->va), 0, p2m_ram_rw); if ( rc == 0 ) paging_mark_pfn_dirty(d, _pfn(gfn_x(iorp->gfn))); diff --git a/xen/common/ioreq.c b/xen/common/ioreq.c index f5fd30ce12..d8d02167b4 100644 --- a/xen/common/ioreq.c +++ b/xen/common/ioreq.c @@ -17,11 +17,11 @@ */ #include -#include #include #include #include #include +#include #include #include #include @@ -262,8 +262,9 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) { struct ioreq_page *iorp = buf ? &s->bufioreq : &s->ioreq; struct page_info *page; + mfn_t mfn; - if ( iorp->page ) + if ( iorp->va ) { /* * If a guest frame has already been mapped (which may happen @@ -291,11 +292,11 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) return -ENODATA; } - iorp->va = __map_domain_page_global(page); + mfn = page_to_mfn(page); + iorp->va = vmap(&mfn, 1); if ( !iorp->va ) goto fail; - iorp->page = page; clear_page(iorp->va); return 0; @@ -309,15 +310,16 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) static void ioreq_server_free_mfn(struct ioreq_server *s, bool buf) { struct ioreq_page *iorp = buf ? &s->bufioreq : &s->ioreq; - struct page_info *page = iorp->page; + struct page_info *page; + void *va; - if ( !page ) + if ( !iorp->va ) return; - iorp->page = NULL; - - unmap_domain_page_global(iorp->va); + va = iorp->va; + page = vmap_to_page(va); iorp->va = NULL; + vunmap(va); put_page_alloc_ref(page); put_page_and_type(page); @@ -333,7 +335,8 @@ bool is_ioreq_server_page(struct domain *d, const struct page_info *page) FOR_EACH_IOREQ_SERVER(d, id, s) { - if ( (s->ioreq.page == page) || (s->bufioreq.page == page) ) + if ( (s->ioreq.va && vmap_to_page(s->ioreq.va) == page) || + (s->bufioreq.va && vmap_to_page(s->bufioreq.va) == page) ) { found = true; break; @@ -627,10 +630,9 @@ static void ioreq_server_deinit(struct ioreq_server *s) * NOTE: It is safe to call both arch_ioreq_server_unmap_pages() and * ioreq_server_free_pages() in that order. * This is because the former will do nothing if the pages - * are not mapped, leaving the page to be freed by the latter. - * However if the pages are mapped then the former will set - * the page_info pointer to NULL, meaning the latter will do - * nothing. + * are not mapped, leaving the pages to be freed by the latter. + * However if the pages are mapped then the former will clear + * iorp->va, meaning the latter will do nothing. */ arch_ioreq_server_unmap_pages(s); ioreq_server_free_pages(s); @@ -819,12 +821,12 @@ int ioreq_server_get_frame(struct domain *d, ioservid_t id, if ( !HANDLE_BUFIOREQ(s) ) goto out; - *mfn = page_to_mfn(s->bufioreq.page); + *mfn = vmap_to_mfn(s->bufioreq.va); rc = 0; break; case XENMEM_resource_ioreq_server_frame_ioreq(0): - *mfn = page_to_mfn(s->ioreq.page); + *mfn = vmap_to_mfn(s->ioreq.va); rc = 0; break; diff --git a/xen/include/xen/ioreq.h b/xen/include/xen/ioreq.h index e86f0869fa..d63fa4729e 100644 --- a/xen/include/xen/ioreq.h +++ b/xen/include/xen/ioreq.h @@ -25,7 +25,6 @@ struct ioreq_page { gfn_t gfn; - struct page_info *page; void *va; }; -- 2.53.0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 09:38:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 09:38:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285561.1566578 (Exim 4.92) (envelope-from ) id 1wEl5S-0001re-71; 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bh=DH2Rgk3UV3w32Q7m6Ik6auoISiJxaMmJr2fSdyVJpEU=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=VpAhtjFnsEXe2d0hFm7nzdC098AexlXl2cXGfDV9piBTNpb+Ybb9ZE7wITOkILo4x qfrGsd6jpVbF8U8HwJ8a58xM6nHSdFHyyilCtL5VRmvQHQ+w7zTSnDDYtbEtoCLfMT Lf6o0cWN1iezd5M7PckORfhl1WS2zAwq/kB2QNY9asKQDbw2yQvcbmxilzu63HualS juy9nRU0q6sUcy60/Y2DmnvXguKEg7rg34P7ndYH7BkTscYbCrr2RoXIGMtzdo7QxC cOuf5aY0+zvrjHTdgg9uoHixcUgplnKmRpjhvpdH4N2ztgPr+wXPn3ftDI00wpEKtK cgxXsrS+Zdgxg== From: "Julian Vetter" Subject: =?utf-8?Q?[PATCH=20v6=203/3]=20x86/ioreq:=20Extend=20ioreq=20server=20to=20support=20multiple=20ioreq=20pages?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776677911153 To: xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Julian Vetter" Message-Id: <20260420093820.825969-4-julian.vetter@vates.tech> In-Reply-To: <20260420093820.825969-1-julian.vetter@vates.tech> References: <20260420093820.825969-1-julian.vetter@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.638eba881eec477b9b9f3a94f3b2a7b1?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 09:38:32 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776677915-E97A6443-096F3498/0/0 X-purgate-type: clean X-purgate-size: 8014 As the number of vCPUs grows, a single ioreq page of 128 slots may not be sufficient. Add support for allocating and mapping multiple ioreq pages so that the ioreq region can scale with d->max_vcpus. Introduce nr_ioreq_pages() to compute the number of pages required for a given domain, and IOREQ_NR_PAGES_MAX as a compile-time upper bound (based on HVM_MAX_VCPUS). ioreq_server_alloc_mfn() is updated to allocate nr_ioreq_pages() pages and map them contiguously via vmap(). is_ioreq_server_page() iterates over all ioreq pages when checking page ownership. ioreq_server_get_frame() allows callers to retrieve any ioreq page by index via the XENMEM_acquire_resource interface. On x86, the legacy GFN mapping path (hvm_map_ioreq_gfn) is limited to a single ioreq page; device models requiring more ioreq slots must use the resource mapping interface (XENMEM_acquire_resource). Signed-off-by: Julian Vetter --- Changes in v6: - Adapted the comment to not mention the guest, but the device model - Replaced the dynamic allocation for the mfns array by a static array - Fixed error handling in ioreq_server_alloc_mfn, using an extra nr_alloc variable to track the already allocated pages - Dropped unnecessary void casts --- xen/arch/x86/hvm/ioreq.c | 8 ++++ xen/common/ioreq.c | 93 ++++++++++++++++++++++++++++------------ xen/include/xen/ioreq.h | 12 ++++++ 3 files changed, 86 insertions(+), 27 deletions(-) diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index 3cabec141c..ee679bdf5a 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -166,6 +166,14 @@ static int hvm_map_ioreq_gfn(struct ioreq_server *s, bool buf) if ( d->is_dying ) return -EINVAL; + /* + * The legacy GFN path supports only a single ioreq page. Device models + * requiring more ioreq slots must use the resource mapping interface + * (XENMEM_acquire_resource). + */ + if ( !buf && nr_ioreq_pages(d) > 1 ) + return -EOPNOTSUPP; + iorp->gfn = hvm_alloc_ioreq_gfn(s); if ( gfn_eq(iorp->gfn, INVALID_GFN) ) diff --git a/xen/common/ioreq.c b/xen/common/ioreq.c index bae9b99c99..3a08e77597 100644 --- a/xen/common/ioreq.c +++ b/xen/common/ioreq.c @@ -261,8 +261,11 @@ bool vcpu_ioreq_handle_completion(struct vcpu *v) static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) { struct ioreq_page *iorp = buf ? &s->bufioreq : &s->ioreq; - struct page_info *page; - mfn_t mfn; + unsigned int i, nr_alloc = 0, nr_pages = buf ? 1 : nr_ioreq_pages(s->target); + mfn_t mfns[IOREQ_NR_PAGES_MAX] = {}; + int rc; + + ASSERT(nr_pages <= IOREQ_NR_PAGES_MAX); if ( iorp->va ) { @@ -277,11 +280,16 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) return 0; } + for ( i = 0; i < nr_pages; i++ ) { - page = alloc_domheap_page(s->target, MEMF_no_refcount); + struct page_info *page = alloc_domheap_page(s->target, + MEMF_no_refcount); if ( !page ) - return -ENOMEM; + { + rc = -ENOMEM; + goto fail; + } if ( !get_page_and_type(page, s->target, PGT_writable_page) ) { @@ -290,41 +298,59 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) * here is a clear indication of something fishy going on. */ domain_crash(s->emulator); - return -ENODATA; + rc = -ENODATA; + goto fail; } - mfn = page_to_mfn(page); + mfns[nr_alloc++] = page_to_mfn(page); } - iorp->va = vmap(&mfn, 1); + + iorp->va = vmap(mfns, nr_pages); if ( !iorp->va ) + { + rc = -ENOMEM; goto fail; + } - clear_page(iorp->va); + memset(iorp->va, 0, nr_pages * PAGE_SIZE); return 0; fail: - put_page_alloc_ref(page); - put_page_and_type(page); + while ( nr_alloc-- ) + { + struct page_info *page = mfn_to_page(mfns[nr_alloc]); + + put_page_alloc_ref(page); + put_page_and_type(page); + } - return -ENOMEM; + return rc; } static void ioreq_server_free_mfn(struct ioreq_server *s, bool buf) { struct ioreq_page *iorp = buf ? &s->bufioreq : &s->ioreq; - struct page_info *page; + unsigned int i, nr_pages = buf ? 1 : nr_ioreq_pages(s->target); + struct page_info *pages[IOREQ_NR_PAGES_MAX]; void *va; if ( !iorp->va ) return; + ASSERT(nr_pages <= IOREQ_NR_PAGES_MAX); + + for ( i = 0; i < nr_pages; i++ ) + pages[i] = vmap_to_page(iorp->va + i * PAGE_SIZE); + va = iorp->va; - page = vmap_to_page(va); iorp->va = NULL; vunmap(va); - put_page_alloc_ref(page); - put_page_and_type(page); + for ( i = 0; i < nr_pages; i++ ) + { + put_page_alloc_ref(pages[i]); + put_page_and_type(pages[i]); + } } bool is_ioreq_server_page(struct domain *d, const struct page_info *page) @@ -337,12 +363,25 @@ bool is_ioreq_server_page(struct domain *d, const struct page_info *page) FOR_EACH_IOREQ_SERVER(d, id, s) { - if ( (s->ioreq.va && vmap_to_page(s->ioreq.va) == page) || - (s->bufioreq.va && vmap_to_page(s->bufioreq.va) == page) ) + unsigned int i; + + if ( s->bufioreq.va && vmap_to_page(s->bufioreq.va) == page ) { found = true; break; } + + for ( i = 0; i < nr_ioreq_pages(d) && s->ioreq.va; i++ ) + { + if ( vmap_to_page(s->ioreq.va + i * PAGE_SIZE) == page ) + { + found = true; + break; + } + } + + if ( found ) + break; } rspin_unlock(&d->ioreq_server.lock); @@ -816,26 +855,26 @@ int ioreq_server_get_frame(struct domain *d, ioservid_t id, if ( rc ) goto out; - switch ( idx ) + if ( idx == XENMEM_resource_ioreq_server_frame_bufioreq ) { - case XENMEM_resource_ioreq_server_frame_bufioreq: rc = -ENOENT; if ( !HANDLE_BUFIOREQ(s) ) goto out; *mfn = vmap_to_mfn(s->bufioreq.va); rc = 0; - break; + } + else if ( idx >= XENMEM_resource_ioreq_server_frame_ioreq(0) && + idx < XENMEM_resource_ioreq_server_frame_ioreq(nr_ioreq_pages(d)) ) + { + unsigned int page_idx = idx - XENMEM_resource_ioreq_server_frame_ioreq(0); - case XENMEM_resource_ioreq_server_frame_ioreq(0): - *mfn = vmap_to_mfn(s->ioreq.va); + ASSERT(page_idx < nr_ioreq_pages(d)); + *mfn = vmap_to_mfn(s->ioreq.va + page_idx * PAGE_SIZE); rc = 0; - break; - - default: - rc = -EINVAL; - break; } + else + rc = -EINVAL; out: rspin_unlock(&d->ioreq_server.lock); diff --git a/xen/include/xen/ioreq.h b/xen/include/xen/ioreq.h index d63fa4729e..d2a08c2371 100644 --- a/xen/include/xen/ioreq.h +++ b/xen/include/xen/ioreq.h @@ -35,6 +35,18 @@ struct ioreq_vcpu { bool pending; }; +/* + * Maximum number of ioreq pages, based on the maximum number + * of vCPUs and the number of ioreq slots per page. + */ +#define IOREQ_NR_PAGES_MAX \ + DIV_ROUND_UP(HVM_MAX_VCPUS, PAGE_SIZE / sizeof(ioreq_t)) + +static inline unsigned int nr_ioreq_pages(const struct domain *d) +{ + return DIV_ROUND_UP(d->max_vcpus, PAGE_SIZE / sizeof(ioreq_t)); +} + #define NR_IO_RANGE_TYPES (XEN_DMOP_IO_RANGE_PCI + 1) #define MAX_NR_IO_RANGES 256 -- 2.53.0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 09:38:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 09:38:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285560.1566566 (Exim 4.92) (envelope-from ) id 1wEl5Q-0001U4-2X; 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bh=p8k8y/LVlfkSFjIR489TVlpP2VQjBt8UHcDivsfmOkw=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=LSrYyx9lvLEY21z6LWF+iTyIQN0zpSkPpNPVmTxU1nNGiEms/5FndmcrIPjEInsZf y64yshv2KBL3VP7Vx3WI1S+LY/DPxO6aDd82a0IOHMJmpvT1wqaK2vuf3fZ0DfWgLt TgEnR0K2hKHNE5jVooEnj5pf0lpgff9nGiMeE2KeZgmULK0kC/sGLtWmPZ8eq74UPX K2Lq4H2wGpIgTe6/GIf19lJrMZNIB0pMQtfhzJuI0RRwR6rim5C1yTTgGip39EiyEM k2rJzBVzJb034p09dzd0TVYmIC5D5qXZ0ZxoYp8zTaiSB+KF43qOW5nbg6mlPSTZkA 85/8OCBHdKTIg== From: "Julian Vetter" Subject: =?utf-8?Q?[PATCH=20v6=202/3]=20ioreq:=20Indent=20ioreq=5Fserver=5Falloc=5Fmfn()=20body=20one=20level=20deeper?= X-Mailer: git-send-email 2.53.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776677910895 To: xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Julian Vetter" Message-Id: <20260420093820.825969-3-julian.vetter@vates.tech> In-Reply-To: <20260420093820.825969-1-julian.vetter@vates.tech> References: <20260420093820.825969-1-julian.vetter@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.2e3c03ff03de4943839f2f7b526ff987?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 09:38:31 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776677913-471728B7-98452ACF/0/0 X-purgate-type: clean X-purgate-size: 1965 No functional change. It adds a wrapping block to prepare for the loop that the subsequent patch introduces to handle multiple ioreq pages. Signed-off-by: Julian Vetter --- Changes in v6: - Dropped the indentation change for ioreq_server_free_mfn, because the modifications in the next patch don't really merit the change anymore --- xen/common/ioreq.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/xen/common/ioreq.c b/xen/common/ioreq.c index d8d02167b4..bae9b99c99 100644 --- a/xen/common/ioreq.c +++ b/xen/common/ioreq.c @@ -277,22 +277,24 @@ static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) return 0; } - page = alloc_domheap_page(s->target, MEMF_no_refcount); + { + page = alloc_domheap_page(s->target, MEMF_no_refcount); - if ( !page ) - return -ENOMEM; + if ( !page ) + return -ENOMEM; - if ( !get_page_and_type(page, s->target, PGT_writable_page) ) - { - /* - * The domain can't possibly know about this page yet, so failure - * here is a clear indication of something fishy going on. - */ - domain_crash(s->emulator); - return -ENODATA; - } + if ( !get_page_and_type(page, s->target, PGT_writable_page) ) + { + /* + * The domain can't possibly know about this page yet, so failure + * here is a clear indication of something fishy going on. + */ + domain_crash(s->emulator); + return -ENODATA; + } - mfn = page_to_mfn(page); + mfn = page_to_mfn(page); + } iorp->va = vmap(&mfn, 1); if ( !iorp->va ) goto fail; -- 2.53.0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 10:05:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 10:05:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285602.1566592 (Exim 4.92) (envelope-from ) id 1wElVg-0006px-Fp; Mon, 20 Apr 2026 10:05:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285602.1566592; Mon, 20 Apr 2026 10:05:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wElVg-0006pq-CA; Mon, 20 Apr 2026 10:05:44 +0000 Received: by outflank-mailman (input) for mailman id 1285602; Mon, 20 Apr 2026 10:05:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wElVf-0006pk-F6 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 10:05:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wElVe-003FMC-Ns for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 12:05:42 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e5fa71-bab6-0a2a0a5309dd-0a2a4506a47c-26 for ; Mon, 20 Apr 2026 12:05:42 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e5fa76-7371-0a2a45060019-d1558033d801-3 for ; Mon, 20 Apr 2026 12:05:42 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso6796945e9.2 for ; Mon, 20 Apr 2026 03:05:42 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260420093820.825969-1-julian.vetter@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776679542-91985D75-A50AC07D/0/0 X-purgate-type: clean X-purgate-size: 1113 On 20.04.2026 11:38, Julian Vetter wrote: > Hello Jan, > thank you again for your thorough feedback. I have addressed your > comments. I just have one remaining issue. For the temporary MFNs array > I now use a static array, i.e., mfns[IOREQ_NR_PAGES_MAX], with a > IOREQ_NR_PAGES_MAX = DIV_ROUND_UP(HVM_MAX_VCPUS, PAGE_SIZE / sizeof(ioreq_t)). > Is this appropriate? Whether using a static array is appropriate I can't tell after merely having read this cover letter. > Or should I leave the HVM_MAX_VCPUS out of this and > instead use a fixed constant value? Also for now I haven't taken the > path to permanently store the MFNs as you suggested. I'm not sure, but I > don't think it's really necessary. Since this array will rarely exceed > the size of 2 or 3. How do you know? The array will need to be large enough to cope with anything the hypervisor was configured for. Until we actually raise the vCPU-s limit, using HVM_MAX_VCPUS for the size calculation looks okay to me. All uses of that constant will need looking at / adjusting anyway during that subsequent effort. Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 10:25:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 10:25:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285612.1566599 (Exim 4.92) (envelope-from ) id 1wEloY-0001Cf-Td; Mon, 20 Apr 2026 10:25:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285612.1566599; Mon, 20 Apr 2026 10:25:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEloY-0001CY-R7; Mon, 20 Apr 2026 10:25:14 +0000 Received: by outflank-mailman (input) for mailman id 1285612; Mon, 20 Apr 2026 10:25:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEloX-0001CS-Sx for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 10:25:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEloW-007tTu-MI for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 12:25:12 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e5ff06-e002-0a2a0a5209dd-0a2a4506ac7c-24 for ; Mon, 20 Apr 2026 12:25:12 +0200 Received: from [209.85.167.47] (helo=mail-lf1-f47.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e5ff08-7371-0a2a45060019-d155a72fd143-3 for ; Mon, 20 Apr 2026 12:25:12 +0200 Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5a283c44478so4906742e87.3 for ; Mon, 20 Apr 2026 03:25:12 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Why would the virtual >>> one's properties have to match that of the physical one? >> >> It is because of how vAPLIC emulation load and store is working. > > Thank you very much. This fully explains things, the more that of course > emulation of loads and stores comes earlier in this series. Oleksii, > really, please. Sorry for that. Let me add some extra details where I think that pointer to physical APLIC regs are needed. When APLIC tries to access TARGET register it is necessary to update real APLIC as inside this register it is coded information about Hart index, Guest Index (guest interrupt file id) and EIID (External Interrupt Identity). So to do that vintc should have access to physical APLIC registers. The similar things I expected to be with some of other register, for example, that one which are stands for turning on/of interrupts (SETIE, CLRIE). If vAPLIC is requesting an enablement of an interrupt then I expect that correspondent physical APLIC register should be updated too as otherwise how then device interrupt will start to occur. So again it is needed a pointer to physical APLIC to access these registers. Does it make sense at least a little bit now? > >>>> --- /dev/null >>>> +++ b/xen/arch/riscv/vaplic.c >>>> @@ -0,0 +1,74 @@ >>>> +/* SPDX-License-Identifier: MIT */ >>>> +/* >>>> + * xen/arch/riscv/vaplic.c >>>> + * >>>> + * Virtual RISC-V Advanced Platform-Level Interrupt Controller support >>>> + * >>>> + * Copyright (c) Microchip. >>>> + * Copyright (c) Vates >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +#include "aplic-priv.h" >>>> + >>>> +static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >>>> +{ >>>> + int rc = 0; >>>> + >>>> + rc = vcpu_imsic_init(v); >>>> + if ( rc ) >>>> + return rc; >>>> + >>>> + imsic_set_guest_file_id(v, vgein_assign(v)); >>> >>> And vgein_assign() can't fail? (Rhetorical question - of course it can. That >>> function shouldn't assert that it can fine a valid ID.) >> >> Technically it can't fail (except some bug of course), this function >> should in general return 0 (when there aren't left h/w IDs) > > Which is "failure". > >> or something > 0 (when there are some h/w IDs). > > Which is "success". > >> ASSERT() inside it was added only >> because of ... >> >>> But then - aren't you limiting the number of vCPU-s a host can handle by the >>> number vgein IDs? >> >> ... At the moment, I am limiting because S/W interrutps guest files >> (IDs) aren't supported. > > As before - return error codes when errors occur. I will return error code on the caller side of vgein_assign() if it returns 0. > >>>> +static struct vintc * __init vaplic_alloc(void) >>>> +{ >>>> + struct vaplic *v = NULL; >>> >>> Onve again - why the initializer? In fact, ... >>> >>>> + v = xvzalloc(struct vaplic); >>> >>> ... this could be the initializer. >> >> Sure, I will use it as initializer. >> >>> >>>> + if ( !v ) >>>> + return NULL; >>>> + >>>> + return &v->base; >>>> +} >>> >>> If you returned and ... >>> >>>> +int __init domain_vaplic_init(struct domain *d) >>>> +{ >>>> + int ret = 0; >>>> + >>>> + d->arch.vintc = vaplic_alloc(); >>> >>> ... stored struct vaplic *, the slightly odd to_vaplic() macro wouldn't >>> be needed. >> >> vaplic_alloc() return struct vintc *, > > Which is what I'm putting under question. Why would a function of this name > return anything else than struct vaplic *? Agree, this function could return struct vaplic *. I will do that. > >> which is then used by to_vaplic() >> to get struct vaplic *. > > And which is what I'm saying can be avoided. 'struct vintc *vintc;' is still needed in arch_domain struct as it is needed to call vintc->ops->... in the case like during vCPU creation: if ( (rc = v->domain->arch.vintc->ops->vcpu_init(v)) ) goto fail; And then if 'struct vintc *vintc;' is still present in arch_domain struct to_vaplic() is still needed in domain_vaplic_deinit(struct domain *d) function to get struct vaplic *. (All it is true for other vAPLIC functions which take as an argument struct domain). > >>>> + if ( !d->arch.vintc ) >>>> + { >>>> + ret = -ENOMEM; >>>> + goto fail; >>> >>> Nit: goto when simply return could be used. >>> >>>> + } >>>> + >>>> + d->arch.vintc->ops = &vaplic_ops; >>> >>> Are other kinds of ops structures going to appear? If not, why the extra >>> indirection? >> >> At the moment, no I don't see any other kinds of ops struct. It was just >> convenient way to group them and then easier to initialize them - just >> one assignment instead of addinng a separate line in domain_vaplic_init(). > > Maybe I wasn't as clear as I should have been: Why the indirection when it > doesn't abstract anything? I.e. why the "ops" field in the first place, > when everyone could access the global (until such time that abstraction > becomes necessary)? It isn't really needed now. I can just embed ops into vintc explicitly without grouping them into structure. Except the case if we want to have 'vintc_ops *ops;' field in arch_domain structure and separately 'void *vintc;' (which futhure could be casted to struct vaplic *) to drop fully to_vaplic() macros. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 10:47:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 10:47:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285667.1566785 (Exim 4.92) (envelope-from ) id 1wEmAN-0005bj-D0; Mon, 20 Apr 2026 10:47:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285667.1566785; Mon, 20 Apr 2026 10:47:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEmAN-0005bc-AA; Mon, 20 Apr 2026 10:47:47 +0000 Received: by outflank-mailman (input) for mailman id 1285667; Mon, 20 Apr 2026 10:47:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEmAL-0005bV-Hs for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 10:47:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEmAK-00HXRL-Fp for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 12:47:44 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e60446-e002-0a2a0a5209dd-0a2a4506cea2-48 for ; Mon, 20 Apr 2026 12:47:44 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e60450-7371-0a2a45060019-d1558035cd91-3 for ; Mon, 20 Apr 2026 12:47:44 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-48896199cbaso30702775e9.1 for ; Mon, 20 Apr 2026 03:47:44 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776682064-91985D75-80A83D7F/0/0 X-purgate-type: clean X-purgate-size: 1966 On 20.04.2026 12:25, Oleksii Kurochko wrote: > On 4/16/26 2:42 PM, Jan Beulich wrote: >> On 14.04.2026 12:27, Oleksii Kurochko wrote: >>> On 4/2/26 1:58 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> @@ -47,6 +48,19 @@ struct intc_hw_operations { >>>>> const struct dt_device_node *intc); >>>>> }; >>>>> + >>>>> +struct vintc { >>>>> + const struct intc_info *info; >>>> >>>> Isn't this referencing a physical INTC's structure? Why would the virtual >>>> one's properties have to match that of the physical one? >>> >>> It is because of how vAPLIC emulation load and store is working. >> >> Thank you very much. This fully explains things, the more that of course >> emulation of loads and stores comes earlier in this series. Oleksii, >> really, please. > > Sorry for that. Let me add some extra details where I think that pointer > to physical APLIC regs are needed. > > When APLIC tries to access TARGET register it is necessary to update > real APLIC as inside this register it is coded information about Hart > index, Guest Index (guest interrupt file id) and EIID (External > Interrupt Identity). So to do that vintc should have access to physical > APLIC registers. > > The similar things I expected to be with some of other register, for > example, that one which are stands for turning on/of interrupts (SETIE, > CLRIE). If vAPLIC is requesting an enablement of an interrupt then I > expect that correspondent physical APLIC register should be updated too > as otherwise how then device interrupt will start to occur. So again it > is needed a pointer to physical APLIC to access these registers. > > Does it make sense at least a little bit now? Yes. Just that there's a "but": I can't spot any use of the field in this patch. Hence I still can't say whether I actually agree. Introduce the field when it's actually needed? Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 11:39:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 11:39:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285679.1566794 (Exim 4.92) (envelope-from ) id 1wEmyG-0003DU-1p; Mon, 20 Apr 2026 11:39:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285679.1566794; Mon, 20 Apr 2026 11:39:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEmyF-0003DN-Uo; Mon, 20 Apr 2026 11:39:19 +0000 Received: by outflank-mailman (input) for mailman id 1285679; Mon, 20 Apr 2026 11:39:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEmyD-0003DH-SE for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 11:39:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEmyC-008Anl-PA for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:39:16 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e61064-5cb7-0a2a0a5109dd-0a2a4504a77e-0 for ; Mon, 20 Apr 2026 13:39:16 +0200 Received: from [209.85.167.42] (helo=mail-lf1-f42.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e61064-1dec-0a2a45040019-d155a72aec71-3 for ; Mon, 20 Apr 2026 13:39:16 +0200 Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-5a3d1561e38so2480556e87.0 for ; Mon, 20 Apr 2026 04:39:16 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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*/ >>> >>> Counter question: Why ... >>> >>>> +/* >>>> + * Retrieves the interrupts configuration from a device tree node and maps >>>> + * those interrupts to the target domain. >>>> + * >>>> + * Returns: >>>> + * < 0 error >>>> + * 0 success >>>> + */ >>>> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >>>> + bool need_mapping, >>>> + struct rangeset *irq_ranges); >>> >>> ... is this not an inline function, when ... >>> >>>> --- a/xen/arch/riscv/intc.c >>>> +++ b/xen/arch/riscv/intc.c >>>> @@ -79,3 +79,11 @@ int __init intc_make_domu_dt_node(const struct kernel_info *kinfo) >>>> >>>> return -ENOSYS; >>>> } >>>> + >>>> +int map_device_irqs_to_domain(struct domain *d, struct dt_device_node *dev, >>>> + bool need_mapping, >>>> + struct rangeset *irq_ranges) >>>> +{ >>>> + return d->arch.vintc->ops->map_device_irqs_to_domain(d, dev, need_mapping, >>>> + irq_ranges); >>>> +} >>> >>> ... it's merely a wrapper around an indirect function call? And then the >>> function isn't used anywhere anyway. >> >> It is used by dom0less common code and it is a wrapper because Arm has >> different implementation and Arm doesn't have >> map_device_irqs_to_domain() in its virtual interrupt controller operations. > > But the question wasn't why this is a wrapper, but why this wrapper isn't an > inline function. Got you, it could be really inline. > >>>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>>> + struct dt_device_node *dev, >>>> + bool need_mapping, >>>> + struct rangeset *irq_ranges) >>>> +{ >>>> + unsigned int i, nirq; >>>> + int res, irq; >>>> + struct dt_raw_irq rirq; >>>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>>> + unsigned int reg_num; >>>> + >>>> + nirq = dt_number_of_irq(dev); >>>> + >>>> + /* Give permission and map IRQs */ >>>> + for ( i = 0; i < nirq; i++ ) >>>> + { >>>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>>> + if ( res ) >>>> + { >>>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>>> + i, dt_node_full_name(dev)); >>>> + return res; >>>> + } >>>> + >>>> + /* >>>> + * Don't map IRQ that have no physical meaning >>>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>>> + */ >>>> + if ( rirq.controller != dt_interrupt_controller ) >>>> + { >>>> + dt_dprintk("irq %u not connected to primary controller." >>>> + "Connected to %s\n", i, >>>> + dt_node_full_name(rirq.controller)); >>>> + continue; >>>> + } >>>> + >>>> + irq = platform_get_irq(dev, i); >>>> + if ( irq < 0 ) >>>> + { >>>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>>> + return irq; >>>> + } >>>> + >>>> + res = irq_permit_access(d, irq); >>>> + if ( res ) >>>> + { >>>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>>> + irq); >>> >>> This time the other way around: %d please with plain int. (Again at least >>> once further down.) >>> >>>> + return res; >>>> + } >>>> + >>>> + reg_num = irq / APLIC_NUM_REGS; >>>> + >>>> + if ( is_irq_shared_among_domains(d, irq) ) >>>> + { >>>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>>> + return -EINVAL; >>>> + } >>>> + >>>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >>> >>> ... all of this leaves me with the impression that IRQ numbering isn't really >>> virtualized. IRQs are merely split into groups, one group per domain (and >>> maybe some unused). How are you going to fit in truly virtual IRQs? >> >> What do you mean by truly virtual IRQs? > > Ones where no aspects are represented by any piece of hardware. > >> I can't totally agree that the current approach isn't use virtual IRQs, >> yes, they are 1:1 mapped but on the other side Xen is responsible to >> give an IRQ number for guest's device and Xen is responsible that guest >> isn't trying to reach IRQ which not belongs to it. > > In a non-virtualized environment I expect IRQs are going to be "sparse" > (i.e. with perhaps large blocks of items used elsewhere). If you had > proper translation of IRQ numbers, the same could be true for your > guests. Partial FDT, which is used to tell which device be passthroughed to guest, is using physical IRQ number (which I am just considering for simplicity to be 1:1 mapped to virtual IRQ number). So if we have the following configuration: Physical (bare-metal) IRQ layout is sparse: IRQ 5 → UART -> domU0 IRQ 23 → Ethernet -> domU1 IRQ 47 → PCIe -> domU0 IRQ 100 → Storage -> domU1 (gaps everywhere, driven by hardware wiring) For such configuration we will have for each domain auth_irq_bmp[] which contains: IRQ 5 and IRQ47 for domU0 and IRQ 23 and IRQ 100 for domU1 And here vIRQ5 = pIRQ5, vIRQ47 = pIRQ47 and so on. auth_irq_bmp just transform xIRQ number to bit position which it will have in real APLIC register. Just as an example, lets take vIRQ5 and vIRQ47. As reading or writing register setie[k] reads or potentially modifies the enable bits for interrupt sources k × 32 through k × 32 + 31. For an implemented interrupt source i within that range, the enable bit for source i corresponds with register bit (i mod 32). So for: - vIRQ5 == pIRQ5 we have to set bit 5 in setie[0] - vIRQ47 == pIRQ47 we have to set bit 15 in setie[1] Probably it was not the best idea to declare auth_irq_bmp as it will look in h/w and maybe just 'bool auth_irq_bmp[1024]' would be more clearer. So irqs number are still stay "sparsed" in guest. > >>>> + dt_dprintk(" - IRQ: %u\n", irq); >>>> + >>>> + if ( irq_ranges ) >>>> + { >>>> + res = rangeset_add_singleton(irq_ranges, irq); >>>> + if ( res ) >>>> + return res; >>>> + } >>> >>> What is irq_ranges? >> >> IIUC based on Arm code irq_ranges is an optional output accumulator, the >> caller allocates and passes it in when it needs to track which IRQs were >> mapped (overlay use case), or passes NULL when that tracking is not needed. >> >> I added here as map_device_irqs_to_domain() is called from the common >> code and so maybe one day someone will decide to pass irq_ranges to this >> functions. At the moment, for RISC-V it is the only one user of >> map_device_irqs_to_domain() and it passes NULL. > > Simply assert then that it's NULL? Won't BUG_ON() be better here as it BUG_ON() macros is always defined and doesn't matter if release or debug build are used. Or maybe you meant: if ( irq_ranges ) assert_failed("irq_ranges arg isn't supported\n"); > >>>> @@ -34,6 +142,7 @@ static int __init cf_check vcpu_vaplic_init(struct vcpu *v) >>>> >>>> static const struct vintc_ops vaplic_ops = { >>>> .vcpu_init = vcpu_vaplic_init, >>>> + .map_device_irqs_to_domain = vaplic_map_device_irqs_to_domain, >>>> }; >>> >>> What about the inverse function, needed for domain cleanup? >> >> I planned to add it when it will be really needed. At the momemnt, I >> don't have such use cases. > > I.e. if any domain needs re-starting, the entire system needs rebooting? > Recall that "dom0less" is slightly misleading a name, as it only allows > there to not be a Dom0. One can be there, and hence re-starting a crashed > domain ought to be possible. For that, you need to correctly clean up > after the crashed one. I haven't investigated yet what will be code path to do a reboot or re-start crashed domain but based on an implementation of vaplic_map_device_irqs_to_domain() as nothing is allocated there and filling of auth_irq_bmp[] is happening there which will stay the same after reboot if it is just re-used or it will be allocated new one if crashed domain will just recreate this domain from scratch. So it seems like it is enough to have only map_device_irqs_to_domain(). ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 11:42:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 11:42:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285690.1566802 (Exim 4.92) (envelope-from ) id 1wEn1L-0004mc-HV; Mon, 20 Apr 2026 11:42:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285690.1566802; Mon, 20 Apr 2026 11:42:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEn1L-0004mV-Er; Mon, 20 Apr 2026 11:42:31 +0000 Received: by outflank-mailman (input) for mailman id 1285690; Mon, 20 Apr 2026 11:42:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEn1K-0004mP-Iw for xen-devel@lists.xenproject.org; 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Tables 2-2 and 2-3 > show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs > instead of fully disabling the interface. >=20 > Fix this by reading GICC_CTLR, setting the bypass-disable bits, and > clearing both group-enable bits before writing the value back. Keep the > existing GICC_CTL_ENABLE definition for the init path and use a separate > mask for the shutdown-side group-enable handling. >=20 > Section 2.3.2 also states that wakeup event signals remain available > even when both GIC interrupt signaling and interrupt bypass are > disabled, so disabling bypass does not break the power-management use > case, i.e. suspend modes. >=20 > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > Signed-off-by: Mykola Kvach > --- > xen/arch/arm/gic-v2.c | 7 ++++++- > xen/arch/arm/include/asm/gic.h | 21 +++++++++++++++++++-- > 2 files changed, 25 insertions(+), 3 deletions(-) >=20 > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > index b23e72a3d0..22aa25bad0 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -408,7 +408,12 @@ static void gicv2_cpu_init(void) >=20 > static void gicv2_cpu_disable(void) > { > - writel_gicc(0x0, GICC_CTLR); > + uint32_t ctlr =3D readl_gicc(GICC_CTLR); > + > + ctlr |=3D GICC_CTL_BYP_DIS_MASK; If the GIC v2 implementation includes the Security Extensions, the bit 7-8 are reserved, but now we are unconditionally writing on them. Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 20 11:53:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 11:53:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285720.1566900 (Exim 4.92) (envelope-from ) id 1wEnBr-0007C6-BE; Mon, 20 Apr 2026 11:53:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285720.1566900; Mon, 20 Apr 2026 11:53:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEnBr-0007Bz-7w; Mon, 20 Apr 2026 11:53:23 +0000 Received: by outflank-mailman (input) for mailman id 1285720; Mon, 20 Apr 2026 11:53:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEnBq-0007Br-Ps for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 11:53:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEnBp-00D9Ea-N3 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:53:21 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e613a8-5cb7-0a2a0a5109dd-0a2a450ab26a-8 for ; Mon, 20 Apr 2026 13:53:21 +0200 Received: from [209.85.167.45] (helo=mail-lf1-f45.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e613b1-56b3-0a2a450a0019-d155a72da9b0-3 for ; Mon, 20 Apr 2026 13:53:21 +0200 Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-5a413f83226so3500098e87.1 for ; Mon, 20 Apr 2026 04:53:21 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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How can you ... >>> >>>> --- a/xen/arch/riscv/vaplic.c >>>> +++ b/xen/arch/riscv/vaplic.c >>>> @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >>>> return 0; >>>> } >>>> >>>> +static int cf_check vaplic_is_access(const struct vcpu *vcpu, >>>> + const unsigned long addr) >>>> +{ >>>> + const struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>>> + const struct aplic_priv *priv = vaplic->base.info->private; >>>> + const paddr_t paddr_end = priv->paddr_start + priv->size; >>>> + >>>> + /* check if it is an APLIC access */ >>>> + if ( priv->paddr_start <= addr && addr < paddr_end ) >>> >>> ... use that here? Or asked differently, again: Where's the virtualization, >>> i.e. the abstraction away from host properties? >> >> With the current use case it was easier to choose such approach then >> provide the full abstraction. >> >>> Furthermore, is it really sufficient to check just the starting address of >>> an access? Shouldn't the last byte accessed also fall into the range in >>> question? >> >> I think that it is okay, my understanding is that *paddr_end technically >> is another range. > > Of course it is. But a multi-byte access crossing the paddr_end boundary > isn't purely an APLIC one. You can reject such for simplicity, but I'm > unconvinced that you can claim you will be able to correctly handle it > without proper merging. Lets say guest has the following description of vAPLIC in its DTB: aplic@d000000 { phandle = <0x06>; riscv,num-sources = <0x60>; reg = <0x00 0xd000000 0x00 0x8000>; ... } What means vAPLIC's MMIO range is [0xd000000, 0xD007FFF]. If some is trying to access 0xd008000 it is not an MMIO address which belongs to vAPLIC so vaplic_is_access() should return 0. IIUC, you concern is that if someone will try to access 0xD007FFF which from this function point of view is legal. I think it is okay to return here 1 what tells that this address is from our vAPLIC range as it will be rejected that on vaplic_emulate_{load,store}() side as addr (more accurate offset got from addr) should be properly aligned: const unsigned int offset = addr & APLIC_REG_OFFSET_MASK; ... if ( offset & 3 ) { gdprintk(XENLOG_WARNING, "Misaligned APLIC access at offset %#x\n", offset); return -EINVAL; } Is it okay? Actually I think we could add ( addr & 3 ) check in vaplic_is_access() function too... ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 12:04:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 12:04:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285734.1566908 (Exim 4.92) (envelope-from ) id 1wEnM4-0000ZV-DA; Mon, 20 Apr 2026 12:03:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285734.1566908; Mon, 20 Apr 2026 12:03:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEnM4-0000ZO-9r; Mon, 20 Apr 2026 12:03:56 +0000 Received: by outflank-mailman (input) for mailman id 1285734; Mon, 20 Apr 2026 12:03:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEnM3-0000ZI-Ev for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 12:03:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEnM2-008GoQ-7I for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:03:54 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e61623-2eae-0a2a0a5409dd-0a2a4501d6f4-18 for ; Mon, 20 Apr 2026 14:03:54 +0200 Received: from [209.85.221.45] (helo=mail-wr1-f45.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e61629-c1f2-0a2a45010019-d155dd2dad8e-3 for ; Mon, 20 Apr 2026 14:03:53 +0200 Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-43cfd832155so2132498f8f.1 for ; Mon, 20 Apr 2026 05:03:53 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776686633-B7A79FF4-04704912/0/0 X-purgate-type: clean X-purgate-size: 3328 On 20.04.2026 13:53, Oleksii Kurochko wrote: > > > On 4/16/26 3:01 PM, Jan Beulich wrote: >> On 14.04.2026 13:45, Oleksii Kurochko wrote: >>> On 4/2/26 3:10 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> --- a/xen/arch/riscv/aplic.c >>>>> +++ b/xen/arch/riscv/aplic.c >>>>> @@ -38,6 +38,7 @@ static struct aplic_priv aplic = { >>>>> >>>>> static struct intc_info __ro_after_init aplic_info = { >>>>> .hw_version = INTC_APLIC, >>>>> + .private = &aplic, >>>> >>>> Isn't this the host instance again? How can you ... >>>> >>>>> --- a/xen/arch/riscv/vaplic.c >>>>> +++ b/xen/arch/riscv/vaplic.c >>>>> @@ -127,6 +127,20 @@ int vaplic_map_device_irqs_to_domain(struct domain *d, >>>>> return 0; >>>>> } >>>>> >>>>> +static int cf_check vaplic_is_access(const struct vcpu *vcpu, >>>>> + const unsigned long addr) >>>>> +{ >>>>> + const struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>>>> + const struct aplic_priv *priv = vaplic->base.info->private; >>>>> + const paddr_t paddr_end = priv->paddr_start + priv->size; >>>>> + >>>>> + /* check if it is an APLIC access */ >>>>> + if ( priv->paddr_start <= addr && addr < paddr_end ) >>>> >>>> ... use that here? Or asked differently, again: Where's the virtualization, >>>> i.e. the abstraction away from host properties? >>> >>> With the current use case it was easier to choose such approach then >>> provide the full abstraction. >>> >>>> Furthermore, is it really sufficient to check just the starting address of >>>> an access? Shouldn't the last byte accessed also fall into the range in >>>> question? >>> >>> I think that it is okay, my understanding is that *paddr_end technically >>> is another range. >> >> Of course it is. But a multi-byte access crossing the paddr_end boundary >> isn't purely an APLIC one. You can reject such for simplicity, but I'm >> unconvinced that you can claim you will be able to correctly handle it >> without proper merging. > > Lets say guest has the following description of vAPLIC in its DTB: > aplic@d000000 { > phandle = <0x06>; > riscv,num-sources = <0x60>; > reg = <0x00 0xd000000 0x00 0x8000>; > ... > } > What means vAPLIC's MMIO range is [0xd000000, 0xD007FFF]. If some is > trying to access 0xd008000 it is not an MMIO address which belongs to > vAPLIC so vaplic_is_access() should return 0. > > IIUC, you concern is that if someone will try to access 0xD007FFF which > from this function point of view is legal. I think it is okay to return > here 1 what tells that this address is from our vAPLIC range as it will > be rejected that on vaplic_emulate_{load,store}() side as addr (more > accurate offset got from addr) should be properly aligned: > const unsigned int offset = addr & APLIC_REG_OFFSET_MASK; > ... > if ( offset & 3 ) > { > gdprintk(XENLOG_WARNING, "Misaligned APLIC access at offset %#x\n", > offset); > return -EINVAL; > } > > Is it okay? Actually I think we could add ( addr & 3 ) check in > vaplic_is_access() function too... Perhaps best. The load/store functions could then simply assert that property. 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Mon, 20 Apr 2026 05:19:35 -0700 (PDT) Message-ID: Date: Mon, 20 Apr 2026 14:19:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC] xen/swiotlb: avoid arch_sync_dma_* on per-device DMA memory To: "Peng Fan (OSS)" , Stefano Stabellini , Oleksandr Tyshchenko Cc: xen-devel@lists.xenproject.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Peng Fan References: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------034tgJUdS8obTrCAMQuKOO5H" X-purgate-ID: tlsNG-ef75cf/1776687576-1585EC48-5F5CF2C9/0/0 X-purgate-type: clean X-purgate-size: 8412 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------034tgJUdS8obTrCAMQuKOO5H Content-Type: multipart/mixed; boundary="------------xAm466dmUFDzKs0FzPVhHxO0"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: "Peng Fan (OSS)" , Stefano Stabellini , Oleksandr Tyshchenko Cc: xen-devel@lists.xenproject.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Peng Fan Message-ID: Subject: Re: [PATCH RFC] xen/swiotlb: avoid arch_sync_dma_* on per-device DMA memory References: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> In-Reply-To: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> --------------xAm466dmUFDzKs0FzPVhHxO0 Content-Type: multipart/mixed; boundary="------------y5RAGzWBaBlt2a08ULXbC0V9" --------------y5RAGzWBaBlt2a08ULXbC0V9 Content-Type: text/plain; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7ea3a5d8-f9ff-4296-9b3e-07b9ba184e6f@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776688100-2AB633FF-CE5717FF/0/0 X-purgate-type: clean X-purgate-size: 253 On 07.04.2026 13:27, Stewart Hildebrand wrote: > I think the patch is good as is, but I just want to give it a few more days to > give Nate or others a chance to chime in. I'll follow up next week if there's no > further discussion. Ping. Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 12:50:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 12:50:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285784.1567024 (Exim 4.92) (envelope-from ) id 1wEo4b-0007hC-SL; Mon, 20 Apr 2026 12:49:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285784.1567024; Mon, 20 Apr 2026 12:49:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEo4b-0007h5-Ou; Mon, 20 Apr 2026 12:49:57 +0000 Received: by outflank-mailman (input) for mailman id 1285784; Mon, 20 Apr 2026 12:49:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEo4a-0007gz-Fi for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 12:49:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEo4Z-0004Q8-CA for xen-devel@lists.xenproject.org; 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dkim=pass header.s=mte1 header.d=mandrillapp.com header.i="@mandrillapp.com" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding"; dkim=pass header.s=mte1 header.d=vates.tech header.i="teddy.astie@vates.tech" header.h="From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID:Date:MIME-Version:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1776689393; x=1776959393; bh=c8iYYSuvv2dPJJ3UYz3BOeX/wQvSA1vuYJkQLpFfBZI=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=aE+rCooCHezqAMIS1CJIiW4LdvGSEAHAStYY7neoVNYWbUUXsRacXZIwEv4kGet9C Mabn0NEI+oqzHZf3zy+EN2iDxxHGDYuVOuiP5eU1qZanWo+b9GkUT5auIYjwvIfKWa fHljvypRrZvxDerFeq8CCjKfJGCI7osPQODlfy8+Azd3LPk0aA4zWNkcrDAbcd86rZ DeIJ0u/sNdTISgBMD0dNYloGJWqs+BMtWEv8lsFKwZOrmYdIaVr7P9jNAHkGgEY69Y UxkqsewML4RGCfwDrTHypqGtq3ZdFqGUUmmsJnS4UzAV22oKTsBeO9m/CkoEoz9OqJ GzbDs48GZR2aQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1776689393; x=1776949893; i=teddy.astie@vates.tech; bh=c8iYYSuvv2dPJJ3UYz3BOeX/wQvSA1vuYJkQLpFfBZI=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=B2VYh0i+Oe9aaektlvVKuKNuqY8aBEW5vr0aFzbMDqo9mBBMH1LqPK7kM8SoXRHDW uxN1D8SPBEmGznr6L21nglt3rePbMo43YcscjwXZMd2FtNt3T003HF+Ya4f8hXu2Fh L46SaqQV6lsrMHYor8KWQ0QztnDWlqXoIrXnL24JtgTG3+NnCPaI8m/T05Vol3LIHG r/yM/JLGbdOdjeackJ4ok+CxKEIIMTsbUXw2ABq/opa+FrRIGo+8GLUBKZYwOKqH2k EMOEPKIC0JZVLgXUCQ7O2VlQFHw3xH4+H1raQwJZ2bc9L4pc0hq3VYy74kznl4d7Fk LkwGqxOPFAdow== From: "Teddy Astie" Subject: =?utf-8?Q?Re:=20[PATCH=20v6=203/3]=20x86/ioreq:=20Extend=20ioreq=20server=20to=20support=20multiple=20ioreq=20pages?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776689391815 Message-Id: To: "Julian Vetter" , xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" References: <20260420093820.825969-1-julian.vetter@vates.tech> <20260420093820.825969-4-julian.vetter@vates.tech> In-Reply-To: <20260420093820.825969-4-julian.vetter@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.884f9eb010b443899f2b5441430958da?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 12:49:53 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1776689395-2A175443-44D4807A/0/0 X-purgate-type: clean X-purgate-size: 9306 Le 20/04/2026 =C3=A0 11:41, Julian Vetter a =C3=A9crit=C2=A0: > As the number of vCPUs grows, a single ioreq page of 128 slots may not > be sufficient. Add support for allocating and mapping multiple ioreq > pages so that the ioreq region can scale with d->max_vcpus. > > Introduce nr_ioreq_pages() to compute the number of pages required for > a given domain, and IOREQ_NR_PAGES_MAX as a compile-time upper bound > (based on HVM_MAX_VCPUS). > > ioreq_server_alloc_mfn() is updated to allocate nr_ioreq_pages() pages > and map them contiguously via vmap(). > > is_ioreq_server_page() iterates over all ioreq pages when checking > page ownership. ioreq_server_get_frame() allows callers to retrieve any > ioreq page by index via the XENMEM_acquire_resource interface. > > On x86, the legacy GFN mapping path (hvm_map_ioreq_gfn) is limited to > a single ioreq page; device models requiring more ioreq slots must use > the resource mapping interface (XENMEM_acquire_resource). > > Signed-off-by: Julian Vetter > --- > Changes in v6: > - Adapted the comment to not mention the guest, but the device model > - Replaced the dynamic allocation for the mfns array by a static array > - Fixed error handling in ioreq_server_alloc_mfn, using an extra > nr_alloc variable to track the already allocated pages > - Dropped unnecessary void casts > --- > xen/arch/x86/hvm/ioreq.c | 8 ++++ > xen/common/ioreq.c | 93 ++++++++++++++++++++++++++++------------ > xen/include/xen/ioreq.h | 12 ++++++ > 3 files changed, 86 insertions(+), 27 deletions(-) > > diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c > index 3cabec141c..ee679bdf5a 100644 > --- a/xen/arch/x86/hvm/ioreq.c > +++ b/xen/arch/x86/hvm/ioreq.c > @@ -166,6 +166,14 @@ static int hvm_map_ioreq_gfn(struct ioreq_server *s,= bool buf) > if ( d->is_dying ) > return -EINVAL; > > + /* > + * The legacy GFN path supports only a single ioreq page. Device mod= els > + * requiring more ioreq slots must use the resource mapping interfac= e > + * (XENMEM_acquire_resource). > + */ > + if ( !buf && nr_ioreq_pages(d) > 1 ) > + return -EOPNOTSUPP; > + > iorp->gfn =3D hvm_alloc_ioreq_gfn(s); > > if ( gfn_eq(iorp->gfn, INVALID_GFN) ) > diff --git a/xen/common/ioreq.c b/xen/common/ioreq.c > index bae9b99c99..3a08e77597 100644 > --- a/xen/common/ioreq.c > +++ b/xen/common/ioreq.c > @@ -261,8 +261,11 @@ bool vcpu_ioreq_handle_completion(struct vcpu *v) > static int ioreq_server_alloc_mfn(struct ioreq_server *s, bool buf) > { > struct ioreq_page *iorp =3D buf ? &s->bufioreq : &s->ioreq; > - struct page_info *page; > - mfn_t mfn; > + unsigned int i, nr_alloc =3D 0, nr_pages =3D buf ? 1 : nr_ioreq_page= s(s->target); > + mfn_t mfns[IOREQ_NR_PAGES_MAX] =3D {}; > + int rc; > + > + ASSERT(nr_pages <=3D IOREQ_NR_PAGES_MAX); > > if ( iorp->va ) > { > @@ -277,11 +280,16 @@ static int ioreq_server_alloc_mfn(struct ioreq_serv= er *s, bool buf) > return 0; > } > > + for ( i =3D 0; i < nr_pages; i++ ) > { > - page =3D alloc_domheap_page(s->target, MEMF_no_refcount); > + struct page_info *page =3D alloc_domheap_page(s->target, > + MEMF_no_refcount); > > if ( !page ) > - return -ENOMEM; > + { > + rc =3D -ENOMEM; > + goto fail; > + } > > if ( !get_page_and_type(page, s->target, PGT_writable_page) ) > { > @@ -290,41 +298,59 @@ static int ioreq_server_alloc_mfn(struct ioreq_serv= er *s, bool buf) > * here is a clear indication of something fishy going on. > */ > domain_crash(s->emulator); > - return -ENODATA; > + rc =3D -ENODATA; > + goto fail; > } > > - mfn =3D page_to_mfn(page); > + mfns[nr_alloc++] =3D page_to_mfn(page); > } > - iorp->va =3D vmap(&mfn, 1); > + > + iorp->va =3D vmap(mfns, nr_pages); > if ( !iorp->va ) > + { > + rc =3D -ENOMEM; > goto fail; > + } > > - clear_page(iorp->va); > + memset(iorp->va, 0, nr_pages * PAGE_SIZE); > return 0; > > fail: > - put_page_alloc_ref(page); > - put_page_and_type(page); > + while ( nr_alloc-- ) > + { > + struct page_info *page =3D mfn_to_page(mfns[nr_alloc]); > + > + put_page_alloc_ref(page); > + put_page_and_type(page); > + } > > - return -ENOMEM; > + return rc; > } > > static void ioreq_server_free_mfn(struct ioreq_server *s, bool buf) > { > struct ioreq_page *iorp =3D buf ? &s->bufioreq : &s->ioreq; > - struct page_info *page; > + unsigned int i, nr_pages =3D buf ? 1 : nr_ioreq_pages(s->target); > + struct page_info *pages[IOREQ_NR_PAGES_MAX]; > void *va; > > if ( !iorp->va ) > return; > > + ASSERT(nr_pages <=3D IOREQ_NR_PAGES_MAX); > + > + for ( i =3D 0; i < nr_pages; i++ ) > + pages[i] =3D vmap_to_page(iorp->va + i * PAGE_SIZE); > + > va =3D iorp->va; > - page =3D vmap_to_page(va); > iorp->va =3D NULL; > vunmap(va); > > - put_page_alloc_ref(page); > - put_page_and_type(page); > + for ( i =3D 0; i < nr_pages; i++ ) > + { > + put_page_alloc_ref(pages[i]); > + put_page_and_type(pages[i]); > + } > } > > bool is_ioreq_server_page(struct domain *d, const struct page_info *pag= e) > @@ -337,12 +363,25 @@ bool is_ioreq_server_page(struct domain *d, const s= truct page_info *page) > > FOR_EACH_IOREQ_SERVER(d, id, s) > { > - if ( (s->ioreq.va && vmap_to_page(s->ioreq.va) =3D=3D page) || > - (s->bufioreq.va && vmap_to_page(s->bufioreq.va) =3D=3D page= ) ) > + unsigned int i; > + > + if ( s->bufioreq.va && vmap_to_page(s->bufioreq.va) =3D=3D page = ) > { > found =3D true; > break; > } > + > + for ( i =3D 0; i < nr_ioreq_pages(d) && s->ioreq.va; i++ ) > + { > + if ( vmap_to_page(s->ioreq.va + i * PAGE_SIZE) =3D=3D page ) > + { > + found =3D true; > + break; > + } > + } > + > + if ( found ) > + break; > } > > rspin_unlock(&d->ioreq_server.lock); > @@ -816,26 +855,26 @@ int ioreq_server_get_frame(struct domain *d, ioserv= id_t id, > if ( rc ) > goto out; > > - switch ( idx ) > + if ( idx =3D=3D XENMEM_resource_ioreq_server_frame_bufioreq ) > { > - case XENMEM_resource_ioreq_server_frame_bufioreq: > rc =3D -ENOENT; > if ( !HANDLE_BUFIOREQ(s) ) > goto out; > > *mfn =3D vmap_to_mfn(s->bufioreq.va); > rc =3D 0; > - break; > + } > + else if ( idx >=3D XENMEM_resource_ioreq_server_frame_ioreq(0) && > + idx < XENMEM_resource_ioreq_server_frame_ioreq(nr_ioreq_pa= ges(d)) ) > + { > + unsigned int page_idx =3D idx - XENMEM_resource_ioreq_server_fra= me_ioreq(0); > > - case XENMEM_resource_ioreq_server_frame_ioreq(0): > - *mfn =3D vmap_to_mfn(s->ioreq.va); > + ASSERT(page_idx < nr_ioreq_pages(d)); > + *mfn =3D vmap_to_mfn(s->ioreq.va + page_idx * PAGE_SIZE); > rc =3D 0; > - break; > - > - default: > - rc =3D -EINVAL; > - break; > } > + else > + rc =3D -EINVAL; > > out: > rspin_unlock(&d->ioreq_server.lock); > diff --git a/xen/include/xen/ioreq.h b/xen/include/xen/ioreq.h > index d63fa4729e..d2a08c2371 100644 > --- a/xen/include/xen/ioreq.h > +++ b/xen/include/xen/ioreq.h > @@ -35,6 +35,18 @@ struct ioreq_vcpu { > bool pending; > }; > > +/* > + * Maximum number of ioreq pages, based on the maximum number > + * of vCPUs and the number of ioreq slots per page. > + */ > +#define IOREQ_NR_PAGES_MAX \ > + DIV_ROUND_UP(HVM_MAX_VCPUS, PAGE_SIZE / sizeof(ioreq_t)) > + > +static inline unsigned int nr_ioreq_pages(const struct domain *d) > +{ > + return DIV_ROUND_UP(d->max_vcpus, PAGE_SIZE / sizeof(ioreq_t)); > +} > + > #define NR_IO_RANGE_TYPES (XEN_DMOP_IO_RANGE_PCI + 1) > #define MAX_NR_IO_RANGES 256 > Is there anything that would prevent the use of alloc_domheap_pages() to allocate a configuous set of pages at once; and vmap_contig() to map it in one go. That also prevents the ioreq pages from being scattered around. We would lose a few pages by aligning the size into a order, but that probably better than the alternatives. That way, we would only have to keep the base gfn (or first page_info) and size of the allocation, and don't have to use a array of mfn nor have to reverse the vmap to track it. Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:21:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:21:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285794.1567033 (Exim 4.92) (envelope-from ) id 1wEoYw-00049a-4Z; Mon, 20 Apr 2026 13:21:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285794.1567033; Mon, 20 Apr 2026 13:21:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEoYw-00049T-1H; Mon, 20 Apr 2026 13:21:18 +0000 Received: by outflank-mailman (input) for mailman id 1285794; Mon, 20 Apr 2026 13:21:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEoYt-00049N-VY for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <8ae3567b-712f-4f0e-9d5c-82a949651b74@amd.com> Date: Mon, 20 Apr 2026 09:21:04 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arinc653: don't assume Dom0 is the control domain To: Jan Beulich CC: Nathan Studer , Stewart Hildebrand , "xen-devel@lists.xenproject.org" , =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= References: <89d17a24-0a1f-4f3f-ac2f-f3701a8d78dd@suse.com> <4a4c011e-9666-4416-be1b-33d1dcad5afe@suse.com> <73e51afc-ae7c-4d08-9054-75dab660bf42@suse.com> <4dfd48a9-37c1-4f28-87f3-19646a339b08@suse.com> <7ea3a5d8-f9ff-4296-9b3e-07b9ba184e6f@amd.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DB:EE_|SN7PR12MB6960:EE_ X-MS-Office365-Filtering-Correlation-Id: a31a10ab-5449-4a3e-edff-08de9edfae4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|30052699003|1800799024|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0P0OfftKNXzcyB8koImd72FNLc/NL52a3QCanlakIPJm5dr5hfk4oMyUbbG+zmWzaIFeJ5R17vOPY+kSUB7aFywrvcnHc6+wSe6c07DlZ1gh4iYcExtd5157F3nRGCjmtO/87TGGVnzxRXUj1yM+/PoiM0PO+liS6KKmBIBkSSiOZn+YLSIeNNp35Lnioy+tNQyzx6/mL3LVS1LZKYLRzZEyLFO5Hx3olmJRg/zQWBEoTHf9EbhdZMThTyfEqpel8/WGu7dAqPxXhbKNacZkMUigf3JpCK3iVONZvkkVAGhduBo2Eu9hrWqlQvF99cMhPlAn0ehswCgtmfcGSwTv/iw5z8SCQs0qppzXEdy3trAngsaZQG+ikz+A7Uvumo6oigxg/VRMG08LAmNrXy5jtVoq97WapHtCJm4XdCyYOnaO6bomcCrZokFE4Gs8msiK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 13:21:07.1903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a31a10ab-5449-4a3e-edff-08de9edfae4c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DB.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6960 X-purgate-ID: tlsNG-d25034/1776691274-6CD63CF5-7AAFDEE1/0/0 X-purgate-type: clean X-purgate-size: 407 On 4/20/26 08:28, Jan Beulich wrote: > On 07.04.2026 13:27, Stewart Hildebrand wrote: >> I think the patch is good as is, but I just want to give it a few more days to >> give Nate or others a chance to chime in. I'll follow up next week if there's no >> further discussion. > > Ping. Thanks. With the patch in its current form: Reviewed-by: Stewart Hildebrand From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:23:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:23:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285803.1567041 (Exim 4.92) (envelope-from ) id 1wEoag-0004ek-FR; Mon, 20 Apr 2026 13:23:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285803.1567041; Mon, 20 Apr 2026 13:23:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEoag-0004ed-Ci; Mon, 20 Apr 2026 13:23:06 +0000 Received: by outflank-mailman (input) for mailman id 1285803; Mon, 20 Apr 2026 13:23:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEoaf-0004eV-BD for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:23:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEoae-003vBn-OK for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:23:04 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e628af-2eae-0a2a0a5409dd-0a2a45018ff6-30 for ; Mon, 20 Apr 2026 15:23:04 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e628b7-c1f2-0a2a45010019-a0658308e3ec-3 for ; Mon, 20 Apr 2026 15:23:04 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id CD100420CEC8; Mon, 20 Apr 2026 09:22:17 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 0/4] xen/mm: Host-side integration test environment for page_alloc.c Date: Mon, 20 Apr 2026 14:19:40 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776691384-BF67FFF4-E02B6EA0/0/0 X-purgate-type: clean X-purgate-size: 4369 Hi all, This patch series introduces a host-side integration test environment for Xen's page allocator in xen/common/page_alloc.c, reduced in size by 60% from 2257 to 1411 new lines with v2. Using this environment, it also introduces integration tests for claims, including NUMA-aware claim sets, complementing the functional system tests submitted as part of the NUMA-aware claims v6 series. The claim tests verify the page allocator's behaviour with multi-node claim sets in scenarios that are easier to isolate and validate using a synthetic Xen heap and domain state, offering full control and visibility into claim states as claims are made and redeemed during heap allocation. For these tests, this series depends on the NUMA claims v6 series, which introduced NUMA-aware claim sets: [PATCH v6 0/7] xen/mm: Introduce NUMA-aware claim sets for domains https://lists.xen.org/archives/html/xen-devel/2026-04/msg00587.html https://patchwork.kernel.org/project/xen-devel/list/?series=1081139 Its design is described in this document: [PATCH v2] docs: Draft Design Document for NUMA-aware claim sets https://lists.xen.org/archives/html/xen-devel/2026-04/msg00569.html https://patchwork.kernel.org/project/xen-devel/list/?series=1081047 Patch summary: 1. tools/tests/alloc: Add a test environment for the page allocator 2. tools/tests/alloc: Add integration tests for claims and claim sets 3. tools/tests/alloc: Add tests for offlining with claims present 4. xen/mm: Recall claims when offlining pages if needed Thanks, Bernhard Kaindl --- Changes since v1: 1. Refactored the test environment for minimalism: - Improved separation of concerns. - Moved extensions to later patch series. - Simplified code with targeted assertions and concise comments. 2. Fixed file names to avoid underscores. 3. Updated include guards to comply with CODING_STYLE. --- PS: The bug fixed in the last commit also affects the global claims in Xen master when offlining pages. While offlining has known limitations, the bug fixed in this series also affects global claims in Xen master when pages are offlined. I will submit a follow-up series to address offlining itself. In the meantime, this test framework enables targeted testing on a synthetic Xen heap and simplifies validation by letting the tests observe heap-state changes during offlining. Bernhard Kaindl (4): tools/tests/alloc: Add Page Allocator Test Environment tools/tests/alloc: Add integration test suite to for NUMA memory claims tools/tests/alloc: Add tests for offlining with claims present xen/mm: Recall claims when offlining pages if needed tools/tests/Makefile | 1 + tools/tests/alloc/.gitignore | 7 + tools/tests/alloc/Makefile | 141 +++++++ tools/tests/alloc/README.rst | 98 +++++ tools/tests/alloc/check-asserts.h | 225 +++++++++++ tools/tests/alloc/harness.h | 57 +++ tools/tests/alloc/hypervisor-macros.h | 95 +++++ tools/tests/alloc/libtest-page-alloc.h | 145 +++++++ tools/tests/alloc/mock-page-list.h | 167 ++++++++ tools/tests/alloc/page-alloc-shim.h | 411 ++++++++++++++++++++ tools/tests/alloc/page-alloc-wrapper.h | 64 +++ tools/tests/alloc/test-claims-basic.c | 108 +++++ tools/tests/alloc/test-claims-numa-redeem.c | 172 ++++++++ tools/tests/alloc/test-offlining-claims.c | 71 ++++ xen/common/page_alloc.c | 42 ++ 15 files changed, 1804 insertions(+) create mode 100644 tools/tests/alloc/.gitignore create mode 100644 tools/tests/alloc/Makefile create mode 100644 tools/tests/alloc/README.rst create mode 100644 tools/tests/alloc/check-asserts.h create mode 100644 tools/tests/alloc/harness.h create mode 100644 tools/tests/alloc/hypervisor-macros.h create mode 100644 tools/tests/alloc/libtest-page-alloc.h create mode 100644 tools/tests/alloc/mock-page-list.h create mode 100644 tools/tests/alloc/page-alloc-shim.h create mode 100644 tools/tests/alloc/page-alloc-wrapper.h create mode 100644 tools/tests/alloc/test-claims-basic.c create mode 100644 tools/tests/alloc/test-claims-numa-redeem.c create mode 100644 tools/tests/alloc/test-offlining-claims.c -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:24:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:24:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285823.1567051 (Exim 4.92) (envelope-from ) id 1wEobZ-0005EJ-TN; Mon, 20 Apr 2026 13:24:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285823.1567051; Mon, 20 Apr 2026 13:24:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEobZ-0005EC-PN; Mon, 20 Apr 2026 13:24:01 +0000 Received: by outflank-mailman (input) for mailman id 1285823; Mon, 20 Apr 2026 13:24:01 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEobY-0005E4-Sq for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:24:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEobW-008KMW-OI for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:24:00 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e628ee-2eae-0a2a0a5409dd-0a2a450b988e-2 for ; Mon, 20 Apr 2026 15:24:00 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e628ef-212f-0a2a450b0019-a0658309e0a6-3 for ; Mon, 20 Apr 2026 15:23:59 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 0F5B78185701; Mon, 20 Apr 2026 09:23:02 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH v2 1/4] tools/tests/alloc: Add Page Allocator Test Environment Date: Mon, 20 Apr 2026 14:19:41 +0100 Message-Id: <3c17deb670d5471f2a5df04084e2a88e62502343.1776690702.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776691440-246B7F3B-55BC0E22/0/0 X-purgate-type: clean X-purgate-size: 56028 Provide a small, self-contained test environment for Xen's page allocator. Instead of reimplementing allocator logic in a model, these tests compile the real allocator code into ordinary host executables and exercise it in a controlled environment with a synthetic Xen heap and domain state. This gives direct visibility into allocator state while keeping the test harness self-contained. This is intended for scenarios that are difficult to cover with system-level testing alone, such as: * inspecting NUMA claims in response to allocator operations * rebuilding buddies after offlining subpages * reproducing edge cases while inspecting heap state during allocation and free operations Signed-off-by: Bernhard Kaindl --- tools/tests/Makefile | 1 + tools/tests/alloc/.gitignore | 7 + tools/tests/alloc/Makefile | 141 +++++++++ tools/tests/alloc/README.rst | 98 ++++++ tools/tests/alloc/check-asserts.h | 225 ++++++++++++++ tools/tests/alloc/harness.h | 57 ++++ tools/tests/alloc/hypervisor-macros.h | 95 ++++++ tools/tests/alloc/libtest-page-alloc.h | 145 +++++++++ tools/tests/alloc/mock-page-list.h | 167 ++++++++++ tools/tests/alloc/page-alloc-shim.h | 411 +++++++++++++++++++++++++ tools/tests/alloc/page-alloc-wrapper.h | 64 ++++ 11 files changed, 1411 insertions(+) create mode 100644 tools/tests/alloc/.gitignore create mode 100644 tools/tests/alloc/Makefile create mode 100644 tools/tests/alloc/README.rst create mode 100644 tools/tests/alloc/check-asserts.h create mode 100644 tools/tests/alloc/harness.h create mode 100644 tools/tests/alloc/hypervisor-macros.h create mode 100644 tools/tests/alloc/libtest-page-alloc.h create mode 100644 tools/tests/alloc/mock-page-list.h create mode 100644 tools/tests/alloc/page-alloc-shim.h create mode 100644 tools/tests/alloc/page-alloc-wrapper.h diff --git a/tools/tests/Makefile b/tools/tests/Makefile index 6477a4386dda..ca3de4c7b54a 100644 --- a/tools/tests/Makefile +++ b/tools/tests/Makefile @@ -2,6 +2,7 @@ XEN_ROOT = $(CURDIR)/../.. include $(XEN_ROOT)/tools/Rules.mk SUBDIRS-y := +SUBDIRS-y += alloc SUBDIRS-y += domid SUBDIRS-y += mem-claim SUBDIRS-y += paging-mempool diff --git a/tools/tests/alloc/.gitignore b/tools/tests/alloc/.gitignore new file mode 100644 index 000000000000..b0597936e234 --- /dev/null +++ b/tools/tests/alloc/.gitignore @@ -0,0 +1,7 @@ +/test-claims-basic +/test-claims-numa-install +/test-claims-numa-redeem +/test-online-page +/test-offlining-claims +/test-reserve-offline-page +/test-unaligned-buddies diff --git a/tools/tests/alloc/Makefile b/tools/tests/alloc/Makefile new file mode 100644 index 000000000000..f5724aa3f699 --- /dev/null +++ b/tools/tests/alloc/Makefile @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Makefile for tools/tests/alloc + +XEN_ROOT := $(abspath $(CURDIR)/../../..) +include $(XEN_ROOT)/tools/Rules.mk +RELDIR := $(subst $(XEN_ROOT)/,,$(CURDIR)) + +TEST_SOURCES := $(notdir $(wildcard test-*.c)) +TARGETS := $(TEST_SOURCES:.c=) + +.PHONY: all +all: $(TARGETS) + +define RUN_TESTS + @echo "Build configuration:" + @echo "CC=$(CC)" + @echo "CFLAGS='$(CFLAGS)'" + @for test in $? ; do \ + echo;echo "$(RELDIR): RUN_TESTS: $$test...";echo; \ + ./$$test ; EXIT_CODE=$$? ; \ + if [ $$EXIT_CODE -ne 0 ]; then \ + echo "Test $$test failed with exit code $$EXIT_CODE"; \ + exit 1; \ + fi; \ + done + @echo + @echo "Tests executed successfully:" + @for test in $? ; do \ + echo " - $$test"; \ + done +endef + +# Run the tests if possible, otherwise print a warning and skip them. +.PHONY: run +# Determine if the tests can be run on the build host. If CC and HOSTCC +# are the same, we can run the tests directly. If they differ, we check +# if binfmt-support and qemu-binfmt are available to run the tests under +# using binfmt-misc using qemu-user-static. +ifeq ($(CC),$(HOSTCC)) + TESTS_RUNNABLE=yes +else + BINFMT_SUPP := $(if $(wildcard /etc/init.d/binfmt-support),1,0) + QEMU_BINFMT := $(if $(wildcard /usr/libexec/qemu-binfmt),1,0) + ifeq ($(BINFMT_SUPP)$(QEMU_BINFMT),11) + # Running static binaries doesn't need extra setup besides qemu-binfmt + CFLAGS += -static + TESTS_RUNNABLE=yes + else + TESTS_RUNNABLE=no + endif +endif + +run: $(TARGETS) +ifeq ($(TESTS_RUNNABLE),yes) + $(RUN_TESTS) +else + $(warning HOSTCC != CC, and qemu-binfmt not detected, skipping alloc tests) +endif + +# Run the tests binfmt-misc set up +BINFMT_SUPP := $(if $(wildcard /etc/init.d/binfmt-support),1,0) +QEMU_BINFMT := $(if $(wildcard /usr/libexec/qemu-binfmt),1,0) +.PHONY: run-tests +run-tests: $(TARGETS) +ifeq ($(CC),$(HOSTCC)) + $(RUN_TESTS) +else ifeq ($(BINFMT_SUPP)$(QEMU_BINFMT),11) + $(RUN_TESTS) +else + $(warning Note: binfmt-support or qemu-user not found, skipping run-tests) +endif + +# +# Build and run the tests for multiple architectures, +# skipping if the appropriate cross-compiler is not found. +# The default XEN_TARGET_ARCH is always built and tested as well. +# This is gcc-specific, but can be adapted for other toolchains. +# +ARCHS := arm64-aarch64-linux-gnu arm32-arm-linux-gnueabihf +ARCHS += x86_32-i686-linux-gnu x86_64-x86_64-linux-gnu +ARCHS += ppc64-powerpc64le-linux-gnu riscv64-riscv64-linux-gnu +.PHONY: run-archs +run-archs: $(TARGETS) +ifneq ($(CC),gcc) + $(warning run-archs target is only supported with CC=gcc for now, skipping) +else + @set -e;PASSES=;SKIPPED_ARCHS=; \ + MAKEFLAGS="$$MAKEFLAGS --no-print-directory"; \ + + for t in $(ARCHS); do \ + A=$${t%%-*}; C=$${t#*-}; \ + [ $$A != $(XEN_TARGET_ARCH) ] || continue; \ + if ! type "$${C}-gcc" >/dev/null 2>&1; then \ + echo " $${C}-gcc not found, skipping $${A}"; \ + SKIPPED_ARCHS="$${SKIPPED_ARCHS} $${A}"; continue; \ + fi; \ + if [ $${A} = $(XEN_TARGET_ARCH) ]; then C=$(CROSS_COMPILE); fi; \ + make XEN_TARGET_ARCH="$${A}" CROSS_COMPILE=$$C- clean run-tests; \ + PASSES="$${PASSES} $${A}"; \ + done;\ + echo "$@ successful for:$${PASSES} $(XEN_TARGET_ARCH)";\ + [ -z "$${SKIPPED_ARCHS}" ] || echo "Skipped architectures:$${SKIPPED_ARCHS}" +endif + +.PHONY: clean +.NOTPARALLEL: clean +clean: + $(RM) -- *.o $(TARGETS) $(DEPS_RM) + +.PHONY: distclean +distclean: clean + $(RM) -- *~ + +.PHONY: install +install: all + $(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests + $(INSTALL_PROG) $(TARGETS) $(DESTDIR)$(LIBEXEC)/tests + +.PHONY: uninstall +uninstall: + $(RM) -- $(patsubst %,$(DESTDIR)$(LIBEXEC)/tests/%,$(TARGETS)) + +# CFLAGS for building the tests +XEN_INCLUDE_ARCH := $(subst x86_64,x86,$(XEN_COMPILE_ARCH)) +CFLAGS += -D__XEN_TOOLS__ +CFLAGS += $(APPEND_CFLAGS) +CFLAGS += -I$(XEN_ROOT)/xen/include +CFLAGS += -I$(XEN_ROOT)/xen/arch/$(XEN_INCLUDE_ARCH)/include +CFLAGS += $(CFLAGS_xeninclude) + +# Enable sanitizers to catch memory errors and undefined behavior in the code +# for x86_64. Other architectures do not support -fstatic with it. +ifeq ($(XEN_TARGET_ARCH),x86_64) +CFLAGS += -fsanitize=address -fsanitize=undefined -fno-common +endif + +# Build rules for the tests +$(TARGETS): %: %.o $(LIB_OBJ) + $(CC) -o $@ $^ $(LDFLAGS) $(CPPFLAGS) $(CFLAGS) $(APPEND_CFLAGS) + +-include $(DEPS_INCLUDE) diff --git a/tools/tests/alloc/README.rst b/tools/tests/alloc/README.rst new file mode 100644 index 000000000000..f91587d7f4b2 --- /dev/null +++ b/tools/tests/alloc/README.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Page Allocator Test Environment +=============================== + +The files in ``tools/tests/alloc`` provide a small, self-contained test +environment for Xen's page allocator in ``xen/common/page_alloc.c``. + +Instead of reimplementing allocator logic in a model, the tests compile +the real allocator code into ordinary host executables and exercise it +inside a controlled environment with a synthetic Xen heap and domain +state and direct visibility into the allocator's internal state. + +This approach is intended for test scenarios that are difficult to cover +through system-level testing alone, such as: + +* rebuilding buddies after offlining subpages, +* checking page-list and zone accounting after allocator operations, +* verifying NUMA-aware allocator behaviour in synthetic topologies, and +* reproducing edge cases with precise control over ``struct page_info`` + state. + +What The Environment Provides +----------------------------- + +The test environment is assembled from a few small components: + +* ``harness.h`` defines the common test harness, assertion helpers, and a + minimal set of Xen-compatible types and macros used by the allocator. + +* ``mock-page-list.h`` provides a lightweight page-list implementation + and the ``struct page_info`` layout needed by ``page_alloc.c``. + +* ``page-alloc-shim.h`` supplies the Xen definitions, stubs, and mock state + that the allocator expects when built inside the test environment. + +* ``page-alloc-wrapper.h`` includes the real ``xen/common/page_alloc.c`` + directly, wraps selected allocator entry points, and adds logging that + makes allocator state transitions easier to follow. + +* ``libtest-page-alloc.h`` ties the pieces together and adds helpers for + common setup tasks such as resetting allocator state, preparing NUMA + nodes, creating synthetic buddies, and checking resulting heap state. + +The result is a test binary that executes real allocator code while keeping +the surrounding test environment small, explicit, and easy to inspect. + +How Tests Work +-------------- + +Each test case starts from a clean allocator state. The library code resets +the imported allocator globals, initialises the synthetic frame table, +prepares the free lists and accounting state, and creates a minimal domain +and NUMA configuration for the scenario. + +Tests then construct the required allocator state directly by manipulating +``struct page_info`` entries in the synthetic frame table and by using the +same allocator helpers that Xen uses at runtime, such as +``free_heap_pages()``. This keeps test setup aligned with allocator +behaviour instead of relying on an idealised model. + +After invoking the allocator operation under test, each test scenario checks +the resulting state through assertion helpers. Typical checks include: + +* the content and order of free lists, +* the contents of the offlined-page and broken-page lists, +* per-zone and per-node accounting, +* buddy order and alignment invariants, and +* page-local state such as ``count_info`` and ``first_dirty``. + +Because the wrapper logs important allocator actions, test failures are +usually accompanied by enough context to show which allocator transition +broke. + +Running The Tests +----------------- + +The ``Makefile`` automatically discovers all ``test-*.c`` files in this +directory and builds one executable per source file. + +To build and run all allocator tests: + +.. code:: shell + + make -C tools/tests/alloc clean all run + +To build and run a single test binary: + +.. code:: shell + + make -C tools/tests/alloc clean all run TARGETS=test-reserve-offline-page + +The ``run`` target executes the built tests when they are runnable on the +build host. If ``CC`` and ``HOSTCC`` differ, it will only attempt execution +when ``binfmt`` support for the target architecture is available. + +For broader coverage, the ``run-archs`` target builds and runs the tests for +multiple Xen target architectures when suitable cross-compilers are installed. diff --git a/tools/tests/alloc/check-asserts.h b/tools/tests/alloc/check-asserts.h new file mode 100644 index 000000000000..fe26de909683 --- /dev/null +++ b/tools/tests/alloc/check-asserts.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Helpers for assertions used by unit tests. + * Copyright (C) 2026 Cloud Software Group + */ + +#ifndef TOOLS_TESTS_ALLOC_CHECK_ASSERTS_H +#define TOOLS_TESTS_ALLOC_CHECK_ASSERTS_H + +#include +#include +#include +#include +#include +#include + +static bool testcase_assert_expected_to_fail = false; +static bool testcase_assert_verbose_assertions = true; +static const char *testcase_assert_current_func = NULL; +static int testcase_assert_verbose_indent_level = 0; +static int testcase_assert_expected_failures = 0; +static int testcase_assert_expected_failures_total = 0; +static int testcase_assert_successful_assert_total = 0; +static void (*testcase_init_func)(int); +#define __used __attribute__((__used__)) +#define assert_failed_str "Assertion failed: " +#define CHECK(condition, fmt, ...) \ + testcase_assert(condition, __FILE__, __LINE__, __func__, fmt, \ + ##__VA_ARGS__) +#define ASSERT(x) \ + testcase_assert(x, __FILE__, __LINE__, __func__, assert_failed_str #x) +#define BUG_ON(x) \ + testcase_assert(!(x), __FILE__, __LINE__, __func__, "BUG_ON: " #x) +#define ASSERT_UNREACHABLE() assert(false) +#define EXPECTED_TO_FAIL_BEGIN() (testcase_assert_expected_to_fail = true) +#define EXPECTED_TO_FAIL_END(c) testcase_assert_check_expected_failures(c) + +static void __used testcase_assert_check_expected_failures(int expected) +{ + if ( testcase_assert_expected_failures != expected ) + { + fprintf(stderr, "Expected %d assertion failures, got %d\n", + expected, testcase_assert_expected_failures); + abort(); + } + testcase_assert_expected_to_fail = false; + testcase_assert_expected_failures = 0; + testcase_assert_expected_failures_total += expected; +} + +static void __used setup_testcase_init_func(void (*init_fn)(int)) +{ + testcase_init_func = init_fn; +} + +__attribute__((format(printf, 5, 6))) +static void testcase_assert(bool condition, const char *file, int line, + const char *func, const char *fmt, ...) +{ + va_list ap; + const char *relpath = file; + + while ( (file = strstr(relpath, "../")) ) + relpath += 3; + + va_start(ap, fmt); + if ( testcase_assert_expected_to_fail ) + { + fprintf(stderr, "\n- Test assertion %s at %s:%d:\n ", + condition ? "unexpectedly passed" : "failed as expected", + relpath, line); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + + if ( condition ) + abort(); /* Unexpected pass, treat as test failure */ + else + testcase_assert_expected_failures++; /* Count for the report. */ + goto out; + } + if ( !condition ) + { + fprintf(stderr, "Test assertion failed at %s:%d: ", relpath, line); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + abort(); + } + testcase_assert_successful_assert_total++; + if ( testcase_assert_verbose_assertions ) + { + if ( strncmp(fmt, assert_failed_str, strlen(assert_failed_str)) == 0 ) + fmt += strlen(assert_failed_str); + + if ( strcmp(fmt, "ret == 0") == 0 ) + goto out; + + for ( int i = 0; i < testcase_assert_verbose_indent_level; i++ ) + printf(" "); + + printf("%s:%d: ", relpath, line); + if ( (testcase_assert_current_func == NULL || + strcmp(testcase_assert_current_func, func)) && + (strncmp(relpath, "test-", strlen("test-")) && + strncmp(func, "test_", strlen("test_"))) ) + printf("%s(): ", func); + + if ( strncmp(fmt, "BUG_ON:", 7) ) + printf("ASSERT("); + + vprintf(fmt, ap); + + if ( strncmp(fmt, "BUG_ON:", 7) ) + printf(")"); + + printf("\n"); + } +out: + va_end(ap); +} + +struct testcase { + const char *name; /* test case name */ + const char *tid; /* Test ID */ + int intarg; /* passed to the test case */ + void (*func)(int); /* Test case function */ + int passed_asserts; /* Number of ASSERTS that passed. */ + int expected_failures; /* Number of XFAILs */ +} testcases[40]; +struct testcase *current_testcase = testcases; + +static void print_testcase_report(struct testcase *tc) +{ + printf("- %-5s %-34s %2d: %3d assertions passed", tc->tid, tc->name, + tc->intarg, tc->passed_asserts); + if ( tc->expected_failures ) + printf(" (%2d XFAIL)", tc->expected_failures); + printf("\n"); +} + +static void run_testcase(void (*case_func)(int), int int_arg, const char *tid, + const char *case_name) +{ + printf("\nTest Case: %s...\n", case_name); + current_testcase->name = case_name; + current_testcase->func = case_func; + current_testcase->intarg = int_arg; + current_testcase->tid = tid; + current_testcase->passed_asserts = 0; + current_testcase->expected_failures = 0; + + if ( testcase_init_func && int_arg >= 0 ) + testcase_init_func(int_arg); + + case_func(int_arg); + + current_testcase->passed_asserts = testcase_assert_successful_assert_total; + current_testcase->expected_failures = + testcase_assert_expected_failures_total; + + testcase_assert_successful_assert_total = 0; + testcase_assert_expected_failures_total = 0; + + printf("\nResults:\n"); + print_testcase_report(current_testcase); + current_testcase++; +} +#define RUN_TESTCASE(tid, func, arg) run_testcase(func, arg, #tid, #func) + +static int testcase_print_summary(const char *argv0) +{ + struct utsname uts; + int total_asserts = 0, expected_failures = 0; + + fprintf(stderr, "\nTest Report:\n"); + + current_testcase = testcases; + for ( size_t i = 0; i < ARRAY_SIZE(testcases) && current_testcase->func; + i++ ) + { + print_testcase_report(current_testcase); + total_asserts += current_testcase->passed_asserts; + expected_failures += current_testcase->expected_failures; + current_testcase++; + } + current_testcase->tid = "Total"; + current_testcase->name = ""; + current_testcase->passed_asserts = total_asserts; + current_testcase->expected_failures = expected_failures; + current_testcase->intarg = current_testcase - testcases; + print_testcase_report(current_testcase); + + uname(&uts); + printf("\nTest suite %s for %s completed.\n", argv0, uts.machine); + return 0; +} + +static const char *parse_args(int argc, char *argv[], const char *topic) +{ + const char *program_name = argv[0]; + struct utsname uts; + + if ( argc != 1 ) + { + fprintf(stderr, "Usage: %s\n", argv[0]); + return NULL; + } + program_name = strrchr(program_name, '/'); + if ( program_name ) + program_name++; + else + program_name = argv[0]; + + uname(&uts); + printf("Suite : %s\n", program_name); + printf("Topic : %s\n", topic); + printf("Config: CONFIG_NUMA %s\n", + config_enabled(CONFIG_NUMA) ? "enabled" : "disabled"); +#ifndef __clang__ + printf("Target: gcc %s/%s\n", __VERSION__, uts.machine); +#else + printf("Target: %s/%s\n", __VERSION__, uts.machine); +#endif + return program_name; +} +#endif diff --git a/tools/tests/alloc/harness.h b/tools/tests/alloc/harness.h new file mode 100644 index 000000000000..e5880cef25cc --- /dev/null +++ b/tools/tests/alloc/harness.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common test harness for page allocation unit tests. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#ifndef TOOLS_TESTS_ALLOC_HARNESS_H +#define TOOLS_TESTS_ALLOC_HARNESS_H + +#include +#include +#include +#include +#include + +/* Enable additional debug checks. */ +#define CONFIG_DEBUG + +/* Common macros compatible with the test environment. */ +#include "hypervisor-macros.h" + +/* Assertion helpers shared by the tests. */ +#include "check-asserts.h" + +/* Common Xen types used by the test environment. */ +typedef uint8_t u8; +typedef uint64_t paddr_t; +typedef unsigned long cpumask_t; +typedef long long s_time_t; +typedef bool spinlock_t; + +/* + * The original reserve_offlined_page() implementation triggers an + * AddressSanitizer (ASAN) stack-buffer-overflow report in both GCC and + * Clang when test_merge_tail_pair runs with ASAN enabled and verifies + * the heap free-list state. + * + * ASAN reports several list-pointer errors in the heap state, and one of + * them appears to trigger the stack-buffer-overflow detection on x86_64. + * + * As a temporary workaround, detect whether ASAN is enabled so the test + * can skip the ASSERT_LIST_EQUAL verification that triggers the report, + * while still running the rest of the case under ASAN. + */ +#if defined(__has_feature) +/* Clang uses __has_feature to detect AddressSanitizer */ +# if __has_feature(address_sanitizer) +# define ASAN_ENABLED 1 +# endif +/* GCC uses __SANITIZE_ADDRESS__ to detect AddressSanitizer */ +#elif defined(__SANITIZE_ADDRESS__) +# define ASAN_ENABLED 1 +#else +# define ASAN_ENABLED 0 +#endif +#endif diff --git a/tools/tests/alloc/hypervisor-macros.h b/tools/tests/alloc/hypervisor-macros.h new file mode 100644 index 000000000000..be59d6dd7df5 --- /dev/null +++ b/tools/tests/alloc/hypervisor-macros.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Common macros and definitions for building host-side unit tests + * for the Xen hypervisor. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#ifndef TOOLS_TESTS_ALLOC_HYPERVISOR_MACROS_H +#define TOOLS_TESTS_ALLOC_HYPERVISOR_MACROS_H + +#include +#include +#include +#include + +/* + * In Xen, STATIC_IF(x) and config_enabled(x) are defined in kconfig.h, + * which cannot be included here. Define the required subset locally. + */ +#define STATIC_IF(option) static_if(option) +#define static_if(value) _static_if(__ARG_PLACEHOLDER_##value) +#define _static_if(arg1_or_junk) ___config_enabled(arg1_or_junk static, ) +#define __ARG_PLACEHOLDER_1 0, +#define config_enabled(cfg) _config_enabled(cfg) +#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value) + +#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0) + +#define ___config_enabled(__ignored, val, ...) val + +/* + * Reuse the Xen-tools macros from common-macros.h. They are not + * necessarily identical to the hypervisor variants, but they are close + * enough for this test environment. + */ +#include + +/* + * Predefine the include guards for Xen headers whose hypervisor + * variants would otherwise conflict with definitions from + * common-macros.h and bitops.h. + */ +#define __XEN_CONST_H__ +#define __MACROS_H__ + +/* + * Provide Xen hypervisor macros used by xen/common/page_alloc.c that + * common-macros.h does not supply, or redefine them where the test + * build must match hypervisor behavior. + */ +#define IS_ALIGNED(x, a) (!((x) & ((a) - 1))) + +/* + * Reuse the Xen-tools bit operations from bitops.h. They are not + * necessarily identical to the hypervisor versions, but they are close + * enough for this test environment. + */ +#include + +/* + * After including Xen-tools bitops.h, redefine ffsl and flsl to match + * Xen hypervisor behavior. Here they return unsigned int, which matters + * for signed/unsigned conversion checks and type expectations. Also + * undefine conflicting macros from the Xen-tools headers. + */ +#undef BITS_PER_LONG +#undef __LITTLE_ENDIAN +#undef __BIG_ENDIAN +#undef ffsl +#define ffsl(x) ((unsigned int)__builtin_ffsl(x)) +#define flsl(x) ((unsigned int)((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0)) + +static bool testcase_assert_expected_to_fail; +__attribute__((format(printf, 5, 6))) +static void testcase_assert(bool condition, const char *file, int line, + const char *func, const char *fmt, ...); +#define BUG() assert(false) +#define domain_crash(d) ((void)(d)) +#define PRI_mfn "lu" +#define PRI_stime "lld" +#define printk printf +#define dprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define gdprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define gprintk(level, fmt, ...) printk(fmt, ##__VA_ARGS__) +#define panic(fmt, ...) \ + do \ + { \ + fprintf(stderr, fmt, ##__VA_ARGS__); \ + abort(); \ + } while ( 0 ) +#define __initdata +#define __init __used +#define __initcall(f) static int __used (*f##_ptr)(void) = (f) +#endif diff --git a/tools/tests/alloc/libtest-page-alloc.h b/tools/tests/alloc/libtest-page-alloc.h new file mode 100644 index 000000000000..2644c87e9c8e --- /dev/null +++ b/tools/tests/alloc/libtest-page-alloc.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Test framework for xen/common/page_alloc.c. + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef TOOLS_TESTS_ALLOC_LIBTEST_PAGE_ALLOC_H +#define TOOLS_TESTS_ALLOC_LIBTEST_PAGE_ALLOC_H + +#pragma GCC diagnostic error "-Wextra" +#include "page-alloc-wrapper.h" +static const unsigned int node = 0; +static const unsigned int node0 = 0; +static const unsigned int node1 = 1; +static const unsigned int order0 = 0; +static const unsigned int order1 = 1; +static const unsigned int order2 = 2; + +static heap_by_zone_and_order_t test_heap_storage[MAX_NUMNODES]; +static unsigned long test_avail_storage[MAX_NUMNODES][NR_ZONES]; +struct domain *domain_list; + +static void init_numa_node_data(unsigned int start_mfn) +{ + (void)start_mfn; +#ifdef CONFIG_NUMA + for ( unsigned int i = 0; i < NR_CPUS; i++ ) + cpu_to_node[i] = i; + + for ( unsigned int i = 0; i < MAX_NUMNODES; i++ ) + node_to_cpumask[i] = (1UL << i); + + for ( unsigned int i = 0; i < MAX_NUMNODES; i++ ) + { + node_data[i].node_start_pfn = start_mfn + (i * 8); + node_data[i].node_present_pages = 8UL; + node_data[i].node_spanned_pages = 8UL; + } + memnode_shift = 3; + for ( unsigned int i = 0; i < 64; i++ ) + memnodemap[i] = (nodeid_t)i; +#endif +} + +static void init_dummy_domains(void) +{ + nodemask_t dom_node_affinity; + struct domain *dom; + int dom_id = 1; + + nodes_clear(dom_node_affinity); + node_set(node0, dom_node_affinity); + node_set(node1, dom_node_affinity); + test_current_vcpu.domain = &test_dummy_domain1; + domain_list = &test_dummy_domain1; + test_dummy_domain1.next_in_list = &test_dummy_domain2; + + for_each_domain ( dom ) + { + dom->node_affinity = dom_node_affinity; + dom->max_pages = MAX_PAGES; + dom->domain_id = dom_id++; + } +} + +static void reset_page_alloc_state(int start_mfn) +{ + unsigned int zone; + unsigned int order; + + memset(frame_table, 0, sizeof(frame_table)); + memset(test_heap_storage, 0, sizeof(test_heap_storage)); + memset(test_avail_storage, 0, sizeof(test_avail_storage)); + memset(&test_dummy_domain1, 0, sizeof(test_dummy_domain1)); + memset(&test_dummy_domain2, 0, sizeof(test_dummy_domain2)); + memset(&test_current_vcpu, 0, sizeof(test_current_vcpu)); + INIT_PAGE_LIST_HEAD(&page_offlined_list); + INIT_PAGE_LIST_HEAD(&page_broken_list); + INIT_PAGE_LIST_HEAD(&test_page_list); + + init_numa_node_data(start_mfn); + for ( nodeid_t node = 0; node < MAX_NUMNODES; node++ ) + { + _heap[node] = &test_heap_storage[node]; + avail[node] = test_avail_storage[node]; + node_avail_pages[node] = 0; + for ( zone = 0; zone < NR_ZONES; zone++ ) + for ( order = 0; order <= MAX_ORDER; order++ ) + INIT_PAGE_LIST_HEAD(&heap(node, zone, order)); + } + total_avail_pages = 0; + outstanding_claims = 0; + first_valid_mfn = start_mfn; + max_page = sizeof(frame_table) / sizeof(frame_table[0]); + assert(first_valid_mfn < max_page); + init_dummy_domains(); +} + +static void __used init_page_alloc_tests(void) +{ + setup_testcase_init_func(reset_page_alloc_state); +} + +static void init_test_page(struct page_info *page, unsigned int order, + unsigned long state) +{ + mfn_t mfn = page_to_mfn(page); + + if ( mfn < first_valid_mfn && mfn > 0 && mfn < max_page ) + first_valid_mfn = mfn; + + if ( mfn >= max_page && mfn < ARRAY_SIZE(frame_table) ) + max_page = mfn + 1; + + memset(page, 0, sizeof(*page)); + page->v.free.order = order; + page->u.free.first_dirty = INVALID_DIRTY_IDX; + page->u.free.scrub_state = BUDDY_NOT_SCRUBBING; + page->count_info = state; +} + +static size_t __used page_list_add_buddy(struct page_info *pages, + unsigned int order, + const char *caller_file, + const char *caller_func, + int caller_line) +{ + size_t i, num_pages = 1U << order; + + init_test_page(&pages[0], order, PGC_state_inuse); + for ( i = 1; i < num_pages; i++ ) + init_test_page(&pages[i], order0, PGC_state_inuse); + free_heap_pages(&pages[0], order, false); + + if ( page_to_zone(&pages[0]) != page_to_zone(&pages[num_pages - 1]) ) + testcase_assert(false, caller_file, caller_line, caller_func, + "Buddy of order %u at MFN %lu crosses zones: " + "start zone %u, end zone %u", order, + page_to_mfn(&pages[0]), + page_to_zone(&pages[0]), + page_to_zone(&pages[num_pages - 1])); + return page_to_zone(&pages[0]); +} +#define test_page_list_add_buddy(pages, order) \ + page_list_add_buddy(pages, order, __FILE__, __func__, __LINE__) +#endif diff --git a/tools/tests/alloc/mock-page-list.h b/tools/tests/alloc/mock-page-list.h new file mode 100644 index 000000000000..d49f43f60933 --- /dev/null +++ b/tools/tests/alloc/mock-page-list.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Mock page-list implementation for page allocator tests. + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef TOOLS_TESTS_ALLOC_MOCK_PAGE_LIST_H +#define TOOLS_TESTS_ALLOC_MOCK_PAGE_LIST_H + +#include +#include +#include + +#include "harness.h" + +#define __XEN_KCONFIG_H +#undef __nonnull +#undef offsetof +#include +#undef cf_check +#define cf_check __used + +#define MAX_ORDER 20 + +struct page_info { + unsigned long count_info; + union { + struct { + unsigned long type_info; + } inuse; + union { + struct { + unsigned int first_dirty : MAX_ORDER + 1; +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + bool need_tlbflush : 1; + unsigned long scrub_state : 2; +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + }; + unsigned long val; + } free; + } u; + union { + struct { + unsigned int order; +#define PFN_ORDER(pg) ((pg)->v.free.order) + } free; + unsigned long type_info; + } v; + uint32_t tlbflush_timestamp; + struct domain *owner; + struct page_info *list_next; + struct page_info *list_prev; +}; + +struct page_list_head { + struct page_info *head; + struct page_info *tail; + unsigned int count; +}; +static struct page_list_head test_page_list; +typedef unsigned long mfn_t; + +#define PAGE_LIST_HEAD(name) struct page_list_head name = {NULL, NULL, 0} + +extern struct page_info frame_table[]; +#define page_to_mfn(pg) ((mfn_t)((pg) - &frame_table[0])) +#define mfn_to_page(mfn) (&frame_table[(mfn)]) +#define mfn_valid(mfn) (mfn >= first_valid_mfn && mfn < max_page) +#define maddr_to_page(pa) (CHECK(false, "Not implemented")) + +static void test_page_list_init(struct page_list_head *list) +{ + list->head = NULL; + list->tail = NULL; + list->count = 0; +} +#define INIT_PAGE_LIST_HEAD(l) test_page_list_init(l) +#define page_list_empty(list) ((list)->head == NULL) +#define page_list_first(list) ((list)->head) +#define page_list_last(list) ((list)->tail) +#define page_list_remove_head(list) test_page_list_del((list)->head, (list)) +#define page_to_list(d, pg) (&test_page_list) +#define page_list_add(pg, list) test_page_list_add(pg, list) +#define page_list_add_tail(pg, list) test_page_list_add_tail(pg, list) +#define page_list_del(pg, list) test_page_list_del(pg, list); +#define page_list_for_each_safe(pos, tmp, list) \ + for ( (pos) = page_list_first(list), \ + (tmp) = (pos) ? (pos)->list_next : NULL; \ + (pos) != NULL; \ + (pos) = (tmp), (tmp) = (pos) ? (pos)->list_next : NULL ) + +static void test_page_list_add_common(struct page_info *pg, + struct page_list_head *list, + bool at_tail) +{ + pg->list_next = NULL; + pg->list_prev = NULL; + + if ( list->head == NULL ) + { + list->head = pg; + list->tail = pg; + } + else if ( at_tail ) + { + pg->list_prev = list->tail; + list->tail->list_next = pg; + list->tail = pg; + } + else + { + pg->list_next = list->head; + list->head->list_prev = pg; + list->head = pg; + } + list->count++; +} + +#define test_page_list_add(pg, list) test_page_list_add_common(pg, list, false) +#define test_page_list_add_tail(pg, list) \ + test_page_list_add_common(pg, list, true) + +static struct page_info *test_page_list_del(struct page_info *pg, + struct page_list_head *list) +{ + if ( !pg ) + return NULL; + if ( pg->list_prev ) + pg->list_prev->list_next = pg->list_next; + else + list->head = pg->list_next; + + if ( pg->list_next ) + pg->list_next->list_prev = pg->list_prev; + else + list->tail = pg->list_prev; + + pg->list_next = NULL; + pg->list_prev = NULL; + + ASSERT(list->count > 0); + list->count--; + return pg; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x##UL << PG_shift(idx)) +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) +#define PGC_allocated PG_mask(1, 1) +#define PGC_xen_heap PG_mask(1, 2) +#define _PGC_need_scrub PG_shift(4) +#define PGC_need_scrub PG_mask(1, 4) +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info & PGC_state) == PGC_state_##st) +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) +#endif diff --git a/tools/tests/alloc/page-alloc-shim.h b/tools/tests/alloc/page-alloc-shim.h new file mode 100644 index 000000000000..0e682327fe07 --- /dev/null +++ b/tools/tests/alloc/page-alloc-shim.h @@ -0,0 +1,411 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Page allocator shim for xen/common/page_alloc.c. + * + * This shim provides the minimal Xen definitions that page_alloc.c needs + * in the unit-test environment. It models a minimal subset of the Xen + * environment, such as domain and NUMA node management, that page_alloc.c + * interacts with, so that the allocator logic so the allocator behaves + * as it does in the hypervisor while giving direct visibility into the + * allocator state for verification in the tests. + * + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef _TEST_ALLOC_PAGE_ALLOC_SHIM_ +#define _TEST_ALLOC_PAGE_ALLOC_SHIM_ + +/* + * Guard against language servers and linters picking up this header in + * the wrong context. + * + * This header is only intended to be used in the test program for unit + * testing functions in xen/common/page_alloc.c, and test programs define + * TEST_USES_PAGE_ALLOC_SHIM to enable the definitions in this header. + */ +#ifndef TEST_USES_PAGE_ALLOC_SHIM +#warning "This header is only for use in page_alloc.c unit tests." +#else +/* + * Inside the intended test context, provide mocks and stub definitions. + */ + +/* Configure the included headers for the test context */ +#ifndef CONFIG_NR_CPUS +#define CONFIG_NR_CPUS 64 +#endif + +#if defined(CONFIG_NUMA) && !defined(CONFIG_NR_NUMA_NODES) +#define CONFIG_NR_NUMA_NODES 64 +#endif + +#define CONFIG_SCRUB_DEBUG + +/* Provide struct page_info and related Xen definitions */ +#include "mock-page-list.h" + +/* Include the common check_asserts library for test assertions */ +#include "check-asserts.h" + +/* + * We add the Xen headers to the include path so page_alloc.c can + * resolve its #include directives without having to replicate all + * headers as actual files in the test tree: + * + * We define the header guards of those files to prevent unwanted + * definitions from those headers that conflict with the test harness. + */ +#define XEN_SOFTIRQ_H +#define XEN__XVMALLOC_H +#define _LINUX_INIT_H +#define _XEN_PARAM_H +#define __LIB_H__ /* C runtime library, only for the hypervisor */ +#define __LINUX_NODEMASK_H +#define __FLUSHTLB_H__ +#define __SCHED_H__ +#define __SPINLOCK_H__ +#define __TYPES_H__ /* Conflicts with the compiler-provided types */ +#define __VM_EVENT_H__ +#define __X86_PAGE_H__ +#define __XEN_CPUMASK_H +#define __XEN_EVENT_H__ +#define __XEN_FRAME_NUM_H__ +#define __XEN_IRQ_H__ +#define __XEN_MM_H__ +#define __XEN_PDX_H__ + +#include +#include +#include + +/* Include xen/numa.h with stubs and unused parameter warnings disabled */ +#define cpumask_clear_cpu(cpu, mask) ((void)(cpu), (void)(mask)) +#define mfn_to_pdx(mfn) ((unsigned long)(mfn)) +#pragma GCC diagnostic push +#ifndef CONFIG_NUMA +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif +#include +#pragma GCC diagnostic pop + +/* Flexible definition to support 32- and 64-bit architectures */ +#undef PADDR_BITS +#define PADDR_BITS (BITS_PER_LONG - PAGE_SHIFT) +#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) +#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define INVALID_MFN_INITIALIZER (~0UL) + +typedef unsigned long nodemask_t; + +/* struct domain for testing domain-specific page allocation and claims */ +struct domain { + spinlock_t page_alloc_lock; + nodemask_t node_affinity; + nodeid_t last_alloc_node; + domid_t domain_id; + unsigned int tot_pages; + unsigned int max_pages; + unsigned int extra_pages; + unsigned int global_claims; + unsigned int node_claims; + unsigned int claims[MAX_NUMNODES]; + unsigned int xenheap_pages; + bool is_dying; + struct domain *next_in_list; +}; +extern struct domain *domain_list; + +struct vcpu { + struct domain *domain; +}; + +/* + * Provide two domains for the test context, so that test helpers can call + * allocator functions that require domain context and verify behavior that + * depends on domain state, such as claims accounting and page allocation + * for specific domains. + */ +static struct domain test_dummy_domain1; +static struct domain test_dummy_domain2; +static struct domain __used *dom1 = &test_dummy_domain1; +static struct domain __used *dom2 = &test_dummy_domain2; + +/* To provide a current vcpu/domain pair for code paths that inspect it. */ +static unsigned char test_dummy_storage[PAGE_SIZE]; +static struct vcpu test_current_vcpu; +static struct vcpu *current = &test_current_vcpu; +static cpumask_t cpu_online_map = ~0UL; + +#define for_each_domain(_d) \ + for ( (_d) = domain_list; (_d) != NULL; (_d) = (_d)->next_in_list ) +#define for_each_online_node(i) for ( (i) = 0; (i) < MAX_NUMNODES; ++(i) ) +#define for_each_cpu(i, mask) for ( (i) = 0; (i) < 1; ++(i) ) + +/* dom_cow is a domain pointer used by the memory sharing code */ +#ifdef CONFIG_MEM_SHARING +static struct domain *dom_cow; +#else +#define dom_cow NULL +#endif + +/* + * Logging spinlock for the test context + */ +static spinlock_t *heap_lock_ptr; + +/* Helper function to track spinlock actions for additional context */ +static void print_spinlock(const char *action, spinlock_t *lock, + const char *file, int line, const char *func) +{ + const char *relpath = file; + + if ( !testcase_assert_verbose_assertions ) + return; + + while ( (file = strstr(relpath, "../")) ) + relpath += 3; + + for ( int i = 0; i < testcase_assert_verbose_indent_level; i++ ) + printf(" "); + + /* Print the path first:*/ + if ( testcase_assert_current_func == NULL || + strcmp(testcase_assert_current_func, func) != 0 ) + printf("%s:%d: %s(): ", relpath, line, func); + else + printf("%s:%d: ", relpath, line); + + if ( lock == heap_lock_ptr ) + printf("heap_lock %s\n", action); + else if ( domain_list && lock == &test_dummy_domain1.page_alloc_lock ) + printf("dom1->page_alloc_lock %s\n", action); + else if ( domain_list && lock == &test_dummy_domain2.page_alloc_lock ) + printf("dom2->page_alloc_lock %s\n", action); + else + printf("unknown lock %p %s\n", (void *)lock, action); +} + +/* + * If testcase_assert_verbose_assertions is enabled, the spinlock + * functions print the spinlock being acquired or released along with + * the file and line number of the assertion that triggered it. + * This can be helpful for debugging test failures and understanding + * the sequence of events leading up to the failure. + */ +#define spin_lock(l) \ + (print_spinlock("acquired", l, __FILE__, __LINE__, __func__), (void)(l)) +#define spin_unlock(l) \ + (print_spinlock("released", l, __FILE__, __LINE__, __func__), (void)(l)) +#define spin_lock_cb(l, cb, data) spin_lock(l) +#define spin_lock_kick() ((void)0) +#define nrspin_lock(l) spin_lock(l) +#define nrspin_unlock(l) spin_unlock(l) +#define rspin_lock(l) spin_lock(l) +#define rspin_unlock(l) spin_unlock(l) +#define DEFINE_SPINLOCK(l) spinlock_t l +/* + * For the test context, we assume all locks are always held to avoid having + * to manage lock state in the test helpers. This allows the test helpers + * to call allocator functions that require locks to be held without needing + * to acquire those locks, which simplifies the test code and focuses on + * exercising the allocator logic under test. + * + * Invariants that would normally be protected by locks must still be upheld + * by the test helpers, but the test helpers can assume they have exclusive + * access to the allocator state and do not need to worry about concurrency. + */ +#define spin_is_locked(l) true +#define rspin_is_locked(l) true + +/* memflags: */ +#define _MEMF_no_refcount 0 +#define MEMF_no_refcount (1U << _MEMF_no_refcount) +#define _MEMF_populate_on_demand 1 +#define MEMF_populate_on_demand (1U << _MEMF_populate_on_demand) +#define _MEMF_keep_scrub 2 +#define MEMF_keep_scrub (1U << _MEMF_keep_scrub) +#define _MEMF_no_dma 3 +#define MEMF_no_dma (1U << _MEMF_no_dma) +#define _MEMF_exact_node 4 +#define MEMF_exact_node (1U << _MEMF_exact_node) +#define _MEMF_no_owner 5 +#define MEMF_no_owner (1U << _MEMF_no_owner) +#define _MEMF_no_tlbflush 6 +#define MEMF_no_tlbflush (1U << _MEMF_no_tlbflush) +#define _MEMF_no_icache_flush 7 +#define MEMF_no_icache_flush (1U << _MEMF_no_icache_flush) +#define _MEMF_no_scrub 8 +#define MEMF_no_scrub (1U << _MEMF_no_scrub) +#define _MEMF_node 16 +#define MEMF_node_mask ((1U << (8 * sizeof(nodeid_t))) - 1) +#define MEMF_node(n) ((((n) + 1)&MEMF_node_mask) << _MEMF_node) +#define MEMF_get_node(f) ((((f) >> _MEMF_node) - 1)&MEMF_node_mask) +#define _MEMF_bits 24 +#define MEMF_bits(n) ((n) << _MEMF_bits) + +#define string_param(name, var) +#define custom_param(name, fn) +#define size_param(name, var) +#define boolean_param(name, func) +#define integer_param(name, var) +#define ACCESS_ONCE(x) (x) +#define cmpxchg(ptr, oldv, newv) \ + ({ \ + *(ptr) = (newv); \ + (oldv); \ + }) + +#define is_xen_heap_page(pg) false +#define page_to_virt(pg) ((void *)(pg)) +#define virt_to_page(v) ((struct page_info *)(v)) +#define mfn_to_virt(mfn) ((void *)&test_dummy_storage) +#define __mfn_to_virt(mfn) mfn_to_virt(mfn) +#define _mfn(x) ((mfn_t)(x)) +#define mfn_x(x) ((unsigned long)(x)) +#define mfn_add(mfn, nr) ((mfn) + (nr)) +#define mfn_min(a, b) ((a) < (b) ? (a) : (b)) + +/* + * NUMA stubs for unit testing NUMA-aware page allocator logic. + * + * nodemask_test() and node_set() implement real bit operations so that + * domain_install_claim_set() can correctly detect duplicate node entries + * in a claim set. mfn_to_pdx() is defined before xen/numa.h is included. + */ + +static nodemask_t node_online_map = ~0UL; +#define num_online_nodes() MAX_NUMNODES +#define node_online(node) ((node) < MAX_NUMNODES) +#define nodes_intersects(a, b) ((a) & (b)) +#define nodes_and(dst, a, b) ((dst) = (a) & (b)) +#define nodes_andnot(dst, a, b) ((dst) = (a) & ~(b)) +#define nodes_clear(dst) ((dst) = 0) +#define nodemask_test(node, mask) ((*(mask) >> (node)) & 1UL) +#define node_set(node, mask) ((mask) |= (1UL << (node))) +#define node_clear(node, mask) ((void)(mask)) +#define node_test_and_set(node, mask) false +#define first_node(mask) 0U +#define next_node(node, mask) MAX_NUMNODES +#define cycle_node(node, mask) 0U + +#ifdef CONFIG_NUMA +#define __node_distance(a, b) 0 +nodeid_t cpu_to_node[NR_CPUS]; +cpumask_t node_to_cpumask[MAX_NUMNODES]; +struct node_data node_data[MAX_NUMNODES]; +unsigned int memnode_shift; + +static typeof(*memnodemap) _memnodemap[64]; +nodeid_t *memnodemap = _memnodemap; +unsigned long memnodemapsize = sizeof(_memnodemap); +#endif /* CONFIG_NUMA */ + +/* + * Stub definitions for Xen functions and macros used by page_alloc.c, + * sufficient to support the test scenarios in tools/tests/alloc. + * + * These are not intended to be complete or accurate for general use + * in other test contexts or as a general-purpose shim for page_alloc.c. + */ +#define rcu_lock_domain(id) (&test_dummy_domain1) +#define rcu_lock_domain_by_any_id(id) (&test_dummy_domain1) +#define NOW() 0LL +#define SYS_STATE_active 1 +#define system_state 0 +#define cpu_online(cpu) ((cpu) == 0) +#define smp_processor_id() 0U +#define smp_wmb() ((void)0) +#define cpumask_empty(mask) true +#define cpumask_clear(mask) ((void)(mask)) +#define cpumask_and(dst, a, b) ((void)(dst), (void)(a), (void)(b)) +#define cpumask_or(dst, a, b) ((void)(dst), (void)(a), (void)(b)) +#define cpumask_copy(dst, src) ((void)(dst), (void)(src)) +#define cpumask_first(mask) 0U +#define cpumask_intersects(a, b) false +#define cpumask_weight(mask) 1 +#define __cpumask_set_cpu(cpu, mask) ((void)(cpu), (void)(mask)) +#define page_get_owner(pg) ((pg)->owner) +#define page_set_owner(pg, d) ((pg)->owner = (d)) +#define page_get_owner_and_reference(pg) ((pg)->owner) +#define page_set_tlbflush_timestamp(pg) ((pg)->tlbflush_timestamp = 0) +#define set_gpfn_from_mfn(mfn, gpfn) ((void)0) +#define page_is_offlinable(mfn) true +#define is_xen_fixed_mfn(mfn) false +#define filtered_flush_tlb_mask(ts) ((void)(ts)) +#define accumulate_tlbflush(need, pg, ts) ((void)(need), (void)(pg), (void)(ts)) +#define flush_page_to_ram(mfn, icache) ((void)(mfn), (void)(icache)) +#define scrub_page_hot(ptr) clear_page_hot(ptr) +#define scrub_page_cold(ptr) clear_page_cold(ptr) +#define send_global_virq(virq) ((void)(virq)) +#define softirq_pending(cpu) false +#define process_pending_softirqs() ((void)0) +#define on_selected_cpus(msk, f, data, w) ((void)0) +#define cpu_relax() ((void)0) +#define xmalloc(type) calloc(1, sizeof(type)) +#define xmalloc_array(type, nr) calloc((nr), sizeof(type)) +#define xvzalloc_array(type, nr) calloc((nr), sizeof(type)) +#define xvmalloc_array(type, nr) calloc((nr), sizeof(type)) +#define get_order_from_pages(nr) 0U +#define get_order_from_bytes(bytes) 0U +#define arch_mfns_in_directmap(mfn, nr) true +#define maddr_to_mfn(pa) ((mfn_t)paddr_to_pfn(pa)) + +#define ASSERT_ALLOC_CONTEXT() ((void)0) +#define arch_free_heap_page(d, pg) ((void)(d), (void)(pg)) +#define get_knownalive_domain(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, bits) (bits) +#define mem_paging_enabled(d) false +#define put_domain(d) ((void)(d)) +#define clear_page_hot(ptr) memset((ptr), 0, PAGE_SIZE) +#define clear_page_cold(ptr) memset((ptr), 0, PAGE_SIZE) +#define unmap_domain_page(ptr) ((void)(ptr)) +#define put_page(pg) ((void)(pg)) + +void *alloc_xenheap_pages(unsigned int order, unsigned int memflags); +void init_domheap_pages(paddr_t ps, paddr_t pe); +struct page_info *alloc_domheap_pages(struct domain *d, unsigned int order, + unsigned int memflags); + +/* Additional stubs for test support */ + +unsigned int arch_get_dma_bitsize(void) +{ + return 32U; +} + +/* Return number of pages currently posessed by the domain */ +static unsigned int domain_tot_pages(const struct domain *d) +{ + assert(d->extra_pages <= d->tot_pages); + return d->tot_pages - d->extra_pages; +} + +/* LLC (Last Level Cache) coloring support stubs */ +#define llc_coloring_enabled false +unsigned int get_max_nr_llc_colors(void) +{ + return 1U; +} +unsigned int page_to_llc_color(const struct page_info *pg) +{ + (void)pg; + return 0U; +} + +#define parse_bool(s, e) (-1) /* Not parsed, use the default */ + +void __init register_keyhandler(unsigned char key, keyhandler_fn_t *fn, + const char *desc, bool diagnostic) +{ + (void)key; + (void)fn; + (void)desc; + (void)diagnostic; +} + +unsigned long simple_strtoul(const char *cp, const char **endp, + unsigned int base) +{ + return strtoul(cp, (char **)endp, base); +} +#endif +#endif diff --git a/tools/tests/alloc/page-alloc-wrapper.h b/tools/tests/alloc/page-alloc-wrapper.h new file mode 100644 index 000000000000..5f595656f099 --- /dev/null +++ b/tools/tests/alloc/page-alloc-wrapper.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Wrapper around xen/common/page_alloc.c for the allocator test framework. + * + * The test framework includes the real page_alloc.c directly in its + * translation unit, together with mocks for the Xen types and functions it + * uses and helper code for NUMA heap initialisation and heap-state checks. + * + * This file provides the definitions needed for that setup. It also wraps + * selected page_alloc.c entry points, such as mark_page_offline() and + * offline_page(), so test scenarios can log allocator actions and resulting + * state during execution. + * + * Copyright (C) 2026 Cloud Software Group + */ +#ifndef TOOLS_TESTS_ALLOC_PAGE_ALLOC_WRAPPER_H +#define TOOLS_TESTS_ALLOC_PAGE_ALLOC_WRAPPER_H + +#define TEST_USES_PAGE_ALLOC_SHIM +#include "page-alloc-shim.h" + +/* Include the real page_alloc.c for testing */ + +#pragma GCC diagnostic push +/* TODO: We should fix the remaining sign-compare warnings in page_alloc.c */ +#pragma GCC diagnostic ignored "-Wsign-compare" +#pragma GCC diagnostic ignored "-Wunused-parameter" +/* + * Instrumenting the BUG() macro asserting to hit it means it is no longer + * noreturn, and a function expects it to be noreturn, so disable this warning + */ +#pragma GCC diagnostic ignored "-Wreturn-type" +#include "../../xen/common/page_alloc.c" +#pragma GCC diagnostic pop + +/* Allow the logging spinlock mocks to identify the allocator heap lock. */ +static spinlock_t *heap_lock_ptr = &heap_lock; + +/* Backing storage for the synthetic allocator state used by the tests. */ +#ifndef PAGES_PER_ZONE +#define PAGES_PER_ZONE 8 +#endif + +#ifndef MAX_PAGES +#define MAX_PAGES (MAX_NUMNODES * NR_ZONES * PAGES_PER_ZONE) +#endif + +/* + * The synthetic frame table backs the page_info entries used by the tests. + * It is indexed by MFN so helper code and the imported allocator can + * translate directly between MFNs and page_info pointers. + */ +struct page_info frame_table[MAX_PAGES]; + +/* Convenience pointer used by test scenarios. */ +static struct page_info *test_pages = frame_table; + +#define TOTAL_CLAIMS ((unsigned long)outstanding_claims) +#define FREE_PAGES \ + avail_heap_pages(MEMZONE_XEN + 1, NR_ZONES - 1, -1) + +#define DOM_GLOBAL_CLAIMS(d) ((d)->global_claims) +#define DOM_NODE_CLAIMS(d, n) ((d)->claims[n]) +#endif -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:24:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:24:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285848.1567059 (Exim 4.92) (envelope-from ) id 1wEocT-0005nl-87; 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Mon, 20 Apr 2026 15:24:55 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e62926-212f-0a2a450b0019-aceafc1f890c-3 for ; Mon, 20 Apr 2026 15:24:55 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 4E84D43DDE; Mon, 20 Apr 2026 13:24:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25315C19425; Mon, 20 Apr 2026 13:24:52 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776691493; bh=lk6iIm7LzLgEvSiocn/nJudNBxNOAcXBoMivMYFfH/Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=udSRzyKvaZpUpHacO3h3I+I8NDvZ5eQUUQOl9Rcl+PACvuF6XhJ+9SOkqn2+FNs35 Wmk95v1kWD5ZqVgIOg9X0Pv5nw6GkKpREKNnT68WFd8SVelwC+Pvi5W+NcdpQlCzah SgD4IwB5Ow4qnMbnb49wRiESSvhSfXjfQxSu50i1IjglijpGuUQkI/G7doikM7YzE8 ZnboB6kzFbKVk4zswFSnoRT/xtT42G7NSsWn/Vb5PrEEqezjh5dpkEBNPi9wbvliCs QuwJ24v0wIq64TC6tx6WIqHjjrxBvU0BgXYrBrzqoBz6xTCJZC8T6iMtbRKMwL1KGl 158HyljEVEvGA== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: Pengpeng Hou , Stefano Stabellini , Juergen Gross , Sasha Levin , linux@armlinux.org.uk, xen-devel@lists.xenproject.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH AUTOSEL 7.0-5.10] ARM: xen: validate hypervisor compatible before parsing its version Date: Mon, 20 Apr 2026 09:17:36 -0400 Message-ID: <20260420132314.1023554-62-sashal@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420132314.1023554-1-sashal@kernel.org> References: <20260420132314.1023554-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 7.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776691495-7F979F3B-C1AEF78A/0/0 X-purgate-type: clean X-purgate-size: 14062 From: Pengpeng Hou [ Upstream commit f45ab27774aadeee28f093a9f074892e9bebb586 ] fdt_find_hyper_node() reads the raw compatible property and then derives hyper_node.version from a prefix match before later printing it with %s. Flat DT properties are external boot input, and this path does not prove that the first compatible entry is NUL-terminated within the returned property length. Keep the existing flat-DT lookup path, but verify that the first compatible entry terminates within the returned property length before deriving the version suffix from it. Signed-off-by: Pengpeng Hou Reviewed-by: Stefano Stabellini Signed-off-by: Juergen Gross Message-ID: <20260405094005.5-arm-xen-v2-pengpeng@iscas.ac.cn> Signed-off-by: Sasha Levin --- LLM Generated explanations, may be completely bogus: Now I have all the information needed. Here is my complete analysis: --- ## PHASE 1: COMMIT MESSAGE FORENSICS ### Step 1.1: Subject Line - **Subsystem:** ARM: xen - **Action verb:** "validate" — implies adding missing input validation, strongly suggestive of a bug fix - **Summary:** Validate the hypervisor compatible string before parsing the version suffix from it ### Step 1.2: Tags - **Signed-off-by:** Pengpeng Hou (author), Juergen Gross (XEN HYPERVISOR INTERFACE maintainer — committer) - **Reviewed-by:** Stefano Stabellini (XEN HYPERVISOR ARM maintainer) - **Message-ID:** 20260405094005.5-arm-xen-v2-pengpeng@iscas.ac.cn (indicates v2 of patch) - No Fixes: tag (expected for review candidates). No Cc: stable. No Reported-by. - **Notable:** Both Xen ARM and Xen Interface maintainers endorsed this patch. ### Step 1.3: Commit Body The commit explains: - `fdt_find_hyper_node()` reads a raw `compatible` property from the flat device tree - It derives `hyper_node.version` via a prefix match - The version is later printed with `%s` - FDT properties are **external boot input** — the code doesn't verify that the first compatible entry is NUL-terminated within the returned property length - The fix adds validation of NUL-termination before deriving the version suffix **Bug:** Potential buffer over-read and NULL pointer dereference from unvalidated external input. **Symptom:** Out-of-bounds read when printing version string, or crash if property is absent. ### Step 1.4: Hidden Bug Fix Detection This is explicitly framed as input validation hardening. "Validate" clearly indicates fixing a missing safety check. This is a real bug fix. --- ## PHASE 2: DIFF ANALYSIS ### Step 2.1: Inventory - **File:** `arch/arm/xen/enlighten.c` — single file - **Function:** `fdt_find_hyper_node()` — single function - **Changes:** ~6 lines modified (net: +4/-2 meaningful lines) - **Scope:** Single-file surgical fix ### Step 2.2: Code Flow Change **Before:** ```c const void *s = NULL; int len; // ... s = of_get_flat_dt_prop(node, "compatible", &len); if (strlen(hyper_node.prefix) + 3 < len && !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) hyper_node.version = s + strlen(hyper_node.prefix); ``` **After:** ```c const char *s = NULL; int len; size_t prefix_len = strlen(hyper_node.prefix); // ... s = of_get_flat_dt_prop(node, "compatible", &len); if (s && len > 0 && strnlen(s, len) < len && len > prefix_len + 3 && !strncmp(hyper_node.prefix, s, prefix_len)) hyper_node.version = s + prefix_len; ``` ### Step 2.3: Bug Mechanism Two bugs fixed: **Bug 1 — NULL pointer dereference:** If `of_get_flat_dt_prop()` returns NULL (property absent), `len` is set to a negative error code. The old comparison `strlen(hyper_node.prefix) + 3 < len` compares `size_t` (unsigned) with `int`. Due to C implicit conversion, the negative `len` becomes a huge unsigned value, making the condition TRUE. Then `strncmp(hyper_node.prefix, NULL, ...)` is called → undefined behavior / crash. **Bug 2 — Buffer over-read:** If the compatible property exists but its first string entry lacks NUL-termination within the property length, `hyper_node.version` points into unterminated data. Later, `pr_info("Xen %s support found\n", hyper_node.version)` at line 268 reads beyond property bounds → information leak or crash. The fix adds: (1) NULL check `s &&`, (2) positive length check `len > 0`, (3) NUL-termination check `strnlen(s, len) < len`, and (4) proper size comparison `len > prefix_len + 3` with correct types. ### Step 2.4: Fix Quality - Obviously correct: adds standard defensive checks - Minimal/surgical: only touches the parsing condition - No regression risk: only adds validation; the happy path is identical - Clean type change from `const void *` to `const char *` is appropriate --- ## PHASE 3: GIT HISTORY ### Step 3.1: Blame The buggy code was introduced in commit `9b08aaa3199a4d` ("ARM: XEN: Move xen_early_init() before efi_init()") by Shannon Zhao, first appearing in **v4.8-rc1** (2016). This code has been present in the kernel for ~10 years and exists in ALL current stable trees. ### Step 3.2: Fixes Tag No Fixes: tag present (expected). The correct Fixes target would be `9b08aaa3199a4d`. ### Step 3.3: File History The `fdt_find_hyper_node()` function has not been modified since its introduction in 2016. Only unrelated parts of `enlighten.c` changed (treewide cleanups, etc.). No prerequisite commits needed. ### Step 3.4: Author Pengpeng Hou appears to contribute security/validation fixes across multiple subsystems (nfc, net, tracing, bluetooth). The patch was reviewed by the subsystem maintainer (Stefano Stabellini) and committed by the Xen interface maintainer (Juergen Gross). ### Step 3.5: Dependencies None. The fix is entirely self-contained. The code structure in stable trees is identical to mainline for this function. --- ## PHASE 4: MAILING LIST Lore was blocked by anti-bot measures. However, the Message-ID indicates this is v2 of the patch, suggesting it went through at least one round of review. The Reviewed-by from the ARM Xen maintainer and SOB from the Xen interface maintainer confirm it was properly reviewed through the standard process. --- ## PHASE 5: CODE SEMANTIC ANALYSIS ### Step 5.1: Functions Modified Only `fdt_find_hyper_node()` is modified. ### Step 5.2: Callers `fdt_find_hyper_node()` is called from `xen_early_init()` (line 257) via `of_scan_flat_dt()`. This is an `__init` function called very early during boot on ARM Xen guests. After the function runs, `hyper_node.version` is used in `pr_info()` at line 268. ### Step 5.3/5.4: Call Chain Boot path: `xen_early_init()` → `of_scan_flat_dt(fdt_find_hyper_node, NULL)` → flat DT scan callback invoked for each node. The data source is the FDT blob — external boot input provided by the hypervisor/bootloader. ### Step 5.5: Similar Patterns `of_get_flat_dt_prop()` is used throughout `drivers/of/fdt.c`. Other callers typically handle the NULL case (e.g., `if (p != NULL && l > 0)` at line 1115). The buggy Xen code was an outlier that skipped this validation. --- ## PHASE 6: STABLE TREE ANALYSIS ### Step 6.1: Buggy Code in Stable The buggy code was introduced in v4.8 and has NOT been modified since. It exists in all active stable trees (5.10.y, 5.15.y, 6.1.y, 6.6.y, 6.12.y). Only tree-wide mechanical changes (kmalloc_obj, sys-off handler) touched this file, none affecting the `fdt_find_hyper_node()` function. ### Step 6.2: Backport Complications The patch should apply cleanly to all stable trees. The function has been untouched since 2016. ### Step 6.3: Related Fixes No other fix for this specific issue exists in any stable tree. --- ## PHASE 7: SUBSYSTEM AND MAINTAINER CONTEXT - **Subsystem:** arch/arm/xen — ARM Xen hypervisor support - **Criticality:** IMPORTANT — affects all ARM systems running as Xen guests - **Maintainer endorsement:** Both the ARM Xen maintainer (Stefano Stabellini, Reviewed-by) and Xen Interface maintainer (Juergen Gross, committed) approved this fix --- ## PHASE 8: IMPACT AND RISK ASSESSMENT ### Step 8.1: Affected Users ARM Xen guest users. While not universal, this is a well-defined and active user population (cloud VMs, embedded Xen deployments). ### Step 8.2: Trigger Conditions - Bug 1 (NULL deref): hypervisor DT node exists but lacks "compatible" property — unusual but possible with malformed DT - Bug 2 (over-read): hypervisor DT compatible property not NUL- terminated — possible with malicious/corrupt FDT - Trigger is boot-time only, from external input ### Step 8.3: Failure Severity - NULL pointer dereference → kernel crash during early boot → CRITICAL - Buffer over-read → information leak or crash → HIGH (potential security issue) ### Step 8.4: Risk-Benefit - **Benefit:** HIGH — prevents potential crash or info leak from external input during boot on ARM Xen guests - **Risk:** VERY LOW — 4-5 lines of pure input validation added to a single condition; happy path unchanged - **Ratio:** Strongly favorable --- ## PHASE 9: FINAL SYNTHESIS ### Step 9.1: Evidence Summary **FOR backporting:** - Fixes two real bugs: NULL pointer dereference and buffer over-read from external input - Surgical fix: ~5 lines in one function, one file - Reviewed and committed by both Xen subsystem maintainers - Buggy code present since v4.8 (2016) — affects all stable trees - Zero regression risk — only adds validation, happy path unchanged - Will apply cleanly to all stable trees - External input validation is security-relevant **AGAINST backporting:** - No user report or syzbot trigger (hardening/proactive fix) - Boot-time only, ARM Xen specific (narrower impact than core kernel) ### Step 9.2: Stable Rules Checklist 1. Obviously correct and tested? **YES** — standard NULL/bounds/NUL checks, reviewed by maintainer 2. Fixes a real bug? **YES** — NULL deref and buffer over-read from external input 3. Important issue? **YES** — potential crash (NULL deref) and info leak (over-read) 4. Small and contained? **YES** — ~5 lines in one function 5. No new features or APIs? **YES** — pure validation 6. Can apply to stable? **YES** — function unchanged since v4.8 ### Step 9.3: Exception Categories Not applicable (not a device ID, quirk, or DT addition — this is a standard bug fix). ### Step 9.4: Decision The fix prevents both a NULL pointer dereference and a buffer over-read on external boot input in ARM Xen guests. It is minimal, obviously correct, endorsed by both relevant subsystem maintainers, and applies cleanly to all stable trees. The benefit clearly outweighs the near-zero risk. --- ## Verification - [Phase 1] Parsed tags: Reviewed-by from Stefano Stabellini (ARM Xen maintainer), SOB from Juergen Gross (Xen Interface maintainer) - [Phase 2] Diff analysis: ~5 lines changed in single condition in `fdt_find_hyper_node()`, adds NULL check, len > 0 check, strnlen NUL- termination check - [Phase 2] Verified `of_get_flat_dt_prop()` returns `const void *` and can return NULL (confirmed in `include/linux/of_fdt.h` line 56 and `drivers/of/fdt.c` line 622-626) - [Phase 2] Verified type promotion bug: `strlen()` returns `size_t` (unsigned), `len` is `int` — negative len promotes to huge unsigned, making condition TRUE with NULL `s` - [Phase 2] Verified `hyper_node.version` used with `%s` at line 268 in `pr_info()` — confirms over-read risk - [Phase 3] git blame: buggy code introduced in commit `9b08aaa3199a4d` (Shannon Zhao, 2016), first in v4.8-rc1 - [Phase 3] git describe: confirmed `9b08aaa3199a4d` is in v4.8-rc1~141^2~36 - [Phase 3] git log v5.10.. / v6.1.. / v6.6..: confirmed function unchanged in all stable trees (only tree-wide mechanical changes to file) - [Phase 5] Traced caller: `xen_early_init()` → `of_scan_flat_dt(fdt_find_hyper_node)` — boot-time path - [Phase 5] Verified other callers of `of_get_flat_dt_prop` typically check for NULL (e.g., fdt.c line 1114-1115) - [Phase 6] Code exists in all active stable trees (5.10+), function unchanged - [Phase 7] MAINTAINERS confirms Stefano Stabellini maintains arch/arm/xen/ and Juergen Gross maintains Xen interface - [Phase 8] Failure mode: NULL deref → crash at boot; over-read → info leak/crash. Severity: CRITICAL/HIGH - UNVERIFIED: Could not access lore.kernel.org discussion due to anti- bot protection. Does not affect decision since maintainer review is confirmed via tags. **YES** arch/arm/xen/enlighten.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c index 4feed2c2498dd..25a0ce3b4584a 100644 --- a/arch/arm/xen/enlighten.c +++ b/arch/arm/xen/enlighten.c @@ -218,8 +218,9 @@ static __initdata struct { static int __init fdt_find_hyper_node(unsigned long node, const char *uname, int depth, void *data) { - const void *s = NULL; + const char *s = NULL; int len; + size_t prefix_len = strlen(hyper_node.prefix); if (depth != 1 || strcmp(uname, "hypervisor") != 0) return 0; @@ -228,9 +229,10 @@ static int __init fdt_find_hyper_node(unsigned long node, const char *uname, hyper_node.found = true; s = of_get_flat_dt_prop(node, "compatible", &len); - if (strlen(hyper_node.prefix) + 3 < len && - !strncmp(hyper_node.prefix, s, strlen(hyper_node.prefix))) - hyper_node.version = s + strlen(hyper_node.prefix); + if (s && len > 0 && strnlen(s, len) < len && + len > prefix_len + 3 && + !strncmp(hyper_node.prefix, s, prefix_len)) + hyper_node.version = s + prefix_len; /* * Check if Xen supports EFI by checking whether there is the -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:25:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:25:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285852.1567069 (Exim 4.92) (envelope-from ) id 1wEocc-00064v-EW; Mon, 20 Apr 2026 13:25:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285852.1567069; Mon, 20 Apr 2026 13:25:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEocc-00064o-BQ; Mon, 20 Apr 2026 13:25:06 +0000 Received: by outflank-mailman (input) for mailman id 1285852; Mon, 20 Apr 2026 13:25:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEocb-00064F-Eh for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:25:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEocZ-008Kfe-A0 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:25:04 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e62930-5cb7-0a2a0a5109dd-0a2a450cc1ba-2 for ; Mon, 20 Apr 2026 15:25:04 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6292f-62f1-0a2a450c0019-a0658309874a-3 for ; Mon, 20 Apr 2026 15:25:04 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 7C0E68185110; Mon, 20 Apr 2026 09:24:07 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH v2 2/4] tools/tests/alloc: Add integration test suite to for NUMA memory claims Date: Mon, 20 Apr 2026 14:19:42 +0100 Message-Id: <079417bb90481b5212b8c7081d0e32f90d0df127.1776690702.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1776691504-F5E0ECF5-7EBEBB8D/0/0 X-purgate-type: clean X-purgate-size: 12487 Test claims behaviour of the page allocator with global claims using domain_set_outstanding_pages() and the new API and test multi-node claims. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-claims-basic.c | 108 ++++++++++++ tools/tests/alloc/test-claims-numa-redeem.c | 172 ++++++++++++++++++++ 2 files changed, 280 insertions(+) create mode 100644 tools/tests/alloc/test-claims-basic.c create mode 100644 tools/tests/alloc/test-claims-numa-redeem.c diff --git a/tools/tests/alloc/test-claims-basic.c b/tools/tests/alloc/test-claims-basic.c new file mode 100644 index 000000000000..ef02ca449023 --- /dev/null +++ b/tools/tests/alloc/test-claims-basic.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Cloud Software Group + */ +#include "libtest-page-alloc.h" + +int test_set_global_claims(struct domain *d, unsigned long pages) +{ + memory_claim_t claim_set[] = { + {.target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, .pages = pages}, + }; + + return domain_install_claim_set(d, ARRAY_SIZE(claim_set), claim_set); +} +typedef int (*set_global_claims)(struct domain *d, unsigned long pages); + +set_global_claims install_global_claims = test_set_global_claims; + +static void test_alloc_domheap_redeems_claims(int start_mfn) +{ + int ret; + struct page_info *pages = test_pages + start_mfn, *pg; + + test_page_list_add_buddy(pages, order2); + ASSERT(!test_set_global_claims(dom1, 3)); + ASSERT(alloc_domheap_pages(dom1, order1, 0) == pages + 2); + ASSERT(alloc_domheap_pages(dom1, order0, 0) == pages + 1); + CHECK(TOTAL_CLAIMS == 0, "Expect all claims consumed after allocations"); + CHECK(FREE_PAGES == 1, "Expect one free page after allocations"); + + ASSERT(!test_set_global_claims(dom2, FREE_PAGES)); + + /* Claim more than dom1 already has fails with ENOMEM (claimed by dom2) */ + ret = test_set_global_claims(dom1, domain_tot_pages(dom1) + 1); + CHECK(ret == -ENOMEM, "dom 1 claim +1 fails due to insufficient pages"); + + /* Claim more than dom1's d->max_pages fails with EINVAL */ + ret = test_set_global_claims(dom1, dom1->max_pages + 1); + CHECK(ret == -EINVAL, "dom 1 claim fails due to exceeding max_pages"); + + /* Attempt to allocate an order-0 page with a foreign claim present */ + pg = alloc_domheap_pages(dom1, order0, 0); + CHECK(pg == NULL, "dom 1 allocation fails because of domain 2's claim"); + CHECK(TOTAL_CLAIMS == 1, "Expect domain 2's claim to be still present"); + CHECK(FREE_PAGES == 1, "Expect one free page after failed alloc"); +} + +/* + * Test that memory claims are consumed correctly during allocations. + */ +static void test_cancel_claims(int start_mfn) +{ + struct page_info *page = test_pages + start_mfn; + unsigned long claims; + + /* Create a buddy of order 2 (4 pages) and add it to the heap. */ + test_page_list_add_buddy(page, order2); + claims = FREE_PAGES / 2; + + /* Claim half of the free pages for dom1 */ + ASSERT(test_set_global_claims(dom1, claims) == 0); + ASSERT(TOTAL_CLAIMS == claims); + + /* Act + Assert 2: Claim all free pages for dom2, should fail */ + ASSERT(test_set_global_claims(dom2, FREE_PAGES) == -ENOMEM); + ASSERT(TOTAL_CLAIMS == claims); + + /* Act + Assert 1: Cancel all claims for dom1 */ + ASSERT(test_set_global_claims(dom1, 0) == 0); + ASSERT(TOTAL_CLAIMS == 0); + + /* Act + Assert 2: Claim all free pages for dom2, should work */ + ASSERT(test_set_global_claims(dom2, FREE_PAGES) == 0); + ASSERT(TOTAL_CLAIMS == FREE_PAGES); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test global claims with old and new interfaces"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + + RUN_TESTCASE(TCCL, test_cancel_claims, 4); + + /* Confirm the baseline of using domain_set_outstanding_pages() */ + install_global_claims = domain_set_outstanding_pages; + RUN_TESTCASE(ADCL, test_alloc_domheap_redeems_claims, 4); + + /* Repeat the same test case using test_set_global_claims() */ + install_global_claims = test_set_global_claims; + RUN_TESTCASE(ADCG, test_alloc_domheap_redeems_claims, 4); + + testcase_print_summary(program_name); + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/alloc/test-claims-numa-redeem.c b/tools/tests/alloc/test-claims-numa-redeem.c new file mode 100644 index 000000000000..aaa1a5b6af5c --- /dev/null +++ b/tools/tests/alloc/test-claims-numa-redeem.c @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Integration tests for redeeming NUMA memory claim set as implemented + * in xen/common/page_alloc.c's redeem_claims_for_allocation() and + * related functions. + * + * redeem_claims_for_allocation() is exercised indirectly through + * alloc_domheap_pages() which is the primary interface for allocating + * pages from a domain's heap. + * + * By means of domain_install_claim_set(), a claim set with global and + * per-NUMA-node claims is installed for a dummy domain, and then + * allocations with NUMA node affinity are performed to verify that the + * appropriate claims are redeemed (same-node first, global fallback next, + * then other nodes to not exceed page limits). The test also verifies that + * aggregate counters are updated correctly after each allocation. + * + * The test verifies that when a domain has a claim set installed with + * global and per-NUMA-node claims, allocations that specify NUMA node + * affinity will redeem the appropriate claims (same-node first, global + * fallback claim next, then other nodes to not exceed page limits). + * It also verifies that the aggregate claim counters are updated + * correctly after each allocation. + * + * Copyright (C) 2026 Cloud Software Group + */ + +#define CONFIG_NUMA 1 +#define CONFIG_SYSCTL 1 +#include "libtest-page-alloc.h" + +/* + * Test redeeming NUMA memory claims in exchange for allocations, + * and the redeemed claims are correctly reflected in the domain's + * claim state and the aggregate claim counters. + */ +static void test_claims_numa_install(int start_mfn) +{ + int zone, ret; + struct page_info *pages = test_pages + start_mfn, *allocated; + + /* + * PREPARE + */ + + /* + * Node 1's pages start at the pfn set by init_numa_node_data(): + * node_data[node1].node_start_pfn = start_mfn + 8 (8 MFNs per node with + * memnode_shift=3). The order-2 buddy (4 pages) placed there satisfies + * the 2-page node1 claim and provides enough total pages for the + * 2 global + 2 node0 + 2 node1 = 6-page claim set (2 + 4 = 6 total). + */ + struct page_info *pages_node1 = + test_pages + node_data[node1].node_start_pfn; + + /* Create an order-1 buddy (2 pages) for node 0 and add it to the heap. */ + zone = test_page_list_add_buddy(pages, order1); + + /* Create an order-2 buddy (4 pages) for node 1 and add it to the heap. */ + test_page_list_add_buddy(pages_node1, order2); + + /* Install a claim set with global + per-NUMA-node claims. */ + memory_claim_t claim_set[] = { + {.target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL, .pages = 2}, + {.target = node0, .pages = 2}, + {.target = node1, .pages = 2}, + }; + ret = domain_install_claim_set(dom1, ARRAY_SIZE(claim_set), claim_set); + CHECK(ret == 0, "domain_install_claim_set should succeed: %d", ret); + + /* Assert dom1's claims */ + CHECK(TOTAL_CLAIMS == 6, "Expect 6 total claims after installation"); + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 having 2 global claims after installation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 2, + "Expect dom1 having 2 claims for node0 after installation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 2, + "Expect dom1 having 2 claims for node1 after installation"); + + /* Allocate an order-0 page from node 0 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node0)); + CHECK(allocated != NULL, "alloc_domheap_pages should succeed"); + + /* Verify the state of the aggregate counters after allocation. */ + CHECK(TOTAL_CLAIMS == 5, "Expect 5 total claims left after allocation"); + CHECK(FREE_PAGES == 5, "Expect 5 free pages left after allocation"); + + /* Assert dom1's claims after the allocation from node0 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 still having 2 global claims after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 2, + "Expect dom1 still having 2 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 2, + "Expect dom1 still having 2 global claims after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 1, + "Expect dom1 having 1 claim for node1 after allocation"); + + /* Allocate an order-1 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order1, MEMF_node(node1)); + CHECK(allocated != NULL, "order-1 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 1, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 0, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 1, + "Expect dom1 having 1 claim for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); + + /* Allocate an order-0 page from node 1 for the dummy domain. */ + allocated = alloc_domheap_pages(dom1, order0, MEMF_node(node1)); + CHECK(allocated != NULL, "order-0 alloc from node1"); + + /* Assert dom1's claims after the allocation from node1 */ + CHECK(DOM_GLOBAL_CLAIMS(dom1) == 0, + "Expect dom1 having redeemed one global claim after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node0) == 0, + "Expect dom1 having 0 claims for node0 after allocation"); + CHECK(DOM_NODE_CLAIMS(dom1, node1) == 0, + "Expect dom1 having 0 claims for node1 after allocation"); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test legacy claims with allocation from the heap"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + /* + * Use test_set_global_claims() which is a wrapper around + * domain_install_claim_set() to check ensure consistent + * behavior with domain_set_outstanding_pages(). + */ + RUN_TESTCASE(CNI0, test_claims_numa_install, 0); + + testcase_print_summary(program_name); + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:25:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:25:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285886.1567078 (Exim 4.92) (envelope-from ) id 1wEod6-0006oI-QR; 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Mon, 20 Apr 2026 15:25:34 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6294d-aaa8-0a2a45050019-a06583088c08-3 for ; Mon, 20 Apr 2026 15:25:34 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id 87EFF420DB75; Mon, 20 Apr 2026 09:24:48 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD Subject: [PATCH v2 3/4] tools/tests/alloc: Add tests for offlining with claims present Date: Mon, 20 Apr 2026 14:19:43 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1776691534-E256B443-EEB0D6C7/0/0 X-purgate-type: clean X-purgate-size: 3590 Add an integration test for offlining pages with outstanding claims. The test offlines two pages, with the second offline operation recalling one claim to prevent over-claiming beyond the available memory. Due to missing checks in the offlining code, there are expected failures which will be fixed in a test-driven manner. Run this test with both global claims and node-local claims. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-offlining-claims.c | 75 +++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 tools/tests/alloc/test-offlining-claims.c diff --git a/tools/tests/alloc/test-offlining-claims.c b/tools/tests/alloc/test-offlining-claims.c new file mode 100644 index 000000000000..a0580af82ef5 --- /dev/null +++ b/tools/tests/alloc/test-offlining-claims.c @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Cloud Software Group + */ +#include "libtest-page-alloc.h" + +static void test_offlining_with_global_claims(int mfn) +{ + struct page_info *page = test_pages + mfn; + uint32_t status = 0; + memory_claim_t claims[1] = { + {.pages = 3, .target = XEN_DOMCTL_CLAIM_MEMORY_GLOBAL} + }; + + test_page_list_add_buddy(page, order2); /* Add a buddy with 4 free pages*/ + ASSERT(domain_install_claim_set(dom1, ARRAY_SIZE(claims), claims) == 0); + + offline_page(mfn + 3, 0, &status); /* Offline the 1st page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + CHECK(TOTAL_CLAIMS == 3, "Still 3 claims before offlining the 2nd page"); + + offline_page(mfn + 1, 0, &status); /* Offline the 2nd page */ + ASSERT(status & PG_OFFLINE_OFFLINED); + + CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); + EXPECTED_TO_FAIL_BEGIN(); + CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); + EXPECTED_TO_FAIL_END(1); +} + + +/* + * Claim 3 of 4 pages on node0, offline two pages, and the 2nd offline should + * recall one claim to prevent over-claiming beyond the available memory. + * + * As part of offline_page(), reserve_offlined_page() should recall the + * needed claims to not exceed the number of pages that are are remaining. + */ +static void test_offlining_with_node_claims(int mfn) +{ + struct page_info *page = test_pages + mfn; + uint32_t status = 0; + memory_claim_t claims[1] = { {.pages = 3, .target = node0} }; + + test_page_list_add_buddy(page, order2); + ASSERT(domain_install_claim_set(dom1, ARRAY_SIZE(claims), claims) == 0); + + ASSERT(offline_page(mfn + 3, 0, &status) == 0); + ASSERT(status & PG_OFFLINE_OFFLINED); + CHECK(TOTAL_CLAIMS == 3, "Still 3 claims before offlining the 2nd page"); + + ASSERT(offline_page(mfn + 1, 0, &status) == 0); + ASSERT(status & PG_OFFLINE_OFFLINED); + + CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); + EXPECTED_TO_FAIL_BEGIN(); + CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); + EXPECTED_TO_FAIL_END(1); +} + +int main(int argc, char *argv[]) +{ + const char *topic = "Test offlining with memory claims"; + const char *program_name = parse_args(argc, argv, topic); + + if ( !program_name ) + return EXIT_FAILURE; + + init_page_alloc_tests(); + + RUN_TESTCASE(OWGC, test_offlining_with_global_claims, 4); + RUN_TESTCASE(OWNC, test_offlining_with_node_claims, 4); + + return testcase_print_summary(program_name); +} -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:26:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:26:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285909.1567088 (Exim 4.92) (envelope-from ) id 1wEodo-0007MZ-3L; Mon, 20 Apr 2026 13:26:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285909.1567088; Mon, 20 Apr 2026 13:26:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEodn-0007MS-Ux; Mon, 20 Apr 2026 13:26:19 +0000 Received: by outflank-mailman (input) for mailman id 1285909; Mon, 20 Apr 2026 13:26:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEodm-0007M4-LO for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:26:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEodm-00B2Mn-29 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:26:18 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e62968-e002-0a2a0a5209dd-0a2a4506b792-36 for ; Mon, 20 Apr 2026 15:26:18 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e62977-7371-0a2a45060019-a0658308d85c-3 for ; Mon, 20 Apr 2026 15:26:16 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id DFFED420DE01; Mon, 20 Apr 2026 09:25:29 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 4/4] xen/mm: Recall claims when offlining pages if needed Date: Mon, 20 Apr 2026 14:19:44 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776691576-51361D75-B170C3DC/0/0 X-purgate-type: clean X-purgate-size: 3980 Fix a bug where offlining pages could cause an unsigned underflow in total_avail_pages - outstanding_claims, leading to incorrect claim behavior. This issue arises when outstanding claims are close to the total available pages. It occurse when domain_set_outstanding_claims() and domain_install_claim_set effectively do this: unsigned long avail_pages = total_avail_pages - outstanding_claims; When this unsigned subtraction underflows, staking claims can succeed even when there is insufficient unclaimed memory for the new claim. This leads to a state where claims always succeed, regardless of actual memory availability. To prevent this, recall claims when offlining pages if needed to maintain equilibrium between `total_avail_pages` and outstanding claims for global and for per-NUMA-node claims. Signed-off-by: Bernhard Kaindl --- tools/tests/alloc/test-offlining-claims.c | 4 --- xen/common/page_alloc.c | 42 +++++++++++++++++++++++ 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/tools/tests/alloc/test-offlining-claims.c b/tools/tests/alloc/test-offlining-claims.c index a0580af82ef5..69a3e8f82e6b 100644 --- a/tools/tests/alloc/test-offlining-claims.c +++ b/tools/tests/alloc/test-offlining-claims.c @@ -23,9 +23,7 @@ static void test_offlining_with_global_claims(int mfn) ASSERT(status & PG_OFFLINE_OFFLINED); CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); - EXPECTED_TO_FAIL_BEGIN(); CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); - EXPECTED_TO_FAIL_END(1); } @@ -53,9 +51,7 @@ static void test_offlining_with_node_claims(int mfn) ASSERT(status & PG_OFFLINE_OFFLINED); CHECK(FREE_PAGES == 2, "Expect 2 free pages after offlining two pages"); - EXPECTED_TO_FAIL_BEGIN(); CHECK(TOTAL_CLAIMS == 2, "Expect 2 claims after offlining two pages"); - EXPECTED_TO_FAIL_END(1); } int main(int argc, char *argv[]) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 6101bd6be9a9..adedf6fae590 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -1575,6 +1575,48 @@ static int reserve_offlined_page(struct page_info *head) count++; } + if ( count ) + { + long recall_pages; + struct domain *d; + + /* Ensure that claims on the node are in line with its free memory. */ + recall_pages = node_outstanding_claims[node] - node_avail_pages[node]; + if ( recall_pages > 0 ) + /* + * node_avail_pages slipped below node_outstanding_claims. + * We need to recall claimed pages until the amount of claimed + * memory is in line with the amount of available memory again. + */ + for_each_domain ( d ) + { + if ( d->claims[node] ) + { + recall_pages -= deduct_node_claims(d, node, recall_pages); + if ( recall_pages <= 0 ) + break; + } + } + + /* Ensure that outstanding claims are in line with available memory. */ + recall_pages = outstanding_claims - total_avail_pages; + if ( recall_pages > 0 ) + /* + * total_avail_pages slipped below outstanding_claims. + * We need to recall claimed pages until the amount of claimed + * memory is in line with the amount of available memory again. + */ + for_each_domain ( d ) + { + if ( d->global_claims ) + { + recall_pages -= deduct_global_claims(d, recall_pages); + if ( recall_pages <= 0 ) + break; + } + } + } + return count; } -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 13:38:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 13:38:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1285955.1567096 (Exim 4.92) (envelope-from ) id 1wEopZ-0000qK-3J; Mon, 20 Apr 2026 13:38:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1285955.1567096; Mon, 20 Apr 2026 13:38:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEopY-0000qD-Vh; Mon, 20 Apr 2026 13:38:28 +0000 Received: by outflank-mailman (input) for mailman id 1285955; Mon, 20 Apr 2026 13:38:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEopX-0000q7-L7 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 13:38:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEopX-00DYNK-1h for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:38:27 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e62c50-5cb7-0a2a0a5109dd-0a2a4502a32e-12 for ; Mon, 20 Apr 2026 15:38:26 +0200 Received: from [209.85.221.48] (helo=mail-wr1-f48.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e62c52-af86-0a2a45020019-d155dd30dc98-3 for ; Mon, 20 Apr 2026 15:38:26 +0200 Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-43fde5b81a1so2247468f8f.0 for ; Mon, 20 Apr 2026 06:38:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776692306-8A4C5161-DC114E90/0/0 X-purgate-type: clean X-purgate-size: 802 On 20.04.2026 14:49, Teddy Astie wrote: > Is there anything that would prevent the use of alloc_domheap_pages() to > allocate a configuous set of pages at once; and vmap_contig() to map it > in one go. > That also prevents the ioreq pages from being scattered around. > > We would lose a few pages by aligning the size into a order, but that > probably better than the alternatives. > > That way, we would only have to keep the base gfn (or first page_info) > and size of the allocation, and don't have to use a array of mfn nor > have to reverse the vmap to track it. Well, higher-order allocations can easily fail when there's ample memory available. Hence why a goal ought to be to avoid such allocations at runtime. That's why we (now) have vmalloc() and xvmalloc(). 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <00fa439d-0327-4c0c-960d-a810820a6e83@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776692759-80A7F8B7-0493567D/0/0 X-purgate-type: clean X-purgate-size: 6380 On 20.04.2026 13:39, Oleksii Kurochko wrote: > On 4/16/26 2:51 PM, Jan Beulich wrote: >> On 14.04.2026 13:29, Oleksii Kurochko wrote: >>> On 4/2/26 2:22 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>>>> + struct dt_device_node *dev, >>>>> + bool need_mapping, >>>>> + struct rangeset *irq_ranges) >>>>> +{ >>>>> + unsigned int i, nirq; >>>>> + int res, irq; >>>>> + struct dt_raw_irq rirq; >>>>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>>>> + unsigned int reg_num; >>>>> + >>>>> + nirq = dt_number_of_irq(dev); >>>>> + >>>>> + /* Give permission and map IRQs */ >>>>> + for ( i = 0; i < nirq; i++ ) >>>>> + { >>>>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>>>> + if ( res ) >>>>> + { >>>>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>>>> + i, dt_node_full_name(dev)); >>>>> + return res; >>>>> + } >>>>> + >>>>> + /* >>>>> + * Don't map IRQ that have no physical meaning >>>>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>>>> + */ >>>>> + if ( rirq.controller != dt_interrupt_controller ) >>>>> + { >>>>> + dt_dprintk("irq %u not connected to primary controller." >>>>> + "Connected to %s\n", i, >>>>> + dt_node_full_name(rirq.controller)); >>>>> + continue; >>>>> + } >>>>> + >>>>> + irq = platform_get_irq(dev, i); >>>>> + if ( irq < 0 ) >>>>> + { >>>>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>>>> + return irq; >>>>> + } >>>>> + >>>>> + res = irq_permit_access(d, irq); >>>>> + if ( res ) >>>>> + { >>>>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>>>> + irq); >>>> >>>> This time the other way around: %d please with plain int. (Again at least >>>> once further down.) >>>> >>>>> + return res; >>>>> + } >>>>> + >>>>> + reg_num = irq / APLIC_NUM_REGS; >>>>> + >>>>> + if ( is_irq_shared_among_domains(d, irq) ) >>>>> + { >>>>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>>>> + return -EINVAL; >>>>> + } >>>>> + >>>>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >>>> >>>> ... all of this leaves me with the impression that IRQ numbering isn't really >>>> virtualized. IRQs are merely split into groups, one group per domain (and >>>> maybe some unused). How are you going to fit in truly virtual IRQs? >>> >>> What do you mean by truly virtual IRQs? >> >> Ones where no aspects are represented by any piece of hardware. >> >>> I can't totally agree that the current approach isn't use virtual IRQs, >>> yes, they are 1:1 mapped but on the other side Xen is responsible to >>> give an IRQ number for guest's device and Xen is responsible that guest >>> isn't trying to reach IRQ which not belongs to it. >> >> In a non-virtualized environment I expect IRQs are going to be "sparse" >> (i.e. with perhaps large blocks of items used elsewhere). If you had >> proper translation of IRQ numbers, the same could be true for your >> guests. > > Partial FDT, which is used to tell which device be passthroughed to > guest, is using physical IRQ number (which I am just considering for > simplicity to be 1:1 mapped to virtual IRQ number). So if we have the > following configuration: > Physical (bare-metal) IRQ layout is sparse: > IRQ 5 → UART -> domU0 > IRQ 23 → Ethernet -> domU1 > IRQ 47 → PCIe -> domU0 > IRQ 100 → Storage -> domU1 > (gaps everywhere, driven by hardware wiring) > > For such configuration we will have for each domain auth_irq_bmp[] which > contains: > IRQ 5 and IRQ47 for domU0 > and > IRQ 23 and IRQ 100 for domU1 > > And here vIRQ5 = pIRQ5, vIRQ47 = pIRQ47 and so on. auth_irq_bmp just > transform xIRQ number to bit position which it will have in real APLIC > register. Just as an example, lets take vIRQ5 and vIRQ47. > > As reading or writing register setie[k] reads or potentially modifies > the enable bits for interrupt sources k × 32 through k × 32 + 31. For an > implemented interrupt source i within that range, the enable bit for > source i corresponds with register bit (i mod 32). > So for: > - vIRQ5 == pIRQ5 we have to set bit 5 in setie[0] > - vIRQ47 == pIRQ47 we have to set bit 15 in setie[1] > > Probably it was not the best idea to declare auth_irq_bmp as it will > look in h/w and maybe just 'bool auth_irq_bmp[1024]' would be more clearer. > > So irqs number are still stay "sparsed" in guest. Well, twice (or more) as sparse in the example you give, compared to the host. >>>>> + dt_dprintk(" - IRQ: %u\n", irq); >>>>> + >>>>> + if ( irq_ranges ) >>>>> + { >>>>> + res = rangeset_add_singleton(irq_ranges, irq); >>>>> + if ( res ) >>>>> + return res; >>>>> + } >>>> >>>> What is irq_ranges? >>> >>> IIUC based on Arm code irq_ranges is an optional output accumulator, the >>> caller allocates and passes it in when it needs to track which IRQs were >>> mapped (overlay use case), or passes NULL when that tracking is not needed. >>> >>> I added here as map_device_irqs_to_domain() is called from the common >>> code and so maybe one day someone will decide to pass irq_ranges to this >>> functions. At the moment, for RISC-V it is the only one user of >>> map_device_irqs_to_domain() and it passes NULL. >> >> Simply assert then that it's NULL? > > Won't BUG_ON() be better here as it BUG_ON() macros is always defined > and doesn't matter if release or debug build are used. Depends on the context, really. > Or maybe you meant: > if ( irq_ranges ) > assert_failed("irq_ranges arg isn't supported\n"); Definitely not. assert_failed() shouldn't be called directly, as I had told you on at least one earlier occasion. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776693171-39D6BDB1-B820A29F/0/0 X-purgate-type: clean X-purgate-size: 2260 On 10.04.2026 12:09, Teddy Astie wrote: > Replace macros with bitfield to allow simplyfing the code and be > less error prone when manipulating PTEs. > > It also has the effect of directly exposing the mfn in the pte struct > instead of derivating it from the raw pte value using dma_pte_addr(). > > Signed-off-by: Teddy Astie > --- > It allows nicer constructs like > > new.snp = iommu_snoop; > > instead of > > if ( iommu_snoop ) > dma_set_pte_snp(new); > > A lot of simplifications could be done afterward when switching the > logic from maddrs to mfns i.e remove many maddr-mfn conversions. There's no real open question here, so it's not quite clear why this is marked RFC. We did do the same on the AMD side a while back, at least partly (I don't think we got all of it converted yet), so doing the conversion here surely is a good thing. The slightly larger ... > bloat-o-meter (along with the previous change) > > add/remove: 0/0 grow/shrink: 7/3 up/down: 227/-45 (182) > Function old new delta > addr_to_dma_page_maddr 949 1058 +109 > vtd_dump_page_table_level 197 233 +36 > fill_qpt 1151 1178 +27 > print_vtd_entries 486 504 +18 > domain_context_mapping_one 2098 2114 +16 > intel_iommu_map_page 909 921 +12 > intel_iommu_unmap_page 731 740 +9 > intel_iommu_lookup_page 185 176 -9 > queue_free_pt 442 425 -17 > vtd_dump_page_table_level.cold 86 67 -19 > Total: Before=18446744073715636162, After=18446744073715636344, chg +0.00% ... code size shouldn't be much of a concern, albeit you may want to at least mention the (presumed) reason for some of the bigger increases, after comparing the generated code. (As an aside, the two values after Total: look entirely bogus.) > I guess using mfns 'everywhere' would improve the bloat-o-meter picture. It's not quite clear to me what you mean here. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260401163521.3603665-4-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776693842-6EB74CF5-EDE52468/0/0 X-purgate-type: clean X-purgate-size: 596 On 01.04.2026 18:35, Ross Lagerwall wrote: > @@ -275,21 +274,18 @@ void flush_area_mask(const cpumask_t *mask, const void *va, unsigned int flags) > if ( (flags & ~FLUSH_ORDER_MASK) && > !cpumask_subset(mask, cpumask_of(cpu)) ) > { > + cpumask_t flush_cpumask; I think we want to avoid introduction of a new on-stack variable of this type. For large NR_CPUS they consume excessively much stack space; it wasn't that long ago that (iirc) in HPET code we successfully eliminated one. Instead a per-CPU variable of type cpumask_var_t may want using. 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Mon, 20 Apr 2026 07:07:35 -0700 (PDT) Message-ID: <0099bc30-ce07-496a-b9b2-6d7ca400737b@suse.com> Date: Mon, 20 Apr 2026 16:07:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jan Beulich Subject: [PATCH v11] x86emul: support LKGS To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776694056-E95A7443-B5C3CEFD/0/0 X-purgate-type: clean X-purgate-size: 9468 Provide support for this insn, which is a prereq to FRED. CPUID-wise, while its and FRED's enumerators were already introduced, their dependency still needs adding. While adding a testcase, also add a SWAPGS one. In order to not affect the behavior of pre-existing tests, install write_{segment,msr} hooks only transiently. Signed-off-by: Jan Beulich --- For PV save_segments() would need adjustment, but the insn being restricted to ring 0 means PV guests can't use it anyway (unless we wanted to emulate it as another privileged insn). I've also dropped the test harness read_segment() change. It generally would be correct to have, but isn't needed anymore with neither SWAPGS nor LKGS handling using the hook. --- v11: Comment adjustments (to Andrew's liking). v10: Drop FRED dependency on LKGS. Replace "best effort unwind". Avoid ->read_segment(). Re-base. v9: Re-base. v8: Re-base. v6: Use MSR constants in test harness. S->s in cpufeatureset.h. Add NMI_SRC feature bits. Re-base. v5: Re-base. v3: Add dependency on LM. Re-base. v2: Use X86_EXC_*. Add comments. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -326,6 +326,7 @@ static const struct { { { 0x00, 0x18 }, { 2, 2 }, T, R }, /* ltr */ { { 0x00, 0x20 }, { 2, 2 }, T, R }, /* verr */ { { 0x00, 0x28 }, { 2, 2 }, T, R }, /* verw */ + { { 0x00, 0x30 }, { 0, 2 }, T, R, pfx_f2 }, /* lkgs */ { { 0x01, 0x00 }, { 2, 2 }, F, W }, /* sgdt */ { { 0x01, 0x08 }, { 2, 2 }, F, W }, /* sidt */ { { 0x01, 0x10 }, { 2, 2 }, F, R }, /* lgdt */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -673,6 +673,10 @@ static int blk( return x86_emul_blk((void *)offset, p_data, bytes, eflags, state, ctxt); } +#ifdef __x86_64__ +static unsigned long gs_base, gs_base_shadow; +#endif + static int read_segment( enum x86_segment seg, struct segment_register *reg, @@ -682,8 +686,25 @@ static int read_segment( return X86EMUL_UNHANDLEABLE; memset(reg, 0, sizeof(*reg)); reg->p = 1; + + return X86EMUL_OKAY; +} + +#ifdef __x86_64__ +static int write_segment( + enum x86_segment seg, + const struct segment_register *reg, + struct x86_emulate_ctxt *ctxt) +{ + if ( !is_x86_user_segment(seg) ) + return X86EMUL_UNHANDLEABLE; + + if ( seg == x86_seg_gs ) + gs_base = reg->base; + return X86EMUL_OKAY; } +#endif static int read_msr( unsigned int reg, @@ -696,6 +717,20 @@ static int read_msr( *val = ctxt->addr_size > 32 ? EFER_LME | EFER_LMA : 0; return X86EMUL_OKAY; +#ifdef __x86_64__ + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val = gs_base; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 ) + break; + *val = gs_base_shadow; + return X86EMUL_OKAY; +#endif + case MSR_TSC_AUX: #define TSC_AUX_VALUE 0xCACACACA *val = TSC_AUX_VALUE; @@ -705,6 +740,32 @@ static int read_msr( return X86EMUL_UNHANDLEABLE; } +#ifdef __x86_64__ +static int write_msr( + unsigned int reg, + uint64_t val, + struct x86_emulate_ctxt *ctxt, + bool explicit) +{ + switch ( reg ) + { + case MSR_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base = val; + return X86EMUL_OKAY; + + case MSR_SHADOW_GS_BASE: + if ( ctxt->addr_size < 64 || !is_canonical_address(val) ) + break; + gs_base_shadow = val; + return X86EMUL_OKAY; + } + + return X86EMUL_UNHANDLEABLE; +} +#endif + #define INVPCID_ADDR 0x12345678 #define INVPCID_PCID 0x123 @@ -1339,6 +1400,41 @@ int main(int argc, char **argv) printf("%u bytes read - ", bytes_read); goto fail; } + printf("okay\n"); + + emulops.write_segment = write_segment; + emulops.write_msr = write_msr; + + printf("%-40s", "Testing swapgs..."); + instr[0] = 0x0f; instr[1] = 0x01; instr[2] = 0xf8; + regs.eip = (unsigned long)&instr[0]; + gs_base = 0xffffeeeecccc8888UL; + gs_base_shadow = 0x0000111122224444UL; + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || + (regs.eip != (unsigned long)&instr[3]) || + (gs_base != 0x0000111122224444UL) || + (gs_base_shadow != 0xffffeeeecccc8888UL) ) + goto fail; + printf("okay\n"); + + printf("%-40s", "Testing lkgs 2(%rdx)..."); + instr[0] = 0xf2; instr[1] = 0x0f; instr[2] = 0x00; instr[3] = 0x72; instr[4] = 0x02; + regs.eip = (unsigned long)&instr[0]; + regs.edx = (unsigned long)res; + res[0] = 0x00004444; + res[1] = 0x8888cccc; + i = cpu_policy.extd.nscb; cpu_policy.extd.nscb = true; /* for AMD */ + rc = x86_emulate(&ctxt, &emulops); + if ( (rc != X86EMUL_OKAY) || + (regs.eip != (unsigned long)&instr[5]) || + (gs_base != 0x0000111122224444UL) || + gs_base_shadow ) + goto fail; + + cpu_policy.extd.nscb = i; + emulops.write_segment = NULL; + emulops.write_msr = NULL; #endif printf("okay\n"); --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -85,6 +85,7 @@ bool emul_test_init(void) cpu_policy.feat.invpcid = true; cpu_policy.feat.adx = true; cpu_policy.feat.rdpid = true; + cpu_policy.feat.lkgs = true; cpu_policy.feat.wrmsrns = true; cpu_policy.extd.clzero = true; --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -745,8 +745,12 @@ decode_twobyte(struct x86_emulate_state case 0: s->desc |= DstMem | SrcImplicit | Mov; break; + case 6: + if ( !(s->modrm_reg & 1) && mode_64bit() ) + { case 2: case 4: - s->desc |= SrcMem16; + s->desc |= SrcMem16; + } break; } break; --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -609,6 +609,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) #define vcpu_has_cmpccxadd() (ctxt->cpuid->feat.cmpccxadd) +#define vcpu_has_lkgs() (ctxt->cpuid->feat.lkgs) #define vcpu_has_wrmsrns() (ctxt->cpuid->feat.wrmsrns) #define vcpu_has_avx_ifma() (ctxt->cpuid->feat.avx_ifma) #define vcpu_has_avx_vnni_int8() (ctxt->cpuid->feat.avx_vnni_int8) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -2899,8 +2899,37 @@ x86_emulate( break; } break; - default: - generate_exception_if(true, X86_EXC_UD); + + case 6: /* lkgs */ + generate_exception_if((modrm_reg & 1) || vex.pfx != vex_f2, + X86_EXC_UD); + generate_exception_if(!mode_64bit() || !mode_ring0(), X86_EXC_UD); + vcpu_must_have(lkgs); + fail_if(!ops->read_msr || !ops->write_segment || !ops->write_msr); + if ( (rc = ops->read_msr(MSR_SHADOW_GS_BASE, &msr_val, + ctxt)) != X86EMUL_OKAY || + (rc = ops->read_msr(MSR_GS_BASE, &sreg.base, + ctxt)) != X86EMUL_OKAY ) + goto done; + dst.orig_val = sreg.base; /* Preserve current GS Base. */ + if ( (rc = protmode_load_seg(x86_seg_gs, src.val, false, &sreg, + ctxt, ops)) != X86EMUL_OKAY ) + goto done; + /* Write new base into SHADOW_GS, zero extended from GDT/LDT. */ + if ( (rc = ops->write_msr(MSR_SHADOW_GS_BASE, sreg.base, + ctxt, false)) != X86EMUL_OKAY || + (sreg.base = dst.orig_val, /* Reinstate original GS Base. */ + (rc = ops->write_segment(x86_seg_gs, &sreg, + ctxt)) != X86EMUL_OKAY) ) + { + /* + * In real hardware, access to the registers cannot fail. It + * is an error in Xen if the writes fail. + */ + ASSERT_UNREACHABLE(); + x86_emul_reset_event(ctxt); + generate_exception(X86_EXC_DF, 0); + } break; } break; --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -282,7 +282,8 @@ def crunch_numbers(state): # superpages, PCID and PKU are only available in 4 level paging. # NO_LMSL indicates the absense of Long Mode Segment Limits, which # have been dropped in hardware. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD], + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD, + LKGS], # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776694642-465748B7-649D5572/10/73395122804 X-purgate-type: spam X-purgate-size: 2066 On 10.04.2026 17:54, Oleksii Kurochko wrote: > The function is implemented out-of-line rather than as a static inline, > to avoid header ordering issues where struct domain is incomplete when > asm/p2m.h is included, leading to build failures: > In file included from ./arch/riscv/include/asm/domain.h:10, > from ./include/xen/domain.h:16, > from ./include/xen/sched.h:11, > from ./include/xen/event.h:12, > from common/cpu.c:3: > ./arch/riscv/include/asm/p2m.h: In function 'get_page_from_gfn': > ./arch/riscv/include/asm/p2m.h:50:33: error: invalid use of undefined type 'struct domain' > 50 | #define p2m_get_hostp2m(d) (&(d)->arch.p2m) > | ^~ > ./arch/riscv/include/asm/p2m.h:180:38: note: in expansion of macro 'p2m_get_hostp2m' > 180 | return p2m_get_page_from_gfn(p2m_get_hostp2m(d), _gfn(gfn), t); > | ^~~~~~~~~~~~~~~ > make[2]: *** [Rules.mk:253: common/cpu.o] Error 1 > make[1]: *** [build.mk:72: common] Error 2 > make: *** [Makefile:623: xen] Error 2 I still think this can and preferably would be sorted, but for now this is good enough. > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich with a comment adjustment: > --- a/xen/arch/riscv/p2m.c > +++ b/xen/arch/riscv/p2m.c > @@ -1534,3 +1534,16 @@ void p2m_handle_vmenter(void) > * won't be reused until need_flush is set to true. > */ > } > + > +struct page_info *get_page_from_gfn(struct domain *d, unsigned long gfn, > + p2m_type_t *t, p2m_query_t q) > +{ > + /* > + * system domains are domains which doesn't have p2m translation tables, > + * so they can't use p2m_get_page_from_gfn() and extra care should be > + * done for them. > + */ This violates style and has two grammar issues. I'll take care of this when committing. Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:22:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286048.1567177 (Exim 4.92) (envelope-from ) id 1wEpWX-0002Xa-2q; Mon, 20 Apr 2026 14:22:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286048.1567177; Mon, 20 Apr 2026 14:22:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWX-0002XT-0F; Mon, 20 Apr 2026 14:22:53 +0000 Received: by outflank-mailman (input) for mailman id 1286048; Mon, 20 Apr 2026 14:22:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWW-0002Oa-9c for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWV-000Q5n-Mh for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:51 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636b5-e002-0a2a0a5209dd-0a2a450bd802-14 for ; Mon, 20 Apr 2026 16:22:51 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636ba-212f-0a2a450b0019-d98c6eacb892-1 for ; Mon, 20 Apr 2026 16:22:51 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B8A516F3; Mon, 20 Apr 2026 07:22:44 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B51A73F7B4; Mon, 20 Apr 2026 07:22:48 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694970; bh=+vsui9ontMRbImpr24T712HFqgwztKghYeAs6axxQu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m38uLElW2SN88vFJmSSpwqVV8dKLr9Lbp4AxlgCsc1zUQDEzF+Umb/3wGlILHWY/I M09xu8MndOKOFF44+ps7FUj+5dISiq8ySeIgEdEqeghFnWq0JjNtUUnlyDnCZxzKo2 G7i66FNS51Vz5RLkuDkyLKNckEVha/8ScqSngKfE= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Mon, 20 Apr 2026 15:22:23 +0100 Message-Id: <20260420142224.1802911-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776694971-0636CF3B-4468D4B2/0/0 X-purgate-type: clean X-purgate-size: 13636 From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 for Armv8-R architecture: MPU or MMU, the former is the default if the property is not passed. The check and setting of this new input parameter for the guest configuration is performed in arch_domain_create() instead of the more usual arch_sanitise_domain_config() because the former has access to the Xen internal guest creation flags which are required to ensure PMSA can work (domain requires static allocation and direct mapping). The property is valid only when used on MPU systems and will result in a panic on MMU ones. Bumped XEN_DOMCTL_INTERFACE_VERSION because of the new domctl input parameter. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v4: - Rework the patch to have the v8r_el1_msa input parameter more enclosed in the Armv8-A (mmu)/Armv8-R (mpu) space. v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 14 ++++ xen/arch/arm/dom0less-build.c | 3 + xen/arch/arm/domain.c | 4 ++ xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/domain_build.h | 8 +++ xen/arch/arm/include/asm/mmu/domain-build.h | 46 +++++++++++++ xen/arch/arm/include/asm/mpu.h | 5 ++ xen/arch/arm/include/asm/mpu/domain-build.h | 27 ++++++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm32/mm.c | 5 ++ xen/arch/arm/mpu/arm64/mm.c | 5 ++ xen/arch/arm/mpu/domain-build.c | 76 +++++++++++++++++++++ xen/include/public/arch-arm.h | 7 ++ xen/include/public/domctl.h | 4 +- 14 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 xen/arch/arm/include/asm/mmu/domain-build.h create mode 100644 xen/arch/arm/include/asm/mpu/domain-build.h create mode 100644 xen/arch/arm/mpu/domain-build.c diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt index 977b4286082f..c3f484a3b01a 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,20 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems, a domain + should use PMSAv8 (MPU) at EL1 or VMSAv8 (MMU) at EL1. + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. + + - "mpu" + Enables PMSAv8 at EL1. This is the default behaviour when the property is + not passed. This configuration requires static allocation (xen,static-mem) + and direct mapping (direct-map). + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f0256f9d825 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #ifdef CONFIG_VGICV2 @@ -322,6 +323,8 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); + arch_dt_v8r_el1_msa_parse(node, d_cfg); + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq = GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..dfa7ace1141b 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -725,6 +726,9 @@ int arch_domain_create(struct domain *d, if ( (rc = sci_domain_init(d, config)) != 0 ) goto fail; + if ( (rc = arch_set_v8r_el1_msa(d, config, flags)) != 0 ) + goto fail; + return 0; fail: diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..4a3fb825962b 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -128,6 +128,10 @@ struct arch_domain #endif struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; struct arch_vcpu diff --git a/xen/arch/arm/include/asm/domain_build.h b/xen/arch/arm/include/asm/domain_build.h index 6674dac5e2f8..921d6f98f4f4 100644 --- a/xen/arch/arm/include/asm/domain_build.h +++ b/xen/arch/arm/include/asm/domain_build.h @@ -4,6 +4,14 @@ #include #include +#if defined(CONFIG_MMU) +#include +#elif defined(CONFIG_MPU) +#include +#else +# error "Unknown memory management layout" +#endif + typedef __be32 gic_interrupt_t[3]; int make_psci_node(void *fdt); void evtchn_allocate(struct domain *d); diff --git a/xen/arch/arm/include/asm/mmu/domain-build.h b/xen/arch/arm/include/asm/mmu/domain-build.h new file mode 100644 index 000000000000..3e0d9a6a2a08 --- /dev/null +++ b/xen/arch/arm/include/asm/mmu/domain-build.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MMU_DOMAIN_BUILD_H__ +#define __ARM_MMU_DOMAIN_BUILD_H__ + +#include +#include +#include +#include +#include + +static inline +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg) +{ + const char *v8r_el1_msa; + + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) + panic("'v8r_el1_msa' property found, but CONFIG_MPU not selected\n"); +} + +static inline +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags) +{ + if ( config->arch.v8r_el1_msa ) + { + dprintk(XENLOG_INFO, + "arch.v8r_el1_msa set, but CONFIG_MPU not selected\n"); + return -EINVAL; + } + + return 0; +} + +#endif /* __ARM_MMU_DOMAIN_BUILD_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 72fa5b00b861..8a8c01086206 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -27,6 +27,11 @@ #ifndef __ASSEMBLER__ +/* + * Utility function to determine if an Armv8-R processor supports VMSA. + */ +bool has_v8r_vmsa_support(void); + /* * Set base address of MPU protection region. * diff --git a/xen/arch/arm/include/asm/mpu/domain-build.h b/xen/arch/arm/include/asm/mpu/domain-build.h new file mode 100644 index 000000000000..463cd85b5b7e --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/domain-build.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_DOMAIN_BUILD_H__ +#define __ARM_MPU_DOMAIN_BUILD_H__ + +#include +#include +#include +#include + +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg); + +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags); + +#endif /* __ARM_MPU_DOMAIN_BUILD_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 3327fadd5d0e..e3997e41b81b 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_ARM_32) += arm32/ obj-$(CONFIG_ARM_64) += arm64/ +obj-y += domain-build.o obj-y += domain-page.o obj-y += mm.o obj-y += p2m.o diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..5eaeb3400e6c 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -38,6 +38,11 @@ break; \ } +bool has_v8r_vmsa_support(void) +{ + return false; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions through * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..b07e729a7d05 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -32,6 +32,11 @@ break; \ } +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac == MM64_MSA_FRAC_VMSA_SUPPORT; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions through * registers: diff --git a/xen/arch/arm/mpu/domain-build.c b/xen/arch/arm/mpu/domain-build.c new file mode 100644 index 000000000000..1bdd0ffedebb --- /dev/null +++ b/xen/arch/arm/mpu/domain-build.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __init arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg) +{ + const char *v8r_el1_msa; + + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; + + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) + { + if ( !strcmp(v8r_el1_msa, "mmu") ) + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA; + else if ( !strcmp(v8r_el1_msa, "mpu") ) + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA; + else + panic("Invalid device tree option for v8r_el1_msa\n"); + } +} + +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags) +{ + switch ( config->arch.v8r_el1_msa ) + { + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE: + fallthrough; + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA: + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + { + dprintk(XENLOG_INFO, + "PMSA is not valid for domain without static allocation and direct map (v8r_el1_msa)\n"); + return -EINVAL; + } + break; + + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA: + if ( !has_v8r_vmsa_support() ) + { + dprintk(XENLOG_INFO, + "Platform does not support VMSA at EL1 (v8r_el1_msa)\n"); + return -EINVAL; + } + break; + + default: + dprintk(XENLOG_INFO, "Unsupported arch.v8r_el1_msa value (%u)\n", + config->arch.v8r_el1_msa); + return -EINVAL; + } + + d->arch.v8r_el1_msa = config->arch.v8r_el1_msa; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..7d6f87e8b2b1 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -330,6 +330,10 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE 0 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 + struct xen_arch_domainconfig { /* IN/OUT */ uint8_t gic_version; @@ -355,6 +359,9 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; + uint16_t pad; }; #endif /* __XEN__ || __XEN_TOOLS__ */ diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..23124547f347 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -30,9 +30,9 @@ * fields) don't require a change of the version. * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! * - * Last version bump: Xen 4.19 + * Last version bump: Xen 4.22 */ -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation. -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:22:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286046.1567169 (Exim 4.92) (envelope-from ) id 1wEpWV-0002KP-UB; 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a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694968; bh=qYmTbaJ+SsNtBEDJGVlBV6iD643KjLqETko4igFDlkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AHi1STTNBpVKXfpv079dXbuoiWoVd8MqQlYxAzKxc3yXlPOdOgL0bBhpEDROFCA7g Um92Yg56HabhO1ka3LIKtPEWWz4oJELcwCNPjzr4NFgXX5WYX5FtDf7ZZ+KVRUd+dn tdnq/F12nPXai/UNox5EUWwbYyUIoSsqHS8tPnIY= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v4 1/3] arm/mpu: implement setup_virt_paging for MPU systems Date: Mon, 20 Apr 2026 15:22:22 +0100 Message-Id: <20260420142224.1802911-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776694969-C0965DB1-E750CBF4/0/0 X-purgate-type: clean X-purgate-size: 7646 From: Penny Zheng Implement setup_virt_paging for AArch64 MPU systems, taking care of stage 2 address translation regime, IPA bits, supported VMID length configuration and VTCR_EL2/VSTCR_EL2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey --- v4: - Fixed typo in the comments - Fixed typo in the commit title and message - moved p2m_vmid_allocator_init() after write of VTCR_EL2 - Fixed printf format specifier %d -> %u v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Separate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..a39a1fc38946 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ #include #include +#include #include void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 = READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] = {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits == PA bits, compare against PA size. + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits = pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identify the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa != MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b0010. */ + if ( (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &= ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation output + * address space to access the Secure PA space as Armv8-R only implements + * secure state. + */ + vtcr_el2 &= ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16-bits VMID only if all cores + * are supporting it. + * + * Set the VS bit only if 16 bit VMID is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |= VTCR_VS; + max_vmid = MAX_VMID_16_BIT; + } + else + vtcr_el2 &= ~VTCR_VS; + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + p2m_vmid_allocator_init(); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address space. + * To make sure that all stage 2 translations for the Secure PA space access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if they + * are different, we set SC bit 1. + */ + vstcr_el2 &= ~VSTCR_EL2_SA; + vstcr_el2 |= VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %u-bit IPA with %u-bit PA and %u-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + ( MAX_VMID == MAX_VMID_16_BIT ) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"); } /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ #define VTCR_RES1 (_AC(1,UL)<<31) +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ extern register_t __cpu_logical_map[]; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:22:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286049.1567186 (Exim 4.92) (envelope-from ) id 1wEpWY-0002nC-Ew; Mon, 20 Apr 2026 14:22:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286049.1567186; Mon, 20 Apr 2026 14:22:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWY-0002mz-9p; Mon, 20 Apr 2026 14:22:54 +0000 Received: by outflank-mailman (input) for mailman id 1286049; Mon, 20 Apr 2026 14:22:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWX-0002XS-5V for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWW-000Q5n-IQ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:52 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636ba-e002-0a2a0a5209dd-0a2a4504b0be-2 for ; Mon, 20 Apr 2026 16:22:52 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636bb-1dec-0a2a45040019-d98c6eaccfd2-1 for ; Mon, 20 Apr 2026 16:22:52 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDFB31516; Mon, 20 Apr 2026 07:22:45 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 748B73F7B4; Mon, 20 Apr 2026 07:22:50 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694971; bh=2jwMTZ96/fznHmHt78iGUnOWdXQ8B7ZjteeUmUTDvnA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RNnZtM1TxQlcuIC9URWpVNKgROgJki95Skz6ZfJudAVau0lSSZCsDUBXG3viAE0bz GiPdbBTqkaJJ7FbK0onORaAiUtN8OyBrqA8dLXm46qjknqkEqeYdW3Hz8qVvu0j1/4 /bIBrdlcYro1k2NkiruLZiJA3/hny4T7qG4Rlezo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v4 3/3] arm/mpu: Implement p2m tables Date: Mon, 20 Apr 2026 15:22:24 +0100 Message-Id: <20260420142224.1802911-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776694972-4B96A3FF-F69A46E1/0/0 X-purgate-type: clean X-purgate-size: 5745 From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v4: - no changes v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 12 +++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 78 ++++++++++++++++++++++++++-- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ #define MPU_REGION_RES0 (0xFFFFULL << 48) +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/mpu/p2m.h index e46d9e757a1d..39fc0c944916 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,20 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ +#include +#include +#include + struct p2m_domain; +/* + * The architecture allows at most 255 EL2 MPU memory regions. The size of the + * MPU structure entry (pr_t) is 32 Bytes on AArch64 (requiring two 4KB pages) + * and 16 bytes on AArch32 (requiring one 4KB page). + */ +#define P2M_ROOT_PAGES DIV_ROUND_UP(255 * sizeof(pr_t), PAGE_SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..ec8f630acd90 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,69 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + void *table = alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping table\n", + d); + return -ENOMEM; + } + + p2m->root = virt_to_page(table); + + for (int i = 0; i < P2M_ROOT_PAGES; i++) + clear_page(page_to_virt(p2m->root + i)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m = p2m_get_hostp2m(d); + int rc = 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid = INVALID_VMID; + p2m->max_mapped_gfn = _gfn(0); + p2m->lowest_mapped_gfn = _gfn(ULONG_MAX); + + p2m->default_access = p2m_access_rwx; + /* mem_access is NOT supported in MPU system. */ + p2m->mem_access_enabled = false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPUS); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU_ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] = INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so that + * p2m_teardown() and related functions know to do something. + */ + p2m->domain = d; + + rc = p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr = ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + rc = p2m_alloc_table(d); + if ( rc ) + { + p2m_free_vmid(d); + return rc; + } + + return 0; } void p2m_save_state(struct vcpu *p) @@ -46,7 +105,20 @@ void p2m_restore_state(struct vcpu *n) void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m = p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root = NULL; + + p2m_free_vmid(d); + + p2m->domain = NULL; } bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:22:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286045.1567159 (Exim 4.92) (envelope-from ) id 1wEpWU-00027P-Ma; Mon, 20 Apr 2026 14:22:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286045.1567159; Mon, 20 Apr 2026 14:22:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWU-00027I-K5; Mon, 20 Apr 2026 14:22:50 +0000 Received: by outflank-mailman (input) for mailman id 1286045; Mon, 20 Apr 2026 14:22:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWT-000273-28 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWS-007nwH-BQ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:48 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636a9-5cb7-0a2a0a5109dd-0a2a4503ade2-42 for ; Mon, 20 Apr 2026 16:22:48 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636b7-672d-0a2a45030019-d98c6eacb866-1 for ; Mon, 20 Apr 2026 16:22:47 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3FED51516; Mon, 20 Apr 2026 07:22:41 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71F023F7B4; Mon, 20 Apr 2026 07:22:45 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694966; bh=uEiDQ0S/JRioWm+0hL1oiuLwlrOvukDwyNsY0rQwBYU=; h=From:To:Cc:Subject:Date:From; b=RBeHS28SayxivulRAXgeGaN2phri66YlWOlzJzxr548TvJOXY6beXc8qTibRzPuJS K39hakzurB8mK3AVy0PxuPKQDKzVbf2FR1g7AiH8RmMBFff1bjIgcwytQE8zIZMLNZ NqSY/ppo3SYR969pRrBCN5fXLSXlGKgoSpGpneg0= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Oleksii Kurochko" Subject: [PATCH v4 0/3] Fifth MPU Series Date: Mon, 20 Apr 2026 15:22:21 +0100 Message-Id: <20260420142224.1802911-1-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776694968-2AF62938-73E8B252/0/0 X-purgate-type: clean X-purgate-size: 2019 This series continues to further the ongoing work to introduce support for MPU systems in Xen. The patches in this series aim to implement MPU specific p2m functions. This serie is based on staging 99912d346009fda1e7fb1510c9501fbab17e92a0. Harry Ramsey (2): arm/mpu: Introduce `v8r_el1_msa` device tree property for domains arm/mpu: Implement p2m tables Penny Zheng (1): arm/mpu: implement setup_virt_paging for MPU systems docs/misc/arm/device-tree/booting.txt | 14 ++++ xen/arch/arm/arm64/mpu/p2m.c | 80 ++++++++++++++++++++- xen/arch/arm/dom0less-build.c | 3 + xen/arch/arm/domain.c | 4 ++ xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/domain_build.h | 8 +++ xen/arch/arm/include/asm/mmu/domain-build.h | 46 ++++++++++++ xen/arch/arm/include/asm/mpu.h | 5 ++ xen/arch/arm/include/asm/mpu/domain-build.h | 27 +++++++ xen/arch/arm/include/asm/mpu/p2m.h | 12 ++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/include/asm/processor.h | 8 +++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm32/mm.c | 5 ++ xen/arch/arm/mpu/arm64/mm.c | 5 ++ xen/arch/arm/mpu/domain-build.c | 76 ++++++++++++++++++++ xen/arch/arm/mpu/p2m.c | 78 +++++++++++++++++++- xen/include/public/arch-arm.h | 7 ++ xen/include/public/domctl.h | 4 +- 23 files changed, 404 insertions(+), 9 deletions(-) create mode 100644 xen/arch/arm/include/asm/mmu/domain-build.h create mode 100644 xen/arch/arm/include/asm/mpu/domain-build.h create mode 100644 xen/arch/arm/mpu/domain-build.c -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286085.1567195 (Exim 4.92) (envelope-from ) id 1wEpZ9-0004DV-Qw; Mon, 20 Apr 2026 14:25:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286085.1567195; Mon, 20 Apr 2026 14:25:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZ9-0004DN-O0; Mon, 20 Apr 2026 14:25:35 +0000 Received: by outflank-mailman (input) for mailman id 1286085; Mon, 20 Apr 2026 14:25:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZ8-0004DG-5Y for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZ7-0049I1-Id for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:33 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6375a-e002-0a2a0a5209dd-0a2a450481ee-10 for ; Mon, 20 Apr 2026 16:25:33 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e6375c-1dec-0a2a45040019-d98c6eacb83e-1 for ; Mon, 20 Apr 2026 16:25:33 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9E7D61516; Mon, 20 Apr 2026 07:25:26 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 423B13F7B4; Mon, 20 Apr 2026 07:25:31 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695132; bh=msE5zKqdYroR2i7+BMMRv2AgU+EIZ5jE7RxEL1s5uwo=; h=From:To:Cc:Subject:Date:From; b=M0lqefgAbq4Tm7Sx10KJ8putI+ayHK52E6dS8/S7b0fHKcukS5YSj1VONT4hcFn5s qEvOiBh+R1yDiUCrd+pyyuGNyXRE4qUtI7bNdjwrM1/NP0XL49iBWRL7z4ip17KNoj +wDoVXoDcc16yXwCKndkwp11DWDZAwUHbz2pdc4M= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , "Oleksii Kurochko" Subject: [PATCH 0/8] Armv8-R AArch64 MPU support (single core) Date: Mon, 20 Apr 2026 15:25:16 +0100 Message-Id: <20260420142524.1804073-1-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776695133-324733FF-C652B545/0/0 X-purgate-type: clean X-purgate-size: 2291 Hi, this serie complete the support for Armv8-R AArch64 MPU support for dom0less DomU boot on single core, it also build for Armv8-R AArch32 but the support is not complete. The serie is based on another serie in the mailing list: "Fifth MPU Series". I've spoken with Oleksii and the Arm maintainer to have the possibilty to have this on the Xen release, of course provided that maintainers have enough bandwidth and depending on the priority of the series to be in. Asking for Oleksii Ack for the release, the changes in this serie are mostly related to MPU apart from few patches that touches common Arm code. Luca Fancellu (2): arm/mpu: Save/restore guest EL1 MPU-related context arm/mpu: Save/restore VTCR_EL2 on vCPU context switch Penny Zheng (6): xen/arm: Implement p2m_set_entry for MPU systems xen/arm: Implement p2m_get_entry for MPU systems xen/mpu: enable device passthrough in MPU system arm/mpu: Support vCPU context switch on MPU systems xen/arm: enable MMIO region trap in MPU system xen/arm: dump debug message in MPU system xen/arch/arm/arm64/mpu/p2m.c | 17 ++ xen/arch/arm/domain.c | 51 +++- xen/arch/arm/include/asm/arm32/mpu.h | 3 +- xen/arch/arm/include/asm/arm64/mpu.h | 3 +- xen/arch/arm/include/asm/domain.h | 10 + xen/arch/arm/include/asm/mm.h | 3 + xen/arch/arm/include/asm/mmu/domain-build.h | 2 + xen/arch/arm/include/asm/mmu/mm.h | 12 + xen/arch/arm/include/asm/mpu.h | 3 + xen/arch/arm/include/asm/mpu/cpregs.h | 7 + xen/arch/arm/include/asm/mpu/domain-build.h | 6 + xen/arch/arm/include/asm/mpu/mm.h | 13 +- xen/arch/arm/include/asm/mpu/p2m.h | 25 ++ xen/arch/arm/include/asm/p2m.h | 3 + xen/arch/arm/mpu/arm32/mm.c | 10 + xen/arch/arm/mpu/arm64/mm.c | 136 +++++++++ xen/arch/arm/mpu/domain-build.c | 17 ++ xen/arch/arm/mpu/mm.c | 101 +++++-- xen/arch/arm/mpu/p2m.c | 295 +++++++++++++++++++- xen/arch/arm/traps.c | 91 ++++-- 20 files changed, 739 insertions(+), 69 deletions(-) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286086.1567203 (Exim 4.92) (envelope-from ) id 1wEpZC-0004RK-0C; Mon, 20 Apr 2026 14:25:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286086.1567203; Mon, 20 Apr 2026 14:25:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZB-0004RD-TT; Mon, 20 Apr 2026 14:25:37 +0000 Received: by outflank-mailman (input) for mailman id 1286086; Mon, 20 Apr 2026 14:25:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZ9-0004DT-V4 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZ9-00DjKj-BW for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:35 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e63750-bab6-0a2a0a5309dd-0a2a450a9acc-16 for ; Mon, 20 Apr 2026 16:25:35 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e6375e-56b3-0a2a450a0019-d98c6eaccd08-1 for ; Mon, 20 Apr 2026 16:25:35 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E7A316F2; Mon, 20 Apr 2026 07:25:28 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 769003F7B4; Mon, 20 Apr 2026 07:25:32 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695133; bh=J3CyMkSY0KMV9Fw732pi6w6qLPzHaJTo8ZwxErzPiWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e9xVvGHL8pn8PbTX3/4XMRA1Ddaaa52XlXWInaCUNZoMlcG0PmKjboXUKjXZsIevC ktjQHQGMMSq7GJgB5qJXYwJN0p+niIbVJn8mqTLdQM2aa5NLKSekU6SmyqZY3f0fXQ bGDcDjkoQtI2ahVJuxUKu1KR2fvLaAYUgAlQ0Ni4= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH 1/8] xen/arm: Implement p2m_set_entry for MPU systems Date: Mon, 20 Apr 2026 15:25:17 +0100 Message-Id: <20260420142524.1804073-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776695135-CE36B8B7-645A68D7/0/0 X-purgate-type: clean X-purgate-size: 12640 From: Penny Zheng Implement the function `p2m_set_entry`, which is responsible for inserting a new entry into the p2m tables, for MPU systems. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey --- xen/arch/arm/include/asm/arm32/mpu.h | 3 +- xen/arch/arm/include/asm/arm64/mpu.h | 3 +- xen/arch/arm/include/asm/mpu/mm.h | 3 +- xen/arch/arm/include/asm/mpu/p2m.h | 10 +++ xen/arch/arm/include/asm/p2m.h | 3 + xen/arch/arm/mpu/mm.c | 43 ++++++---- xen/arch/arm/mpu/p2m.c | 123 ++++++++++++++++++++++++++- 7 files changed, 167 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h index d565230f84ee..ab58df079920 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -42,7 +42,8 @@ typedef struct { prbar_t prbar; prlar_t prlar; uint8_t refcount; - uint8_t pad[7]; /* Pad structure to 16 Bytes */ + uint8_t p2m_type; + uint8_t pad[6]; /* Pad structure to 16 Bytes */ } pr_t; #endif /* __ASSEMBLER__ */ diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h index 8b86a03fee44..c82624f0f2cf 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -41,7 +41,8 @@ typedef struct { prbar_t prbar; prlar_t prlar; uint8_t refcount; - uint8_t pad[15]; /* Pad structure to 32 Bytes */ + uint8_t p2m_type; + uint8_t pad[14]; /* Pad structure to 32 Bytes */ } pr_t; #endif /* __ASSEMBLER__ */ diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h index 1b5ffa5b644d..24bffdee4fb6 100644 --- a/xen/arch/arm/include/asm/mpu/mm.h +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -75,9 +75,10 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel); * @param base Base address of the range to map (inclusive). * @param limit Limit address of the range to map (exclusive). * @param flags Flags for the memory range to map. + * @param p2m True for a stage 2 mapping, otherwise False. * @return 0 on success, negative on error. */ -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags); +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags, bool p2m); /* * Creates a pr_t structure describing a protection region. diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/mpu/p2m.h index 39fc0c944916..b9c7be2d9dcc 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -21,6 +21,16 @@ static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} +static inline void region_set_p2m(pr_t *pr, p2m_type_t p2m_type) +{ + pr->p2m_type = p2m_type; +} + +static inline p2m_type_t region_get_p2m(pr_t *pr) +{ + return pr->p2m_type; +} + #endif /* __ARM_MPU_P2M_H__ */ /* diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index ed1b6dd40f40..43b383885da0 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -54,6 +54,9 @@ struct p2m_domain { #else /* Current Virtualization System Control Register for the p2m */ register_t vsctlr; + + /* Number of MPU memory regions in P2M MPU memory mapping table. */ + uint8_t nr_regions; #endif /* Highest guest frame that's ever been mapped in the p2m */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index aff88bd3a9c1..4ee58ded5ad6 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -317,13 +317,14 @@ static int xen_mpumap_free_entry(uint8_t idx, int region_found_type) * Update the entry in the MPU memory region mapping table (xen_mpumap) for the * given memory range and flags, creating one if none exists. * - * @param base Base address (inclusive). - * @param limit Limit address (exclusive). - * @param flags Region attributes (a combination of PAGE_HYPERVISOR_XXX) + * @param base Base address (inclusive). + * @param limit Limit address (exclusive). + * @param flags Region attributes (a combination of PAGE_HYPERVISOR_XXX) + * @param p2m True for a stage 2 mapping, otherwise False. * @return 0 on success, otherwise negative on error. */ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit, - unsigned int flags) + unsigned int flags, bool p2m) { bool flags_has_page_present; uint8_t idx; @@ -399,6 +400,8 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit, return -ENOENT; xen_mpumap[idx] = pr_of_addr(base, limit, flags); + /* AP[0] always 1 for stage 2 */ + xen_mpumap[idx].prbar.reg.ap_0 = (p2m ? 1 : 0); write_protection_region(&xen_mpumap[idx], idx); } @@ -418,33 +421,41 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit, return 0; } -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags) +int check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags) { - int rc; - if ( flags_has_rwx(flags) ) { printk("Mappings should not be both Writeable and Executable\n"); - return -EINVAL; + return false; } if ( base >= limit ) { printk("Base address %#"PRIpaddr" must be smaller than limit address %#"PRIpaddr"\n", base, limit); - return -EINVAL; + return false; } if ( !IS_ALIGNED(base, PAGE_SIZE) || !IS_ALIGNED(limit, PAGE_SIZE) ) { printk("base address %#"PRIpaddr", or limit address %#"PRIpaddr" is not page aligned\n", base, limit); - return -EINVAL; + return false; } + return true; +} + +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags, bool p2m) +{ + int rc; + + if ( !check_mpu_mapping(base, limit, flags) ) + return -EINVAL; + spin_lock(&xen_mpumap_lock); - rc = xen_mpumap_update_entry(base, limit, flags); + rc = xen_mpumap_update_entry(base, limit, flags, p2m); if ( !rc ) context_sync_mpu(); @@ -459,7 +470,7 @@ int destroy_xen_mappings(unsigned long s, unsigned long e) ASSERT(IS_ALIGNED(e, PAGE_SIZE)); ASSERT(s < e); - return xen_mpumap_update(s, e, 0); + return xen_mpumap_update(s, e, 0, false); } int destroy_xen_mapping_containing(paddr_t s) @@ -499,7 +510,7 @@ int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns, unsigned int flags) { /* MPU systems have no translation, ma == va, so pass virt directly */ - return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags); + return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags, false); } /* @@ -520,7 +531,7 @@ void __init setup_mm_helper(void) paddr_t bank_end = bank_start + bank_size; /* Map static heap with one MPU protection region */ - if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) ) + if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR, false) ) panic("Failed to map static heap\n"); break; @@ -533,7 +544,7 @@ void __init setup_mm_helper(void) int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf) { - return xen_mpumap_update(s, e, nf); + return xen_mpumap_update(s, e, nf, false); } void dump_hyp_walk(vaddr_t addr) @@ -598,7 +609,7 @@ void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags) paddr_t start_pg = round_pgdown(start); paddr_t end_pg = round_pgup(start + len); - if ( xen_mpumap_update(start_pg, end_pg, flags) ) + if ( xen_mpumap_update(start_pg, end_pg, flags, false) ) return NULL; /* Mapped or already mapped */ diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index ec8f630acd90..4a8595b1b25e 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -8,12 +8,131 @@ #include #include #include +#include + +static inline unsigned int build_p2m_flags(p2m_type_t t) +{ + unsigned int flags = 0; + + BUILD_BUG_ON(p2m_max_real_type > (1 << 4)); + + switch ( t ) + { + case p2m_ram_rw: + /* Nothing to do, XN=0, RO=0 */ + break; + + case p2m_ram_ro: + flags |= _PAGE_RO; + break; + + case p2m_invalid: + flags |= _PAGE_XN | _PAGE_RO; + break; + + case p2m_max_real_type: + BUG(); + break; + + case p2m_mmio_direct_dev: + case p2m_mmio_direct_nc: + case p2m_mmio_direct_c: + case p2m_iommu_map_ro: + case p2m_iommu_map_rw: + case p2m_map_foreign_ro: + case p2m_map_foreign_rw: + case p2m_grant_map_ro: + case p2m_grant_map_rw: + panic(XENLOG_G_ERR "p2m: UNIMPLEMENTED p2m permission in MPU system\n"); + break; + } + + flags |= MT_NORMAL; + + return flags; +} + +/* + * Check whether guest memory region [`sgfn`, `sgfn` + `nr_gfns`) is mapped in + * mpumap `table`. + * + * If the memory region is mapped, `idx` is set to the index of the associated + * MPU memory region and 0 is returned. + * If the memory region is not mapped, -ENOENT is returned. + */ +static int is_gfns_mapped(pr_t *table, uint8_t nr_regions, gfn_t sgfn, + unsigned long nr_gfns, uint8_t *idx) +{ + paddr_t gbase = gfn_to_gaddr(sgfn); + paddr_t glimit = gfn_to_gaddr(gfn_add(sgfn, nr_gfns)); + int rc; + + rc = mpumap_contains_region(table, nr_regions, gbase, glimit, idx); + if ( MPUMAP_REGION_OVERLAP == rc ) + return -EINVAL; + + if ( MPUMAP_REGION_NOTFOUND == rc ) + return -ENOENT; + + return 0; +} + +static int __p2m_set_entry(struct p2m_domain *p2m, gfn_t sgfn, unsigned int nr, + mfn_t smfn, p2m_type_t t, p2m_access_t a) +{ + pr_t *table; + mfn_t emfn = mfn_add(smfn, nr); + unsigned int flags; + uint8_t idx = INVALID_REGION_IDX; + + /* + * In all cases other than when removing a mapping (mfn == MFN_INVALID), + * gfn == mfn on MPU systems. + */ + if ( !mfn_eq(smfn, INVALID_MFN) && gfn_x(sgfn) != mfn_x(smfn) ) + { + printk(XENLOG_G_ERR "Unable to map MFN %#"PRI_mfn" at %#"PRI_mfn"\n", + mfn_x(smfn), gfn_x(sgfn)); + return -EINVAL; + } + + table = (pr_t *)page_to_virt(p2m->root); + if ( !table ) + return -EINVAL; + + /* Already mapped */ + if ( is_gfns_mapped(table, p2m->nr_regions, sgfn, nr, &idx) != -ENOENT ) + { + printk(XENLOG_G_ERR "Unable to insert P2M MPU memory region %#"PRIpaddr"-%#"PRIpaddr"\n", + gfn_to_gaddr(sgfn), gfn_to_gaddr(gfn_add(sgfn, nr))); + return -EINVAL; + } + + flags = build_p2m_flags(t); + table[p2m->nr_regions] = pr_of_addr(mfn_to_maddr(smfn), + mfn_to_maddr(mfn_add(smfn, nr)), flags); + region_set_p2m(&table[p2m->nr_regions], t); + p2m->nr_regions++; + + p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn, _gfn(mfn_x(emfn))); + p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, _gfn(mfn_x(smfn))); + + return 0; +} int p2m_set_entry(struct p2m_domain *p2m, gfn_t sgfn, unsigned long nr, mfn_t smfn, p2m_type_t t, p2m_access_t a) { - BUG_ON("unimplemented"); - return -EINVAL; + /* + * Any reference taken by the P2M mappings (e.g. foreign mapping) will + * be dropped in relinquish_p2m_mapping(). As the P2M will still + * be accessible after, we need to prevent mapping to be added when the + * domain is dying. + */ + if ( unlikely(p2m->domain->is_dying) ) + return -ENOMEM; + + return __p2m_set_entry(p2m, sgfn, nr, smfn, t, a); } mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286087.1567212 (Exim 4.92) (envelope-from ) id 1wEpZD-0004fK-6Q; Mon, 20 Apr 2026 14:25:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286087.1567212; Mon, 20 Apr 2026 14:25:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZD-0004fB-3n; Mon, 20 Apr 2026 14:25:39 +0000 Received: by outflank-mailman (input) for mailman id 1286087; Mon, 20 Apr 2026 14:25:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZB-0004QW-9t for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZA-00DjKj-Mp for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:36 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6375d-bab6-0a2a0a5309dd-0a2a45039354-10 for ; Mon, 20 Apr 2026 16:25:36 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e6375f-672d-0a2a45030019-d98c6eac8c36-1 for ; Mon, 20 Apr 2026 16:25:36 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2A321516; Mon, 20 Apr 2026 07:25:29 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 373183F7B4; Mon, 20 Apr 2026 07:25:34 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695135; bh=iv//vNmwKiPVjQpsnbCcSAu2c4KT7uRXnN6HNwH7kRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C60P+blvO8zZ4OFaL3RS+PmAMBSRQ+8U/4URgbc7Ivw8aJfCG320v+cCN1h5wellN WH7EO3gbwuZ+/QAQRjQHbjkbxWgtfOdVToEJ5q+WlVQ09epfIhQTsnDiIT/hA9rTqi lS7LsTqjA7xVIZfOOQtxPtfidMEcipMIaXbeHYUE= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye Subject: [PATCH 2/8] xen/arm: Implement p2m_get_entry for MPU systems Date: Mon, 20 Apr 2026 15:25:18 +0100 Message-Id: <20260420142524.1804073-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776695136-485AB938-8FD3651C/0/0 X-purgate-type: clean X-purgate-size: 3903 From: Penny Zheng Implement the function p2m_get_entry for MPU systems, which is responsible for looking up an entry in the p2m table. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye --- xen/arch/arm/include/asm/mpu/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 76 ++++++++++++++++++++++++++++-- 2 files changed, 77 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/mpu/p2m.h index b9c7be2d9dcc..d0ec8a77a15a 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -31,6 +31,11 @@ static inline p2m_type_t region_get_p2m(pr_t *pr) return pr->p2m_type; } +static inline bool region_is_p2m_valid(pr_t *pr) +{ + return (pr->p2m_type != p2m_invalid); +} + #endif /* __ARM_MPU_P2M_H__ */ /* diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index 4a8595b1b25e..681717eacf37 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -135,11 +135,79 @@ int p2m_set_entry(struct p2m_domain *p2m, gfn_t sgfn, unsigned long nr, return __p2m_set_entry(p2m, sgfn, nr, smfn, t, a); } -mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t, - p2m_access_t *a, unsigned int *page_order, bool *valid) +/* + * Get the details of guest MPU memory region [gfn, gfn + nr_gfns). + * + * If the region is mapped, `t` is set to the p2m_type of the region and the + * starting MFN is returned. + * If the region is not mapped, INVALID_MFN is returned. + */ +static mfn_t p2m_get_mpu_region(struct p2m_domain *p2m, gfn_t gfn, + unsigned long nr_gfns, p2m_type_t *type, + bool *valid) { - BUG_ON("unimplemented"); - return INVALID_MFN; + pr_t *table = NULL; + pr_t *region = NULL; + uint8_t idx = INVALID_REGION_IDX; + gfn_t egfn = gfn_add(gfn, nr_gfns); + p2m_type_t optional_type = p2m_invalid; + bool optional_valid = false; + mfn_t ret = INVALID_MFN; + + ASSERT(p2m_is_locked(p2m)); + + /* + * Check if the ending gfn is higher than the highest the p2m map + * currently holds, or the starting gfn lower than the lowest it holds. + */ + if ( (gfn_x(egfn) > gfn_x(p2m->max_mapped_gfn)) || + (gfn_x(gfn) < gfn_x(p2m->lowest_mapped_gfn)) ) + goto out; + + table = (pr_t *)page_to_virt(p2m->root); + /* The table should always be non-NULL and is always present. */ + if ( !table ) + ASSERT_UNREACHABLE(); + + if ( is_gfns_mapped(table, p2m->nr_regions, gfn, nr_gfns, &idx) ) + goto out; + + region = &table[idx]; + if ( region_is_p2m_valid(region) ) + { + optional_type = region_get_p2m(region); + optional_valid = region_is_valid(region); + } + + /* Always GFN == MFN on MPU systems. */ + ret = _mfn(gfn_x(gfn)); + +out: + if ( type ) + *type = optional_type; + + if ( valid ) + *valid = optional_valid; + + return ret; +} + +/* + * Get the details of a given gfn. + * + * If the entry is present, the associated MFN will be returned and the + * p2m type gets filled up. + * If the entry is not present, INVALID_MFN will be returned + * + * The page_order is meaningless in MPU system, and we keep it here + * to be compatible with MMU system. + */ +mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, + p2m_type_t *t, p2m_access_t *a, + unsigned int *page_order, + bool *valid) +{ + return p2m_get_mpu_region(p2m, gfn, 1, t, valid); } void p2m_dump_info(struct domain *d) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286088.1567218 (Exim 4.92) (envelope-from ) id 1wEpZD-0004kf-IJ; Mon, 20 Apr 2026 14:25:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286088.1567218; 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Mon, 20 Apr 2026 16:25:37 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5300916F2; Mon, 20 Apr 2026 07:25:31 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B9A5C3F7B4; Mon, 20 Apr 2026 07:25:35 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695136; bh=zydSLBd6tN5qexvU/dn56PdspdQkRiPjvNZz/rLJDIo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S8XRPHeMliAOMeBJjotCrRwclZtbZiPa/8onyrk1Y/8K4Rnnxfk2/nqWtrOyPljAD cAREu9wb91FmJFuKP8XtSqPxOMMvHdzI6CtOGP6jhbEBE3qfyF7GB45Vra1iAz3sG4 jdd8cmIyTM/X1GqKEe6Q95TxRQ3zw1665byMvIoA= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen Subject: [PATCH 3/8] xen/mpu: enable device passthrough in MPU system Date: Mon, 20 Apr 2026 15:25:19 +0100 Message-Id: <20260420142524.1804073-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776695137-C1F6ADB1-76E20B7C/0/0 X-purgate-type: clean X-purgate-size: 1422 From: Penny Zheng In order to enable device passthrough in MPU system, we only need to provide p2m_mmio_direct_dev permission set up. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu --- xen/arch/arm/mpu/p2m.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index 681717eacf37..f2482237412b 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -13,6 +13,7 @@ static inline unsigned int build_p2m_flags(p2m_type_t t) { unsigned int flags = 0; + unsigned int attr_idx = MT_NORMAL; BUILD_BUG_ON(p2m_max_real_type > (1 << 4)); @@ -30,11 +31,15 @@ static inline unsigned int build_p2m_flags(p2m_type_t t) flags |= _PAGE_XN | _PAGE_RO; break; + case p2m_mmio_direct_dev: + flags |= _PAGE_XN; + attr_idx = MT_DEVICE_nGnRE; + break; + case p2m_max_real_type: BUG(); break; - case p2m_mmio_direct_dev: case p2m_mmio_direct_nc: case p2m_mmio_direct_c: case p2m_iommu_map_ro: @@ -47,7 +52,7 @@ static inline unsigned int build_p2m_flags(p2m_type_t t) break; } - flags |= MT_NORMAL; + flags |= attr_idx; return flags; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286089.1567231 (Exim 4.92) (envelope-from ) id 1wEpZF-0005Aa-Tb; Mon, 20 Apr 2026 14:25:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286089.1567231; Mon, 20 Apr 2026 14:25:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZF-0005AN-PF; Mon, 20 Apr 2026 14:25:41 +0000 Received: by outflank-mailman (input) for mailman id 1286089; Mon, 20 Apr 2026 14:25:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZE-00050r-Ee for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:40 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZD-00DjKj-RW for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:39 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6375d-bab6-0a2a0a5309dd-0a2a45039354-22 for ; Mon, 20 Apr 2026 16:25:39 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e63762-672d-0a2a45030019-d98c6eacb926-1 for ; Mon, 20 Apr 2026 16:25:39 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE7721758; Mon, 20 Apr 2026 07:25:32 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C8DB3F7B4; Mon, 20 Apr 2026 07:25:37 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695138; bh=qbZ9gSgQc0geGpYjPZJQGW1qcpmolTJxT0noQsC0zDg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A1kcUv112S14tZVWxdUhhSO4oRu3GAcs+kbCy1eOQNVfFvzWDYuiJ8OsPJHqMoWTY Qo+c22nZFCkqQ1EuoRA2VDf2weuePmyPvw1Z/Cee4sYHMbfqN1i1L+fM+Uk2JVgmjZ 2txr7iS7VplQUEYS5PD2NC86sqk6OIbs41R6HeOQ= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH 4/8] arm/mpu: Support vCPU context switch on MPU systems Date: Mon, 20 Apr 2026 15:25:20 +0100 Message-Id: <20260420142524.1804073-5-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776695139-29D7B938-47532FEC/0/0 X-purgate-type: clean X-purgate-size: 4660 From: Penny Zheng Implement the functions p2m_save_state and p2m_restore_state for MPU systems. Unlike on MMU systems, where we simply update VTTBR_EL2 with the incoming guest's p2m table on context switch, we have to disable the outgoing guest's p2m memory regions and enable the incoming guest's p2m memory regions. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey --- xen/arch/arm/include/asm/mpu/cpregs.h | 4 +++ xen/arch/arm/mpu/mm.c | 11 +++++-- xen/arch/arm/mpu/p2m.c | 47 +++++++++++++++++++++++++-- 3 files changed, 57 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h index 9f3b32acd79f..5a3d92cf5389 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -6,6 +6,9 @@ /* CP15 CR0: MPU Type Register */ #define HMPUIR p15,4,c0,c0,4 +/* CP15 CR2: Virtualization System Control register */ +#define VSCTLR p15,4,c2,c0,1 + /* CP15 CR6: Protection Region Enable Register */ #define HPRENR p15,4,c6,c1,1 @@ -88,6 +91,7 @@ #define PRENR_EL2 HPRENR #define PRLAR_EL2 HPRLAR #define PRSELR_EL2 HPRSELR +#define VSCTLR_EL2 VSCTLR #endif /* CONFIG_ARM_32 */ #endif /* __ARM_MPU_CPREGS_H */ diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 4ee58ded5ad6..5ed77355a5f9 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -421,9 +421,14 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit, return 0; } -int check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags) +static bool check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags, + bool p2m) { - if ( flags_has_rwx(flags) ) + /* + * Mappings should not be both Writeable and Executable, unless + * it is for guest P2M mapping. + */ + if ( flags_has_rwx(flags) && !p2m ) { printk("Mappings should not be both Writeable and Executable\n"); return false; @@ -450,7 +455,7 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags, bool p2m) { int rc; - if ( !check_mpu_mapping(base, limit, flags) ) + if ( !check_mpu_mapping(base, limit, flags, p2m) ) return -EINVAL; spin_lock(&xen_mpumap_lock); diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f2482237412b..bf87c65c106c 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -285,14 +285,57 @@ int p2m_init(struct domain *d) return 0; } +static int p2m_xenmpu_update(struct p2m_domain *p2m, bool online) +{ + pr_t *p2m_table; + unsigned int flags = online ? _PAGE_PRESENT : 0; + + p2m_table = (pr_t *)page_to_virt(p2m->root); + if ( !p2m_table ) + return -EINVAL; + + for ( unsigned int i = 0; i < p2m->nr_regions; i++ ) + { + paddr_t base = pr_get_base(&p2m_table[i]); + paddr_t limit = pr_get_limit(&p2m_table[i]) + 1; + unsigned int region_flags; + + region_flags = build_p2m_flags(region_get_p2m(&p2m_table[i])) | flags; + if ( xen_mpumap_update(base, limit, region_flags, true) ) + { + printk(XENLOG_G_ERR "Unable to update MPU memory mapping with P2M region %#"PRIpaddr"-%#"PRIpaddr"\n", + base, limit); + return -EINVAL; + } + } + + return 0; +} + +/* p2m_save_state and p2m_restore_state work in pair. */ void p2m_save_state(struct vcpu *p) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m = p2m_get_hostp2m(p->domain); + + p->arch.sctlr = READ_SYSREG(SCTLR_EL1); + + if ( p2m_xenmpu_update(p2m, false) ) + panic("Failed to offline P2M MPU memory mapping\n"); } void p2m_restore_state(struct vcpu *n) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m = p2m_get_hostp2m(n->domain); + uint8_t *last_vcpu_ran = &p2m->last_vcpu_ran[smp_processor_id()]; + + WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1); + WRITE_SYSREG(n->arch.hcr_el2, HCR_EL2); + + WRITE_SYSREG(p2m->vsctlr, VSCTLR_EL2); + if ( p2m_xenmpu_update(p2m, true) ) + panic("Failed to online P2M MPU memory mapping\n"); + + *last_vcpu_ran = n->vcpu_id; } void p2m_final_teardown(struct domain *d) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286091.1567240 (Exim 4.92) (envelope-from ) id 1wEpZH-0005Q6-6O; Mon, 20 Apr 2026 14:25:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286091.1567240; Mon, 20 Apr 2026 14:25:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZH-0005Px-27; Mon, 20 Apr 2026 14:25:43 +0000 Received: by outflank-mailman (input) for mailman id 1286091; Mon, 20 Apr 2026 14:25:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZF-0005A0-PH for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZF-00BFc6-3z for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:41 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e63753-2eae-0a2a0a5409dd-0a2a4506d4a6-46 for ; Mon, 20 Apr 2026 16:25:41 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e63764-7371-0a2a45060019-d98c6eacd072-1 for ; Mon, 20 Apr 2026 16:25:40 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E45E16F2; Mon, 20 Apr 2026 07:25:34 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C672D3F7B4; Mon, 20 Apr 2026 07:25:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695139; bh=7NVH7QgOJjbAjD26LtB1wsu/7pirLzYhzd1KxWkCV3U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uvOv0+BNiAmystHk22rMykjakgdlygV7SrTPltD8ab7waAmmUa31WhoZzlpJdGt7F I8PWWqtYNrHctgT7lPpZHHx7UG+2XfDVBJIeUy70KVcrhA/I/BTbpGJ8gIj67YRj4a b3CJU/1qMHWc1ZUjO2n+mciwDDplK3Y1c3rX3Rwo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen Subject: [PATCH 5/8] xen/arm: enable MMIO region trap in MPU system Date: Mon, 20 Apr 2026 15:25:21 +0100 Message-Id: <20260420142524.1804073-6-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776695141-91985D75-F6D49A57/0/0 X-purgate-type: clean X-purgate-size: 5352 From: Penny Zheng MMIO region traps, generating from insufficient access permissions, will lead to data abort with Permission Fault in MPU system. It is different with MMU system, which generates Translation Fault instead. We extract common codes for dealing with MMIO trap into a new helper do_mmio_trap_stage2_abort_guest(). Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu --- xen/arch/arm/traps.c | 83 ++++++++++++++++++++++++++++++-------------- 1 file changed, 56 insertions(+), 27 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0c01f37ad6b4..081bd2e51979 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1815,6 +1815,47 @@ static inline bool check_p2m(bool is_data, paddr_t gpa) return false; } +static int do_mmio_trap_stage2_abort_guest(struct cpu_user_regs *regs, + const union hsr hsr, + mmio_info_t *info, + vaddr_t gva, paddr_t gpa) +{ + enum io_state state; + + state = try_handle_mmio(regs, info); + + switch ( state ) + { + case IO_ABORT: + gdprintk(XENLOG_DEBUG, + "HSR=%#"PRIregister" pc=%#"PRIregister" gva=%#"PRIvaddr" gpa=%#"PRIpaddr"\n", + hsr.bits, regs->pc, gva, gpa); + inject_dabt_exception(regs, gva); + break; + case IO_HANDLED: + /* + * If the instruction was decoded and has executed successfully + * on the MMIO region, then Xen should execute the next part of + * the instruction. (for eg increment the rn if it is a + * post-indexing instruction. + */ + finalize_instr_emulation(&info->dabt_instr); + advance_pc(regs, hsr); + break; + case IO_RETRY: + /* finish later */ + break; + case IO_UNHANDLED: + /* IO unhandled, try another way to handle it. */ + return -EFAULT; + default: + ASSERT_UNREACHABLE(); + return -EFAULT; + } + + return 0; +} + static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, const union hsr hsr) { @@ -1829,7 +1870,6 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, uint8_t fsc = xabt.fsc & ~FSC_LL_MASK; bool is_data = (hsr.ec == HSR_EC_DATA_ABORT_LOWER_EL); mmio_info_t info; - enum io_state state; /* * If this bit has been set, it means that this stage-2 abort is caused @@ -1863,6 +1903,8 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, return; /* Try again */ } + info.gpa = gpa; + info.dabt = hsr.dabt; switch ( fsc ) { case FSC_FLT_PERM: @@ -1876,6 +1918,17 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, }; p2m_mem_access_check(gpa, gva, npfec); + +#if !defined(CONFIG_MMU) + /* + * MMIO region traps, generating from insufficient access permissions, + * will lead to data abort with Permission fault. + */ + if ( is_data && (do_mmio_trap_stage2_abort_guest(regs, hsr, &info, gva, + gpa) == 0) ) + return; +#endif + /* * The only way to get here right now is because of mem_access, * thus reinjecting the exception to the guest is never required. @@ -1884,9 +1937,6 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, } case FSC_FLT_TRANS: { - info.gpa = gpa; - info.dabt = hsr.dabt; - /* * Assumption :- Most of the times when we get a data abort and the ISS * is invalid or an instruction abort, the underlying cause is that the @@ -1923,29 +1973,8 @@ static void do_trap_stage2_abort_guest(struct cpu_user_regs *regs, if ( (info.dabt_instr.state == INSTR_VALID) && check_p2m(is_data, gpa) ) return; - state = try_handle_mmio(regs, &info); - - switch ( state ) - { - case IO_ABORT: - goto inject_abt; - case IO_HANDLED: - /* - * If the instruction was decoded and has executed successfully - * on the MMIO region, then Xen should execute the next part of - * the instruction. (for eg increment the rn if it is a - * post-indexing instruction. - */ - finalize_instr_emulation(&info.dabt_instr); - advance_pc(regs, hsr); - return; - case IO_RETRY: - /* finish later */ - return; - case IO_UNHANDLED: - /* IO unhandled, try another way to handle it. */ - break; - } + if ( do_mmio_trap_stage2_abort_guest(regs, hsr, &info, gva, gpa) == 0 ) + return; break; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286092.1567249 (Exim 4.92) (envelope-from ) id 1wEpZJ-0005ic-Hu; Mon, 20 Apr 2026 14:25:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286092.1567249; Mon, 20 Apr 2026 14:25:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZJ-0005iF-AZ; Mon, 20 Apr 2026 14:25:45 +0000 Received: by outflank-mailman (input) for mailman id 1286092; Mon, 20 Apr 2026 14:25:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZH-0005QG-Bq for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZG-007oXE-P0 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:42 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e63758-5cb7-0a2a0a5109dd-0a2a450cba0e-44 for ; Mon, 20 Apr 2026 16:25:42 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e63765-62f1-0a2a450c0019-d98c6eacb948-1 for ; Mon, 20 Apr 2026 16:25:42 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C8F921516; Mon, 20 Apr 2026 07:25:35 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 38E6D3F7B4; Mon, 20 Apr 2026 07:25:40 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695141; bh=Al7AOCud4lNxulX4r/nJBRzdtBBDHwwUvlyzIFQQIKY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X9UfO1TxDU5WDQ4XOfEZVuqUA7Cxo97hg/3n6y2wcT9I8yPJMNwz+5dgCMK66TUJZ rkc2y93ONuRunueaVzcWPnz0v1koP+p3ws8Dlg86Oe79Nld4MwWdwHx0SLcvf1121n yBzfkKc94C+c3O/uRbURDIbCVDXr65wqAelBMRSo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen Subject: [PATCH 6/8] xen/arm: dump debug message in MPU system Date: Mon, 20 Apr 2026 15:25:22 +0100 Message-Id: <20260420142524.1804073-7-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1776695142-F4C07CF5-F184B584/0/0 X-purgate-type: clean X-purgate-size: 4208 From: Penny Zheng A set of helpers dump_xxx and show_registers are responsible for dumping memory mapping info and register info when debugging. In this commit, we implement them all in MPU system too. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu --- xen/arch/arm/mpu/mm.c | 12 +++++++++++- xen/arch/arm/mpu/p2m.c | 40 +++++++++++++++++++++++++++++++++++++++- xen/arch/arm/traps.c | 8 ++++++++ 3 files changed, 58 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 5ed77355a5f9..459fb952d125 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -554,7 +554,17 @@ int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf) void dump_hyp_walk(vaddr_t addr) { - BUG_ON("unimplemented"); + uint8_t i = 0; + pr_t region; + + for ( i = 0; i < max_mpu_regions; i++ ) + { + read_protection_region(®ion, i); + if ( region_is_valid(®ion) ) + printk(XENLOG_INFO + "Walking hypervisor MPU memory region [%u]: 0x%"PRIpaddr"-0x%"PRIpaddr"\n", + i, pr_get_base(®ion), pr_get_limit(®ion)); + } } /* Release all __init and __initdata ranges to be reused */ diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index bf87c65c106c..06c92a3ef41b 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -215,9 +215,47 @@ mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, return p2m_get_mpu_region(p2m, gfn, 1, t, valid); } +static void dump_mpu_walk(pr_t *table, uint8_t nr_regions) +{ + uint8_t i = 0; + + for ( ; i < nr_regions; i++ ) + { + paddr_t base, limit; + + if ( region_is_valid(&table[i]) ) + { + base = pr_get_base(&table[i]); + limit = pr_get_limit(&table[i]); + + printk(XENLOG_INFO + "Walking MPU memory mapping table: Region[%u]: 0x%"PRIpaddr"-0x%"PRIpaddr"\n", + i, base, limit); + } + } +} + +void dump_p2m_lookup(struct domain *d, paddr_t addr) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + + printk("dom%d IPA 0x%"PRIpaddr"\n", d->domain_id, addr); + + printk("P2M @ %p mfn:%#"PRI_mfn"\n", + p2m->root, mfn_x(page_to_mfn(p2m->root))); + + dump_mpu_walk((pr_t *)page_to_virt(p2m->root), p2m->nr_regions); +} + void p2m_dump_info(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m = p2m_get_hostp2m(d); + + p2m_read_lock(p2m); + printk("p2m mappings for domain %d (vmid %d):\n", + d->domain_id, p2m->vmid); + printk(" Number of P2M Memory Region: %u \n", p2m->nr_regions); + p2m_read_unlock(p2m); } static int p2m_alloc_table(struct domain *d) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 081bd2e51979..fba7d6c00e37 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -718,6 +718,8 @@ struct reg_ctxt { #ifdef CONFIG_MMU /* Hypervisor-side state */ uint64_t vttbr_el2; +#else + uint64_t vsctlr_el2; #endif }; @@ -918,6 +920,8 @@ static void _show_registers(const struct cpu_user_regs *regs, printk(" VTCR_EL2: %"PRIregister"\n", READ_SYSREG(VTCR_EL2)); #ifdef CONFIG_MMU printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2); +#else + printk(" VSCTLR_EL2: %016"PRIx64"\n", ctxt->vsctlr_el2); #endif printk("\n"); @@ -959,6 +963,8 @@ void show_registers(const struct cpu_user_regs *regs) #endif #ifdef CONFIG_MMU ctxt.vttbr_el2 = READ_SYSREG64(VTTBR_EL2); +#else + ctxt.vsctlr_el2 = READ_SYSREG(VSCTLR_EL2); #endif _show_registers(regs, &ctxt, guest_mode(regs), current); @@ -985,6 +991,8 @@ void vcpu_show_registers(struct vcpu *v) #ifdef CONFIG_MMU ctxt.vttbr_el2 = v->domain->arch.p2m.vttbr; +#else + ctxt.vsctlr_el2 = v->domain->arch.p2m.vsctlr; #endif _show_registers(&v->arch.cpu_info->guest_cpu_user_regs, &ctxt, 1, v); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286094.1567254 (Exim 4.92) (envelope-from ) id 1wEpZK-0005lI-9c; Mon, 20 Apr 2026 14:25:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286094.1567254; Mon, 20 Apr 2026 14:25:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZJ-0005kb-OQ; Mon, 20 Apr 2026 14:25:45 +0000 Received: by outflank-mailman (input) for mailman id 1286094; Mon, 20 Apr 2026 14:25:44 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpZI-0005fl-FR for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:25:44 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpZH-00BFc6-Ru for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:25:43 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e63760-2eae-0a2a0a5409dd-0a2a450882fc-36 for ; Mon, 20 Apr 2026 16:25:43 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e63767-63b5-0a2a45080019-d98c6eacb956-1 for ; Mon, 20 Apr 2026 16:25:43 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 05BCE1758; Mon, 20 Apr 2026 07:25:37 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9F9473F7B4; Mon, 20 Apr 2026 07:25:41 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695142; bh=POwMy0a+mxqsay/MzYgDqyjsTTEYght2gW9VVJxJBz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iFLQu4L1MjrxmtfYHsLxLuv0UPDZvOLH4psmVR7VcRh6has4yzl+fjB3TwnUR1kUs Wn8C0hKN1198xG8cQSM59wpSjmtbDzp1I1Zh2I1oxOXVjR4jSMTc+41zZRkclWcLuD VrrXQVwZBJ1vM6AH9BCHpMyjFQEPmDHTLgkuk+Ko= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH 7/8] arm/mpu: Save/restore guest EL1 MPU-related context Date: Mon, 20 Apr 2026 15:25:23 +0100 Message-Id: <20260420142524.1804073-8-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1776695143-3AD73DB1-0CCEDBC0/0/0 X-purgate-type: clean X-purgate-size: 18418 Implement save/restore of guest MPU-related context, as all MPU memory regions must be saved/restored on vCPU context switch when domain is using PMSAv8-64 translation regime. Introduce is_mpu_domain() helper function that is always false on MMU and it checks if PMSA is selected at EL1 for MPU domains. Split the save/restore functions into MPU arm64 and arm32, the latter is currently not implemented, the former is fully implemented and uses the PR{B,L}AR_EL1 register access in order to issue the minimum amount of ISB as possible while changing the selector and writing/reading the registers. struct arch_vcpu now includes a pointer to the allocated storage for the additional MPU regions to be saved on context switch. Signed-off-by: Luca Fancellu --- xen/arch/arm/arm64/mpu/p2m.c | 2 + xen/arch/arm/domain.c | 49 +++++++--- xen/arch/arm/include/asm/domain.h | 5 + xen/arch/arm/include/asm/mm.h | 3 + xen/arch/arm/include/asm/mmu/mm.h | 12 +++ xen/arch/arm/include/asm/mpu.h | 3 + xen/arch/arm/include/asm/mpu/cpregs.h | 3 + xen/arch/arm/include/asm/mpu/mm.h | 10 ++ xen/arch/arm/mpu/arm32/mm.c | 10 ++ xen/arch/arm/mpu/arm64/mm.c | 136 ++++++++++++++++++++++++++ xen/arch/arm/mpu/mm.c | 39 ++++++++ 11 files changed, 260 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index a39a1fc38946..a1ec9fcd6195 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -62,6 +62,8 @@ void __init setup_virt_paging(void) p2m_vmid_allocator_init(); + load_nr_mpu_regions_el1(); + /* * VSTCR_EL2.SA defines secure stage 2 translation output address space. * To make sure that all stage 2 translations for the Secure PA space access diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index dfa7ace1141b..221b1f8a7f9d 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -123,11 +123,23 @@ static void ctxt_switch_from(struct vcpu *p) isb(); - /* MMU */ + /* MMU/MPU */ + if ( is_mpu_domain(p->domain) ) + { + /* + * Domain is using PMSAv8-64 translation regime at EL1, so we need to + * save EL1 MPU memory regions. + */ + save_el1_mpu_regions(p); + } + else + { + /* Domain is using VMSAv8-64 translation regime via MMU. */ + p->arch.ttbcr = READ_SYSREG(TCR_EL1); + p->arch.ttbr0 = READ_SYSREG64(TTBR0_EL1); + p->arch.ttbr1 = READ_SYSREG64(TTBR1_EL1); + } p->arch.vbar = READ_SYSREG(VBAR_EL1); - p->arch.ttbcr = READ_SYSREG(TCR_EL1); - p->arch.ttbr0 = READ_SYSREG64(TTBR0_EL1); - p->arch.ttbr1 = READ_SYSREG64(TTBR1_EL1); if ( is_32bit_domain(p->domain) ) p->arch.dacr = READ_SYSREG(DACR32_EL2); p->arch.par = read_sysreg_par(); @@ -156,8 +168,6 @@ static void ctxt_switch_from(struct vcpu *p) p->arch.afsr0 = READ_SYSREG(AFSR0_EL1); p->arch.afsr1 = READ_SYSREG(AFSR1_EL1); - /* XXX MPU */ - /* VGIC */ gic_save_state(p); @@ -181,8 +191,6 @@ static void ctxt_switch_to(struct vcpu *n) /* VGIC */ gic_restore_state(n); - /* XXX MPU */ - /* Fault Status */ #if defined(CONFIG_ARM_32) WRITE_CP32(n->arch.dfar, DFAR); @@ -198,11 +206,23 @@ static void ctxt_switch_to(struct vcpu *n) WRITE_SYSREG(n->arch.afsr0, AFSR0_EL1); WRITE_SYSREG(n->arch.afsr1, AFSR1_EL1); - /* MMU */ + /* MMU/MPU */ + if ( is_mpu_domain(n->domain) ) + { + /* + * Domain is using PMSAv8-64 translation regime at EL1, so we need to + * restore EL1 MPU memory regions. + */ + restore_el1_mpu_regions(n); + } + else + { + /* Domain is using VMSAv8-64 translation regime via MMU. */ + WRITE_SYSREG(n->arch.ttbcr, TCR_EL1); + WRITE_SYSREG64(n->arch.ttbr0, TTBR0_EL1); + WRITE_SYSREG64(n->arch.ttbr1, TTBR1_EL1); + } WRITE_SYSREG(n->arch.vbar, VBAR_EL1); - WRITE_SYSREG(n->arch.ttbcr, TCR_EL1); - WRITE_SYSREG64(n->arch.ttbr0, TTBR0_EL1); - WRITE_SYSREG64(n->arch.ttbr1, TTBR1_EL1); /* * Erratum #852523 (Cortex-A57) or erratum #853709 (Cortex-A72): @@ -518,6 +538,9 @@ int arch_vcpu_create(struct vcpu *v) if ( get_ssbd_state() == ARM_SSBD_RUNTIME ) v->arch.cpu_info->flags |= CPUINFO_WORKAROUND_2_FLAG; + if ( is_mpu_domain(v->domain) ) + allocate_el1_mpu_regions(v); + return rc; fail: @@ -532,6 +555,8 @@ void arch_vcpu_destroy(struct vcpu *v) vcpu_timer_destroy(v); vcpu_vgic_free(v); free_xenheap_pages(v->arch.stack, STACK_ORDER); + if ( is_mpu_domain(v->domain) ) + free_el1_mpu_regions(v); } void vcpu_switch_to_aarch64_mode(struct vcpu *v) diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 4a3fb825962b..44c304ef8aa9 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -202,6 +202,11 @@ struct arch_vcpu register_t actlr; uint32_t cpacr; +#ifdef CONFIG_MPU + /* EL1 MPU memory regions */ + pr_t *mpu_regions; +#endif + uint32_t contextidr; register_t tpidr_el0; register_t tpidr_el1; diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 72a692862420..9e35800aba5e 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -202,6 +202,9 @@ extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); void setup_mm_helper(void); /* map a physical range in virtual memory */ void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int attributes); +/* Allocate space for EL1 MPU region info */ +void allocate_el1_mpu_regions(struct vcpu *v); +void free_el1_mpu_regions(struct vcpu *v); static inline void __iomem *ioremap_nocache(paddr_t start, size_t len) { diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h index 7f4d59137d0d..c441af50c3a9 100644 --- a/xen/arch/arm/include/asm/mmu/mm.h +++ b/xen/arch/arm/include/asm/mmu/mm.h @@ -9,6 +9,8 @@ #include #include +struct domain; + /* Non-boot CPUs use this to find the correct pagetables. */ extern uint64_t init_ttbr; @@ -91,6 +93,16 @@ static inline struct page_info *virt_to_page(const void *v) return frame_table + pdx - frametable_base_pdx; } +/* If this domain should use PMSAv8-64 translation regime (MPU) at EL1. */ +static inline bool is_mpu_domain(struct domain *d) +{ + return false; +} + +/* Stub for MPU EL1 region save/restore */ +static inline void save_el1_mpu_regions(struct vcpu *p) { } +static inline void restore_el1_mpu_regions(struct vcpu *n) { } + /* * Print a walk of a page table or p2m * diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 8a8c01086206..525944987713 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -27,6 +27,9 @@ #ifndef __ASSEMBLER__ +/* Load the number of regions supported by the EL1 MPU from MPUIR_EL1. */ +void load_nr_mpu_regions_el1(void); + /* * Utility function to determine if an Armv8-R processor supports VMSA. */ diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h index 5a3d92cf5389..f6fb3c93c032 100644 --- a/xen/arch/arm/include/asm/mpu/cpregs.h +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -5,6 +5,7 @@ /* CP15 CR0: MPU Type Register */ #define HMPUIR p15,4,c0,c0,4 +#define MPUIR p15,0,c0,c0,4 /* CP15 CR2: Virtualization System Control register */ #define VSCTLR p15,4,c2,c0,1 @@ -16,6 +17,7 @@ #define HPRSELR p15,4,c6,c2,1 #define HPRBAR p15,4,c6,c3,0 #define HPRLAR p15,4,c6,c3,1 +#define PRSELR p15,0,c6,c2,1 /* CP15 CR6: MPU Protection Region Base/Limit Address Register */ #define HPRBAR0 p15,4,c6,c8,0 @@ -86,6 +88,7 @@ /* Aliases of AArch64 names for use in common code */ #ifdef CONFIG_ARM_32 /* Alphabetically... */ +#define MPUIR_EL1 MPUIR #define MPUIR_EL2 HMPUIR #define PRBAR_EL2 HPRBAR #define PRENR_EL2 HPRENR diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h index 24bffdee4fb6..a536ec4431df 100644 --- a/xen/arch/arm/include/asm/mpu/mm.h +++ b/xen/arch/arm/include/asm/mpu/mm.h @@ -20,6 +20,7 @@ extern struct page_info *frame_table; extern uint8_t max_mpu_regions; +extern uint8_t max_mpu_regions_el1; extern DECLARE_BITMAP(xen_mpumap_mask, MAX_MPU_REGION_NR); @@ -55,6 +56,15 @@ static inline void context_sync_mpu(void) isb(); } +/* If this domain should use PMSAv8-64 translation regime (MPU) at EL1. */ +bool is_mpu_domain(struct domain *d); + +/* Save EL1 MPU base and limit registers. */ +void save_el1_mpu_regions(struct vcpu *p); + +/* Restore EL1 MPU base and limit registers. */ +void restore_el1_mpu_regions(struct vcpu *n); + /* * The following API requires context_sync_mpu() after being used to modify MPU * regions: diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index 5eaeb3400e6c..3dd71228b4ed 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -159,6 +159,16 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel) } } +void save_el1_mpu_regions(struct vcpu *p) +{ + BUG_ON("unimplemented"); +} + +void restore_el1_mpu_regions(struct vcpu *n) +{ + BUG_ON("unimplemented"); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index b07e729a7d05..ce9947851173 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include +#include #include #include @@ -10,9 +12,13 @@ * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE * and GENERATE_READ_PR_REG_CASE with num==0 */ +#define PRBAR0_EL1 PRBAR_EL1 +#define PRLAR0_EL1 PRLAR_EL1 #define PRBAR0_EL2 PRBAR_EL2 #define PRLAR0_EL2 PRLAR_EL2 +#define PRBAR_EL1_(n) PRBAR##n##_EL1 +#define PRLAR_EL1_(n) PRLAR##n##_EL1 #define PRBAR_EL2_(n) PRBAR##n##_EL2 #define PRLAR_EL2_(n) PRLAR##n##_EL2 @@ -32,6 +38,22 @@ break; \ } +#define GENERATE_SAVE_EL1_PR_REG_CASE(num, pr, sel) \ + case num: \ + { \ + pr->prbar.bits = READ_SYSREG(PRBAR_EL1_(num)); \ + pr->prlar.bits = READ_SYSREG(PRLAR_EL1_(num)); \ + sel--; \ + } + +#define GENERATE_RESTORE_EL1_PR_REG_CASE(num, pr, sel) \ + case num: \ + { \ + WRITE_SYSREG(pr->prbar.bits & ~MPU_REGION_RES0, PRBAR_EL1_(num)); \ + WRITE_SYSREG(pr->prlar.bits & ~MPU_REGION_RES0, PRLAR_EL1_(num)); \ + sel--; \ + } + bool has_v8r_vmsa_support(void) { return system_cpuinfo.mm64.msa_frac == MM64_MSA_FRAC_VMSA_SUPPORT; @@ -125,6 +147,120 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel) } } +void save_el1_mpu_regions(struct vcpu *p) +{ + int sel = max_mpu_regions_el1 - 1; + pr_t *table; + + if ( max_mpu_regions_el1 == 0 ) + return; + + if ( p->arch.mpu_regions == NULL ) + return; + table = p->arch.mpu_regions; + + while ( sel >= 0 ) + { + WRITE_SYSREG( (sel & 0xF0), PRSELR_EL1); + isb(); + switch ( sel & 0xF ) { + GENERATE_SAVE_EL1_PR_REG_CASE(15, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(14, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(13, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(12, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(11, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(10, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(9, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(8, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(7, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(6, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(5, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(4, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(3, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(2, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(1, (&table[sel]), sel); + fallthrough; + GENERATE_SAVE_EL1_PR_REG_CASE(0, (&table[sel]), sel); + break; + default: + BUG(); /* Can't happen */ + break; + } + } +} + +void restore_el1_mpu_regions(struct vcpu *n) +{ + int sel = max_mpu_regions_el1 - 1; + pr_t *table; + + if ( max_mpu_regions_el1 == 0 ) + return; + + if ( !n->arch.mpu_regions ) + return; + table = n->arch.mpu_regions; + + while ( sel >= 0 ) + { + WRITE_SYSREG( (sel & 0xF0), PRSELR_EL1); + isb(); + switch ( sel & 0xF ) { + GENERATE_RESTORE_EL1_PR_REG_CASE(15, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(14, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(13, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(12, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(11, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(10, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(9, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(8, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(7, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(6, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(5, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(4, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(3, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(2, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(1, (&table[sel]), sel); + fallthrough; + GENERATE_RESTORE_EL1_PR_REG_CASE(0, (&table[sel]), sel); + break; + default: + BUG(); /* Can't happen */ + break; + } + } + + context_sync_mpu(); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index 459fb952d125..d6703bf0c005 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #define MPU_ATTR_XN_RO_MISMATCH -1 #define MPU_ATTR_AI_MISMATCH -2 @@ -23,6 +25,9 @@ struct page_info *frame_table; /* Maximum number of supported MPU memory regions by the EL2 MPU. */ uint8_t __ro_after_init max_mpu_regions; +/* Maximum number of supported MPU memory regions by the EL1 MPU. */ +uint8_t __read_mostly max_mpu_regions_el1; + /* * Bitmap xen_mpumap_mask is to record the usage of EL2 MPU memory regions. * Bit 0 represents MPU memory region 0, bit 1 represents MPU memory @@ -631,6 +636,40 @@ void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags) return maddr_to_virt(start); } +bool is_mpu_domain(struct domain *d) +{ + return (d->arch.v8r_el1_msa == XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE) || + (d->arch.v8r_el1_msa == XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA); +} + +void load_nr_mpu_regions_el1(void) +{ + max_mpu_regions_el1 = (uint8_t)(READ_SYSREG(MPUIR_EL1) & + NUM_MPU_REGIONS_MASK); +} + +void allocate_el1_mpu_regions(struct vcpu *v) +{ + if ( max_mpu_regions_el1 == 0 ) + return; + + if ( v->arch.mpu_regions ) + return; + + v->arch.mpu_regions = (pr_t *)_xzalloc(sizeof(pr_t) * max_mpu_regions_el1, + SMP_CACHE_BYTES); + if ( !v->arch.mpu_regions ) + panic("DOM%pd: mpu: no memory to store EL1 MPU memory region info\n", + v->domain); + memset(v->arch.mpu_regions, 0, sizeof(pr_t) * max_mpu_regions_el1); +} + +void free_el1_mpu_regions(struct vcpu *v) +{ + if ( v->arch.mpu_regions ) + xfree(v->arch.mpu_regions); +} + /* * Local variables: * mode: C -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:25:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:25:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286099.1567266 (Exim 4.92) (envelope-from ) id 1wEpZL-0006Dj-P8; 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a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776695143; bh=DZDq1tuHld+v7+buygc/it5ATvErstw+AN1u/SO6z5U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cql5dYQz5MqXn40DAJLyQby//2LqjdikrSawBIJejgCAbGxmXoVzAGseR2UGeHvbm gOtdH0DPaOpL14OXm1RP8KkKqSOHumxoIkkiYgzykkflW4Uzrj5x+AWc/OP7I1HTLB IVlR7QhPN849+MJ1RVjZ+lbPaK7UdkKLaE78rBgo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH 8/8] arm/mpu: Save/restore VTCR_EL2 on vCPU context switch Date: Mon, 20 Apr 2026 15:25:24 +0100 Message-Id: <20260420142524.1804073-9-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142524.1804073-1-luca.fancellu@arm.com> References: <20260420142524.1804073-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776695144-05969F3B-B9F5DBF5/0/0 X-purgate-type: clean X-purgate-size: 6845 On AArch64 MPU systems, the VTCR register contains the MSA bit that determines if the guest is using MPU or MMU at EL1, which is required to be saved/restored on vCPU context switch. On AArch64 MPU systems the VTCR_EL2 register configuration will be saved during setup_virt_paging and will be placed in a new member of 'struct arch_vcpu' named vtcr_el2, to be retrieved by context switch. AArch32 MPU systems and MMU systems don't need to save/restore this register because they don't have any MSA bit and related functionality, so for these architecture a stub is provided. Signed-off-by: Luca Fancellu --- xen/arch/arm/arm64/mpu/p2m.c | 15 +++++++++++++++ xen/arch/arm/domain.c | 2 ++ xen/arch/arm/include/asm/domain.h | 5 +++++ xen/arch/arm/include/asm/mmu/domain-build.h | 2 ++ xen/arch/arm/include/asm/mpu/domain-build.h | 6 ++++++ xen/arch/arm/include/asm/mpu/p2m.h | 10 ++++++++++ xen/arch/arm/mpu/domain-build.c | 17 +++++++++++++++++ xen/arch/arm/mpu/p2m.c | 4 ++++ 8 files changed, 61 insertions(+) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index a1ec9fcd6195..350cbd7ae94c 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -3,8 +3,12 @@ #include #include #include +#include #include +/* VTCR_EL2 value to be configured for the boot CPU. */ +register_t __read_mostly vtcr; + void __init setup_virt_paging(void) { register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); @@ -58,6 +62,7 @@ void __init setup_virt_paging(void) else vtcr_el2 &= ~VTCR_VS; + vtcr = vtcr_el2; WRITE_SYSREG(vtcr_el2, VTCR_EL2); p2m_vmid_allocator_init(); @@ -89,6 +94,16 @@ void __init setup_virt_paging(void) panic("Hardware with no PMSAv8-64 support in any translation regime\n"); } +void p2m_save_vtcr(struct vcpu *p) +{ + p->arch.vtcr_el2 = READ_SYSREG(VTCR_EL2); +} + +void p2m_restore_vtcr(struct vcpu *n) +{ + WRITE_SYSREG(n->arch.vtcr_el2, VTCR_EL2); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 221b1f8a7f9d..e928301d7cb0 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -538,6 +538,8 @@ int arch_vcpu_create(struct vcpu *v) if ( get_ssbd_state() == ARM_SSBD_RUNTIME ) v->arch.cpu_info->flags |= CPUINFO_WORKAROUND_2_FLAG; + arch_set_vtcr_msa(v); + if ( is_mpu_domain(v->domain) ) allocate_el1_mpu_regions(v); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 44c304ef8aa9..3ab004518427 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -203,6 +203,11 @@ struct arch_vcpu uint32_t cpacr; #ifdef CONFIG_MPU +#ifdef CONFIG_ARM_64 + /* Virtualization Translation Control Register */ + uint64_t vtcr_el2; +#endif + /* EL1 MPU memory regions */ pr_t *mpu_regions; #endif diff --git a/xen/arch/arm/include/asm/mmu/domain-build.h b/xen/arch/arm/include/asm/mmu/domain-build.h index 3e0d9a6a2a08..0919c0097da9 100644 --- a/xen/arch/arm/include/asm/mmu/domain-build.h +++ b/xen/arch/arm/include/asm/mmu/domain-build.h @@ -34,6 +34,8 @@ int arch_set_v8r_el1_msa(struct domain *d, return 0; } +static inline void arch_set_vtcr_msa(struct vcpu *v) {} + #endif /* __ARM_MMU_DOMAIN_BUILD_H__ */ /* diff --git a/xen/arch/arm/include/asm/mpu/domain-build.h b/xen/arch/arm/include/asm/mpu/domain-build.h index 463cd85b5b7e..8d3a743219ce 100644 --- a/xen/arch/arm/include/asm/mpu/domain-build.h +++ b/xen/arch/arm/include/asm/mpu/domain-build.h @@ -15,6 +15,12 @@ int arch_set_v8r_el1_msa(struct domain *d, const struct xen_domctl_createdomain *config, unsigned int flags); +#ifdef CONFIG_ARM_64 +void arch_set_vtcr_msa(struct vcpu *v); +#else +static inline void arch_set_vtcr_msa(struct vcpu *v) {} +#endif + #endif /* __ARM_MPU_DOMAIN_BUILD_H__ */ /* diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/mpu/p2m.h index d0ec8a77a15a..1628148ba578 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -9,6 +9,8 @@ struct p2m_domain; +extern register_t vtcr; + /* * The architecture allows at most 255 EL2 MPU memory regions. The size of the * MPU structure entry (pr_t) is 32 Bytes on AArch64 (requiring two 4KB pages) @@ -36,6 +38,14 @@ static inline bool region_is_p2m_valid(pr_t *pr) return (pr->p2m_type != p2m_invalid); } +#ifdef CONFIG_ARM_64 +void p2m_save_vtcr(struct vcpu *p); +void p2m_restore_vtcr(struct vcpu *n); +#else +static inline void p2m_save_vtcr(struct vcpu *p) {} +static inline void p2m_restore_vtcr(struct vcpu *n) {} +#endif + #endif /* __ARM_MPU_P2M_H__ */ /* diff --git a/xen/arch/arm/mpu/domain-build.c b/xen/arch/arm/mpu/domain-build.c index 1bdd0ffedebb..19e504f7149e 100644 --- a/xen/arch/arm/mpu/domain-build.c +++ b/xen/arch/arm/mpu/domain-build.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -66,6 +67,22 @@ int arch_set_v8r_el1_msa(struct domain *d, return 0; } +#ifdef CONFIG_ARM_64 +void arch_set_vtcr_msa(struct vcpu *v) +{ + /* + * When ID_AA64MMFR0_EL1.MSA_frac is 0b0010 (MM64_MSA_FRAC_VMSA_SUPPORT), + * then VTCR_EL2.MSA determines the memory system architecture enabled + * at stage 1 of the Secure EL1&0 translation regime. + */ + v->arch.vtcr_el2 = vtcr; + if ( is_mpu_domain(v->domain) ) + v->arch.vtcr_el2 &= ~VTCR_MSA; + else + v->arch.vtcr_el2 |= VTCR_MSA; +} +#endif + /* * Local variables: * mode: C diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index 06c92a3ef41b..b41abd8f2d37 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -357,6 +357,8 @@ void p2m_save_state(struct vcpu *p) p->arch.sctlr = READ_SYSREG(SCTLR_EL1); + p2m_save_vtcr(p); + if ( p2m_xenmpu_update(p2m, false) ) panic("Failed to offline P2M MPU memory mapping\n"); } @@ -369,6 +371,8 @@ void p2m_restore_state(struct vcpu *n) WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1); WRITE_SYSREG(n->arch.hcr_el2, HCR_EL2); + p2m_restore_vtcr(n); + WRITE_SYSREG(p2m->vsctlr, VSCTLR_EL2); if ( p2m_xenmpu_update(p2m, true) ) panic("Failed to online P2M MPU memory mapping\n"); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:35:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:35:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286170.1567276 (Exim 4.92) (envelope-from ) id 1wEpiB-00025A-Gv; Mon, 20 Apr 2026 14:34:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286170.1567276; Mon, 20 Apr 2026 14:34:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpiB-000253-D8; Mon, 20 Apr 2026 14:34:55 +0000 Received: by outflank-mailman (input) for mailman id 1286170; Mon, 20 Apr 2026 14:34:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEpiA-00024x-Ft for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:34:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpi9-000SbR-Dr for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:34:53 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e63987-bab6-0a2a0a5309dd-0a2a450ccf6c-20 for ; Mon, 20 Apr 2026 16:34:53 +0200 Received: from [209.85.208.170] (helo=mail-lj1-f170.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6398d-62f1-0a2a450c0019-d155d0aac876-3 for ; Mon, 20 Apr 2026 16:34:53 +0200 Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-38e936caafeso31291361fa.2 for ; Mon, 20 Apr 2026 07:34:53 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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AFNElJ8NUWbBQLkrvPGLhG0M0jdjAfokwIlsrQrECPQMYOSskwazOC1T0wY629IGuqHvj0Z3U4LRiy5Qh+8=@lists.xenproject.org X-Gm-Message-State: AOJu0YxFPSI2CVrIAErn6d/jcO+zilLy5/my5pKmIY0rHwvVqtbqafY+ dtwU4W4G+DUJofRXgfN2Mx4CUXhQN15tds/DIPJa9LDrIm2DTxacFRGU X-Gm-Gg: AeBDievy3NZFbdcl79Ll6oTTUSElcpA439fNB1hAxVdmvEG9P0LW2rVCRio1eHETgIv SNpVPtUgDhTFlyMmMEM3IisjR1Ew4Vg7jZQPle9O8kwA/bT3C65E0x0J7i5/k72ctIDZJ0KPjf/ dyToQprVb4t71rwuIjhhIlFnt4dFx/pGjBPd6BTmC8uKhVobWjgdxlhujEJ6jZ2o6+Ijv9ht5zM g8pM5h0Ax1z7XXOTWFJepoc+JtTvmLDELbbzIwZfEtu0VJ171JaXts3vowIPfNIeObWzwqN13Tc 2oFhCwbGNlLDARFuy43z+836r9ta2KvFnbAkxTrgSnTW+mGkOkYrZJRHq15ElCIvLUT65hZQQCe ZKKW5yMOB8VncPXMYD35XB44BQ1LuW2JWpE/axKIROMvxrnAST83IZGJw80TaP4hvYACOw8CFW7 dcWQGyu2tuIaZjVOxcufME6JGDcYpRIm2XrAmxornVUou7E5jgTitKZvhDtFPsA4+MKSbJGEUo9 PBr3KXb95WhgA== X-Received: by 2002:a05:651c:b27:b0:38e:ac6:a50f with SMTP id 38308e7fff4ca-38ec7830e46mr46683641fa.10.1776695692202; Mon, 20 Apr 2026 07:34:52 -0700 (PDT) Message-ID: <7c059a67-3f3f-4633-aebb-939aa9ac7955@gmail.com> Date: Mon, 20 Apr 2026 16:34:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 16/27] xen/riscv: implement IRQ mapping for device passthrough To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <10654a6c38fa929b5fdf6f214badfe4f60fe78d4.1773157782.git.oleksii.kurochko@gmail.com> <8a8a2afd-6f53-4f45-b8c8-fb34a6fbb970@suse.com> <00fa439d-0327-4c0c-960d-a810820a6e83@gmail.com> <09a260ca-5a98-461d-9f57-d298a483d3d6@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <09a260ca-5a98-461d-9f57-d298a483d3d6@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1776695693-6F370CF5-EC2E2962/10/73395122804 X-purgate-type: spam X-purgate-size: 5993 On 4/20/26 3:45 PM, Jan Beulich wrote: > On 20.04.2026 13:39, Oleksii Kurochko wrote: >> On 4/16/26 2:51 PM, Jan Beulich wrote: >>> On 14.04.2026 13:29, Oleksii Kurochko wrote: >>>> On 4/2/26 2:22 PM, Jan Beulich wrote: >>>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>>>>> + struct dt_device_node *dev, >>>>>> + bool need_mapping, >>>>>> + struct rangeset *irq_ranges) >>>>>> +{ >>>>>> + unsigned int i, nirq; >>>>>> + int res, irq; >>>>>> + struct dt_raw_irq rirq; >>>>>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>>>>> + unsigned int reg_num; >>>>>> + >>>>>> + nirq = dt_number_of_irq(dev); >>>>>> + >>>>>> + /* Give permission and map IRQs */ >>>>>> + for ( i = 0; i < nirq; i++ ) >>>>>> + { >>>>>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>>>>> + if ( res ) >>>>>> + { >>>>>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>>>>> + i, dt_node_full_name(dev)); >>>>>> + return res; >>>>>> + } >>>>>> + >>>>>> + /* >>>>>> + * Don't map IRQ that have no physical meaning >>>>>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>>>>> + */ >>>>>> + if ( rirq.controller != dt_interrupt_controller ) >>>>>> + { >>>>>> + dt_dprintk("irq %u not connected to primary controller." >>>>>> + "Connected to %s\n", i, >>>>>> + dt_node_full_name(rirq.controller)); >>>>>> + continue; >>>>>> + } >>>>>> + >>>>>> + irq = platform_get_irq(dev, i); >>>>>> + if ( irq < 0 ) >>>>>> + { >>>>>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>>>>> + return irq; >>>>>> + } >>>>>> + >>>>>> + res = irq_permit_access(d, irq); >>>>>> + if ( res ) >>>>>> + { >>>>>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>>>>> + irq); >>>>> This time the other way around: %d please with plain int. (Again at least >>>>> once further down.) >>>>> >>>>>> + return res; >>>>>> + } >>>>>> + >>>>>> + reg_num = irq / APLIC_NUM_REGS; >>>>>> + >>>>>> + if ( is_irq_shared_among_domains(d, irq) ) >>>>>> + { >>>>>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>>>>> + return -EINVAL; >>>>>> + } >>>>>> + >>>>>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >>>>> ... all of this leaves me with the impression that IRQ numbering isn't really >>>>> virtualized. IRQs are merely split into groups, one group per domain (and >>>>> maybe some unused). How are you going to fit in truly virtual IRQs? >>>> What do you mean by truly virtual IRQs? >>> Ones where no aspects are represented by any piece of hardware. >>> >>>> I can't totally agree that the current approach isn't use virtual IRQs, >>>> yes, they are 1:1 mapped but on the other side Xen is responsible to >>>> give an IRQ number for guest's device and Xen is responsible that guest >>>> isn't trying to reach IRQ which not belongs to it. >>> In a non-virtualized environment I expect IRQs are going to be "sparse" >>> (i.e. with perhaps large blocks of items used elsewhere). If you had >>> proper translation of IRQ numbers, the same could be true for your >>> guests. >> Partial FDT, which is used to tell which device be passthroughed to >> guest, is using physical IRQ number (which I am just considering for >> simplicity to be 1:1 mapped to virtual IRQ number). So if we have the >> following configuration: >> Physical (bare-metal) IRQ layout is sparse: >> IRQ 5 → UART -> domU0 >> IRQ 23 → Ethernet -> domU1 >> IRQ 47 → PCIe -> domU0 >> IRQ 100 → Storage -> domU1 >> (gaps everywhere, driven by hardware wiring) >> >> For such configuration we will have for each domain auth_irq_bmp[] which >> contains: >> IRQ 5 and IRQ47 for domU0 >> and >> IRQ 23 and IRQ 100 for domU1 >> >> And here vIRQ5 = pIRQ5, vIRQ47 = pIRQ47 and so on. auth_irq_bmp just >> transform xIRQ number to bit position which it will have in real APLIC >> register. Just as an example, lets take vIRQ5 and vIRQ47. >> >> As reading or writing register setie[k] reads or potentially modifies >> the enable bits for interrupt sources k × 32 through k × 32 + 31. For an >> implemented interrupt source i within that range, the enable bit for >> source i corresponds with register bit (i mod 32). >> So for: >> - vIRQ5 == pIRQ5 we have to set bit 5 in setie[0] >> - vIRQ47 == pIRQ47 we have to set bit 15 in setie[1] >> >> Probably it was not the best idea to declare auth_irq_bmp as it will >> look in h/w and maybe just 'bool auth_irq_bmp[1024]' would be more clearer. >> >> So irqs number are still stay "sparsed" in guest. > Well, twice (or more) as sparse in the example you give, compared to the > host. Just to be sure that I fully understand your concern here. The difference between xIRQ5 and xIRQ47 is 42 bits (if for 1 irq we are using 1 bit) which leads to that we have somewhere allocated 48 bit bitmap where only two bits will be set, all others will be zero. Instead it would be better to have to do mapping: pIRQ5 -> vIRQ1, pIRQ47 ->vIRQ2, right? If yes, won't we still store somewhere this mapping? it seems like having 'unsigned int auth_irq_bmp[1024]' is a good option where index will be vIRQ number and 'unsigned int' will be pIRQ number. But at the moment I think that we could go with 1:1 IRQ number mapping and then have 'bool auth_irq_bmp[1024]' will be more then enough and will safe some memory. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 14:56:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 14:56:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286182.1567284 (Exim 4.92) (envelope-from ) id 1wEq2h-0005ma-2h; Mon, 20 Apr 2026 14:56:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286182.1567284; Mon, 20 Apr 2026 14:56:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEq2h-0005mT-0A; Mon, 20 Apr 2026 14:56:07 +0000 Received: by outflank-mailman (input) for mailman id 1286182; Mon, 20 Apr 2026 14:56:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEq2f-0005mN-SB for xen-devel@lists.xenproject.org; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a4187e7a62sm2971869e87.56.2026.04.20.08.02.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Apr 2026 08:02:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776697340; x=1777302140; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=9pHylE/WjW6XUQ0m8ic5aY3Qs3biYzaa9JkC4on7POw=; b=apvWCjkwE9jbp91JZl3HQMo4AqZCNK/Sales5jjQQBJDAJQ3N2qkIz0QUkyEP+B480 I1PMlTfV09+BO3EWd56ls6LfnaOV+k42Xkb7fYTYFRLjPRWcA6AeENe1mVFRlGR6eEgt OOc4PTSHqNYzNLXch6Dx8bvGbGs3OTw2bEq5mHi0nbOcr7xxs1eMeBAMbtY6q08Ka1ys nQdA7fnxYlC7xb81Oh+Ubk1ekXLoySm9VNtUqA+W5kh7nxpQg/JslM1kErg8SK9JgSRK TfuKnxYKXRv8YLNNIWus39nDPvDvFXHV6PBf+fD+979kekpN3zlJvyPmiC8z6VdcAqXX IALA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776697340; x=1777302140; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9pHylE/WjW6XUQ0m8ic5aY3Qs3biYzaa9JkC4on7POw=; b=ldu8dth95pdtHtB5x/4cQX+hDhrrhCpsVhDOannUW46b7Evs/9hGRZTumU6TObb7H9 930uxU33cv2kVISI6WWsqy8Ad+ZPNSu1pEzmn03x8Z//S2XC/2ZUXmAce8XaLmGfzU2/ vRbaS5FyX5LAJ6hSUEiNnB+8wPyH3QjohB4iJu7hbd4ujinGwsapRBzB9uaiZ717jxCI uZduWIuy5FDQ/lc2wmi5V6kX35icKrUz+fo7ocrgIQAkfEuXZE6vlt420NRUxpb3xPLx AtYnkQnJyyWeRJTsc26a0hTU1FVqzssCE/HsHt78A3I363cm/TEonsHE2C1c/osJhuw8 jSvQ== X-Forwarded-Encrypted: i=1; AFNElJ9lpZRysqU7+TO3kg/OJg6iOW8QCfZnBoTB5tGOu7Fm3On423frALcQwztbJjUEhgaBonxNMPpgnHk=@lists.xenproject.org X-Gm-Message-State: AOJu0YwPK/s3+nA8/EOPsh/vlHOLcMRtSlYhbArC9YWc5mU+B8R4pbCi PZdsod7BhFirw11eQ6253t8N6QG+3QpJUgjf1nPqK9Nl0SD/RdPqnfm5 X-Gm-Gg: AeBDietNKeChb5VdR2FmFZ3GXOPXDfKdIYrj3q3GX3Cdc4IbNc+ZQxyrbq0BE2tI9Qo 5jBE7JB3QOS5M5ebx8+3M0o+rHbScMCXtc/B4VQ8G6Zkm2Tj6dWJNZ2GZTLGcR3Mp8z3GX+D58j YNupDe6bx2Q05ku8E5+uLXkHBCDI/BruM/+8LALmroFHmsjBUYr3Um/UfpUni+wUkcdxWqK+Eg7 +4azhtDenCDqLGSvkZFbWRdLi7Qk9qfn1QjXFf777nxd1peB774CMzcNEbQvUIJh0pxuZ1XTv0Z daZaLJooPgZIHB+5F8FTmH9mjB73Qn+H0NAnun2nqoxW5Y9crLCeKMNJYtMR2vdAsLlNzn9MDL3 h5RrG6+93cntrkDx6TIyDDxOGzh2X07lHpJpGoZDNr5ToQ3uZfRYCU9CzhJlAC2Z7epI68YfOVz kiHX3Bh2taqxqA2CnFBHsZGSglJtpMfNY0AfTAE/WKzhmxmWLIfBim25ZPHIX92aXTCnU/vBK4Z NSl7MTbGHQpmA== X-Received: by 2002:a05:6512:3c91:b0:5a2:b514:4fbb with SMTP id 2adb3069b0e04-5a4172999c9mr4096567e87.11.1776697337906; Mon, 20 Apr 2026 08:02:17 -0700 (PDT) Message-ID: <276c68cb-51c0-4775-8b70-3af80d0d0f27@gmail.com> Date: Mon, 20 Apr 2026 17:02:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 19/27] xen/riscv: emulate guest writes to virtual APLIC MMIO To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <2bff40f5-2eef-4e72-8191-b3442607e0e4@suse.com> <76ea5954-89cd-47a4-872a-239bbc08b785@gmail.com> <910f0720-1e83-4b0d-a1bd-09799d6f8264@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <910f0720-1e83-4b0d-a1bd-09799d6f8264@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776697340-4216DA53-B1A4962F/10/73395122804 X-purgate-type: spam X-purgate-size: 6531 On 4/16/26 3:19 PM, Jan Beulich wrote: > On 14.04.2026 18:04, Oleksii Kurochko wrote: >> On 4/2/26 4:18 PM, Jan Beulich wrote: >>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>> +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, >>>> + unsigned long addr, uint32_t value) >>>> +{ >>>> + struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>>> + struct aplic_priv *priv = vaplic->base.info->private; >>>> + uint32_t offset = addr & APLIC_REG_OFFSET_MASK; >>> >>> See ./CODING_STYLE as to uses of fixed-width types. >>> >>>> + unsigned long aplic_addr = addr - priv->paddr_start; >>>> + const uint32_t *auth_irq_bmp = vcpu->domain->arch.vintc->private; >>>> + >>>> + switch ( offset ) >>>> + { >>>> + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: >>> >>> And (taking this just as example) any misaligned accesses falling in this range >>> are fine? >> >> Do you mean something like 0x1C02 instead of 0x1C00 or 0x1C04? > > Yes. > >>>> + /* >>>> + * As sourcecfg register starts from 1: >>>> + * 0x0000 domaincfg >>>> + * 0x0004 sourcecfg[1] >>>> + * 0x0008 sourcecfg[2] >>>> + * ... >>>> + * 0x0FFC sourcecfg[1023] >>>> + * It is necessary to calculate an interrupt number by substracting >>> >>> Nit: subtracting >>> >>>> + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. >>>> + */ >>>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) >>>> + /* interrupt not enabled, ignore it */ >>> >>> Throughout the series: Please adhere to ./CODING_STYLE. >>> >>>> + return 0; >>>> + >>>> + break; >>> >>> And any value is okay to write? >> >> No, it should be in a range >> [APLIC_SOURCECFG_SM_INACTIVE,APLIC_SOURCECFG_SM_LEVEL_LOW]. >> >> I will add the check before break: >> if ( value > APLIC_SOURCECFG_SM_LEVEL_LOW ) >> { >> gdprintk(XENLOG_WARNING, >> "value(%u) is incorrect for sourcecfg register\n", >> value); >> value = APLIC_SOURCECFG_SM_INACTIVE; >> } > > And why would writing APLIC_SOURCECFG_SM_INACTIVE be any better, when > that's not what the guest wanted? Simply ignore such writes, unless the > spec mandates specific behavior for out-of-range avlues? The spec doesn't mandate specific behavior for out-of-range values but I thought it would be better to make irq inactive instead of just ignoring so it won't affect somehow potential occurrence of this interrupt. > >>>> + case APLIC_TARGET_BASE ... APLIC_TARGET_LAST: >>>> + struct vcpu *target_vcpu = NULL; >>>> + >>>> + /* >>>> + * Look at vaplic_emulate_load() for explanation why >>>> + * APLIC_GENMSI is substracted. >>>> + */ >>> >>> There's no vaplic_emulate_load() - how can I go look there? >> >> It is introduced in the next patch. > > As before - it should be possible to review patch series strictly > sequentially. Further, what if this patch gets committed, and the other > gets delayed by several months? Got you, I will re-order patches. > >>>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) >>>> + /* interrupt not enabled, ignore it */ >>>> + return 0; >>>> + >>>> + for ( int i = 0; i < vcpu->domain->max_vcpus; i++ ) >>> >>> unsigned int >>> >>>> + { >>>> + struct vcpu *v = vcpu->domain->vcpu[i]; >>>> + >>>> + if ( v->vcpu_id == (value >> APLIC_TARGET_HART_IDX_SHIFT) ) >>>> + { >>>> + target_vcpu = v; >>>> + break; >>>> + } >>>> + } >>>> + >>>> + ASSERT(target_vcpu); >>> >>> What guarantees the pointer to be non-NULL? The incoming value can be >>> arbitrary, afaict. >> >> I didn't understand your point. It is just checking that target_vcpu has >> been found. If after for() loop the value of target_vcpu is still NULL >> then something wrong in Xen. > > If that's true, then the assertion is fine to have. I can't help the > impression though that a guest could pick a value such that you can't > possibly find the target vCPU. Asserting on guest controlled input is > not okay, as was said several times before. I will then do domain_crash() that as a value is incorrect in case if target_vcpu is NULL, I missed that guest could put wrong value. > >>>> + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) >>>> + { >>>> + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor), >>>> + &value); >>>> + } >>>> + else >>>> + vaplic_update_target(priv->imsic_cfg, >>>> + vcpu_guest_file_id(target_vcpu), >>>> + cpuid_to_hartid(target_vcpu->processor), >>>> + &value); >>> >>> I'm struggling with the naming here: When DM is clear, a function with "dm" >>> in the name is called. >> >> it means direct (delivery) mode. Maybe it is better to put dm at the end >> of the function name? Or it is just better to change it to something else? > > Without a better understanding of what is wanted, all I can say is that > calling something with "dm" in its name when the condition says it's not > "dm" is confusing. Basically it should be the following. If domaincfg.DM (here dm is delivery mode according to spec) is 0 then it means that APLIC works in direct delivery mode, if DM bit is 1 then MSI delivery mode is used. So just for clarity I will rename: - vaplic_dm_update_target -> vaplic_ddm_update_target - vaplic_update_target -> vaplic_mdm_update_target Or maybe just s/ddm/direct and s/mdm/msi will be just better in the function names. > >>>> + default: >>>> + panic("%s: unsupported register offset: %#x\n", __func__, offset); >>> >>> Crashing the host for the guest doing something odd? It's odd that the function >>> only ever returns 0 anyway - it could simply return an error here (if the >>> itention is to not ignore such writes). >> >> But maybe it is a legal offset and we really want to support it? > > Still not a reason to crash the entire host? Agree, domain crash will be more then enough. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <7c059a67-3f3f-4633-aebb-939aa9ac7955@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1776698515-B3961161-1E8FF53C/0/0 X-purgate-type: clean X-purgate-size: 6758 On 20.04.2026 16:34, Oleksii Kurochko wrote: > > > On 4/20/26 3:45 PM, Jan Beulich wrote: >> On 20.04.2026 13:39, Oleksii Kurochko wrote: >>> On 4/16/26 2:51 PM, Jan Beulich wrote: >>>> On 14.04.2026 13:29, Oleksii Kurochko wrote: >>>>> On 4/2/26 2:22 PM, Jan Beulich wrote: >>>>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>>>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>>>>>> + struct dt_device_node *dev, >>>>>>> + bool need_mapping, >>>>>>> + struct rangeset *irq_ranges) >>>>>>> +{ >>>>>>> + unsigned int i, nirq; >>>>>>> + int res, irq; >>>>>>> + struct dt_raw_irq rirq; >>>>>>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>>>>>> + unsigned int reg_num; >>>>>>> + >>>>>>> + nirq = dt_number_of_irq(dev); >>>>>>> + >>>>>>> + /* Give permission and map IRQs */ >>>>>>> + for ( i = 0; i < nirq; i++ ) >>>>>>> + { >>>>>>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>>>>>> + if ( res ) >>>>>>> + { >>>>>>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>>>>>> + i, dt_node_full_name(dev)); >>>>>>> + return res; >>>>>>> + } >>>>>>> + >>>>>>> + /* >>>>>>> + * Don't map IRQ that have no physical meaning >>>>>>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>>>>>> + */ >>>>>>> + if ( rirq.controller != dt_interrupt_controller ) >>>>>>> + { >>>>>>> + dt_dprintk("irq %u not connected to primary controller." >>>>>>> + "Connected to %s\n", i, >>>>>>> + dt_node_full_name(rirq.controller)); >>>>>>> + continue; >>>>>>> + } >>>>>>> + >>>>>>> + irq = platform_get_irq(dev, i); >>>>>>> + if ( irq < 0 ) >>>>>>> + { >>>>>>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>>>>>> + return irq; >>>>>>> + } >>>>>>> + >>>>>>> + res = irq_permit_access(d, irq); >>>>>>> + if ( res ) >>>>>>> + { >>>>>>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>>>>>> + irq); >>>>>> This time the other way around: %d please with plain int. (Again at least >>>>>> once further down.) >>>>>> >>>>>>> + return res; >>>>>>> + } >>>>>>> + >>>>>>> + reg_num = irq / APLIC_NUM_REGS; >>>>>>> + >>>>>>> + if ( is_irq_shared_among_domains(d, irq) ) >>>>>>> + { >>>>>>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>>>>>> + return -EINVAL; >>>>>>> + } >>>>>>> + >>>>>>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >>>>>> ... all of this leaves me with the impression that IRQ numbering isn't really >>>>>> virtualized. IRQs are merely split into groups, one group per domain (and >>>>>> maybe some unused). How are you going to fit in truly virtual IRQs? >>>>> What do you mean by truly virtual IRQs? >>>> Ones where no aspects are represented by any piece of hardware. >>>> >>>>> I can't totally agree that the current approach isn't use virtual IRQs, >>>>> yes, they are 1:1 mapped but on the other side Xen is responsible to >>>>> give an IRQ number for guest's device and Xen is responsible that guest >>>>> isn't trying to reach IRQ which not belongs to it. >>>> In a non-virtualized environment I expect IRQs are going to be "sparse" >>>> (i.e. with perhaps large blocks of items used elsewhere). If you had >>>> proper translation of IRQ numbers, the same could be true for your >>>> guests. >>> Partial FDT, which is used to tell which device be passthroughed to >>> guest, is using physical IRQ number (which I am just considering for >>> simplicity to be 1:1 mapped to virtual IRQ number). So if we have the >>> following configuration: >>> Physical (bare-metal) IRQ layout is sparse: >>> IRQ 5 → UART -> domU0 >>> IRQ 23 → Ethernet -> domU1 >>> IRQ 47 → PCIe -> domU0 >>> IRQ 100 → Storage -> domU1 >>> (gaps everywhere, driven by hardware wiring) >>> >>> For such configuration we will have for each domain auth_irq_bmp[] which >>> contains: >>> IRQ 5 and IRQ47 for domU0 >>> and >>> IRQ 23 and IRQ 100 for domU1 >>> >>> And here vIRQ5 = pIRQ5, vIRQ47 = pIRQ47 and so on. auth_irq_bmp just >>> transform xIRQ number to bit position which it will have in real APLIC >>> register. Just as an example, lets take vIRQ5 and vIRQ47. >>> >>> As reading or writing register setie[k] reads or potentially modifies >>> the enable bits for interrupt sources k × 32 through k × 32 + 31. For an >>> implemented interrupt source i within that range, the enable bit for >>> source i corresponds with register bit (i mod 32). >>> So for: >>> - vIRQ5 == pIRQ5 we have to set bit 5 in setie[0] >>> - vIRQ47 == pIRQ47 we have to set bit 15 in setie[1] >>> >>> Probably it was not the best idea to declare auth_irq_bmp as it will >>> look in h/w and maybe just 'bool auth_irq_bmp[1024]' would be more clearer. >>> >>> So irqs number are still stay "sparsed" in guest. >> Well, twice (or more) as sparse in the example you give, compared to the >> host. > > Just to be sure that I fully understand your concern here. > > The difference between xIRQ5 and xIRQ47 is 42 bits (if for 1 irq we are > using 1 bit) which leads to that we have somewhere allocated 48 bit > bitmap where only two bits will be set, all others will be zero. Why 48-bit bitmap? As you inherit the property from the host, it'll be e.g. 1024 bits. Compared to the host, each guest will have yet fewer bits set in there. > Instead it would be better to have to do mapping: pIRQ5 -> vIRQ1, pIRQ47 > ->vIRQ2, right? Which specific mapping I don't care very much. There may also be conventions to adhere to (on x86 for example there are). > If yes, won't we still store somewhere this mapping? it seems like > having 'unsigned int auth_irq_bmp[1024]' is a good option where index > will be vIRQ number and 'unsigned int' will be pIRQ number. But at the > moment I think that we could go with 1:1 IRQ number mapping and then > have 'bool auth_irq_bmp[1024]' will be more then enough and will safe > some memory. Well, if using 1:1 mapping was clearly identified as "for the time being", then that might be acceptable (for the time being). As to you (again) suggesting "bool auth_irq_bmp[1024]" - why would you use an array of bool-s when a bitmap can do the same in 1/8th of the space? Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:23:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:23:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286209.1567313 (Exim 4.92) (envelope-from ) id 1wEqTI-0002nI-MC; Mon, 20 Apr 2026 15:23:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286209.1567313; Mon, 20 Apr 2026 15:23:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqTI-0002nB-I0; Mon, 20 Apr 2026 15:23:36 +0000 Received: by outflank-mailman (input) for mailman id 1286209; Mon, 20 Apr 2026 15:23:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqTH-0002n5-SD for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:23:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEqTH-007yMB-7O for xen-devel@lists.xenproject.org; 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Regards, -- -- Yann Sionneau | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:23:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:23:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286211.1567321 (Exim 4.92) (envelope-from ) id 1wEqTV-000358-1C; Mon, 20 Apr 2026 15:23:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286211.1567321; Mon, 20 Apr 2026 15:23:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqTU-00034z-T4; Mon, 20 Apr 2026 15:23:48 +0000 Received: by outflank-mailman (input) for mailman id 1286211; Mon, 20 Apr 2026 15:23:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqTT-00034F-AW for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: viS8hH7JOx8kQG6k67LkzxPK5J3QVzDw7sCOt7FULkez3z1/ygcpn4iV/Evozct7fvWU8BxlTmROkRq5jufnxOBw3mzuOyoxJEK8DWCrFQLW6nbfE+VFnDfu5Jy5RHH7sERbO+RmaEA7Vj3/OgtVgRT3V+TOkHwSkYFezkjoUmBp6HeDizcr+RMXHVEv0Qkvp+EZk3x16pYhaDIjIOJ2RA2MuvEJk004DvUmBEMWRjs2ZLOl/P4qmkGqe0nG/wfVQiAVbGtIfywrF6BCLhSePQyHQWu9daJruWJRzp1EGePxypaKLBnWXVr57Wj9tLrEYs60AKzKOc2w6Q+q6u0NTusRZfKmgTW/u2D6J5rcrCZgmaAS3uj/X2ohsHxvZLXTxmbLgFwxbY7rvJuAhUhXFTDy/cgMk07KtL7caP8AfLCS7eI0e8mKqeV0gg4v91b1 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 15:23:41.2021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7951f75-516c-48c1-3896-08de9ef0cda9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000094.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9548 X-purgate-ID: tlsNG-ebf023/1776698625-4BB6B3FF-45C80D12/0/0 X-purgate-type: clean X-purgate-size: 1286 Hi Mykola, > On 2 Apr 2026, at 11:45, Mykola Kvach wrote: >=20 > From: Mirela Simonovic >=20 > Timer interrupts must be disabled while the system is suspended to preven= t > spurious wake-ups. Suspending timers in Xen consists of disabling the > physical timer and the hypervisor timer on the current CPU. The virtual > timer does not need explicit handling here, as it is already disabled on > vCPU context switch and its state is restored per-vCPU on the next contex= t > restore. >=20 > Resuming consists of raising TIMER_SOFTIRQ, which prompts the generic > timer code to reprogram the hypervisor timer with the correct timeout. >=20 > Xen does not use or expose the physical timer, so it remains disabled > across suspend/resume. >=20 > Introduce a new helper, disable_phys_hyp_timers(), to encapsulate disabli= ng > of the physical and hypervisor timers. >=20 > Signed-off-by: Mirela Simonovic > Signed-off-by: Saeed Nowshadi > Signed-off-by: Mykola Kvach > Acked-by: Julien Grall > --- >=20 Changes looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:27:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:27:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286227.1567331 (Exim 4.92) (envelope-from ) id 1wEqX2-0003tI-Fh; Mon, 20 Apr 2026 15:27:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286227.1567331; Mon, 20 Apr 2026 15:27:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqX2-0003tA-Bk; Mon, 20 Apr 2026 15:27:28 +0000 Received: by outflank-mailman (input) for mailman id 1286227; Mon, 20 Apr 2026 15:27:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqX1-0003t4-6m for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:27:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEqX0-000eNK-G4 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 17:27:26 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e645d0-bab6-0a2a0a5309dd-0a2a4506a18c-12 for ; Mon, 20 Apr 2026 17:27:26 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e645de-7371-0a2a45060019-d1558034ed53-3 for ; Mon, 20 Apr 2026 17:27:26 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4891e86fabeso12810805e9.1 for ; Mon, 20 Apr 2026 08:27:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <276c68cb-51c0-4775-8b70-3af80d0d0f27@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776698846-51D6AD75-A2455228/0/0 X-purgate-type: clean X-purgate-size: 6505 On 20.04.2026 17:02, Oleksii Kurochko wrote: > On 4/16/26 3:19 PM, Jan Beulich wrote: >> On 14.04.2026 18:04, Oleksii Kurochko wrote: >>> On 4/2/26 4:18 PM, Jan Beulich wrote: >>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>> +static int cf_check vaplic_emulate_store(const struct vcpu *vcpu, >>>>> + unsigned long addr, uint32_t value) >>>>> +{ >>>>> + struct vaplic *vaplic = to_vaplic(vcpu->domain->arch.vintc); >>>>> + struct aplic_priv *priv = vaplic->base.info->private; >>>>> + uint32_t offset = addr & APLIC_REG_OFFSET_MASK; >>>> >>>> See ./CODING_STYLE as to uses of fixed-width types. >>>> >>>>> + unsigned long aplic_addr = addr - priv->paddr_start; >>>>> + const uint32_t *auth_irq_bmp = vcpu->domain->arch.vintc->private; >>>>> + >>>>> + switch ( offset ) >>>>> + { >>>>> + case APLIC_SETIP_BASE ... APLIC_SETIP_LAST: >>>> >>>> And (taking this just as example) any misaligned accesses falling in this range >>>> are fine? >>> >>> Do you mean something like 0x1C02 instead of 0x1C00 or 0x1C04? >> >> Yes. >> >>>>> + /* >>>>> + * As sourcecfg register starts from 1: >>>>> + * 0x0000 domaincfg >>>>> + * 0x0004 sourcecfg[1] >>>>> + * 0x0008 sourcecfg[2] >>>>> + * ... >>>>> + * 0x0FFC sourcecfg[1023] >>>>> + * It is necessary to calculate an interrupt number by substracting >>>> >>>> Nit: subtracting >>>> >>>>> + * of APLIC_DOMAINCFG instead of APLIC_SOURCECFG_BASE. >>>>> + */ >>>>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_DOMAINCFG)) ) >>>>> + /* interrupt not enabled, ignore it */ >>>> >>>> Throughout the series: Please adhere to ./CODING_STYLE. >>>> >>>>> + return 0; >>>>> + >>>>> + break; >>>> >>>> And any value is okay to write? >>> >>> No, it should be in a range >>> [APLIC_SOURCECFG_SM_INACTIVE,APLIC_SOURCECFG_SM_LEVEL_LOW]. >>> >>> I will add the check before break: >>> if ( value > APLIC_SOURCECFG_SM_LEVEL_LOW ) >>> { >>> gdprintk(XENLOG_WARNING, >>> "value(%u) is incorrect for sourcecfg register\n", >>> value); >>> value = APLIC_SOURCECFG_SM_INACTIVE; >>> } >> >> And why would writing APLIC_SOURCECFG_SM_INACTIVE be any better, when >> that's not what the guest wanted? Simply ignore such writes, unless the >> spec mandates specific behavior for out-of-range avlues? > > The spec doesn't mandate specific behavior for out-of-range values but I > thought it would be better to make irq inactive instead of just ignoring > so it won't affect somehow potential occurrence of this interrupt. I'd find it concerning if we did anything not mandated by the spec. Just doing nothing is imo still the best course of action. >>>>> + if ( !AUTH_IRQ_BIT(regval_to_irqn(offset - APLIC_GENMSI)) ) >>>>> + /* interrupt not enabled, ignore it */ >>>>> + return 0; >>>>> + >>>>> + for ( int i = 0; i < vcpu->domain->max_vcpus; i++ ) >>>> >>>> unsigned int >>>> >>>>> + { >>>>> + struct vcpu *v = vcpu->domain->vcpu[i]; >>>>> + >>>>> + if ( v->vcpu_id == (value >> APLIC_TARGET_HART_IDX_SHIFT) ) >>>>> + { >>>>> + target_vcpu = v; >>>>> + break; >>>>> + } >>>>> + } >>>>> + >>>>> + ASSERT(target_vcpu); >>>> >>>> What guarantees the pointer to be non-NULL? The incoming value can be >>>> arbitrary, afaict. >>> >>> I didn't understand your point. It is just checking that target_vcpu has >>> been found. If after for() loop the value of target_vcpu is still NULL >>> then something wrong in Xen. >> >> If that's true, then the assertion is fine to have. I can't help the >> impression though that a guest could pick a value such that you can't >> possibly find the target vCPU. Asserting on guest controlled input is >> not okay, as was said several times before. > > I will then do domain_crash() that as a value is incorrect in case if > target_vcpu is NULL, I missed that guest could put wrong value. Would domain_crash() come close to anything real hardware would do? I doubt it. Doing nothing (besides perhaps logging a debug message) may once again the best we can do. >>>>> + if ( !(vaplic->regs.domaincfg & APLIC_DOMAINCFG_DM) ) >>>>> + { >>>>> + vaplic_dm_update_target(cpuid_to_hartid(target_vcpu->processor), >>>>> + &value); >>>>> + } >>>>> + else >>>>> + vaplic_update_target(priv->imsic_cfg, >>>>> + vcpu_guest_file_id(target_vcpu), >>>>> + cpuid_to_hartid(target_vcpu->processor), >>>>> + &value); >>>> >>>> I'm struggling with the naming here: When DM is clear, a function with "dm" >>>> in the name is called. >>> >>> it means direct (delivery) mode. Maybe it is better to put dm at the end >>> of the function name? Or it is just better to change it to something else? >> >> Without a better understanding of what is wanted, all I can say is that >> calling something with "dm" in its name when the condition says it's not >> "dm" is confusing. > > Basically it should be the following. If domaincfg.DM (here dm is > delivery mode according to spec) is 0 then it means that APLIC works in > direct delivery mode, if DM bit is 1 then MSI delivery mode is used. > > So just for clarity I will rename: > - vaplic_dm_update_target -> vaplic_ddm_update_target > - vaplic_update_target -> vaplic_mdm_update_target > > Or maybe just s/ddm/direct and s/mdm/msi will be just better in the > function names. Afaic - yes to these latter two names. >>>>> + default: >>>>> + panic("%s: unsupported register offset: %#x\n", __func__, offset); >>>> >>>> Crashing the host for the guest doing something odd? It's odd that the function >>>> only ever returns 0 anyway - it could simply return an error here (if the >>>> itention is to not ignore such writes). >>> >>> But maybe it is a legal offset and we really want to support it? >> >> Still not a reason to crash the entire host? > > Agree, domain crash will be more then enough. See above as to even that possibly being too harsh. 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bh=zrDGop4vqMVPetlkme5uH9vCu0jZJzVmxo6QNeagp3c=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=CnD9fh5WTIOMfkyn2yuq0Muyz145oTN8KsOsxJE4QZANwt/Fae/R68zIOI6O2QXu4 K2cuR2pI8I6QxTSpZrqMbgeL2vtSsih6vASAz85BnWIk8GRrxQsMmQLizamigxoS1x n1OX5OCULTZREpZxWYxGmBBmXTLPaMq5JyOlQ2Sm5eMfR1dH/hxRJCElfioFklLq1e TyzLQabmP6Qo3uavO7igzXMooQSqka6rFW7eOK6YAUQAj8Voigl36ajIKK3TWHTkK3 Oig3IGPI9i/558cSSLNQUe4PLYU0kTEwPhfQ4HE+ct7TEBwwl0loIQ937V61u+sxIT V1XyGwf1BoqGA== From: "Yann Sionneau" Subject: =?utf-8?Q?Re:=20[PATCH=201/8]=20xen/arm:=20Implement=20p2m=5Fset=5Fentry=20for=20MPU=20systems?= X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776698952944 Message-Id: <6cb62e24-54e2-4ae8-823f-8cc37af9c224@vates.tech> To: "Luca Fancellu" Cc: xen-devel@lists.xenproject.org, "Penny Zheng" , "Stefano Stabellini" , "Julien Grall" , "Bertrand Marquis" , "Michal Orzel" , "Volodymyr Babchuk" , "Wei Chen" , "Hari Limaye" , "Harry Ramsey" References: <20260420142524.1804073-1-luca.fancellu@arm.com> <20260420142524.1804073-2-luca.fancellu@arm.com> <758d9182-aa50-4c60-9834-bf8136c4ef3d@vates.tech> <9D8E2C9A-FAA4-49C4-BABB-968B61314B90@arm.com> In-Reply-To: <9D8E2C9A-FAA4-49C4-BABB-968B61314B90@arm.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.2d3ff4bb5334467fb90e2e3739eaca1c?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260420:md Date: Mon, 20 Apr 2026 15:29:14 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1776698956-C1161DB1-A9DBF543/0/0 X-purgate-type: clean X-purgate-size: 1042 On 4/20/26 17:28, Luca Fancellu wrote: > Hi Yann, > >> On 20 Apr 2026, at 16:23, Yann Sionneau wrote= : >> >> On 4/20/26 16:27, Luca Fancellu wrote: >>> From: Penny Zheng >>> >>> Implement the function `p2m_set_entry`, which is responsible for >>> inserting a new entry into the p2m tables, for MPU systems. >>> >> Hello Luca, >> >> It seems this patch does not apply on master if I'm not mistaken. > > This serie applies on top of these patches: > https://patchwork.kernel.org/project/xen-devel/list/?series=3D1083371 > > In the cover letter I wrote: > > ``` > [=E2=80=A6] > The serie is based on another serie in the mailing list: "Fifth MPU Serie= s". > [=E2=80=A6] > ``` > > Cheers, > Luca > > Oopsy, sorry for the noise, I checked but ... it seems I did not read the cover letter carefully enough :) Regards, -- -- Yann Sionneau | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:31:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:31:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286257.1567357 (Exim 4.92) (envelope-from ) id 1wEqat-0006Jq-Fy; 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AFNElJ8Z7t/AqnXufse9+H+cDyLx3eKXTysSNiwzKQMoWtCVgLi3wBqBAmwIRc4JKqkRHnlpIefBr2QmfVo=@lists.xenproject.org X-Gm-Message-State: AOJu0YyHNPohB67h0NnVc5IIBE705HtEK4npBQeIxAs9eZUj0iCls6m+ lyistn3EHlmR20AqOuvdinf0Ntc3OrSqQJbW6rPIOYVf0VGn1R0Qe+D0 X-Gm-Gg: AeBDievIygYzXQ+oMKC4Bb2cIWZc7dWvcTIIBjmm12jnnzDCNqANKh1x4bIzq0QtSxC IUNG0zZWkpZ2KMEms1WcX09H0Wk9Eik8XUPf1iybLpdyjF5C9hC7i7LowTiPTaWljBraweDf/mR PKQW5gD9SIrLxgOJoxQ0TYHxDo069ViNC7b8eD2WNwuIcTyXUTIoskHjDGrvopwVXT0YlbMfWsb uyAkb14bgA6MkdcfVgKMBhqCt6m0if/BH1ZFs2KaIBGZCkPXPahxLRWTnyUGcJfrUvWOm0+b4YQ H+NVluREQndeDDWW1aJhVCexregwD8y55ONkL/45hooQLjJf6POf8aG3gSuOmgGJMajtatKYvPP 9E5hzjpB7kgC/EpWRLCY5oce08yegnW9gHpDJbH2AUmqQLLm6L+hm0Z13ARg+x4gWYOm5QL/jS4 1Me942+f2irJAbALSwMYLTCH24FrVk1RQxEmKGJOeGVcrp7/QgqewkqU6MYgBCAxAvhgxPLAvqQ p5Uh+4tuA5oAg== X-Received: by 2002:a05:6512:3b91:b0:5a4:9a7:7e66 with SMTP id 2adb3069b0e04-5a4172faa04mr5449547e87.45.1776699083601; Mon, 20 Apr 2026 08:31:23 -0700 (PDT) Message-ID: <6042263f-49e5-4139-978f-38cb10769c0e@gmail.com> Date: Mon, 20 Apr 2026 17:31:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 16/27] xen/riscv: implement IRQ mapping for device passthrough To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <10654a6c38fa929b5fdf6f214badfe4f60fe78d4.1773157782.git.oleksii.kurochko@gmail.com> <8a8a2afd-6f53-4f45-b8c8-fb34a6fbb970@suse.com> <00fa439d-0327-4c0c-960d-a810820a6e83@gmail.com> <09a260ca-5a98-461d-9f57-d298a483d3d6@suse.com> <7c059a67-3f3f-4633-aebb-939aa9ac7955@gmail.com> <0ccf093f-cc2a-4729-bf8f-b39bf73fd202@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <0ccf093f-cc2a-4729-bf8f-b39bf73fd202@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776699084-7D76AF3B-389658C6/10/73395122804 X-purgate-type: spam X-purgate-size: 7430 On 4/20/26 5:21 PM, Jan Beulich wrote: > On 20.04.2026 16:34, Oleksii Kurochko wrote: >> >> >> On 4/20/26 3:45 PM, Jan Beulich wrote: >>> On 20.04.2026 13:39, Oleksii Kurochko wrote: >>>> On 4/16/26 2:51 PM, Jan Beulich wrote: >>>>> On 14.04.2026 13:29, Oleksii Kurochko wrote: >>>>>> On 4/2/26 2:22 PM, Jan Beulich wrote: >>>>>>> On 10.03.2026 18:08, Oleksii Kurochko wrote: >>>>>>>> +int vaplic_map_device_irqs_to_domain(struct domain *d, >>>>>>>> + struct dt_device_node *dev, >>>>>>>> + bool need_mapping, >>>>>>>> + struct rangeset *irq_ranges) >>>>>>>> +{ >>>>>>>> + unsigned int i, nirq; >>>>>>>> + int res, irq; >>>>>>>> + struct dt_raw_irq rirq; >>>>>>>> + uint32_t *auth_irq_bmp = d->arch.vintc->private; >>>>>>>> + unsigned int reg_num; >>>>>>>> + >>>>>>>> + nirq = dt_number_of_irq(dev); >>>>>>>> + >>>>>>>> + /* Give permission and map IRQs */ >>>>>>>> + for ( i = 0; i < nirq; i++ ) >>>>>>>> + { >>>>>>>> + res = dt_device_get_raw_irq(dev, i, &rirq); >>>>>>>> + if ( res ) >>>>>>>> + { >>>>>>>> + printk(XENLOG_ERR "Unable to retrieve irq %u for %s\n", >>>>>>>> + i, dt_node_full_name(dev)); >>>>>>>> + return res; >>>>>>>> + } >>>>>>>> + >>>>>>>> + /* >>>>>>>> + * Don't map IRQ that have no physical meaning >>>>>>>> + * ie: IRQ whose controller is not APLIC/IMSIC/PLIC. >>>>>>>> + */ >>>>>>>> + if ( rirq.controller != dt_interrupt_controller ) >>>>>>>> + { >>>>>>>> + dt_dprintk("irq %u not connected to primary controller." >>>>>>>> + "Connected to %s\n", i, >>>>>>>> + dt_node_full_name(rirq.controller)); >>>>>>>> + continue; >>>>>>>> + } >>>>>>>> + >>>>>>>> + irq = platform_get_irq(dev, i); >>>>>>>> + if ( irq < 0 ) >>>>>>>> + { >>>>>>>> + printk("Unable to get irq %u for %s\n", i, dt_node_full_name(dev)); >>>>>>>> + return irq; >>>>>>>> + } >>>>>>>> + >>>>>>>> + res = irq_permit_access(d, irq); >>>>>>>> + if ( res ) >>>>>>>> + { >>>>>>>> + printk(XENLOG_ERR "Unable to permit to %pd access to IRQ %u\n", d, >>>>>>>> + irq); >>>>>>> This time the other way around: %d please with plain int. (Again at least >>>>>>> once further down.) >>>>>>> >>>>>>>> + return res; >>>>>>>> + } >>>>>>>> + >>>>>>>> + reg_num = irq / APLIC_NUM_REGS; >>>>>>>> + >>>>>>>> + if ( is_irq_shared_among_domains(d, irq) ) >>>>>>>> + { >>>>>>>> + printk("%s: Shared IRQ isn't supported\n", __func__); >>>>>>>> + return -EINVAL; >>>>>>>> + } >>>>>>>> + >>>>>>>> + auth_irq_bmp[reg_num] |= BIT(irq % APLIC_NUM_REGS, U); >>>>>>> ... all of this leaves me with the impression that IRQ numbering isn't really >>>>>>> virtualized. IRQs are merely split into groups, one group per domain (and >>>>>>> maybe some unused). How are you going to fit in truly virtual IRQs? >>>>>> What do you mean by truly virtual IRQs? >>>>> Ones where no aspects are represented by any piece of hardware. >>>>> >>>>>> I can't totally agree that the current approach isn't use virtual IRQs, >>>>>> yes, they are 1:1 mapped but on the other side Xen is responsible to >>>>>> give an IRQ number for guest's device and Xen is responsible that guest >>>>>> isn't trying to reach IRQ which not belongs to it. >>>>> In a non-virtualized environment I expect IRQs are going to be "sparse" >>>>> (i.e. with perhaps large blocks of items used elsewhere). If you had >>>>> proper translation of IRQ numbers, the same could be true for your >>>>> guests. >>>> Partial FDT, which is used to tell which device be passthroughed to >>>> guest, is using physical IRQ number (which I am just considering for >>>> simplicity to be 1:1 mapped to virtual IRQ number). So if we have the >>>> following configuration: >>>> Physical (bare-metal) IRQ layout is sparse: >>>> IRQ 5 → UART -> domU0 >>>> IRQ 23 → Ethernet -> domU1 >>>> IRQ 47 → PCIe -> domU0 >>>> IRQ 100 → Storage -> domU1 >>>> (gaps everywhere, driven by hardware wiring) >>>> >>>> For such configuration we will have for each domain auth_irq_bmp[] which >>>> contains: >>>> IRQ 5 and IRQ47 for domU0 >>>> and >>>> IRQ 23 and IRQ 100 for domU1 >>>> >>>> And here vIRQ5 = pIRQ5, vIRQ47 = pIRQ47 and so on. auth_irq_bmp just >>>> transform xIRQ number to bit position which it will have in real APLIC >>>> register. Just as an example, lets take vIRQ5 and vIRQ47. >>>> >>>> As reading or writing register setie[k] reads or potentially modifies >>>> the enable bits for interrupt sources k × 32 through k × 32 + 31. For an >>>> implemented interrupt source i within that range, the enable bit for >>>> source i corresponds with register bit (i mod 32). >>>> So for: >>>> - vIRQ5 == pIRQ5 we have to set bit 5 in setie[0] >>>> - vIRQ47 == pIRQ47 we have to set bit 15 in setie[1] >>>> >>>> Probably it was not the best idea to declare auth_irq_bmp as it will >>>> look in h/w and maybe just 'bool auth_irq_bmp[1024]' would be more clearer. >>>> >>>> So irqs number are still stay "sparsed" in guest. >>> Well, twice (or more) as sparse in the example you give, compared to the >>> host. >> >> Just to be sure that I fully understand your concern here. >> >> The difference between xIRQ5 and xIRQ47 is 42 bits (if for 1 irq we are >> using 1 bit) which leads to that we have somewhere allocated 48 bit >> bitmap where only two bits will be set, all others will be zero. > > Why 48-bit bitmap? As you inherit the property from the host, it'll be e.g. > 1024 bits. Compared to the host, each guest will have yet fewer bits set in > there. 48-bit bitmap specifically in this example because IRQ47 is the highest mentioned here, so if we won't compress zeros between IRQ0-4 and IRQ6-46 it will be needed 48-bit to cover IRQs from IRQ0 to IRQ47. I thought about that as it seems like I misunderstood what you mean by "sparsed in guest" and the way how I have to deal with that. > >> Instead it would be better to have to do mapping: pIRQ5 -> vIRQ1, pIRQ47 >> ->vIRQ2, right? > > Which specific mapping I don't care very much. There may also be conventions > to adhere to (on x86 for example there are). If just bitmap is okay here ... then I am okay with using it. > >> If yes, won't we still store somewhere this mapping? it seems like >> having 'unsigned int auth_irq_bmp[1024]' is a good option where index >> will be vIRQ number and 'unsigned int' will be pIRQ number. But at the >> moment I think that we could go with 1:1 IRQ number mapping and then >> have 'bool auth_irq_bmp[1024]' will be more then enough and will safe >> some memory. > > Well, if using 1:1 mapping was clearly identified as "for the time being", > then that might be acceptable (for the time being). > > As to you (again) suggesting "bool auth_irq_bmp[1024]" - why would you use > an array of bool-s when a bitmap can do the same in 1/8th of the space? ... just bitmap will better. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:43:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:43:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286271.1567367 (Exim 4.92) (envelope-from ) id 1wEqmI-0000BG-GJ; Mon, 20 Apr 2026 15:43:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286271.1567367; Mon, 20 Apr 2026 15:43:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqmI-0000B8-Cj; Mon, 20 Apr 2026 15:43:14 +0000 Received: by outflank-mailman (input) for mailman id 1286271; Mon, 20 Apr 2026 15:43:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEqmH-0000B1-6P for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:43:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEqmG-00Dxww-Ja for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 17:43:12 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e64961-5cb7-0a2a0a5109dd-0a2a4503bb5a-44 for ; Mon, 20 Apr 2026 17:43:12 +0200 Received: from [209.85.208.181] (helo=mail-lj1-f181.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e64990-672d-0a2a45030019-d155d0b5e841-3 for ; Mon, 20 Apr 2026 17:43:12 +0200 Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-38e7d983f91so35157511fa.2 for ; Mon, 20 Apr 2026 08:43:12 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Straightforward bug fixes may continue to be accepted by maintainers beyond this point. They could go without R-Acked. If you would like your features included in this release, please ensure they are committed by the deadline. Thank you in advance, and have a great week! Best regards, Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:43:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:43:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286273.1567374 (Exim 4.92) (envelope-from ) id 1wEqmR-0000R3-M8; Mon, 20 Apr 2026 15:43:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286273.1567374; Mon, 20 Apr 2026 15:43:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqmR-0000Qw-Ir; Mon, 20 Apr 2026 15:43:23 +0000 Received: by outflank-mailman (input) for mailman id 1286273; Mon, 20 Apr 2026 15:43:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEqmP-0000Q2-VJ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:43:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEqmP-00BTxY-Bq for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 17:43:21 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e64985-bab6-0a2a0a5309dd-0a2a450191e4-24 for ; Mon, 20 Apr 2026 17:43:21 +0200 Received: from [209.85.128.43] (helo=mail-wm1-f43.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e64999-c1f2-0a2a45010019-d155802bb5d9-3 for ; Mon, 20 Apr 2026 17:43:21 +0200 Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-488b150559bso24874805e9.1 for ; Mon, 20 Apr 2026 08:43:21 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <9154aea41a11bc0ba95ad15c217db79d029dd119.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776699801-BC617FF4-BD82409F/10/73395122804 X-purgate-type: spam X-purgate-size: 2241 On 10.04.2026 17:54, Oleksii Kurochko wrote: > Widen the len argument of copy_to_guest_phys_flush_dcache() and the > copy_to_guest_phys_cb typedef from unsigned int to unsigned long, as > the function can be used to copy large blobs such as the initrd which > may exceed 4GB. Update the internal copy_guest() len argument to > unsigned long accordingly. > > Change the type for local variable size in copy_guest() to avoid > compilation error because of type mismatch. > > raw_* wrappers above copy_guest() keep returning unsigned long to > avoid type narrowing; it is not an issue for raw_*'s len argument > to remain 'unsigned int' since the assignment to copy_guest()'s wider > unsigned long parameter is safe and there is no raw_* users who > are using a value bigger than what can fit into 'unsigned int'. > > Reported-by: Jan Beulich > Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich With two suggestions: For one, the patch subject prefix may want to be (or include) "arm:", to draw Arm maintainers' attention. And then ... > --- a/xen/arch/arm/guestcopy.c > +++ b/xen/arch/arm/guestcopy.c > @@ -53,7 +53,7 @@ static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, > return page; > } > > -static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, > +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, > copy_info_t info, unsigned int flags) > { > /* XXX needs to handle faults */ > @@ -65,7 +65,7 @@ static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, > while ( len ) > { > void *p; > - unsigned int size = min(len, (unsigned int)PAGE_SIZE - offset); > + unsigned long size = min_t(unsigned long, len, PAGE_SIZE - offset); ... I think we'd be better off avoiding min_t() whenever possible, i.e. when min() can sensibly be used (preferably, unlike originally here, also without a cast). PAGE_SIZE being of type long, "PAGE_SIZE + 0UL - offset" would look to be an option. Yet of course Arm maintainers may dislike that form ... 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776699875-886D4161-9CCD578C/10/73395122804 X-purgate-type: spam X-purgate-size: 1044 On 10.04.2026 17:54, Oleksii Kurochko wrote: > Widen the len argument of copy_to_guest_phys_flush_dcache() and the > copy_to_guest_phys_cb typedef from unsigned int to unsigned long, as > the function can be used to copy large blobs such as the initrd which > may exceed 4GB. Update the internal copy_guest() len argument to > unsigned long accordingly. > > Change the type for local variable size in copy_guest() to avoid > compilation error because of type mismatch. > > raw_* wrappers above copy_guest() keep returning unsigned long to > avoid type narrowing; it is not an issue for raw_*'s len argument > to remain 'unsigned int' since the assignment to copy_guest()'s wider > unsigned long parameter is safe and there is no raw_* users who > are using a value bigger than what can fit into 'unsigned int'. > > Reported-by: Jan Beulich > Signed-off-by: Oleksii Kurochko Actually: You say "fix" in the subject. How about sorting out a correct Fixes: tag then? Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:47:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:47:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286304.1567397 (Exim 4.92) (envelope-from ) id 1wEqpv-0001nC-IF; Mon, 20 Apr 2026 15:46:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286304.1567397; Mon, 20 Apr 2026 15:46:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEqpv-0001n5-Ee; Mon, 20 Apr 2026 15:46:59 +0000 Received: by outflank-mailman (input) for mailman id 1286304; Mon, 20 Apr 2026 15:46:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEqpu-0001mz-J8 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 15:46:58 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEqpt-0092gc-Le for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 17:46:57 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e64a68-5cb7-0a2a0a5109dd-0a2a45079ae8-16 for ; Mon, 20 Apr 2026 17:46:57 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e64a71-229c-0a2a45070019-d1558031bcfe-3 for ; Mon, 20 Apr 2026 17:46:57 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4896c22fcbaso7689745e9.0 for ; Mon, 20 Apr 2026 08:46:57 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <265d9fe7c0ff46c1c969156c889e133593d57fff.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776700017-AF57BC48-A4402F70/10/73395122804 X-purgate-type: spam X-purgate-size: 2918 On 10.04.2026 17:54, Oleksii Kurochko wrote: > Introduce copy_to_guest_phys() for RISC-V, based on the Arm implementation. > > Add a generic copy_guest() helper for copying to and from guest physical > (and potentially virtual addresses in the future), and implement > translate_get_page() to translate a guest physical address into a struct > page_info via the domain p2m. > > Compared to the Arm code: > - Drop COPY_flush_dcache(), as no such use cases exist on RISC-V. > - Do not implement the linear mapping case, which is currently unused. > - Use PAGE_OFFSET() to initialize the local offset variable in copy_guest(). > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich with ... > --- /dev/null > +++ b/xen/arch/riscv/guestcopy.c > @@ -0,0 +1,116 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#define COPY_from_guest 0U > +#define COPY_to_guest BIT(0, U) > +#define COPY_gpa 0U > +#define COPY_gva BIT(1, U) > + > +typedef union > +{ > + struct > + { > + struct vcpu *v; > + } gva; > + > + struct > + { > + struct domain *d; > + } gpa; > +} copy_info_t; > + > +#define GVA_INFO(vcpu) ((copy_info_t) { .gva = { vcpu } }) > +#define GPA_INFO(domain) ((copy_info_t) { .gpa = { domain } }) > + > +static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, > + bool gva, bool write) > +{ > + p2m_type_t p2mt; > + struct page_info *page; > + > + /* > + * Not implemented yet. > + * > + * If gva == true, the operation will likely require a struct vcpu > + * rather than just a struct domain. For this reason copy_info_t is > + * already passed here instead of only struct domain. > + */ > + BUG_ON(gva); > + > + page = get_page_from_gfn(info.gpa.d, paddr_to_pfn(addr), &p2mt, P2M_ALLOC); > + > + if ( !page ) > + return NULL; > + > + if ( write ? p2mt != p2m_ram_rw : !p2m_is_ram(p2mt) ) > + { > + put_page(page); > + return NULL; > + } > + > + return page; > +} > + > +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, > + copy_info_t info, unsigned int flags) > +{ > + unsigned int offset = PAGE_OFFSET(addr); > + > + BUILD_BUG_ON((sizeof(addr)) < sizeof(vaddr_t)); > + BUILD_BUG_ON((sizeof(addr)) < sizeof(paddr_t)); > + > + while ( len ) > + { > + void *p; > + unsigned long size = min_t(unsigned long, len, PAGE_SIZE - offset); ... this adjusted to whatever the final shape is going to be on Arm. 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Mon, 20 Apr 2026 08:49:20 -0700 (PDT) Message-ID: <5752e2b2-9d5d-4bd0-b645-0f4d06035be0@suse.com> Date: Mon, 20 Apr 2026 17:49:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/8] tools/xenstored: add support for watch depth feature To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260313074751.2904215-1-jgross@suse.com> Content-Language: en-US From: Juergen Gross Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <20260313074751.2904215-1-jgross@suse.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------K0et2j3EZuDg5QB8H8WWtxpi" X-purgate-ID: tlsNG-16d1c6/1776700161-51F6BD75-EBFAFC66/0/0 X-purgate-type: clean X-purgate-size: 11508 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------K0et2j3EZuDg5QB8H8WWtxpi Content-Type: multipart/mixed; boundary="------------kOYSd3m3MjnfZUdUIOIM0Pjp"; protected-headers="v1" From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Message-ID: <5752e2b2-9d5d-4bd0-b645-0f4d06035be0@suse.com> Subject: Re: [PATCH 0/8] tools/xenstored: add support for watch depth feature References: <20260313074751.2904215-1-jgross@suse.com> In-Reply-To: <20260313074751.2904215-1-jgross@suse.com> Autocrypt-Gossip: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJ3BBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AAIQkQoDSui/t3IH4WIQQ+pJkfkcoLMCa4X6CgNK6L+3cgfgn7AJ9DmMd0SMJE ePbc7/m22D2v04iu7ACffXTdZQhNl557tJuDXZSBxDmW/tLOwU0EWTecRBAIAIK5OMKMU5R2 Lk2bbjgX7vyQuCFFyKf9rC/4itNwhYWFSlKzVj3WJBDsoi2KvPm7AI+XB6NIkNAkshL5C0kd pcNd5Xo0jRR5/WE/bT7LyrJ0OJWS/qUit5eNNvsO+SxGAk28KRa1ieVLeZi9D03NL0+HIAtZ tecfqwgl3Y72UpLUyt+r7LQhcI/XR5IUUaD4C/chB4Vq2QkDKO7Q8+2HJOrFIjiVli4lU+Sf OBp64m//Y1xys++Z4ODoKh7tkh5DxiO3QBHG7bHK0CSQsJ6XUvPVYubAuy1XfSDzSeSBl//C v78Fclb+gi9GWidSTG/4hsEzd1fY5XwCZG/XJJY9M/sAAwUH/09Ar9W2U1Qm+DwZeP2ii3Ou 14Z9VlVVPhcEmR/AFykL9dw/OV2O/7cdi52+l00reUu6Nd4Dl8s4f5n8b1YFzmkVVIyhwjvU jxtPyUgDOt6DRa+RaDlXZZmxQyWcMv2anAgYWGVszeB8Myzsw8y7xhBEVV1S+1KloCzw4V8Z DSJrcsZlyMDoiTb7FyqxwQnM0f6qHxWbmOOnbzJmBqpNpFuDcz/4xNsymJylm6oXiucHQBAP Xb/cE1YNHpuaH4SRhIxwQilCYEznWowQphNAbJtEKOmcocY7EbSt8VjXTzmYENkIfkrHRyXQ dUm5AoL51XZljkCqNwrADGkTvkwsWSvCSQQYEQIACQUCWTecRAIbDAAKCRCgNK6L+3cgfuef AJ9wlZQNQUp0KwEf8Tl37RmcxCL4bQCcC5alCSMzUBJ5DBIcR4BY+CyQFAs= --------------kOYSd3m3MjnfZUdUIOIM0Pjp Content-Type: multipart/mixed; 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnmSv8FAwAAAAAACgkQsN6d1ii/Ey+0 qgf/Z+g7e9GmVzIfFyzWKjBLroIMMhYzPJZz0TH8vnZKuMtN8eIyLqY1fm4viM5SrvG3UyJfdMlz DnGoyHfn1zWCtYaZr0pDOiFk/6oivc0mTFuIHzTWknkJRzEb+GTwkCV783ZsOv1/1OOsJNZWTp/1 S4nNBc+J+jztCLL8LOzK9xa5sDMBJpUnEPoTpjaykGeG7WiNHw4KuzfNMBsUr0LulMEUVOJuXMI4 lAtya1fSDnau1RK/w1zrp/M8Y8p0ImdfMbrz7G5n3JGxhPnOPmdJYM16yt34DcH2AZFVzjbf2dCx 2j3rULmLKGeKZroJdOu4b9oUSidQghemaRmAQYDO6g== =tutt -----END PGP SIGNATURE----- --------------K0et2j3EZuDg5QB8H8WWtxpi-- From xen-devel-bounces@lists.xenproject.org Mon Apr 20 15:50:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 15:50:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286324.1567415 (Exim 4.92) (envelope-from ) id 1wEqtT-0004Fc-9A; Mon, 20 Apr 2026 15:50:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286324.1567415; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776700237-8A0C7161-5CB4D230/0/0 X-purgate-type: clean X-purgate-size: 550 On 20.04.2026 17:43, Oleksii Kurochko wrote: > The feature freeze date for Xen 4.22 is Fri May 08, 2026 > > Patches adding new features must be committed by this date. > > Straightforward bug fixes may continue to be accepted by maintainers > beyond this point. They could go without R-Acked. > > If you would like your features included in this release, please ensure > they are committed by the deadline. Among the large amount of stuff which is in flight, have we settled on a subset which we want to see make the release? Jan From xen-devel-bounces@lists.xenproject.org Mon Apr 20 16:00:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 16:00:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286332.1567424 (Exim 4.92) (envelope-from ) id 1wEr2t-0006Po-1g; Mon, 20 Apr 2026 16:00:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286332.1567424; Mon, 20 Apr 2026 16:00:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEr2s-0006Ph-Uw; Mon, 20 Apr 2026 16:00:22 +0000 Received: by outflank-mailman (input) for mailman id 1286332; Mon, 20 Apr 2026 16:00:21 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wEr2r-0006Pb-87 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:00:21 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEr2q-000jXH-6z for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 18:00:20 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e64d8f-2eae-0a2a0a5409dd-0a2a450281e0-22 for ; Mon, 20 Apr 2026 18:00:20 +0200 Received: from [209.85.167.46] (helo=mail-lf1-f46.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e64d93-af86-0a2a45020019-d155a72ed18d-3 for ; Mon, 20 Apr 2026 18:00:20 +0200 Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-5a283c44478so5611125e87.3 for ; Mon, 20 Apr 2026 09:00:20 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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They could go without R-Acked. >> >> If you would like your features included in this release, please ensure >> they are committed by the deadline. > > Among the large amount of stuff which is in flight, have we settled on a > subset which we want to see make the release? Not yet. I think we should either address this during the committers’ and maintainers’ call, or we can list the items here and discuss them. If anyone has items in mind that they would like included in the release, please add them here. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 20 16:14:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 16:14:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286347.1567435 (Exim 4.92) (envelope-from ) id 1wErGX-0000LH-T8; Mon, 20 Apr 2026 16:14:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286347.1567435; Mon, 20 Apr 2026 16:14:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wErGX-0000LA-QQ; Mon, 20 Apr 2026 16:14:29 +0000 Received: by outflank-mailman (input) for mailman id 1286347; Mon, 20 Apr 2026 16:14:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wErGW-0000L4-CS for xen-devel@lists.xenproject.org; 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Date: Mon, 20 Apr 2026 18:14:20 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Jan Beulich Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Teddy Astie , Marek Marczykowski Subject: Re: [PATCH] x86/cpuidle: split the max_cstate variable Message-ID: References: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> X-ClientProxiedBy: MA3P292CA0071.ESPP292.PROD.OUTLOOK.COM (2603:10a6:250:49::12) To CH7PR03MB7860.namprd03.prod.outlook.com (2603:10b6:610:24e::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH7PR03MB7860:EE_|CH0PR03MB6162:EE_ X-MS-Office365-Filtering-Correlation-Id: f7fe3565-2c10-444b-2a6f-08de9ef7e2c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: wIcq5DZuhd7qAbYYFX6eQQXiMS3rusp3uuqEaPrZf2KC3mSGwZwMXkR+noQ11cUViw9K5Oy5IediOtC4fKG9KFReII59LBrRg/JsKQhhKX2oBgD/XinQEnyEw0Mkuy4oSziOGa+UyRvPvTogB9T9GxFPo78AK2yYZnaeMaktxftejyDb39G5cGUc+1acNWfFNhDWMsrjwQKPXKd880jisWdlazC0A2Q6r9ABiF+BXl/BoAmrtcXZAYWIKAiyX7YsoZ8zcy0lSX8YnJHTlmxNm5OPwEAQI8HMKbHerXH2IQcFyI3IP1vVYU9PfLAjIT4g9Iei72/kJqysmlXbSRGAq8q9nrnjVLC4s2btQQH1rNP57mqfoo3L/YfOmlpNHW0Grfio3xdtDMreZeleYkoTrNCnAB+twK9ra6p2Upq9m0+5qjo3TV5sUj+n+JXGSypmdiFlUFZllXxgRxp2Ac9EEl9jtGMDtM8LkTrVtPbJvp2tAmtsagp3q2suzcY+9s7CzGgX1FxuCnEy4W5CzQ+ZSNoBQBSr/fuTDZ+KaEhSXkKCxRcqpVabtwgU6pxWALGLK5fpZtx3pZ1qIt/b8q7Os/KuK1jGHn39zw/DHfEcv/C1VgenK+7XwuNJszIDVWzNFa5HzSJsrcYQkNTc2dTOyWqxHKtvSJz98osyYSimRko0XSOLkigw194XmdY+0iJEzVbRfnUu0t29BiWXq20179GOBCoWpcEUpq80OPdzxDk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH7PR03MB7860.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(376014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; 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While decisions how > to set up the system are okay this way as long as we deem the command line > option a strict upper bound, what to do during S3 resume should not be > based on that potentially varying value. Decisions there need to use > solely the strict upper bound we may have enforced ourselves (or which was > forced onto us via command line option). > > Rather than altering pit_broadcast_is_available(), drop the function > altogether. It's pretty odd for acpi/cpu_idle.c to call into time.c, just > for that to call into acpi/cpu_idle.c again. > > Fixes: 8d24303023ec ("x86: don't write_tsc() non-zero values on CPUs updating only the lower 32 bits") > Signed-off-by: Jan Beulich > --- > cpuidle_disable_deep_cstate(), when called from handle_rtc_once(), is > still somewhat of a problem: Boot time and resume time runs of > _disable_pit_irq() may still behave differently because of that. > > If we wanted the sysctl to possibly move the maximum C-state beyond what > was given on the command line, things would get yet more complicated, as > we'd then need to re-configure the driver that's in use. > > I wonder how useful the ACPI_STATE_C #define-s really are. Plain 1 is > used in e.g. probe_c3_errata(), and the plain 7 doesn't even have a > respective constant (nor would that be suitable, as that's not really an > ACPI state). > > --- a/xen/arch/x86/acpi/cpu_idle.c > +++ b/xen/arch/x86/acpi/cpu_idle.c > @@ -119,7 +119,7 @@ bool lapic_timer_init(void) > lapic_timer_off = hpet_broadcast_enter; > lapic_timer_on = hpet_broadcast_exit; > } > - else if ( pit_broadcast_is_available() ) > + else if ( cpuidle_usable_deep_cstate() ) > { > lapic_timer_off = pit_broadcast_enter; > lapic_timer_on = pit_broadcast_exit; > @@ -131,12 +131,15 @@ bool lapic_timer_init(void) > } > > void (*__read_mostly pm_idle_save)(void); > -unsigned int max_cstate __read_mostly = UINT_MAX; > + > +unsigned int max_usable_cstate __read_mostly = UINT_MAX; > +unsigned int max_allowed_cstate __read_mostly = UINT_MAX; > unsigned int max_csubstate __read_mostly = UINT_MAX; > > static int __init cf_check parse_cstate(const char *s) > { > - max_cstate = simple_strtoul(s, &s, 0); > + max_allowed_cstate = simple_strtoul(s, &s, 0); > + max_usable_cstate = max_allowed_cstate; > if ( *s == ',' ) > max_csubstate = simple_strtoul(s + 1, NULL, 0); > return 0; > @@ -413,10 +416,11 @@ static void cf_check dump_cx(unsigned ch > unsigned int cpu; > > printk("'%c' pressed -> printing ACPI Cx structures\n", key); > - if ( max_cstate < UINT_MAX ) > + if ( max_cstate() < UINT_MAX ) > { > - printk("max state: C%u\n", max_cstate); > - if ( max_csubstate < UINT_MAX ) > + printk("max state: C%u\n", max_cstate()); > + if ( max_allowed_cstate <= max_usable_cstate && > + max_csubstate < UINT_MAX ) > printk("max sub-state: %u\n", max_csubstate); > else > printk("max sub-state: unlimited\n"); > @@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle > u32 exp = 0, pred = 0; > u32 irq_traced[4] = { 0 }; > > - if ( max_cstate > 0 && power && > + if ( max_cstate() > 0 && power && > (next_state = cpuidle_current_governor->select(power)) > 0 ) > { > unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 > - : max_cstate; > + : max_cstate(); > > do { > cx = &power->states[next_state]; > } while ( (cx->type > max_state || > cx->entry_method == ACPI_CSTATE_EM_NONE || > (cx->entry_method == ACPI_CSTATE_EM_FFH && > - cx->type == max_cstate && > + cx->type == max_allowed_cstate && I'm afraid I'm missing why this uses max_allowed_cstate instead of max_state. > (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) && > --next_state ); > if ( next_state ) > @@ -1448,7 +1452,7 @@ static void amd_cpuidle_init(struct acpi > > for ( i = 0; i < nr; ++i ) > { > - if ( cx[i].type > max_cstate ) > + if ( cx[i].type > max_cstate() ) > break; > power->states[i + 1] = cx[i]; > power->states[i + 1].idx = i + 1; > @@ -1611,21 +1615,22 @@ int pmstat_reset_cx_stat(unsigned int cp > > void cpuidle_disable_deep_cstate(void) > { > - if ( max_cstate > ACPI_STATE_C1 ) > + if ( max_usable_cstate > ACPI_STATE_C1 ) > { > if ( local_apic_timer_c2_ok ) > - max_cstate = ACPI_STATE_C2; > + max_usable_cstate = ACPI_STATE_C2; > else > - max_cstate = ACPI_STATE_C1; > + max_usable_cstate = ACPI_STATE_C1; > } > > hpet_disable_legacy_broadcast(); > } > > -bool cpuidle_using_deep_cstate(void) > +bool cpuidle_usable_deep_cstate(void) > { > - return xen_cpuidle && max_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2 > - : ACPI_STATE_C1); > + return xen_cpuidle && > + max_usable_cstate > (local_apic_timer_c2_ok ? ACPI_STATE_C2 > + : ACPI_STATE_C1); > } > > static int cf_check cpu_callback( > --- a/xen/arch/x86/cpu/intel.c > +++ b/xen/arch/x86/cpu/intel.c > @@ -384,12 +384,12 @@ static void probe_c3_errata(const struct > }; > > /* Serialized by the AP bringup code. */ > - if ( max_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && > + if ( max_usable_cstate > 1 && (c->apicid & (c->x86_num_siblings - 1)) && > x86_match_cpu(models) ) > { > printk(XENLOG_WARNING > "Disabling C-states C3 and C6 due to CPU errata\n"); > - max_cstate = 1; > + max_usable_cstate = 1; > } > } > > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -1045,15 +1045,16 @@ static void cf_check mwait_idle(void) > u64 before, after; > u32 exp = 0, pred = 0, irq_traced[4] = { 0 }; > > - if (max_cstate > 0 && power && > + if (max_cstate() > 0 && power && > (next_state = cpuidle_current_governor->select(power)) > 0) { > unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 > - : max_cstate; > + : max_cstate(); > > do { > cx = &power->states[next_state]; > - } while ((cx->type > max_state || (cx->type == max_cstate && > - MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > + } while ((cx->type > max_state || > + (cx->type == max_allowed_cstate && Indentation is weird for the above line IMO, you should use hard 3 tabs plus spaces afterwards, like the surrounding indentation? > + MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > --next_state); > if (!next_state) > cx = NULL; Seeing max_cstate() is used in multiple places here, you might want to introduce a local max_cstate variable? > @@ -1458,7 +1459,7 @@ static void __init sklh_idle_state_table > u64 msr; > > /* if PC10 disabled via cmdline max_cstate=7 or shallower */ > - if (max_cstate <= 7) > + if (max_cstate() <= 7) > return; > > /* if PC10 not present in CPUID.MWAIT.EDX */ > @@ -1623,7 +1624,7 @@ static int __init mwait_idle_probe(void) > !mwait_substates) > return -ENODEV; > > - if (!max_cstate || !opt_mwait_idle) { > + if (!max_cstate() || !opt_mwait_idle) { > pr_debug(PREFIX "disabled\n"); > return -EPERM; > } > @@ -1714,8 +1715,8 @@ static int cf_check mwait_idle_cpu_init( > hint = flg2MWAIT(cpuidle_state_table[cstate].flags); > state = MWAIT_HINT2CSTATE(hint) + 1; > > - if (state > max_cstate) { > - printk(PREFIX "max C-state %u reached\n", max_cstate); > + if (state > max_cstate()) { > + printk(PREFIX "max C-state %u reached\n", max_cstate()); > break; > } > > --- a/xen/arch/x86/include/asm/time.h > +++ b/xen/arch/x86/include/asm/time.h > @@ -31,7 +31,6 @@ int cpu_frequency_change(u64 freq); > > void cf_check pit_broadcast_enter(void); > void cf_check pit_broadcast_exit(void); > -int pit_broadcast_is_available(void); > > uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks); > > --- a/xen/arch/x86/time.c > +++ b/xen/arch/x86/time.c > @@ -517,7 +517,7 @@ static int64_t __init cf_check init_hpet > bool disable_hpet = false; > > if ( hpet_address && strcmp(opt_clocksource, pts->id) && > - cpuidle_using_deep_cstate() ) > + cpuidle_usable_deep_cstate() ) > { > if ( pci_conf_read16(PCI_SBDF(0, 0, 0x1f, 0), > PCI_VENDOR_ID) == PCI_VENDOR_ID_INTEL ) > @@ -2655,7 +2655,7 @@ static int _disable_pit_irq(bool init) > * XXX dom0 may rely on RTC interrupt delivery, so only enable > * hpet_broadcast if FSB mode available or if force_hpet_broadcast. > */ > - if ( cpuidle_using_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) > + if ( cpuidle_usable_deep_cstate() && !boot_cpu_has(X86_FEATURE_XEN_ARAT) ) > { > init ? hpet_broadcast_init() : hpet_broadcast_resume(); > if ( !hpet_broadcast_is_available() ) > @@ -2707,11 +2707,6 @@ void cf_check pit_broadcast_exit(void) > reprogram_timer(this_cpu(timer_deadline)); > } > > -int pit_broadcast_is_available(void) > -{ > - return cpuidle_using_deep_cstate(); > -} > - > void send_timer_event(struct vcpu *v) > { > send_guest_vcpu_virq(v, VIRQ_TIMER); > @@ -2999,7 +2994,7 @@ static void cf_check dump_softtsc(unsign > else if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC ) ) > { > printk("TSC has constant rate, "); > - if ( max_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 ) > + if ( max_usable_cstate <= ACPI_STATE_C2 && tsc_max_warp == 0 ) > printk("no deep Cstates, passed warp test, deemed reliable, "); > else > printk("deep Cstates possible, so not reliable, "); > --- a/xen/include/xen/acpi.h > +++ b/xen/include/xen/acpi.h > @@ -142,30 +142,33 @@ int acpi_gsi_to_irq (u32 gsi, unsigned i > > #ifdef CONFIG_ACPI_CSTATE > /* > - * max_cstate sets the highest legal C-state. > - * max_cstate = 0: C0 okay, but not C1 > - * max_cstate = 1: C1 okay, but not C2 > - * max_cstate = 2: C2 okay, but not C3 etc. > - > - * max_csubstate sets the highest legal C-state sub-state. Only applies to the > - * highest legal C-state. > - * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E > - * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 > - * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 > - * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 > + * max_{allowed,usable}_cstate sets the highest allowed / usable C-state, where > + * "allowed" is command line / sysctl based. Hm, this is a bit misleading, because max_usable_cstate is also command line based (plus system errata). What about: "max_{allowed,usable}_cstate sets the highest allowed / usable C-state. max_usable_cstate can only be set from the command line, while max_allowed_cstate can be set from both command line and systcl." > + * max_*_cstate = 0: C0 okay, but not C1 > + * max_*_cstate = 1: C1 okay, but not C2 > + * max_*_cstate = 2: C2 okay, but not C3 etc. > + * > + * max_csubstate sets the highest allowed C-state sub-state. Only applies to > + * the highest allowed C-state. > + * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E > + * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 > + * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 > + * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 > */ > > -extern unsigned int max_cstate; > +extern unsigned int max_usable_cstate; > +extern unsigned int max_allowed_cstate; > extern unsigned int max_csubstate; > > +#define max_cstate() min(max_usable_cstate, max_allowed_cstate) I would be tempted to drop the ending parenthesis so that you don't need to adjust callers, but that's likely misleading, as then it would need to be uppercase MAX_CSTATE. > + > static inline unsigned int acpi_get_cstate_limit(void) > { > - return max_cstate; > + return max_allowed_cstate; > } > static inline void acpi_set_cstate_limit(unsigned int new_limit) > { > - max_cstate = new_limit; > - return; > + max_allowed_cstate = new_limit; Do we want to check the new limit doesn't exceed max_usable_cstate and return -ERANGE or similar on failure? After this change it's a bit weird to silently ignore invalid values IMO. > } > > static inline unsigned int acpi_get_csubstate_limit(void) > --- a/xen/include/xen/cpuidle.h > +++ b/xen/include/xen/cpuidle.h > @@ -89,7 +89,7 @@ struct cpuidle_governor > extern int8_t xen_cpuidle; > extern struct cpuidle_governor *cpuidle_current_governor; > > -bool cpuidle_using_deep_cstate(void); > +bool cpuidle_usable_deep_cstate(void); > void cpuidle_disable_deep_cstate(void); > > #define CPUIDLE_DRIVER_STATE_START 1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 16:14:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 16:14:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286349.1567445 (Exim 4.92) (envelope-from ) id 1wErGf-0000ao-93; Mon, 20 Apr 2026 16:14:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286349.1567445; Mon, 20 Apr 2026 16:14:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wErGf-0000ah-5E; Mon, 20 Apr 2026 16:14:37 +0000 Received: by outflank-mailman (input) for mailman id 1286349; Mon, 20 Apr 2026 16:14:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wErGe-0000aO-Cs for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:14:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wErGd-00BZ3a-Ps for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 18:14:35 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e650d0-e002-0a2a0a5209dd-0a2a4508df38-40 for ; Mon, 20 Apr 2026 18:14:35 +0200 Received: from [209.85.218.42] (helo=mail-ej1-f42.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e650eb-63b5-0a2a45080019-d155da2acc72-3 for ; Mon, 20 Apr 2026 18:14:35 +0200 Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-ba25fd27571so465799566b.0 for ; Mon, 20 Apr 2026 09:14:35 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnmUOoFAwAAAAAACgkQsN6d1ii/Ey+a 8AgAmGVweEo5CX2qrgzz3d0brhOY7+O7I6TRGD8UAp+FFsXiTssBQpq1E62Us2T6zztX9vVLQmeA gS11fGFaQsT1XJ7mO1ZJje1VQRSAfH6nCOz6Cy4liWoxa6XMIxYLGq+mqqKBCluC+r2CKHamcW2r 9/7aBB6YIlCrVZ5xKJ4jSlH+lhx7vt/W0eq0rQahslfo938TYTwuKLrq6o0YAEEIw+Pe7s7uX3H7 1sE8gt72V2nmPyXiJoEEqNs1Pjg98HkXJ4cTmIpUWtAAmG+0dyGRJNX6RhoSzeUjEfRVcndWGmT1 KtHCQpLSLu9p5ZtQwZ4xIz1Ba4cX15usNM71/sLL3A== =u4ia -----END PGP SIGNATURE----- --------------aqGf4ELZISJyc8q7cPAa0xho-- From xen-devel-bounces@lists.xenproject.org Mon Apr 20 17:04:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 17:04:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286371.1567454 (Exim 4.92) (envelope-from ) id 1wEs2P-0007gd-OM; Mon, 20 Apr 2026 17:03:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286371.1567454; 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To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------k6tjV2iCtnYnEvXZeEhxMv7R" X-purgate-ID: tlsNG-d25034/1776704635-6F77ECF5-FFF41692/0/0 X-purgate-type: clean X-purgate-size: 18454 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------k6tjV2iCtnYnEvXZeEhxMv7R Content-Type: multipart/mixed; boundary="------------XzUtzQuDURgw8Shm50KGUc7R"; protected-headers="v1" Message-ID: <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> Date: Mon, 20 Apr 2026 13:03:45 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> --------------XzUtzQuDURgw8Shm50KGUc7R Content-Type: multipart/mixed; boundary="------------10JM7oBQQbSgbPWSKCMrkIaC" --------------10JM7oBQQbSgbPWSKCMrkIaC Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/20/26 04:49, Christian K=C3=B6nig wrote: > On 4/17/26 21:35, Demi Marie Obenour wrote: >> On 4/17/26 03:53, Christian K=C3=B6nig wrote: >>> On 4/16/26 18:13, Demi Marie Obenour wrote: >>>> On 4/16/26 05:57, Christian K=C3=B6nig wrote: > ... >>>> Unless I am >>>> mistaken, client workloads are highly non-uniform: a single game or >>>> compute job might well use more VRAM than every other program on the= >>>> system combined. >>> >>> Yeah, perfectly correct. >>> >>>> Are these workloads impossible to make work well with pinning? >>> >>> No, as long as you don't know the workload beforehand, e.g. when you = define the limit. >>> >>> I mean that's why basically everybody avoids pinning and assigning fi= xed amounts of resources. >>> >>> Even if you can make it work technically pinning usually results in a= rather bad end user experience. >>> >>> Regards, >>> Christian. >> >> Do drivers and programs assume that they can access VRAM from the CPU?= >=20 > Yes, and that is actually really important for performance. >=20 > That's why Alex and I came up with the idea of using the resize able BA= R feature to access all of VRAM on modern GPUs. >=20 > There are a couple of hacks which have been implemented over the years = for exotic platforms were MMIO/VRAM access was problematic. For example o= n a page fault you use a GPU DMA engine to copy the VRAM buffer into syst= em memory, make the CPU memory access and then copy it back again on dema= nd at the next command submission. >=20 > But all of those hacks are basically just prove of concepts and result = in completely unusable performance. I'm reminded of Asahi considering emulating unaligned accesses to PCI BARs in a fault handler. >> Are any of the following reasonable options? >> >> 1. Change the guest kernel to only map (and thus pin) a small subset >> of VRAM at any given time. If unmapped VRAM is accessed the guest >> traps the page fault, evicts an old VRAM mapping, and creates a >> new one. >=20 > Yeah, that could potentially work. >=20 > This is basically what we do on the host kernel driver when we can't re= size the BAR for some reason. In that use case VRAM buffers are shuffled = in and out of the CPU accessible window of VRAM on demand. How much is this going to hurt performance? =20 >> 2. Pretend that resizable BAR is not enabled, so the guest doesn't >> think it can map much of VRAM at once. If resizable BAR is enabled= >> on the host, it might be possible to split the large BAR mapping >> in a lot of ways. >=20 > That won't work. The userspace parts of the driver stack don't care how= large the BAR to access VRAM with the CPU is. >=20 > The expectation is that the kernel driver makes thing CPU accessible as= needed in the page fault handler. >=20 > It is still a good idea for your solution #1 to give the amount of "pin= -able" VRAM to the userspace stack as CPU visible VRAM limit so that test= cases and applications try to lower their usage of VRAM, e.g. use system= memory bounce buffers when possible. That makes sense. >> Or does Xen really need to allow the host to handle guest page faults?= >> That adds a huge amount of complexity to trusted and security-critical= >> parts of the system, so it really is a last resort. Putting the >> complexity in to the guest virtio-GPU driver is vastly preferable if >> it can be made to work well. >=20 > Well the nested page fault handling KVM offers has proven to be extreme= ly useful. So when XEN can't do this it is clearly lacking an important f= eature. I agree. However, it is a lot of work to implement, which is why I'm looking for alternatives if possible. KVM is part of the Linux kernel, so it can just call the Linux kernel functions used to handle userspace page faults. Xen is separate from Linux, so it can't do that. Instead, it will need to: 1. Determine that the fault needs to be handled by another VM, and the ID of the VM that needs to handle the fault. 2. Send a message to the VM asking it to handle the fault. 3. Block the vCPU until it gets a response. Then the VM owning the memory will need to call the page fault handler and provide the memory to Xen. Xen then needs to: 4. Map the memory into the nested page tables of the VM that faulted. 5. Resume the vCPU. > But I have one question: When XEN has a problem handling faults from th= e guest on the host then how does that work for system memory mappings? >=20 > There is really no difference between VRAM and system memory in the han= dling for the GPU driver stack. >=20 > Regards, > Christian. Generally, Xen makes the frontend (usually an unprivileged VM) responsible for providing mappings to the backend (usually the host). That is possible with system RAM but not with VRAM, because Xen has no awareness of VRAM. To Xen, VRAM is just a PCI BAR. KVM runs in the same kernel as the GPU driver. Xen doesn't, and that is the source of the extra complexity. --=20 Sincerely, Demi Marie Obenour (she/her/hers) --------------10JM7oBQQbSgbPWSKCMrkIaC Content-Type: application/pgp-keys; name="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Disposition: attachment; filename="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Description: OpenPGP public key Content-Transfer-Encoding: quoted-printable -----BEGIN PGP PUBLIC KEY BLOCK----- xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49y B+l2nipdaq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYf bWpr/si88QKgyGSVZ7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/ UorR+FaSuVwT7rqzGrTlscnTDlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7M MPCJwI8JpPlBedRpe9tfVyfu3euTPLPxwcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9H zx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR6h3nBc3eyuZ+q62HS1pJ5EvU T1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl5FMWo8TCniHynNXs BtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2Bkg1b//r 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[78.146.242.105]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fb7a0c13sm96463505e9.21.2026.04.20.10.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 10:46:07 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1776707168; x=1777311968; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=nQ1dtS+UVA2Zj6+lVhX2vjjkpgXkpEEgSIyaxC0p6Kw=; b=nn0C7kY6Z+YdJS3Zo7Z1bmD/LMbrbmEdSjQK6jYSHTih26fbtrt/hSlvComNGKjRHC ++nz2fkge93vpdrn5ZzZOFiUEPoZZlZCfpdQ3NgdUkx/pODAhazAoXQ2wKMHcFU3AW7T pzVQ8fHmQGJE2Z/EdyH3U9Ho7wmMWil5Su5Q4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776707168; x=1777311968; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=nQ1dtS+UVA2Zj6+lVhX2vjjkpgXkpEEgSIyaxC0p6Kw=; b=S+DieXm7aC19VK5KQxBzpNkeblyOKYIP2gwDCsF/r61DmjCZgA4R5n2TFLOkS7a7KE MR4i6wJDNhDRfbl/gb1Ne6sZZSJjXBhi8RPzLpIhBUrE8I185VoONty/Dl9caSVjajC6 jE8dx4IOg/bwi4ipJjL2RsfTiOLdmyJldupCLCt0hWXNn6rER1JIKa5LGQ7zKtIBXB75 1xXIYyWIFh2SuDsfb/35SDZomcNwTpL7B1ddWxwMY9VHkFsXPWOhe0FF2xhKv4KSknQP XAOGKRuf+rIqrJIbTK0TMIX56DAFSM1HwAnVe5y9DQOQo0QhKbXYFb32MenN0t4RrWN/ aD1A== X-Gm-Message-State: AOJu0YwxZq9VnRbYZAlpYAOmetI2zoYMjOsKIMQWsjn1iqbW0C4fnQbp q7T5bLJktPHdT+Pwfg51jNRVbGRdJNFQ/6W2HuLZ3qZmgPq2HwT2WnmMCsVXFIUHBGCtEuxVSc2 c2b18pL4Z9g== X-Gm-Gg: AeBDiesoSx6CWUcGE++IpQOz9M2G75uTumbIx85FFOi8EBnN2bpj60gwx+zt5ZayThB fQn1DXeJ0p8bAdNUoVMNAkvdOG7JZxmpfcJyXXkB1H+28EnnqAMT+vQUmtHeu0W/hKhMthNYUzZ YvaqpIL5QiNwoOvcgtTi0+3XsnhUN6a8yfN7kUxFZY/bECiME7VOR/0vXt7yCr1SnZvH8l6m1Ya PKyROhGzk46pJQnfHcCrBeI1VrgXnBkX/6Va2i6qH1MId76ycZn8DHmOK631C+YbcuNSSlFCjVA HdYbZDRn3A6zZVGjSrezpRhqAKb3X1uUmDxsfDram2BMGLIlTBFG68IOj/UdJtUhZAiLQPApJtI yHaFPPWtSgBIGV2aSDBjxqqM69yrs4veUdsg0A9U208n9KOnNee1n6JQcLTSGv5tmbYHk8wGrhC ubH1W2bFKLF1A2IsK4yEXFHN41DXGvFdBZI0O6dyhBcqmwsOVKWbenAQgTtvaEG34kaL4AqvA6l sKxIS/MRAon1jpwSwqekCaJHA== X-Received: by 2002:a05:600c:8909:b0:489:1b10:d896 with SMTP id 5b1f17b1804b1-4891b10dd45mr72830655e9.0.1776707167691; Mon, 20 Apr 2026 10:46:07 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH Xen 4.20] x86/apic: Fix asm() constraints in TMICT calculation Date: Mon, 20 Apr 2026 18:46:05 +0100 Message-Id: <20260420174605.706329-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776707168-B6862FF4-1804EAD3/0/0 X-purgate-type: clean X-purgate-size: 1925 The encoded MUL is 64 bits, so writes %rdx too. At a minimum, this needs expressing as a clobber. Also fix a logical disconnect between 'overflow' being the carry flag not the overflow flag. CF and OF are always the same for MUL instructions, so use the flag which matches the variable name. Fixes: d5c70a51bfbe ("x86/APIC: handle overflow in TMICT calculation") Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monné CC: Teddy Astie Only affects 4.20 (and earlier) where __builtin_umull_overflow() can't be used. I've kept this form because it produces best code generation for GCCs which support flag outputs. An alternative would be to capture product_hi and check the nonzero-ness, as that's how OF/CF are produced in hardware, which would be better code generation on very old GCCs. --- xen/arch/x86/apic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index daf597ed44b7..764ee1e98f77 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1317,9 +1317,10 @@ int reprogram_timer(s_time_t timeout) apic_tmict = UINT32_MAX; asm ( "mul %[expire]\n\t" - ASM_FLAG_OUT(, "setc %[cf]") - : "=a" (product), [cf] ASM_FLAG_OUT("=@ccc", "=qm") (overflow) - : "0" ((unsigned long)bus_scale), [expire] "r" (expire) ); + ASM_FLAG_OUT(, "seto %[of]") + : "=a" (product), [of] ASM_FLAG_OUT("=@cco", "=qm") (overflow) + : "0" ((unsigned long)bus_scale), [expire] "r" (expire) + : "rdx" ); if ( !overflow && (product >>= BUS_SCALE_SHIFT) < apic_tmict ) apic_tmict = product; base-commit: 5f7054258c6937b74aee411f16db5eb54ce9fda1 -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 17:59:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 17:59:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286406.1567471 (Exim 4.92) (envelope-from ) id 1wEstc-0006T8-P9; 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Change the guest kernel to only map (and thus pin) a small subset >>> of VRAM at any given time. If unmapped VRAM is accessed the guest >>> traps the page fault, evicts an old VRAM mapping, and creates a >>> new one. >> >> Yeah, that could potentially work. >> >> This is basically what we do on the host kernel driver when we can't resize the BAR for some reason. In that use case VRAM buffers are shuffled in and out of the CPU accessible window of VRAM on demand. > > How much is this going to hurt performance? Hard to say, resizing the BAR can easily give you 10-15% more performance on some use cases. But that involves physically transferring the data using a DMA. For this solution we basically only have to we basically only have to transfer a few messages between host and guest. No idea how performant that is. >>> 2. Pretend that resizable BAR is not enabled, so the guest doesn't >>> think it can map much of VRAM at once. If resizable BAR is enabled >>> on the host, it might be possible to split the large BAR mapping >>> in a lot of ways. >> >> That won't work. The userspace parts of the driver stack don't care how large the BAR to access VRAM with the CPU is. >> >> The expectation is that the kernel driver makes thing CPU accessible as needed in the page fault handler. >> >> It is still a good idea for your solution #1 to give the amount of "pin-able" VRAM to the userspace stack as CPU visible VRAM limit so that test cases and applications try to lower their usage of VRAM, e.g. use system memory bounce buffers when possible. > > That makes sense. > >>> Or does Xen really need to allow the host to handle guest page faults? >>> That adds a huge amount of complexity to trusted and security-critical >>> parts of the system, so it really is a last resort. Putting the >>> complexity in to the guest virtio-GPU driver is vastly preferable if >>> it can be made to work well. >> >> Well the nested page fault handling KVM offers has proven to be extremely useful. So when XEN can't do this it is clearly lacking an important feature. > > I agree. However, it is a lot of work to implement, which is why I'm > looking for alternatives if possible. > > KVM is part of the Linux kernel, so it can just call the Linux kernel > functions used to handle userspace page faults. Xen is separate from > Linux, so it can't do that. Instead, it will need to: > > 1. Determine that the fault needs to be handled by another VM, and > the ID of the VM that needs to handle the fault. > 2. Send a message to the VM asking it to handle the fault. > 3. Block the vCPU until it gets a response. > > Then the VM owning the memory will need to call the page fault handler > and provide the memory to Xen. Xen then needs to: > > 4. Map the memory into the nested page tables of the VM that faulted. > 5. Resume the vCPU. > >> But I have one question: When XEN has a problem handling faults from the guest on the host then how does that work for system memory mappings? >> >> There is really no difference between VRAM and system memory in the handling for the GPU driver stack. >> >> Regards, >> Christian. > > Generally, Xen makes the frontend (usually an unprivileged VM) > responsible for providing mappings to the backend (usually the host). > That is possible with system RAM but not with VRAM, because Xen has > no awareness of VRAM. To Xen, VRAM is just a PCI BAR. No, that doesn't work with system memory allocations of GPU drivers either. We already had it multiple times that people tried to be clever and incremented the page reference counter on driver allocated system memory and were totally surprised that this can result in security issues and data corruption. I seriously hope that this isn't the case here again. As far as I know XEN already has support for accessing VMAs with VM_PFN or otherwise I don't know how driver allocated system memory access could potentially work. Accessing VRAM is pretty much the same use case as far as I can see. Regards, Christian. > KVM runs in the same kernel as the GPU driver. Xen doesn't, and that > is the source of the extra complexity. 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To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------UO7W0PHisfTunOflIlWzKcyO" X-purgate-ID: tlsNG-bad1c0/1776710782-49AB6A53-59D2A063/0/0 X-purgate-type: clean X-purgate-size: 19031 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------UO7W0PHisfTunOflIlWzKcyO Content-Type: multipart/mixed; boundary="------------J0Ikx2XPeEGPGmR0bq5owBjA"; protected-headers="v1" Message-ID: <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> Date: Mon, 20 Apr 2026 14:46:15 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> --------------J0Ikx2XPeEGPGmR0bq5owBjA Content-Type: multipart/mixed; boundary="------------DQrFbbCzHC2DaqSP7y0lzlLn" --------------DQrFbbCzHC2DaqSP7y0lzlLn Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/20/26 13:58, Christian K=C3=B6nig wrote: > On 4/20/26 19:03, Demi Marie Obenour wrote: >> On 4/20/26 04:49, Christian K=C3=B6nig wrote: >>> On 4/17/26 21:35, Demi Marie Obenour wrote: > ... >>>> Are any of the following reasonable options? >>>> >>>> 1. Change the guest kernel to only map (and thus pin) a small subset= >>>> of VRAM at any given time. If unmapped VRAM is accessed the gues= t >>>> traps the page fault, evicts an old VRAM mapping, and creates a >>>> new one. >>> >>> Yeah, that could potentially work. >>> >>> This is basically what we do on the host kernel driver when we can't = resize the BAR for some reason. In that use case VRAM buffers are shuffle= d in and out of the CPU accessible window of VRAM on demand. >> >> How much is this going to hurt performance? >=20 > Hard to say, resizing the BAR can easily give you 10-15% more performan= ce on some use cases. >=20 > But that involves physically transferring the data using a DMA. For thi= s solution we basically only have to we basically only have to transfer a= few messages between host and guest. >=20 > No idea how performant that is. In this use-case, 20-30% performance penalties are likely to be "business as usual". Close to native performance would be ideal, but to be useful it just needs to beat software rendering by a wide margin, and not cause data corruption or vulnerabilities. >>>> 2. Pretend that resizable BAR is not enabled, so the guest doesn't >>>> think it can map much of VRAM at once. If resizable BAR is enabl= ed >>>> on the host, it might be possible to split the large BAR mapping >>>> in a lot of ways. >>> >>> That won't work. The userspace parts of the driver stack don't care h= ow large the BAR to access VRAM with the CPU is. >>> >>> The expectation is that the kernel driver makes thing CPU accessible = as needed in the page fault handler. >>> >>> It is still a good idea for your solution #1 to give the amount of "p= in-able" VRAM to the userspace stack as CPU visible VRAM limit so that te= st cases and applications try to lower their usage of VRAM, e.g. use syst= em memory bounce buffers when possible. >> >> That makes sense. >> >>>> Or does Xen really need to allow the host to handle guest page fault= s? >>>> That adds a huge amount of complexity to trusted and security-critic= al >>>> parts of the system, so it really is a last resort. Putting the >>>> complexity in to the guest virtio-GPU driver is vastly preferable if= >>>> it can be made to work well. >>> >>> Well the nested page fault handling KVM offers has proven to be extre= mely useful. So when XEN can't do this it is clearly lacking an important= feature. >> >> I agree. However, it is a lot of work to implement, which is why I'm >> looking for alternatives if possible. >> >> KVM is part of the Linux kernel, so it can just call the Linux kernel >> functions used to handle userspace page faults. Xen is separate from >> Linux, so it can't do that. Instead, it will need to: >> >> 1. Determine that the fault needs to be handled by another VM, and >> the ID of the VM that needs to handle the fault. >> 2. Send a message to the VM asking it to handle the fault. >> 3. Block the vCPU until it gets a response. >> >> Then the VM owning the memory will need to call the page fault handler= >> and provide the memory to Xen. Xen then needs to: >> >> 4. Map the memory into the nested page tables of the VM that faulted. >> 5. Resume the vCPU. >> >>> But I have one question: When XEN has a problem handling faults from = the guest on the host then how does that work for system memory mappings?= >>> >>> There is really no difference between VRAM and system memory in the h= andling for the GPU driver stack. >>> >>> Regards, >>> Christian. >> >> Generally, Xen makes the frontend (usually an unprivileged VM) >> responsible for providing mappings to the backend (usually the host). >> That is possible with system RAM but not with VRAM, because Xen has >> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. >=20 > No, that doesn't work with system memory allocations of GPU drivers eit= her. >=20 > We already had it multiple times that people tried to be clever and inc= remented the page reference counter on driver allocated system memory and= were totally surprised that this can result in security issues and data = corruption. >=20 > I seriously hope that this isn't the case here again. As far as I know = XEN already has support for accessing VMAs with VM_PFN or otherwise I don= 't know how driver allocated system memory access could potentially work.= >=20 > Accessing VRAM is pretty much the same use case as far as I can see. >=20 > Regards, > Christian. The Xen-native approach would be for system memory allocations to be made using the Xen driver and then imported into the virtio-GPU driver via dmabuf. Is there any chance this could be made to happen? If it's a lost cause, then how much is the memory overhead of pinning everything ever used in a dmabuf? It should be possible to account pinned host memory against a guest's quota, but if that leads to an unusable system it isn't going to be good. Is supporting page faults in Xen the only solution that will be viable long-term, considering the tolerance for very substantial performance overheads compared to native? AAA gaming isn't the initial goal here. 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SIGNATURE----- iQIzBAEBCgAdFiEEopQtqVJW1aeuo9/sszaHOrMp8lMFAmnmdHcACgkQszaHOrMp 8lMvCBAAiEpdcmZepZcksF1OYgnp7QuUn/aJGxwxt9Ioti8YOzvBGPNUuAGiqSj6 tylnRMxnDo74nCvIGjRRAX8oQ6JVAMHuf+GguCWqsb5alDnP3G3GpSTSeaUg+cc9 OFK7KEzuOHHz1Nawu315h8otumTxQKwR0TiwO2tqb8jYYWxgVuU/zExXF70uU1ju OP1TUbVWegATUpRJuX05pQoGcy6Go/4zfFGj/ipLug0IRW0X3scAFjOpeTYGPlcW 8doVY/lLQQ3ORE2D3XVW638W7YMQsD3ahOh2rPu9/Jj8FOYcWQXNy1KfEW5l1AYF tuDU9UraCuZCat5Q+Pv1l7fLCQrwqyOqHsq9gIKo/G84RGeixO9QAHQojRpr7C+n lq/pL7psahiVHfH3N7auAd8a0OBqYbdjmxlOPBJWlOiWPlcWtcUH4S3z8JoMBM7t AQR6QQfuzSF4fK6XyW/F9nm4Fd50Pnt2odQt/jDEhEyxLys76PkXNQUuA0Jr6rCT +KsqEr3lFaNX2QWPKdY5p0cyTjdQspMrrhnHCOLygt1xdmqXqH6+P72qW0wIZkFw 98K7aolksqQ0Rzh2TclUJyFTrUSYdNKlmebZZ5e9TvUO72JturfYKlbRnxgSm5Mk rV44denq+79l0+sOY8PjqCLS/Fnsmr5qeD/nydHS+esGhReGKwM= =0mmn -----END PGP SIGNATURE----- --------------UO7W0PHisfTunOflIlWzKcyO-- From xen-devel-bounces@lists.xenproject.org Mon Apr 20 18:53:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 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To: Demi Marie Obenour , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BL1PR13CA0382.namprd13.prod.outlook.com (2603:10b6:208:2c0::27) To SJ0PR12MB5673.namprd12.prod.outlook.com (2603:10b6:a03:42b::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ0PR12MB5673:EE_|MW4PR12MB6777:EE_ X-MS-Office365-Filtering-Correlation-Id: 922fa92f-3899-47ed-2dd5-08de9f0e231d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|56012099003|18096099003|22082099003|18002099003; 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Change the guest kernel to only map (and thus pin) a small subset >>>>> of VRAM at any given time. If unmapped VRAM is accessed the guest >>>>> traps the page fault, evicts an old VRAM mapping, and creates a >>>>> new one. >>>> >>>> Yeah, that could potentially work. >>>> >>>> This is basically what we do on the host kernel driver when we can't resize the BAR for some reason. In that use case VRAM buffers are shuffled in and out of the CPU accessible window of VRAM on demand. >>> >>> How much is this going to hurt performance? >> >> Hard to say, resizing the BAR can easily give you 10-15% more performance on some use cases. >> >> But that involves physically transferring the data using a DMA. For this solution we basically only have to we basically only have to transfer a few messages between host and guest. >> >> No idea how performant that is. > > In this use-case, 20-30% performance penalties are likely to be > "business as usual". Well that is quite a bit. > Close to native performance would be ideal, but > to be useful it just needs to beat software rendering by a wide margin, > and not cause data corruption or vulnerabilities. That should still easily be the case, even trivial use cases are multiple magnitudes faster on GPUs compared to software rendering. >>> >>>> But I have one question: When XEN has a problem handling faults from the guest on the host then how does that work for system memory mappings? >>>> >>>> There is really no difference between VRAM and system memory in the handling for the GPU driver stack. >>>> >>>> Regards, >>>> Christian. >>> >>> Generally, Xen makes the frontend (usually an unprivileged VM) >>> responsible for providing mappings to the backend (usually the host). >>> That is possible with system RAM but not with VRAM, because Xen has >>> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. >> >> No, that doesn't work with system memory allocations of GPU drivers either. >> >> We already had it multiple times that people tried to be clever and incremented the page reference counter on driver allocated system memory and were totally surprised that this can result in security issues and data corruption. >> >> I seriously hope that this isn't the case here again. As far as I know XEN already has support for accessing VMAs with VM_PFN or otherwise I don't know how driver allocated system memory access could potentially work. >> >> Accessing VRAM is pretty much the same use case as far as I can see. >> >> Regards, >> Christian. > > The Xen-native approach would be for system memory allocations to > be made using the Xen driver and then imported into the virtio-GPU > driver via dmabuf. Is there any chance this could be made to happen? That could be. Adding Pierre-Eric to comment since he knows that use much better than I do. > If it's a lost cause, then how much is the memory overhead of pinning > everything ever used in a dmabuf? It should be possible to account > pinned host memory against a guest's quota, but if that leads to an > unusable system it isn't going to be good. That won't work at all. We have use cases where you *must* migrate a DMA-buf to VRAM or otherwise the GPU can't use it. A simple scanout to a monitor is such an use case for example, that is usually not possible from system memory. > Is supporting page faults in Xen the only solution that will be viable > long-term, considering the tolerance for very substantial performance > overheads compared to native? AAA gaming isn't the initial goal here. > Qubes OS already supports PCI passthrough for that. We have AAA gaming working on XEN through native context working for quite a while. Pierre-Eric can tell you more about that. Regards, Christian. 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To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------oLcefsVzkSfrb6uaB7hzzgLl" X-purgate-ID: tlsNG-42698a/1776712353-0415DF3B-5760599E/0/0 X-purgate-type: clean X-purgate-size: 18599 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------oLcefsVzkSfrb6uaB7hzzgLl Content-Type: multipart/mixed; boundary="------------h9T0I0ygGOGJXLDPzJnCSWj0"; protected-headers="v1" Message-ID: <686713fc-c762-4b1b-88b2-d486d4f38ac6@gmail.com> Date: Mon, 20 Apr 2026 15:12:25 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Val Packett , Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: --------------h9T0I0ygGOGJXLDPzJnCSWj0 Content-Type: multipart/mixed; boundary="------------tPVaFr0yvTUet01h9p9LgABE" --------------tPVaFr0yvTUet01h9p9LgABE Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/20/26 14:53, Christian K=C3=B6nig wrote: > On 4/20/26 20:46, Demi Marie Obenour wrote: >> On 4/20/26 13:58, Christian K=C3=B6nig wrote: >>> On 4/20/26 19:03, Demi Marie Obenour wrote: >>>> On 4/20/26 04:49, Christian K=C3=B6nig wrote: >>>>> On 4/17/26 21:35, Demi Marie Obenour wrote: >>> ... >>>>>> Are any of the following reasonable options? >>>>>> >>>>>> 1. Change the guest kernel to only map (and thus pin) a small subs= et >>>>>> of VRAM at any given time. If unmapped VRAM is accessed the gu= est >>>>>> traps the page fault, evicts an old VRAM mapping, and creates a= >>>>>> new one. >>>>> >>>>> Yeah, that could potentially work. >>>>> >>>>> This is basically what we do on the host kernel driver when we can'= t resize the BAR for some reason. In that use case VRAM buffers are shuff= led in and out of the CPU accessible window of VRAM on demand. >>>> >>>> How much is this going to hurt performance? >>> >>> Hard to say, resizing the BAR can easily give you 10-15% more perform= ance on some use cases. >>> >>> But that involves physically transferring the data using a DMA. For t= his solution we basically only have to we basically only have to transfer= a few messages between host and guest. >>> >>> No idea how performant that is. >> >> In this use-case, 20-30% performance penalties are likely to be >> "business as usual". >=20 > Well that is quite a bit. >=20 >> Close to native performance would be ideal, but >> to be useful it just needs to beat software rendering by a wide margin= , >> and not cause data corruption or vulnerabilities. >=20 > That should still easily be the case, even trivial use cases are multip= le magnitudes faster on GPUs compared to software rendering. Makes sense. If only GPUs supported easy and flexible virtualization the= way CPUs do :(. >>>> >>>>> But I have one question: When XEN has a problem handling faults fro= m the guest on the host then how does that work for system memory mapping= s? >>>>> >>>>> There is really no difference between VRAM and system memory in the= handling for the GPU driver stack. >>>>> >>>>> Regards, >>>>> Christian. >>>> >>>> Generally, Xen makes the frontend (usually an unprivileged VM) >>>> responsible for providing mappings to the backend (usually the host)= =2E >>>> That is possible with system RAM but not with VRAM, because Xen has >>>> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. >>> >>> No, that doesn't work with system memory allocations of GPU drivers e= ither. >>> >>> We already had it multiple times that people tried to be clever and i= ncremented the page reference counter on driver allocated system memory a= nd were totally surprised that this can result in security issues and dat= a corruption. >>> >>> I seriously hope that this isn't the case here again. As far as I kno= w XEN already has support for accessing VMAs with VM_PFN or otherwise I d= on't know how driver allocated system memory access could potentially wor= k. >>> >>> Accessing VRAM is pretty much the same use case as far as I can see. >>> >>> Regards, >>> Christian. >> >> The Xen-native approach would be for system memory allocations to >> be made using the Xen driver and then imported into the virtio-GPU >> driver via dmabuf. Is there any chance this could be made to happen? >=20 > That could be. Adding Pierre-Eric to comment since he knows that use mu= ch better than I do. >=20 >> If it's a lost cause, then how much is the memory overhead of pinning >> everything ever used in a dmabuf? It should be possible to account >> pinned host memory against a guest's quota, but if that leads to an >> unusable system it isn't going to be good. >=20 > That won't work at all. >=20 > We have use cases where you *must* migrate a DMA-buf to VRAM or otherwi= se the GPU can't use it. >=20 > A simple scanout to a monitor is such an use case for example, that is = usually not possible from system memory. Direct scanout isn't a concern here. >> Is supporting page faults in Xen the only solution that will be viable= >> long-term, considering the tolerance for very substantial performance >> overheads compared to native? AAA gaming isn't the initial goal here.= >> Qubes OS already supports PCI passthrough for that. >=20 > We have AAA gaming working on XEN through native context working for qu= ite a while. >=20 > Pierre-Eric can tell you more about that. >=20 > Regards, > Christian. I've heard of that, but last I checked it required downstream patches to Xen, Linux, and QEMU. I don't know if any of those have been upstreamed since, but I believe that upstreaming the Xen and Linux patches (or rewriting them and upstreaming the rewritten version) would be necessary. Qubes OS (which I don't work for anymore but still want to help with this) almost certainly won't be using QEMU for GPU stuff. --=20 Sincerely, Demi Marie Obenour (she/her/hers) --------------tPVaFr0yvTUet01h9p9LgABE Content-Type: application/pgp-keys; name="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Disposition: attachment; filename="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Description: OpenPGP public key Content-Transfer-Encoding: quoted-printable -----BEGIN PGP PUBLIC KEY BLOCK----- xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49y B+l2nipdaq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYf bWpr/si88QKgyGSVZ7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/ UorR+FaSuVwT7rqzGrTlscnTDlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7M MPCJwI8JpPlBedRpe9tfVyfu3euTPLPxwcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9H zx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR6h3nBc3eyuZ+q62HS1pJ5EvU T1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl5FMWo8TCniHynNXs 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Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEopQtqVJW1aeuo9/sszaHOrMp8lMFAmnmepoACgkQszaHOrMp 8lOe5w/+KjpGlyI9G3fHlW7AUGjL8ojXIHalSkjbdJ1ErYaySIUYiJ7iBnotUcW+ nOdIAZv6EoqBQrrieYY88OhX2t5Aqu8b00Fviwb/nWFklsbEMRTIahvWNJJokeV/ poveO3O2A7dnwtoyZiLXXpDzQ2aPBX9GFOcamqnO2chA3AjftpJtjrfZJYPmJImE 8/SVjJAKuCTM0/Mh9cxBgwYrjVvXs0rfWG1ZzOD1FAVWd/tlDnMwmvC9/EFSCXh2 AXCjM+YJEscggLsV2mXlZ3oLaUShUqkmLCMNSvdEzCDPFdYU7O3d5axcuP19g6VD BirBlfddKETzxiuxv15v5jxC7vuVSlMRBDdFkA8s8/GAvQ2ZPo+3FHOVlCZ+rKUR bHLLaxGmXTGG7JGQe33SgaHA11yP2aHkEhMVyqQ0CmbhgE/In1XDh1D27TcsB+Zs fsEU2dmdafcHRkbTY8LHBLyYjvFt4Q87ml0C5JIzJmZitDo0CoeR5I9mQjjRqzgV fpappRRkPuGZN33R2pD51ZmbfXHeefWxtaEBb+M7lvXEje2I0huUxUn7L2huDWjQ KEnHt4qqS1kRzqhSgQJC56a5MjtjnS0cOVYgzvQtxLUFMh1IAwtefJ2h9LuQKbWl F+tpIy9kl2RI4YA4oJ+MUZDdsrNiyLM+M6FD3XeHpRn6HTO/FQI= =Uhuz -----END PGP SIGNATURE----- --------------oLcefsVzkSfrb6uaB7hzzgLl-- From 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eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=PJC6vAx39QYhhYufZEnwEGLPQM6gOCrIWNOV40YBgzgMKXw1ddLQv7aEQcW4Br8sfz1QckVvYSqBT3BbimUkqExezwv7bX14ArzGrsqSzX+CoJpzXkPgUaRHWKLw2YGj+lC/mZtYBkRwezUkaBlyCrSVdoIO5pkVDSvkRFDAEcCQwfWdePjGKfbx907cDTrT6zzhc3KClP6QIwudqs5rLF5+kdfrR+UDmwV7s1AwBdUVAm0sP3CRoOdyh9w9Tcik5i2pmr41aPooN7/HL1uDJ52ABCrMCY4IDtyBMDULt/Vd+1QxNTvCRmGjLOqr/LoKmRKzjEEBlbJvvgDUEQn8bA==; s=purelymail1; d=purelymail.com; v=1; bh=BL+nVHDN3Ay2hLoHiDXEh2wB+DvkjUQnXBWbZIQGO7E=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [RFC PATCH v6 14/43] altp2m: Move altp2m_{init,teardown} to common code Date: Mon, 20 Apr 2026 15:50:13 -0400 Message-Id: <20260420195042.207624-15-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c1860d/1776714657-C3D7BDB1-695BFE6A/0/0 X-purgate-type: clean X-purgate-size: 6140 From: Rose Spangler This commit moves the init and teardown routines into common code. The functions are gated by CONFIG_X86, so there is effectively no difference despite common code normally being compiled for ARM. This commit contains only renames/code movement, and no functional change i= s intended. This is commit 3/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 8 ----- xen/arch/x86/mm/altp2m.c | 45 ---------------------------- xen/arch/x86/mm/p2m-basic.c | 1 + xen/common/altp2m.c | 49 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 13 ++++++++ 5 files changed, 63 insertions(+), 53 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 7cff40beb7c6..13017525a62f 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -97,12 +97,6 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, uns= igned int idx) return true; } =20 -/* Initialize altp2m views */ -int altp2m_init(struct domain *d); - -/* Free altp2m views */ -void altp2m_teardown(struct domain *d); - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); =20 @@ -184,8 +178,6 @@ static inline int _altp2m_get_effective_entry(struct p2= m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) =20 /* Only declaration is needed. DCE will optimise it out when linking. */ -int altp2m_init(struct domain *d); -void altp2m_teardown(struct domain *d); struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 371bf3f0b8d4..46374373848d 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -123,51 +123,6 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } =20 -int altp2m_init(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); - - altp2m_lock_init(d); - d->altp2m_p2m =3D xvzalloc_array(struct p2m_domain *, d->nr_altp2m); - - if ( !d->altp2m_p2m ) - return -ENOMEM; - - for ( i =3D 0; i < d->nr_altp2m; i++ ) - { - d->altp2m_p2m[i] =3D p2m =3D p2m_init_one(d); - if ( p2m =3D=3D NULL ) - { - altp2m_teardown(d); - return -ENOMEM; - } - p2m->p2m_class =3D p2m_alternate; - p2m->access_required =3D hostp2m->access_required; - _atomic_set(&p2m->active_vcpus, 0); - } - - return 0; -} - -void altp2m_teardown(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - - for ( i =3D 0; i < d->nr_altp2m; i++ ) - { - if ( !d->altp2m_p2m[i] ) - continue; - p2m =3D d->altp2m_p2m[i]; - d->altp2m_p2m[i] =3D NULL; - p2m_free_one(p2m); - } - - XVFREE(d->altp2m_p2m); -} - int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *= mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index 433e7d08b78f..67cef5d2b6ef 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ =20 +#include #include #include #include diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 3a3283f0860a..cda653b713f0 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -2,8 +2,10 @@ #include #include #include +#include =20 #include +#include =20 #include =20 @@ -13,6 +15,53 @@ #include #endif =20 +#if CONFIG_X86 +int altp2m_init(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); + + altp2m_lock_init(d); + d->altp2m_p2m =3D xvzalloc_array(struct p2m_domain *, d->nr_altp2m); + + if ( !d->altp2m_p2m ) + return -ENOMEM; + + for ( i =3D 0; i < d->nr_altp2m; i++ ) + { + d->altp2m_p2m[i] =3D p2m =3D p2m_init_one(d); + if ( p2m =3D=3D NULL ) + { + altp2m_teardown(d); + return -ENOMEM; + } + p2m->p2m_class =3D p2m_alternate; + p2m->access_required =3D hostp2m->access_required; + _atomic_set(&p2m->active_vcpus, 0); + } + + return 0; +} + +void altp2m_teardown(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + + for ( i =3D 0; i < d->nr_altp2m; i++ ) + { + if ( !d->altp2m_p2m[i] ) + continue; + p2m =3D d->altp2m_p2m[i]; + d->altp2m_p2m[i] =3D NULL; + p2m_free_one(p2m); + } + + XVFREE(d->altp2m_p2m); +} +#endif /* CONFIG_X86 */ + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index be627152668a..85ef22c2b29e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,19 @@ =20 #include =20 +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +#ifdef CONFIG_X86 +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); + +/* Free altp2m views */ +void altp2m_teardown(struct domain *d); +#endif + #ifdef CONFIG_ALTP2M =20 /* Alternate p2m HVM on/off per domain */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286484.1567616 (Exim 4.92) (envelope-from ) id 1wEvBO-0003uH-0f; Mon, 20 Apr 2026 20:25:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286484.1567616; Mon, 20 Apr 2026 20:25:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBN-0003nl-Ep; Mon, 20 Apr 2026 20:25:25 +0000 Received: by outflank-mailman (input) for mailman id 1286484; Mon, 20 Apr 2026 19:50:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue2-0006Iu-5y for xen-devel@lists.xenproject.org; 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dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=nh/3b739kWlXbEwQ2vP9czBWHaEbT/ciL86qmTDx6PuvJ+UpniIuY8UJrFKr2PwwUhUiPGSSEczTs41M23Zlfs4niXXVQbror/q+RTI2hk/T2WOqGQmNYOyRzx460DUaErPhDvSeTwD43H62YE9iDKbdPE1iQ1eUGlPgne5bznGbcaUlOw0kezmUZ0odpV5RwLDCTktOx7pXJUacyjq1o5Tj4ssUrap4R9ALb/QUn4U0S4XcU/+xtwc+wsI4Fig2YZN930DTmWfr7zNNe4AyZkexb0DW7KjSjoFoLmR5APvSldDgzZVH6FMzHiuP559t41sK5tUViqDbh7Am/1EkaQ==; s=purelymail1; d=purelymail.com; v=1; bh=2CcuIQJepfXS1zs62wK057xIURAv8ZCI9/irpntDfIw=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 13/43] x86/altp2m: Add lock functions accessible from common code Date: Mon, 20 Apr 2026 15:50:12 -0400 Message-Id: <20260420195042.207624-14-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-ebf023/1776714657-2A7613FF-26D3FBF8/0/0 X-purgate-type: clean X-purgate-size: 6637 From: Rose Spangler This commit adds three altp2m_lock functions which wrap the corresponding altp2m_list_lock functions present in "mm-locks.h". The "mm-locks.h" file is only accessible in x86 code. In order to make altp2m common across architectures, it must be possible to acquire the altp2m lock without including an x86-specific header file. These functions cannot be static inline like their "mm-locks.h" counterparts, since "mm-locks.h" is only included in source files, not header files. Therefore, these functions might introduce a slight function call overhead over their "mm-locks.h" counterparts. However, the altp2m lock is mostly used in init/teardown routines and HVMOP implementations. For these cases, the altp2m_list_lock functions have been switched out for the altp2m_lock functions so they can be later migrated to common code. The only other function using the altp2m lock is altp2m_get_or_propagate, which is in the hot path of the page fault handler, so the altp2m_list_lock calls have not been replaced for that function. This is commit 2/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This seems like the solution which makes the most sense here, but it would be nicer if it could be static inline. I'm also not sure if the "mm-locks.h" functions are really supposed to be exposed outside of their translation unit like this, so feedback on this is appreciated. --- xen/arch/x86/include/asm/altp2m.h | 4 +++ xen/arch/x86/mm/altp2m.c | 42 ++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 9c58a396448d..7cff40beb7c6 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -156,6 +156,10 @@ int p2m_set_suppress_ve_multi(struct domain *d, int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, unsigned int altp2m_idx); =20 +void altp2m_lock_init(struct domain *d); +void altp2m_lock(struct domain *d); +void altp2m_unlock(struct domain *d); + #else =20 static inline bool altp2m_is_eptp_valid(const struct domain *d, diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 2dc84b76b8c1..371bf3f0b8d4 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -129,7 +129,7 @@ int altp2m_init(struct domain *d) struct p2m_domain *p2m; struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); =20 - mm_lock_init(&d->arch.altp2m_list_lock); + altp2m_lock_init(d); d->altp2m_p2m =3D xvzalloc_array(struct p2m_domain *, d->nr_altp2m); =20 if ( !d->altp2m_p2m ) @@ -221,7 +221,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned = int idx) if ( idx >=3D d->nr_altp2m ) return rc; =20 - altp2m_list_lock(d); + altp2m_lock(d); =20 if ( d->arch.altp2m_eptp[idx] !=3D mfn_x(INVALID_MFN) ) { @@ -230,7 +230,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned = int idx) rc =3D 1; } =20 - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } =20 @@ -348,7 +348,7 @@ void altp2m_flush(struct domain *d) { unsigned int i; =20 - altp2m_list_lock(d); + altp2m_lock(d); =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { @@ -357,7 +357,7 @@ void altp2m_flush(struct domain *d) d->arch.altp2m_visible_eptp[i] =3D mfn_x(INVALID_MFN); } =20 - altp2m_list_unlock(d); + altp2m_unlock(d); } =20 static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, @@ -409,13 +409,13 @@ int altp2m_init_by_id(struct domain *d, unsigned int = idx) if ( idx >=3D d->nr_altp2m ) return rc; =20 - altp2m_list_lock(d); + altp2m_lock(d); =20 if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] =3D=3D mfn_x(INVALID_MFN) ) rc =3D altp2m_activate_altp2m(d, idx, hostp2m->default_access); =20 - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } =20 @@ -431,7 +431,7 @@ int altp2m_init_next_available(struct domain *d, uint16= _t *idx, !xenmem_access_to_p2m_access(hostp2m, hvmmem_default_access, &a) = ) return rc; =20 - altp2m_list_lock(d); + altp2m_lock(d); =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { @@ -446,7 +446,7 @@ int altp2m_init_next_available(struct domain *d, uint16= _t *idx, break; } =20 - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } =20 @@ -463,7 +463,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int= idx) return rc; =20 rc =3D -EBUSY; - altp2m_list_lock(d); + altp2m_lock(d); =20 if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] !=3D mfn_x(INVALID_MFN) ) @@ -481,7 +481,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int= idx) } } =20 - altp2m_list_unlock(d); + altp2m_unlock(d); =20 domain_unpause_except_self(d); =20 @@ -501,7 +501,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d,= unsigned int idx) return rc; =20 rc =3D -EINVAL; - altp2m_list_lock(d); + altp2m_lock(d); =20 if ( d->arch.altp2m_visible_eptp[idx] !=3D mfn_x(INVALID_MFN) ) { @@ -512,7 +512,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d,= unsigned int idx) rc =3D 0; } =20 - altp2m_list_unlock(d); + altp2m_unlock(d); =20 domain_unpause_except_self(d); =20 @@ -773,7 +773,7 @@ int altp2m_set_view_visibility(struct domain *d, unsign= ed int altp2m_idx, { int rc =3D 0; =20 - altp2m_list_lock(d); + altp2m_lock(d); =20 if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) rc =3D -EINVAL; @@ -784,11 +784,23 @@ int altp2m_set_view_visibility(struct domain *d, unsi= gned int altp2m_idx, d->arch.altp2m_visible_eptp[array_index_nospec(altp2m_idx, MAX_EPT= P)] =3D mfn_x(INVALID_MFN); =20 - altp2m_list_unlock(d); + altp2m_unlock(d); =20 return rc; } =20 +void altp2m_lock_init(struct domain *d) { + mm_lock_init(&d->arch.altp2m_list_lock); +} + +void altp2m_lock(struct domain *d) { + altp2m_list_lock(d); +} + +void altp2m_unlock(struct domain *d) { + altp2m_list_unlock(d); +} + /* * Local variables: * mode: C --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286481.1567589 (Exim 4.92) (envelope-from ) id 1wEvBM-0003DE-0J; Mon, 20 Apr 2026 20:25:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286481.1567589; Mon, 20 Apr 2026 20:25:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBL-000395-Iv; Mon, 20 Apr 2026 20:25:23 +0000 Received: by outflank-mailman (input) for mailman id 1286481; Mon, 20 Apr 2026 19:50:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue2-0006Io-1u for xen-devel@lists.xenproject.org; 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charset=UTF-8 X-purgate-ID: tlsNG-d25034/1776714657-6D161CF5-C07D9204/0/0 X-purgate-type: clean X-purgate-size: 4553 From: Rose Spangler This commit makes the minimum required changes necessary for do_altp2m_op to compile on ARM. All altp2m commands in the switch statement are gated by CONFIG_X86, with a default case of returning EOPNOTSUPP. This allows future commits to move the #ifdef CONFIG_X86 down as support for ARM is added. Additionally, a call to do_altp2m_op is added in the ARM HVMOP code. This is commit 2/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: Replaced patches 2 and 3 from v4/v5 patch set with this patch. Made HVM_PARAM_ALTP2M read-only, following the change to the x86 implementation in commit 0291089f6ea8. The DOMCTL to enable altp2m on ARM is implemented in a later commit in this patch series. --- xen/arch/arm/hvm.c | 9 +++++++++ xen/common/altp2m.c | 29 ++++++++++++++--------------- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/hvm.c b/xen/arch/arm/hvm.c index 86e49bf47403..7c778795a280 100644 --- a/xen/arch/arm/hvm.c +++ b/xen/arch/arm/hvm.c @@ -5,6 +5,7 @@ * Arch-specific hardware virtual machine abstractions. */ =20 +#include #include #include #include @@ -23,6 +24,10 @@ static int hvm_allow_set_param(const struct domain *d, u= nsigned int param) { switch ( param ) { + /* The following parameters are read-only. */ + case HVM_PARAM_ALTP2M: + return -EEXIST; + /* * The following parameters are intended for toolstack usage only. * They may not be set by the domain. @@ -123,6 +128,10 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARA= M(void) arg) rc =3D -EINVAL; break; =20 + case HVMOP_altp2m: + rc =3D do_altp2m_op(arg); + break; + default: { gdprintk(XENLOG_DEBUG, "HVMOP op=3D%lu: not implemented\n", op); diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a43b3a3e34b3..6481fae1ed12 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -9,8 +9,10 @@ =20 #include =20 -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) && defined(CONFIG_HVM) #include +#endif + /* * altp2m operations are envisioned as being used in several different * modes: @@ -18,13 +20,13 @@ * - external: All control and decisions are made by an external agent * running domain 0. * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. + * - internal (x86 only): altp2m operations are used exclusively by an + * in-guest agent to protect itself from the guest kernel and + * in-guest attackers. * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). + * - coordinated (x86 only): An in-guest agent handles #VE and VMFUNCs + * locally, but makes requests of an agent running outside the + * domain for bigger changes (such as modifying altp2m entires). * * This corresponds to the three values for HVM_PARAM_ALTP2M * (external, mixed, limited). All three models have advantages and @@ -97,7 +99,7 @@ int do_altp2m_op( =20 if ( (a.cmd !=3D HVMOP_altp2m_get_domain_state) && (a.cmd !=3D HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) + !altp2m_active(d) ) { rc =3D -EOPNOTSUPP; goto out; @@ -122,6 +124,7 @@ int do_altp2m_op( =20 switch ( a.cmd ) { +#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state =3D altp2m_active(d); rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; @@ -394,9 +397,12 @@ int do_altp2m_op( rc =3D altp2m_set_view_visibility(d, idx, a.u.set_visibility.v= isible); break; } +#endif /* CONFIG_X86 */ =20 default: +#ifdef CONFIG_X86 ASSERT_UNREACHABLE(); +#endif rc =3D -EOPNOTSUPP; break; } @@ -406,13 +412,6 @@ int do_altp2m_op( =20 return rc; } -#else -int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ - return -EOPNOTSUPP; -} -#endif =20 /* * Local variables: --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286465.1567516 (Exim 4.92) (envelope-from ) id 1wEvBH-0001oA-So; Mon, 20 Apr 2026 20:25:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286465.1567516; Mon, 20 Apr 2026 20:25:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBH-0001nb-Nz; Mon, 20 Apr 2026 20:25:19 +0000 Received: by outflank-mailman (input) for mailman id 1286465; Mon, 20 Apr 2026 19:50:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEudt-0006FK-Mp for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:50:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuds-004tZC-Kz for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:50:48 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68380-2eae-0a2a0a5409dd-0a2a4501a5ac-36 for ; Mon, 20 Apr 2026 21:50:48 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e68397-c1f2-0a2a45010019-22cac1c584b0-3 for ; Mon, 20 Apr 2026 21:50:48 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:46 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=cQ3Kj18vTq+h+BnFJ531gezYODBGfokD+/LNu0kYWa16sn1xWZcfla/MM9fmKszMJiIqmmNTOzuqiSf4XwexfKtk19lamJ0H5B5JSrmrBux+Lxw9SqbJjry0lKcQWvCibE4GMH3pUvKUcN6Hi2qEfq/eNE5uAaGQvKeYGAWk9/OqbJIDMfNwjUIF3WGAhvNVsp8eeLUPo3GHb+3JjX7/Blug9TsSkxaI5s97x1To5/i+f/PpcCI1pA8ijcGMm8xAMcLSRXTpVvpiiMpj2rfwJjY37i/fci4qkiul5oB8iYiYPUBpi6IZF1E0PQPqDrsxD0YgNkfn/EgAVa4sqDjJug==; s=purelymail1; d=purelymail.com; v=1; bh=lNTQ4fq1EGY2M7SJPoOmAlK5TMMs/JCORxDPd0QwIXw=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Teddy Astie , Tamas K Lengyel , Bertrand Marquis , Volodymyr Babchuk , "Daniel P. Smith" , Rahul Singh , Julien Grall Subject: [RFC PATCH v6 00/43] altp2m: Move altp2m routines to common code and add ARM support Date: Mon, 20 Apr 2026 15:49:59 -0400 Message-Id: <20260420195042.207624-1-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-d62444/1776714648-B6A61FF4-907AD702/0/0 X-purgate-type: clean X-purgate-size: 9570 From: Rose Spangler Hi all, For the past few months, myself and Aqib Javid have been working to port altp2m to ARM with support from Stewart Hildebrand and Stefano Stabellini. At the recent Spring Xen Summit, Aqib and Stewart gave a presentation which discussed the motivation behind this, along with an overview of the rebasing and testing process. While this effort started as a rebase[1] of the v5 patch series[2] by Sergej Proskurin and Tamas Lengyel, I have been reworking the branch to make most of the altp2m code common between x86 and ARM. This should address the major concerns that came up during review of the original patch series. For a quick overview of altp2m functionality and scope of the patch series, here's an excerpt from Sergej's cover letter: > In this patch series, we provide an implementation of the altp2m > subsystem for ARM. Our implementation is based on the altp2m subsystem fo= r > x86, providing additional --alternate-- views on the guest's physical > memory by means of the ARM 2nd stage translation mechanism. The patches > introduce new HVMOPs and extend the p2m subsystem. [...] To be more > precise, altp2m allows to create and switch to additional p2m views (i.e. > gfn to mfn mappings). These views can be manipulated and activated as wil= l > through the provided HVMOPs. In this way, the active guest instance in > question can seamlessly proceed execution without noticing that anything > has changed. As of right now, I've reworked patch series up through the HVMOP_altp2m_set_domain_state command and plan to continue implementing the remaining altp2m features. I've continued the patch series versioning by labeling my notes as v6, and the patch notes from v1-v5 have been preserved where applicable. I am hoping for some feedback on the general approach I've taken with this patch series, and I can incorporate any changes requested into the actual patch series submission. This is a pretty big patch series, so I've tried to make it as easy as possible to follow. I've tried to minimize the number of changes in each patch; there are quite a lot of patches so if it would be preferred to combine some patches I can do so. Here is the general approach I used throughout the patch series to turn x86 altp2m code into common altp2m code with ARM support: - Move function(s) from arch/x86/mm/altp2m.c to common/altp2m.c, gating declarations/definitions with #ifdef CONFIG_X86 - Add any additional features to ARM code needed to implement these functions - Make any changes necessary to functions to support ARM, and remove #ifdef CONFIG_X86 This approach makes it possible to separate out code movement patches from the actual changes needed to support ARM. Furthermore, each patch in the patch series still compiles for both x86 and ARM. Additionally, I've split the patch series into a number of "phases" to make it easier to understand the context of each patch. Each patch description indicates which phase it's a part of. - Preparation (8 commits) - Common do_altp2m_op (2 commits) - get_domain_state (1 commit) - altp2m_{init,teardown} routines (12 commits) - altp2m_{get,set}_altp2m (4 commits) - Needed for altp2m_vcpu_{initialise,destroy} - altp2m_vcpu_{initialise,destroy} (2 commits) - Needed for HVMOP_set_domain_state - altp2m view visibility (5 commits) - Needed for altp2m_init_by_id, altp2m_flush - altp2m_activate_altp2m (2 commits) - Needed for altp2m_init_by_id - altp2m_init_by_id (2 commits) - Needed for HVMOP_altp2m_set_domain_state - altp2m_reset_altp2m (2 commits) - Needed for altp2m_flush - altp2m_flush (2 commits) - Needed for HVMOP_altp2m_set_domain_state - set_domain_state (1 commit) The code for this patch series can also be found on GitLab: https://gitlab.com/xen-project/people/elektrobit/xen/-/tree/altp2m-arm-rewo= rk-rfc Best, Rose Spangler [1] Rebase of original patch series: https://gitlab.com/xen-project/people/elektrobit/xen/-/commits/altp2m-arm-r= ebase [2] Original patch series: v1: https://lore.kernel.org/xen-devel/20160704114605.10086-1-proskurin@sec.= in.tum.de/ v2: https://lore.kernel.org/xen-devel/20160801171028.11615-1-proskurin@sec.= in.tum.de/ v3: https://lore.kernel.org/xen-devel/20160816221714.22041-1-proskurin@sec.= in.tum.de/ v4: https://lore.kernel.org/xen-devel/20170830183258.14612-1-proskurin@sec.= in.tum.de/ v5 was never submitted to mailing list, but is available on GitHub: https://github.com/sergej-proskurin/xen/tree/arm-altp2m-v5 Rose Spangler (38): altp2m: Add template common altp2m.c/altp2m.h altp2m: Move altp2m_active to common domain struct altp2m: Move altp2m_p2m to common domain struct x86/altp2m: Rename hvm_altp2m_supported to altp2m_supported altp2m: Move altp2m_supported to arch header arm/altp2m: Add template arch-specific altp2m.c/altp2m.h arm/altp2m: Introduce CONFIG_ALTP2M Kconfig option altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h altp2m: Move do_altp2m_op to common code altp2m: Add ARM support to do_altp2m_op arm/altp2m: Add support for HVMOP_altp2m_get_domain_state x86/p2m: Move p2m_{init,free}_one declarations to arch header x86/altp2m: Add lock functions accessible from common code altp2m: Move altp2m_{init,teardown} to common code arm/p2m: Allocate hostp2m with xzalloc arm/p2m: Move hostp2m init/teardown to individual functions arm/p2m: Invalidate root page table entries and flush TLB in p2m_flush_table arm/altp2m: Add support for altp2m init/teardown routines altp2m: Move altp2m_{get,set}_altp2m to common code arm/altp2m: Add altp2m index to arch_vcpu altp2m: Add altp2m_set_vcpu_idx arm/altp2m: Add support for altp2m_{get,set}_altp2m altp2m: Move altp2m_vcpu_{initialise,destroy} to common code arm/altp2m: Add support for altp2m_vcpu_{initialise,destroy} arm/altp2m: Add altp2m view validity/visibility indicator altp2m: Add altp2m_view_is_{valid,visible} x86/altp2m: Add altp2m_set_view_visibility_locked arm/altp2m: Add altp2m_set_view_visibility{,_locked} support arm/altp2m: Add support for HVMOP_altp2m_set_visibility x86/altp2m: Add altp2m_activate_altp2m declaration to arch header arm/altp2m: Add support for altp2m_activate_altp2m altp2m: Move altp2m_init_by_id to common code arm/altp2m: Add support for altp2m_init_by_id x86/altp2m: Add altp2m_reset_altp2m declaration to arch header arm/altp2m: Add altp2m_reset_altp2m routine altp2m: Move altp2m_flush to common code arm/altp2m: Add support for altp2m_flush arm/p2m: Add support for HVMOP_altp2m_set_domain_state Sergej Proskurin (5): arm/p2m: Cosmetic fix - substitute _gfn(ULONG_MAX) for INVALID_GFN arm/p2m: Change function prototype of p2m_alloc_table arm/p2m: Rename parameter in p2m_alloc_vmid arm/p2m: Change func prototype and impl of p2m_{alloc,free}_vmid arm/p2m: Introduce p2m_is_{hostp2m,altp2m} xen/arch/arm/Kconfig | 11 + xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 122 +++++ xen/arch/arm/domain.c | 2 +- xen/arch/arm/hvm.c | 9 + xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 84 ++++ xen/arch/arm/include/asm/domain.h | 19 +- xen/arch/arm/include/asm/p2m.h | 41 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 162 ++++++- xen/arch/arm/p2m.c | 31 +- xen/arch/arm/traps.c | 2 +- xen/arch/x86/domain.c | 3 +- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 413 +---------------- xen/arch/x86/hvm/monitor.c | 3 +- xen/arch/x86/hvm/vmx/vmx.c | 9 +- xen/arch/x86/include/asm/altp2m.h | 115 ++++- xen/arch/x86/include/asm/domain.h | 5 - xen/arch/x86/include/asm/hvm/hvm.h | 11 - xen/arch/x86/include/asm/p2m.h | 112 +---- xen/arch/x86/mm/altp2m.c | 242 +++------- xen/arch/x86/mm/hap/hap.c | 17 +- xen/arch/x86/mm/mem_access.c | 22 +- xen/arch/x86/mm/mem_sharing.c | 3 +- xen/arch/x86/mm/p2m-basic.c | 7 +- xen/arch/x86/mm/p2m-ept.c | 13 +- xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 9 +- xen/arch/x86/mm/p2m.h | 6 - xen/common/Makefile | 1 + xen/common/altp2m.c | 551 +++++++++++++++++++++++ xen/common/monitor.c | 1 + xen/common/vm_event.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- xen/include/asm-generic/altp2m.h | 5 +- xen/include/xen/altp2m.h | 98 ++++ xen/include/xen/p2m-common.h | 2 +- xen/include/xen/sched.h | 3 + 42 files changed, 1330 insertions(+), 818 deletions(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286476.1567549 (Exim 4.92) (envelope-from ) id 1wEvBJ-0002Ki-LF; Mon, 20 Apr 2026 20:25:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286476.1567549; Mon, 20 Apr 2026 20:25:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBJ-0002Hk-8I; Mon, 20 Apr 2026 20:25:21 +0000 Received: by outflank-mailman (input) for mailman id 1286476; Mon, 20 Apr 2026 19:50:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue0-0006IO-Ce for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:50:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEudz-004tZC-Pj for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:50:55 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6836c-2eae-0a2a0a5409dd-0a2a4503b316-32 for ; Mon, 20 Apr 2026 21:50:55 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6839e-672d-0a2a45030019-22cac1c5a53a-3 for ; Mon, 20 Apr 2026 21:50:55 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:48 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=T0h1p+KPW6xskaiN1TF/GqkmjkwnuwDjImGiUUhasrOTP48+CrkHmkHwqcexT9o7AkpH4PMPACLL8fu8UVo/ZDALP3IAyZ4mlaqOguHhZmM2tgKBzT6D64HnmGHfF/2al5LFIjaJHKkSUOsl0RhB9svFbQ5JKHHgcVmFSt3M/KPV1bH330irr3D/NiOASgijgnExV9lN9Rplc8V29HtGUNj6QiNZ+XylNy15VkThWPCMSd9SroGaGUpQKVXV/Z9lcnoag3C9Y+8LaTeAG+v+4AWlt7sJbmcTdM6DqaNj2WG1bKKo2bbGcSdBzkD/qdFEN9QbRyvHsT+1QFICIvgLEA==; s=purelymail1; d=purelymail.com; v=1; bh=MOrqrKIcHuJwSbppidFvZIeRSx3vTlSfdSMUlXig51U=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [RFC PATCH v6 05/43] altp2m: Move altp2m_supported to arch header Date: Mon, 20 Apr 2026 15:50:04 -0400 Message-Id: <20260420195042.207624-6-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-33051d/1776714655-A2F62938-A23BEFAB/0/0 X-purgate-type: clean X-purgate-size: 3291 From: Rose Spangler Following from the previous commit, this commit makes altp2m_supported available through the asm/altp2m.h header. This is commit 5/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 +++++++++++ xen/arch/x86/include/asm/hvm/hvm.h | 11 ----------- xen/include/asm-generic/altp2m.h | 7 +++++++ 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 512b18d4010f..e4f1cbf3b51e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -39,6 +39,7 @@ #include #include =20 +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index ad5ded833a75..07e760f60659 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,6 +28,12 @@ static inline bool altp2m_is_eptp_valid(const struct dom= ain *d, mfn_x(INVALID_MFN); } =20 +/* returns true if hardware supports alternate p2m's */ +static inline bool altp2m_supported(void) +{ + return hvm_funcs.caps.altp2m; +} + static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -58,6 +64,11 @@ static inline bool altp2m_is_eptp_valid(const struct dom= ain *d, return false; } =20 +static inline bool altp2m_supported(void) +{ + return false; +} + /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 6406bb687718..e6d8042831dc 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -701,12 +701,6 @@ static inline bool hvm_hap_supported(void) return hvm_funcs.caps.hap; } =20 -/* returns true if hardware supports alternate p2m's */ -static inline bool altp2m_supported(void) -{ - return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; -} - /* Returns true if we have the minimum hardware requirements for nested vi= rt */ static inline bool hvm_nested_virt_supported(void) { @@ -876,11 +870,6 @@ static inline bool hvm_hap_supported(void) return false; } =20 -static inline bool altp2m_supported(void) -{ - return false; -} - static inline bool hvm_nested_virt_supported(void) { return false; diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/alt= p2m.h index ecee6942f4e8..a3cdbdae9953 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -6,6 +6,13 @@ =20 struct vcpu; =20 +/* returns true if hardware supports alternate p2m's */ +static inline bool altp2m_supported(void) +{ + /* Not implemented on GENERIC. */ + return false; +} + /* Alternate p2m VCPU */ static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) { --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286469.1567524 (Exim 4.92) (envelope-from ) id 1wEvBI-0001ut-Bf; Mon, 20 Apr 2026 20:25:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286469.1567524; Mon, 20 Apr 2026 20:25:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBI-0001t0-8J; Mon, 20 Apr 2026 20:25:20 +0000 Received: by outflank-mailman (input) for mailman id 1286469; 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charset=UTF-8 X-purgate-ID: tlsNG-ef75cf/1776714650-AF374C48-8025B929/0/0 X-purgate-type: clean X-purgate-size: 5531 From: Rose Spangler Using a generic name for altp2m_supported makes it possible to indicate whether altp2m is supported on other architectures as well. Even if other architectures always support altp2m at a hardware level (like ARM), altp2m might not be supported due to CONFIG_ALTP2M being disabled. Therefore, the altp2m_supported function can be implemented on all architectures to indicate if the hardware supports altp2m *and* if CONFIG_ALTP2M is enabled. This is commit 4/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/hvm.c | 6 +++--- xen/arch/x86/include/asm/hvm/hvm.h | 4 ++-- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/p2m-basic.c | 4 ++-- xen/arch/x86/mm/p2m-ept.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1d458f1372e5..512b18d4010f 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -698,7 +698,7 @@ int arch_sanitise_domain_config(struct xen_domctl_creat= edomain *config) =20 if ( altp2m_mode ) { - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) { dprintk(XENLOG_INFO, "altp2m is not supported\n"); return -EINVAL; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 86c12c0d1ef4..bc35efdf2c02 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1692,7 +1692,7 @@ void hvm_vcpu_destroy(struct vcpu *v) =20 ioreq_server_remove_vcpu_all(v->domain, v); =20 - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) altp2m_vcpu_destroy(v); =20 nestedhvm_vcpu_destroy(v); @@ -4566,7 +4566,7 @@ static int do_altp2m_op( int rc =3D 0; uint64_t mode; =20 - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; =20 if ( copy_from_guest(&a, arg, 1) ) @@ -4965,7 +4965,7 @@ static int compat_altp2m_op( struct xen_hvm_altp2m_op *altp2m_op; } nat; =20 - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; =20 if ( copy_from_guest(&a, arg, 1) ) diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index e7c1364802f8..6406bb687718 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -702,7 +702,7 @@ static inline bool hvm_hap_supported(void) } =20 /* returns true if hardware supports alternate p2m's */ -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; } @@ -876,7 +876,7 @@ static inline bool hvm_hap_supported(void) return false; } =20 -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return false; } diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 6918a00a2a25..563eba3c0d36 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -501,7 +501,7 @@ int hap_enable(struct domain *d, u32 mode) } =20 #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { /* Init alternate p2m data */ if ( (d->arch.altp2m_eptp =3D alloc_xenheap_page()) =3D=3D NULL ) @@ -546,7 +546,7 @@ void hap_final_teardown(struct domain *d) unsigned int i; =20 #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) for ( i =3D 0; i < d->nr_altp2m; i++ ) p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif @@ -590,7 +590,7 @@ void hap_teardown(struct domain *d, bool *preempted) =20 #ifdef CONFIG_ALTP2M /* Leave the root pt in case we get further attempts to modify the p2m= . */ - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { if ( altp2m_active(d) ) for_each_vcpu ( d, v ) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index e126fda26760..ce14066fedaf 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } =20 - rc =3D hvm_altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc =3D altp2m_supported() ? p2m_init_altp2m(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -197,7 +197,7 @@ void p2m_final_teardown(struct domain *d) { if ( is_hvm_domain(d) ) { - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) p2m_teardown_altp2m(d); /* * We must tear down nestedp2m unconditionally because diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ddb4c7606be1..84159198f3a0 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -995,7 +995,7 @@ out: if ( is_epte_present(&old_entry) ) ept_free_entry(p2m, &old_entry, target); =20 - if ( hvm_altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) + if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { ret =3D p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt= , p2ma); if ( !rc ) --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286485.1567621 (Exim 4.92) (envelope-from ) id 1wEvBO-00044q-Hx; Mon, 20 Apr 2026 20:25:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286485.1567621; Mon, 20 Apr 2026 20:25:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBO-00042q-6g; Mon, 20 Apr 2026 20:25:26 +0000 Received: by outflank-mailman (input) for mailman id 1286485; Mon, 20 Apr 2026 19:50:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue2-0006J2-EH for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:50:58 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEue1-004tZC-RT for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:50:57 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68399-2eae-0a2a0a5409dd-0a2a45069f96-6 for ; Mon, 20 Apr 2026 21:50:57 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a0-7371-0a2a45060019-22cac1c5ec9e-3 for ; Mon, 20 Apr 2026 21:50:57 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:53 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=muZEtg+9hqCE9Xngud7IsV5yfOov+EcqU29MXHjlBiJJoKKLeG17AyyQMjEuJBE/lFBATMhGh02nsfzoCW0kOcJYx4T8+yqBGXvyEk5Ey53qfQKH3sAP73dkuPX4IQVhqdIwtgpQIgKU9ZEF0yKvA4B6GzMb71LDcckniZKrGw2/flY09Lvmeu6k6yk1p7PN96bBRoHjo/T/N+q6lhxYElm/6ev09NHw/ljoB1mXg9dvx+kS4BuKOUxrOPep8YyYpTyTJ6AHq3c7542Cf7hn2LpF7LQariPVlDYdngpsytm2thifqeygcRnA1Y2m69+/MM7ApUfUNzKmfM7fjWP6RQ==; s=purelymail1; d=purelymail.com; v=1; bh=hBUDJnrzrDzoRhr8LXgAIgyY4sGh7Kuf0/4gA394m2s=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Rahul Singh Subject: [RFC PATCH v6 15/43] arm/p2m: Allocate hostp2m with xzalloc Date: Mon, 20 Apr 2026 15:50:14 -0400 Message-Id: <20260420195042.207624-16-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-16d1c6/1776714657-CE974D75-ECB1B77F/0/0 X-purgate-type: clean X-purgate-size: 7464 From: Rose Spangler This commit replaces the concrete p2m_domain member in arch_domain with a pointer to p2m_domain, which is allocated with xzalloc during p2m initialization. In the following commits, the altp2m_init and altp2m_teardown routines from x86 are be moved to common code. These routines (respectively) allocate and free the p2m_domain structs for altp2m views. While it would be possible to have special code paths for allocating/freeing altp2m views while keeping the hostp2m as an concrete member, this results in code duplication and increases complexity without any clear benefit. Therefore, switching the hostp2m to be allocated separately from arch_domain (similarly to x86) makes it possible to use the same functions for both allocation/teardown/freeing of the hostp2m and altp2m views. This is commit 4/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/include/asm/domain.h | 2 +- xen/arch/arm/include/asm/p2m.h | 2 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 27 +++++++++++++++++++++--- xen/arch/arm/traps.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- 9 files changed, 32 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..be824a5ba18d 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -1099,7 +1099,7 @@ int domain_relinquish_resources(struct domain *d) * We are about to free the intermediate page-tables, so clear the * root to prevent any walk to use them. */ - p2m_clear_root_pages(&d->arch.p2m); + p2m_clear_root_pages(d->arch.p2m); =20 PROGRESS(p2m): ret =3D p2m_teardown(d); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index ffe5d0d9f0a6..576dbdec20af 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -72,7 +72,7 @@ struct arch_domain #endif =20 /* Virtual MMU */ - struct p2m_domain p2m; + struct p2m_domain *p2m; =20 struct hvm_domain hvm; =20 diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.= h index 010ce8c9ebbd..23df91ea13e9 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -410,7 +410,7 @@ static inline int get_page_and_type(struct page_info *p= age, } =20 /* get host p2m table */ -#define p2m_get_hostp2m(d) (&(d)->arch.p2m) +#define p2m_get_hostp2m(d) ((d)->arch.p2m) =20 static inline bool p2m_vm_event_sanity_check(struct domain *d) { diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6df8b616e464..46f9363ea851 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -116,7 +116,7 @@ bool page_is_offlinable(mfn_t mfn) =20 unsigned long domain_get_maximum_gpfn(struct domain *d) { - return gfn_x(d->arch.p2m.max_mapped_gfn); + return gfn_x(d->arch.p2m->max_mapped_gfn); } =20 void share_xen_page_with_guest(struct page_info *page, struct domain *d, diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51abf3504fcf..3ecb969a0369 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -5,6 +5,7 @@ #include #include #include +#include =20 #include #include @@ -1475,7 +1476,7 @@ void p2m_final_teardown(struct domain *d) =20 /* p2m not actually initialized */ if ( !p2m->domain ) - return; + goto free_p2m; =20 /* * No need to call relinquish_p2m_mapping() here because @@ -1499,11 +1500,13 @@ void p2m_final_teardown(struct domain *d) radix_tree_destroy(&p2m->mem_access_settings, NULL); =20 p2m->domain =3D NULL; + +free_p2m: + xfree(p2m); } =20 -int p2m_init(struct domain *d) +static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) { - struct p2m_domain *p2m =3D p2m_get_hostp2m(d); int rc; unsigned int cpu; =20 @@ -1556,6 +1559,24 @@ int p2m_init(struct domain *d) return 0; } =20 +int p2m_init(struct domain *d) +{ + struct p2m_domain *p2m =3D xzalloc(struct p2m_domain); + int rc; + + if ( !p2m ) + return -ENOMEM; + + rc =3D p2m_initialise(d, p2m); + + if ( !rc ) + d->arch.p2m =3D p2m; + else + xfree(p2m); + + return rc; +} + /* * The function will go through the p2m and remove page reference when it * is required. The mapping will be removed from the p2m. diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0c01f37ad6b4..637d27659b20 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -984,7 +984,7 @@ void vcpu_show_registers(struct vcpu *v) #endif =20 #ifdef CONFIG_MMU - ctxt.vttbr_el2 =3D v->domain->arch.p2m.vttbr; + ctxt.vttbr_el2 =3D v->domain->arch.p2m->vttbr; #endif =20 _show_registers(&v->arch.cpu_info->guest_cpu_user_regs, &ctxt, 1, v); diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index fa9ab9cb1330..d246c5e59005 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -565,7 +565,7 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_= domain *domain) * Use P2M table for this Xen domain. */ ASSERT(domain->d !=3D NULL); - ttbr =3D page_to_maddr(domain->d->arch.p2m.root); + ttbr =3D page_to_maddr(domain->d->arch.p2m->root); =20 dev_info(domain->mmu->root->dev, "%pd: Set IPMMU context %u (pgd 0x%"P= RIx64")\n", domain->d, domain->context_id, ttbr); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index bf153227dbd9..a7fbe58cba77 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1205,7 +1205,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smm= u_domain *smmu_domain, =09vtcr->tsz =3D 64 - p2m_ipa_bits; =09vtcr->sl =3D 2 - P2M_ROOT_LEVEL; =20 -=09arm_lpae_s2_cfg.vttbr =3D page_to_maddr(smmu_domain->d->arch.p2m.root)= ; +=09arm_lpae_s2_cfg.vttbr =3D page_to_maddr(smmu_domain->d->arch.p2m->root= ); =20 =09vmid =3D arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); =09if (vmid < 0) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index d63c9015510e..0975be2562bb 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1247,7 +1247,7 @@ static void arm_smmu_init_context_bank(struct arm_smm= u_domain *smmu_domain) =09/* TTBR0 */ =09/* Xen: The page table is shared with the P2M code */ =09ASSERT(smmu_domain->cfg.domain !=3D NULL); -=09p2maddr =3D page_to_maddr(smmu_domain->cfg.domain->arch.p2m.root); +=09p2maddr =3D page_to_maddr(smmu_domain->cfg.domain->arch.p2m->root); =20 =09dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", =09=09 smmu_domain->cfg.domain->domain_id, p2maddr); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286478.1567560 (Exim 4.92) (envelope-from ) id 1wEvBK-0002da-BA; Mon, 20 Apr 2026 20:25:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286478.1567560; Mon, 20 Apr 2026 20:25:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBK-0002bc-2G; Mon, 20 Apr 2026 20:25:22 +0000 Received: by outflank-mailman (input) for mailman id 1286478; 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dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=cpY2maM903g/OQMRmoi/K3FI7pEjR3/A+YruwAnmtiRHf9omKMSl8nfgytOWe/2WJ4y6LMidModJRjxD3299SATM+cYIt1FE6PyfCf+NvghidAp+e73oESRZl4qyDsToAEBWqb9ecanlP/9uCoEgFY+9DDGun6z7hikU3gjJjTSoZJGCyLMN1c8mSrQ8FWwSVogH7Oledm2jlUlKTlogTaryjXH0+3UUdp+qwKD3IuM02wlQwy4h5plrt78CVSM0w41v4T3zrYJX80nJcAuK9h6tqFQY4vkJamCeSbdBo2SdeDkT/ucR69l+T3dYf3ruc2KR9LSiZ19JHnrg2pmrkQ==; s=purelymail1; d=purelymail.com; v=1; bh=3vj2WBNpAfn2BAOUgjc4RDRuR1cwEZPmFeAg8+48xGU=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Tamas K Lengyel Subject: [RFC PATCH v6 08/43] altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h Date: Mon, 20 Apr 2026 15:50:07 -0400 Message-Id: <20260420195042.207624-9-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-d62444/1776714655-B7C74FF4-1611EB2B/0/0 X-purgate-type: clean X-purgate-size: 32837 From: Rose Spangler This commit renames altp2m functions with a p2m prefix. These functions were originally defined in p2m.c, hence the p2m prefix. When they were moved to altp2m.c in commit ae7584f63678, the function names were kept and the declarations remained in p2m.h. This commit finishes that move by renaming these functions to have an altp2m prefix and moving the declarations to altp2m.h. Since these functions will either be moved to the common altp2m.c, or implemented separately for ARM, it doesn't seem to make sense to continue with this naming convention. Therefore, this commit preemptively renames the x86 implementations of these functions so they can later be implemented with altp2m function name prefixes in common code or for ARM. For convenience, here is the full list of renames: - p2m_init_altp2m -> altp2m_init - p2m_teardown_altp2m -> altp2m_teardown - p2m_flush_altp2m -> altp2m_flush - p2m_altp2m_get_or_propagate -> altp2m_get_or_propagate - p2m_altp2m_propagate_change -> altp2m_propagate_change - p2m_get_altp2m -> altp2m_get_altp2m - p2m_set_altp2m -> altp2m_set_altp2m - p2m_reset_altp2m -> altp2m_reset_altp2m - p2m_activate_altp2m -> altp2m_activate_altp2m - p2m_init_altp2m_by_id -> altp2m_init_by_id - p2m_init_next_altp2m -> altp2m_init_next_available - p2m_destroy_altp2m_by_id -> altp2m_destroy_by_id - p2m_switch_domain_altp2m_by_id -> altp2m_switch_domain_altp2m_by_id - p2m_change_altp2m_gfn -> altp2m_change_gfn - p2m_set_altp2m_view_visibility -> altp2m_set_view_visibility This commit contains only function renames and code movement, and no functional change is intended. This is commit 8/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/altp2m.c | 2 +- xen/arch/x86/hvm/hvm.c | 30 ++++---- xen/arch/x86/hvm/monitor.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 6 +- xen/arch/x86/include/asm/altp2m.h | 116 +++++++++++++++++++++++++++++- xen/arch/x86/include/asm/p2m.h | 109 ---------------------------- xen/arch/x86/mm/altp2m.c | 76 ++++++++++---------- xen/arch/x86/mm/mem_access.c | 13 ++-- xen/arch/x86/mm/p2m-basic.c | 4 +- xen/arch/x86/mm/p2m-ept.c | 4 +- xen/arch/x86/mm/p2m.h | 3 - xen/common/vm_event.c | 2 +- xen/include/xen/p2m-common.h | 2 +- 13 files changed, 186 insertions(+), 183 deletions(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 8bd174ea8f37..339f82835caf 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -8,7 +8,7 @@ #include =20 /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { /* Not yet implemented */ BUG(); diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index bc35efdf2c02..5b6e91adce17 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1885,15 +1885,15 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned= long gla, =20 if ( altp2m_active(currd) ) { - p2m =3D p2m_get_altp2m(curr); + p2m =3D altp2m_get_altp2m(curr); =20 /* * Get the altp2m entry if present; or if not, propagate from * the host p2m. NB that this returns with gfn locked in the * altp2m. */ - if ( p2m_altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, - &p2ma, &page_order) ) + if ( altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, &p2ma, + &page_order) ) { /* Entry was copied from host -- retry fault */ rc =3D 1; @@ -2036,7 +2036,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned l= ong gla, paging_mark_pfn_dirty(currd, _pfn(gfn)); /* * If p2m is really an altp2m, unlock it before changing the t= ype, - * as p2m_altp2m_propagate_change() needs to acquire the + * as altp2m_propagate_change() needs to acquire the * altp2m_list lock. */ if ( p2m !=3D hostp2m ) @@ -4663,7 +4663,7 @@ static int do_altp2m_op( =20 /* If the alternate p2m state has changed, handle appropriately */ if ( d->altp2m_active !=3D ostate && - (ostate || !(rc =3D p2m_init_altp2m_by_id(d, 0))) ) + (ostate || !(rc =3D altp2m_init_by_id(d, 0))) ) { for_each_vcpu( d, v ) { @@ -4674,7 +4674,7 @@ static int do_altp2m_op( } =20 if ( ostate ) - p2m_flush_altp2m(d); + altp2m_flush(d); } else if ( rc ) d->altp2m_active =3D false; @@ -4729,17 +4729,18 @@ static int do_altp2m_op( } =20 case HVMOP_altp2m_create_p2m: - if ( !(rc =3D p2m_init_next_altp2m(d, &a.u.view.view, - a.u.view.hvmmem_default_access)) = ) + rc =3D altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; =20 case HVMOP_altp2m_destroy_p2m: - rc =3D p2m_destroy_altp2m_by_id(d, a.u.view.view); + rc =3D altp2m_destroy_by_id(d, a.u.view.view); break; =20 case HVMOP_altp2m_switch_p2m: - rc =3D p2m_switch_domain_altp2m_by_id(d, a.u.view.view); + rc =3D altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); break; =20 case HVMOP_altp2m_set_suppress_ve: @@ -4871,9 +4872,9 @@ static int do_altp2m_op( if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) rc =3D -EINVAL; else - rc =3D p2m_change_altp2m_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); + rc =3D altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); break; =20 case HVMOP_altp2m_get_p2m_idx: @@ -4906,8 +4907,7 @@ static int do_altp2m_op( else if ( !altp2m_active(d) ) rc =3D -EOPNOTSUPP; else - rc =3D p2m_set_altp2m_view_visibility(d, idx, - a.u.set_visibility.visible= ); + rc =3D altp2m_set_view_visibility(d, idx, a.u.set_visibility.v= isible); break; } =20 diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index 84c1c2234ca9..78137220b22a 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -182,7 +182,7 @@ int hvm_monitor_debug(unsigned long rip, enum hvm_monit= or_debug_type type, #ifdef CONFIG_ALTP2M if ( curr->arch.hvm.fast_single_step.enabled ) { - p2m_altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx)= ; + altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx); curr->arch.hvm.single_step =3D false; curr->arch.hvm.fast_single_step.enabled =3D false; curr->arch.hvm.fast_single_step.p2midx =3D 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0909929c00e0..f2cf95ee500e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2452,7 +2452,7 @@ static void cf_check vmx_vcpu_update_eptp(struct vcpu= *v) struct ept_data *ept; =20 if ( altp2m_active(d) ) - p2m =3D p2m_get_altp2m(v); + p2m =3D altp2m_get_altp2m(v); if ( !p2m ) p2m =3D p2m_get_hostp2m(d); =20 @@ -2521,7 +2521,7 @@ static int cf_check vmx_vcpu_emulate_vmfunc(const str= uct cpu_user_regs *regs) =20 if ( !cpu_has_vmx_vmfunc && altp2m_active(curr->domain) && regs->eax =3D=3D 0 && - p2m_switch_vcpu_altp2m_by_id(curr, regs->ecx) ) + altp2m_switch_vcpu_by_id(curr, regs->ecx) ) rc =3D X86EMUL_OKAY; =20 return rc; @@ -4277,7 +4277,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_re= gs *regs) } } =20 - p2m_set_altp2m(v, idx); + altp2m_set_altp2m(v, idx); } =20 if ( vm_event_is_enabled(v) && diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 07e760f60659..9c58a396448d 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -7,12 +7,33 @@ #ifndef __ASM_X86_ALTP2M_H #define __ASM_X86_ALTP2M_H =20 -#ifdef CONFIG_ALTP2M =20 #include #include /* for struct vcpu, struct domain */ + +#include #include /* for vcpu_altp2m */ =20 +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +/* Alternate p2m paging */ +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p= 2ma, + unsigned int *page_order); + +/* Propagate a host p2m change to all alternate p2m's */ +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma); + +#ifdef CONFIG_ALTP2M + +#define AP2MGET_prepopulate true +#define AP2MGET_query false + static inline bool altp2m_is_eptp_valid(const struct domain *d, unsigned int idx) { @@ -39,6 +60,85 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu= *v) return vcpu_altp2m(v).p2midx; } =20 +/* + * Alternate p2m: shadow p2m tables used for alternate memory views + */ + +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index =3D vcpu_altp2m(v).p2midx; + + if ( index =3D=3D INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >=3D v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >=3D v->domain->nr_altp2m); + + if ( idx =3D=3D vcpu_altp2m(v).p2midx ) + return false; + + orig =3D altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx =3D idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} + +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); + +/* Free altp2m views */ +void altp2m_teardown(struct domain *d); + +/* Switch alternate p2m for a single vcpu */ +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); + +/* Flush all the alternate p2m's for a domain */ +void altp2m_flush(struct domain *d); + +/* Make a specific alternate p2m valid */ +int altp2m_init_by_id(struct domain *d, unsigned int idx); + +/* Find an available alternate p2m and make it valid */ +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access); + +/* Make a specific alternate p2m invalid */ +int altp2m_destroy_by_id(struct domain *d, unsigned int idx); + +/* Switch alternate p2m for entire domain */ +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); + +/* Change a gfn->mfn mapping */ +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn); + +/* Set a specific p2m view visibility */ +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + +/* + * Looks up altp2m entry. If the entry is not found it looks up the entry = in + * hostp2m. + * The prepopulate param is used to set the found entry in altp2m. + */ +int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *= mfn, + p2m_type_t *t, p2m_access_t *a, + bool prepopulate); + /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); @@ -69,7 +169,21 @@ static inline bool altp2m_supported(void) return false; } =20 +static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, + gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *= a) +{ + ASSERT_UNREACHABLE(); + return -EOPNOTSUPP; +} +#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ + _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) + /* Only declaration is needed. DCE will optimise it out when linking. */ +int altp2m_init(struct domain *d); +void altp2m_teardown(struct domain *d); +struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); +bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.= h index ec871717a9e4..5110b3e77807 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -582,30 +582,6 @@ static inline gfn_t mfn_to_gfn(const struct domain *d,= mfn_t mfn) return _gfn(mfn_x(mfn)); } =20 -#ifdef CONFIG_ALTP2M -#define AP2MGET_prepopulate true -#define AP2MGET_query false - -/* - * Looks up altp2m entry. If the entry is not found it looks up the entry = in - * hostp2m. - * The prepopulate param is used to set the found entry in altp2m. - */ -int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *= mfn, - p2m_type_t *t, p2m_access_t *a, - bool prepopulate); -#else -static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, - gfn_t gfn, mfn_t *mfn, - p2m_type_t *t, p2m_access_t *= a) -{ - ASSERT_UNREACHABLE(); - return -EOPNOTSUPP; -} -#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ - _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) -#endif - /* Init the datastructures for later use by the p2m code */ int p2m_init(struct domain *d); =20 @@ -885,91 +861,6 @@ void shadow_p2m_init(struct p2m_domain *p2m); void cf_check nestedp2m_write_p2m_entry_post( struct p2m_domain *p2m, unsigned int oflags); =20 -#ifdef CONFIG_ALTP2M - -/* - * Alternate p2m: shadow p2m tables used for alternate memory views - */ - -/* get current alternate p2m table */ -static inline struct p2m_domain *p2m_get_altp2m(struct vcpu *v) -{ - unsigned int index =3D vcpu_altp2m(v).p2midx; - - if ( index =3D=3D INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >=3D v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool p2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >=3D v->domain->nr_altp2m); - - if ( idx =3D=3D vcpu_altp2m(v).p2midx ) - return false; - - orig =3D p2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx =3D idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - -/* Switch alternate p2m for a single vcpu */ -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx); - -/* Flush all the alternate p2m's for a domain */ -void p2m_flush_altp2m(struct domain *d); - -/* Make a specific alternate p2m valid */ -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Find an available alternate p2m and make it valid */ -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access); - -/* Make a specific alternate p2m invalid */ -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Switch alternate p2m for entire domain */ -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Change a gfn->mfn mapping */ -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn); - -/* Set a specific p2m view visibility */ -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_i= dx, - uint8_t visible); - -#else /* !CONFIG_ALTP2M */ -struct p2m_domain *p2m_get_altp2m(struct vcpu *v); -bool p2m_set_altp2m(struct vcpu *v, unsigned int idx); -#endif /* CONFIG_ALTP2M */ - -/* - * Common alternate p2m declarations that need to be visible - * regardless of CONFIG_ALTP2M - */ - -/* Alternate p2m paging */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gf= n_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_or= der); - =20 -/* Propagate a host p2m change to all alternate p2m's */ -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma); #endif /* CONFIG_HVM */ =20 /* p2m access to IOMMU flags */ diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 8dd3c0f96be0..2dc84b76b8c1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -24,7 +24,7 @@ altp2m_vcpu_initialise(struct vcpu *v) vcpu_pause(v); =20 vcpu_altp2m(v).p2midx =3D 0; - atomic_inc(&p2m_get_altp2m(v)->active_vcpus); + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); =20 altp2m_vcpu_update_p2m(v); =20 @@ -43,7 +43,7 @@ altp2m_vcpu_destroy(struct vcpu *v) if ( v !=3D current ) vcpu_pause(v); =20 - if ( (p2m =3D p2m_get_altp2m(v)) ) + if ( (p2m =3D altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); =20 altp2m_vcpu_disable_ve(v); @@ -123,7 +123,7 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } =20 -int p2m_init_altp2m(struct domain *d) +int altp2m_init(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -140,7 +140,7 @@ int p2m_init_altp2m(struct domain *d) d->altp2m_p2m[i] =3D p2m =3D p2m_init_one(d); if ( p2m =3D=3D NULL ) { - p2m_teardown_altp2m(d); + altp2m_teardown(d); return -ENOMEM; } p2m->p2m_class =3D p2m_alternate; @@ -151,7 +151,7 @@ int p2m_init_altp2m(struct domain *d) return 0; } =20 -void p2m_teardown_altp2m(struct domain *d) +void altp2m_teardown(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -207,13 +207,13 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2= m, gfn_t gfn, mfn_t *mfn, return 0; } =20 -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { if ( altp2m_active(v->domain) ) - p2m_switch_vcpu_altp2m_by_id(v, idx); + altp2m_switch_vcpu_by_id(v, idx); } =20 -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) { struct domain *d =3D v->domain; bool rc =3D false; @@ -225,7 +225,7 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsig= ned int idx) =20 if ( d->arch.altp2m_eptp[idx] !=3D mfn_x(INVALID_MFN) ) { - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); rc =3D 1; } @@ -246,9 +246,9 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsig= ned int idx) * the host's entry to the altp2m (retaining page order), and indicate * that the caller should re-try the faulting instruction. */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gf= n_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_or= der) +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p= 2ma, + unsigned int *page_order) { p2m_type_t ap2mt; p2m_access_t ap2ma; @@ -319,8 +319,8 @@ enum altp2m_reset_type { ALTP2M_DEACTIVATE }; =20 -static void p2m_reset_altp2m(struct domain *d, unsigned int idx, - enum altp2m_reset_type reset_type) +static void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type) { struct p2m_domain *p2m; =20 @@ -344,7 +344,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned= int idx, p2m_unlock(p2m); } =20 -void p2m_flush_altp2m(struct domain *d) +void altp2m_flush(struct domain *d) { unsigned int i; =20 @@ -352,7 +352,7 @@ void p2m_flush_altp2m(struct domain *d) =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - p2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[i] =3D mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[i] =3D mfn_x(INVALID_MFN); } @@ -360,8 +360,8 @@ void p2m_flush_altp2m(struct domain *d) altp2m_list_unlock(d); } =20 -static int p2m_activate_altp2m(struct domain *d, unsigned int idx, - p2m_access_t hvmmem_default_access) +static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access) { struct p2m_domain *hostp2m, *p2m; int rc; @@ -399,9 +399,9 @@ static int p2m_activate_altp2m(struct domain *d, unsign= ed int idx, p2m_unlock(p2m); =20 return rc; -} + } =20 -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_init_by_id(struct domain *d, unsigned int idx) { int rc =3D -EINVAL; struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); @@ -413,14 +413,14 @@ int p2m_init_altp2m_by_id(struct domain *d, unsigned = int idx) =20 if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] =3D=3D mfn_x(INVALID_MFN) ) - rc =3D p2m_activate_altp2m(d, idx, hostp2m->default_access); + rc =3D altp2m_activate_altp2m(d, idx, hostp2m->default_access); =20 altp2m_list_unlock(d); return rc; } =20 -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access) +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access) { int rc =3D -EINVAL; unsigned int i; @@ -438,7 +438,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *id= x, if ( d->arch.altp2m_eptp[i] !=3D mfn_x(INVALID_MFN) ) continue; =20 - rc =3D p2m_activate_altp2m(d, i, a); + rc =3D altp2m_activate_altp2m(d, i, a); =20 if ( !rc ) *idx =3D i; @@ -450,7 +450,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *id= x, return rc; } =20 -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_destroy_by_id(struct domain *d, unsigned int idx) { struct p2m_domain *p2m; int rc =3D -EBUSY; @@ -472,7 +472,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned= int idx) =20 if ( !_atomic_read(p2m->active_vcpus) ) { - p2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] =3D mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[array_index_nospec(idx, MAX_EPTP)]= =3D @@ -488,7 +488,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned= int idx) return rc; } =20 -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) { struct vcpu *v; int rc =3D -EINVAL; @@ -506,7 +506,7 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, un= signed int idx) if ( d->arch.altp2m_visible_eptp[idx] !=3D mfn_x(INVALID_MFN) ) { for_each_vcpu( d, v ) - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); =20 rc =3D 0; @@ -519,8 +519,8 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, un= signed int idx) return rc; } =20 -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn) +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn) { struct p2m_domain *hp2m, *ap2m; p2m_access_t a; @@ -571,11 +571,11 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned = int idx, p2m_unlock(ap2m); p2m_unlock(hp2m); return rc; -} + } =20 -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma) +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma) { struct p2m_domain *p2m; unsigned int i; @@ -605,7 +605,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t= gfn, { if ( !reset_count++ ) { - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); last_reset_idx =3D i; } else @@ -617,7 +617,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t= gfn, d->arch.altp2m_eptp[i] =3D=3D mfn_x(INVALID_MFN) = ) continue; =20 - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); } =20 ret =3D 0; @@ -768,8 +768,8 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bo= ol *suppress_ve, return rc; } =20 -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_i= dx, - uint8_t visible) +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) { int rc =3D 0; =20 diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e5548e64d8d0..0492356d99ad 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -81,7 +81,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v, struct p2m_domain *p2m =3D NULL; =20 if ( altp2m_active(d) ) - p2m =3D p2m_get_altp2m(v); + p2m =3D altp2m_get_altp2m(v); if ( !p2m ) p2m =3D p2m_get_hostp2m(d); =20 @@ -145,7 +145,7 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gl= a, int rc; =20 if ( altp2m_active(d) ) - p2m =3D p2m_get_altp2m(v); + p2m =3D altp2m_get_altp2m(v); if ( !p2m ) p2m =3D p2m_get_hostp2m(d); =20 @@ -252,9 +252,10 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long g= la, return (p2ma !=3D p2m_access_n2rwx); } =20 -static int p2m_set_altp2m_mem_access(struct domain *d, struct p2m_domain *= hp2m, - struct p2m_domain *ap2m, p2m_access_t= a, - gfn_t gfn) +static int altp2m_set_altp2m_mem_access(struct domain *d, + struct p2m_domain *hp2m, + struct p2m_domain *ap2m, p2m_acces= s_t a, + gfn_t gfn) { mfn_t mfn; p2m_type_t t; @@ -281,7 +282,7 @@ static int set_mem_access(struct domain *d, struct p2m_= domain *p2m, =20 if ( ap2m ) { - rc =3D p2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); + rc =3D altp2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); /* If the corresponding mfn is invalid we will want to just skip i= t */ if ( rc =3D=3D -ESRCH ) rc =3D 0; diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index ce14066fedaf..433e7d08b78f 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } =20 - rc =3D altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc =3D altp2m_supported() ? altp2m_init(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -198,7 +198,7 @@ void p2m_final_teardown(struct domain *d) if ( is_hvm_domain(d) ) { if ( altp2m_supported() ) - p2m_teardown_altp2m(d); + altp2m_teardown(d); /* * We must tear down nestedp2m unconditionally because * we initialise it unconditionally. diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index 84159198f3a0..a6f61a9dd3d7 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -773,7 +773,7 @@ bool ept_handle_misconfig(uint64_t gpa) int rc; =20 if ( altp2m_active(curr->domain) ) - p2m =3D p2m_get_altp2m(curr); + p2m =3D altp2m_get_altp2m(curr); =20 p2m_lock(p2m); =20 @@ -997,7 +997,7 @@ out: =20 if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { - ret =3D p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt= , p2ma); + ret =3D altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2= ma); if ( !rc ) rc =3D ret; } diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 635f5a7f45cd..64218878067e 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -19,9 +19,6 @@ static inline int p2m_init_logdirty(struct p2m_domain *p2= m) { return 0; } static inline void p2m_free_logdirty(struct p2m_domain *p2m) {} #endif =20 -int p2m_init_altp2m(struct domain *d); -void p2m_teardown_altp2m(struct domain *d); - void p2m_flush_table_locked(struct p2m_domain *p2m); int __must_check p2m_remove_entry(struct p2m_domain *p2m, gfn_t gfn, mfn_t= mfn, unsigned int page_order); diff --git a/xen/common/vm_event.c b/xen/common/vm_event.c index cf0258223f50..77e0c8a0b240 100644 --- a/xen/common/vm_event.c +++ b/xen/common/vm_event.c @@ -433,7 +433,7 @@ static int vm_event_resume(struct domain *d, struct vm_= event_domain *ved) /* Check for altp2m switch */ if ( IS_ENABLED(CONFIG_ALTP2M) && rsp.flags & VM_EVENT_FLAG_ALTERNATE_P2M ) - p2m_altp2m_check(v, rsp.altp2m_idx); + altp2m_check(v, rsp.altp2m_idx); =20 if ( rsp.flags & VM_EVENT_FLAG_SET_REGISTERS ) vm_event_set_registers(v, &rsp); diff --git a/xen/include/xen/p2m-common.h b/xen/include/xen/p2m-common.h index f0bd9a6b9896..6da330acca1f 100644 --- a/xen/include/xen/p2m-common.h +++ b/xen/include/xen/p2m-common.h @@ -25,7 +25,7 @@ int unmap_mmio_regions(struct domain *d, mfn_t mfn); =20 /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx); +void altp2m_check(struct vcpu *v, uint16_t idx); =20 /* * Populate-on-Demand --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286490.1567639 (Exim 4.92) (envelope-from ) id 1wEvBQ-0004kJ-Tp; Mon, 20 Apr 2026 20:25:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286490.1567639; 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d=purelymail.com; v=1; bh=5qX8VqlfLuFzhxCaItkjpTl/pD3HY4nQgg/454o6cjs=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Sergej Proskurin , Stefano Stabellini , Julien Grall Subject: [RFC PATCH v6 17/43] arm/p2m: Move hostp2m init/teardown to individual functions Date: Mon, 20 Apr 2026 15:50:16 -0400 Message-Id: <20260420195042.207624-18-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-bad1c0/1776714658-486A8A53-5272C0EC/0/0 X-purgate-type: clean X-purgate-size: 10277 From: Rose Spangler This commit pulls out generic init/teardown functionality out of "p2m_init" and "p2m_teardown" into "p2m_init_one", "p2m_teardown_one", "p2m_free_one", and "p2m_flush_table" functions. This allows our future implementation to reuse existing code for the initialization/teardown of altp2m views. On failure, the p2m_init_one function returns a null pointer. This means p2m_init_one doesn't return an error code, which prevents it from propagating the exact error from p2m_initialise (specifically, ENOMEM if allocation fails and EBUSY if the VMID pool is exhausted). However, returning a p2m_domain pointer simplifies usage for callers of p2m_init_one, as they can receive an allocated and initialized p2m_domain without needing to handle allocation separately. Therefore, the main p2m_init function will now return ENOMEM instead of EBUSY when the VMID pool is exhausted. This is commit 6/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- Cc: Stefano Stabellini Cc: Julien Grall --- v2: Added the function p2m_flush_table to the previous version. v3: Removed struct vttbr. Moved define INVALID_VTTBR to p2m.h. Exported function prototypes of "p2m_flush_table", "p2m_init_one", and "p2m_teardown_one" in p2m.h. Extended the function "p2m_flush_table" by additionally resetting the fields lowest_mapped_gfn and max_mapped_gfn. Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. Added a check checking whether p2m->root is NULL in p2m_flush_table. Renamed the function "p2m_free_one" to "p2m_teardown_one". Removed resetting p2m->vttbr in "p2m_teardown_one", as it the p2m will be destroyed afterwards. Moved call to "p2m_alloc_table" back to "p2m_init_one". Moved the introduction of the type p2m_class_t out of this patch. Moved the backpointer to the struct domain out of the struct p2m_domain. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). Removed unnecessary initializations in the functions "p2m_init_one" and "p2m_teardown_one". Removed the define INVALID_VTTBR as it is not used any more. Cosmetic fixes. v6: Reworked to accommodate the hostp2m being allocated separately from arch_domain. Split p2m_teardown_one into p2m_teardown_one and p2m_free_one, with both having the same semantics as their x86 counterparts. The previous version of this patch also added code to p2m_flush_table. This has been split out into a separate commit to minimize the number of actual changes in this commit. Updated to account for the introduction of p2m_final_teardown. The code which previously was used to reclaim resources from the hostp2m during p2m_final_teardown was extracted into p2m_free_one. Now, p2m_final_teardown will call p2m_free_one on the hostp2m instead. The check for whether the p2m was actually initialized was moved into p2m_free_one. This means there is a slight behavior change where p2m_teardown_allocation will always be called, even if the p2m_domain was never initialized. I'm not sure if this is really a big deal (it does require the lock to be obtained, but this shouldn't be an issue at final teardown?), but if it is then I can duplicate the check from p2m_free_one to the top of p2m_final_teardown, which would replicate the previous behavior. For the sake of making the p2m_init_one function simple to use (and match the x86 function prototype), it returns a null pointer on error rather than an error code. While on x86 an error from p2m_init_one is always due to an ENOMEM return code (from xzalloc, zalloc_cpumask_var), on ARM p2m_initialise (called by p2m_init_one) can actually return EBUSY if the VMID pool is exhausted. Therefore, in this error case the null pointer return value of p2m_init_one obscures the true error code (EBUSY). Callers of p2m_init_one always return ENOMEM when p2m_init_one returns a null pointer, so this error will be propagated up as ENOMEM rather than EBUSY. The alternative to this would be to have callers pass a null **p2m_domain to p2m_init_one while still returning an integer return code. In order to preserve a common altp2m_init routine, this change would also have to be made on x86 (where there wouldn't be any real benefit, the return code is truly only ever ENOMEM). Therefore, it seems like an acceptable tradeoff to me to obscure the error in this case, but if other folks think we should handle this differently than I can revisit this. The p2m_teardown_allocation call and p2m_init_one return code changes mentioned above should be the only actual behavior changes in this patch, otherwise it should be just code movement. --- xen/arch/arm/include/asm/p2m.h | 12 ++++++ xen/arch/arm/mmu/p2m.c | 77 +++++++++++++++++++++++----------- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.= h index 23df91ea13e9..5c6dfe4a9789 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -216,6 +216,18 @@ int p2m_init(struct domain *d); int p2m_teardown(struct domain *d); void p2m_final_teardown(struct domain *d); =20 +/* Flushes the page table held by the p2m. */ +int p2m_flush_table(struct p2m_domain *p2m); + +/* Initialize the p2m structure. */ +struct p2m_domain *p2m_init_one(struct domain *d); + +/* Release resources held by the p2m structure. */ +int p2m_teardown_one(struct p2m_domain *p2m); + +/* Free the p2m structure allocation. */ +void p2m_free_one(struct p2m_domain *p2m); + /* * Remove mapping refcount on each mapping page in the p2m * diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1009f10e5db4..1d598c66450b 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1444,14 +1444,10 @@ static int p2m_alloc_table(struct domain *d) return 0; } =20 -int p2m_teardown(struct domain *d) +int p2m_flush_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m =3D p2m_get_hostp2m(d); unsigned long count =3D 0; struct page_info *pg; - int rc =3D 0; - - p2m_write_lock(p2m); =20 while ( (pg =3D page_list_remove_head(&p2m->pages)) ) { @@ -1460,23 +1456,34 @@ int p2m_teardown(struct domain *d) /* Arbitrarily preempt every 512 iterations */ if ( !(count % 512) && hypercall_preempt_check() ) { - rc =3D -ERESTART; - break; + return -ERESTART; } } =20 + return 0; +} + +int p2m_teardown_one(struct p2m_domain *p2m) +{ + int rc; + + p2m_write_lock(p2m); + rc =3D p2m_flush_table(p2m); p2m_write_unlock(p2m); =20 return rc; } =20 -void p2m_final_teardown(struct domain *d) +int p2m_teardown(struct domain *d) { struct p2m_domain *p2m =3D p2m_get_hostp2m(d); =20 - /* p2m not actually initialized */ - if ( !p2m->domain ) - goto free_p2m; + return p2m_teardown_one(p2m); +} + +void p2m_final_teardown(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); =20 /* * No need to call relinquish_p2m_mapping() here because @@ -1484,18 +1491,27 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ =20 - ASSERT(page_list_empty(&p2m->pages)); - while ( p2m_teardown_allocation(d) =3D=3D -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); =20 + p2m_free_one(p2m); +} + +void p2m_free_one(struct p2m_domain *p2m) +{ + /* p2m not actually initialized */ + if ( !p2m->domain ) + goto free_p2m; + + ASSERT(page_list_empty(&p2m->pages)); + if ( p2m->root ) free_domheap_pages(p2m->root, P2M_ROOT_ORDER); =20 p2m->root =3D NULL; =20 - p2m_free_vmid(d); + p2m_free_vmid(p2m->domain); =20 radix_tree_destroy(&p2m->mem_access_settings, NULL); =20 @@ -1511,9 +1527,7 @@ static int p2m_initialise(struct domain *d, struct p2= m_domain *p2m) unsigned int cpu; =20 rwlock_init(&p2m->lock); - spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&p2m->pages); - INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); =20 p2m->vmid =3D INVALID_VMID; p2m->max_mapped_gfn =3D _gfn(0); @@ -1559,22 +1573,37 @@ static int p2m_initialise(struct domain *d, struct = p2m_domain *p2m) return 0; } =20 -int p2m_init(struct domain *d) +struct p2m_domain *p2m_init_one(struct domain *d) { struct p2m_domain *p2m =3D xzalloc(struct p2m_domain); - int rc; + + if ( !p2m ) + return NULL; + + if ( !p2m_initialise(d, p2m) ) + return p2m; + + xfree(p2m); + return NULL; +} + +static int p2m_init_hostp2m(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_init_one(d); =20 if ( !p2m ) return -ENOMEM; =20 - rc =3D p2m_initialise(d, p2m); + d->arch.p2m =3D p2m; + return 0; +} =20 - if ( !rc ) - d->arch.p2m =3D p2m; - else - xfree(p2m); +int p2m_init(struct domain *d) +{ + spin_lock_init(&d->arch.paging.lock); + INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); =20 - return rc; + return p2m_init_hostp2m(d); } =20 /* --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286480.1567579 (Exim 4.92) (envelope-from ) id 1wEvBL-00033E-CV; Mon, 20 Apr 2026 20:25:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286480.1567579; Mon, 20 Apr 2026 20:25:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBK-00030H-W7; Mon, 20 Apr 2026 20:25:22 +0000 Received: by outflank-mailman (input) for mailman id 1286480; Mon, 20 Apr 2026 19:50:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue1-0006In-TJ for xen-devel@lists.xenproject.org; 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dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=ZfRbcmN7j4RW4dTVDZPstZ52p5xuNQyJkowqmjLG7VTyYNxugUPBUj9yDrvIw3BvahQvlL5kQiYvvoSdtFJ17E8ieLE5kq7TScI7xLkqhaDMBxqNcWZp5Lxy92eUjsEqhFo/FyAxraBJCTEU/cxuBMNilRtxcVdl34nMXxSoth0iTmLUhc7D3CH6ToSlNOixxVVwieKzhvtrsiBadPVjeKyr2qeurljwDM/KuRZKwS0KxJSEMNDR/oJ07sTg1FX6yyzMapY+gbj5hYtTdTzTZqWEGUUsZHitUSQ8NILccgAWE9sGK59VBypDy4L/ZWqXbh9hcT9rZmUp/NePUMgUjw==; s=purelymail1; d=purelymail.com; v=1; bh=Hus8g9FcCxBCtWlrCzMkC4ORYsW88lGiIhFMrIDvnqs=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 11/43] arm/altp2m: Add support for HVMOP_altp2m_get_domain_state Date: Mon, 20 Apr 2026 15:50:10 -0400 Message-Id: <20260420195042.207624-12-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-bad1c0/1776714657-8BF7EA53-C04C92A3/0/0 X-purgate-type: clean X-purgate-size: 1279 From: Rose Spangler This commit adds support for the altp2m_get_domain_state HVMOP on ARM. All code used in the command implementation already works on ARM, so no further changes beyond moving the #ifdef are necessary. This is commit 1/1 of the get_domain_state phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This commit can be squashed into the previous commit for the actual submission if that would be preferred, but I thought it might be easier to understand the command #ifdef gate approach by splitting this into a separate patch. --- xen/common/altp2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 6481fae1ed12..3a3283f0860a 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -124,12 +124,12 @@ int do_altp2m_op( =20 switch ( a.cmd ) { -#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state =3D altp2m_active(d); rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; =20 +#ifdef CONFIG_X86 case HVMOP_altp2m_set_domain_state: { struct vcpu *v; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286479.1567568 (Exim 4.92) (envelope-from ) id 1wEvBK-0002me-Lp; Mon, 20 Apr 2026 20:25:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286479.1567568; Mon, 20 Apr 2026 20:25:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBK-0002kN-F8; Mon, 20 Apr 2026 20:25:22 +0000 Received: by outflank-mailman (input) for mailman id 1286479; Mon, 20 Apr 2026 19:50:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue0-0006IW-LG for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:50:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEue0-00EWC2-1x for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:50:56 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6835b-5cb7-0a2a0a5109dd-0a2a4508c320-28 for ; Mon, 20 Apr 2026 21:50:56 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6839e-63b5-0a2a45080019-22cac1c59c98-3 for ; Mon, 20 Apr 2026 21:50:55 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:50 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=QHeYVgAjoAe2aeyzRnA9SjAaQGGMS5KFcHverUnPbaE0xdYsYbbfpAzsen8s6X4NnAaGSLFaihsmFazNvfG5+s0lGodMF99KDWyzJUYWXu603latBFwPdEsMHQ44Am9HyLoilxqvTfwGda4pPSyr/FFYsYURtvjALB1FDXc6I7k+ckcIvX+UL52Wqnw2aTUxfSWabc15IHghbn94xmnUOKcTC0AW4fABs+QBOPfxNBmEmtgn52UaA45d9qXuW0qFCm9lzjoLKUrwtlhE6OHuKE+VfTudwjpkxBj7IK5loLZ5DPsHtrVW8kQviM9JkE3FKtq0NIHIOvVeteyX7vZDKA==; s=purelymail1; d=purelymail.com; v=1; bh=SVKLQ6kcKUAU2bennXpDwH0c/FyTIXAe5xYEJVfFFsY=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , "Daniel P. Smith" , Aqib Javaid Subject: [RFC PATCH v6 09/43] altp2m: Move do_altp2m_op to common code Date: Mon, 20 Apr 2026 15:50:08 -0400 Message-Id: <20260420195042.207624-10-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c1860d/1776714656-C2B74DB1-90B90380/0/0 X-purgate-type: clean X-purgate-size: 26850 From: Rose Spangler This commit moves the altp2m HVMOP implementation to common code, making it possible to re-use it across architectures. In this commit, the entire implementation is gated behind CONFIG_X86, with no changes to the body of do_altp2m_op. A stub implementation is added for ARM, which will be removed once do_altp2m_op has been modified to add ARM support. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/x86/hvm/hvm.c | 400 ------------------------------------- xen/common/altp2m.c | 413 +++++++++++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 11 ++ 3 files changed, 424 insertions(+), 400 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5b6e91adce17..4adcc3c49d95 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4526,406 +4526,6 @@ static int hvmop_get_param( return rc; } =20 -/* - * altp2m operations are envisioned as being used in several different - * modes: - * - * - external: All control and decisions are made by an external agent - * running domain 0. - * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. - * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). - * - * This corresponds to the three values for HVM_PARAM_ALTP2M - * (external, mixed, limited). All three models have advantages and - * disadvantages. - * - * Normally hypercalls made by a program in domain 0 in order to - * control a guest would be DOMCTLs rather than HVMOPs. But in order - * to properly enable the 'internal' use case, as well as to avoid - * fragmentation, all altp2m subops should come under this single - * HVMOP. - * - * Note that 'internal' mode (HVM_PARAM_ALTP2M =3D=3D XEN_ALTP2M_mixed) - * has not been evaluated for safety from a security perspective. - * Before using this mode in a security-critical environment, each - * subop should be evaluated for safety, with unsafe subops - * blacklisted in xsm_hvm_altp2mhvm_op(). - */ -static int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ -#ifdef CONFIG_ALTP2M - struct xen_hvm_altp2m_op a; - struct domain *d =3D NULL; - int rc =3D 0; - uint64_t mode; - - if ( !altp2m_supported() ) - return -EOPNOTSUPP; - - if ( copy_from_guest(&a, arg, 1) ) - return -EFAULT; - - if ( a.pad1 || a.pad2 || - (a.version !=3D HVMOP_ALTP2M_INTERFACE_VERSION) ) - return -EINVAL; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - case HVMOP_altp2m_set_domain_state: - case HVMOP_altp2m_vcpu_enable_notify: - case HVMOP_altp2m_vcpu_disable_notify: - case HVMOP_altp2m_create_p2m: - case HVMOP_altp2m_destroy_p2m: - case HVMOP_altp2m_switch_p2m: - case HVMOP_altp2m_set_suppress_ve: - case HVMOP_altp2m_set_suppress_ve_multi: - case HVMOP_altp2m_get_suppress_ve: - case HVMOP_altp2m_set_mem_access: - case HVMOP_altp2m_set_mem_access_multi: - case HVMOP_altp2m_get_mem_access: - case HVMOP_altp2m_change_gfn: - case HVMOP_altp2m_get_p2m_idx: - case HVMOP_altp2m_set_visibility: - break; - - default: - return -EOPNOTSUPP; - } - - d =3D rcu_lock_domain_by_any_id(a.domain); - - if ( d =3D=3D NULL ) - return -ESRCH; - - if ( !is_hvm_domain(d) ) - { - rc =3D -EOPNOTSUPP; - goto out; - } - - if ( (a.cmd !=3D HVMOP_altp2m_get_domain_state) && - (a.cmd !=3D HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) - { - rc =3D -EOPNOTSUPP; - goto out; - } - - mode =3D d->arch.hvm.params[HVM_PARAM_ALTP2M]; - - if ( XEN_ALTP2M_disabled =3D=3D mode ) - { - rc =3D -EINVAL; - goto out; - } - - if ( d->nr_altp2m =3D=3D 0 ) - { - rc =3D -EOPNOTSUPP; - goto out; - } - - if ( (rc =3D xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) - goto out; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - a.u.domain_state.state =3D altp2m_active(d); - rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_set_domain_state: - { - struct vcpu *v; - bool ostate; - - if ( nestedhvm_enabled(d) ) - { - rc =3D -EINVAL; - break; - } - - rc =3D domain_pause_except_self(d); - if ( rc ) - break; - - ostate =3D d->altp2m_active; - d->altp2m_active =3D !!a.u.domain_state.state; - - /* If the alternate p2m state has changed, handle appropriately */ - if ( d->altp2m_active !=3D ostate && - (ostate || !(rc =3D altp2m_init_by_id(d, 0))) ) - { - for_each_vcpu( d, v ) - { - if ( !ostate ) - altp2m_vcpu_initialise(v); - else - altp2m_vcpu_destroy(v); - } - - if ( ostate ) - altp2m_flush(d); - } - else if ( rc ) - d->altp2m_active =3D false; - - domain_unpause_except_self(d); - break; - } - - case HVMOP_altp2m_vcpu_enable_notify: - { - struct vcpu *v; - - if ( a.u.enable_notify.pad || - a.u.enable_notify.vcpu_id >=3D d->max_vcpus ) - { - rc =3D -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc =3D -EOPNOTSUPP; - break; - } - - v =3D d->vcpu[a.u.enable_notify.vcpu_id]; - - rc =3D altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); - break; - } - - case HVMOP_altp2m_vcpu_disable_notify: - { - struct vcpu *v; - - if ( a.u.disable_notify.vcpu_id >=3D d->max_vcpus ) - { - rc =3D -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc =3D -EOPNOTSUPP; - break; - } - - v =3D d->vcpu[a.u.enable_notify.vcpu_id]; - - altp2m_vcpu_disable_ve(v); - break; - } - - case HVMOP_altp2m_create_p2m: - rc =3D altp2m_init_next_available(d, &a.u.view.view, - a.u.view.hvmmem_default_access); - if ( !rc ) - rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_destroy_p2m: - rc =3D altp2m_destroy_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_switch_p2m: - rc =3D altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_set_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc =3D -EINVAL; - else - { - gfn_t gfn =3D _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx =3D a.u.suppress_ve.view; - bool suppress_ve =3D a.u.suppress_ve.suppress_ve; - - rc =3D p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); - } - break; - - case HVMOP_altp2m_set_suppress_ve_multi: - { - uint64_t max_phys_addr =3D (1UL << d->arch.cpuid->extd.maxphysaddr= ) - 1; - - a.u.suppress_ve_multi.last_gfn =3D min(a.u.suppress_ve_multi.last_= gfn, - max_phys_addr); - - if ( a.u.suppress_ve_multi.pad1 || - a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_= gfn ) - rc =3D -EINVAL; - else - { - rc =3D p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); - if ( (!rc || rc =3D=3D -ERESTART) && __copy_to_guest(arg, &a, = 1) ) - rc =3D -EFAULT; - } - break; - } - - case HVMOP_altp2m_get_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc =3D -EINVAL; - else - { - gfn_t gfn =3D _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx =3D a.u.suppress_ve.view; - bool suppress_ve; - - rc =3D p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); - if ( !rc ) - { - a.u.suppress_ve.suppress_ve =3D suppress_ve; - rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_set_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc =3D -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc =3D -EINVAL; - else - rc =3D p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0= , - a.u.mem_access.access, - a.u.mem_access.view); - break; - - case HVMOP_altp2m_set_mem_access_multi: - if ( !vm_event_is_enabled(current) ) - { - rc =3D -EOPNOTSUPP; - break; - } - - if ( a.u.set_mem_access_multi.pad || - a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr= ) - { - rc =3D -EINVAL; - break; - } - - /* - * Unlike XENMEM_access_op_set_access_multi, we don't need any bit= s of - * the 'continuation' counter to be zero (to stash a command in). - * However, 0x40 is a good 'stride' to make sure that we make - * a reasonable amount of forward progress before yielding, - * so use a mask of 0x3F here. - */ - rc =3D p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_li= st, - a.u.set_mem_access_multi.access_list= , - a.u.set_mem_access_multi.nr, - a.u.set_mem_access_multi.opaque, - 0x3F, - a.u.set_mem_access_multi.view); - if ( rc > 0 ) - { - a.u.set_mem_access_multi.opaque =3D rc; - rc =3D -ERESTART; - if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp= 2m_op_t), - &a, u.set_mem_access_multi.opaque) = ) - rc =3D -EFAULT; - } - break; - - case HVMOP_altp2m_get_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc =3D -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc =3D -EINVAL; - else - { - xenmem_access_t access; - - rc =3D p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access= , - a.u.mem_access.view); - if ( !rc ) - { - a.u.mem_access.access =3D access; - rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_change_gfn: - if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) - rc =3D -EINVAL; - else - rc =3D altp2m_change_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); - break; - - case HVMOP_altp2m_get_p2m_idx: - { - struct vcpu *v; - - if ( !altp2m_active(d) ) - { - rc =3D -EOPNOTSUPP; - break; - } - - if ( (v =3D domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) =3D=3D N= ULL ) - { - rc =3D -EINVAL; - break; - } - - a.u.get_vcpu_p2m_idx.altp2m_idx =3D altp2m_vcpu_idx(v); - rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - } - - case HVMOP_altp2m_set_visibility: - { - unsigned int idx =3D a.u.set_visibility.altp2m_idx; - - if ( a.u.set_visibility.pad ) - rc =3D -EINVAL; - else if ( !altp2m_active(d) ) - rc =3D -EOPNOTSUPP; - else - rc =3D altp2m_set_view_visibility(d, idx, a.u.set_visibility.v= isible); - break; - } - - default: - ASSERT_UNREACHABLE(); - rc =3D -EOPNOTSUPP; - break; - } - - out: - rcu_unlock_domain(d); - - return rc; -#else /* !CONFIG_ALTP2M */ - return -EOPNOTSUPP; -#endif /* CONFIG_ALTP2M */ -} - DEFINE_XEN_GUEST_HANDLE(compat_hvm_altp2m_op_t); =20 /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 1a4e102324d4..a43b3a3e34b3 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -1,5 +1,418 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include + +#include + +#include + +#include + +#ifdef CONFIG_X86 +#include +/* + * altp2m operations are envisioned as being used in several different + * modes: + * + * - external: All control and decisions are made by an external agent + * running domain 0. + * + * - internal: altp2m operations are used exclusively by an in-guest + * agent to protect itself from the guest kernel and in-guest + * attackers. + * + * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, + * but makes requests of an agent running outside the domain for + * bigger changes (such as modifying altp2m entires). + * + * This corresponds to the three values for HVM_PARAM_ALTP2M + * (external, mixed, limited). All three models have advantages and + * disadvantages. + * + * Normally hypercalls made by a program in domain 0 in order to + * control a guest would be DOMCTLs rather than HVMOPs. But in order + * to properly enable the 'internal' use case, as well as to avoid + * fragmentation, all altp2m subops should come under this single + * HVMOP. + * + * Note that 'internal' mode (HVM_PARAM_ALTP2M =3D=3D XEN_ALTP2M_mixed) + * has not been evaluated for safety from a security perspective. + * Before using this mode in a security-critical environment, each + * subop should be evaluated for safety, with unsafe subops + * blacklisted in xsm_hvm_altp2mhvm_op(). + */ +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + struct xen_hvm_altp2m_op a; + struct domain *d =3D NULL; + int rc =3D 0; + uint64_t mode; + + if ( !altp2m_supported() ) + return -EOPNOTSUPP; + + if ( copy_from_guest(&a, arg, 1) ) + return -EFAULT; + + if ( a.pad1 || a.pad2 || + (a.version !=3D HVMOP_ALTP2M_INTERFACE_VERSION) ) + return -EINVAL; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + case HVMOP_altp2m_set_domain_state: + case HVMOP_altp2m_vcpu_enable_notify: + case HVMOP_altp2m_vcpu_disable_notify: + case HVMOP_altp2m_create_p2m: + case HVMOP_altp2m_destroy_p2m: + case HVMOP_altp2m_switch_p2m: + case HVMOP_altp2m_set_suppress_ve: + case HVMOP_altp2m_set_suppress_ve_multi: + case HVMOP_altp2m_get_suppress_ve: + case HVMOP_altp2m_set_mem_access: + case HVMOP_altp2m_set_mem_access_multi: + case HVMOP_altp2m_get_mem_access: + case HVMOP_altp2m_change_gfn: + case HVMOP_altp2m_get_p2m_idx: + case HVMOP_altp2m_set_visibility: + break; + + default: + return -EOPNOTSUPP; + } + + d =3D rcu_lock_domain_by_any_id(a.domain); + + if ( d =3D=3D NULL ) + return -ESRCH; + + if ( !is_hvm_domain(d) ) + { + rc =3D -EOPNOTSUPP; + goto out; + } + + if ( (a.cmd !=3D HVMOP_altp2m_get_domain_state) && + (a.cmd !=3D HVMOP_altp2m_set_domain_state) && + !d->altp2m_active ) + { + rc =3D -EOPNOTSUPP; + goto out; + } + + mode =3D d->arch.hvm.params[HVM_PARAM_ALTP2M]; + + if ( XEN_ALTP2M_disabled =3D=3D mode ) + { + rc =3D -EINVAL; + goto out; + } + + if ( d->nr_altp2m =3D=3D 0 ) + { + rc =3D -EOPNOTSUPP; + goto out; + } + + if ( (rc =3D xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) + goto out; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + a.u.domain_state.state =3D altp2m_active(d); + rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_set_domain_state: + { + struct vcpu *v; + bool ostate; + + if ( nestedhvm_enabled(d) ) + { + rc =3D -EINVAL; + break; + } + + rc =3D domain_pause_except_self(d); + if ( rc ) + break; + + ostate =3D d->altp2m_active; + d->altp2m_active =3D !!a.u.domain_state.state; + + /* If the alternate p2m state has changed, handle appropriately */ + if ( d->altp2m_active !=3D ostate && + (ostate || !(rc =3D altp2m_init_by_id(d, 0))) ) + { + for_each_vcpu( d, v ) + { + if ( !ostate ) + altp2m_vcpu_initialise(v); + else + altp2m_vcpu_destroy(v); + } + + if ( ostate ) + altp2m_flush(d); + } + else if ( rc ) + d->altp2m_active =3D false; + + domain_unpause_except_self(d); + break; + } + + case HVMOP_altp2m_vcpu_enable_notify: + { + struct vcpu *v; + + if ( a.u.enable_notify.pad || + a.u.enable_notify.vcpu_id >=3D d->max_vcpus ) + { + rc =3D -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc =3D -EOPNOTSUPP; + break; + } + + v =3D d->vcpu[a.u.enable_notify.vcpu_id]; + + rc =3D altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); + break; + } + + case HVMOP_altp2m_vcpu_disable_notify: + { + struct vcpu *v; + + if ( a.u.disable_notify.vcpu_id >=3D d->max_vcpus ) + { + rc =3D -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc =3D -EOPNOTSUPP; + break; + } + + v =3D d->vcpu[a.u.enable_notify.vcpu_id]; + + altp2m_vcpu_disable_ve(v); + break; + } + + case HVMOP_altp2m_create_p2m: + rc =3D altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) + rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_destroy_p2m: + rc =3D altp2m_destroy_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_switch_p2m: + rc =3D altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_set_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc =3D -EINVAL; + else + { + gfn_t gfn =3D _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx =3D a.u.suppress_ve.view; + bool suppress_ve =3D a.u.suppress_ve.suppress_ve; + + rc =3D p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); + } + break; + + case HVMOP_altp2m_set_suppress_ve_multi: + { + uint64_t max_phys_addr =3D (1UL << d->arch.cpuid->extd.maxphysaddr= ) - 1; + + a.u.suppress_ve_multi.last_gfn =3D min(a.u.suppress_ve_multi.last_= gfn, + max_phys_addr); + + if ( a.u.suppress_ve_multi.pad1 || + a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_= gfn ) + rc =3D -EINVAL; + else + { + rc =3D p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); + if ( (!rc || rc =3D=3D -ERESTART) && __copy_to_guest(arg, &a, = 1) ) + rc =3D -EFAULT; + } + break; + } + + case HVMOP_altp2m_get_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc =3D -EINVAL; + else + { + gfn_t gfn =3D _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx =3D a.u.suppress_ve.view; + bool suppress_ve; + + rc =3D p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); + if ( !rc ) + { + a.u.suppress_ve.suppress_ve =3D suppress_ve; + rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_set_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc =3D -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc =3D -EINVAL; + else + rc =3D p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0= , + a.u.mem_access.access, + a.u.mem_access.view); + break; + + case HVMOP_altp2m_set_mem_access_multi: + if ( !vm_event_is_enabled(current) ) + { + rc =3D -EOPNOTSUPP; + break; + } + + if ( a.u.set_mem_access_multi.pad || + a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr= ) + { + rc =3D -EINVAL; + break; + } + + /* + * Unlike XENMEM_access_op_set_access_multi, we don't need any bit= s of + * the 'continuation' counter to be zero (to stash a command in). + * However, 0x40 is a good 'stride' to make sure that we make + * a reasonable amount of forward progress before yielding, + * so use a mask of 0x3F here. + */ + rc =3D p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_li= st, + a.u.set_mem_access_multi.access_list= , + a.u.set_mem_access_multi.nr, + a.u.set_mem_access_multi.opaque, + 0x3F, + a.u.set_mem_access_multi.view); + if ( rc > 0 ) + { + a.u.set_mem_access_multi.opaque =3D rc; + rc =3D -ERESTART; + if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp= 2m_op_t), + &a, u.set_mem_access_multi.opaque) = ) + rc =3D -EFAULT; + } + break; + + case HVMOP_altp2m_get_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc =3D -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc =3D -EINVAL; + else + { + xenmem_access_t access; + + rc =3D p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access= , + a.u.mem_access.view); + if ( !rc ) + { + a.u.mem_access.access =3D access; + rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_change_gfn: + if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) + rc =3D -EINVAL; + else + rc =3D altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); + break; + + case HVMOP_altp2m_get_p2m_idx: + { + struct vcpu *v; + + if ( !altp2m_active(d) ) + { + rc =3D -EOPNOTSUPP; + break; + } + + if ( (v =3D domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) =3D=3D N= ULL ) + { + rc =3D -EINVAL; + break; + } + + a.u.get_vcpu_p2m_idx.altp2m_idx =3D altp2m_vcpu_idx(v); + rc =3D __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + } + + case HVMOP_altp2m_set_visibility: + { + unsigned int idx =3D a.u.set_visibility.altp2m_idx; + + if ( a.u.set_visibility.pad ) + rc =3D -EINVAL; + else if ( !altp2m_active(d) ) + rc =3D -EOPNOTSUPP; + else + rc =3D altp2m_set_view_visibility(d, idx, a.u.set_visibility.v= isible); + break; + } + + default: + ASSERT_UNREACHABLE(); + rc =3D -EOPNOTSUPP; + break; + } + + out: + rcu_unlock_domain(d); + + return rc; +} +#else +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} +#endif =20 /* * Local variables: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index b3b21124dd7e..be627152668a 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,8 +2,12 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ =20 +#include +#include #include =20 +#include + #ifdef CONFIG_ALTP2M =20 /* Alternate p2m HVM on/off per domain */ @@ -12,6 +16,8 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } =20 +int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); + #else /* CONFIG_ALTP2M */ =20 static inline bool altp2m_active(const struct domain *d) @@ -19,6 +25,11 @@ static inline bool altp2m_active(const struct domain *d) return false; } =20 +static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_ALTP2M */ =20 #endif /* __XEN_ALTP2M_H__ */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286464.1567511 (Exim 4.92) (envelope-from ) id 1wEvBH-0001l3-Kj; Mon, 20 Apr 2026 20:25:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286464.1567511; Mon, 20 Apr 2026 20:25:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBH-0001kw-Hm; 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Mon, 20 Apr 2026 19:50:46 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=U7Aj0TmlQMo2OaiARr833Wx8B5UJDkYDILENNQJui75UvlKQU6oEmzSiJ0BjFolip1mlZN84vjT4JUXT3hFYofgGxRdHZabD55DYLpNNaU9qn5va7KJ+gXZsQ5CkYM12zHkn7pmU/DGMCJzbP71DPD1zU7eZqQfq7fJvjOow0VI1ZdT3MKcEpN25tTXVyL2jeLQSxEgcj/27rVu3kmzo8J2dIfDBguYa37GP47bnO4Q6u7aKJX6gJq7ycGXlBbp33jEEjrHIbSvVsKjKwyJTwkSmYl0/ACeYhXiZpjdBeUIEc0N7J0pYgJLC6a6le5OeDibjUnB2qPRAgvdpvuCgGQ==; s=purelymail1; d=purelymail.com; v=1; bh=F9DP5LK5B/VL9yfk52EOu4d/RW0pXvXOczcYQ78lIz8=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 01/43] altp2m: Add template common altp2m.c/altp2m.h Date: Mon, 20 Apr 2026 15:50:00 -0400 Message-Id: <20260420195042.207624-2-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-720697/1776714648-81971161-87202937/0/0 X-purgate-type: clean X-purgate-size: 1865 From: Rose Spangler This commit adds an empty common altp2m.c and altp2m.h file to be added to in later commits. Creating a commit with just the empty file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 1/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/common/Makefile | 1 + xen/common/altp2m.c | 12 ++++++++++++ xen/include/xen/altp2m.h | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h diff --git a/xen/common/Makefile b/xen/common/Makefile index 6018e256147f..dbe0094006df 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ALTP2M) +=3D altp2m.o obj-$(CONFIG_ARGO) +=3D argo.o obj-y +=3D bitmap.o obj-bin-$(CONFIG_SELF_TESTS) +=3D bitops.init.o diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c new file mode 100644 index 000000000000..1a4e102324d4 --- /dev/null +++ b/xen/common/altp2m.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h new file mode 100644 index 000000000000..520328fd3fa8 --- /dev/null +++ b/xen/include/xen/altp2m.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __XEN_ALTP2M_H__ +#define __XEN_ALTP2M_H__ + +#endif /* __XEN_ALTP2M_H__ */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286468.1567521 (Exim 4.92) (envelope-from ) id 1wEvBI-0001qJ-6U; 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Mon, 20 Apr 2026 21:50:50 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e68399-672d-0a2a45030019-22cac1c5e3bc-3 for ; Mon, 20 Apr 2026 21:50:50 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:47 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=MmOQ5QAe41G+mdw+wA2MuMRrWAiWf7RNONJMHOx4I3iOvgsHJSBFN2fUuAoO9ibEODwfLeXYVGNQ1bvKt88DLz3cGN1qn6xc/h1RnWIUeTJS9DnkKxWWxxOW3B3bZdMF1bGVWReGOm+pesXQvbrD3JF3hBWz7HNM1KkvTnAVVGLVPod8A5/NquOFR38ciqu9o+0qc7LPqUNNm82mtfFbczL/d8eaJDLTe65v4uLO8I0Zqqi9XygoJxzjruV4PsBOy9WjeQRlD8n5THzERfkW8wIyWM0F7N3D8BlJ4rb+gyL7OnmFbGs7RBw40q7fzjITNVbwY8WxCv/aQgykXcBPNA==; s=purelymail1; d=purelymail.com; v=1; bh=2PvdWtImHt0iTtxQjPZi9MEx0U+dnWA9pNgCxK8uhgE=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , Tamas K Lengyel Subject: [RFC PATCH v6 02/43] altp2m: Move altp2m_active to common domain struct Date: Mon, 20 Apr 2026 15:50:01 -0400 Message-Id: <20260420195042.207624-3-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-33051d/1776714650-A0975938-808CC524/0/0 X-purgate-type: clean X-purgate-size: 10782 From: Rose Spangler This commit moves altp2m_active from arch_domain on x86 to the common domain struct. Similarly to nr_altp2m, this is not an arch-specific value. Moving it to common code allows the common altp2m routines introduced later in this patch series to operate on altp2m_active without needing an altp2m_active member on arch_domain for each architecture supporting altp2m. This is commit 2/8 of the preparation phase. This commit is a refactor, and no change in functionality is intended. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 11 ++++++----- xen/arch/x86/hvm/monitor.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 ----------- xen/arch/x86/include/asm/domain.h | 2 -- xen/arch/x86/mm/altp2m.c | 1 + xen/arch/x86/mm/hap/hap.c | 5 +++-- xen/arch/x86/mm/mem_access.c | 1 + xen/arch/x86/mm/mem_sharing.c | 1 + xen/arch/x86/mm/p2m-ept.c | 1 + xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 1 + xen/common/monitor.c | 1 + xen/include/asm-generic/altp2m.h | 8 -------- xen/include/xen/altp2m.h | 19 +++++++++++++++++++ xen/include/xen/sched.h | 2 ++ 17 files changed, 40 insertions(+), 28 deletions(-) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index f3aae158e9f8..9a9b89a232e6 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -9,6 +9,7 @@ * Keir Fraser */ =20 +#include #include #include #include diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4a81afce02e7..86c12c0d1ef4 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -7,6 +7,7 @@ * Copyright (c) 2008, Citrix Systems, Inc. */ =20 +#include #include #include #include @@ -4612,7 +4613,7 @@ static int do_altp2m_op( =20 if ( (a.cmd !=3D HVMOP_altp2m_get_domain_state) && (a.cmd !=3D HVMOP_altp2m_set_domain_state) && - !d->arch.altp2m_active ) + !d->altp2m_active ) { rc =3D -EOPNOTSUPP; goto out; @@ -4657,11 +4658,11 @@ static int do_altp2m_op( if ( rc ) break; =20 - ostate =3D d->arch.altp2m_active; - d->arch.altp2m_active =3D !!a.u.domain_state.state; + ostate =3D d->altp2m_active; + d->altp2m_active =3D !!a.u.domain_state.state; =20 /* If the alternate p2m state has changed, handle appropriately */ - if ( d->arch.altp2m_active !=3D ostate && + if ( d->altp2m_active !=3D ostate && (ostate || !(rc =3D p2m_init_altp2m_by_id(d, 0))) ) { for_each_vcpu( d, v ) @@ -4676,7 +4677,7 @@ static int do_altp2m_op( p2m_flush_altp2m(d); } else if ( rc ) - d->arch.altp2m_active =3D false; + d->altp2m_active =3D false; =20 domain_unpause_except_self(d); break; diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index d22a2e464460..84c1c2234ca9 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -22,6 +22,7 @@ * this program; If not, see . */ =20 +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 269ca5643346..ff895f7f9437 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4,6 +4,7 @@ * Copyright (c) 2004, Intel Corporation. */ =20 +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 9c1ac3cc2676..ad5ded833a75 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,12 +28,6 @@ static inline bool altp2m_is_eptp_valid(const struct dom= ain *d, mfn_x(INVALID_MFN); } =20 -/* Alternate p2m HVM on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - return d->arch.altp2m_active; -} - static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -64,11 +58,6 @@ static inline bool altp2m_is_eptp_valid(const struct dom= ain *d, return false; } =20 -static inline bool altp2m_active(const struct domain *d) -{ - return false; -} - /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index 385a6666dafa..0cf0c0d92087 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,8 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; =20 #ifdef CONFIG_ALTP2M - /* altp2m: allow multiple copies of host p2m */ - bool altp2m_active; struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 0bc9b9ad2f52..08db8f37c1b1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mm-locks.h" diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5d3..3d563b3bc2d1 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -7,6 +7,7 @@ * Parts of this code are Copyright (c) 2007 by XenSource Inc. */ =20 +#include #include #include #include @@ -528,7 +529,7 @@ int hap_enable(struct domain *d, u32 mode) goto out; } =20 - d->arch.altp2m_active =3D false; + d->altp2m_active =3D false; } #endif /* CONFIG_ALTP2M */ =20 @@ -595,7 +596,7 @@ void hap_teardown(struct domain *d, bool *preempted) for_each_vcpu ( d, v ) altp2m_vcpu_disable_ve(v); =20 - d->arch.altp2m_active =3D false; + d->altp2m_active =3D false; =20 FREE_XENHEAP_PAGE(d->arch.altp2m_eptp); FREE_XENHEAP_PAGE(d->arch.altp2m_visible_eptp); diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e55e53f44c78..a9d6b081a523 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -9,6 +9,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ =20 +#include #include /* copy_from_guest() */ #include #include diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 5c7a0ff30e8b..8319733b1bb6 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -8,6 +8,7 @@ * Copyright (c) 2009 Citrix Systems, Inc. (Grzegorz Milos) */ =20 +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index dfdbfa0afec8..ed850723f5fd 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -4,6 +4,7 @@ * Copyright (c) 2007, Intel Corporation. */ =20 +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-pt.c b/xen/arch/x86/mm/p2m-pt.c index 5a6ce2f8bc2e..17f38aac14d5 100644 --- a/xen/arch/x86/mm/p2m-pt.c +++ b/xen/arch/x86/mm/p2m-pt.c @@ -12,6 +12,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ =20 +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index fddecdf978ec..41517765c5ec 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ =20 +#include #include #include #include diff --git a/xen/common/monitor.c b/xen/common/monitor.c index d5c9ff1cbf8c..e758a3fea9f1 100644 --- a/xen/common/monitor.c +++ b/xen/common/monitor.c @@ -19,6 +19,7 @@ * License along with this program; If not, see . */ =20 +#include #include #include #include diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/alt= p2m.h index 39865a842ab3..ecee6942f4e8 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -4,16 +4,8 @@ =20 #include =20 -struct domain; struct vcpu; =20 -/* Alternate p2m on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - /* Not implemented on GENERIC. */ - return false; -} - /* Alternate p2m VCPU */ static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 520328fd3fa8..b3b21124dd7e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,4 +2,23 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ =20 +#include + +#ifdef CONFIG_ALTP2M + +/* Alternate p2m HVM on/off per domain */ +static inline bool altp2m_active(const struct domain *d) +{ + return d->altp2m_active; +} + +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_active(const struct domain *d) +{ + return false; +} + +#endif /* CONFIG_ALTP2M */ + #endif /* __XEN_ALTP2M_H__ */ diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..458f2f260dd7 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -623,6 +623,8 @@ struct domain } monitor; =20 #ifdef CONFIG_ALTP2M + /* altp2m: allow multiple copies of host p2m */ + bool altp2m_active; unsigned int nr_altp2m; /* Number of altp2m tables. */ #endif =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286471.1567539 (Exim 4.92) (envelope-from ) id 1wEvBJ-0002B1-77; Mon, 20 Apr 2026 20:25:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286471.1567539; Mon, 20 Apr 2026 20:25:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBI-00027C-Tq; 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Mon, 20 Apr 2026 19:50:47 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=B+nYO9KEh9q0WYoB0d58RVBlQDqbuZ0LyKTA/IITuj2TR7ZhTS0wwg5scl5p9rvXSzxa9QEYQD3jbf9n6ecs0f8J5nBFDBkNq8/8U/8356GgJuD5U4N8/8EetghCFWCETsI2KOo+YgBwGMVUTOY+xBdu/p88u7/U3jYkpirPGNwULO8o1nU5YgKPdbkKfU4VxswtMItj5Bna6L3ePWAvUpOTpPvT0hJ14HL0bqUMDdSCfHup+/ZEqPMQxpigOyxTXzqDmQygBpDX1DQQtlwKiREzqKwR8A/QXUHswtjLepy6ymEDw+NesNGQGNq1F8iPAxknJGZ+LvbbBqMkTPmSTw==; s=purelymail1; d=purelymail.com; v=1; bh=6QrBhjpqDTM5a7ZOSMJOwL5c5AsZbPxqt9UWvAKgsrc=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , Tamas K Lengyel Subject: [RFC PATCH v6 03/43] altp2m: Move altp2m_p2m to common domain struct Date: Mon, 20 Apr 2026 15:50:02 -0400 Message-Id: <20260420195042.207624-4-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-16d1c6/1776714651-52B75D75-EC441CBA/0/0 X-purgate-type: clean X-purgate-size: 13719 From: Rose Spangler Similarly to the previous commit, this commit moves altp2m_p2m to the common domain struct. The representation of altp2m views as an array of p2m_domain pointers is the same on x86 and ARM, and it seems that this would be the case for other architectures as well. This commit is a refactor, and no change in functionality is intended. This is commit 3/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/include/asm/domain.h | 1 - xen/arch/x86/include/asm/p2m.h | 4 ++-- xen/arch/x86/mm/altp2m.c | 28 ++++++++++++++-------------- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/mem_access.c | 8 ++++---- xen/arch/x86/mm/mem_sharing.c | 2 +- xen/arch/x86/mm/p2m-ept.c | 6 +++--- xen/arch/x86/mm/p2m.c | 8 ++++---- xen/include/xen/sched.h | 1 + 10 files changed, 33 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index ff895f7f9437..0909929c00e0 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -5004,7 +5004,7 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_u= ser_regs *regs) if ( currd->arch.altp2m_eptp[i] =3D=3D mfn_x(INVALID_MFN) = ) continue; =20 - ept =3D &currd->arch.altp2m_p2m[i]->ept; + ept =3D &currd->altp2m_p2m[i]->ept; if ( cpumask_test_cpu(cpu, ept->invalidate) ) { cpumask_clear_cpu(cpu, ept->invalidate); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index 0cf0c0d92087..f8038087e612 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,7 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; =20 #ifdef CONFIG_ALTP2M - struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; uint64_t *altp2m_visible_eptp; diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.= h index 3a5a5fd43c2a..ec871717a9e4 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -901,7 +901,7 @@ static inline struct p2m_domain *p2m_get_altp2m(struct = vcpu *v) =20 BUG_ON(index >=3D v->domain->nr_altp2m); =20 - return v->domain->arch.altp2m_p2m[index]; + return v->domain->altp2m_p2m[index]; } =20 /* set current alternate p2m table */ @@ -919,7 +919,7 @@ static inline bool p2m_set_altp2m(struct vcpu *v, unsig= ned int idx) atomic_dec(&orig->active_vcpus); =20 vcpu_altp2m(v).p2midx =3D idx; - atomic_inc(&v->domain->arch.altp2m_p2m[idx]->active_vcpus); + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); =20 return true; } diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 08db8f37c1b1..8dd3c0f96be0 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -130,14 +130,14 @@ int p2m_init_altp2m(struct domain *d) struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); =20 mm_lock_init(&d->arch.altp2m_list_lock); - d->arch.altp2m_p2m =3D xvzalloc_array(struct p2m_domain *, d->nr_altp2= m); + d->altp2m_p2m =3D xvzalloc_array(struct p2m_domain *, d->nr_altp2m); =20 - if ( !d->arch.altp2m_p2m ) + if ( !d->altp2m_p2m ) return -ENOMEM; =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - d->arch.altp2m_p2m[i] =3D p2m =3D p2m_init_one(d); + d->altp2m_p2m[i] =3D p2m =3D p2m_init_one(d); if ( p2m =3D=3D NULL ) { p2m_teardown_altp2m(d); @@ -158,14 +158,14 @@ void p2m_teardown_altp2m(struct domain *d) =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - if ( !d->arch.altp2m_p2m[i] ) + if ( !d->altp2m_p2m[i] ) continue; - p2m =3D d->arch.altp2m_p2m[i]; - d->arch.altp2m_p2m[i] =3D NULL; + p2m =3D d->altp2m_p2m[i]; + d->altp2m_p2m[i] =3D NULL; p2m_free_one(p2m); } =20 - XVFREE(d->arch.altp2m_p2m); + XVFREE(d->altp2m_p2m); } =20 int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *= mfn, @@ -325,7 +325,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned= int idx, struct p2m_domain *p2m; =20 ASSERT(idx < d->nr_altp2m); - p2m =3D d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m =3D d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; =20 p2m_lock(p2m); =20 @@ -368,7 +368,7 @@ static int p2m_activate_altp2m(struct domain *d, unsign= ed int idx, =20 ASSERT(idx < d->nr_altp2m); =20 - p2m =3D d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m =3D d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; hostp2m =3D p2m_get_hostp2m(d); =20 p2m_lock(p2m); @@ -468,7 +468,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned= int idx) if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] !=3D mfn_x(INVALID_MFN) ) { - p2m =3D d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m =3D d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; =20 if ( !_atomic_read(p2m->active_vcpus) ) { @@ -532,7 +532,7 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned in= t idx, return rc; =20 hp2m =3D p2m_get_hostp2m(d); - ap2m =3D d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + ap2m =3D d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; =20 p2m_lock(hp2m); p2m_lock(ap2m); @@ -596,7 +596,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t= gfn, if ( d->arch.altp2m_eptp[i] =3D=3D mfn_x(INVALID_MFN) ) continue; =20 - p2m =3D d->arch.altp2m_p2m[i]; + p2m =3D d->altp2m_p2m[i]; =20 /* Check for a dropped page that may impact this altp2m */ if ( mfn_eq(mfn, INVALID_MFN) && @@ -679,7 +679,7 @@ int p2m_set_suppress_ve_multi(struct domain *d, return -EINVAL; =20 p2m =3D ap2m =3D - d->arch.altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)= ]; + d->altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)]; } =20 p2m_lock(host_p2m); @@ -746,7 +746,7 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bo= ol *suppress_ve, return -EINVAL; =20 p2m =3D ap2m =3D - d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m= )]; + d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } else p2m =3D host_p2m; diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 3d563b3bc2d1..6918a00a2a25 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -524,7 +524,7 @@ int hap_enable(struct domain *d, u32 mode) =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - rv =3D p2m_alloc_table(d->arch.altp2m_p2m[i]); + rv =3D p2m_alloc_table(d->altp2m_p2m[i]); if ( rv !=3D 0 ) goto out; } @@ -548,7 +548,7 @@ void hap_final_teardown(struct domain *d) #ifdef CONFIG_ALTP2M if ( hvm_altp2m_supported() ) for ( i =3D 0; i < d->nr_altp2m; i++ ) - p2m_teardown(d->arch.altp2m_p2m[i], true, NULL); + p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif =20 /* Destroy nestedp2m's first */ @@ -603,7 +603,7 @@ void hap_teardown(struct domain *d, bool *preempted) =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - p2m_teardown(d->arch.altp2m_p2m[i], false, preempted); + p2m_teardown(d->altp2m_p2m[i], false, preempted); if ( preempted && *preempted ) return; } diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index a9d6b081a523..e5548e64d8d0 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -319,7 +319,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, ui= nt32_t nr, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; =20 - ap2m =3D d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_a= ltp2m)]; + ap2m =3D d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m= )]; } #endif =20 @@ -375,7 +375,7 @@ long p2m_set_mem_access_multi(struct domain *d, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; =20 - ap2m =3D d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_a= ltp2m)]; + ap2m =3D d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m= )]; } #endif =20 @@ -438,7 +438,7 @@ int p2m_get_mem_access(struct domain *d, gfn_t gfn, xen= mem_access_t *access, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; =20 - p2m =3D d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_al= tp2m)]; + p2m =3D d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)= ]; } #endif =20 @@ -457,7 +457,7 @@ void arch_p2m_set_access_required(struct domain *d, boo= l access_required) unsigned int i; for ( i =3D 0; i < d->nr_altp2m; i++ ) { - struct p2m_domain *p2m =3D d->arch.altp2m_p2m[i]; + struct p2m_domain *p2m =3D d->altp2m_p2m[i]; =20 if ( p2m ) p2m->access_required =3D access_required; diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 8319733b1bb6..b7d8fb9ad1aa 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -919,7 +919,7 @@ static int nominate_page(struct domain *d, gfn_t gfn, =20 for ( i =3D 0; i < d->nr_altp2m; i++ ) { - ap2m =3D d->arch.altp2m_p2m[i]; + ap2m =3D d->altp2m_p2m[i]; if ( !ap2m ) continue; =20 diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ed850723f5fd..ddb4c7606be1 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -1311,7 +1311,7 @@ static void ept_set_ad_sync(struct domain *d, bool va= lue) if ( d->arch.altp2m_eptp[i] =3D=3D mfn_x(INVALID_MFN) ) continue; =20 - p2m =3D d->arch.altp2m_p2m[i]; + p2m =3D d->altp2m_p2m[i]; =20 p2m_lock(p2m); p2m->ept.ad =3D value; @@ -1579,7 +1579,7 @@ void __init setup_ept_dump(void) void p2m_init_altp2m_ept(struct domain *d, unsigned int i) { struct p2m_domain *p2m =3D - d->arch.altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; struct p2m_domain *hostp2m =3D p2m_get_hostp2m(d); struct ept_data *ept; =20 @@ -1603,7 +1603,7 @@ unsigned int p2m_find_altp2m_by_eptp(struct domain *d= , uint64_t eptp) if ( d->arch.altp2m_eptp[i] =3D=3D mfn_x(INVALID_MFN) ) continue; =20 - p2m =3D d->arch.altp2m_p2m[i]; + p2m =3D d->altp2m_p2m[i]; ept =3D &p2m->ept; =20 if ( eptp =3D=3D ept->eptp ) diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index 41517765c5ec..5bd426296f20 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -111,7 +111,7 @@ void p2m_change_entry_type_global(struct domain *d, { if ( d->arch.altp2m_eptp[i] !=3D mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m =3D d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m =3D d->altp2m_p2m[i]; =20 p2m_lock(altp2m); change_entry_type_global(altp2m, ot, nt); @@ -157,7 +157,7 @@ bool p2m_memory_type_changed(struct domain *d) { if ( d->arch.altp2m_eptp[i] !=3D mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m =3D d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m =3D d->altp2m_p2m[i]; =20 p2m_lock(altp2m); _memory_type_changed(altp2m); @@ -955,7 +955,7 @@ void p2m_change_type_range(struct domain *d, { if ( d->arch.altp2m_eptp[i] !=3D mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m =3D d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m =3D d->altp2m_p2m[i]; =20 p2m_lock(altp2m); change_type_range(altp2m, start, end, ot, nt); @@ -1031,7 +1031,7 @@ int p2m_finish_type_change(struct domain *d, { if ( d->arch.altp2m_eptp[i] !=3D mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m =3D d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m =3D d->altp2m_p2m[i]; =20 p2m_lock(altp2m); rc =3D finish_type_change(altp2m, first_gfn, max_nr); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 458f2f260dd7..5d8ba2d2ab19 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -626,6 +626,7 @@ struct domain /* altp2m: allow multiple copies of host p2m */ bool altp2m_active; unsigned int nr_altp2m; /* Number of altp2m tables. */ + struct p2m_domain **altp2m_p2m; #endif =20 #ifdef CONFIG_VMTRACE --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286483.1567608 (Exim 4.92) (envelope-from ) id 1wEvBN-0003fY-9p; Mon, 20 Apr 2026 20:25:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286483.1567608; Mon, 20 Apr 2026 20:25:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBM-0003bJ-QU; Mon, 20 Apr 2026 20:25:24 +0000 Received: by outflank-mailman (input) for mailman id 1286483; Mon, 20 Apr 2026 19:50:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEue2-0006Iv-8S for xen-devel@lists.xenproject.org; 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dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=L+19iyv+EUeaGWGFsg/BWJiBVxeE/no+P5K1P6qeD1YfVN0hoZLm9oaLIw6VWXRXAUpq/+f4X1tX/9pPrs/LCvAUWLJuWJpuofTpMMIi2KWtHiEIbwiYy618cbKCfOeMiNBqbOqmV433K3tYmJWbz4SrMySSCYWLfIuOMMgZxx752i4ZdVSJYfbUg47mkpzSXf9MyXxp13UwHeBMgqX4SuuBoLcWvi/Lkf0R8q9R2YzRvM+T6wLpmvCv3IjHXGidnHQgYJx83PsQxhjadG0baQ0Hw0UonKx/H7Fxo+Z4ABSs4r9bY+xpYAgOWWoRGPflw+8rsvXOnBqHM9R30lo8IA==; s=purelymail1; d=purelymail.com; v=1; bh=UaefyhWKaHg0ZXhca3L3b/zEeIpQmNz0OQTE/cAPZp8=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 12/43] x86/p2m: Move p2m_{init,free}_one declarations to arch header Date: Mon, 20 Apr 2026 15:50:11 -0400 Message-Id: <20260420195042.207624-13-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-4011c0/1776714657-CF3738B7-D404BC4A/0/0 X-purgate-type: clean X-purgate-size: 1681 From: Rose Spangler This commit moves the p2m_init_one and p2m_free_one declarations from the x86-only p2m.h header file to the asm/p2m.h header. This makes it possible to use these functions in the common altp2m init/teardown routines. This is commit 1/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/p2m.h | 3 +++ xen/arch/x86/mm/p2m.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.= h index 5110b3e77807..ce8eeb751ee9 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -592,6 +592,9 @@ int p2m_alloc_table(struct p2m_domain *p2m); void p2m_teardown(struct p2m_domain *p2m, bool remove_root, bool *preempte= d); void p2m_final_teardown(struct domain *d); =20 +struct p2m_domain *p2m_init_one(struct domain *d); +void p2m_free_one(struct p2m_domain *p2m); + /* Add/remove a page to/from a domain's p2m table. */ int p2m_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, unsigned int page_order, p2m_type_t t); diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 64218878067e..be8ed85c2aba 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -6,9 +6,6 @@ #ifndef __ARCH_MM_P2M_H__ #define __ARCH_MM_P2M_H__ =20 -struct p2m_domain *p2m_init_one(struct domain *d); -void p2m_free_one(struct p2m_domain *p2m); - void p2m_pod_init(struct p2m_domain *p2m); =20 #ifdef CONFIG_HVM --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286470.1567535 (Exim 4.92) (envelope-from ) id 1wEvBI-00023m-Sy; Mon, 20 Apr 2026 20:25:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286470.1567535; Mon, 20 Apr 2026 20:25:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBI-00022Z-Kk; Mon, 20 Apr 2026 20:25:20 +0000 Received: by outflank-mailman (input) for mailman id 1286470; Mon, 20 Apr 2026 19:50:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEudv-0006GM-Os for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:50:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEudv-00EW0U-5e for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:50:51 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6835b-e002-0a2a0a5209dd-0a2a45099984-24 for ; Mon, 20 Apr 2026 21:50:51 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6839a-2497-0a2a45090019-22cac1c5af54-3 for ; Mon, 20 Apr 2026 21:50:51 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:49 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=BUWViz1HX1BBqALyZx+7NkZJniZ89w3OKNPE8ISNw+sIMhTi8LW/OkdsUfen+redgW4BaE1sPJPuSclmSl14wSKVVqUPCUU8AI9UN4wKdJmWsXT7h5W/Aq7reLYLxdlotCQ3QmdRxskqppq7/q718B6v/7s/9SeMOo9J3H7FiiBzbdfdz9rTdqCzzEeTnAiCMzRtJiqk5/m7Yrv6+JlVCa924NwRw93Gq2JLW1eYSaXViKJC17bZtup4P/Yjd1ZslZL5RItn3ekihAk6LiqCIQmQu91pUyOcs/ht6PgYL3m3VECQ2ttJlLQLGsW4uYodXPAuEfG31iik4cC3EqnN/Q==; s=purelymail1; d=purelymail.com; v=1; bh=FUGBLopHINZhG1l1iHXBX4rky0Br+fp5HvqRUDdfpzM=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Aqib Javaid Subject: [RFC PATCH v6 06/43] arm/altp2m: Add template arch-specific altp2m.c/altp2m.h Date: Mon, 20 Apr 2026 15:50:05 -0400 Message-Id: <20260420195042.207624-7-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-bad1c0/1776714651-92D77A53-40B251C1/0/0 X-purgate-type: clean X-purgate-size: 3304 From: Rose Spangler Similarly to the earlier common altp2m.c/altp2m.h commit, this commit adds a template altp2m.c and altp2m.h file for ARM to be added to in later commits. Creating a commit with just the template file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 6/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 16 +++++++++++++ xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 37 +++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 69200b27280d..d995d4ff7aa1 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TEE) +=3D tee/ obj-$(CONFIG_HAS_VPCI) +=3D vpci.o =20 obj-$(CONFIG_HAS_ALTERNATIVE) +=3D alternative.o +obj-$(CONFIG_ALTP2M) +=3D altp2m.o obj-y +=3D cpuerrata.o obj-y +=3D cpufeature.o obj-y +=3D decode.o diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c new file mode 100644 index 000000000000..2bd1ff4df223 --- /dev/null +++ b/xen/arch/arm/altp2m.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.c: Alternate p2m + * + * Copyright (c) 2016 Sergej Proskurin + */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/Makefile b/xen/arch/arm/include/asm/M= akefile index 4565baca6a4d..fef4dd42b6cb 100644 --- a/xen/arch/arm/include/asm/Makefile +++ b/xen/arch/arm/include/asm/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -generic-y +=3D altp2m.h generic-y +=3D device.h generic-y +=3D hardirq.h generic-y +=3D iocap.h diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h new file mode 100644 index 000000000000..ca836bae7330 --- /dev/null +++ b/xen/arch/arm/include/asm/altp2m.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.h: Alternate p2m + * + * Copyright (c) 2014, Intel Corporation. + * Copyright (c) 2016, Sergej Proskurin . + */ + +#ifndef __ASM_ARM_ALTP2M_H +#define __ASM_ARM_ALTP2M_H + +#include + +static inline bool altp2m_supported(void) +{ + /* Not implemented yet */ + return false; +} + +/* Alternate p2m VCPU */ +static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + /* Not implemented yet */ + BUG(); + return 0; +} + +#endif /* __ASM_ARM_ALTP2M_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286477.1567554 (Exim 4.92) (envelope-from ) id 1wEvBJ-0002PY-W3; Mon, 20 Apr 2026 20:25:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286477.1567554; Mon, 20 Apr 2026 20:25:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBJ-0002NW-Js; Mon, 20 Apr 2026 20:25:21 +0000 Received: by outflank-mailman (input) for mailman id 1286477; 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charset=UTF-8 X-purgate-ID: tlsNG-bad1c0/1776714655-93374A53-B98F9258/0/0 X-purgate-type: clean X-purgate-size: 2913 From: Rose Spangler Following the x86 implementation in commit e96831ece819, this commit adds the CONFIG_ALTP2M Kconfig option for ARM. This makes it possible to build Xen without building altp2m code. This commit also implements a stub for p2m_altp2m_check, as some implementation is needed when CONFIG_ALTP2M is enabled. This is due to a call to p2m_altp2m_check in vm_event.c which is gated by CONFIG_ALTP2M. This is commit 7/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Kconfig | 11 +++++++++++ xen/arch/arm/altp2m.c | 9 +++++++++ xen/arch/arm/include/asm/altp2m.h | 18 ++++++++++++++++-- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..fdf0721c3c03 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -98,6 +98,17 @@ config MPU =09 systems supporting EL2. (UNSUPPORTED) endchoice =20 +config ALTP2M +=09bool "Alternate P2M support" if EXPERT +=09depends on MMU +=09default y +=09help +=09 Alternate-p2m allows a guest to manage multiple p2m guest physical +=09 "memory views" (as opposed to a single p2m). +=09 Useful for memory introspection. + +=09 If unsure, stay with defaults. + source "arch/Kconfig" =20 config ACPI diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 2bd1ff4df223..8bd174ea8f37 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -5,6 +5,15 @@ * Copyright (c) 2016 Sergej Proskurin */ =20 +#include + +/* Check to see if vcpu should be switched to a different p2m. */ +void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not yet implemented */ + BUG(); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index ca836bae7330..698c35427e75 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -11,10 +11,12 @@ =20 #include =20 +#ifdef CONFIG_ALTP2M + +/* Hardware always supports altp2m on ARM */ static inline bool altp2m_supported(void) { - /* Not implemented yet */ - return false; + return true; } =20 /* Alternate p2m VCPU */ @@ -25,6 +27,18 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu= *v) return 0; } =20 +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_supported(void) +{ + return false; +} + +/* Only declaration is needed. DCE will optimise it out when linking. */ +uint16_t altp2m_vcpu_idx(const struct vcpu *v); + +#endif /* CONFIG_ALTP2M */ + #endif /* __ASM_ARM_ALTP2M_H */ =20 /* --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286498.1567648 (Exim 4.92) (envelope-from ) id 1wEvBS-0004vD-JK; Mon, 20 Apr 2026 20:25:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286498.1567648; Mon, 20 Apr 2026 20:25:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBQ-0004rZ-Uh; Mon, 20 Apr 2026 20:25:28 +0000 Received: by outflank-mailman (input) for mailman id 1286498; Mon, 20 Apr 2026 19:54:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhC-0006RK-5O for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:54:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhB-008XBJ-IS for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:54:13 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6842b-bab6-0a2a0a5309dd-0a2a4501dfd2-48 for ; Mon, 20 Apr 2026 21:54:13 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683b0-c1f2-0a2a45010019-22cac1c5ed76-3 for ; Mon, 20 Apr 2026 21:51:13 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:58 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=ckCzk1RLU5H7o8z98jVbNDtfQVfZx3Dgw741GYACJI5hgysSvN+Ozn9xSf0uu4iuwrQwTm3N6RmSleU2HQTtR0TDOAK2uI2ywKgBYLOA9nMN0bn8GSpOaKFgs5cDw8y/PGLJvnaMLR+pNzODuL8ep5d6RJu2L5wj4YppD1uk1gNKUQKbHobOUaebMEwE07nLyR5RAO0KM1dWc9LoO41CpL2+q5LSzoeeLurU6d44lXjJ8AcocwNoasw3nL0Lue0VE9e8xOPvvO2Dw8sCsB4DZJfzgsOIQJfa455onP1lGj0Cpp1Qau9P/AsKRQK946Kx2Gr1A1bsZVEE/q24lS696A==; s=purelymail1; d=purelymail.com; v=1; bh=sJtt5sv+KSdQzbFQSigMs7fjAJ9VYApzYG1/06R78L4=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Sergej Proskurin Subject: [RFC PATCH v6 25/43] arm/altp2m: Add altp2m index to arch_vcpu Date: Mon, 20 Apr 2026 15:50:24 -0400 Message-Id: <20260420195042.207624-26-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-d62444/1776714673-BEA61FF4-CC81A8CE/0/0 X-purgate-type: clean X-purgate-size: 1940 From: Rose Spangler This commit adds ap2m_idx to the VCPU struct on ARM. This makes it possible to track the current altp2m view being used by a VCPU. This is commit 2/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: This patch was originally part of the "arm/p2m: Add HVMOP_altp2m_set_domain_state" patch from the v4/v5 patch series. It has been extracted into its own commit to make the patch series easier to follow. If it would be preferred, this commit can be squashed into another commit. Added support for the CONFIG_ALTP2M option. --- xen/arch/arm/include/asm/altp2m.h | 4 +--- xen/arch/arm/include/asm/domain.h | 5 +++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index 5a217f48b103..bc695018e62c 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -26,9 +26,7 @@ static inline bool altp2m_supported(void) /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { - /* Not implemented yet */ - BUG(); - return 0; + return v->arch.ap2m_idx; } =20 #else /* CONFIG_ALTP2M */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 9e69d62086cd..4d497a21b648 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -249,6 +249,11 @@ struct arch_vcpu struct vtimer virt_timer; bool vtimer_initialized; =20 +#if CONFIG_ALTP2M + /* Alternate p2m index */ + uint16_t ap2m_idx; +#endif + /* * The full P2M may require some cleaning (e.g when emulation * set/way). As the action can take a long time, it requires --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286499.1567654 (Exim 4.92) (envelope-from ) id 1wEvBT-00057N-PY; Mon, 20 Apr 2026 20:25:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286499.1567654; Mon, 20 Apr 2026 20:25:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBS-000529-9D; Mon, 20 Apr 2026 20:25:30 +0000 Received: by outflank-mailman (input) for mailman id 1286499; Mon, 20 Apr 2026 19:54:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhC-0006RL-7I for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:54:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhB-001Dle-KN for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:54:13 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68454-5cb7-0a2a0a5109dd-0a2a4503cb20-14 for ; Mon, 20 Apr 2026 21:54:13 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683b0-672d-0a2a45030019-22cac1c5ed78-3 for ; Mon, 20 Apr 2026 21:51:13 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:59 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=jyLGAcgSR6t3hWjZwx7uMdSZpDIEbDwOYrxRjZ+6+Pmnt+aGAD6SoaShwQ8Bh72FF/ZmLSkOEyMUmN8BRirbhRoeBFIfazMHKmCrxMjAFwx/yzGpaQ0mbb9RrWlmOJQHkxIkN4PqwHUIzB3jOzUL0msJjzV83RZa6Esbjl/YL0mdEQrBS3anCTZ7e7D46NS1gTT9ystRQGXHfAJAPzOw8Mko+V5/qI3nx8GFJ3WjNwvQhX3f/YjOSq34iw99Gn92mGx2e3Q6K+wn+C6fhdCHMWLQ66/A9JrUy27mm5LmMkMMa4+iNTBTsjChRchweB+RANnfHW9RjIdbu4el42TwBA==; s=purelymail1; d=purelymail.com; v=1; bh=REsQIKHl7J7AKoiHPZNWVFk+81JDE53ulC3Q/fRj3U0=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 26/43] altp2m: Add altp2m_set_vcpu_idx Date: Mon, 20 Apr 2026 15:50:25 -0400 Message-Id: <20260420195042.207624-27-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-33051d/1776714673-48FD6938-BEA2AA01/0/0 X-purgate-type: clean X-purgate-size: 1731 From: Rose Spangler This commit adds the altp2m_set_vcpu_idx function for both x86 and ARM. Since the altp2m VCPU index is stored differently depending on which architecture is used, the altp2m_set_vcpu_idx function makes it possible to set this value in an architecture independent way for common code routines. This is commit 3/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/include/asm/altp2m.h | 5 +++++ xen/arch/x86/include/asm/altp2m.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index bc695018e62c..f001e022a213 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -29,6 +29,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu= *v) return v->arch.ap2m_idx; } =20 +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + v->arch.ap2m_idx =3D idx; +} + #else /* CONFIG_ALTP2M */ =20 static inline bool altp2m_supported(void) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index a1b078783b3e..b3d348386a00 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -60,6 +60,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu= *v) return vcpu_altp2m(v).p2midx; } =20 +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + vcpu_altp2m(v).p2midx =3D idx; +} + /* * Alternate p2m: shadow p2m tables used for alternate memory views */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286502.1567661 (Exim 4.92) (envelope-from ) id 1wEvBW-0005Mp-4S; Mon, 20 Apr 2026 20:25:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286502.1567661; Mon, 20 Apr 2026 20:25:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBT-0005Ic-M7; Mon, 20 Apr 2026 20:25:31 +0000 Received: by outflank-mailman (input) for mailman id 1286502; Mon, 20 Apr 2026 19:54:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhu-0006SQ-JZ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:54:58 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhu-008XH6-0R for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:54:58 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68454-bab6-0a2a0a5309dd-0a2a45079f0a-38 for ; Mon, 20 Apr 2026 21:54:57 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a0-229c-0a2a45070019-22cac1c59abe-3 for ; Mon, 20 Apr 2026 21:50:57 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:54 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=F9MbV6ACJ4uu8xz4nBiYL+aJEaI7vNYgek40kUHpvesIb6Iaboxo61gh+uvAXEzLMJLkNoVW4PQhgcq/Nf3Gpvq4bPtaOW5TmF/HnTF4goJZnO44JqyaTHYLQJpz6b5CUpSz/1JOBSamtbwsGKYfY0pmkmxSKpfYWmH+WWw1cOqnapmEzR0OyBRIrAd8NEnivQuoKbwEjUIi879wTLBDus0BvqoiV76eZCkCuLyAevRI+ixmQ3kla0ordVy/vImR8d0vgS6YP8f9vvoKMxGaSfdxQsZY8Jwh4ElMQurIU3Zo7XU4m/Mh4xy9IIVhyfVRc7qrCyKkZ0AIoefoYzQMhA==; s=purelymail1; d=purelymail.com; v=1; bh=J3+KXe+q3SuG3x2Q+RtXcVoXETWE7y6frhf/lsuIM/c=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 16/43] arm/p2m: Cosmetic fix - substitute _gfn(ULONG_MAX) for INVALID_GFN Date: Mon, 20 Apr 2026 15:50:15 -0400 Message-Id: <20260420195042.207624-17-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-ef75cf/1776714657-ADB68C48-575F2930/0/0 X-purgate-type: clean X-purgate-size: 1020 From: Sergej Proskurin In ./xen/arch/arm/p2m.c, we compare the gfn's with INVALID_GFN throughout the code. Thus it makes sense to use the macro INVALID_GFN instead of a hard coded value to initialize "p2m->lowest_mapped_gfn". This is commit 5/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/mmu/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 3ecb969a0369..1009f10e5db4 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1517,7 +1517,7 @@ static int p2m_initialise(struct domain *d, struct p2= m_domain *p2m) =20 p2m->vmid =3D INVALID_VMID; p2m->max_mapped_gfn =3D _gfn(0); - p2m->lowest_mapped_gfn =3D _gfn(ULONG_MAX); + p2m->lowest_mapped_gfn =3D INVALID_GFN; =20 p2m->default_access =3D p2m_access_rwx; p2m->mem_access_enabled =3D false; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286503.1567665 (Exim 4.92) (envelope-from ) id 1wEvBY-0005kf-Py; Mon, 20 Apr 2026 20:25:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286503.1567665; Mon, 20 Apr 2026 20:25:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBV-0005bS-RB; Mon, 20 Apr 2026 20:25:33 +0000 Received: by outflank-mailman (input) for mailman id 1286503; Mon, 20 Apr 2026 19:54:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhv-0006SW-0I for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:54:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhu-008XH6-Da for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:54:58 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6843f-bab6-0a2a0a5309dd-0a2a4505bfc4-34 for ; Mon, 20 Apr 2026 21:54:58 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a0-aaa8-0a2a45050019-22cac1c59978-3 for ; Mon, 20 Apr 2026 21:50:57 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:55 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=Y1Z3a/0ZFeJbvvg34y5PogXq5DFlqhRhk10bT3/xkvHbswu1iULGf3KAjonxOYEKvO1wMItuikExB7MFJfMSHf08RSO7Nr0Kg1DijZTk9EWJbCXzTMbd2KHBIgPGiwXrzqjquOt0hDOXliLdjxvYCaVMIvqX54IroAh4XTPrvPS4UtzOsddwHbW7TkvSTPYcvwUjl9cOE28D/JBfTh0OFzYRXEpRRGdODGSk6Hr4k+Hk5hS/SzpkChktk0bNKfTSpFE6nepCNNLSNaCd2+3e2H1ld14+r/yTY1xVp/hNFfedRpr2E3+MtZcbbdBS7tCeS1x3RYw6NL11YvDLwKC+Ug==; s=purelymail1; d=purelymail.com; v=1; bh=e683LwwNMa3+lnrdWdK52Gu9IfTTlss7Pk0lZ8mbuPc=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Sergej Proskurin Subject: [RFC PATCH v6 18/43] arm/p2m: Invalidate root page table entries and flush TLB in p2m_flush_table Date: Mon, 20 Apr 2026 15:50:17 -0400 Message-Id: <20260420195042.207624-19-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c201ff/1776714657-2B762443-8C89B9DA/0/0 X-purgate-type: clean X-purgate-size: 4946 From: Rose Spangler This commit invalidates the root page table entries and flushes the TLB when the table is flushed. The TLB is flushed to ensure that altp2m views after being reset or torn down. Previously, the code in p2m_flush_table was only used to free p2m pages during domain teardown. This function will later be used to teardown/reset altp2m views of a still-running domain, so the page table entries must be properly invalidated. Additionally, the p2m_invalidate_root function is split into p2m_invalidate_root and p2m_invalidate_root_locked. The p2m_flush_table function already holds the lock, so it calls p2m_invalidate_root_locked directly, as opposed to the existing callers which don't already hold the lock. This is commit 7/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v3: Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). v6: Introduced this patch. While the code in this patch is mostly new, it is the same in spirit as the p2m_flush_table additions in the original patch series, so the relevant comments have been reproduced above. In the v4/v5 versions of this patch series, this patch was a part of the previous patch. It has been split out to minimize the number of functionality changes in the previous patch. Additionally, the original patch series used a routine here which was nearly identical to p2m_invalidate_root, which was implemented a few years after the patch series. Therefore, the existing p2m_invalidate_root implementation is used here instead. Also, since the original patch series p2m_teardown (and by extension p2m_flush_table, as it was extracted from p2m_teardown) was made preemptible. As a consequence of this, introducing a call to p2m_invalidate_root here also means that p2m_invalidate_root and p2m_tlb_flush_sync is called each time p2m_flush_table is called, even if a previous call to p2m_flush_table was preempted. This might cause some additional overhead, as p2m_flush_table will iterate over the root page tables and flush the TLB before it can return to freeing p2m pages. I'm not sure if there's a better way of handling this, or if the overhead here is negligible/acceptable. I'm not sure how IOMMU interacts with altp2m here. I haven't looked into it extensively, so I would appreciate some feedback here. I've just copied over the iommu_use_hap_pt conditional from p2m_domain_creation_finished, but this is probably not the right behavior since we probably still need to invalidate the altp2m view page tables on flush somehow. Is the issue with invalidating root page tables when using IOMMU only relevant for the hostp2m, or is it also relevant for the altp2m views? --- xen/arch/arm/mmu/p2m.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1d598c66450b..51753bb2c34d 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1271,17 +1271,20 @@ void p2m_clear_root_pages(struct p2m_domain *p2m) * p2m_invalid_root() should not be called when the P2M is shared with * the IOMMU because it will cause IOMMU fault. */ -static void p2m_invalidate_root(struct p2m_domain *p2m) +static void p2m_invalidate_root_locked(struct p2m_domain *p2m) { unsigned int i; =20 ASSERT(!iommu_use_hap_pt(p2m->domain)); =20 - p2m_write_lock(p2m); - for ( i =3D 0; i < P2M_ROOT_PAGES; i++ ) p2m_invalidate_table(p2m, page_to_mfn(p2m->root + i)); +} =20 +static void p2m_invalidate_root(struct p2m_domain *p2m) +{ + p2m_write_lock(p2m); + p2m_invalidate_root_locked(p2m); p2m_write_unlock(p2m); } =20 @@ -1449,6 +1452,13 @@ int p2m_flush_table(struct p2m_domain *p2m) unsigned long count =3D 0; struct page_info *pg; =20 + /* TODO: How does IOMMU interact with altp2m? */ + if ( !iommu_use_hap_pt(p2m->domain) ) + { + p2m_invalidate_root_locked(p2m); + p2m_tlb_flush_sync(p2m); + } + while ( (pg =3D page_list_remove_head(&p2m->pages)) ) { p2m_free_page(p2m->domain, pg); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286506.1567675 (Exim 4.92) (envelope-from ) id 1wEvBc-000690-HJ; Mon, 20 Apr 2026 20:25:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286506.1567675; Mon, 20 Apr 2026 20:25:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBZ-00060B-2i; Mon, 20 Apr 2026 20:25:37 +0000 Received: by outflank-mailman (input) for mailman id 1286506; Mon, 20 Apr 2026 19:55:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhz-0006TW-GR for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:55:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhy-001DqV-S8 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:55:02 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6844b-e002-0a2a0a5209dd-0a2a450aa842-44 for ; Mon, 20 Apr 2026 21:55:02 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a5-56b3-0a2a450a0019-22cac1c59618-3 for ; Mon, 20 Apr 2026 21:51:02 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:55 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=Lxhym/cOQ4qYy9GgreYlWhVreh6oiF53H10JumcP6H06uRDLwJLk0s0KpRoWZzOZPdbu8PQ7CxqFX4QZIRnnEjDpywuAMg9skBImiwABLsR+7E/dGlMayS/taxre2B9cuk35ujy4yQGDrQA5uNm7JAHTIc27AVOd1JMjTameBBl24iYZfrf4f0u8erjx5niUBScDxGd0Dp+923XIIPP6ogUenTrTJzT8pI8A8H8LE6gqyyAZXFav6mkhwKVN3UKvPXKY1PN3nA2Idj67nv7nqLlu0ZdH82vuz92hAwfdr72zYN2Wn6Y/23b1zFNcum5SIC/1ZPIx16OFtivSBPysAg==; s=purelymail1; d=purelymail.com; v=1; bh=wx+7amyQeojfvKKlVkM7oqIEEdzw0LZWV6YBeYQcTbg=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Julien Grall Subject: [RFC PATCH v6 19/43] arm/p2m: Change function prototype of p2m_alloc_table Date: Mon, 20 Apr 2026 15:50:18 -0400 Message-Id: <20260420195042.207624-20-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-4011c0/1776714662-8087E8B7-C9B41944/0/0 X-purgate-type: clean X-purgate-size: 1608 From: Sergej Proskurin The function "p2m_alloc_table" should be able to allocate 2nd stage translation tables not only for the host's p2m but also for alternate p2m's. This commit is a refactor and contains no functional changes. This is commit 8/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin Acked-by: Julien Grall --- v2: Removed altp2m table initialization from "p2m_table_init". v3: Removed initialization of the field d->arch.altp2m_active in "p2m_table_init" to avoid altp2m initialization throughout different files. Merged the function "p2m_alloc_table" and "p2m_table_init". --- xen/arch/arm/mmu/p2m.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51753bb2c34d..f546f63f2489 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1426,10 +1426,8 @@ static struct page_info *p2m_allocate_root(void) return page; } =20 -static int p2m_alloc_table(struct domain *d) +static int p2m_alloc_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m =3D p2m_get_hostp2m(d); - p2m->root =3D p2m_allocate_root(); if ( !p2m->root ) return -ENOMEM; @@ -1576,7 +1574,7 @@ static int p2m_initialise(struct domain *d, struct p2= m_domain *p2m) if ( rc ) return rc; =20 - rc =3D p2m_alloc_table(d); + rc =3D p2m_alloc_table(p2m); if ( rc ) return rc; =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286507.1567683 (Exim 4.92) (envelope-from ) id 1wEvBf-0006hp-Hr; Mon, 20 Apr 2026 20:25:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286507.1567683; Mon, 20 Apr 2026 20:25:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBd-0006Yt-1O; Mon, 20 Apr 2026 20:25:41 +0000 Received: by outflank-mailman (input) for mailman id 1286507; Mon, 20 Apr 2026 19:55:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEuhz-0006Tc-SM for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:55:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuhz-008XH6-9A for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:55:03 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6843f-bab6-0a2a0a5309dd-0a2a4505bfc4-40 for ; Mon, 20 Apr 2026 21:55:03 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a5-aaa8-0a2a45050019-22cac1c5d9aa-3 for ; Mon, 20 Apr 2026 21:51:02 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:56 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=KyDwv5OmmuLRC4ucXPhbnuUebxNOworiZxGrTOcDB/S/5+jSU3Rp2Xdd6LkMkjMjOO893MIVid+zQoa6y9sVfNfInJ2c/ETVwILYzoJEnK+mIVzoWTaQu5a9HBwNLjoJYrex+1u1WXH5Zt0r4Vslw1Q1z8aCV63rUPopyZ2HYzIJq9xcKNFfPTdAVAqgFYJxb/TeXix8zeqsW7VQkDRRrEmkMeFboDanjkijyZqz0Fn32sSrh2zY4O9G4jwTX/EFhXXVkOWKGT8OBd5ednQa2PbTbtZdCLvdlxdQN+Lisy7I70nZNa1KgTtQgpMOaoN3ykGfP5gA33hvL5m6JN8dxA==; s=purelymail1; d=purelymail.com; v=1; bh=rEbX4y8NSItxI+ya2K695AgqL2qzX4yowYtNn0i53K0=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 20/43] arm/p2m: Rename parameter in p2m_alloc_vmid Date: Mon, 20 Apr 2026 15:50:19 -0400 Message-Id: <20260420195042.207624-21-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c201ff/1776714662-2A56B443-0C4D73E0/0/0 X-purgate-type: clean X-purgate-size: 1390 From: Sergej Proskurin This commit does not change or introduce any additional functionality but rather is a part of the following commit that alters the functionality of the function "p2m_alloc_vmid". This is commit 9/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/p2m.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index fb03978a19af..2c43b6033360 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -286,24 +286,24 @@ int p2m_alloc_vmid(struct domain *d) { struct p2m_domain *p2m =3D p2m_get_hostp2m(d); =20 - int rc, nr; + int rc, vmid; =20 spin_lock(&vmid_alloc_lock); =20 - nr =3D find_first_zero_bit(vmid_mask, MAX_VMID); + vmid =3D find_first_zero_bit(vmid_mask, MAX_VMID); =20 - ASSERT(nr !=3D INVALID_VMID); + ASSERT(vmid !=3D INVALID_VMID); =20 - if ( nr =3D=3D MAX_VMID ) + if ( vmid =3D=3D MAX_VMID ) { rc =3D -EBUSY; printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain= _id); goto out; } =20 - set_bit(nr, vmid_mask); + set_bit(vmid, vmid_mask); =20 - p2m->vmid =3D nr; + p2m->vmid =3D vmid; =20 rc =3D 0; =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286508.1567688 (Exim 4.92) (envelope-from ) id 1wEvBh-0007DF-7B; Mon, 20 Apr 2026 20:25:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286508.1567688; Mon, 20 Apr 2026 20:25:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBf-0006y2-40; Mon, 20 Apr 2026 20:25:43 +0000 Received: by outflank-mailman (input) for mailman id 1286508; Mon, 20 Apr 2026 19:55:04 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEui0-0006Ti-LD for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:55:04 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEui0-00C0mN-1r for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:55:04 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68466-5cb7-0a2a0a5109dd-0a2a4501c7ca-34 for ; Mon, 20 Apr 2026 21:55:04 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683a6-c1f2-0a2a45010019-22cac1c5e34a-3 for ; Mon, 20 Apr 2026 21:51:03 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:56 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=ka8fHWy78Y8Am3DZ+DOWFlUlI8NsfFGLMVGXLLSLHp2kp/XVRQX7fNlA+vH3ochrPLpSUxQZQMkngqzd2KIegerlEJVr1lhhPC2zCn61k32n5TlmqEJ19sEnjfbfaiSmJ7DXGwgBY5IDthd7HS/LJH/NV1/IwUDH0HDAv4cllxy/i3NXNq+6Xir2EXYAjjjNrKB1XR6lQ6ErVqgNbugrOrKfBaRXinGyJocEuMzu0mzsqZ2wkyDcH2K62tG41gscBoD5MEGOfIQCj7mRcX5BXWNvtkVkYW5vcx1ENTKBBnD0rKxNJfVOMPBtg1lFw20RfjrMDOMAUVWO5OmqLtabUw==; s=purelymail1; d=purelymail.com; v=1; bh=jide0Bu43AqjkQJCMlxee9HKevJGR4BOO3MM8yiGrIs=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 21/43] arm/p2m: Change func prototype and impl of p2m_{alloc,free}_vmid Date: Mon, 20 Apr 2026 15:50:20 -0400 Message-Id: <20260420195042.207624-22-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-d62444/1776714663-B6460FF4-34C17615/0/0 X-purgate-type: clean X-purgate-size: 4021 From: Sergej Proskurin This commit changes the prototype and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". The function "p2m_alloc_vmid" does not expect the struct domain as argument anymore and returns an allocated vmid. The function "p2m_free_vmid" takes only the vmid that is to be freed as argument. This is commit 10/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v3: Changed function prototypes and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". Changes in "p2m_alloc_vmid": This function does not expect any arguments. Also, in this commit, the function "p2m_alloc_vmid" returns either the successfully allocated vmid or the value INVALID_VMID. Thus, it is now the responsibility of the caller to set the returned vmid in the associated fields. Changes in "p2m_free_vmid": This function expects now only the vmid of type uint8_t. --- xen/arch/arm/include/asm/p2m.h | 4 ++-- xen/arch/arm/mmu/p2m.c | 8 ++++---- xen/arch/arm/p2m.c | 23 ++++++++--------------- 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.= h index 5c6dfe4a9789..62261d41e780 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -195,8 +195,8 @@ static inline bool arch_acquire_resource_check(struct d= omain *d) void p2m_restrict_ipa_bits(unsigned int ipa_bits); =20 void p2m_vmid_allocator_init(void); -int p2m_alloc_vmid(struct domain *d); -void p2m_free_vmid(struct domain *d); +uint8_t p2m_alloc_vmid(void); +void p2m_free_vmid(uint8_t vmid); =20 /* Second stage paging setup, to be called on all CPUs */ void setup_virt_paging(void); diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index f546f63f2489..0d37760ef5d5 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1519,7 +1519,7 @@ void p2m_free_one(struct p2m_domain *p2m) =20 p2m->root =3D NULL; =20 - p2m_free_vmid(p2m->domain); + p2m_free_vmid(p2m->vmid); =20 radix_tree_destroy(&p2m->mem_access_settings, NULL); =20 @@ -1570,9 +1570,9 @@ static int p2m_initialise(struct domain *d, struct p2= m_domain *p2m) */ p2m->domain =3D d; =20 - rc =3D p2m_alloc_vmid(d); - if ( rc ) - return rc; + p2m->vmid =3D p2m_alloc_vmid(); + if ( p2m->vmid =3D=3D INVALID_VMID ) + return -EBUSY; =20 rc =3D p2m_alloc_table(p2m); if ( rc ) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2c43b6033360..3342fafcc8a7 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -282,11 +282,9 @@ void p2m_vmid_allocator_init(void) set_bit(INVALID_VMID, vmid_mask); } =20 -int p2m_alloc_vmid(struct domain *d) +uint8_t p2m_alloc_vmid(void) { - struct p2m_domain *p2m =3D p2m_get_hostp2m(d); - - int rc, vmid; + uint8_t vmid; =20 spin_lock(&vmid_alloc_lock); =20 @@ -296,28 +294,23 @@ int p2m_alloc_vmid(struct domain *d) =20 if ( vmid =3D=3D MAX_VMID ) { - rc =3D -EBUSY; - printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain= _id); + vmid =3D INVALID_VMID; + printk(XENLOG_ERR "p2m.c: VMID pool exhausted\n"); goto out; } =20 set_bit(vmid, vmid_mask); =20 - p2m->vmid =3D vmid; - - rc =3D 0; - out: spin_unlock(&vmid_alloc_lock); - return rc; + return vmid; } =20 -void p2m_free_vmid(struct domain *d) +void p2m_free_vmid(uint8_t vmid) { - struct p2m_domain *p2m =3D p2m_get_hostp2m(d); spin_lock(&vmid_alloc_lock); - if ( p2m->vmid !=3D INVALID_VMID ) - clear_bit(p2m->vmid, vmid_mask); + if ( vmid !=3D INVALID_VMID ) + clear_bit(vmid, vmid_mask); =20 spin_unlock(&vmid_alloc_lock); } --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286512.1567697 (Exim 4.92) (envelope-from ) id 1wEvBj-0007lN-Hr; Mon, 20 Apr 2026 20:25:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286512.1567697; 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Mon, 20 Apr 2026 21:51:07 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:56 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=JWYWRquuSTuhciHLqgYeswBxBv5VcCkgO9tLKcp9bU685iDQuLM/Vwga9hxf0HtCz1rnGyPnhqI2ROb2eGvcedsGtHDyiOcoqU5Yh/ueglfvyLjOG8n6WydAhTsfcrJloa5EWmFwwCKztE28l7gLqAyVn/baLQY3GzTiqqoUPR5JApcTV7kRZxz44xltCmE/ohAVlrCFdWo3aEh6QBEvw1ZMp25JFSS40fBahPK7+R7DYy9qs4Zb6yoYfHbrnvAmjDakXOPGBUv75Hxhbm7TZW1SAzRrxemzqUnpyih6f/YFfNi6ckXP16Ql5aeomQcBnEeVdpxcKWW+leamLbowtA==; s=purelymail1; d=purelymail.com; v=1; bh=cqbeVhxhas1SelZKmRR5Y1Q1CkbmNFmzg1IsVkQqEdU=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 22/43] arm/p2m: Introduce p2m_is_{hostp2m,altp2m} Date: Mon, 20 Apr 2026 15:50:21 -0400 Message-Id: <20260420195042.207624-23-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-33051d/1776714667-2A567938-7BB031FC/13/0 X-purgate-type: clean X-purgate-size: 1756 From: Sergej Proskurin This commit adds a p2m class to the struct p2m_domain to distinguish between the host's original p2m and alternate p2m's. The need for this functionality will be shown in the following commits. This is commit 11/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v4: Change return type of p2m_is_(hostp2m|altp2m) from bool_t to bool. --- xen/arch/arm/include/asm/p2m.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.= h index 62261d41e780..8ae0cd7ff589 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -32,6 +32,11 @@ struct domain; =20 extern void memory_type_changed(struct domain *d); =20 +typedef enum { + p2m_host, + p2m_alternate, +} p2m_class_t; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -111,6 +116,9 @@ struct p2m_domain { =20 /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; + + /* Choose between: host/alternate. */ + p2m_class_t p2m_class; }; =20 /* @@ -424,6 +432,16 @@ static inline int get_page_and_type(struct page_info *= page, /* get host p2m table */ #define p2m_get_hostp2m(d) ((d)->arch.p2m) =20 +static inline bool p2m_is_hostp2m(const struct p2m_domain *p2m) +{ + return p2m->p2m_class =3D=3D p2m_host; +} + +static inline bool p2m_is_altp2m(const struct p2m_domain *p2m) +{ + return p2m->p2m_class =3D=3D p2m_alternate; +} + static inline bool p2m_vm_event_sanity_check(struct domain *d) { return true; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286513.1567703 (Exim 4.92) (envelope-from ) id 1wEvBl-0008Gl-OM; Mon, 20 Apr 2026 20:25:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286513.1567703; Mon, 20 Apr 2026 20:25:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBj-00088v-E1; Mon, 20 Apr 2026 20:25:47 +0000 Received: by outflank-mailman (input) for mailman id 1286513; Mon, 20 Apr 2026 19:55:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEui5-0006VB-U5 for xen-devel@lists.xenproject.org; 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dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=G8Au/F7w0kr3yWBN493bKoUzi1aJp5ehASYi4BlnUh6gTILN9XNytRgGapOi7MBFApd8IY5pvk4fGWY7FmNiOdKTP3NFVO+EVEVwOKjasT+Pi5mMEkubMSLcxQJj/QtiILUpuLEtAiQK/+wab7YXBiO7jPtJfWQ95xa5JzwwrkiIhxOjhmFPSFMgRE5R3R+TbmS35xpSYX5JTAXMoQSIO2ZL3QsYCw/RVEoau4CHHuV8Ely0Q1pwwo36pTfdPYZWCJUy/yxpWYpfiqoaP0bIhU6HY6WbbejJpCdA5neGJGo2D2WCi3SRI51XOBnov+kYae9EDSlUHk+A0KRdFT597A==; s=purelymail1; d=purelymail.com; v=1; bh=3WaQvrna8zsFCyA45arxMyrce2HZKSIAvzQk5fZ8kuY=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [RFC PATCH v6 24/43] altp2m: Move altp2m_{get,set}_altp2m to common code Date: Mon, 20 Apr 2026 15:50:23 -0400 Message-Id: <20260420195042.207624-25-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-42698a/1776714668-246B7F3B-BCC1441B/13/0 X-purgate-type: clean X-purgate-size: 5177 From: Rose Spangler This commit moves the altp2m_get_altp2m and altp2m_set_altp2m functions to the common code. This make sit possible to use them in other common routines (namely, altp2m_vcpu_{initialise,destroy}). This commit contains only code movement, and no change in functionality is intended. This is commit 1/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 35 ------------------------- xen/arch/x86/include/asm/domain.h | 2 -- xen/common/altp2m.c | 1 - xen/include/xen/altp2m.h | 43 +++++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 38 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 13017525a62f..a1b078783b3e 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -64,39 +64,6 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu= *v) * Alternate p2m: shadow p2m tables used for alternate memory views */ =20 -/* get current alternate p2m table */ -static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) -{ - unsigned int index =3D vcpu_altp2m(v).p2midx; - - if ( index =3D=3D INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >=3D v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >=3D v->domain->nr_altp2m); - - if ( idx =3D=3D vcpu_altp2m(v).p2midx ) - return false; - - orig =3D altp2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx =3D idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); =20 @@ -178,8 +145,6 @@ static inline int _altp2m_get_effective_entry(struct p2= m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) =20 /* Only declaration is needed. DCE will optimise it out when linking. */ -struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); -bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index f8038087e612..72460e38f581 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -277,8 +277,6 @@ struct paging_vcpu { #define MAX_NR_ALTP2M MAX_EPTP #define MAX_NESTEDP2M 10 =20 -#define INVALID_ALTP2M 0xffff - struct p2m_domain; struct time_scale { int shift; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 989d8bdcb923..a731ad7cdab8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -5,7 +5,6 @@ #include =20 #include -#include =20 #include =20 diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 238c7a935586..58e74be6deb0 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,10 @@ =20 #include =20 +#include + +#define INVALID_ALTP2M 0xffff + /* * Common alternate p2m declarations that need to be visible * regardless of CONFIG_ALTP2M @@ -27,6 +31,41 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } =20 +#ifdef CONFIG_X86 +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index =3D vcpu_altp2m(v).p2midx; + + if ( index =3D=3D INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >=3D v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >=3D v->domain->nr_altp2m); + + if ( idx =3D=3D vcpu_altp2m(v).p2midx ) + return false; + + orig =3D altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx =3D idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} +#endif + int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); =20 #else /* CONFIG_ALTP2M */ @@ -41,6 +80,10 @@ static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(vo= id) arg) return -EOPNOTSUPP; } =20 +/* Only declaration is needed. DCE will optimise it out when linking. */ +struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); +bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); + #endif /* CONFIG_ALTP2M */ =20 #endif /* __XEN_ALTP2M_H__ */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286514.1567712 (Exim 4.92) (envelope-from ) id 1wEvBn-0000IT-5p; Mon, 20 Apr 2026 20:25:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286514.1567712; Mon, 20 Apr 2026 20:25:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBl-00009I-6R; Mon, 20 Apr 2026 20:25:49 +0000 Received: by outflank-mailman (input) for mailman id 1286514; Mon, 20 Apr 2026 19:55:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEui5-0006VA-Sw for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 19:55:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEui5-00C0mN-9p for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 21:55:09 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e6849d-5cb7-0a2a0a5109dd-0a2a450bd69e-0 for ; Mon, 20 Apr 2026 21:55:09 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e683ab-212f-0a2a450b0019-22cac1c5c2e6-3 for ; Mon, 20 Apr 2026 21:51:08 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -306608446; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 19:50:57 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=YcLB+fWp94ky5pCPnNruujNicg8BuQxICWMz3/BkwTq5ox4j84lmQRhd/i/oJFV+bGrH/feNXuOJKUqWO7iRTJSJvCkQoO7DEhapiVl2SYkjE+kdkZt7F8FqHaXpUrr5ic/CYEiirwTnijxiNkgQnSXBk+OlXjsWW4IJa50rBGNCoT8Fikyua5CIFly1yk1FBT3iKWowcukxfNakHan6jqBuc9ejBefxwfCvbpzCIEpEP9zVwzXBpQpDnX97oU4sMWOSUdFnEH4mPqrqN+CNo/4ZTlCmktbbO8OWwxujmWCkzu+iHTOu3x2F3Xhz1iEeMCu4fPp/+sbYhQH2pNFYAQ==; s=purelymail1; d=purelymail.com; v=1; bh=pik6B7HNWf3xgS0SgW/KnVIMif31sL93P+diA7yc3/I=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Sergej Proskurin , Aqib Javaid Subject: [RFC PATCH v6 23/43] arm/altp2m: Add support for altp2m init/teardown routines Date: Mon, 20 Apr 2026 15:50:22 -0400 Message-Id: <20260420195042.207624-24-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420195042.207624-1-Rose.Spangler@purelymail.com> References: <20260420195042.207624-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-42698a/1776714668-0636CF3B-EAFEFEF9/13/0 X-purgate-type: clean X-purgate-size: 7918 From: Rose Spangler The p2m initialization now invokes initialization routines responsible for the allocation and initialization of altp2m structures. The same applies to teardown routines. This commit adds the prerequisites for the common altp2m_init and altp2m_teardown functions to work on ARM; No further changes were necessary other than removing the CONFIG_X86 gating. This is commit 12/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin Signed-off-by: Aqib Javaid --- v2: Shared code between host/altp2m init/teardown functions. Added conditional init/teardown of altp2m. Altp2m related functions are moved to altp2m.c v3: Removed locking the altp2m_lock in altp2m_teardown. Locking this lock at this point is unnecessary. Removed re-setting altp2m_vttbr, altp2m_p2m, and altp2m_active values in the function "altp2m_teardown". Re-setting these values is unnecessary as the entire domain will be destroyed right afterwards. Removed check for "altp2m_enabled" in "p2m_init" as altp2m has not yet been enabled by libxl at this point. Removed check for "altp2m_enabled" before tearing down altp2m within the function "p2m_teardown" so that altp2m gets destroyed even if the HVM_PARAM_ALTP2M gets reset before "p2m_teardown" is called. Added initialization of the field d->arch.altp2m_active in "altp2m_init". Removed check for already initialized vmid's in "altp2m_init_one", as "altp2m_init_one" is now called always with an uninitialized p2m. Removed the array altp2m_vttbr[] in struct arch_domain. v4: Removed initialization of altp2m_p2m[] to NULL in altp2m_init, as the "struct arch_domain" is already initialized to zero. We moved the definition of the macro MAX_ALTP2M to a common place in a separate commit. v6: Reworked to use common altp2m init and teardown routines. Added altp2m_lock_init macro for use in altp2m_init. Split altp2m initialization in p2m_init into a separate function, p2m_init_altp2m, to more easily gate code behind CONFIG_ALTP2M. Pulled in addition of active_vcpus from a later patch in the patch series. Split teardown and free of altp2m views into p2m_teardown and p2m_teardown_final (part of altp2m_teardown), respectively. --- xen/arch/arm/include/asm/altp2m.h | 4 +++ xen/arch/arm/include/asm/domain.h | 8 ++++++ xen/arch/arm/include/asm/p2m.h | 5 ++++ xen/arch/arm/mmu/p2m.c | 44 ++++++++++++++++++++++++++++++- xen/common/altp2m.c | 2 -- xen/include/xen/altp2m.h | 2 -- 6 files changed, 60 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index 698c35427e75..5a217f48b103 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -19,6 +19,10 @@ static inline bool altp2m_supported(void) return true; } =20 +#define altp2m_lock_init(d) spin_lock_init(&(d)->arch.altp2m_lock) +#define altp2m_lock(d) spin_lock(&(d)->arch.altp2m_lock) +#define altp2m_unlock(d) spin_unlock(&(d)->arch.altp2m_lock) + /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 576dbdec20af..9e69d62086cd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -128,6 +128,14 @@ struct arch_domain #endif =20 struct resume_info resume_ctx; + +#ifdef CONFIG_ALTP2M + /* + * Lock that protects critical altp2m operations that must not be perf= ormed + * concurrently. + */ + spinlock_t altp2m_lock; +#endif } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.= h index 8ae0cd7ff589..db715c4f8bfc 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -9,6 +9,8 @@ #include #include =20 +#include + #define paddr_bits PADDR_BITS =20 /* Holds the bit size of IPAs in p2m tables. */ @@ -117,6 +119,9 @@ struct p2m_domain { /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; =20 + /* Alternate p2m: count of vcpu's currently using this p2m. */ + atomic_t active_vcpus; + /* Choose between: host/alternate. */ p2m_class_t p2m_class; }; diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 0d37760ef5d5..04d17e787259 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,7 @@ #include #include =20 +#include #include #include #include @@ -1486,6 +1488,20 @@ int p2m_teardown(struct domain *d) { struct p2m_domain *p2m =3D p2m_get_hostp2m(d); =20 +#ifdef CONFIG_ALTP2M + unsigned int i; + int rc; + + d->altp2m_active =3D false; + + for ( i =3D 0; i < d->nr_altp2m; i++ ) + { + rc =3D p2m_teardown_one(d->altp2m_p2m[i]); + if ( rc ) + return rc; + } +#endif + return p2m_teardown_one(p2m); } =20 @@ -1499,6 +1515,9 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ =20 + if ( altp2m_supported() ) + altp2m_teardown(d); + while ( p2m_teardown_allocation(d) =3D=3D -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); @@ -1595,6 +1614,24 @@ struct p2m_domain *p2m_init_one(struct domain *d) return NULL; } =20 +static int p2m_init_altp2m(struct domain *d) +{ +#ifdef CONFIG_ALTP2M + int rc; + + rc =3D altp2m_init(d); + if ( rc ) + { + p2m_free_one(p2m_get_hostp2m(d)); + return rc; + } + + d->altp2m_active =3D false; +#endif + + return 0; +} + static int p2m_init_hostp2m(struct domain *d) { struct p2m_domain *p2m =3D p2m_init_one(d); @@ -1608,10 +1645,15 @@ static int p2m_init_hostp2m(struct domain *d) =20 int p2m_init(struct domain *d) { + int rc; spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); =20 - return p2m_init_hostp2m(d); + rc =3D p2m_init_hostp2m(d); + if ( rc ) + return rc; + + return p2m_init_altp2m(d); } =20 /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index cda653b713f0..989d8bdcb923 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -15,7 +15,6 @@ #include #endif =20 -#if CONFIG_X86 int altp2m_init(struct domain *d) { unsigned int i; @@ -60,7 +59,6 @@ void altp2m_teardown(struct domain *d) =20 XVFREE(d->altp2m_p2m); } -#endif /* CONFIG_X86 */ =20 /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 85ef22c2b29e..238c7a935586 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -13,13 +13,11 @@ * regardless of CONFIG_ALTP2M */ =20 -#ifdef CONFIG_X86 /* Initialize altp2m views */ int altp2m_init(struct domain *d); =20 /* Free altp2m views */ void altp2m_teardown(struct domain *d); -#endif =20 #ifdef CONFIG_ALTP2M =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286518.1567720 (Exim 4.92) (envelope-from ) id 1wEvBp-0000j7-Jk; Mon, 20 Apr 2026 20:25:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286518.1567720; Mon, 20 Apr 2026 20:25:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBn-0000cG-5y; Mon, 20 Apr 2026 20:25:51 +0000 Received: by outflank-mailman (input) for mailman id 1286518; Mon, 20 Apr 2026 19:57:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEukO-0006fo-UJ for xen-devel@lists.xenproject.org; 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charset=UTF-8 X-purgate-ID: tlsNG-720697/1776715052-88EC8161-383666E4/0/0 X-purgate-type: clean X-purgate-size: 1886 From: Rose Spangler This commit adds support for altp2m_get_altp2m and altp2m_set_altp2m on ARM. The x86-specific VCPU accesses have been replaced with the architecture independent functions altp2m_vcpu_idx and altp2m_set_vcpu_idx. This is commit 4/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/include/xen/altp2m.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 58e74be6deb0..f5a4d0e60562 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,7 @@ =20 #include =20 +#include #include =20 #define INVALID_ALTP2M 0xffff @@ -31,11 +32,10 @@ static inline bool altp2m_active(const struct domain *d= ) return d->altp2m_active; } =20 -#ifdef CONFIG_X86 /* get current alternate p2m table */ static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) { - unsigned int index =3D vcpu_altp2m(v).p2midx; + unsigned int index =3D altp2m_vcpu_idx(v); =20 if ( index =3D=3D INVALID_ALTP2M ) return NULL; @@ -52,19 +52,18 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, un= signed int idx) =20 BUG_ON(idx >=3D v->domain->nr_altp2m); =20 - if ( idx =3D=3D vcpu_altp2m(v).p2midx ) + if ( idx =3D=3D altp2m_vcpu_idx(v) ) return false; =20 orig =3D altp2m_get_altp2m(v); BUG_ON(!orig); atomic_dec(&orig->active_vcpus); =20 - vcpu_altp2m(v).p2midx =3D idx; + altp2m_set_vcpu_idx(v, idx); atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); =20 return true; } -#endif =20 int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286520.1567726 (Exim 4.92) (envelope-from ) id 1wEvBr-00015v-8d; Mon, 20 Apr 2026 20:25:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286520.1567726; Mon, 20 Apr 2026 20:25:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBp-0000y1-98; Mon, 20 Apr 2026 20:25:53 +0000 Received: by outflank-mailman (input) for mailman id 1286520; Mon, 20 Apr 2026 20:06:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEusj-0007oA-P2 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 20:06:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEuse-009HKD-PE for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 22:06:06 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e686da-5cb7-0a2a0a5109dd-0a2a4505af3a-48 for ; Mon, 20 Apr 2026 22:06:06 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e6872d-aaa8-0a2a45050019-22cac1c5d822-3 for ; Mon, 20 Apr 2026 22:06:06 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id 894788268; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 20:06:02 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=c6Uo50C3us1qXsCWidSWfDOGOxihcFAWL2GAjzQ3mgcmdXFMu/mRs8jfHz0jMmN5HAqUSz9USKAqpKqAVJeSz0YTClxj/Li28FsH3Cojha6EWVTuvRIFCm8WgIbjnsj1NsSmBKqUgPwHmq+ykNUHP9TIMq7tGc5n2eID7bpEiHWKBkQEoy7Mr2S5J5NFxouspxF++aMgCkgVDVgL2gnphoqd7y+ESKz7ew60In54QNupWFplE06re304wNpqkxYEhmBUeslwVxeWJ82NXoZ2XBO6j/DjMVgS7vlqwXbT1nuSaDj7sWK6PmDE9DwBmwhJC6vmz0oFm6S0BUZ+ld4rUA==; s=purelymail1; d=purelymail.com; v=1; bh=vaO/7eskJABAM8GcpLXrSRGVxvX12VbJzyiOSdPRPvg=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [RFC PATCH v6 28/43] altp2m: Move altp2m_vcpu_{initialise,destroy} to common code Date: Mon, 20 Apr 2026 16:05:42 -0400 Message-Id: <20260420200557.207930-1-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c201ff/1776715566-E336C443-30DAC370/0/0 X-purgate-type: clean X-purgate-size: 4770 From: Rose Spangler This commit moves the altp2m_vcpu_initialise and altp2m_vcpu_destroy functions to common code. This makes it possible to use them in the common implementation of HVMOP_altp2m_set_domain_state. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 6 ----- xen/arch/x86/mm/altp2m.c | 41 ------------------------------- xen/common/altp2m.c | 41 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 6 +++++ 4 files changed, 47 insertions(+), 47 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index b3d348386a00..43dd5d2acd9c 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -105,10 +105,6 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2m= , gfn_t gfn, mfn_t *mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate); =20 -/* Alternate p2m VCPU */ -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); =20 @@ -151,8 +147,6 @@ static inline int _altp2m_get_effective_entry(struct p2= m_domain *ap2m, =20 /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); =20 diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 46374373848d..0542e3ef9196 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -14,47 +14,6 @@ #include "mm-locks.h" #include "p2m.h" =20 -void -altp2m_vcpu_initialise(struct vcpu *v) -{ - if ( !v->domain->nr_altp2m ) - return; - - if ( v !=3D current ) - vcpu_pause(v); - - vcpu_altp2m(v).p2midx =3D 0; - atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); - - altp2m_vcpu_update_p2m(v); - - if ( v !=3D current ) - vcpu_unpause(v); -} - -void -altp2m_vcpu_destroy(struct vcpu *v) -{ - struct p2m_domain *p2m; - - if ( !v->domain->nr_altp2m ) - return; - - if ( v !=3D current ) - vcpu_pause(v); - - if ( (p2m =3D altp2m_get_altp2m(v)) ) - atomic_dec(&p2m->active_vcpus); - - altp2m_vcpu_disable_ve(v); - - vcpu_altp2m(v).p2midx =3D INVALID_ALTP2M; - altp2m_vcpu_update_p2m(v); - - if ( v !=3D current ) - vcpu_unpause(v); -} - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn) { struct domain *d =3D v->domain; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a731ad7cdab8..e699b64678d8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -59,6 +59,47 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } =20 +#ifdef CONFIG_X86 +void altp2m_vcpu_initialise(struct vcpu *v) +{ + if ( !v->domain->nr_altp2m ) + return; + + if ( v !=3D current ) + vcpu_pause(v); + + vcpu_altp2m(v).p2midx =3D 0; + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); + + altp2m_vcpu_update_p2m(v); + + if ( v !=3D current ) + vcpu_unpause(v); +} + +void altp2m_vcpu_destroy(struct vcpu *v) +{ + struct p2m_domain *p2m; + + if ( !v->domain->nr_altp2m ) + return; + + if ( v !=3D current ) + vcpu_pause(v); + + if ( (p2m =3D altp2m_get_altp2m(v)) ) + atomic_dec(&p2m->active_vcpus); + + altp2m_vcpu_disable_ve(v); + + vcpu_altp2m(v).p2midx =3D INVALID_ALTP2M; + altp2m_vcpu_update_p2m(v); + + if ( v !=3D current ) + vcpu_unpause(v); +} +#endif + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index f5a4d0e60562..7defe6126563 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,6 +24,12 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); =20 +#ifdef CONFIG_X86 +/* Alternate p2m VCPU */ +void altp2m_vcpu_initialise(struct vcpu *v); +void altp2m_vcpu_destroy(struct vcpu *v); +#endif + #ifdef CONFIG_ALTP2M =20 /* Alternate p2m HVM on/off per domain */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:25:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:25:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286522.1567735 (Exim 4.92) (envelope-from ) id 1wEvBs-0001VA-Qv; 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s=purelymail1; d=purelymail.com; v=1; bh=6JpqCKE14Ko8dp6uJ3eg+NGvA3AnOZiNuyDPfwkQfOU=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 29/43] arm/altp2m: Add support for altp2m_vcpu_{initialise,destroy} Date: Mon, 20 Apr 2026 16:20:12 -0400 Message-Id: <20260420202026.208110-1-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-720697/1776716434-8077A161-152131EC/0/0 X-purgate-type: clean X-purgate-size: 3276 From: Rose Spangler This commit adds support for the altp2m_vcpu_initialise and altp2m_vcpu_destroy functions on ARM. The x86-specific function calls, altp2m_vcpu_disable_ve and altp2m_vcpu_update_p2m, are gated with #ifdef CONFIG_X86. This is commit 2/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. The equivalent to this patch in the v4/v5 was originally part of the patch named "arm/altp2m: Add HVMOP_altp2m_set_domain_state". In that patch, the check that the VCPU passed to altp2m_vcpu_initialise isn't the current CPU was removed. This was because ARM only implements the external altp2m mode, meaning the current VCPU could never be a VCPU of the guest for which altp2m is being initialized for. Therefore, skipping this check was a slight optimization. I've removed that here because altp2m_vcpu_initialise is only called during an HVMOP, and skipping this check on ARM (especially when x86 also implements the external altp2m mode) causes more confusion than the slight optimization is worth in my view. --- xen/common/altp2m.c | 14 ++++++++++---- xen/include/xen/altp2m.h | 2 -- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index e699b64678d8..7b80426c7798 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -11,6 +11,7 @@ #include =20 #if defined(CONFIG_X86) && defined(CONFIG_HVM) +#include #include #endif =20 @@ -59,7 +60,6 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } =20 -#ifdef CONFIG_X86 void altp2m_vcpu_initialise(struct vcpu *v) { if ( !v->domain->nr_altp2m ) @@ -68,10 +68,12 @@ void altp2m_vcpu_initialise(struct vcpu *v) if ( v !=3D current ) vcpu_pause(v); =20 - vcpu_altp2m(v).p2midx =3D 0; + altp2m_set_vcpu_idx(v, 0); atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); =20 +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif =20 if ( v !=3D current ) vcpu_unpause(v); @@ -90,15 +92,19 @@ void altp2m_vcpu_destroy(struct vcpu *v) if ( (p2m =3D altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); =20 +#ifdef CONFIG_X86 altp2m_vcpu_disable_ve(v); +#endif =20 - vcpu_altp2m(v).p2midx =3D INVALID_ALTP2M; + altp2m_set_vcpu_idx(v, INVALID_ALTP2M); + +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif =20 if ( v !=3D current ) vcpu_unpause(v); } -#endif =20 /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 7defe6126563..37c875a52327 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,11 +24,9 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); =20 -#ifdef CONFIG_X86 /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); -#endif =20 #ifdef CONFIG_ALTP2M =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:26:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:26:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286523.1567747 (Exim 4.92) (envelope-from ) id 1wEvBv-000276-01; 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Mon, 20 Apr 2026 22:20:34 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e68a91-63b5-0a2a45080019-22cac1c5b4ee-3 for ; Mon, 20 Apr 2026 22:20:34 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -1875363766; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 20:20:32 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=X7BlSDaHD2ZN34svscwHtzMfbiMmT2qfzrjzlITnOA5z8VSmdQKwqfWkynM2turRCGNeCrBLyGZjTriSpJwaldmF2rhgB/hqeKX60WflFBuQLptyO9atGRXWlwuCqwO/xnhV1MCnMlATCPvWbEzuoVCpK7XhQXPYqMzHCWLEEVYZg3LN/GMEbHhvVbQAqaQK44vcJlYg3JDtW1OiduhgOQpWqvqU03EDFMoJIY7vOsOQWx7OlShlCkH63nNJ4R5aMgQWZfJY8OU/YyfyJTR06sp19FDM9ahqc1nxiZtaoOynBRvdn9ohRjgiQ0OwaFvovQUKbXm54bMfDpbozylzHw==; s=purelymail1; d=purelymail.com; v=1; bh=Kv6dybNvgNtP37AvVC3V395nXDoMWOm3zuegSLm3PkU=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 30/43] arm/altp2m: Add altp2m view validity/visibility indicator Date: Mon, 20 Apr 2026 16:20:13 -0400 Message-Id: <20260420202026.208110-2-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420202026.208110-1-Rose.Spangler@purelymail.com> References: <20260420202026.208110-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-c1860d/1776716434-C357FDB1-F7CE8E96/0/0 X-purgate-type: clean X-purgate-size: 5580 From: Rose Spangler This commit adds the altp2m_view_state enum, which indicates whether an altp2m view is invalid, visible, or invisible. The altp2m_state array is comprised of altp2m_view_state values, where each entry corresponds to the altp2m view with the same entry. This is analogous to the altp2m_eptp and altp2m_visible_eptp arrays on x86. This addition is necessary to tell whether an altp2m is valid, in addition to whether it is visible. Since all altp2m views are allocated up-front during p2m initialization, there must be an additional mechanism to determine whether an altp2m view is valid. Since the implementation of HVMOP_altp2m_set_visibility also needs an additional mechanism to determine whether a view is visible, it makes sense to combine altp2m view validity and visibility into a single mechanism. Therefore, the altp2m_state array is used to track both view validitity and visibility. This is commit 1/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. In the v4/v5 patch series, view validity was determined by simply checking if the altp2m p2m_domain pointer is NULL. This isn't possible in the v6 patch series, since altp2m views are allocated up-front during altp2m_init. Since the altp2m_view_state enum definition has to be available in asm/domain.h, this commit removes the sched.h dependency from altp2m.h. Unfortunately, this means that it's not possible to have static inline functions in altp2m.h which need a complete definition of arch_domain and arch_vcpu. If there would be a better place to put the altp2m_view_state definition, feedback would be appreciated. --- xen/arch/arm/altp2m.c | 13 +++++++++++++ xen/arch/arm/include/asm/altp2m.h | 23 +++++++++++++---------- xen/arch/arm/include/asm/domain.h | 4 ++++ xen/arch/arm/mmu/p2m.c | 14 +++++++++++++- 4 files changed, 43 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 339f82835caf..e741648ff5a1 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -5,6 +5,8 @@ * Copyright (c) 2016 Sergej Proskurin */ =20 +#include + #include =20 /* Check to see if vcpu should be switched to a different p2m. */ @@ -14,6 +16,17 @@ void altp2m_check(struct vcpu *v, uint16_t idx) BUG(); } =20 +/* Alternate p2m VCPU */ +uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + return v->arch.ap2m_idx; +} + +void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + v->arch.ap2m_idx =3D idx; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index f001e022a213..05beb7f698a7 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -9,7 +9,10 @@ #ifndef __ASM_ARM_ALTP2M_H #define __ASM_ARM_ALTP2M_H =20 -#include +#include + +struct domain; +struct vcpu; =20 #ifdef CONFIG_ALTP2M =20 @@ -24,15 +27,15 @@ static inline bool altp2m_supported(void) #define altp2m_unlock(d) spin_unlock(&(d)->arch.altp2m_lock) =20 /* Alternate p2m VCPU */ -static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) -{ - return v->arch.ap2m_idx; -} - -static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) -{ - v->arch.ap2m_idx =3D idx; -} +uint16_t altp2m_vcpu_idx(const struct vcpu *v); +void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx); + +/* The current state of an altp2m view */ +enum altp2m_view_state { + ALTP2M_INVALID, + ALTP2M_VISIBLE, + ALTP2M_INVISIBLE, +}; =20 #else /* CONFIG_ALTP2M */ =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 4d497a21b648..28533b08db1f 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -3,6 +3,7 @@ =20 #include #include +#include #include #include #include @@ -135,6 +136,9 @@ struct arch_domain * concurrently. */ spinlock_t altp2m_lock; + + /* Validity/visibility of altp2m views */ + enum altp2m_view_state *altp2m_state; #endif } __cacheline_aligned; =20 diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 04d17e787259..7c23995f8074 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1494,6 +1494,8 @@ int p2m_teardown(struct domain *d) =20 d->altp2m_active =3D false; =20 + FREE_XENHEAP_PAGE(d->arch.altp2m_state); + for ( i =3D 0; i < d->nr_altp2m; i++ ) { rc =3D p2m_teardown_one(d->altp2m_p2m[i]); @@ -1617,7 +1619,7 @@ struct p2m_domain *p2m_init_one(struct domain *d) static int p2m_init_altp2m(struct domain *d) { #ifdef CONFIG_ALTP2M - int rc; + int rc, i; =20 rc =3D altp2m_init(d); if ( rc ) @@ -1626,6 +1628,16 @@ static int p2m_init_altp2m(struct domain *d) return rc; } =20 + if ( (d->arch.altp2m_state =3D alloc_xenheap_page()) =3D=3D NULL ) + { + return -ENOMEM; + } + + for ( i =3D 0; i < d->nr_altp2m; i++ ) + { + d->arch.altp2m_state[i] =3D ALTP2M_INVALID; + } + d->altp2m_active =3D false; #endif =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:26:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:26:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1286524.1567756 (Exim 4.92) (envelope-from ) id 1wEvBx-0002Vp-2Y; Mon, 20 Apr 2026 20:26:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1286524.1567756; Mon, 20 Apr 2026 20:26:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvBv-0002PF-EE; Mon, 20 Apr 2026 20:25:59 +0000 Received: by outflank-mailman (input) for mailman id 1286524; Mon, 20 Apr 2026 20:20:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEv6h-0001fE-Ca for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 20:20:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEv6g-00C4rw-Px for xen-devel@lists.xenproject.org; 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b=XrpheRDvgB46tE5EI6AUV9q6jqeSHTcLexgsVx4Q4It+SteGCzQ2BGNcIdXXUt4Gwfq33c+G3+NuIT5wrwWd9OD113QfmH4FjZeCJbHkHql0pd+zTCRlJodNCNp1m5xzOUUabZR4O/ZnPlu66u1eR+JFcujMn8UJCIEW56GnfeU3+i8bgz3GeJy7i8+EvfBWTz9XtxuCIWqQoZM/VXHmsv6d6PFFGb5Dk0z+GTzD7KFMDUVASIqnASJvfmNYUlGN4Rmk86LAYaoX0I4yNaGYnIBm+ZeHvrCNunPsyH2R2SKuFMIBlgYqcUyoIka15+jz+WhkKvyQOX+gjDid4ckZFQ==; s=purelymail1; d=purelymail.com; v=1; bh=J3AjVDX1lXR4hMM7xwvgtHJ0IKFDxOCh6rCV/eiLd40=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Aqib Javaid Subject: [RFC PATCH v6 31/43] altp2m: Add altp2m_view_is_{valid,visible} Date: Mon, 20 Apr 2026 16:20:14 -0400 Message-Id: <20260420202026.208110-3-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420202026.208110-1-Rose.Spangler@purelymail.com> References: <20260420202026.208110-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-ebf023/1776716434-2A37F3FF-05C10323/0/0 X-purgate-type: clean X-purgate-size: 3592 From: Rose Spangler This commit adds arch independent helper functions to determine whether a view is valid or visible. This makes it possible to determine whether a view is valid and/or visible in common altp2m routines (namely, altp2m_init_by_id). This is commit 2/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. These functions could be used to replace the equivalent calls in x86 code if that would be preferred. For now, they are only used in common code. The altp2m_view_is_valid function also has overlap with the altp2m_is_ept_valid function, but that function has an additional ASSERT and check that idx < d->nr_altp2m, so I wasn't sure if that function should be repurposed for this. If renaming that function instead of introducing a new function on x86 would be preferred, then I can do that. Additionally, these functions don't have bounds checks since the functions are intended to replace code which don't have bounds checks currently. Bounds checks could be added here if that would be preferred. --- xen/arch/arm/altp2m.c | 10 ++++++++++ xen/arch/arm/include/asm/altp2m.h | 3 +++ xen/arch/x86/include/asm/altp2m.h | 10 ++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index e741648ff5a1..0e19e197e826 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -27,6 +27,16 @@ void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int id= x) v->arch.ap2m_idx =3D idx; } =20 +bool altp2m_view_is_valid(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] != =3D ALTP2M_INVALID; +} + +bool altp2m_view_is_visible(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] =3D= =3D ALTP2M_VISIBLE; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index 05beb7f698a7..fbe66ad5536d 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -30,6 +30,9 @@ static inline bool altp2m_supported(void) uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx); =20 +bool altp2m_view_is_valid(struct domain *d, unsigned int idx); +bool altp2m_view_is_visible(struct domain *d, unsigned int idx); + /* The current state of an altp2m view */ enum altp2m_view_state { ALTP2M_INVALID, diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 43dd5d2acd9c..56ae19b24b42 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -65,6 +65,16 @@ static inline void altp2m_set_vcpu_idx(struct vcpu *v, u= nsigned int idx) vcpu_altp2m(v).p2midx =3D idx; } =20 +static inline bool altp2m_view_is_valid(struct domain *d, unsigned int idx= ) +{ + return d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] !=3D mfn= _x(INVALID_MFN); +} + +static inline bool altp2m_view_is_visible(struct domain *d, unsigned int i= dx) +{ + return d->arch.altp2m_visible_eptp[array_index_nospec(idx, MAX_EPTP)] = !=3D mfn_x(INVALID_MFN); +} + /* * Alternate p2m: shadow p2m tables used for alternate memory views */ --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:30:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:30:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287344.1567800 (Exim 4.92) (envelope-from ) id 1wEvGD-0004IQ-UO; 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s=purelymail1; d=purelymail.com; v=1; bh=1n2x3Sc6bG4P+vvG8u+e4XEkaninvIkxhNvSvfMquGM=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 32/43] x86/altp2m: Add altp2m_set_view_visibility_locked Date: Mon, 20 Apr 2026 16:30:09 -0400 Message-Id: <20260420203020.208184-1-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-16d1c6/1776717024-9047FD75-D9307B76/0/0 X-purgate-type: clean X-purgate-size: 2593 From: Rose Spangler This commit splits the altp2m_set_view_visibility into two functions, where the altp2m_set_view_visibility_locked variant has the preconditions that the altp2m lock is held. This makes it possible to change a view's visibility in an architecture independent way in code that already holds the altp2m lock (namely, altp2m_flush). This is commit 3/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 4 ++++ xen/arch/x86/mm/altp2m.c | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/a= ltp2m.h index 56ae19b24b42..99c4cfa5a68b 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -106,6 +106,10 @@ int altp2m_change_gfn(struct domain *d, unsigned int i= dx, gfn_t old_gfn, int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, uint8_t visible); =20 +/* Set a specific p2m view visibility (with lock already held) */ +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2= m_idx, + uint8_t visible); + /* * Looks up altp2m entry. If the entry is not found it looks up the entry = in * hostp2m. diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 0542e3ef9196..8672b8c061d3 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -685,9 +685,19 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, b= ool *suppress_ve, int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, uint8_t visible) { - int rc =3D 0; + int rc; =20 altp2m_lock(d); + rc =3D altp2m_set_view_visibility_locked(d, altp2m_idx, visible); + altp2m_unlock(d); + + return rc; +} + +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2= m_idx, + uint8_t visible) +{ + int rc =3D 0; =20 if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) rc =3D -EINVAL; @@ -698,8 +708,6 @@ int altp2m_set_view_visibility(struct domain *d, unsign= ed int altp2m_idx, d->arch.altp2m_visible_eptp[array_index_nospec(altp2m_idx, MAX_EPT= P)] =3D mfn_x(INVALID_MFN); =20 - altp2m_unlock(d); - return rc; } =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 20:30:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 20:30:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287346.1567809 (Exim 4.92) (envelope-from ) id 1wEvGG-0004WB-4h; Mon, 20 Apr 2026 20:30:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287346.1567809; Mon, 20 Apr 2026 20:30:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvGG-0004W2-1z; Mon, 20 Apr 2026 20:30:28 +0000 Received: by outflank-mailman (input) for mailman id 1287346; Mon, 20 Apr 2026 20:30:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEvGE-0004QR-K2 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 20:30:26 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEvGE-004xrJ-0s for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 22:30:26 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e68cd1-5cb7-0a2a0a5109dd-0a2a450995c4-18 for ; Mon, 20 Apr 2026 22:30:26 +0200 Received: from [34.202.193.197] (helo=sendmail.purelymail.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e68ce0-2497-0a2a45090019-22cac1c5b5c6-3 for ; Mon, 20 Apr 2026 22:30:25 +0200 Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -1174183712; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 20 Apr 2026 20:30:23 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=purelymail1 header.d=purelymail.com header.i="@purelymail.com" header.h="Feedback-ID:Received:From:To:Subject:Date" DKIM-Signature: a=rsa-sha256; b=oGwrXRxo+8rDytkzsBudPYgJAfDqFQFXgDhS5gjW/b3psLDpu2NSmxb6pCHEMrOZhmr3L4qbYtWaHh5vp/lz1GE1/fssqthRgZ9gQ6tFT6XnT8e9UtLRxsie9BOwnO1nw8a3+M+oUGxNH6Db8bBNJMBGxgTxO20I8Uwsk56LEaWAmbQFgXKzQYs3bT9oqq/gcNnYrXHY8jnMwaT7rGN07EyTCU996y9N+Kwbe2CdGQZQJejGvy/jn/awCC/5cFsAz2GEmqeLPpkovzRRzIaYFR5yhEt67ar1ss7WN99XHxvJxHg4GPzU9KIVJABRweWWtTnftRdbkPU2trqzItrV+w==; s=purelymail1; d=purelymail.com; v=1; bh=Lr/7jgBlmzXiiMhb4wIsFSy3Z++fKD5Dugfwfpq6hO8=; h=Feedback-ID:Received:From:To:Subject:Date; Feedback-ID: 685805:22403:null:purelymail X-Pm-Original-To: xen-devel@lists.xenproject.org From: Rose.Spangler@purelymail.com To: xen-devel@lists.xenproject.org Cc: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 33/43] arm/altp2m: Add altp2m_set_view_visibility{,_locked} support Date: Mon, 20 Apr 2026 16:30:10 -0400 Message-Id: <20260420203020.208184-2-Rose.Spangler@purelymail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420203020.208184-1-Rose.Spangler@purelymail.com> References: <20260420203020.208184-1-Rose.Spangler@purelymail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by Purelymail Content-Type: text/plain; charset=UTF-8 X-purgate-ID: tlsNG-bad1c0/1776717025-93175A53-A29C2BAD/0/0 X-purgate-type: clean X-purgate-size: 2633 From: Rose Spangler This commit adds the altp2m_set_view_visibility and altp2m_set_view_visibility_locked functions on ARM. This makes it possible to set the altp2m view visibility in common altp2m routines (namely, altp2m_flush). This is commit 4/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/altp2m.c | 30 ++++++++++++++++++++++++++++++ xen/arch/arm/include/asm/altp2m.h | 8 ++++++++ 2 files changed, 38 insertions(+) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 0e19e197e826..aa48c17e11a3 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -37,6 +37,36 @@ bool altp2m_view_is_visible(struct domain *d, unsigned i= nt idx) return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] =3D= =3D ALTP2M_VISIBLE; } =20 +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) +{ + int rc; + + altp2m_lock(d); + rc =3D altp2m_set_view_visibility_locked(d, altp2m_idx, visible); + altp2m_unlock(d); + + return rc; +} + +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2= m_idx, + uint8_t visible) +{ + int rc =3D 0; + + if ( altp2m_idx >=3D d->nr_altp2m || !altp2m_view_is_valid(d, altp2m_i= dx) ) + rc =3D -EINVAL; + else if ( visible ) + d->arch.altp2m_state[array_index_nospec(altp2m_idx, d->nr_altp2m)]= =3D + ALTP2M_VISIBLE; + else + d->arch.altp2m_state[array_index_nospec(altp2m_idx, d->nr_altp2m)]= =3D + ALTP2M_INVISIBLE; + + return rc; +} + + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/a= ltp2m.h index fbe66ad5536d..f8d0dd799a4a 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -40,6 +40,14 @@ enum altp2m_view_state { ALTP2M_INVISIBLE, }; =20 +/* Set a specific p2m view visibility */ +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + +/* Set a specific p2m view visibility (with lock already held) */ +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2= m_idx, + uint8_t visible); + #else /* CONFIG_ALTP2M */ =20 static inline bool altp2m_supported(void) --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:16:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:16:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287405.1567817 (Exim 4.92) (envelope-from ) id 1wEvyQ-0003fO-Dy; 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Smith" , Rahul Singh , "Julien Grall" Subject: [RESEND RFC PATCH v6 00/43] altp2m: Move altp2m routines to common code and add ARM support Date: Mon, 20 Apr 2026 17:11:04 -0400 Message-ID: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDA:EE_|PH0PR08MB10955:EE_|SA2PEPF00001507:EE_|DS0PR08MB9112:EE_ X-MS-Office365-Filtering-Correlation-Id: 7321a47b-d8a7-4ff4-3fa4-08de9f2161ff X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162111799003|82310400026|36860700016|7416014|376014|1800799024|13003099007|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: w5Dl3amvpy/karG7QPIgn0SDd3oIgyp8U0DbJgIEOkHT4tgfX40xoNW3gV0XyYrMOHRUOCKjn3bpxG9DhKG7Kc3HOxRXv8EKzoaQZYnIi+Iiz49840ZZUlA9TXaU1BLZHYc9Shzw/AdNpxGwwDU755bU+s2PE/8Y3Vyc/cSMI8ZHl1zGEOHdIiAV/msNGhriIdjK6ls38G3caddwLN++NJSW6UhsgbSKRCXRfwWvKjPrEHDOGcCnKtjpUHILyMjQ5Rba11pxwAkeO4g7ywwirvnU6KRq80DctBj6mSADKl+H+OqVyzZ75PWBuqPVjOrp2TLK4QSRN6HtBF8h9fGTHz3A6xUFbaxOGvIJjxRn8WbTpW6wQk4K/GyG6ueLjAguY/0geTmAn0X4Q9fg5i4Ap40E7cx9dKCB4+0sy4ed/TRJsBPgWnnzOM4Aul7YuCWO X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:11:25.7094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7321a47b-d8a7-4ff4-3fa4-08de9f2161ff X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB9112 X-purgate-ID: tlsNG-c1860d/1776719500-3A577DB1-B783FF80/0/0 X-purgate-type: clean X-purgate-size: 9546 Hi all, For the past few months, myself and Aqib Javid have been working to port altp2m to ARM with support from Stewart Hildebrand and Stefano Stabellini. At the recent Spring Xen Summit, Aqib and Stewart gave a presentation which discussed the motivation behind this, along with an overview of the rebasing and testing process. While this effort started as a rebase[1] of the v5 patch series[2] by Sergej Proskurin and Tamas Lengyel, I have been reworking the branch to make most of the altp2m code common between x86 and ARM. This should address the major concerns that came up during review of the original patch series. For a quick overview of altp2m functionality and scope of the patch series, here's an excerpt from Sergej's cover letter: > In this patch series, we provide an implementation of the altp2m > subsystem for ARM. Our implementation is based on the altp2m subsystem for > x86, providing additional --alternate-- views on the guest's physical > memory by means of the ARM 2nd stage translation mechanism. The patches > introduce new HVMOPs and extend the p2m subsystem. [...] To be more > precise, altp2m allows to create and switch to additional p2m views (i.e. > gfn to mfn mappings). These views can be manipulated and activated as will > through the provided HVMOPs. In this way, the active guest instance in > question can seamlessly proceed execution without noticing that anything > has changed. As of right now, I've reworked patch series up through the HVMOP_altp2m_set_domain_state command and plan to continue implementing the remaining altp2m features. I've continued the patch series versioning by labeling my notes as v6, and the patch notes from v1-v5 have been preserved where applicable. I am hoping for some feedback on the general approach I've taken with this patch series, and I can incorporate any changes requested into the actual patch series submission. This is a pretty big patch series, so I've tried to make it as easy as possible to follow. I've tried to minimize the number of changes in each patch; there are quite a lot of patches so if it would be preferred to combine some patches I can do so. Here is the general approach I used throughout the patch series to turn x86 altp2m code into common altp2m code with ARM support: - Move function(s) from arch/x86/mm/altp2m.c to common/altp2m.c, gating declarations/definitions with #ifdef CONFIG_X86 - Add any additional features to ARM code needed to implement these functions - Make any changes necessary to functions to support ARM, and remove #ifdef CONFIG_X86 This approach makes it possible to separate out code movement patches from the actual changes needed to support ARM. Furthermore, each patch in the patch series still compiles for both x86 and ARM. Additionally, I've split the patch series into a number of "phases" to make it easier to understand the context of each patch. Each patch description indicates which phase it's a part of. - Preparation (8 commits) - Common do_altp2m_op (2 commits) - get_domain_state (1 commit) - altp2m_{init,teardown} routines (12 commits) - altp2m_{get,set}_altp2m (4 commits) - Needed for altp2m_vcpu_{initialise,destroy} - altp2m_vcpu_{initialise,destroy} (2 commits) - Needed for HVMOP_set_domain_state - altp2m view visibility (5 commits) - Needed for altp2m_init_by_id, altp2m_flush - altp2m_activate_altp2m (2 commits) - Needed for altp2m_init_by_id - altp2m_init_by_id (2 commits) - Needed for HVMOP_altp2m_set_domain_state - altp2m_reset_altp2m (2 commits) - Needed for altp2m_flush - altp2m_flush (2 commits) - Needed for HVMOP_altp2m_set_domain_state - set_domain_state (1 commit) The code for this patch series can also be found on GitLab: https://gitlab.com/xen-project/people/elektrobit/xen/-/tree/altp2m-arm-rework-rfc Best, Rose Spangler [1] Rebase of original patch series: https://gitlab.com/xen-project/people/elektrobit/xen/-/commits/altp2m-arm-rebase [2] Original patch series: v1: https://lore.kernel.org/xen-devel/20160704114605.10086-1-proskurin@sec.in.tum.de/ v2: https://lore.kernel.org/xen-devel/20160801171028.11615-1-proskurin@sec.in.tum.de/ v3: https://lore.kernel.org/xen-devel/20160816221714.22041-1-proskurin@sec.in.tum.de/ v4: https://lore.kernel.org/xen-devel/20170830183258.14612-1-proskurin@sec.in.tum.de/ v5 was never submitted to mailing list, but is available on GitHub: https://github.com/sergej-proskurin/xen/tree/arm-altp2m-v5 (Resend due to threading issues in first send attempt) Rose Spangler (38): altp2m: Add template common altp2m.c/altp2m.h altp2m: Move altp2m_active to common domain struct altp2m: Move altp2m_p2m to common domain struct x86/altp2m: Rename hvm_altp2m_supported to altp2m_supported altp2m: Move altp2m_supported to arch header arm/altp2m: Add template arch-specific altp2m.c/altp2m.h arm/altp2m: Introduce CONFIG_ALTP2M Kconfig option altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h altp2m: Move do_altp2m_op to common code altp2m: Add ARM support to do_altp2m_op arm/altp2m: Add support for HVMOP_altp2m_get_domain_state x86/p2m: Move p2m_{init,free}_one declarations to arch header x86/altp2m: Add lock functions accessible from common code altp2m: Move altp2m_{init,teardown} to common code arm/p2m: Allocate hostp2m with xzalloc arm/p2m: Move hostp2m init/teardown to individual functions arm/p2m: Invalidate root page table entries and flush TLB in p2m_flush_table arm/altp2m: Add support for altp2m init/teardown routines altp2m: Move altp2m_{get,set}_altp2m to common code arm/altp2m: Add altp2m index to arch_vcpu altp2m: Add altp2m_set_vcpu_idx arm/altp2m: Add support for altp2m_{get,set}_altp2m altp2m: Move altp2m_vcpu_{initialise,destroy} to common code arm/altp2m: Add support for altp2m_vcpu_{initialise,destroy} arm/altp2m: Add altp2m view validity/visibility indicator altp2m: Add altp2m_view_is_{valid,visible} x86/altp2m: Add altp2m_set_view_visibility_locked arm/altp2m: Add altp2m_set_view_visibility{,_locked} support arm/altp2m: Add support for HVMOP_altp2m_set_visibility x86/altp2m: Add altp2m_activate_altp2m declaration to arch header arm/altp2m: Add support for altp2m_activate_altp2m altp2m: Move altp2m_init_by_id to common code arm/altp2m: Add support for altp2m_init_by_id x86/altp2m: Add altp2m_reset_altp2m declaration to arch header arm/altp2m: Add altp2m_reset_altp2m routine altp2m: Move altp2m_flush to common code arm/altp2m: Add support for altp2m_flush arm/p2m: Add support for HVMOP_altp2m_set_domain_state Sergej Proskurin (5): arm/p2m: Cosmetic fix - substitute _gfn(ULONG_MAX) for INVALID_GFN arm/p2m: Change function prototype of p2m_alloc_table arm/p2m: Rename parameter in p2m_alloc_vmid arm/p2m: Change func prototype and impl of p2m_{alloc,free}_vmid arm/p2m: Introduce p2m_is_{hostp2m,altp2m} xen/arch/arm/Kconfig | 11 + xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 122 +++++ xen/arch/arm/domain.c | 2 +- xen/arch/arm/hvm.c | 9 + xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 84 ++++ xen/arch/arm/include/asm/domain.h | 19 +- xen/arch/arm/include/asm/p2m.h | 41 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 162 ++++++- xen/arch/arm/p2m.c | 31 +- xen/arch/arm/traps.c | 2 +- xen/arch/x86/domain.c | 3 +- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 413 +---------------- xen/arch/x86/hvm/monitor.c | 3 +- xen/arch/x86/hvm/vmx/vmx.c | 9 +- xen/arch/x86/include/asm/altp2m.h | 115 ++++- xen/arch/x86/include/asm/domain.h | 5 - xen/arch/x86/include/asm/hvm/hvm.h | 11 - xen/arch/x86/include/asm/p2m.h | 112 +---- xen/arch/x86/mm/altp2m.c | 242 +++------- xen/arch/x86/mm/hap/hap.c | 17 +- xen/arch/x86/mm/mem_access.c | 22 +- xen/arch/x86/mm/mem_sharing.c | 3 +- xen/arch/x86/mm/p2m-basic.c | 7 +- xen/arch/x86/mm/p2m-ept.c | 13 +- xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 9 +- xen/arch/x86/mm/p2m.h | 6 - xen/common/Makefile | 1 + xen/common/altp2m.c | 551 +++++++++++++++++++++++ xen/common/monitor.c | 1 + xen/common/vm_event.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- xen/include/asm-generic/altp2m.h | 5 +- xen/include/xen/altp2m.h | 98 ++++ xen/include/xen/p2m-common.h | 2 +- xen/include/xen/sched.h | 3 + 42 files changed, 1330 insertions(+), 818 deletions(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:16:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:16:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287407.1567822 (Exim 4.92) (envelope-from ) id 1wEvyQ-0003hP-Km; Mon, 20 Apr 2026 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X-MS-Exchange-CrossTenant-Network-Message-Id: 6e3a45e7-31d7-44a6-107f-08de9f219db3 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB10990 X-purgate-ID: tlsNG-720697/1776719591-8A6C4161-059C4634/0/0 X-purgate-type: clean X-purgate-size: 1801 This commit adds an empty common altp2m.c and altp2m.h file to be added to in later commits. Creating a commit with just the empty file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 1/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/common/Makefile | 1 + xen/common/altp2m.c | 12 ++++++++++++ xen/include/xen/altp2m.h | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h diff --git a/xen/common/Makefile b/xen/common/Makefile index 6018e256147f..dbe0094006df 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ALTP2M) += altp2m.o obj-$(CONFIG_ARGO) += argo.o obj-y += bitmap.o obj-bin-$(CONFIG_SELF_TESTS) += bitops.init.o diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c new file mode 100644 index 000000000000..1a4e102324d4 --- /dev/null +++ b/xen/common/altp2m.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h new file mode 100644 index 000000000000..520328fd3fa8 --- /dev/null +++ b/xen/include/xen/altp2m.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __XEN_ALTP2M_H__ +#define __XEN_ALTP2M_H__ + +#endif /* __XEN_ALTP2M_H__ */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:17:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:17:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287427.1567836 (Exim 4.92) (envelope-from ) id 1wEvzT-0004fC-3l; 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client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , "Michal Orzel" , Julien Grall , "Stefano Stabellini" , Tamas K Lengyel Subject: [RFC PATCH v6 02/43] altp2m: Move altp2m_active to common domain struct Date: Mon, 20 Apr 2026 17:16:37 -0400 Message-ID: <20260420211637.208503-1-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> References: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|DM6PR08MB6427:EE_|BL6PEPF0002256E:EE_|CO6PR08MB7771:EE_ X-MS-Office365-Filtering-Correlation-Id: c2abedaa-3679-4253-044c-08de9f22294e X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162011799003|36860700016|1800799024|7416014|376014|82310400026|13003099007|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZGnHesQTMak874m5yD+kvevsHbLvRsxZhIwOmSnkNxNyQii/+xAwvr4cSbI2IFTSEqnroZ6d9xQf7m5OhJXLVwPZbXw2lyOX+xJZgpAOQH3N8VAMLms5fsthHvpMBoex0LL2OhTj5oLsa84V+hiqTto521Dx4KR0E321oPXJ5RBPni5sM6gB32+XTuCVexVAUMlR2HzH7BDN7s4wb6oUUA3H86On2/x7lvbK1lUXo6mq19edEVCYhw8OhykL9ZtKv42PEbj7etMv27L8xy/UYH3ym1xeTWXHMuGtL+cKWgWpcVvki41lOIr5Ms7c/WgDA3TsUS4GHFRV6+gsCGT0lT2eKBnXOlfq1iy67+mmtQN5jkZMcPgr0LyNW3IMyQHyVuz5B+ihYw3u2/56YCwS1AlsISI0c2yl9nTuVNHvfn1cWZYAsUWh2pTpD+K3l1Y0 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:16:59.9803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2abedaa-3679-4253-044c-08de9f22294e X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR08MB7771 X-purgate-ID: tlsNG-c1860d/1776719828-C2368DB1-EB01C23D/0/0 X-purgate-type: clean X-purgate-size: 10620 This commit moves altp2m_active from arch_domain on x86 to the common domain struct. Similarly to nr_altp2m, this is not an arch-specific value. Moving it to common code allows the common altp2m routines introduced later in this patch series to operate on altp2m_active without needing an altp2m_active member on arch_domain for each architecture supporting altp2m. This is commit 2/8 of the preparation phase. This commit is a refactor, and no change in functionality is intended. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 11 ++++++----- xen/arch/x86/hvm/monitor.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 ----------- xen/arch/x86/include/asm/domain.h | 2 -- xen/arch/x86/mm/altp2m.c | 1 + xen/arch/x86/mm/hap/hap.c | 5 +++-- xen/arch/x86/mm/mem_access.c | 1 + xen/arch/x86/mm/mem_sharing.c | 1 + xen/arch/x86/mm/p2m-ept.c | 1 + xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 1 + xen/common/monitor.c | 1 + xen/include/asm-generic/altp2m.h | 8 -------- xen/include/xen/altp2m.h | 19 +++++++++++++++++++ xen/include/xen/sched.h | 2 ++ 17 files changed, 40 insertions(+), 28 deletions(-) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index f3aae158e9f8..9a9b89a232e6 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -9,6 +9,7 @@ * Keir Fraser */ +#include #include #include #include diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4a81afce02e7..86c12c0d1ef4 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -7,6 +7,7 @@ * Copyright (c) 2008, Citrix Systems, Inc. */ +#include #include #include #include @@ -4612,7 +4613,7 @@ static int do_altp2m_op( if ( (a.cmd != HVMOP_altp2m_get_domain_state) && (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->arch.altp2m_active ) + !d->altp2m_active ) { rc = -EOPNOTSUPP; goto out; @@ -4657,11 +4658,11 @@ static int do_altp2m_op( if ( rc ) break; - ostate = d->arch.altp2m_active; - d->arch.altp2m_active = !!a.u.domain_state.state; + ostate = d->altp2m_active; + d->altp2m_active = !!a.u.domain_state.state; /* If the alternate p2m state has changed, handle appropriately */ - if ( d->arch.altp2m_active != ostate && + if ( d->altp2m_active != ostate && (ostate || !(rc = p2m_init_altp2m_by_id(d, 0))) ) { for_each_vcpu( d, v ) @@ -4676,7 +4677,7 @@ static int do_altp2m_op( p2m_flush_altp2m(d); } else if ( rc ) - d->arch.altp2m_active = false; + d->altp2m_active = false; domain_unpause_except_self(d); break; diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index d22a2e464460..84c1c2234ca9 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -22,6 +22,7 @@ * this program; If not, see . */ +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 269ca5643346..ff895f7f9437 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4,6 +4,7 @@ * Copyright (c) 2004, Intel Corporation. */ +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 9c1ac3cc2676..ad5ded833a75 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,12 +28,6 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, mfn_x(INVALID_MFN); } -/* Alternate p2m HVM on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - return d->arch.altp2m_active; -} - static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -64,11 +58,6 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, return false; } -static inline bool altp2m_active(const struct domain *d) -{ - return false; -} - /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index 385a6666dafa..0cf0c0d92087 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,8 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; #ifdef CONFIG_ALTP2M - /* altp2m: allow multiple copies of host p2m */ - bool altp2m_active; struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 0bc9b9ad2f52..08db8f37c1b1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mm-locks.h" diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5d3..3d563b3bc2d1 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -7,6 +7,7 @@ * Parts of this code are Copyright (c) 2007 by XenSource Inc. */ +#include #include #include #include @@ -528,7 +529,7 @@ int hap_enable(struct domain *d, u32 mode) goto out; } - d->arch.altp2m_active = false; + d->altp2m_active = false; } #endif /* CONFIG_ALTP2M */ @@ -595,7 +596,7 @@ void hap_teardown(struct domain *d, bool *preempted) for_each_vcpu ( d, v ) altp2m_vcpu_disable_ve(v); - d->arch.altp2m_active = false; + d->altp2m_active = false; FREE_XENHEAP_PAGE(d->arch.altp2m_eptp); FREE_XENHEAP_PAGE(d->arch.altp2m_visible_eptp); diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e55e53f44c78..a9d6b081a523 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -9,6 +9,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include /* copy_from_guest() */ #include #include diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 5c7a0ff30e8b..8319733b1bb6 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -8,6 +8,7 @@ * Copyright (c) 2009 Citrix Systems, Inc. (Grzegorz Milos) */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index dfdbfa0afec8..ed850723f5fd 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -4,6 +4,7 @@ * Copyright (c) 2007, Intel Corporation. */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-pt.c b/xen/arch/x86/mm/p2m-pt.c index 5a6ce2f8bc2e..17f38aac14d5 100644 --- a/xen/arch/x86/mm/p2m-pt.c +++ b/xen/arch/x86/mm/p2m-pt.c @@ -12,6 +12,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index fddecdf978ec..41517765c5ec 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/common/monitor.c b/xen/common/monitor.c index d5c9ff1cbf8c..e758a3fea9f1 100644 --- a/xen/common/monitor.c +++ b/xen/common/monitor.c @@ -19,6 +19,7 @@ * License along with this program; If not, see . */ +#include #include #include #include diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/altp2m.h index 39865a842ab3..ecee6942f4e8 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -4,16 +4,8 @@ #include -struct domain; struct vcpu; -/* Alternate p2m on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - /* Not implemented on GENERIC. */ - return false; -} - /* Alternate p2m VCPU */ static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 520328fd3fa8..b3b21124dd7e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,4 +2,23 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ +#include + +#ifdef CONFIG_ALTP2M + +/* Alternate p2m HVM on/off per domain */ +static inline bool altp2m_active(const struct domain *d) +{ + return d->altp2m_active; +} + +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_active(const struct domain *d) +{ + return false; +} + +#endif /* CONFIG_ALTP2M */ + #endif /* __XEN_ALTP2M_H__ */ diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..458f2f260dd7 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -623,6 +623,8 @@ struct domain } monitor; #ifdef CONFIG_ALTP2M + /* altp2m: allow multiple copies of host p2m */ + bool altp2m_active; unsigned int nr_altp2m; /* Number of altp2m tables. */ #endif -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:19:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:19:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287441.1567845 (Exim 4.92) (envelope-from ) id 1wEw1G-0005TP-H7; Mon, 20 Apr 2026 21:19:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287441.1567845; Mon, 20 Apr 2026 21:19:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEw1G-0005TI-E1; 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Even if other architectures always support altp2m at a hardware level (like ARM), altp2m might not be supported due to CONFIG_ALTP2M being disabled. Therefore, the altp2m_supported function can be implemented on all architectures to indicate if the hardware supports altp2m *and* if CONFIG_ALTP2M is enabled. This is commit 4/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/hvm.c | 6 +++--- xen/arch/x86/include/asm/hvm/hvm.h | 4 ++-- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/p2m-basic.c | 4 ++-- xen/arch/x86/mm/p2m-ept.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1d458f1372e5..512b18d4010f 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -698,7 +698,7 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) if ( altp2m_mode ) { - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) { dprintk(XENLOG_INFO, "altp2m is not supported\n"); return -EINVAL; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 86c12c0d1ef4..bc35efdf2c02 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1692,7 +1692,7 @@ void hvm_vcpu_destroy(struct vcpu *v) ioreq_server_remove_vcpu_all(v->domain, v); - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) altp2m_vcpu_destroy(v); nestedhvm_vcpu_destroy(v); @@ -4566,7 +4566,7 @@ static int do_altp2m_op( int rc = 0; uint64_t mode; - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; if ( copy_from_guest(&a, arg, 1) ) @@ -4965,7 +4965,7 @@ static int compat_altp2m_op( struct xen_hvm_altp2m_op *altp2m_op; } nat; - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; if ( copy_from_guest(&a, arg, 1) ) diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index e7c1364802f8..6406bb687718 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -702,7 +702,7 @@ static inline bool hvm_hap_supported(void) } /* returns true if hardware supports alternate p2m's */ -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; } @@ -876,7 +876,7 @@ static inline bool hvm_hap_supported(void) return false; } -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return false; } diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 6918a00a2a25..563eba3c0d36 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -501,7 +501,7 @@ int hap_enable(struct domain *d, u32 mode) } #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { /* Init alternate p2m data */ if ( (d->arch.altp2m_eptp = alloc_xenheap_page()) == NULL ) @@ -546,7 +546,7 @@ void hap_final_teardown(struct domain *d) unsigned int i; #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) for ( i = 0; i < d->nr_altp2m; i++ ) p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif @@ -590,7 +590,7 @@ void hap_teardown(struct domain *d, bool *preempted) #ifdef CONFIG_ALTP2M /* Leave the root pt in case we get further attempts to modify the p2m. */ - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { if ( altp2m_active(d) ) for_each_vcpu ( d, v ) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index e126fda26760..ce14066fedaf 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } - rc = hvm_altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc = altp2m_supported() ? p2m_init_altp2m(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -197,7 +197,7 @@ void p2m_final_teardown(struct domain *d) { if ( is_hvm_domain(d) ) { - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) p2m_teardown_altp2m(d); /* * We must tear down nestedp2m unconditionally because diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ddb4c7606be1..84159198f3a0 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -995,7 +995,7 @@ out: if ( is_epte_present(&old_entry) ) ept_free_entry(p2m, &old_entry, target); - if ( hvm_altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) + if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { ret = p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); if ( !rc ) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:19:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:19:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287442.1567854 (Exim 4.92) (envelope-from ) id 1wEw1H-0005h8-NU; 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This is commit 5/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 +++++++++++ xen/arch/x86/include/asm/hvm/hvm.h | 11 ----------- xen/include/asm-generic/altp2m.h | 7 +++++++ 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 512b18d4010f..e4f1cbf3b51e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -39,6 +39,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index ad5ded833a75..07e760f60659 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,6 +28,12 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, mfn_x(INVALID_MFN); } +/* returns true if hardware supports alternate p2m's */ +static inline bool altp2m_supported(void) +{ + return hvm_funcs.caps.altp2m; +} + static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -58,6 +64,11 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, return false; } +static inline bool altp2m_supported(void) +{ + return false; +} + /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index 6406bb687718..e6d8042831dc 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -701,12 +701,6 @@ static inline bool hvm_hap_supported(void) return hvm_funcs.caps.hap; } -/* returns true if hardware supports alternate p2m's */ -static inline bool altp2m_supported(void) -{ - return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; -} - /* Returns true if we have the minimum hardware requirements for nested virt */ static inline bool hvm_nested_virt_supported(void) { @@ -876,11 +870,6 @@ static inline bool hvm_hap_supported(void) return false; } -static inline bool altp2m_supported(void) -{ - return false; -} - static inline bool hvm_nested_virt_supported(void) { return false; diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/altp2m.h index ecee6942f4e8..a3cdbdae9953 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -6,6 +6,13 @@ struct vcpu; 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jRLoxsuohqR21r1f42+aEEmWEGpw45nncUOaZm3GjeU=; b=ChUuAdw4vp6m0/XRQ+xEY/kOcNhD9O/EkcIjc+1TlKFuf968i6j1WetoTlSu/kq4ydMW2g8sz+vo0FIWOo0eawhNRHjEOnwOJuQqBQIi6gINN21jfkr42mtb/RpOaUO0vFIm+LWi4uOux+ok8VNlsmJCgP7Vnj9NmTCP73GFThc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Aqib Javaid Subject: [RFC PATCH v6 06/43] arm/altp2m: Add template arch-specific altp2m.c/altp2m.h Date: Mon, 20 Apr 2026 17:18:30 -0400 Message-ID: <20260420211831.208600-4-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420211831.208600-1-Rose.Spangler@elektrobit.com> References: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> <20260420211831.208600-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|CYXPR08MB9211:EE_|SA2PEPF00003AE5:EE_|CO1PR08MB7676:EE_ X-MS-Office365-Filtering-Correlation-Id: ea45ce5e-ae5d-4c0e-5d84-08de9f226ede X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|18002099003|22082099003|56012099003; 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Creating a commit with just the template file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 6/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 16 +++++++++++++ xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 37 +++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 69200b27280d..d995d4ff7aa1 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_HAS_VPCI) += vpci.o obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o +obj-$(CONFIG_ALTP2M) += altp2m.o obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c new file mode 100644 index 000000000000..2bd1ff4df223 --- /dev/null +++ b/xen/arch/arm/altp2m.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.c: Alternate p2m + * + * Copyright (c) 2016 Sergej Proskurin + */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/Makefile b/xen/arch/arm/include/asm/Makefile index 4565baca6a4d..fef4dd42b6cb 100644 --- a/xen/arch/arm/include/asm/Makefile +++ b/xen/arch/arm/include/asm/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -generic-y += altp2m.h generic-y += device.h generic-y += hardirq.h generic-y += iocap.h diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h new file mode 100644 index 000000000000..ca836bae7330 --- /dev/null +++ b/xen/arch/arm/include/asm/altp2m.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.h: Alternate p2m + * + * Copyright (c) 2014, Intel Corporation. + * Copyright (c) 2016, Sergej Proskurin . + */ + +#ifndef __ASM_ARM_ALTP2M_H +#define __ASM_ARM_ALTP2M_H + +#include + +static inline bool altp2m_supported(void) +{ + /* Not implemented yet */ + return false; +} + +/* Alternate p2m VCPU */ +static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + /* Not implemented yet */ + BUG(); + return 0; +} + +#endif /* __ASM_ARM_ALTP2M_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:19:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:19:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287444.1567868 (Exim 4.92) (envelope-from ) id 1wEw1L-00060X-Cy; Mon, 20 Apr 2026 21:19:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287444.1567868; Mon, 20 Apr 2026 21:19:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEw1L-0005zt-6t; Mon, 20 Apr 2026 21:19:07 +0000 Received: by outflank-mailman (input) for mailman id 1287444; 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This makes it possible to build Xen without building altp2m code. This commit also implements a stub for p2m_altp2m_check, as some implementation is needed when CONFIG_ALTP2M is enabled. This is due to a call to p2m_altp2m_check in vm_event.c which is gated by CONFIG_ALTP2M. This is commit 7/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Kconfig | 11 +++++++++++ xen/arch/arm/altp2m.c | 9 +++++++++ xen/arch/arm/include/asm/altp2m.h | 18 ++++++++++++++++-- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..fdf0721c3c03 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -98,6 +98,17 @@ config MPU systems supporting EL2. (UNSUPPORTED) endchoice +config ALTP2M + bool "Alternate P2M support" if EXPERT + depends on MMU + default y + help + Alternate-p2m allows a guest to manage multiple p2m guest physical + "memory views" (as opposed to a single p2m). + Useful for memory introspection. + + If unsure, stay with defaults. + source "arch/Kconfig" config ACPI diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 2bd1ff4df223..8bd174ea8f37 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -5,6 +5,15 @@ * Copyright (c) 2016 Sergej Proskurin */ +#include + +/* Check to see if vcpu should be switched to a different p2m. */ +void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not yet implemented */ + BUG(); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index ca836bae7330..698c35427e75 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -11,10 +11,12 @@ #include +#ifdef CONFIG_ALTP2M + +/* Hardware always supports altp2m on ARM */ static inline bool altp2m_supported(void) { - /* Not implemented yet */ - return false; + return true; } /* Alternate p2m VCPU */ @@ -25,6 +27,18 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return 0; } +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_supported(void) +{ + return false; +} + +/* Only declaration is needed. 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2ZAemscrHmCDKhZ6RJ1poqZ5UjAED/22jekv/5eW7eQ=; b=nxaaY2nprOobJpQm5s4mRdNqkVV4NB+B2zZc3FBK37y1ANSV1NsTl3BQ/hhNNHTPw5/7MHI4sBOdC+8b2QO1WZaO8AMLobBBe0PrOZVIY+igxW/Xhq4lL0YzJ1XoLRgqglnlEb34ZkcRJpDUPvyh1OlSPjaB0Zi2GMvyu+Nu2Qg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Anthony PERARD , "Michal Orzel" , Julien Grall , "Stefano Stabellini" , Tamas K Lengyel Subject: [RFC PATCH v6 03/43] altp2m: Move altp2m_p2m to common domain struct Date: Mon, 20 Apr 2026 17:18:27 -0400 Message-ID: <20260420211831.208600-1-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> References: <20260420211104.208444-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: DS3PEPF0000C380:EE_|CH3PR08MB9950:EE_|SA2PEPF00003AE9:EE_|MWHPR08MB9872:EE_ X-MS-Office365-Filtering-Correlation-Id: d8466819-255c-4766-a98e-08de9f226da6 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eB1HgBlSeJ+cfUWwJjLt8M+D1Qw6n/Q2UfmM8/mExeOrns4se9jQzxgDKlxusHJ5ywwhrnecoyWf8/EigCliacY3j1PArB2+RQ8kWbtQ5iMvt03PfGsqcCXmwCpJFRKLOgrTKBq3WYrepL09ZSoES25Pm7BePFDOPi5GrEW7gzVJfsKLApOKg1mP9ZC5gYhFmnfAqmIx3QA+xBrtQlZN1iNMBgi9R3Drt4HkTHzSNVVF8gz/UIXkBUXODuaqK7Au4TARPpSoZdL9SmTTQAZ2vnIj/kYUnCMECTdob3qn4F6AjMeWpoVYuV+sI+2nfYhFIUl4OfUCV72HI+2RsRZvP0I9wOIcZyjipUP4GtX5WUIrnwEI2rdlsYhUUCFmG3DPebFTK0nvs96ZBGDqWBYPTYI3DSdDIfaMR7fvrXnkGuTooFEwl+LoXuapdi+zXZfq X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:18:54.7514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8466819-255c-4766-a98e-08de9f226da6 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR08MB9872 X-purgate-ID: tlsNG-d62444/1776719945-B4A11FF4-2653A649/0/0 X-purgate-type: clean X-purgate-size: 13310 Similarly to the previous commit, this commit moves altp2m_p2m to the common domain struct. The representation of altp2m views as an array of p2m_domain pointers is the same on x86 and ARM, and it seems that this would be the case for other architectures as well. This commit is a refactor, and no change in functionality is intended. This is commit 3/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/include/asm/domain.h | 1 - xen/arch/x86/include/asm/p2m.h | 4 ++-- xen/arch/x86/mm/altp2m.c | 28 ++++++++++++++-------------- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/mem_access.c | 8 ++++---- xen/arch/x86/mm/mem_sharing.c | 2 +- xen/arch/x86/mm/p2m-ept.c | 6 +++--- xen/arch/x86/mm/p2m.c | 8 ++++---- xen/include/xen/sched.h | 1 + 10 files changed, 33 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index ff895f7f9437..0909929c00e0 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -5004,7 +5004,7 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( currd->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - ept = &currd->arch.altp2m_p2m[i]->ept; + ept = &currd->altp2m_p2m[i]->ept; if ( cpumask_test_cpu(cpu, ept->invalidate) ) { cpumask_clear_cpu(cpu, ept->invalidate); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index 0cf0c0d92087..f8038087e612 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,7 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; #ifdef CONFIG_ALTP2M - struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; uint64_t *altp2m_visible_eptp; diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 3a5a5fd43c2a..ec871717a9e4 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -901,7 +901,7 @@ static inline struct p2m_domain *p2m_get_altp2m(struct vcpu *v) BUG_ON(index >= v->domain->nr_altp2m); - return v->domain->arch.altp2m_p2m[index]; + return v->domain->altp2m_p2m[index]; } /* set current alternate p2m table */ @@ -919,7 +919,7 @@ static inline bool p2m_set_altp2m(struct vcpu *v, unsigned int idx) atomic_dec(&orig->active_vcpus); vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->arch.altp2m_p2m[idx]->active_vcpus); + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); return true; } diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 08db8f37c1b1..8dd3c0f96be0 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -130,14 +130,14 @@ int p2m_init_altp2m(struct domain *d) struct p2m_domain *hostp2m = p2m_get_hostp2m(d); mm_lock_init(&d->arch.altp2m_list_lock); - d->arch.altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); + d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); - if ( !d->arch.altp2m_p2m ) + if ( !d->altp2m_p2m ) return -ENOMEM; for ( i = 0; i < d->nr_altp2m; i++ ) { - d->arch.altp2m_p2m[i] = p2m = p2m_init_one(d); + d->altp2m_p2m[i] = p2m = p2m_init_one(d); if ( p2m == NULL ) { p2m_teardown_altp2m(d); @@ -158,14 +158,14 @@ void p2m_teardown_altp2m(struct domain *d) for ( i = 0; i < d->nr_altp2m; i++ ) { - if ( !d->arch.altp2m_p2m[i] ) + if ( !d->altp2m_p2m[i] ) continue; - p2m = d->arch.altp2m_p2m[i]; - d->arch.altp2m_p2m[i] = NULL; + p2m = d->altp2m_p2m[i]; + d->altp2m_p2m[i] = NULL; p2m_free_one(p2m); } - XVFREE(d->arch.altp2m_p2m); + XVFREE(d->altp2m_p2m); } int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, @@ -325,7 +325,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned int idx, struct p2m_domain *p2m; ASSERT(idx < d->nr_altp2m); - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; p2m_lock(p2m); @@ -368,7 +368,7 @@ static int p2m_activate_altp2m(struct domain *d, unsigned int idx, ASSERT(idx < d->nr_altp2m); - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; hostp2m = p2m_get_hostp2m(d); p2m_lock(p2m); @@ -468,7 +468,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN) ) { - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; if ( !_atomic_read(p2m->active_vcpus) ) { @@ -532,7 +532,7 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, return rc; hp2m = p2m_get_hostp2m(d); - ap2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; p2m_lock(hp2m); p2m_lock(ap2m); @@ -596,7 +596,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; /* Check for a dropped page that may impact this altp2m */ if ( mfn_eq(mfn, INVALID_MFN) && @@ -679,7 +679,7 @@ int p2m_set_suppress_ve_multi(struct domain *d, return -EINVAL; p2m = ap2m = - d->arch.altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)]; } p2m_lock(host_p2m); @@ -746,7 +746,7 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, return -EINVAL; p2m = ap2m = - d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } else p2m = host_p2m; diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 3d563b3bc2d1..6918a00a2a25 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -524,7 +524,7 @@ int hap_enable(struct domain *d, u32 mode) for ( i = 0; i < d->nr_altp2m; i++ ) { - rv = p2m_alloc_table(d->arch.altp2m_p2m[i]); + rv = p2m_alloc_table(d->altp2m_p2m[i]); if ( rv != 0 ) goto out; } @@ -548,7 +548,7 @@ void hap_final_teardown(struct domain *d) #ifdef CONFIG_ALTP2M if ( hvm_altp2m_supported() ) for ( i = 0; i < d->nr_altp2m; i++ ) - p2m_teardown(d->arch.altp2m_p2m[i], true, NULL); + p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif /* Destroy nestedp2m's first */ @@ -603,7 +603,7 @@ void hap_teardown(struct domain *d, bool *preempted) for ( i = 0; i < d->nr_altp2m; i++ ) { - p2m_teardown(d->arch.altp2m_p2m[i], false, preempted); + p2m_teardown(d->altp2m_p2m[i], false, preempted); if ( preempted && *preempted ) return; } diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index a9d6b081a523..e5548e64d8d0 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -319,7 +319,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - ap2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -375,7 +375,7 @@ long p2m_set_mem_access_multi(struct domain *d, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - ap2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -438,7 +438,7 @@ int p2m_get_mem_access(struct domain *d, gfn_t gfn, xenmem_access_t *access, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - p2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -457,7 +457,7 @@ void arch_p2m_set_access_required(struct domain *d, bool access_required) unsigned int i; for ( i = 0; i < d->nr_altp2m; i++ ) { - struct p2m_domain *p2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *p2m = d->altp2m_p2m[i]; if ( p2m ) p2m->access_required = access_required; diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 8319733b1bb6..b7d8fb9ad1aa 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -919,7 +919,7 @@ static int nominate_page(struct domain *d, gfn_t gfn, for ( i = 0; i < d->nr_altp2m; i++ ) { - ap2m = d->arch.altp2m_p2m[i]; + ap2m = d->altp2m_p2m[i]; if ( !ap2m ) continue; diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ed850723f5fd..ddb4c7606be1 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -1311,7 +1311,7 @@ static void ept_set_ad_sync(struct domain *d, bool value) if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; p2m_lock(p2m); p2m->ept.ad = value; @@ -1579,7 +1579,7 @@ void __init setup_ept_dump(void) void p2m_init_altp2m_ept(struct domain *d, unsigned int i) { struct p2m_domain *p2m = - d->arch.altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); struct ept_data *ept; @@ -1603,7 +1603,7 @@ unsigned int p2m_find_altp2m_by_eptp(struct domain *d, uint64_t eptp) if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; ept = &p2m->ept; if ( eptp == ept->eptp ) diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index 41517765c5ec..5bd426296f20 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -111,7 +111,7 @@ void p2m_change_entry_type_global(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); change_entry_type_global(altp2m, ot, nt); @@ -157,7 +157,7 @@ bool p2m_memory_type_changed(struct domain *d) { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); _memory_type_changed(altp2m); @@ -955,7 +955,7 @@ void p2m_change_type_range(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); change_type_range(altp2m, start, end, ot, nt); @@ -1031,7 +1031,7 @@ int p2m_finish_type_change(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); rc = finish_type_change(altp2m, first_gfn, max_nr); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 458f2f260dd7..5d8ba2d2ab19 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -626,6 +626,7 @@ struct domain /* altp2m: allow multiple copies of host p2m */ bool altp2m_active; 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This makes it possible to use these functions in the common altp2m init/teardown routines. This is commit 1/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/p2m.h | 3 +++ xen/arch/x86/mm/p2m.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 5110b3e77807..ce8eeb751ee9 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -592,6 +592,9 @@ int p2m_alloc_table(struct p2m_domain *p2m); void p2m_teardown(struct p2m_domain *p2m, bool remove_root, bool *preempted); void p2m_final_teardown(struct domain *d); +struct p2m_domain *p2m_init_one(struct domain *d); +void p2m_free_one(struct p2m_domain *p2m); + /* Add/remove a page to/from a domain's p2m table. */ int p2m_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, unsigned int page_order, p2m_type_t t); diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 64218878067e..be8ed85c2aba 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -6,9 +6,6 @@ #ifndef __ARCH_MM_P2M_H__ #define __ARCH_MM_P2M_H__ -struct p2m_domain *p2m_init_one(struct domain *d); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6mt3ceESEHsvTznaO1cMjDFf382TVKM9D476cpVD9f7Mvbv/b7/9ZJG2l6mrRLcGWBkS/IElko37Bl04ObDzJhvapBev9LH00hX5w5EiFs9HVXa/BhLFiVyZDt4hrJBjVnIPwKp+5p1UsoTJLTHZRuqoNmPv75/JgW6YPeyIu9FDnp8Y6H/oFSo/6+r/JtXVXAu8iV0YX3LOy/zCa8Y5nPtzwfjtcqTP0iWCxWwKeYz2d1vuMsuvo0bQ3RJyh6q8mP5IQlH3NCeapb8p4eYTuC80e8w3K7wbGDPPwjBVdBj7cYnoB44CdAJQAEtjaeqmNafyKfoOadVK9mU+6PiYFlzKyKUG2sRMxrEPxQcThArF5ZcyFsqZ/Er5QozS1yzSwxDG7R/4MrEcw5G4G1+RF2HmxJ+IpOgWWZ2iOoesR6IR2Zkg3dJIiN5R25PtO+dK X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:23.0297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b1834a0-a819-4122-56ba-08de9f239c9a X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR08MB8547 X-purgate-ID: tlsNG-c201ff/1776720449-E19A5443-4A3B7F93/0/0 X-purgate-type: clean X-purgate-size: 1215 This commit adds support for the altp2m_get_domain_state HVMOP on ARM. All code used in the command implementation already works on ARM, so no further changes beyond moving the #ifdef are necessary. This is commit 1/1 of the get_domain_state phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This commit can be squashed into the previous commit for the actual submission if that would be preferred, but I thought it might be easier to understand the command #ifdef gate approach by splitting this into a separate patch. --- xen/common/altp2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 6481fae1ed12..3a3283f0860a 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -124,12 +124,12 @@ int do_altp2m_op( switch ( a.cmd ) { -#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state = altp2m_active(d); rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; +#ifdef CONFIG_X86 case HVMOP_altp2m_set_domain_state: { struct vcpu *v; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287492.1567900 (Exim 4.92) (envelope-from ) id 1wEw9W-000133-10; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2o8OXGtqE0GEM+fq0SAxupZ1zAybyGXWR+pd0QNvDe/reRh5U4c0NqpL6z2yZo9cQCQSwz+bbxXKHSrD2QWukmpa64o9axTJ8/0kZbLaHgFOut9VLzEJXYONkVgSZHofGmksRPKeNDmjOvbmhKt/UIyvJz+x++dIWAe60jaIt6HCZ3pEtTYFS0Vd23ejoatEy/H9/RDjp1TyJpreQZsupIVkN5iDrhzxAPlUjcxo7fKSijvF1B5xNZ3IXFB8pN5B4jGFdWXTEpEnBCFL+M83TkqRvx1D4mK9YptTb5CbQLR65c+Q4Iz5bPsEB/yZgduI5TVZJ/EL0luz9wfYXWSjgzLHo/6+eGPJpGjTgCIOgztFw1gwiTPy4glQrgOK2q73M+aSVLGuH/vesLinHjuqQb0eSN0R1bqjKYMPPAstBuCyRade/0SSIHd3u7suHa+1 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:24.2422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 201c0ff5-9827-4898-a539-08de9f239d51 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR08MB9906 X-purgate-ID: tlsNG-720697/1776720451-8A6C4161-4207A49B/0/0 X-purgate-type: clean X-purgate-size: 4450 This commit makes the minimum required changes necessary for do_altp2m_op to compile on ARM. All altp2m commands in the switch statement are gated by CONFIG_X86, with a default case of returning EOPNOTSUPP. This allows future commits to move the #ifdef CONFIG_X86 down as support for ARM is added. Additionally, a call to do_altp2m_op is added in the ARM HVMOP code. This is commit 2/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: Replaced patches 2 and 3 from v4/v5 patch set with this patch. Made HVM_PARAM_ALTP2M read-only, following the change to the x86 implementation in commit 0291089f6ea8. The DOMCTL to enable altp2m on ARM is implemented in a later commit in this patch series. --- xen/arch/arm/hvm.c | 9 +++++++++ xen/common/altp2m.c | 29 ++++++++++++++--------------- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/hvm.c b/xen/arch/arm/hvm.c index 86e49bf47403..7c778795a280 100644 --- a/xen/arch/arm/hvm.c +++ b/xen/arch/arm/hvm.c @@ -5,6 +5,7 @@ * Arch-specific hardware virtual machine abstractions. */ +#include #include #include #include @@ -23,6 +24,10 @@ static int hvm_allow_set_param(const struct domain *d, unsigned int param) { switch ( param ) { + /* The following parameters are read-only. */ + case HVM_PARAM_ALTP2M: + return -EEXIST; + /* * The following parameters are intended for toolstack usage only. * They may not be set by the domain. @@ -123,6 +128,10 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg) rc = -EINVAL; break; + case HVMOP_altp2m: + rc = do_altp2m_op(arg); + break; + default: { gdprintk(XENLOG_DEBUG, "HVMOP op=%lu: not implemented\n", op); diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a43b3a3e34b3..6481fae1ed12 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -9,8 +9,10 @@ #include -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) && defined(CONFIG_HVM) #include +#endif + /* * altp2m operations are envisioned as being used in several different * modes: @@ -18,13 +20,13 @@ * - external: All control and decisions are made by an external agent * running domain 0. * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. + * - internal (x86 only): altp2m operations are used exclusively by an + * in-guest agent to protect itself from the guest kernel and + * in-guest attackers. * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). + * - coordinated (x86 only): An in-guest agent handles #VE and VMFUNCs + * locally, but makes requests of an agent running outside the + * domain for bigger changes (such as modifying altp2m entires). * * This corresponds to the three values for HVM_PARAM_ALTP2M * (external, mixed, limited). All three models have advantages and @@ -97,7 +99,7 @@ int do_altp2m_op( if ( (a.cmd != HVMOP_altp2m_get_domain_state) && (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) + !altp2m_active(d) ) { rc = -EOPNOTSUPP; goto out; @@ -122,6 +124,7 @@ int do_altp2m_op( switch ( a.cmd ) { +#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state = altp2m_active(d); rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; @@ -394,9 +397,12 @@ int do_altp2m_op( rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); break; } +#endif /* CONFIG_X86 */ default: +#ifdef CONFIG_X86 ASSERT_UNREACHABLE(); +#endif rc = -EOPNOTSUPP; break; } @@ -406,13 +412,6 @@ int do_altp2m_op( return rc; } -#else -int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ - return -EOPNOTSUPP; -} -#endif /* * Local variables: -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287495.1567925 (Exim 4.92) (envelope-from ) id 1wEw9b-0001mL-Vq; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +Pt5qoZv1jQUjeMl3ulkZW0CulHOunDLfuioTnwq6v/9iYN7/DhjtEIjGAem2o9IlUySvRP3cV2oPBYyzcGoRpiEZNgizaMmLq/4Y/a2ccw1pLEpW7EsbmqjHJxlWqmVrcFFKCq9cR05c7dCknnt5ldENSsvwLtRQSCGkVWDcouypQwz4O6gB4w/SAgB/XXxxpRGYocJsQjQbn+PlUprYWxBU+hVrgqtEFRUwYEQuqs4anPjoB2BnFUq1qXzdbz45N8k8rkSZC9ljAY7xDukdFbBdeyNsClL+hk6pse2pBsqQF3jk6C1L7AxFL+7RKSiMo7xO3rBV++vsqZrcVLyF/W/gtsW6o+Vwbu23jt6HpO2P53DYhfoKQGf83lBfWGeyNCcFTubq3kWAvq2hLCeSkyoAND8WvUrXmvhwl4GlJpP+QAOEl1L4Yww1v3nhT+5 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:25.8202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4079c5c-9814-40b0-3381-08de9f239e43 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR08MB8984 X-purgate-ID: tlsNG-c1860d/1776720457-C0766DB1-F25C9B5D/0/0 X-purgate-type: clean X-purgate-size: 32242 This commit renames altp2m functions with a p2m prefix. These functions were originally defined in p2m.c, hence the p2m prefix. When they were moved to altp2m.c in commit ae7584f63678, the function names were kept and the declarations remained in p2m.h. This commit finishes that move by renaming these functions to have an altp2m prefix and moving the declarations to altp2m.h. Since these functions will either be moved to the common altp2m.c, or implemented separately for ARM, it doesn't seem to make sense to continue with this naming convention. Therefore, this commit preemptively renames the x86 implementations of these functions so they can later be implemented with altp2m function name prefixes in common code or for ARM. For convenience, here is the full list of renames: - p2m_init_altp2m -> altp2m_init - p2m_teardown_altp2m -> altp2m_teardown - p2m_flush_altp2m -> altp2m_flush - p2m_altp2m_get_or_propagate -> altp2m_get_or_propagate - p2m_altp2m_propagate_change -> altp2m_propagate_change - p2m_get_altp2m -> altp2m_get_altp2m - p2m_set_altp2m -> altp2m_set_altp2m - p2m_reset_altp2m -> altp2m_reset_altp2m - p2m_activate_altp2m -> altp2m_activate_altp2m - p2m_init_altp2m_by_id -> altp2m_init_by_id - p2m_init_next_altp2m -> altp2m_init_next_available - p2m_destroy_altp2m_by_id -> altp2m_destroy_by_id - p2m_switch_domain_altp2m_by_id -> altp2m_switch_domain_altp2m_by_id - p2m_change_altp2m_gfn -> altp2m_change_gfn - p2m_set_altp2m_view_visibility -> altp2m_set_view_visibility This commit contains only function renames and code movement, and no functional change is intended. This is commit 8/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/altp2m.c | 2 +- xen/arch/x86/hvm/hvm.c | 30 ++++---- xen/arch/x86/hvm/monitor.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 6 +- xen/arch/x86/include/asm/altp2m.h | 116 +++++++++++++++++++++++++++++- xen/arch/x86/include/asm/p2m.h | 109 ---------------------------- xen/arch/x86/mm/altp2m.c | 76 ++++++++++---------- xen/arch/x86/mm/mem_access.c | 13 ++-- xen/arch/x86/mm/p2m-basic.c | 4 +- xen/arch/x86/mm/p2m-ept.c | 4 +- xen/arch/x86/mm/p2m.h | 3 - xen/common/vm_event.c | 2 +- xen/include/xen/p2m-common.h | 2 +- 13 files changed, 186 insertions(+), 183 deletions(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 8bd174ea8f37..339f82835caf 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -8,7 +8,7 @@ #include /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { /* Not yet implemented */ BUG(); diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index bc35efdf2c02..5b6e91adce17 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1885,15 +1885,15 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla, if ( altp2m_active(currd) ) { - p2m = p2m_get_altp2m(curr); + p2m = altp2m_get_altp2m(curr); /* * Get the altp2m entry if present; or if not, propagate from * the host p2m. NB that this returns with gfn locked in the * altp2m. */ - if ( p2m_altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, - &p2ma, &page_order) ) + if ( altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, &p2ma, + &page_order) ) { /* Entry was copied from host -- retry fault */ rc = 1; @@ -2036,7 +2036,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla, paging_mark_pfn_dirty(currd, _pfn(gfn)); /* * If p2m is really an altp2m, unlock it before changing the type, - * as p2m_altp2m_propagate_change() needs to acquire the + * as altp2m_propagate_change() needs to acquire the * altp2m_list lock. */ if ( p2m != hostp2m ) @@ -4663,7 +4663,7 @@ static int do_altp2m_op( /* If the alternate p2m state has changed, handle appropriately */ if ( d->altp2m_active != ostate && - (ostate || !(rc = p2m_init_altp2m_by_id(d, 0))) ) + (ostate || !(rc = altp2m_init_by_id(d, 0))) ) { for_each_vcpu( d, v ) { @@ -4674,7 +4674,7 @@ static int do_altp2m_op( } if ( ostate ) - p2m_flush_altp2m(d); + altp2m_flush(d); } else if ( rc ) d->altp2m_active = false; @@ -4729,17 +4729,18 @@ static int do_altp2m_op( } case HVMOP_altp2m_create_p2m: - if ( !(rc = p2m_init_next_altp2m(d, &a.u.view.view, - a.u.view.hvmmem_default_access)) ) + rc = altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; case HVMOP_altp2m_destroy_p2m: - rc = p2m_destroy_altp2m_by_id(d, a.u.view.view); + rc = altp2m_destroy_by_id(d, a.u.view.view); break; case HVMOP_altp2m_switch_p2m: - rc = p2m_switch_domain_altp2m_by_id(d, a.u.view.view); + rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); break; case HVMOP_altp2m_set_suppress_ve: @@ -4871,9 +4872,9 @@ static int do_altp2m_op( if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) rc = -EINVAL; else - rc = p2m_change_altp2m_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); + rc = altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); break; case HVMOP_altp2m_get_p2m_idx: @@ -4906,8 +4907,7 @@ static int do_altp2m_op( else if ( !altp2m_active(d) ) rc = -EOPNOTSUPP; else - rc = p2m_set_altp2m_view_visibility(d, idx, - a.u.set_visibility.visible); + rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); break; } diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index 84c1c2234ca9..78137220b22a 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -182,7 +182,7 @@ int hvm_monitor_debug(unsigned long rip, enum hvm_monitor_debug_type type, #ifdef CONFIG_ALTP2M if ( curr->arch.hvm.fast_single_step.enabled ) { - p2m_altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx); + altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx); curr->arch.hvm.single_step = false; curr->arch.hvm.fast_single_step.enabled = false; curr->arch.hvm.fast_single_step.p2midx = 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0909929c00e0..f2cf95ee500e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2452,7 +2452,7 @@ static void cf_check vmx_vcpu_update_eptp(struct vcpu *v) struct ept_data *ept; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -2521,7 +2521,7 @@ static int cf_check vmx_vcpu_emulate_vmfunc(const struct cpu_user_regs *regs) if ( !cpu_has_vmx_vmfunc && altp2m_active(curr->domain) && regs->eax == 0 && - p2m_switch_vcpu_altp2m_by_id(curr, regs->ecx) ) + altp2m_switch_vcpu_by_id(curr, regs->ecx) ) rc = X86EMUL_OKAY; return rc; @@ -4277,7 +4277,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs) } } - p2m_set_altp2m(v, idx); + altp2m_set_altp2m(v, idx); } if ( vm_event_is_enabled(v) && diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 07e760f60659..9c58a396448d 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -7,12 +7,33 @@ #ifndef __ASM_X86_ALTP2M_H #define __ASM_X86_ALTP2M_H -#ifdef CONFIG_ALTP2M #include #include /* for struct vcpu, struct domain */ + +#include #include /* for vcpu_altp2m */ +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +/* Alternate p2m paging */ +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p2ma, + unsigned int *page_order); + +/* Propagate a host p2m change to all alternate p2m's */ +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma); + +#ifdef CONFIG_ALTP2M + +#define AP2MGET_prepopulate true +#define AP2MGET_query false + static inline bool altp2m_is_eptp_valid(const struct domain *d, unsigned int idx) { @@ -39,6 +60,85 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return vcpu_altp2m(v).p2midx; } +/* + * Alternate p2m: shadow p2m tables used for alternate memory views + */ + +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index = vcpu_altp2m(v).p2midx; + + if ( index == INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >= v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >= v->domain->nr_altp2m); + + if ( idx == vcpu_altp2m(v).p2midx ) + return false; + + orig = altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx = idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} + +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); + +/* Free altp2m views */ +void altp2m_teardown(struct domain *d); + +/* Switch alternate p2m for a single vcpu */ +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); + +/* Flush all the alternate p2m's for a domain */ +void altp2m_flush(struct domain *d); + +/* Make a specific alternate p2m valid */ +int altp2m_init_by_id(struct domain *d, unsigned int idx); + +/* Find an available alternate p2m and make it valid */ +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access); + +/* Make a specific alternate p2m invalid */ +int altp2m_destroy_by_id(struct domain *d, unsigned int idx); + +/* Switch alternate p2m for entire domain */ +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); + +/* Change a gfn->mfn mapping */ +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn); + +/* Set a specific p2m view visibility */ +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + +/* + * Looks up altp2m entry. If the entry is not found it looks up the entry in + * hostp2m. + * The prepopulate param is used to set the found entry in altp2m. + */ +int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *a, + bool prepopulate); + /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); @@ -69,7 +169,21 @@ static inline bool altp2m_supported(void) return false; } +static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, + gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *a) +{ + ASSERT_UNREACHABLE(); + return -EOPNOTSUPP; +} +#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ + _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) + /* Only declaration is needed. DCE will optimise it out when linking. */ +int altp2m_init(struct domain *d); +void altp2m_teardown(struct domain *d); +struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); +bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index ec871717a9e4..5110b3e77807 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -582,30 +582,6 @@ static inline gfn_t mfn_to_gfn(const struct domain *d, mfn_t mfn) return _gfn(mfn_x(mfn)); } -#ifdef CONFIG_ALTP2M -#define AP2MGET_prepopulate true -#define AP2MGET_query false - -/* - * Looks up altp2m entry. If the entry is not found it looks up the entry in - * hostp2m. - * The prepopulate param is used to set the found entry in altp2m. - */ -int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, - p2m_type_t *t, p2m_access_t *a, - bool prepopulate); -#else -static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, - gfn_t gfn, mfn_t *mfn, - p2m_type_t *t, p2m_access_t *a) -{ - ASSERT_UNREACHABLE(); - return -EOPNOTSUPP; -} -#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ - _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) -#endif - /* Init the datastructures for later use by the p2m code */ int p2m_init(struct domain *d); @@ -885,91 +861,6 @@ void shadow_p2m_init(struct p2m_domain *p2m); void cf_check nestedp2m_write_p2m_entry_post( struct p2m_domain *p2m, unsigned int oflags); -#ifdef CONFIG_ALTP2M - -/* - * Alternate p2m: shadow p2m tables used for alternate memory views - */ - -/* get current alternate p2m table */ -static inline struct p2m_domain *p2m_get_altp2m(struct vcpu *v) -{ - unsigned int index = vcpu_altp2m(v).p2midx; - - if ( index == INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >= v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool p2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >= v->domain->nr_altp2m); - - if ( idx == vcpu_altp2m(v).p2midx ) - return false; - - orig = p2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - -/* Switch alternate p2m for a single vcpu */ -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx); - -/* Flush all the alternate p2m's for a domain */ -void p2m_flush_altp2m(struct domain *d); - -/* Make a specific alternate p2m valid */ -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Find an available alternate p2m and make it valid */ -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access); - -/* Make a specific alternate p2m invalid */ -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Switch alternate p2m for entire domain */ -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Change a gfn->mfn mapping */ -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn); - -/* Set a specific p2m view visibility */ -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_idx, - uint8_t visible); - -#else /* !CONFIG_ALTP2M */ -struct p2m_domain *p2m_get_altp2m(struct vcpu *v); -bool p2m_set_altp2m(struct vcpu *v, unsigned int idx); -#endif /* CONFIG_ALTP2M */ - -/* - * Common alternate p2m declarations that need to be visible - * regardless of CONFIG_ALTP2M - */ - -/* Alternate p2m paging */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_order); - -/* Propagate a host p2m change to all alternate p2m's */ -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma); #endif /* CONFIG_HVM */ /* p2m access to IOMMU flags */ diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 8dd3c0f96be0..2dc84b76b8c1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -24,7 +24,7 @@ altp2m_vcpu_initialise(struct vcpu *v) vcpu_pause(v); vcpu_altp2m(v).p2midx = 0; - atomic_inc(&p2m_get_altp2m(v)->active_vcpus); + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); altp2m_vcpu_update_p2m(v); @@ -43,7 +43,7 @@ altp2m_vcpu_destroy(struct vcpu *v) if ( v != current ) vcpu_pause(v); - if ( (p2m = p2m_get_altp2m(v)) ) + if ( (p2m = altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); altp2m_vcpu_disable_ve(v); @@ -123,7 +123,7 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } -int p2m_init_altp2m(struct domain *d) +int altp2m_init(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -140,7 +140,7 @@ int p2m_init_altp2m(struct domain *d) d->altp2m_p2m[i] = p2m = p2m_init_one(d); if ( p2m == NULL ) { - p2m_teardown_altp2m(d); + altp2m_teardown(d); return -ENOMEM; } p2m->p2m_class = p2m_alternate; @@ -151,7 +151,7 @@ int p2m_init_altp2m(struct domain *d) return 0; } -void p2m_teardown_altp2m(struct domain *d) +void altp2m_teardown(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -207,13 +207,13 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, return 0; } -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { if ( altp2m_active(v->domain) ) - p2m_switch_vcpu_altp2m_by_id(v, idx); + altp2m_switch_vcpu_by_id(v, idx); } -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) { struct domain *d = v->domain; bool rc = false; @@ -225,7 +225,7 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) if ( d->arch.altp2m_eptp[idx] != mfn_x(INVALID_MFN) ) { - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); rc = 1; } @@ -246,9 +246,9 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) * the host's entry to the altp2m (retaining page order), and indicate * that the caller should re-try the faulting instruction. */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_order) +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p2ma, + unsigned int *page_order) { p2m_type_t ap2mt; p2m_access_t ap2ma; @@ -319,8 +319,8 @@ enum altp2m_reset_type { ALTP2M_DEACTIVATE }; -static void p2m_reset_altp2m(struct domain *d, unsigned int idx, - enum altp2m_reset_type reset_type) +static void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type) { struct p2m_domain *p2m; @@ -344,7 +344,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned int idx, p2m_unlock(p2m); } -void p2m_flush_altp2m(struct domain *d) +void altp2m_flush(struct domain *d) { unsigned int i; @@ -352,7 +352,7 @@ void p2m_flush_altp2m(struct domain *d) for ( i = 0; i < d->nr_altp2m; i++ ) { - p2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[i] = mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); } @@ -360,8 +360,8 @@ void p2m_flush_altp2m(struct domain *d) altp2m_list_unlock(d); } -static int p2m_activate_altp2m(struct domain *d, unsigned int idx, - p2m_access_t hvmmem_default_access) +static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access) { struct p2m_domain *hostp2m, *p2m; int rc; @@ -399,9 +399,9 @@ static int p2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_unlock(p2m); return rc; -} + } -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_init_by_id(struct domain *d, unsigned int idx) { int rc = -EINVAL; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); @@ -413,14 +413,14 @@ int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == mfn_x(INVALID_MFN) ) - rc = p2m_activate_altp2m(d, idx, hostp2m->default_access); + rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); altp2m_list_unlock(d); return rc; } -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access) +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access) { int rc = -EINVAL; unsigned int i; @@ -438,7 +438,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) continue; - rc = p2m_activate_altp2m(d, i, a); + rc = altp2m_activate_altp2m(d, i, a); if ( !rc ) *idx = i; @@ -450,7 +450,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, return rc; } -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_destroy_by_id(struct domain *d, unsigned int idx) { struct p2m_domain *p2m; int rc = -EBUSY; @@ -472,7 +472,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) if ( !_atomic_read(p2m->active_vcpus) ) { - p2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] = mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[array_index_nospec(idx, MAX_EPTP)] = @@ -488,7 +488,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) return rc; } -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) { struct vcpu *v; int rc = -EINVAL; @@ -506,7 +506,7 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_visible_eptp[idx] != mfn_x(INVALID_MFN) ) { for_each_vcpu( d, v ) - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); rc = 0; @@ -519,8 +519,8 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) return rc; } -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn) +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn) { struct p2m_domain *hp2m, *ap2m; p2m_access_t a; @@ -571,11 +571,11 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, p2m_unlock(ap2m); p2m_unlock(hp2m); return rc; -} + } -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma) +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma) { struct p2m_domain *p2m; unsigned int i; @@ -605,7 +605,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, { if ( !reset_count++ ) { - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); last_reset_idx = i; } else @@ -617,7 +617,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); } ret = 0; @@ -768,8 +768,8 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, return rc; } -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_idx, - uint8_t visible) +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) { int rc = 0; diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e5548e64d8d0..0492356d99ad 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -81,7 +81,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v, struct p2m_domain *p2m = NULL; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -145,7 +145,7 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, int rc; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -252,9 +252,10 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, return (p2ma != p2m_access_n2rwx); } -static int p2m_set_altp2m_mem_access(struct domain *d, struct p2m_domain *hp2m, - struct p2m_domain *ap2m, p2m_access_t a, - gfn_t gfn) +static int altp2m_set_altp2m_mem_access(struct domain *d, + struct p2m_domain *hp2m, + struct p2m_domain *ap2m, p2m_access_t a, + gfn_t gfn) { mfn_t mfn; p2m_type_t t; @@ -281,7 +282,7 @@ static int set_mem_access(struct domain *d, struct p2m_domain *p2m, if ( ap2m ) { - rc = p2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); + rc = altp2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); /* If the corresponding mfn is invalid we will want to just skip it */ if ( rc == -ESRCH ) rc = 0; diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index ce14066fedaf..433e7d08b78f 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } - rc = altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc = altp2m_supported() ? altp2m_init(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -198,7 +198,7 @@ void p2m_final_teardown(struct domain *d) if ( is_hvm_domain(d) ) { if ( altp2m_supported() ) - p2m_teardown_altp2m(d); + altp2m_teardown(d); /* * We must tear down nestedp2m unconditionally because * we initialise it unconditionally. diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index 84159198f3a0..a6f61a9dd3d7 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -773,7 +773,7 @@ bool ept_handle_misconfig(uint64_t gpa) int rc; if ( altp2m_active(curr->domain) ) - p2m = p2m_get_altp2m(curr); + p2m = altp2m_get_altp2m(curr); p2m_lock(p2m); @@ -997,7 +997,7 @@ out: if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { - ret = p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); + ret = altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); if ( !rc ) rc = ret; } diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 635f5a7f45cd..64218878067e 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -19,9 +19,6 @@ static inline int p2m_init_logdirty(struct p2m_domain *p2m) { return 0; } static inline void p2m_free_logdirty(struct p2m_domain *p2m) {} #endif -int p2m_init_altp2m(struct domain *d); -void p2m_teardown_altp2m(struct domain *d); - void p2m_flush_table_locked(struct p2m_domain *p2m); int __must_check p2m_remove_entry(struct p2m_domain *p2m, gfn_t gfn, mfn_t mfn, unsigned int page_order); diff --git a/xen/common/vm_event.c b/xen/common/vm_event.c index cf0258223f50..77e0c8a0b240 100644 --- a/xen/common/vm_event.c +++ b/xen/common/vm_event.c @@ -433,7 +433,7 @@ static int vm_event_resume(struct domain *d, struct vm_event_domain *ved) /* Check for altp2m switch */ if ( IS_ENABLED(CONFIG_ALTP2M) && rsp.flags & VM_EVENT_FLAG_ALTERNATE_P2M ) - p2m_altp2m_check(v, rsp.altp2m_idx); + altp2m_check(v, rsp.altp2m_idx); if ( rsp.flags & VM_EVENT_FLAG_SET_REGISTERS ) vm_event_set_registers(v, &rsp); diff --git a/xen/include/xen/p2m-common.h b/xen/include/xen/p2m-common.h index f0bd9a6b9896..6da330acca1f 100644 --- a/xen/include/xen/p2m-common.h +++ b/xen/include/xen/p2m-common.h @@ -25,7 +25,7 @@ int unmap_mmio_regions(struct domain *d, mfn_t mfn); /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx); +void altp2m_check(struct vcpu *v, uint16_t idx); /* * Populate-on-Demand -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287494.1567914 (Exim 4.92) (envelope-from ) id 1wEw9Y-0001OF-Oo; Mon, 20 Apr 2026 21:27:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287494.1567914; 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The functions are gated by CONFIG_X86, so there is effectively no difference despite common code normally being compiled for ARM. This commit contains only renames/code movement, and no functional change is intended. This is commit 3/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 8 ----- xen/arch/x86/mm/altp2m.c | 45 ---------------------------- xen/arch/x86/mm/p2m-basic.c | 1 + xen/common/altp2m.c | 49 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 13 ++++++++ 5 files changed, 63 insertions(+), 53 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 7cff40beb7c6..13017525a62f 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -97,12 +97,6 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) return true; } -/* Initialize altp2m views */ -int altp2m_init(struct domain *d); - -/* Free altp2m views */ -void altp2m_teardown(struct domain *d); - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); @@ -184,8 +178,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) /* Only declaration is needed. DCE will optimise it out when linking. */ -int altp2m_init(struct domain *d); -void altp2m_teardown(struct domain *d); struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 371bf3f0b8d4..46374373848d 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -123,51 +123,6 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } -int altp2m_init(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - struct p2m_domain *hostp2m = p2m_get_hostp2m(d); - - altp2m_lock_init(d); - d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); - - if ( !d->altp2m_p2m ) - return -ENOMEM; - - for ( i = 0; i < d->nr_altp2m; i++ ) - { - d->altp2m_p2m[i] = p2m = p2m_init_one(d); - if ( p2m == NULL ) - { - altp2m_teardown(d); - return -ENOMEM; - } - p2m->p2m_class = p2m_alternate; - p2m->access_required = hostp2m->access_required; - _atomic_set(&p2m->active_vcpus, 0); - } - - return 0; -} - -void altp2m_teardown(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - - for ( i = 0; i < d->nr_altp2m; i++ ) - { - if ( !d->altp2m_p2m[i] ) - continue; - p2m = d->altp2m_p2m[i]; - d->altp2m_p2m[i] = NULL; - p2m_free_one(p2m); - } - - XVFREE(d->altp2m_p2m); -} - int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index 433e7d08b78f..67cef5d2b6ef 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 3a3283f0860a..cda653b713f0 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -2,8 +2,10 @@ #include #include #include +#include #include +#include #include @@ -13,6 +15,53 @@ #include #endif +#if CONFIG_X86 +int altp2m_init(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + struct p2m_domain *hostp2m = p2m_get_hostp2m(d); + + altp2m_lock_init(d); + d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); + + if ( !d->altp2m_p2m ) + return -ENOMEM; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + d->altp2m_p2m[i] = p2m = p2m_init_one(d); + if ( p2m == NULL ) + { + altp2m_teardown(d); + return -ENOMEM; + } + p2m->p2m_class = p2m_alternate; + p2m->access_required = hostp2m->access_required; + _atomic_set(&p2m->active_vcpus, 0); + } + + return 0; +} + +void altp2m_teardown(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + if ( !d->altp2m_p2m[i] ) + continue; + p2m = d->altp2m_p2m[i]; + d->altp2m_p2m[i] = NULL; + p2m_free_one(p2m); + } + + XVFREE(d->altp2m_p2m); +} +#endif /* CONFIG_X86 */ + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index be627152668a..85ef22c2b29e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,19 @@ #include +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +#ifdef CONFIG_X86 +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yIbI7Z0q3lXJU+nOYvRW36Lh6wKWhfwhF7qmIzuTXnQ=; b=ab4jTs6bKH+CeLpBl4CEYtLc1JdhOiEVhSFGe3hBySKmdGOHp8231kY+JzTWhIQ4JtR67b+jBn3BGG+EpWZ4GDKBC+3mdKcmiAak+uCXHzNr1Br886FOv+8JlRrsPikA+IYnmSUSFinlOAl0bEirZUIeTeDTCHhhuiBrEVzk+UA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Sergej Proskurin , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH v6 16/43] arm/p2m: Cosmetic fix - substitute _gfn(ULONG_MAX) for INVALID_GFN Date: Mon, 20 Apr 2026 17:26:21 -0400 Message-ID: <20260420212648.208640-9-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|BL4PR08MB10598:EE_|CY4PEPF0000EDD6:EE_|PH0PR08MB9861:EE_ X-MS-Office365-Filtering-Correlation-Id: 325ae214-868e-43c3-f237-08de9f23a110 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: u+CJe+WNqqT5WxTzlNIvjK0f8D8w+0o/r32CIycAdJUhMPPErv6qHGVhCmhfHFDEJ+qlLlhIzRHWuB/Fx+3IINOtOcbzEfV03AR7l+F4Bp3iPxLlXRCwFl/mZHCzCZaUnUUMJTs5HHwfm8eSsegxhnuN5VWb7gJ/ywkdKfKYepz8rYpA537OOGAbndJOiHoA+yQuyNU1VawGKGgo+1DCuZpFBpRL74cjerrvPrVmvmG+GRTeeGZ2t27vwxVqNFyKmimdVbnvwotwNFRMUaCoWBDVOHI2fZ2+vc5G6jQ2k+yixZeDoEObEYm4SoWDr+Zk6V8F2xCKqBCANwhwR1u80FrMqqu9Fr0AMNvNo6PLz5L+6/nahYxVWNjr3LEvbC5A+KJtghmqK1fVOc9LwTG44rTwELVKlQDUtZzxN5nPDVUeoliijmrnGr21wFIBT3wJ X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:30.5226 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 325ae214-868e-43c3-f237-08de9f23a110 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR08MB9861 X-purgate-ID: tlsNG-d62444/1776720458-B4A11FF4-6ADA3E45/0/0 X-purgate-type: clean X-purgate-size: 999 From: Sergej Proskurin In ./xen/arch/arm/p2m.c, we compare the gfn's with INVALID_GFN throughout the code. Thus it makes sense to use the macro INVALID_GFN instead of a hard coded value to initialize "p2m->lowest_mapped_gfn". This is commit 5/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/mmu/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 3ecb969a0369..1009f10e5db4 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1517,7 +1517,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) p2m->vmid = INVALID_VMID; p2m->max_mapped_gfn = _gfn(0); - p2m->lowest_mapped_gfn = _gfn(ULONG_MAX); + p2m->lowest_mapped_gfn = INVALID_GFN; p2m->default_access = p2m_access_rwx; p2m->mem_access_enabled = false; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287501.1567939 (Exim 4.92) (envelope-from ) id 1wEw9d-00026F-Pt; Mon, 20 Apr 2026 21:27:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287501.1567939; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b5UanR2p00UfKCA6aaY9tFmf96UpwGCoxOr2tItpeAh9NvVc8czHXZSDhS5v52u8mqaeRjJY/nBCg8v+cym0AO/g1LdQNAbUMXTvjmJ2LEXW3KCby6lfdFrW25n/33ZuXqx+0n0t6JAShhRC+vmUkRgoFGXDfAvupVgVU8aINR+c/+InaNF//f/hc6u+30zNxEWg6zmdzPZhckZ3MkaO4h9HGCQdtrjM4P7MgRIXX9mOHfoZQwLJC1/dPrPND1w+kurmjT4SCnBJ0AN4fr41S+8+uxWiwM18LAf3pVhvEU4yJrl9000PkkMDsrJLBWyVVa+9bchIx2HYz5R/3jEaO/zMxLV+j3D945C09DtR2soJ1ahHrYEF4Cl18ayEHlcBybdbIOCpLQqUGY4uvM56ExQg/9hsFVW2TVq0x4HQFBcSus/KR2dTSmTCpyFsiHhx X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:21.4081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 256f584b-748e-4060-630e-08de9f239baa X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR08MB9498 X-purgate-ID: tlsNG-42698a/1776720459-0556BF3B-D9AF3AC8/0/0 X-purgate-type: clean X-purgate-size: 26338 This commit moves the altp2m HVMOP implementation to common code, making it possible to re-use it across architectures. In this commit, the entire implementation is gated behind CONFIG_X86, with no changes to the body of do_altp2m_op. A stub implementation is added for ARM, which will be removed once do_altp2m_op has been modified to add ARM support. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/x86/hvm/hvm.c | 400 ------------------------------------- xen/common/altp2m.c | 413 +++++++++++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 11 ++ 3 files changed, 424 insertions(+), 400 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5b6e91adce17..4adcc3c49d95 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4526,406 +4526,6 @@ static int hvmop_get_param( return rc; } -/* - * altp2m operations are envisioned as being used in several different - * modes: - * - * - external: All control and decisions are made by an external agent - * running domain 0. - * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. - * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). - * - * This corresponds to the three values for HVM_PARAM_ALTP2M - * (external, mixed, limited). All three models have advantages and - * disadvantages. - * - * Normally hypercalls made by a program in domain 0 in order to - * control a guest would be DOMCTLs rather than HVMOPs. But in order - * to properly enable the 'internal' use case, as well as to avoid - * fragmentation, all altp2m subops should come under this single - * HVMOP. - * - * Note that 'internal' mode (HVM_PARAM_ALTP2M == XEN_ALTP2M_mixed) - * has not been evaluated for safety from a security perspective. - * Before using this mode in a security-critical environment, each - * subop should be evaluated for safety, with unsafe subops - * blacklisted in xsm_hvm_altp2mhvm_op(). - */ -static int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ -#ifdef CONFIG_ALTP2M - struct xen_hvm_altp2m_op a; - struct domain *d = NULL; - int rc = 0; - uint64_t mode; - - if ( !altp2m_supported() ) - return -EOPNOTSUPP; - - if ( copy_from_guest(&a, arg, 1) ) - return -EFAULT; - - if ( a.pad1 || a.pad2 || - (a.version != HVMOP_ALTP2M_INTERFACE_VERSION) ) - return -EINVAL; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - case HVMOP_altp2m_set_domain_state: - case HVMOP_altp2m_vcpu_enable_notify: - case HVMOP_altp2m_vcpu_disable_notify: - case HVMOP_altp2m_create_p2m: - case HVMOP_altp2m_destroy_p2m: - case HVMOP_altp2m_switch_p2m: - case HVMOP_altp2m_set_suppress_ve: - case HVMOP_altp2m_set_suppress_ve_multi: - case HVMOP_altp2m_get_suppress_ve: - case HVMOP_altp2m_set_mem_access: - case HVMOP_altp2m_set_mem_access_multi: - case HVMOP_altp2m_get_mem_access: - case HVMOP_altp2m_change_gfn: - case HVMOP_altp2m_get_p2m_idx: - case HVMOP_altp2m_set_visibility: - break; - - default: - return -EOPNOTSUPP; - } - - d = rcu_lock_domain_by_any_id(a.domain); - - if ( d == NULL ) - return -ESRCH; - - if ( !is_hvm_domain(d) ) - { - rc = -EOPNOTSUPP; - goto out; - } - - if ( (a.cmd != HVMOP_altp2m_get_domain_state) && - (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) - { - rc = -EOPNOTSUPP; - goto out; - } - - mode = d->arch.hvm.params[HVM_PARAM_ALTP2M]; - - if ( XEN_ALTP2M_disabled == mode ) - { - rc = -EINVAL; - goto out; - } - - if ( d->nr_altp2m == 0 ) - { - rc = -EOPNOTSUPP; - goto out; - } - - if ( (rc = xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) - goto out; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - a.u.domain_state.state = altp2m_active(d); - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_set_domain_state: - { - struct vcpu *v; - bool ostate; - - if ( nestedhvm_enabled(d) ) - { - rc = -EINVAL; - break; - } - - rc = domain_pause_except_self(d); - if ( rc ) - break; - - ostate = d->altp2m_active; - d->altp2m_active = !!a.u.domain_state.state; - - /* If the alternate p2m state has changed, handle appropriately */ - if ( d->altp2m_active != ostate && - (ostate || !(rc = altp2m_init_by_id(d, 0))) ) - { - for_each_vcpu( d, v ) - { - if ( !ostate ) - altp2m_vcpu_initialise(v); - else - altp2m_vcpu_destroy(v); - } - - if ( ostate ) - altp2m_flush(d); - } - else if ( rc ) - d->altp2m_active = false; - - domain_unpause_except_self(d); - break; - } - - case HVMOP_altp2m_vcpu_enable_notify: - { - struct vcpu *v; - - if ( a.u.enable_notify.pad || - a.u.enable_notify.vcpu_id >= d->max_vcpus ) - { - rc = -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc = -EOPNOTSUPP; - break; - } - - v = d->vcpu[a.u.enable_notify.vcpu_id]; - - rc = altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); - break; - } - - case HVMOP_altp2m_vcpu_disable_notify: - { - struct vcpu *v; - - if ( a.u.disable_notify.vcpu_id >= d->max_vcpus ) - { - rc = -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc = -EOPNOTSUPP; - break; - } - - v = d->vcpu[a.u.enable_notify.vcpu_id]; - - altp2m_vcpu_disable_ve(v); - break; - } - - case HVMOP_altp2m_create_p2m: - rc = altp2m_init_next_available(d, &a.u.view.view, - a.u.view.hvmmem_default_access); - if ( !rc ) - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_destroy_p2m: - rc = altp2m_destroy_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_switch_p2m: - rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_set_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc = -EINVAL; - else - { - gfn_t gfn = _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx = a.u.suppress_ve.view; - bool suppress_ve = a.u.suppress_ve.suppress_ve; - - rc = p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); - } - break; - - case HVMOP_altp2m_set_suppress_ve_multi: - { - uint64_t max_phys_addr = (1UL << d->arch.cpuid->extd.maxphysaddr) - 1; - - a.u.suppress_ve_multi.last_gfn = min(a.u.suppress_ve_multi.last_gfn, - max_phys_addr); - - if ( a.u.suppress_ve_multi.pad1 || - a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_gfn ) - rc = -EINVAL; - else - { - rc = p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); - if ( (!rc || rc == -ERESTART) && __copy_to_guest(arg, &a, 1) ) - rc = -EFAULT; - } - break; - } - - case HVMOP_altp2m_get_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc = -EINVAL; - else - { - gfn_t gfn = _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx = a.u.suppress_ve.view; - bool suppress_ve; - - rc = p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); - if ( !rc ) - { - a.u.suppress_ve.suppress_ve = suppress_ve; - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_set_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc = -EINVAL; - else - rc = p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0, - a.u.mem_access.access, - a.u.mem_access.view); - break; - - case HVMOP_altp2m_set_mem_access_multi: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.set_mem_access_multi.pad || - a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr ) - { - rc = -EINVAL; - break; - } - - /* - * Unlike XENMEM_access_op_set_access_multi, we don't need any bits of - * the 'continuation' counter to be zero (to stash a command in). - * However, 0x40 is a good 'stride' to make sure that we make - * a reasonable amount of forward progress before yielding, - * so use a mask of 0x3F here. - */ - rc = p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_list, - a.u.set_mem_access_multi.access_list, - a.u.set_mem_access_multi.nr, - a.u.set_mem_access_multi.opaque, - 0x3F, - a.u.set_mem_access_multi.view); - if ( rc > 0 ) - { - a.u.set_mem_access_multi.opaque = rc; - rc = -ERESTART; - if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp2m_op_t), - &a, u.set_mem_access_multi.opaque) ) - rc = -EFAULT; - } - break; - - case HVMOP_altp2m_get_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc = -EINVAL; - else - { - xenmem_access_t access; - - rc = p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access, - a.u.mem_access.view); - if ( !rc ) - { - a.u.mem_access.access = access; - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_change_gfn: - if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) - rc = -EINVAL; - else - rc = altp2m_change_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); - break; - - case HVMOP_altp2m_get_p2m_idx: - { - struct vcpu *v; - - if ( !altp2m_active(d) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( (v = domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) == NULL ) - { - rc = -EINVAL; - break; - } - - a.u.get_vcpu_p2m_idx.altp2m_idx = altp2m_vcpu_idx(v); - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - } - - case HVMOP_altp2m_set_visibility: - { - unsigned int idx = a.u.set_visibility.altp2m_idx; - - if ( a.u.set_visibility.pad ) - rc = -EINVAL; - else if ( !altp2m_active(d) ) - rc = -EOPNOTSUPP; - else - rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); - break; - } - - default: - ASSERT_UNREACHABLE(); - rc = -EOPNOTSUPP; - break; - } - - out: - rcu_unlock_domain(d); - - return rc; -#else /* !CONFIG_ALTP2M */ - return -EOPNOTSUPP; -#endif /* CONFIG_ALTP2M */ -} - DEFINE_XEN_GUEST_HANDLE(compat_hvm_altp2m_op_t); /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 1a4e102324d4..a43b3a3e34b3 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -1,5 +1,418 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include + +#include + +#include + +#include + +#ifdef CONFIG_X86 +#include +/* + * altp2m operations are envisioned as being used in several different + * modes: + * + * - external: All control and decisions are made by an external agent + * running domain 0. + * + * - internal: altp2m operations are used exclusively by an in-guest + * agent to protect itself from the guest kernel and in-guest + * attackers. + * + * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, + * but makes requests of an agent running outside the domain for + * bigger changes (such as modifying altp2m entires). + * + * This corresponds to the three values for HVM_PARAM_ALTP2M + * (external, mixed, limited). All three models have advantages and + * disadvantages. + * + * Normally hypercalls made by a program in domain 0 in order to + * control a guest would be DOMCTLs rather than HVMOPs. But in order + * to properly enable the 'internal' use case, as well as to avoid + * fragmentation, all altp2m subops should come under this single + * HVMOP. + * + * Note that 'internal' mode (HVM_PARAM_ALTP2M == XEN_ALTP2M_mixed) + * has not been evaluated for safety from a security perspective. + * Before using this mode in a security-critical environment, each + * subop should be evaluated for safety, with unsafe subops + * blacklisted in xsm_hvm_altp2mhvm_op(). + */ +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + struct xen_hvm_altp2m_op a; + struct domain *d = NULL; + int rc = 0; + uint64_t mode; + + if ( !altp2m_supported() ) + return -EOPNOTSUPP; + + if ( copy_from_guest(&a, arg, 1) ) + return -EFAULT; + + if ( a.pad1 || a.pad2 || + (a.version != HVMOP_ALTP2M_INTERFACE_VERSION) ) + return -EINVAL; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + case HVMOP_altp2m_set_domain_state: + case HVMOP_altp2m_vcpu_enable_notify: + case HVMOP_altp2m_vcpu_disable_notify: + case HVMOP_altp2m_create_p2m: + case HVMOP_altp2m_destroy_p2m: + case HVMOP_altp2m_switch_p2m: + case HVMOP_altp2m_set_suppress_ve: + case HVMOP_altp2m_set_suppress_ve_multi: + case HVMOP_altp2m_get_suppress_ve: + case HVMOP_altp2m_set_mem_access: + case HVMOP_altp2m_set_mem_access_multi: + case HVMOP_altp2m_get_mem_access: + case HVMOP_altp2m_change_gfn: + case HVMOP_altp2m_get_p2m_idx: + case HVMOP_altp2m_set_visibility: + break; + + default: + return -EOPNOTSUPP; + } + + d = rcu_lock_domain_by_any_id(a.domain); + + if ( d == NULL ) + return -ESRCH; + + if ( !is_hvm_domain(d) ) + { + rc = -EOPNOTSUPP; + goto out; + } + + if ( (a.cmd != HVMOP_altp2m_get_domain_state) && + (a.cmd != HVMOP_altp2m_set_domain_state) && + !d->altp2m_active ) + { + rc = -EOPNOTSUPP; + goto out; + } + + mode = d->arch.hvm.params[HVM_PARAM_ALTP2M]; + + if ( XEN_ALTP2M_disabled == mode ) + { + rc = -EINVAL; + goto out; + } + + if ( d->nr_altp2m == 0 ) + { + rc = -EOPNOTSUPP; + goto out; + } + + if ( (rc = xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) + goto out; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + a.u.domain_state.state = altp2m_active(d); + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_set_domain_state: + { + struct vcpu *v; + bool ostate; + + if ( nestedhvm_enabled(d) ) + { + rc = -EINVAL; + break; + } + + rc = domain_pause_except_self(d); + if ( rc ) + break; + + ostate = d->altp2m_active; + d->altp2m_active = !!a.u.domain_state.state; + + /* If the alternate p2m state has changed, handle appropriately */ + if ( d->altp2m_active != ostate && + (ostate || !(rc = altp2m_init_by_id(d, 0))) ) + { + for_each_vcpu( d, v ) + { + if ( !ostate ) + altp2m_vcpu_initialise(v); + else + altp2m_vcpu_destroy(v); + } + + if ( ostate ) + altp2m_flush(d); + } + else if ( rc ) + d->altp2m_active = false; + + domain_unpause_except_self(d); + break; + } + + case HVMOP_altp2m_vcpu_enable_notify: + { + struct vcpu *v; + + if ( a.u.enable_notify.pad || + a.u.enable_notify.vcpu_id >= d->max_vcpus ) + { + rc = -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc = -EOPNOTSUPP; + break; + } + + v = d->vcpu[a.u.enable_notify.vcpu_id]; + + rc = altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); + break; + } + + case HVMOP_altp2m_vcpu_disable_notify: + { + struct vcpu *v; + + if ( a.u.disable_notify.vcpu_id >= d->max_vcpus ) + { + rc = -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc = -EOPNOTSUPP; + break; + } + + v = d->vcpu[a.u.enable_notify.vcpu_id]; + + altp2m_vcpu_disable_ve(v); + break; + } + + case HVMOP_altp2m_create_p2m: + rc = altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_destroy_p2m: + rc = altp2m_destroy_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_switch_p2m: + rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_set_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc = -EINVAL; + else + { + gfn_t gfn = _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx = a.u.suppress_ve.view; + bool suppress_ve = a.u.suppress_ve.suppress_ve; + + rc = p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); + } + break; + + case HVMOP_altp2m_set_suppress_ve_multi: + { + uint64_t max_phys_addr = (1UL << d->arch.cpuid->extd.maxphysaddr) - 1; + + a.u.suppress_ve_multi.last_gfn = min(a.u.suppress_ve_multi.last_gfn, + max_phys_addr); + + if ( a.u.suppress_ve_multi.pad1 || + a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_gfn ) + rc = -EINVAL; + else + { + rc = p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); + if ( (!rc || rc == -ERESTART) && __copy_to_guest(arg, &a, 1) ) + rc = -EFAULT; + } + break; + } + + case HVMOP_altp2m_get_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc = -EINVAL; + else + { + gfn_t gfn = _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx = a.u.suppress_ve.view; + bool suppress_ve; + + rc = p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); + if ( !rc ) + { + a.u.suppress_ve.suppress_ve = suppress_ve; + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_set_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc = -EINVAL; + else + rc = p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0, + a.u.mem_access.access, + a.u.mem_access.view); + break; + + case HVMOP_altp2m_set_mem_access_multi: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.set_mem_access_multi.pad || + a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr ) + { + rc = -EINVAL; + break; + } + + /* + * Unlike XENMEM_access_op_set_access_multi, we don't need any bits of + * the 'continuation' counter to be zero (to stash a command in). + * However, 0x40 is a good 'stride' to make sure that we make + * a reasonable amount of forward progress before yielding, + * so use a mask of 0x3F here. + */ + rc = p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_list, + a.u.set_mem_access_multi.access_list, + a.u.set_mem_access_multi.nr, + a.u.set_mem_access_multi.opaque, + 0x3F, + a.u.set_mem_access_multi.view); + if ( rc > 0 ) + { + a.u.set_mem_access_multi.opaque = rc; + rc = -ERESTART; + if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp2m_op_t), + &a, u.set_mem_access_multi.opaque) ) + rc = -EFAULT; + } + break; + + case HVMOP_altp2m_get_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc = -EINVAL; + else + { + xenmem_access_t access; + + rc = p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access, + a.u.mem_access.view); + if ( !rc ) + { + a.u.mem_access.access = access; + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_change_gfn: + if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) + rc = -EINVAL; + else + rc = altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); + break; + + case HVMOP_altp2m_get_p2m_idx: + { + struct vcpu *v; + + if ( !altp2m_active(d) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( (v = domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) == NULL ) + { + rc = -EINVAL; + break; + } + + a.u.get_vcpu_p2m_idx.altp2m_idx = altp2m_vcpu_idx(v); + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + } + + case HVMOP_altp2m_set_visibility: + { + unsigned int idx = a.u.set_visibility.altp2m_idx; + + if ( a.u.set_visibility.pad ) + rc = -EINVAL; + else if ( !altp2m_active(d) ) + rc = -EOPNOTSUPP; + else + rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); + break; + } + + default: + ASSERT_UNREACHABLE(); + rc = -EOPNOTSUPP; + break; + } + + out: + rcu_unlock_domain(d); + + return rc; +} +#else +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} +#endif /* * Local variables: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index b3b21124dd7e..be627152668a 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,8 +2,12 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ +#include +#include #include +#include + #ifdef CONFIG_ALTP2M /* Alternate p2m HVM on/off per domain */ @@ -12,6 +16,8 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } +int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); + #else /* CONFIG_ALTP2M */ static inline bool altp2m_active(const struct domain *d) @@ -19,6 +25,11 @@ static inline bool altp2m_active(const struct domain *d) return false; } +static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_ALTP2M */ #endif /* __XEN_ALTP2M_H__ */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287504.1567953 (Exim 4.92) (envelope-from ) id 1wEw9g-0002cq-Cf; Mon, 20 Apr 2026 21:27:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287504.1567953; Mon, 20 Apr 2026 21:27:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEw9g-0002cj-96; Mon, 20 Apr 2026 21:27:44 +0000 Received: by outflank-mailman (input) for mailman id 1287504; Mon, 20 Apr 2026 21:27:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEw9e-00027J-0q for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2Fvt8Kd+xOnJoawRPR2lCMhCkX9WijTA0PWu6jPK+pBe5IW5ACIqegeHq7SVYP1aWW9Yopc18rjK02fVKPcQw7R37YULtQbyY/MJ8Wy/rXDo4XJaesHaQBLDzU3O1THL8xSLn7t2ndjjkSXpVH+r4XQMYThAyf6ZWsSskq6KKX1c9ySvwzuZFfwdCZ8D+wd/vAqxi4oEMD5484q+wHhF6iTIjrHdRR5CaSqOlKpcZgNJOznnJM1KzUEioqSqE2IEbUx0abI4clUAHw4OkIsGc7olBdhlRI012nm5oeIDWl0aM3VOKpZvcrjWc6Q0e1VlrsA4TRd29zijj+ncQ4D9h+0c57Wd2PIO8vkMbg34MZ2u/zyEjymIfnA7uHaF78IKMxN9RLdO1+9gKyC3I+KwBW/VlpfapghVIOgXgDrQjKywHGF2IHGxaJ1Is67YjjAZ X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:30.5364 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37284b46-519a-49e6-f973-08de9f23a111 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR08MB9645 X-purgate-ID: tlsNG-c1860d/1776720461-C3F7ADB1-315A97EC/0/0 X-purgate-type: clean X-purgate-size: 7264 This commit replaces the concrete p2m_domain member in arch_domain with a pointer to p2m_domain, which is allocated with xzalloc during p2m initialization. In the following commits, the altp2m_init and altp2m_teardown routines from x86 are be moved to common code. These routines (respectively) allocate and free the p2m_domain structs for altp2m views. While it would be possible to have special code paths for allocating/freeing altp2m views while keeping the hostp2m as an concrete member, this results in code duplication and increases complexity without any clear benefit. Therefore, switching the hostp2m to be allocated separately from arch_domain (similarly to x86) makes it possible to use the same functions for both allocation/teardown/freeing of the hostp2m and altp2m views. This is commit 4/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/include/asm/domain.h | 2 +- xen/arch/arm/include/asm/p2m.h | 2 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 27 +++++++++++++++++++++--- xen/arch/arm/traps.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- 9 files changed, 32 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..be824a5ba18d 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -1099,7 +1099,7 @@ int domain_relinquish_resources(struct domain *d) * We are about to free the intermediate page-tables, so clear the * root to prevent any walk to use them. */ - p2m_clear_root_pages(&d->arch.p2m); + p2m_clear_root_pages(d->arch.p2m); PROGRESS(p2m): ret = p2m_teardown(d); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..576dbdec20af 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -72,7 +72,7 @@ struct arch_domain #endif /* Virtual MMU */ - struct p2m_domain p2m; + struct p2m_domain *p2m; struct hvm_domain hvm; diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..23df91ea13e9 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -410,7 +410,7 @@ static inline int get_page_and_type(struct page_info *page, } /* get host p2m table */ -#define p2m_get_hostp2m(d) (&(d)->arch.p2m) +#define p2m_get_hostp2m(d) ((d)->arch.p2m) static inline bool p2m_vm_event_sanity_check(struct domain *d) { diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6df8b616e464..46f9363ea851 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -116,7 +116,7 @@ bool page_is_offlinable(mfn_t mfn) unsigned long domain_get_maximum_gpfn(struct domain *d) { - return gfn_x(d->arch.p2m.max_mapped_gfn); + return gfn_x(d->arch.p2m->max_mapped_gfn); } void share_xen_page_with_guest(struct page_info *page, struct domain *d, diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51abf3504fcf..3ecb969a0369 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -1475,7 +1476,7 @@ void p2m_final_teardown(struct domain *d) /* p2m not actually initialized */ if ( !p2m->domain ) - return; + goto free_p2m; /* * No need to call relinquish_p2m_mapping() here because @@ -1499,11 +1500,13 @@ void p2m_final_teardown(struct domain *d) radix_tree_destroy(&p2m->mem_access_settings, NULL); p2m->domain = NULL; + +free_p2m: + xfree(p2m); } -int p2m_init(struct domain *d) +static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); int rc; unsigned int cpu; @@ -1556,6 +1559,24 @@ int p2m_init(struct domain *d) return 0; } +int p2m_init(struct domain *d) +{ + struct p2m_domain *p2m = xzalloc(struct p2m_domain); + int rc; + + if ( !p2m ) + return -ENOMEM; + + rc = p2m_initialise(d, p2m); + + if ( !rc ) + d->arch.p2m = p2m; + else + xfree(p2m); + + return rc; +} + /* * The function will go through the p2m and remove page reference when it * is required. The mapping will be removed from the p2m. diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0c01f37ad6b4..637d27659b20 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -984,7 +984,7 @@ void vcpu_show_registers(struct vcpu *v) #endif #ifdef CONFIG_MMU - ctxt.vttbr_el2 = v->domain->arch.p2m.vttbr; + ctxt.vttbr_el2 = v->domain->arch.p2m->vttbr; #endif _show_registers(&v->arch.cpu_info->guest_cpu_user_regs, &ctxt, 1, v); diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index fa9ab9cb1330..d246c5e59005 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -565,7 +565,7 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) * Use P2M table for this Xen domain. */ ASSERT(domain->d != NULL); - ttbr = page_to_maddr(domain->d->arch.p2m.root); + ttbr = page_to_maddr(domain->d->arch.p2m->root); dev_info(domain->mmu->root->dev, "%pd: Set IPMMU context %u (pgd 0x%"PRIx64")\n", domain->d, domain->context_id, ttbr); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index bf153227dbd9..a7fbe58cba77 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1205,7 +1205,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, vtcr->tsz = 64 - p2m_ipa_bits; vtcr->sl = 2 - P2M_ROOT_LEVEL; - arm_lpae_s2_cfg.vttbr = page_to_maddr(smmu_domain->d->arch.p2m.root); + arm_lpae_s2_cfg.vttbr = page_to_maddr(smmu_domain->d->arch.p2m->root); vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); if (vmid < 0) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index d63c9015510e..0975be2562bb 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1247,7 +1247,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) /* TTBR0 */ /* Xen: The page table is shared with the P2M code */ ASSERT(smmu_domain->cfg.domain != NULL); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ct7OYHDuserQjrdnXDT2Q3J5e72VZGG2o8HBBgpiIsc=; b=BQ9mD1vz27gAQQlAgYdXw6gX4wmBMCNVTTQd2QJr/RI+F2WKhLisuIgRg4VVJxwZi8J4auyOLW6ORPM5RcU31U5jQ+Ld9RcWilXJGw8gwp1uowAwQo2b1evZrd7CRGdlrgRGlJHZdkocVFeeayPa9Q105iYfPR/PcwVuqXYhOzY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 13/43] x86/altp2m: Add lock functions accessible from common code Date: Mon, 20 Apr 2026 17:26:18 -0400 Message-ID: <20260420212648.208640-6-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|BL3PR08MB7364:EE_|SN1PEPF0002529D:EE_|DS4PR08MB10791:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ea5f87b-1d35-40c0-4c8d-08de9f239f75 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162011799003|82310400026|36860700016|376014|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HpdXB1xWVXQCLHFzYoiluWcJM9Inm13O/3QIP2PsqDXzEtOLZskBbc/SELGQqg98ll8+2RtV2u+7yJTovXONDcQaK+6wXXofZTSmURW6Og3/iKwBTdnA0zO4Lo3Ag0Ud23He9fqa5vqK9iHacqRFOSBgXeu4Ebag+oRtGMTRZoqfVm1RuLPc9vw5lexksijWlTtQTsIzTsRyBXOdDzaM3ECuSYFLSh+KitWRm2chcGnDKQZwTB+VwzdkKO6PXu8wrU12qli8Rmn7GthTh9hplNuzYn7WMwlY4hJDcKNyDxMd7Si+pi0YsoqNOc2qo4hjLhgCzEz3iudQj1kxWqnR6aIl9UT9oZGwhiBtyj2C1yCF4ra8wpK3ukFMshnH8Q3GM0kqwAu59BpRDs2hvyhPbh85XI9XGuM+ZQto1MOmXazI8St+PfzMAknrgyBaTDgH X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:27.8113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ea5f87b-1d35-40c0-4c8d-08de9f239f75 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR08MB10791 X-purgate-ID: tlsNG-33051d/1776720461-A2965938-B53D01F8/0/0 X-purgate-type: clean X-purgate-size: 6429 This commit adds three altp2m_lock functions which wrap the corresponding altp2m_list_lock functions present in "mm-locks.h". The "mm-locks.h" file is only accessible in x86 code. In order to make altp2m common across architectures, it must be possible to acquire the altp2m lock without including an x86-specific header file. These functions cannot be static inline like their "mm-locks.h" counterparts, since "mm-locks.h" is only included in source files, not header files. Therefore, these functions might introduce a slight function call overhead over their "mm-locks.h" counterparts. However, the altp2m lock is mostly used in init/teardown routines and HVMOP implementations. For these cases, the altp2m_list_lock functions have been switched out for the altp2m_lock functions so they can be later migrated to common code. The only other function using the altp2m lock is altp2m_get_or_propagate, which is in the hot path of the page fault handler, so the altp2m_list_lock calls have not been replaced for that function. This is commit 2/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This seems like the solution which makes the most sense here, but it would be nicer if it could be static inline. I'm also not sure if the "mm-locks.h" functions are really supposed to be exposed outside of their translation unit like this, so feedback on this is appreciated. --- xen/arch/x86/include/asm/altp2m.h | 4 +++ xen/arch/x86/mm/altp2m.c | 42 ++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 9c58a396448d..7cff40beb7c6 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -156,6 +156,10 @@ int p2m_set_suppress_ve_multi(struct domain *d, int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, unsigned int altp2m_idx); +void altp2m_lock_init(struct domain *d); +void altp2m_lock(struct domain *d); +void altp2m_unlock(struct domain *d); + #else static inline bool altp2m_is_eptp_valid(const struct domain *d, diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 2dc84b76b8c1..371bf3f0b8d4 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -129,7 +129,7 @@ int altp2m_init(struct domain *d) struct p2m_domain *p2m; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); - mm_lock_init(&d->arch.altp2m_list_lock); + altp2m_lock_init(d); d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); if ( !d->altp2m_p2m ) @@ -221,7 +221,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) if ( idx >= d->nr_altp2m ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[idx] != mfn_x(INVALID_MFN) ) { @@ -230,7 +230,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) rc = 1; } - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -348,7 +348,7 @@ void altp2m_flush(struct domain *d) { unsigned int i; - altp2m_list_lock(d); + altp2m_lock(d); for ( i = 0; i < d->nr_altp2m; i++ ) { @@ -357,7 +357,7 @@ void altp2m_flush(struct domain *d) d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); } - altp2m_list_unlock(d); + altp2m_unlock(d); } static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, @@ -409,13 +409,13 @@ int altp2m_init_by_id(struct domain *d, unsigned int idx) if ( idx >= d->nr_altp2m ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == mfn_x(INVALID_MFN) ) rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -431,7 +431,7 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, !xenmem_access_to_p2m_access(hostp2m, hvmmem_default_access, &a) ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); for ( i = 0; i < d->nr_altp2m; i++ ) { @@ -446,7 +446,7 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, break; } - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -463,7 +463,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int idx) return rc; rc = -EBUSY; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN) ) @@ -481,7 +481,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int idx) } } - altp2m_list_unlock(d); + altp2m_unlock(d); domain_unpause_except_self(d); @@ -501,7 +501,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) return rc; rc = -EINVAL; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_visible_eptp[idx] != mfn_x(INVALID_MFN) ) { @@ -512,7 +512,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) rc = 0; } - altp2m_list_unlock(d); + altp2m_unlock(d); domain_unpause_except_self(d); @@ -773,7 +773,7 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, { int rc = 0; - altp2m_list_lock(d); + altp2m_lock(d); if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) rc = -EINVAL; @@ -784,11 +784,23 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, d->arch.altp2m_visible_eptp[array_index_nospec(altp2m_idx, MAX_EPTP)] = mfn_x(INVALID_MFN); - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } +void altp2m_lock_init(struct domain *d) { + mm_lock_init(&d->arch.altp2m_list_lock); +} + +void altp2m_lock(struct domain *d) { + altp2m_list_lock(d); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qwOwmfrmWpA5bcreD0lLuuQUt9f7SqfexhLWTcmlGbU=; b=1Xjw1GIyJgWJ+fOWapuVo3epCodvZLGDi4BcONF4Di8p7mjNd8bQGQWkRiKR8j93EZ5M9aDCS6ECBsKhdB7IuJVKMon/0o0+nxFCaxoaanFnI7shxUc9OcuJqOca9iIouakRQnj4rBiFdxOINXu+Httkc7uSlEEQi5iy8jrpofM= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Sergej Proskurin Subject: [RFC PATCH v6 18/43] arm/p2m: Invalidate root page table entries and flush TLB in p2m_flush_table Date: Mon, 20 Apr 2026 17:26:23 -0400 Message-ID: <20260420212648.208640-11-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|LV2PR08MB972878:EE_|BL6PEPF0001AB56:EE_|CH3PR08MB9569:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ba325b9-8fc0-4e39-824b-08de9f23a202 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lDsp+67GXhvLnPeqaTu2H7Lvq5E1MbhF7hMLw4Mxa1Nm85i4ow1v4B81s7ruun80pFkV4eyd8ogyTeowxAMFHLAlheSEzMS4djgNGCyRK5oho21OzRdeODa8XQNhuR4KEpoMAqZVah3w4IA4uuF9JrF2se62b5eYy2xdv/cPbH/k1/noy0+dC+hkpZCVgNJ/dl6ub4c+MvZMZSHB5XJHvINBsgky+LW3O/bG7J7S+DPPHA8FL69WzxvcNP8lAZ/QozkHwp/pNyYtTYAj8WQrJ2bYHtutMJ/OCUs1tLDJHkG99pMs0VoHQwh7Cov89LewEV9a5cylZryrCT7t7JDOi5YqkiOaY0dCYjMYYG8Ge+pNHtn6qk8dxKCDzclmPQYkbzfEakcVRllHldE9/5DegjhENTr5w5907s2SA1kHvlynkZrqLw9RfouosdSa/FIW X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:31.9896 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ba325b9-8fc0-4e39-824b-08de9f23a202 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0001AB56.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR08MB9569 X-purgate-ID: tlsNG-ef75cf/1776720461-AD969C48-6D67B4B2/0/0 X-purgate-type: clean X-purgate-size: 4874 This commit invalidates the root page table entries and flushes the TLB when the table is flushed. The TLB is flushed to ensure that altp2m views after being reset or torn down. Previously, the code in p2m_flush_table was only used to free p2m pages during domain teardown. This function will later be used to teardown/reset altp2m views of a still-running domain, so the page table entries must be properly invalidated. Additionally, the p2m_invalidate_root function is split into p2m_invalidate_root and p2m_invalidate_root_locked. The p2m_flush_table function already holds the lock, so it calls p2m_invalidate_root_locked directly, as opposed to the existing callers which don't already hold the lock. This is commit 7/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v3: Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). v6: Introduced this patch. While the code in this patch is mostly new, it is the same in spirit as the p2m_flush_table additions in the original patch series, so the relevant comments have been reproduced above. In the v4/v5 versions of this patch series, this patch was a part of the previous patch. It has been split out to minimize the number of functionality changes in the previous patch. Additionally, the original patch series used a routine here which was nearly identical to p2m_invalidate_root, which was implemented a few years after the patch series. Therefore, the existing p2m_invalidate_root implementation is used here instead. Also, since the original patch series p2m_teardown (and by extension p2m_flush_table, as it was extracted from p2m_teardown) was made preemptible. As a consequence of this, introducing a call to p2m_invalidate_root here also means that p2m_invalidate_root and p2m_tlb_flush_sync is called each time p2m_flush_table is called, even if a previous call to p2m_flush_table was preempted. This might cause some additional overhead, as p2m_flush_table will iterate over the root page tables and flush the TLB before it can return to freeing p2m pages. I'm not sure if there's a better way of handling this, or if the overhead here is negligible/acceptable. I'm not sure how IOMMU interacts with altp2m here. I haven't looked into it extensively, so I would appreciate some feedback here. I've just copied over the iommu_use_hap_pt conditional from p2m_domain_creation_finished, but this is probably not the right behavior since we probably still need to invalidate the altp2m view page tables on flush somehow. Is the issue with invalidating root page tables when using IOMMU only relevant for the hostp2m, or is it also relevant for the altp2m views? --- xen/arch/arm/mmu/p2m.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1d598c66450b..51753bb2c34d 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1271,17 +1271,20 @@ void p2m_clear_root_pages(struct p2m_domain *p2m) * p2m_invalid_root() should not be called when the P2M is shared with * the IOMMU because it will cause IOMMU fault. */ -static void p2m_invalidate_root(struct p2m_domain *p2m) +static void p2m_invalidate_root_locked(struct p2m_domain *p2m) { unsigned int i; ASSERT(!iommu_use_hap_pt(p2m->domain)); - p2m_write_lock(p2m); - for ( i = 0; i < P2M_ROOT_PAGES; i++ ) p2m_invalidate_table(p2m, page_to_mfn(p2m->root + i)); +} +static void p2m_invalidate_root(struct p2m_domain *p2m) +{ + p2m_write_lock(p2m); + p2m_invalidate_root_locked(p2m); p2m_write_unlock(p2m); } @@ -1449,6 +1452,13 @@ int p2m_flush_table(struct p2m_domain *p2m) unsigned long count = 0; struct page_info *pg; + /* TODO: How does IOMMU interact with altp2m? */ + if ( !iommu_use_hap_pt(p2m->domain) ) + { + p2m_invalidate_root_locked(p2m); + p2m_tlb_flush_sync(p2m); + } + while ( (pg = page_list_remove_head(&p2m->pages)) ) { p2m_free_page(p2m->domain, pg); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287514.1567980 (Exim 4.92) (envelope-from ) id 1wEw9j-0003Sn-Pg; Mon, 20 Apr 2026 21:27:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287514.1567980; Mon, 20 Apr 2026 21:27:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEw9j-0003RY-KV; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: riy/kOz6frt4iKZ0TUo54SssfbLJOjpiWCcFOmxCS63vDLNLHxMimnW040OgMnogp9LSQn/xNcCPzpVa+6KnevryM8ZiujurqwgfEvMsNYO42yZPLZQW8qUHzTkp0K74X2q0XZ993qrexYdM1xO3MGsuV2rAk8vPjer215HknteRKtNJ1Lb89MM1avXP3aojEdAkAOG6U55yx3NBCg7WofReRv4UXRHUXAgY/tzzKPWZzhiMhOoKO/jKOPCFlu/lMLQWpDBwMK38TWE/igpYBQoexLxsoVnvbUCGdC+aq16K9jvtaXVxeITGeS9uLsxPCP9GFNv8BSYlqkLUwZrIimzKVHSY6hqyhG3N+yzApnFwZF4SpADCthtO3WDVSSAFoxQvplGLvXDgI/qI1df3mEOpgxRplVjBa1rE7gUOKqf4u8zfdJLuBqYrAWNxB3nZ X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:39.3790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8baa4ee8-8569-4bbf-218d-08de9f23a66a X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0001AB58.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR08MB10336 X-purgate-ID: tlsNG-720697/1776720465-83F66161-3FDD5E90/0/0 X-purgate-type: clean X-purgate-size: 1589 From: Sergej Proskurin The function "p2m_alloc_table" should be able to allocate 2nd stage translation tables not only for the host's p2m but also for alternate p2m's. This commit is a refactor and contains no functional changes. This is commit 8/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin Acked-by: Julien Grall --- v2: Removed altp2m table initialization from "p2m_table_init". v3: Removed initialization of the field d->arch.altp2m_active in "p2m_table_init" to avoid altp2m initialization throughout different files. Merged the function "p2m_alloc_table" and "p2m_table_init". --- xen/arch/arm/mmu/p2m.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51753bb2c34d..f546f63f2489 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1426,10 +1426,8 @@ static struct page_info *p2m_allocate_root(void) return page; } -static int p2m_alloc_table(struct domain *d) +static int p2m_alloc_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); - p2m->root = p2m_allocate_root(); if ( !p2m->root ) return -ENOMEM; @@ -1576,7 +1574,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) if ( rc ) return rc; - rc = p2m_alloc_table(d); + rc = p2m_alloc_table(p2m); if ( rc ) return rc; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287515.1567984 (Exim 4.92) (envelope-from ) id 1wEw9k-0003Xm-BG; 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This is commit 9/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/p2m.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index fb03978a19af..2c43b6033360 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -286,24 +286,24 @@ int p2m_alloc_vmid(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - int rc, nr; + int rc, vmid; spin_lock(&vmid_alloc_lock); - nr = find_first_zero_bit(vmid_mask, MAX_VMID); + vmid = find_first_zero_bit(vmid_mask, MAX_VMID); - ASSERT(nr != INVALID_VMID); + ASSERT(vmid != INVALID_VMID); - if ( nr == MAX_VMID ) + if ( vmid == MAX_VMID ) { rc = -EBUSY; printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain_id); goto out; } - set_bit(nr, vmid_mask); + set_bit(vmid, vmid_mask); - p2m->vmid = nr; + p2m->vmid = vmid; rc = 0; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:27:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:27:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287521.1567997 (Exim 4.92) (envelope-from ) id 1wEw9n-00049G-0c; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CYGLJEApKv3lXb6SevOviDlZ6CP8Vv2YqzswogWKNX2ODUfMpdtzhRJISh4X/8yj0mLuMOWIoeZY9dDYTFHBoMsF4evCG1USze/WwH4tVnXz+1jH9WIeMyyoxAAHd35gXBDo26FvS3IbottWai8WCRmhlH4oA+T0nrHSV+1Gisim5DDFFPKbfsmAp1pN3B7DQz6+XChzg6wjj/g5FCB5cFaDPI0CZMkeTilNLjk4q5UL1ROmntwA58Jif/tPkVIhQyhEgRxmCnVKk6Jja92QT4D//+uUW/ealNxayS7si6kRfk8qsp+JmdJVFkp7k671rSNfl672WGOvXRsySv+G5NKhmNNkyrR3pYmVk9zivHe/0czEtSOhAXGFSMLhos2KFoAO1cz50uo6g5zvlzJtwmxQBdDhRTToEAzOcHK9tNIkRIsMQKgQjCEOWgLmg+Pr X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:41.4112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5fa44b4-3540-4ec7-0a9c-08de9f23a79d X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DSSPR08MB972959 X-purgate-ID: tlsNG-33051d/1776720468-28F72938-CC9AE319/0/0 X-purgate-type: clean X-purgate-size: 3941 From: Sergej Proskurin This commit changes the prototype and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". The function "p2m_alloc_vmid" does not expect the struct domain as argument anymore and returns an allocated vmid. The function "p2m_free_vmid" takes only the vmid that is to be freed as argument. This is commit 10/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v3: Changed function prototypes and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". Changes in "p2m_alloc_vmid": This function does not expect any arguments. Also, in this commit, the function "p2m_alloc_vmid" returns either the successfully allocated vmid or the value INVALID_VMID. Thus, it is now the responsibility of the caller to set the returned vmid in the associated fields. Changes in "p2m_free_vmid": This function expects now only the vmid of type uint8_t. --- xen/arch/arm/include/asm/p2m.h | 4 ++-- xen/arch/arm/mmu/p2m.c | 8 ++++---- xen/arch/arm/p2m.c | 23 ++++++++--------------- 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 5c6dfe4a9789..62261d41e780 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -195,8 +195,8 @@ static inline bool arch_acquire_resource_check(struct domain *d) void p2m_restrict_ipa_bits(unsigned int ipa_bits); void p2m_vmid_allocator_init(void); -int p2m_alloc_vmid(struct domain *d); -void p2m_free_vmid(struct domain *d); +uint8_t p2m_alloc_vmid(void); +void p2m_free_vmid(uint8_t vmid); /* Second stage paging setup, to be called on all CPUs */ void setup_virt_paging(void); diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index f546f63f2489..0d37760ef5d5 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1519,7 +1519,7 @@ void p2m_free_one(struct p2m_domain *p2m) p2m->root = NULL; - p2m_free_vmid(p2m->domain); + p2m_free_vmid(p2m->vmid); radix_tree_destroy(&p2m->mem_access_settings, NULL); @@ -1570,9 +1570,9 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) */ p2m->domain = d; - rc = p2m_alloc_vmid(d); - if ( rc ) - return rc; + p2m->vmid = p2m_alloc_vmid(); + if ( p2m->vmid == INVALID_VMID ) + return -EBUSY; rc = p2m_alloc_table(p2m); if ( rc ) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2c43b6033360..3342fafcc8a7 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -282,11 +282,9 @@ void p2m_vmid_allocator_init(void) set_bit(INVALID_VMID, vmid_mask); } -int p2m_alloc_vmid(struct domain *d) +uint8_t p2m_alloc_vmid(void) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); - - int rc, vmid; + uint8_t vmid; spin_lock(&vmid_alloc_lock); @@ -296,28 +294,23 @@ int p2m_alloc_vmid(struct domain *d) if ( vmid == MAX_VMID ) { - rc = -EBUSY; - printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain_id); + vmid = INVALID_VMID; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: aZSD+No7Vpjq8eC+HXZ9nbtAMqsGxEaP8QH3QoKY/BCyvcequsT8YLiy2BhxIdOkB4J99oF8K/C+P9g9OaukSPAWoIIe3/wx+akvT9b2EzKY4+HdTtA9P61enKjYi3uDlA8n1Pt/DPzBQvWhboG7rYjngIDxd+QnyE4j900wxKT5N6ZLpsNWwh7ScuEF32bTvsWxD5SVv/M1EQ+sZFt5iUpqDZpJKli0O1BIfJ9wB+i0N2f+vJrehzJTkxjZ1Fv3q3nw/xtko0Sp/DnpiQ5wjZ1SwbuYKNhGa0cMmw2RsrYMMCL32nMvX6iYC7epHVdd6yqeoz2rZIJ0x5r8V4PMyqXtG8jP2RWyC7mpizogZfV1JMjJJbWPAynt+/VjulgrbKkbAn87n6nvzZ4KBjOc/WQuCb9YmMpViqaWv1Z9dyy7WePvZq/O/CyNGNEH6xI7 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:45.1508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b54807c0-55ea-468b-4acd-08de9f23a9d8 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR08MB8595 X-purgate-ID: tlsNG-ef75cf/1776720471-AC762C48-5825F5E7/0/0 X-purgate-type: clean X-purgate-size: 1730 From: Sergej Proskurin This commit adds a p2m class to the struct p2m_domain to distinguish between the host's original p2m and alternate p2m's. The need for this functionality will be shown in the following commits. This is commit 11/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v4: Change return type of p2m_is_(hostp2m|altp2m) from bool_t to bool. --- xen/arch/arm/include/asm/p2m.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 62261d41e780..8ae0cd7ff589 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -32,6 +32,11 @@ struct domain; extern void memory_type_changed(struct domain *d); +typedef enum { + p2m_host, + p2m_alternate, +} p2m_class_t; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -111,6 +116,9 @@ struct p2m_domain { /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; + + /* Choose between: host/alternate. */ + p2m_class_t p2m_class; }; /* @@ -424,6 +432,16 @@ static inline int get_page_and_type(struct page_info *page, /* get host p2m table */ #define p2m_get_hostp2m(d) ((d)->arch.p2m) +static inline bool p2m_is_hostp2m(const struct p2m_domain *p2m) +{ + return p2m->p2m_class == p2m_host; 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This make sit possible to use them in other common routines (namely, altp2m_vcpu_{initialise,destroy}). This commit contains only code movement, and no change in functionality is intended. This is commit 1/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 35 ------------------------- xen/arch/x86/include/asm/domain.h | 2 -- xen/common/altp2m.c | 1 - xen/include/xen/altp2m.h | 43 +++++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 38 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 13017525a62f..a1b078783b3e 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -64,39 +64,6 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) * Alternate p2m: shadow p2m tables used for alternate memory views */ -/* get current alternate p2m table */ -static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) -{ - unsigned int index = vcpu_altp2m(v).p2midx; - - if ( index == INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >= v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >= v->domain->nr_altp2m); - - if ( idx == vcpu_altp2m(v).p2midx ) - return false; - - orig = altp2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); @@ -178,8 +145,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) /* Only declaration is needed. DCE will optimise it out when linking. */ -struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); -bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index f8038087e612..72460e38f581 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -277,8 +277,6 @@ struct paging_vcpu { #define MAX_NR_ALTP2M MAX_EPTP #define MAX_NESTEDP2M 10 -#define INVALID_ALTP2M 0xffff - struct p2m_domain; struct time_scale { int shift; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 989d8bdcb923..a731ad7cdab8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -5,7 +5,6 @@ #include #include -#include #include diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 238c7a935586..58e74be6deb0 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,10 @@ #include +#include + +#define INVALID_ALTP2M 0xffff + /* * Common alternate p2m declarations that need to be visible * regardless of CONFIG_ALTP2M @@ -27,6 +31,41 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } +#ifdef CONFIG_X86 +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index = vcpu_altp2m(v).p2midx; + + if ( index == INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >= v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >= v->domain->nr_altp2m); + + if ( idx == vcpu_altp2m(v).p2midx ) + return false; + + orig = altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx = idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} +#endif + int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); #else /* CONFIG_ALTP2M */ @@ -41,6 +80,10 @@ static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg) return -EOPNOTSUPP; } +/* Only declaration is needed. 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OAj59kWKN8biXOebnwdzq5ky5bvMG5PNKC5Jot+tZ8s=; b=Cnyc79bWCglclRLJqu4OuHaL2TtDQnEvAXy1UAJmGr26COabSNkg1lq57qYl7gdbwQXlmuCKZWZd0Aa1aLhL+/rochiA816xuWUZwXKVRJWSNJJsfdmJm9NSeRyQcGgVhgAulYCZaErPUxmQFYT+IrDEm5pDd0Vp9dlcBfZ0jCA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Sergej Proskurin , Stefano Stabellini , Julien Grall Subject: [RFC PATCH v6 17/43] arm/p2m: Move hostp2m init/teardown to individual functions Date: Mon, 20 Apr 2026 17:26:22 -0400 Message-ID: <20260420212648.208640-10-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|DM3PR08MB9136:EE_|BL6PEPF0001AB72:EE_|SJ0PR08MB6750:EE_ X-MS-Office365-Filtering-Correlation-Id: f019f542-e825-4a2c-dc2b-08de9f23a677 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: y6iRlWMwn4VT5gL+q4gxQeo4Zb0HB1xdBkWtcg3LEDx+fe/o+9AdPB33UMZVsyaWJnTc1dAydOr0aE0paot9xTOn06HlcVBk0YQqq+y7Uw2ezrZxg0Atr1AyI7QB7R1ph7g63KVNqKBXvQr52wcG0f4LjL30AlRwsOTgLuThP95diKh8XPlMcsp+gKJ6PAYis8f6JmZPmF/YjPxYMQh//DZ5vNVs2AZqo2ZJjHRDfEyYCQEoMNdEI6XhCqTYcZBN1QY6o5NeRDBLeOwI3Z0fzg9YDrt1x3/nW9mjmuXYOcJkAMCpfvS0w5/xxxkjUrguWVuX0LopORmfvHiRcWKGYyaye6BjFq9f7a6aNu+I1qnxUGX5omKVueER9PIRVzBYfwA/fAdZSyBU/E+SvAn1TMIN6ZYA3hXbsWPZEe7SHxPY4XKSiWk+vcRScOI7SeMT X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:39.4765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f019f542-e825-4a2c-dc2b-08de9f23a677 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR08MB6750 X-purgate-ID: tlsNG-16d1c6/1776720471-CF97CD75-9EAC6CB0/0/0 X-purgate-type: clean X-purgate-size: 10132 This commit pulls out generic init/teardown functionality out of "p2m_init" and "p2m_teardown" into "p2m_init_one", "p2m_teardown_one", "p2m_free_one", and "p2m_flush_table" functions. This allows our future implementation to reuse existing code for the initialization/teardown of altp2m views. On failure, the p2m_init_one function returns a null pointer. This means p2m_init_one doesn't return an error code, which prevents it from propagating the exact error from p2m_initialise (specifically, ENOMEM if allocation fails and EBUSY if the VMID pool is exhausted). However, returning a p2m_domain pointer simplifies usage for callers of p2m_init_one, as they can receive an allocated and initialized p2m_domain without needing to handle allocation separately. Therefore, the main p2m_init function will now return ENOMEM instead of EBUSY when the VMID pool is exhausted. This is commit 6/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- Cc: Stefano Stabellini Cc: Julien Grall --- v2: Added the function p2m_flush_table to the previous version. v3: Removed struct vttbr. Moved define INVALID_VTTBR to p2m.h. Exported function prototypes of "p2m_flush_table", "p2m_init_one", and "p2m_teardown_one" in p2m.h. Extended the function "p2m_flush_table" by additionally resetting the fields lowest_mapped_gfn and max_mapped_gfn. Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. Added a check checking whether p2m->root is NULL in p2m_flush_table. Renamed the function "p2m_free_one" to "p2m_teardown_one". Removed resetting p2m->vttbr in "p2m_teardown_one", as it the p2m will be destroyed afterwards. Moved call to "p2m_alloc_table" back to "p2m_init_one". Moved the introduction of the type p2m_class_t out of this patch. Moved the backpointer to the struct domain out of the struct p2m_domain. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). Removed unnecessary initializations in the functions "p2m_init_one" and "p2m_teardown_one". Removed the define INVALID_VTTBR as it is not used any more. Cosmetic fixes. v6: Reworked to accommodate the hostp2m being allocated separately from arch_domain. Split p2m_teardown_one into p2m_teardown_one and p2m_free_one, with both having the same semantics as their x86 counterparts. The previous version of this patch also added code to p2m_flush_table. This has been split out into a separate commit to minimize the number of actual changes in this commit. Updated to account for the introduction of p2m_final_teardown. The code which previously was used to reclaim resources from the hostp2m during p2m_final_teardown was extracted into p2m_free_one. Now, p2m_final_teardown will call p2m_free_one on the hostp2m instead. The check for whether the p2m was actually initialized was moved into p2m_free_one. This means there is a slight behavior change where p2m_teardown_allocation will always be called, even if the p2m_domain was never initialized. I'm not sure if this is really a big deal (it does require the lock to be obtained, but this shouldn't be an issue at final teardown?), but if it is then I can duplicate the check from p2m_free_one to the top of p2m_final_teardown, which would replicate the previous behavior. For the sake of making the p2m_init_one function simple to use (and match the x86 function prototype), it returns a null pointer on error rather than an error code. While on x86 an error from p2m_init_one is always due to an ENOMEM return code (from xzalloc, zalloc_cpumask_var), on ARM p2m_initialise (called by p2m_init_one) can actually return EBUSY if the VMID pool is exhausted. Therefore, in this error case the null pointer return value of p2m_init_one obscures the true error code (EBUSY). Callers of p2m_init_one always return ENOMEM when p2m_init_one returns a null pointer, so this error will be propagated up as ENOMEM rather than EBUSY. The alternative to this would be to have callers pass a null **p2m_domain to p2m_init_one while still returning an integer return code. In order to preserve a common altp2m_init routine, this change would also have to be made on x86 (where there wouldn't be any real benefit, the return code is truly only ever ENOMEM). Therefore, it seems like an acceptable tradeoff to me to obscure the error in this case, but if other folks think we should handle this differently than I can revisit this. The p2m_teardown_allocation call and p2m_init_one return code changes mentioned above should be the only actual behavior changes in this patch, otherwise it should be just code movement. --- xen/arch/arm/include/asm/p2m.h | 12 ++++++ xen/arch/arm/mmu/p2m.c | 77 +++++++++++++++++++++++----------- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 23df91ea13e9..5c6dfe4a9789 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -216,6 +216,18 @@ int p2m_init(struct domain *d); int p2m_teardown(struct domain *d); void p2m_final_teardown(struct domain *d); +/* Flushes the page table held by the p2m. */ +int p2m_flush_table(struct p2m_domain *p2m); + +/* Initialize the p2m structure. */ +struct p2m_domain *p2m_init_one(struct domain *d); + +/* Release resources held by the p2m structure. */ +int p2m_teardown_one(struct p2m_domain *p2m); + +/* Free the p2m structure allocation. */ +void p2m_free_one(struct p2m_domain *p2m); + /* * Remove mapping refcount on each mapping page in the p2m * diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1009f10e5db4..1d598c66450b 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1444,14 +1444,10 @@ static int p2m_alloc_table(struct domain *d) return 0; } -int p2m_teardown(struct domain *d) +int p2m_flush_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); unsigned long count = 0; struct page_info *pg; - int rc = 0; - - p2m_write_lock(p2m); while ( (pg = page_list_remove_head(&p2m->pages)) ) { @@ -1460,23 +1456,34 @@ int p2m_teardown(struct domain *d) /* Arbitrarily preempt every 512 iterations */ if ( !(count % 512) && hypercall_preempt_check() ) { - rc = -ERESTART; - break; + return -ERESTART; } } + return 0; +} + +int p2m_teardown_one(struct p2m_domain *p2m) +{ + int rc; + + p2m_write_lock(p2m); + rc = p2m_flush_table(p2m); p2m_write_unlock(p2m); return rc; } -void p2m_final_teardown(struct domain *d) +int p2m_teardown(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - /* p2m not actually initialized */ - if ( !p2m->domain ) - goto free_p2m; + return p2m_teardown_one(p2m); +} + +void p2m_final_teardown(struct domain *d) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); /* * No need to call relinquish_p2m_mapping() here because @@ -1484,18 +1491,27 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ - ASSERT(page_list_empty(&p2m->pages)); - while ( p2m_teardown_allocation(d) == -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); + p2m_free_one(p2m); +} + +void p2m_free_one(struct p2m_domain *p2m) +{ + /* p2m not actually initialized */ + if ( !p2m->domain ) + goto free_p2m; + + ASSERT(page_list_empty(&p2m->pages)); + if ( p2m->root ) free_domheap_pages(p2m->root, P2M_ROOT_ORDER); p2m->root = NULL; - p2m_free_vmid(d); + p2m_free_vmid(p2m->domain); radix_tree_destroy(&p2m->mem_access_settings, NULL); @@ -1511,9 +1527,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) unsigned int cpu; rwlock_init(&p2m->lock); - spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&p2m->pages); - INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); p2m->vmid = INVALID_VMID; p2m->max_mapped_gfn = _gfn(0); @@ -1559,22 +1573,37 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) return 0; } -int p2m_init(struct domain *d) +struct p2m_domain *p2m_init_one(struct domain *d) { struct p2m_domain *p2m = xzalloc(struct p2m_domain); - int rc; + + if ( !p2m ) + return NULL; + + if ( !p2m_initialise(d, p2m) ) + return p2m; + + xfree(p2m); + return NULL; +} + +static int p2m_init_hostp2m(struct domain *d) +{ + struct p2m_domain *p2m = p2m_init_one(d); if ( !p2m ) return -ENOMEM; - rc = p2m_initialise(d, p2m); + d->arch.p2m = p2m; + return 0; +} - if ( !rc ) - d->arch.p2m = p2m; - else - xfree(p2m); +int p2m_init(struct domain *d) +{ + spin_lock_init(&d->arch.paging.lock); + INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); - return rc; + return p2m_init_hostp2m(d); } /* -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:28:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:28:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287549.1568026 (Exim 4.92) (envelope-from ) id 1wEw9w-0005hn-4U; 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This makes it possible to track the current altp2m view being used by a VCPU. This is commit 2/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: This patch was originally part of the "arm/p2m: Add HVMOP_altp2m_set_domain_state" patch from the v4/v5 patch series. It has been extracted into its own commit to make the patch series easier to follow. If it would be preferred, this commit can be squashed into another commit. Added support for the CONFIG_ALTP2M option. --- xen/arch/arm/include/asm/altp2m.h | 4 +--- xen/arch/arm/include/asm/domain.h | 5 +++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 5a217f48b103..bc695018e62c 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -26,9 +26,7 @@ static inline bool altp2m_supported(void) /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { - /* Not implemented yet */ - BUG(); - return 0; + return v->arch.ap2m_idx; } #else /* CONFIG_ALTP2M */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 9e69d62086cd..4d497a21b648 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -249,6 +249,11 @@ struct arch_vcpu struct vtimer virt_timer; bool vtimer_initialized; +#if CONFIG_ALTP2M + /* Alternate p2m index */ + uint16_t ap2m_idx; +#endif + /* * The full P2M may require some cleaning (e.g when emulation * set/way). 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This makes it possible to use them in the common implementation of HVMOP_altp2m_set_domain_state. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 6 ----- xen/arch/x86/mm/altp2m.c | 41 ------------------------------- xen/common/altp2m.c | 41 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 6 +++++ 4 files changed, 47 insertions(+), 47 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index b3d348386a00..43dd5d2acd9c 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -105,10 +105,6 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate); -/* Alternate p2m VCPU */ -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); @@ -151,8 +147,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 46374373848d..0542e3ef9196 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -14,47 +14,6 @@ #include "mm-locks.h" #include "p2m.h" -void -altp2m_vcpu_initialise(struct vcpu *v) -{ - if ( !v->domain->nr_altp2m ) - return; - - if ( v != current ) - vcpu_pause(v); - - vcpu_altp2m(v).p2midx = 0; - atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); - - altp2m_vcpu_update_p2m(v); - - if ( v != current ) - vcpu_unpause(v); -} - -void -altp2m_vcpu_destroy(struct vcpu *v) -{ - struct p2m_domain *p2m; - - if ( !v->domain->nr_altp2m ) - return; - - if ( v != current ) - vcpu_pause(v); - - if ( (p2m = altp2m_get_altp2m(v)) ) - atomic_dec(&p2m->active_vcpus); - - altp2m_vcpu_disable_ve(v); - - vcpu_altp2m(v).p2midx = INVALID_ALTP2M; - altp2m_vcpu_update_p2m(v); - - if ( v != current ) - vcpu_unpause(v); -} - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn) { struct domain *d = v->domain; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a731ad7cdab8..e699b64678d8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -59,6 +59,47 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } +#ifdef CONFIG_X86 +void altp2m_vcpu_initialise(struct vcpu *v) +{ + if ( !v->domain->nr_altp2m ) + return; + + if ( v != current ) + vcpu_pause(v); + + vcpu_altp2m(v).p2midx = 0; + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); + + altp2m_vcpu_update_p2m(v); + + if ( v != current ) + vcpu_unpause(v); +} + +void altp2m_vcpu_destroy(struct vcpu *v) +{ + struct p2m_domain *p2m; + + if ( !v->domain->nr_altp2m ) + return; + + if ( v != current ) + vcpu_pause(v); + + if ( (p2m = altp2m_get_altp2m(v)) ) + atomic_dec(&p2m->active_vcpus); + + altp2m_vcpu_disable_ve(v); + + vcpu_altp2m(v).p2midx = INVALID_ALTP2M; + altp2m_vcpu_update_p2m(v); + + if ( v != current ) + vcpu_unpause(v); +} +#endif + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index f5a4d0e60562..7defe6126563 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,6 +24,12 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); +#ifdef CONFIG_X86 +/* Alternate p2m VCPU */ +void altp2m_vcpu_initialise(struct vcpu *v); +void altp2m_vcpu_destroy(struct vcpu *v); +#endif + #ifdef CONFIG_ALTP2M /* Alternate p2m HVM on/off per domain */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:28:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:28:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287560.1568037 (Exim 4.92) (envelope-from ) id 1wEwA0-0006Yj-Bb; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4kOxaOL98lHbEV5pOudnNkAMwnWJxFFz3jGVAIiRzFfzxvq4rH7w3rrRd1pw+IALzigEvhoVTyQB01gS+erLnpbY+rYcUEvf+LJGIAKS+Gdw1cfJxx0ARDUNls9mk4ZFJayct5QjqTDYiYkxc1ukxxbZCYelE8UULdEzmIn4YDwEWyIJdEXHfsIDkOKgQb7oV+Invjum+Y1SsG9KyHKIXnD2jfU5xlTifN5JNIlPbOb0UfNwdZQRUDESsSwpb5XGXiF6n0RFS9nez8KNsNgpFG4zxkPkrr2gQiYG6F418T3+T+Ig2/uP/HshLigiGPAeEExrCjxOdwJvN5TRx6CUFVHUFobqUSIu1W8gy00cS6QwffCcSs7M5EAXeQk6Nd34NH7qopPNxaOdKKEbx255Bl+wrih9ZqzhfhmzuiQg31xFcCP7P091ciMenywfxQAC X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:44.4777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac698512-317e-4966-d2b4-08de9f23a970 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB9565 X-purgate-ID: tlsNG-d25034/1776720477-6D360CF5-A81DA81B/0/0 X-purgate-type: clean X-purgate-size: 7788 The p2m initialization now invokes initialization routines responsible for the allocation and initialization of altp2m structures. The same applies to teardown routines. This commit adds the prerequisites for the common altp2m_init and altp2m_teardown functions to work on ARM; No further changes were necessary other than removing the CONFIG_X86 gating. This is commit 12/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin Signed-off-by: Aqib Javaid --- v2: Shared code between host/altp2m init/teardown functions. Added conditional init/teardown of altp2m. Altp2m related functions are moved to altp2m.c v3: Removed locking the altp2m_lock in altp2m_teardown. Locking this lock at this point is unnecessary. Removed re-setting altp2m_vttbr, altp2m_p2m, and altp2m_active values in the function "altp2m_teardown". Re-setting these values is unnecessary as the entire domain will be destroyed right afterwards. Removed check for "altp2m_enabled" in "p2m_init" as altp2m has not yet been enabled by libxl at this point. Removed check for "altp2m_enabled" before tearing down altp2m within the function "p2m_teardown" so that altp2m gets destroyed even if the HVM_PARAM_ALTP2M gets reset before "p2m_teardown" is called. Added initialization of the field d->arch.altp2m_active in "altp2m_init". Removed check for already initialized vmid's in "altp2m_init_one", as "altp2m_init_one" is now called always with an uninitialized p2m. Removed the array altp2m_vttbr[] in struct arch_domain. v4: Removed initialization of altp2m_p2m[] to NULL in altp2m_init, as the "struct arch_domain" is already initialized to zero. We moved the definition of the macro MAX_ALTP2M to a common place in a separate commit. v6: Reworked to use common altp2m init and teardown routines. Added altp2m_lock_init macro for use in altp2m_init. Split altp2m initialization in p2m_init into a separate function, p2m_init_altp2m, to more easily gate code behind CONFIG_ALTP2M. Pulled in addition of active_vcpus from a later patch in the patch series. Split teardown and free of altp2m views into p2m_teardown and p2m_teardown_final (part of altp2m_teardown), respectively. --- xen/arch/arm/include/asm/altp2m.h | 4 +++ xen/arch/arm/include/asm/domain.h | 8 ++++++ xen/arch/arm/include/asm/p2m.h | 5 ++++ xen/arch/arm/mmu/p2m.c | 44 ++++++++++++++++++++++++++++++- xen/common/altp2m.c | 2 -- xen/include/xen/altp2m.h | 2 -- 6 files changed, 60 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 698c35427e75..5a217f48b103 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -19,6 +19,10 @@ static inline bool altp2m_supported(void) return true; } +#define altp2m_lock_init(d) spin_lock_init(&(d)->arch.altp2m_lock) +#define altp2m_lock(d) spin_lock(&(d)->arch.altp2m_lock) +#define altp2m_unlock(d) spin_unlock(&(d)->arch.altp2m_lock) + /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 576dbdec20af..9e69d62086cd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -128,6 +128,14 @@ struct arch_domain #endif struct resume_info resume_ctx; + +#ifdef CONFIG_ALTP2M + /* + * Lock that protects critical altp2m operations that must not be performed + * concurrently. + */ + spinlock_t altp2m_lock; +#endif } __cacheline_aligned; struct arch_vcpu diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 8ae0cd7ff589..db715c4f8bfc 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -9,6 +9,8 @@ #include #include +#include + #define paddr_bits PADDR_BITS /* Holds the bit size of IPAs in p2m tables. */ @@ -117,6 +119,9 @@ struct p2m_domain { /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; + /* Alternate p2m: count of vcpu's currently using this p2m. */ + atomic_t active_vcpus; + /* Choose between: host/alternate. */ p2m_class_t p2m_class; }; diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 0d37760ef5d5..04d17e787259 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,7 @@ #include #include +#include #include #include #include @@ -1486,6 +1488,20 @@ int p2m_teardown(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); +#ifdef CONFIG_ALTP2M + unsigned int i; + int rc; + + d->altp2m_active = false; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + rc = p2m_teardown_one(d->altp2m_p2m[i]); + if ( rc ) + return rc; + } +#endif + return p2m_teardown_one(p2m); } @@ -1499,6 +1515,9 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ + if ( altp2m_supported() ) + altp2m_teardown(d); + while ( p2m_teardown_allocation(d) == -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); @@ -1595,6 +1614,24 @@ struct p2m_domain *p2m_init_one(struct domain *d) return NULL; } +static int p2m_init_altp2m(struct domain *d) +{ +#ifdef CONFIG_ALTP2M + int rc; + + rc = altp2m_init(d); + if ( rc ) + { + p2m_free_one(p2m_get_hostp2m(d)); + return rc; + } + + d->altp2m_active = false; +#endif + + return 0; +} + static int p2m_init_hostp2m(struct domain *d) { struct p2m_domain *p2m = p2m_init_one(d); @@ -1608,10 +1645,15 @@ static int p2m_init_hostp2m(struct domain *d) int p2m_init(struct domain *d) { + int rc; spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); - return p2m_init_hostp2m(d); + rc = p2m_init_hostp2m(d); + if ( rc ) + return rc; + + return p2m_init_altp2m(d); } /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index cda653b713f0..989d8bdcb923 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -15,7 +15,6 @@ #include #endif -#if CONFIG_X86 int altp2m_init(struct domain *d) { unsigned int i; @@ -60,7 +59,6 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } -#endif /* CONFIG_X86 */ /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 85ef22c2b29e..238c7a935586 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -13,13 +13,11 @@ * regardless of CONFIG_ALTP2M */ -#ifdef CONFIG_X86 /* Initialize altp2m views */ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); 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Since the altp2m VCPU index is stored differently depending on which architecture is used, the altp2m_set_vcpu_idx function makes it possible to set this value in an architecture independent way for common code routines. This is commit 3/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/include/asm/altp2m.h | 5 +++++ xen/arch/x86/include/asm/altp2m.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index bc695018e62c..f001e022a213 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -29,6 +29,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return v->arch.ap2m_idx; } +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + v->arch.ap2m_idx = idx; +} + #else /* CONFIG_ALTP2M */ static inline bool altp2m_supported(void) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index a1b078783b3e..b3d348386a00 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -60,6 +60,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return vcpu_altp2m(v).p2midx; } +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + vcpu_altp2m(v).p2midx = idx; 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2GKS7huUjzjhqkDR3rg4P6NQTDEiD+t2h7OWKwFuOAU=; b=BLexTEX28gMTcpxZjIMstX+Hl7PtBB3G6I2t3suDP1105siAy8ia/oPfFUHevRDDQnxiM7tTXMg1fr70lLT3RCK7ix0gMmwJ7ATnp8I04LKUBKuA/2Ii486RfbtjMDyiQT/fdN9MT/hWlBbLpARSVMlq7SsNhmoVYmbrseVlYUY= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 27/43] arm/altp2m: Add support for altp2m_{get,set}_altp2m Date: Mon, 20 Apr 2026 17:26:32 -0400 Message-ID: <20260420212648.208640-20-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|LV3PR08MB9527:EE_|SA2PEPF00003F64:EE_|DS4PR08MB10703:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d1eabce-c283-4f71-80c4-08de9f23ab9e X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704161411799003|82310400026|36860700016|376014|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7o5W4k0+P0eOej6V+OLjkTYipicnkFZIpdr2V3o64ZnspMXlVL9NkZ1U7CYiZEs4m2hre41mdLO29vgBPMP1vbbVKTkH7VgsE+d9v+Sj+3n9WpnE9nieOOZGFl2nEMxWRvY4kwu8ZJC0lMR9zE6hR/YEo0eKLU+nOIRrOi6t5VKBFWd96o7ZWiP9N891xY6+G3Z/jiq47vidm7ytbwbwZFbSyxDPBAuEe8jaLEugOWs620gQ0ukQmdGZ4CRbFrzGRcu71N1ZMTcp4uhvdtOnniXWf66nfowwhwlj/MazTz/djpdKTxdjDEXhW60rOQkWI+YBlvrH7c39uH8I/X9uzMXjbIGJmKNqDWVjgFTA8F2nuSBstqZkLqjy+ZE62mc8CyworEyrDay9rrYXSjFSl3EBNmbrFKgu/gTw3mIuUz952DgDrp5huIT7uuq0ixZD X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:27:48.1604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d1eabce-c283-4f71-80c4-08de9f23ab9e X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR08MB10703 X-purgate-ID: tlsNG-bad1c0/1776720479-8BF7EA53-B364D9E8/0/0 X-purgate-type: clean X-purgate-size: 1778 This commit adds support for altp2m_get_altp2m and altp2m_set_altp2m on ARM. The x86-specific VCPU accesses have been replaced with the architecture independent functions altp2m_vcpu_idx and altp2m_set_vcpu_idx. This is commit 4/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/include/xen/altp2m.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 58e74be6deb0..f5a4d0e60562 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,7 @@ #include +#include #include #define INVALID_ALTP2M 0xffff @@ -31,11 +32,10 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } -#ifdef CONFIG_X86 /* get current alternate p2m table */ static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) { - unsigned int index = vcpu_altp2m(v).p2midx; + unsigned int index = altp2m_vcpu_idx(v); if ( index == INVALID_ALTP2M ) return NULL; @@ -52,19 +52,18 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) BUG_ON(idx >= v->domain->nr_altp2m); - if ( idx == vcpu_altp2m(v).p2midx ) + if ( idx == altp2m_vcpu_idx(v) ) return false; orig = altp2m_get_altp2m(v); BUG_ON(!orig); atomic_dec(&orig->active_vcpus); - vcpu_altp2m(v).p2midx = idx; + altp2m_set_vcpu_idx(v, idx); atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); return true; } -#endif int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:28:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:28:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287588.1568059 (Exim 4.92) (envelope-from ) id 1wEwA6-0007lA-79; Mon, 20 Apr 2026 21:28:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287588.1568059; Mon, 20 Apr 2026 21:28:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwA5-0007hX-73; Mon, 20 Apr 2026 21:28:09 +0000 Received: by outflank-mailman (input) for mailman id 1287588; Mon, 20 Apr 2026 21:28:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwA0-0006mT-VB for xen-devel@lists.xenproject.org; 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GvY1Hq4hwLu2aLmi7v9CAxN3huVX6llKANSCVnMm0ZU=; b=gBLKsFEpBpxDjZYWykV5lZuc+vLLAJwJYcGZRBIRmWkEhf1RGu8SamoYo4++TYUuBSDvhOLSWabQaoFfv6H1VrsHuy6HARPIUmkY8FGY75GgIphFCquWG69qZqQWwQ5IJzBAcb8JOyC1js64hO9xrxJ7I7d7Qxh+y9+oQLAd9E4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 29/43] arm/altp2m: Add support for altp2m_vcpu_{initialise,destroy} Date: Mon, 20 Apr 2026 17:26:34 -0400 Message-ID: <20260420212648.208640-22-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> References: <20260420212648.208640-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es013.ebgroup.elektrobit.com (10.243.160.141) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|DS0PR08MB9619:EE_|MWH0EPF000A6731:EE_|CH3PR08MB8803:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e785e4b-54c3-426f-7e08-08de9f23af79 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704161411799003|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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The x86-specific function calls, altp2m_vcpu_disable_ve and altp2m_vcpu_update_p2m, are gated with #ifdef CONFIG_X86. This is commit 2/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. The equivalent to this patch in the v4/v5 was originally part of the patch named "arm/altp2m: Add HVMOP_altp2m_set_domain_state". In that patch, the check that the VCPU passed to altp2m_vcpu_initialise isn't the current CPU was removed. This was because ARM only implements the external altp2m mode, meaning the current VCPU could never be a VCPU of the guest for which altp2m is being initialized for. Therefore, skipping this check was a slight optimization. I've removed that here because altp2m_vcpu_initialise is only called during an HVMOP, and skipping this check on ARM (especially when x86 also implements the external altp2m mode) causes more confusion than the slight optimization is worth in my view. --- xen/common/altp2m.c | 14 ++++++++++---- xen/include/xen/altp2m.h | 2 -- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index e699b64678d8..7b80426c7798 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -11,6 +11,7 @@ #include #if defined(CONFIG_X86) && defined(CONFIG_HVM) +#include #include #endif @@ -59,7 +60,6 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } -#ifdef CONFIG_X86 void altp2m_vcpu_initialise(struct vcpu *v) { if ( !v->domain->nr_altp2m ) @@ -68,10 +68,12 @@ void altp2m_vcpu_initialise(struct vcpu *v) if ( v != current ) vcpu_pause(v); - vcpu_altp2m(v).p2midx = 0; + altp2m_set_vcpu_idx(v, 0); atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif if ( v != current ) vcpu_unpause(v); @@ -90,15 +92,19 @@ void altp2m_vcpu_destroy(struct vcpu *v) if ( (p2m = altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); +#ifdef CONFIG_X86 altp2m_vcpu_disable_ve(v); +#endif - vcpu_altp2m(v).p2midx = INVALID_ALTP2M; + altp2m_set_vcpu_idx(v, INVALID_ALTP2M); + +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif if ( v != current ) vcpu_unpause(v); } -#endif /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 7defe6126563..37c875a52327 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,11 +24,9 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); -#ifdef CONFIG_X86 /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); -#endif #ifdef CONFIG_ALTP2M -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:28:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:28:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287710.1568088 (Exim 4.92) (envelope-from ) id 1wEwAe-0003MP-5s; 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pr=C Message-ID: Date: Mon, 20 Apr 2026 17:28:34 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] tools/xenstored: allow domU to get own features To: Juergen Gross , CC: Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-2-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-2-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|PH7PR12MB6835:EE_ X-MS-Office365-Filtering-Correlation-Id: 4dd93f28-fe3f-4a7b-77bc-08de9f23c858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HENEAHweVZM9dx1Voiw7aSFf3MAFVwqfPKdMlyTXNfpFmkiokTT9YGdzmr7t8bf8xyoZQwTtRTL4lAzhvK+y5NFsiEbCvYlI1Uo69qStJMARVeIlsj9UZljYSWAcQlJY9f/zLkcRJqNyLWDHRscrnagY2D+FM+z8g4YSln6+3LX+t17DlQ+v19XxCCv34MeAJTgbkCJHp43mfvVVzvbT/UDAJB2ng5vxAyjPbIaBs7eqgTAdt4ep6wKY6VAp85f9mExtgfrjycpEj2/zH/Myntzrb/li/ilstCc8+t+GqtGggfaPczxNjoc4wbzWpIAtQlzR2+itjmr3JeTlKz1xDzJvnvCw5wUIFx99J5SPlRvQoG2XxAbmfRESLm6E4bEo+DRXaEzjyFHwXH2IiGxQEOD1e5f+29pSHR2WEpswhT7Mtan0w73+vtvHZJtAAPD8 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:28:36.5765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4dd93f28-fe3f-4a7b-77bc-08de9f23c858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6835 X-purgate-ID: tlsNG-720697/1776720521-8A2C6161-3F6434FC/0/0 X-purgate-type: clean X-purgate-size: 2195 On 2026-03-13 03:47, Juergen Gross wrote: > Expand the XS_GET_FEATURE command to allow an unprivileged domain to > read its own available features. While this information is available > via the related field in the shared page used for communication with > Xenstore, user land components of the domU would need special support > in the related kernel driver to obtain that data. With supporting the > XS_GET_FEATURE for that purpose, only an up to date libxenstore is > needed. > > Signed-off-by: Juergen Gross > --- > docs/misc/xenstore.txt | 9 +++++---- > tools/xenstored/core.c | 3 +-- > tools/xenstored/domain.c | 16 +++++++++++----- > 3 files changed, 17 insertions(+), 11 deletions(-) > > diff --git a/docs/misc/xenstore.txt b/docs/misc/xenstore.txt > index 4eccbc2f7f..8a2c19d116 100644 > --- a/docs/misc/xenstore.txt > +++ b/docs/misc/xenstore.txt > @@ -427,13 +427,14 @@ SET_FEATURE || > to set a bit for a feature not being supported by the running > Xenstore will be denied. Providing no with the > GET_FEATURE command will return the features which are supported > - by Xenstore. > + by Xenstore for the domain issuing the command. > > SET_FEATURE for a domain will be rejected after the INTRODUCE > - command for this domain has been sent to xenstored. > + command for this domain has been sent to xenstored. This has the > + effect that dom0 will always have all supported features enabled. This statement... > --- a/tools/xenstored/domain.c > +++ b/tools/xenstored/domain.c > @@ -1293,17 +1293,23 @@ int do_get_feature(const void *ctx, struct connection *conn, > char *result; > > n_args = get_strings(in, vec, ARRAY_SIZE(vec)); > - if (n_args > 1) > - return EINVAL; > > - if (n_args == 1) { > + if (!n_args) { > + features = conn->domain ? conn->domain->features > + : XENSTORE_FEATURES; ... cover this, yes? With a stubdom, dom0 will have conn->domain. conn->domain->features is initialized to XENSTORE_FEATURES and cannot change. Provided that is correct: Reviewed-by: Jason Andryuk Thanks, Jason From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:28:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:28:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287712.1568097 (Exim 4.92) (envelope-from ) id 1wEwAk-0003jW-Hb; Mon, 20 Apr 2026 21:28:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287712.1568097; Mon, 20 Apr 2026 21:28:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwAk-0003jI-E9; Mon, 20 Apr 2026 21:28:50 +0000 Received: by outflank-mailman (input) for mailman id 1287712; Mon, 20 Apr 2026 21:28:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwAj-0003hb-Ki for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <29caaacb-6ec0-4a2a-b32d-b0cd4fc7df13@amd.com> Date: Mon, 20 Apr 2026 17:28:42 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/8] docs: clarify Xenstore watch depth feature To: Juergen Gross , CC: Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-3-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-3-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|PH0PR12MB8052:EE_ X-MS-Office365-Filtering-Correlation-Id: ee9ef4de-434a-4806-1d3c-08de9f23cce7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|82310400026|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sQVcgROuM4xSoDlPElB/qgxDVWWDWZzM1S15w+2VIYRj/b2tHrAgJ5BxYcBaGr/lhqsZVL31J8TibXpFbDP6vu79lNrMY7qAkcH0ql9q2twt1xLOnIHGUY9itvYGRWaAmUumhvNSqEPArUipm+JPhVIPYvU/g6wxhZfiV01BnOGhveDW0O5rCKtrD2jQaK9TfJPZsWcM6H+DjuxFKCrwT4CkUF48LoulDTlTcciwI1msbvsugSDLfZDAuHUwoOnR4mIXtsrPgBwxJsrtDv7aj0W2fphX5pWPnGQ7Iy0s9rztxVWMzjbwcD8+E81zpNmo09ov/LgxLizIyTKp0+lTgtcZd0Kl5fz0wfyJ7NY2X7F1avibmNEXJt0DCgPqJVr984og9BYJFE4aEpbQ0Oi/ruse0JtAXLgdH0FjFIxdxgiG3J4ojYYzphF8F8q2/i1E X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:28:44.2745 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee9ef4de-434a-4806-1d3c-08de9f23cce7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8052 X-purgate-ID: tlsNG-d25034/1776720528-6D76ECF5-7E808F65/0/0 X-purgate-type: clean X-purgate-size: 283 On 2026-03-13 03:47, Juergen Gross wrote: > Make it explicit that for watching the @releaseDomain/ special > node, the XENSTORE_SERVER_FEATURE_WATCHDEPTH is needed. > > Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:30:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:30:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287730.1568105 (Exim 4.92) (envelope-from ) id 1wEwC8-0006FL-TY; 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pr=C Message-ID: <75667f07-b997-4bba-a905-9c5d80e8ba0c@amd.com> Date: Mon, 20 Apr 2026 17:30:03 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] tools/libs/store: add support to use watches with a depth parameter To: Juergen Gross , CC: Anthony PERARD , Julien Grall References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-4-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-4-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F4:EE_|DS0PR12MB8501:EE_ X-MS-Office365-Filtering-Correlation-Id: e576d413-ff71-4ef5-7f27-08de9f23fecd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|18096099003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: YyrjqxUs3q1tbdcvGLukBPugjO8bmiiyassRdVm7x6+u+WGKbaM3un5JIWfejPhl4dmR06orBl/Z6j5EnGIdwLpnY30mJezy2Z+vmRwCP10Jw/OW71XysGiT9DZ8mc+euDWdt19j/O6eg0lQBzIYQu38I1+JJ82Re4m7ZJuLpBsnkxiqSgbAZf8t4bVNzupn5OeYmBQ6wusad+XHKLoY64rEbi+jSngYHZh0SFS9CDG+4+ctzlx36GD6JPId2KyAltg6H1DVEaGEe8LhPqfzgeo5qPnMhltkhitNQdMxroVsyDtQwq8GA/s4z0XlSTD9jTMddHGxLDRo+eC626Gl5nbAczMeYMMoNb3ADpd/KQZ/ukvi+u4yK967/xNIWlA9S+Jh3rCBs8auwVaCiZcfO8DJA0BF4duVJYg5KAjubXzRfO1wMijWcNYJw0RKOrot6I60PdegUfz0uGydnZvsAWRTwDy3OMBTKO1qjC8DOfsD+3WRn8Mmcv8YkrdR9VQ7uOfXEhAWNCzigzGLL38mGPEnPcOhhH9pFijumAfti2IYADMyVcTwJl1/F4mKcIhs5DyqUZ2mCW2ySr0HPjXEqo6GRgj4lvRXq4sJCtmerBEvsKrNayNqX7KQHqOdZl+HIb9YEll0mp/a65VPdDH0Q8sZuGTgvFbeuYZGA9yr6Qkk1hXmzs9HUCH9Sacs81JolVfpidqd/knAvciOqm4wGeiBWzHJRg9PDhq9bEZ4L2UkOmFExwGLWDhOxgxppYN5KsDVBgFBPIOs2+FP8zuKDw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(18096099003)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AWRHASxo+7Nl7yZjoX6xuvkfUG9g1z4RjLAgiILz//cYukHeoqQ+px/FWoY2n5pgL0X7UlRLrbc+OrPzBFRsyAr7Jd75RN3UX1C5mZ6RVmA1IuBOKerb4LgXLQY/iR028GA8HVIt/bfydht9hAlzOsqU660js9InOE3neDpSivq+ebqxri4YpOmLSDKytLFFrIWy6oxL1zV2am1QFuoNZHHdl8pUYn1qWV41LW5jnCrdp5OLO724rYPp5ZSJFUw9FK/fjdeRjdxeVRck7p8WA5hySXTkp1TPSb8eqhBrNu1JI11q9aFl04h5VXjfth1H6cL13RverQxzHP20qAlId/KeJgWYP8CmucUnVIjVOZQNQk+MthpNxeL0CCL5PwXHbbptaWSt/eWJHBV+g5FdQ2np4mcbCzbwGxfBiTl16hKIRReogU9hKHeJArFJP8v1 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:30:07.9949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e576d413-ff71-4ef5-7f27-08de9f23fecd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8501 X-purgate-ID: tlsNG-ebf023/1776720614-4BD6C3FF-8A4DEB86/0/0 X-purgate-type: clean X-purgate-size: 2246 On 2026-03-13 03:47, Juergen Gross wrote: > Add a new xs_watch_depth() function to libxenstore allowing to limit > the scope of a Xenstore watch. It can be used only in case Xenstore is > supporting the XENSTORE_SERVER_FEATURE_WATCHDEPTH feature. > > For convenience add a xs_watch_try_depth() wrapper, which will call > xs_watch_depth() if supported and xs_watch() otherwise. > > Cache the supported features of Xenstore in order not having to get > them from Xenstore for each call of one of the new functions. > > Signed-off-by: Juergen Gross > @@ -984,37 +984,29 @@ bool xs_restrict(struct xs_handle *h, unsigned domid) > return false; > } > > -/* Watch a node for changes (poll on fd to detect, or call read_watch()). > - * When the node (or any child) changes, fd will become readable. > - * Token is returned when watch is read, to allow matching. > - * Returns false on failure. > - */ > -bool xs_watch(struct xs_handle *h, const char *path, const char *token) > +static bool xs_watch_helper(struct xs_handle *h) > { > - struct xsd_sockmsg msg = { .type = XS_WATCH }; > - struct iovec iov[3]; > - > #ifdef USE_PTHREAD > + sigset_t set, old_set; > + pthread_attr_t attr; > + static size_t stack_size; > +#ifdef USE_DLSYM > + size_t (*getsz)(pthread_attr_t *attr); > +#endif > + > #define DEFAULT_THREAD_STACKSIZE (16 * 1024) > /* NetBSD doesn't have PTHREAD_STACK_MIN. */ > #ifndef PTHREAD_STACK_MIN > # define PTHREAD_STACK_MIN 0 > #endif > > -#define READ_THREAD_STACKSIZE \ > - ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ > +#define READ_THREAD_STACKSIZE \ > + ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ > PTHREAD_STACK_MIN : DEFAULT_THREAD_STACKSIZE) > > /* We dynamically create a reader thread on demand. */ > mutex_lock(&h->request_mutex); > if (!h->read_thr_exists) { > - sigset_t set, old_set; > - pthread_attr_t attr; > - static size_t stack_size; > -#ifdef USE_DLSYM > - size_t (*getsz)(pthread_attr_t *attr); > -#endif AFAICT, there is no particular reason to change the scope of these variables. Am I missing something? Everything else looks okay. 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This is commit 5/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 +++++++++++ xen/arch/x86/include/asm/hvm/hvm.h | 11 ----------- xen/include/asm-generic/altp2m.h | 7 +++++++ 4 files changed, 19 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 512b18d4010f..e4f1cbf3b51e 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -39,6 +39,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index ad5ded833a75..07e760f60659 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,6 +28,12 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, mfn_x(INVALID_MFN); } +/* returns true if hardware supports alternate p2m's */ +static inline bool altp2m_supported(void) +{ + return hvm_funcs.caps.altp2m; +} + static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -58,6 +64,11 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, return false; } +static inline bool altp2m_supported(void) +{ + return false; +} + /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index 6406bb687718..e6d8042831dc 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -701,12 +701,6 @@ static inline bool hvm_hap_supported(void) return hvm_funcs.caps.hap; } -/* returns true if hardware supports alternate p2m's */ -static inline bool altp2m_supported(void) -{ - return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; -} - /* Returns true if we have the minimum hardware requirements for nested virt */ static inline bool hvm_nested_virt_supported(void) { @@ -876,11 +870,6 @@ static inline bool hvm_hap_supported(void) return false; } -static inline bool altp2m_supported(void) -{ - return false; -} - static inline bool hvm_nested_virt_supported(void) { return false; diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/altp2m.h index ecee6942f4e8..a3cdbdae9953 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -6,6 +6,13 @@ struct vcpu; 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Creating a commit with just the empty file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 1/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/common/Makefile | 1 + xen/common/altp2m.c | 12 ++++++++++++ xen/include/xen/altp2m.h | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h diff --git a/xen/common/Makefile b/xen/common/Makefile index 6018e256147f..dbe0094006df 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -1,3 +1,4 @@ +obj-$(CONFIG_ALTP2M) += altp2m.o obj-$(CONFIG_ARGO) += argo.o obj-y += bitmap.o obj-bin-$(CONFIG_SELF_TESTS) += bitops.init.o diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c new file mode 100644 index 000000000000..1a4e102324d4 --- /dev/null +++ b/xen/common/altp2m.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h new file mode 100644 index 000000000000..520328fd3fa8 --- /dev/null +++ b/xen/include/xen/altp2m.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __XEN_ALTP2M_H__ +#define __XEN_ALTP2M_H__ + +#endif /* __XEN_ALTP2M_H__ */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:32:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:32:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287751.1568134 (Exim 4.92) (envelope-from ) id 1wEwEd-0007HK-UT; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nO2vQnDj+g67qkhl/vnsVjDzGEh4mUtED4k6uTv2NSfQlaLYZA8sUy3daxzJ2p6+U5517okDGSwxEcwlYpWbsV5ZYCyO4Rhaj25tnDK3kXnkcoIDTWOLKjgLtIPzR/O1dRpZycQA1FrIAP4Ume2J7CaOQIsihsxZ2W9IB2NzrM0xdNiMTt0FOqBVsghIVZOxX8+NLrfCNweC9yTRqgtLf0CVFyrfb6e6YcdU3etxVkvS65CouF3CYZrrPB9hrrbgYMb7ghhZZy9S0BvS9sjqo31a22Fll2DWqBYbp6Dtc8o8pRJoPSatkbfxsTgd2b3uixhFQK+DA0npfzN49ix0z6GI1ikD+IvSiZRUpaYSbma1Yapve9jlprMs7oMV3Yhub7kXanlSKsPDP/Cpqg/0OqlyP5215w24uMZPQcPajdUyz4dDVElrsgtLwi8ulxPn X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:32:41.2309 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9553204c-2db9-4b80-569a-08de9f245a4a X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN2PEPF00004FBE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR08MB10562 X-purgate-ID: tlsNG-720697/1776720769-8336C161-4E52AD19/0/0 X-purgate-type: clean X-purgate-size: 5417 Using a generic name for altp2m_supported makes it possible to indicate whether altp2m is supported on other architectures as well. Even if other architectures always support altp2m at a hardware level (like ARM), altp2m might not be supported due to CONFIG_ALTP2M being disabled. Therefore, the altp2m_supported function can be implemented on all architectures to indicate if the hardware supports altp2m *and* if CONFIG_ALTP2M is enabled. This is commit 4/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/hvm.c | 6 +++--- xen/arch/x86/include/asm/hvm/hvm.h | 4 ++-- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/p2m-basic.c | 4 ++-- xen/arch/x86/mm/p2m-ept.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 1d458f1372e5..512b18d4010f 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -698,7 +698,7 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) if ( altp2m_mode ) { - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) { dprintk(XENLOG_INFO, "altp2m is not supported\n"); return -EINVAL; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 86c12c0d1ef4..bc35efdf2c02 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1692,7 +1692,7 @@ void hvm_vcpu_destroy(struct vcpu *v) ioreq_server_remove_vcpu_all(v->domain, v); - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) altp2m_vcpu_destroy(v); nestedhvm_vcpu_destroy(v); @@ -4566,7 +4566,7 @@ static int do_altp2m_op( int rc = 0; uint64_t mode; - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; if ( copy_from_guest(&a, arg, 1) ) @@ -4965,7 +4965,7 @@ static int compat_altp2m_op( struct xen_hvm_altp2m_op *altp2m_op; } nat; - if ( !hvm_altp2m_supported() ) + if ( !altp2m_supported() ) return -EOPNOTSUPP; if ( copy_from_guest(&a, arg, 1) ) diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index e7c1364802f8..6406bb687718 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -702,7 +702,7 @@ static inline bool hvm_hap_supported(void) } /* returns true if hardware supports alternate p2m's */ -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return IS_ENABLED(CONFIG_ALTP2M) && hvm_funcs.caps.altp2m; } @@ -876,7 +876,7 @@ static inline bool hvm_hap_supported(void) return false; } -static inline bool hvm_altp2m_supported(void) +static inline bool altp2m_supported(void) { return false; } diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 6918a00a2a25..563eba3c0d36 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -501,7 +501,7 @@ int hap_enable(struct domain *d, u32 mode) } #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { /* Init alternate p2m data */ if ( (d->arch.altp2m_eptp = alloc_xenheap_page()) == NULL ) @@ -546,7 +546,7 @@ void hap_final_teardown(struct domain *d) unsigned int i; #ifdef CONFIG_ALTP2M - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) for ( i = 0; i < d->nr_altp2m; i++ ) p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif @@ -590,7 +590,7 @@ void hap_teardown(struct domain *d, bool *preempted) #ifdef CONFIG_ALTP2M /* Leave the root pt in case we get further attempts to modify the p2m. */ - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) { if ( altp2m_active(d) ) for_each_vcpu ( d, v ) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index e126fda26760..ce14066fedaf 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } - rc = hvm_altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc = altp2m_supported() ? p2m_init_altp2m(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -197,7 +197,7 @@ void p2m_final_teardown(struct domain *d) { if ( is_hvm_domain(d) ) { - if ( hvm_altp2m_supported() ) + if ( altp2m_supported() ) p2m_teardown_altp2m(d); /* * We must tear down nestedp2m unconditionally because diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ddb4c7606be1..84159198f3a0 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -995,7 +995,7 @@ out: if ( is_epte_present(&old_entry) ) ept_free_entry(p2m, &old_entry, target); - if ( hvm_altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) + if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { ret = p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); if ( !rc ) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:32:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:32:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287752.1568138 (Exim 4.92) (envelope-from ) id 1wEwEe-0007KS-97; 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Creating a commit with just the template file additions makes it easier to reorder later commits which add to these files. This commit can be squashed into the first commit which actually adds something to altp2m.c/altp2m.h for the actual submission if that would be preferred. This is commit 6/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 16 +++++++++++++ xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 37 +++++++++++++++++++++++++++++++ 4 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 69200b27280d..d995d4ff7aa1 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_HAS_VPCI) += vpci.o obj-$(CONFIG_HAS_ALTERNATIVE) += alternative.o +obj-$(CONFIG_ALTP2M) += altp2m.o obj-y += cpuerrata.o obj-y += cpufeature.o obj-y += decode.o diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c new file mode 100644 index 000000000000..2bd1ff4df223 --- /dev/null +++ b/xen/arch/arm/altp2m.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.c: Alternate p2m + * + * Copyright (c) 2016 Sergej Proskurin + */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/Makefile b/xen/arch/arm/include/asm/Makefile index 4565baca6a4d..fef4dd42b6cb 100644 --- a/xen/arch/arm/include/asm/Makefile +++ b/xen/arch/arm/include/asm/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -generic-y += altp2m.h generic-y += device.h generic-y += hardirq.h generic-y += iocap.h diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h new file mode 100644 index 000000000000..ca836bae7330 --- /dev/null +++ b/xen/arch/arm/include/asm/altp2m.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * altp2m.h: Alternate p2m + * + * Copyright (c) 2014, Intel Corporation. + * Copyright (c) 2016, Sergej Proskurin . + */ + +#ifndef __ASM_ARM_ALTP2M_H +#define __ASM_ARM_ALTP2M_H + +#include + +static inline bool altp2m_supported(void) +{ + /* Not implemented yet */ + return false; +} + +/* Alternate p2m VCPU */ +static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + /* Not implemented yet */ + BUG(); + return 0; +} + +#endif /* __ASM_ARM_ALTP2M_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:32:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:32:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287755.1568151 (Exim 4.92) (envelope-from ) id 1wEwEi-0007pD-Ho; Mon, 20 Apr 2026 21:32:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287755.1568151; Mon, 20 Apr 2026 21:32:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwEi-0007p2-E7; Mon, 20 Apr 2026 21:32:56 +0000 Received: by outflank-mailman (input) for mailman id 1287755; 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This makes it possible to build Xen without building altp2m code. This commit also implements a stub for p2m_altp2m_check, as some implementation is needed when CONFIG_ALTP2M is enabled. This is due to a call to p2m_altp2m_check in vm_event.c which is gated by CONFIG_ALTP2M. This is commit 7/8 of the preparation phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/arm/Kconfig | 11 +++++++++++ xen/arch/arm/altp2m.c | 9 +++++++++ xen/arch/arm/include/asm/altp2m.h | 18 ++++++++++++++++-- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..fdf0721c3c03 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -98,6 +98,17 @@ config MPU systems supporting EL2. (UNSUPPORTED) endchoice +config ALTP2M + bool "Alternate P2M support" if EXPERT + depends on MMU + default y + help + Alternate-p2m allows a guest to manage multiple p2m guest physical + "memory views" (as opposed to a single p2m). + Useful for memory introspection. + + If unsure, stay with defaults. + source "arch/Kconfig" config ACPI diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 2bd1ff4df223..8bd174ea8f37 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -5,6 +5,15 @@ * Copyright (c) 2016 Sergej Proskurin */ +#include + +/* Check to see if vcpu should be switched to a different p2m. */ +void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not yet implemented */ + BUG(); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index ca836bae7330..698c35427e75 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -11,10 +11,12 @@ #include +#ifdef CONFIG_ALTP2M + +/* Hardware always supports altp2m on ARM */ static inline bool altp2m_supported(void) { - /* Not implemented yet */ - return false; + return true; } /* Alternate p2m VCPU */ @@ -25,6 +27,18 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return 0; } +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_supported(void) +{ + return false; +} + +/* Only declaration is needed. DCE will optimise it out when linking. */ +uint16_t altp2m_vcpu_idx(const struct vcpu *v); + +#endif /* CONFIG_ALTP2M */ + #endif /* __ASM_ARM_ALTP2M_H */ /* -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:32:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:32:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287757.1568159 (Exim 4.92) (envelope-from ) id 1wEwEk-000864-2T; Mon, 20 Apr 2026 21:32:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287757.1568159; Mon, 20 Apr 2026 21:32:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwEj-00085v-VW; Mon, 20 Apr 2026 21:32:57 +0000 Received: by outflank-mailman (input) for mailman id 1287757; Mon, 20 Apr 2026 21:32:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwEi-0007oF-78 for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +MyymflaFjgAyhQpDKMkybRTtCfZw4Qu7e0pGaYIpfhO1qZzeuA9uL5yJSoOhZphPlORpn37gstjnBRezs6/cshAbJE3UwN/RUzggUcEnqOtzNsoaBt4kJtW6w5P8bNHjcEt2G/dKbQF1KIzr60HrcuEAmkaetSgXDxcXo3zALwFpRgIYpwzUf1zHM6cJ6qezWu5M0yMDKTEn4As5sn6HppWO57xOny9ZvF7Gsq8HyG6ZjP+i/7WOZiZ9zBQaZ+cReTR06QNgZ+faustMpVhQqDi51NRAFdrsTdVtnbRVYGa1oSsxTxKYRCh48m8vIo3jgiTTRWu6X89BxtftKARW93R8kwZF/gKCcyxHW1N0L/FkkdBurrz5jNcjaxlaYQkSAmCCT3kfebLWizRxeHVED4495Ko/4ky2cOloEQe7fMyugAarsih5TjpMG6+SwG2 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:32:46.1162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87086589-79e7-4a65-e530-08de9f245d0d X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CO1PEPF000066EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR08MB9151 X-purgate-ID: tlsNG-42698a/1776720775-252B9F3B-295B4CEC/0/0 X-purgate-type: clean X-purgate-size: 13310 Similarly to the previous commit, this commit moves altp2m_p2m to the common domain struct. The representation of altp2m views as an array of p2m_domain pointers is the same on x86 and ARM, and it seems that this would be the case for other architectures as well. This commit is a refactor, and no change in functionality is intended. This is commit 3/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/vmx/vmx.c | 2 +- xen/arch/x86/include/asm/domain.h | 1 - xen/arch/x86/include/asm/p2m.h | 4 ++-- xen/arch/x86/mm/altp2m.c | 28 ++++++++++++++-------------- xen/arch/x86/mm/hap/hap.c | 6 +++--- xen/arch/x86/mm/mem_access.c | 8 ++++---- xen/arch/x86/mm/mem_sharing.c | 2 +- xen/arch/x86/mm/p2m-ept.c | 6 +++--- xen/arch/x86/mm/p2m.c | 8 ++++---- xen/include/xen/sched.h | 1 + 10 files changed, 33 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index ff895f7f9437..0909929c00e0 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -5004,7 +5004,7 @@ bool asmlinkage vmx_vmenter_helper(const struct cpu_user_regs *regs) if ( currd->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - ept = &currd->arch.altp2m_p2m[i]->ept; + ept = &currd->altp2m_p2m[i]->ept; if ( cpumask_test_cpu(cpu, ept->invalidate) ) { cpumask_clear_cpu(cpu, ept->invalidate); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index 0cf0c0d92087..f8038087e612 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,7 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; #ifdef CONFIG_ALTP2M - struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; uint64_t *altp2m_visible_eptp; diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 3a5a5fd43c2a..ec871717a9e4 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -901,7 +901,7 @@ static inline struct p2m_domain *p2m_get_altp2m(struct vcpu *v) BUG_ON(index >= v->domain->nr_altp2m); - return v->domain->arch.altp2m_p2m[index]; + return v->domain->altp2m_p2m[index]; } /* set current alternate p2m table */ @@ -919,7 +919,7 @@ static inline bool p2m_set_altp2m(struct vcpu *v, unsigned int idx) atomic_dec(&orig->active_vcpus); vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->arch.altp2m_p2m[idx]->active_vcpus); + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); return true; } diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 08db8f37c1b1..8dd3c0f96be0 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -130,14 +130,14 @@ int p2m_init_altp2m(struct domain *d) struct p2m_domain *hostp2m = p2m_get_hostp2m(d); mm_lock_init(&d->arch.altp2m_list_lock); - d->arch.altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); + d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); - if ( !d->arch.altp2m_p2m ) + if ( !d->altp2m_p2m ) return -ENOMEM; for ( i = 0; i < d->nr_altp2m; i++ ) { - d->arch.altp2m_p2m[i] = p2m = p2m_init_one(d); + d->altp2m_p2m[i] = p2m = p2m_init_one(d); if ( p2m == NULL ) { p2m_teardown_altp2m(d); @@ -158,14 +158,14 @@ void p2m_teardown_altp2m(struct domain *d) for ( i = 0; i < d->nr_altp2m; i++ ) { - if ( !d->arch.altp2m_p2m[i] ) + if ( !d->altp2m_p2m[i] ) continue; - p2m = d->arch.altp2m_p2m[i]; - d->arch.altp2m_p2m[i] = NULL; + p2m = d->altp2m_p2m[i]; + d->altp2m_p2m[i] = NULL; p2m_free_one(p2m); } - XVFREE(d->arch.altp2m_p2m); + XVFREE(d->altp2m_p2m); } int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, @@ -325,7 +325,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned int idx, struct p2m_domain *p2m; ASSERT(idx < d->nr_altp2m); - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; p2m_lock(p2m); @@ -368,7 +368,7 @@ static int p2m_activate_altp2m(struct domain *d, unsigned int idx, ASSERT(idx < d->nr_altp2m); - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; hostp2m = p2m_get_hostp2m(d); p2m_lock(p2m); @@ -468,7 +468,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN) ) { - p2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; if ( !_atomic_read(p2m->active_vcpus) ) { @@ -532,7 +532,7 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, return rc; hp2m = p2m_get_hostp2m(d); - ap2m = d->arch.altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; p2m_lock(hp2m); p2m_lock(ap2m); @@ -596,7 +596,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; /* Check for a dropped page that may impact this altp2m */ if ( mfn_eq(mfn, INVALID_MFN) && @@ -679,7 +679,7 @@ int p2m_set_suppress_ve_multi(struct domain *d, return -EINVAL; p2m = ap2m = - d->arch.altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(sve->view, d->nr_altp2m)]; } p2m_lock(host_p2m); @@ -746,7 +746,7 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, return -EINVAL; p2m = ap2m = - d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } else p2m = host_p2m; diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 3d563b3bc2d1..6918a00a2a25 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -524,7 +524,7 @@ int hap_enable(struct domain *d, u32 mode) for ( i = 0; i < d->nr_altp2m; i++ ) { - rv = p2m_alloc_table(d->arch.altp2m_p2m[i]); + rv = p2m_alloc_table(d->altp2m_p2m[i]); if ( rv != 0 ) goto out; } @@ -548,7 +548,7 @@ void hap_final_teardown(struct domain *d) #ifdef CONFIG_ALTP2M if ( hvm_altp2m_supported() ) for ( i = 0; i < d->nr_altp2m; i++ ) - p2m_teardown(d->arch.altp2m_p2m[i], true, NULL); + p2m_teardown(d->altp2m_p2m[i], true, NULL); #endif /* Destroy nestedp2m's first */ @@ -603,7 +603,7 @@ void hap_teardown(struct domain *d, bool *preempted) for ( i = 0; i < d->nr_altp2m; i++ ) { - p2m_teardown(d->arch.altp2m_p2m[i], false, preempted); + p2m_teardown(d->altp2m_p2m[i], false, preempted); if ( preempted && *preempted ) return; } diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index a9d6b081a523..e5548e64d8d0 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -319,7 +319,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - ap2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -375,7 +375,7 @@ long p2m_set_mem_access_multi(struct domain *d, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - ap2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + ap2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -438,7 +438,7 @@ int p2m_get_mem_access(struct domain *d, gfn_t gfn, xenmem_access_t *access, if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) return -EINVAL; - p2m = d->arch.altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; + p2m = d->altp2m_p2m[array_index_nospec(altp2m_idx, d->nr_altp2m)]; } #endif @@ -457,7 +457,7 @@ void arch_p2m_set_access_required(struct domain *d, bool access_required) unsigned int i; for ( i = 0; i < d->nr_altp2m; i++ ) { - struct p2m_domain *p2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *p2m = d->altp2m_p2m[i]; if ( p2m ) p2m->access_required = access_required; diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 8319733b1bb6..b7d8fb9ad1aa 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -919,7 +919,7 @@ static int nominate_page(struct domain *d, gfn_t gfn, for ( i = 0; i < d->nr_altp2m; i++ ) { - ap2m = d->arch.altp2m_p2m[i]; + ap2m = d->altp2m_p2m[i]; if ( !ap2m ) continue; diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index ed850723f5fd..ddb4c7606be1 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -1311,7 +1311,7 @@ static void ept_set_ad_sync(struct domain *d, bool value) if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; p2m_lock(p2m); p2m->ept.ad = value; @@ -1579,7 +1579,7 @@ void __init setup_ept_dump(void) void p2m_init_altp2m_ept(struct domain *d, unsigned int i) { struct p2m_domain *p2m = - d->arch.altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; + d->altp2m_p2m[array_index_nospec(i, d->nr_altp2m)]; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); struct ept_data *ept; @@ -1603,7 +1603,7 @@ unsigned int p2m_find_altp2m_by_eptp(struct domain *d, uint64_t eptp) if ( d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m = d->arch.altp2m_p2m[i]; + p2m = d->altp2m_p2m[i]; ept = &p2m->ept; if ( eptp == ept->eptp ) diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index 41517765c5ec..5bd426296f20 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -111,7 +111,7 @@ void p2m_change_entry_type_global(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); change_entry_type_global(altp2m, ot, nt); @@ -157,7 +157,7 @@ bool p2m_memory_type_changed(struct domain *d) { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); _memory_type_changed(altp2m); @@ -955,7 +955,7 @@ void p2m_change_type_range(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); change_type_range(altp2m, start, end, ot, nt); @@ -1031,7 +1031,7 @@ int p2m_finish_type_change(struct domain *d, { if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) { - struct p2m_domain *altp2m = d->arch.altp2m_p2m[i]; + struct p2m_domain *altp2m = d->altp2m_p2m[i]; p2m_lock(altp2m); rc = finish_type_change(altp2m, first_gfn, max_nr); diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 458f2f260dd7..5d8ba2d2ab19 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -626,6 +626,7 @@ struct domain /* altp2m: allow multiple copies of host p2m */ bool altp2m_active; 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All altp2m commands in the switch statement are gated by CONFIG_X86, with a default case of returning EOPNOTSUPP. This allows future commits to move the #ifdef CONFIG_X86 down as support for ARM is added. Additionally, a call to do_altp2m_op is added in the ARM HVMOP code. This is commit 2/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: Replaced patches 2 and 3 from v4/v5 patch set with this patch. Made HVM_PARAM_ALTP2M read-only, following the change to the x86 implementation in commit 0291089f6ea8. The DOMCTL to enable altp2m on ARM is implemented in a later commit in this patch series. --- xen/arch/arm/hvm.c | 9 +++++++++ xen/common/altp2m.c | 29 ++++++++++++++--------------- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/hvm.c b/xen/arch/arm/hvm.c index 86e49bf47403..7c778795a280 100644 --- a/xen/arch/arm/hvm.c +++ b/xen/arch/arm/hvm.c @@ -5,6 +5,7 @@ * Arch-specific hardware virtual machine abstractions. */ +#include #include #include #include @@ -23,6 +24,10 @@ static int hvm_allow_set_param(const struct domain *d, unsigned int param) { switch ( param ) { + /* The following parameters are read-only. */ + case HVM_PARAM_ALTP2M: + return -EEXIST; + /* * The following parameters are intended for toolstack usage only. * They may not be set by the domain. @@ -123,6 +128,10 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg) rc = -EINVAL; break; + case HVMOP_altp2m: + rc = do_altp2m_op(arg); + break; + default: { gdprintk(XENLOG_DEBUG, "HVMOP op=%lu: not implemented\n", op); diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a43b3a3e34b3..6481fae1ed12 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -9,8 +9,10 @@ #include -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) && defined(CONFIG_HVM) #include +#endif + /* * altp2m operations are envisioned as being used in several different * modes: @@ -18,13 +20,13 @@ * - external: All control and decisions are made by an external agent * running domain 0. * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. + * - internal (x86 only): altp2m operations are used exclusively by an + * in-guest agent to protect itself from the guest kernel and + * in-guest attackers. * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). + * - coordinated (x86 only): An in-guest agent handles #VE and VMFUNCs + * locally, but makes requests of an agent running outside the + * domain for bigger changes (such as modifying altp2m entires). * * This corresponds to the three values for HVM_PARAM_ALTP2M * (external, mixed, limited). All three models have advantages and @@ -97,7 +99,7 @@ int do_altp2m_op( if ( (a.cmd != HVMOP_altp2m_get_domain_state) && (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) + !altp2m_active(d) ) { rc = -EOPNOTSUPP; goto out; @@ -122,6 +124,7 @@ int do_altp2m_op( switch ( a.cmd ) { +#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state = altp2m_active(d); rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; @@ -394,9 +397,12 @@ int do_altp2m_op( rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); break; } +#endif /* CONFIG_X86 */ default: +#ifdef CONFIG_X86 ASSERT_UNREACHABLE(); +#endif rc = -EOPNOTSUPP; break; } @@ -406,13 +412,6 @@ int do_altp2m_op( return rc; } -#else -int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ - return -EOPNOTSUPP; -} -#endif /* * Local variables: -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287764.1568178 (Exim 4.92) (envelope-from ) id 1wEwEp-0000H1-0H; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZjekY8MFl0nXFrjGpv9K0LoMduEov5ssr96fU6DEHfseF+iCh0exQjhFqNZ2W06QSYvWk5ninQEl1+c4cYigKoD5v/eWCCD6N0uzi0KX4cPu8TtuLHcsNoOStOO744oZvpIPorK/BFK3k7AhxQ5EDTVZGvtyOGmKiqWnkjcaWmOwAuYMPXOOgYSwefEu30KOxMw4WjkuUgy/M0I2mWbyPYCcnTjQRHRj/Ih5UpRXsdstJiXyxCl2SnVRfk2wCwQZ6YBpb9GmN+vf+ZSvTcE9bU4YaKcE4887HiTXqnkOz4Ny+A3MECXQlY4abfkYf70WFYKsRwwQnx3FeHXmXLSgzEtyaFDpZ6Ijog+OKxJQQP3B6jwe8ATUwmoN6rxfeHVcmKN3mWvzlL8IiSrLnSaHnmVyiSXB2iC16n/DpHsWSg324s4Xb9H+BvY5/pOxvtZb X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:32:49.5644 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80cac74d-727e-469d-773a-08de9f245f42 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR08MB8837 X-purgate-ID: tlsNG-4011c0/1776720780-4777D8B7-72F31C00/0/0 X-purgate-type: clean X-purgate-size: 32242 This commit renames altp2m functions with a p2m prefix. These functions were originally defined in p2m.c, hence the p2m prefix. When they were moved to altp2m.c in commit ae7584f63678, the function names were kept and the declarations remained in p2m.h. This commit finishes that move by renaming these functions to have an altp2m prefix and moving the declarations to altp2m.h. Since these functions will either be moved to the common altp2m.c, or implemented separately for ARM, it doesn't seem to make sense to continue with this naming convention. Therefore, this commit preemptively renames the x86 implementations of these functions so they can later be implemented with altp2m function name prefixes in common code or for ARM. For convenience, here is the full list of renames: - p2m_init_altp2m -> altp2m_init - p2m_teardown_altp2m -> altp2m_teardown - p2m_flush_altp2m -> altp2m_flush - p2m_altp2m_get_or_propagate -> altp2m_get_or_propagate - p2m_altp2m_propagate_change -> altp2m_propagate_change - p2m_get_altp2m -> altp2m_get_altp2m - p2m_set_altp2m -> altp2m_set_altp2m - p2m_reset_altp2m -> altp2m_reset_altp2m - p2m_activate_altp2m -> altp2m_activate_altp2m - p2m_init_altp2m_by_id -> altp2m_init_by_id - p2m_init_next_altp2m -> altp2m_init_next_available - p2m_destroy_altp2m_by_id -> altp2m_destroy_by_id - p2m_switch_domain_altp2m_by_id -> altp2m_switch_domain_altp2m_by_id - p2m_change_altp2m_gfn -> altp2m_change_gfn - p2m_set_altp2m_view_visibility -> altp2m_set_view_visibility This commit contains only function renames and code movement, and no functional change is intended. This is commit 8/8 of the preparation phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/altp2m.c | 2 +- xen/arch/x86/hvm/hvm.c | 30 ++++---- xen/arch/x86/hvm/monitor.c | 2 +- xen/arch/x86/hvm/vmx/vmx.c | 6 +- xen/arch/x86/include/asm/altp2m.h | 116 +++++++++++++++++++++++++++++- xen/arch/x86/include/asm/p2m.h | 109 ---------------------------- xen/arch/x86/mm/altp2m.c | 76 ++++++++++---------- xen/arch/x86/mm/mem_access.c | 13 ++-- xen/arch/x86/mm/p2m-basic.c | 4 +- xen/arch/x86/mm/p2m-ept.c | 4 +- xen/arch/x86/mm/p2m.h | 3 - xen/common/vm_event.c | 2 +- xen/include/xen/p2m-common.h | 2 +- 13 files changed, 186 insertions(+), 183 deletions(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 8bd174ea8f37..339f82835caf 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -8,7 +8,7 @@ #include /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { /* Not yet implemented */ BUG(); diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index bc35efdf2c02..5b6e91adce17 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1885,15 +1885,15 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla, if ( altp2m_active(currd) ) { - p2m = p2m_get_altp2m(curr); + p2m = altp2m_get_altp2m(curr); /* * Get the altp2m entry if present; or if not, propagate from * the host p2m. NB that this returns with gfn locked in the * altp2m. */ - if ( p2m_altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, - &p2ma, &page_order) ) + if ( altp2m_get_or_propagate(p2m, gfn, &mfn, &p2mt, &p2ma, + &page_order) ) { /* Entry was copied from host -- retry fault */ rc = 1; @@ -2036,7 +2036,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla, paging_mark_pfn_dirty(currd, _pfn(gfn)); /* * If p2m is really an altp2m, unlock it before changing the type, - * as p2m_altp2m_propagate_change() needs to acquire the + * as altp2m_propagate_change() needs to acquire the * altp2m_list lock. */ if ( p2m != hostp2m ) @@ -4663,7 +4663,7 @@ static int do_altp2m_op( /* If the alternate p2m state has changed, handle appropriately */ if ( d->altp2m_active != ostate && - (ostate || !(rc = p2m_init_altp2m_by_id(d, 0))) ) + (ostate || !(rc = altp2m_init_by_id(d, 0))) ) { for_each_vcpu( d, v ) { @@ -4674,7 +4674,7 @@ static int do_altp2m_op( } if ( ostate ) - p2m_flush_altp2m(d); + altp2m_flush(d); } else if ( rc ) d->altp2m_active = false; @@ -4729,17 +4729,18 @@ static int do_altp2m_op( } case HVMOP_altp2m_create_p2m: - if ( !(rc = p2m_init_next_altp2m(d, &a.u.view.view, - a.u.view.hvmmem_default_access)) ) + rc = altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; case HVMOP_altp2m_destroy_p2m: - rc = p2m_destroy_altp2m_by_id(d, a.u.view.view); + rc = altp2m_destroy_by_id(d, a.u.view.view); break; case HVMOP_altp2m_switch_p2m: - rc = p2m_switch_domain_altp2m_by_id(d, a.u.view.view); + rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); break; case HVMOP_altp2m_set_suppress_ve: @@ -4871,9 +4872,9 @@ static int do_altp2m_op( if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) rc = -EINVAL; else - rc = p2m_change_altp2m_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); + rc = altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); break; case HVMOP_altp2m_get_p2m_idx: @@ -4906,8 +4907,7 @@ static int do_altp2m_op( else if ( !altp2m_active(d) ) rc = -EOPNOTSUPP; else - rc = p2m_set_altp2m_view_visibility(d, idx, - a.u.set_visibility.visible); + rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); break; } diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index 84c1c2234ca9..78137220b22a 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -182,7 +182,7 @@ int hvm_monitor_debug(unsigned long rip, enum hvm_monitor_debug_type type, #ifdef CONFIG_ALTP2M if ( curr->arch.hvm.fast_single_step.enabled ) { - p2m_altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx); + altp2m_check(curr, curr->arch.hvm.fast_single_step.p2midx); curr->arch.hvm.single_step = false; curr->arch.hvm.fast_single_step.enabled = false; curr->arch.hvm.fast_single_step.p2midx = 0; diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 0909929c00e0..f2cf95ee500e 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2452,7 +2452,7 @@ static void cf_check vmx_vcpu_update_eptp(struct vcpu *v) struct ept_data *ept; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -2521,7 +2521,7 @@ static int cf_check vmx_vcpu_emulate_vmfunc(const struct cpu_user_regs *regs) if ( !cpu_has_vmx_vmfunc && altp2m_active(curr->domain) && regs->eax == 0 && - p2m_switch_vcpu_altp2m_by_id(curr, regs->ecx) ) + altp2m_switch_vcpu_by_id(curr, regs->ecx) ) rc = X86EMUL_OKAY; return rc; @@ -4277,7 +4277,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs) } } - p2m_set_altp2m(v, idx); + altp2m_set_altp2m(v, idx); } if ( vm_event_is_enabled(v) && diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 07e760f60659..9c58a396448d 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -7,12 +7,33 @@ #ifndef __ASM_X86_ALTP2M_H #define __ASM_X86_ALTP2M_H -#ifdef CONFIG_ALTP2M #include #include /* for struct vcpu, struct domain */ + +#include #include /* for vcpu_altp2m */ +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +/* Alternate p2m paging */ +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p2ma, + unsigned int *page_order); + +/* Propagate a host p2m change to all alternate p2m's */ +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma); + +#ifdef CONFIG_ALTP2M + +#define AP2MGET_prepopulate true +#define AP2MGET_query false + static inline bool altp2m_is_eptp_valid(const struct domain *d, unsigned int idx) { @@ -39,6 +60,85 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return vcpu_altp2m(v).p2midx; } +/* + * Alternate p2m: shadow p2m tables used for alternate memory views + */ + +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index = vcpu_altp2m(v).p2midx; + + if ( index == INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >= v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >= v->domain->nr_altp2m); + + if ( idx == vcpu_altp2m(v).p2midx ) + return false; + + orig = altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx = idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} + +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); + +/* Free altp2m views */ +void altp2m_teardown(struct domain *d); + +/* Switch alternate p2m for a single vcpu */ +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); + +/* Flush all the alternate p2m's for a domain */ +void altp2m_flush(struct domain *d); + +/* Make a specific alternate p2m valid */ +int altp2m_init_by_id(struct domain *d, unsigned int idx); + +/* Find an available alternate p2m and make it valid */ +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access); + +/* Make a specific alternate p2m invalid */ +int altp2m_destroy_by_id(struct domain *d, unsigned int idx); + +/* Switch alternate p2m for entire domain */ +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); + +/* Change a gfn->mfn mapping */ +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn); + +/* Set a specific p2m view visibility */ +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + +/* + * Looks up altp2m entry. If the entry is not found it looks up the entry in + * hostp2m. + * The prepopulate param is used to set the found entry in altp2m. + */ +int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *a, + bool prepopulate); + /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); @@ -69,7 +169,21 @@ static inline bool altp2m_supported(void) return false; } +static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, + gfn_t gfn, mfn_t *mfn, + p2m_type_t *t, p2m_access_t *a) +{ + ASSERT_UNREACHABLE(); + return -EOPNOTSUPP; +} +#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ + _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) + /* Only declaration is needed. DCE will optimise it out when linking. */ +int altp2m_init(struct domain *d); +void altp2m_teardown(struct domain *d); +struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); +bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index ec871717a9e4..5110b3e77807 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -582,30 +582,6 @@ static inline gfn_t mfn_to_gfn(const struct domain *d, mfn_t mfn) return _gfn(mfn_x(mfn)); } -#ifdef CONFIG_ALTP2M -#define AP2MGET_prepopulate true -#define AP2MGET_query false - -/* - * Looks up altp2m entry. If the entry is not found it looks up the entry in - * hostp2m. - * The prepopulate param is used to set the found entry in altp2m. - */ -int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, - p2m_type_t *t, p2m_access_t *a, - bool prepopulate); -#else -static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, - gfn_t gfn, mfn_t *mfn, - p2m_type_t *t, p2m_access_t *a) -{ - ASSERT_UNREACHABLE(); - return -EOPNOTSUPP; -} -#define altp2m_get_effective_entry(ap2m, gfn, mfn, t, a, prepopulate) \ - _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) -#endif - /* Init the datastructures for later use by the p2m code */ int p2m_init(struct domain *d); @@ -885,91 +861,6 @@ void shadow_p2m_init(struct p2m_domain *p2m); void cf_check nestedp2m_write_p2m_entry_post( struct p2m_domain *p2m, unsigned int oflags); -#ifdef CONFIG_ALTP2M - -/* - * Alternate p2m: shadow p2m tables used for alternate memory views - */ - -/* get current alternate p2m table */ -static inline struct p2m_domain *p2m_get_altp2m(struct vcpu *v) -{ - unsigned int index = vcpu_altp2m(v).p2midx; - - if ( index == INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >= v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool p2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >= v->domain->nr_altp2m); - - if ( idx == vcpu_altp2m(v).p2midx ) - return false; - - orig = p2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - -/* Switch alternate p2m for a single vcpu */ -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx); - -/* Flush all the alternate p2m's for a domain */ -void p2m_flush_altp2m(struct domain *d); - -/* Make a specific alternate p2m valid */ -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Find an available alternate p2m and make it valid */ -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access); - -/* Make a specific alternate p2m invalid */ -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Switch alternate p2m for entire domain */ -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); - -/* Change a gfn->mfn mapping */ -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn); - -/* Set a specific p2m view visibility */ -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_idx, - uint8_t visible); - -#else /* !CONFIG_ALTP2M */ -struct p2m_domain *p2m_get_altp2m(struct vcpu *v); -bool p2m_set_altp2m(struct vcpu *v, unsigned int idx); -#endif /* CONFIG_ALTP2M */ - -/* - * Common alternate p2m declarations that need to be visible - * regardless of CONFIG_ALTP2M - */ - -/* Alternate p2m paging */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_order); - -/* Propagate a host p2m change to all alternate p2m's */ -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma); #endif /* CONFIG_HVM */ /* p2m access to IOMMU flags */ diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 8dd3c0f96be0..2dc84b76b8c1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -24,7 +24,7 @@ altp2m_vcpu_initialise(struct vcpu *v) vcpu_pause(v); vcpu_altp2m(v).p2midx = 0; - atomic_inc(&p2m_get_altp2m(v)->active_vcpus); + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); altp2m_vcpu_update_p2m(v); @@ -43,7 +43,7 @@ altp2m_vcpu_destroy(struct vcpu *v) if ( v != current ) vcpu_pause(v); - if ( (p2m = p2m_get_altp2m(v)) ) + if ( (p2m = altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); altp2m_vcpu_disable_ve(v); @@ -123,7 +123,7 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } -int p2m_init_altp2m(struct domain *d) +int altp2m_init(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -140,7 +140,7 @@ int p2m_init_altp2m(struct domain *d) d->altp2m_p2m[i] = p2m = p2m_init_one(d); if ( p2m == NULL ) { - p2m_teardown_altp2m(d); + altp2m_teardown(d); return -ENOMEM; } p2m->p2m_class = p2m_alternate; @@ -151,7 +151,7 @@ int p2m_init_altp2m(struct domain *d) return 0; } -void p2m_teardown_altp2m(struct domain *d) +void altp2m_teardown(struct domain *d) { unsigned int i; struct p2m_domain *p2m; @@ -207,13 +207,13 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, return 0; } -void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +void altp2m_check(struct vcpu *v, uint16_t idx) { if ( altp2m_active(v->domain) ) - p2m_switch_vcpu_altp2m_by_id(v, idx); + altp2m_switch_vcpu_by_id(v, idx); } -bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) +bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) { struct domain *d = v->domain; bool rc = false; @@ -225,7 +225,7 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) if ( d->arch.altp2m_eptp[idx] != mfn_x(INVALID_MFN) ) { - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); rc = 1; } @@ -246,9 +246,9 @@ bool p2m_switch_vcpu_altp2m_by_id(struct vcpu *v, unsigned int idx) * the host's entry to the altp2m (retaining page order), and indicate * that the caller should re-try the faulting instruction. */ -bool p2m_altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, - mfn_t *mfn, p2m_type_t *p2mt, - p2m_access_t *p2ma, unsigned int *page_order) +bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, + mfn_t *mfn, p2m_type_t *p2mt, p2m_access_t *p2ma, + unsigned int *page_order) { p2m_type_t ap2mt; p2m_access_t ap2ma; @@ -319,8 +319,8 @@ enum altp2m_reset_type { ALTP2M_DEACTIVATE }; -static void p2m_reset_altp2m(struct domain *d, unsigned int idx, - enum altp2m_reset_type reset_type) +static void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type) { struct p2m_domain *p2m; @@ -344,7 +344,7 @@ static void p2m_reset_altp2m(struct domain *d, unsigned int idx, p2m_unlock(p2m); } -void p2m_flush_altp2m(struct domain *d) +void altp2m_flush(struct domain *d) { unsigned int i; @@ -352,7 +352,7 @@ void p2m_flush_altp2m(struct domain *d) for ( i = 0; i < d->nr_altp2m; i++ ) { - p2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[i] = mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); } @@ -360,8 +360,8 @@ void p2m_flush_altp2m(struct domain *d) altp2m_list_unlock(d); } -static int p2m_activate_altp2m(struct domain *d, unsigned int idx, - p2m_access_t hvmmem_default_access) +static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access) { struct p2m_domain *hostp2m, *p2m; int rc; @@ -399,9 +399,9 @@ static int p2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_unlock(p2m); return rc; -} + } -int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_init_by_id(struct domain *d, unsigned int idx) { int rc = -EINVAL; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); @@ -413,14 +413,14 @@ int p2m_init_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == mfn_x(INVALID_MFN) ) - rc = p2m_activate_altp2m(d, idx, hostp2m->default_access); + rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); altp2m_list_unlock(d); return rc; } -int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, - xenmem_access_t hvmmem_default_access) +int altp2m_init_next_available(struct domain *d, uint16_t *idx, + xenmem_access_t hvmmem_default_access) { int rc = -EINVAL; unsigned int i; @@ -438,7 +438,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, if ( d->arch.altp2m_eptp[i] != mfn_x(INVALID_MFN) ) continue; - rc = p2m_activate_altp2m(d, i, a); + rc = altp2m_activate_altp2m(d, i, a); if ( !rc ) *idx = i; @@ -450,7 +450,7 @@ int p2m_init_next_altp2m(struct domain *d, uint16_t *idx, return rc; } -int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_destroy_by_id(struct domain *d, unsigned int idx) { struct p2m_domain *p2m; int rc = -EBUSY; @@ -472,7 +472,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) if ( !_atomic_read(p2m->active_vcpus) ) { - p2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); + altp2m_reset_altp2m(d, idx, ALTP2M_DEACTIVATE); d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] = mfn_x(INVALID_MFN); d->arch.altp2m_visible_eptp[array_index_nospec(idx, MAX_EPTP)] = @@ -488,7 +488,7 @@ int p2m_destroy_altp2m_by_id(struct domain *d, unsigned int idx) return rc; } -int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) +int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) { struct vcpu *v; int rc = -EINVAL; @@ -506,7 +506,7 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) if ( d->arch.altp2m_visible_eptp[idx] != mfn_x(INVALID_MFN) ) { for_each_vcpu( d, v ) - if ( p2m_set_altp2m(v, idx) ) + if ( altp2m_set_altp2m(v, idx) ) altp2m_vcpu_update_p2m(v); rc = 0; @@ -519,8 +519,8 @@ int p2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) return rc; } -int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, - gfn_t old_gfn, gfn_t new_gfn) +int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, + gfn_t new_gfn) { struct p2m_domain *hp2m, *ap2m; p2m_access_t a; @@ -571,11 +571,11 @@ int p2m_change_altp2m_gfn(struct domain *d, unsigned int idx, p2m_unlock(ap2m); p2m_unlock(hp2m); return rc; -} + } -int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, - mfn_t mfn, unsigned int page_order, - p2m_type_t p2mt, p2m_access_t p2ma) +int altp2m_propagate_change(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order, p2m_type_t p2mt, + p2m_access_t p2ma) { struct p2m_domain *p2m; unsigned int i; @@ -605,7 +605,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, { if ( !reset_count++ ) { - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); last_reset_idx = i; } else @@ -617,7 +617,7 @@ int p2m_altp2m_propagate_change(struct domain *d, gfn_t gfn, d->arch.altp2m_eptp[i] == mfn_x(INVALID_MFN) ) continue; - p2m_reset_altp2m(d, i, ALTP2M_RESET); + altp2m_reset_altp2m(d, i, ALTP2M_RESET); } ret = 0; @@ -768,8 +768,8 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, return rc; } -int p2m_set_altp2m_view_visibility(struct domain *d, unsigned int altp2m_idx, - uint8_t visible) +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) { int rc = 0; diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e5548e64d8d0..0492356d99ad 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -81,7 +81,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v, struct p2m_domain *p2m = NULL; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -145,7 +145,7 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, int rc; if ( altp2m_active(d) ) - p2m = p2m_get_altp2m(v); + p2m = altp2m_get_altp2m(v); if ( !p2m ) p2m = p2m_get_hostp2m(d); @@ -252,9 +252,10 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, return (p2ma != p2m_access_n2rwx); } -static int p2m_set_altp2m_mem_access(struct domain *d, struct p2m_domain *hp2m, - struct p2m_domain *ap2m, p2m_access_t a, - gfn_t gfn) +static int altp2m_set_altp2m_mem_access(struct domain *d, + struct p2m_domain *hp2m, + struct p2m_domain *ap2m, p2m_access_t a, + gfn_t gfn) { mfn_t mfn; p2m_type_t t; @@ -281,7 +282,7 @@ static int set_mem_access(struct domain *d, struct p2m_domain *p2m, if ( ap2m ) { - rc = p2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); + rc = altp2m_set_altp2m_mem_access(d, p2m, ap2m, a, gfn); /* If the corresponding mfn is invalid we will want to just skip it */ if ( rc == -ESRCH ) rc = 0; diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index ce14066fedaf..433e7d08b78f 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -128,7 +128,7 @@ int p2m_init(struct domain *d) return rc; } - rc = altp2m_supported() ? p2m_init_altp2m(d) : 0; + rc = altp2m_supported() ? altp2m_init(d) : 0; if ( rc ) { p2m_teardown_hostp2m(d); @@ -198,7 +198,7 @@ void p2m_final_teardown(struct domain *d) if ( is_hvm_domain(d) ) { if ( altp2m_supported() ) - p2m_teardown_altp2m(d); + altp2m_teardown(d); /* * We must tear down nestedp2m unconditionally because * we initialise it unconditionally. diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index 84159198f3a0..a6f61a9dd3d7 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -773,7 +773,7 @@ bool ept_handle_misconfig(uint64_t gpa) int rc; if ( altp2m_active(curr->domain) ) - p2m = p2m_get_altp2m(curr); + p2m = altp2m_get_altp2m(curr); p2m_lock(p2m); @@ -997,7 +997,7 @@ out: if ( altp2m_supported() && entry_written && p2m_is_hostp2m(p2m) ) { - ret = p2m_altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); + ret = altp2m_propagate_change(d, _gfn(gfn), mfn, order, p2mt, p2ma); if ( !rc ) rc = ret; } diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 635f5a7f45cd..64218878067e 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -19,9 +19,6 @@ static inline int p2m_init_logdirty(struct p2m_domain *p2m) { return 0; } static inline void p2m_free_logdirty(struct p2m_domain *p2m) {} #endif -int p2m_init_altp2m(struct domain *d); -void p2m_teardown_altp2m(struct domain *d); - void p2m_flush_table_locked(struct p2m_domain *p2m); int __must_check p2m_remove_entry(struct p2m_domain *p2m, gfn_t gfn, mfn_t mfn, unsigned int page_order); diff --git a/xen/common/vm_event.c b/xen/common/vm_event.c index cf0258223f50..77e0c8a0b240 100644 --- a/xen/common/vm_event.c +++ b/xen/common/vm_event.c @@ -433,7 +433,7 @@ static int vm_event_resume(struct domain *d, struct vm_event_domain *ved) /* Check for altp2m switch */ if ( IS_ENABLED(CONFIG_ALTP2M) && rsp.flags & VM_EVENT_FLAG_ALTERNATE_P2M ) - p2m_altp2m_check(v, rsp.altp2m_idx); + altp2m_check(v, rsp.altp2m_idx); if ( rsp.flags & VM_EVENT_FLAG_SET_REGISTERS ) vm_event_set_registers(v, &rsp); diff --git a/xen/include/xen/p2m-common.h b/xen/include/xen/p2m-common.h index f0bd9a6b9896..6da330acca1f 100644 --- a/xen/include/xen/p2m-common.h +++ b/xen/include/xen/p2m-common.h @@ -25,7 +25,7 @@ int unmap_mmio_regions(struct domain *d, mfn_t mfn); /* Check to see if vcpu should be switched to a different p2m. */ -void p2m_altp2m_check(struct vcpu *v, uint16_t idx); +void altp2m_check(struct vcpu *v, uint16_t idx); /* * Populate-on-Demand -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287765.1568183 (Exim 4.92) (envelope-from ) id 1wEwEp-0000LC-EP; Mon, 20 Apr 2026 21:33:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287765.1568183; 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All code used in the command implementation already works on ARM, so no further changes beyond moving the #ifdef are necessary. This is commit 1/1 of the get_domain_state phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This commit can be squashed into the previous commit for the actual submission if that would be preferred, but I thought it might be easier to understand the command #ifdef gate approach by splitting this into a separate patch. --- xen/common/altp2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 6481fae1ed12..3a3283f0860a 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -124,12 +124,12 @@ int do_altp2m_op( switch ( a.cmd ) { -#ifdef CONFIG_X86 case HVMOP_altp2m_get_domain_state: a.u.domain_state.state = altp2m_active(d); rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; +#ifdef CONFIG_X86 case HVMOP_altp2m_set_domain_state: { struct vcpu *v; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287774.1568196 (Exim 4.92) (envelope-from ) id 1wEwEu-000175-Cw; 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This makes it possible to use these functions in the common altp2m init/teardown routines. This is commit 1/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/p2m.h | 3 +++ xen/arch/x86/mm/p2m.h | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 5110b3e77807..ce8eeb751ee9 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -592,6 +592,9 @@ int p2m_alloc_table(struct p2m_domain *p2m); void p2m_teardown(struct p2m_domain *p2m, bool remove_root, bool *preempted); void p2m_final_teardown(struct domain *d); +struct p2m_domain *p2m_init_one(struct domain *d); +void p2m_free_one(struct p2m_domain *p2m); + /* Add/remove a page to/from a domain's p2m table. */ int p2m_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, unsigned int page_order, p2m_type_t t); diff --git a/xen/arch/x86/mm/p2m.h b/xen/arch/x86/mm/p2m.h index 64218878067e..be8ed85c2aba 100644 --- a/xen/arch/x86/mm/p2m.h +++ b/xen/arch/x86/mm/p2m.h @@ -6,9 +6,6 @@ #ifndef __ARCH_MM_P2M_H__ #define __ARCH_MM_P2M_H__ -struct p2m_domain *p2m_init_one(struct domain *d); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ct7OYHDuserQjrdnXDT2Q3J5e72VZGG2o8HBBgpiIsc=; b=yup9cAILf0EpH+wtp1z5sA7aIKNNcykenfh2egbPAUzo60O53UcUxcxfZJ+JOm60VD7YxEZC9FSvKCYIcdBX7jOeQU33EtenmVB7t99gaxIwq0HGAf+r/pVqZlcBXxYlZ6EqS/9jmaUG0yyxernG8Uyg17ZJfp/CNAF0x/hI37U= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 13/43] x86/altp2m: Add lock functions accessible from common code Date: Mon, 20 Apr 2026 17:31:36 -0400 Message-ID: <20260420213206.208750-14-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C8:EE_|DM4PR08MB8193:EE_|SJ1PEPF00001CE0:EE_|DM3PR08MB9588:EE_ X-MS-Office365-Filtering-Correlation-Id: ab5465d7-e51c-437d-14c8-08de9f246640 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162011799003|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Jx5Ffm19SI+vyxU1BNRtqCnpOeoKQcy9sD9oLma7K7LBYo+TzAO/Sk65rryYAkHfUJjpmpDI6VzkFjGk8HDsla9WdLtBXC15qKhtz3tMZ5KZub1JyuKKQSh++JWpReLR+4nsk8qG8I/UtDg/b+T7g0OhzCnV1bEe0fKNwDi76JUNUQYcjHMG2zFsweetYZ3R35CEwDEVdC6F9reJxRANGySq3RvLXvqyiWEkWTxGewTjV+TNU12qOrSjov5waWNZe/KJgewBPlzrkVuUgyhKzdYRKulWr0GibmQfoV9D/H6QpcAUz0t4S1y2RG2Wo3cFeTmzt1iPM/3lJZb9GD2Ppkd5ZfXXSjqJwBmjhBwvLVGqKeHn0myWy7R12GI7Wf098MPJ1oX2ZzQlkinkZG+bHQTJHDCiknf1uR6An2rlBDC8OXdxhHXZSkMLZJerU3q4 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:01.3929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab5465d7-e51c-437d-14c8-08de9f246640 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ1PEPF00001CE0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR08MB9588 X-purgate-ID: tlsNG-d62444/1776720790-BEC7CFF4-766920CD/0/0 X-purgate-type: clean X-purgate-size: 6429 This commit adds three altp2m_lock functions which wrap the corresponding altp2m_list_lock functions present in "mm-locks.h". The "mm-locks.h" file is only accessible in x86 code. In order to make altp2m common across architectures, it must be possible to acquire the altp2m lock without including an x86-specific header file. These functions cannot be static inline like their "mm-locks.h" counterparts, since "mm-locks.h" is only included in source files, not header files. Therefore, these functions might introduce a slight function call overhead over their "mm-locks.h" counterparts. However, the altp2m lock is mostly used in init/teardown routines and HVMOP implementations. For these cases, the altp2m_list_lock functions have been switched out for the altp2m_lock functions so they can be later migrated to common code. The only other function using the altp2m lock is altp2m_get_or_propagate, which is in the hot path of the page fault handler, so the altp2m_list_lock calls have not been replaced for that function. This is commit 2/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This seems like the solution which makes the most sense here, but it would be nicer if it could be static inline. I'm also not sure if the "mm-locks.h" functions are really supposed to be exposed outside of their translation unit like this, so feedback on this is appreciated. --- xen/arch/x86/include/asm/altp2m.h | 4 +++ xen/arch/x86/mm/altp2m.c | 42 ++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 9c58a396448d..7cff40beb7c6 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -156,6 +156,10 @@ int p2m_set_suppress_ve_multi(struct domain *d, int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, unsigned int altp2m_idx); +void altp2m_lock_init(struct domain *d); +void altp2m_lock(struct domain *d); +void altp2m_unlock(struct domain *d); + #else static inline bool altp2m_is_eptp_valid(const struct domain *d, diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 2dc84b76b8c1..371bf3f0b8d4 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -129,7 +129,7 @@ int altp2m_init(struct domain *d) struct p2m_domain *p2m; struct p2m_domain *hostp2m = p2m_get_hostp2m(d); - mm_lock_init(&d->arch.altp2m_list_lock); + altp2m_lock_init(d); d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); if ( !d->altp2m_p2m ) @@ -221,7 +221,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) if ( idx >= d->nr_altp2m ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[idx] != mfn_x(INVALID_MFN) ) { @@ -230,7 +230,7 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx) rc = 1; } - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -348,7 +348,7 @@ void altp2m_flush(struct domain *d) { unsigned int i; - altp2m_list_lock(d); + altp2m_lock(d); for ( i = 0; i < d->nr_altp2m; i++ ) { @@ -357,7 +357,7 @@ void altp2m_flush(struct domain *d) d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); } - altp2m_list_unlock(d); + altp2m_unlock(d); } static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, @@ -409,13 +409,13 @@ int altp2m_init_by_id(struct domain *d, unsigned int idx) if ( idx >= d->nr_altp2m ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == mfn_x(INVALID_MFN) ) rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -431,7 +431,7 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, !xenmem_access_to_p2m_access(hostp2m, hvmmem_default_access, &a) ) return rc; - altp2m_list_lock(d); + altp2m_lock(d); for ( i = 0; i < d->nr_altp2m; i++ ) { @@ -446,7 +446,7 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, break; } - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } @@ -463,7 +463,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int idx) return rc; rc = -EBUSY; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN) ) @@ -481,7 +481,7 @@ int altp2m_destroy_by_id(struct domain *d, unsigned int idx) } } - altp2m_list_unlock(d); + altp2m_unlock(d); domain_unpause_except_self(d); @@ -501,7 +501,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) return rc; rc = -EINVAL; - altp2m_list_lock(d); + altp2m_lock(d); if ( d->arch.altp2m_visible_eptp[idx] != mfn_x(INVALID_MFN) ) { @@ -512,7 +512,7 @@ int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx) rc = 0; } - altp2m_list_unlock(d); + altp2m_unlock(d); domain_unpause_except_self(d); @@ -773,7 +773,7 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, { int rc = 0; - altp2m_list_lock(d); + altp2m_lock(d); if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) rc = -EINVAL; @@ -784,11 +784,23 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, d->arch.altp2m_visible_eptp[array_index_nospec(altp2m_idx, MAX_EPTP)] = mfn_x(INVALID_MFN); - altp2m_list_unlock(d); + altp2m_unlock(d); return rc; } +void altp2m_lock_init(struct domain *d) { + mm_lock_init(&d->arch.altp2m_list_lock); +} + +void altp2m_lock(struct domain *d) { + altp2m_list_lock(d); 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The functions are gated by CONFIG_X86, so there is effectively no difference despite common code normally being compiled for ARM. This commit contains only renames/code movement, and no functional change is intended. This is commit 3/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 8 ----- xen/arch/x86/mm/altp2m.c | 45 ---------------------------- xen/arch/x86/mm/p2m-basic.c | 1 + xen/common/altp2m.c | 49 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 13 ++++++++ 5 files changed, 63 insertions(+), 53 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 7cff40beb7c6..13017525a62f 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -97,12 +97,6 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) return true; } -/* Initialize altp2m views */ -int altp2m_init(struct domain *d); - -/* Free altp2m views */ -void altp2m_teardown(struct domain *d); - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); @@ -184,8 +178,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) /* Only declaration is needed. DCE will optimise it out when linking. */ -int altp2m_init(struct domain *d); -void altp2m_teardown(struct domain *d); struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 371bf3f0b8d4..46374373848d 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -123,51 +123,6 @@ void altp2m_vcpu_disable_ve(struct vcpu *v) } } -int altp2m_init(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - struct p2m_domain *hostp2m = p2m_get_hostp2m(d); - - altp2m_lock_init(d); - d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); - - if ( !d->altp2m_p2m ) - return -ENOMEM; - - for ( i = 0; i < d->nr_altp2m; i++ ) - { - d->altp2m_p2m[i] = p2m = p2m_init_one(d); - if ( p2m == NULL ) - { - altp2m_teardown(d); - return -ENOMEM; - } - p2m->p2m_class = p2m_alternate; - p2m->access_required = hostp2m->access_required; - _atomic_set(&p2m->active_vcpus, 0); - } - - return 0; -} - -void altp2m_teardown(struct domain *d) -{ - unsigned int i; - struct p2m_domain *p2m; - - for ( i = 0; i < d->nr_altp2m; i++ ) - { - if ( !d->altp2m_p2m[i] ) - continue; - p2m = d->altp2m_p2m[i]; - d->altp2m_p2m[i] = NULL; - p2m_free_one(p2m); - } - - XVFREE(d->altp2m_p2m); -} - int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate) diff --git a/xen/arch/x86/mm/p2m-basic.c b/xen/arch/x86/mm/p2m-basic.c index 433e7d08b78f..67cef5d2b6ef 100644 --- a/xen/arch/x86/mm/p2m-basic.c +++ b/xen/arch/x86/mm/p2m-basic.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 3a3283f0860a..cda653b713f0 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -2,8 +2,10 @@ #include #include #include +#include #include +#include #include @@ -13,6 +15,53 @@ #include #endif +#if CONFIG_X86 +int altp2m_init(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + struct p2m_domain *hostp2m = p2m_get_hostp2m(d); + + altp2m_lock_init(d); + d->altp2m_p2m = xvzalloc_array(struct p2m_domain *, d->nr_altp2m); + + if ( !d->altp2m_p2m ) + return -ENOMEM; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + d->altp2m_p2m[i] = p2m = p2m_init_one(d); + if ( p2m == NULL ) + { + altp2m_teardown(d); + return -ENOMEM; + } + p2m->p2m_class = p2m_alternate; + p2m->access_required = hostp2m->access_required; + _atomic_set(&p2m->active_vcpus, 0); + } + + return 0; +} + +void altp2m_teardown(struct domain *d) +{ + unsigned int i; + struct p2m_domain *p2m; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + if ( !d->altp2m_p2m[i] ) + continue; + p2m = d->altp2m_p2m[i]; + d->altp2m_p2m[i] = NULL; + p2m_free_one(p2m); + } + + XVFREE(d->altp2m_p2m); +} +#endif /* CONFIG_X86 */ + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index be627152668a..85ef22c2b29e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,19 @@ #include +/* + * Common alternate p2m declarations that need to be visible + * regardless of CONFIG_ALTP2M + */ + +#ifdef CONFIG_X86 +/* Initialize altp2m views */ +int altp2m_init(struct domain *d); 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This is commit 9/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/p2m.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index fb03978a19af..2c43b6033360 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -286,24 +286,24 @@ int p2m_alloc_vmid(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - int rc, nr; + int rc, vmid; spin_lock(&vmid_alloc_lock); - nr = find_first_zero_bit(vmid_mask, MAX_VMID); + vmid = find_first_zero_bit(vmid_mask, MAX_VMID); - ASSERT(nr != INVALID_VMID); + ASSERT(vmid != INVALID_VMID); - if ( nr == MAX_VMID ) + if ( vmid == MAX_VMID ) { rc = -EBUSY; printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain_id); goto out; } - set_bit(nr, vmid_mask); + set_bit(vmid, vmid_mask); - p2m->vmid = nr; + p2m->vmid = vmid; rc = 0; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287797.1568225 (Exim 4.92) (envelope-from ) id 1wEwF3-0002bO-6r; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ej7dFzE95/mxjle91y5ZtkEL1w2ddUa/q0swOMw/TCSYmDnpHXrvAszO7Zc/9MshORWAYj5KByFS9jf+9dOWizThvl68udctGlA2QU8TAVlLbDzCBTaf1Yv28W2aXFU5dsEd2Eoz0VvuaRsk3uphTQpp6/y1+34PMUKzUPwR/F/0+aVh57w/HRfxne5zL/mXfdNvP0hw4oRwQ1aqrkgGhGHPW/7tJ2PXels9OWCp2h6FMPrE413VOI6xsYN5NjEZYExQ74x48Ka8xoJdlh4NrDATSQcr+ldVWZatMVaYmyJTPewExk8C0fYlxryaqZtl5H+2zIp0PMFUlVlsX4hdcy4TXHBHym7p2XQU3QY9Bh35C0sCYt6rHuvytujuL4Ds+3mSUeR1wQZulIdO+kKwbieH8gP3T1savTZ8m+CHdLE3EtcbzfJkikLN1i3ZxZ51 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:08.8042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00101def-7e94-437e-9704-08de9f246abb X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF00000142.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR08MB8854 X-purgate-ID: tlsNG-d25034/1776720794-6EB74CF5-E87EB8AB/0/0 X-purgate-type: clean X-purgate-size: 4874 This commit invalidates the root page table entries and flushes the TLB when the table is flushed. The TLB is flushed to ensure that altp2m views after being reset or torn down. Previously, the code in p2m_flush_table was only used to free p2m pages during domain teardown. This function will later be used to teardown/reset altp2m views of a still-running domain, so the page table entries must be properly invalidated. Additionally, the p2m_invalidate_root function is split into p2m_invalidate_root and p2m_invalidate_root_locked. The p2m_flush_table function already holds the lock, so it calls p2m_invalidate_root_locked directly, as opposed to the existing callers which don't already hold the lock. This is commit 7/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v3: Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). v6: Introduced this patch. While the code in this patch is mostly new, it is the same in spirit as the p2m_flush_table additions in the original patch series, so the relevant comments have been reproduced above. In the v4/v5 versions of this patch series, this patch was a part of the previous patch. It has been split out to minimize the number of functionality changes in the previous patch. Additionally, the original patch series used a routine here which was nearly identical to p2m_invalidate_root, which was implemented a few years after the patch series. Therefore, the existing p2m_invalidate_root implementation is used here instead. Also, since the original patch series p2m_teardown (and by extension p2m_flush_table, as it was extracted from p2m_teardown) was made preemptible. As a consequence of this, introducing a call to p2m_invalidate_root here also means that p2m_invalidate_root and p2m_tlb_flush_sync is called each time p2m_flush_table is called, even if a previous call to p2m_flush_table was preempted. This might cause some additional overhead, as p2m_flush_table will iterate over the root page tables and flush the TLB before it can return to freeing p2m pages. I'm not sure if there's a better way of handling this, or if the overhead here is negligible/acceptable. I'm not sure how IOMMU interacts with altp2m here. I haven't looked into it extensively, so I would appreciate some feedback here. I've just copied over the iommu_use_hap_pt conditional from p2m_domain_creation_finished, but this is probably not the right behavior since we probably still need to invalidate the altp2m view page tables on flush somehow. Is the issue with invalidating root page tables when using IOMMU only relevant for the hostp2m, or is it also relevant for the altp2m views? --- xen/arch/arm/mmu/p2m.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1d598c66450b..51753bb2c34d 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1271,17 +1271,20 @@ void p2m_clear_root_pages(struct p2m_domain *p2m) * p2m_invalid_root() should not be called when the P2M is shared with * the IOMMU because it will cause IOMMU fault. */ -static void p2m_invalidate_root(struct p2m_domain *p2m) +static void p2m_invalidate_root_locked(struct p2m_domain *p2m) { unsigned int i; ASSERT(!iommu_use_hap_pt(p2m->domain)); - p2m_write_lock(p2m); - for ( i = 0; i < P2M_ROOT_PAGES; i++ ) p2m_invalidate_table(p2m, page_to_mfn(p2m->root + i)); +} +static void p2m_invalidate_root(struct p2m_domain *p2m) +{ + p2m_write_lock(p2m); + p2m_invalidate_root_locked(p2m); p2m_write_unlock(p2m); } @@ -1449,6 +1452,13 @@ int p2m_flush_table(struct p2m_domain *p2m) unsigned long count = 0; struct page_info *pg; + /* TODO: How does IOMMU interact with altp2m? */ + if ( !iommu_use_hap_pt(p2m->domain) ) + { + p2m_invalidate_root_locked(p2m); + p2m_tlb_flush_sync(p2m); + } + while ( (pg = page_list_remove_head(&p2m->pages)) ) { p2m_free_page(p2m->domain, pg); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287808.1568235 (Exim 4.92) (envelope-from ) id 1wEwF5-000323-AX; Mon, 20 Apr 2026 21:33:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287808.1568235; Mon, 20 Apr 2026 21:33:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwF4-00030o-R8; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3zKjeuTBo5ThjLRAR4VX8MiSoHzlUKvbdA67uPmxOQWgAHJQH6nGtPhMiZ6HeMS0G8l15t1SpO60pHPhf9I2554hE39awFKnkUMAY433l8H7gGNJhw/B5KX8PMovQ3mxV0Yi5hMGITEg2o768T4X8xplCawY5/f9fcM2hJmLBtYUuQrEYARs2l22269jzIFbuvZGfK+dADqaUZUMAzqf6VtfC34JgLEdNOqnRWQEik2h22S5MLTlMBoGEokliTz1mJonIq5A/kvFPr0/2NRbFPS1Y33P+WucY1qnoGgK64+X6FdJkJSS5zI8QmluiEHoZiLS1E/b3jlZjV9LuTpH9HYuc7Zd1tPqDxkU4itABuQQLoUhUG0pSWulI10/7FMuCyPklrZPYScrpnWMRnulVohaA+vDBN6q78585pwc2USyKNP85p31so8ilQVqJd0Q X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:10.8475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6ebd96d-aeb3-451e-35d2-08de9f246bf2 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR08MB6541 X-purgate-ID: tlsNG-720697/1776720796-886D4161-1FEE0194/0/0 X-purgate-type: clean X-purgate-size: 1730 From: Sergej Proskurin This commit adds a p2m class to the struct p2m_domain to distinguish between the host's original p2m and alternate p2m's. The need for this functionality will be shown in the following commits. This is commit 11/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v4: Change return type of p2m_is_(hostp2m|altp2m) from bool_t to bool. --- xen/arch/arm/include/asm/p2m.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 62261d41e780..8ae0cd7ff589 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -32,6 +32,11 @@ struct domain; extern void memory_type_changed(struct domain *d); +typedef enum { + p2m_host, + p2m_alternate, +} p2m_class_t; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -111,6 +116,9 @@ struct p2m_domain { /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; + + /* Choose between: host/alternate. */ + p2m_class_t p2m_class; }; /* @@ -424,6 +432,16 @@ static inline int get_page_and_type(struct page_info *page, /* get host p2m table */ #define p2m_get_hostp2m(d) ((d)->arch.p2m) +static inline bool p2m_is_hostp2m(const struct p2m_domain *p2m) +{ + return p2m->p2m_class == p2m_host; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: We0n7kf4vpuWmcMuhnIplB4lhjmFZi8kulX/NM2scKTnyCVywmkdcfW5ASVzkW5QeNRg3ZI3KJ68jVOUx/+xHk0hZNQcW8yI3nYppeUF1SHNjlI7bPCa9/tSATXS9WFJ06rtA2OlOKf3d0Ihkt9UVHolBjmIRUr1zNq5cVFtJ4QQw9sFzChXGxy1l+mKhGVjzX0k6Ch0EABOgBFHf9UDOD/kZoAgVWKTLKwZUm3RkhXyNct0y29xXm5y3ODn+aH0nnjl+13KaoFUNMEPKhW224d5yjoJerJa6fyYZaksucm++Azo+zin1QqbxzqW0YDN9SZYvRHPdI3rbcS+Un38oL5iM4MWlHKWykkD+5TEyjT3nxCJMAyBgAWL0PIYqQcO6ViqQVRLdxewmlegMKQt015g0pe0gz0VjCrN7VbX1wfvDK7W5wb0qr3zdktuHQaG X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:08.4622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d92189a4-97ed-4be0-92ad-08de9f246a82 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF00000140.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB9466 X-purgate-ID: tlsNG-bad1c0/1776720796-92772A53-59463CAE/0/0 X-purgate-type: clean X-purgate-size: 7264 This commit replaces the concrete p2m_domain member in arch_domain with a pointer to p2m_domain, which is allocated with xzalloc during p2m initialization. In the following commits, the altp2m_init and altp2m_teardown routines from x86 are be moved to common code. These routines (respectively) allocate and free the p2m_domain structs for altp2m views. While it would be possible to have special code paths for allocating/freeing altp2m views while keeping the hostp2m as an concrete member, this results in code duplication and increases complexity without any clear benefit. Therefore, switching the hostp2m to be allocated separately from arch_domain (similarly to x86) makes it possible to use the same functions for both allocation/teardown/freeing of the hostp2m and altp2m views. This is commit 4/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/include/asm/domain.h | 2 +- xen/arch/arm/include/asm/p2m.h | 2 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 27 +++++++++++++++++++++--- xen/arch/arm/traps.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- 9 files changed, 32 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..be824a5ba18d 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -1099,7 +1099,7 @@ int domain_relinquish_resources(struct domain *d) * We are about to free the intermediate page-tables, so clear the * root to prevent any walk to use them. */ - p2m_clear_root_pages(&d->arch.p2m); + p2m_clear_root_pages(d->arch.p2m); PROGRESS(p2m): ret = p2m_teardown(d); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..576dbdec20af 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -72,7 +72,7 @@ struct arch_domain #endif /* Virtual MMU */ - struct p2m_domain p2m; + struct p2m_domain *p2m; struct hvm_domain hvm; diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..23df91ea13e9 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -410,7 +410,7 @@ static inline int get_page_and_type(struct page_info *page, } /* get host p2m table */ -#define p2m_get_hostp2m(d) (&(d)->arch.p2m) +#define p2m_get_hostp2m(d) ((d)->arch.p2m) static inline bool p2m_vm_event_sanity_check(struct domain *d) { diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6df8b616e464..46f9363ea851 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -116,7 +116,7 @@ bool page_is_offlinable(mfn_t mfn) unsigned long domain_get_maximum_gpfn(struct domain *d) { - return gfn_x(d->arch.p2m.max_mapped_gfn); + return gfn_x(d->arch.p2m->max_mapped_gfn); } void share_xen_page_with_guest(struct page_info *page, struct domain *d, diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51abf3504fcf..3ecb969a0369 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include @@ -1475,7 +1476,7 @@ void p2m_final_teardown(struct domain *d) /* p2m not actually initialized */ if ( !p2m->domain ) - return; + goto free_p2m; /* * No need to call relinquish_p2m_mapping() here because @@ -1499,11 +1500,13 @@ void p2m_final_teardown(struct domain *d) radix_tree_destroy(&p2m->mem_access_settings, NULL); p2m->domain = NULL; + +free_p2m: + xfree(p2m); } -int p2m_init(struct domain *d) +static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); int rc; unsigned int cpu; @@ -1556,6 +1559,24 @@ int p2m_init(struct domain *d) return 0; } +int p2m_init(struct domain *d) +{ + struct p2m_domain *p2m = xzalloc(struct p2m_domain); + int rc; + + if ( !p2m ) + return -ENOMEM; + + rc = p2m_initialise(d, p2m); + + if ( !rc ) + d->arch.p2m = p2m; + else + xfree(p2m); + + return rc; +} + /* * The function will go through the p2m and remove page reference when it * is required. The mapping will be removed from the p2m. diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 0c01f37ad6b4..637d27659b20 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -984,7 +984,7 @@ void vcpu_show_registers(struct vcpu *v) #endif #ifdef CONFIG_MMU - ctxt.vttbr_el2 = v->domain->arch.p2m.vttbr; + ctxt.vttbr_el2 = v->domain->arch.p2m->vttbr; #endif _show_registers(&v->arch.cpu_info->guest_cpu_user_regs, &ctxt, 1, v); diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index fa9ab9cb1330..d246c5e59005 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -565,7 +565,7 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain) * Use P2M table for this Xen domain. */ ASSERT(domain->d != NULL); - ttbr = page_to_maddr(domain->d->arch.p2m.root); + ttbr = page_to_maddr(domain->d->arch.p2m->root); dev_info(domain->mmu->root->dev, "%pd: Set IPMMU context %u (pgd 0x%"PRIx64")\n", domain->d, domain->context_id, ttbr); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index bf153227dbd9..a7fbe58cba77 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1205,7 +1205,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, vtcr->tsz = 64 - p2m_ipa_bits; vtcr->sl = 2 - P2M_ROOT_LEVEL; - arm_lpae_s2_cfg.vttbr = page_to_maddr(smmu_domain->d->arch.p2m.root); + arm_lpae_s2_cfg.vttbr = page_to_maddr(smmu_domain->d->arch.p2m->root); vmid = arm_smmu_bitmap_alloc(smmu->vmid_map, smmu->vmid_bits); if (vmid < 0) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index d63c9015510e..0975be2562bb 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -1247,7 +1247,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) /* TTBR0 */ /* Xen: The page table is shared with the P2M code */ ASSERT(smmu_domain->cfg.domain != NULL); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r5reXL1z6K5EdEg/2NZM7zmALNw0WD7hQk1Clp9adUSzPfVK1MxYBWEo4zuZJgWx7Mqjsj0C/z/jmRpb4in1+LEV+IhlA49cLyRyjp1qg9X0K0vMYf1bquxfqvxR1mTkfaXCtSIiW+ybLOTVCIZVMmDNuPubZOs/MEEfZ1JGaiQdPYYKdYpTqbk9Az4Dpl5ASmxgGTx0/j5vUBySMLaRFgPXxYofOu7+7wTX8g8fVt62IbKiUmXXzvcOjeZaTssPizSLYIwjlPU+K1bMy/yafmaa9whGULCidntFlwlKGj0Vq6c15ztuFEL/0KmneakgUQP3nmkGPxt+d3652j7MHlDPF4YPX1PHOM6/bizJduqKeHrzZ+uxh1qzbU8BjIo0q1ZhjTjVx+E0i9EHLLqJlzYxQN6JKgDfDdv5TOgZ10XVALXoUONmLe+9xu5ZiwOk X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:09.8813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 506760c6-d271-40b4-4ea2-08de9f246b3a X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CO1PEPF00012E80.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR08MB11076 X-purgate-ID: tlsNG-42698a/1776720797-7E36CF3B-2DB5D848/0/0 X-purgate-type: clean X-purgate-size: 3941 From: Sergej Proskurin This commit changes the prototype and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". The function "p2m_alloc_vmid" does not expect the struct domain as argument anymore and returns an allocated vmid. The function "p2m_free_vmid" takes only the vmid that is to be freed as argument. This is commit 10/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- v3: Changed function prototypes and implementation of the functions "p2m_alloc_vmid" and "p2m_free_vmid". Changes in "p2m_alloc_vmid": This function does not expect any arguments. Also, in this commit, the function "p2m_alloc_vmid" returns either the successfully allocated vmid or the value INVALID_VMID. Thus, it is now the responsibility of the caller to set the returned vmid in the associated fields. Changes in "p2m_free_vmid": This function expects now only the vmid of type uint8_t. --- xen/arch/arm/include/asm/p2m.h | 4 ++-- xen/arch/arm/mmu/p2m.c | 8 ++++---- xen/arch/arm/p2m.c | 23 ++++++++--------------- 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 5c6dfe4a9789..62261d41e780 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -195,8 +195,8 @@ static inline bool arch_acquire_resource_check(struct domain *d) void p2m_restrict_ipa_bits(unsigned int ipa_bits); void p2m_vmid_allocator_init(void); -int p2m_alloc_vmid(struct domain *d); -void p2m_free_vmid(struct domain *d); +uint8_t p2m_alloc_vmid(void); +void p2m_free_vmid(uint8_t vmid); /* Second stage paging setup, to be called on all CPUs */ void setup_virt_paging(void); diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index f546f63f2489..0d37760ef5d5 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1519,7 +1519,7 @@ void p2m_free_one(struct p2m_domain *p2m) p2m->root = NULL; - p2m_free_vmid(p2m->domain); + p2m_free_vmid(p2m->vmid); radix_tree_destroy(&p2m->mem_access_settings, NULL); @@ -1570,9 +1570,9 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) */ p2m->domain = d; - rc = p2m_alloc_vmid(d); - if ( rc ) - return rc; + p2m->vmid = p2m_alloc_vmid(); + if ( p2m->vmid == INVALID_VMID ) + return -EBUSY; rc = p2m_alloc_table(p2m); if ( rc ) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 2c43b6033360..3342fafcc8a7 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -282,11 +282,9 @@ void p2m_vmid_allocator_init(void) set_bit(INVALID_VMID, vmid_mask); } -int p2m_alloc_vmid(struct domain *d) +uint8_t p2m_alloc_vmid(void) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); - - int rc, vmid; + uint8_t vmid; spin_lock(&vmid_alloc_lock); @@ -296,28 +294,23 @@ int p2m_alloc_vmid(struct domain *d) if ( vmid == MAX_VMID ) { - rc = -EBUSY; - printk(XENLOG_ERR "p2m.c: dom%d: VMID pool exhausted\n", d->domain_id); + vmid = INVALID_VMID; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZGBQ3CiD4S7jBPBcrE2PlEsoH4GXHS78CwX4r10ql3Yt5FgorPc/IV2iClEVHsdugjQe1Pvkff98s4tYwex7W+uQQWtQl99a3wMugeGLYU1BshUZSkqaIiq8qBntxdjSOR36tmUdZ9JzqXywITzhm1zd7jVK/grYBO6fQgxId3QACwVOXL0z/Ej4JdWcQGnSpX2Rsi/cwDKTYTOouarazSn1O3B5gdAu6g0O7j+TCpmz0RBiW/b/w39OVelBLWlTn87Y+AcBNH1ub+/4lJphwa58TI0GS7UYgY0TCcYfKR1F15dVW2PgNFBBgH3sqfWnNaFKZ9GwSlcqCCq4thXzC2azX+fVnPb34ab++5hr7l7CDr5zTQObSVx1nrTuKc10xfYKq2JXr21QSOm2+JI/zrL4LW51u8D4eMUjyTEwsJs4kAx3Ux61bo0OeELk9pka X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:09.2141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f49ddc1c-3c46-49a9-59fc-08de9f246af9 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF0000013C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLAPR08MB6900 X-purgate-ID: tlsNG-4011c0/1776720797-81B878B7-ADDE490D/0/0 X-purgate-type: clean X-purgate-size: 10132 This commit pulls out generic init/teardown functionality out of "p2m_init" and "p2m_teardown" into "p2m_init_one", "p2m_teardown_one", "p2m_free_one", and "p2m_flush_table" functions. This allows our future implementation to reuse existing code for the initialization/teardown of altp2m views. On failure, the p2m_init_one function returns a null pointer. This means p2m_init_one doesn't return an error code, which prevents it from propagating the exact error from p2m_initialise (specifically, ENOMEM if allocation fails and EBUSY if the VMID pool is exhausted). However, returning a p2m_domain pointer simplifies usage for callers of p2m_init_one, as they can receive an allocated and initialized p2m_domain without needing to handle allocation separately. Therefore, the main p2m_init function will now return ENOMEM instead of EBUSY when the VMID pool is exhausted. This is commit 6/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- Cc: Stefano Stabellini Cc: Julien Grall --- v2: Added the function p2m_flush_table to the previous version. v3: Removed struct vttbr. Moved define INVALID_VTTBR to p2m.h. Exported function prototypes of "p2m_flush_table", "p2m_init_one", and "p2m_teardown_one" in p2m.h. Extended the function "p2m_flush_table" by additionally resetting the fields lowest_mapped_gfn and max_mapped_gfn. Added a "p2m_flush_tlb" call in "p2m_flush_table". On altp2m reset in function "altp2m_reset", it is important to flush the TLBs after clearing the root table pages and before clearing the intermediate altp2m page tables to prevent illegal access to stalled TLB entries on currently active VCPUs. Added a check checking whether p2m->root is NULL in p2m_flush_table. Renamed the function "p2m_free_one" to "p2m_teardown_one". Removed resetting p2m->vttbr in "p2m_teardown_one", as it the p2m will be destroyed afterwards. Moved call to "p2m_alloc_table" back to "p2m_init_one". Moved the introduction of the type p2m_class_t out of this patch. Moved the backpointer to the struct domain out of the struct p2m_domain. v4: Replaced the former use of clear_and_clean_page in p2m_flush_table by a routine that invalidates every p2m entry atomically. This avoids inconsistencies on CPUs that continue to use the views that are to be flushed (e.g., see altp2m_reset). Removed unnecessary initializations in the functions "p2m_init_one" and "p2m_teardown_one". Removed the define INVALID_VTTBR as it is not used any more. Cosmetic fixes. v6: Reworked to accommodate the hostp2m being allocated separately from arch_domain. Split p2m_teardown_one into p2m_teardown_one and p2m_free_one, with both having the same semantics as their x86 counterparts. The previous version of this patch also added code to p2m_flush_table. This has been split out into a separate commit to minimize the number of actual changes in this commit. Updated to account for the introduction of p2m_final_teardown. The code which previously was used to reclaim resources from the hostp2m during p2m_final_teardown was extracted into p2m_free_one. Now, p2m_final_teardown will call p2m_free_one on the hostp2m instead. The check for whether the p2m was actually initialized was moved into p2m_free_one. This means there is a slight behavior change where p2m_teardown_allocation will always be called, even if the p2m_domain was never initialized. I'm not sure if this is really a big deal (it does require the lock to be obtained, but this shouldn't be an issue at final teardown?), but if it is then I can duplicate the check from p2m_free_one to the top of p2m_final_teardown, which would replicate the previous behavior. For the sake of making the p2m_init_one function simple to use (and match the x86 function prototype), it returns a null pointer on error rather than an error code. While on x86 an error from p2m_init_one is always due to an ENOMEM return code (from xzalloc, zalloc_cpumask_var), on ARM p2m_initialise (called by p2m_init_one) can actually return EBUSY if the VMID pool is exhausted. Therefore, in this error case the null pointer return value of p2m_init_one obscures the true error code (EBUSY). Callers of p2m_init_one always return ENOMEM when p2m_init_one returns a null pointer, so this error will be propagated up as ENOMEM rather than EBUSY. The alternative to this would be to have callers pass a null **p2m_domain to p2m_init_one while still returning an integer return code. In order to preserve a common altp2m_init routine, this change would also have to be made on x86 (where there wouldn't be any real benefit, the return code is truly only ever ENOMEM). Therefore, it seems like an acceptable tradeoff to me to obscure the error in this case, but if other folks think we should handle this differently than I can revisit this. The p2m_teardown_allocation call and p2m_init_one return code changes mentioned above should be the only actual behavior changes in this patch, otherwise it should be just code movement. --- xen/arch/arm/include/asm/p2m.h | 12 ++++++ xen/arch/arm/mmu/p2m.c | 77 +++++++++++++++++++++++----------- 2 files changed, 65 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 23df91ea13e9..5c6dfe4a9789 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -216,6 +216,18 @@ int p2m_init(struct domain *d); int p2m_teardown(struct domain *d); void p2m_final_teardown(struct domain *d); +/* Flushes the page table held by the p2m. */ +int p2m_flush_table(struct p2m_domain *p2m); + +/* Initialize the p2m structure. */ +struct p2m_domain *p2m_init_one(struct domain *d); + +/* Release resources held by the p2m structure. */ +int p2m_teardown_one(struct p2m_domain *p2m); + +/* Free the p2m structure allocation. */ +void p2m_free_one(struct p2m_domain *p2m); + /* * Remove mapping refcount on each mapping page in the p2m * diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 1009f10e5db4..1d598c66450b 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1444,14 +1444,10 @@ static int p2m_alloc_table(struct domain *d) return 0; } -int p2m_teardown(struct domain *d) +int p2m_flush_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); unsigned long count = 0; struct page_info *pg; - int rc = 0; - - p2m_write_lock(p2m); while ( (pg = page_list_remove_head(&p2m->pages)) ) { @@ -1460,23 +1456,34 @@ int p2m_teardown(struct domain *d) /* Arbitrarily preempt every 512 iterations */ if ( !(count % 512) && hypercall_preempt_check() ) { - rc = -ERESTART; - break; + return -ERESTART; } } + return 0; +} + +int p2m_teardown_one(struct p2m_domain *p2m) +{ + int rc; + + p2m_write_lock(p2m); + rc = p2m_flush_table(p2m); p2m_write_unlock(p2m); return rc; } -void p2m_final_teardown(struct domain *d) +int p2m_teardown(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); - /* p2m not actually initialized */ - if ( !p2m->domain ) - goto free_p2m; + return p2m_teardown_one(p2m); +} + +void p2m_final_teardown(struct domain *d) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); /* * No need to call relinquish_p2m_mapping() here because @@ -1484,18 +1491,27 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ - ASSERT(page_list_empty(&p2m->pages)); - while ( p2m_teardown_allocation(d) == -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); + p2m_free_one(p2m); +} + +void p2m_free_one(struct p2m_domain *p2m) +{ + /* p2m not actually initialized */ + if ( !p2m->domain ) + goto free_p2m; + + ASSERT(page_list_empty(&p2m->pages)); + if ( p2m->root ) free_domheap_pages(p2m->root, P2M_ROOT_ORDER); p2m->root = NULL; - p2m_free_vmid(d); + p2m_free_vmid(p2m->domain); radix_tree_destroy(&p2m->mem_access_settings, NULL); @@ -1511,9 +1527,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) unsigned int cpu; rwlock_init(&p2m->lock); - spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&p2m->pages); - INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); p2m->vmid = INVALID_VMID; p2m->max_mapped_gfn = _gfn(0); @@ -1559,22 +1573,37 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) return 0; } -int p2m_init(struct domain *d) +struct p2m_domain *p2m_init_one(struct domain *d) { struct p2m_domain *p2m = xzalloc(struct p2m_domain); - int rc; + + if ( !p2m ) + return NULL; + + if ( !p2m_initialise(d, p2m) ) + return p2m; + + xfree(p2m); + return NULL; +} + +static int p2m_init_hostp2m(struct domain *d) +{ + struct p2m_domain *p2m = p2m_init_one(d); if ( !p2m ) return -ENOMEM; - rc = p2m_initialise(d, p2m); + d->arch.p2m = p2m; + return 0; +} - if ( !rc ) - d->arch.p2m = p2m; - else - xfree(p2m); +int p2m_init(struct domain *d) +{ + spin_lock_init(&d->arch.paging.lock); + INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); - return rc; + return p2m_init_hostp2m(d); } /* -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287817.1568264 (Exim 4.92) (envelope-from ) id 1wEwFB-0004E6-Bw; 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This makes it possible to track the current altp2m view being used by a VCPU. This is commit 2/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin --- v6: This patch was originally part of the "arm/p2m: Add HVMOP_altp2m_set_domain_state" patch from the v4/v5 patch series. It has been extracted into its own commit to make the patch series easier to follow. If it would be preferred, this commit can be squashed into another commit. Added support for the CONFIG_ALTP2M option. --- xen/arch/arm/include/asm/altp2m.h | 4 +--- xen/arch/arm/include/asm/domain.h | 5 +++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 5a217f48b103..bc695018e62c 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -26,9 +26,7 @@ static inline bool altp2m_supported(void) /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { - /* Not implemented yet */ - BUG(); - return 0; + return v->arch.ap2m_idx; } #else /* CONFIG_ALTP2M */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 9e69d62086cd..4d497a21b648 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -249,6 +249,11 @@ struct arch_vcpu struct vtimer virt_timer; bool vtimer_initialized; +#if CONFIG_ALTP2M + /* Alternate p2m index */ + uint16_t ap2m_idx; +#endif + /* * The full P2M may require some cleaning (e.g when emulation * set/way). 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: G19aiybS5qTlN6jNTwFEtE/gDynFwRnTfEnU5kVi4vcY/HovihddFd6mP7nTC2tfRfjEkabhijCnFzR1tRIeqF6YuxbsiW5JIMKguoPegAP0+mf9RZMpcmTbwmrDxePK9RTkFkSKE0IU5Sw7wZf9t6ftW+kMpOp/tmYVePhQm91/YgTfaNqpZE8UHsmDNu2Pw+snwEsfpXjuN6XW2k4ftQcfMU4iFp94oK74yCKlAqLLAAKCRcx5Mtl9NevDMHvLch+/xjA1iw0VcCM5dYvq7RYXCoUeMxtu7Wp1AUQrjzcvval82nwpDA7PfA0eKeBt+Q41OaoFyCIuRZdYynS8AqQFeryvw7EDfMGNzmK0hAKuUnI+bfKH0U+UifjxS6k4rijyCOvjQuYtolLufxiqesjDnodLHWFAufb/lFEwlBXuseB5RSN4Uw1UOR+rlXXu X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:11.4409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dab8fd8-aafc-4d97-beba-08de9f246c3f X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR08MB6382 X-purgate-ID: tlsNG-33051d/1776720799-28577938-0AED14B5/0/0 X-purgate-type: clean X-purgate-size: 999 From: Sergej Proskurin In ./xen/arch/arm/p2m.c, we compare the gfn's with INVALID_GFN throughout the code. Thus it makes sense to use the macro INVALID_GFN instead of a hard coded value to initialize "p2m->lowest_mapped_gfn". This is commit 5/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin --- xen/arch/arm/mmu/p2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 3ecb969a0369..1009f10e5db4 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1517,7 +1517,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) p2m->vmid = INVALID_VMID; p2m->max_mapped_gfn = _gfn(0); - p2m->lowest_mapped_gfn = _gfn(ULONG_MAX); + p2m->lowest_mapped_gfn = INVALID_GFN; p2m->default_access = p2m_access_rwx; p2m->mem_access_enabled = false; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287840.1568279 (Exim 4.92) (envelope-from ) id 1wEwFF-0004yt-5D; Mon, 20 Apr 2026 21:33:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287840.1568279; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lEnYNFwXbNo+tWP6FwCDEEuxsCurDgN3tGFmRfRiibJctrsKVi/ApggoZMHH28UJ7OOW8YskOcvdt4yMC89e0h66TBwNHGPy2J01sI6IwVCdAR6dG/+2V6FVMKOsUDAlqteTXyqZJo2QY6oOw2LgQ43c45syHXoNqP5Ytuooj6dYIq5ihRawb1f9sCFuxOEYpRDon8DghKPkBTUh8K6MWcsUDa0Yq9hPx0B8uB6vUh0TjqvZzyWVX0e9JKEqYiIylLq1CcZIpaLQyMsfK7gf4Nc08auuw/xy+O7c/lpq2evr3UguWPmQzC8Y3HFqpHvmJKx0wOYW446COR1VEVTFRwEtEFDqASmhm/O2dp2CIcaoi+8CCRlz1A8hhk17hEDm0c+Vj8ykgkMbjvhW8R8jvpXcg/DG2JhOi8K8KnKYANIGqnPSB6jkipXngT1Zbroo X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:16.9783 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f277f4c-68c8-4c54-ffdd-08de9f246f97 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-DS2PEPF00003446.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR08MB10871 X-purgate-ID: tlsNG-d25034/1776720803-6D56FCF5-715972C7/0/0 X-purgate-type: clean X-purgate-size: 1653 This commit adds the altp2m_set_vcpu_idx function for both x86 and ARM. Since the altp2m VCPU index is stored differently depending on which architecture is used, the altp2m_set_vcpu_idx function makes it possible to set this value in an architecture independent way for common code routines. This is commit 3/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/include/asm/altp2m.h | 5 +++++ xen/arch/x86/include/asm/altp2m.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index bc695018e62c..f001e022a213 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -29,6 +29,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return v->arch.ap2m_idx; } +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + v->arch.ap2m_idx = idx; +} + #else /* CONFIG_ALTP2M */ static inline bool altp2m_supported(void) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index a1b078783b3e..b3d348386a00 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -60,6 +60,11 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) return vcpu_altp2m(v).p2midx; } +static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + vcpu_altp2m(v).p2midx = idx; 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2GKS7huUjzjhqkDR3rg4P6NQTDEiD+t2h7OWKwFuOAU=; b=1VQqidNwjqYSxrjHGICCjdD8Ar4gKWypkx+I7zfg4upTrw1f19yefVmMw7+Y4jEe06eMfPbHcLUCQH5u9WbStl4H0b7m1P+YDo9wzwZANtpVyqtlKularEl/xHP6+47VfDkz37h6MBadpRhIcZATxsM/royIwX8Nlzqfc62tXJA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [RFC PATCH v6 27/43] arm/altp2m: Add support for altp2m_{get,set}_altp2m Date: Mon, 20 Apr 2026 17:31:50 -0400 Message-ID: <20260420213206.208750-28-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C5:EE_|PH7PR08MB8179:EE_|SJ5PEPF000001CA:EE_|CYXPR08MB9321:EE_ X-MS-Office365-Filtering-Correlation-Id: 7c9bd3d8-bb54-4dbc-7c83-08de9f247100 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704161411799003|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +U5MP/qAvqabj9vaHrSAxddta1q6t9drd6hhsUt1Q7uy66BoCbmsf9AvewP1gB1hWNOfnJE3be3yipIYHdnnqDlPE+8BhXI7nlfufjSGBxnV+JoI1eLwrvzu2li+hYJ3VvekOxiG09zQZNELcj/d5Icbl7JxlFBGGZ2OQ/WeexLuTuM+gwEz2lriap498VWG4bZoA4KOpxxpzIl/V2URabzvgGnuThpKGZMpyyQJYQmr7Dkxhm3Ijyp2mPMaOc9rKSHhnPYPT5Bll77eAD4mEwxoQU4WDEmJ1HdhmJodUen1/LBumn3mQx4vw5EoRnFjsVCC95LyQgaxZS9bK1SO7ZHvAY+8nNJL2/fP39vzDkOx5ZGWKIarOtoDyzlWkQDGfszSBV9VwWgNAa9500vqVtiorhUI8z0sRuljjXF2PYvVdhBeDmGvwObD2cSa3Ef6 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:19.4172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7c9bd3d8-bb54-4dbc-7c83-08de9f247100 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR08MB9321 X-purgate-ID: tlsNG-ef75cf/1776720805-2BF7EC48-CD86CD37/0/0 X-purgate-type: clean X-purgate-size: 1778 This commit adds support for altp2m_get_altp2m and altp2m_set_altp2m on ARM. The x86-specific VCPU accesses have been replaced with the architecture independent functions altp2m_vcpu_idx and altp2m_set_vcpu_idx. This is commit 4/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/include/xen/altp2m.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 58e74be6deb0..f5a4d0e60562 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,7 @@ #include +#include #include #define INVALID_ALTP2M 0xffff @@ -31,11 +32,10 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } -#ifdef CONFIG_X86 /* get current alternate p2m table */ static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) { - unsigned int index = vcpu_altp2m(v).p2midx; + unsigned int index = altp2m_vcpu_idx(v); if ( index == INVALID_ALTP2M ) return NULL; @@ -52,19 +52,18 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) BUG_ON(idx >= v->domain->nr_altp2m); - if ( idx == vcpu_altp2m(v).p2midx ) + if ( idx == altp2m_vcpu_idx(v) ) return false; orig = altp2m_get_altp2m(v); BUG_ON(!orig); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=s+lzv+re9KLW9t3mTXnO2Av9Vu/LGRGNe05U4kI1kS4=; b=i7wJwiTasTdQ3xK977NNQ1qNksIN540kd9nhBODppVL1Un/OsIuxorf0ZKOCtCuWFL+srud1v5LEs9KSVlW1Bzxv19tS9q3wcis59SqrtwDYzilgxNqNy+gmuU8PsNJPMGmeqTj4iBd+ZDsrvtTu3A/mWG1QEKZm6M/eK2UHomQ= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [RFC PATCH v6 30/43] arm/altp2m: Add altp2m view validity/visibility indicator Date: Mon, 20 Apr 2026 17:31:53 -0400 Message-ID: <20260420213206.208750-31-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C9:EE_|BN8PR08MB6290:EE_|SJ5PEPF000001CF:EE_|LV2PR08MB10982:EE_ X-MS-Office365-Filtering-Correlation-Id: 36464852-9bae-492f-0b58-08de9f24728f X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 85Hp4dXszp5nQQK7ICLbcOKUzA6ZnOWHvI0AaqKQiukGoyt0M462px05vjr+frD69c7FsbHJ9NRN6Q/DNhkuFNdpJuQ7myu0anbMZjOQh4iPj8MpUbkbTwJsPxYdt/eJ9q6PzA77WG8sI1zWPwsk6CAJSjP5b59j5mPyS/T9z7IZ7p6RKa81sxlTR6kiVZ1BAAYarI029gnP+wHuzqPFlVSCP5Tq1o9WiW1YxhKIpkPVwmF3r+malwzDRPI1kl2n0rVj1V7VifU/WzmQM4I7zJngrt7gSXDCMKgDqPGZttF+FTraZTwG3UUHmJyz9rgcOlcf9fSDbdBIMAOTu6Aq9GrqZUL6F7U66FBfSsMLDXzxnZeCXllDX2s4qIFXT+BzUXH2Es1e/oEPJvXZYRRsxcixlGF+rxkCyPwQ5il2PukQiku6Igz88thk4kxygLVI X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:22.0113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36464852-9bae-492f-0b58-08de9f24728f X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ5PEPF000001CF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR08MB10982 X-purgate-ID: tlsNG-33051d/1776720808-A197D938-0C4ABDD8/0/0 X-purgate-type: clean X-purgate-size: 5462 This commit adds the altp2m_view_state enum, which indicates whether an altp2m view is invalid, visible, or invisible. The altp2m_state array is comprised of altp2m_view_state values, where each entry corresponds to the altp2m view with the same entry. This is analogous to the altp2m_eptp and altp2m_visible_eptp arrays on x86. This addition is necessary to tell whether an altp2m is valid, in addition to whether it is visible. Since all altp2m views are allocated up-front during p2m initialization, there must be an additional mechanism to determine whether an altp2m view is valid. Since the implementation of HVMOP_altp2m_set_visibility also needs an additional mechanism to determine whether a view is visible, it makes sense to combine altp2m view validity and visibility into a single mechanism. Therefore, the altp2m_state array is used to track both view validitity and visibility. This is commit 1/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. In the v4/v5 patch series, view validity was determined by simply checking if the altp2m p2m_domain pointer is NULL. This isn't possible in the v6 patch series, since altp2m views are allocated up-front during altp2m_init. Since the altp2m_view_state enum definition has to be available in asm/domain.h, this commit removes the sched.h dependency from altp2m.h. Unfortunately, this means that it's not possible to have static inline functions in altp2m.h which need a complete definition of arch_domain and arch_vcpu. If there would be a better place to put the altp2m_view_state definition, feedback would be appreciated. --- xen/arch/arm/altp2m.c | 13 +++++++++++++ xen/arch/arm/include/asm/altp2m.h | 23 +++++++++++++---------- xen/arch/arm/include/asm/domain.h | 4 ++++ xen/arch/arm/mmu/p2m.c | 14 +++++++++++++- 4 files changed, 43 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 339f82835caf..e741648ff5a1 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -5,6 +5,8 @@ * Copyright (c) 2016 Sergej Proskurin */ +#include + #include /* Check to see if vcpu should be switched to a different p2m. */ @@ -14,6 +16,17 @@ void altp2m_check(struct vcpu *v, uint16_t idx) BUG(); } +/* Alternate p2m VCPU */ +uint16_t altp2m_vcpu_idx(const struct vcpu *v) +{ + return v->arch.ap2m_idx; +} + +void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) +{ + v->arch.ap2m_idx = idx; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index f001e022a213..05beb7f698a7 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -9,7 +9,10 @@ #ifndef __ASM_ARM_ALTP2M_H #define __ASM_ARM_ALTP2M_H -#include +#include + +struct domain; +struct vcpu; #ifdef CONFIG_ALTP2M @@ -24,15 +27,15 @@ static inline bool altp2m_supported(void) #define altp2m_unlock(d) spin_unlock(&(d)->arch.altp2m_lock) /* Alternate p2m VCPU */ -static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) -{ - return v->arch.ap2m_idx; -} - -static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) -{ - v->arch.ap2m_idx = idx; -} +uint16_t altp2m_vcpu_idx(const struct vcpu *v); +void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx); + +/* The current state of an altp2m view */ +enum altp2m_view_state { + ALTP2M_INVALID, + ALTP2M_VISIBLE, + ALTP2M_INVISIBLE, +}; #else /* CONFIG_ALTP2M */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 4d497a21b648..28533b08db1f 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -135,6 +136,9 @@ struct arch_domain * concurrently. */ spinlock_t altp2m_lock; + + /* Validity/visibility of altp2m views */ + enum altp2m_view_state *altp2m_state; #endif } __cacheline_aligned; diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 04d17e787259..7c23995f8074 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1494,6 +1494,8 @@ int p2m_teardown(struct domain *d) d->altp2m_active = false; + FREE_XENHEAP_PAGE(d->arch.altp2m_state); + for ( i = 0; i < d->nr_altp2m; i++ ) { rc = p2m_teardown_one(d->altp2m_p2m[i]); @@ -1617,7 +1619,7 @@ struct p2m_domain *p2m_init_one(struct domain *d) static int p2m_init_altp2m(struct domain *d) { #ifdef CONFIG_ALTP2M - int rc; + int rc, i; rc = altp2m_init(d); if ( rc ) @@ -1626,6 +1628,16 @@ static int p2m_init_altp2m(struct domain *d) return rc; } + if ( (d->arch.altp2m_state = alloc_xenheap_page()) == NULL ) + { + return -ENOMEM; + } + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + d->arch.altp2m_state[i] = ALTP2M_INVALID; + } + d->altp2m_active = false; #endif -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287873.1568313 (Exim 4.92) (envelope-from ) id 1wEwFO-0006rk-Nt; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dO2g5M6zhX8U6aCIPU2TKZdw3p3JLXYuNsZrN/I5FhBKMXMpl8Id3kHB0FGKbKf61cECLYBrKJRyxWLS8eEzCEWm3vb27uDl7Vn2xOVYYcFeFCDrBpMsmEGl+G5do/l3+bY8/pbr8dXbpxUdIDsyXlCjQawULtfI7Bd+7N4JAWyr7np9fZnUrJkNZC9VCPPx3U1PS578Awzn6sh4u311ImRSReiojktUCrxM70m8lgeja3dr3WOUeBKhG5bSYTKnlmXUSh277dm1LFziWxrVhhDIa/OnezjgVQdp7ZlCWq+hFkhU291sJ1gWnKblqb+YK4o1n2wR2Jt54ki7C6Gi+JnKz93wkGsDvdiD4Dm/j14hldCB1Cno5O5EIwPOYYhc6Vqgyq4JlJQF9wiOMnYeq3gvRfqwDl1HCaP0guNFJk0ZNni0O6IiBe7GTMyZ0HFq X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:26.8045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 441271fa-6c5d-4e9e-a055-08de9f247586 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN1PEPF00004689.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR08MB10695 X-purgate-ID: tlsNG-bad1c0/1776720812-91969A53-69D0BBE6/0/0 X-purgate-type: clean X-purgate-size: 3182 This commit adds support for the altp2m_vcpu_initialise and altp2m_vcpu_destroy functions on ARM. The x86-specific function calls, altp2m_vcpu_disable_ve and altp2m_vcpu_update_p2m, are gated with #ifdef CONFIG_X86. This is commit 2/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. The equivalent to this patch in the v4/v5 was originally part of the patch named "arm/altp2m: Add HVMOP_altp2m_set_domain_state". In that patch, the check that the VCPU passed to altp2m_vcpu_initialise isn't the current CPU was removed. This was because ARM only implements the external altp2m mode, meaning the current VCPU could never be a VCPU of the guest for which altp2m is being initialized for. Therefore, skipping this check was a slight optimization. I've removed that here because altp2m_vcpu_initialise is only called during an HVMOP, and skipping this check on ARM (especially when x86 also implements the external altp2m mode) causes more confusion than the slight optimization is worth in my view. --- xen/common/altp2m.c | 14 ++++++++++---- xen/include/xen/altp2m.h | 2 -- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index e699b64678d8..7b80426c7798 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -11,6 +11,7 @@ #include #if defined(CONFIG_X86) && defined(CONFIG_HVM) +#include #include #endif @@ -59,7 +60,6 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } -#ifdef CONFIG_X86 void altp2m_vcpu_initialise(struct vcpu *v) { if ( !v->domain->nr_altp2m ) @@ -68,10 +68,12 @@ void altp2m_vcpu_initialise(struct vcpu *v) if ( v != current ) vcpu_pause(v); - vcpu_altp2m(v).p2midx = 0; + altp2m_set_vcpu_idx(v, 0); atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif if ( v != current ) vcpu_unpause(v); @@ -90,15 +92,19 @@ void altp2m_vcpu_destroy(struct vcpu *v) if ( (p2m = altp2m_get_altp2m(v)) ) atomic_dec(&p2m->active_vcpus); +#ifdef CONFIG_X86 altp2m_vcpu_disable_ve(v); +#endif - vcpu_altp2m(v).p2midx = INVALID_ALTP2M; + altp2m_set_vcpu_idx(v, INVALID_ALTP2M); + +#ifdef CONFIG_X86 altp2m_vcpu_update_p2m(v); +#endif if ( v != current ) vcpu_unpause(v); } -#endif /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 7defe6126563..37c875a52327 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,11 +24,9 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); -#ifdef CONFIG_X86 /* Alternate p2m VCPU */ void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); -#endif #ifdef CONFIG_ALTP2M -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287876.1568320 (Exim 4.92) (envelope-from ) id 1wEwFQ-00073y-5s; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nhp6YUWy2TKi+AEGF4P4Ifj6TEP8P7UBokm6jK6L/9bSEdkYBHICgJnINSVcJnEf8macmbjVPsv8vY4wC5vDcSA0IDYFhNDSBlvuJQXSnT/hCr4Dj16qy3XS9Qfib8k7HLXM+Utb7eirT5VbYbodyDyogWAA7F83ob7FCEBReLqNIF1nRVbV0cARDSBK3yZbYO1pvfRkxVjX5N6MOmtVO7wn+diLI173+INgMI1ltB7NMq7OGAtK+Vvt9+RAMzNiScgK+IN8ui8LUWQOWVZCUMurVjUF5bYoh0pYTB66zrEo1+GHd7uJ+884qAMdm6VB9OaiqDplcgbsjWCXjpY9Wmg0Tdt7tY3AFqbZpkC4H1IxelKBTL7Rb8zmSbQSRHxVgN4c7N+UpbqcPei4t1oV9G6d8V+sbqH3C6ZMNpjjgMZ20JM1IcTGCWKSCXonY2/L X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:27.1875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc4cf3b0-e184-4da0-e70b-08de9f2475b9 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN1PEPF00004687.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB9617 X-purgate-ID: tlsNG-ef75cf/1776720813-16A61C48-57281748/0/0 X-purgate-type: clean X-purgate-size: 2493 This commit splits the altp2m_set_view_visibility into two functions, where the altp2m_set_view_visibility_locked variant has the preconditions that the altp2m lock is held. This makes it possible to change a view's visibility in an architecture independent way in code that already holds the altp2m lock (namely, altp2m_flush). This is commit 3/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 4 ++++ xen/arch/x86/mm/altp2m.c | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 56ae19b24b42..99c4cfa5a68b 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -106,6 +106,10 @@ int altp2m_change_gfn(struct domain *d, unsigned int idx, gfn_t old_gfn, int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, uint8_t visible); +/* Set a specific p2m view visibility (with lock already held) */ +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + /* * Looks up altp2m entry. If the entry is not found it looks up the entry in * hostp2m. diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 0542e3ef9196..8672b8c061d3 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -685,9 +685,19 @@ int p2m_get_suppress_ve(struct domain *d, gfn_t gfn, bool *suppress_ve, int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, uint8_t visible) { - int rc = 0; + int rc; altp2m_lock(d); + rc = altp2m_set_view_visibility_locked(d, altp2m_idx, visible); + altp2m_unlock(d); + + return rc; +} + +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) +{ + int rc = 0; if ( !altp2m_is_eptp_valid(d, altp2m_idx) ) rc = -EINVAL; @@ -698,8 +708,6 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, d->arch.altp2m_visible_eptp[array_index_nospec(altp2m_idx, MAX_EPTP)] = mfn_x(INVALID_MFN); - altp2m_unlock(d); - return rc; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287892.1568326 (Exim 4.92) (envelope-from ) id 1wEwFR-0007TJ-Uq; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /jAHSWtmgzWwbxa79b/cFx4AN141F195DYsXHOt5Jx71bEA2LSytGJes56RkjaqVe7Pko6Y1uJk6pYZDlmbxtpprU8vufGk8/tDsee7m+ItX6k9NuE3O5d/HAPb2yGBtaikWaiGjRDFyKeWoLsSYHadkmSTs3tNo5lRsXH9qJt8jySwWk7w4MEb513yaOT2Of1SntUETimsWjJvbpWc3amuhVCmSNjFcVWvLkG5OZPlFiyhwdkI+FSMeWYhlujyxiz44snv9MdOq9mHTQWsvisTDzlrm3YKmBhmjuBUwBgQzeliWhw14q3w4qgoIcimoqIf2X0aDYjyR5zHXsYZKGq0UZqENZjRUv5QvUrXfMr4l7PKTC3BAB7KKjBz+PhhHE0VsMk2Q9cT8p7kISz9jkrbFzIDRu2gvcXRGeKwGYCroRSRedkgdsTREgLJBEkse X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:30.3131 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15c18219-52ba-4382-286c-08de9f24778d X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF00000141.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY3PR08MB7169 X-purgate-ID: tlsNG-ebf023/1776720816-31C4F3FF-D5594AB2/0/0 X-purgate-type: clean X-purgate-size: 2531 This commit adds the altp2m_set_view_visibility and altp2m_set_view_visibility_locked functions on ARM. This makes it possible to set the altp2m view visibility in common altp2m routines (namely, altp2m_flush). This is commit 4/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/arm/altp2m.c | 30 ++++++++++++++++++++++++++++++ xen/arch/arm/include/asm/altp2m.h | 8 ++++++++ 2 files changed, 38 insertions(+) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index 0e19e197e826..aa48c17e11a3 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -37,6 +37,36 @@ bool altp2m_view_is_visible(struct domain *d, unsigned int idx) return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] == ALTP2M_VISIBLE; } +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) +{ + int rc; + + altp2m_lock(d); + rc = altp2m_set_view_visibility_locked(d, altp2m_idx, visible); + altp2m_unlock(d); + + return rc; +} + +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, + uint8_t visible) +{ + int rc = 0; + + if ( altp2m_idx >= d->nr_altp2m || !altp2m_view_is_valid(d, altp2m_idx) ) + rc = -EINVAL; + else if ( visible ) + d->arch.altp2m_state[array_index_nospec(altp2m_idx, d->nr_altp2m)] = + ALTP2M_VISIBLE; + else + d->arch.altp2m_state[array_index_nospec(altp2m_idx, d->nr_altp2m)] = + ALTP2M_INVISIBLE; + + return rc; +} + + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index fbe66ad5536d..f8d0dd799a4a 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -40,6 +40,14 @@ enum altp2m_view_state { ALTP2M_INVISIBLE, }; +/* Set a specific p2m view visibility */ +int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + +/* Set a specific p2m view visibility (with lock already held) */ +int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, + uint8_t visible); + #else /* CONFIG_ALTP2M */ static inline bool altp2m_supported(void) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287894.1568334 (Exim 4.92) (envelope-from ) id 1wEwFT-0007kz-Rp; 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With altp2m_set_view_visibility being implemented, no further changes beyond updating the #ifdef CONFIG_X86 gates are necessary. This is commit 5/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/common/altp2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 7b80426c7798..c234bb3774f4 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -477,6 +477,7 @@ int do_altp2m_op( rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; } +#endif /* CONFIG_X86 */ case HVMOP_altp2m_set_visibility: { @@ -490,7 +491,6 @@ int do_altp2m_op( rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); break; } -#endif /* CONFIG_X86 */ default: #ifdef CONFIG_X86 -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287896.1568343 (Exim 4.92) (envelope-from ) id 1wEwFX-0008LY-HF; Mon, 20 Apr 2026 21:33:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287896.1568343; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OvvuozzQHNqqjIJeWcdp0QnIe9/kqM1WJCwMRXQseyFUahlOGYV7uyTrRpDuoPb8pxUU8vDniAi6wJtA2rqY0qYuM9cKMwZHBT7y83PShyxYc/QylGSn7coOaKzzLAKU5IpkaOqvrPaLNXX48GB8DP+WXFN8Uq9arrLAnVN8BwelimuTD3rkQozv2Y/MhYdpbrHDRV3w7zcIklYC+EnMC9KNHRteIk0y4U/vgu98LBMQ7OmSQrWnOW7JWju1VdMWVbfJESZbOiVyWx2/puuv9dJXO6/qzE03OhQsH+IV+c8tAi4r0x/JBkD8VGlvkTBax53FrKj7CyFqv5HCuLu2insFkOjnZz0Bknx/hf0+YH1aPX2gJbSw14Oir1InySugR25NANwTn4Dm2CaIsL8RqahSZJuwN3f0EtTF3j8iVivtkzraD4wHQ3DZyr3mBUJm X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:23.9523 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d20c053e-eac1-4249-ad6b-08de9f2473bb X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-CH2PEPF00000142.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA6PR08MB10353 X-purgate-ID: tlsNG-720697/1776720818-8057B161-3C65FB2F/0/0 X-purgate-type: clean X-purgate-size: 3486 This commit adds arch independent helper functions to determine whether a view is valid or visible. This makes it possible to determine whether a view is valid and/or visible in common altp2m routines (namely, altp2m_init_by_id). This is commit 2/5 of the altp2m view validity/visibility phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. These functions could be used to replace the equivalent calls in x86 code if that would be preferred. For now, they are only used in common code. The altp2m_view_is_valid function also has overlap with the altp2m_is_ept_valid function, but that function has an additional ASSERT and check that idx < d->nr_altp2m, so I wasn't sure if that function should be repurposed for this. If renaming that function instead of introducing a new function on x86 would be preferred, then I can do that. Additionally, these functions don't have bounds checks since the functions are intended to replace code which don't have bounds checks currently. Bounds checks could be added here if that would be preferred. --- xen/arch/arm/altp2m.c | 10 ++++++++++ xen/arch/arm/include/asm/altp2m.h | 3 +++ xen/arch/x86/include/asm/altp2m.h | 10 ++++++++++ 3 files changed, 23 insertions(+) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index e741648ff5a1..0e19e197e826 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -27,6 +27,16 @@ void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) v->arch.ap2m_idx = idx; } +bool altp2m_view_is_valid(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] != ALTP2M_INVALID; +} + +bool altp2m_view_is_visible(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] == ALTP2M_VISIBLE; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 05beb7f698a7..fbe66ad5536d 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -30,6 +30,9 @@ static inline bool altp2m_supported(void) uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx); +bool altp2m_view_is_valid(struct domain *d, unsigned int idx); +bool altp2m_view_is_visible(struct domain *d, unsigned int idx); + /* The current state of an altp2m view */ enum altp2m_view_state { ALTP2M_INVALID, diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 43dd5d2acd9c..56ae19b24b42 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -65,6 +65,16 @@ static inline void altp2m_set_vcpu_idx(struct vcpu *v, unsigned int idx) vcpu_altp2m(v).p2midx = idx; } +static inline bool altp2m_view_is_valid(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN); +} + +static inline bool altp2m_view_is_visible(struct domain *d, unsigned int idx) +{ + return d->arch.altp2m_visible_eptp[array_index_nospec(idx, MAX_EPTP)] != mfn_x(INVALID_MFN); +} + /* * Alternate p2m: shadow p2m tables used for alternate memory views */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287901.1568348 (Exim 4.92) (envelope-from ) id 1wEwFZ-0000Kk-8N; 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This makes it possible to activate altp2m views in common altp2m routines (namely, altp2m_init_by_id). This is commit 2/2 of the altp2m_activate_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. While the ARM version of this function is very similar to the x86 version of this function, I still think it makes sense to have this implemented on both architectures instead of using a common implementation. A significant portion of the function would need to be #ifdef CONFIG_X86/#else CONFIG_ARM gated (like p2m->min_mapped_gfn vs. p2m->lowest_mapped_gfn on ARM, for example). This would become even more of an issue if other architectures implement altp2m in the future, so I think it's best to keep these architecture specific. --- xen/arch/arm/altp2m.c | 26 +++++++++++++++++++++++++- xen/arch/arm/include/asm/altp2m.h | 4 ++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index aa48c17e11a3..aa56b3ca79b5 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -37,6 +37,31 @@ bool altp2m_view_is_visible(struct domain *d, unsigned int idx) return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] == ALTP2M_VISIBLE; } +int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access) +{ + struct p2m_domain *hostp2m, *p2m; + + ASSERT(idx < d->nr_altp2m); + + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + hostp2m = p2m_get_hostp2m(d); + + p2m_write_lock(p2m); + + p2m->default_access = hvmmem_default_access; + p2m->domain = hostp2m->domain; + + p2m->lowest_mapped_gfn = INVALID_GFN; + p2m->max_mapped_gfn = _gfn(0); + + d->arch.altp2m_state[idx] = ALTP2M_VISIBLE; + + p2m_write_unlock(p2m); + + return 0; +} + int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, uint8_t visible) { @@ -66,7 +91,6 @@ int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, return rc; } - /* * Local variables: * mode: C diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index f8d0dd799a4a..192240f48c33 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -48,6 +48,10 @@ int altp2m_set_view_visibility(struct domain *d, unsigned int altp2m_idx, int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, uint8_t visible); +/* Activate an altp2m view */ +int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access); + #else /* CONFIG_ALTP2M */ static inline bool altp2m_supported(void) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287906.1568359 (Exim 4.92) (envelope-from ) id 1wEwFd-0000uc-Ea; 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This makes it possible to call the function in the common HVMOP_altp2m_set_domain state implementation. This is commit 2/2 of the altp2m_init_by_id phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/common/altp2m.c | 5 +---- xen/include/xen/altp2m.h | 2 -- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 9f5f98e1e8a5..929449b1b03c 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -106,7 +106,6 @@ void altp2m_vcpu_destroy(struct vcpu *v) vcpu_unpause(v); } -#ifdef CONFIG_X86 int altp2m_init_by_id(struct domain *d, unsigned int idx) { int rc = -EINVAL; @@ -117,14 +116,12 @@ int altp2m_init_by_id(struct domain *d, unsigned int idx) altp2m_lock(d); - if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == - mfn_x(INVALID_MFN) ) + if ( !altp2m_view_is_valid(d, idx) ) rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); altp2m_unlock(d); return rc; } -#endif /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index cd96c3b4792a..8fc16346d95b 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -71,10 +71,8 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); 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This makes it possible to call in the common HVMOP_altp2m_set_domain_state command implementation. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the altp2m_init_by_id phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 3 --- xen/arch/x86/mm/altp2m.c | 18 ------------------ xen/common/altp2m.c | 20 ++++++++++++++++++++ xen/include/xen/altp2m.h | 5 +++++ 4 files changed, 25 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 203dba44e2bf..e7239326c71d 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -85,9 +85,6 @@ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); /* Flush all the alternate p2m's for a domain */ void altp2m_flush(struct domain *d); -/* Make a specific alternate p2m valid */ -int altp2m_init_by_id(struct domain *d, unsigned int idx); - /* Find an available alternate p2m and make it valid */ int altp2m_init_next_available(struct domain *d, uint16_t *idx, xenmem_access_t hvmmem_default_access); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 40c6ea72a621..edbaf54c3761 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -315,24 +315,6 @@ int altp2m_activate_altp2m(struct domain *d, unsigned int idx, return rc; } -int altp2m_init_by_id(struct domain *d, unsigned int idx) -{ - int rc = -EINVAL; - struct p2m_domain *hostp2m = p2m_get_hostp2m(d); - - if ( idx >= d->nr_altp2m ) - return rc; - - altp2m_lock(d); - - if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == - mfn_x(INVALID_MFN) ) - rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); - - altp2m_unlock(d); - return rc; -} - int altp2m_init_next_available(struct domain *d, uint16_t *idx, xenmem_access_t hvmmem_default_access) { diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index c234bb3774f4..9f5f98e1e8a5 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -106,6 +106,26 @@ void altp2m_vcpu_destroy(struct vcpu *v) vcpu_unpause(v); } +#ifdef CONFIG_X86 +int altp2m_init_by_id(struct domain *d, unsigned int idx) +{ + int rc = -EINVAL; + struct p2m_domain *hostp2m = p2m_get_hostp2m(d); + + if ( idx >= d->nr_altp2m ) + return rc; + + altp2m_lock(d); + + if ( d->arch.altp2m_eptp[array_index_nospec(idx, MAX_EPTP)] == + mfn_x(INVALID_MFN) ) + rc = altp2m_activate_altp2m(d, idx, hostp2m->default_access); + + altp2m_unlock(d); + return rc; +} +#endif + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 37c875a52327..cd96c3b4792a 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -71,6 +71,11 @@ static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); +#ifdef CONFIG_X86 +/* Make a specific alternate p2m valid */ +int altp2m_init_by_id(struct domain *d, unsigned int idx); +#endif + #else /* CONFIG_ALTP2M */ static inline bool altp2m_active(const struct domain *d) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:33:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:33:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287922.1568374 (Exim 4.92) (envelope-from ) id 1wEwFg-0001jj-UZ; Mon, 20 Apr 2026 21:33:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287922.1568374; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8+NdLyPprCdCj3SMjh/5XbLTBqrjD0tnuhkeJ9TusAAYfeX4FprfAr15p3Z/rcVDIZRoaMC0jplzpB4utpkin/joIH3miEW0Aaa8mA4AEj7w8g5Ii23i5KrMk4qETp4P07ws2fXJjJVTn4Q/1AN8u7whp4JpFBDqrJR7XiE37syySqMdHvj8aBojrSKQztzH6i4gcum41r8S7QYVc5qYY8g8PlDMyAS5ILogK3mAZMiTGEVDWc7AE8BariKgN2pm58QByh4MGlBrHj/qfYEhxqbDIHCuqnXgRNLEX9MCs1ZaLZNy8hwbD3sJ3/b2m94bHOqM6W+HU/jni1fNuE+yso2ZCVI2qKjYC01+u7PjOsnSyWCfRv3TUlGrcFNp21k3IofnDpH6S/jI7KiCPR0I29BYaql4/T3iIQI0eyBPmYsYDOl9+mw7uv0YH07k+2Zd X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:40.3694 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2401a26c-74af-4c81-3b81-08de9f247d65 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-MWH0EPF000A6735.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY3PR08MB7201 X-purgate-ID: tlsNG-720697/1776720825-B2969161-FA4B2E62/0/0 X-purgate-type: clean X-purgate-size: 2484 This commit makes the altp2m_flush compatible with ARM by replacing the x86-specific set view visibility code with the architecture independent altp2m_set_view_visibility locked. This is commit 2/2 of the altp2m_flush phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. There is a small amount of additional overhead introduced on x86 by replacing these direct array sets with calls to altp2m_set_view_visibility_locked. That function also calls altp2m_is_eptp_valid, which performs additional checks, and also bounds the array sets with array_index_nospec, which isn't technically necessary here since we can be certain that the array set will be less than nr_altp2m. This could be resolved by introducing another altp2m_set_view_visibility variant (ex. altp2m_set_view_visibility_unchecked?) which would replace usages of altp2m_set_view_visibility_locked, but I'm not sure if the overhead is enough to matter here. --- xen/common/altp2m.c | 5 +---- xen/include/xen/altp2m.h | 2 -- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 0dd3ecf226fd..d980ebed08ab 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -123,7 +123,6 @@ int altp2m_init_by_id(struct domain *d, unsigned int idx) return rc; } -#ifdef CONFIG_X86 void altp2m_flush(struct domain *d) { unsigned int i; @@ -133,13 +132,11 @@ void altp2m_flush(struct domain *d) for ( i = 0; i < d->nr_altp2m; i++ ) { altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); - d->arch.altp2m_eptp[i] = mfn_x(INVALID_MFN); - d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); + altp2m_set_view_visibility_locked(d, i, 0); } altp2m_unlock(d); } -#endif /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index fa2c11f5432e..5222c24ef418 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -74,10 +74,8 @@ int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); /* Make a specific alternate p2m valid */ int altp2m_init_by_id(struct domain *d, unsigned int idx); -#ifdef CONFIG_X86 /* Flush all the alternate p2m's for a domain */ void altp2m_flush(struct domain *d); -#endif #else /* CONFIG_ALTP2M */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:34:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:34:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287924.1568381 (Exim 4.92) (envelope-from ) id 1wEwFk-0002Ou-6Z; Mon, 20 Apr 2026 21:34:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287924.1568381; Mon, 20 Apr 2026 21:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwFi-0002GI-Gd; Mon, 20 Apr 2026 21:33:58 +0000 Received: by outflank-mailman (input) for mailman id 1287924; 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+XnwEw2LkEZsqrQt7TCPVOkF1Np7ZHiylY2Nnd/lA20=; b=qy4OxXo/yi1hnlY7uxDjofXtPsTmYct5+syZRTbfhkQX0DKC3b+fiih7p72pj5579ZSgRDQ6xIpahCPm5AejfOjQ99oMDqGlcDcS7OEcKtA1k0DI4Sz3QOgzXNyPB4Mo32C/e9wTyHEXgbsS15OGhNeV3fMLpmDAsqrbyLs+Lvw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 39/43] x86/altp2m: Add altp2m_reset_altp2m declaration to arch header Date: Mon, 20 Apr 2026 17:32:02 -0400 Message-ID: <20260420213206.208750-40-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C9:EE_|SN4PR0801MB7744:EE_|MWH0EPF000A672E:EE_|CH0PR08MB8613:EE_ X-MS-Office365-Filtering-Correlation-Id: 51c387a7-23ea-462f-bd5f-08de9f247b08 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162011799003|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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This makes it possible to call this function in common altp2m routines. The altp2m_reset_type enum (which is the type of one of the parameters of altp2m_reset) is also moved to the asm/altp2m.h header. This is commit 1/2 of the altp2m_reset_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 8 ++++++++ xen/arch/x86/mm/altp2m.c | 9 ++------- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index e7239326c71d..02b5e1a11220 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -92,6 +92,14 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, /* Make a specific alternate p2m invalid */ int altp2m_destroy_by_id(struct domain *d, unsigned int idx); +/* Reset an altp2m view */ +enum altp2m_reset_type { + ALTP2M_RESET, + ALTP2M_DEACTIVATE +}; +void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type); + /* Activate an altp2m view */ int altp2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_access_t hvmmem_default_access); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index edbaf54c3761..18f8a71f1682 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -228,13 +228,8 @@ bool altp2m_get_or_propagate(struct p2m_domain *ap2m, unsigned long gfn_l, return true; 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This makes it possible to call in the common implementation of HVMOP_set_domain_state. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the altp2m_flush phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 2 -- xen/arch/x86/mm/altp2m.c | 16 ---------------- xen/common/altp2m.c | 18 ++++++++++++++++++ xen/include/xen/altp2m.h | 5 +++++ 4 files changed, 23 insertions(+), 18 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 02b5e1a11220..d11f20f1e790 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -82,8 +82,6 @@ static inline bool altp2m_view_is_visible(struct domain *d, unsigned int idx) /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); -/* Flush all the alternate p2m's for a domain */ -void altp2m_flush(struct domain *d); /* Find an available alternate p2m and make it valid */ int altp2m_init_next_available(struct domain *d, uint16_t *idx, diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 18f8a71f1682..de91d1e67709 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -253,22 +253,6 @@ void altp2m_reset_altp2m(struct domain *d, unsigned int idx, p2m_unlock(p2m); } -void altp2m_flush(struct domain *d) -{ - unsigned int i; - - altp2m_lock(d); - - for ( i = 0; i < d->nr_altp2m; i++ ) - { - altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); - d->arch.altp2m_eptp[i] = mfn_x(INVALID_MFN); - d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); - } - - altp2m_unlock(d); -} - int altp2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_access_t hvmmem_default_access) { diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 929449b1b03c..0dd3ecf226fd 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -123,6 +123,24 @@ int altp2m_init_by_id(struct domain *d, unsigned int idx) return rc; } +#ifdef CONFIG_X86 +void altp2m_flush(struct domain *d) +{ + unsigned int i; + + altp2m_lock(d); + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + altp2m_reset_altp2m(d, i, ALTP2M_DEACTIVATE); + d->arch.altp2m_eptp[i] = mfn_x(INVALID_MFN); + d->arch.altp2m_visible_eptp[i] = mfn_x(INVALID_MFN); + } + + altp2m_unlock(d); +} +#endif + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 8fc16346d95b..fa2c11f5432e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -74,6 +74,11 @@ int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); 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s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QEvCOJ/znG1Y9sl6sTHGiqT4+0IS7dn5KAJvNg29AXA=; b=1pDXNGpv/cLnvLpEprLKBTUImwPkTecH6SIBAjXNbohm+qvYeOvPGI9jkDhgqJBPD76vt8rLvdW45C4hc16JbTc93jrn44VmTF2M/XUmYeQZcSALUChFcrQ4vneGwVQ/t9CzVGHsVo1fKUoyntwtETHdWDQc/GyJvF60wuLvnqw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 213.95.148.172) smtp.mailfrom=elektrobit.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=elektrobit.com; Received-SPF: Pass (protection.outlook.com: domain of elektrobit.com designates 213.95.148.172 as permitted sender) receiver=protection.outlook.com; client-ip=213.95.148.172; helo=denue6es012.ebgroup.elektrobit.com; pr=C From: Rose Spangler To: CC: Rose Spangler , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [RFC PATCH v6 35/43] x86/altp2m: Add altp2m_activate_altp2m declaration to arch header Date: Mon, 20 Apr 2026 17:31:58 -0400 Message-ID: <20260420213206.208750-36-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C9:EE_|PH0PR08MB9934:EE_|SN1PEPF00036F3F:EE_|DM3PR08MB9165:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b1455e2-4cab-46e0-c048-08de9f2479a7 X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|36860700016|1800799024|376014|82310400026|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cUHXrfb6FJbdtPo6vV2U709O36d4sO0Nb8rilLZPPISwhjgHhVvtCA1DHBa8UoiHF+wugP/a8kSwLD7n4pkCrkVrE40m2sq0KzpIfp/WQsXaoIVfPIt0G7iK6E04z1xZL1c5zPPSq8HvomPCM+DvZ2p3hRqodAulItRm65FfML6gEPZDE/7JP5zt8LjA2yswXtW7MFvyoZfWL2kB503tSQ8/AH465QaLf8cfcWeNSL/2d9xY+u2k/80V9sEpY0KNYp6QTCHebaBdwTCCCr67GHdK13N3e0Bj1o9A4ypWibSkY1uawcxgdKIQiiOEQ8qSrzyXat9GpT0qEtyl3aCtXJt8eSinYaxJmN4VKUd29MhYIbkCUP+vEPaTNHbsqwBqNQKoIEbJa0LFfTUckq35V33DOxcDcEESN5s812mn3lLA00L/9uJbb4Yuwl5pd45D X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:33.8382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b1455e2-4cab-46e0-c048-08de9f2479a7 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SN1PEPF00036F3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR08MB9165 X-purgate-ID: tlsNG-c201ff/1776720828-2A969443-796E502A/0/0 X-purgate-type: clean X-purgate-size: 1798 This commit adds a declaration for altp2m_activate_altp2m to the x86 asm/altp2m.h header. This makes it possible to call the function in common altp2m routines (namely, altp2m_init_by_id). This is commit 1/2 of the altp2m_activate_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 4 ++++ xen/arch/x86/mm/altp2m.c | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 99c4cfa5a68b..203dba44e2bf 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -95,6 +95,10 @@ int altp2m_init_next_available(struct domain *d, uint16_t *idx, /* Make a specific alternate p2m invalid */ int altp2m_destroy_by_id(struct domain *d, unsigned int idx); +/* Activate an altp2m view */ +int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access); + /* Switch alternate p2m for entire domain */ int altp2m_switch_domain_altp2m_by_id(struct domain *d, unsigned int idx); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 8672b8c061d3..40c6ea72a621 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -274,8 +274,8 @@ void altp2m_flush(struct domain *d) altp2m_unlock(d); } -static int altp2m_activate_altp2m(struct domain *d, unsigned int idx, - p2m_access_t hvmmem_default_access) +int altp2m_activate_altp2m(struct domain *d, unsigned int idx, + p2m_access_t hvmmem_default_access) { struct p2m_domain *hostp2m, *p2m; int rc; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:34:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:34:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1287941.1568406 (Exim 4.92) (envelope-from ) id 1wEwFq-0003ao-7n; Mon, 20 Apr 2026 21:34:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1287941.1568406; Mon, 20 Apr 2026 21:34:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwFo-0003UW-PZ; Mon, 20 Apr 2026 21:34:04 +0000 Received: by outflank-mailman (input) for mailman id 1287941; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dwZyBiBD99JqkrBkyJmkBFFJ0eo0gfn7CN6N9/KHPdkbz0ffDmbwQQPK6lgbl7q6iAab1BKobnxorc2OZt3hFkWlK14t/jCaH5c57eUnrpI7vwlgPH0giBoamf0ARFkpQa10gRoD3Qy9tyrxpvCJhk2Qc4IeJnVzZldz271BcSmBUSydQ9EzK+JvjMaCx6qZO76oHBmp3daZLRd/mSC2oMlkWDZRBbr/LxcmaKawm6dM1aIhgAPIgtnf3w0aA69nZhpg4GH0Zg21OtvloFEIMH/r8QgnCxfDH+ey3DLHaiUyhAz1UmwtNh/B7eQnfiyCrRseUwPrtedICz7eUGvoYlFYmKDINLg/pvhJLx76iojPhVmR9MvURY5jGFyZUvU+0yIy1TP5QWJ+H7aGfu5rFbXKxuAGbW2mEO7ES9o8NpTYQpDjM8kjsENJ8Bfj3ZyU X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:40.1651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf24d18c-5d95-462b-b2d2-08de9f247d63 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ1PEPF000023D0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR08MB8873 X-purgate-ID: tlsNG-4011c0/1776720829-45B6F8B7-073EC061/0/0 X-purgate-type: clean X-purgate-size: 3083 This commit adds the altp2m_reset_altp2m routine on ARM. This will later be used as part of the altp2m_flush routine. This is commit 2/2 of the altp2m_reset_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. I'm not sure if duplicating the altp2m_reset_type enum is really the best way to handle this. The distinction isn't even relevant on ARM since the logdirty ranges don't need to be freed. However, the function prototype has to be the same in order to call it on both x86 and ARM. Ideally the altp2m_reset_type enum would be part of a header that asm/altp2m.h includes on both architectures. The main xen/altp2m.h header can't fill this role since it includes asm/altp2m.h, so it would be a circular include. Introducing *another* header file to just hold altp2m_reset_type also isn't great, so I chose to just duplicate the enum. Any better ideas here would be appreciated. --- xen/arch/arm/altp2m.c | 20 ++++++++++++++++++++ xen/arch/arm/include/asm/altp2m.h | 8 ++++++++ 2 files changed, 28 insertions(+) diff --git a/xen/arch/arm/altp2m.c b/xen/arch/arm/altp2m.c index aa56b3ca79b5..bf2d9095830f 100644 --- a/xen/arch/arm/altp2m.c +++ b/xen/arch/arm/altp2m.c @@ -7,6 +7,7 @@ #include +#include #include /* Check to see if vcpu should be switched to a different p2m. */ @@ -37,6 +38,25 @@ bool altp2m_view_is_visible(struct domain *d, unsigned int idx) return d->arch.altp2m_state[array_index_nospec(idx, d->nr_altp2m)] == ALTP2M_VISIBLE; } +void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type) +{ + struct p2m_domain *p2m; + + ASSERT(idx < d->nr_altp2m); + p2m = d->altp2m_p2m[array_index_nospec(idx, d->nr_altp2m)]; + + p2m_write_lock(p2m); + + while ( p2m_flush_table(p2m) == -ERESTART ) + continue; /* No preemption support here */ + + p2m->lowest_mapped_gfn = INVALID_GFN; + p2m->max_mapped_gfn = _gfn(0); + + p2m_write_unlock(p2m); +} + int altp2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_access_t hvmmem_default_access) { diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 192240f48c33..14961736a238 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -52,6 +52,14 @@ int altp2m_set_view_visibility_locked(struct domain *d, unsigned int altp2m_idx, int altp2m_activate_altp2m(struct domain *d, unsigned int idx, p2m_access_t hvmmem_default_access); +/* Reset an altp2m view */ +enum altp2m_reset_type { + ALTP2M_RESET, + ALTP2M_DEACTIVATE +}; +void altp2m_reset_altp2m(struct domain *d, unsigned int idx, + enum altp2m_reset_type reset_type); + #else /* CONFIG_ALTP2M */ static inline bool altp2m_supported(void) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:34:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:34:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288048.1568439 (Exim 4.92) (envelope-from ) id 1wEwG6-0006bS-8o; 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This make sit possible to use them in other common routines (namely, altp2m_vcpu_{initialise,destroy}). This commit contains only code movement, and no change in functionality is intended. This is commit 1/4 of the altp2m_{get,set}_altp2m phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 35 ------------------------- xen/arch/x86/include/asm/domain.h | 2 -- xen/common/altp2m.c | 1 - xen/include/xen/altp2m.h | 43 +++++++++++++++++++++++++++++++ 4 files changed, 43 insertions(+), 38 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 13017525a62f..a1b078783b3e 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -64,39 +64,6 @@ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) * Alternate p2m: shadow p2m tables used for alternate memory views */ -/* get current alternate p2m table */ -static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) -{ - unsigned int index = vcpu_altp2m(v).p2midx; - - if ( index == INVALID_ALTP2M ) - return NULL; - - BUG_ON(index >= v->domain->nr_altp2m); - - return v->domain->altp2m_p2m[index]; -} - -/* set current alternate p2m table */ -static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) -{ - struct p2m_domain *orig; - - BUG_ON(idx >= v->domain->nr_altp2m); - - if ( idx == vcpu_altp2m(v).p2midx ) - return false; - - orig = altp2m_get_altp2m(v); - BUG_ON(!orig); - atomic_dec(&orig->active_vcpus); - - vcpu_altp2m(v).p2midx = idx; - atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); - - return true; -} - /* Switch alternate p2m for a single vcpu */ bool altp2m_switch_vcpu_by_id(struct vcpu *v, unsigned int idx); @@ -178,8 +145,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, _altp2m_get_effective_entry(ap2m, gfn, mfn, t, a) /* Only declaration is needed. DCE will optimise it out when linking. */ -struct p2m_domain *altp2m_get_altp2m(struct vcpu *v); -bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx); uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); void altp2m_vcpu_destroy(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index f8038087e612..72460e38f581 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -277,8 +277,6 @@ struct paging_vcpu { #define MAX_NR_ALTP2M MAX_EPTP #define MAX_NESTEDP2M 10 -#define INVALID_ALTP2M 0xffff - struct p2m_domain; struct time_scale { int shift; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 989d8bdcb923..a731ad7cdab8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -5,7 +5,6 @@ #include #include -#include #include diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 238c7a935586..58e74be6deb0 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -8,6 +8,10 @@ #include +#include + +#define INVALID_ALTP2M 0xffff + /* * Common alternate p2m declarations that need to be visible * regardless of CONFIG_ALTP2M @@ -27,6 +31,41 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } +#ifdef CONFIG_X86 +/* get current alternate p2m table */ +static inline struct p2m_domain *altp2m_get_altp2m(struct vcpu *v) +{ + unsigned int index = vcpu_altp2m(v).p2midx; + + if ( index == INVALID_ALTP2M ) + return NULL; + + BUG_ON(index >= v->domain->nr_altp2m); + + return v->domain->altp2m_p2m[index]; +} + +/* set current alternate p2m table */ +static inline bool altp2m_set_altp2m(struct vcpu *v, unsigned int idx) +{ + struct p2m_domain *orig; + + BUG_ON(idx >= v->domain->nr_altp2m); + + if ( idx == vcpu_altp2m(v).p2midx ) + return false; + + orig = altp2m_get_altp2m(v); + BUG_ON(!orig); + atomic_dec(&orig->active_vcpus); + + vcpu_altp2m(v).p2midx = idx; + atomic_inc(&v->domain->altp2m_p2m[idx]->active_vcpus); + + return true; +} +#endif + int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); #else /* CONFIG_ALTP2M */ @@ -41,6 +80,10 @@ static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg) return -EOPNOTSUPP; } +/* Only declaration is needed. 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This makes it possible to activate altp2m on a domain. This is commit 1/1 of the set_domain_state phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. This patch replaces the "arm/p2m: Add HVMOP_altp2m_set_domain_state" patch from the v4/v5 patch series. --- xen/common/altp2m.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index d980ebed08ab..951e56a2aba5 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -254,17 +254,18 @@ int do_altp2m_op( rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; break; -#ifdef CONFIG_X86 case HVMOP_altp2m_set_domain_state: { struct vcpu *v; bool ostate; +#if defined(CONFIG_X86) && defined(CONFIG_HVM) if ( nestedhvm_enabled(d) ) { rc = -EINVAL; break; } +#endif rc = domain_pause_except_self(d); if ( rc ) @@ -295,6 +296,7 @@ int do_altp2m_op( break; } +#ifdef CONFIG_X86 case HVMOP_altp2m_vcpu_enable_notify: { struct vcpu *v; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:36:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:36:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288129.1568457 (Exim 4.92) (envelope-from ) id 1wEwIT-0001Of-8e; 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Similarly to nr_altp2m, this is not an arch-specific value. Moving it to common code allows the common altp2m routines introduced later in this patch series to operate on altp2m_active without needing an altp2m_active member on arch_domain for each architecture supporting altp2m. This is commit 2/8 of the preparation phase. This commit is a refactor, and no change in functionality is intended. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 11 ++++++----- xen/arch/x86/hvm/monitor.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 1 + xen/arch/x86/include/asm/altp2m.h | 11 ----------- xen/arch/x86/include/asm/domain.h | 2 -- xen/arch/x86/mm/altp2m.c | 1 + xen/arch/x86/mm/hap/hap.c | 5 +++-- xen/arch/x86/mm/mem_access.c | 1 + xen/arch/x86/mm/mem_sharing.c | 1 + xen/arch/x86/mm/p2m-ept.c | 1 + xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 1 + xen/common/monitor.c | 1 + xen/include/asm-generic/altp2m.h | 8 -------- xen/include/xen/altp2m.h | 19 +++++++++++++++++++ xen/include/xen/sched.h | 2 ++ 17 files changed, 40 insertions(+), 28 deletions(-) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index f3aae158e9f8..9a9b89a232e6 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -9,6 +9,7 @@ * Keir Fraser */ +#include #include #include #include diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4a81afce02e7..86c12c0d1ef4 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -7,6 +7,7 @@ * Copyright (c) 2008, Citrix Systems, Inc. */ +#include #include #include #include @@ -4612,7 +4613,7 @@ static int do_altp2m_op( if ( (a.cmd != HVMOP_altp2m_get_domain_state) && (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->arch.altp2m_active ) + !d->altp2m_active ) { rc = -EOPNOTSUPP; goto out; @@ -4657,11 +4658,11 @@ static int do_altp2m_op( if ( rc ) break; - ostate = d->arch.altp2m_active; - d->arch.altp2m_active = !!a.u.domain_state.state; + ostate = d->altp2m_active; + d->altp2m_active = !!a.u.domain_state.state; /* If the alternate p2m state has changed, handle appropriately */ - if ( d->arch.altp2m_active != ostate && + if ( d->altp2m_active != ostate && (ostate || !(rc = p2m_init_altp2m_by_id(d, 0))) ) { for_each_vcpu( d, v ) @@ -4676,7 +4677,7 @@ static int do_altp2m_op( p2m_flush_altp2m(d); } else if ( rc ) - d->arch.altp2m_active = false; + d->altp2m_active = false; domain_unpause_except_self(d); break; diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c index d22a2e464460..84c1c2234ca9 100644 --- a/xen/arch/x86/hvm/monitor.c +++ b/xen/arch/x86/hvm/monitor.c @@ -22,6 +22,7 @@ * this program; If not, see . */ +#include #include #include #include diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 269ca5643346..ff895f7f9437 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -4,6 +4,7 @@ * Copyright (c) 2004, Intel Corporation. */ +#include #include #include #include diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index 9c1ac3cc2676..ad5ded833a75 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -28,12 +28,6 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, mfn_x(INVALID_MFN); } -/* Alternate p2m HVM on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - return d->arch.altp2m_active; -} - static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { return vcpu_altp2m(v).p2midx; @@ -64,11 +58,6 @@ static inline bool altp2m_is_eptp_valid(const struct domain *d, return false; } -static inline bool altp2m_active(const struct domain *d) -{ - return false; -} - /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); void altp2m_vcpu_initialise(struct vcpu *v); diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h index 385a6666dafa..0cf0c0d92087 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -368,8 +368,6 @@ struct arch_domain mm_lock_t nested_p2m_lock; #ifdef CONFIG_ALTP2M - /* altp2m: allow multiple copies of host p2m */ - bool altp2m_active; struct p2m_domain **altp2m_p2m; mm_lock_t altp2m_list_lock; uint64_t *altp2m_eptp; diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 0bc9b9ad2f52..08db8f37c1b1 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mm-locks.h" diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 5ccb80bda5d3..3d563b3bc2d1 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -7,6 +7,7 @@ * Parts of this code are Copyright (c) 2007 by XenSource Inc. */ +#include #include #include #include @@ -528,7 +529,7 @@ int hap_enable(struct domain *d, u32 mode) goto out; } - d->arch.altp2m_active = false; + d->altp2m_active = false; } #endif /* CONFIG_ALTP2M */ @@ -595,7 +596,7 @@ void hap_teardown(struct domain *d, bool *preempted) for_each_vcpu ( d, v ) altp2m_vcpu_disable_ve(v); - d->arch.altp2m_active = false; + d->altp2m_active = false; FREE_XENHEAP_PAGE(d->arch.altp2m_eptp); FREE_XENHEAP_PAGE(d->arch.altp2m_visible_eptp); diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index e55e53f44c78..a9d6b081a523 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -9,6 +9,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include /* copy_from_guest() */ #include #include diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 5c7a0ff30e8b..8319733b1bb6 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -8,6 +8,7 @@ * Copyright (c) 2009 Citrix Systems, Inc. (Grzegorz Milos) */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c index dfdbfa0afec8..ed850723f5fd 100644 --- a/xen/arch/x86/mm/p2m-ept.c +++ b/xen/arch/x86/mm/p2m-ept.c @@ -4,6 +4,7 @@ * Copyright (c) 2007, Intel Corporation. */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m-pt.c b/xen/arch/x86/mm/p2m-pt.c index 5a6ce2f8bc2e..17f38aac14d5 100644 --- a/xen/arch/x86/mm/p2m-pt.c +++ b/xen/arch/x86/mm/p2m-pt.c @@ -12,6 +12,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index fddecdf978ec..41517765c5ec 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -11,6 +11,7 @@ * Parts based on earlier work by Michael A Fetterman, Ian Pratt et al. */ +#include #include #include #include diff --git a/xen/common/monitor.c b/xen/common/monitor.c index d5c9ff1cbf8c..e758a3fea9f1 100644 --- a/xen/common/monitor.c +++ b/xen/common/monitor.c @@ -19,6 +19,7 @@ * License along with this program; If not, see . */ +#include #include #include #include diff --git a/xen/include/asm-generic/altp2m.h b/xen/include/asm-generic/altp2m.h index 39865a842ab3..ecee6942f4e8 100644 --- a/xen/include/asm-generic/altp2m.h +++ b/xen/include/asm-generic/altp2m.h @@ -4,16 +4,8 @@ #include -struct domain; struct vcpu; -/* Alternate p2m on/off per domain */ -static inline bool altp2m_active(const struct domain *d) -{ - /* Not implemented on GENERIC. */ - return false; -} - /* Alternate p2m VCPU */ static inline unsigned int altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 520328fd3fa8..b3b21124dd7e 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,4 +2,23 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ +#include + +#ifdef CONFIG_ALTP2M + +/* Alternate p2m HVM on/off per domain */ +static inline bool altp2m_active(const struct domain *d) +{ + return d->altp2m_active; +} + +#else /* CONFIG_ALTP2M */ + +static inline bool altp2m_active(const struct domain *d) +{ + return false; +} + +#endif /* CONFIG_ALTP2M */ + #endif /* __XEN_ALTP2M_H__ */ diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..458f2f260dd7 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -623,6 +623,8 @@ struct domain } monitor; #ifdef CONFIG_ALTP2M + /* altp2m: allow multiple copies of host p2m */ + bool altp2m_active; unsigned int nr_altp2m; /* Number of altp2m tables. */ #endif -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:38:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:38:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288146.1568465 (Exim 4.92) (envelope-from ) id 1wEwK7-0002q2-IU; Mon, 20 Apr 2026 21:38:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288146.1568465; Mon, 20 Apr 2026 21:38:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEwK7-0002pv-Fk; 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This makes it possible to use them in the common implementation of HVMOP_altp2m_set_domain_state. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the altp2m_vcpu_{initialise,destroy} phase. Signed-off-by: Rose Spangler --- v6: Introduced this patch. --- xen/arch/x86/include/asm/altp2m.h | 6 ----- xen/arch/x86/mm/altp2m.c | 41 ------------------------------- xen/common/altp2m.c | 41 +++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 6 +++++ 4 files changed, 47 insertions(+), 47 deletions(-) diff --git a/xen/arch/x86/include/asm/altp2m.h b/xen/arch/x86/include/asm/altp2m.h index b3d348386a00..43dd5d2acd9c 100644 --- a/xen/arch/x86/include/asm/altp2m.h +++ b/xen/arch/x86/include/asm/altp2m.h @@ -105,10 +105,6 @@ int altp2m_get_effective_entry(struct p2m_domain *ap2m, gfn_t gfn, mfn_t *mfn, p2m_type_t *t, p2m_access_t *a, bool prepopulate); -/* Alternate p2m VCPU */ -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); @@ -151,8 +147,6 @@ static inline int _altp2m_get_effective_entry(struct p2m_domain *ap2m, /* Only declaration is needed. DCE will optimise it out when linking. */ uint16_t altp2m_vcpu_idx(const struct vcpu *v); -void altp2m_vcpu_initialise(struct vcpu *v); -void altp2m_vcpu_destroy(struct vcpu *v); int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn); void altp2m_vcpu_disable_ve(struct vcpu *v); diff --git a/xen/arch/x86/mm/altp2m.c b/xen/arch/x86/mm/altp2m.c index 46374373848d..0542e3ef9196 100644 --- a/xen/arch/x86/mm/altp2m.c +++ b/xen/arch/x86/mm/altp2m.c @@ -14,47 +14,6 @@ #include "mm-locks.h" #include "p2m.h" -void -altp2m_vcpu_initialise(struct vcpu *v) -{ - if ( !v->domain->nr_altp2m ) - return; - - if ( v != current ) - vcpu_pause(v); - - vcpu_altp2m(v).p2midx = 0; - atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); - - altp2m_vcpu_update_p2m(v); - - if ( v != current ) - vcpu_unpause(v); -} - -void -altp2m_vcpu_destroy(struct vcpu *v) -{ - struct p2m_domain *p2m; - - if ( !v->domain->nr_altp2m ) - return; - - if ( v != current ) - vcpu_pause(v); - - if ( (p2m = altp2m_get_altp2m(v)) ) - atomic_dec(&p2m->active_vcpus); - - altp2m_vcpu_disable_ve(v); - - vcpu_altp2m(v).p2midx = INVALID_ALTP2M; - altp2m_vcpu_update_p2m(v); - - if ( v != current ) - vcpu_unpause(v); -} - int altp2m_vcpu_enable_ve(struct vcpu *v, gfn_t gfn) { struct domain *d = v->domain; diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index a731ad7cdab8..e699b64678d8 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -59,6 +59,47 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } +#ifdef CONFIG_X86 +void altp2m_vcpu_initialise(struct vcpu *v) +{ + if ( !v->domain->nr_altp2m ) + return; + + if ( v != current ) + vcpu_pause(v); + + vcpu_altp2m(v).p2midx = 0; + atomic_inc(&altp2m_get_altp2m(v)->active_vcpus); + + altp2m_vcpu_update_p2m(v); + + if ( v != current ) + vcpu_unpause(v); +} + +void altp2m_vcpu_destroy(struct vcpu *v) +{ + struct p2m_domain *p2m; + + if ( !v->domain->nr_altp2m ) + return; + + if ( v != current ) + vcpu_pause(v); + + if ( (p2m = altp2m_get_altp2m(v)) ) + atomic_dec(&p2m->active_vcpus); + + altp2m_vcpu_disable_ve(v); + + vcpu_altp2m(v).p2midx = INVALID_ALTP2M; + altp2m_vcpu_update_p2m(v); + + if ( v != current ) + vcpu_unpause(v); +} +#endif + /* * altp2m operations are envisioned as being used in several different * modes: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index f5a4d0e60562..7defe6126563 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -24,6 +24,12 @@ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); +#ifdef CONFIG_X86 +/* Alternate p2m VCPU */ +void altp2m_vcpu_initialise(struct vcpu *v); +void altp2m_vcpu_destroy(struct vcpu *v); +#endif + #ifdef CONFIG_ALTP2M /* Alternate p2m HVM on/off per domain */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:42:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:42:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288159.1568475 (Exim 4.92) (envelope-from ) id 1wEwNp-0005ez-5A; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3EhjpJEHMQnct9dyhsV5u6R1QwxylZ6yIouDcbYOinsikcZnu2UXbeLdOYDNU7DhW8h9rOQ04Q4vvEXJZUyZguKz5XUAl4qFoVNPB2dVMoZpYLoFaGPtL8AOZRNjRKbV0v6qxvl/r01d9uq2U4SPUdCRrzDy03o1O8RywoU80CZEuGGOo3Qqh+Ykuw3hQI/4nESw9AJCzBkhodFWTXh9+5zCD7eaHsFcZw9j0wE6LHAR9RGDL40jIzKRbXBx4Bftmj011iEPKyWtJ0cG/51r7kuX9J3HFqurjbBaN5MHjPL9NZ/rMlRFDn/EncXoSBUBpIeg3LVdZLU2louK9scxLCs6JknHpkvkWwA+30ZtYQwg8WW2wyVsYFs7nUsxpljGw2Cp3z6DUDmFmAZExHE5ObprMTq/rAJdYvpT/4wQYNS8v+E9mOYuo+NZCBgJIH+G X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:12.4667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b190bcd-d176-453d-8c40-08de9f246cea X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA6PR08MB10332 X-purgate-ID: tlsNG-ebf023/1776720797-4B7693FF-7995FDB3/0/0 X-purgate-type: clean X-purgate-size: 1589 From: Sergej Proskurin The function "p2m_alloc_table" should be able to allocate 2nd stage translation tables not only for the host's p2m but also for alternate p2m's. This commit is a refactor and contains no functional changes. This is commit 8/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Sergej Proskurin Acked-by: Julien Grall --- v2: Removed altp2m table initialization from "p2m_table_init". v3: Removed initialization of the field d->arch.altp2m_active in "p2m_table_init" to avoid altp2m initialization throughout different files. Merged the function "p2m_alloc_table" and "p2m_table_init". --- xen/arch/arm/mmu/p2m.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51753bb2c34d..f546f63f2489 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1426,10 +1426,8 @@ static struct page_info *p2m_allocate_root(void) return page; } -static int p2m_alloc_table(struct domain *d) +static int p2m_alloc_table(struct p2m_domain *p2m) { - struct p2m_domain *p2m = p2m_get_hostp2m(d); - p2m->root = p2m_allocate_root(); if ( !p2m->root ) return -ENOMEM; @@ -1576,7 +1574,7 @@ static int p2m_initialise(struct domain *d, struct p2m_domain *p2m) if ( rc ) return rc; - rc = p2m_alloc_table(d); + rc = p2m_alloc_table(p2m); if ( rc ) return rc; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:42:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:42:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288160.1568484 (Exim 4.92) (envelope-from ) id 1wEwNu-0005wV-Ci; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: q9b0/8OOMM0eMr4FbIda31N4yIbjebZqGyZx7EqXLeSUdyiDUwC9gKFlUs7THpn2Z+iSHuFyLMNP5qIQevshVSHI3nOqF8vWZfsEbWR+Oj7aps0GLHbhcySz8PFPSqtYquaVLLzNX0k0rYlmAT4XScVD4JwwFseg3GJWc5uJZSaOS+AyGVtr/CfBmUZFHqsWp2zIZX2xIuFRL03k4Q3sLSuT03J8NBBoOAFwS/VW70Pd+iVIzqPhDVXmLYGTvNWfUwPQ9U2iBII4Mt7P+qOzX2HWdBF+8zvC2SetAbqVfeu3FPCE34Sx16jjtv+EP1ua4IWUsYOhi4JAJfiPHT2Dvoa/MwTJ2rFgkfflxwEwRXFFivhHRg82PyDp2hAimyAhZ3pTYMIkTUt5YjVi8/03AjWYaAlF4dbtrvF0SezJo6QTADTWCOuBuObFaJa19TAJ X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:33:11.8995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ec4ddb7-dd66-4878-c2b7-08de9f246c93 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF00003F65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB8541 X-purgate-ID: tlsNG-c1860d/1776720803-38567DB1-9DEF0F34/0/0 X-purgate-type: clean X-purgate-size: 7788 The p2m initialization now invokes initialization routines responsible for the allocation and initialization of altp2m structures. The same applies to teardown routines. This commit adds the prerequisites for the common altp2m_init and altp2m_teardown functions to work on ARM; No further changes were necessary other than removing the CONFIG_X86 gating. This is commit 12/12 of the altp2m_init/altp2m_teardown routines phase. Signed-off-by: Rose Spangler Signed-off-by: Sergej Proskurin Signed-off-by: Aqib Javaid --- v2: Shared code between host/altp2m init/teardown functions. Added conditional init/teardown of altp2m. Altp2m related functions are moved to altp2m.c v3: Removed locking the altp2m_lock in altp2m_teardown. Locking this lock at this point is unnecessary. Removed re-setting altp2m_vttbr, altp2m_p2m, and altp2m_active values in the function "altp2m_teardown". Re-setting these values is unnecessary as the entire domain will be destroyed right afterwards. Removed check for "altp2m_enabled" in "p2m_init" as altp2m has not yet been enabled by libxl at this point. Removed check for "altp2m_enabled" before tearing down altp2m within the function "p2m_teardown" so that altp2m gets destroyed even if the HVM_PARAM_ALTP2M gets reset before "p2m_teardown" is called. Added initialization of the field d->arch.altp2m_active in "altp2m_init". Removed check for already initialized vmid's in "altp2m_init_one", as "altp2m_init_one" is now called always with an uninitialized p2m. Removed the array altp2m_vttbr[] in struct arch_domain. v4: Removed initialization of altp2m_p2m[] to NULL in altp2m_init, as the "struct arch_domain" is already initialized to zero. We moved the definition of the macro MAX_ALTP2M to a common place in a separate commit. v6: Reworked to use common altp2m init and teardown routines. Added altp2m_lock_init macro for use in altp2m_init. Split altp2m initialization in p2m_init into a separate function, p2m_init_altp2m, to more easily gate code behind CONFIG_ALTP2M. Pulled in addition of active_vcpus from a later patch in the patch series. Split teardown and free of altp2m views into p2m_teardown and p2m_teardown_final (part of altp2m_teardown), respectively. --- xen/arch/arm/include/asm/altp2m.h | 4 +++ xen/arch/arm/include/asm/domain.h | 8 ++++++ xen/arch/arm/include/asm/p2m.h | 5 ++++ xen/arch/arm/mmu/p2m.c | 44 ++++++++++++++++++++++++++++++- xen/common/altp2m.c | 2 -- xen/include/xen/altp2m.h | 2 -- 6 files changed, 60 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/include/asm/altp2m.h b/xen/arch/arm/include/asm/altp2m.h index 698c35427e75..5a217f48b103 100644 --- a/xen/arch/arm/include/asm/altp2m.h +++ b/xen/arch/arm/include/asm/altp2m.h @@ -19,6 +19,10 @@ static inline bool altp2m_supported(void) return true; } +#define altp2m_lock_init(d) spin_lock_init(&(d)->arch.altp2m_lock) +#define altp2m_lock(d) spin_lock(&(d)->arch.altp2m_lock) +#define altp2m_unlock(d) spin_unlock(&(d)->arch.altp2m_lock) + /* Alternate p2m VCPU */ static inline uint16_t altp2m_vcpu_idx(const struct vcpu *v) { diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index 576dbdec20af..9e69d62086cd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -128,6 +128,14 @@ struct arch_domain #endif struct resume_info resume_ctx; + +#ifdef CONFIG_ALTP2M + /* + * Lock that protects critical altp2m operations that must not be performed + * concurrently. + */ + spinlock_t altp2m_lock; +#endif } __cacheline_aligned; struct arch_vcpu diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 8ae0cd7ff589..db715c4f8bfc 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -9,6 +9,8 @@ #include #include +#include + #define paddr_bits PADDR_BITS /* Holds the bit size of IPAs in p2m tables. */ @@ -117,6 +119,9 @@ struct p2m_domain { /* Keeping track on which CPU this p2m was used and for which vCPU */ uint8_t last_vcpu_ran[NR_CPUS]; + /* Alternate p2m: count of vcpu's currently using this p2m. */ + atomic_t active_vcpus; + /* Choose between: host/alternate. */ p2m_class_t p2m_class; }; diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 0d37760ef5d5..04d17e787259 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -7,6 +8,7 @@ #include #include +#include #include #include #include @@ -1486,6 +1488,20 @@ int p2m_teardown(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); +#ifdef CONFIG_ALTP2M + unsigned int i; + int rc; + + d->altp2m_active = false; + + for ( i = 0; i < d->nr_altp2m; i++ ) + { + rc = p2m_teardown_one(d->altp2m_p2m[i]); + if ( rc ) + return rc; + } +#endif + return p2m_teardown_one(p2m); } @@ -1499,6 +1515,9 @@ void p2m_final_teardown(struct domain *d) * where relinquish_p2m_mapping() has been called. */ + if ( altp2m_supported() ) + altp2m_teardown(d); + while ( p2m_teardown_allocation(d) == -ERESTART ) continue; /* No preemption support here */ ASSERT(page_list_empty(&d->arch.paging.p2m_freelist)); @@ -1595,6 +1614,24 @@ struct p2m_domain *p2m_init_one(struct domain *d) return NULL; } +static int p2m_init_altp2m(struct domain *d) +{ +#ifdef CONFIG_ALTP2M + int rc; + + rc = altp2m_init(d); + if ( rc ) + { + p2m_free_one(p2m_get_hostp2m(d)); + return rc; + } + + d->altp2m_active = false; +#endif + + return 0; +} + static int p2m_init_hostp2m(struct domain *d) { struct p2m_domain *p2m = p2m_init_one(d); @@ -1608,10 +1645,15 @@ static int p2m_init_hostp2m(struct domain *d) int p2m_init(struct domain *d) { + int rc; spin_lock_init(&d->arch.paging.lock); INIT_PAGE_LIST_HEAD(&d->arch.paging.p2m_freelist); - return p2m_init_hostp2m(d); + rc = p2m_init_hostp2m(d); + if ( rc ) + return rc; + + return p2m_init_altp2m(d); } /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index cda653b713f0..989d8bdcb923 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -15,7 +15,6 @@ #include #endif -#if CONFIG_X86 int altp2m_init(struct domain *d) { unsigned int i; @@ -60,7 +59,6 @@ void altp2m_teardown(struct domain *d) XVFREE(d->altp2m_p2m); } -#endif /* CONFIG_X86 */ /* * altp2m operations are envisioned as being used in several different diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index 85ef22c2b29e..238c7a935586 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -13,13 +13,11 @@ * regardless of CONFIG_ALTP2M */ -#ifdef CONFIG_X86 /* Initialize altp2m views */ int altp2m_init(struct domain *d); /* Free altp2m views */ void altp2m_teardown(struct domain *d); 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Smith" , Rahul Singh , "Julien Grall" Subject: [RESEND-2 RFC PATCH v6 00/43] altp2m: Move altp2m routines to common code and add ARM support Date: Mon, 20 Apr 2026 17:31:23 -0400 Message-ID: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.10.178.50] X-ClientProxiedBy: denue6es012.ebgroup.elektrobit.com (10.243.160.140) To denue6es012.ebgroup.elektrobit.com (10.243.160.140) X-EOPAttributedMessage: 1 X-MS-Exchange-SkipListedInternetSender: ip=[213.95.148.172];domain=denue6es012.ebgroup.elektrobit.com X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C7:EE_|SJ0PR08MB7797:EE_|SA2PEPF000015C9:EE_|SA2PR08MB6748:EE_ X-MS-Office365-Filtering-Correlation-Id: e474e0b6-aa80-428e-254f-08de9f24587c X-SM-outgoing: yes X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|704162111799003|36860700016|1800799024|7416014|376014|82310400026|13003099007|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 47ytyXz1UpSD9cJKZSwqVR1ukiEfNtrEWgFnlPS+tgw7cdh0/8/i4lwN/b+KXh2Eyi1p8Mq2rP2TY1Kv9f8ViXWRC3tO62keEOTdlhSah3b5Ox5D+uptykc56hXLbqh3zs2/lg0+xGhHBmQhKhgDUnJVYEmmAFJfzxylBFSvOtB4+fMuha2IwIJGgjrjUKhAFAicby1yZ4rk/gBj5Fgjb/5KS/XQ3463WmCsW5kuWWtVmk4dri1wOIdrMKwy0iSnOY3DhIh2RTYabqF/Vxeu216JO1OIzD/H2RztIGZzrnpO6VogDl/oVFn/AAdLVaji1e80nDDNDn3yjxg2uxYBHoJ1ZNq2hs9VRMYv6R/QnfziwyYUUrd2S/icMQjVWPJ3K9Stiw8svZx4zE1aydYkPtQZfzl6PIuxUXa0ztFxxyebGtDBNuGgk2vq8TUu4ccV X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:32:38.1818 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e474e0b6-aa80-428e-254f-08de9f24587c X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR08MB6748 X-purgate-ID: tlsNG-ebf023/1776720767-4BB6B3FF-3A0F23C8/0/0 X-purgate-type: clean X-purgate-size: 9546 Hi all, For the past few months, myself and Aqib Javid have been working to port altp2m to ARM with support from Stewart Hildebrand and Stefano Stabellini. At the recent Spring Xen Summit, Aqib and Stewart gave a presentation which discussed the motivation behind this, along with an overview of the rebasing and testing process. While this effort started as a rebase[1] of the v5 patch series[2] by Sergej Proskurin and Tamas Lengyel, I have been reworking the branch to make most of the altp2m code common between x86 and ARM. This should address the major concerns that came up during review of the original patch series. For a quick overview of altp2m functionality and scope of the patch series, here's an excerpt from Sergej's cover letter: > In this patch series, we provide an implementation of the altp2m > subsystem for ARM. Our implementation is based on the altp2m subsystem for > x86, providing additional --alternate-- views on the guest's physical > memory by means of the ARM 2nd stage translation mechanism. The patches > introduce new HVMOPs and extend the p2m subsystem. [...] To be more > precise, altp2m allows to create and switch to additional p2m views (i.e. > gfn to mfn mappings). These views can be manipulated and activated as will > through the provided HVMOPs. In this way, the active guest instance in > question can seamlessly proceed execution without noticing that anything > has changed. As of right now, I've reworked patch series up through the HVMOP_altp2m_set_domain_state command and plan to continue implementing the remaining altp2m features. I've continued the patch series versioning by labeling my notes as v6, and the patch notes from v1-v5 have been preserved where applicable. I am hoping for some feedback on the general approach I've taken with this patch series, and I can incorporate any changes requested into the actual patch series submission. This is a pretty big patch series, so I've tried to make it as easy as possible to follow. I've tried to minimize the number of changes in each patch; there are quite a lot of patches so if it would be preferred to combine some patches I can do so. Here is the general approach I used throughout the patch series to turn x86 altp2m code into common altp2m code with ARM support: - Move function(s) from arch/x86/mm/altp2m.c to common/altp2m.c, gating declarations/definitions with #ifdef CONFIG_X86 - Add any additional features to ARM code needed to implement these functions - Make any changes necessary to functions to support ARM, and remove #ifdef CONFIG_X86 This approach makes it possible to separate out code movement patches from the actual changes needed to support ARM. Furthermore, each patch in the patch series still compiles for both x86 and ARM. Additionally, I've split the patch series into a number of "phases" to make it easier to understand the context of each patch. Each patch description indicates which phase it's a part of. - Preparation (8 commits) - Common do_altp2m_op (2 commits) - get_domain_state (1 commit) - altp2m_{init,teardown} routines (12 commits) - altp2m_{get,set}_altp2m (4 commits) - Needed for altp2m_vcpu_{initialise,destroy} - altp2m_vcpu_{initialise,destroy} (2 commits) - Needed for HVMOP_set_domain_state - altp2m view visibility (5 commits) - Needed for altp2m_init_by_id, altp2m_flush - altp2m_activate_altp2m (2 commits) - Needed for altp2m_init_by_id - altp2m_init_by_id (2 commits) - Needed for HVMOP_altp2m_set_domain_state - altp2m_reset_altp2m (2 commits) - Needed for altp2m_flush - altp2m_flush (2 commits) - Needed for HVMOP_altp2m_set_domain_state - set_domain_state (1 commit) The code for this patch series can also be found on GitLab: https://gitlab.com/xen-project/people/elektrobit/xen/-/tree/altp2m-arm-rework-rfc Best, Rose Spangler [1] Rebase of original patch series: https://gitlab.com/xen-project/people/elektrobit/xen/-/commits/altp2m-arm-rebase [2] Original patch series: v1: https://lore.kernel.org/xen-devel/20160704114605.10086-1-proskurin@sec.in.tum.de/ v2: https://lore.kernel.org/xen-devel/20160801171028.11615-1-proskurin@sec.in.tum.de/ v3: https://lore.kernel.org/xen-devel/20160816221714.22041-1-proskurin@sec.in.tum.de/ v4: https://lore.kernel.org/xen-devel/20170830183258.14612-1-proskurin@sec.in.tum.de/ v5 was never submitted to mailing list, but is available on GitHub: https://github.com/sergej-proskurin/xen/tree/arm-altp2m-v5 (Resend due to threading issues in first send attempt) Rose Spangler (38): altp2m: Add template common altp2m.c/altp2m.h altp2m: Move altp2m_active to common domain struct altp2m: Move altp2m_p2m to common domain struct x86/altp2m: Rename hvm_altp2m_supported to altp2m_supported altp2m: Move altp2m_supported to arch header arm/altp2m: Add template arch-specific altp2m.c/altp2m.h arm/altp2m: Introduce CONFIG_ALTP2M Kconfig option altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h altp2m: Move do_altp2m_op to common code altp2m: Add ARM support to do_altp2m_op arm/altp2m: Add support for HVMOP_altp2m_get_domain_state x86/p2m: Move p2m_{init,free}_one declarations to arch header x86/altp2m: Add lock functions accessible from common code altp2m: Move altp2m_{init,teardown} to common code arm/p2m: Allocate hostp2m with xzalloc arm/p2m: Move hostp2m init/teardown to individual functions arm/p2m: Invalidate root page table entries and flush TLB in p2m_flush_table arm/altp2m: Add support for altp2m init/teardown routines altp2m: Move altp2m_{get,set}_altp2m to common code arm/altp2m: Add altp2m index to arch_vcpu altp2m: Add altp2m_set_vcpu_idx arm/altp2m: Add support for altp2m_{get,set}_altp2m altp2m: Move altp2m_vcpu_{initialise,destroy} to common code arm/altp2m: Add support for altp2m_vcpu_{initialise,destroy} arm/altp2m: Add altp2m view validity/visibility indicator altp2m: Add altp2m_view_is_{valid,visible} x86/altp2m: Add altp2m_set_view_visibility_locked arm/altp2m: Add altp2m_set_view_visibility{,_locked} support arm/altp2m: Add support for HVMOP_altp2m_set_visibility x86/altp2m: Add altp2m_activate_altp2m declaration to arch header arm/altp2m: Add support for altp2m_activate_altp2m altp2m: Move altp2m_init_by_id to common code arm/altp2m: Add support for altp2m_init_by_id x86/altp2m: Add altp2m_reset_altp2m declaration to arch header arm/altp2m: Add altp2m_reset_altp2m routine altp2m: Move altp2m_flush to common code arm/altp2m: Add support for altp2m_flush arm/p2m: Add support for HVMOP_altp2m_set_domain_state Sergej Proskurin (5): arm/p2m: Cosmetic fix - substitute _gfn(ULONG_MAX) for INVALID_GFN arm/p2m: Change function prototype of p2m_alloc_table arm/p2m: Rename parameter in p2m_alloc_vmid arm/p2m: Change func prototype and impl of p2m_{alloc,free}_vmid arm/p2m: Introduce p2m_is_{hostp2m,altp2m} xen/arch/arm/Kconfig | 11 + xen/arch/arm/Makefile | 1 + xen/arch/arm/altp2m.c | 122 +++++ xen/arch/arm/domain.c | 2 +- xen/arch/arm/hvm.c | 9 + xen/arch/arm/include/asm/Makefile | 1 - xen/arch/arm/include/asm/altp2m.h | 84 ++++ xen/arch/arm/include/asm/domain.h | 19 +- xen/arch/arm/include/asm/p2m.h | 41 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/p2m.c | 162 ++++++- xen/arch/arm/p2m.c | 31 +- xen/arch/arm/traps.c | 2 +- xen/arch/x86/domain.c | 3 +- xen/arch/x86/hvm/emulate.c | 1 + xen/arch/x86/hvm/hvm.c | 413 +---------------- xen/arch/x86/hvm/monitor.c | 3 +- xen/arch/x86/hvm/vmx/vmx.c | 9 +- xen/arch/x86/include/asm/altp2m.h | 115 ++++- xen/arch/x86/include/asm/domain.h | 5 - xen/arch/x86/include/asm/hvm/hvm.h | 11 - xen/arch/x86/include/asm/p2m.h | 112 +---- xen/arch/x86/mm/altp2m.c | 242 +++------- xen/arch/x86/mm/hap/hap.c | 17 +- xen/arch/x86/mm/mem_access.c | 22 +- xen/arch/x86/mm/mem_sharing.c | 3 +- xen/arch/x86/mm/p2m-basic.c | 7 +- xen/arch/x86/mm/p2m-ept.c | 13 +- xen/arch/x86/mm/p2m-pt.c | 1 + xen/arch/x86/mm/p2m.c | 9 +- xen/arch/x86/mm/p2m.h | 6 - xen/common/Makefile | 1 + xen/common/altp2m.c | 551 +++++++++++++++++++++++ xen/common/monitor.c | 1 + xen/common/vm_event.c | 2 +- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 2 +- xen/include/asm-generic/altp2m.h | 5 +- xen/include/xen/altp2m.h | 98 ++++ xen/include/xen/p2m-common.h | 2 +- xen/include/xen/sched.h | 3 + 42 files changed, 1330 insertions(+), 818 deletions(-) create mode 100644 xen/arch/arm/altp2m.c create mode 100644 xen/arch/arm/include/asm/altp2m.h create mode 100644 xen/common/altp2m.c create mode 100644 xen/include/xen/altp2m.h -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 21:45:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 21:45:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288185.1568501 (Exim 4.92) (envelope-from ) id 1wEwQY-00085W-4A; Mon, 20 Apr 2026 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TOFnOmifBHmO1VS6QLW1+Si+aqCZQ6b5YGqmNFJL9R8/+I+5VLnBIGWxZqZRFIN24COdczVHvTgm82O0O+Jn5v3NdIsydxZfcxbYkTV4TD1PjpVt6QS+JMGwUdCaBDVdab4O6hk58b3Gf+MVF/fx28B7F7O2UcLZkv08Wjw2ADXVx3rt8TrqMsk77apAX2XBsVNxvo+t/QlZPSM6x81+mmRwzWdcnVtCvWGhzwBjtF//Tx8BwaS6WVlKwFF+IlIx6o/ugYxvuo15j/KL3vmaX9G7vYSdTn2mcGLdsflHeqebn02ygjJFCfqBN6HZQW99jqlssRNToE+yjrL5hxoiWH0vN6YBT7wMiiD3/Y9eVivMWm88gdtSmTSXVGJ3oLS/2CaBEaAg1CxuVFiXCxWfliV2+6z59MSRVIg6khyYmwqcNslFxOhy3jlD6b4VaACc X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 21:32:52.8449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47507922-bb98-4df0-2e62-08de9f246136 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BN3PEPF0000B070.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR08MB6817 X-purgate-ID: tlsNG-42698a/1776720784-07F7EF3B-1E434C2F/37/8714975798-1487109 X-purgate-type: bulk X-purgate-size: 26338 This commit moves the altp2m HVMOP implementation to common code, making it possible to re-use it across architectures. In this commit, the entire implementation is gated behind CONFIG_X86, with no changes to the body of do_altp2m_op. A stub implementation is added for ARM, which will be removed once do_altp2m_op has been modified to add ARM support. This commit contains only code movement, and no change in functionality is intended. This is commit 1/2 of the common do_altp2m_op phase. Signed-off-by: Rose Spangler Signed-off-by: Aqib Javaid --- v6: Introduced this patch. --- xen/arch/x86/hvm/hvm.c | 400 ------------------------------------- xen/common/altp2m.c | 413 +++++++++++++++++++++++++++++++++++++++ xen/include/xen/altp2m.h | 11 ++ 3 files changed, 424 insertions(+), 400 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5b6e91adce17..4adcc3c49d95 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4526,406 +4526,6 @@ static int hvmop_get_param( return rc; } -/* - * altp2m operations are envisioned as being used in several different - * modes: - * - * - external: All control and decisions are made by an external agent - * running domain 0. - * - * - internal: altp2m operations are used exclusively by an in-guest - * agent to protect itself from the guest kernel and in-guest - * attackers. - * - * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, - * but makes requests of an agent running outside the domain for - * bigger changes (such as modifying altp2m entires). - * - * This corresponds to the three values for HVM_PARAM_ALTP2M - * (external, mixed, limited). All three models have advantages and - * disadvantages. - * - * Normally hypercalls made by a program in domain 0 in order to - * control a guest would be DOMCTLs rather than HVMOPs. But in order - * to properly enable the 'internal' use case, as well as to avoid - * fragmentation, all altp2m subops should come under this single - * HVMOP. - * - * Note that 'internal' mode (HVM_PARAM_ALTP2M == XEN_ALTP2M_mixed) - * has not been evaluated for safety from a security perspective. - * Before using this mode in a security-critical environment, each - * subop should be evaluated for safety, with unsafe subops - * blacklisted in xsm_hvm_altp2mhvm_op(). - */ -static int do_altp2m_op( - XEN_GUEST_HANDLE_PARAM(void) arg) -{ -#ifdef CONFIG_ALTP2M - struct xen_hvm_altp2m_op a; - struct domain *d = NULL; - int rc = 0; - uint64_t mode; - - if ( !altp2m_supported() ) - return -EOPNOTSUPP; - - if ( copy_from_guest(&a, arg, 1) ) - return -EFAULT; - - if ( a.pad1 || a.pad2 || - (a.version != HVMOP_ALTP2M_INTERFACE_VERSION) ) - return -EINVAL; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - case HVMOP_altp2m_set_domain_state: - case HVMOP_altp2m_vcpu_enable_notify: - case HVMOP_altp2m_vcpu_disable_notify: - case HVMOP_altp2m_create_p2m: - case HVMOP_altp2m_destroy_p2m: - case HVMOP_altp2m_switch_p2m: - case HVMOP_altp2m_set_suppress_ve: - case HVMOP_altp2m_set_suppress_ve_multi: - case HVMOP_altp2m_get_suppress_ve: - case HVMOP_altp2m_set_mem_access: - case HVMOP_altp2m_set_mem_access_multi: - case HVMOP_altp2m_get_mem_access: - case HVMOP_altp2m_change_gfn: - case HVMOP_altp2m_get_p2m_idx: - case HVMOP_altp2m_set_visibility: - break; - - default: - return -EOPNOTSUPP; - } - - d = rcu_lock_domain_by_any_id(a.domain); - - if ( d == NULL ) - return -ESRCH; - - if ( !is_hvm_domain(d) ) - { - rc = -EOPNOTSUPP; - goto out; - } - - if ( (a.cmd != HVMOP_altp2m_get_domain_state) && - (a.cmd != HVMOP_altp2m_set_domain_state) && - !d->altp2m_active ) - { - rc = -EOPNOTSUPP; - goto out; - } - - mode = d->arch.hvm.params[HVM_PARAM_ALTP2M]; - - if ( XEN_ALTP2M_disabled == mode ) - { - rc = -EINVAL; - goto out; - } - - if ( d->nr_altp2m == 0 ) - { - rc = -EOPNOTSUPP; - goto out; - } - - if ( (rc = xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) - goto out; - - switch ( a.cmd ) - { - case HVMOP_altp2m_get_domain_state: - a.u.domain_state.state = altp2m_active(d); - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_set_domain_state: - { - struct vcpu *v; - bool ostate; - - if ( nestedhvm_enabled(d) ) - { - rc = -EINVAL; - break; - } - - rc = domain_pause_except_self(d); - if ( rc ) - break; - - ostate = d->altp2m_active; - d->altp2m_active = !!a.u.domain_state.state; - - /* If the alternate p2m state has changed, handle appropriately */ - if ( d->altp2m_active != ostate && - (ostate || !(rc = altp2m_init_by_id(d, 0))) ) - { - for_each_vcpu( d, v ) - { - if ( !ostate ) - altp2m_vcpu_initialise(v); - else - altp2m_vcpu_destroy(v); - } - - if ( ostate ) - altp2m_flush(d); - } - else if ( rc ) - d->altp2m_active = false; - - domain_unpause_except_self(d); - break; - } - - case HVMOP_altp2m_vcpu_enable_notify: - { - struct vcpu *v; - - if ( a.u.enable_notify.pad || - a.u.enable_notify.vcpu_id >= d->max_vcpus ) - { - rc = -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc = -EOPNOTSUPP; - break; - } - - v = d->vcpu[a.u.enable_notify.vcpu_id]; - - rc = altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); - break; - } - - case HVMOP_altp2m_vcpu_disable_notify: - { - struct vcpu *v; - - if ( a.u.disable_notify.vcpu_id >= d->max_vcpus ) - { - rc = -EINVAL; - break; - } - - if ( !cpu_has_vmx_virt_exceptions ) - { - rc = -EOPNOTSUPP; - break; - } - - v = d->vcpu[a.u.enable_notify.vcpu_id]; - - altp2m_vcpu_disable_ve(v); - break; - } - - case HVMOP_altp2m_create_p2m: - rc = altp2m_init_next_available(d, &a.u.view.view, - a.u.view.hvmmem_default_access); - if ( !rc ) - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - - case HVMOP_altp2m_destroy_p2m: - rc = altp2m_destroy_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_switch_p2m: - rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); - break; - - case HVMOP_altp2m_set_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc = -EINVAL; - else - { - gfn_t gfn = _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx = a.u.suppress_ve.view; - bool suppress_ve = a.u.suppress_ve.suppress_ve; - - rc = p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); - } - break; - - case HVMOP_altp2m_set_suppress_ve_multi: - { - uint64_t max_phys_addr = (1UL << d->arch.cpuid->extd.maxphysaddr) - 1; - - a.u.suppress_ve_multi.last_gfn = min(a.u.suppress_ve_multi.last_gfn, - max_phys_addr); - - if ( a.u.suppress_ve_multi.pad1 || - a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_gfn ) - rc = -EINVAL; - else - { - rc = p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); - if ( (!rc || rc == -ERESTART) && __copy_to_guest(arg, &a, 1) ) - rc = -EFAULT; - } - break; - } - - case HVMOP_altp2m_get_suppress_ve: - if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) - rc = -EINVAL; - else - { - gfn_t gfn = _gfn(a.u.suppress_ve.gfn); - unsigned int altp2m_idx = a.u.suppress_ve.view; - bool suppress_ve; - - rc = p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); - if ( !rc ) - { - a.u.suppress_ve.suppress_ve = suppress_ve; - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_set_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc = -EINVAL; - else - rc = p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0, - a.u.mem_access.access, - a.u.mem_access.view); - break; - - case HVMOP_altp2m_set_mem_access_multi: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.set_mem_access_multi.pad || - a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr ) - { - rc = -EINVAL; - break; - } - - /* - * Unlike XENMEM_access_op_set_access_multi, we don't need any bits of - * the 'continuation' counter to be zero (to stash a command in). - * However, 0x40 is a good 'stride' to make sure that we make - * a reasonable amount of forward progress before yielding, - * so use a mask of 0x3F here. - */ - rc = p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_list, - a.u.set_mem_access_multi.access_list, - a.u.set_mem_access_multi.nr, - a.u.set_mem_access_multi.opaque, - 0x3F, - a.u.set_mem_access_multi.view); - if ( rc > 0 ) - { - a.u.set_mem_access_multi.opaque = rc; - rc = -ERESTART; - if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp2m_op_t), - &a, u.set_mem_access_multi.opaque) ) - rc = -EFAULT; - } - break; - - case HVMOP_altp2m_get_mem_access: - if ( !vm_event_is_enabled(current) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( a.u.mem_access.pad ) - rc = -EINVAL; - else - { - xenmem_access_t access; - - rc = p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access, - a.u.mem_access.view); - if ( !rc ) - { - a.u.mem_access.access = access; - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - } - } - break; - - case HVMOP_altp2m_change_gfn: - if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) - rc = -EINVAL; - else - rc = altp2m_change_gfn(d, a.u.change_gfn.view, - _gfn(a.u.change_gfn.old_gfn), - _gfn(a.u.change_gfn.new_gfn)); - break; - - case HVMOP_altp2m_get_p2m_idx: - { - struct vcpu *v; - - if ( !altp2m_active(d) ) - { - rc = -EOPNOTSUPP; - break; - } - - if ( (v = domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) == NULL ) - { - rc = -EINVAL; - break; - } - - a.u.get_vcpu_p2m_idx.altp2m_idx = altp2m_vcpu_idx(v); - rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; - break; - } - - case HVMOP_altp2m_set_visibility: - { - unsigned int idx = a.u.set_visibility.altp2m_idx; - - if ( a.u.set_visibility.pad ) - rc = -EINVAL; - else if ( !altp2m_active(d) ) - rc = -EOPNOTSUPP; - else - rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); - break; - } - - default: - ASSERT_UNREACHABLE(); - rc = -EOPNOTSUPP; - break; - } - - out: - rcu_unlock_domain(d); - - return rc; -#else /* !CONFIG_ALTP2M */ - return -EOPNOTSUPP; -#endif /* CONFIG_ALTP2M */ -} - DEFINE_XEN_GUEST_HANDLE(compat_hvm_altp2m_op_t); /* diff --git a/xen/common/altp2m.c b/xen/common/altp2m.c index 1a4e102324d4..a43b3a3e34b3 100644 --- a/xen/common/altp2m.c +++ b/xen/common/altp2m.c @@ -1,5 +1,418 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include + +#include + +#include + +#include + +#ifdef CONFIG_X86 +#include +/* + * altp2m operations are envisioned as being used in several different + * modes: + * + * - external: All control and decisions are made by an external agent + * running domain 0. + * + * - internal: altp2m operations are used exclusively by an in-guest + * agent to protect itself from the guest kernel and in-guest + * attackers. + * + * - coordinated: An in-guest agent handles #VE and VMFUNCs locally, + * but makes requests of an agent running outside the domain for + * bigger changes (such as modifying altp2m entires). + * + * This corresponds to the three values for HVM_PARAM_ALTP2M + * (external, mixed, limited). All three models have advantages and + * disadvantages. + * + * Normally hypercalls made by a program in domain 0 in order to + * control a guest would be DOMCTLs rather than HVMOPs. But in order + * to properly enable the 'internal' use case, as well as to avoid + * fragmentation, all altp2m subops should come under this single + * HVMOP. + * + * Note that 'internal' mode (HVM_PARAM_ALTP2M == XEN_ALTP2M_mixed) + * has not been evaluated for safety from a security perspective. + * Before using this mode in a security-critical environment, each + * subop should be evaluated for safety, with unsafe subops + * blacklisted in xsm_hvm_altp2mhvm_op(). + */ +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + struct xen_hvm_altp2m_op a; + struct domain *d = NULL; + int rc = 0; + uint64_t mode; + + if ( !altp2m_supported() ) + return -EOPNOTSUPP; + + if ( copy_from_guest(&a, arg, 1) ) + return -EFAULT; + + if ( a.pad1 || a.pad2 || + (a.version != HVMOP_ALTP2M_INTERFACE_VERSION) ) + return -EINVAL; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + case HVMOP_altp2m_set_domain_state: + case HVMOP_altp2m_vcpu_enable_notify: + case HVMOP_altp2m_vcpu_disable_notify: + case HVMOP_altp2m_create_p2m: + case HVMOP_altp2m_destroy_p2m: + case HVMOP_altp2m_switch_p2m: + case HVMOP_altp2m_set_suppress_ve: + case HVMOP_altp2m_set_suppress_ve_multi: + case HVMOP_altp2m_get_suppress_ve: + case HVMOP_altp2m_set_mem_access: + case HVMOP_altp2m_set_mem_access_multi: + case HVMOP_altp2m_get_mem_access: + case HVMOP_altp2m_change_gfn: + case HVMOP_altp2m_get_p2m_idx: + case HVMOP_altp2m_set_visibility: + break; + + default: + return -EOPNOTSUPP; + } + + d = rcu_lock_domain_by_any_id(a.domain); + + if ( d == NULL ) + return -ESRCH; + + if ( !is_hvm_domain(d) ) + { + rc = -EOPNOTSUPP; + goto out; + } + + if ( (a.cmd != HVMOP_altp2m_get_domain_state) && + (a.cmd != HVMOP_altp2m_set_domain_state) && + !d->altp2m_active ) + { + rc = -EOPNOTSUPP; + goto out; + } + + mode = d->arch.hvm.params[HVM_PARAM_ALTP2M]; + + if ( XEN_ALTP2M_disabled == mode ) + { + rc = -EINVAL; + goto out; + } + + if ( d->nr_altp2m == 0 ) + { + rc = -EOPNOTSUPP; + goto out; + } + + if ( (rc = xsm_hvm_altp2mhvm_op(XSM_OTHER, d, mode, a.cmd)) ) + goto out; + + switch ( a.cmd ) + { + case HVMOP_altp2m_get_domain_state: + a.u.domain_state.state = altp2m_active(d); + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_set_domain_state: + { + struct vcpu *v; + bool ostate; + + if ( nestedhvm_enabled(d) ) + { + rc = -EINVAL; + break; + } + + rc = domain_pause_except_self(d); + if ( rc ) + break; + + ostate = d->altp2m_active; + d->altp2m_active = !!a.u.domain_state.state; + + /* If the alternate p2m state has changed, handle appropriately */ + if ( d->altp2m_active != ostate && + (ostate || !(rc = altp2m_init_by_id(d, 0))) ) + { + for_each_vcpu( d, v ) + { + if ( !ostate ) + altp2m_vcpu_initialise(v); + else + altp2m_vcpu_destroy(v); + } + + if ( ostate ) + altp2m_flush(d); + } + else if ( rc ) + d->altp2m_active = false; + + domain_unpause_except_self(d); + break; + } + + case HVMOP_altp2m_vcpu_enable_notify: + { + struct vcpu *v; + + if ( a.u.enable_notify.pad || + a.u.enable_notify.vcpu_id >= d->max_vcpus ) + { + rc = -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc = -EOPNOTSUPP; + break; + } + + v = d->vcpu[a.u.enable_notify.vcpu_id]; + + rc = altp2m_vcpu_enable_ve(v, _gfn(a.u.enable_notify.gfn)); + break; + } + + case HVMOP_altp2m_vcpu_disable_notify: + { + struct vcpu *v; + + if ( a.u.disable_notify.vcpu_id >= d->max_vcpus ) + { + rc = -EINVAL; + break; + } + + if ( !cpu_has_vmx_virt_exceptions ) + { + rc = -EOPNOTSUPP; + break; + } + + v = d->vcpu[a.u.enable_notify.vcpu_id]; + + altp2m_vcpu_disable_ve(v); + break; + } + + case HVMOP_altp2m_create_p2m: + rc = altp2m_init_next_available(d, &a.u.view.view, + a.u.view.hvmmem_default_access); + if ( !rc ) + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + + case HVMOP_altp2m_destroy_p2m: + rc = altp2m_destroy_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_switch_p2m: + rc = altp2m_switch_domain_altp2m_by_id(d, a.u.view.view); + break; + + case HVMOP_altp2m_set_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc = -EINVAL; + else + { + gfn_t gfn = _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx = a.u.suppress_ve.view; + bool suppress_ve = a.u.suppress_ve.suppress_ve; + + rc = p2m_set_suppress_ve(d, gfn, suppress_ve, altp2m_idx); + } + break; + + case HVMOP_altp2m_set_suppress_ve_multi: + { + uint64_t max_phys_addr = (1UL << d->arch.cpuid->extd.maxphysaddr) - 1; + + a.u.suppress_ve_multi.last_gfn = min(a.u.suppress_ve_multi.last_gfn, + max_phys_addr); + + if ( a.u.suppress_ve_multi.pad1 || + a.u.suppress_ve_multi.first_gfn > a.u.suppress_ve_multi.last_gfn ) + rc = -EINVAL; + else + { + rc = p2m_set_suppress_ve_multi(d, &a.u.suppress_ve_multi); + if ( (!rc || rc == -ERESTART) && __copy_to_guest(arg, &a, 1) ) + rc = -EFAULT; + } + break; + } + + case HVMOP_altp2m_get_suppress_ve: + if ( a.u.suppress_ve.pad1 || a.u.suppress_ve.pad2 ) + rc = -EINVAL; + else + { + gfn_t gfn = _gfn(a.u.suppress_ve.gfn); + unsigned int altp2m_idx = a.u.suppress_ve.view; + bool suppress_ve; + + rc = p2m_get_suppress_ve(d, gfn, &suppress_ve, altp2m_idx); + if ( !rc ) + { + a.u.suppress_ve.suppress_ve = suppress_ve; + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_set_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc = -EINVAL; + else + rc = p2m_set_mem_access(d, _gfn(a.u.mem_access.gfn), 1, 0, 0, + a.u.mem_access.access, + a.u.mem_access.view); + break; + + case HVMOP_altp2m_set_mem_access_multi: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.set_mem_access_multi.pad || + a.u.set_mem_access_multi.opaque > a.u.set_mem_access_multi.nr ) + { + rc = -EINVAL; + break; + } + + /* + * Unlike XENMEM_access_op_set_access_multi, we don't need any bits of + * the 'continuation' counter to be zero (to stash a command in). + * However, 0x40 is a good 'stride' to make sure that we make + * a reasonable amount of forward progress before yielding, + * so use a mask of 0x3F here. + */ + rc = p2m_set_mem_access_multi(d, a.u.set_mem_access_multi.pfn_list, + a.u.set_mem_access_multi.access_list, + a.u.set_mem_access_multi.nr, + a.u.set_mem_access_multi.opaque, + 0x3F, + a.u.set_mem_access_multi.view); + if ( rc > 0 ) + { + a.u.set_mem_access_multi.opaque = rc; + rc = -ERESTART; + if ( __copy_field_to_guest(guest_handle_cast(arg, xen_hvm_altp2m_op_t), + &a, u.set_mem_access_multi.opaque) ) + rc = -EFAULT; + } + break; + + case HVMOP_altp2m_get_mem_access: + if ( !vm_event_is_enabled(current) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( a.u.mem_access.pad ) + rc = -EINVAL; + else + { + xenmem_access_t access; + + rc = p2m_get_mem_access(d, _gfn(a.u.mem_access.gfn), &access, + a.u.mem_access.view); + if ( !rc ) + { + a.u.mem_access.access = access; + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + } + } + break; + + case HVMOP_altp2m_change_gfn: + if ( a.u.change_gfn.pad1 || a.u.change_gfn.pad2 ) + rc = -EINVAL; + else + rc = altp2m_change_gfn(d, a.u.change_gfn.view, + _gfn(a.u.change_gfn.old_gfn), + _gfn(a.u.change_gfn.new_gfn)); + break; + + case HVMOP_altp2m_get_p2m_idx: + { + struct vcpu *v; + + if ( !altp2m_active(d) ) + { + rc = -EOPNOTSUPP; + break; + } + + if ( (v = domain_vcpu(d, a.u.get_vcpu_p2m_idx.vcpu_id)) == NULL ) + { + rc = -EINVAL; + break; + } + + a.u.get_vcpu_p2m_idx.altp2m_idx = altp2m_vcpu_idx(v); + rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0; + break; + } + + case HVMOP_altp2m_set_visibility: + { + unsigned int idx = a.u.set_visibility.altp2m_idx; + + if ( a.u.set_visibility.pad ) + rc = -EINVAL; + else if ( !altp2m_active(d) ) + rc = -EOPNOTSUPP; + else + rc = altp2m_set_view_visibility(d, idx, a.u.set_visibility.visible); + break; + } + + default: + ASSERT_UNREACHABLE(); + rc = -EOPNOTSUPP; + break; + } + + out: + rcu_unlock_domain(d); + + return rc; +} +#else +int do_altp2m_op( + XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} +#endif /* * Local variables: diff --git a/xen/include/xen/altp2m.h b/xen/include/xen/altp2m.h index b3b21124dd7e..be627152668a 100644 --- a/xen/include/xen/altp2m.h +++ b/xen/include/xen/altp2m.h @@ -2,8 +2,12 @@ #ifndef __XEN_ALTP2M_H__ #define __XEN_ALTP2M_H__ +#include +#include #include +#include + #ifdef CONFIG_ALTP2M /* Alternate p2m HVM on/off per domain */ @@ -12,6 +16,8 @@ static inline bool altp2m_active(const struct domain *d) return d->altp2m_active; } +int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg); + #else /* CONFIG_ALTP2M */ static inline bool altp2m_active(const struct domain *d) @@ -19,6 +25,11 @@ static inline bool altp2m_active(const struct domain *d) return false; } +static inline int do_altp2m_op(XEN_GUEST_HANDLE_PARAM(void) arg) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_ALTP2M */ #endif /* __XEN_ALTP2M_H__ */ -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Apr 20 23:01:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 23:01:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288222.1568510 (Exim 4.92) (envelope-from ) id 1wExce-0007b4-Jl; Mon, 20 Apr 2026 23:01:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288222.1568510; Mon, 20 Apr 2026 23:01:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wExce-0007ax-HE; Mon, 20 Apr 2026 23:01:44 +0000 Received: by outflank-mailman (input) for mailman id 1288222; Mon, 20 Apr 2026 23:01:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wExcc-0007ar-PM for xen-devel@lists.xenproject.org; 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Mon, 20 Apr 2026 16:01:39 -0700 (PDT) Date: Mon, 20 Apr 2026 20:01:37 -0300 From: Jason Gunthorpe To: "Peng Fan (OSS)" Cc: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Peng Fan Subject: Re: [PATCH RFC] xen/swiotlb: avoid arch_sync_dma_* on per-device DMA memory Message-ID: <20260420230137.GQ2577880@ziepe.ca> References: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> X-purgate-ID: tlsNG-ef75cf/1776726101-AFB78C48-24534E36/0/0 X-purgate-type: clean X-purgate-size: 2212 On Wed, Apr 15, 2026 at 11:08:36PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > On ARM64, arch_sync_dma_for_{cpu,device}() assumes that the > physical address passed in refers to normal RAM that is part of the > kernel linear(direct) mapping, as it unconditionally derives a CPU > virtual address via phys_to_virt(). > > With Xen swiotlb, devices may use per-device coherent DMA memory, > such as reserved-memory regions described by 'shared-dma-pool', > which are assigned to dev->dma_mem. These regions may be marked > no-map in DT and therefore are not part of the kernel linear map. > In such cases, pfn_valid() still returns true, but phys_to_virt() > is not valid and cache maintenance via arch_sync_dma_* will fault. > > Prevent this by excluding devices with a private DMA memory pool > (dev->dma_mem) from the arch_sync_dma_* fast path, and always > fall back to xen_dma_sync_* for those devices to avoid invalid > phys_to_virt() conversions for no-map DMA memory while preserving the > existing fast path for normal, linear-mapped RAM. I think this is the same sort of weirdness the other two CC threads are dealing with.. We already have two different flags indicating the cache flush should be skipped, it would make more sense to have the swiotlb mangle the flags, just like for cc. https://lore.kernel.org/r/20260420061415.3650870-1-aneesh.kumar@kernel.org Then you know that the swiotlb was used and it should flow down to here. > * physical address to use is returned. > @@ -262,7 +267,8 @@ static dma_addr_t xen_swiotlb_map_phys(struct device *dev, phys_addr_t phys, > > done: > if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { > - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr)))) { > + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr))) && > + !dev_has_private_dma_pool(dev)) { Also this pfn_valid() is totally bogus. Unless DMA_ATTR_MMIO the phys must have a struct page, be pfn_valid, etc. This is why you are getting into trouble here, beacuse swiotlb created a non-struct page address and passed it to lower layers without setting something like DMA_ATTR_MMIO.. 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pr=C Message-ID: Date: Mon, 20 Apr 2026 18:37:49 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/8] tools/xenstored: add depth information to watches To: Juergen Gross , CC: Julien Grall , Anthony PERARD References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-5-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-5-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B36E:EE_|IA0PR12MB7602:EE_ X-MS-Office365-Filtering-Correlation-Id: e190bafb-565d-43e3-ea88-08de9f35555b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 8tOgjStQjO5mFySfvIke0Dk2Tb10wrj9uJapuRhvz+DNaza98vxpdB106fEPakv/4rQsqXC8w29KTD+n88XdrJFWM35mYDB/3trlCNROM8yaRDenVx/f8mma1F9Ft4VPiMwqhmobmH4IPRKZAUPd3/3n0C4SB+j/RFjf47vn8wOKePHlxyqd1n4rdRtAsKu2dIjKwjAN27ycL4KOYzvMLKwAvkzPw7bFy3/FY8GYFlF3LvKdv4Xt5J5G8JZXexdxQhtQk/CI7ZXzReRQE097rJ65WFrwnRdtjWUSwv8LYSE6feIkxDzvkirUhBABLF4srliGVLDrXPn+njNlHWSYcssaIAP85r8J73qKhOe018OqJ5UcZG4P4baxxlLoOO4dPPSQcpHVKITzcKE723jFEXTHFBYH/PvlNhKJZQ0jReXn2g/7xhE0K6DVy4e5jNAl8njs8X1aocFBlGr5vwTBPBD9+Ryqwf7ISwaaES4gVJj4FKv6u7Kv2BGkhDaDPreOKlxv6hMZdXpPAcA4VmsYYjM1v+PEbM6Bu103pO3gfmrohjLu1iLejuEoBywd52YiSfKqFaKXTcm6fLk0/auc6+R4dfmxmKrrrF6pgssIGffibnUCvtANpj9KcYHwO8AkdcL2JVeVAYCe1teK5nJcGNuEY3hz8Ccc2aMzuUZH7m1knPChMLRU/WYNXATvDlCPm6ymjS2nFYpMAcOYo4EE5xCQRJbzQB2tFdpdQQ1P72MxIeEFxrgQtOqEsy6x92XmVYoVPiTUx+ezIq89EHITXA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; 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A depth value of -1 is used for the current model of no > limit. > > Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Mon Apr 20 23:35:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 23:35:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288240.1568529 (Exim 4.92) (envelope-from ) id 1wEy9L-0004Ml-8o; Mon, 20 Apr 2026 23:35:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288240.1568529; Mon, 20 Apr 2026 23:35:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEy9L-0004Me-60; Mon, 20 Apr 2026 23:35:31 +0000 Received: by outflank-mailman (input) for mailman id 1288240; Mon, 20 Apr 2026 23:35:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEy9J-0004MU-Ak for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <76f82d46-9b47-475c-9fbb-732750332f56@amd.com> Date: Mon, 20 Apr 2026 18:49:48 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/8] tools/xenstored: replace the fire_watches() exact parameter To: Juergen Gross , CC: Julien Grall , Anthony PERARD References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-7-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-7-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D0:EE_|LV9PR12MB9808:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c103238-ac0b-46d3-92cb-08de9f36e10b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1x4jES18wa2EYrYsF4sBQt7lZG+rmP8BAc4cnDWV+INZHveCUoklNOaLQsC5kyAqg1n1Gz6BJoHRQ2oSHRg7uFgeu1HOyDHVd6hLQXxOCvmaVq+vuYh0npZt59Rdv9zRU2D6NrxAk7v88I5/HyIWyeV87BW/F33yjBhXqemNKwHiDxuo4j4cfhYOEa1uOiQFzgk4sgwr93h5SntDjxVK2Ar4F2JTusFYxSiHab7eY9pTh+aI5QavcLyZbxJCAZuGibQQvxcC3xMy3lWHPW40ab7TjWvPwEJvwDsxPXcwOQDQ2D5pm7IGfGZQz+GilDzGAipxjXrIUGyVINVveXR8Yf23OPrBvvN2u7s+YubZoo0++1NJRUcMJ3mz/7V16fanY5qcHRzukxvVXP/+ZjJZd7nkH305zaW0YZTyQEKmdU6wztNDBUjB4I9tCS789z0i X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 23:45:18.5136 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c103238-ac0b-46d3-92cb-08de9f36e10b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9808 X-purgate-ID: tlsNG-c201ff/1776728723-2A374443-BA623F4B/0/0 X-purgate-type: clean X-purgate-size: 934 On 2026-03-13 03:47, Juergen Gross wrote: > Today fire_watches() has the boolean "exact" parameter specifying how > the matching of the modified node with registered watches is to be > handled (only the exact node name is matching or all nodes being > in the subtree beneath the watched node). > > For the handling of / watch events 2 additional > matching possibility needs to be added, as those events should only > be delivered to clients having requested such events, either by > watching with the depth=1 parameter, or by directly > watching for /, while the traditional special > watch events should NOT delivered to those watchers. > > For this purpose rename the "exact" parameter to "match" and make it > an enum with four possible values. > > Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Mon Apr 20 23:51:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 23:51:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288261.1568547 (Exim 4.92) (envelope-from ) id 1wEyOT-0006Lq-R0; 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pr=C Message-ID: <262d66a0-972d-46e1-80cb-13d29866b874@amd.com> Date: Mon, 20 Apr 2026 18:55:56 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/8] tools/xenstored: expand special watch handling with depth feature To: Juergen Gross , CC: Julien Grall , Anthony PERARD References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-8-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-8-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC8:EE_|SA0PR12MB4381:EE_ X-MS-Office365-Filtering-Correlation-Id: 891ccf73-c908-48af-b7f6-08de9f37abc4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: C8TvHD1NDbdHKNxumQSXNZr74laywmpoQEKgqT5fN+lkJ1yy2rti1CMV+itsgY3+huMTkHZ+bXJJ1434XgMUTqUjLtsqZdR/hz9YyzewpuW2xjdbIFF+P4+mgNNgnzOfD+sf5c6OxVUHAdCLHO4jxjNIVnxqC3l0XzDQ2DQfypWFvTeOWy0yKYYS6YRvAEpsPYWKb2aNZKjxCURCROkliMhIk4Qv4CsmXUrkkaKxRsAMyP1bm9BjnAkVnNXc74HPUoITymD2aKEViDso8+axoNYySeEKwOyPo10V5l8CN6t4USh3xF8gjKKFIH8e8LaRcdSvOB1yDOCDncrvhzSlndt/FtVfv70Oqmb7rvKVwN7tF99w7/2l/Tz7gG/bEQfCtwonw3+ItG/NkGZUpkecjhj47FGYu6xQ8O7Vm+5J8+ItLm7rsSlpnjG4CrdciyEYVzDqHRW+AlzpMo0SF9EeFgnLzHx5luoDHehJFSnSzwXMyaMPv/nY1Uhcr1dXVC6TteFnsTgvk25RPxUnTA50ytaePxxhpxbhOK/U3vNCo+B1asV9bEl8VqUWHj8PhAiWJgoAwVGT+ufbZ7DOoevQAWg6Ya+iDRFASbG/ftcO7gzTSZ3JkTl4tDWsGKgAu37CWtB5Ihpy7tqjhv/EUHhK81blgjmHpjixTME/bJfqylJ9FFQVcgSytgGe9EOlhAT0cLe7pVuVsATcDY6kHYFPhVrrrrDpGmm+nC1KAWCV/NZ+z+OQwdxG0ucPd6NUrUeuB85SAlosXxs/p1gjhjXong== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +AhnAyaSZVWPdmLfTYSFKr1envXMAVmgaVGLqPZQKRFG/Iuk4FPhFrmIDP2GZpkmlLApfwAW8sClSb7KdwV9PCHVsK3cCb69G0utmMdBlT1/FdBtLLc+IOrEfOSNePLgXh7QBWGXny0RxnxwbgpuqTyP/Scuc6vPoJj38zC9broWwCqFupXtBESgS6uZMsHCcmbfcpsC0Th6Xfczxxy411aMTJzog2c9NrEtU4v6DkvYPRSG/3WrPTynO+o/EUbYwGo270XGobJJ08t5qTbksuYKWJODYLD/am2tWVUDb4NA0+RBFM99m5keeLYTxV/mZyCRVnkblMbCQQdg0YeNcaVxO8i4GRfHlSdLGMbdUfHl1H90POFXMrU+WFjw6XeXfIlBlcur4sAPmiceekhjtwdRDmeaDEkYXFagQaNJPbCNziebSrJ/8RwKmLIJAQhy X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 23:50:58.6438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 891ccf73-c908-48af-b7f6-08de9f37abc4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4381 X-purgate-ID: tlsNG-42698a/1776729067-7F57BF3B-D7E2B85F/0/0 X-purgate-type: clean X-purgate-size: 999 On 2026-03-13 03:47, Juergen Gross wrote: > With XENSTORE_SERVER_FEATURE_WATCHDEPTH available, special watch > handling needs to be extended: > > - when a special watch is set with depth = 1, the domid is added to > the watch event > > - it is possible to watch for @releaseDomain/ > > Signed-off-by: Juergen Gross > @@ -678,10 +693,13 @@ static int do_check_domain(struct domain *domain, bool *notify, > if ((state & XENMANAGE_GETDOMSTATE_STATE_SHUTDOWN) > && !domain->shutdown) { > domain->shutdown = true; > + fire_special_watches("@releaseDomain", domain->domid, > + WATCH_DOM); > *notify = true; > } > - if (!(state & XENMANAGE_GETDOMSTATE_STATE_DEAD)) > + if (!(state & XENMANAGE_GETDOMSTATE_STATE_DEAD)) { > return 0; > + } Stray {} addition? Reviewed-by: Jason Andryuk > } > if (domain->conn) { > /* domain is a talloc child of domain->conn. */ From xen-devel-bounces@lists.xenproject.org Mon Apr 20 23:51:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 20 Apr 2026 23:51:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288268.1568556 (Exim 4.92) (envelope-from ) id 1wEyOy-00074o-2Y; Mon, 20 Apr 2026 23:51:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288268.1568556; Mon, 20 Apr 2026 23:51:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEyOx-00074h-V2; Mon, 20 Apr 2026 23:51:39 +0000 Received: by outflank-mailman (input) for mailman id 1288268; Mon, 20 Apr 2026 23:51:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEyOw-000728-Fp for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <47c69c4c-aefa-4666-9b35-8bc84209f350@amd.com> Date: Mon, 20 Apr 2026 18:56:27 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] tools/xenstored: make XENSTORE_SERVER_FEATURE_WATCHDEPTH available To: Juergen Gross , CC: Julien Grall , Anthony PERARD References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-9-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260313074751.2904215-9-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|MN6PR12MB8567:EE_ X-MS-Office365-Filtering-Correlation-Id: 1acc870f-61be-4687-be31-08de9f37beb1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: mCXl5fqQYaqHl1fXQD1lCirlDL13F896BHCN0OOwXUjvWCk7YnV+JGrObH34pZmanpVueQGLTJHclQWuogwYFrH2iu0qlRjPy7hR2XmcGNUObqJ6FShZ2aHt5Lk2KCZIrPpr9BNv16wNCVq2PACtEgWyYeK9h+p0npIIFkJGlxLKB+5BpOkzFm37FiKJGju0XYncN1AE697XSGI8sNt+W/2JKAVMNggK3xFhzpvFjzbgWsae0na/+Abkw/zg7bmkQ4Ypn/qcNfKPyK8iJyL4OsmGfwTB9gFRLJ7g7G8NelfLhNBkbGjYh5EwMnbN1sALrzElxjvgik1lWJ+CzCOuE6rMdOQ6AEqk3ZWZCYMJa0g5gjJVrmCREHLHW+uPRovVxKSztukRgqhVGD1VoEmUvqPYTgreMfS2+4heiymH8enHBHOj2Co9eiKjgPnsTS7RS7tisQnD3uIQP31KPa1XwSkJ7JzYu9SUb5EDRwexlNIk4tFydILYrqyzw2BTip07/KyxaxGpbPv67yqTAMx+i2Ps4vgFL8dH1DezMUAf23XcXRlzEI5JYygr65k8YdE7Lo+pMFNgfd7sLjq/gGCX123CMPlX9OgCdZQc8jrpIqUOdPgszBVIZvT9lYYu6nsOztVF2ZoBynHjrGCI9bToYbxDTZRgT3T4pIugj8nq9PNsugK6QYaCeTFgqEwfZp5mKJugK8Kg015Ol4JKWoxUPY9adyadPP5jS8yVCjGHogdikFx9qWrpz7Wu25HTuNGuBrQ4lrXswIQFW2WjREzSRw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; 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pr=C Message-ID: <0744dac1-4154-426f-889e-efedf7c34803@amd.com> Date: Mon, 20 Apr 2026 18:59:07 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 9/8] tools/xs-clients: support depth with xenstore-watch To: Juergen Gross , CC: Julien Grall , Anthony PERARD References: <20260313074751.2904215-1-jgross@suse.com> <20260319150626.436719-1-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260319150626.436719-1-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD78:EE_|EAYPR12MB999180:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d1f6fc5-6e95-4c24-2296-08de9f381466 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: amFMLXD0R5uasg8I/mrxQraarUKzpSwHbcu6CudeOEjEJgrkP9PJ4KGZ1kR3ZjB+sp0eqPKNTj/gWEtKnwioIZlu5nLJ6HvTwvQyAgwhZtmoCwvwrIDVvVoF7Eyow8/eQR4FdXkute75934Ach6jGePf/erZaT9Pt5TaJ3QMQyfPiR0aey9/YqYr4NuOVVqBECllYEN1EB8vUZiZEtD8hsKQKqDgdQVFvp9cmUWa/rGP/P/WFu+I1iCOveNw5FKdj8UCqqc9gQhtMa/oUVXD2nbs8olMPmwtUk60fYseqGcR9II+lx/1bA133usy2hO6zac0VruLO7/s8tCzjLCCOkvwvIXKjHc0uVMJ3LqUdlbRK0iq9lULlpPH8HIzt+msBMZVDaHeo7qYEsq6597vGxldYjwjc8SjVYkEu4cC6PwT7XvfieD1L8J3QujEOlsf X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 23:53:54.2099 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d1f6fc5-6e95-4c24-2296-08de9f381466 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD78.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: EAYPR12MB999180 X-purgate-ID: tlsNG-bad1c0/1776729239-400ABA53-3B04D88A/0/0 X-purgate-type: clean X-purgate-size: 437 On 2026-03-19 11:06, Juergen Gross wrote: > Add a "-d " parameter to xenstore-watch, allowing to specify > the depth parameter of the XS_WATCH command. > > Using "-d" without support of depth by xenstored will refuse to set > the watch(es). > > Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk For bonus points, you can add it to the man page :) Regards, Jason From xen-devel-bounces@lists.xenproject.org Tue Apr 21 06:39:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 06:39:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288294.1568574 (Exim 4.92) (envelope-from ) id 1wF4lJ-0002xv-RZ; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260420174605.706329-1-andrew.cooper3@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776753546-E1BA4443-50D61DF6/0/0 X-purgate-type: clean X-purgate-size: 1984 On 20.04.2026 19:46, Andrew Cooper wrote: > The encoded MUL is 64 bits, so writes %rdx too. At a minimum, this needs > expressing as a clobber. I'm embarrassed of missing this. > Also fix a logical disconnect between 'overflow' being the carry flag not the > overflow flag. CF and OF are always the same for MUL instructions, so use the > flag which matches the variable name. I don't mind this too much, but the use of CF was deliberate: Imo OF is relevant to signed arithmetic only, whereas CF is the flag to use with unsigned operations. > Fixes: d5c70a51bfbe ("x86/APIC: handle overflow in TMICT calculation") > Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich > I've kept this form because it produces best code generation for GCCs which > support flag outputs. > > An alternative would be to capture product_hi and check the nonzero-ness, as > that's how OF/CF are produced in hardware, which would be better code > generation on very old GCCs. We could fit both, by further widening the use of ASM_FLAG_OUT(). > --- a/xen/arch/x86/apic.c > +++ b/xen/arch/x86/apic.c > @@ -1317,9 +1317,10 @@ int reprogram_timer(s_time_t timeout) > > apic_tmict = UINT32_MAX; > asm ( "mul %[expire]\n\t" > - ASM_FLAG_OUT(, "setc %[cf]") > - : "=a" (product), [cf] ASM_FLAG_OUT("=@ccc", "=qm") (overflow) > - : "0" ((unsigned long)bus_scale), [expire] "r" (expire) ); > + ASM_FLAG_OUT(, "seto %[of]") > + : "=a" (product), [of] ASM_FLAG_OUT("=@cco", "=qm") (overflow) Noticing only now - for the non-flag-output case this should be "=&a". With > + : "0" ((unsigned long)bus_scale), [expire] "r" (expire) ... %rax also being an input, there's no risk of the compiler using the register for the other input, but still. Would you mind making that adjustment as well, while at it? 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pr=C Message-ID: <137bd391-926d-4047-a760-638f2e58b99f@amd.com> Date: Tue, 21 Apr 2026 08:41:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] device-tree: Improve hwdom memory allocation for DMA To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" References: <20260417091155.39653-1-michal.orzel@amd.com> <412A9DF8-6F5C-402D-AEBD-88E6DE139E07@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <412A9DF8-6F5C-402D-AEBD-88E6DE139E07@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|DS0PR12MB8562:EE_ X-MS-Office365-Filtering-Correlation-Id: 58c7a0d4-9313-4443-fe7d-08de9f71107b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SmcPBV49rqBpTcfAUdCQthCHIVBp4PkoDg35AcLgpQpL2mbZJP2UprVEpVUozlozl1VMgn+cv9YCY36SX1K+s+ZzxTthh+PblF+sCPAhK9BdUAHGkQ/hufivDGSfrzM2S96LiOlW/GigUiqpnn5d9Xyq6flZ0mS8Upk0sQMrt43IjEwdIDXaIYIrLSVnhA/ZzMJ6cnIuXco4W0PfkFU3H1fLKRJqsctQQyR5nfjP2CZS03cEAtQhBpYF10gHYrDopWg8gbjKvt9YbFOaph1SE+ohsJuMgU63l6wFVHyOiru+sn9iXvhgM7lyjs5XDPTuusKtahYG4qKIEgDTXY9gco7AsYdNCbG2tAkpU2MjRpvYF8eR0L3dBCY/CPst/6yBdUHi5fU7Oy4V6VHjCsrHdLiuoQOqiRTSpsWEdjPe1RE9kqxC7hRi1PdbQ5XDxt2B X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 06:41:48.8761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58c7a0d4-9313-4443-fe7d-08de9f71107b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8562 X-purgate-ID: tlsNG-c201ff/1776753713-E09AD443-3D178CB2/0/0 X-purgate-type: clean X-purgate-size: 1763 On 20/04/2026 16:54, Luca Fancellu wrote: > Hi Michal, > >> On 17 Apr 2026, at 10:11, Michal Orzel wrote: >> >> When LLC coloring is enabled, the hardware domain gets memory from >> host free regions rather than the fixed guest RAM banks. The previous >> code sorted these regions by descending size, which usually causes >> high-address memory to be allocated first. >> >> All allocated memory could reside above 4 GB leaving DMA non-functional >> for devices with limited addressing capabilities. >> >> Improve the handling as follows: >> - Sort free regions by ascending address instead of descending size, >> so low-memory banks are allocated first, >> - Skip banks smaller than 128 MB (or the total remaining allocation, >> whichever is less) until the first bank is placed, ensuring >> place_modules() has enough contiguous space, >> - Extract the hardware domain allocation path into its own function >> (allocate_hwdom_memory) for clarity. >> >> Signed-off-by: Michal Orzel >> --- >> xen/common/device-tree/domain-build.c | 152 ++++++++++++++++---------- >> 1 file changed, 96 insertions(+), 56 deletions(-) > > It looks ok to me, the only thing is that if we have many smaller banks < 128 Mb before reaching > one that is at least 128 Mb, we won’t allocate them and loose them forever. > > It feels only a corner case so for me it’s ok Yes, that's something documented in the commit msg, so if we ever face upon the issue due to that we could revisit the implementation. For now, we haven't observed any issues. > > Reviewed-by: Luca Fancellu > Thanks. ~Michal > > Cheers, > Luca > > From xen-devel-bounces@lists.xenproject.org Tue Apr 21 06:47:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 06:47:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288316.1568593 (Exim 4.92) (envelope-from ) id 1wF4tP-0005Km-VI; Tue, 21 Apr 2026 06:47:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288316.1568593; Tue, 21 Apr 2026 06:47:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF4tP-0005Kf-QT; Tue, 21 Apr 2026 06:47:31 +0000 Received: by outflank-mailman (input) for mailman id 1288316; Tue, 21 Apr 2026 06:47:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF4tO-0005Hs-2i for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 06:47:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF4tL-00AVSJ-Q2 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:47:29 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e71d70-2eae-0a2a0a5409dd-0a2a450788d4-44 for ; Tue, 21 Apr 2026 08:47:29 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e71d81-229c-0a2a45070019-d155dd33e0b4-3 for ; Tue, 21 Apr 2026 08:47:29 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43d0deb7ad5so3067316f8f.2 for ; Mon, 20 Apr 2026 23:47:29 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnnHX8FAwAAAAAACgkQsN6d1ii/Ey/2 Pgf+N/w3KQc5a5gg/4WEdn6VFUTwXynKccOv+R6YQREDWEib6ZabYJWmBiHT0ASH3lC7w8Uo8Fpf mQQpGriaLne3Cl02SSgJAmNd+bF7M/2k8BLt3wqdTzxYxVtkoTyq41e+ITSkaeQjCF663qZNqNqf JBF2xA2cxUtRybsTP+jrX24jfYVZkKTYN7/C2U+Y+iJSXfvbq/pCekH51ReRVge+VcCFmRmUmp+r dbGWKdpiLNFHvwD6S+gEPoOIRXIUErCKlM8f3DoeAx65Qs9Q6WUfzjWs8KdkhhciYe9wiO+r36dZ /4/UaseQxBqZMOsAxTReYyGfZs9FhKasNef0py5zWw== =9W1+ -----END PGP SIGNATURE----- --------------gZQevFdlNm10dsOQUBwVI3vL-- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 06:54:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 06:54:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288325.1568601 (Exim 4.92) (envelope-from ) id 1wF50K-0006um-K0; Tue, 21 Apr 2026 06:54:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288325.1568601; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------ZSWoV6RU9DtjzB3DRNM0QY8R" X-purgate-ID: tlsNG-ebf023/1776754477-4BF6D3FF-DAC710BC/0/0 X-purgate-type: clean X-purgate-size: 9627 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------ZSWoV6RU9DtjzB3DRNM0QY8R Content-Type: multipart/mixed; boundary="------------Px9KkMhQVrNoGzHNqVfi3e1G"; protected-headers="v1" From: Juergen Gross To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Julien Grall Message-ID: Subject: Re: [PATCH 3/8] tools/libs/store: add support to use watches with a depth parameter References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-4-jgross@suse.com> <75667f07-b997-4bba-a905-9c5d80e8ba0c@amd.com> In-Reply-To: <75667f07-b997-4bba-a905-9c5d80e8ba0c@amd.com> --------------Px9KkMhQVrNoGzHNqVfi3e1G Content-Type: multipart/mixed; boundary="------------oNpgzHj051dAB4qkUxhRMpLI" --------------oNpgzHj051dAB4qkUxhRMpLI Content-Type: text/plain; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------Wf0mbeWitrpkJ4Dn0kNcmSH2" X-purgate-ID: tlsNG-16d1c6/1776754567-90E7CD75-A7751526/13/0 X-purgate-type: clean X-purgate-size: 6625 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------Wf0mbeWitrpkJ4Dn0kNcmSH2 Content-Type: multipart/mixed; boundary="------------dLr4yPIkNwdrrkusBEGzXA0J"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: Julien Grall , Anthony PERARD Message-ID: Subject: Re: [PATCH 9/8] tools/xs-clients: support depth with xenstore-watch References: <20260313074751.2904215-1-jgross@suse.com> <20260319150626.436719-1-jgross@suse.com> <0744dac1-4154-426f-889e-efedf7c34803@amd.com> In-Reply-To: <0744dac1-4154-426f-889e-efedf7c34803@amd.com> --------------dLr4yPIkNwdrrkusBEGzXA0J Content-Type: multipart/mixed; boundary="------------NjY8kP9omiIBxhG4d67TWfx0" --------------NjY8kP9omiIBxhG4d67TWfx0 Content-Type: text/plain; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------XBw0IpDbaIgGclcQBWW7oeuZ" X-purgate-ID: tlsNG-4011c0/1776754544-CEF718B7-FEFC6871/13/0 X-purgate-type: clean X-purgate-size: 7686 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------XBw0IpDbaIgGclcQBWW7oeuZ Content-Type: multipart/mixed; boundary="------------GkrmPigrT1zQ40meD9WIu9Qm"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: Julien Grall , Anthony PERARD Message-ID: <97872b47-c7e6-4ee4-89e3-a544900a1310@suse.com> Subject: Re: [PATCH 7/8] tools/xenstored: expand special watch handling with depth feature References: <20260313074751.2904215-1-jgross@suse.com> <20260313074751.2904215-8-jgross@suse.com> <262d66a0-972d-46e1-80cb-13d29866b874@amd.com> In-Reply-To: <262d66a0-972d-46e1-80cb-13d29866b874@amd.com> --------------GkrmPigrT1zQ40meD9WIu9Qm Content-Type: multipart/mixed; boundary="------------p8y6aMsHekD9jLgSToO3OH9Y" --------------p8y6aMsHekD9jLgSToO3OH9Y Content-Type: text/plain; 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bh=gP9v7Lo4itR1w9JAq840Ab8a/avBxLl0HToJo1/EYvY=; b=aFC4iJYDj4pwPwrCtjYWg1xDpF2SfAfIU754oNCRMt7+A0XNkaPDRpQwzhClN6+gx/bxTY 6w9TAUWEA7ovge7sv95BK1HLWwOUHWTJiQcuuwchknh+REWaC2BfdPnkRWc5nF4oO06THc gLjEURGYjG1ZP+L6CI/NZpjhz9Hey8U= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD Subject: [PATCH v2] tools/xenstored: remove unneeded check in create_node() Date: Tue, 21 Apr 2026 09:15:10 +0200 Message-ID: <20260421071510.222547-1-jgross@suse.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:dkim,suse.com:email]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; 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This means that the "conn" parameter is never NULL. Remove checking whether "conn" is not NULL. Coverity ID: 1690859 Signed-off-by: Juergen Gross --- V2: - added Coverity ID (Jan Beulich) --- tools/xenstored/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 4786a2a82e..34cb266e8a 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -1524,7 +1524,7 @@ static struct node *create_node(struct connection *conn, const void *ctx, if (!node) return NULL; - if (conn && conn->transaction) + if (conn->transaction) ta_node_created(conn->transaction); node->data = data; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:24:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:24:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288365.1568638 (Exim 4.92) (envelope-from ) id 1wF5TC-000547-Na; Tue, 21 Apr 2026 07:24:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288365.1568638; Tue, 21 Apr 2026 07:24:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5TC-000540-JH; Tue, 21 Apr 2026 07:24:30 +0000 Received: by outflank-mailman (input) for mailman id 1288365; Tue, 21 Apr 2026 07:24:29 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF5TA-00053u-Vi for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 07:24:29 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF5TA-009w2S-8v for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:24:28 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e72618-bab6-0a2a0a5309dd-0a2a4503e0da-30 for ; Tue, 21 Apr 2026 09:24:28 +0200 Received: from [209.85.208.169] (helo=mail-lj1-f169.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7262b-672d-0a2a45030019-d155d0a9a88e-3 for ; Tue, 21 Apr 2026 09:24:28 +0200 Received: by mail-lj1-f169.google.com with SMTP id 38308e7fff4ca-38dd9f0fdc6so51803171fa.0 for ; Tue, 21 Apr 2026 00:24:28 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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With rewording it to "Introduce get-core-temp command to xenpm to query CPU temperatures on Intel platforms.": Acked-by: Oleksii Kurochko Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:25:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:25:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288371.1568646 (Exim 4.92) (envelope-from ) id 1wF5Tj-0005Vt-US; Tue, 21 Apr 2026 07:25:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288371.1568646; Tue, 21 Apr 2026 07:25:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5Tj-0005Vm-R1; Tue, 21 Apr 2026 07:25:03 +0000 Received: by outflank-mailman (input) for mailman id 1288371; Tue, 21 Apr 2026 07:25:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5Ti-0005UF-2Z for xen-devel@lists.xenproject.org; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a4187ec277sm3524366e87.84.2026.04.21.00.32.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Apr 2026 00:32:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776756736; x=1777361536; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=mUTCUhVtcctCX2T3AeSdAHlM06T+CtqBLPNdEJl594I=; b=ZPC4FRIQOgw42MvVMn7avxxVaeWGJQlqfUyv5ldq+ANrrQ2iKzen1vRUe1cEs10KgP Iu4Ncy24mfH/Y+32CNSDqJlQ1i4/yqBZ5dKyvucZW2AdUq1mzOlgi/oPBIcMo+pO8YkC E9sHqvjqlPqFYVC7WOoiNyh72Q+jdTEap1TUOiPgi1NecgSG+PlpDH8WvbLNjhd5E+dh EQd0w1RZu+441RILyzXai/iO21oYWbbzTmWHFF1GRVtiurOgStQcYKIPI9skCyW976SL X9rhBOWmuq/WpZ7Jndv4Ae8WI19ZEYgbpNlNb6xarjM2g8iiKL2HzHGU588sVGxrpWn8 iXqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776756736; x=1777361536; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mUTCUhVtcctCX2T3AeSdAHlM06T+CtqBLPNdEJl594I=; b=qzQpU43JXcMLQdGMLbIzog4p9pMnesbe2MoedpAcXsMylODJT2/V7R/fWrZk/PGrAn PETBA0v1Ge6IF0WmJLQsTbsJ3hXVFGRdk8BFD8mz32jZM2X34zRv2FZl3QnzSpWTNzeR OUBBFMBDIdfqXUuqHZxU4hBF+cCTB4ZzO4CrzuLQjRHO6bRXeI8kFTMPjbFcuKSZf3g+ TpyPAKYka1SmFt30Fw4sgADamhm59MAsFk41tBqKpciolYevHAdsIay77jDqL9wSYZxE vKx5fJAsbzZggrSId+NQXUCi6tZS3wdHaY05egqoG0YD+ObyQZbQelV9OGkFGDeB9ds9 ECDQ== X-Forwarded-Encrypted: i=1; AFNElJ/B/xVxYIr60bnI+VC7nuBBOAnEC4Ai406bmd+hSQLL9VnYF+frCb+hZwvrnlTZJ4RrLp0yHUKInt8=@lists.xenproject.org X-Gm-Message-State: AOJu0Yz8ZZkZdWHN/0O/td/Hq7YrR7Q/GtD7WxOtTHoM4Mz/5puoukrf 0QcKx21ShJoi2CDRJAuzY2oRay7fONldaks+1A5Ugm4Hflmg7ghYVFdl X-Gm-Gg: AeBDieuS9MZuK4Xym+UMkBJL8QcfdqPc+svluKbjcYpo0LXKVwY0EWZ6257DKmO+GZ6 1aO347PyLxrVxdlHCOVOf/VWvmsf+zeruc/hfGXs3HGaLGFUg0qM4Ne0nMjbEITN0XLWMnnNpwK FynDhvWsGDA+JbFtaG2Kq3wo9uz5XJV03Un8J4C/t3zwMHfZQCRExZ0IK0DqyvuUPsRame3DA+M 0E2UXZ2Rx6i8ZNVLqJ08L7cX+hvFacUCudlAg77716jYhak3lS5Um/nE2j/+h6vFB4fX4gP16SY ShOl/LV94veK//HTmzwzJkcgXUJP/B5PWg6IGKs4f8F7KnTsQUXRUyCOL0lgejPpJw8I1jwVkDd wfzLuXxgz31KdkFgrIawE+cGMNbCYUsxRI8wbRn/fHk/Kubg4viWrfUp6PQaW/FT1ZL7d37NfUP 0t+Qkvi18cxmwR/IHJrVPlNdZoc0FkkdS83xCcaV5niIUb1kDCWkCw1hRrjTv791wAJsdzmOMwd lqSj7f+h5ozDw== X-Received: by 2002:a05:6512:12c4:b0:5a2:be43:c57d with SMTP id 2adb3069b0e04-5a4172c77f5mr5686450e87.12.1776756735324; Tue, 21 Apr 2026 00:32:15 -0700 (PDT) Message-ID: Date: Tue, 21 Apr 2026 09:32:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 03/16] x86emul: support AVX10.1 To: Jan Beulich , "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie , Community Manager References: <1e2ff012-b07a-43be-9ba6-290b38d3c97c@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776756736-AFB78C48-7BF6EC86/10/73395122804 X-purgate-type: spam X-purgate-size: 2680 On 4/9/26 5:03 PM, Jan Beulich wrote: > This requires relaxing various pre-existing AVX512* checks, as AVX10.1 > covers all AVX512* except PF, ER, 4FMAPS, 4VNNIW (support for all of > which was removed meanwhile anyway), and VP2INTERSECT. At the same time > all vector widths are always supported. > > Note that visa_check(), replacing host_and_vcpu_must_have() uses, checks > only the guest capability: We wouldn't expose AVX512* (nor AVX10) > without the hardware supporting it. Similarly in avx512_vlen_check() the > original host_and_vcpu_must_have() is reduced just vcpu_must_have(). > This also simplifies (resulting) code in the test and fuzzing harnesses, > as there the XCR0 checks that are part of cpu_has_avx512* are only > needed in local code, not in the emulator itself (where respective > checking occurs elsewhere anyway, utilizing emul_test_read_xcr()). > > While in most cases the changes to x86_emulate() are entirely > mechanical, for opmask insns earlier unconditional AVX512F checks are > converted into "else" clauses to existing if/else-if ones. > > To be certain that no uses remain, also drop respective cpu_has_avx512* > (except in the test harness) and vcpu_has_avx512*(). > > Signed-off-by: Jan Beulich > --- > Probably avx512_vlen_check() should have the avx512_ prefix dropped, now > that it also covers AVX10. But if so that wants to be either a prereq or > a follow-on patch. > > visa_check() won't cover AVX10.2 and higher, but probably we will want > independent checking logic for that anyway. > > Spec version 2 still leaves unclear what the xstate components are which > would need enabling for AVX10/256. x86emul_get_fpu() is therefore > untouched for now. > > Since it'll be reducing code size, we may want to further convert > host_and_vcpu_must_have() to just vcpu_must_have() where appropriate > (should be [almost?] everywhere). > --- > v4: Switch to using fallthrough pseudo-keyword. Drop new _vlen_check() > helper again. Re-base. > v3: Add ChangeLog entry. > v2: Drop use of vsz128 field. Re-base, in particular over dropping of > Xeon Phi support. > > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -16,6 +16,7 @@ The format is based on [Keep a Changelog > mitigate (by rate-limiting) the system wide impact of an HVM guest > misusing atomic instructions. > - Support for CPIO microcode in discrete multiboot modules. > + - Support for AVX10.1. (Experimental) Acked-by: Oleksii Kurochko . What should be done else to have not experimental support of AVX10.1? Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:32:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:32:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288387.1568663 (Exim 4.92) (envelope-from ) id 1wF5b8-0007yH-Na; Tue, 21 Apr 2026 07:32:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288387.1568663; Tue, 21 Apr 2026 07:32:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5b8-0007yA-Kj; Tue, 21 Apr 2026 07:32:42 +0000 Received: by outflank-mailman (input) for mailman id 1288387; Tue, 21 Apr 2026 07:32:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF5b8-0007xx-51 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 07:32:42 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF5b7-00DRbB-Hb for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:32:41 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e72815-2eae-0a2a0a5409dd-0a2a450cd90c-26 for ; Tue, 21 Apr 2026 09:32:41 +0200 Received: from [209.85.167.53] (helo=mail-lf1-f53.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e72819-62f1-0a2a450c0019-d155a735a85c-3 for ; Tue, 21 Apr 2026 09:32:41 +0200 Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-5a3be187ffbso4698026e87.0 for ; Tue, 21 Apr 2026 00:32:41 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Switch to using fallthrough pseudo-keyword. > Series re-ordering adjustments. Update to spec version 6. Add ChangeLog entry. > v3: New. > > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -16,7 +16,7 @@ The format is based on [Keep a Changelog > mitigate (by rate-limiting) the system wide impact of an HVM guest > misusing atomic instructions. > - Support for CPIO microcode in discrete multiboot modules. > - - Support for AVX10.1. (Experimental) > + - Support for AVX10.2. (Experimental) Acked-by: Oleksii Kurochko . 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Tue, 21 Apr 2026 00:34:33 -0700 (PDT) Message-ID: <18030a33-5280-4c15-ae72-159ba2a25018@suse.com> Date: Tue, 21 Apr 2026 09:34:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpuidle: split the max_cstate variable To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Teddy Astie , Marek Marczykowski References: <4b89f640-046a-49c1-95f1-947d98135e5b@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776756874-246B7F3B-CFC83654/0/0 X-purgate-type: clean X-purgate-size: 6729 On 20.04.2026 18:14, Roger Pau Monné wrote: > On Wed, Apr 08, 2026 at 01:34:43PM +0200, Jan Beulich wrote: >> @@ -690,18 +694,18 @@ static void cf_check acpi_processor_idle >> u32 exp = 0, pred = 0; >> u32 irq_traced[4] = { 0 }; >> >> - if ( max_cstate > 0 && power && >> + if ( max_cstate() > 0 && power && >> (next_state = cpuidle_current_governor->select(power)) > 0 ) >> { >> unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 >> - : max_cstate; >> + : max_cstate(); >> >> do { >> cx = &power->states[next_state]; >> } while ( (cx->type > max_state || >> cx->entry_method == ACPI_CSTATE_EM_NONE || >> (cx->entry_method == ACPI_CSTATE_EM_FFH && >> - cx->type == max_cstate && >> + cx->type == max_allowed_cstate && > > I'm afraid I'm missing why this uses max_allowed_cstate instead of > max_state. max_allowed_cstate is what needs using along with ... >> (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) && ... max_csubstate, as both are driven by the "max_cstate=" command line option. Renaming max_csubstate to max_allowed_csubstate would be an option, but would incure yet more churn. >> --- a/xen/arch/x86/cpu/mwait-idle.c >> +++ b/xen/arch/x86/cpu/mwait-idle.c >> @@ -1045,15 +1045,16 @@ static void cf_check mwait_idle(void) >> u64 before, after; >> u32 exp = 0, pred = 0, irq_traced[4] = { 0 }; >> >> - if (max_cstate > 0 && power && >> + if (max_cstate() > 0 && power && >> (next_state = cpuidle_current_governor->select(power)) > 0) { >> unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 >> - : max_cstate; >> + : max_cstate(); >> >> do { >> cx = &power->states[next_state]; >> - } while ((cx->type > max_state || (cx->type == max_cstate && >> - MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && >> + } while ((cx->type > max_state || >> + (cx->type == max_allowed_cstate && > > Indentation is weird for the above line IMO, you should use hard 3 > tabs plus spaces afterwards, like the surrounding indentation? Ouch, indeed. >> + MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && >> --next_state); >> if (!next_state) >> cx = NULL; > > Seeing max_cstate() is used in multiple places here, you might want to > introduce a local max_cstate variable? Except that Misra doesn't like such naming, and any other name would feel odd to use. >> --- a/xen/include/xen/acpi.h >> +++ b/xen/include/xen/acpi.h >> @@ -142,30 +142,33 @@ int acpi_gsi_to_irq (u32 gsi, unsigned i >> >> #ifdef CONFIG_ACPI_CSTATE >> /* >> - * max_cstate sets the highest legal C-state. >> - * max_cstate = 0: C0 okay, but not C1 >> - * max_cstate = 1: C1 okay, but not C2 >> - * max_cstate = 2: C2 okay, but not C3 etc. >> - >> - * max_csubstate sets the highest legal C-state sub-state. Only applies to the >> - * highest legal C-state. >> - * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E >> - * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 >> - * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 >> - * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 >> + * max_{allowed,usable}_cstate sets the highest allowed / usable C-state, where >> + * "allowed" is command line / sysctl based. > > Hm, this is a bit misleading, because max_usable_cstate is also > command line based (plus system errata). What about: > > "max_{allowed,usable}_cstate sets the highest allowed / usable C-state. > max_usable_cstate can only be set from the command line, while > max_allowed_cstate can be set from both command line and systcl." Well. While I think I get your point, what I'm trying to get across is that max_usable_cstate is internally controlled (bounded by command line setting of max_allowed_cstate, but possibly forced lower than that internally). So maybe "max_{allowed,usable}_cstate sets the highest allowed / usable C-state. max_usable_cstate, while affected by the command line, is internally driven, whereas max_allowed_cstate can be set from both command line and systcl." ? >> + * max_*_cstate = 0: C0 okay, but not C1 >> + * max_*_cstate = 1: C1 okay, but not C2 >> + * max_*_cstate = 2: C2 okay, but not C3 etc. >> + * >> + * max_csubstate sets the highest allowed C-state sub-state. Only applies to >> + * the highest allowed C-state. >> + * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E >> + * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 >> + * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 >> + * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 >> */ >> >> -extern unsigned int max_cstate; >> +extern unsigned int max_usable_cstate; >> +extern unsigned int max_allowed_cstate; >> extern unsigned int max_csubstate; >> >> +#define max_cstate() min(max_usable_cstate, max_allowed_cstate) > > I would be tempted to drop the ending parenthesis so that you don't > need to adjust callers, but that's likely misleading, as then it would > need to be uppercase MAX_CSTATE. I deliberately want to have the parentheses, to make sure all uses of max_cstate (without the parentheses) have been covered (by converting in whatever appropriate way). Which extends to possible backports. In a subsequent, not to be backported commit we could drop them again if so desired. >> static inline unsigned int acpi_get_cstate_limit(void) >> { >> - return max_cstate; >> + return max_allowed_cstate; >> } >> static inline void acpi_set_cstate_limit(unsigned int new_limit) >> { >> - max_cstate = new_limit; >> - return; >> + max_allowed_cstate = new_limit; > > Do we want to check the new limit doesn't exceed max_usable_cstate and > return -ERANGE or similar on failure? > > After this change it's a bit weird to silently ignore invalid values > IMO. I disagree. Those values may be valid, just not usable (i.e. they are still a valid upper bound, but we'd never go as high up). If people wanted to use the same settings across their fleet, undue (and confusing) errors might result on some of their systems if we did as you suggest. Plus we have always accepted arbitrarily large (and hence entirely meaningless) values anyway. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776757098-AE971C48-7A8C7A27/10/73395122804 X-purgate-type: spam X-purgate-size: 2863 On 21.04.2026 09:32, Oleksii Kurochko wrote: > > > On 4/9/26 5:03 PM, Jan Beulich wrote: >> This requires relaxing various pre-existing AVX512* checks, as AVX10.1 >> covers all AVX512* except PF, ER, 4FMAPS, 4VNNIW (support for all of >> which was removed meanwhile anyway), and VP2INTERSECT. At the same time >> all vector widths are always supported. >> >> Note that visa_check(), replacing host_and_vcpu_must_have() uses, checks >> only the guest capability: We wouldn't expose AVX512* (nor AVX10) >> without the hardware supporting it. Similarly in avx512_vlen_check() the >> original host_and_vcpu_must_have() is reduced just vcpu_must_have(). >> This also simplifies (resulting) code in the test and fuzzing harnesses, >> as there the XCR0 checks that are part of cpu_has_avx512* are only >> needed in local code, not in the emulator itself (where respective >> checking occurs elsewhere anyway, utilizing emul_test_read_xcr()). >> >> While in most cases the changes to x86_emulate() are entirely >> mechanical, for opmask insns earlier unconditional AVX512F checks are >> converted into "else" clauses to existing if/else-if ones. >> >> To be certain that no uses remain, also drop respective cpu_has_avx512* >> (except in the test harness) and vcpu_has_avx512*(). >> >> Signed-off-by: Jan Beulich >> --- >> Probably avx512_vlen_check() should have the avx512_ prefix dropped, now >> that it also covers AVX10. But if so that wants to be either a prereq or >> a follow-on patch. >> >> visa_check() won't cover AVX10.2 and higher, but probably we will want >> independent checking logic for that anyway. >> >> Spec version 2 still leaves unclear what the xstate components are which >> would need enabling for AVX10/256. x86emul_get_fpu() is therefore >> untouched for now. >> >> Since it'll be reducing code size, we may want to further convert >> host_and_vcpu_must_have() to just vcpu_must_have() where appropriate >> (should be [almost?] everywhere). >> --- >> v4: Switch to using fallthrough pseudo-keyword. Drop new _vlen_check() >> helper again. Re-base. >> v3: Add ChangeLog entry. >> v2: Drop use of vsz128 field. Re-base, in particular over dropping of >> Xeon Phi support. >> >> --- a/CHANGELOG.md >> +++ b/CHANGELOG.md >> @@ -16,6 +16,7 @@ The format is based on [Keep a Changelog >> mitigate (by rate-limiting) the system wide impact of an HVM guest >> misusing atomic instructions. >> - Support for CPIO microcode in discrete multiboot modules. >> + - Support for AVX10.1. (Experimental) > > Acked-by: Oleksii Kurochko . Thanks. > What should be done else to have not experimental support of AVX10.1? Someone to actually try it out on real hardware. All my testing was with Intel's SDE. Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288420.1568700 (Exim 4.92) (envelope-from ) id 1wF5kV-00037G-Fq; Tue, 21 Apr 2026 07:42:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288420.1568700; Tue, 21 Apr 2026 07:42:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5kV-000377-CQ; Tue, 21 Apr 2026 07:42:23 +0000 Received: by outflank-mailman (input) for mailman id 1288420; Tue, 21 Apr 2026 07:42:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5kU-00036B-DG for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 07:42:22 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF5kR-00Aiof-Fk for xen-devel@lists.xenproject.org; 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Tue, 21 Apr 2026 07:42:19 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 53KPBVsq52n9NQAAD6G6ig (envelope-from ); Tue, 21 Apr 2026 07:42:19 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757340; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ReIly1atvh5rbm6DWS8EB7RxMnUs54f1iHdpQVFl9VA=; b=IFWssi8NDTX1FX3vbVE7W0gyiQmMrE0DPQaWlgYJLSoTyNvF9Q8GrWE5K7KLX1Hiu/zyNl RPhXtKLGMt8bc23G5M0gJaPmXMNjlIQynNxIGFQToS0XnPUlBMU7mg7clvvwD+Iyhib0h7 Upqb4LsW3JHhH6Cwzs4WjOgKtjkHqZY= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757339; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ReIly1atvh5rbm6DWS8EB7RxMnUs54f1iHdpQVFl9VA=; b=sNJz12Ks7Ia8ZjR5xXJWOPjYBd7aqAtUctmXudA44EQj5AveCbAzLXwER1TQBKv5dmu5Dm wH7rRKVB2RxfLWbwobfY0XHGPGpHhFg9gBZRM0ogEIs1no0zRZVkroU9VqhNGoM7RcAcMm vBhjpl0qwvG0NmXvgizRbwzjfYO5Hqw= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Jason Andryuk Subject: [PATCH v2 1/9] tools/xenstored: allow domU to get own features Date: Tue, 21 Apr 2026 09:42:03 +0200 Message-ID: <20260421074211.308473-2-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Score: -2.80 X-Spam-Level: X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; MIME_TRACE(0.00)[0:+]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,amd.com:email,imap1.dmz-prg2.suse.org:helo]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[10]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-purgate-ID: tlsNG-720697/1776757340-81772161-E6BDC29E/0/0 X-purgate-type: clean X-purgate-size: 3357 Expand the XS_GET_FEATURE command to allow an unprivileged domain to read its own available features. While this information is available via the related field in the shared page used for communication with Xenstore, user land components of the domU would need special support in the related kernel driver to obtain that data. With supporting the XS_GET_FEATURE for that purpose, only an up to date libxenstore is needed. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- docs/misc/xenstore.txt | 9 +++++---- tools/xenstored/core.c | 3 +-- tools/xenstored/domain.c | 16 +++++++++++----- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/docs/misc/xenstore.txt b/docs/misc/xenstore.txt index 4eccbc2f7f..8a2c19d116 100644 --- a/docs/misc/xenstore.txt +++ b/docs/misc/xenstore.txt @@ -427,13 +427,14 @@ SET_FEATURE || to set a bit for a feature not being supported by the running Xenstore will be denied. Providing no with the GET_FEATURE command will return the features which are supported - by Xenstore. + by Xenstore for the domain issuing the command. SET_FEATURE for a domain will be rejected after the INTRODUCE - command for this domain has been sent to xenstored. + command for this domain has been sent to xenstored. This has the + effect that dom0 will always have all supported features enabled. - xenstored prevents the use of GET_FEATURE and SET_FEATURE other - than by dom0. + xenstored prevents the use of GET_FEATURE with a domid specified + and SET_FEATURE other than by dom0. GET_QUOTA [[|]|] | SET_QUOTA [|]|| diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 34cb266e8a..93244d0ac4 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -2031,8 +2031,7 @@ static struct { { "SET_TARGET", do_set_target, XS_FLAG_PRIV }, [XS_RESET_WATCHES] = { "RESET_WATCHES", do_reset_watches }, [XS_DIRECTORY_PART] = { "DIRECTORY_PART", send_directory_part }, - [XS_GET_FEATURE] = - { "GET_FEATURE", do_get_feature, XS_FLAG_PRIV }, + [XS_GET_FEATURE] = { "GET_FEATURE", do_get_feature }, [XS_SET_FEATURE] = { "SET_FEATURE", do_set_feature, XS_FLAG_PRIV }, [XS_GET_QUOTA] = diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index 1684f6dee7..b0b339f569 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -1323,10 +1323,17 @@ int do_get_feature(const void *ctx, struct connection *conn, char *result; n_args = get_strings(in, vec, ARRAY_SIZE(vec)); - if (n_args > 1) - return EINVAL; - if (n_args == 1) { + if (!n_args) { + features = conn->domain ? conn->domain->features + : XENSTORE_FEATURES; + } else { + if (domain_is_unprivileged(conn)) + return EACCES; + + if (n_args > 1) + return EINVAL; + domid = parse_domid(vec[0]); if (errno) return errno; @@ -1334,8 +1341,7 @@ int do_get_feature(const void *ctx, struct connection *conn, if (!domain) return ENOENT; features = domain->features; - } else - features = XENSTORE_FEATURES; + } result = talloc_asprintf(ctx, "%u", features); if (!result) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288418.1568691 (Exim 4.92) (envelope-from ) id 1wF5kP-0002rr-4G; Tue, 21 Apr 2026 07:42:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288418.1568691; Tue, 21 Apr 2026 07:42:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5kP-0002rk-1P; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757334; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=GiCl29ziqUuQLuJlMeZlJuHJz+kWks534SS9M1I17Ug=; b=Hz1QnGSfVZNt1eIuMY9LSbhvALsPzAAEqb24kuFoEf7N8HdzwPp01dHX1f4LTSxhhEphZn k8GJLiT/7Fq8IVvl8oQbdlC17I7L26lhf0edYr111rNhpvwwmEaCyyApWt3N7s1NK9lgAw 10uVggoGl6l9Gei2zIU2HzEJijFqUNw= Authentication-Results: smtp-out1.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=Q3MqWZsL DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757333; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=GiCl29ziqUuQLuJlMeZlJuHJz+kWks534SS9M1I17Ug=; b=Q3MqWZsLsRb7dca3DyjcT7VPodi5wfSDUExbq4IX06CKABSf5G+xrLnivGlyjqVk0osqKt ecmPtLsQwsVk02f/NLIxoysdU+DloaA7bZJjvbTOOMNQAqkTqNwcfjcP7wKDq1hX9QV4JQ 2VMYMAL+VXNk7O8WTJRbl0uq+zYp3x0= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 0/9] tools/xenstored: add support for watch depth feature Date: Tue, 21 Apr 2026 09:42:02 +0200 Message-ID: <20260421074211.308473-1-jgross@suse.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCPT_COUNT_SEVEN(0.00)[9]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.com:dkim,suse.com:mid]; RCVD_TLS_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DKIM_TRACE(0.00)[suse.com:+] X-Rspamd-Queue-Id: CD6526A7F5 X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: X-purgate-ID: tlsNG-c201ff/1776757334-2BD67443-C6CE8F72/0/0 X-purgate-type: clean X-purgate-size: 2338 In order to reduce excessive number of watch events the watch depth feature has been defined, allowing the user to limit the number of node levels below the watched node to cause events. This series is implementing this feature for xenstored (including the PV and PVH stubdom variants). Possible users are: - xl/libxl: use domid information for the special @introduceDomain and @releaseDomain watches, which will be available when using depth = 1 - xenconsoled, like xl/libxl - any PV-device backends watching directories for added devices (no watch events when any device specific node is modified) - any PV-device frontend and backend watching the "state" node of the other side, in case the other side plays dirty games by building large sub-trees beneath the "state" node Changes in V2: - some minor stale changes reverted - last patch covered by the series now, man page updated Juergen Gross (9): tools/xenstored: allow domU to get own features docs: clarify Xenstore watch depth feature tools/libs/store: add support to use watches with a depth parameter tools/xenstored: add depth information to watches tools/xenstored: add depth handling to XS_WATCH tools/xenstored: replace the fire_watches() exact parameter tools/xenstored: expand special watch handling with depth feature tools/xenstored: make XENSTORE_SERVER_FEATURE_WATCHDEPTH available tools/xs-clients: support depth with xenstore-watch docs/man/xenstore-watch.1.pod | 9 ++ docs/man/xl.cfg.5.pod.in | 6 ++ docs/misc/xenstore.txt | 14 ++- tools/include/xenstore.h | 16 +++ tools/libs/store/libxenstore.map | 2 + tools/libs/store/xs.c | 102 +++++++++++++++--- tools/xenstored/core.c | 15 ++- tools/xenstored/domain.c | 61 ++++++++--- tools/xenstored/domain.h | 2 + tools/xenstored/lu.c | 3 + tools/xenstored/transaction.c | 14 +-- tools/xenstored/transaction.h | 4 +- tools/xenstored/watch.c | 161 ++++++++++++++++++++--------- tools/xenstored/watch.h | 10 +- tools/xs-clients/xenstore_client.c | 19 +++- xen/include/public/io/xs_wire.h | 2 + 16 files changed, 343 insertions(+), 97 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288423.1568709 (Exim 4.92) (envelope-from ) id 1wF5kc-0003Pc-Mc; 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none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757345; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iPRg4Ly3QUYx8/2y91VHHoWO9h9Vdg/2TbCdnDBP890=; b=YHumWoUwxokJOMJLqSgOVZ/DFcIwgdDUraFYeyOJdC2Fyab48AiFkUgtsbvhUwTFwzcFW2 sV1Wbi8xNp7f9M+2gQZJH9qAIearK9CkzopEMK8kp8R9UiLeJ/feGPXkpODp7tBL+32PCq ZFVG/1BnoqTTbwSptYVDIpgkxiW2X7Y= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Jason Andryuk Subject: [PATCH v2 2/9] docs: clarify Xenstore watch depth feature Date: Tue, 21 Apr 2026 09:42:04 +0200 Message-ID: <20260421074211.308473-3-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-2.80 / 50.00]; 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Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- docs/misc/xenstore.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/misc/xenstore.txt b/docs/misc/xenstore.txt index 8a2c19d116..dba6471387 100644 --- a/docs/misc/xenstore.txt +++ b/docs/misc/xenstore.txt @@ -266,7 +266,8 @@ WATCH ||[|]? decimal value of 0 or larger): it denotes the directory levels below to consider for a match ("0" would not match for a child of , "1" would match only for a direct child, - etc.). + etc.). The depth specification is possible only, if the + XENSTORE_SERVER_FEATURE_WATCHDEPTH feature is available. can be a to watch or @. In the latter case may have any syntax but it matches @@ -284,6 +285,8 @@ WATCH ||[|]? values are not supported. For @releaseDomain it is possible to watch only for a specific domain by specifying @releaseDomain/ for the path. + This requires the XENSTORE_SERVER_FEATURE_WATCHDEPTH to be + available. When a watch is first set up it is triggered once straight away, with equal to . Watches may be triggered -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288427.1568718 (Exim 4.92) (envelope-from ) id 1wF5kg-0003kv-Us; Tue, 21 Apr 2026 07:42:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288427.1568718; Tue, 21 Apr 2026 07:42:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5kg-0003ko-RG; Tue, 21 Apr 2026 07:42:34 +0000 Received: by outflank-mailman (input) for mailman id 1288427; Tue, 21 Apr 2026 07:42:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5kf-0003gn-Hj for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 07:42:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF5ke-00G0bm-UF for xen-devel@lists.xenproject.org; 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bh=A9/LjZwHaY/WSjnhzdGz7a4hIoUeCs2d8a5kulnUVaQ=; b=MT5Vwtx8VnnpCB53Z/CnAwrgEqwRk9i24LthB00dDjMTWQ9SNq2bgjdjm7feZnNRAiHVVt RK3tAGFDWBFkTvzsITlv61UlxJ/KA0wDdSpOoHxer31hi+xjMTku84rrtA85d8sWnk7Vu+ vYnM8nNWHTMhMES9JoDJPnh+x3RKOpc= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757350; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A9/LjZwHaY/WSjnhzdGz7a4hIoUeCs2d8a5kulnUVaQ=; b=JrZj0EOd5dpSIXt79POy8P1Iy1+QvB0uZZkMM4VevCpvEjKbZwX0Gfd4EQb7sXXT+T0tIQ 1qkcc8nD/q4wfLHp3nSofVLaJ/YMpy3ptV6b/N7LJIklEVK+tArHQVfak7nCux7BgUh3Mx 7TkN66RnfXeMpAJx09dWl5kOUhOnoQo= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Anthony PERARD , Julien Grall Subject: [PATCH v2 3/9] tools/libs/store: add support to use watches with a depth parameter Date: Tue, 21 Apr 2026 09:42:05 +0200 Message-ID: <20260421074211.308473-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Score: -2.80 X-Spam-Level: X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_THREE(0.00)[4]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-purgate-ID: tlsNG-d62444/1776757352-B6A61FF4-E1024CFE/0/0 X-purgate-type: clean X-purgate-size: 8639 Add a new xs_watch_depth() function to libxenstore allowing to limit the scope of a Xenstore watch. It can be used only in case Xenstore is supporting the XENSTORE_SERVER_FEATURE_WATCHDEPTH feature. For convenience add a xs_watch_try_depth() wrapper, which will call xs_watch_depth() if supported and xs_watch() otherwise. Cache the supported features of Xenstore in order not having to get them from Xenstore for each call of one of the new functions. Signed-off-by: Juergen Gross --- V2: - undo unmotivated change of variable scope (Jason Andryuk) --- docs/man/xl.cfg.5.pod.in | 6 ++ tools/include/xenstore.h | 16 +++++ tools/libs/store/libxenstore.map | 2 + tools/libs/store/xs.c | 102 +++++++++++++++++++++++++++---- xen/include/public/io/xs_wire.h | 2 + 5 files changed, 116 insertions(+), 12 deletions(-) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 3aac0bc4fb..2f77016ecf 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -740,6 +740,12 @@ Xenstore is capable to reconnect to a guest. Xenstore will present an error value in case it disconnects due to an error condition. +=item B<0x00000004> + +Xenstore supports to set watches with a limited depth (depth 0 matches +only the watched node, depth 1 matches the node and its direct children, +etc.). + =back The features supported by the running Xenstore instance can be retrieved diff --git a/tools/include/xenstore.h b/tools/include/xenstore.h index bf6d767a22..9422ed5657 100644 --- a/tools/include/xenstore.h +++ b/tools/include/xenstore.h @@ -177,6 +177,22 @@ bool xs_set_permissions(struct xs_handle *h, xs_transaction_t t, */ bool xs_watch(struct xs_handle *h, const char *path, const char *token); +/* Same as xs_watch(), but with limiting the matching for modified + * children to a specified depth (depth 0 only matches the node itself, + * depth 1 will additionally match direct children of the node, etc.). + * Only supported if the XENSTORE_SERVER_FEATURE_WATCHDEPTH (4) is set + * in the returned features of xs_get_features_supported(). + */ +bool xs_watch_depth(struct xs_handle *h, const char *path, const char *token, + unsigned int depth); + +/* If supported, same as xs_watch_depth(), use xs_watch() otherwise. + * As a result watches might trigger for nodes below the watched path, too. + * Not to be used for special watches! + */ +bool xs_watch_try_depth(struct xs_handle *h, const char *path, + const char *token, unsigned int depth); + /* Return the FD to poll on to see if a watch has fired. */ int xs_fileno(struct xs_handle *h); diff --git a/tools/libs/store/libxenstore.map b/tools/libs/store/libxenstore.map index a08ddd549f..7067068998 100644 --- a/tools/libs/store/libxenstore.map +++ b/tools/libs/store/libxenstore.map @@ -52,4 +52,6 @@ VERS_4.2 { xs_set_global_quota; xs_get_domain_quota; xs_set_domain_quota; + xs_watch_depth; + xs_watch_try_depth; } VERS_4.1; diff --git a/tools/libs/store/xs.c b/tools/libs/store/xs.c index 06462445e0..cb3508a86a 100644 --- a/tools/libs/store/xs.c +++ b/tools/libs/store/xs.c @@ -984,16 +984,8 @@ bool xs_restrict(struct xs_handle *h, unsigned domid) return false; } -/* Watch a node for changes (poll on fd to detect, or call read_watch()). - * When the node (or any child) changes, fd will become readable. - * Token is returned when watch is read, to allow matching. - * Returns false on failure. - */ -bool xs_watch(struct xs_handle *h, const char *path, const char *token) +static bool xs_watch_helper(struct xs_handle *h) { - struct xsd_sockmsg msg = { .type = XS_WATCH }; - struct iovec iov[3]; - #ifdef USE_PTHREAD #define DEFAULT_THREAD_STACKSIZE (16 * 1024) /* NetBSD doesn't have PTHREAD_STACK_MIN. */ @@ -1001,8 +993,8 @@ bool xs_watch(struct xs_handle *h, const char *path, const char *token) # define PTHREAD_STACK_MIN 0 #endif -#define READ_THREAD_STACKSIZE \ - ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ +#define READ_THREAD_STACKSIZE \ + ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ PTHREAD_STACK_MIN : DEFAULT_THREAD_STACKSIZE) /* We dynamically create a reader thread on demand. */ @@ -1050,16 +1042,89 @@ bool xs_watch(struct xs_handle *h, const char *path, const char *token) mutex_unlock(&h->request_mutex); #endif + return true; +} + +/* Watch a node for changes (poll on fd to detect, or call read_watch()). + * When the node (or any child) changes, fd will become readable. + * Token is returned when watch is read, to allow matching. + * Returns false on failure. + */ +bool xs_watch(struct xs_handle *h, const char *path, const char *token) +{ + struct xsd_sockmsg msg = { .type = XS_WATCH }; + struct iovec iov[3]; + + if (!xs_watch_helper(h)) + return false; + + iov[0].iov_base = &msg; + iov[0].iov_len = sizeof(msg); + iov[1].iov_base = (void *)path; + iov[1].iov_len = strlen(path) + 1; + iov[2].iov_base = (void *)token; + iov[2].iov_len = strlen(token) + 1; + + return xs_bool(xs_talkv(h, iov, ARRAY_SIZE(iov), NULL)); +} + +/* Same as xs_watch(), but with limiting the matching for modified + * children to a specified depth (depth 0 only matches the node itself, + * depth 1 will additionally match direct children of the node, etc.). + * Only supported if the XENSTORE_SERVER_FEATURE_WATCHDEPTH (4) is set + * in the returned features of xs_get_features_supported(). + */ +bool xs_watch_depth(struct xs_handle *h, const char *path, const char *token, + unsigned int depth) +{ + struct xsd_sockmsg msg = { .type = XS_WATCH }; + struct iovec iov[4]; + char depthstr[MAX_STRLEN(depth)]; + static bool depth_supported; + + if (!xs_watch_helper(h)) + return false; + + if (!depth_supported) { + unsigned int features; + + if (!xs_get_features_supported(h, &features)) + return false; + if (!(features & XENSTORE_SERVER_FEATURE_WATCHDEPTH)) + return false; + depth_supported = true; + } + + snprintf(depthstr, sizeof(depthstr), "%u", depth); + iov[0].iov_base = &msg; iov[0].iov_len = sizeof(msg); iov[1].iov_base = (void *)path; iov[1].iov_len = strlen(path) + 1; iov[2].iov_base = (void *)token; iov[2].iov_len = strlen(token) + 1; + iov[3].iov_base = depthstr; + iov[3].iov_len = strlen(depthstr) + 1; return xs_bool(xs_talkv(h, iov, ARRAY_SIZE(iov), NULL)); } +/* If supported, same as xs_watch_depth(), use xs_watch() otherwise. + * As a result watches might trigger for nodes below the watched path, too. + * Not to be used for special watches! + */ +bool xs_watch_try_depth(struct xs_handle *h, const char *path, + const char *token, unsigned int depth) +{ + unsigned int features; + + if (xs_get_features_supported(h, &features) && + (features & XENSTORE_SERVER_FEATURE_WATCHDEPTH) && + xs_watch_depth(h, path, token, depth)) + return true; + + return xs_watch(h, path, token); +} /* Clear the pipe token if there are no more pending watchs. * We suppose the watch_mutex is already taken. @@ -1420,13 +1485,26 @@ static bool xs_uint(char *reply, unsigned int *uintval) bool xs_get_features_supported(struct xs_handle *h, unsigned int *features) { + static unsigned int own_features = 0; + static bool features_valid = false; struct xsd_sockmsg msg = { .type = XS_GET_FEATURE }; struct iovec iov[1]; + if (features_valid) { + *features = own_features; + return true; + } + iov[0].iov_base = &msg; iov[0].iov_len = sizeof(msg); - return xs_uint(xs_talkv(h, iov, ARRAY_SIZE(iov), NULL), features); + if (!xs_uint(xs_talkv(h, iov, ARRAY_SIZE(iov), NULL), &own_features)) + return false; + + features_valid = true; + *features = own_features; + + return true; } bool xs_get_features_domain(struct xs_handle *h, unsigned int domid, diff --git a/xen/include/public/io/xs_wire.h b/xen/include/public/io/xs_wire.h index d2e2b8b9eb..2e763bc877 100644 --- a/xen/include/public/io/xs_wire.h +++ b/xen/include/public/io/xs_wire.h @@ -124,6 +124,8 @@ struct xenstore_domain_interface { #define XENSTORE_SERVER_FEATURE_RECONNECTION 1 /* The presence of the "error" field in the ring page */ #define XENSTORE_SERVER_FEATURE_ERROR 2 +/* The XS_WATCH command can be used with a parameter */ +#define XENSTORE_SERVER_FEATURE_WATCHDEPTH 4 /* Valid values for the connection field */ #define XENSTORE_CONNECTED 0 /* the steady-state */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288434.1568727 (Exim 4.92) (envelope-from ) id 1wF5kl-00046Q-4A; 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Tue, 21 Apr 2026 07:42:36 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757356; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yvTy7t/SOB7ZmlQaiUwnQjIziWvNFoKtoQktytGzRzE=; b=Ic8wK2spGH4AKeuUrHfNo8rO8FmowfiZKk3jGG0n+/uRb9E/VyDiclt14w8TIjt0gAu0Xx dpcmWuK1m85op6i0xLxtwJ401OBKLDRGoFpiN1n8JcAYopY6oFXhc/VIYYNuPOk2mWC6iS yPt0gG2IsupGS6u6tfCNzEdEl63KO3Y= Authentication-Results: smtp-out2.suse.de; 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A depth value of -1 is used for the current model of no limit. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- tools/xenstored/lu.c | 3 ++ tools/xenstored/watch.c | 110 ++++++++++++++++++++++++++++------------ tools/xenstored/watch.h | 1 + 3 files changed, 81 insertions(+), 33 deletions(-) diff --git a/tools/xenstored/lu.c b/tools/xenstored/lu.c index eaffdbc69e..7d9f086a59 100644 --- a/tools/xenstored/lu.c +++ b/tools/xenstored/lu.c @@ -183,6 +183,9 @@ void lu_read_state(void) case XS_STATE_TYPE_WATCH: read_state_watch(ctx, state.buf); break; + case XS_STATE_TYPE_WATCH_EXT: + read_state_watch_ext(ctx, state.buf); + break; case XS_STATE_TYPE_TA: xprintf("live-update: ignore transaction record\n"); break; diff --git a/tools/xenstored/watch.c b/tools/xenstored/watch.c index becb9c339d..42e24d3201 100644 --- a/tools/xenstored/watch.c +++ b/tools/xenstored/watch.c @@ -39,26 +39,35 @@ struct watch /* Offset into path for skipping prefix (used for relative paths). */ unsigned int prefix_len; + int depth; /* -1: no depth limit. */ char *token; char *node; }; /* Is child a subnode of parent, or equal? */ -static bool is_child(const char *child, const char *parent) +static bool is_child(const char *child, const char *parent, int depth) { - unsigned int len = strlen(parent); - - /* - * / should really be "" for this algorithm to work, but that's a - * usability nightmare. - */ - if (streq(parent, "/")) - return true; + unsigned int len = strlen(parent); /* len == 1 if parent is "/". */ + unsigned int sub_levels = (len == 1) ? 1 : 0; if (strncmp(child, parent, len) != 0) return false; - return child[len] == '/' || child[len] == '\0'; + if (child[len] != '/' && child[len] != '\0' && len > 1) + return false; + + if (depth < 0 || child[len] == '\0') + return true; + + while (sub_levels <= depth) { + if (child[len] == '\0') + return true; + if (child[len] == '/') + sub_levels++; + len++; + } + + return false; } static const char *get_watch_path(const struct watch *watch, const char *name) @@ -145,7 +154,7 @@ void fire_watches(struct connection *conn, const void *ctx, const char *name, get_watch_path(watch, name), watch->token); } else { - if (is_child(name, watch->node)) + if (is_child(name, watch->node, watch->depth)) send_event(req, i, get_watch_path(watch, name), watch->token); @@ -170,7 +179,7 @@ static int check_watch_path(struct connection *conn, const void *ctx, } static struct watch *add_watch(struct connection *conn, const char *path, - const char *token, bool relative, + const char *token, int depth, bool relative, bool no_quota_check) { struct watch *watch; @@ -178,6 +187,7 @@ static struct watch *add_watch(struct connection *conn, const char *path, watch = talloc(conn, struct watch); if (!watch) goto nomem; + watch->depth = depth; watch->node = talloc_strdup(watch, path); watch->token = talloc_strdup(watch, token); if (!watch->node || !watch->token) @@ -204,6 +214,7 @@ int do_watch(const void *ctx, struct connection *conn, struct buffered_data *in) { struct watch *watch; const char *vec[2]; + int depth = -1; bool relative; if (get_strings(in, vec, ARRAY_SIZE(vec)) != ARRAY_SIZE(vec)) @@ -223,7 +234,7 @@ int do_watch(const void *ctx, struct connection *conn, struct buffered_data *in) if (domain_quota_add_exceeds(conn->domain, ACC_WATCH, 1)) return ENOSPC; - watch = add_watch(conn, vec[0], vec[1], relative, false); + watch = add_watch(conn, vec[0], vec[1], depth, relative, false); if (!watch) return errno; @@ -287,28 +298,47 @@ const char *dump_state_watches(FILE *fp, struct connection *conn, const char *ret = NULL; struct watch *watch; struct xs_state_watch sw; + struct xs_state_watch_ext swe; struct xs_state_record_header head; const char *path; - - head.type = XS_STATE_TYPE_WATCH; + size_t path_len, token_len; list_for_each_entry(watch, &conn->watches, list) { - head.length = sizeof(sw); - - sw.conn_id = conn_id; path = get_watch_path(watch, watch->node); - sw.path_length = strlen(path) + 1; - sw.token_length = strlen(watch->token) + 1; - head.length += sw.path_length + sw.token_length; + path_len = strlen(path) + 1; + token_len = strlen(watch->token) + 1; + + if (watch->depth >= 0) { + head.type = XS_STATE_TYPE_WATCH_EXT; + head.length = sizeof(swe); + swe.conn_id = conn_id; + swe.path_length = path_len; + swe.token_length = token_len; + swe.depth = watch->depth; + } else { + head.type = XS_STATE_TYPE_WATCH; + head.length = sizeof(sw); + sw.conn_id = conn_id; + sw.path_length = path_len; + sw.token_length = token_len; + } + + head.length += path_len + token_len; head.length = ROUNDUP(head.length, 3); if (fwrite(&head, sizeof(head), 1, fp) != 1) return "Dump watch state error"; - if (fwrite(&sw, sizeof(sw), 1, fp) != 1) - return "Dump watch state error"; - if (fwrite(path, sw.path_length, 1, fp) != 1) + if (watch->depth >= 0) { + if (fwrite(&swe, sizeof(sw), 1, fp) != 1) + return "Dump watch state ext error"; + } else { + if (fwrite(&sw, sizeof(sw), 1, fp) != 1) + return "Dump watch state error"; + } + + if (fwrite(path, path_len, 1, fp) != 1) return "Dump watch path error"; - if (fwrite(watch->token, sw.token_length, 1, fp) != 1) + if (fwrite(watch->token, token_len, 1, fp) != 1) return "Dump watch token error"; ret = dump_state_align(fp); @@ -319,27 +349,41 @@ const char *dump_state_watches(FILE *fp, struct connection *conn, return ret; } -void read_state_watch(const void *ctx, const void *state) +static void process_state_watch(const void *ctx, unsigned int conn_id, + const char *path, const char *token, + int depth) { - const struct xs_state_watch *sw = state; struct connection *conn; - const char *path, *token; bool relative; - conn = get_connection_by_id(sw->conn_id); + conn = get_connection_by_id(conn_id); if (!conn) barf("connection not found for read watch"); - path = (char *)sw->data; - token = path + sw->path_length; - /* Don't check success, we want the relative information only. */ check_watch_path(conn, ctx, &path, &relative); if (!path) barf("allocation error for read watch"); - if (!add_watch(conn, path, token, relative, true)) + if (!add_watch(conn, path, token, depth, relative, true)) barf("error adding watch"); + +} + +void read_state_watch(const void *ctx, const void *state) +{ + const struct xs_state_watch *sw = state; + + process_state_watch(ctx, sw->conn_id, (char *)sw->data, + (char *)sw->data + sw->path_length, -1); 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d=suse.com; s=susede1; t=1776757361; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NTh41V/BJEBo815LhqNiJ9PaLEavgsQdAx4aeK8HTHQ=; b=KIp/c1/FL5788YEL97/5yCrDmrY9qzCmzNSl8AFX2Or3843M96TG5nj7SUP3C3LJQ+WRqV Xnr52EeuBeT/GvCkj6lUWZNRvOcVgN4kINR/ZKtQOCp6mvpi9/mb2PTtO9ooHdGppIkaqu 3f8bmeujbUrlj7ILBQHefVqA+sqXRd8= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD , Jason Andryuk Subject: [PATCH v2 5/9] tools/xenstored: add depth handling to XS_WATCH Date: Tue, 21 Apr 2026 09:42:07 +0200 Message-ID: <20260421074211.308473-6-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; 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Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- tools/xenstored/domain.c | 8 ++++++++ tools/xenstored/domain.h | 2 ++ tools/xenstored/watch.c | 11 +++++++++-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index b0b339f569..7f2fa16cf2 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -390,6 +390,14 @@ void wrl_apply_debit_trans_commit(struct connection *conn) wrl_apply_debit_actual(conn->domain); } +bool feature_available(const struct connection *conn, unsigned int feature) +{ + if (!conn->domain) + return XENSTORE_FEATURES & feature; + + return conn->domain->features & feature; +} + static unsigned int domain_get_soft_quota(struct domain *d, enum accitem what) { if (d && d->acc[what].val[Q_IDX_SOFT] != Q_VAL_DISABLED) diff --git a/tools/xenstored/domain.h b/tools/xenstored/domain.h index ca38b5e0ea..b1cfb5cd82 100644 --- a/tools/xenstored/domain.h +++ b/tools/xenstored/domain.h @@ -188,4 +188,6 @@ struct hashtable *domain_check_acc_init(void); void domain_check_acc_add(const struct node *node, struct hashtable *domains); void domain_check_acc(struct hashtable *domains); +bool feature_available(const struct connection *conn, unsigned int feature); + #endif /* _XENSTORED_DOMAIN_H */ diff --git a/tools/xenstored/watch.c b/tools/xenstored/watch.c index 42e24d3201..860c219f29 100644 --- a/tools/xenstored/watch.c +++ b/tools/xenstored/watch.c @@ -213,11 +213,18 @@ static struct watch *add_watch(struct connection *conn, const char *path, int do_watch(const void *ctx, struct connection *conn, struct buffered_data *in) { struct watch *watch; - const char *vec[2]; + const char *vec[3]; + unsigned int n_pars; int depth = -1; bool relative; - if (get_strings(in, vec, ARRAY_SIZE(vec)) != ARRAY_SIZE(vec)) + n_pars = get_strings(in, vec, ARRAY_SIZE(vec)); + if (n_pars == 3 && + feature_available(conn, XENSTORE_SERVER_FEATURE_WATCHDEPTH)) { + depth = atoi(vec[2]); + if (depth < 0) + return EINVAL; + } else if (n_pars != 2) return EINVAL; errno = check_watch_path(conn, ctx, &(vec[0]), &relative); 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Tue, 21 Apr 2026 07:42:47 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 0bd2BXcq52krNwAAD6G6ig (envelope-from ); Tue, 21 Apr 2026 07:42:47 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776757367; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,amd.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_FIVE(0.00)[5]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-purgate-ID: tlsNG-42698a/1776757367-0576AF3B-4AD8B1FA/0/0 X-purgate-type: clean X-purgate-size: 8378 Today fire_watches() has the boolean "exact" parameter specifying how the matching of the modified node with registered watches is to be handled (only the exact node name is matching or all nodes being in the subtree beneath the watched node). For the handling of / watch events 2 additional matching possibility needs to be added, as those events should only be delivered to clients having requested such events, either by watching with the depth=1 parameter, or by directly watching for /, while the traditional special watch events should NOT delivered to those watchers. For this purpose rename the "exact" parameter to "match" and make it an enum with four possible values. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- tools/xenstored/core.c | 12 +++++----- tools/xenstored/transaction.c | 14 +++++++----- tools/xenstored/transaction.h | 4 +++- tools/xenstored/watch.c | 42 +++++++++++++++++++++++++---------- tools/xenstored/watch.h | 9 +++++++- 5 files changed, 55 insertions(+), 26 deletions(-) diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 93244d0ac4..6d82111e29 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -1613,7 +1613,7 @@ static int do_write(const void *ctx, struct connection *conn, return errno; } - fire_watches(conn, ctx, name, node, false, NULL); + fire_watches(conn, ctx, name, node, MATCH_SUBTREE, NULL); send_ack(conn, XS_WRITE); return 0; @@ -1637,7 +1637,7 @@ static int do_mkdir(const void *ctx, struct connection *conn, node = create_node(conn, ctx, name, NULL, 0); if (!node) return errno; - fire_watches(conn, ctx, name, node, false, NULL); + fire_watches(conn, ctx, name, node, MATCH_SUBTREE, NULL); } send_ack(conn, XS_MKDIR); @@ -1683,7 +1683,7 @@ static int delnode_sub(const void *ctx, struct connection *conn, struct node *node, void *arg) { const char *root = arg; - bool watch_exact; + enum watch_match watch_match; int ret; const char *db_name; @@ -1703,8 +1703,8 @@ static int delnode_sub(const void *ctx, struct connection *conn, * This fine as we are single threaded and the next possible read will * be handled only after the node has been really removed. */ - watch_exact = strcmp(root, node->name); - fire_watches(conn, ctx, node->name, node, watch_exact, NULL); + watch_match = strcmp(root, node->name) ? MATCH_EXACT : MATCH_SUBTREE; + fire_watches(conn, ctx, node->name, node, watch_match, NULL); return WALK_TREE_RM_CHILDENTRY; } @@ -1858,7 +1858,7 @@ static int do_set_perms(const void *ctx, struct connection *conn, if (write_node(conn, node, NODE_MODIFY, false)) return errno; - fire_watches(conn, ctx, name, node, false, &old_perms); + fire_watches(conn, ctx, name, node, MATCH_SUBTREE, &old_perms); send_ack(conn, XS_SET_PERMS); return 0; diff --git a/tools/xenstored/transaction.c b/tools/xenstored/transaction.c index 47cd6ecd3c..ec5b122a3f 100644 --- a/tools/xenstored/transaction.c +++ b/tools/xenstored/transaction.c @@ -134,7 +134,7 @@ struct accessed_node /* Watch event flags. */ bool fire_watch; - bool watch_exact; + enum watch_match watch_match; }; struct transaction @@ -327,8 +327,10 @@ err: * A watch event should be fired for a node modified inside a transaction. * Set the corresponding information. A non-exact event is replacing an exact * one, but not the other way round. + * No special watch handling needed here, so MATCH_DEPTH is no issue. */ -void queue_watches(struct connection *conn, const char *name, bool watch_exact) +void queue_watches(struct connection *conn, const char *name, + enum watch_match watch_match) { struct accessed_node *i; @@ -340,9 +342,9 @@ void queue_watches(struct connection *conn, const char *name, bool watch_exact) if (!i->fire_watch) { i->fire_watch = true; - i->watch_exact = watch_exact; - } else if (!watch_exact) { - i->watch_exact = false; + i->watch_match = watch_match; + } else if (watch_match == MATCH_SUBTREE) { + i->watch_match = MATCH_SUBTREE; } } @@ -419,7 +421,7 @@ static int finalize_transaction(struct connection *conn, db_delete(conn, i->node, NULL); } if (i->fire_watch) - fire_watches(conn, trans, i->node, NULL, i->watch_exact, + fire_watches(conn, trans, i->node, NULL, i->watch_match, i->perms.p ? &i->perms : NULL); list_del(&i->list); diff --git a/tools/xenstored/transaction.h b/tools/xenstored/transaction.h index 90435b4fc9..b4f5f757e2 100644 --- a/tools/xenstored/transaction.h +++ b/tools/xenstored/transaction.h @@ -18,6 +18,7 @@ #ifndef _XENSTORED_TRANSACTION_H #define _XENSTORED_TRANSACTION_H #include "core.h" +#include "watch.h" enum node_access_type { NODE_ACCESS_READ, @@ -44,7 +45,8 @@ int __must_check access_node(struct connection *conn, struct node *node, enum node_access_type type, const char **db_name); /* Queue watches for a modified node. */ -void queue_watches(struct connection *conn, const char *name, bool watch_exact); +void queue_watches(struct connection *conn, const char *name, + enum watch_match watch_match); /* Prepend the transaction to name if appropriate. */ const char *transaction_prepend(struct connection *conn, const char *name); diff --git a/tools/xenstored/watch.c b/tools/xenstored/watch.c index 860c219f29..a9a06e9e48 100644 --- a/tools/xenstored/watch.c +++ b/tools/xenstored/watch.c @@ -128,7 +128,8 @@ static bool watch_permitted(struct connection *conn, const void *ctx, * watch event, too. */ void fire_watches(struct connection *conn, const void *ctx, const char *name, - const struct node *node, bool exact, struct node_perms *perms) + const struct node *node, enum watch_match match, + struct node_perms *perms) { struct connection *i; struct buffered_data *req; @@ -136,7 +137,7 @@ void fire_watches(struct connection *conn, const void *ctx, const char *name, /* During transactions, don't fire watches, but queue them. */ if (conn && conn->transaction) { - queue_watches(conn, name, exact); + queue_watches(conn, name, match); return; } @@ -148,17 +149,34 @@ void fire_watches(struct connection *conn, const void *ctx, const char *name, continue; list_for_each_entry(watch, &i->watches, list) { - if (exact) { - if (streq(name, watch->node)) - send_event(req, i, - get_watch_path(watch, name), - watch->token); - } else { - if (is_child(name, watch->node, watch->depth)) - send_event(req, i, - get_watch_path(watch, name), - watch->token); + bool send = false; + + switch (match) { + case MATCH_EXACT: + send = streq(name, watch->node); + break; + + case MATCH_SUBTREE: + send = is_child(name, watch->node, + watch->depth); + break; + + case MATCH_DEPTH: + send = streq(name, watch->node) || + (watch->depth > 0 && + is_child(name, watch->node, + watch->depth)); + break; + + case MATCH_NODEPTH: + send = streq(name, watch->node) && + watch->depth < 0; + break; } + + if (send) + send_event(req, i, get_watch_path(watch, name), + watch->token); } } } diff --git a/tools/xenstored/watch.h b/tools/xenstored/watch.h index afdfdc6b2f..692343389f 100644 --- a/tools/xenstored/watch.h +++ b/tools/xenstored/watch.h @@ -27,8 +27,15 @@ int do_unwatch(const void *ctx, struct connection *conn, struct buffered_data *in); /* Fire all watches: !exact means all the children are affected (ie. rm). */ +enum watch_match { + MATCH_EXACT, + MATCH_SUBTREE, + MATCH_DEPTH, /* watches with depth > 0, MATCH_SUBTREE semantics */ + MATCH_NODEPTH /* watches with no depth, MATCH_EXACT semantics */ +}; + void fire_watches(struct connection *conn, const void *tmp, const char *name, - const struct node *node, bool exact, + const struct node *node, enum watch_match match, struct node_perms *perms); void conn_delete_all_watches(struct connection *conn); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:42:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:42:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288455.1568754 (Exim 4.92) (envelope-from ) id 1wF5l1-0005T9-4h; Tue, 21 Apr 2026 07:42:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288455.1568754; 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d=suse.com; s=susede1; t=1776757372; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=H4xDwurhkvE0j1k8kqAZ1un0445rmmWmoyaVKvtmHfs=; b=dKdo7mVNbb2833HOzBH8ax9gOs1Nfz18pBlDL0RE+ngF+aWCzA6q6+EgKEM+onCdc5Gh1u nD8I7lGjymPFmGZD6hFZCFYGBCQOwzgS79/CvfEJRTXCXwSIaE2MYgQItIAV0/cCwGgVeG aKubo8f7B28haR3P6H9biqznReHI/rA= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD , Jason Andryuk Subject: [PATCH v2 7/9] tools/xenstored: expand special watch handling with depth feature Date: Tue, 21 Apr 2026 09:42:09 +0200 Message-ID: <20260421074211.308473-8-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; 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} -static void fire_special_watches(const char *name) +#define WATCH_NODOM 1 /* Fire watches without extension. */ +#define WATCH_DOM 2 /* Fire watches with extension. */ +#define WATCH_BOTH (WATCH_NODOM | WATCH_DOM) + +static void fire_special_watches(const char *name, unsigned int domid, + unsigned int watchdom_flag) { void *ctx = talloc_new(NULL); const struct node *node; @@ -626,9 +631,19 @@ static void fire_special_watches(const char *name) node = read_node_const(NULL, ctx, name); - if (node) - fire_watches(NULL, ctx, name, node, true, NULL); - else + if (node) { + if (watchdom_flag & WATCH_NODOM) + fire_watches(NULL, ctx, name, node, MATCH_NODEPTH, + NULL); + if (watchdom_flag & WATCH_DOM) { + char name_dom[24]; /* max. "@introduceDomain/domid" */ + + snprintf(name_dom, sizeof(name_dom), + "%s/%u", name, domid); + fire_watches(NULL, ctx, name_dom, node, MATCH_DEPTH, + NULL); + } + } else log("special node %s not found\n", name); talloc_free(ctx); @@ -653,7 +668,7 @@ static int destroy_domain(void *_domain) if (domain->interface) unmap_interface(domain->domid, domain->interface); - fire_special_watches("@releaseDomain"); + fire_special_watches("@releaseDomain", domain->domid, WATCH_BOTH); wrl_domain_destroy(domain); @@ -681,6 +696,8 @@ static int do_check_domain(struct domain *domain, bool *notify, if ((state & XENMANAGE_GETDOMSTATE_STATE_SHUTDOWN) && !domain->shutdown) { domain->shutdown = true; + fire_special_watches("@releaseDomain", domain->domid, + WATCH_DOM); *notify = true; } if (!(state & XENMANAGE_GETDOMSTATE_STATE_DEAD)) @@ -723,7 +740,7 @@ void check_domains(void) ; if (notify) - fire_special_watches("@releaseDomain"); + fire_special_watches("@releaseDomain", 0, WATCH_NODOM); } static struct domain *find_domain_struct(unsigned int domid) @@ -747,7 +764,7 @@ static void do_check_domains(void) } if (notify) - fire_special_watches("@releaseDomain"); + fire_special_watches("@releaseDomain", 0, WATCH_NODOM); } /* We scan all domains rather than use the information given here. */ @@ -1112,7 +1129,8 @@ static struct domain *introduce_domain(const void *ctx, talloc_steal(domain->conn, domain); if (!is_priv_domain && !restore) - fire_special_watches("@introduceDomain"); + fire_special_watches("@introduceDomain", domid, + WATCH_BOTH); } else { /* Use XS_INTRODUCE for recreating the xenbus event-channel. */ if (domain->port) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:43:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:43:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288466.1568763 (Exim 4.92) (envelope-from ) id 1wF5l6-00060i-GF; Tue, 21 Apr 2026 07:43:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288466.1568763; Tue, 21 Apr 2026 07:43:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5l6-00060a-CI; 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bh=KTqmf1xyf3XOmhzfHM4kVR7INI+guIyweqMv4PH8HFk=; b=B54tmGhihPT2R3BnEz/fgBfKivKnAx6y60GfjxZzdvHY8ctP6GN35d82xvNTEUseq2eglT c1sqUYaBZorDQjjufRuS3et5jApgu/DhmWNMe5JwX67nu0quya46cfI8H7hm8a8XJ0kG1O aFeffKDgdxE7spdX9qc5R37Q9vXl37c= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD , Jason Andryuk Subject: [PATCH v2 8/9] tools/xenstored: make XENSTORE_SERVER_FEATURE_WATCHDEPTH available Date: Tue, 21 Apr 2026 09:42:10 +0200 Message-ID: <20260421074211.308473-9-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; 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Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- tools/xenstored/domain.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index a5258dae6d..00875d6b5c 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -43,7 +43,8 @@ #include #endif -#define XENSTORE_FEATURES XENSTORE_SERVER_FEATURE_ERROR +#define XENSTORE_FEATURES (XENSTORE_SERVER_FEATURE_ERROR | \ + XENSTORE_SERVER_FEATURE_WATCHDEPTH) static xenmanage_handle *xm_handle; xengnttab_handle **xgt_handle; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:43:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:43:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288474.1568772 (Exim 4.92) (envelope-from ) id 1wF5lC-0006aR-Ow; Tue, 21 Apr 2026 07:43:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288474.1568772; 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d=suse.com; s=susede1; t=1776757383; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AZ9uOpSwscCXmBP1ykyoRIThmyiK1apA4EI7JRD8j+A=; b=IdV5N36UKXP0qHpVN6dZ7oBh+lkURsr51AQY0rFjUcfwnp6kWvC+9fE4t2dldDvVJJxQxs Bhr80nK9N8iTISLqK/3vV0tpo8N9yF73kX+7FtMD7J32LBvDFMe8mUsKnwe5aTPx/C6hYX nDmGs9zRUp5LkfAG9HCNLH3hwP2fnQk= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Anthony PERARD , Julien Grall , Jason Andryuk Subject: [PATCH v2 9/9] tools/xs-clients: support depth with xenstore-watch Date: Tue, 21 Apr 2026 09:42:11 +0200 Message-ID: <20260421074211.308473-10-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260421074211.308473-1-jgross@suse.com> References: <20260421074211.308473-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; 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Using "-d" without support of depth by xenstored will refuse to set the watch(es). Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- V2: - add new flag to man page (Jason Andryuk) --- docs/man/xenstore-watch.1.pod | 9 +++++++++ tools/xs-clients/xenstore_client.c | 19 +++++++++++++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/docs/man/xenstore-watch.1.pod b/docs/man/xenstore-watch.1.pod index de28d380b7..716c5521bc 100644 --- a/docs/man/xenstore-watch.1.pod +++ b/docs/man/xenstore-watch.1.pod @@ -17,6 +17,15 @@ event happening. Show the usage information for xenstore-watch and exit the program. +=item B<-d> B + +Limit the number of sub-directories below the specified Is to be +watched. A B of 0 will watch only the specified nodes, a B +of 1 will watch the specified nodes and their direct children, etc. + +Using this option requires xenstored to support the Xenstore watch depth +feature. In case it is not supported, the B<-d> usage will be rejected. + =item B<-n> B Stop waiting after having received B watch events. diff --git a/tools/xs-clients/xenstore_client.c b/tools/xs-clients/xenstore_client.c index 9a25704b91..4a14cb334f 100644 --- a/tools/xs-clients/xenstore_client.c +++ b/tools/xs-clients/xenstore_client.c @@ -445,7 +445,7 @@ do_watch(struct xs_handle *xsh, int max_events) static int perform(enum mode mode, int optind, int argc, char **argv, struct xs_handle *xsh, xs_transaction_t xth, int prefix, int tidy, int upto, int recurse, int nr_watches, - int raw) + int raw, int depth) { switch (mode) { case MODE_ls: @@ -627,8 +627,11 @@ perform(enum mode mode, int optind, int argc, char **argv, struct xs_handle *xsh for (; argv[optind]; optind++) { const char *w = argv[optind]; - if (!xs_watch(xsh, w, w)) + if (depth < 0 && !xs_watch(xsh, w, w)) errx(1, "Unable to add watch on %s\n", w); + if (depth >= 0 && !xs_watch_depth(xsh, w, w, depth)) + errx(1, "Unable to add watch on %s with depth %d\n", w, + depth); } do_watch(xsh, nr_watches); } @@ -676,6 +679,7 @@ main(int argc, char **argv) int nr_watches = -1; int transaction; int raw = 0; + int depth = -1; struct winsize ws; enum mode mode; @@ -709,10 +713,11 @@ main(int argc, char **argv) {"recurse", 0, 0, 'r'}, /* MODE_chmod */ {"number", 1, 0, 'n'}, /* MODE_watch */ {"raw", 0, 0, 'R'}, /* MODE_read || MODE_write */ + {"depth", 1, 0, 'd'}, /* MODE_watch */ {0, 0, 0, 0} }; - c = getopt_long(argc - switch_argv, argv + switch_argv, "hfspturn:R", + c = getopt_long(argc - switch_argv, argv + switch_argv, "hfspturn:Rd:", long_options, &index); if (c == -1) break; @@ -766,6 +771,12 @@ main(int argc, char **argv) else usage(1, mode, switch_argv, argv[0]); break; + case 'd': + if ( mode == MODE_watch ) + depth = atoi(optarg); + else + usage(1, mode, switch_argv, argv[0]); + break; } } @@ -819,7 +830,7 @@ again: errx(1, "couldn't start transaction"); } - ret = perform(mode, optind, argc - switch_argv, argv + switch_argv, xsh, xth, prefix, tidy, upto, recurse, nr_watches, raw); + ret = perform(mode, optind, argc - switch_argv, argv + switch_argv, xsh, xth, prefix, tidy, upto, recurse, nr_watches, raw, depth); if (transaction && !xs_transaction_end(xsh, xth, ret)) { if (ret == 0 && errno == EAGAIN) { -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:55:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:55:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288508.1568780 (Exim 4.92) (envelope-from ) id 1wF5x3-0001NR-Lw; Tue, 21 Apr 2026 07:55:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288508.1568780; Tue, 21 Apr 2026 07:55:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5x3-0001NK-JB; Tue, 21 Apr 2026 07:55:21 +0000 Received: by outflank-mailman (input) for mailman id 1288508; Tue, 21 Apr 2026 07:55:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5x2-0001My-8e for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 07:55:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF5x1-002hqb-9L for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:55:19 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e72d5d-e002-0a2a0a5209dd-0a2a4502eb68-42 for ; Tue, 21 Apr 2026 09:55:19 +0200 Received: from [209.85.221.42] (helo=mail-wr1-f42.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e72d66-af86-0a2a45020019-d155dd2ae0a4-3 for ; Tue, 21 Apr 2026 09:55:19 +0200 Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-43d0deb7ad5so3129030f8f.2 for ; Tue, 21 Apr 2026 00:55:19 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260421074211.308473-1-jgross@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776758119-88ACA161-42DD32EB/0/0 X-purgate-type: clean X-purgate-size: 1330 On 21.04.2026 09:42, Juergen Gross wrote: > In order to reduce excessive number of watch events the watch depth > feature has been defined, allowing the user to limit the number of > node levels below the watched node to cause events. > > This series is implementing this feature for xenstored (including the > PV and PVH stubdom variants). > > Possible users are: > > - xl/libxl: use domid information for the special @introduceDomain and > @releaseDomain watches, which will be available when using depth = 1 > > - xenconsoled, like xl/libxl > > - any PV-device backends watching directories for added devices (no > watch events when any device specific node is modified) > > - any PV-device frontend and backend watching the "state" node of the > other side, in case the other side plays dirty games by building > large sub-trees beneath the "state" node > > Changes in V2: > - some minor stale changes reverted > - last patch covered by the series now, man page updated Is this really everything that changed? I wanted to commit the first two patches from v1, but I had to leave out patch 1 as it didn't apply. Patch 2 I have in pre-push testing already, but as mentioned on Matrix there's a so far unexplained build issue (definitely not related to this series, though). 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1cad9d25-1e34-4a63-ed08-08de9f7b9a67 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2026 07:57:14.1877 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mBKfZ12opV29qaJOOiCyjh31nN+wkmWGe9iwgzyiyKPLh6Rq+y20O4ZtujgbhPGtpOMMiAeePSdvp7dQyq1uQQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMBPR03MB11567 X-purgate-ID: tlsNG-d25034/1776758236-6FD7BCF5-A81FECCC/0/0 X-purgate-type: clean X-purgate-size: 4165 This patch is a preparatory work for adding Region ID support on Renesas R-Car series boards. Add new host bridge op "fixup_bar" that allows platforms to modify BAR addresses before they are mapped. Because x86 don't have support for PCI Host Bridge drivers, add another level of indirection in form of platform_pci_fixup_bar() function, that will call host bridge op on ARM and do nothing on x86. Signed-off-by: Mykyta Poturai --- xen/arch/arm/include/asm/pci.h | 3 +++ xen/arch/arm/include/asm/vpci.h | 9 +++++++++ xen/arch/arm/vpci.c | 12 ++++++++++++ xen/arch/x86/include/asm/vpci.h | 6 ++++++ xen/drivers/vpci/header.c | 2 ++ 5 files changed, 32 insertions(+) diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.= h index 7c3211823f..398a4eb746 100644 --- a/xen/arch/arm/include/asm/pci.h +++ b/xen/arch/arm/include/asm/pci.h @@ -80,6 +80,9 @@ struct pci_ops { void (*init_bus_range)(struct dt_device_node *dev, struct pci_host_bridge *bridge, struct pci_config_window *cfg); + void (*fixup_bar)(struct pci_host_bridge *bridge, + unsigned int bar_num, + paddr_t *addr); }; =20 /* diff --git a/xen/arch/arm/include/asm/vpci.h b/xen/arch/arm/include/asm/vpc= i.h index 0cc6f5a105..f5c817a51c 100644 --- a/xen/arch/arm/include/asm/vpci.h +++ b/xen/arch/arm/include/asm/vpci.h @@ -16,6 +16,10 @@ struct vpci_arch_msix_entry { =20 int domain_vpci_init(struct domain *d); unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d); + +void platform_pci_fixup_bar(const struct pci_dev *pdev, unsigned int bar_n= um, + paddr_t *addr); + #else static inline int domain_vpci_init(struct domain *d) { @@ -26,6 +30,11 @@ static inline unsigned int domain_vpci_get_num_mmio_hand= lers(struct domain *d) { return 0; } + +static inline void platform_pci_fixup_bar(const struct pci_dev *pdev, + unsigned int bar_num, + paddr_t *addr) +{} #endif /* CONFIG_HAS_VPCI */ =20 #endif /* ARM_VPCI_H */ diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c index d41aa383a8..ec6efec22e 100644 --- a/xen/arch/arm/vpci.c +++ b/xen/arch/arm/vpci.c @@ -189,6 +189,18 @@ unsigned int domain_vpci_get_num_mmio_handlers(struct = domain *d) return 1; } =20 +void platform_pci_fixup_bar(const struct pci_dev *pdev, + unsigned int bar_num, + paddr_t *addr) +{ + struct pci_host_bridge *bridge =3D pci_find_host_bridge(pdev->sbdf.seg= , pdev->sbdf.bus); + + if ( bridge->ops->fixup_bar ) + { + bridge->ops->fixup_bar(bridge, bar_num, addr); + } +} + /* * Local variables: * mode: C diff --git a/xen/arch/x86/include/asm/vpci.h b/xen/arch/x86/include/asm/vpc= i.h index c501ff1709..a05b70abbf 100644 --- a/xen/arch/x86/include/asm/vpci.h +++ b/xen/arch/x86/include/asm/vpci.h @@ -16,6 +16,12 @@ struct vpci_arch_msix_entry { int pirq; }; =20 +/* X86 does not require PCI BAR modifications */ +static inline void platform_pci_fixup_bar(const struct pci_dev *pdev, + unsigned int bar_num, + paddr_t *addr) +{} + #endif /* X86_VPCI_H */ =20 /* diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c index a760d8c32f..d89e43354c 100644 --- a/xen/drivers/vpci/header.c +++ b/xen/drivers/vpci/header.c @@ -882,6 +882,8 @@ int vpci_init_header(struct pci_dev *pdev) bars[i].size =3D size; bars[i].prefetchable =3D val & PCI_BASE_ADDRESS_MEM_PREFETCH; =20 + platform_pci_fixup_bar(pdev, i, &bars[i].addr); + rc =3D vpci_add_register(pdev->vpci, is_hwdom ? vpci_hw_read32 : guest_mem_bar_r= ead, is_hwdom ? bar_write : guest_mem_bar_write, --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:57:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:57:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288515.1568790 (Exim 4.92) (envelope-from ) id 1wF5yx-0001u3-0l; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6525d359-4782-4269-596d-08de9f7b9964 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2026 07:57:13.5587 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5QRfrmnKft++ehWsXLRcGhixIbzglZlV0oeBMnlnpr7TOGefnWVkAA8e2E7Bga98Z6z9REt+GwKEr3MStlCXew== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMBPR03MB11567 X-purgate-ID: tlsNG-d25034/1776758236-F6809CF5-358DCFBE/0/0 X-purgate-type: clean X-purgate-size: 1305 On Renesas R-Car platforms, the Region ID (RGID) feature encodes an identifier into the upper bits of the physical address for every CPU memory access. This address manipulations can mostly be done via system and domain congirutaion, but for PCI bar it is not possible as some BARs are 32bit onl= y. This series introduces a platform hook that lets the PCI host bridge driver rewrite BAR addresses at vPCI init time, and provides the R-Car Gen4 implementation that adds the configured RGID into each address. This is sent as RFC to get early feedback on the approach:=20 - Is a pci_ops callback the right place for this kind of address fixup? - Is platform Kconfig a good place for RGID related options or is it better= to put them in some other place. Mykyta Poturai (2): pci: Allow platforms to modify BAR adresses plat/rcar: Add region id support for PCI xen/arch/arm/include/asm/pci.h | 3 +++ xen/arch/arm/include/asm/vpci.h | 9 +++++++++ xen/arch/arm/pci/pci-host-rcar4.c | 15 +++++++++++++++ xen/arch/arm/platforms/Kconfig | 21 +++++++++++++++++++++ xen/arch/arm/vpci.c | 12 ++++++++++++ xen/arch/x86/include/asm/vpci.h | 6 ++++++ xen/drivers/vpci/header.c | 2 ++ 7 files changed, 68 insertions(+) --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 07:57:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 07:57:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288517.1568809 (Exim 4.92) (envelope-from ) id 1wF5yy-0002L1-IJ; Tue, 21 Apr 2026 07:57:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288517.1568809; Tue, 21 Apr 2026 07:57:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF5yy-0002Kr-Ce; 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b=gZ2QMZlR8lbqXMu2T0IVz4CbUMRJkmjhRbC+BDKHy0iVZH6JCY1YHdgRGRnfSOIeDFCYs9g+rP+Wx4eln+B+Wg6hb0qpGAv7mZ2HeHzZP8rBvIpSpRpW5twg8Xmn/gR1guCEbL/2FsWZrwVmtmfilOMJpns1wnYgh7unohvicURn7pLMhVIGv7m1cXng71jGRiihW15iJiE5G6m1yiT0CpgekS06LNBQoVs9KSiWBkFeIurKcifNV5B2t3Qhjib7/qMoG3C/6aovUlssaMQgv+W5A/rnWflkDlGcYq6XAmlND7Xs3gVqtvTZ9ZPjxy1LnazAvvC6ecexNsNy7xkQ8A== From: Mykyta Poturai To: "xen-devel@lists.xenproject.org" CC: Mykyta Poturai , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [RFC PATCH 2/2] plat/rcar: Add region id support for PCI Thread-Topic: [RFC PATCH 2/2] plat/rcar: Add region id support for PCI Thread-Index: AQHc0WR3HLVfDHqP50KPW64J7aGgdQ== Date: Tue, 21 Apr 2026 07:57:14 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PAVPR03MB10102:EE_|AMBPR03MB11567:EE_ x-ms-office365-filtering-correlation-id: a05233a1-9261-48ca-b01a-08de9f7b9aa6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|1800799024|366016|376014|38070700021|56012099003|18002099003|22082099003; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a05233a1-9261-48ca-b01a-08de9f7b9aa6 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2026 07:57:14.6462 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vcyJf0dz23qi9VuCDsNlhniQiWcxt1awaan660WPrAxo0w3KNMhP7dA5Eu+Dnyao1iKsOYIRvZ0idZs3X9Kabg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMBPR03MB11567 X-purgate-ID: tlsNG-d25034/1776758237-6EF72CF5-AE44305C/0/0 X-purgate-type: clean X-purgate-size: 2996 With Region ID enabled, all CPU memory accesses need to have rgid bits set in the physical address. This creates a problem for PCI BAR accesses, as it would require all BARs to be 64bit. Implement fixup_bar callback to add rgid bits to the address before mapping it to the guests. Add Kconfig options to enable region id support and set the rgid value and physical address space size. Signed-off-by: Mykyta Poturai --- xen/arch/arm/pci/pci-host-rcar4.c | 15 +++++++++++++++ xen/arch/arm/platforms/Kconfig | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/xen/arch/arm/pci/pci-host-rcar4.c b/xen/arch/arm/pci/pci-host-= rcar4.c index e1e8eb0ee1..50400c04c4 100644 --- a/xen/arch/arm/pci/pci-host-rcar4.c +++ b/xen/arch/arm/pci/pci-host-rcar4.c @@ -43,6 +43,12 @@ struct rcar4_pcie_priv { DECLARE_BITMAP(osid_regs, NUM_OSID_REGS); }; =20 +#define ULL(X) _AC(X, ULL) +#define MADDR_RGID(a) (ULL(a) << CONFIG_RCAR_PA_BITS) +#define MADDR_PA_MASK ((1ULL << CONFIG_RCAR_PA_BITS) - 1) + +#define MADDR_ENCODE_RGID(a) (MADDR_RGID(CONFIG_RCAR_RGID) | (a)) + /* * PCI host bridges often have different ways to access the root and child * bus config spaces: @@ -61,6 +67,14 @@ static int __init rcar4_child_cfg_reg_index(struct dt_de= vice_node *np) return dt_property_match_string(np, "reg-names", "config"); } =20 +static void rcar4_pcie_fixup_bar(struct pci_host_bridge *bridge, + unsigned int bar_num, + paddr_t *addr) +{ + if ( IS_ENABLED(CONFIG_RCAR_REGION_ID_SUPPORT) ) + *addr =3D MADDR_ENCODE_RGID(*addr); +} + /* ECAM ops */ static const struct pci_ecam_ops rcar4_pcie_ops =3D { .bus_shift =3D 20, @@ -71,6 +85,7 @@ static const struct pci_ecam_ops rcar4_pcie_ops =3D { .write =3D pci_generic_config_write, .need_p2m_hwdom_mapping =3D pci_ecam_need_p2m_hwdom_mapping, .init_bus_range =3D pci_generic_init_bus_range, + .fixup_bar =3D rcar4_pcie_fixup_bar, } }; =20 diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfi= g index 888d0b85d5..db096952c8 100644 --- a/xen/arch/arm/platforms/Kconfig +++ b/xen/arch/arm/platforms/Kconfig @@ -64,6 +64,27 @@ config NO_PLAT =20 endchoice =20 +menu "RCar Region ID Support" + visible if RCAR4 + +config RCAR_REGION_ID_SUPPORT + bool "Renesas Region ID support for R-Car Gen4 platforms" if EXPERT + depends on RCAR4 + help + Enable experimental Region ID support for R-Car Gen4 platforms + +config RCAR_RGID + int "Region ID encoded in physical address" + depends on RCAR_REGION_ID_SUPPORT + default 0 + +config RCAR_PA_BITS + int "Physical address space size" + depends on RCAR_REGION_ID_SUPPORT + default 36 + +endmenu + config ALL64_PLAT bool default (ALL_PLAT && ARM_64) --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:13:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:13:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288555.1568817 (Exim 4.92) (envelope-from ) id 1wF6Eo-0007YD-4P; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM9PR03MB7526.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 99fb0c34-5fb2-48e6-4f1d-08de9f7de2dd X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Apr 2026 08:13:35.8450 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: g15U2TxS674RGqwyp7nZWsUiaf19X6GTl1Y4g/2rrE5+eI+M9KBXgoeG9zsMFJi8q1cEkWCgbDxsxWMyo0miwR/OJX732KwxR+gTMy9nNow= X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR03MB10430 X-purgate-ID: tlsNG-bad1c0/1776759219-41AB6A53-D664EE93/0/0 X-purgate-type: clean X-purgate-size: 1570 Clang 22.x.x or Arm Toolchain for Embedded 22.x.x reports: In file included from arch/arm/tee/ffa.c:75: arch/arm/tee/ffa_private.h:439:17: error: 'used' attribute ignored on a non= -definition declaration [-Werror,-Wignored-attributes] 439 | extern uint32_t __ro_after_init ffa_fw_version; | ^ There is a fix for clang 16 in the git history: a1a1e2b7dc4f ("xen/arm: ffa: fix build with clang") which was broken by the following commit: a90376c6adbc ("xen/arm: ffa: Add FF-A 1.2 endpoint memory access descriptor= s") Remove __ro_after_init from the extern declaration of ffa_fw_version. The attribute is already present on the definition in ffa.c, which is sufficient and correct. Fixes: a90376c6adbc ("xen/arm: ffa: Add FF-A 1.2 endpoint memory access des= criptors") Signed-off-by: Dmytro Prokopchuk --- Test CI pipeline: https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2467446333 --- xen/arch/arm/tee/ffa_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.= h index c291f32b56..e16bc0d83d 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -436,7 +436,7 @@ struct ffa_ctx { }; =20 extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE); -extern uint32_t __ro_after_init ffa_fw_version; +extern uint32_t ffa_fw_version; =20 extern struct list_head ffa_ctx_head; extern rwlock_t ffa_ctx_list_rwlock; --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:15:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:15:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288567.1568826 (Exim 4.92) (envelope-from ) id 1wF6Ge-00087Y-ID; Tue, 21 Apr 2026 08:15:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288567.1568826; Tue, 21 Apr 2026 08:15:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6Ge-00087R-En; Tue, 21 Apr 2026 08:15:36 +0000 Received: by outflank-mailman (input) for mailman id 1288567; Tue, 21 Apr 2026 08:15:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6Gd-00087L-Pf for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:15:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6Gd-00BERw-6M for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:15:35 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e73225-5cb7-0a2a0a5109dd-0a2a450abec0-4 for ; Tue, 21 Apr 2026 10:15:34 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e73226-56b3-0a2a450a0019-d155dd33adbb-3 for ; Tue, 21 Apr 2026 10:15:34 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43cfd832155so2868340f8f.1 for ; Tue, 21 Apr 2026 01:15:34 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776760139-BE460FF4-6463BE8B/0/0 X-purgate-type: clean X-purgate-size: 478 On 21.04.2026 09:57, Mykyta Poturai wrote: > With Region ID enabled, all CPU memory accesses need to have rgid bits > set in the physical address. This creates a problem for PCI BAR > accesses, as it would require all BARs to be 64bit. I don't understand this. CPU accesses of addresses read / derived from BARs can be massaged in any way the OS likes. That doesn't require the BARs to be 64-bit. Are you trying to arrange for RGID to be transparent to guests? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:31:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:31:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288589.1568845 (Exim 4.92) (envelope-from ) id 1wF6WC-0003og-1r; Tue, 21 Apr 2026 08:31:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288589.1568845; Tue, 21 Apr 2026 08:31:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6WB-0003oZ-UB; Tue, 21 Apr 2026 08:31:39 +0000 Received: by outflank-mailman (input) for mailman id 1288589; Tue, 21 Apr 2026 08:31:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6WA-0003oS-74 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:31:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6W9-00DgwI-K0 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:31:37 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e735e0-e002-0a2a0a5209dd-0a2a45049682-24 for ; Tue, 21 Apr 2026 10:31:37 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e735e9-1dec-0a2a45040019-d1558036dde7-3 for ; Tue, 21 Apr 2026 10:31:37 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4891b0786beso17332595e9.1 for ; Tue, 21 Apr 2026 01:31:37 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776760297-2B1663FF-D4C9B6CA/0/0 X-purgate-type: clean X-purgate-size: 2264 On 21.04.2026 09:57, Mykyta Poturai wrote: > This patch is a preparatory work for adding Region ID support on Renesas > R-Car series boards. Add new host bridge op "fixup_bar" that allows > platforms to modify BAR addresses before they are mapped. > > Because x86 don't have support for PCI Host Bridge drivers, add another > level of indirection in form of platform_pci_fixup_bar() function, that > will call host bridge op on ARM and do nothing on x86. > > Signed-off-by: Mykyta Poturai > --- > xen/arch/arm/include/asm/pci.h | 3 +++ > xen/arch/arm/include/asm/vpci.h | 9 +++++++++ > xen/arch/arm/vpci.c | 12 ++++++++++++ > xen/arch/x86/include/asm/vpci.h | 6 ++++++ > xen/drivers/vpci/header.c | 2 ++ > 5 files changed, 32 insertions(+) > > diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.h > index 7c3211823f..398a4eb746 100644 > --- a/xen/arch/arm/include/asm/pci.h > +++ b/xen/arch/arm/include/asm/pci.h > @@ -80,6 +80,9 @@ struct pci_ops { > void (*init_bus_range)(struct dt_device_node *dev, > struct pci_host_bridge *bridge, > struct pci_config_window *cfg); > + void (*fixup_bar)(struct pci_host_bridge *bridge, > + unsigned int bar_num, > + paddr_t *addr); I'm not an Arm maintainer, but if such a hook - used only when a certain CONFIG_* is active, as per patch 2 - was introduced in common or x86 code, I'd ask for the hook to also be conditional. Doing so avoids accidental use without ... > --- a/xen/arch/arm/vpci.c > +++ b/xen/arch/arm/vpci.c > @@ -189,6 +189,18 @@ unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) > return 1; > } > > +void platform_pci_fixup_bar(const struct pci_dev *pdev, > + unsigned int bar_num, > + paddr_t *addr) > +{ > + struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->sbdf.seg, pdev->sbdf.bus); > + > + if ( bridge->ops->fixup_bar ) > + { > + bridge->ops->fixup_bar(bridge, bar_num, addr); > + } ... such a conditional around it. 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Tue, 21 Apr 2026 01:36:20 -0700 (PDT) Message-ID: Date: Tue, 21 Apr 2026 10:36:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/2] include: move KB() etc to macros.h From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <5f299d7a-be1b-4bdb-a10b-37c334606bdf@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5f299d7a-be1b-4bdb-a10b-37c334606bdf@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776760581-6E169CF5-EE00B4F2/0/0 X-purgate-type: clean X-purgate-size: 1125 Allow them to be used by build tools which don't include config.h. (They also don't really fit into config.h, as there's nothing "configuration" related about them.) Signed-off-by: Jan Beulich --- a/xen/arch/x86/efi/relocs-dummy.S +++ b/xen/arch/x86/efi/relocs-dummy.S @@ -1,3 +1,4 @@ +#include .section .reloc, "a", @progbits .balign 4 --- a/xen/include/xen/config.h +++ b/xen/include/xen/config.h @@ -82,10 +82,6 @@ #define __force #define __bitwise -#define KB(_kb) (_AC(_kb, ULL) << 10) -#define MB(_mb) (_AC(_mb, ULL) << 20) -#define GB(_gb) (_AC(_gb, ULL) << 30) - /* allow existing code to work with Kconfig variable */ #define NR_CPUS CONFIG_NR_CPUS --- a/xen/include/xen/macros.h +++ b/xen/include/xen/macros.h @@ -38,6 +38,10 @@ #define __STR(...) #__VA_ARGS__ #define STR(...) __STR(__VA_ARGS__) +#define KB(_kb) (_AC(_kb, ULL) << 10) +#define MB(_mb) (_AC(_mb, ULL) << 20) +#define GB(_gb) (_AC(_gb, ULL) << 30) + #ifndef __ASSEMBLER__ /* Force a compilation error if condition is true */ From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:36:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:36:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288616.1568870 (Exim 4.92) (envelope-from ) id 1wF6bB-0005KZ-2p; Tue, 21 Apr 2026 08:36:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288616.1568870; Tue, 21 Apr 2026 08:36:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6bB-0005KQ-04; Tue, 21 Apr 2026 08:36:49 +0000 Received: by outflank-mailman (input) for mailman id 1288616; Tue, 21 Apr 2026 08:36:48 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6bA-0005J8-3B for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:36:48 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wF6b9-00CeQV-22; Tue, 21 Apr 2026 08:36:47 +0000 Received: from [2a02:8012:3a1:0:3d55:1646:9f87:e5f0] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wF6b9-00DygZ-1L; Tue, 21 Apr 2026 08:36:47 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=3x7ZA5fd2nnuA0ufHxBALV6fxOVywYgqzpL+x6BowS4=; b=37blrnjxrZzjQ66cGJQLvVEPQJ hGt2pTzeFAoOMrbaUh0iuzB7jRSS7/IDYRHD+yuTUWGi5QUVmTJUs+y28oZxLtY7/pAfJzhhVwWma Myi3pH4qgl4HTLqjwqHMwHskLJwfCWXzUjU9ZwIv9ZGMdNzDOA6zp94b91WGAjxfZt80=; Message-ID: <3708372f-c2e9-4d84-89eb-ab9845ac4798@xen.org> Date: Tue, 21 Apr 2026 09:36:45 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 2/2] plat/rcar: Add region id support for PCI To: Mykyta Poturai , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: Content-Language: en-GB From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Mykyta, On 21/04/2026 08:57, Mykyta Poturai wrote: > diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig > index 888d0b85d5..db096952c8 100644 > --- a/xen/arch/arm/platforms/Kconfig > +++ b/xen/arch/arm/platforms/Kconfig > @@ -64,6 +64,27 @@ config NO_PLAT > > endchoice > > +menu "RCar Region ID Support" > + visible if RCAR4 > + > +config RCAR_REGION_ID_SUPPORT > + bool "Renesas Region ID support for R-Car Gen4 platforms" if EXPERT > + depends on RCAR4 > + help > + Enable experimental Region ID support for R-Car Gen4 platforms > + > +config RCAR_RGID > + int "Region ID encoded in physical address" > + depends on RCAR_REGION_ID_SUPPORT > + default 0 > + > +config RCAR_PA_BITS > + int "Physical address space size" > + depends on RCAR_REGION_ID_SUPPORT > + default 36 The 3 configs above implies that the value will change per-board. Is that correct? If so, this should be described in the firmware table so a single Xen binary can boot on all the platforms. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:37:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:37:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288626.1568880 (Exim 4.92) (envelope-from ) id 1wF6be-0005qU-Ac; Tue, 21 Apr 2026 08:37:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288626.1568880; Tue, 21 Apr 2026 08:37:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6be-0005qN-7l; Tue, 21 Apr 2026 08:37:18 +0000 Received: by outflank-mailman (input) for mailman id 1288626; Tue, 21 Apr 2026 08:37:17 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6bd-0005q5-4t for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:37:17 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6bc-00AE0R-HV for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:37:16 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e73738-e002-0a2a0a5209dd-0a2a4508cba6-4 for ; Tue, 21 Apr 2026 10:37:16 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7373c-63b5-0a2a45080019-d1558035d144-3 for ; Tue, 21 Apr 2026 10:37:16 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4891cd41959so19735165e9.3 for ; Tue, 21 Apr 2026 01:37:16 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 21 Apr 2026 01:37:15 -0700 (PDT) Message-ID: <4922ac38-e6d9-439a-a4de-2eafe2569017@suse.com> Date: Tue, 21 Apr 2026 10:37:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/2] x86/mkelf32: use xen/macros.h From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie References: <5f299d7a-be1b-4bdb-a10b-37c334606bdf@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5f299d7a-be1b-4bdb-a10b-37c334606bdf@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776760636-3B97DDB1-E90039A2/0/0 X-purgate-type: clean X-purgate-size: 1003 Avoid open-coding macros we have readily available. Being able to use MB() there might have avoided the flaw corrected by 5416c455f656 ("x86/mkelf32: Actually pad load segment to 2 MiB boundary"). Signed-off-by: Jan Beulich --- a/xen/arch/x86/boot/mkelf32.c +++ b/xen/arch/x86/boot/mkelf32.c @@ -17,7 +17,9 @@ #include #include +#include "../../../include/xen/const.h" #include "../../../include/xen/elfstructs.h" +#include "../../../include/xen/macros.h" #define DYNAMICALLY_FILLED 0 #define RAW_OFFSET 128 @@ -345,7 +347,7 @@ int main(int argc, char **argv) * the Xen image using 2M pages. To avoid running into adjacent non-RAM * regions, pad the segment to the next 2M boundary. */ - mem_siz = ((uint32_t)in64_phdr.p_memsz + (1U << 21) - 1) & (-1U << 21); + mem_siz = ROUNDUP((uint32_t)in64_phdr.p_memsz, MB(2)); note_sz = note_base = offset = 0; if ( num_phdrs > 1 ) From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:43:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:43:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288638.1568888 (Exim 4.92) (envelope-from ) id 1wF6hq-000820-VD; Tue, 21 Apr 2026 08:43:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288638.1568888; Tue, 21 Apr 2026 08:43:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6hq-00081t-SV; Tue, 21 Apr 2026 08:43:42 +0000 Received: by outflank-mailman (input) for mailman id 1288638; Tue, 21 Apr 2026 08:43:41 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6hp-00081n-Sl for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:43:41 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wF6hp-00CeXM-1C; Tue, 21 Apr 2026 08:43:41 +0000 Received: from [2a02:8012:3a1:0:3d55:1646:9f87:e5f0] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wF6hp-00DzCt-0F; Tue, 21 Apr 2026 08:43:41 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=/sWBWZ+VL4Uk1olJf5ck2+T6iicOdc+sknJgATHn+ck=; b=zMN4ueF9nud6cSWqkk02h7R2Vr ZEwUcW0MMA2V3HzPAWuWQkmQPuGWUZTAMkky24H7ST0iSjKwNpzDF9uhsuazyJ3MSAA9mYaWnnoqN OsaPboK5kL7I33ulLkpjiN+1aWinGQd5tAcoQpYhAb8FzIxND9+grC1CrHJ86RynyU9c=; Message-ID: Date: Tue, 21 Apr 2026 09:43:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/23] xen/arm: smmuv3: Add support for stage-1 and nested stage translation Content-Language: en-GB To: Milan Djokic , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk References: <56a7c116-4ecb-4dfc-a7dd-774d53041fe9@xen.org> <87a04781-5765-43b6-8b21-cb993609bd91@epam.com> From: Julien Grall In-Reply-To: <87a04781-5765-43b6-8b21-cb993609bd91@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Milan, On 19/04/2026 18:34, Milan Djokic wrote: > Hi Julien, > > On 4/14/26 04:17, Julien Grall wrote: >> Hi Milan, >> >> On 24/03/2026 07:51, Milan Djokic wrote: >>> From: Rahul Singh >>> >>> Xen SMMUv3 driver only supports stage-2 translation. Add support for >>> Stage-1 translation that is required to support nested stage >>> translation. >>> >>> In true nested mode, both s1_cfg and s2_cfg will coexist. >>> Let's remove the union. When nested stage translation is setup, both >>> s1_cfg and s2_cfg are valid. >>> >>> We introduce a new smmu_domain abort field that will be set >>> upon guest stage-1 configuration passing. If no guest stage-1 >>> config has been attached, it is ignored when writing the STE. >>> >>> arm_smmu_write_strtab_ent() is modified to write both stage >>> fields in the STE and deal with the abort field. >>> >>> Signed-off-by: Rahul Singh >>> Signed-off-by: Milan Djokic >>> --- >>>    xen/drivers/passthrough/arm/smmu-v3.c | 93 ++++++++++++++++++++++ >>> +---- >>>    xen/drivers/passthrough/arm/smmu-v3.h |  9 +++ >>>    2 files changed, 91 insertions(+), 11 deletions(-) >>> >>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/ >>> passthrough/arm/smmu-v3.c >>> index 73cc4ef08f..f9c6837919 100644 >>> --- a/xen/drivers/passthrough/arm/smmu-v3.c >>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c >>> @@ -683,8 +683,10 @@ static void arm_smmu_write_strtab_ent(struct >>> arm_smmu_master *master, u32 sid, >>>         * 3. Update Config, sync >>>         */ >>>        u64 val = le64_to_cpu(dst[0]); >>> -    bool ste_live = false; >>> +    bool s1_live = false, s2_live = false, ste_live = false; >>> +    bool abort, translate = false; >>>        struct arm_smmu_device *smmu = NULL; >>> +    struct arm_smmu_s1_cfg *s1_cfg = NULL; >>>        struct arm_smmu_s2_cfg *s2_cfg = NULL; >>>        struct arm_smmu_domain *smmu_domain = NULL; >>>        struct arm_smmu_cmdq_ent prefetch_cmd = { >>> @@ -699,30 +701,54 @@ static void arm_smmu_write_strtab_ent(struct >>> arm_smmu_master *master, u32 sid, >>>            smmu = master->smmu; >>>        } >>> -    if (smmu_domain) >>> -        s2_cfg = &smmu_domain->s2_cfg; >>> +    if (smmu_domain) { >>> +        switch (smmu_domain->stage) { >>> +        case ARM_SMMU_DOMAIN_NESTED: >>> +            s1_cfg = &smmu_domain->s1_cfg; >>> +            fallthrough; >>> +        case ARM_SMMU_DOMAIN_S2: >>> +            s2_cfg = &smmu_domain->s2_cfg; >>> +            break; >>> +        default: >>> +            break; >>> +        } >>> +        translate = !!s1_cfg || !!s2_cfg; >> >> NIT: translate is a bool. So do you actually need the !!? >> > > No, !! is not necessary here, will fix this. > >>> +    } >>>        if (val & STRTAB_STE_0_V) { >>>            switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { >>>            case STRTAB_STE_0_CFG_BYPASS: >>>                break; >>> +        case STRTAB_STE_0_CFG_S1_TRANS: >>> +            s1_live = true; >>> +            break; >>>            case STRTAB_STE_0_CFG_S2_TRANS: >>> -            ste_live = true; >>> +            s2_live = true; >>> +            break; >>> +        case STRTAB_STE_0_CFG_NESTED: >>> +            s1_live = true; >>> +            s2_live = true; >>>                break; >>>            case STRTAB_STE_0_CFG_ABORT: >>> -            BUG_ON(!disable_bypass); >> >> I am not sure I understand why this was removed. Can you clarify? >> > > Yes. With the stage-1 support, abort is controlled per guest smmu > configuration, so abort state is valid and not controlled by the global > disable_bypass, but with per-config smmu_domain->abort field instead. Are we ok to allow the guest to control the bit? For instance, what does it mean if the guest decide to that no abort is necessary but the region is not mapped in stage-2? [...] > > The original idea was to also allow stage-1-only support. But I'm not > sure if stage-1-only usecase is useful or even valid for Xen.. I will > update the patch series with the missing parts for stage-1-only support, > pointed out by Luca, but the question remains if this is needed at all. > If not, I can revert to original state where stage-2 was always required. By "stage-1 only" support, do you mean Xen would use the stage-1 in replacement of the stage-2? Or do you mean the guest will use the stage-1 page-table and there will be no isolation from Xen? If the former, then I believe the page tables don't have the exact same format. Today, the page-tables are shared between the CPU and IOMMU, so this would need to be duplicated. For now, I am not sure this is worth to do. If the latter, this would require the guest to be directly mapped (i.e. IPA == PA) but it would also open a big hole. So I would want to understand the exact use case first. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:45:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:45:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288650.1568897 (Exim 4.92) (envelope-from ) id 1wF6jv-00009j-DP; Tue, 21 Apr 2026 08:45:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288650.1568897; Tue, 21 Apr 2026 08:45:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6jv-00009c-AY; Tue, 21 Apr 2026 08:45:51 +0000 Received: by outflank-mailman (input) for mailman id 1288650; Tue, 21 Apr 2026 08:45:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6jt-00009W-OI for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:45:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6js-00AFjC-Dj for xen-devel@lists.xenproject.org; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <29ec8e444792caa925ba92cdc406ef8c0b3bd678.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776761863-CE576D75-496E8A33/0/0 X-purgate-type: clean X-purgate-size: 7507 On 10.04.2026 17:54, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/config.h > +++ b/xen/arch/riscv/include/asm/config.h > @@ -151,6 +151,19 @@ > extern unsigned long phys_offset; /* = load_start - XEN_VIRT_START */ > #endif > > +/* > + * KERNEL_LOAD_ADDR_ALIGNMENT is defined based on paragraph of > + * "Kernel location" of boot.rst: > + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location I.e. this is entirely Linux-centric? If so, maybe the patch subject should then reflect this? > --- /dev/null > +++ b/xen/arch/riscv/kernel.c > @@ -0,0 +1,230 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#define IMAGE64_MAGIC_V2 0x05435352 /* Magic number 2, le, "RSC\x05" */ > + > +static void __init place_modules(struct kernel_info *info, paddr_t kernbase, > + paddr_t kernend) > +{ > + const struct boot_module *mod = info->bd.initrd; > + const struct membanks *banks = kernel_info_get_mem_const(info); > + const paddr_t initrd_len = ROUNDUP(mod ? mod->size : 0, > + KERNEL_LOAD_ADDR_ALIGNMENT); > + const paddr_t dtb_len = ROUNDUP(fdt_totalsize(info->fdt), > + KERNEL_LOAD_ADDR_ALIGNMENT); > + const paddr_t modsize = initrd_len + dtb_len; > + int bi; Please can variables used for array indexing be of unsigned types? The use ... > + BUG_ON(modsize < initrd_len); > + > + /* > + * Place modules as high in RAM as possible, scanning banks from > + * last to first so that the end of the last bank is preferred. > + */ > + for ( bi = banks->nr_banks - 1; bi >= 0; bi-- ) ... here can easily be replaced: for ( bi = banks->nr_banks; bi-- > 0; ) Or you could have unsigned int bi = banks->nr_banks; ... while ( bi-- > 0 ) . > + { > + const struct membank *bank = &banks->bank[bi]; > + const paddr_t bank_end = bank->start + bank->size; > + paddr_t modbase; > + > + if ( modsize > bank->size ) > + continue; > + > + modbase = ROUNDDOWN(bank_end - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); > + > + if ( modbase < bank->start ) > + continue; > + > + /* > + * If the kernel resides in this bank, ensure modules do not > + * overlap with it. > + */ > + if ( (kernbase >= bank->start) && (kernbase < bank_end) && > + (modbase < ROUNDUP(kernend, KERNEL_LOAD_ADDR_ALIGNMENT)) && > + (modbase + modsize > kernbase) ) > + continue; Can't this be had with only two comparisons? Same bank or not doesn't really matter - if it's different banks, there'll be no overlap anyway. So all you need here is that the module range doesn't overlap the kernel range, entirely independent of the bank. What is dependent on the bank is that the bank may fit both kernel and module even if there is an overlap as per your current calculation: You may be able to place the module below the kernel if it doesn't fit above. > +static paddr_t __init kernel_image_place(struct kernel_info *info) > +{ > + paddr_t load_addr = INVALID_PADDR; > + uint64_t image_size = info->image.image_size ?: info->image.len; > + const struct membanks *banks = kernel_info_get_mem_const(info); > + unsigned int nr_banks = banks->nr_banks; > + unsigned int bi; > + > + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); > + > + /* > + * At the moment, RISC-V's Linux kernel should be always position > + * independent based on "Per-MMU execution" of boot.rst: > + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution > + * > + * But just for the case when RISC-V's Linux kernel isn't position > + * independent it is needed to take load address from > + * info->image.start. > + * > + * If `start` is zero, the Image is position independent. > + */ > + if ( likely(!info->image.start) ) > + { > + for ( bi = 0; bi != nr_banks; bi++ ) > + { > + const struct membank *bank = &banks->bank[bi]; > + paddr_t bank_start = bank->start; > + /* > + * According to boot.rst kernel load address should be properly > + * aligned: > + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location > + * > + * As Image in this case is PIC we can ignore > + * info->image.text_offset. > + */ > + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); > + paddr_t bank_end = bank_start + bank->size; > + paddr_t bank_size; > + > + if ( aligned_start > bank_end ) > + continue; > + > + bank_size = bank_end - aligned_start; > + > + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); > + > + if ( image_size <= bank_size ) > + { > + load_addr = aligned_start; > + break; > + } > + } > + } > + else > + { > + load_addr = info->image.start + info->image.text_offset; Why does stuff ahead of text_offset not need loading? > + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); > + > + for ( bi = 0; bi != nr_banks; bi++ ) > + { > + const struct membank *bank = &banks->bank[bi]; > + paddr_t bank_start = bank->start; > + paddr_t bank_end = bank_start + bank->size; > + > + if ( (load_addr >= bank_start) && (load_addr < bank_end) && > + (bank_end - load_addr) >= image_size ) Do we have to fear overflow? (If so, shouldn't such an image be rejected rather than an attempt being made to place it?) If not, simply: if ( (load_addr >= bank_start) && (load_addr + image_size <= bank_end) ) Also, does image_size really only cover space starting from .text_offset, rather than from .start? > +static void __init kernel_image_load(struct kernel_info *info) > +{ > + int rc; > + paddr_t load_addr = kernel_image_place(info); > + paddr_t paddr = info->image.kernel_addr; > + paddr_t len = info->image.len; > + paddr_t effective_size = info->image.image_size ?: len; > + void *kernel; > + > + place_modules(info, load_addr, load_addr + effective_size); > + > + printk("Loading Image from %"PRIpaddr" to %"PRIpaddr"-%"PRIpaddr"\n", > + paddr, load_addr, load_addr + effective_size); As on earlier occasions: Please represent ranges as mathematical ones, to disambiguate whether the bounds (the upper one in particular) are inclusive or exclusive. > +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, > + paddr_t size) > +{ > +#ifdef CONFIG_RISCV_64 > + return kernel_image64_probe(info, addr, size); > +#else > + return -EOPNOTSUPP; Better #error, as you have it elsewhere (iirc)? Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 21 08:59:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 08:59:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288677.1568915 (Exim 4.92) (envelope-from ) id 1wF6xO-0003OW-Po; Tue, 21 Apr 2026 08:59:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288677.1568915; Tue, 21 Apr 2026 08:59:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6xO-0003OP-Mu; Tue, 21 Apr 2026 08:59:46 +0000 Received: by outflank-mailman (input) for mailman id 1288677; Tue, 21 Apr 2026 08:59:46 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6xO-0003OJ-6c for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 08:59:46 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wF6xN-00Ceo1-2K; Tue, 21 Apr 2026 08:59:45 +0000 Received: from [2a02:8012:3a1:0:3d55:1646:9f87:e5f0] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wF6xN-00Dzpz-1m; Tue, 21 Apr 2026 08:59:45 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=vjimEAhbBkA6s9fQAKUpjTLlnUsV5+OSt4H8OMfVmgo=; b=0NPx11DVzlphuB4w22xLpS18Qg dSd1UbAC+jdKvOArWYBHIp+2DAoQ9/XW+68oBdciWI+eftdwtPM3OyKhudncCScaLEjNZ6sRxQFIT VpkUBERs2L1hDyUKnAr8MTijq1+KfKLxyqbPT3M8QYR2DfCeOC8MUFdGmcvj5koCR/+U=; Message-ID: Date: Tue, 21 Apr 2026 09:59:43 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm64: flushtlb: Optimize ARM64_WORKAROUND_REPEAT_TLBI Content-Language: en-GB To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Mark.Rutland@arm.com References: <20260414081124.48741-1-michal.orzel@amd.com> From: Julien Grall In-Reply-To: <20260414081124.48741-1-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 14/04/2026 09:11, Michal Orzel wrote: > Rework the workaround logic as follows: > - add TLB_HELPER_LOCAL() to be used for local TLB ops without a > workaround, > - modify TLB_HELPER() workaround to use tlbi vale2is, xzr as a second > TLB, > - drop TLB_HELPER_VA(). It's used only by __flush_xen_tlb_one_local > which is local and does not need workaround and by > __flush_xen_tlb_one. In the latter case, since it's used in a loop, > we don't need a workaround in the middle. Add __tlb_repeat_sync with > a workaround to be used at the end after DSB and before final ISB, > - TLBI VALE2IS passing XZR is used as an additional TLBI. While there is > an identity mapping there, it's used very rarely. The performance > impact is therefore negligible. If things change in the future, we > can revisit the decision. Can you document the use of 0 in arch/arm/include/asm/mmu/layout.h as well? > > Signed-off-by: Michal Orzel Reviewed-by: Julien Grall Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 21 09:01:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 09:01:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288689.1568925 (Exim 4.92) (envelope-from ) id 1wF6zW-0004tP-63; Tue, 21 Apr 2026 09:01:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288689.1568925; Tue, 21 Apr 2026 09:01:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6zW-0004tI-3K; Tue, 21 Apr 2026 09:01:58 +0000 Received: by outflank-mailman (input) for mailman id 1288689; Tue, 21 Apr 2026 09:01:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6zU-0004tC-Tw for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:01:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6zU-00AJv4-AY for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:01:56 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e73d04-e002-0a2a0a5209dd-0a2a4509d0de-0 for ; Tue, 21 Apr 2026 11:01:56 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e73d04-2497-0a2a45090019-d1558034d908-3 for ; Tue, 21 Apr 2026 11:01:56 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4852b81c73aso33841305e9.3 for ; Tue, 21 Apr 2026 02:01:56 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <29ec8e444792caa925ba92cdc406ef8c0b3bd678.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776762116-414B1A53-9152CC60/0/0 X-purgate-type: clean X-purgate-size: 2066 On 10.04.2026 17:54, Oleksii Kurochko wrote: > +/* Check if the image is a 64-bit Image */ > +static int __init kernel_image64_probe(struct kernel_info *info, > + paddr_t addr, paddr_t size) > +{ > + /* riscv/boot-image-header.rst */ Is this meant to refer to Linux'es Documentation/arch/riscv/boot-image-header.rst? This needs making unambiguous. Jan > + struct { > + uint32_t code0; /* Executable code */ > + uint32_t code1; /* Executable code */ > + uint64_t text_offset; /* Image load offset, little endian */ > + uint64_t image_size; /* Effective Image size, little endian */ > + uint64_t flags; /* kernel flags, little endian */ > + uint32_t version; /* Version of this header */ > + uint32_t res1; /* Reserved */ > + uint64_t res2; /* Reserved */ > + uint64_t magic; /* Deprecated: Magic number, little endian, "RISCV" */ > + uint32_t magic2; /* Magic number 2, little endian, "RSC\x05" */ > + uint32_t res3; /* Reserved for PE COFF offset */ > + } image; > + uint64_t effective_size; > + > + if ( size < sizeof(image) ) > + return -EINVAL; > + > + copy_from_paddr(&image, addr, sizeof(image)); > + > + /* Magic v1 is deprecated and may be removed. Only use v2 */ > + if ( le32_to_cpu(image.magic2) != IMAGE64_MAGIC_V2 ) > + return -EINVAL; > + > + effective_size = le64_to_cpu(image.image_size); > + > + if ( effective_size && size > effective_size ) > + return -EINVAL; > + > + info->image.kernel_addr = addr; > + /* Actual size in the binary file */ > + info->image.len = size; > + /* Total memory the kernel occupies at runtime */ > + info->image.image_size = effective_size; > + info->image.text_offset = le64_to_cpu(image.text_offset); > + info->image.start = 0; > + > + info->load = kernel_image_load; > + > + return 0; > +} From xen-devel-bounces@lists.xenproject.org Tue Apr 21 09:02:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 09:02:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288691.1568934 (Exim 4.92) (envelope-from ) id 1wF6zb-00058Z-HL; Tue, 21 Apr 2026 09:02:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288691.1568934; Tue, 21 Apr 2026 09:02:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF6zb-00058S-EI; Tue, 21 Apr 2026 09:02:03 +0000 Received: by outflank-mailman (input) for mailman id 1288691; Tue, 21 Apr 2026 09:02:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF6za-00057s-4K for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:02:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF6zZ-002zaS-Gj for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:02:01 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e73d04-2eae-0a2a0a5409dd-0a2a4504c5f4-6 for ; Tue, 21 Apr 2026 11:02:01 +0200 Received: from [209.85.167.43] (helo=mail-lf1-f43.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e73d05-1dec-0a2a45040019-d155a72bd876-3 for ; Tue, 21 Apr 2026 11:01:57 +0200 Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-5a525aedb24so2119298e87.2 for ; Tue, 21 Apr 2026 02:01:57 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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But this will cause a build issue in 64-bit builds. csr_write64(CSR_STIMECMP, ...) └─ __csr_write32h(csr, _v) ← csr is NOT ##-adjacent here so preprocessor expands it FIRST CSR_STIMECMP → 0x14D └─ (void)csr ## H ← csr is already 0x14D here 0x14D ## H → 0x14DH ERROR Probably, it would be better to do in the following way: #ifdef CONFIG_RISCV_32 #define csr_write64(csr, val) \ ({ \ uint64_t v_ = (val); \ csr_write(csr, v_); \ csr_write(csr ## H, v_ >> 32); \ }) #else #define csr_write64(csr, val) \ ({ \ uint64_t v_ = (val); \ csr_write(csr, v_); \ }) #endif Am I missing something? > > Apart from this, no matter that it was Andrew to suggest this, I'd like to > (once again) point out that identifiers starting with two underscores are > reserved. I don't see why a single underscore wouldn't do here. Or > alternatively csr__write32h(). I will apply your suggestion. > >> @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) >> return sbi_err_map_xen_errno(ret.error); >> } >> >> -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; >> - >> int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, >> size_t size) >> { >> @@ -360,10 +378,9 @@ int __init sbi_init(void) >> } >> >> if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) >> - { >> - sbi_set_timer = sbi_set_timer_v02; >> - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); >> - } >> + set_xen_timer = sbi_set_timer_v02; >> + else >> + set_xen_timer = sbi_set_timer_v01; >> } > > Sadly this isn't quite equivalent to sbi_set_timer having had an initializer. > I would have wanted to suggest to use a constructor function, but we call > init_constructors() even later than do_initcalls() on both Arm and x86 (we > don't call the latter at all on RISC-V so far). Might it be necessary to > introduce sbi_early_init(), called very early during boot? Else how do you > guarantee no accidental use of the variable before it is first set? I thought about an introduction of sbi_early_init() but then decided that set_xen_timer() won't be used earlier than at lest timer_init() + local_irq_enable(). Also, sbi_init() is executed pretty early. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1776762652-ADB68C48-3717CC09/0/0 X-purgate-type: clean X-purgate-size: 3707 On 21.04.2026 11:01, Oleksii Kurochko wrote: > On 4/20/26 9:56 AM, Jan Beulich wrote: >> On 17.04.2026 09:24, Oleksii Kurochko wrote: >>> --- a/xen/arch/riscv/include/asm/csr.h >>> +++ b/xen/arch/riscv/include/asm/csr.h >>> @@ -32,6 +32,20 @@ >>> : "memory" ); \ >>> }) >>> >>> +#ifdef CONFIG_RISCV_32 >>> +# define __csr_write32h(csr, val) csr_write(csr ## H, (val) >> 32) In my reply I followed this. If this compiled, then ... >>> +#else >>> +# define __csr_write32h(csr, val) ((void)(csr), (void)(val)) >> >> In order to be able to spot issues in 64-bit builds, how about >> >> # define __csr_write32h(csr, val) ((void)csr ## H, (void)(val)) >> >> ? ... aiui this would compile as well. Looks like the RV32 case then is in need of adjustment as well. > But this will cause a build issue in 64-bit builds. > > csr_write64(CSR_STIMECMP, ...) > └─ __csr_write32h(csr, _v) ← csr is NOT ##-adjacent here > so preprocessor expands it FIRST > CSR_STIMECMP → 0x14D > └─ (void)csr ## H ← csr is already 0x14D here > 0x14D ## H → 0x14DH ERROR > > Probably, it would be better to do in the following way: > > #ifdef CONFIG_RISCV_32 > #define csr_write64(csr, val) \ > ({ \ > uint64_t v_ = (val); \ > csr_write(csr, v_); \ > csr_write(csr ## H, v_ >> 32); \ > }) > #else > #define csr_write64(csr, val) \ > ({ \ > uint64_t v_ = (val); \ > csr_write(csr, v_); \ > }) > #endif E.g. like this, albeit in the RV64 case the local v_ isn't needed. Instead, again to be able to spot issues in RV64 builds, (void)csr ## H may want adding. A clear downside to all of this is that this helper can only be used with CSR_* constants, not with runtime-calculated CSR numbers. >>> @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) >>> return sbi_err_map_xen_errno(ret.error); >>> } >>> >>> -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; >>> - >>> int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, >>> size_t size) >>> { >>> @@ -360,10 +378,9 @@ int __init sbi_init(void) >>> } >>> >>> if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) >>> - { >>> - sbi_set_timer = sbi_set_timer_v02; >>> - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); >>> - } >>> + set_xen_timer = sbi_set_timer_v02; >>> + else >>> + set_xen_timer = sbi_set_timer_v01; >>> } >> >> Sadly this isn't quite equivalent to sbi_set_timer having had an initializer. >> I would have wanted to suggest to use a constructor function, but we call >> init_constructors() even later than do_initcalls() on both Arm and x86 (we >> don't call the latter at all on RISC-V so far). Might it be necessary to >> introduce sbi_early_init(), called very early during boot? Else how do you >> guarantee no accidental use of the variable before it is first set? > > I thought about an introduction of sbi_early_init() but then decided > that set_xen_timer() won't be used earlier than at lest timer_init() + > local_irq_enable(). > Also, sbi_init() is executed pretty early. Many more additions to setup.c are to be expected. Are you sure hardly any will go ahead of the call to sbi_init()? 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776763211-E2B68443-8D69B6B3/0/0 X-purgate-type: clean X-purgate-size: 1256 On 10.04.2026 17:54, Oleksii Kurochko wrote: > --- /dev/null > +++ b/xen/include/xen/domain-layout.h > @@ -0,0 +1,28 @@ > +#ifndef __XEN_DOMAIN_LAYOUT_H__ > +#define __XEN_DOMAIN_LAYOUT_H__ > + > +#include > +#include > +#include > + > +/* > + * Is a domain using the host memory layout? > + * > + * domain_use_host_layout() is always False for PV guests. > + * > + * Direct-mapped domains (autotranslated domains with memory allocated > + * contiguously and mapped 1:1 so that GFN == MFN) are always using the > + * host memory layout to avoid address clashes. What is "to avoid address clashes" about? If GFN == MFN, how could there be clashes? > + * The hardware domain will use the host layout (regardless of > + * direct-mapped) because some OS may rely on specific address ranges > + * for the devices. PV Dom0, like any other PV guests, has > + * domain_use_host_layout() returning False. This last sentence is somewhat redundant and somewhat in conflict with what is said further up. If you did s/guests/domains (including Dom0)/ there, imo this sentence would best be dropped from down here. With these adjustments: Acked-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 21 09:33:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 09:33:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288728.1568961 (Exim 4.92) (envelope-from ) id 1wF7UD-0003Pk-6q; Tue, 21 Apr 2026 09:33:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288728.1568961; Tue, 21 Apr 2026 09:33:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF7UD-0003Pd-3q; Tue, 21 Apr 2026 09:33:41 +0000 Received: by outflank-mailman (input) for mailman id 1288728; Tue, 21 Apr 2026 09:33:39 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF7UB-0003PV-Oi for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:33:39 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF7UB-0034d9-5V for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:33:39 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7446f-5cb7-0a2a0a5109dd-0a2a450b8fe6-16 for ; Tue, 21 Apr 2026 11:33:39 +0200 Received: from [209.85.167.47] (helo=mail-lf1-f47.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e74472-212f-0a2a450b0019-d155a72fa9a7-3 for ; Tue, 21 Apr 2026 11:33:39 +0200 Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5a413f83226so4508397e87.1 for ; Tue, 21 Apr 2026 02:33:38 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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If this compiled, then ... > >>>> +#else >>>> +# define __csr_write32h(csr, val) ((void)(csr), (void)(val)) >>> >>> In order to be able to spot issues in 64-bit builds, how about >>> >>> # define __csr_write32h(csr, val) ((void)csr ## H, (void)(val)) >>> >>> ? > > ... aiui this would compile as well. Looks like the RV32 case then is in > need of adjustment as well. > >> But this will cause a build issue in 64-bit builds. >> >> csr_write64(CSR_STIMECMP, ...) >> └─ __csr_write32h(csr, _v) ← csr is NOT ##-adjacent here >> so preprocessor expands it FIRST >> CSR_STIMECMP → 0x14D >> └─ (void)csr ## H ← csr is already 0x14D here >> 0x14D ## H → 0x14DH ERROR >> >> Probably, it would be better to do in the following way: >> >> #ifdef CONFIG_RISCV_32 >> #define csr_write64(csr, val) \ >> ({ \ >> uint64_t v_ = (val); \ >> csr_write(csr, v_); \ >> csr_write(csr ## H, v_ >> 32); \ >> }) >> #else >> #define csr_write64(csr, val) \ >> ({ \ >> uint64_t v_ = (val); \ >> csr_write(csr, v_); \ >> }) >> #endif > > E.g. like this, albeit in the RV64 case the local v_ isn't needed. Instead, > again to be able to spot issues in RV64 builds, (void)csr ## H may want > adding. > > A clear downside to all of this is that this helper can only be used with > CSR_* constants, not with runtime-calculated CSR numbers. Yes, but it isn't critical downside as I don't see cases where it will be useful to have runtime-calculated CSR numbers. > >>>> @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) >>>> return sbi_err_map_xen_errno(ret.error); >>>> } >>>> >>>> -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; >>>> - >>>> int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, >>>> size_t size) >>>> { >>>> @@ -360,10 +378,9 @@ int __init sbi_init(void) >>>> } >>>> >>>> if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) >>>> - { >>>> - sbi_set_timer = sbi_set_timer_v02; >>>> - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); >>>> - } >>>> + set_xen_timer = sbi_set_timer_v02; >>>> + else >>>> + set_xen_timer = sbi_set_timer_v01; >>>> } >>> >>> Sadly this isn't quite equivalent to sbi_set_timer having had an initializer. >>> I would have wanted to suggest to use a constructor function, but we call >>> init_constructors() even later than do_initcalls() on both Arm and x86 (we >>> don't call the latter at all on RISC-V so far). Might it be necessary to >>> introduce sbi_early_init(), called very early during boot? Else how do you >>> guarantee no accidental use of the variable before it is first set? >> >> I thought about an introduction of sbi_early_init() but then decided >> that set_xen_timer() won't be used earlier than at lest timer_init() + >> local_irq_enable(). >> Also, sbi_init() is executed pretty early. > > Many more additions to setup.c are to be expected. Are you sure hardly any will > go ahead of the call to sbi_init()? Looking at the current state, I don't see something new what will added before sbi_init() except percpu_init_areas(). I am okay to introduce sbi_early_init() if it will be really better: --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -387,3 +387,8 @@ int __init sbi_init(void) return 0; } + +void __init sbi_early_init(void) +{ + set_xen_timer = sbi_set_timer_v01; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 56a0907a855f..b187a84cd28d 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -78,6 +78,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, const char *cmdline; size_t fdt_size; + sbi_early_init(); But it looks to me that is fine to have what we have now as even someone will try to use set_xen_timer earlier a trap will occur and thereby it will be need to put the code which start to use set_xen_timer after sbi_init(). Best regards, Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 09:39:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 09:39:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288739.1568969 (Exim 4.92) (envelope-from ) id 1wF7ZZ-0004Tu-SU; Tue, 21 Apr 2026 09:39:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288739.1568969; Tue, 21 Apr 2026 09:39:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF7ZZ-0004Tn-Oz; Tue, 21 Apr 2026 09:39:13 +0000 Received: by outflank-mailman (input) for mailman id 1288739; Tue, 21 Apr 2026 09:39:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF7ZY-0004Th-D3 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 09:39:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF7ZX-00DxJe-Ln for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:39:11 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e745b4-5cb7-0a2a0a5109dd-0a2a4509b10e-38 for ; Tue, 21 Apr 2026 11:39:11 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e745bf-2497-0a2a45090019-d155802cc9ae-3 for ; Tue, 21 Apr 2026 11:39:11 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so27910155e9.3 for ; Tue, 21 Apr 2026 02:39:11 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776764351-498B7A53-18EA1A27/0/0 X-purgate-type: clean X-purgate-size: 3544 On 10.04.2026 17:54, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/p2m.c > +++ b/xen/arch/riscv/p2m.c > @@ -45,12 +45,27 @@ struct p2m_pte_ctx { > unsigned int level; /* Paging level at which the PTE resides. */ > }; > > -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { > - .mode = HGATP_MODE_OFF, > - .paging_levels = 0, > - .name = "Bare", > +/* Values should be sorted by ->mode in this array */ > +static const struct gstage_mode_desc modes[] = { As before, I'm of the clear opinion that this is too generic an identifier for use at file scope. > @@ -331,8 +324,40 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m) > return 0; > } > > -int p2m_init(struct domain *d) > +static const struct gstage_mode_desc * find_gstage_mode(const char *mmu_type) Nit (style): Stray blank after *. > { > + for ( unsigned int mode_idx = 0; mode_idx < ARRAY_SIZE(modes); mode_idx++ ) Can't the variable be just idx or even i? Would likely help readability some. > + { > + if ( !strcasecmp(mmu_type, modes[mode_idx].name) ) > + { > + if ( modes[mode_idx].mode == HGATP_MODE_OFF || Instead of this, start the loop at index 1, with ... > + modes[mode_idx].mode > max_gstage_mode->mode ) > + break; > + > + return &modes[mode_idx]; > + } > + } > + > + ASSERT(modes[0].mode == HGATP_MODE_OFF); ... this moved up? > + dprintk(XENLOG_ERR, "Requested G-stage mode (%s) isn't supported\n", > + mmu_type); > + > + /* > + * Return the Bare-mode sentinel. p2m_init() will reject it with > + * -EINVAL, producing the appropriate domain-creation failure. > + */ > + return &modes[0]; > +} Yet better return NULL on error? > +int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) > +{ > + /* > + * TODO: This static is a temporary constraint: all guests must use the > + * same MMU mode because p2m_gpa_bits is not yet per-domain. > + * Drop this once per-domain p2m_gpa_bits is introduced. > + */ > + static const struct gstage_mode_desc *m = &modes[0]; It being temporary it may not matter much, but couldn't this be __ro_after_init?` At least one domain needs creating during boot, so ... > @@ -341,6 +366,27 @@ int p2m_init(struct domain *d) > */ > p2m->domain = d; > > + if ( !config ) > + { > + dprintk(XENLOG_ERR, "NULL config is passed\n"); > + return -EINVAL; > + } > + > + p2m->mode = find_gstage_mode(config->arch.gstage_mode); > + > + if ( p2m->mode->mode == HGATP_MODE_OFF ) > + return -EINVAL; > + > + if ( m->mode == HGATP_MODE_OFF ) > + m = p2m->mode; ... this path won't be taken post-init. > --- a/xen/include/public/arch-riscv.h > +++ b/xen/include/public/arch-riscv.h > @@ -56,6 +56,11 @@ typedef struct vcpu_guest_context vcpu_guest_context_t; > DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); > > struct xen_arch_domainconfig { > + /* > + * G-stage MMU mode for the guest (e.g. "sv39", "sv48", "sv57"). > + * Must be set; an empty string is invalid. > + */ > + char gstage_mode[8]; > }; I have to say that I find it odd to use a string literal for this purpose. Specifying the number of wanted address bits would feel more natural. Plus the strings named aren't valid G-stage modes afaict - they lack the x4. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8f93b170-da98-4105-ba83-a0f8421e672b@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776764601-F7612CF5-46202B35/0/0 X-purgate-type: clean X-purgate-size: 2998 On 21.04.2026 11:33, Oleksii Kurochko wrote: > On 4/21/26 11:10 AM, Jan Beulich wrote: >> On 21.04.2026 11:01, Oleksii Kurochko wrote: >>> On 4/20/26 9:56 AM, Jan Beulich wrote: >>>> On 17.04.2026 09:24, Oleksii Kurochko wrote: >>>>> @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) >>>>> return sbi_err_map_xen_errno(ret.error); >>>>> } >>>>> >>>>> -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; >>>>> - >>>>> int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, >>>>> size_t size) >>>>> { >>>>> @@ -360,10 +378,9 @@ int __init sbi_init(void) >>>>> } >>>>> >>>>> if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) >>>>> - { >>>>> - sbi_set_timer = sbi_set_timer_v02; >>>>> - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); >>>>> - } >>>>> + set_xen_timer = sbi_set_timer_v02; >>>>> + else >>>>> + set_xen_timer = sbi_set_timer_v01; >>>>> } >>>> >>>> Sadly this isn't quite equivalent to sbi_set_timer having had an initializer. >>>> I would have wanted to suggest to use a constructor function, but we call >>>> init_constructors() even later than do_initcalls() on both Arm and x86 (we >>>> don't call the latter at all on RISC-V so far). Might it be necessary to >>>> introduce sbi_early_init(), called very early during boot? Else how do you >>>> guarantee no accidental use of the variable before it is first set? >>> >>> I thought about an introduction of sbi_early_init() but then decided >>> that set_xen_timer() won't be used earlier than at lest timer_init() + >>> local_irq_enable(). >>> Also, sbi_init() is executed pretty early. >> >> Many more additions to setup.c are to be expected. Are you sure hardly any will >> go ahead of the call to sbi_init()? > > Looking at the current state, I don't see something new what will added > before sbi_init() except percpu_init_areas(). > > I am okay to introduce sbi_early_init() if it will be really better: > > --- a/xen/arch/riscv/sbi.c > +++ b/xen/arch/riscv/sbi.c > @@ -387,3 +387,8 @@ int __init sbi_init(void) > > return 0; > } > + > +void __init sbi_early_init(void) > +{ > + set_xen_timer = sbi_set_timer_v01; > +} > diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c > index 56a0907a855f..b187a84cd28d 100644 > --- a/xen/arch/riscv/setup.c > +++ b/xen/arch/riscv/setup.c > @@ -78,6 +78,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, > const char *cmdline; > size_t fdt_size; > > + sbi_early_init(); > > But it looks to me that is fine to have what we have now as even someone > will try to use set_xen_timer earlier a trap will occur and thereby it > will be need to put the code which start to use set_xen_timer after > sbi_init(). It's your call really. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <87d8050f252fb76e241a40809763e60d9874e902.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <29c2a896-59b4-4804-ade4-362f65ffadfc@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776765872-E1DDB443-7DD972EB/0/0 X-purgate-type: clean X-purgate-size: 2358 On 16.04.2026 16:32, Jan Beulich wrote: > What c4f427ec879e ("xen: Swap order of actions in the FREE*() macros") did > should have been done right away when XVFREE() was introduced. > > Amends: 9102fcd9579f ("mm: introduce xvmalloc() et al and use for grant table allocations") > Signed-off-by: Jan Beulich On Arm64, and only for alpine-3.18-gcc-debug-arm64-boot-cpupools, this reproducibly causes: diff -u ./.xen-syms.1.o.sym ./.xen-syms.2.o.sym --- ./.xen-syms.1.o.sym +++ ./.xen-syms.2.o.sym @@ -7,11 +7,11 @@ 0000000000000000 l d .bss 0000000000000000 .bss 0000000000000000 l d .rodata 0000000000000000 .rodata 0000000000000000 l d .note.GNU-stack 0000000000000000 .note.GNU-stack -0000000000000000 g O .rodata 0000000000004dd8 .hidden symbols_addresses -0000000000004dd8 g O .rodata 0000000000000004 .hidden symbols_num_addrs -0000000000004ddc g O .rodata 0000000000007721 .hidden symbols_names -000000000000c500 g O .rodata 0000000000000028 .hidden symbols_markers -000000000000c528 g O .rodata 00000000000003b5 .hidden symbols_token_table -000000000000c8de g O .rodata 0000000000000200 .hidden symbols_token_index +0000000000000000 g O .rodata 0000000000004de8 .hidden symbols_addresses +0000000000004de8 g O .rodata 0000000000000004 .hidden symbols_num_addrs +0000000000004dec g O .rodata 0000000000007749 .hidden symbols_names +000000000000c538 g O .rodata 0000000000000028 .hidden symbols_markers +000000000000c560 g O .rodata 00000000000003b5 .hidden symbols_token_table +000000000000c916 g O .rodata 0000000000000200 .hidden symbols_token_index There are only two uses of XVFREE() in code that is built for Arm. I'll see if I can repro locally with the exact same .config, but I fear my chances are slim. It feels wrong to push the patch nevertheless, but it also feels wrong to have to keep it out. Jan > --- a/xen/include/xen/xvmalloc.h > +++ b/xen/include/xen/xvmalloc.h > @@ -71,8 +71,9 @@ void *_xvrealloc(void *va, size_t size, > > /* Free an allocation, and zero the pointer to it. */ > #define XVFREE(p) do { \ > - xvfree(p); \ > + void *_ptr_ = (p); \ > (p) = NULL; \ > + xvfree(_ptr_); \ > } while ( false ) > > static inline void *_xvmalloc_array( From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:19:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:19:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288781.1569022 (Exim 4.92) (envelope-from ) id 1wF8C2-00045k-Gi; Tue, 21 Apr 2026 10:18:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288781.1569022; Tue, 21 Apr 2026 10:18:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8C2-00045d-Da; Tue, 21 Apr 2026 10:18:58 +0000 Received: by outflank-mailman (input) for mailman id 1288781; Tue, 21 Apr 2026 10:18:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF8C1-00045V-19 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:18:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8Bz-00E6S9-S2 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 12:18:55 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e74f08-e002-0a2a0a5209dd-0a2a4506a582-26 for ; Tue, 21 Apr 2026 12:18:55 +0200 Received: from [209.85.167.44] (helo=mail-lf1-f44.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e74f0f-7371-0a2a45060019-d155a72ca5f1-3 for ; Tue, 21 Apr 2026 12:18:55 +0200 Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-5a415fd6bceso4495468e87.1 for ; Tue, 21 Apr 2026 03:18:55 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Furthermore, removing the "sstc" string from riscv,isa is not a reliable way to disable SSTC, because OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. Note: clearing RISCV_ISA_EXT_sstc from the DTS riscv,isa property is deferred to a follow-up patch. Also, the corresponding HENVCFG bit is not set so guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. Drop sbi_set_timer() as it is more than enough to have only introduced set_xen_timer(). Drop "SBI v0.2 TIME extension detected" message to avoid confusion which set timer function is really used. Signed-off-by: Oleksii Kurochko ---- Changes in v5: - Update defintion of csr_write64() to avoid compilation issue. ---- Changes in v4: - Introduce csr_write64() and __csr_write32h(). - Sort numericaly definitions of CSR_VSTIMECMP{H}. --- Changes in v3: - Reword print message when SSTC extension is detected. - s/__clear_bit/__set_bit() for the case when SSTC is detected in riscv_fill_hwcap(). Update also the comment above __set_bit(). - Drop BUG_ON()s in vtimer.c. - s/printk/dprintk for the message: SSTC detected... - Drop sbi_set_timer global variable, it is enough just to have set_xen_timer. - As we set bit in riscv_isa bitmap there is no need to use csr_read_safe(CSR_STIMECMP) second time. - Move init of CSR_VSTIMECMP in preinit_xen_time as it looks more correct place. - Update the commit message. --- Changes in v2: - Minor style fixes. - Drop from vcpu_csr_init() setting of SSTC bit in HENVCFG register. Add it back when SSTC for guests will be available. - Add static to set_xen_timer function pointer. - Refactor sstc_set_xen_timer(). - s/csr_allowed_read/csr_read_safe() --- xen/arch/riscv/cpufeature.c | 18 +++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/csr.h | 15 ++++++++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + xen/arch/riscv/include/asm/sbi.h | 18 --------- xen/arch/riscv/include/asm/time.h | 3 ++ xen/arch/riscv/sbi.c | 29 +++++++++++--- xen/arch/riscv/time.c | 42 +++++++++++++-------- xen/arch/riscv/vtimer.c | 1 + 9 files changed, 90 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..92235fdfd5ab 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include #include +#include #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_ext[] = { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount = ARRAY_SIZE(required_extensions); bool all_extns_available = true; + unsigned long tmp; riscv_fill_hwcap_from_isa_string(); @@ -495,6 +498,21 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + dprintk(XENLOG_DEBUG, + "SSTC detected; supported for Xen use, but not for guests\n"); + + /* + * As there is no any guarantee that SSTC will be added to riscv,isa + * property by OpenSBI(it doesn't add it now) or whatever ran before + * Xen, it is needed to set this bit manually. + * + * Guest isolation is maintained by not setting ENVCFG_STCE in henvcfg. + */ + __set_bit(RISCV_ISA_EXT_sstc, riscv_isa); + } + for ( i = 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext = required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/csr.h index 27d4b7942f6b..888d6a2a86d6 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -32,6 +32,21 @@ : "memory" ); \ }) +#ifdef CONFIG_RISCV_32 +#define csr_write64(csr, val) \ +({ \ + uint64_t v_ = (val); \ + csr_write(csr, v_); \ + csr_write(csr ## H, v_ >> 32); \ +}) +#else +#define csr_write64(csr, val) \ +({ \ + csr_write(csr, val); \ + (void)csr ## H; \ +}) +#endif + #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/include/asm/riscv_encoding.h index dd15731a86fa..03e186bcdb8c 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -395,6 +395,8 @@ #define CSR_VSCAUSE 0x242 #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d #define CSR_VSATP 0x280 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/sbi.h index ed7af200288f..1952868e963c 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,7 +13,6 @@ #define ASM__RISCV__SBI_H #include -#include /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -139,23 +138,6 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); -/* - * Programs the clock for next event at (or after) stime_value. stime_value is - * in absolute time. This function must clear the pending timer interrupt bit - * as well. - * - * If the supervisor wishes to clear the timer interrupt without scheduling the - * next timer event, it can either request a timer interrupt infinitely far - * into the future (i.e., (uint64_t)-1), or it can instead mask the timer - * interrupt by clearing sie.STIE CSR bit. - * - * The stime_value parameter represents absolute time measured in ticks. - * - * This SBI call returns 0 upon success or an implementation specific negative - * error code. - */ -extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); - /* * Initialize SBI library * diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h index be3875b9984e..4d68900151a7 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -4,6 +4,7 @@ #include #include +#include #include @@ -26,6 +27,8 @@ static inline cycles_t get_cycles(void) void preinit_xen_time(void); +extern int (* __ro_after_init set_xen_timer)(uint64_t deadline); + #endif /* ASM__RISCV__TIME_H */ /* diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index b4a7ae6940c1..3576e26033a5 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -22,6 +22,7 @@ #include #include +#include static unsigned long __ro_after_init sbi_spec_version = SBI_SPEC_VERSION_DEFAULT; @@ -249,6 +250,21 @@ static int (* __ro_after_init sbi_rfence)(unsigned long fid, unsigned long arg4, unsigned long arg5); +/* + * Programs the clock for next event at (or after) stime_value. stime_value is + * in absolute time. This function must clear the pending timer interrupt bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without scheduling the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific negative + * error code. + */ static int cf_check sbi_set_timer_v02(uint64_t stime_value) { struct sbiret ret; @@ -264,6 +280,10 @@ static int cf_check sbi_set_timer_v02(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } +/* + * Legacy SBI v0.1 SET_TIMER; functionally equivalent to sbi_set_timer_v02 + * from Xen's perspective. + */ static int cf_check sbi_set_timer_v01(uint64_t stime_value) { struct sbiret ret; @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_value) return sbi_err_map_xen_errno(ret.error); } -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) = sbi_set_timer_v01; - int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -360,10 +378,9 @@ int __init sbi_init(void) } if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) - { - sbi_set_timer = sbi_set_timer_v02; - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); - } + set_xen_timer = sbi_set_timer_v02; + else + set_xen_timer = sbi_set_timer_v01; } else panic("Ooops. SBI spec version 0.1 detected. Need to add support"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 698ab49d1292..8769709e5227 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,12 +7,21 @@ #include #include +#include #include -#include unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write64(CSR_STIMECMP, deadline); + + return 0; +} + +int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks = get_cycles() - boot_clock_cycles; @@ -61,20 +70,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <= now ) return 0; - /* - * TODO: When the SSTC extension is supported, it would be preferable to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementation. - * For example, it is not ideal to panic() if sbi_set_timer() returns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc = sbi_set_timer(deadline)) ) + if ( (rc = set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); /* Enable timer interrupt */ @@ -91,4 +87,20 @@ void __init preinit_xen_time(void) panic("%s: ACPI isn't supported\n", __func__); boot_clock_cycles = get_cycles(); + + /* set_xen_timer must have been set by sbi_init() already */ + ASSERT(set_xen_timer); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) + { + set_xen_timer = sstc_set_xen_timer; + + /* + * A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CSR. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + */ + csr_write64(CSR_STIMECMP, ULONG_MAX); + } } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..d5a8dfcb2edb 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include +#include #include static void vtimer_expired(void *data) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:22:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:22:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288790.1569031 (Exim 4.92) (envelope-from ) id 1wF8Fn-0005xP-0a; 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At a minimum, this needs >> expressing as a clobber. > I'm embarrassed of missing this. > >> Also fix a logical disconnect between 'overflow' being the carry flag not the >> overflow flag. CF and OF are always the same for MUL instructions, so use the >> flag which matches the variable name. > I don't mind this too much, but the use of CF was deliberate: Imo OF is > relevant to signed arithmetic only, whereas CF is the flag to use with > unsigned operations. > >> Fixes: d5c70a51bfbe ("x86/APIC: handle overflow in TMICT calculation") >> Signed-off-by: Andrew Cooper > Reviewed-by: Jan Beulich Thanks.  I could rename the variable to carry instead then?  Either works. > >> I've kept this form because it produces best code generation for GCCs which >> support flag outputs. >> >> An alternative would be to capture product_hi and check the nonzero-ness, as >> that's how OF/CF are produced in hardware, which would be better code >> generation on very old GCCs. > We could fit both, by further widening the use of ASM_FLAG_OUT(). > >> --- a/xen/arch/x86/apic.c >> +++ b/xen/arch/x86/apic.c >> @@ -1317,9 +1317,10 @@ int reprogram_timer(s_time_t timeout) >> >> apic_tmict = UINT32_MAX; >> asm ( "mul %[expire]\n\t" >> - ASM_FLAG_OUT(, "setc %[cf]") >> - : "=a" (product), [cf] ASM_FLAG_OUT("=@ccc", "=qm") (overflow) >> - : "0" ((unsigned long)bus_scale), [expire] "r" (expire) ); >> + ASM_FLAG_OUT(, "seto %[of]") >> + : "=a" (product), [of] ASM_FLAG_OUT("=@cco", "=qm") (overflow) > Noticing only now - for the non-flag-output case this should be "=&a". With > >> + : "0" ((unsigned long)bus_scale), [expire] "r" (expire) > ... %rax also being an input, there's no risk of the compiler using the > register for the other input, but still. Would you mind making that adjustment > as well, while at it? Ok. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:24:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:24:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288801.1569039 (Exim 4.92) (envelope-from ) id 1wF8HK-0006VX-CU; Tue, 21 Apr 2026 10:24:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288801.1569039; Tue, 21 Apr 2026 10:24:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8HK-0006VQ-9x; Tue, 21 Apr 2026 10:24:26 +0000 Received: by outflank-mailman (input) for mailman id 1288801; Tue, 21 Apr 2026 10:24:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF8HI-0006VI-M8 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:24:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8HH-003Jx8-VP for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 12:24:23 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7504e-bab6-0a2a0a5309dd-0a2a4509bd7e-34 for ; Tue, 21 Apr 2026 12:24:23 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e75057-2497-0a2a45090019-d1558029cc86-3 for ; Tue, 21 Apr 2026 12:24:23 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-48984d29fe3so24225595e9.0 for ; Tue, 21 Apr 2026 03:24:23 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8280fe1a5effacd595d3dd69b2b11e06226411b2.1775836193.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1776767063-416B0A53-5C2EA19A/10/73395122804 X-purgate-type: spam X-purgate-size: 1373 On 10.04.2026 17:54, Oleksii Kurochko wrote: > The dom0less solution uses defined RAM banks as compile-time constants, > so introduce macros to describe guest RAM banks. > > The reason for 2 banks is that there is typically always a use case for > low memory under 4 GB, but the bank under 4 GB ends up being small because > there are other things under 4 GB it can conflict with (interrupt > controller, PCI BARs, etc.). So a second bank is added above that MMIO > region (starting at 8 GiB) to provide the remaining RAM; the gap between > the two banks also exercises code paths handling discontiguous memory. > For Sv32 guests (34-bit GPA, 16 GiB addressable), bank0 provides 2 GB > (2–4 GB) and the first 8 GB of bank1 (8–16 GB) is accessible. > > Extended regions are useful for RISC-V: they could be used to provide a > "space" for Linux to map grant mappings. > > Despite the fact that for every guest MMU mode the GPA could be up > to 56 bits wide (except Sv32 whose GPA is 34 bits), the combined size > of both banks is limited to 1018 GB as it is more than enough for most > use cases. > > Add inclusion of asm/guest-layout.h to asm/domain.h to make dom0less > common code build happy. > > Signed-off-by: Oleksii Kurochko Again pretty hesitantly: Acked-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:26:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:26:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288811.1569049 (Exim 4.92) (envelope-from ) id 1wF8Iy-00070x-Mg; Tue, 21 Apr 2026 10:26:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288811.1569049; Tue, 21 Apr 2026 10:26:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8Iy-00070q-JX; Tue, 21 Apr 2026 10:26:08 +0000 Received: by outflank-mailman (input) for mailman id 1288811; Tue, 21 Apr 2026 10:26:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8Ix-00070i-9d for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:26:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8Iw-00BiZU-MM for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 12:26:06 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e750ba-e002-0a2a0a5209dd-0a2a4504b67e-26 for ; Tue, 21 Apr 2026 12:26:06 +0200 Received: from [209.85.221.50] (helo=mail-wr1-f50.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e750be-1dec-0a2a45040019-d155dd32c153-3 for ; Tue, 21 Apr 2026 12:26:06 +0200 Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-43eb05b1875so2378287f8f.3 for ; Tue, 21 Apr 2026 03:26:06 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1776767166-2AD643FF-FB2B7A93/0/0 X-purgate-type: clean X-purgate-size: 1006 On 21.04.2026 12:22, Andrew Cooper wrote: > On 21/04/2026 7:39 am, Jan Beulich wrote: >> On 20.04.2026 19:46, Andrew Cooper wrote: >>> The encoded MUL is 64 bits, so writes %rdx too. At a minimum, this needs >>> expressing as a clobber. >> I'm embarrassed of missing this. >> >>> Also fix a logical disconnect between 'overflow' being the carry flag not the >>> overflow flag. CF and OF are always the same for MUL instructions, so use the >>> flag which matches the variable name. >> I don't mind this too much, but the use of CF was deliberate: Imo OF is >> relevant to signed arithmetic only, whereas CF is the flag to use with >> unsigned operations. >> >>> Fixes: d5c70a51bfbe ("x86/APIC: handle overflow in TMICT calculation") >>> Signed-off-by: Andrew Cooper >> Reviewed-by: Jan Beulich > > Thanks.  I could rename the variable to carry instead then?  Either works. I'd slightly prefer that alternative, yes. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <2d5892447d6b6ad72962b8bbcb7c4d865b9e9989.1776765651.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776767293-1505AC48-4914A7CB/10/73395122804 X-purgate-type: spam X-purgate-size: 1592 On 21.04.2026 12:18, Oleksii Kurochko wrote: > OpenSBI currently does not advertise the SSTC extension via the device > tree, so if SSTC support is detected by Xen the riscv_isa bitmap is updated > manually. Furthermore, removing the "sstc" string from riscv,isa is not > a reliable way to disable SSTC, because OpenSBI probes support by > attempting to access CSR_STIMECMP. > > Introduce a runtime probe in Xen to determine whether SSTC is available. > The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the > access succeeds, SSTC is considered available; if a trap occurs, it is > treated as unsupported. > > When SSTC is detected, Xen may use it internally to program timers. > However, the extension is not exposed to guests because the required > context switch handling for the SSTC CSRs is not yet implemented. > > Note: clearing RISCV_ISA_EXT_sstc from the DTS riscv,isa property is > deferred to a follow-up patch. Also, the corresponding HENVCFG bit is > not set so guests fall back to the SBI timer interface. Timer requests > are then handled by Xen via the usual SBI interception path. > > Introduce set_xen_timer() to abstract how the timer is programmed, > either via the SSTC extension or an SBI call. > > Drop sbi_set_timer() as it is more than enough to have only introduced > set_xen_timer(). > > Drop "SBI v0.2 TIME extension detected" message to avoid confusion > which set timer function is really used. > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:28:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:28:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288828.1569066 (Exim 4.92) (envelope-from ) id 1wF8LQ-0008Tg-A5; Tue, 21 Apr 2026 10:28:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288828.1569066; Tue, 21 Apr 2026 10:28:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8LQ-0008TZ-7L; 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if anything, it would probably be > autoconf.h which it might include if so needed. > > 1: include: move KB() etc to macros.h > 2: x86/mkelf32: use xen/macros.h Ah yes, I've been wanting to move them out of config.h for a while. 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pr=C Message-ID: <6a6aefa7-530b-4221-b2b3-65ca3298aef1@amd.com> Date: Tue, 21 Apr 2026 12:33:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: skip holes in physical address space when setting up frametable To: Luca Fancellu CC: "xen-devel@lists.xenproject.org" , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Volodymyr Babchuk References: <20260417091124.39552-1-michal.orzel@amd.com> <10ef543f-ec21-47ae-aeb2-f569f8d48e27@amd.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|BN7PPF3C1137D8A:EE_ X-MS-Office365-Filtering-Correlation-Id: 42e78135-147f-4f2d-5b91-08de9f917953 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|18002099003|18096099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Bx/7z7wPkdGsL8/M8UgVN3UJrgUf579tNNBCv+KafMPU4ta2kV/zq84BZR3LAt4rdtv3xwqknaWihZ4zEE61EOD3UwZROS42LoQxygwSJMfuHg2AKEqu/Pj7BGEguwYXxdLOH07R6xmkO1lGMy1Fxla5Om3OsPQyMj8bYxht/m4t77VWdTwGWjpmCVkRp4q9KEnOecg/G08celjjIufN+jmVn3eQAFyHrCRYFDEpXrhepbwfEYPK/lzMj/ZLBxSKwvKdFZAzuttoQKcFpS8RM1zcIujtmI+JFFr7+2dzDN5TihDY2gWNPdKQPEzb+K/fDMF6nC1TMrnzydRC4U7S4wS2GhW3+846Kj1jFBQRqEyE+5uFrYtd4YLLGDggdHEInjb009ZPuhndqAIQN8bJ0Tc2KrKOltYhMdWhjxiYH6agXVR/o/xTTIFW/tT6JXQs X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 10:33:48.7222 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42e78135-147f-4f2d-5b91-08de9f917953 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF3C1137D8A X-purgate-ID: tlsNG-720697/1776767636-82374161-C161E082/0/0 X-purgate-type: clean X-purgate-size: 3976 On 20/04/2026 16:06, Luca Fancellu wrote: > HI Michal, > >>>> +void __init init_frametable(paddr_t ram_start) >>>> +{ >>>> + unsigned int sidx, nidx, max_idx; >>>> >>>> /* >>>> * The size of paddr_t should be sufficient for the complete range of >>>> @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >>>> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >>>> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >>>> >>>> - if ( frametable_size > FRAMETABLE_SIZE ) >>>> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >>>> - ps, pe); >>>> + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); >>>> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >>>> >>>> - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); >>>> - /* Round up to 2M or 32M boundary, as appropriate. */ >>>> - frametable_size = ROUNDUP(frametable_size, mapping_size); >>>> - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); >>>> + /* >>>> + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned >>>> + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this >>>> + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of >>>> + * PAGE_SIZE by construction. >>>> + */ >>>> + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); >>> >>> We are now rounding down frametable_base_pdx which before this patch it was the start of the ram, >>> but in xen/xen/arch/arm/include/asm/mm.h, mfn_valid(mfn) is using frametable_base_pdx to check for >>> mfn validity, this means that we could pass an mfn before the start of the ram and if __mfn_valid is happy, >>> we are getting a regression. >>> >>> Can this happen or am I missing something? >> mfn_valid() can indeed return true for an MFN below ram_start that falls >> in the same PDX group, but this is safe. init_frametable_chunk() maps >> and zeroes the frametable for that range, so mfn_to_page() won't fault. >> The zeroed page_info has count_info == 0 and no owner, so any get_page() >> call on it will fail — the page is effectively inert. > > Yes, I’ve checked and many path relying on mfn_valid() go also through mfn_to_page() > and/or get_page(), there is only one in process_shm() that potentially could add a shared memory page > given that we are relaxing mfn_valid now. We are not relaxing mfn_valid now. It has never meant to mean RAM. It means the MFN has a corresponding frame table entry with struct page_info. This is what it's comment says. Static shmem is safe for ghost MFN. In prepare_staticmem_pages() we have a check for count_info that for ghost MFN is 0. > > I’m trying also to follow is_iomem_page(), to check if subsequent mfn_to_page() fail safely, but I think that depending > on that (mfn_valid) the page will be only treated differently, not sure if it’s a latent bug to leave mfn_valid() as it is.\ On Arm, is_iomem_page() is just !mfn_valid(), so yes, ghost MFNs would be classified as not IOMEM. But this is harmless because is_iomem_page() on ARM is only called from grant table paths that operate on pages obrtained by get_page(), so no Arm code can reach is_iomem_page with a ghost MFN. > > Would it be valid to have something like mfn_to_page() != 0 to be part of mfn_valid() to ensure it’s a real host ram page? > I’m truly asking here because I didn’t check if it’s doable. As already said, mfn_valid was never supposed to mean RAM page. It is just that on ARM the two happened to coincide until this patch. > > Otherwise we could split the round down and the frametable_base_pdx in this way maybe? I don't think we need this extra complexity for something that is safe and has always been in use. We've never had mfn_valid == RAM guarantee. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:43:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:43:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288853.1569084 (Exim 4.92) (envelope-from ) id 1wF8ZP-0003pC-Qb; Tue, 21 Apr 2026 10:43:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288853.1569084; Tue, 21 Apr 2026 10:43:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8ZP-0003p5-NC; Tue, 21 Apr 2026 10:43:07 +0000 Received: by outflank-mailman (input) for mailman id 1288853; Tue, 21 Apr 2026 10:43:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8ZN-0003oz-KL for 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a4185ad0fdsm3633203e87.13.2026.04.21.03.47.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Apr 2026 03:47:57 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776768478; x=1777373278; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=5YmlL2hT0KtsZVaCj5CBsqfzKc6l01c1MMkDFyMd+5g=; b=avVGPwbGW+AWOIdNmQ46Nwq6r692NizuuP9MBzezOWuVP5SycO1waluuUrhc3yDxiP jPa6NxfB8mzEhnQ4UDGDtX+bJSgiI8iUDwcrFBDWxk6bRV66UpoGBsLsqehmZnobLcf1 TsWY/bfDdC6v5iW6Bd+ccs0E5BcwrhMVwKu0yGnyLuJBxY/wCZSM8xlpqFfAWu7ZY58R GXZ9eY2iRsr++OSpt4g7El/pYraIHLoeffOPxTk70UBoJNIjyTTSRBDH/5aNHiVeSU8d 3oBgaoQA2nZGPZreKksuWIXWuSFF/9bP/ITez35aT/WxFie2oFSpsp8PA1hv1enVlCTK 65Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776768478; x=1777373278; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5YmlL2hT0KtsZVaCj5CBsqfzKc6l01c1MMkDFyMd+5g=; b=JflUfacqPAa/PPoHTHIBF7+nRAHRU1/+exY+BO4TWDHJKDcuHIDEdCFtyMtNHM3R2U i98xFOWB4J/EtbDvEXEWU6IWzRzOxS8dh7xtM1jYzftdfukZ04+f0U2nLF2bRJTgvLoY khAwkKbCDMCQDJAtw+hKVmz4WsZJe0f4IMsvqbi9JQVKP24Tw5xWf7w3oC0ZBHF9kA6w FI12btTc737KiTgVW8PgjZqAZm1rSFtxEF4LtbhSn8yM5i5ZLB90QG+fxpG6KoA/LHSe X8kjDYgDxXW/yslke6uPoI5rH37fsM5AgRUJuGsmNhhitvFhOMcO11EltHZbYSOAVvqO WSYA== X-Forwarded-Encrypted: i=1; AFNElJ+1BT3W5C3w5S4u7b+H3IB4OnoePZb0zNzGs1a+QyOjco4BHGIJcI4di7gew+4p4OvemXqvlNHzbA8=@lists.xenproject.org X-Gm-Message-State: AOJu0YzVYYdOM0BcISuFzJPjJE9SvAcY8jArgkqvC/uDKkNocPEH+4AP WtSvcB7A3M4D5ukyqYOsY2qIJrZHhX7ceiWrE8E5fn47runCppsZnVKO X-Gm-Gg: AeBDievGY65ETJNxXQB47b6H/gkviJmx/XsGlq/GWEfzbxSHlE1BxOV1F2syJUu05LA ZHiswf58jTKIonbsfsksF1xFo74iD0kfiS5cAtCww82qMSiL5Mb0O1BS5cqDyBdmal31s2ofiDv y3DUfEZjcDJD5uSvOYsBpEVUD8QFoHJnU0BgjZUQ2TQd62dGOBg26YuYVauwwj95dnCHPf5hqNi 7Tzf3uiEfWb7H+MZt7HTIvkY2XThHS9bVdC4tlPxf7VS9RrmRmNROkACRnvWFMNoEHf1eRTHgoK S6AalZtwV4nJWMKT/As6jZcrg2D2jHwPSmdMr8Xi4sVrb0dBsVKpjRo6UTKStBfkB2pyfgCRpM9 bG6vR3TY9fDtezJw02dHgsu8190zRqvRj9N3lyDbqJcx55TKboVzaVtuY8ahVkEMwZAR+K0NQyY SgRGmo3yVfdHJb/4BK316VnSc33D+Uae1oMMhZeGDfrxONWA2fFRLSekbG6+MT8pt16NYSTYpud a0gugUglj1T6lT49xDgdL6X X-Received: by 2002:a05:6512:1287:b0:5a2:bef4:5e8a with SMTP id 2adb3069b0e04-5a4172d368bmr5752769e87.18.1776768477811; Tue, 21 Apr 2026 03:47:57 -0700 (PDT) Message-ID: <120bdb84-4f1d-4e26-aff7-2832fde245a1@gmail.com> Date: Tue, 21 Apr 2026 12:47:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] xen/dom0less: introduce free_phandle in struct kernel_info To: "Orzel, Michal" , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <58f59a071f6329acac610688a6c25b67b30e5b92.1776340422.git.oleksii.kurochko@gmail.com> <6188df37-47f1-4b46-8b4a-56316221b86c@amd.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <6188df37-47f1-4b46-8b4a-56316221b86c@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776768479-291763FF-B9E29561/10/73395122804 X-purgate-type: spam X-purgate-size: 1621 On 4/20/26 9:26 AM, Orzel, Michal wrote: > On 16/04/2026 16:20, Oleksii Kurochko wrote: >> There are cases where it is necessary to know the next available phandle >> number in order to generate phandles for guest device nodes. >> >> When a partial FDT (pfdt) is provided, special care is needed during >> initialization of free_phandle, as the pfdt may already contain a dummy >> interrupt controller node with a phandle assigned to it. free_phandle >> must therefore be initialized to one past the highest phandle already >> present in the pfdt, to avoid collisions. >> >> Since free_phandle may be needed for the very first guest node generated, > I would prefer next_phandle rather than free_phandle given that it always holds > the *next* phandle to be allocated. Free is implied. I am okay with such naming as I had it before and decided to change at last minute. > >> domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). >> The new call site also aligns better with the existing comment stating >> that domain_handle_dtb_boot_module() must be called before the rest of >> the device tree is generated. >> >> Introduce get_next_free_phandle() to ensure that phandles allocated for > The name is a bit confusing. It reads as "get the next one after the current > free phandle" but it actually returns the current value of free_phandle and post > increments it. Let's call it alloc_phandle(). This will also make it clear to > use the return value of this function instead of directly kinfo value. alloc_phandle() sounds good to me. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 10:48:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 10:48:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288872.1569103 (Exim 4.92) (envelope-from ) id 1wF8ey-0005M2-N0; Tue, 21 Apr 2026 10:48:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288872.1569103; Tue, 21 Apr 2026 10:48:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8ey-0005Lv-KJ; Tue, 21 Apr 2026 10:48:52 +0000 Received: by outflank-mailman (input) for mailman id 1288872; Tue, 21 Apr 2026 10:48:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF8ex-0005Lk-KY for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 10:48:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8ex-0076m1-1B for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 12:48:51 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7560a-e002-0a2a0a5209dd-0a2a4505b9a8-26 for ; Tue, 21 Apr 2026 12:48:51 +0200 Received: from [209.85.208.182] (helo=mail-lj1-f182.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e75612-aaa8-0a2a45050019-d155d0b6b08b-3 for ; Tue, 21 Apr 2026 12:48:50 +0200 Received: by mail-lj1-f182.google.com with SMTP id 38308e7fff4ca-38e91b06006so33424231fa.2 for ; Tue, 21 Apr 2026 03:48:50 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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Align prototype with what other make_*_node() are passed. >> 2. A follow-up RISC-V patch will call get_next_free_phandle() inside >> make_cpus_node(), requiring mutable access to kinfo->free_phandle. >> >> Signed-off-by: Oleksii Kurochko >> --- >> xen/arch/arm/domain_build.c | 5 +++-- >> xen/common/device-tree/dom0less-build.c | 2 +- >> xen/include/xen/fdt-domain-build.h | 2 +- >> 3 files changed, 5 insertions(+), 4 deletions(-) >> >> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c >> index 60a7cbf915a5..6740da3d324b 100644 >> --- a/xen/arch/arm/domain_build.c >> +++ b/xen/arch/arm/domain_build.c >> @@ -1164,7 +1164,7 @@ int __init make_psci_node(void *fdt) >> return res; >> } >> >> -int __init make_cpus_node(const struct domain *d, void *fdt) >> +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) >> { >> int res; >> const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); >> @@ -1178,6 +1178,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) >> /* Keep the compiler happy with -Og */ >> bool clock_valid = false; >> uint64_t mpidr_aff; >> + void *fdt = kinfo; > You're assigning kinfo to fdt pointer which is a bug. > Instead, you should do: > void *fdt = kinfo->fdt Oh, right. Missed apply changes properly. As you noticed it was fixed in the next patch. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 11:06:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 11:06:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288890.1569128 (Exim 4.92) (envelope-from ) id 1wF8vy-0000Id-9p; Tue, 21 Apr 2026 11:06:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288890.1569128; Tue, 21 Apr 2026 11:06:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8vy-0000IW-78; Tue, 21 Apr 2026 11:06:26 +0000 Received: by outflank-mailman (input) for mailman id 1288890; Tue, 21 Apr 2026 11:06:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF8vw-0000IQ-Ix for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:06:24 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8vv-00AmrS-Vl for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 13:06:23 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e75a29-5cb7-0a2a0a5109dd-0a2a450195d4-18 for ; Tue, 21 Apr 2026 13:06:23 +0200 Received: from [209.85.208.171] (helo=mail-lj1-f171.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e75a2f-c1f2-0a2a45010019-d155d0abc4a5-3 for ; Tue, 21 Apr 2026 13:06:23 +0200 Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-38e8292423fso35634001fa.0 for ; Tue, 21 Apr 2026 04:06:23 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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For x86_32 >> it is fine to follow generic is_{32,64}_bit_domain() implementations. > I thought x86_32 Xen no longer builds. This means the fallback is only for arm32. Will you be okay with Since x86_32 Xen no longer builds, the fallback is currently only relevant for arm32. ? From xen-devel-bounces@lists.xenproject.org Tue Apr 21 11:08:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 11:08:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288900.1569136 (Exim 4.92) (envelope-from ) id 1wF8yM-0000rv-LZ; Tue, 21 Apr 2026 11:08:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288900.1569136; Tue, 21 Apr 2026 11:08:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8yM-0000ro-Ix; Tue, 21 Apr 2026 11:08:54 +0000 Received: by outflank-mailman (input) for mailman id 1288900; Tue, 21 Apr 2026 11:08:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF8yK-0000rg-WA for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:08:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF8yI-00BWGn-78 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 13:08:52 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e75ab6-5cb7-0a2a0a5109dd-0a2a4508819e-32 for ; Tue, 21 Apr 2026 13:08:50 +0200 Received: from [192.198.163.8] (helo=mgamail.intel.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e75ac0-63b5-0a2a45080019-c0c6a308a67c-3 for ; Tue, 21 Apr 2026 13:08:50 +0200 Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 04:08:47 -0700 Received: from lkp-server01.sh.intel.com (HELO 7e48d0ff8e22) ([10.239.97.150]) by fmviesa001.fm.intel.com with ESMTP; 21 Apr 2026 04:08:46 -0700 Received: from kbuild by 7e48d0ff8e22 with local (Exim 4.98.2) (envelope-from ) id 1wF8yB-000000003Qa-3dGO; Tue, 21 Apr 2026 11:08:43 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=Intel header.d=intel.com header.i="@intel.com" header.h="Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776769729; x=1808305729; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=OeDNHRU79WaG0ZKrqxuZJYzFNK66hcB5aJigefNW67s=; b=c/qrtmhZfh9R/ls2F6Zxb/JIsutBUJzFnqz38XNDCoopkaIxak21qTBR 8VSKfRYYNsovpKyr4oEYP+mKwUn+HrpqlcoSGozq9/unAwgh9mJHBjCxb FnwXQV89wuV6KYa13eajG9mtcqe1h4o2nrZZnb3Z63OtVDsJ0N4boTwi0 EH7iByg4a4E37jpGKn6JcrCxK/7b9cUwYVp5Y/hhz61iNC20kktSKuDZD oXsh3uMKQMuRlBvjKVUoljdeK4bsqEP3Y81CcxDtYupwbo54f1wupQWpQ 9foAIYScgD0SnKV8f6hJ1Eb+y2Qo+aG9UzGyRQ8rP8i7FUlqIsRGgTylE A==; X-CSE-ConnectionGUID: nC9Y4b84R4at0C3monpQpQ== X-CSE-MsgGUID: 5tWbveVwS3CV+041hxC5yQ== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="95257951" X-IronPort-AV: E=Sophos;i="6.23,191,1770624000"; d="scan'208";a="95257951" X-CSE-ConnectionGUID: gUCRgVilQF+/8zgWNJVDBw== X-CSE-MsgGUID: h5r2wrwxT16rd+Nk+oK+MQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,191,1770624000"; d="scan'208";a="255473858" Date: Tue, 21 Apr 2026 19:08:06 +0800 From: kernel test robot To: zhaoguohan@kylinos.cn, jgross@suse.com, sstabellini@kernel.org Cc: oe-kbuild-all@lists.linux.dev, oleksandr_tyshchenko@epam.com, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, GuoHan Zhao Subject: Re: [PATCH] xen/manage: unwind partial shutdown watcher setup on error Message-ID: <202604211801.rqptlYaS-lkp@intel.com> References: <20260407022443.12971-1-zhaoguohan@kylinos.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260407022443.12971-1-zhaoguohan@kylinos.cn> X-purgate-ID: tlsNG-c1860d/1776769730-C2169DB1-E575909F/0/0 X-purgate-type: clean X-purgate-size: 3615 Hi, kernel test robot noticed the following build warnings: [auto build test WARNING on v7.0] [cannot apply to xen-tip/linux-next linus/master next-20260420] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/zhaoguohan-kylinos-cn/xen-manage-unwind-partial-shutdown-watcher-setup-on-error/20260416-185003 base: v7.0 patch link: https://lore.kernel.org/r/20260407022443.12971-1-zhaoguohan%40kylinos.cn patch subject: [PATCH] xen/manage: unwind partial shutdown watcher setup on error config: arm64-randconfig-002-20260421 (https://download.01.org/0day-ci/archive/20260421/202604211801.rqptlYaS-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.4.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260421/202604211801.rqptlYaS-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202604211801.rqptlYaS-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/xen/manage.c: In function 'setup_shutdown_watcher': >> drivers/xen/manage.c:380:1: warning: label 'err_unregister_shutdown' defined but not used [-Wunused-label] 380 | err_unregister_shutdown: | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/xen/manage.c: In function 'shutdown_event': drivers/xen/manage.c:357:60: warning: '%s' directive output may be truncated writing up to 71 bytes into a region of size 12 [-Wformat-truncation=] 357 | snprintf(node, FEATURE_PATH_SIZE, "feature-%s", | ^~ In function 'setup_shutdown_watcher', inlined from 'shutdown_event' at drivers/xen/manage.c:389:2: drivers/xen/manage.c:357:17: note: 'snprintf' output between 9 and 80 bytes into a destination of size 20 357 | snprintf(node, FEATURE_PATH_SIZE, "feature-%s", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 358 | shutdown_handlers[idx].command); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +/err_unregister_shutdown +380 drivers/xen/manage.c 353 354 for (idx = 0; idx < ARRAY_SIZE(shutdown_handlers); idx++) { 355 if (!shutdown_handlers[idx].flag) 356 continue; 357 snprintf(node, FEATURE_PATH_SIZE, "feature-%s", 358 shutdown_handlers[idx].command); 359 err = xenbus_printf(XBT_NIL, "control", node, "%u", 1); 360 if (err) { 361 pr_err("%s: Error %d writing %s\n", __func__, 362 err, node); 363 goto err_remove_features; 364 } 365 } 366 367 return 0; 368 369 err_remove_features: 370 while (--idx >= 0) { 371 if (!shutdown_handlers[idx].flag) 372 continue; 373 snprintf(node, FEATURE_PATH_SIZE, "feature-%s", 374 shutdown_handlers[idx].command); 375 xenbus_rm(XBT_NIL, "control", node); 376 } 377 #ifdef CONFIG_MAGIC_SYSRQ 378 unregister_xenbus_watch(&sysrq_watch); 379 #endif > 380 err_unregister_shutdown: 381 unregister_xenbus_watch(&shutdown_watch); 382 return err; 383 } 384 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki From xen-devel-bounces@lists.xenproject.org Tue Apr 21 11:53:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 11:53:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288914.1569145 (Exim 4.92) (envelope-from ) id 1wF9fj-0000Sv-Sq; Tue, 21 Apr 2026 11:53:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288914.1569145; Tue, 21 Apr 2026 11:53:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wF9fj-0000So-QA; Tue, 21 Apr 2026 11:53:43 +0000 Received: by outflank-mailman (input) for mailman id 1288914; Tue, 21 Apr 2026 11:53:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wF9fi-0000Si-Ca for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 11:53:42 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wF9fh-007J4d-Aa for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 13:53:41 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7653d-bab6-0a2a0a5309dd-0a2a4509e0da-30 for ; Tue, 21 Apr 2026 13:53:41 +0200 Received: from [209.85.167.47] (helo=mail-lf1-f47.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e76544-2497-0a2a45090019-d155a72fa57e-3 for ; Tue, 21 Apr 2026 13:53:41 +0200 Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5a415fd6bceso4579889e87.1 for ; Tue, 21 Apr 2026 04:53:41 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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I can update that. Just tried to keep changes smaller. > >> x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as >> x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. For x86_32 >> it is fine to follow generic is_{32,64}_bit_domain() implementations. > > As Michal has also alluded to, the use of x86_32 here needs some further > qualification, as Xen hasn't been possible to be built for that target > for many years. Quite possibly you mean guest type there, but then it's > unclear why you would restrict the explanation to 32-bit guests. I suggested to rephrase that part to: "Since x86_32 Xen no longer builds, the fallback is currently only relevant for arm32." > >> Generally it probably would be better to introduce CONFIG_32BIT >> and use it to define is_{32,64}bit_domain() as if one day >> CONFIG_128BIT will be introduced is_{32,64}bit_domain() will be >> defined incorrectly but considering that CONFIG_64BIT is maximum >> supported bitness it is fine to define in this way. > > Many things will need adjustment for a future CONFIG_128BIT. Imo this > kind of statement doesn't belong in a patch description; it could be a > post-commit-message remark. I will drop that part of the message. > >> --- a/xen/arch/Kconfig >> +++ b/xen/arch/Kconfig >> @@ -1,6 +1,9 @@ >> config 64BIT >> bool >> >> +config HAS_DOMAIN_TYPE >> + bool >> + >> config PHYS_ADDR_T_32 >> bool > > Why here rather than where the bulk of the other HAS_* are? Because it is a little arch-specific now as not all arch-s support it. I can move it to xen/common/Kconfig. > >> --- a/xen/arch/arm/domain_build.c >> +++ b/xen/arch/arm/domain_build.c >> @@ -1178,7 +1178,7 @@ int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) >> /* Keep the compiler happy with -Og */ >> bool clock_valid = false; >> uint64_t mpidr_aff; >> - void *fdt = kinfo; >> + void *fdt = kinfo->fdt; >> >> dt_dprintk("Create cpus node\n"); >> >> @@ -1774,13 +1774,13 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) >> >> #ifdef CONFIG_ARM_64 >> /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ >> - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) >> + if ( !(cpu_has_el1_32) && kinfo->type == DOMAIN_32BIT ) > > I'm not an Arm maintainer; if I was, I'd ask for the stray parentheses to be > dropped on this occasion. They could be dropped. Should be then it mentioned in commit message? > >> @@ -1896,7 +1896,7 @@ int __init construct_hwdom(struct kernel_info *kinfo, >> >> #ifdef CONFIG_ARM_64 >> /* type must be set before allocate_memory */ >> - d->arch.type = kinfo->arch.type; >> + d->type = kinfo->type; >> #endif > > I wonder why this doesn't use set_domain_type() (see also below). I assume that domain_build.c could be used for both dom0 and dom0less but set_domain_type() was used for dom0less. But generally I think it shouldn't be a problem to re-use it in construct_hwdom(). If it is fine to ... > >> --- a/xen/common/device-tree/dom0less-build.c >> +++ b/xen/common/device-tree/dom0less-build.c >> @@ -809,7 +809,10 @@ static int __init construct_domU(struct kernel_info *kinfo, >> if ( rc < 0 ) >> return rc; >> >> - set_domain_type(d, kinfo); >> +#ifdef CONFIG_HAS_DOMAIN_TYPE >> + /* type must be set before allocate memory */ > > Nit: Comment style. > >> + d->type = kinfo->type; >> +#endif > > Imo it would be preferable to retain set_domain_type(), to avoid #ifdef-ary > here and in construct_hwdom(). Of course its implementation would need to > move. Couldn't it be ... > >> --- a/xen/include/xen/dom0less-build.h >> +++ b/xen/include/xen/dom0less-build.h >> @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, >> int make_intc_domU_node(struct kernel_info *kinfo); >> int make_arch_nodes(struct kernel_info *kinfo); >> >> -void set_domain_type(struct domain *d, struct kernel_info *kinfo); > > ... an inline function here? ... move set_domain_type() to then it would be fine for me to have the following implementation: static void inline set_domain_type(struct domain *d, struct kernel_info *kinfo) { #ifdef CONFIG_HAS_DOMAIN /* type must be set before allocate memory */ d->arch.type = kinfo->arch.type; #endif } and re-use it everywhere it is needed. > >> --- a/xen/include/xen/sched.h >> +++ b/xen/include/xen/sched.h >> @@ -668,6 +668,10 @@ struct domain >> struct page_info *pending_scrub; >> unsigned int pending_scrub_order; >> unsigned int pending_scrub_index; >> + >> +#ifdef CONFIG_HAS_DOMAIN_TYPE >> + enum domain_type type; >> +#endif >> } __aligned(PAGE_SIZE); > > I'm not quite happy with all new fields getting put at the bottom, when > better options may exist. If the enum was a packed one, it could go next > to domain_id (where 16 bits of padding presently exist). The five *_pages > fields also have a padding field following them (unless MEM_SHARING != > MEM_PAGING). Just to be sure that I understand correctly what you meant: enum __attribute__((packed)) domain_type { DOMAIN_32BIT, DOMAIN_64BIT, }; struct domain { domid_t domain_id; #ifdef CONFIG_HAS_DOMAIN_TYPE enum domain_type type; #endif .... It is what you suggested? I thought that it make sense only for struct and unions to remove padding between members. Maybe do you mean just declare type member as uint16_t or even uint8_t, place it after domain_id and and keep the enum as symbolic constants? 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pr=C Message-ID: <1eeb93a1-bb57-4ac8-a280-2b78b045fc2f@amd.com> Date: Tue, 21 Apr 2026 13:55:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE To: Oleksii Kurochko , CC: Andrew Cooper , Anthony PERARD , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|CH2PR12MB4136:EE_ X-MS-Office365-Filtering-Correlation-Id: ae48f8c6-946d-42c2-8aad-08de9f9cdd89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|1800799024|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 06vQnzg3Yqk3fZjbrg6r9wm0M69lhX32QP5i3HlgNsI+g0XT6duaVvHrsfgBdNQb9yaC4LISO0j6wQFECzS9HbTf8DUlMCFyi5NOlbWJiw7Zg4q/eAnPxCs5yKTg08Gd0VtLo6OctHlbZmWd6AAZJlq4aagxaN1G42fzSDb7gYv/0KqdtfmoiPiCjElRZhOWzTGloNjoYVrY7vABJjI+SGjO+ST0SdX7Y51xn4ag1dk1TlSenLOpw2kXH/rlt8nfLCNZwCbsS0FhTWzOykI7EXw86ID+UFVxnPmw1QDmP0Qh/7aRM/1Fuyppry0MVM8inoXb6KzrUlN68j0e5JwueAjht+Qfcah0Qj8rTOMo1GIgBqjhFHc6hp+67om98Ih7CBz1y4ZyFqtojacRRPTv5veEayEE8LrI2SLaaEdzZc9YPb2KG9KGMM/uDn8DZixKwcFN+VecuYxwSPVb4gkwb0zUTlqP2ZDy8R+mBWQc1xa1YYBbrAyh/0DGjVDrgdx065aTftSlb3pJrGbSvGfVxmXvsN4vfjLRpFYCo2V/jsSZxntXy/3lL9LrlV+tDPILlM9kK8NaY9JHYQXKZszfUjMDhlnnE+thkToZ/QWdUdOEgVOsPIlzNU1uuSLZB2Q7pC/DHeiBaZNffQD47exubOzkHfQplY0hHa2qta8+WIPFNki4VhTAPukG16/C9oG6fMRfb4npC1Y9rLcRfuKKb/KO+jEHrmwDf5tB0aYrwFB6heGOcbc9gojjyB6r6ureCZJhbTO9RysBqkVRYrAtBw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(7416014)(1800799024)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4uOe6sSZld2TuaaPpQhniUFETrGQ/7LyxQsreInOrEc6ODXGWFMyT41ZhVdNZkeYzVKCe0Wr1fmkEiSLZKwRVTnmV/KABT1n1FSp1Eb2N2wPnugoQXb8/e3i57A4/zTXT8H18C6kROclhZOn4HwsjqnNPSB4Wv7HuWxUboKMlloBMt9L3saRV/FcCtgbFbRRci/ns3v1/UQw4n4CoDYi1MBlp4YmxhP/qE5gqccYzPfQDXCcop4Tl68svmwHQQlc2Eu47VdlYPSRdXaJfVlhTVRWdLSymbE69F3Uvmanj8NjB9HYNIxmjfGSeohPKQbVxBAkOg32f7l9poT6xtstEsvpgJp+1Qin3YDu+sX3WdiHfMEtuqD8108sv8b+YJtmDzRjnPI38w/RLAPwoVyf1xJudMruL+/H/ZKrJqSNGkFhylPe+LyYUkPsoFCXgx/9 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 11:55:21.2332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae48f8c6-946d-42c2-8aad-08de9f9cdd89 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4136 X-purgate-ID: tlsNG-720697/1776772527-80979161-50E45FB4/0/0 X-purgate-type: clean X-purgate-size: 973 On 21/04/2026 13:06, Oleksii Kurochko wrote: > > > On 4/20/26 10:03 AM, Orzel, Michal wrote: >> >> >> On 16/04/2026 16:21, Oleksii Kurochko wrote: >>> As domain type is part of common code now there is no any reason >>> to have architecture-specific set_domain_type() functions so >>> it is dropped. >>> >>> The CONFIG_ARM_64 guard in xen/arch/arm/domain_build.c is intentionally >>> left unchanged: it is ARM-specific code, and ARM_64 selects >>> HAS_DOMAIN_TYPE, so the semantics are identical. >>> >>> x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as >>> x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. For x86_32 >>> it is fine to follow generic is_{32,64}_bit_domain() implementations. >> I thought x86_32 Xen no longer builds. This means the fallback is only for arm32. > > Will you be okay with > Since x86_32 Xen no longer builds, the fallback is currently only > relevant for arm32. Yes. I would. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 21 12:41:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 12:41:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288948.1569167 (Exim 4.92) (envelope-from ) id 1wFAQC-0000Vs-Mf; Tue, 21 Apr 2026 12:41:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288948.1569167; Tue, 21 Apr 2026 12:41:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFAQC-0000Vl-Jf; Tue, 21 Apr 2026 12:41:44 +0000 Received: by outflank-mailman (input) for mailman id 1288948; Tue, 21 Apr 2026 12:41:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFAQB-0000Vf-5c for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 12:41:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFAQA-003noz-HJ for xen-devel@lists.xenproject.org; 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bh=LlkMuZfQjLigKOcgc4RUDQi/iQqyZKZyTcPalzo85jo=; b=GE0IjCdshD/1hK6pNuDLfWERhwgR566rCDwiqChmcBLMc4y4HfGe9q/PqnKdcGRV A7g0OIxaG/v5T632idc1cR7GEuEAA71brWh1aZSne1lWA9cQA6Mu0sYR5AuXkualgej +L1Ff6/4mQR774l/tE4vINnuj5d7Zg7zKKq9WYDQ= X-Gm-Message-State: AOJu0YzFqpZCvU/KlB/SYmpQOqrFkE1A0KGCU1z/boNoUaQNRYjno5yp SaM+0RjdCPHGvW2vASy9pE7cZC6fwiOtKzHJsMP88XCYVZ33QAn70PdiLk60dQWH68zlKpBTG6D g77Ozflla/pxBBP2NtDVdrrPRWFrQaTA= X-Received: by 2002:a05:6871:384e:b0:42c:2464:4ec3 with SMTP id 586e51a60fabf-42c2466f612mr1665283fac.38.1776775295584; Tue, 21 Apr 2026 05:41:35 -0700 (PDT) MIME-Version: 1.0 References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> <20260420213206.208750-9-Rose.Spangler@elektrobit.com> In-Reply-To: <20260420213206.208750-9-Rose.Spangler@elektrobit.com> From: Tamas K Lengyel Date: Tue, 21 Apr 2026 08:40:59 -0400 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDgFampPPP5f09O2e0AsTkKwKS-saSa1R-zl-sMd6o37GUCmh3nTwJbHo8 Message-ID: Subject: Re: [RFC PATCH v6 08/43] altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h To: Rose Spangler Cc: xen-devel@lists.xenproject.org, Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie Content-Type: multipart/alternative; boundary="00000000000056d194064ff7bc21" X-purgate-ID: tlsNG-bad1c0/1776775301-484A9A53-23B6948E/0/0 X-purgate-type: clean X-purgate-size: 1078 --00000000000056d194064ff7bc21 Content-Type: text/plain; charset="UTF-8" The following function names could reasonably drop the _altp2m suffix: > - p2m_get_altp2m -> altp2m_get_altp2m > - p2m_set_altp2m -> altp2m_set_altp2m > - p2m_reset_altp2m -> altp2m_reset_altp2m > - p2m_activate_altp2m -> altp2m_activate_altp2m Tamas --00000000000056d194064ff7bc21 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

    =
    The following function names could reasonably drop the _altp2m s= uffix:
    =C2=A0
    - p2m_get_altp2m -> altp2m_get_altp2m
    - p2m_set_altp2m -> altp2m_set_altp2m
    - p2m_reset_altp2m -> altp2m_reset_altp2m
    - p2m_activate_altp2m -> altp2m_activate_altp2m

    Tamas=C2=A0
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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <62fe5597-4230-48d1-8b3d-35715fc824c8@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776777168-93374A53-164CFC87/0/0 X-purgate-type: clean X-purgate-size: 3182 On 21.04.2026 13:53, Oleksii Kurochko wrote: > On 4/20/26 10:22 AM, Jan Beulich wrote: >> On 16.04.2026 16:21, Oleksii Kurochko wrote: >>> --- a/xen/arch/Kconfig >>> +++ b/xen/arch/Kconfig >>> @@ -1,6 +1,9 @@ >>> config 64BIT >>> bool >>> >>> +config HAS_DOMAIN_TYPE >>> + bool >>> + >>> config PHYS_ADDR_T_32 >>> bool >> >> Why here rather than where the bulk of the other HAS_* are? > > Because it is a little arch-specific now as not all arch-s support it. Most HAS_* are there to deal with per-arch differences. > I can move it to xen/common/Kconfig. Please do. >>> --- a/xen/arch/arm/domain_build.c >>> +++ b/xen/arch/arm/domain_build.c >>> @@ -1178,7 +1178,7 @@ int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) >>> /* Keep the compiler happy with -Og */ >>> bool clock_valid = false; >>> uint64_t mpidr_aff; >>> - void *fdt = kinfo; >>> + void *fdt = kinfo->fdt; >>> >>> dt_dprintk("Create cpus node\n"); >>> >>> @@ -1774,13 +1774,13 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) >>> >>> #ifdef CONFIG_ARM_64 >>> /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ >>> - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) >>> + if ( !(cpu_has_el1_32) && kinfo->type == DOMAIN_32BIT ) >> >> I'm not an Arm maintainer; if I was, I'd ask for the stray parentheses to be >> dropped on this occasion. > > They could be dropped. Should be then it mentioned in commit message? For something this small I wouldn't insist. But recall that I'm not the one to ack this part of the change. >>> --- a/xen/include/xen/sched.h >>> +++ b/xen/include/xen/sched.h >>> @@ -668,6 +668,10 @@ struct domain >>> struct page_info *pending_scrub; >>> unsigned int pending_scrub_order; >>> unsigned int pending_scrub_index; >>> + >>> +#ifdef CONFIG_HAS_DOMAIN_TYPE >>> + enum domain_type type; >>> +#endif >>> } __aligned(PAGE_SIZE); >> >> I'm not quite happy with all new fields getting put at the bottom, when >> better options may exist. If the enum was a packed one, it could go next >> to domain_id (where 16 bits of padding presently exist). The five *_pages >> fields also have a padding field following them (unless MEM_SHARING != >> MEM_PAGING). > > Just to be sure that I understand correctly what you meant: > > enum __attribute__((packed)) domain_type { > DOMAIN_32BIT, > DOMAIN_64BIT, > }; > > struct domain > { > domid_t domain_id; > > #ifdef CONFIG_HAS_DOMAIN_TYPE > enum domain_type type; > #endif > .... > > It is what you suggested? Yes, just without open-coding of __packed. > I thought that it make sense only for struct and unions to remove > padding between members. That's the attribute's effect on struct / union, yes. The effect is different for enum. > Maybe do you mean just declare type member as uint16_t or even uint8_t, > place it after domain_id and and keep the enum as symbolic constants? Preferably use the real type for the field. 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Instead of mapping one contiguous frametable > covering ram_start to ram_end (including holes), iterate the > pdx_group_valid bitmap to allocate and map frametable memory only for > valid PDX groups, skipping gaps in the physical address space. At the > moment we don't really take into account pdx_group_valid bitmap. > > This reduces memory consumption on systems with sparse RAM layouts by > not allocating frametable entries for non-existent memory regions. > > A file-local pdx_to_page() override is needed because the generic macro > in xen/include/xen/pdx.h does not account for ARM's non-zero > frametable_base_pdx. > > Update the MPU implementation to match the new init_frametable() > signature. Since MPU has no virtual address translation (ma == va), > hole-skipping is not possible and the frametable remains a single > contiguous allocation. > > Signed-off-by: Michal Orzel > --- > We've been using this approach at AMD for a while now. Without this we would not > be able to boot some of our boards that have huge holes in the PA space, so I > consider this patch a great improvement. > > Two things to consider as a follow-up in the future: > - change generic pdx_to_page, page_to_pdx to take into account offset that > on x86 is zero but on other arches it is not. The page list code is > for now unaffected because the offset cancels out, > - use the same on RISCV. Do you have such plans to do that for RISC-V? ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 21 13:34:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 13:34:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1288985.1569216 (Exim 4.92) (envelope-from ) id 1wFBFZ-0001u4-9Y; Tue, 21 Apr 2026 13:34:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1288985.1569216; Tue, 21 Apr 2026 13:34:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFBFZ-0001tx-6w; Tue, 21 Apr 2026 13:34:49 +0000 Received: by outflank-mailman (input) for mailman id 1288985; Tue, 21 Apr 2026 13:34:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFBFY-0001tr-Au for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 13:34:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFBFX-007fFw-DD for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 15:34:47 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e77cf1-e002-0a2a0a5209dd-0a2a4507b86e-18 for ; Tue, 21 Apr 2026 15:34:47 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e77cf7-229c-0a2a45070019-d1558029b59e-3 for ; Tue, 21 Apr 2026 15:34:47 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-488b150559bso33589655e9.1 for ; Tue, 21 Apr 2026 06:34:47 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260406191203.97662-5-stewart.hildebrand@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776778487-15255C48-6B54B943/0/0 X-purgate-type: clean X-purgate-size: 2291 On 06.04.2026 21:11, Stewart Hildebrand wrote: > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -670,6 +670,7 @@ static void cf_check bar_write( > { > struct vpci_bar *bar = data; > bool hi = false; > + uint16_t cmd = 0; > > ASSERT(is_hardware_domain(pdev->domain)); > > @@ -683,19 +684,29 @@ static void cf_check bar_write( > val &= PCI_BASE_ADDRESS_MEM_MASK; > > /* > - * Xen only cares whether the BAR is mapped into the p2m, so allow BAR > - * writes as long as the BAR is not mapped into the p2m. > + * Allow 64-bit BAR writes only when the BAR is not mapped in p2m. Always > + * allow 32-bit BAR writes. > */ > if ( bar->enabled ) > { > - /* If the value written is the current one avoid printing a warning. */ > - if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) > - gprintk(XENLOG_WARNING, > - "%pp: ignored BAR %zu write while mapped\n", > - &pdev->sbdf, bar - pdev->vpci->header.bars + hi); > - return; > - } > + if ( bar->type == VPCI_BAR_MEM32 ) > + { > + if ( val == bar->addr ) > + return; > > + cmd = pci_conf_read16(pdev->sbdf, PCI_COMMAND); > + modify_bars(pdev, cmd, false, false); > + } > + else > + { > + /* If the value written is the same avoid printing a warning. */ > + if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) > + gprintk(XENLOG_WARNING, > + "%pp: ignored BAR %zu write while mapped\n", > + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); > + return; > + } > + } > > /* > * Update the cached address, so that when memory decoding is enabled > @@ -715,6 +726,9 @@ static void cf_check bar_write( > } > > pci_conf_write32(pdev->sbdf, reg, val); > + > + if ( bar->enabled ) > + modify_bars(pdev, cmd, false, true); > } > > static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, While this all looks plausible, isn't something similar needed in rom_write() then as well? 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pr=C Message-ID: Date: Tue, 21 Apr 2026 09:54:46 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/9] tools/libs/store: add support to use watches with a depth parameter To: Juergen Gross , CC: Anthony PERARD , Julien Grall References: <20260421074211.308473-1-jgross@suse.com> <20260421074211.308473-4-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260421074211.308473-4-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A348:EE_|MN0PR12MB6173:EE_ X-MS-Office365-Filtering-Correlation-Id: cb5d97c5-35e1-4eed-291a-08de9fad8cca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: C7RfGo4ue3hvyxakVJ9c+CzVJ6J/nDd9Yun/ByVwXBjYRml/d+eAse+PvkauVFc/fwQR+tnUhiiC5Mj3175NZcOuedJ/bDcf1I84rcFGVa/kRDupAytkD4UAXgTGa2g59mrfhuR8XLrSvGr0dVtEXk3ol4R1bSIy74l3zukd8lyNaAjmRycQbPMOjPBwOJ7/e0SG/QFNO27qCbmO5cQmQm8eQJHAjQ+j1Kf83Vzhv8tiNewzvbqmMJg69IJ1q7VIvBp6s2jCkHD3CzPYnGZxNbirgCDZBBeX6suMi/YLm5Jq4t4iNcsX496gEvq/1yRCa4nepTu78yaI7HM2ZaA5ZcndDJvEk9ehgoOB0hfPgFyQl1/qvO1UsnEDEz4THpm18oIrZAlgrfXjENh6v+cVlrRytznKyIfqhzLMfiALl6FNMTCM0TfvoSXMnO7VmiGsXQNRW+uDfCjCOZeSyW7H5g3HTArj88pdYw9H+2coGD0WACyvy4nflNVuNEzwA5S7kqZwJed5m5kzbCkXGojzLQbVe3hTZPmLl/aFNnga0XwwAE9exGq+cESe9vXhipFgps4Hjo84EcKQ1Rf69fZE4eYVjviyGEYykRiBAeB74Ib3O2OdSn4zS7LnLzPTt4+luR3rUrixmH7PM4F47s12YwQ1HT9Ngyvps4qKysjw6YGeuLY1SXpRyHrYjMevW1JXM0EwiAg0sVbpfyq2N2DUAsBuVtQOYt/Y9Pa46QTzTsrMPKVUwdGWdt38+eRk4eSmTxcQ96a6zDlCOQ0BWbG43A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9CmnsaMm6/uDRHD244WkTeDBXkL+56daKi1lpVJMIDC1V8WHvfw05j6KQYYrg8vr4gBuQho1wKcUHVr31TseTUwHLt3coxutEefOb2QMttP5OTjtGprT61fZNTbmd85rmExqQ2VieKRl/fFmJUi/wkQHnu8OK7glnF36dki0LG0dZsCaai7QKFxa61Fkd/JRaXoWjuyAijIezZsG0eWq7KOenwPSPrHx2VvxuidMmE3HtouKXztREPCYLTHnWsiN/D/X0w/ggMrwKdB5wh/o0Y1QxWDlZ0Lz+1hu0PbqupDLT8Xeh0Aa288Vx1K/6rGtorThvb7Nr31go10evGfFRTpx5BEIx4tAt36rWSnuYIXBqyMOrVZbNKXFnK8YfCClRyV8Dkj3ndfboFUDEnRtIFEELFn8DoAXOm+Aha/obd/hYEMhjFnm0OzkYtNsX5ir X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 13:54:47.3120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb5d97c5-35e1-4eed-291a-08de9fad8cca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A348.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6173 X-purgate-ID: tlsNG-ef75cf/1776779693-AF77AC48-E656B825/0/0 X-purgate-type: clean X-purgate-size: 1514 On 2026-04-21 03:42, Juergen Gross wrote: > Add a new xs_watch_depth() function to libxenstore allowing to limit > the scope of a Xenstore watch. It can be used only in case Xenstore is > supporting the XENSTORE_SERVER_FEATURE_WATCHDEPTH feature. > > For convenience add a xs_watch_try_depth() wrapper, which will call > xs_watch_depth() if supported and xs_watch() otherwise. > > Cache the supported features of Xenstore in order not having to get > them from Xenstore for each call of one of the new functions. > > Signed-off-by: Juergen Gross > diff --git a/tools/libs/store/xs.c b/tools/libs/store/xs.c > index 06462445e0..cb3508a86a 100644 > --- a/tools/libs/store/xs.c > +++ b/tools/libs/store/xs.c > @@ -1001,8 +993,8 @@ bool xs_watch(struct xs_handle *h, const char *path, const char *token) > # define PTHREAD_STACK_MIN 0 > #endif > > -#define READ_THREAD_STACKSIZE \ > - ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ > +#define READ_THREAD_STACKSIZE \ > + ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ? \ This is an unrelated whitespace change, and not mentioned in the commit message. It should probably be dropped since the surrounding lines are no longer touched. Alternatively kept and mentioned. With either of those: Reviewed-by: Jason Andryuk Thanks, Jason > PTHREAD_STACK_MIN : DEFAULT_THREAD_STACKSIZE) > > /* We dynamically create a reader thread on demand. */ From xen-devel-bounces@lists.xenproject.org Tue Apr 21 14:04:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 14:04:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289008.1569238 (Exim 4.92) (envelope-from ) id 1wFBiH-0007lz-Ob; Tue, 21 Apr 2026 14:04:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289008.1569238; Tue, 21 Apr 2026 14:04:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFBiH-0007lr-LI; Tue, 21 Apr 2026 14:04:29 +0000 Received: by outflank-mailman (input) for mailman id 1289008; Tue, 21 Apr 2026 14:04:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFBiF-0007lj-7Q for xen-devel@lists.xenproject.org; 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Tue, 21 Apr 2026 16:04:23 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=MB/m/ZZNg4unA9O5EHjaJEeR/qWt44l6z4I1gSVJ4dk=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=TOaVLUo48manl0zBOhikmTndS8SRmxCYo/SVIfMXhxAmDpqDSRquYdrAmuvStYy0K+3ZzB/hz vbZZSMFd8hk6aZgZwB5d7AzxXF1KClJgQ8YbEqAi75SInffl0jUq0THAt+XSmkXpUrby+JBkDno Y0DbY/SzCQmmep0A+W9IIByyWoClaCmGAFhYI+3IRmiXTAwNXLlLHECdb+aJ2qX1Issu7AnmsSo okPHy5DfOHP3cIgxZYotBkChG4y/isshSDZpC/cebEOouDe3NSDJlBXOJbUa5862Czuyv/GxX8Z Dtz/XYF7Wy8Qs8CfKPeV8XOOyY1SFKCQ626fiTQ93YDA== X-Zone-Loop: 3fc5128abaea35f35050ab85e6d5e76fcaf417e7d227 x-campaign-type: default x-transaction-id: e53f060e-b64b-4739-82cc-34a2e2128896 x-swg-uid: 01-cc4ac554-f169-4f4d-9b60-469fa7643f91 X-Mailer: Sweego Message-ID: <1776780264.8631fc262581453bbf619ec5b2062170.19db05b44aa000f373@vates.tech> x-swg-bid: 1776780264.8631fc262581453bbf619ec5b2062170.19db05b44aa000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 21 Apr 2026 16:04:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/2] x86/svm: Use the virtual NMI when available To: Abdelkareem Abdelsaamad , andrew.cooper3@citrix.com, xen-devel@lists.xenproject.org Cc: roger.pau@citrix.com, jbeulich@suse.com, jason.andryuk@amd.com References: <29068558780bd9c6182d7bd74b357acc44409bfe.1772109484.git.abdelkareem.abdelsaamad@citrix.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <29068558780bd9c6182d7bd74b357acc44409bfe.1772109484.git.abdelkareem.abdelsaamad@citrix.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2489.c2540df3f714e6ac.19db05b4251.729abd03c36de791=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776780264017 X-purgate-ID: tlsNG-33051d/1776780266-A3161938-1411CCFA/0/0 X-purgate-type: clean X-purgate-size: 3025 ---=Part.2489.c2540df3f714e6ac.19db05b4251.729abd03c36de791=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 26/02/2026 =C3=A0 14:23, Abdelkareem Abdelsaamad a =C3=A9crit=C2=A0: > With the Virtual NMI (vNMI), the pending NMI is simply stuffed into the = VMCB > and handed off to the hardware=2E There is no need for the artificial tr= acking > of the NMI handling completion with the IRET instruction interception=2E >=20 > Adjust the svm_inject_nmi to rather inject the NMIs using the vNMI Hardw= are > accelerated feature when the AMD platform supports the vNMI=2E >=20 > Signed-off-by: Abdelkareem Abdelsaamad > --- > xen/arch/x86/hvm/svm/intr=2Ec | 6 ++++++ > xen/arch/x86/hvm/svm/svm=2Ec | 1 + > xen/arch/x86/hvm/svm/vmcb=2Ec | 2 ++ > 3 files changed, 9 insertions(+) >=20 > diff --git a/xen/arch/x86/hvm/svm/intr=2Ec b/xen/arch/x86/hvm/svm/intr= =2Ec > index 6453a46b85=2E=2E112a393211 100644 > --- a/xen/arch/x86/hvm/svm/intr=2Ec > +++ b/xen/arch/x86/hvm/svm/intr=2Ec > @@ -33,6 +33,12 @@ static void svm_inject_nmi(struct vcpu *v) > u32 general1_intercepts =3D vmcb_get_general1_intercepts(vmcb); > intinfo_t event; > =20 > + if ( vmcb->_vintr=2Efields=2Evnmi_enable ) > + { > + vmcb->_vintr=2Efields=2Evnmi_pending =3D 1; > + return; > + } > + > event=2Eraw =3D 0; > event=2Ev =3D true; > event=2Etype =3D X86_ET_NMI; > diff --git a/xen/arch/x86/hvm/svm/svm=2Ec b/xen/arch/x86/hvm/svm/svm=2Ec > index 18ba837738=2E=2E815565c33f 100644 > --- a/xen/arch/x86/hvm/svm/svm=2Ec > +++ b/xen/arch/x86/hvm/svm/svm=2Ec > @@ -2524,6 +2524,7 @@ const struct hvm_function_table * __init start_svm= (void) > P(cpu_has_tsc_ratio, "TSC Rate MSR"); > P(cpu_has_svm_sss, "NPT Supervisor Shadow Stack"); > P(cpu_has_svm_spec_ctrl, "MSR_SPEC_CTRL virtualisation"); > + P(cpu_has_svm_vnmi, "Virtual NMI"); > P(cpu_has_svm_bus_lock, "Bus Lock Filter"); > #undef P > =20 > diff --git a/xen/arch/x86/hvm/svm/vmcb=2Ec b/xen/arch/x86/hvm/svm/vmcb= =2Ec > index e583ef8548=2E=2Ee90bbac332 100644 > --- a/xen/arch/x86/hvm/svm/vmcb=2Ec > +++ b/xen/arch/x86/hvm/svm/vmcb=2Ec > @@ -184,6 +184,8 @@ static int construct_vmcb(struct vcpu *v) > if ( default_xen_spec_ctrl =3D=3D SPEC_CTRL_STIBP ) > v->arch=2Emsrs->spec_ctrl=2Eraw =3D SPEC_CTRL_STIBP; > =20 > + vmcb->_vintr=2Efields=2Evnmi_enable =3D cpu_has_svm_vnmi; > + > return 0; > } > =20 What is the status of this ? IIRC the main concern was regarding whether or not the vnmi_pending bit=20 requires to set the clean_bits=2E But it seems it is not the case here=2E Do we have a official confirmation on that ? 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bh=rMAbdzkmZ5IVwEOyN/4S2RtyRj/t40Q5Se0zwlSipfc=; b=GMjt5lBIh4iB+TpZD719z1AJYza7nPMFhTYse8QVnC3I+byKU5woR5HWqbswMpp1m5sCipUvI5yF3WNYZ14eY1zjoaCp3RG+l14IUBeta1EE1B9KpQ5Unq5Ag0RHS9epxBeCIYeFX3dxI4zFmP0veht6ZlztbY/WtJRdfP0eYOU= From: "Spangler, Rose" To: Tamas K Lengyel CC: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Teddy Astie Subject: Re: [RFC PATCH v6 08/43] altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h Thread-Topic: [RFC PATCH v6 08/43] altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h Thread-Index: AQHc0Q08g9UjbgeVPU23tPISZnL/sLXpdhuAgAAVnXI= Date: Tue, 21 Apr 2026 14:07:09 +0000 Message-ID: References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> <20260420213206.208750-9-Rose.Spangler@elektrobit.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=elektrobit.com; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JNh/0st8fKYb7DQsFRzW67MZZJDatAoJzEoRp4DErSbFtyEFEQdiHBLrkxE0KlKjx4qdS4c8DcWhDxAZmSSnd9WSTp/o2/yTRki6gTf415MRjQPTIGPw6PJA8UmNjisV1Mq+yiRDyt/+WDItM5OOB9X2/3S7fdXmYt2J0zZKsmBnHuzWWyEQVoFcgUuBTU/lr3QJgTvC2GPhufGvcatr56WlHSQj6tmtZQ9Y5iiiOsmVc30cXMpHo7TxmsHc3Qom143dHtd/LUYJghOcGv2AsblXT2HfIONHHkPZtlwg04CwcSyuhrhgh3TQ8TaG2xSeSAcDzSNNLXGxlvyLXQwtFgUU+0SMM6eXTXR2si63PN32AZPmPfq5zBzW7tnawO79Pqv7W2oD+lChEOaljDEnYDW9cRsTHF4I6vBMNK4YJOscX2C9OX6ujVMrQvZDYR9C X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 14:07:19.7089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46fc4ad9-f930-41ab-e4cd-08de9faf4d63 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-SJ5PEPF000001EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR08MB10938 X-purgate-ID: tlsNG-d25034/1776780445-F7C1FCF5-7301F3AC/0/0 X-purgate-type: clean X-purgate-size: 998 >The following function names could reasonably drop the _altp2m suffix:=0A= >=0A= >=0A= >> - p2m_get_altp2m -> altp2m_get_altp2m=0A= >> - p2m_set_altp2m -> altp2m_set_altp2m=0A= >> - p2m_reset_altp2m -> altp2m_reset_altp2m=0A= >> - p2m_activate_altp2m -> altp2m_activate_altp2m=0A= =0A= I used these names to try to differentiate between these functions, which= =0A= operate on a single altp2m view, and the altp2m_init / altp2m_teardown /=0A= altp2m_flush functions, which operate on all the views of a domain. For exa= mple,=0A= without the suffix I don't think it's necessarily immediately obvious that= =0A= "altp2m_activate" or "altp2m_reset" operate on only a single view. That bei= ng=0A= said, some of the other functions such as "altp2m_change_gfn" and=0A= "altp2m_get_or_propagate" don't follow this convention so I could go either= way=0A= on this, I just think the suffix /could/ provide a bit more clarity for the= se=0A= functions.=0A= =0A= Best,=0A= Rose= From xen-devel-bounces@lists.xenproject.org Tue Apr 21 14:23:41 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 14:23:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289029.1569257 (Exim 4.92) (envelope-from ) id 1wFC0a-0003LN-G7; Tue, 21 Apr 2026 14:23:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289029.1569257; Tue, 21 Apr 2026 14:23:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFC0a-0003LG-Bk; Tue, 21 Apr 2026 14:23:24 +0000 Received: by outflank-mailman (input) for mailman id 1289029; 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b=uiNRNgPw/OYcHA79Onr8u5EkFHjL7yyXmfJqflMB7tymSRuENUHTZVyg0bxHzYLd8HK9zJ7JzfPbFGuzt3DHZ1EVa714YQNbsESRUmovyH0XPdE6zH2BzjGaZJulcxt/fvc99wxKL02IfxKu3J6G7khN9rqf66CeXNn2QwDKY44= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com; Message-ID: <5787a185-0963-4c4f-94d3-d464871a88be@citrix.com> Date: Tue, 21 Apr 2026 15:23:13 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , roger.pau@citrix.com, jbeulich@suse.com, jason.andryuk@amd.com Subject: Re: [PATCH v5 2/2] x86/svm: Use the virtual NMI when available To: Teddy Astie , Abdelkareem Abdelsaamad , xen-devel@lists.xenproject.org References: <29068558780bd9c6182d7bd74b357acc44409bfe.1772109484.git.abdelkareem.abdelsaamad@citrix.com> <1776780264.8631fc262581453bbf619ec5b2062170.19db05b44aa000f373@vates.tech> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <1776780264.8631fc262581453bbf619ec5b2062170.19db05b44aa000f373@vates.tech> Content-Type: text/plain; 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There is no need for the artificial tracking >> of the NMI handling completion with the IRET instruction interception. >> >> Adjust the svm_inject_nmi to rather inject the NMIs using the vNMI Hardware >> accelerated feature when the AMD platform supports the vNMI. >> >> Signed-off-by: Abdelkareem Abdelsaamad >> --- >> xen/arch/x86/hvm/svm/intr.c | 6 ++++++ >> xen/arch/x86/hvm/svm/svm.c | 1 + >> xen/arch/x86/hvm/svm/vmcb.c | 2 ++ >> 3 files changed, 9 insertions(+) >> >> diff --git a/xen/arch/x86/hvm/svm/intr.c b/xen/arch/x86/hvm/svm/intr.c >> index 6453a46b85..112a393211 100644 >> --- a/xen/arch/x86/hvm/svm/intr.c >> +++ b/xen/arch/x86/hvm/svm/intr.c >> @@ -33,6 +33,12 @@ static void svm_inject_nmi(struct vcpu *v) >> u32 general1_intercepts = vmcb_get_general1_intercepts(vmcb); >> intinfo_t event; >> >> + if ( vmcb->_vintr.fields.vnmi_enable ) >> + { >> + vmcb->_vintr.fields.vnmi_pending = 1; >> + return; >> + } >> + >> event.raw = 0; >> event.v = true; >> event.type = X86_ET_NMI; >> diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c >> index 18ba837738..815565c33f 100644 >> --- a/xen/arch/x86/hvm/svm/svm.c >> +++ b/xen/arch/x86/hvm/svm/svm.c >> @@ -2524,6 +2524,7 @@ const struct hvm_function_table * __init start_svm(void) >> P(cpu_has_tsc_ratio, "TSC Rate MSR"); >> P(cpu_has_svm_sss, "NPT Supervisor Shadow Stack"); >> P(cpu_has_svm_spec_ctrl, "MSR_SPEC_CTRL virtualisation"); >> + P(cpu_has_svm_vnmi, "Virtual NMI"); >> P(cpu_has_svm_bus_lock, "Bus Lock Filter"); >> #undef P >> >> diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c >> index e583ef8548..e90bbac332 100644 >> --- a/xen/arch/x86/hvm/svm/vmcb.c >> +++ b/xen/arch/x86/hvm/svm/vmcb.c >> @@ -184,6 +184,8 @@ static int construct_vmcb(struct vcpu *v) >> if ( default_xen_spec_ctrl == SPEC_CTRL_STIBP ) >> v->arch.msrs->spec_ctrl.raw = SPEC_CTRL_STIBP; >> >> + vmcb->_vintr.fields.vnmi_enable = cpu_has_svm_vnmi; >> + >> return 0; >> } >> > What is the status of this ? > > IIRC the main concern was regarding whether or not the vnmi_pending bit > requires to set the clean_bits. But it seems it is not the case here. > > Do we have a official confirmation on that ? The status is it's waiting on me to do some additional testing as part of reviewing. I think it's correct now, but I want to confirm some corner cases. I have confirmation from AMD in private, and there is not a cleanbit involved.  No ETA on if/when the docs will be adjusted. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 21 14:27:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 14:27:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289041.1569265 (Exim 4.92) (envelope-from ) id 1wFC4E-0003vI-WC; Tue, 21 Apr 2026 14:27:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289041.1569265; Tue, 21 Apr 2026 14:27:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFC4E-0003vB-TX; Tue, 21 Apr 2026 14:27:10 +0000 Received: by outflank-mailman (input) for mailman id 1289041; Tue, 21 Apr 2026 14:27:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFC4D-0003v5-No for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 14:27:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFC4C-00BXYE-W5 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 16:27:09 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e78937-e002-0a2a0a5209dd-0a2a4505e5dc-20 for ; Tue, 21 Apr 2026 16:27:08 +0200 Received: from [170.10.129.124] (helo=us-smtp-delivery-124.mimecast.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7893b-aaa8-0a2a45050019-aa0a817cdedf-3 for ; Tue, 21 Apr 2026 16:27:08 +0200 Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-673-aNzvu0kYNpe-BCfSi7bC5Q-1; Tue, 21 Apr 2026 10:27:05 -0400 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 95FF91956089; Tue, 21 Apr 2026 14:27:04 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.44.49.140]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 7BDB4180047F; Tue, 21 Apr 2026 14:27:02 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mimecast20190719 header.d=redhat.com header.i="@redhat.com" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:content-type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1776781627; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=K8OFS7cyWvYenINAYlZhvmiwwCjJ2oV+n9qF7Hqe8c0=; b=YnNi/rLOPBxSPkcE5Yw2A8hO/PgYOV7w5jLvQTQ9FEfIIjmqsKe8bLBILwAPWt/ONFRYjl n7PdplwSNwrc9TxA0mkKHsszuhnt/YLBvW73JdziqdbeA1FCwklvI9OkzuZh0izWH3Tnwm 5gta37YlAHXmt4r/h0V1gj0ilR4eQEo= X-MC-Unique: aNzvu0kYNpe-BCfSi7bC5Q-1 X-Mimecast-MFC-AGG-ID: aNzvu0kYNpe-BCfSi7bC5Q_1776781624 From: Thomas Huth To: Juergen Gross , Stefano Stabellini Cc: Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Subject: [PATCH] xen/arm: Replace __ASSEMBLY__ with __ASSEMBLER__ in interface.h Date: Tue, 21 Apr 2026 16:27:01 +0200 Message-ID: <20260421142701.548978-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 X-Mimecast-MFC-PROC-ID: Fo9w7dORjlthjzKwaPWORily0J5vC8aJ69GQ_ePpzDg_1776781624 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit content-type: text/plain; charset="US-ASCII"; x-default=true X-purgate-ID: tlsNG-c201ff/1776781628-E09AD443-79164B1D/0/0 X-purgate-type: clean X-purgate-size: 1269 From: Thomas Huth While the GCC and Clang compilers already define __ASSEMBLER__ automatically when compiling assembly code, __ASSEMBLY__ is a macro that only gets defined by the Makefiles in the kernel. This can be very confusing when switching between userspace and kernelspace coding, or when dealing with uapi headers that rather should use __ASSEMBLER__ instead. So let's standardize now on the __ASSEMBLER__ macro that is provided by the compilers. Signed-off-by: Thomas Huth --- Note: This patch has been split from an earlier patch series of mine to ease reviewing. include/xen/arm/interface.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/xen/arm/interface.h b/include/xen/arm/interface.h index c3eada2642aa9..61360b89da405 100644 --- a/include/xen/arm/interface.h +++ b/include/xen/arm/interface.h @@ -30,7 +30,7 @@ #define __HYPERVISOR_platform_op_raw __HYPERVISOR_platform_op -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /* Explicitly size integers that represent pfns in the interface with * Xen so that we can have one ABI that works for 32 and 64 bit guests. * Note that this means that the xen_pfn_t type may be capable of -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 14:30:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 14:30:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289049.1569274 (Exim 4.92) (envelope-from ) id 1wFC7Z-0005rh-Ep; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Ona3yVn+fNktJ1KaWDji91Croo5WOO98HpSBgotTXE0rQfofOmRt3Q7qcYIVe84TXeW65OhMc0R5yeutHFchcxuKwF3MtaPdhe60OQplNpAiA+1eclU8yjB2Bx98bX5F1Y3t94gNJf9V03sM8c6NBYzLAF7Zk7Ew3nnuTG9fa4mDcRk2MLZnbALdt9mDgvzipFm6Ji0a40ltHb0rpQYggdqi2gkHCqdWhyEJEw+q+xIkRivNF9OO4OozPL/ijOab3KLUwiX6YoT1AzIGGRrsBYS4KtBmvuE9vSun/ixem3tHtfi+Pt7nAqwHzL1FcGYP/VJwpKFPOY4NgjyQSboP/O9r25ffgQ/X70nTzSxzlUbI9Jdphyu6NJf7KYSzrVSlrO2T/Uar0+no4bZi/mYA0VzHBD8c2Ih3Gy1RAeUyg7o9MWmrc2GJMXA59X0yR27Q X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 14:30:29.3102 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3af373f1-8df9-4e3c-0c39-08de9fb2898c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9811 X-purgate-ID: tlsNG-16d1c6/1776781834-50158D75-64DC150B/0/0 X-purgate-type: clean X-purgate-size: 1991 On 21/04/2026 15:30, Oleksii Kurochko wrote: > Hello Michał, > > On 4/17/26 11:11 AM, Michal Orzel wrote: >> Refactor setup_frametable_mappings() into init_frametable(), modeled >> after x86's implementation. Instead of mapping one contiguous frametable >> covering ram_start to ram_end (including holes), iterate the >> pdx_group_valid bitmap to allocate and map frametable memory only for >> valid PDX groups, skipping gaps in the physical address space. At the >> moment we don't really take into account pdx_group_valid bitmap. >> >> This reduces memory consumption on systems with sparse RAM layouts by >> not allocating frametable entries for non-existent memory regions. >> >> A file-local pdx_to_page() override is needed because the generic macro >> in xen/include/xen/pdx.h does not account for ARM's non-zero >> frametable_base_pdx. >> >> Update the MPU implementation to match the new init_frametable() >> signature. Since MPU has no virtual address translation (ma == va), >> hole-skipping is not possible and the frametable remains a single >> contiguous allocation. >> >> Signed-off-by: Michal Orzel >> --- >> We've been using this approach at AMD for a while now. Without this we would not >> be able to boot some of our boards that have huge holes in the PA space, so I >> consider this patch a great improvement. >> >> Two things to consider as a follow-up in the future: >> - change generic pdx_to_page, page_to_pdx to take into account offset that >> on x86 is zero but on other arches it is not. The page list code is >> for now unaffected because the offset cancels out, >> - use the same on RISCV. > > Do you have such plans to do that for RISC-V? My plan for this release cycle is to do this for Arm as we can observe great improvement in space management. Other things that I mentioned I planned for the future. I don't want to add new things on our plate in this release. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 21 14:43:40 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 14:43:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289060.1569283 (Exim 4.92) (envelope-from ) id 1wFCK4-0007x8-Fr; Tue, 21 Apr 2026 14:43:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289060.1569283; Tue, 21 Apr 2026 14:43:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFCK4-0007x1-Cp; Tue, 21 Apr 2026 14:43:32 +0000 Received: by outflank-mailman (input) for mailman id 1289060; Tue, 21 Apr 2026 14:43:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFCK2-0007wv-P1 for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 14:43:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFCK2-007ug8-5n for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 16:43:30 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e78cfe-5cb7-0a2a0a5109dd-0a2a45039320-42 for ; Tue, 21 Apr 2026 16:43:30 +0200 Received: from [209.85.221.52] (helo=mail-wr1-f52.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e78d11-672d-0a2a45030019-d155dd34e892-3 for ; Tue, 21 Apr 2026 16:43:29 +0200 Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-43cf7683a28so2969269f8f.2 for ; Tue, 21 Apr 2026 07:43:29 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Smith" , "xen-devel@lists.xenproject.org" References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1776782609-A1F7A938-DAF3DDC5/0/0 X-purgate-type: clean X-purgate-size: 8962 On 09.04.2026 16:01, Mykyta Poturai wrote: > From: Stewart Hildebrand > > This code is expected to only be used by privileged domains, > unprivileged domains should not get access to the SR-IOV capability. > > Implement RW handlers for PCI_SRIOV_CTRL register to dynamically > map/unmap VF BARS. Recalculate BAR sizes before mapping VFs to account > for possible changes in the system page size register. Also force VFs to > always use emulated reads for command register, this is needed to > prevent some drivers accidentally unmapping BARs. This apparently refers to the change to vpci_init_header(). Writes are already intercepted. How would a read lead to accidental BAR unmap? Even for writes I don't see how a VF driver could accidentally unmap BARs, as the memory decode bit there is hardwired to 0. > Discovery of VFs is > done by Dom0, which must register them with Xen. If we intercept control register writes, why would we still require Dom0 to report the VFs that appear? > Signed-off-by: Roger Pau Monné > Signed-off-by: Stewart Hildebrand > Signed-off-by: Mykyta Poturai First S-o-b doesn't match From: - is that correct? > --- a/xen/drivers/vpci/Makefile > +++ b/xen/drivers/vpci/Makefile > @@ -1,3 +1,4 @@ > obj-y += cap.o > obj-y += vpci.o header.o rebar.o > +obj-y += sriov.o > obj-$(CONFIG_HAS_PCI_MSI) += msi.o msix.o I understand the one line with multiple objects is unhelpful here, but for new additions (like was the case with cap.o) I think we want to respect alphabetical ordering, excluding the one odd line. > --- /dev/null > +++ b/xen/drivers/vpci/sriov.c > @@ -0,0 +1,314 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Handlers for accesses to the SR-IOV capability structure. > + * > + * Copyright (C) 2026 Citrix Systems R&D > + */ > + > +#include > +#include > +#include > +#include "private.h" > + > +static int vf_init_bars(const struct pci_dev *vf_pdev) > +{ > + int vf_idx; > + unsigned int i; > + const struct pci_dev *pf_pdev = vf_pdev->pf_pdev; > + struct vpci_bar *bars = vf_pdev->vpci->header.bars; > + struct vpci_bar *physfn_vf_bars = pf_pdev->vpci->sriov->vf_bars; > + unsigned int sriov_pos = pci_find_ext_capability(pf_pdev, > + PCI_EXT_CAP_ID_SRIOV); > + uint16_t offset = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_OFFSET); > + uint16_t stride = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_STRIDE); > + > + vf_idx = vf_pdev->sbdf.sbdf - (pf_pdev->sbdf.sbdf + offset); > + if ( vf_idx < 0 ) > + return -EINVAL; Why is underflow checked for, but too large a value isn't? > + if ( stride ) > + { > + if ( vf_idx % stride ) > + return -EINVAL; > + vf_idx /= stride; > + } What if stride is 0 and there are multiple VFs? > + /* > + * Set up BARs for this VF out of PF's VF BARs taking into account > + * the index of the VF. > + */ > + for ( i = 0; i < PCI_SRIOV_NUM_BARS; i++ ) > + { > + bars[i].addr = physfn_vf_bars[i].addr + vf_idx * physfn_vf_bars[i].size; > + bars[i].guest_addr = bars[i].addr; > + bars[i].size = physfn_vf_bars[i].size; > + bars[i].type = physfn_vf_bars[i].type; > + bars[i].prefetchable = physfn_vf_bars[i].prefetchable; This may end up quite a bit easier to read if &bar[i] and &physfn_vf_bars[i] were latched into local variables. It might further help if the = were all aligned with one another. > +static int map_vfs(const struct pci_dev *pf_pdev, uint16_t cmd) > +{ > + struct pci_dev *vf_pdev; > + int rc; > + > + ASSERT(rw_is_write_locked(&pf_pdev->domain->pci_lock)); > + > + list_for_each_entry(vf_pdev, &pf_pdev->vf_list, vf_list) > + { > + rc = vpci_modify_bars(vf_pdev, cmd, false); > + if ( rc ) > + { > + gprintk(XENLOG_ERR, "failed to %s VF %pp: %d\n", > + (cmd & PCI_COMMAND_MEMORY) ? "map" : "unmap", > + &vf_pdev->sbdf, rc); > + return rc; > + } > + > + vf_pdev->vpci->header.guest_cmd &= ~PCI_COMMAND_MEMORY; > + vf_pdev->vpci->header.guest_cmd |= (cmd & PCI_COMMAND_MEMORY); As mentioned elsewhere as well, this bit is supposed to be 0 for VFs. > +static void cf_check control_write(const struct pci_dev *pdev, unsigned int reg, > + uint32_t val, void *data) > +{ > + unsigned int sriov_pos = reg - PCI_SRIOV_CTRL; > + struct vpci_sriov *sriov = pdev->vpci->sriov; > + uint16_t control = pci_conf_read16(pdev->sbdf, reg); > + bool mem_enabled = control & PCI_SRIOV_CTRL_MSE; > + bool new_mem_enabled = val & PCI_SRIOV_CTRL_MSE; > + bool enabled = control & PCI_SRIOV_CTRL_VFE; > + bool new_enabled = val & PCI_SRIOV_CTRL_VFE; > + int rc; > + > + ASSERT(!pdev->info.is_virtfn); > + > + if ( new_enabled == enabled && new_mem_enabled == mem_enabled ) > + { > + pci_conf_write16(pdev->sbdf, reg, val); > + return; > + } > + > + if ( mem_enabled && !new_mem_enabled ) > + map_vfs(pdev, 0); Why are {new_,}enabled not also taken into account here? > + if ( !enabled && new_enabled ) > + { > + size_vf_bars(pdev, sriov_pos, (uint64_t *)data); (The cast is generally unnecessary here. If you want to keep it, I think a comment is needed.) > + /* > + * Only update the number of active VFs when enabling, when > + * disabling use the cached value in order to always remove the same > + * number of VFs that were active. > + */ > + sriov->num_vfs = pci_conf_read16(pdev->sbdf, > + sriov_pos + PCI_SRIOV_NUM_VF); > + } > + > + if ( !mem_enabled && new_mem_enabled ) > + { > + rc = map_vfs(pdev, PCI_COMMAND_MEMORY); Same here. > + if ( rc ) > + map_vfs(pdev, 0); > + } > + > + pci_conf_write16(pdev->sbdf, reg, val); > +} > + > +int vpci_vf_init_header(struct pci_dev *vf_pdev) I think this would better move (up or down), to not sit in the middle of PF functions. > +{ > + const struct pci_dev *pf_pdev; > + unsigned int sriov_pos; > + int rc = 0; > + uint16_t ctrl; > + > + ASSERT(rw_is_write_locked(&vf_pdev->domain->pci_lock)); > + > + if ( !vf_pdev->info.is_virtfn ) > + return 0; Looking at the sole call site, this apparently wants to be an assertion. > + pf_pdev = vf_pdev->pf_pdev; > + ASSERT(pf_pdev); The caller doesn't guarantee this, does it? > + rc = vf_init_bars(vf_pdev); > + if ( rc ) > + return rc; > + > + sriov_pos = pci_find_ext_capability(pf_pdev, PCI_EXT_CAP_ID_SRIOV); > + ctrl = pci_conf_read16(pf_pdev->sbdf, sriov_pos + PCI_SRIOV_CTRL); > + > + if ( (pf_pdev->domain == vf_pdev->domain) && (ctrl & PCI_SRIOV_CTRL_MSE) ) > + { > + rc = vpci_modify_bars(vf_pdev, PCI_COMMAND_MEMORY, false); Doesn't VF enable also need to be set for the BARs to be mapped? > + if ( rc ) > + return rc; > + > + vf_pdev->vpci->header.guest_cmd |= PCI_COMMAND_MEMORY; But the bit is required to be zero in the VF command register. > + } > + > + return rc; > +} > + > +static int cf_check init_sriov(struct pci_dev *pdev) > +{ > + unsigned int pos; > + > + ASSERT(!pdev->info.is_virtfn); Where's the check that prevents this from triggering? Aiui if vpci_init_capabilities() finds an SR-IOV capability in a VF's config space, it'll call here. > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); > + > + if ( !pos ) > + return 0; Can't this be an assertion? (In fact I was wondering why the caller, which already had to find the capability, doesn't pass the position.) > +static int cf_check cleanup_sriov(const struct pci_dev *pdev, bool hide) > +{ > + unsigned int pos; > + int rc; > + > + if ( !pdev->vpci->sriov ) > + return 0; > + > + ASSERT(!pdev->info.is_virtfn); > + ASSERT(list_empty(&pdev->vf_list)); What guarantees this latter property? > + if ( !hide ) > + { > + XFREE(pdev->vpci->sriov); > + return 0; > + } > + > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); As was explained in 9ebba62ca843 ("vPCI/ReBAR: improve cleanup") and d734babf8bc3 ("vPCI: re-init extended-capabilities when MMCFG availability changed"), you may not call this function during cleanup. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <1aaf1a087ca0003d943d43c55500b3ab84195cf5.1775742115.git.mykyta_poturai@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776783327-CFD788B7-EC7F7163/0/0 X-purgate-type: clean X-purgate-size: 848 On 09.04.2026 16:01, Mykyta Poturai wrote: > From: Stewart Hildebrand > > Emulate guest BAR register values based on PF BAR values for VFs. > This allows creating a guest view of the normal BAR registers and emulates > the size and properties as it is done during PCI device enumeration by > the guest. > > Expose VID/DID and class/revision to the guest. > > Note, that VFs ROM BAR is read-only and is all zeros, but VF may provide > access to the PFs ROM via emulation and is not implemented. > > Signed-off-by: Stewart Hildebrand > Signed-off-by: Mykyta Poturai So this change is merely to avoid having yet another gap on the road to DomU support in vPCI? I.e. there's no claim or expectation that VFs could now be used in DomU-s? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <65100dbbd16c10a76d2b1847f8fd77850f134559.1775742115.git.mykyta_poturai@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776783384-B5C64FF4-6A90D5FC/0/0 X-purgate-type: clean X-purgate-size: 453 On 09.04.2026 16:01, Mykyta Poturai wrote: > Signed-off-by: Mykyta Poturai Might this better be part of patch 5? Jan > --- a/SUPPORT.md > +++ b/SUPPORT.md > @@ -170,8 +170,6 @@ unexpected behavior or issues on some hardware. > > At least the following features are missing on a PVH dom0: > > - * PCI SR-IOV. > - > * Native NMI forwarding (nmi=dom0 command line option). > > * MCE handling. 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| ^ 1 error generated. Fixes: edb657887a60 ("xenpm: Add get-core-temp subcommand") Signed-off-by: Roger Pau Monné --- tools/misc/xenpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index 87107bd6c617..ecb39c911d84 100644 --- a/tools/misc/xenpm.c +++ b/tools/misc/xenpm.c @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *te { case 0: /* This CPU isn't online or can't query this MSR */ - errno = ENODATA; + errno = ENODEV; return -1; case 1: -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 15:35:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 15:35:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289113.1569318 (Exim 4.92) (envelope-from ) id 1wFD7q-0000mS-Tu; Tue, 21 Apr 2026 15:34:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289113.1569318; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20260421153224.36368-1-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776785760-0757BF3B-3A8C9D87/0/0 X-purgate-type: clean X-purgate-size: 1109 On 21.04.2026 17:32, Roger Pau Monne wrote: > ENODATA is not defined on FreeBSD: > > xenpm.c:1380:17: error: use of undeclared identifier 'ENODATA' > 1380 | errno = ENODATA; > | ^ > 1 error generated. > > Fixes: edb657887a60 ("xenpm: Add get-core-temp subcommand") > Signed-off-by: Roger Pau Monné > --- > tools/misc/xenpm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c > index 87107bd6c617..ecb39c911d84 100644 > --- a/tools/misc/xenpm.c > +++ b/tools/misc/xenpm.c > @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *te > { > case 0: > /* This CPU isn't online or can't query this MSR */ > - errno = ENODATA; > + errno = ENODEV; > return -1; "No such device", however, isn't quite what we want to convey here. If no better error code can be found that's available on FreeBSD and Linux, I'm inclined to suggest that we stick to ENODATA where available. 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> > | ^ > > 1 error generated. > > > > Fixes: edb657887a60 ("xenpm: Add get-core-temp subcommand") > > Signed-off-by: Roger Pau Monné > > --- > > tools/misc/xenpm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c > > index 87107bd6c617..ecb39c911d84 100644 > > --- a/tools/misc/xenpm.c > > +++ b/tools/misc/xenpm.c > > @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *te > > { > > case 0: > > /* This CPU isn't online or can't query this MSR */ > > - errno = ENODATA; > > + errno = ENODEV; > > return -1; > > "No such device", however, isn't quite what we want to convey here. If no > better error code can be found that's available on FreeBSD and Linux, I'm > inclined to suggest that we stick to ENODATA where available. Seems like a lot of complexity, for very limited usefulness. The only usage of errno is to be printed in the error message, and for the purposes of this function ENODEV is already unique in the function, as ENODATA was. FWIW, I think ENODEV is not that far fetched: the CPU being offline or the MSR not being present seems like what you would convey by using ENODEV. Thanks, Roger. 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=JM13Gw6w4R8wxXoYrniZxEvDfakgM/fcbZGm4Wqt84Y=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=DjgDaKtqMpeUdTKKNsz0krM6fmHvC6pX4SOuaKVn6pC6waPb+MHXO4m9io/fUMdGl1ULp/BJw yHxc2hiPxa2/ezvRpb3TeAyHg7PoOeuu2MyQOhH2z+wj0S8LXP16SEOO2VXvXElvZu/WyZ5zor5 juHIh05S1G9Tv0zsbhMyAVowfiwYh80SuD2lGBjpsmW62BO3bpO0dcDOchHpHYBwp5/2C+kvrLv E/E8pn+p+D4fK5sJplDePNJEixZPlK+673f2lyjQqreVq39AZuCi3xAUeSEsXe7GYJ1404LM+Yj zvIjrSMkJI8KeNszxrB1IsPhw3n7NPioYplHiyPABV+g== X-Zone-Loop: b1bbe22708f74e1c3708b643a51d8294da5fa711da23 x-campaign-type: default x-transaction-id: 3dc07649-3f99-4fd7-a025-5116eac5ece5 x-swg-uid: 01-0f43bdf8-a9db-44b2-b510-442e6f416311 X-Mailer: Sweego Message-ID: <1776787083.8631fc262581453bbf619ec5b2062170.19db0c3520e000f373@vates.tech> x-swg-bid: 1776787083.8631fc262581453bbf619ec5b2062170.19db0c3520e000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 21 Apr 2026 17:58:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] tools/xenpm: fix FreeBSD build To: Roger Pau Monne , xen-devel@lists.xenproject.org Cc: Anthony PERARD References: <20260421153224.36368-1-roger.pau@citrix.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <20260421153224.36368-1-roger.pau@citrix.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.24d7.5d37ca5e4ae1a4ca.19db0c34ff1.5ebb0072a08026e5=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776787083250 X-purgate-ID: tlsNG-42698a/1776787086-0415DF3B-727D99DF/0/0 X-purgate-type: clean X-purgate-size: 1507 ---=Part.24d7.5d37ca5e4ae1a4ca.19db0c34ff1.5ebb0072a08026e5=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 21/04/2026 =C3=A0 17:36, Roger Pau Monne a =C3=A9crit=C2=A0: > ENODATA is not defined on FreeBSD: >=20 > xenpm=2Ec:1380:17: error: use of undeclared identifier 'ENODATA' > 1380 | errno =3D ENODATA; > | ^ > 1 error generated=2E >=20 > Fixes: edb657887a60 ("xenpm: Add get-core-temp subcommand") > Signed-off-by: Roger Pau Monn=C3=A9 > --- > tools/misc/xenpm=2Ec | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/tools/misc/xenpm=2Ec b/tools/misc/xenpm=2Ec > index 87107bd6c617=2E=2Eecb39c911d84 100644 > --- a/tools/misc/xenpm=2Ec > +++ b/tools/misc/xenpm=2Ec > @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint3= 2_t cpu, bool package, int *te > { > case 0: > /* This CPU isn't online or can't query this MSR */ > - errno =3D ENODATA; > + errno =3D ENODEV; > return -1; > =20 > case 1: I wasn't aware ENODATA wasn't available on some BSDs=2E Even though it's= =20 supposed to be a part of POSIX=2E Regardless, Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.24d7.5d37ca5e4ae1a4ca.19db0c34ff1.5ebb0072a08026e5=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 16:00:39 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 16:00:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289154.1569354 (Exim 4.92) (envelope-from ) id 1wFDWf-0007tl-Hp; Tue, 21 Apr 2026 16:00:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289154.1569354; Tue, 21 Apr 2026 16:00:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFDWf-0007te-FE; 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> > | ^ > > 1 error generated. > > > > Fixes: edb657887a60 ("xenpm: Add get-core-temp subcommand") > > Signed-off-by: Roger Pau Monné > > --- > > tools/misc/xenpm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c > > index 87107bd6c617..ecb39c911d84 100644 > > --- a/tools/misc/xenpm.c > > +++ b/tools/misc/xenpm.c > > @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *te > > { > > case 0: > > /* This CPU isn't online or can't query this MSR */ > > - errno = ENODATA; > > + errno = ENODEV; > > return -1; > > > > case 1: > > I wasn't aware ENODATA wasn't available on some BSDs. Even though it's > supposed to be a part of POSIX. Not in the last version I think? https://pubs.opengroup.org/onlinepubs/9799919799/basedefs/errno.h.html Regards, Roger. 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnnoOUFAwAAAAAACgkQsN6d1ii/Ey+E UQf6AvimrCjT+qeS/EMALzX54pVz4XVR4Ic+oP0KoC9I6M1lZDdj/u47Q8df8+eKMm7E7Skcx/M3 /yV4ISbhNbJjo4F87ZAcPvhhHhdjEA9G/mMjORYdynKdpTaCZ+ARhv9wfOkBABsG4nQ2vnZjNb7O oWLJvtqusHz+AzCzm++NE0C/MO6aulSoLvXYiLAUD58jZdHRBFsPNCSsDn/QHtMeLlkBq9beJPnR pvHQ/+Ll+kbqyD8d2SMMb/TKAMHiQYK4mxgHRZ9klAAdHHXaOEWoRvi6GuMg6hb3Qm3vtFcIQo9x GiGWltqXWTMqYURuZARJAYIpVIB+0/8QwWUrzqD1yA== =E4br -----END PGP SIGNATURE----- --------------tNrAKuoyg0AsY90OCqZRp0zv-- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 16:16:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 16:16:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289180.1569373 (Exim 4.92) (envelope-from ) id 1wFDln-00026z-3b; Tue, 21 Apr 2026 16:16:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289180.1569373; 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Tue, 21 Apr 2026 18:16:12 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 8849981B9152; Tue, 21 Apr 2026 12:15:14 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 1/1] xen/efi: Config parsing: Free the same page count as allocated. Date: Tue, 21 Apr 2026 17:13:50 +0100 Message-Id: <127e7a4e0bf360d7ffe8be94022840a353a307b2.1776787216.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c201ff/1776788172-E07AE443-785AB7C8/0/0 X-purgate-type: clean X-purgate-size: 4121 When reading the config file or the config section, we may need to append a terminating NUL byte to the config buffer if the last byte is not a control character. This may cause an additional page to be allocated by efi_bs->AllocatePages() if the config file or config section size is a multiple of the page size. For this case, increment file->size by one so the number of pages to be freed by efi_bs->FreePages() is the same as the number of pages allocated by efi_bs->AllocatePages() when the additional byte is allocated. I moved the dcache flush after the NUL termination so the flushed range covers the final buffer contents. I didn't add a dcache flush for the copied cfg buffer in read_section(): that buffer is created by memcpy() and then consumed only by normal CPU reads in the EFI loader, so there is no non-coherent producer or other observer that would require cache maintenance. Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") Signed-off-by: Bernhard Kaindl ---- PS: The same fix applies to its backport to 4.21 and other branches, for example: stable-4.21: Fixes: feb99494bf59 ("EFI: avoid OOB config file reads") stable-4.20: Fixes: 05b8f716aa32 ("EFI: avoid OOB config file reads") PPS: A review using GPT-5.4 (just a data point for review) confirms what I've found by manual code inspection: > The fix in boot.c:882-886 and boot.c:913-928 is consistent with the existing > free sites at boot.c:790-797, boot.c:1564-1567, and boot.c:1638-1641: Once the > config buffer gets an extra terminating byte, using the incremented size for > PFN_UP during FreePages is the right fix. > > I also checked the parser helpers at boot.c:584-641; they already operate on > a bounded buffer and treat NUL/control bytes as terminators, so the synthetic > extra byte does not create an obvious parsing regression. --- xen/common/efi/boot.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index b44762878be4..94461b113180 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -858,7 +858,8 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, what = L"Allocation"; file->addr = min(1UL << (32 + PAGE_SHIFT), HYPERVISOR_VIRT_END - DIRECTMAP_VIRT_START); - /* For config files allocate an extra byte to put a NUL there. */ + + /* For config file buffers, allocate space for the terminating NUL byte */ ret = efi_bs->AllocatePages(AllocateMaxAddress, EfiLoaderData, PFN_UP(size + (file == &cfg)), &file->addr); if ( EFI_ERROR(ret) ) @@ -877,10 +878,12 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, FileHandle->Close(FileHandle); - efi_arch_flush_dcache_area(file->ptr, file->size); - if ( file == &cfg ) - file->str[file->size] = 0; + { + file->str[file->size] = 0; /* NUL-terminate the config data buffer. */ + file->size += 1; /* Free the same page count as allocated. */ + } + efi_arch_flush_dcache_area(file->ptr, file->size); return true; @@ -907,9 +910,9 @@ static bool __init read_section(const EFI_LOADED_IMAGE *image, file->ptr = ptr; - /* For cfg file, if necessary allocate space to put an extra NUL there. */ if ( file == &cfg && file->size && !iscntrl(file->str[file->size - 1]) ) { + /* Create a copy the config section for terminating the config buffer */ EFI_PHYSICAL_ADDRESS addr; EFI_STATUS ret = efi_bs->AllocatePages(AllocateMaxAddress, EfiLoaderData, @@ -922,6 +925,7 @@ static bool __init read_section(const EFI_LOADED_IMAGE *image, file->addr = addr; file->need_to_free = true; file->str[file->size] = 0; + file->size += 1; /* Free the same page count as allocated. */ } handle_file_info(name, file, options); -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 21 16:55:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 16:55:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289227.1569382 (Exim 4.92) (envelope-from ) id 1wFENe-00008b-Ud; Tue, 21 Apr 2026 16:55:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289227.1569382; Tue, 21 Apr 2026 16:55:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFENe-00008T-Rk; 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To: Demi Marie Obenour , =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> <686713fc-c762-4b1b-88b2-d486d4f38ac6@gmail.com> Content-Language: en-US From: Val Packett Autocrypt: addr=val@invisiblethingslab.com; keydata= xm8EaFTEiRMFK4EEACIDAwQ+qzawvLuE95iu+QkRqp8P9z6XvFopWtYOaEnYf/nE8KWCnsCD jz82tdbKBpmVOdR6ViLD9tzHvaZ1NqZ9mbrszMXq09VfefoCfZp8jnA2yCT8Y4ykmv6902Ne NnlkVwrNKFZhbCBQYWNrZXR0IDx2YWxAaW52aXNpYmxldGhpbmdzbGFiLmNvbT7CswQTEwkA OxYhBAFMrro+oMGIFPc7Uc87uZxqzalRBQJoVMSJAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMB Ah4HAheAAAoJEM87uZxqzalRlIIBf0cujzfSLhvib9iY8LBh8Tirgypm+hJHoY563xhP0YRS pmqZ6goIuSGpEKcW5mV3egF/TLLAOjsfroWae4giImTVOJvLOsUycxAP4O5b1Qiy+cCGsHKA nCRzrvqnPkyf4OeRznMEaFTEiRIFK4EEACIDAwSffe3tlMmmg3eKVp7SJ+CNZLN0M5qzHSCV dBBkIVvEJo+8SDg4jrx/832rxpvMCz2+x7+OHaeBHKafhOWUccYBLKqV/3nBftxCkbzXDbfY d02BY9H4wBIn0Y3GnwoIXRgDAQkJwpgEGBMJACAWIQQBTK66PqDBiBT3O1HPO7mcas2pUQUC aFTEiQIbDAAKCRDPO7mcas2pUaptAX9f7yUJLGU4C6XjMJvXd8Sz6cGTyxkngPtUyFiNqtad /GXBi3vHKYNfSrdqJ8wmZ8MBgOqWaaa1wE4/3qZU8d4RNR8mF7O40WYK/wdf1ycq1uGad8PN UDOwAqdfvuF3w8QMPw== In-Reply-To: <686713fc-c762-4b1b-88b2-d486d4f38ac6@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1776790520-45F698B7-5C0A7948/0/0 X-purgate-type: clean X-purgate-size: 6599 On 4/20/26 4:12 PM, Demi Marie Obenour wrote: > On 4/20/26 14:53, Christian König wrote: >> On 4/20/26 20:46, Demi Marie Obenour wrote: >>> On 4/20/26 13:58, Christian König wrote: >>>> On 4/20/26 19:03, Demi Marie Obenour wrote: >>>>> On 4/20/26 04:49, Christian König wrote: >>>>>> On 4/17/26 21:35, Demi Marie Obenour wrote: >>>> ... >>>>>>> Are any of the following reasonable options? >>>>>>> >>>>>>> 1. Change the guest kernel to only map (and thus pin) a small subset >>>>>>> of VRAM at any given time. If unmapped VRAM is accessed the guest >>>>>>> traps the page fault, evicts an old VRAM mapping, and creates a >>>>>>> new one. >>>>>> Yeah, that could potentially work. >>>>>> >>>>>> This is basically what we do on the host kernel driver when we can't resize the BAR for some reason. In that use case VRAM buffers are shuffled in and out of the CPU accessible window of VRAM on demand. >>>>> How much is this going to hurt performance? >>>> Hard to say, resizing the BAR can easily give you 10-15% more performance on some use cases. >>>> >>>> But that involves physically transferring the data using a DMA. For this solution we basically only have to we basically only have to transfer a few messages between host and guest. >>>> >>>> No idea how performant that is. >>> In this use-case, 20-30% performance penalties are likely to be >>> "business as usual". >> Well that is quite a bit. >> >>> Close to native performance would be ideal, but >>> to be useful it just needs to beat software rendering by a wide margin, >>> and not cause data corruption or vulnerabilities. >> That should still easily be the case, even trivial use cases are multiple magnitudes faster on GPUs compared to software rendering. > Makes sense. If only GPUs supported easy and flexible virtualization the way CPUs do :(. > >>>>>> But I have one question: When XEN has a problem handling faults from the guest on the host then how does that work for system memory mappings? >>>>>> >>>>>> There is really no difference between VRAM and system memory in the handling for the GPU driver stack. >>>>>> >>>>>> Regards, >>>>>> Christian. >>>>> Generally, Xen makes the frontend (usually an unprivileged VM) >>>>> responsible for providing mappings to the backend (usually the host). >>>>> That is possible with system RAM but not with VRAM, because Xen has >>>>> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. >>>> No, that doesn't work with system memory allocations of GPU drivers either. >>>> >>>> We already had it multiple times that people tried to be clever and incremented the page reference counter on driver allocated system memory and were totally surprised that this can result in security issues and data corruption. >>>> >>>> I seriously hope that this isn't the case here again. As far as I know XEN already has support for accessing VMAs with VM_PFN or otherwise I don't know how driver allocated system memory access could potentially work. >>>> >>>> Accessing VRAM is pretty much the same use case as far as I can see. >>>> >>>> Regards, >>>> Christian. >>> The Xen-native approach would be for system memory allocations to >>> be made using the Xen driver and then imported into the virtio-GPU >>> driver via dmabuf. Is there any chance this could be made to happen? >> That could be. Adding Pierre-Eric to comment since he knows that use much better than I do. >> >>> If it's a lost cause, then how much is the memory overhead of pinning >>> everything ever used in a dmabuf? It should be possible to account >>> pinned host memory against a guest's quota, but if that leads to an >>> unusable system it isn't going to be good. >> That won't work at all. >> >> We have use cases where you *must* migrate a DMA-buf to VRAM or otherwise the GPU can't use it. >> >> A simple scanout to a monitor is such an use case for example, that is usually not possible from system memory. > Direct scanout isn't a concern here. > >>> Is supporting page faults in Xen the only solution that will be viable >>> long-term, considering the tolerance for very substantial performance >>> overheads compared to native? AAA gaming isn't the initial goal here. >>> Qubes OS already supports PCI passthrough for that. >> We have AAA gaming working on XEN through native context working for quite a while. >> >> Pierre-Eric can tell you more about that. >> >> Regards, >> Christian. > I've heard of that, but last I checked it required downstream patches > to Xen, Linux, and QEMU. I don't know if any of those have been > upstreamed since, but I believe that upstreaming the Xen and Linux > patches (or rewriting them and upstreaming the rewritten version) would > be necessary. Qubes OS (which I don't work for anymore but still want > to help with this) almost certainly won't be using QEMU for GPU stuff. Yeah, our plan is to use xen-vhost-frontend[1] + vhost-device-gpu, ported/extended/modified as necessary. (I already have xen-vhost-frontend itself working on amd64 PVH with purely xenbus-based hotplug/configuration, currently working on cleaning up and submitting the necessary patches.) I'm curious to hear more details about how AMD has it working but last time I checked, there weren't any missing pieces in Xen or Linux that we'd need.. The AMD downstream changes were mostly related to QEMU. As for the memory management concerns, I would like to remind everyone once again that the pinning of GPU dmabufs in regular graphics workloads would be *very* short-term. In GPU paravirtualization (native contexts or venus or whatever else) the guest mostly operates on *opaque handles* that refer to buffers owned by the host GPU process. The typical rendering process (roughly) only involves submitting commands to the GPU that refer to memory using these handles. Only upon mmap() would a buffer be pinned/granted to the guest, and those are typically only used for *uploads* where the guest immediately does its memcpy() and unmaps the buffer. So I'm not worried about (unintentionally) pinning too much GPU driver memory. In terms of deliberate denial-of-service attacks from the guest to the host, the only reasonable response is: ¯\_(ツ)_/¯ CPU-mapping lots of GPU memory is far from the only DoS vector, the GPU commands themselves can easily wedge the GPU core in a million ways (and last time I checked amdgpu was noooot so good at recovering from hangs). [1]: https://github.com/vireshk/xen-vhost-frontend ~val From xen-devel-bounces@lists.xenproject.org Tue Apr 21 17:44:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 17:44:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289260.1569391 (Exim 4.92) (envelope-from ) id 1wFF8b-0007zI-BH; Tue, 21 Apr 2026 17:43:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289260.1569391; Tue, 21 Apr 2026 17:43:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFF8b-0007zB-8N; Tue, 21 Apr 2026 17:43:53 +0000 Received: by outflank-mailman (input) for mailman id 1289260; Tue, 21 Apr 2026 17:43:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFF8Z-0007z5-So for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 17:43:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFF8Z-008LGe-9s for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 19:43:51 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7b744-2eae-0a2a0a5409dd-0a2a450cd4a8-4 for ; Tue, 21 Apr 2026 19:43:50 +0200 Received: from [40.107.209.60] (helo=PH8PR06CU001.outbound.protection.outlook.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7b755-62f1-0a2a450c0019-286bd13cf869-3 for ; Tue, 21 Apr 2026 19:43:50 +0200 Received: from PH7PR12MB5685.namprd12.prod.outlook.com (2603:10b6:510:13c::22) by CY8PR12MB9035.namprd12.prod.outlook.com (2603:10b6:930:77::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.16; Tue, 21 Apr 2026 17:43:46 +0000 Received: from PH7PR12MB5685.namprd12.prod.outlook.com ([fe80::ce69:cfae:774d:a65c]) by PH7PR12MB5685.namprd12.prod.outlook.com ([fe80::ce69:cfae:774d:a65c%5]) with mapi id 15.20.9846.016; Tue, 21 Apr 2026 17:43:46 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=amd.com header.i="@amd.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SZwvTrAloADlkrK62GVftDHR9MlSoXn226+3QrUbKK1fA6E5NoNRybv+THU7lZrNk5et7u1FSkupo34azI4VJvGU2OigOazYliHJ/vTY9BhgQRepLvbQGYkgdaixWaWGi3KM9bF7PwR0HFXSb9Jj5GXj4vRFirIJ8eoqKk0eG4FV5fDC8OfTgP0Dl3+r3K4rVo1VClVawla7jEmZmgK+6gSwyZJp0Kf24mi4etsR9z2i9xRnGOY0x0YM45zLaLPEHDsTTS4FH0UmbwFCw39YxIJf/encmNd7/fd18uNblzCNHd3TitD+VkoXxLIwY/8KDsfztVaEo3kD7mWNzstgMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/d20sBKFlUaHRpoAKBBhzJ1Qu39OZv02Y2A0bpdBgCg=; b=nZJx9pJTwYmVkb9qOQ2qQHz2cdcI5s105lKNSBoft/rCciaFLDHmuxb5LY9UyRLJxcZsqTHd5eNZn4DqWyod19MRXSGO/r7uEochmRSblWB41U7jTvIBv+uw4fXHKCw0KoCh9Ua9NJUy/BV0fcF9yYbrOXOol98EJV7PF0tLDFBOf4Hcyo4o7qT40BZ6Qeme2WWHcGdsaB7KjG1xicivcct/Dl8jaCC9hKUt96mZS83nKH3lnYuf0xYE2TyZ/xDrSnUuPqVquwrZJwLRx5SZSe4tnz/oTfmOiwna9W0I3jGsdrAt2sLJ7kcfE2SgX2J7qN9Al9n+wSBw9mBvnVu7LQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/d20sBKFlUaHRpoAKBBhzJ1Qu39OZv02Y2A0bpdBgCg=; b=f+qv87RIhx6KVnFhweSYxVlB1nHVX9xOiFzGR7RfO20Aj9bjh5ENJ4Mv+JpFQyM3brlGxU6QDYCOMtbkNiMu50BiFThMmNAQcWwVjuw6DJt4JMNACxuGwfMbU0qPfSk5W54of/goMuW83VtODLPQS9JeZznBHagQotYiy3farao= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Message-ID: Date: Tue, 21 Apr 2026 19:43:42 +0200 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? 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Change the guest kernel to only map (and thus pin) a small subset >>>>>>>>     of VRAM at any given time.  If unmapped VRAM is accessed the guest >>>>>>>>     traps the page fault, evicts an old VRAM mapping, and creates a >>>>>>>>     new one. >>>>>>> Yeah, that could potentially work. >>>>>>> >>>>>>> This is basically what we do on the host kernel driver when we can't resize the BAR for some reason. In that use case VRAM buffers are shuffled in and out of the CPU accessible window of VRAM on demand. >>>>>> How much is this going to hurt performance? >>>>> Hard to say, resizing the BAR can easily give you 10-15% more performance on some use cases. >>>>> >>>>> But that involves physically transferring the data using a DMA. For this solution we basically only have to we basically only have to transfer a few messages between host and guest. >>>>> >>>>> No idea how performant that is. >>>> In this use-case, 20-30% performance penalties are likely to be >>>> "business as usual". >>> Well that is quite a bit. >>> >>>> Close to native performance would be ideal, but >>>> to be useful it just needs to beat software rendering by a wide margin, >>>> and not cause data corruption or vulnerabilities. >>> That should still easily be the case, even trivial use cases are multiple magnitudes faster on GPUs compared to software rendering. >> Makes sense.  If only GPUs supported easy and flexible virtualization the way CPUs do :(. >> >>>>>>> But I have one question: When XEN has a problem handling faults from the guest on the host then how does that work for system memory mappings? >>>>>>> >>>>>>> There is really no difference between VRAM and system memory in the handling for the GPU driver stack. >>>>>>> >>>>>>> Regards, >>>>>>> Christian. >>>>>> Generally, Xen makes the frontend (usually an unprivileged VM) >>>>>> responsible for providing mappings to the backend (usually the host). >>>>>> That is possible with system RAM but not with VRAM, because Xen has >>>>>> no awareness of VRAM.  To Xen, VRAM is just a PCI BAR. >>>>> No, that doesn't work with system memory allocations of GPU drivers either. >>>>> >>>>> We already had it multiple times that people tried to be clever and incremented the page reference counter on driver allocated system memory and were totally surprised that this can result in security issues and data corruption. >>>>> >>>>> I seriously hope that this isn't the case here again. As far as I know XEN already has support for accessing VMAs with VM_PFN or otherwise I don't know how driver allocated system memory access could potentially work. >>>>> >>>>> Accessing VRAM is pretty much the same use case as far as I can see. >>>>> >>>>> Regards, >>>>> Christian. >>>> The Xen-native approach would be for system memory allocations to >>>> be made using the Xen driver and then imported into the virtio-GPU >>>> driver via dmabuf.  Is there any chance this could be made to happen? >>> That could be. Adding Pierre-Eric to comment since he knows that use much better than I do. >>> >>>> If it's a lost cause, then how much is the memory overhead of pinning >>>> everything ever used in a dmabuf?  It should be possible to account >>>> pinned host memory against a guest's quota, but if that leads to an >>>> unusable system it isn't going to be good. >>> That won't work at all. >>> >>> We have use cases where you *must* migrate a DMA-buf to VRAM or otherwise the GPU can't use it. >>> >>> A simple scanout to a monitor is such an use case for example, that is usually not possible from system memory. >> Direct scanout isn't a concern here. >> >>>> Is supporting page faults in Xen the only solution that will be viable >>>> long-term, considering the tolerance for very substantial performance >>>> overheads compared to native?  AAA gaming isn't the initial goal here. >>>> Qubes OS already supports PCI passthrough for that. >>> We have AAA gaming working on XEN through native context working for quite a while. >>> >>> Pierre-Eric can tell you more about that. >>> >>> Regards, >>> Christian. >> I've heard of that, but last I checked it required downstream patches >> to Xen, Linux, and QEMU.  I don't know if any of those have been >> upstreamed since, but I believe that upstreaming the Xen and Linux >> patches (or rewriting them and upstreaming the rewritten version) would >> be necessary.  Qubes OS (which I don't work for anymore but still want >> to help with this) almost certainly won't be using QEMU for GPU stuff. > > Yeah, our plan is to use xen-vhost-frontend[1] + vhost-device-gpu, ported/extended/modified as necessary. (I already have xen-vhost-frontend itself working on amd64 PVH with purely xenbus-based hotplug/configuration, currently working on cleaning up and submitting the necessary patches.) > > I'm curious to hear more details about how AMD has it working but last time I checked, there weren't any missing pieces in Xen or Linux that we'd need.. The AMD downstream changes were mostly related to QEMU. > > As for the memory management concerns, I would like to remind everyone once again that the pinning of GPU dmabufs in regular graphics workloads would be *very* short-term. In GPU paravirtualization (native contexts or venus or whatever else) the guest mostly operates on *opaque handles* that refer to buffers owned by the host GPU process. The typical rendering process (roughly) only involves submitting commands to the GPU that refer to memory using these handles. Only upon mmap() would a buffer be pinned/granted to the guest, and those are typically only used for *uploads* where the guest immediately does its memcpy() and unmaps the buffer. No that is not correct at all. CPU mapping a buffers for GPUs are pretty much permanent through the whole lifetime of the buffer. Otherwise you can completely forget running any halve way modern workloads. > So I'm not worried about (unintentionally) pinning too much GPU driver memory. > > In terms of deliberate denial-of-service attacks from the guest to the host, the only reasonable response is: > > ¯\_(ツ)_/¯ > > CPU-mapping lots of GPU memory is far from the only DoS vector, the GPU commands themselves can easily wedge the GPU core in a million ways (and last time I checked amdgpu was noooot so good at recovering from hangs). Yeah that is certainly true :) Regards, Christian. > > > [1]: https://github.com/vireshk/xen-vhost-frontend > > ~val > From xen-devel-bounces@lists.xenproject.org Tue Apr 21 18:42:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 18:42:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289287.1569400 (Exim 4.92) (envelope-from ) id 1wFG3R-0000aS-FH; Tue, 21 Apr 2026 18:42:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289287.1569400; Tue, 21 Apr 2026 18:42:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFG3R-0000aL-CM; Tue, 21 Apr 2026 18:42:37 +0000 Received: by outflank-mailman (input) for mailman id 1289287; Tue, 21 Apr 2026 18:42:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFG3Q-0000aF-Jy for xen-devel@lists.xenproject.org; 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I've = fixed=0A= this in my working branch by adding a new arch-specific function,=0A= altp2m_deactivate_altp2m, which both calls altp2m_reset_altp2m and sets the= =0A= views as invalid by setting the eptp/visible_eptp values to INVALID_MFN on = x86,=0A= and sets the altp2m_state value to ALTP2M_INVALID on ARM.=0A= =0A= A side effect of this is that altp2m_reset_altp2m doesn't actually need to = be=0A= callable from common code anymore, so the concern I raised previously about= =0A= ARM's altp2m_reset_altp2m implementation needing a useless altp2m_reset_typ= e=0A= parameter is no longer an issue. altp2m_reset_altp2m is used in=0A= altp2m_propagate_change however, so this issue might pop back up later.= From xen-devel-bounces@lists.xenproject.org Tue Apr 21 19:33:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 19:33:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289304.1569410 (Exim 4.92) (envelope-from ) id 1wFGqu-0008VM-7P; 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a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776800020; x=1808336020; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=EodzOw099fBLPHA+FoPk6IybrQpy3PL/jN5TTS/wIZM=; b=HnPfWDarnevhbmxhtAS/mLv3pYI2maYxKC7RHp2sZwfpDN55H2Kan2Ml GoAXU4X0cAfneIfp5v0Z/Y1RN0tsILmUVsmWxGhN/3vmWQQYdDGJcegw6 mYR0kEk+rj2E8beBOaClsJgTPZc0ZE/0FYhRpzsl2KwScZwOZnpAU0BYQ 68nX8i6Mc7W8RkOUishSbzeQiHPlfe8Jaw3wzgSJgNJhX9XI6oD9RiqzI yWyHbv1/FjNNFVqEkA7oiMjbksDXl4mU2g5GmphMCqLIczaK748bu33x7 VoqoXowH+q811r78wN5a20Uvy65ovGzkn0aAl29E6T9AWf7RGCt5j7+Mi A==; X-CSE-ConnectionGUID: rJUJfUqqSMSZocOybOL/fg== X-CSE-MsgGUID: iatpzdGxTbGb91jGuXZ9Zw== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="76780802" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="76780802" X-CSE-ConnectionGUID: ljT4FAQ4RNGrLowVQzmhyw== X-CSE-MsgGUID: 0Yl7qQdVRAutyyQJGhYAig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="233904186" Date: Wed, 22 Apr 2026 03:33:26 +0800 From: kernel test robot To: zhaoguohan@kylinos.cn, jgross@suse.com, sstabellini@kernel.org Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, oleksandr_tyshchenko@epam.com, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, GuoHan Zhao Subject: Re: [PATCH] xen/manage: unwind partial shutdown watcher setup on error Message-ID: <202604220332.2gWBxnrF-lkp@intel.com> References: <20260407022443.12971-1-zhaoguohan@kylinos.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260407022443.12971-1-zhaoguohan@kylinos.cn> X-purgate-ID: tlsNG-16d1c6/1776800020-90C7BD75-836F12F8/0/0 X-purgate-type: clean X-purgate-size: 2766 Hi, kernel test robot noticed the following build warnings: [auto build test WARNING on v7.0] [cannot apply to xen-tip/linux-next linus/master next-20260421] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/zhaoguohan-kylinos-cn/xen-manage-unwind-partial-shutdown-watcher-setup-on-error/20260416-185003 base: v7.0 patch link: https://lore.kernel.org/r/20260407022443.12971-1-zhaoguohan%40kylinos.cn patch subject: [PATCH] xen/manage: unwind partial shutdown watcher setup on error config: arm64-randconfig-001-20260421 (https://download.01.org/0day-ci/archive/20260422/202604220332.2gWBxnrF-lkp@intel.com/config) compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 5bac06718f502014fade905512f1d26d578a18f3) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260422/202604220332.2gWBxnrF-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202604220332.2gWBxnrF-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/xen/manage.c:380:1: warning: unused label 'err_unregister_shutdown' [-Wunused-label] 380 | err_unregister_shutdown: | ^~~~~~~~~~~~~~~~~~~~~~~~ 1 warning generated. vim +/err_unregister_shutdown +380 drivers/xen/manage.c 353 354 for (idx = 0; idx < ARRAY_SIZE(shutdown_handlers); idx++) { 355 if (!shutdown_handlers[idx].flag) 356 continue; 357 snprintf(node, FEATURE_PATH_SIZE, "feature-%s", 358 shutdown_handlers[idx].command); 359 err = xenbus_printf(XBT_NIL, "control", node, "%u", 1); 360 if (err) { 361 pr_err("%s: Error %d writing %s\n", __func__, 362 err, node); 363 goto err_remove_features; 364 } 365 } 366 367 return 0; 368 369 err_remove_features: 370 while (--idx >= 0) { 371 if (!shutdown_handlers[idx].flag) 372 continue; 373 snprintf(node, FEATURE_PATH_SIZE, "feature-%s", 374 shutdown_handlers[idx].command); 375 xenbus_rm(XBT_NIL, "control", node); 376 } 377 #ifdef CONFIG_MAGIC_SYSRQ 378 unregister_xenbus_watch(&sysrq_watch); 379 #endif > 380 err_unregister_shutdown: 381 unregister_xenbus_watch(&shutdown_watch); 382 return err; 383 } 384 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki From xen-devel-bounces@lists.xenproject.org Tue Apr 21 20:50:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 20:50:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289354.1569417 (Exim 4.92) (envelope-from ) id 1wFI3A-0003i6-Gv; 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d=kernel.org; s=k20201202; t=1776804623; bh=Fec1iEqDKYnxd6w5Ro5mBeDLbHPHRYMts/hOlSeHe5w=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=kBRlwtk7qsxs2+Mx6JxLl/9NAOwQ65OiNOke71tpNJxJu65MTW20SgLeBng4bRC68 5Qw1S4vRi7S50sNBMqjiWlXVQwr0VqakJvIBS8cx0zsCedWgXwNGebI7a6Fi26GhmC Jj7KdXd/23Dw6EOisXa9TgLZh6GFJFvU9gmeIGUOMCJjMBxT7Gvvo12bUE3dkW/fhZ kP2YA43oGq8hr86kMF+oIScr0Y7iwSeQrxeclSiSWKtwb+xWhRsYFKWCj/DOfE8PVv tzVvfiQlx6dRQNvFMB5UPX1ckMe9FxfI3iwOVlaIKXIr6UKTgL+QXFyJM5UdRdgidx Ql1gV3v1yRDyA== Date: Tue, 21 Apr 2026 13:50:20 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: "Orzel, Michal" , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH] device-tree: Improve hwdom memory allocation for DMA In-Reply-To: <78440FF6-499A-4997-AA60-AB7EEC6AF67E@arm.com> Message-ID: References: <20260417091155.39653-1-michal.orzel@amd.com> <412A9DF8-6F5C-402D-AEBD-88E6DE139E07@arm.com> <137bd391-926d-4047-a760-638f2e58b99f@amd.com> <78440FF6-499A-4997-AA60-AB7EEC6AF67E@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-833083000-1776804623=:2712345" X-purgate-ID: tlsNG-ef75cf/1776804626-AF374C48-B981353B/0/0 X-purgate-type: clean X-purgate-size: 1078 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-833083000-1776804623=:2712345 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Tue, 21 Apr 2026, Luca Fancellu wrote: > >> It looks ok to me, the only thing is that if we have many smaller banks < 128 Mb before reaching > >> one that is at least 128 Mb, we won’t allocate them and loose them forever. > >> > >> It feels only a corner case so for me it’s ok > > Yes, that's something documented in the commit msg, so if we ever face upon the > > issue due to that we could revisit the implementation. For now, we haven't > > observed any issues. > > > >> > >> Reviewed-by: Luca Fancellu > > > Thanks. > > I realised my mail client messed up the tag: > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini --8323329-833083000-1776804623=:2712345-- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 20:51:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 20:51:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289361.1569426 (Exim 4.92) (envelope-from ) id 1wFI44-0004A3-Oy; Tue, 21 Apr 2026 20:51:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289361.1569426; Tue, 21 Apr 2026 20:51:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFI44-00049w-MI; Tue, 21 Apr 2026 20:51:24 +0000 Received: by outflank-mailman (input) for mailman id 1289361; Tue, 21 Apr 2026 20:51:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFI43-00049k-MK for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 20:51:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFI43-004mvp-3C for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:51:23 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7e304-5cb7-0a2a0a5109dd-0a2a4501af86-48 for ; Tue, 21 Apr 2026 22:51:23 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7e34a-c1f2-0a2a45010019-ac6904fe9c60-3 for ; Tue, 21 Apr 2026 22:51:22 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 5CC4E61335; Tue, 21 Apr 2026 20:51:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC88EC2BCB0; Tue, 21 Apr 2026 20:51:20 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776804681; bh=gRmE5P/xqA0B49fPpP73v8SZCSrWIw7Xn5tY9bP7e3o=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=fl9IN31nX8VMmbis2euxwy9B92RizBapt/fGy2jMJzJ4h90pIXZxx3CtrZpbXKPBP 9jXbgFKqxxEofueIMM1I+uwELGFz+zxY/v1FhQmM4SYsgAjNsD9T3Ieosz4BpeLXck lncoXgGBS53we36i8xHgNSkgbNf6TMYeVPGWYBztjyV0ks2fVtpwjUqVECSz1aItIj 7X6ZB0WPQfFTPsqRWkYNBRI4ar1VgZWhcTX/5sk5ell9F3dEwWq9MHRoYd+8PFb9wV g/ybMD9I4jYIpWRnbnd11894qGz2KjRZUYCjeIHuJTQB0Om0xdszZGfzlQqpsexvL6 4uFcd+iSwwhQA== Date: Tue, 21 Apr 2026 13:51:20 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: "Orzel, Michal" , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH] xen/arm: skip holes in physical address space when setting up frametable In-Reply-To: Message-ID: References: <20260417091124.39552-1-michal.orzel@amd.com> <10ef543f-ec21-47ae-aeb2-f569f8d48e27@amd.com> <6a6aefa7-530b-4221-b2b3-65ca3298aef1@amd.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-768840311-1776804681=:2712345" X-purgate-ID: tlsNG-d62444/1776804683-BCC6CFF4-0DBDB590/0/0 X-purgate-type: clean X-purgate-size: 793 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-768840311-1776804681=:2712345 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Tue, 21 Apr 2026, Luca Fancellu wrote: > >> Otherwise we could split the round down and the frametable_base_pdx in this way maybe? > > I don't think we need this extra complexity for something that is safe and has > > always been in use. We've never had mfn_valid == RAM guarantee. > > Thanks for checking my points, I think it’s all clear to me now. > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini --8323329-768840311-1776804681=:2712345-- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:16:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:16:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289503.1569435 (Exim 4.92) (envelope-from ) id 1wFJNo-0008ET-Do; Tue, 21 Apr 2026 22:15:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289503.1569435; Tue, 21 Apr 2026 22:15:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJNo-0008EM-Av; Tue, 21 Apr 2026 22:15:52 +0000 Received: by outflank-mailman (input) for mailman id 1289503; Tue, 21 Apr 2026 22:15:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJNm-0008EG-RT for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:15:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJNm-004wr3-4u for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:15:50 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f713-e002-0a2a0a5209dd-0a2a4501e340-2 for ; Wed, 22 Apr 2026 00:15:50 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f714-c1f2-0a2a45010019-aceafc1faaa0-3 for ; Wed, 22 Apr 2026 00:15:49 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id D0B924398A; Tue, 21 Apr 2026 22:15:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7C38AC2BCB0; Tue, 21 Apr 2026 22:15:47 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809747; bh=NfBjnF3RMsUTEmScq9PdBZRS6CXEDdg+7HmbQnO8qxo=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=R2bYwOXyngl7K8YMlwELC+H3KmwMPxDNGPvAnwtynguqOQLPwx0rEmH+fRKumO7+H iDWROpX0Qc91c3+KZq/1QDz0FzBU6q7H0O0T2NQ9Ybq7l9PFAeOGx0aS7Jkfanx2+o y2vUnnV424ZqgVusAhXqlcAKeWswdbO0fuURUIgRrN5rboJLT+aqnkQJptyRB+SmxD M4FNIqxLmpnDfz6dUmPYuBWjavgWolv7wpnSIeJCqvejWkHZgFiE6At8aCtPS5SKMD CazwAbbxj584SiM49PRLUYOW9YqhJ5uMCXW3SPHeBQogSlr3WwtEsaS8q+4XrMAjlO hnz4oWHY6GHjg== Date: Tue, 21 Apr 2026 15:15:44 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Thomas Huth cc: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] xen/arm: Replace __ASSEMBLY__ with __ASSEMBLER__ in interface.h In-Reply-To: <20260421142701.548978-1-thuth@redhat.com> Message-ID: References: <20260421142701.548978-1-thuth@redhat.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-d62444/1776809750-BD66FFF4-29793DDF/0/0 X-purgate-type: clean X-purgate-size: 1743 On Tue, 21 Apr 2026, Thomas Huth wrote: > From: Thomas Huth > > While the GCC and Clang compilers already define __ASSEMBLER__ > automatically when compiling assembly code, __ASSEMBLY__ is a > macro that only gets defined by the Makefiles in the kernel. > This can be very confusing when switching between userspace > and kernelspace coding, or when dealing with uapi headers that > rather should use __ASSEMBLER__ instead. So let's standardize now > on the __ASSEMBLER__ macro that is provided by the compilers. > > Signed-off-by: Thomas Huth I haven't been closely following the __ASSEMBLER__ vs __ASSEMBLY__ discussion. If there is general agreement to use __ASSEMBLER__ in headers, I am happy to go along with that. Currently, I see more than 140 uses of __ASSEMBLY__ compared to fewer than 20 uses of __ASSEMBLER__, but I'll defer to your judgment if the project is moving in that direction. > --- > Note: This patch has been split from an earlier patch series of mine > to ease reviewing. > > include/xen/arm/interface.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/xen/arm/interface.h b/include/xen/arm/interface.h > index c3eada2642aa9..61360b89da405 100644 > --- a/include/xen/arm/interface.h > +++ b/include/xen/arm/interface.h > @@ -30,7 +30,7 @@ > > #define __HYPERVISOR_platform_op_raw __HYPERVISOR_platform_op > > -#ifndef __ASSEMBLY__ > +#ifndef __ASSEMBLER__ > /* Explicitly size integers that represent pfns in the interface with > * Xen so that we can have one ABI that works for 32 and 64 bit guests. > * Note that this means that the xen_pfn_t type may be capable of > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:17:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:17:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289511.1569445 (Exim 4.92) (envelope-from ) id 1wFJPL-0000g7-Mi; Tue, 21 Apr 2026 22:17:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289511.1569445; Tue, 21 Apr 2026 22:17:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPL-0000g0-K1; Tue, 21 Apr 2026 22:17:27 +0000 Received: by outflank-mailman (input) for mailman id 1289511; Tue, 21 Apr 2026 22:17:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPK-0000IM-Ml for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:17:26 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJPH-00FslP-TK for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:17:23 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f6ec-5cb7-0a2a0a5109dd-0a2a450285d8-48 for ; Wed, 22 Apr 2026 00:17:23 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f772-af86-0a2a45020019-aceafc1fa924-3 for ; Wed, 22 Apr 2026 00:17:23 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id C9D7C4027F; Tue, 21 Apr 2026 22:17:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28B88C2BCB0; Tue, 21 Apr 2026 22:17:21 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809841; bh=xn3A0NuiXervtpsnojkWIHY+IxM7mxFsV2qRaCcwuBw=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=KtkGvelEDf1hG0x8PyI9REg7xzzQaxMRvWbeJOoOnx1VK9XlOV/dnFn9qBOFQSmRX 9JqSmfS+j1Tu48/gjLu+/w1V0p0eEfX0H4KYeJ/RfGnktJ7aCGn/8Kfe6fTif0YHmF ry2VzX72a4Bo7ZmGOZKA8dhKg481w6hqJDtc6Lnr7pFwWsiRau27MzI9eTNPyTZKKU XREwupqJbtttt/HVlvxSP8TGrrFKd3ruUgd+hBE5tMEXJHtLQwzdi5AiDJAOVMWcuR sHuxp1PTJgo8GdYDOHO4Yel17ObEmwI/zQMuGDtDnDP+w87Qtpsr3IeWXGczP8a4q1 fCYMiFIscQ/Jg== Date: Tue, 21 Apr 2026 15:17:20 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Gyujeong Jin Subject: Re: [PATCH 1/6] xen/dt-overlay: fix double-free of rangesets on attach failure In-Reply-To: Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-2-michal.orzel@amd.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-720697/1776809843-82B68161-A53F0E86/0/0 X-purgate-type: clean X-purgate-size: 1002 On Wed, 15 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 15 Apr 2026, at 12:36, Michal Orzel wrote: > > > > handle_attach_overlay_nodes() destroys the IRQ and IOMEM rangesets on > > failure but leaves the pointers dangling in the tracker entry. A > > subsequent handle_remove_overlay_nodes() for the same overlay will call > > rangeset_consume_ranges() on freed memory followed by a second > > rangeset_destroy(), resulting in use-after-free and double-free. > > > > NULL the pointers after rangeset_destroy() so that remove_nodes() and > > handle_remove_overlay_nodes() skip the stale entries. > > > > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains") > > Reported-by: Gyujeong Jin > > Signed-off-by: Michal Orzel > > --- > > Looks ok to me > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:17:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:17:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289513.1569454 (Exim 4.92) (envelope-from ) id 1wFJPW-0000xi-UH; Tue, 21 Apr 2026 22:17:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289513.1569454; Tue, 21 Apr 2026 22:17:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPW-0000xb-QJ; Tue, 21 Apr 2026 22:17:38 +0000 Received: by outflank-mailman (input) for mailman id 1289513; Tue, 21 Apr 2026 22:17:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPV-0000x3-LV for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:17:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJPV-004wxQ-2Z for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:17:37 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f77a-e002-0a2a0a5209dd-0a2a4505a99a-4 for ; Wed, 22 Apr 2026 00:17:37 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f77f-aaa8-0a2a45050019-aceafc1fbc22-3 for ; Wed, 22 Apr 2026 00:17:36 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 5415840ABC; Tue, 21 Apr 2026 22:17:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D5D01C2BCB0; Tue, 21 Apr 2026 22:17:34 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809855; bh=vXU7Zt2l4M8G60BE1c8ZN9B628h/QdmUsGy42HqenXo=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=FNdtPAUoIer4gcLCjIByRdrBvDT6mt2BUhuh9N7PzxY3Bm6MNQblen6BwAv0C+wga EWIpZR5P/KaWuWN2ETOoR7dM7HeumTUPg/2ywgYZHflZMNlTUF1q5XEdWBfarAdR/U d1JZi3n17cyy/3YatGNfLk/CEVrhf0aUIw4nvgpZvNS0RYEr/jP61YgLMFMmJrD+Oo MfFimqrNMYjjhTSxNxyF6yDH2L7ACDxpWIv7d3EgOSwyvY24rbpJcbU8MDGshz2vc4 M7jVq+yarMY0t2+R2dILVK0ZzIEn6ZUK1zYrWUtqqgcv1IA4ZuRGX4yIlQSLTFGDaj 5daxqncPX/U+g== Date: Tue, 21 Apr 2026 15:17:34 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Jan Beulich Subject: Re: [PATCH 2/6] xen/dt-overlay: fix rangeset leak and dead code in domctl path In-Reply-To: <33C5577E-F6AE-4FC2-BE53-879BA4EB6198@arm.com> Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-3-michal.orzel@amd.com> <33C5577E-F6AE-4FC2-BE53-879BA4EB6198@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-c201ff/1776809857-E8BAC443-83659651/0/0 X-purgate-type: clean X-purgate-size: 939 On Wed, 15 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 15 Apr 2026, at 12:36, Michal Orzel wrote: > > > > handle_attach_overlay_nodes() unconditionally creates new rangesets > > without checking whether they already exist from a prior attach. A > > repeated attach for the same overlay leaks the original pair. Reject the > > operation with -EEXIST if rangesets are already present. > > > > Also, dt_overlay_domctl() early-returns -EOPNOTSUPP for any operation > > other than ATTACH, making the if/else at the bottom unreachable. Remove > > the dead branch. > > > > Fixes: 4c733873b5c2 ("xen/arm: Add XEN_DOMCTL_dt_overlay and device attachment to domains") > > Reported-by: Jan Beulich > > Signed-off-by: Michal Orzel > > --- > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:17:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:17:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289521.1569462 (Exim 4.92) (envelope-from ) id 1wFJPi-0001Pk-7y; Tue, 21 Apr 2026 22:17:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289521.1569462; Tue, 21 Apr 2026 22:17:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPi-0001Pd-53; Tue, 21 Apr 2026 22:17:50 +0000 Received: by outflank-mailman (input) for mailman id 1289521; Tue, 21 Apr 2026 22:17:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPh-0001PC-PE for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:17:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJPh-000y8Y-5r for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:17:49 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f767-e002-0a2a0a5209dd-0a2a450abba8-16 for ; Wed, 22 Apr 2026 00:17:49 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f78b-56b3-0a2a450a0019-aceafc1fa868-3 for ; Wed, 22 Apr 2026 00:17:48 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 6C3BE4171F; Tue, 21 Apr 2026 22:17:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D3DFC2BCB0; Tue, 21 Apr 2026 22:17:47 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809867; bh=LPo7tVyH/24wj01Stx7zcbN5lhedJIwpaXTZlSeA/dM=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=nnyuU6QspuxnUbGajZmzv9QgzBbvfcz4RSflKs2crXmSSFgCZu8Vep4o6mj7taCm9 VCdv92qVvINYDxC0dC2QKBQPCbpy43OcBAA0T9Uv7HBTESKoTSPg39vb0/C/iCDSZ5 2PjtFUctBMofjhm28m0Uz1OheuzKlQPhvjIa6eFjw9JE5eEriWoTNSazPjSCVpgw1P KRWB1jRKyfahdt2mOxumLydHyEc+eBXYRRGO1qcdNAhlhfZUNY1o8u3WVdExKdSotB 7HJ/zHkRzBdgILXyEdIBURhM6EiUxLggf2nkxz6noc6ULiBab/gQ9e/qA+jXOKZ/8A dW5+dnU0We6IA== Date: Tue, 21 Apr 2026 15:17:46 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH 3/6] xen/dt-overlay: check overlay size before memcmp in tracker lookup In-Reply-To: Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-4-michal.orzel@amd.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-4011c0/1776809869-44F618B7-82C6F0C9/0/0 X-purgate-type: clean X-purgate-size: 964 On Wed, 15 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 15 Apr 2026, at 12:36, Michal Orzel wrote: > > > > find_track_entry_from_tracker() compares overlay_fdt_size bytes of the > > stored overlay against the input without verifying that the stored > > overlay is at least that large. If the input is larger, memcmp reads > > past the stored allocation. If smaller, a prefix match could falsely > > succeed. > > > > Compare fdt_totalsize() of the stored overlay against overlay_fdt_size > > first. Both values are validated by check_overlay_fdt() at their > > respective entry points, so no additional field in overlay_track is > > needed. > > > > Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functionalities") > > Signed-off-by: Michal Orzel > > --- > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:18:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:18:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289529.1569472 (Exim 4.92) (envelope-from ) id 1wFJPs-0001t6-Fq; Tue, 21 Apr 2026 22:18:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289529.1569472; Tue, 21 Apr 2026 22:18:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPs-0001sv-CR; Tue, 21 Apr 2026 22:18:00 +0000 Received: by outflank-mailman (input) for mailman id 1289529; Tue, 21 Apr 2026 22:17:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJPr-0001qx-CA for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:17:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJPq-00CV3J-PU for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:17:58 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f774-bab6-0a2a0a5309dd-0a2a4502dd44-22 for ; Wed, 22 Apr 2026 00:17:58 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f795-af86-0a2a45020019-ac6904febb14-3 for ; Wed, 22 Apr 2026 00:17:58 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 4A45161335; Tue, 21 Apr 2026 22:17:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9617C2BCB0; Tue, 21 Apr 2026 22:17:56 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809877; bh=J9vaM3OKaCkqhTApqyllVmpe1yCscLm46h/f+zHtfjE=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=QsfthhKFZc4jFzf4IQB7RQYeI52PkWCTCojBlyBFd/xsOICz1L921HShVeRLl5h19 WRX87wCY0iT9XVoI6bCUNDxXwAfSMmU1Vt7DU+zoWrXJSeN8Udz870zLiQjbN3K92/ wGh0G7Cp9ziExB20h1/vVEKeDnMsTK2VfME0nmF3M3bnAmQ8/il6FQI2tJrsSWAlxr qOYjpI3wwIVUfII0VdM+KzFFaNmaQoLLo0grLyvCC7ORA1763GWJgdWIGT1zgWmYnW 7oWjdb7JrRcahhPex9wksibOYTx6W6qRGwqcR+gI51wYOK8JscQGTiY63AzWaXoISQ L0lYybZONX1Fw== Date: Tue, 21 Apr 2026 15:17:56 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH 4/6] xen/dt-overlay: fix silent success in dt_overlay_remove_node In-Reply-To: <30CCBA3C-D43C-4516-9DB7-9333428AE277@arm.com> Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-5-michal.orzel@amd.com> <30CCBA3C-D43C-4516-9DB7-9333428AE277@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-720697/1776809878-83B60161-B5CB9EEB/0/0 X-purgate-type: clean X-purgate-size: 872 On Wed, 15 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 15 Apr 2026, at 12:36, Michal Orzel wrote: > > > > dt_overlay_remove_node() silently returns 0 when the target node is not > > found in the parent's sibling list. The loop simply exits without > > matching and falls through to "return 0", making the caller believe the > > node was successfully removed. > > > > Return -ENODEV after the loop when no match is found, and change the > > found-path from break to an explicit return 0 so the two outcomes are > > distinct. > > > > Fixes: 7e5c4a8b86f1 ("xen/arm: Implement device tree node removal functionalities") > > Signed-off-by: Michal Orzel > > --- > > Looks ok to me > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:18:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:18:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289544.1569481 (Exim 4.92) (envelope-from ) id 1wFJQ7-0002Uo-My; Tue, 21 Apr 2026 22:18:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289544.1569481; Tue, 21 Apr 2026 22:18:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJQ7-0002Uh-Jb; Tue, 21 Apr 2026 22:18:15 +0000 Received: by outflank-mailman (input) for mailman id 1289544; Tue, 21 Apr 2026 22:18:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJQ6-0002RD-5o for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:18:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJQ5-00CV3J-Iw for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:18:13 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f795-bab6-0a2a0a5309dd-0a2a450cc294-16 for ; Wed, 22 Apr 2026 00:18:13 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f7a4-62f1-0a2a450c0019-aceafc1f8c9a-3 for ; Wed, 22 Apr 2026 00:18:13 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 921DD442F6; Tue, 21 Apr 2026 22:18:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 40D2FC2BCB0; Tue, 21 Apr 2026 22:18:11 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809891; bh=2xeBObuedmJATaRuUNLkyPnDkO0LC0/L6UFg5lUnibI=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=ryPDxwZGTu0dKSqz6U10NYCRcfQ7FTiz80TfcN8ceh1r3zXykUeLEhqSJK6rwlROE oE9ES3QGJ2XfWm5341uSLnuOnRUe0Iku5m5nA4Y2zj+vpQWq5lUjWgwd7ho6OJraWX +9fsMvzXUFtANqGDuj6MNIOuEd5nwhkWmk7fCmTpnxUVvjENp+wq9qe43qV4WKeMRg CgMivQSG8zlsdeQklXt5cfMTgTQTN2vEp8sQYXEbqjbnQL/P7NjcTUNB3vfqo2ox+6 uK3IvD6SAXmt0i2upZaY7+Q4vympL62s5TdGyZorhYBLBKEIT4IkR3ItKDo9OQJ/3y 6+83NCuKaPjSA== Date: Tue, 21 Apr 2026 15:18:10 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: "Orzel, Michal" , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH 5/6] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info In-Reply-To: <2CD46F3B-C978-47F3-ACBC-BF2F39985B42@arm.com> Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-6-michal.orzel@amd.com> <519E2133-12B9-4E51-A7A5-FDBADF82159E@arm.com> <1ab0c888-e890-490e-adad-938222f31a62@amd.com> <6E811F82-6F9F-4894-B2A3-03AA166E78F4@arm.com> <2CD46F3B-C978-47F3-ACBC-BF2F39985B42@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-2027018740-1776809891=:2712345" X-purgate-ID: tlsNG-d25034/1776809893-6FB7CCF5-2F89B701/0/0 X-purgate-type: clean X-purgate-size: 745 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-2027018740-1776809891=:2712345 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Thu, 16 Apr 2026, Luca Fancellu wrote: > >> Ok, do we also want to print a warning in case of malformed properties instead > >> of ignoring and continue? > > That's really a matter of taste. I would not do it unless you really want to. > > I’ll leave this to the other maintainer, with the fix above: > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini --8323329-2027018740-1776809891=:2712345-- From xen-devel-bounces@lists.xenproject.org Tue Apr 21 22:18:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 22:18:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289552.1569489 (Exim 4.92) (envelope-from ) id 1wFJQI-0002uy-UC; Tue, 21 Apr 2026 22:18:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289552.1569489; Tue, 21 Apr 2026 22:18:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJQI-0002ur-RX; Tue, 21 Apr 2026 22:18:26 +0000 Received: by outflank-mailman (input) for mailman id 1289552; Tue, 21 Apr 2026 22:18:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFJQH-0002tW-4A for xen-devel@lists.xenproject.org; Tue, 21 Apr 2026 22:18:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFJQG-00CVAL-HN for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 00:18:24 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e7f774-bab6-0a2a0a5309dd-0a2a4502dd44-44 for ; Wed, 22 Apr 2026 00:18:24 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e7f7af-af86-0a2a45020019-aceafc1fc04c-3 for ; Wed, 22 Apr 2026 00:18:24 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id BC30D44346; Tue, 21 Apr 2026 22:18:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BED6C2BCB0; Tue, 21 Apr 2026 22:18:22 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776809902; bh=xY5cI7DXMyU9Nx2r71/2aeXZWERBlGLgKOcoLddlEAY=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=J+8PdrNNgP2NOr9wFVWGRxTvihCzC05lYl5/sncLZI3U2ASpYR+6L5S8FYYizI3VE EzoinrKsC/IWeIqUt55qxs8dZAqg8m9U7a+p36VnMoPRVzRtXUFhvwtqQyzTo2sGz9 0YdqrsKX4tfDhnOv93bJpDvY9m7qfMe3/y3q3k2mCfOrTqY58KODoCbaDpzslciiC4 Bl06feLTkzBJAD4Qq/QFBMZpIyGjUzWC4IYRlR27YJgpMzVGQmjRP0YL8IZJjO+UNc UHzFnI+QrKBcTPMF0j5oAPppTzulXulcC6reOx5V06mEQ/xoG0uzaEAdAx1qcOWTBz x4Mpkt+sVLS3Q== Date: Tue, 21 Apr 2026 15:18:21 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Luca Fancellu cc: Michal Orzel , "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis Subject: Re: [PATCH 6/6] xen/dt-overlay: attach resources for child nodes in overlay In-Reply-To: <399078B8-E138-4689-AF98-8BDC6052C080@arm.com> Message-ID: References: <20260415113700.107915-1-michal.orzel@amd.com> <20260415113700.107915-7-michal.orzel@amd.com> <399078B8-E138-4689-AF98-8BDC6052C080@arm.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-720697/1776809904-8137C161-35518EB2/0/0 X-purgate-type: clean X-purgate-size: 1224 On Wed, 15 Apr 2026, Luca Fancellu wrote: > Hi Michal, > > > On 15 Apr 2026, at 12:37, Michal Orzel wrote: > > > > handle_attach_overlay_nodes() only calls handle_device() on the > > top-level overlay nodes tracked in entry->nodes_address[]. Child nodes > > that have their own reg, interrupts, or iommus properties are never > > processed, so their IRQs are not routed, MMIO regions are not mapped, > > and IOMMU setup is skipped. > > > > Introduce handle_device_and_children() which recursively walks the > > subtree rooted at each overlay node and calls handle_device() on every > > descendant, ensuring all resources in the overlay are properly attached. > > > > Note that the attach error path has a pre-existing bug: on partial > > failure, the tracking rangesets are destroyed without first revoking the > > IRQ/MMIO permissions and IOMMU assignments that were already granted by > > the successful handle_device() calls. Add a TODO comment to flag this. > > > > Signed-off-by: Michal Orzel > > --- > > > > Looks ok to me > > Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini From xen-devel-bounces@lists.xenproject.org Tue Apr 21 23:42:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 21 Apr 2026 23:42:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289702.1569498 (Exim 4.92) (envelope-from ) id 1wFKj4-0000WA-KW; Tue, 21 Apr 2026 23:41:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289702.1569498; Tue, 21 Apr 2026 23:41:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFKj4-0000W3-Hn; Tue, 21 Apr 2026 23:41:54 +0000 Received: by outflank-mailman (input) for mailman id 1289702; Tue, 21 Apr 2026 23:41:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFKj2-0000Vw-MB for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 02:03:01 +0200 Received: from [136.143.188.12] (helo=sender4-op-o12.zoho.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e81033-229c-0a2a45070019-888fbc0c433e-3 for ; Wed, 22 Apr 2026 02:03:01 +0200 Received: by mx.zohomail.com with SMTPS id 1776816174730416.17740676882624; Tue, 21 Apr 2026 17:02:54 -0700 (PDT) Received: by mail-oa1-f41.google.com with SMTP id 586e51a60fabf-40974bf7781so4567563fac.0 for ; Tue, 21 Apr 2026 17:02:54 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=zmail header.d=tklengyel.com header.i="tamas@tklengyel.com" header.h="MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Content-Type" ARC-Seal: i=1; a=rsa-sha256; t=1776816177; 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bh=zd1lEyRoFzTLgQItSNg7tNN3pcIh4yEX3S7ffIydiQA=; b=TGAKTmlXQTmlDVWVPVPJykUgLf/ts6wjvLOiV5totqIfKLirECauU8X8Jy91m+59 j2uIIGrYxBvcuyeBo9c3aNmTE/HcvBLTIx/8H5xw3Y+eMi0oaKGyT4z9uYGJRQB4Cw/ vRBz1itX3YNgMo1/Y+xWuXrq9yclRytaueG3SbyY= X-Gm-Message-State: AOJu0Yxfd83/eGrC53x9AZVhjPWCLWNtRxVEUgxDSjxMA3iqdkfhDqhh QG7TbyLYiiD3g5HUDW45QUEWJ+9Y+l5TxuYxMA2e2twcVPCySNIjd5kbzrgTUkKQogAH4ieH1qi HJukd83i8LM3KPlNjekTQFwUhoYnGqMk= X-Received: by 2002:a05:6870:a793:b0:41c:9797:d1e6 with SMTP id 586e51a60fabf-42a99ab682bmr9703095fac.14.1776816173961; Tue, 21 Apr 2026 17:02:53 -0700 (PDT) MIME-Version: 1.0 References: <20260420213206.208750-1-Rose.Spangler@elektrobit.com> <20260420213206.208750-9-Rose.Spangler@elektrobit.com> In-Reply-To: From: Tamas K Lengyel Date: Tue, 21 Apr 2026 20:02:17 -0400 X-Gmail-Original-Message-ID: X-Gm-Features: AQROBzDXqVm6cwC8bc6fH7GkxSh6NHqMx_eWB2LQdtm-V9_1G1YHiTFScZJ4JC0 Message-ID: Subject: Re: [RFC PATCH v6 08/43] altp2m: Rename p2m_*_altp2m functions and move declarations out of p2m.h To: "Spangler, Rose" Cc: "xen-devel@lists.xenproject.org" , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie Content-Type: multipart/alternative; boundary="000000000000e157ef065001400f" X-purgate-ID: tlsNG-ef75cf/1776816181-ADF6EC48-A70332E5/0/0 X-purgate-type: clean X-purgate-size: 2666 --000000000000e157ef065001400f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Apr 21, 2026 at 10:07=E2=80=AFAM Spangler, Rose < Rose.Spangler@elektrobit.com> wrote: > >The following function names could reasonably drop the _altp2m suffix: > > > > > >> - p2m_get_altp2m -> altp2m_get_altp2m > >> - p2m_set_altp2m -> altp2m_set_altp2m > >> - p2m_reset_altp2m -> altp2m_reset_altp2m > >> - p2m_activate_altp2m -> altp2m_activate_altp2m > > I used these names to try to differentiate between these functions, which > operate on a single altp2m view, and the altp2m_init / altp2m_teardown / > altp2m_flush functions, which operate on all the views of a domain. For > example, > without the suffix I don't think it's necessarily immediately obvious tha= t > "altp2m_activate" or "altp2m_reset" operate on only a single view. How about you add the _view suffix for these? I think it would help disambiguate them and also read better than the current _altp2m suffix ones= . Tamas --000000000000e157ef065001400f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


    On Tue, Apr 21,= 2026 at 10:07=E2=80=AFAM Spangler, Rose <Rose.Spangler@elektrobit.com> wrote:
    >The following function na= mes could reasonably drop the _altp2m suffix:
    >
    >
    >> - p2m_get_altp2m -> altp2m_get_altp2m
    >> - p2m_set_altp2m -> altp2m_set_altp2m
    >> - p2m_reset_altp2m -> altp2m_reset_altp2m
    >> - p2m_activate_altp2m -> altp2m_activate_altp2m

    I used these names to try to differentiate between these functions, which operate on a single altp2m view, and the altp2m_init / altp2m_teardown / altp2m_flush functions, which operate on all the views of a domain. For exa= mple,
    without the suffix I don't think it's necessarily immediately obvio= us that
    "altp2m_activate" or "altp2m_reset" operate on only a s= ingle view.

    How about you add the _view suf= fix for these? I think it would help disambiguate them and also read better= than the current _altp2m suffix ones.

    Tamas=C2=A0=
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[69.131.150.190]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-65314b7d42bsm7570306d50.8.2026.04.21.18.27.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Apr 2026 18:27:16 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="In-Reply-To:Autocrypt:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776821237; x=1777426037; darn=lists.xenproject.org; h=in-reply-to:autocrypt:from:content-language:references:cc:to :subject:user-agent:mime-version:date:message-id:from:to:cc:subject :date:message-id:reply-to; bh=m9fhkqi5RYYYf8jtou/uXhqtRGhljUy8t+WuNuRPkCY=; b=rzMfidDA15UmJCdjN0rcwBzZyjroHG4URCPfmnYrkQdsiRk1PPBYKuw0pb8y5E1XHO QtxSAGUPd4UD8MY1f4DLSntHfURnXy6+uUAEl6I7FukC7xO9zjAYarf3tLeatytccMI3 bDrsaJPqe0foR8bN/XpnmYRAra1qjjd5MYqlNmZwdKB8NMqwjjS1K3TQlDLWiOq4DgKI 5HljS1h3j6fXK+X0hDCWu/ingfc0unEJqr2OzzDZp5lFH8Z1UwniI0tLvelAXXEYytre wcfPeECUb9F3NgBNIp5FjoAIrlaXHjyj9IxL3H+UwpGIyd5ES2q33EjdxIW44G8M3wBN WUsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776821237; x=1777426037; h=in-reply-to:autocrypt:from:content-language:references:cc:to :subject:user-agent:mime-version:date:message-id:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=m9fhkqi5RYYYf8jtou/uXhqtRGhljUy8t+WuNuRPkCY=; b=GcpsjNUQraIfaustIIZE5R8DLRRcntjZS6McumlA7rgmFDi8FIj+ujagdGK6IMznNg JzlUjURtOKNEi6rgPdTIYokSrqIft3NM1k3631SNtjIFwXUqrZcvcjhiTqFdqN2hpfYu Cz9sWHqs6o8u14opDHq9EHvQeG8mZl8zAnvbGp61UvGMA9KrrVGi+pOVW26Y5udFdMVb ot90p6BY2AhHe3nVo7SYoi7rjf/pOvK5rOOTJPUaLfaWdE1nw89peeun9rfdpxJ061VL laK/7hAri7P7xkwb++upon93oxfFH3xBRsvsPesODAJBq4nxef+iT1pdF7HWnEW/bKmV M6bg== X-Forwarded-Encrypted: i=1; AFNElJ9g1+rjw6RcqHii+xmjIUdiGuGes7INWwm9+6Y+RmNckofR2JH+Z1aWY+tr8gIuUGJSRyEMM4x9qwc=@lists.xenproject.org X-Gm-Message-State: AOJu0YzXlO/cinivFmMhlNNGY9AVs47dQ7F+Kv4v0bTb+KLZS6qkaPPy rVP4nZaZMd0Qqxrwqv7+vD7uzhKNQMPJuZ85C/pXcQEdVvygkH4+lmka X-Gm-Gg: AeBDievlnzacmbFU0QvQWVPekRXO3wI59KVFKeJLEG7iv13eShXA+tCaqz/iVSmH+tD e1C39sletfdvDP/avmiAnznRNjh1IiEx0KEMbVwG6Zw+LswODUYK2IGIVZQ3smlhCJETjeiPXjo H7DWn7WywLOSF0AodQ2lkGWY9T+zqwHM9ruLw8cryYbuIIOKp/BIHWDXQA8rTU47GRoVONS99mj U5R9+KkUgwJbR12FHMiTfO8bMTjtq/U28xRldnyI3kJcNk0HXI3p5tRFWQarW4/rGl+aVgPI+vq 6NoA0ppc7kB0hLOvd4xypxjxD17+szVxv1JaWyLnpo3jilENXj3mo2LI9hyzDwsr8cKnn52Iv6R dUlFNe8JoxyC22ugmZ629Zhr9sMdv4bC8jwCjZ2y4TQ9m3mL9JP58Etq/rLvMTmBdDYmDWVf8Gz 2KHckB0fbBt92tY+ac1MVxMwMeDdBKOF0tpOVbYcMGd69ouiSYvodYk6UFsdVwwS3JFhf4fCEq6 dPeyHl9diemFxNue8K5e7dl1JKhBvgGQxOndaOtO5jxCwFGmhbn X-Received: by 2002:a05:690e:4844:b0:650:70da:bc25 with SMTP id 956f58d0204a3-65310b44cfbmr12505506d50.58.1776821237271; Tue, 21 Apr 2026 18:27:17 -0700 (PDT) Message-ID: Date: Tue, 21 Apr 2026 21:27:12 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: Val Packett , =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> <686713fc-c762-4b1b-88b2-d486d4f38ac6@gmail.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------SebHAdj8yxVfqcchjV0gaqoc" X-purgate-ID: tlsNG-c1860d/1776821239-C2B74DB1-65C5C13E/0/0 X-purgate-type: clean X-purgate-size: 21615 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------SebHAdj8yxVfqcchjV0gaqoc Content-Type: multipart/mixed; boundary="------------fCxYjExTx4afN7vZNGscsPeS"; protected-headers="v1" Message-ID: Date: Tue, 21 Apr 2026 21:27:12 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: Val Packett , =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org Cc: Suwit Semal , "Pelloux-Prayer, Pierre-Eric" References: <4751cf03-d3c1-4d5d-af8e-39ad7c8ffb84@amd.com> <7472bfcf-8c22-4ac7-b903-a883cdb8f1c6@gmail.com> <8fe8b78b-5294-4319-af92-a4fb00527417@amd.com> <8846bac5-77ff-4439-ac5c-c33cdb4a94e3@gmail.com> <964c3670-fad3-44ce-bd93-2057bca2dcb8@amd.com> <08ad2301-3163-4497-8869-fa4cea30b384@gmail.com> <686713fc-c762-4b1b-88b2-d486d4f38ac6@gmail.com> Content-Language: en-US From: Demi Marie Obenour Autocrypt: addr=demiobenour@gmail.com; keydata= xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49yB+l2nipd aq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYfbWpr/si88QKgyGSV Z7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/UorR+FaSuVwT7rqzGrTlscnT DlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7MMPCJwI8JpPlBedRpe9tfVyfu3euTPLPx wcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9Hzx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR 6h3nBc3eyuZ+q62HS1pJ5EvUT1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl 5FMWo8TCniHynNXsBtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2 Bkg1b//r6bTBswMBXVJ5H44Qf0+eKeUg7whSC9qpYOzzrm7+0r9F5u3qF8ZTx55TJc2g656C 9a1P1MYVysLvkLvS4H+crmxA/i08Tc1h+x9RRvqba4lSzZ6/Tmt60DPM5Sc4R0nSm9BBff0N m0bSNRS8InXdO1Aq3362QKX2NOwcL5YaStwODNyZUqF7izjK4QARAQABzTxEZW1pIE1hcmll IE9iZW5vdXIgKGxvdmVyIG9mIGNvZGluZykgPGRlbWlvYmVub3VyQGdtYWlsLmNvbT7CwXgE EwECACIFAlp+A0oCGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJELKItV//nCLBhr8Q AK/xrb4wyi71xII2hkFBpT59ObLN+32FQT7R3lbZRjVFjc6yMUjOb1H/hJVxx+yo5gsSj5LS 9AwggioUSrcUKldfA/PKKai2mzTlUDxTcF3vKx6iMXKA6AqwAw4B57ZEJoMM6egm57TV19kz PMc879NV2nc6+elaKl+/kbVeD3qvBuEwsTe2Do3HAAdrfUG/j9erwIk6gha/Hp9yZlCnPTX+ VK+xifQqt8RtMqS5R/S8z0msJMI/ajNU03kFjOpqrYziv6OZLJ5cuKb3bZU5aoaRQRDzkFIR 6aqtFLTohTo20QywXwRa39uFaOT/0YMpNyel0kdOszFOykTEGI2u+kja35g9TkH90kkBTG+a EWttIht0Hy6YFmwjcAxisSakBuHnHuMSOiyRQLu43ej2+mDWgItLZ48Mu0C3IG1seeQDjEYP tqvyZ6bGkf2Vj+L6wLoLLIhRZxQOedqArIk/Sb2SzQYuxN44IDRt+3ZcDqsPppoKcxSyd1Ny 2tpvjYJXlfKmOYLhTWs8nwlAlSHX/c/jz/ywwf7eSvGknToo1Y0VpRtoxMaKW1nvH0OeCSVJ itfRP7YbiRVc2aNqWPCSgtqHAuVraBRbAFLKh9d2rKFB3BmynTUpc1BQLJP8+D5oNyb8Ts4x Xd3iV/uD8JLGJfYZIR7oGWFLP4uZ3tkneDfYzsFNBFp+A0oBEAC9ynZI9LU+uJkMeEJeJyQ/ 8VFkCJQPQZEsIGzOTlPnwvVna0AS86n2Z+rK7R/usYs5iJCZ55/JISWd8xD57ue0eB47bcJv VqGlObI2DEG8TwaW0O0duRhDgzMEL4t1KdRAepIESBEA/iPpI4gfUbVEIEQuqdqQyO4GAe+M kD0Hy5JH/0qgFmbaSegNTdQg5iqYjRZ3ttiswalql1/iSyv1WYeC1OAs+2BLOAT2NEggSiVO txEfgewsQtCWi8H1SoirakIfo45Hz0tk/Ad9ZWh2PvOGt97Ka85o4TLJxgJJqGEnqcFUZnJJ riwoaRIS8N2C8/nEM53jb1sH0gYddMU3QxY7dYNLIUrRKQeNkF30dK7V6JRH7pleRlf+wQcN fRAIUrNlatj9TxwivQrKnC9aIFFHEy/0mAgtrQShcMRmMgVlRoOA5B8RTulRLCmkafvwuhs6 dCxN0GNAORIVVFxjx9Vn7OqYPgwiofZ6SbEl0hgPyWBQvE85klFLZLoj7p+joDY1XNQztmfA rnJ9x+YV4igjWImINAZSlmEcYtd+xy3Li/8oeYDAqrsnrOjb+WvGhCykJk4urBog2LNtcyCj kTs7F+WeXGUo0NDhbd3Z6AyFfqeF7uJ3D5hlpX2nI9no/ugPrrTVoVZAgrrnNz0iZG2DVx46 x913pVKHl5mlYQARAQABwsFfBBgBAgAJBQJafgNKAhsMAAoJELKItV//nCLBwNIP/AiIHE8b oIqReFQyaMzxq6lE4YZCZNj65B/nkDOvodSiwfwjjVVE2V3iEzxMHbgyTCGA67+Bo/d5aQGj gn0TPtsGzelyQHipaUzEyrsceUGWYoKXYyVWKEfyh0cDfnd9diAm3VeNqchtcMpoehETH8fr RHnJdBcjf112PzQSdKC6kqU0Q196c4Vp5HDOQfNiDnTf7gZSj0BraHOByy9LEDCLhQiCmr+2 E0rW4tBtDAn2HkT9uf32ZGqJCn1O+2uVfFhGu6vPE5qkqrbSE8TG+03H8ecU2q50zgHWPdHM OBvy3EhzfAh2VmOSTcRK+tSUe/u3wdLRDPwv/DTzGI36Kgky9MsDC5gpIwNbOJP2G/q1wT1o Gkw4IXfWv2ufWiXqJ+k7HEi2N1sree7Dy9KBCqb+ca1vFhYPDJfhP75I/VnzHVssZ/rYZ9+5 1yDoUABoNdJNSGUYl+Yh9Pw9pE3Kt4EFzUlFZWbE4xKL/NPno+z4J9aWemLLszcYz/u3XnbO vUSQHSrmfOzX3cV4yfmjM5lewgSstoxGyTx2M8enslgdXhPthZlDnTnOT+C+OTsh8+m5tos8 HQjaPM01MKBiAqdPgksm1wu2DrrwUi6ChRVTUBcj6+/9IJ81H2P2gJk3Ls3AVIxIffLoY34E +MYSfkEjBz0E8CLOcAw7JIwAaeBT In-Reply-To: --------------fCxYjExTx4afN7vZNGscsPeS Content-Type: multipart/mixed; boundary="------------q9AC06bCVyaPOibqDCDhtYPK" --------------q9AC06bCVyaPOibqDCDhtYPK Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 4/21/26 12:55, Val Packett wrote: >=20 > On 4/20/26 4:12 PM, Demi Marie Obenour wrote: >> On 4/20/26 14:53, Christian K=C3=B6nig wrote: >>> On 4/20/26 20:46, Demi Marie Obenour wrote: >>>> On 4/20/26 13:58, Christian K=C3=B6nig wrote: >>>>> On 4/20/26 19:03, Demi Marie Obenour wrote: >>>>>> On 4/20/26 04:49, Christian K=C3=B6nig wrote: >>>>>>> On 4/17/26 21:35, Demi Marie Obenour wrote: >>>>> ... >>>>>>>> Are any of the following reasonable options? >>>>>>>> >>>>>>>> 1. Change the guest kernel to only map (and thus pin) a small su= bset >>>>>>>> of VRAM at any given time. If unmapped VRAM is accessed the= guest >>>>>>>> traps the page fault, evicts an old VRAM mapping, and create= s a >>>>>>>> new one. >>>>>>> Yeah, that could potentially work. >>>>>>> >>>>>>> This is basically what we do on the host kernel driver when we ca= n't resize the BAR for some reason. In that use case VRAM buffers are shu= ffled in and out of the CPU accessible window of VRAM on demand. >>>>>> How much is this going to hurt performance? >>>>> Hard to say, resizing the BAR can easily give you 10-15% more perfo= rmance on some use cases. >>>>> >>>>> But that involves physically transferring the data using a DMA. For= this solution we basically only have to we basically only have to transf= er a few messages between host and guest. >>>>> >>>>> No idea how performant that is. >>>> In this use-case, 20-30% performance penalties are likely to be >>>> "business as usual". >>> Well that is quite a bit. >>> >>>> Close to native performance would be ideal, but >>>> to be useful it just needs to beat software rendering by a wide marg= in, >>>> and not cause data corruption or vulnerabilities. >>> That should still easily be the case, even trivial use cases are mult= iple magnitudes faster on GPUs compared to software rendering. >> Makes sense. If only GPUs supported easy and flexible virtualization = the way CPUs do :(. >> >>>>>>> But I have one question: When XEN has a problem handling faults f= rom the guest on the host then how does that work for system memory mappi= ngs? >>>>>>> >>>>>>> There is really no difference between VRAM and system memory in t= he handling for the GPU driver stack. >>>>>>> >>>>>>> Regards, >>>>>>> Christian. >>>>>> Generally, Xen makes the frontend (usually an unprivileged VM) >>>>>> responsible for providing mappings to the backend (usually the hos= t). >>>>>> That is possible with system RAM but not with VRAM, because Xen ha= s >>>>>> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. >>>>> No, that doesn't work with system memory allocations of GPU drivers= either. >>>>> >>>>> We already had it multiple times that people tried to be clever and= incremented the page reference counter on driver allocated system memory= and were totally surprised that this can result in security issues and d= ata corruption. >>>>> >>>>> I seriously hope that this isn't the case here again. As far as I k= now XEN already has support for accessing VMAs with VM_PFN or otherwise I= don't know how driver allocated system memory access could potentially w= ork. >>>>> >>>>> Accessing VRAM is pretty much the same use case as far as I can see= =2E >>>>> >>>>> Regards, >>>>> Christian. >>>> The Xen-native approach would be for system memory allocations to >>>> be made using the Xen driver and then imported into the virtio-GPU >>>> driver via dmabuf. Is there any chance this could be made to happen= ? >>> That could be. Adding Pierre-Eric to comment since he knows that use = much better than I do. >>> >>>> If it's a lost cause, then how much is the memory overhead of pinnin= g >>>> everything ever used in a dmabuf? It should be possible to account >>>> pinned host memory against a guest's quota, but if that leads to an >>>> unusable system it isn't going to be good. >>> That won't work at all. >>> >>> We have use cases where you *must* migrate a DMA-buf to VRAM or other= wise the GPU can't use it. >>> >>> A simple scanout to a monitor is such an use case for example, that i= s usually not possible from system memory. >> Direct scanout isn't a concern here. >> >>>> Is supporting page faults in Xen the only solution that will be viab= le >>>> long-term, considering the tolerance for very substantial performanc= e >>>> overheads compared to native? AAA gaming isn't the initial goal her= e. >>>> Qubes OS already supports PCI passthrough for that. >>> We have AAA gaming working on XEN through native context working for = quite a while. >>> >>> Pierre-Eric can tell you more about that. >>> >>> Regards, >>> Christian. >> I've heard of that, but last I checked it required downstream patches >> to Xen, Linux, and QEMU. I don't know if any of those have been >> upstreamed since, but I believe that upstreaming the Xen and Linux >> patches (or rewriting them and upstreaming the rewritten version) woul= d >> be necessary. Qubes OS (which I don't work for anymore but still want= >> to help with this) almost certainly won't be using QEMU for GPU stuff.= >=20 > Yeah, our plan is to use xen-vhost-frontend[1] + vhost-device-gpu,=20 > ported/extended/modified as necessary. (I already have=20 > xen-vhost-frontend itself working on amd64 PVH with purely xenbus-based= =20 > hotplug/configuration, currently working on cleaning up and submitting = > the necessary patches.) >=20 > I'm curious to hear more details about how AMD has it working but last = > time I checked, there weren't any missing pieces in Xen or Linux that=20 > we'd need.. The AMD downstream changes were mostly related to QEMU. >=20 > As for the memory management concerns, I would like to remind everyone = > once again that the pinning of GPU dmabufs in regular graphics workload= s=20 > would be *very* short-term. In GPU paravirtualization (native contexts = > or venus or whatever else) the guest mostly operates on *opaque handles= *=20 > that refer to buffers owned by the host GPU process. The typical=20 > rendering process (roughly) only involves submitting commands to the GP= U=20 > that refer to memory using these handles. Only upon mmap() would a=20 > buffer be pinned/granted to the guest, and those are typically only use= d=20 > for *uploads* where the guest immediately does its memcpy() and unmaps = > the buffer. >=20 > So I'm not worried about (unintentionally) pinning too much GPU driver = > memory. >=20 > In terms of deliberate denial-of-service attacks from the guest to the = > host, the only reasonable response is: >=20 > =C2=AF\_(=E3=83=84)_/=C2=AF >=20 > CPU-mapping lots of GPU memory is far from the only DoS vector, the GPU= =20 > commands themselves can easily wedge the GPU core in a million ways (an= d=20 > last time I checked amdgpu was noooot so good at recovering from hangs)= =2E >=20 >=20 > [1]: https://github.com/vireshk/xen-vhost-frontend >=20 > ~val I think it is best to handle things like GPU crashes by giving the guest some time to unmap its grants, and if that fails, crashing it. This shou= ld be done from a revoke callback, as afterwards the VRAM might get reused. Does amdgpu call revoke callbacks when the device is reset and VRAM is lost? It seems like it at least ought to. As an aside, Qubes needs to use the process isolation mode of the amdgpu driver. This means that only one process will be on the GPU at a time, so it _should_ be possible to blow away all GPU-resident state except VRAM without affecting other processes. Unfortunately, I think AMD GPUs might have HW or FW limitations that prevent that, at least on dGPUs. It might make sense to recommend KDE with GPU acceleration. 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22:03:49 -0400 X-Gm-Features: AQROBzCq3JY-5ArkKnDyVVr-Wl_czV3R7nte4oTZblqOBZ3Fd9cc3qiKy3Gryh4 Message-ID: Subject: Re: Pinned, non-revocable mappings of VRAM: will bad things happen? To: Demi Marie Obenour Cc: Val Packett , =?UTF-8?Q?Christian_K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Xen developer discussion , linux-media@vger.kernel.org, Suwit Semal , "Pelloux-Prayer, Pierre-Eric" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1776823443-2BB78C48-DC55805D/0/0 X-purgate-type: clean X-purgate-size: 8296 On Tue, Apr 21, 2026 at 9:34=E2=80=AFPM Demi Marie Obenour wrote: > > On 4/21/26 12:55, Val Packett wrote: > > > > On 4/20/26 4:12 PM, Demi Marie Obenour wrote: > >> On 4/20/26 14:53, Christian K=C3=B6nig wrote: > >>> On 4/20/26 20:46, Demi Marie Obenour wrote: > >>>> On 4/20/26 13:58, Christian K=C3=B6nig wrote: > >>>>> On 4/20/26 19:03, Demi Marie Obenour wrote: > >>>>>> On 4/20/26 04:49, Christian K=C3=B6nig wrote: > >>>>>>> On 4/17/26 21:35, Demi Marie Obenour wrote: > >>>>> ... > >>>>>>>> Are any of the following reasonable options? > >>>>>>>> > >>>>>>>> 1. Change the guest kernel to only map (and thus pin) a small su= bset > >>>>>>>> of VRAM at any given time. If unmapped VRAM is accessed the= guest > >>>>>>>> traps the page fault, evicts an old VRAM mapping, and create= s a > >>>>>>>> new one. > >>>>>>> Yeah, that could potentially work. > >>>>>>> > >>>>>>> This is basically what we do on the host kernel driver when we ca= n't resize the BAR for some reason. In that use case VRAM buffers are shuff= led in and out of the CPU accessible window of VRAM on demand. > >>>>>> How much is this going to hurt performance? > >>>>> Hard to say, resizing the BAR can easily give you 10-15% more perfo= rmance on some use cases. > >>>>> > >>>>> But that involves physically transferring the data using a DMA. For= this solution we basically only have to we basically only have to transfer= a few messages between host and guest. > >>>>> > >>>>> No idea how performant that is. > >>>> In this use-case, 20-30% performance penalties are likely to be > >>>> "business as usual". > >>> Well that is quite a bit. > >>> > >>>> Close to native performance would be ideal, but > >>>> to be useful it just needs to beat software rendering by a wide marg= in, > >>>> and not cause data corruption or vulnerabilities. > >>> That should still easily be the case, even trivial use cases are mult= iple magnitudes faster on GPUs compared to software rendering. > >> Makes sense. If only GPUs supported easy and flexible virtualization = the way CPUs do :(. > >> > >>>>>>> But I have one question: When XEN has a problem handling faults f= rom the guest on the host then how does that work for system memory mapping= s? > >>>>>>> > >>>>>>> There is really no difference between VRAM and system memory in t= he handling for the GPU driver stack. > >>>>>>> > >>>>>>> Regards, > >>>>>>> Christian. > >>>>>> Generally, Xen makes the frontend (usually an unprivileged VM) > >>>>>> responsible for providing mappings to the backend (usually the hos= t). > >>>>>> That is possible with system RAM but not with VRAM, because Xen ha= s > >>>>>> no awareness of VRAM. To Xen, VRAM is just a PCI BAR. > >>>>> No, that doesn't work with system memory allocations of GPU drivers= either. > >>>>> > >>>>> We already had it multiple times that people tried to be clever and= incremented the page reference counter on driver allocated system memory a= nd were totally surprised that this can result in security issues and data = corruption. > >>>>> > >>>>> I seriously hope that this isn't the case here again. As far as I k= now XEN already has support for accessing VMAs with VM_PFN or otherwise I d= on't know how driver allocated system memory access could potentially work. > >>>>> > >>>>> Accessing VRAM is pretty much the same use case as far as I can see= . > >>>>> > >>>>> Regards, > >>>>> Christian. > >>>> The Xen-native approach would be for system memory allocations to > >>>> be made using the Xen driver and then imported into the virtio-GPU > >>>> driver via dmabuf. Is there any chance this could be made to happen= ? > >>> That could be. Adding Pierre-Eric to comment since he knows that use = much better than I do. > >>> > >>>> If it's a lost cause, then how much is the memory overhead of pinnin= g > >>>> everything ever used in a dmabuf? It should be possible to account > >>>> pinned host memory against a guest's quota, but if that leads to an > >>>> unusable system it isn't going to be good. > >>> That won't work at all. > >>> > >>> We have use cases where you *must* migrate a DMA-buf to VRAM or other= wise the GPU can't use it. > >>> > >>> A simple scanout to a monitor is such an use case for example, that i= s usually not possible from system memory. > >> Direct scanout isn't a concern here. > >> > >>>> Is supporting page faults in Xen the only solution that will be viab= le > >>>> long-term, considering the tolerance for very substantial performanc= e > >>>> overheads compared to native? AAA gaming isn't the initial goal her= e. > >>>> Qubes OS already supports PCI passthrough for that. > >>> We have AAA gaming working on XEN through native context working for = quite a while. > >>> > >>> Pierre-Eric can tell you more about that. > >>> > >>> Regards, > >>> Christian. > >> I've heard of that, but last I checked it required downstream patches > >> to Xen, Linux, and QEMU. I don't know if any of those have been > >> upstreamed since, but I believe that upstreaming the Xen and Linux > >> patches (or rewriting them and upstreaming the rewritten version) woul= d > >> be necessary. Qubes OS (which I don't work for anymore but still want > >> to help with this) almost certainly won't be using QEMU for GPU stuff. > > > > Yeah, our plan is to use xen-vhost-frontend[1] + vhost-device-gpu, > > ported/extended/modified as necessary. (I already have > > xen-vhost-frontend itself working on amd64 PVH with purely xenbus-based > > hotplug/configuration, currently working on cleaning up and submitting > > the necessary patches.) > > > > I'm curious to hear more details about how AMD has it working but last > > time I checked, there weren't any missing pieces in Xen or Linux that > > we'd need.. The AMD downstream changes were mostly related to QEMU. > > > > As for the memory management concerns, I would like to remind everyone > > once again that the pinning of GPU dmabufs in regular graphics workload= s > > would be *very* short-term. In GPU paravirtualization (native contexts > > or venus or whatever else) the guest mostly operates on *opaque handles= * > > that refer to buffers owned by the host GPU process. The typical > > rendering process (roughly) only involves submitting commands to the GP= U > > that refer to memory using these handles. Only upon mmap() would a > > buffer be pinned/granted to the guest, and those are typically only use= d > > for *uploads* where the guest immediately does its memcpy() and unmaps > > the buffer. > > > > So I'm not worried about (unintentionally) pinning too much GPU driver > > memory. > > > > In terms of deliberate denial-of-service attacks from the guest to the > > host, the only reasonable response is: > > > > =C2=AF\_(=E3=83=84)_/=C2=AF > > > > CPU-mapping lots of GPU memory is far from the only DoS vector, the GPU > > commands themselves can easily wedge the GPU core in a million ways (an= d > > last time I checked amdgpu was noooot so good at recovering from hangs)= . > > > > > > [1]: https://github.com/vireshk/xen-vhost-frontend > > > > ~val > > I think it is best to handle things like GPU crashes by giving the guest > some time to unmap its grants, and if that fails, crashing it. This shou= ld > be done from a revoke callback, as afterwards the VRAM might get reused. > > Does amdgpu call revoke callbacks when the device is reset and VRAM > is lost? It seems like it at least ought to. > > As an aside, Qubes needs to use the process isolation mode of the > amdgpu driver. This means that only one process will be on the GPU > at a time, so it _should_ be possible to blow away all GPU-resident > state except VRAM without affecting other processes. Unfortunately, > I think AMD GPUs might have HW or FW limitations that prevent that, > at least on dGPUs. The driver has supported per queue resets for a few kernel releases now so only the bad app would be affected in that case. Alex > > It might make sense to recommend KDE with GPU acceleration. KWin can > recover from losing VRAM. > -- > Sincerely, > Demi Marie Obenour (she/her/hers) From xen-devel-bounces@lists.xenproject.org Wed Apr 22 04:57:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 04:57:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289844.1569536 (Exim 4.92) (envelope-from ) id 1wFPeS-00037k-5p; Wed, 22 Apr 2026 04:57:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289844.1569536; Wed, 22 Apr 2026 04:57:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFPeS-00037L-0g; Wed, 22 Apr 2026 04:57:28 +0000 Received: by outflank-mailman (input) for mailman id 1289844; Wed, 22 Apr 2026 04:57:26 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFPeQ-0002xO-IM for xen-devel@lists.xenproject.org; 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Tue, 21 Apr 2026 21:57:21 -0700 (PDT) X-Received: by 2002:a05:600c:48a1:b0:489:a4:e58a with SMTP id 5b1f17b1804b1-48900a4e881mr160289815e9.19.1776833840649; Tue, 21 Apr 2026 21:57:20 -0700 (PDT) Message-ID: <68b36ad0-2233-49d0-a3a6-bce053686bf1@redhat.com> Date: Wed, 22 Apr 2026 06:57:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: Replace __ASSEMBLY__ with __ASSEMBLER__ in interface.h To: Stefano Stabellini Cc: Juergen Gross , Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org References: <20260421142701.548978-1-thuth@redhat.com> From: Thomas Huth Autocrypt: addr=thuth@redhat.com; keydata= xsFNBFH7eUwBEACzyOXKU+5Pcs6wNpKzrlJwzRl3VGZt95VCdb+FgoU9g11m7FWcOafrVRwU yYkTm9+7zBUc0sW5AuPGR/dp3pSLX/yFWsA/UB4nJsHqgDvDU7BImSeiTrnpMOTXb7Arw2a2 4CflIyFqjCpfDM4MuTmzTjXq4Uov1giGE9X6viNo1pxyEpd7PanlKNnf4PqEQp06X4IgUacW tSGj6Gcns1bCuHV8OPWLkf4hkRnu8hdL6i60Yxz4E6TqlrpxsfYwLXgEeswPHOA6Mn4Cso9O 0lewVYfFfsmokfAVMKWzOl1Sr0KGI5T9CpmRfAiSHpthhHWnECcJFwl72NTi6kUcUzG4se81 O6n9d/kTj7pzTmBdfwuOZ0YUSqcqs0W+l1NcASSYZQaDoD3/SLk+nqVeCBB4OnYOGhgmIHNW 0CwMRO/GK+20alxzk//V9GmIM2ACElbfF8+Uug3pqiHkVnKqM7W9/S1NH2qmxB6zMiJUHlTH gnVeZX0dgH27mzstcF786uPcdEqS0KJuxh2kk5IvUSL3Qn3ZgmgdxBMyCPciD/1cb7/Ahazr 3ThHQXSHXkH/aDXdfLsKVuwDzHLVSkdSnZdt5HHh75/NFHxwaTlydgfHmFFwodK8y/TjyiGZ zg2Kje38xnz8zKn9iesFBCcONXS7txENTzX0z80WKBhK+XSFJwARAQABzR5UaG9tYXMgSHV0 aCA8dGh1dGhAcmVkaGF0LmNvbT7CwXgEEwECACIFAlVgX6oCGwMGCwkIBwMCBhUIAgkKCwQW AgMBAh4BAheAAAoJEC7Z13T+cC21EbIP/ii9cvT2HHGbFRl8HqGT6+7Wkb+XLMqJBMAIGiQK QIP3xk1HPTsLfVG0ao4hy/oYkGNOP8+ubLnZen6Yq3zAFiMhQ44lvgigDYJo3Ve59gfe99KX EbtB+X95ODARkq0McR6OAsPNJ7gpEUzfkQUUJTXRDQXfG/FX303Gvk+YU0spm2tsIKPl6AmV 1CegDljzjycyfJbk418MQmMu2T82kjrkEofUO2a24ed3VGC0/Uz//XCR2ZTo+vBoBUQl41BD eFFtoCSrzo3yPFS+w5fkH9NT8ChdpSlbNS32NhYQhJtr9zjWyFRf0Zk+T/1P7ECn6gTEkp5k ofFIA4MFBc/fXbaDRtBmPB0N9pqTFApIUI4vuFPPO0JDrII9dLwZ6lO9EKiwuVlvr1wwzsgq zJTPBU3qHaUO4d/8G+gD7AL/6T4zi8Jo/GmjBsnYaTzbm94lf0CjXjsOX3seMhaE6WAZOQQG tZHAO1kAPWpaxne+wtgMKthyPLNwelLf+xzGvrIKvLX6QuLoWMnWldu22z2ICVnLQChlR9d6 WW8QFEpo/FK7omuS8KvvopFcOOdlbFMM8Y/8vBgVMSsK6fsYUhruny/PahprPbYGiNIhKqz7 UvgyZVl4pBFjTaz/SbimTk210vIlkDyy1WuS8Zsn0htv4+jQPgo9rqFE4mipJjy/iboDzsFN BFH7eUwBEAC2nzfUeeI8dv0C4qrfCPze6NkryUflEut9WwHhfXCLjtvCjnoGqFelH/PE9NF4 4VPSCdvD1SSmFVzu6T9qWdcwMSaC+e7G/z0/AhBfqTeosAF5XvKQlAb9ZPkdDr7YN0a1XDfa +NgA+JZB4ROyBZFFAwNHT+HCnyzy0v9Sh3BgJJwfpXHH2l3LfncvV8rgFv0bvdr70U+On2XH 5bApOyW1WpIG5KPJlDdzcQTyptOJ1dnEHfwnABEfzI3dNf63rlxsGouX/NFRRRNqkdClQR3K gCwciaXfZ7ir7fF0u1N2UuLsWA8Ei1JrNypk+MRxhbvdQC4tyZCZ8mVDk+QOK6pyK2f4rMf/ WmqxNTtAVmNuZIwnJdjRMMSs4W4w6N/bRvpqtykSqx7VXcgqtv6eqoDZrNuhGbekQA0sAnCJ VPArerAZGArm63o39me/bRUQeQVSxEBmg66yshF9HkcUPGVeC4B0TPwz+HFcVhheo6hoJjLq knFOPLRj+0h+ZL+D0GenyqD3CyuyeTT5dGcNU9qT74bdSr20k/CklvI7S9yoQje8BeQAHtdV cvO8XCLrpGuw9SgOS7OP5oI26a0548M4KldAY+kqX6XVphEw3/6U1KTf7WxW5zYLTtadjISB X9xsRWSU+Yqs3C7oN5TIPSoj9tXMoxZkCIHWvnqGwZ7JhwARAQABwsFfBBgBAgAJBQJR+3lM AhsMAAoJEC7Z13T+cC21hPAQAIsBL9MdGpdEpvXs9CYrBkd6tS9mbaSWj6XBDfA1AEdQkBOn ZH1Qt7HJesk+qNSnLv6+jP4VwqK5AFMrKJ6IjE7jqgzGxtcZnvSjeDGPF1h2CKZQPpTw890k fy18AvgFHkVk2Oylyexw3aOBsXg6ukN44vIFqPoc+YSU0+0QIdYJp/XFsgWxnFIMYwDpxSHS 5fdDxUjsk3UBHZx+IhFjs2siVZi5wnHIqM7eK9abr2cK2weInTBwXwqVWjsXZ4tq5+jQrwDK cvxIcwXdUTLGxc4/Z/VRH1PZSvfQxdxMGmNTGaXVNfdFZjm4fz0mz+OUi6AHC4CZpwnsliGV ODqwX8Y1zic9viSTbKS01ZNp175POyWViUk9qisPZB7ypfSIVSEULrL347qY/hm9ahhqmn17 Ng255syASv3ehvX7iwWDfzXbA0/TVaqwa1YIkec+/8miicV0zMP9siRcYQkyTqSzaTFBBmqD oiT+z+/E59qj/EKfyce3sbC9XLjXv3mHMrq1tKX4G7IJGnS989E/fg6crv6NHae9Ckm7+lSs IQu4bBP2GxiRQ+NV3iV/KU3ebMRzqIC//DCOxzQNFNJAKldPe/bKZMCxEqtVoRkuJtNdp/5a yXFZ6TfE1hGKrDBYAm4vrnZ4CXFSBDllL59cFFOJCkn4Xboj/aVxxJxF30bn In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: rs0CzFgOnuZPdlIH1-_sPVSL185A7T9HGqq04vD-m7I_1776833841 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776833845-BC016FF4-4917173E/0/0 X-purgate-type: clean X-purgate-size: 1443 On 22/04/2026 00.15, Stefano Stabellini wrote: > On Tue, 21 Apr 2026, Thomas Huth wrote: >> From: Thomas Huth >> >> While the GCC and Clang compilers already define __ASSEMBLER__ >> automatically when compiling assembly code, __ASSEMBLY__ is a >> macro that only gets defined by the Makefiles in the kernel. >> This can be very confusing when switching between userspace >> and kernelspace coding, or when dealing with uapi headers that >> rather should use __ASSEMBLER__ instead. So let's standardize now >> on the __ASSEMBLER__ macro that is provided by the compilers. >> >> Signed-off-by: Thomas Huth > > I haven't been closely following the __ASSEMBLER__ vs __ASSEMBLY__ > discussion. If there is general agreement to use __ASSEMBLER__ in > headers, I am happy to go along with that. Currently, I see more than > 140 uses of __ASSEMBLY__ compared to fewer than 20 uses of > __ASSEMBLER__, but I'll defer to your judgment if the project is moving > in that direction. I assume you only counted the occurrences in the main include/ folder? Please also take the arch/*/include/ folders into account: thuth:~/devel/linux$ grep -r __ASSEMBLER__ arch/*/include/ | wc -l 1492 thuth:~/devel/linux$ grep -r __ASSEMBLY__ arch/*/include/ | wc -l 120 So most spots have been converted already. It would be great if you could help with the xen header! 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: //L9G6O3g3PCVU1NXKMiMiXuG44D2nbJMk6ZuhLV9romtBIgUPbfwpJMjZkH/FQkJdv3a1ZgYtX5hwpWo56wyXY468LzvUttD2jxjG+CA/X61sP+hgAtZY156qaLA9utgZnLEbj2ma/SdY4gMm7DDaY/uZTa3hQs2cNEE93altOTtBwIGuxKCsS1Wy9CjUUrwxk9iZh7wt40xMaMTYn8CsVzQE7yDszx+FDzx7og333jqpdoLgQVzY72sswbHEexwaTgtGgZwX+l7P3cMa0ZBSCMKn32qTW9toONkoyUMG9UZJAQ/JDBcD0/1PafOqqyCOXmxqrwa5xzqCWn4yNKt2UkalSwpdjSqRP6+Jy0FDcHzfBVrWm/uicR+/tf0FhX+Jc+Mq5IpoN7L9H9PexllU8IAg/Qvu64m1EM8P7sly2cZoyt2vo17gC1DWJDwBLq X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 05:14:48.5758 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9089b2a-f459-4c45-88e0-08dea02e1359 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB11610 X-purgate-ID: tlsNG-42698a/1776834892-7E16DF3B-EE8DED18/0/0 X-purgate-type: clean X-purgate-size: 1868 Hi Dmytro, > On 21 Apr 2026, at 10:13, Dmytro Prokopchuk1 wrote: >=20 > Clang 22.x.x or Arm Toolchain for Embedded 22.x.x reports: >=20 > In file included from arch/arm/tee/ffa.c:75: > arch/arm/tee/ffa_private.h:439:17: error: 'used' attribute ignored on a n= on-definition declaration [-Werror,-Wignored-attributes] > 439 | extern uint32_t __ro_after_init ffa_fw_version; > | ^ >=20 > There is a fix for clang 16 in the git history: > a1a1e2b7dc4f ("xen/arm: ffa: fix build with clang") > which was broken by the following commit: > a90376c6adbc ("xen/arm: ffa: Add FF-A 1.2 endpoint memory access descript= ors") >=20 > Remove __ro_after_init from the extern declaration of ffa_fw_version. > The attribute is already present on the definition in ffa.c, which is > sufficient and correct. >=20 > Fixes: a90376c6adbc ("xen/arm: ffa: Add FF-A 1.2 endpoint memory access d= escriptors") > Signed-off-by: Dmytro Prokopchuk Sounds right to me: Reviewed-by: Bertrand Marquis Cheers Bertrand > --- > Test CI pipeline: > https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/24674463= 33 > --- > xen/arch/arm/tee/ffa_private.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat= e.h > index c291f32b56..e16bc0d83d 100644 > --- a/xen/arch/arm/tee/ffa_private.h > +++ b/xen/arch/arm/tee/ffa_private.h > @@ -436,7 +436,7 @@ struct ffa_ctx { > }; >=20 > extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE); > -extern uint32_t __ro_after_init ffa_fw_version; > +extern uint32_t ffa_fw_version; >=20 > extern struct list_head ffa_ctx_head; > extern rwlock_t ffa_ctx_list_rwlock; > --=20 > 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 05:59:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 05:59:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289868.1569553 (Exim 4.92) (envelope-from ) id 1wFQcB-00033Y-N3; Wed, 22 Apr 2026 05:59:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289868.1569553; Wed, 22 Apr 2026 05:59:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFQcB-00033R-K1; Wed, 22 Apr 2026 05:59:11 +0000 Received: by outflank-mailman (input) for mailman id 1289868; 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1776838781-06D77F3B-10CD3B08/0/0 X-purgate-type: clean X-purgate-size: 1881 On 21.04.2026 18:08, Jürgen Groß wrote: > On 21.04.26 15:54, Jason Andryuk wrote: >> On 2026-04-21 03:42, Juergen Gross wrote: >>> Add a new xs_watch_depth() function to libxenstore allowing to limit >>> the scope of a Xenstore watch. It can be used only in case Xenstore is >>> supporting the XENSTORE_SERVER_FEATURE_WATCHDEPTH feature. >>> >>> For convenience add a xs_watch_try_depth() wrapper, which will call >>> xs_watch_depth() if supported and xs_watch() otherwise. >>> >>> Cache the supported features of Xenstore in order not having to get >>> them from Xenstore for each call of one of the new functions. >>> >>> Signed-off-by: Juergen Gross >> >> >>> diff --git a/tools/libs/store/xs.c b/tools/libs/store/xs.c >>> index 06462445e0..cb3508a86a 100644 >>> --- a/tools/libs/store/xs.c >>> +++ b/tools/libs/store/xs.c >> >>> @@ -1001,8 +993,8 @@ bool xs_watch(struct xs_handle *h, const char *path, >>> const char *token) >>>   # define PTHREAD_STACK_MIN 0 >>>   #endif >>> -#define READ_THREAD_STACKSIZE                     \ >>> -    ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ?     \ >>> +#define READ_THREAD_STACKSIZE                    \ >>> +    ((DEFAULT_THREAD_STACKSIZE < PTHREAD_STACK_MIN) ?    \ >> >> This is an unrelated whitespace change, and not mentioned in the commit >> message.  It should probably be dropped since the surrounding lines are no >> longer touched.  Alternatively kept and mentioned.  With either of those: >> >> Reviewed-by: Jason Andryuk > > Thanks. > > Whoever is committing this: I'd rather expand the commit message with: > > While touching the file fix a whitespace issue. > > Shall I resubmit this patch, or can this be amended while committing? Of course it can be. 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To: Bernhard Kaindl Cc: "Daniel P. Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , xen-devel@lists.xenproject.org, Julien Grall , Stefano Stabellini , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel References: <127e7a4e0bf360d7ffe8be94022840a353a307b2.1776787216.git.bernhard.kaindl@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <127e7a4e0bf360d7ffe8be94022840a353a307b2.1776787216.git.bernhard.kaindl@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776840542-A396D938-CF2F463F/0/0 X-purgate-type: clean X-purgate-size: 4749 On 21.04.2026 18:13, Bernhard Kaindl wrote: > When reading the config file or the config section, we may need to append > a terminating NUL byte to the config buffer if the last byte is not a > control character. > > This may cause an additional page to be allocated by efi_bs->AllocatePages() > if the config file or config section size is a multiple of the page size. > > For this case, increment file->size by one so the number of pages to be > freed by efi_bs->FreePages() is the same as the number of pages allocated > by efi_bs->AllocatePages() when the additional byte is allocated. > > I moved the dcache flush after the NUL termination so the flushed range > covers the final buffer contents. > > I didn't add a dcache flush for the copied cfg buffer in read_section(): > that buffer is created by memcpy() and then consumed only by normal CPU > reads in the EFI loader, so there is no non-coherent producer or other > observer that would require cache maintenance. > > Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") > Signed-off-by: Bernhard Kaindl > > ---- > PS: The same fix applies to its backport to 4.21 and other branches, > for example: > > stable-4.21: > Fixes: feb99494bf59 ("EFI: avoid OOB config file reads") > > stable-4.20: > Fixes: 05b8f716aa32 ("EFI: avoid OOB config file reads") > > PPS: A review using GPT-5.4 (just a data point for review) confirms what > I've found by manual code inspection: > >> The fix in boot.c:882-886 and boot.c:913-928 is consistent with the existing >> free sites at boot.c:790-797, boot.c:1564-1567, and boot.c:1638-1641: Once the >> config buffer gets an extra terminating byte, using the incremented size for >> PFN_UP during FreePages is the right fix. >> >> I also checked the parser helpers at boot.c:584-641; they already operate on >> a bounded buffer and treat NUL/control bytes as terminators, so the synthetic >> extra byte does not create an obvious parsing regression. To avoid something non-obvious was why I deliberately left file->size un-incremented. But yes, I failed to recall that ->FreePages() takes a size. > --- a/xen/common/efi/boot.c > +++ b/xen/common/efi/boot.c > @@ -858,7 +858,8 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, > what = L"Allocation"; > file->addr = min(1UL << (32 + PAGE_SHIFT), > HYPERVISOR_VIRT_END - DIRECTMAP_VIRT_START); > - /* For config files allocate an extra byte to put a NUL there. */ > + > + /* For config file buffers, allocate space for the terminating NUL byte */ > ret = efi_bs->AllocatePages(AllocateMaxAddress, EfiLoaderData, > PFN_UP(size + (file == &cfg)), &file->addr); > if ( EFI_ERROR(ret) ) I don't really see why this or the other comment you alter would need touching. But of course it'll be the EFI maintainers to judge. > @@ -877,10 +878,12 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, > > FileHandle->Close(FileHandle); > > - efi_arch_flush_dcache_area(file->ptr, file->size); > - > if ( file == &cfg ) > - file->str[file->size] = 0; > + { > + file->str[file->size] = 0; /* NUL-terminate the config data buffer. */ > + file->size += 1; /* Free the same page count as allocated. */ _If_ we want to go with incrementing file->size, then I don't see why it can't be done using the increment operator. That specifically exists as a shorthand for "+= 1". As indicated above, I'm not convinced though that we really want to alter file->size. I'd instead add 1 in the few instances of "efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size))". Sadly the adding of 1 is conditional in read_section(), so maybe a "need_to_increment" boolean wants adding next to the need_to_free one? Then a small helper function may be warranted for those few instances of freeing cfg.addr. > + } > + efi_arch_flush_dcache_area(file->ptr, file->size); A separating blank line wants maintaining here. But is this change really needed at all? Besides being unrelated to the purpose of the patch, the flushing - aiui - exists so that buffers handed on to domains (Dom0) are in proper state. The config file isn't exposed to Dom0, though. (Furthermore I question the effectiveness of this flush: Speculation and prefetching can easily lead to the data being brought back into the cache. Such flushing likely requires unmapping first, and the concept of "unmapping" is a questionable one in the first place while still running in boot services context. Cc-ing the Arm maintainers for possible input.) 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pr=C Message-ID: Date: Wed, 22 Apr 2026 08:53:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm64: flushtlb: Optimize ARM64_WORKAROUND_REPEAT_TLBI To: Julien Grall , CC: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , References: <20260414081124.48741-1-michal.orzel@amd.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|DM4PR12MB7575:EE_ X-MS-Office365-Filtering-Correlation-Id: 07d4768b-f41b-4e0e-6294-08dea03bdb94 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: 33+EEMpdU6409SxkMJwsEUgxykJOGp9ENqIRNocmYfkehlshg236DwAbN5zm4RbYS+Vpsvo5ndgpuEwrtvGVHN0ku7me4BP6SWgg8Jci6gnU2YApk7fMgL9Hc0whHCZRvoAPE+PNJYIU2r9FTw9dDWwg968pY0yYQ/VbtAWRAOHzP75Snm5jiq1wv1y4T5N495+qYSviy2Yb0PIpVzY9tBsN6QpVXG9cw0RxEyQAFRt0fQLU4jY0mAFRjtbPLy/iT5somSEeB6FoelR4ucV5UhkaNkO6reuShVHRhpo5nAX9F24uCEkoBqTuhNtKnEYNZYHeuhOmzqTqw3mLwjFSrliI2yLMjazLZctsUeTbtZAp3NkznZ3lxizKJGOkhtL22W93qcp+o6dIvmmaI2pap4ZVykvi32suBPHxDiRJbfc8ZjGdLTykiNG+F95VkJuNWyu0Cv3nYg4VXN7UkIiqCKbpIpHKhl3viB1T+9Roz4rvkuRLAidhXAIlJqhUvh05bPtcclaP75ugX4ZIlP4h+bAtpUSQ83M+CoEl00t4RouaA9ooshJ9aFE2xjtOAHYKnn7GZWYVpoC/uEQINV8myUJYyB+vdLdYGbKFylwenmSD7pZsXYSCmsmNPRjmz/XpU5JN2hcZj5Ei6I0m0O2A9CmqDaGyH95/xH253BxaON3YjCraV3wNNara3VgUDmIAQXPybkp4ssaFH8n7Qk9iVju44s4N3IdgHeGh8SZX5rhVhAcfhgZF+8gCURAyF0vFKNqRXYQdXvIY1kmGxyFS6g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CjVP4BwPelvTPXQUh4eopOF6Gj2RS+nhPNuxYHISgqGAw35GmsHp/mqDHZ5HeaCF+uF2lNh+Kf33H7gRuwXfAJX5aOMkcDBh6JYbpvBZfrcyM+vqTvT2iuNZm5A1kJeLNFm/P3ISQvo6/jUJ2S6FfH/RO2pEAc3U/yNiIo68nSwZG7nCfg3uk2InGvhf2HLeBXX7oBPpUbDrQcHD0PuAJ9i0/etatGeznen38Klqb9rfnUZYbwW3eSZR2+5OU+LCNagzF1CkEFn+1F3GmnaCFHDv4uRt9T9QaTVdUt6YZA8d9nQB5O+Qy25+T0ZoJzlPO5TfnGdDU0fqsZtnDlzus/yz7TtjsPij0R6NeQqV2H9gZiOpiPl5UyKE3wbZy10xKo9sz6Fi58hkwKl4rDFZFGikiUvgYaAtJ1adWIK+ulMT+eqA9kgktVMuQ2dZlVto X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 06:53:28.0348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07d4768b-f41b-4e0e-6294-08dea03bdb94 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7575 X-purgate-ID: tlsNG-c201ff/1776840815-E01A9443-91EEF6B0/0/0 X-purgate-type: clean X-purgate-size: 1201 On 21/04/2026 10:59, Julien Grall wrote: > Hi Michal, > > On 14/04/2026 09:11, Michal Orzel wrote: >> Rework the workaround logic as follows: >> - add TLB_HELPER_LOCAL() to be used for local TLB ops without a >> workaround, >> - modify TLB_HELPER() workaround to use tlbi vale2is, xzr as a second >> TLB, >> - drop TLB_HELPER_VA(). It's used only by __flush_xen_tlb_one_local >> which is local and does not need workaround and by >> __flush_xen_tlb_one. In the latter case, since it's used in a loop, >> we don't need a workaround in the middle. Add __tlb_repeat_sync with >> a workaround to be used at the end after DSB and before final ISB, >> - TLBI VALE2IS passing XZR is used as an additional TLBI. While there is >> an identity mapping there, it's used very rarely. The performance >> impact is therefore negligible. If things change in the future, we >> can revisit the decision. > > Can you document the use of 0 in arch/arm/include/asm/mmu/layout.h as well? Ok, will do on commit. > >> >> Signed-off-by: Michal Orzel > > Reviewed-by: Julien Grall Thanks. ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 07:01:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 07:01:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289914.1569588 (Exim 4.92) (envelope-from ) id 1wFRaF-0002W1-OP; Wed, 22 Apr 2026 07:01:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289914.1569588; Wed, 22 Apr 2026 07:01:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFRaF-0002Vu-LT; Wed, 22 Apr 2026 07:01:15 +0000 Received: by outflank-mailman (input) for mailman id 1289914; Wed, 22 Apr 2026 07:01:13 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFRaD-0002Vo-OJ for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 07:01:13 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wFRaD-00EB7T-1F; Wed, 22 Apr 2026 07:01:13 +0000 Received: from [2a02:8012:3a1:0:a171:8b59:6670:784a] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wFRaD-00F4Ig-09; Wed, 22 Apr 2026 07:01:13 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=Dz4gErmCIIkM30bY14XeUH7vMfnqt1t5br/PitpWIV8=; b=gRd3lBJtahMFQ+Wgj0i75p7Kd3 GxEh+AmdSUfYgAxlv4P0SQS3s8aQfhYDKlbFosqWIDWnnAJHMIF4iT0ZqtKRSB5jfP/5t0r+lE/Zh Imi4Go8/L3pS+y9QPeHXlV+ahXWaAh0ddeHd2QAwh/BtH8gdWHhanJQp3OCap719vofQ=; Message-ID: <6a43af84-ca86-41f2-b58d-57be5baf49de@xen.org> Date: Wed, 22 Apr 2026 08:01:09 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: skip holes in physical address space when setting up frametable Content-Language: en-GB To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Luca Fancellu References: <20260417091124.39552-1-michal.orzel@amd.com> From: Julien Grall In-Reply-To: <20260417091124.39552-1-michal.orzel@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 17/04/2026 10:11, Michal Orzel wrote: > Refactor setup_frametable_mappings() into init_frametable(), modeled > after x86's implementation. Instead of mapping one contiguous frametable > covering ram_start to ram_end (including holes), iterate the > pdx_group_valid bitmap to allocate and map frametable memory only for > valid PDX groups, skipping gaps in the physical address space. At the > moment we don't really take into account pdx_group_valid bitmap. > > This reduces memory consumption on systems with sparse RAM layouts by > not allocating frametable entries for non-existent memory regions. > > A file-local pdx_to_page() override is needed because the generic macro > in xen/include/xen/pdx.h does not account for ARM's non-zero > frametable_base_pdx. Can you provide a bit more details? I am a bit concerned that this could result to subttle bug in the future if code within mm.c is expecting the original behavior. It would be preferable if the change is either for everyone on Arm or the function is renamed to avoid any clash. [...] > +void __init init_frametable(paddr_t ram_start) > +{ > + unsigned int sidx, nidx, max_idx; > > /* > * The size of paddr_t should be sufficient for the complete range of > @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) > BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); > BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); > > - if ( frametable_size > FRAMETABLE_SIZE ) > - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", > - ps, pe); > + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); > + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); > > - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); > - /* Round up to 2M or 32M boundary, as appropriate. */ > - frametable_size = ROUNDUP(frametable_size, mapping_size); > - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); > + /* > + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned > + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this > + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of > + * PAGE_SIZE by construction. > + */ > + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); > > - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, > - frametable_size >> PAGE_SHIFT, > - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); > - if ( rc ) > - panic("Unable to setup the frametable mappings.\n"); > + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) > + panic("Frametable too small\n"); > + > + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) > + { > + unsigned int eidx; > + > + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); > + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); > + > + if ( nidx >= max_idx ) > + break; > + > + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); The function will do a round-up the mapping to either a 2MiB or 32MiB aligned size. This means we could potentially cover the previous mapped region or the next one. I can't seem to find any code to cover this use-case. What did I miss? Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Apr 22 07:16:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 07:16:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289923.1569597 (Exim 4.92) (envelope-from ) id 1wFRoW-0004x7-Ty; Wed, 22 Apr 2026 07:16:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289923.1569597; Wed, 22 Apr 2026 07:16:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFRoW-0004wz-RP; Wed, 22 Apr 2026 07:16:00 +0000 Received: by outflank-mailman (input) for mailman id 1289923; Wed, 22 Apr 2026 07:16:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFRoW-0004wt-4e for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 07:16:00 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFRoV-00Ecjq-HS for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 09:15:59 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e875af-e002-0a2a0a5209dd-0a2a4507b1c8-2 for ; Wed, 22 Apr 2026 09:15:59 +0200 Received: from [209.85.221.52] (helo=mail-wr1-f52.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e875af-229c-0a2a45070019-d155dd34a976-3 for ; Wed, 22 Apr 2026 09:15:59 +0200 Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-43d75312379so3776815f8f.1 for ; Wed, 22 Apr 2026 00:15:59 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1776842159-23D7FC48-71BAA9DA/0/0 X-purgate-type: clean X-purgate-size: 1536 On 21.04.2026 17:51, Roger Pau Monné wrote: > On Tue, Apr 21, 2026 at 05:35:57PM +0200, Jan Beulich wrote: >> On 21.04.2026 17:32, Roger Pau Monne wrote: >>> --- a/tools/misc/xenpm.c >>> +++ b/tools/misc/xenpm.c >>> @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch, uint32_t cpu, bool package, int *te >>> { >>> case 0: >>> /* This CPU isn't online or can't query this MSR */ >>> - errno = ENODATA; >>> + errno = ENODEV; >>> return -1; >> >> "No such device", however, isn't quite what we want to convey here. If no >> better error code can be found that's available on FreeBSD and Linux, I'm >> inclined to suggest that we stick to ENODATA where available. > > Seems like a lot of complexity, for very limited usefulness. What's complex about #ifndef ENODATA # define ENODATA ENODEV #endif (perhaps with a brief comment)? > The only > usage of errno is to be printed in the error message, and for the > purposes of this function ENODEV is already unique in the function, as > ENODATA was. Right, but "No data available" is more precise than "No such device". > FWIW, I think ENODEV is not that far fetched: the CPU being offline > or the MSR not being present seems like what you would convey by using > ENODEV. Yes, there is a connection. Hence I'm not outright opposed, yet I think we can do better. Formally Anthony is the maintainer of the file, so in a case like this one maybe he ought to have the final say? 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Wed, 22 Apr 2026 01:04:43 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Jens Wiklander Date: Wed, 22 Apr 2026 10:04:31 +0200 X-Gm-Features: AQROBzC7bB4FQig0mzTxUpS0in5VDMjc43F87Gjf8I43gViVqd5-DG2514z0Syo Message-ID: Subject: Re: [PATCH 1/6] xen/arm: ffa: Fix NPI injection when vcpu0 is offline To: Bertrand Marquis Cc: xen-devel@lists.xenproject.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d62444/1776845085-B5468FF4-383709DD/0/0 X-purgate-type: clean X-purgate-size: 3712 Hi Bertrand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > RX-buffer-full notifications currently inject the notification pending > interrupt through vcpu0 only. Secure notification delivery already walks > the domain's online vCPUs, but the RX-buffer-full path does not. When > vcpu0 is offline, the notification remains pending and the guest never > receives it. > > Extract the common notification injection path and reuse it from > ffa_raise_rx_buffer_full(). The shared helper delivers the global > notification to the first online vCPU and keeps the existing ratelimited > debug message when none are online. > > Functional impact: RX-buffer-full notifications are delivered even when > vcpu0 is offline. > > Fixes: 3935c705688e ("xen/arm: ffa: Add buffer full notification support"= ) > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa_notif.c | 45 ++++++++++++++++++++---------------- > 1 file changed, 25 insertions(+), 20 deletions(-) Looks good: Reviewed-by: Jens Wiklander Cheers, Jens > > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index 186e72641237..07bc5cb3a430 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -19,6 +19,29 @@ > static bool __ro_after_init fw_notif_enabled; > static unsigned int __ro_after_init notif_sri_irq; > > +static void inject_notif_pending(struct domain *d) > +{ > + struct vcpu *v; > + > + /* > + * Since we're only delivering global notification, always > + * deliver to the first online vCPU. It doesn't matter > + * which we chose, as long as it's available. > + */ > + for_each_vcpu(d, v) > + { > + if ( is_vcpu_online(v) ) > + { > + vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); > + return; > + } > + } > + > + if ( printk_ratelimit() ) > + printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs off= line\n", > + d); > +} > + > int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) > { > struct domain *d =3D current->domain; > @@ -190,7 +213,7 @@ void ffa_raise_rx_buffer_full(struct domain *d) > > ACCESS_ONCE(ctx->notif.buff_full_pending) =3D true; > if ( !test_and_set_bool(ctx->notif.vm_pending) ) > - vgic_inject_irq(d, d->vcpu[0], GUEST_FFA_NOTIF_PEND_INTR_ID, tru= e); > + inject_notif_pending(d); > } > #endif > > @@ -238,7 +261,6 @@ static void notif_vm_pend_intr(uint16_t vm_id) > { > struct ffa_ctx *ctx; > struct domain *d; > - struct vcpu *v; > > /* > * vm_id =3D=3D 0 means a notifications pending for Xen itself, but > @@ -277,24 +299,7 @@ static void notif_vm_pend_intr(uint16_t vm_id) > * it. > */ > ACCESS_ONCE(ctx->notif.secure_pending) =3D true; > - > - /* > - * Since we're only delivering global notification, always > - * deliver to the first online vCPU. It doesn't matter > - * which we chose, as long as it's available. > - */ > - for_each_vcpu(d, v) > - { > - if ( is_vcpu_online(v) ) > - { > - vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, > - true); > - break; > - } > - } > - if ( !v && printk_ratelimit() ) > - printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs off= line\n", > - d); > + inject_notif_pending(d); > > out_unlock: > rcu_unlock_domain(d); > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 08:15:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 08:15:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1289962.1569617 (Exim 4.92) (envelope-from ) id 1wFSk1-00009y-Nt; Wed, 22 Apr 2026 08:15:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1289962.1569617; Wed, 22 Apr 2026 08:15:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFSk1-00009q-KE; Wed, 22 Apr 2026 08:15:25 +0000 Received: by outflank-mailman (input) for mailman id 1289962; Wed, 22 Apr 2026 08:15:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFSjz-00009j-Ta for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 08:15:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFSjy-006VIK-RT for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 10:15:22 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e88396-e002-0a2a0a5209dd-0a2a450ad710-2 for ; Wed, 22 Apr 2026 10:15:22 +0200 Received: from [209.85.221.53] (helo=mail-wr1-f53.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8839a-56b3-0a2a450a0019-d155dd35d498-3 for ; Wed, 22 Apr 2026 10:15:22 +0200 Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-43cfbd17589so4011213f8f.0 for ; Wed, 22 Apr 2026 01:15:22 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <10315bf1a012edf4821f7386b3142e56b6c23e34.1776332054.git.teddy.astie@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776845722-4596E8B7-A38C37F6/0/0 X-purgate-type: clean X-purgate-size: 1511 On 16.04.2026 11:36, Teddy Astie wrote: > When settings HVM_PARAM_IDENT_PT, skip domain pausing when : > - there is no vcpu > - unrestricted guest capability is used > > Signed-off-by: Teddy Astie > --- > v2: > - rebased patches with staging The main open issue, however, is that Andrew didn't indicate yet whether the concern he raised on v1 was addressed. I can't very well ack the change with a pending objection (and we still haven't settled on how to deal with effectively abandoned ones, i.e. when one was responded to but the response was never acknowledged). And then surely you could have noticed yourself that ... > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -4237,11 +4237,13 @@ static int hvm_set_param(struct domain *d, uint32_t index, uint64_t value) > rc = -EINVAL; > break; > case HVM_PARAM_IDENT_PT: > + v = domain_vcpu(d, 0); > + > /* > * Only actually required for VT-x lacking unrestricted_guest > * capabilities. Short circuit the pause if possible. > */ > - if ( paging_mode_shadow(d) || !using_vmx() ) > + if ( paging_mode_shadow(d) || !using_vmx() || !v || vmx_unrestricted_guest(v) ) ... this line is now too long, and there's a stray blank being added ahead of the final closing parenthesis. > { > d->arch.hvm.params[index] = value; Tangential: We don't need this, do we? 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From: Jan Beulich To: Bernhard Kaindl Cc: "Daniel P. Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , xen-devel@lists.xenproject.org, Julien Grall , Stefano Stabellini , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel References: <127e7a4e0bf360d7ffe8be94022840a353a307b2.1776787216.git.bernhard.kaindl@citrix.com> <170028cb-ce5c-4677-88e4-32f57f372fea@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <170028cb-ce5c-4677-88e4-32f57f372fea@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776846009-3A169DB1-E8F34408/0/0 X-purgate-type: clean X-purgate-size: 4296 On 22.04.2026 08:48, Jan Beulich wrote: > On 21.04.2026 18:13, Bernhard Kaindl wrote: >> When reading the config file or the config section, we may need to append >> a terminating NUL byte to the config buffer if the last byte is not a >> control character. >> >> This may cause an additional page to be allocated by efi_bs->AllocatePages() >> if the config file or config section size is a multiple of the page size. >> >> For this case, increment file->size by one so the number of pages to be >> freed by efi_bs->FreePages() is the same as the number of pages allocated >> by efi_bs->AllocatePages() when the additional byte is allocated. >> >> I moved the dcache flush after the NUL termination so the flushed range >> covers the final buffer contents. >> >> I didn't add a dcache flush for the copied cfg buffer in read_section(): >> that buffer is created by memcpy() and then consumed only by normal CPU >> reads in the EFI loader, so there is no non-coherent producer or other >> observer that would require cache maintenance. >> >> Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") >> Signed-off-by: Bernhard Kaindl >> >> ---- >> PS: The same fix applies to its backport to 4.21 and other branches, >> for example: >> >> stable-4.21: >> Fixes: feb99494bf59 ("EFI: avoid OOB config file reads") >> >> stable-4.20: >> Fixes: 05b8f716aa32 ("EFI: avoid OOB config file reads") >> >> PPS: A review using GPT-5.4 (just a data point for review) confirms what >> I've found by manual code inspection: >> >>> The fix in boot.c:882-886 and boot.c:913-928 is consistent with the existing >>> free sites at boot.c:790-797, boot.c:1564-1567, and boot.c:1638-1641: Once the >>> config buffer gets an extra terminating byte, using the incremented size for >>> PFN_UP during FreePages is the right fix. >>> >>> I also checked the parser helpers at boot.c:584-641; they already operate on >>> a bounded buffer and treat NUL/control bytes as terminators, so the synthetic >>> extra byte does not create an obvious parsing regression. > > To avoid something non-obvious was why I deliberately left file->size > un-incremented. But yes, I failed to recall that ->FreePages() takes a > size. > >> --- a/xen/common/efi/boot.c >> +++ b/xen/common/efi/boot.c >> @@ -858,7 +858,8 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, >> what = L"Allocation"; >> file->addr = min(1UL << (32 + PAGE_SHIFT), >> HYPERVISOR_VIRT_END - DIRECTMAP_VIRT_START); >> - /* For config files allocate an extra byte to put a NUL there. */ >> + >> + /* For config file buffers, allocate space for the terminating NUL byte */ >> ret = efi_bs->AllocatePages(AllocateMaxAddress, EfiLoaderData, >> PFN_UP(size + (file == &cfg)), &file->addr); >> if ( EFI_ERROR(ret) ) > > I don't really see why this or the other comment you alter would need > touching. But of course it'll be the EFI maintainers to judge. > >> @@ -877,10 +878,12 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name, >> >> FileHandle->Close(FileHandle); >> >> - efi_arch_flush_dcache_area(file->ptr, file->size); >> - >> if ( file == &cfg ) >> - file->str[file->size] = 0; >> + { >> + file->str[file->size] = 0; /* NUL-terminate the config data buffer. */ >> + file->size += 1; /* Free the same page count as allocated. */ > > _If_ we want to go with incrementing file->size, then I don't see why > it can't be done using the increment operator. That specifically exists > as a shorthand for "+= 1". > > As indicated above, I'm not convinced though that we really want to > alter file->size. I'd instead add 1 in the few instances of > "efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size))". Sadly the adding of 1 > is conditional in read_section(), so maybe a "need_to_increment" > boolean wants adding next to the need_to_free one? Then a small helper > function may be warranted for those few instances of freeing cfg.addr. Actually, no separate flag looks to be needed. If for the cfg file we set ->need_to_free, we know we allocated the one extra byte. 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pr=C Message-ID: Date: Wed, 22 Apr 2026 10:25:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: skip holes in physical address space when setting up frametable To: Julien Grall , CC: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Luca Fancellu References: <20260417091124.39552-1-michal.orzel@amd.com> <6a43af84-ca86-41f2-b58d-57be5baf49de@xen.org> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <6a43af84-ca86-41f2-b58d-57be5baf49de@xen.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615E:EE_|DS0PR12MB7802:EE_ X-MS-Office365-Filtering-Correlation-Id: 82fdca39-a71d-41be-fd6d-08dea048c312 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|18096099003|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: dDkcE0BgaooLq/Ux9xe2dGpnBwjGPah5oazwnG4aylfZ9Om7SqONuGkqgjHDh3VmjN2RhvURVj9Ckv9DlpVI3JDELNAyC+qJqZFJylGZ3WK3Js5FhATfBPfEEYjD78o9JhfIpd7urTsLm81uSPTx5g5sDhpMN3FF301ZaPsN+nQO9w5BjPdMfJlikihcXKRDiEhvSjzRMaIS7h1oRC0kyAueaobCWeXqsDf+ADWja/ti7TzvpHsnpbPclx6BGxrFLAHJfSYUiOdaH3tGimxTTMeYIcoR6MiBgtAl5ut0tMsTPmAnKBBKixWQ2HwzE0wbfyY07wYsmiyuXHJyY8QsLnqy/EFkLEDPPybiFRj0y3i/JmjTdgKJ5mGjbUrkhzNcKllu/U+B93oMNAS5ouhPgXUleG6pSH5lQZZtdMTtV3QsG7y/dGXrOb0cHQ+VmcEqUOdTBp0+oB6BQGtTLBpo34Vy1JVIf65SEXFWfof3pwClKcFLhzD3GILjeSK/U+xO9BzzfdYkBQDBV0y5t/nLbPaiNvDtztcq1JDRhKas9fIgP3ACo4ydvqr0rW0JrPQB5gODWBM1+b58kMERQH4lvljfEDGEYkGsh0gS1EvNEDg9gpCTu8fOw/bTAydhy80gFhTi8EJPxbHTN6lbTxl31fGh6om1Od/RkKpRgEGEqRFFyOSlAbbqyOkp6144GZX3i54qRpgehVyqjvFFusJ2V/6VGY5b8VVqZn6ZcHytl92bIsXdhVQwpB/+Q8nufMaWrYffIXCrfkB5QotMPugAhg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(18096099003)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RPJ79BiP0B7vKWImwLE+leo2lavhMy3zpi6IhAWsimMWFf2iGIVs435UYlDabtUyk4uMBQivmRTYMGIh+vw4FjbL3zo+j5zVUdZ2G4keDhLX25Mz/ZWgNDZEtOn9RjRV/WeL5MGwUk/EyGcmvSI+a3GiBtfLp7ZS49+WgkB4C/91QrrjcqBG3V81hlaQqh7rikQMaFQtY8Q604vA9Dc+906bipOnJit9MgsRt6J7lAFGRIGwR4sv4SB2tiHB45upHbTPxse/1Ca/Jorplz5rMnx3wOrz5pEHXR19+oFEwOoqajnIZeHFJzHjwA6hXRLWHcLZiFvNf/6DIapUqVCRGHopyIT57IexeKsh4xo/5gykXdCXY9IOdVMfMO6k5eDG94rV+o30uCPWCHed2fBBm61etGJnchRBFytyt7HYSMMIO7CP57JueN2TytU3vU6M X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 08:25:50.2755 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82fdca39-a71d-41be-fd6d-08dea048c312 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7802 X-purgate-ID: tlsNG-4011c0/1776846356-815848B7-2E916D50/0/0 X-purgate-type: clean X-purgate-size: 4706 On 22/04/2026 09:01, Julien Grall wrote: > Hi Michal, > > On 17/04/2026 10:11, Michal Orzel wrote: >> Refactor setup_frametable_mappings() into init_frametable(), modeled >> after x86's implementation. Instead of mapping one contiguous frametable >> covering ram_start to ram_end (including holes), iterate the >> pdx_group_valid bitmap to allocate and map frametable memory only for >> valid PDX groups, skipping gaps in the physical address space. At the >> moment we don't really take into account pdx_group_valid bitmap. >> >> This reduces memory consumption on systems with sparse RAM layouts by >> not allocating frametable entries for non-existent memory regions. >> >> A file-local pdx_to_page() override is needed because the generic macro >> in xen/include/xen/pdx.h does not account for ARM's non-zero >> frametable_base_pdx. > > Can you provide a bit more details? I am a bit concerned that this could > result to subttle bug in the future if code within mm.c is expecting the > original behavior. It would be preferable if the change is either for > everyone on Arm or the function is renamed to avoid any clash. The generic pdx_to_page macro does not account for offset which is something I mentioned in the footer and I'm willing to work on in the future. As of today, this macro is *unused* on Arm. It's only used by x86 in some special big mem related scenario. Using generic pdx_to_page on Arm would be wrong, so a future patch doing that would be wrong (the fact that this patch adds a local redefine does not change anything). Do we need a rename for a local redefine in a file that is only related to frametable? Maybe a comment and a TODO would be ok? > > [...] > >> +void __init init_frametable(paddr_t ram_start) >> +{ >> + unsigned int sidx, nidx, max_idx; >> >> /* >> * The size of paddr_t should be sufficient for the complete range of >> @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >> >> - if ( frametable_size > FRAMETABLE_SIZE ) >> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >> - ps, pe); >> + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); >> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >> >> - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); >> - /* Round up to 2M or 32M boundary, as appropriate. */ >> - frametable_size = ROUNDUP(frametable_size, mapping_size); >> - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); >> + /* >> + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned >> + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this >> + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of >> + * PAGE_SIZE by construction. >> + */ >> + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); >> >> - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, >> - frametable_size >> PAGE_SHIFT, >> - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); >> - if ( rc ) >> - panic("Unable to setup the frametable mappings.\n"); >> + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) >> + panic("Frametable too small\n"); >> + >> + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) >> + { >> + unsigned int eidx; >> + >> + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); >> + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); >> + >> + if ( nidx >= max_idx ) >> + break; >> + >> + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); > > The function will do a round-up the mapping to either a 2MiB or 32MiB > aligned size. This means we could potentially cover the previous mapped > region or the next one. I can't seem to find any code to cover this > use-case. What did I miss? Hmm, I think I calculated something wrong here. Anyway, how about using 2MB mapping size all the time? PDX group size is 2MB, in-loop chunks are multiple of 2MB, there is no roundup needed - zero overshoot. The last chunk may have ~2MB overshoot but it does not matter as there is nothing after it to conflict with. The downside is more TLB pressure. Alternatively, we could reduce the mapping size closer to boundaries (x86 choice) but that would require a bit more work. ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 08:40:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 08:40:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290009.1569683 (Exim 4.92) (envelope-from ) id 1wFT7n-0006I0-Fj; Wed, 22 Apr 2026 08:39:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290009.1569683; Wed, 22 Apr 2026 08:39:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFT7n-0006Ht-Cb; Wed, 22 Apr 2026 08:39:59 +0000 Received: by outflank-mailman (input) for mailman id 1290009; Wed, 22 Apr 2026 08:39:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFT7l-0006Hn-Fd for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 08:39:57 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFT7k-002Ots-SQ for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 10:39:56 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e88954-bab6-0a2a0a5309dd-0a2a450ab3ee-30 for ; Wed, 22 Apr 2026 10:39:56 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8895c-56b3-0a2a450a0019-d1558036e1f0-3 for ; Wed, 22 Apr 2026 10:39:56 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso70622115e9.3 for ; Wed, 22 Apr 2026 01:39:56 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5302d33e7e896347acc7a8212df4f28ea098e28e.1776172526.git.bernhard.kaindl@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776847196-4616A8B7-46D3BF0D/0/0 X-purgate-type: clean X-purgate-size: 2427 On 14.04.2026 15:22, Bernhard Kaindl wrote: > Refactor claim deduction to make the claims accounting model easier to > follow ahead of later functional changes. > > Three new callers will need to deduct claims, and two of them will also > need the number of pages deducted to be returned. > > No functional change. > > Signed-off-by: Bernhard Kaindl > --- > History: > > Functionally unchanged since v4, only minor cleanups have been applied and: > - Updated the function name deduct_global_claims() to follow standard naming. > - Moved the other function into another commit as it had no users here. Is this true? In v4 ... > --- a/xen/common/page_alloc.c > +++ b/xen/common/page_alloc.c > @@ -518,6 +518,19 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages) > return d->tot_pages; > } > > +/* Deduct up to the given amount of pages from the global claims of a domain */ > +static unsigned long deduct_global_claims(struct domain *d, > + unsigned long reduction) > +{ > + reduction = min(reduction, d->outstanding_pages + 0UL); > + ASSERT(reduction <= outstanding_claims); ... this was still BUG_ON(), matching ... > @@ -1067,11 +1079,7 @@ static struct page_info *alloc_heap_pages( > * the domain being destroyed before creation is finished. Losing part > * of the claim makes no difference. > */ > - unsigned long outstanding = min(d->outstanding_pages + 0UL, request); > - > - BUG_ON(outstanding > outstanding_claims); ... the original code. Changing this may be okay (albeit I'm unconvinced), but it would want justifying in the description then. As to the rename to deduct_global_claims(): With that, wouldn't its 2nd parameter then better also change to "deduction"? Furthermore, "global" in the name is ambiguous: It may mean "not per-node", but it may also mean "not per-domain". The v4 name didn't have such an issue. One other, wider aspect (which I may or may not have mentioned before): The mix of unsigned long vs unsigned int for page counts is concerning. It is why the not overly nice "+ 0UL" is needed. I wonder if we wouldn't do ourselves a favor if we first normalized all that. Considering that systems (and hence guests) only ever get larger, it likely should all be unsigned long. Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 22 08:46:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 08:46:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290018.1569693 (Exim 4.92) (envelope-from ) id 1wFTEU-0007pb-66; Wed, 22 Apr 2026 08:46:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290018.1569693; Wed, 22 Apr 2026 08:46:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFTEU-0007pU-24; Wed, 22 Apr 2026 08:46:54 +0000 Received: by outflank-mailman (input) for mailman id 1290018; Wed, 22 Apr 2026 08:46:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFTES-0007pM-Kk for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 08:46:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFTER-002Q7b-QV for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 10:46:51 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e88af1-bab6-0a2a0a5309dd-0a2a450b973e-18 for ; Wed, 22 Apr 2026 10:46:51 +0200 Received: from [40.93.198.56] (helo=CY7PR03CU001.outbound.protection.outlook.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e88afa-212f-0a2a450b0019-285dc6384d50-3 for ; Wed, 22 Apr 2026 10:46:51 +0200 Received: from LV3PR03MB7707.namprd03.prod.outlook.com (2603:10b6:408:28b::21) by SA6PR03MB7735.namprd03.prod.outlook.com (2603:10b6:806:43c::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Wed, 22 Apr 2026 08:46:47 +0000 Received: from LV3PR03MB7707.namprd03.prod.outlook.com ([fe80::97e8:ef9c:9031:e2bf]) by LV3PR03MB7707.namprd03.prod.outlook.com ([fe80::97e8:ef9c:9031:e2bf%6]) with mapi id 15.20.9846.019; Wed, 22 Apr 2026 08:46:47 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=citrix.com header.i="@citrix.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:x-ms-exchange-senderadcheck" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=g6MG05fQmg/SiM7he6nm4Oo0GDTADvdGsUhJvocpkp5B0IYv5/3ljkK0CK/zzMP4fzmkAIgQkLoVM5vill6tpfr73VDd28NUSwdWxxqJJ2F+0YBNeZz8ZVh7ZYdWoC8sxpXbFcWw1xgThRoqADKrq3fqBnqRoNxMrN/SbhTG1bV4i5t2dOo/MImEmnUjzu6FseWVc83OWD3eRTVzZ4paqJ0fZzlGRk1q8XLQscA8hKhPLcNVx7weJFAoF5eV7suVhn2enOTJ/9OBvtyYD7/ss9b1I9HOmCQAweMGObo69laGvMXvbrf7GuUeMRMsmZwEbAdltneEkH8s0xIJ7XNBZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8a1RXM1tQDcGMOWLsBO8l1ptl3QnA8qqh+dA2O0n26c=; b=b8kitPCN5s4Eh6h/soQpqUb1Joo7owVua7lke997wbHfEkzLe6usZSNcQnLifNRZVRhdQwULwJIkdvlco/PzPB4fBNvqaDuPSBUCKWl3I+jG70KTgxJ+SLXuuqzeIkU+3VONkfuRg2FiLF9/vuklzAlWN8KsPnpaaydgvIxhydYEZY2Z/7zS4QyIU231zXuoi5cnsI8izo7PFH6WfcsD1Nx6RnxS15lbjsS4ZebtTx5GA/wcGNVuW4pdLXoghsNuLdgOTKUbJh/luK2QUhWtaO/I6GD/IKeQiS8PooV5vW4wvH3qs23BIHuTbTPk5z8LEvQxQ/SJF98E0A7xL8zAfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8a1RXM1tQDcGMOWLsBO8l1ptl3QnA8qqh+dA2O0n26c=; b=Hv6JvbklwON707Q0DasfYtezdDkBdel27aMZiTZIrL+gbMdlscKj+PhiFQmtyNhlIQzK16UgeTNO9aRR29OtKjIJ2jE9qSTcRXyxPiaB5vx0bK2+HdmoSWvF/ezRt7JCFjdirzMlEbPD3Z+2ldPCpGCZk44BGYHqzn/XtEL4gH8= From: Bernhard Kaindl To: Jan Beulich CC: "Daniel P. Smith" , =?utf-8?B?TWFyZWsgTWFyY3p5a293c2tpLUfDs3JlY2tp?= , "xen-devel@lists.xenproject.org" , Julien Grall , Stefano Stabellini , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: RE: [PATCH 1/1] xen/efi: Config parsing: Free the same page count as allocated. Thread-Topic: [PATCH 1/1] xen/efi: Config parsing: Free the same page count as allocated. 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776847834-52B75D75-5B52AD73/0/0 X-purgate-type: clean X-purgate-size: 843 On 16.04.2026 11:36, Teddy Astie wrote: > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -4237,11 +4237,13 @@ static int hvm_set_param(struct domain *d, uint32_t index, uint64_t value) > rc = -EINVAL; > break; > case HVM_PARAM_IDENT_PT: > + v = domain_vcpu(d, 0); > + > /* > * Only actually required for VT-x lacking unrestricted_guest > * capabilities. Short circuit the pause if possible. > */ > - if ( paging_mode_shadow(d) || !using_vmx() ) > + if ( paging_mode_shadow(d) || !using_vmx() || !v || vmx_unrestricted_guest(v) ) > { > d->arch.hvm.params[index] = value; > break; Btw, considering the use in vmx_update_guest_cr(), why not also when !hvm_paging_enabled(v)? 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> >>> + errno = ENODEV; > >>> return -1; > >> > >> "No such device", however, isn't quite what we want to convey here. If no > >> better error code can be found that's available on FreeBSD and Linux, I'm > >> inclined to suggest that we stick to ENODATA where available. > > > > Seems like a lot of complexity, for very limited usefulness. > > What's complex about > > #ifndef ENODATA > # define ENODATA ENODEV > #endif > > (perhaps with a brief comment)? IMO it's best if we can avoid instances of ENODATA in the toolstack code base, specially if it's individual ones like this that can be fixed. Otherwise new instances might appear elsewhere, and we don't want to be adding this bodge everywhere if avoidable. If we had a sizable usage of ENODATA in the code base I would indeed recommend such define approach. > > The only > > usage of errno is to be printed in the error message, and for the > > purposes of this function ENODEV is already unique in the function, as > > ENODATA was. > > Right, but "No data available" is more precise than "No such device". > > > FWIW, I think ENODEV is not that far fetched: the CPU being offline > > or the MSR not being present seems like what you would convey by using > > ENODEV. > > Yes, there is a connection. Hence I'm not outright opposed, yet I think > we can do better. > > Formally Anthony is the maintainer of the file, so in a case like this > one maybe he ought to have the final say? I'm fine with letting Anthony resolve. Thanks, Roger. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e421a2a-4a1d-4eb8-cc13-08dea0522d76 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:33:14.3355 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ZKswPy/+HuWuXumqhpQTEsYXxoI0UguotPh5LEUd9dSAeMjr1jNaZAaS4GuloBmIAV89jsDc30zPKGr3WOicrrOquW5bZzaqsn5rj5GmZPM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7710 X-purgate-ID: tlsNG-4011c0/1776850396-45F698B7-E2206A9F/0/0 X-purgate-type: clean X-purgate-size: 2667 In cuart_init_postirq(), two code paths could reach the interrupt-enable write to IER without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IER write, enabling the receive data interrupt with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IER write, arming the receive hardware interrupt line with no handler to service it. On platforms where the GIC receives this asserted line, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure cuart_init_postirq() to use early returns in both error paths. Signed-off-by: Oleksii Moisieiev --- Changes in v3: - clear pending error interrupts before setup_irq call for cadence uart - change uart->irq <=3D 0 to uart->irq =3D=3D 0 since irq is unsigned xen/drivers/char/cadence-uart.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uar= t.c index b2f379833f..8961d39de1 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -72,19 +72,25 @@ static void __init cuart_init_postirq(struct serial_por= t *port) struct cuart *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) - { - uart->irqaction.handler =3D cuart_interrupt; - uart->irqaction.name =3D "cadence-uart"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart= ->irq); - } + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq =3D=3D 0 ) + return; + + uart->irqaction.handler =3D cuart_interrupt; + uart->irqaction.name =3D "cadence-uart"; + uart->irqaction.dev_id =3D port; =20 /* Clear pending error interrupts */ cuart_write(uart, R_UART_RTRIG, 1); cuart_write(uart, R_UART_CISR, ~0); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->ir= q); + /* Do not unmask interrupts if irq handler wasn't set */ + return; + } + /* Unmask interrupts */ cuart_write(uart, R_UART_IDR, ~0); cuart_write(uart, R_UART_IER, UART_SR_INTR_RTRIG); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:33:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:33:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290082.1569774 (Exim 4.92) (envelope-from ) id 1wFTxO-0000y6-UV; Wed, 22 Apr 2026 09:33:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290082.1569774; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07b75fff-a301-4f0b-dec0-08dea0522d46 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:33:14.0000 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: M2WDQRhRHo05/l+j528oiPgc3D6a8bWxvNUcDwnatDkr2sLNiX91V1nNiM3nh4VoVgPay6MFBazLHukXK5z3plFPghX8hQh4n+VG/KgDbgM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7710 X-purgate-ID: tlsNG-4011c0/1776850396-CE36B8B7-1CB6F78A/0/0 X-purgate-type: clean X-purgate-size: 2617 In pl011_init_postirq(), two code paths could reach the interrupt-unmask write to IMSC without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IMSC write, unmasking RTI|OEI|BEI|PEI|FEI|TXI|RXI with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IMSC write, arming all hardware interrupt lines with no handler to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure pl011_init_postirq() to use early returns: return immediately when no valid IRQ is provided, and return after logging the error when setup_irq() fails. The interrupt-enable write to IMSC is only reached when IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev --- Changes in v3: - clear pending error interrupts before setup_irq for pl011 xen/drivers/char/pl011.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 5f9913367d..9e308f4936 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -150,18 +150,24 @@ static void __init pl011_init_postirq(struct serial_p= ort *port) struct pl011 *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) - { - uart->irqaction.handler =3D pl011_interrupt; - uart->irqaction.name =3D "pl011"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); - } + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq <=3D 0 ) + return; + + uart->irqaction.handler =3D pl011_interrupt; + uart->irqaction.name =3D "pl011"; + uart->irqaction.dev_id =3D port; =20 /* Clear pending error interrupts */ pl011_write(uart, ICR, OEI|BEI|PEI|FEI); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); + /* Do not unmask interrupts if irq handler wasn't set */ + return; + } + /* Unmask interrupts */ pl011_write(uart, IMSC, RTI|OEI|BEI|PEI|FEI|TXI|RXI); } --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:33:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:33:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290080.1569763 (Exim 4.92) (envelope-from ) id 1wFTxO-0000rJ-DQ; Wed, 22 Apr 2026 09:33:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290080.1569763; Wed, 22 Apr 2026 09:33:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFTxO-0000rC-Ar; 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b=u80AFmYawfm22rXF8YndzZiuFYeM8AOhwwXdWLGWaEVnZnzoEUiJJJJKAAK9RjPNnBsJA/usoF/+GEY4/pqigZeOWW4F/85un0U+413E0I0oFFfICtN2PRm6CV2LuCVoVlXB+3IPOnJOUKghsGB/7plZtZYHhCz+DKZuP2XEkSZ949TQTzZ8qFQUSJ7zQ/IOi+P6sFDUmpvGhSZ9E/UewtReagGViT1Gn0Vrv28GMxMUDtF3mQNnrMA/lv0EInAQZGbfKXEGs23VW13kJvZ/5vBt5Osk0bdiPo6dsfNQHod82qHa0ZBaTtSJ2b/tQHdHgUpoMxCtskRkMkHT2e/OqQ== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Michal Orzel , Stefano Stabellini , Volodymyr Babchuk , Oleksii Moisieiev Subject: [PATCH v3 0/4] xen/drivers/char: fix IRQ registration failure propagation Thread-Topic: [PATCH v3 0/4] xen/drivers/char: fix IRQ registration failure propagation Thread-Index: AQHc0jsKINuSTAnYQkaUPLk67EYWSw== Date: Wed, 22 Apr 2026 09:33:13 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DU5PR03MB10263:EE_|AM9PR03MB7710:EE_ x-ms-office365-filtering-correlation-id: 5000c751-deae-45db-07c0-08dea0522cc0 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|376014|1800799024|366016|38070700021|56012099003|18002099003; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5000c751-deae-45db-07c0-08dea0522cc0 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:33:13.1405 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bzWcpDqqkLCIwq0n7AKvo0EGQAly5kOZ3XU7ITyzU7nclt+YbScIy6+2tclJyIZYSCZaUE3kKQSMu2L3stLnbBv2Gtq0TwsWpReTV9nA10E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7710 X-purgate-ID: tlsNG-4011c0/1776850395-CF97E8B7-BB155827/0/0 X-purgate-type: clean X-purgate-size: 2200 This series fixes a common bug pattern found in several Xen UART drivers: when setup_irq() fails during post-IRQ initialization, drivers log the error but continue executing and unconditionally unmask hardware interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Patch 1, originally submitted as a standalone fix in v1, addresses the issue in the SCIF driver and moves the hardware error-flag clearing sequence to before the setup_irq() call so that stale error bits are cleared unconditionally. Patches 2-4 apply the same early-return fix to the pl011, cadence-uart, and exynos4210-uart drivers. The pl011 and cadence-uart drivers additionally had a positive-condition IRQ guard (if uart->irq > 0) that could fall through to the interrupt unmask even when no valid IRQ was provided. Both are restructured to use the early-return idiom. Changes in v3: - clear pending error interrupts before setup_irq for pl011 - clear pending error interrupts before setup_irq call for cadence uart - change uart->irq <=3D 0 to uart->irq =3D=3D 0 since irq is unsigned - skip clearing pending interrupts if setup_irq was failed because according to the 13.4.1.13 of the RM: it must be cleared after cleaning interrupt pending in INTC. Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description Oleksii Moisieiev (4): xen/drivers/char: fix SCIF IRQ registration failure propagation xen/drivers/char/pl011: fix IRQ registration failure propagation xen/drivers/char/cadence-uart: fix IRQ registration failure propagation xen/drivers/char: fix exynos4210 IRQ registration failure propagation xen/drivers/char/cadence-uart.c | 22 ++++++++++++++-------- xen/drivers/char/exynos4210-uart.c | 4 ++++ xen/drivers/char/pl011.c | 22 ++++++++++++++-------- xen/drivers/char/scif-uart.c | 16 ++++++++++++---- 4 files changed, 44 insertions(+), 20 deletions(-) --=20 2.43.0 base-commit: 077dcf9841ad7df4e63c718249d8ac95f8a709ff branch: amoi_dfmea_scifv3= From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:33:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:33:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290084.1569785 (Exim 4.92) (envelope-from ) id 1wFTxP-0001FB-Hh; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1bcbeea7-831e-4d47-c909-08dea0522dd6 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:33:14.9617 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SBCvcigsaohM8T65ZEV56R3NvDn/wOKJdpsTXihQCyeVlKOPlU/UhkeJFDZETaygCcXZ48MAGQ8wNYjfleKQbzbQoTWWY1hOQTbp440QFUc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7710 X-purgate-ID: tlsNG-4011c0/1776850396-473738B7-89EAAD5C/0/0 X-purgate-type: clean X-purgate-size: 1655 In exynos4210_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled receive and transmit interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Add an early return in the setup_irq() error branch so that the interrupt-enable writes to UINTM and UMCON are skipped when IRQ registration fails. Signed-off-by: Oleksii Moisieiev --- Changes in v3: - skip clearing pending interrupts if setup_irq was failed because according to the 13.4.1.13 of the RM: it must be cleared after cleaning interrupt pending in INTC. xen/drivers/char/exynos4210-uart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos42= 10-uart.c index 58901df554..2e5860ea2b 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -199,8 +199,12 @@ static void __init exynos4210_uart_init_postirq(struct= serial_port *port) uart->irqaction.dev_id =3D port; =20 if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %d\n"= , uart->irq); + /* Don't enable interrupts if irq setup was failed */ + return; + } =20 /* Unmask interrupts */ exynos4210_write(uart, UINTM, ~UINTM_ALLI); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:33:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:33:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290081.1569766 (Exim 4.92) (envelope-from ) id 1wFTxO-0000uH-JJ; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40a909f0-720c-4429-84e7-08dea0522d03 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:33:13.6031 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ulqNtfuQBBUJ+pn98mgs5l4dSKIRdQ3V6MRkh0vYRGKjU92HeTlUTN3DFP5vjmwuV2oIPelJSuxcmYGUw3xs5xIN1RVcuo/A5SVDT/G+wEo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB7710 X-purgate-ID: tlsNG-4011c0/1776850395-815848B7-4717532A/0/0 X-purgate-type: clean X-purgate-size: 3042 In scif_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally writing TIE|RIE|REIE into the Serial Control Register (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, RX data ready, receive error) with no handler registered to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. The fix adds an early return inside the error branch. The interrupt-enable write to SCSCR is skipped entirely when no handler is registered. SCIF TX continues to operate correctly after this change. The Xen serial framework never calls serial_async_transmit() for SCIF, so port->txbuf is always NULL. This causes __serial_putc() to take the synchronous finite-capacity path, which polls the SCFSR_TDFE hardware flag directly and does not depend on the interrupt mechanism. RX wouldn't work if irq wasn't registered. As a secondary clean-up, the hardware error-flag clearing sequence is moved to before the setup_irq() call so that error bits accumulated since init_preirq() are cleared unconditionally, regardless of whether IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev --- (no changes since v2) Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description xen/drivers/char/scif-uart.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 888821a3b8..673a2d3800 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct seri= al_port *port) uart->irqaction.name =3D "scif_uart"; uart->irqaction.dev_id =3D port; =20 - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", - uart->irq); - /* Clear all errors */ if ( scif_readw(uart, params->status_reg) & params->error_mask ) scif_writew(uart, params->status_reg, ~params->error_mask); if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", + uart->irq); + /* + * If the IRQ handler could not be installed (setup_irq failed), + * do not enable TX/RX or error interrupts. Serial transmit will + * fall back to polling mode. + */ + return; + } + /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | params->irq_flags); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:34:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:34:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290125.1569807 (Exim 4.92) (envelope-from ) id 1wFTyl-0003Ml-8q; Wed, 22 Apr 2026 09:34:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290125.1569807; Wed, 22 Apr 2026 09:34:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFTyl-0003Me-6G; Wed, 22 Apr 2026 09:34:43 +0000 Received: by outflank-mailman (input) for mailman id 1290125; Wed, 22 Apr 2026 09:34:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFTyj-0003MV-Ox for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 02:34:39 -0700 (PDT) MIME-Version: 1.0 References: <7053b8c14bbe50cc855dad0a82cde2bb10153d2b.1776266307.git.bertrand.marquis@arm.com> In-Reply-To: <7053b8c14bbe50cc855dad0a82cde2bb10153d2b.1776266307.git.bertrand.marquis@arm.com> From: Jens Wiklander Date: Wed, 22 Apr 2026 11:34:27 +0200 X-Gm-Features: AQROBzCz5_jC5njY6PS3Hdagxogu3g53p99f8Avu2f8VjavqSIrjuDcbIdWOC9k Message-ID: Subject: Re: [PATCH 2/6] xen/arm: ffa: Track hypervisor notifications in a bitmap To: Bertrand Marquis Cc: xen-devel@lists.xenproject.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1776850481-83961161-D049620E/0/0 X-purgate-type: clean X-purgate-size: 5630 Hi Bertrand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > Hypervisor notifications are currently tracked with a dedicated > buff_full_pending boolean. That state only represents a single HYP > notification bit and keeps HYP bitmap handling tied to single-purpose > bookkeeping. > > Replace the boolean with a hypervisor notification bitmap protected by > notif_lock. INFO_GET reports pending when the bitmap is non-zero, GET > returns and clears the HYP bitmap under the lock, and RX-buffer-full > sets FFA_NOTIF_RX_BUFFER_FULL in the bitmap instead of updating > separate state. > > Initialize and clear the bitmap during domain lifecycle handling, and > use ctx->ffa_id for bitmap create and destroy so the notification state > stays tied to the cached FF-A endpoint ID. > > No functional changes. > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa_notif.c | 46 ++++++++++++++++++++++++++-------- > xen/arch/arm/tee/ffa_private.h | 9 +++++-- > 2 files changed, 43 insertions(+), 12 deletions(-) > > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index 07bc5cb3a430..d15119409a25 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -94,8 +94,15 @@ void ffa_handle_notification_info_get(struct cpu_user_= regs *regs) > > notif_pending =3D test_and_clear_bool(ctx->notif.secure_pending); > if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + { > notif_pending |=3D test_and_clear_bool(ctx->notif.vm_pending); > > + spin_lock(&ctx->notif.notif_lock); > + if ( ctx->notif.hyp_pending ) > + notif_pending =3D true; > + spin_unlock(&ctx->notif.notif_lock); Isn't this a functional change? Before this patch, we didn't consider ctx->notif.buff_full_pending here. Am I missing something? > + } > + > if ( notif_pending ) > { > /* A pending global notification for the guest */ > @@ -174,12 +181,17 @@ void ffa_handle_notification_get(struct cpu_user_re= gs *regs) > w6 =3D resp.a6; > } > > - if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && > - flags & FFA_NOTIF_FLAG_BITMAP_HYP && > - test_and_clear_bool(ctx->notif.buff_full_pending) ) > + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > { > - ACCESS_ONCE(ctx->notif.vm_pending) =3D false; > - w7 =3D FFA_NOTIF_RX_BUFFER_FULL; > + spin_lock(&ctx->notif.notif_lock); > + > + if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pendi= ng ) > + { > + w7 =3D ctx->notif.hyp_pending; > + ctx->notif.hyp_pending =3D 0; > + } > + > + spin_unlock(&ctx->notif.notif_lock); > } > > ffa_set_regs(regs, FFA_SUCCESS_32, 0, w2, w3, w4, w5, w6, w7); > @@ -207,12 +219,17 @@ int32_t ffa_handle_notification_set(struct cpu_user= _regs *regs) > void ffa_raise_rx_buffer_full(struct domain *d) > { > struct ffa_ctx *ctx =3D d->arch.tee; > + uint32_t prev_bitmap; > > if ( !ctx ) > return; > > - ACCESS_ONCE(ctx->notif.buff_full_pending) =3D true; > - if ( !test_and_set_bool(ctx->notif.vm_pending) ) > + spin_lock(&ctx->notif.notif_lock); > + prev_bitmap =3D ctx->notif.hyp_pending; > + ctx->notif.hyp_pending |=3D FFA_NOTIF_RX_BUFFER_FULL; > + spin_unlock(&ctx->notif.notif_lock); > + > + if ( !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) ) Do we need to check for FFA_NOTIF_RX_BUFFER_FULL? Isn't !prev_bitmap more accurate, if any other bit would ever be used in the bitmap? Cheers, Jens > inject_notif_pending(d); > } > #endif > @@ -426,12 +443,15 @@ void ffa_notif_init(void) > > int ffa_notif_domain_init(struct domain *d) > { > + struct ffa_ctx *ctx =3D d->arch.tee; > int32_t res; > > + spin_lock_init(&ctx->notif.notif_lock); > + ctx->notif.hyp_pending =3D 0; > + > if ( fw_notif_enabled ) > { > - > - res =3D ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_= vcpus); > + res =3D ffa_notification_bitmap_create(ctx->ffa_id, d->max_vcpus= ); > if ( res ) > return -ENOMEM; > } > @@ -441,10 +461,16 @@ int ffa_notif_domain_init(struct domain *d) > > void ffa_notif_domain_destroy(struct domain *d) > { > + struct ffa_ctx *ctx =3D d->arch.tee; > + > + spin_lock(&ctx->notif.notif_lock); > + ctx->notif.hyp_pending =3D 0; > + spin_unlock(&ctx->notif.notif_lock); > + > /* > * Call bitmap_destroy even if bitmap create failed as the SPMC will > * return a DENIED error that we will ignore. > */ > if ( fw_notif_enabled ) > - ffa_notification_bitmap_destroy(ffa_get_vm_id(d)); > + ffa_notification_bitmap_destroy(ctx->ffa_id); > } > diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat= e.h > index c291f32b56ff..5693772481ed 100644 > --- a/xen/arch/arm/tee/ffa_private.h > +++ b/xen/arch/arm/tee/ffa_private.h > @@ -340,9 +340,14 @@ struct ffa_ctx_notif { > bool vm_pending; > > /* > - * True if domain has buffer full notification pending > + * Lock protecting the hypervisor-managed notification state. > */ > - bool buff_full_pending; > + spinlock_t notif_lock; > + > + /* > + * Bitmap of pending hypervisor notifications (for HYP bitmap querie= s). > + */ > + uint32_t hyp_pending; > }; > > struct ffa_ctx { > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:44:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:44:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290140.1569832 (Exim 4.92) (envelope-from ) id 1wFU8J-0005tS-LE; Wed, 22 Apr 2026 09:44:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290140.1569832; Wed, 22 Apr 2026 09:44:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFU8J-0005st-FK; Wed, 22 Apr 2026 09:44:35 +0000 Received: by outflank-mailman (input) for mailman id 1290140; Wed, 22 Apr 2026 09:44:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFU8H-0005eC-VF for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 09:44:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFU8H-00E82D-By for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:44:33 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e89879-5cb7-0a2a0a5109dd-0a2a4503bf1a-48 for ; Wed, 22 Apr 2026 11:44:33 +0200 Received: from [209.85.167.46] (helo=mail-lf1-f46.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e89880-672d-0a2a45030019-d155a72ed0f4-3 for ; Wed, 22 Apr 2026 11:44:32 +0200 Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-5a41099fa86so4655054e87.2 for ; Wed, 22 Apr 2026 02:44:32 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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When a partial FDT (pfdt) is provided, special care is needed during initialization of next_phandle, as the pfdt may already contain a dummy interrupt controller node with a phandle assigned to it. next_phandle must therefore be initialized to one past the highest phandle already present in the pfdt, to avoid collisions. Since next_phandle may be needed for the very first guest node generated, domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). The new call site also aligns better with the existing comment stating that domain_handle_dtb_boot_module() must be called before the rest of the device tree is generated. Introduce alloc_phandle() to ensure that phandles allocated for guest nodes do not overlap the Xen-reserved phandle range. This helper will be used by subsequent patches (by RISC-V at the moment). Signed-off-by: Oleksii Kurochko --- Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandle is generated in this example not by get_next_free_phandle(). For non RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC it is interrupt controller which provides MSI and connects to each CPU. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt --- Changes in v2: - s/free_phandle/next_phandle. - s/get_next_free_phandle/alloc_phandle. --- xen/common/device-tree/dom0less-build.c | 44 ++++++++++++++++++------- xen/include/xen/fdt-domain-build.h | 6 ++++ xen/include/xen/fdt-kernel.h | 3 ++ 3 files changed, 41 insertions(+), 12 deletions(-) diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 840d14419da2..ca3ac84a3ef3 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, if ( res < 0 ) goto out; + /* + * Find the highest phandle in the partial FDT so next_phandle starts + * above it, avoiding collisions with pfdt's own phandle assignments. + */ + res = fdt_generate_phandle(pfdt, &kinfo->next_phandle); + if ( res ) + { + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; + goto out; + } + + if ( kinfo->next_phandle >= GUEST_PHANDLE_GIC ) + { + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); + res = -EOVERFLOW; + goto out; + } + for ( node_next = fdt_first_subnode(pfdt, 0); node_next > 0; node_next = fdt_next_subnode(pfdt, node_next) ) @@ -459,6 +477,8 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); kinfo->phandle_intc = GUEST_PHANDLE_GIC; + kinfo->next_phandle = 1; + BUILD_BUG_ON(GUEST_PHANDLE_GIC == 1); #ifdef CONFIG_GRANT_TABLE kinfo->gnttab_start = GUEST_GNTTAB_BASE; @@ -499,6 +519,18 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; + /* + * domain_handle_dtb_boot_module() must be called before the rest of the + * device tree is generated because it sets phandle_intc and next_phandle, + * which subsequent node generation depends on. + */ + if ( kinfo->dtb ) + { + ret = domain_handle_dtb_boot_module(d, kinfo); + if ( ret ) + goto err; + } + ret = make_chosen_node(kinfo); if ( ret ) goto err; @@ -516,18 +548,6 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - /* - * domain_handle_dtb_boot_module has to be called before the rest of - * the device tree is generated because it depends on the value of - * the field phandle_intc. - */ - if ( kinfo->dtb ) - { - ret = domain_handle_dtb_boot_module(d, kinfo); - if ( ret ) - goto err; - } - ret = make_intc_domU_node(kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 1d9e77df0eb3..a604f3983fe6 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -63,6 +63,12 @@ int find_unallocated_memory(const struct kernel_info *kinfo, unsigned long e_gfn, void *data)); +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ +static inline uint32_t alloc_phandle(struct kernel_info *kinfo) +{ + return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index aa977a50f4fc..438adfe3855b 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -44,6 +44,9 @@ struct kernel_info { /* Interrupt controller phandle */ uint32_t phandle_intc; + /* Next free phandle available for assigning to guest device nodes */ + uint32_t next_phandle; + /* loader to use for this kernel */ void (*load)(struct kernel_info *info); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:44:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:44:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290141.1569837 (Exim 4.92) (envelope-from ) id 1wFU8K-00063P-3x; Wed, 22 Apr 2026 09:44:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290141.1569837; Wed, 22 Apr 2026 09:44:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFU8J-00062U-Tx; Wed, 22 Apr 2026 09:44:35 +0000 Received: by outflank-mailman (input) for mailman id 1290141; Wed, 22 Apr 2026 09:44:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFU8J-0005rJ-86 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 09:44:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFU8I-00E82D-LI for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:44:34 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e89880-5cb7-0a2a0a5109dd-0a2a4502b5ae-12 for ; Wed, 22 Apr 2026 11:44:34 +0200 Received: from [209.85.208.178] (helo=mail-lj1-f178.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e89882-af86-0a2a45020019-d155d0b2a8a6-3 for ; Wed, 22 Apr 2026 11:44:34 +0200 Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-38dd9f0fdc6so65609271fa.0 for ; Wed, 22 Apr 2026 02:44:34 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a41cc7f832sm3494193e87.28.2026.04.22.02.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 02:44:32 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776851073; x=1777455873; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QdrnKw1Nlrntb+VNA/letozKDP4oOCl6jEuvPSlVYk8=; b=Y3sMvdCND6IDq5Mj7XAiwD5w7VzHeVcDKyVMsNbALvrTbAi8o+cb3EI18sCodetykM LLSplgYQD8pnnFmsC75sSbBo2L2oeAYoI7DHSg1rPTt9U9GENoi4uPJacPwjTHZBpPrq r3hA1dz5/+w/SH28OpFSA31/Z17Chefbb801AFRLu5PiLpgrD+UUu8KxiHuEtoj+BW7f cfLsDdbCdIFr7avCRMHM5a+VjvQVkB+BlEpbNUw+pwdGyX8xpqhG2ZcPUU5iCU52lytm u30k8Iy8oamREKBgW+87EOynqLlHLdEFVMr42FkW0Z1iGANGJ8V3XoL4Zc2p5vmLMCPh n0RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776851073; x=1777455873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QdrnKw1Nlrntb+VNA/letozKDP4oOCl6jEuvPSlVYk8=; b=TRlnUruI8NcAVLndQbR+r0BOHRI7TwmOqNOytqJIkh4PN7hlZsA6XxmQWKSCqWtci4 BxV+aHri6DTqy/Wk/UatlkODMl2ZUTu9iEAZT9EDisJGFIJg1NM9XnuqtSQpdugGouaT nkXnon8h7ZYt7iJcQX0ztFzWkRVXJmK/w4tk4WhFHRynZZDaU/wElaessicIDmT3vcy4 rNBHAnWFlxIgSyjhewy6D3pfZMJum2sKimnl2T3oSRK46EhBJ9QK7hz6Bt710EjKC0FP KEGf2NxI+a81ZIiwO0uzNvMpBiyFRa+CIUn5lNooa7vSCMe5eJsYxbIORA7IqK2SPZWQ 5ZoQ== X-Gm-Message-State: AOJu0Yzz9e2MxL1jJEPGeJEZ75VxHHZy+O5IRwUPOHZFq1GCTHBUyE24 uSSPUi+4NZSETkuCAiZYY6MgNljljkdSpvsdXFIjyC7V9lXw1ZXTY7CZ0pXRwQ== X-Gm-Gg: AeBDiesWLOaPsufrk5eoUM7QlgnDI6NtWI4AsX7WxtZE4SlHjwavGxhI5gr/+XGeuGB FNooakBYLJSW4FXGDtyfkJwEqQYJYMm5wvAMJXRtCBDZvYTU1TPtw0r6YK+kcVLrWPyGk9SRAJ1 aEncwBbXTOTvPUjD4/QLqxMSrQWgP2Z6S5DbnuRSXHFctCF4Pv0dQCQgH9HY7taSaK5hjWiqm6j V7zPaBJdMFcK8RcY0F21DjmE1EvcevPkcjwqiF/wztsayc9QwiEWcvMYRPqXCMnXVijWeVwMFzW 135bGOR/lqm+/RbXKp0i+d9xxpbUH085P2YQ4K7+VLIVsY7Y20ygvBSf6WTKJ2OY/JlDaTu8F8Z 2rFHU1x6BCc14JLwmGouCiRJ/enUjwf0DbOOhGFeMdmyAp+zWfYHzOvHXCgmNomv9Pc1D0v7mHL rf7oKPIEMvL9vH2d9P8uBevR1pd6EW4lClm8rFIuHv4dz8Ngm+cA8X2x7gEyntpT4odEYVM0qcE 6zY X-Received: by 2002:a05:6512:31d3:b0:5a4:156:aea3 with SMTP id 2adb3069b0e04-5a417174a77mr6977256e87.7.1776851073183; Wed, 22 Apr 2026 02:44:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE Date: Wed, 22 Apr 2026 11:44:19 +0200 Message-ID: <61c33c15d046110b5c99490f54191facf18068e1.1776780944.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1776851074-898C3161-DB3835E2/10/73395122804 X-purgate-type: spam X-purgate-size: 11008 As domain type is part of common code now there is no any reason to have architecture-specific set_domain_type() functions so it is dropped. Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE for consistency. Also, drop and add some parentheses to be aligned with the similar if() below. x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no longer builds, the fallback is currently only relevant for arm32. Signed-off-by: Oleksii Kurochko --- Changes in v2: - Update the commit message. - Move HAS_DOMAIN_TYPE to xen/common/Kconfig. - Return set_domain_type(), move it to xen/fdt-domain-build.h and make it static inline. - s/CONFIG_ARM_64/CONFIG_HAS_DOMAIN for the places where kinfo->type is used. - Drop parantethes around cpu_has_el1_32 in if() and add around (kinfo->type == DOMAIN_32BIT) to be consistent with the similar check below. - Fix comment code style. - Add __packed to definition of enum domain_type --- xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 ++-- xen/arch/arm/dom0less-build.c | 14 -------------- xen/arch/arm/domain_build.c | 12 +++++------- xen/arch/arm/include/asm/domain.h | 12 ------------ xen/arch/arm/include/asm/kernel.h | 4 ---- xen/arch/arm/kernel.c | 16 ++++++++-------- xen/common/Kconfig | 3 +++ xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++++++++ xen/include/xen/fdt-domain-build.h | 9 +++++++++ xen/include/xen/fdt-kernel.h | 5 +++++ xen/include/xen/sched.h | 4 ++++ 13 files changed, 50 insertions(+), 49 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..79622b46a10d 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -7,6 +7,7 @@ config ARM_64 def_bool y depends on !ARM_32 select 64BIT + select HAS_DOMAIN_TYPE select HAS_FAST_MULTIPLY select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c index 8720d126c97d..9e9a29eb1e78 100644 --- a/xen/arch/arm/arm64/domctl.c +++ b/xen/arch/arm/arm64/domctl.c @@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type) return -EINVAL; if ( domain_tot_pages(d) != 0 ) return -EBUSY; - if ( d->arch.type == type ) + if ( d->type == type ) return 0; - d->arch.type = type; + d->type = type; if ( is_64bit_domain(d) ) for_each_vcpu(d, v) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f73c65e5151 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) return 0; } -/* TODO: make arch.type generic ? */ -#ifdef CONFIG_ARM_64 -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* type must be set before allocate memory */ - d->arch.type = kinfo->arch.type; -} -#else -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* Nothing to do */ -} -#endif - int __init init_vuart(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 98f5dab35e83..1efddc60ef0a 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1772,15 +1772,15 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) BUG_ON(d->vcpu[0] == NULL); BUG_ON(v->is_initialised); -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) + if ( !cpu_has_el1_32 && (kinfo->type == DOMAIN_32BIT) ) { printk("Platform does not support 32-bit domain\n"); return -EINVAL; } - if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) ) + if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) ) { printk("SVE is not available for 32-bit domain\n"); return -EINVAL; @@ -1894,10 +1894,8 @@ int __init construct_hwdom(struct kernel_info *kinfo, iommu_hwdom_init(d); -#ifdef CONFIG_ARM_64 - /* type must be set before allocate_memory */ - d->arch.type = kinfo->arch.type; -#endif + set_domain_type(d, kinfo); + find_gnttab_region(d, kinfo); if ( is_domain_direct_mapped(d) ) allocate_memory_11(d, kinfo); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index f95ad1285e6e..2d4c1bdecb66 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -18,18 +18,6 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; -#ifdef CONFIG_ARM_64 -enum domain_type { - DOMAIN_32BIT, - DOMAIN_64BIT, -}; -#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT) -#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT) -#else -#define is_32bit_domain(d) (1) -#define is_64bit_domain(d) (0) -#endif - struct vtimer { struct vcpu *v; int irq; diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h index 7c3b7fde5b64..21f4273fa1b5 100644 --- a/xen/arch/arm/include/asm/kernel.h +++ b/xen/arch/arm/include/asm/kernel.h @@ -10,10 +10,6 @@ struct arch_kernel_info { -#ifdef CONFIG_ARM_64 - enum domain_type type; -#endif - /* Enable pl011 emulation */ bool vpl011; }; diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 3c613cdb233f..a5554714cd7b 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -100,8 +100,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) const struct membanks *mem = kernel_info_get_mem(info); paddr_t load_addr; -#ifdef CONFIG_ARM_64 - if ( (info->arch.type == DOMAIN_64BIT) && (info->image.start == 0) ) +#ifdef CONFIG_HAS_DOMAIN_TYPE + if ( (info->type == DOMAIN_64BIT) && (info->image.start == 0) ) return mem->bank[0].start + info->image.text_offset; #endif @@ -268,14 +268,14 @@ int __init kernel_uimage_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE switch ( uimage.arch ) { case IH_ARCH_ARM: - info->arch.type = DOMAIN_32BIT; + info->type = DOMAIN_32BIT; break; case IH_ARCH_ARM64: - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; break; default: printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch); @@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, info->load = kernel_zimage_load; - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; return 0; } @@ -396,8 +396,8 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 - info->arch.type = DOMAIN_32BIT; +#ifdef CONFIG_HAS_DOMAIN_TYPE + info->type = DOMAIN_32BIT; #endif return 0; diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 0a20aa0a1249..ab62e9b07546 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -29,6 +29,9 @@ config DOM0LESS_BOOT config DOMAIN_BUILD_HELPERS bool +config HAS_DOMAIN_TYPE + bool + config GRANT_TABLE bool "Grant table support" if EXPERT default y diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h index faaf660424b2..4118dec76c0a 100644 --- a/xen/include/xen/dom0less-build.h +++ b/xen/include/xen/dom0less-build.h @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, int make_intc_domU_node(struct kernel_info *kinfo); int make_arch_nodes(struct kernel_info *kinfo); -void set_domain_type(struct domain *d, struct kernel_info *kinfo); - int init_intc_phandle(struct kernel_info *kinfo, const char *name, const int node_next, const void *pfdt); diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 93c0fd00c1d7..fcb6dc136517 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -13,6 +13,19 @@ struct guest_area { void *map; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE +enum __packed domain_type { + DOMAIN_32BIT, + DOMAIN_64BIT, +}; +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) +#elif !defined(CONFIG_64BIT) +/* On 32-bit-only platforms all domains are 32-bit. */ +#define is_32bit_domain(d) (true) +#define is_64bit_domain(d) (false) +#endif + #include typedef union { diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index b7f6b1fc36a9..6ad9e8fd1642 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -7,6 +7,7 @@ #include #include #include +#include #include struct domain; @@ -69,6 +70,14 @@ static inline uint32_t alloc_phandle(struct kernel_info *kinfo) return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; } +static inline void set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ +#ifdef CONFIG_HAS_DOMAIN_TYPE + /* Type must be set before allocate memory */ + d->type = kinfo->type; +#endif +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 438adfe3855b..8bcc9471814b 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -9,6 +9,7 @@ #include #include +#include #include #if __has_include() @@ -69,6 +70,10 @@ struct kernel_info { } image; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + #if __has_include() struct arch_kernel_info arch; #endif diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..00db1da12f21 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -386,6 +386,10 @@ struct domain { domid_t domain_id; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + unsigned int max_vcpus; uint64_t unique_id; /* Unique domain identifier */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:44:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:44:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290138.1569818 (Exim 4.92) (envelope-from ) id 1wFU8I-0005eP-6k; Wed, 22 Apr 2026 09:44:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290138.1569818; Wed, 22 Apr 2026 09:44:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFU8I-0005eI-1p; Wed, 22 Apr 2026 09:44:34 +0000 Received: by outflank-mailman (input) for mailman id 1290138; Wed, 22 Apr 2026 09:44:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFU8G-0005e6-Bz for xen-devel@lists.xenproject.org; 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For example, on the RISC-V side in make_cpus_node() [1] it is necessary to know which phandle number is unused to use it for device tree node generation. Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandles for imsic and riscv,cpu-intc are generated in this example not by get_next_free_phandle(), that is why they have such big numbers. For non-RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC is an interrupt controller that provides MSI and connects to each CPU. So (based on the DTS above) for APLIC, kinfo->phandle_intc is reused, which will also be re-used for the device node's interrupt property. For all others, I just introduced GUEST_PHANDLE_LAST [2] and used it for generation [3]. But I expect that it could be useful for other architectures too so I just moved it to common and re-use pfdt to understand what the maximum used phandle is. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt [2] https://lore.kernel.org/xen-devel/ccd6d21b224b478c88ca5f2fdd2d1dd507671510.1773157782.git.oleksii.kurochko@gmail.com/ [3] https://lore.kernel.org/xen-devel/fd64b8526a23e9d7775b9b48c5a933b0673c4fba.1773157782.git.oleksii.kurochko@gmail.com/ ************************************* Another thing introduced in this patch series is moving domain type to common code as several architectures (ARM and RISC-V for now) use them and it looks pretty architecture-independent. Also, is_64bit_domain() is used by dom0less common code, so I found it useful also to move is_{32,64}bit_domain macros to common code. ************************************* And the last thing is changing the prototype of make_cpus_node() to be aligned with other make_*_node() and since RISC-V will need access to the free_phandle field (even if it will be moved to kinfo->arch.free_phandle) and for the reason that this ->free_phandle is updated in make_*_node(), the kinfo argument is passed as non-const. CI: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2468475835 --- Changes in v2: - Address the comments from ML. --- Oleksii Kurochko (3): xen/dom0less: introduce next_phandle in struct kernel_info xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() xen: introduce CONFIG_HAS_DOMAIN_TYPE xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 +-- xen/arch/arm/dom0less-build.c | 14 -------- xen/arch/arm/domain_build.c | 17 +++++---- xen/arch/arm/include/asm/domain.h | 12 ------- xen/arch/arm/include/asm/kernel.h | 4 --- xen/arch/arm/kernel.c | 16 ++++----- xen/common/Kconfig | 3 ++ xen/common/device-tree/dom0less-build.c | 46 ++++++++++++++++++------- xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++ xen/include/xen/fdt-domain-build.h | 17 ++++++++- xen/include/xen/fdt-kernel.h | 8 +++++ xen/include/xen/sched.h | 4 +++ 14 files changed, 96 insertions(+), 65 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:44:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:44:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290139.1569826 (Exim 4.92) (envelope-from ) id 1wFU8J-0005rT-Cv; Wed, 22 Apr 2026 09:44:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290139.1569826; Wed, 22 Apr 2026 09:44:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFU8J-0005rM-8q; Wed, 22 Apr 2026 09:44:35 +0000 Received: by outflank-mailman (input) for mailman id 1290139; Wed, 22 Apr 2026 09:44:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFU8H-0005eD-VS for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 09:44:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFU8H-006sRK-CS for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:44:33 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e89881-2eae-0a2a0a5409dd-0a2a4506d542-0 for ; Wed, 22 Apr 2026 11:44:33 +0200 Received: from [209.85.167.42] (helo=mail-lf1-f42.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e89881-7371-0a2a45060019-d155a72ac892-3 for ; Wed, 22 Apr 2026 11:44:33 +0200 Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-59e4a04f059so5864904e87.2 for ; Wed, 22 Apr 2026 02:44:33 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Align prototype with what other make_*_node() are passed. 2. A follow-up RISC-V patch will call get_next_free_phandle() inside make_cpus_node(), requiring mutable access to kinfo->free_phandle. Signed-off-by: Oleksii Kurochko --- Look at the footer to the prev. patch to understand why phandle is needed inside cpu node. --- Changes in v2: - Properly initialize local variable fdt in Arm's make_cpus_node(). --- xen/arch/arm/domain_build.c | 5 +++-- xen/common/device-tree/dom0less-build.c | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 60a7cbf915a5..98f5dab35e83 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1164,7 +1164,7 @@ int __init make_psci_node(void *fdt) return res; } -int __init make_cpus_node(const struct domain *d, void *fdt) +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) { int res; const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); @@ -1178,6 +1178,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) /* Keep the compiler happy with -Og */ bool clock_valid = false; uint64_t mpidr_aff; + void *fdt = kinfo->fdt; dt_dprintk("Create cpus node\n"); @@ -1626,7 +1627,7 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo, if ( res ) return res; - res = make_cpus_node(d, kinfo->fdt); + res = make_cpus_node(d, kinfo); if ( res ) return res; diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index ca3ac84a3ef3..f8b1166e4169 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -535,7 +535,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - ret = make_cpus_node(d, kinfo->fdt); + ret = make_cpus_node(d, kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index a604f3983fe6..b7f6b1fc36a9 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -25,7 +25,7 @@ int construct_domain(struct domain *d, struct kernel_info *kinfo); int construct_hwdom(struct kernel_info *kinfo, const struct dt_device_node *node); int make_chosen_node(const struct kernel_info *kinfo); -int make_cpus_node(const struct domain *d, void *fdt); +int make_cpus_node(const struct domain *d, struct kernel_info *kinfo); int make_hypervisor_node(struct domain *d, const struct kernel_info *kinfo, int addrcells, int sizecells); int make_memory_node(const struct kernel_info *kinfo, int addrcells, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 09:57:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 09:57:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290186.1569854 (Exim 4.92) (envelope-from ) id 1wFULB-0001aV-3P; Wed, 22 Apr 2026 09:57:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290186.1569854; Wed, 22 Apr 2026 09:57:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFULA-0001aO-W0; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PAVPR03MB10102.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 645f12f4-bd57-4f23-f05d-08dea0559c3e X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Apr 2026 09:57:48.6636 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NzirEGj5FKaYzJOhLPwA1GpNcxoP2eUjQk/u6vUu3jQKn0PJXH/8gPCY2WgRh3uoaY7FObsKZs9oAk5njiIWKQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR03MB10597 X-purgate-ID: tlsNG-42698a/1776851870-0777AF3B-3ED51FD0/0/0 X-purgate-type: clean X-purgate-size: 6015 Allow for removing devices from SMMUv3. arm_smmu_deassign_dev handles most of the work by disabling ATS and zeroing STEs. Additionally, unset the dt_device_is_protected flag and free no longer needed smmu_master. Free iommu_fwspec for PCI devices only, for DT devices it is handled by generic IOMMU layer. Rework dt_device_set_protected to accept a boolean parameter, update callsites. Signed-off-by: Mykyta Poturai --- Tested on QEMU with SRIOV series[1] by repeatedly enabling/disabling VFs. [1]: https://patchew.org/Xen/cover.1772806036.git.mykyta._5Fpoturai@epam.co= m/ V2->V3: * free fwspec for pci devices * remove testing note from commit message V1->V2: * check for phantom functions * simplify pci/dt device split * improve error handling * don't try to free master for unprotected devices * rework dt_device_set_protected --- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- xen/drivers/passthrough/arm/smmu-v3.c | 65 +++++++++++++++++++++++- xen/drivers/passthrough/arm/smmu.c | 4 +- xen/include/xen/device_tree.h | 5 +- 4 files changed, 70 insertions(+), 6 deletions(-) diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr= ough/arm/ipmmu-vmsa.c index fa9ab9cb13..0648f9b407 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -1367,7 +1367,7 @@ static int ipmmu_add_device(u8 devfn, struct device *= dev) } =20 /* Let Xen know that the master device is protected by an IOMMU. *= / - dt_device_set_protected(dev_to_dt(dev)); + dt_device_set_protected(dev_to_dt(dev), true); } #ifdef CONFIG_HAS_PCI if ( dev_is_pci(dev) ) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug= h/arm/smmu-v3.c index bf153227db..a46c421399 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1493,6 +1493,68 @@ static int arm_smmu_assign_dev(struct domain *d, u8 = devfn, struct device *dev, static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, struct device *dev); =20 +static int arm_smmu_remove_device(u8 devfn, struct device *dev) +{ + struct arm_smmu_master *master; + struct iommu_fwspec *fwspec; + struct domain *d =3D NULL; + + fwspec =3D dev_iommu_fwspec_get(dev); + if ( !fwspec ) + return -ENODEV; + + master =3D dev_iommu_priv_get(dev); + if ( !master ) + return -ENODEV; + + if ( IS_ENABLED(CONFIG_HAS_PCI) && dev_is_pci(dev) ) + { + struct pci_dev *pdev =3D dev_to_pci(dev); + + /* Ignore calls for phantom functions */ + if ( devfn !=3D pdev->devfn ) + return 0; + + d =3D pdev->domain; + } + else + { + if ( !dt_device_is_protected(dev_to_dt(dev)) ) + { + dev_err(dev, "Not added to SMMUv3\n"); + return -ENODEV; + } + + dt_device_set_protected(dev_to_dt(dev), false); + if ( master->domain && master->domain->d ) + d =3D master->domain->d; + } + + if ( d ) + { + int ret =3D arm_smmu_deassign_dev(d, devfn, dev); + /* This should never fail because we already checked the domain */ + ASSERT(!ret); + } + + arm_smmu_disable_pasid(master); + + dev_info(dev, "Removed master device (SMMUv3 %s StreamIds %u)\n", + dev_name(fwspec->iommu_dev), fwspec->num_ids); + + xfree(master); + dev_iommu_priv_set(dev, NULL); + + /* + * For DT devices the fwspec is freed by iommu subsystem, but for PCI + * devices we need to free it here + */ + if ( IS_ENABLED(CONFIG_HAS_PCI) && dev_is_pci(dev) ) + iommu_fwspec_free(dev); + + return 0; +} + static int arm_smmu_add_device(u8 devfn, struct device *dev) { int i, ret; @@ -1571,7 +1633,7 @@ static int arm_smmu_add_device(u8 devfn, struct devic= e *dev) } =20 /* Let Xen know that the master device is protected by an IOMMU. */ - dt_device_set_protected(dev_to_dt(dev)); + dt_device_set_protected(dev_to_dt(dev), true); } =20 dev_info(dev, "Added master device (SMMUv3 %s StreamIds %u)\n", @@ -2867,6 +2929,7 @@ static const struct iommu_ops arm_smmu_iommu_ops =3D = { .unmap_page =3D arm_iommu_unmap_page, .dt_xlate =3D arm_smmu_dt_xlate, .add_device =3D arm_smmu_add_device, + .remove_device =3D arm_smmu_remove_device, }; =20 static __init int arm_smmu_dt_init(struct dt_device_node *dev, diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/a= rm/smmu.c index d63c901551..4d2f71f152 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -825,7 +825,7 @@ static int arm_smmu_dt_add_device_legacy(struct arm_smm= u_device *smmu, if ( !dev_is_pci(dev) ) { /* Xen: Let Xen know that the device is protected by an SMMU */ - dt_device_set_protected(dev_node); + dt_device_set_protected(dev_node, true); } =20 for (i =3D 0; i < fwspec->num_ids; ++i) { @@ -862,7 +862,7 @@ static int arm_smmu_dt_remove_device_legacy(struct arm_= smmu_device *smmu, =20 if ( !dev_is_pci(dev) ) /* Protected by dt_host_lock and dtdevs_lock as caller holds these locks= . */ - dev_node->is_protected =3D false; + dt_device_set_protected(dev_node, false); =20 kfree(master); return 0; diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 06d7643622..76ae1e674a 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -300,9 +300,10 @@ static inline domid_t dt_device_used_by(const struct d= t_device_node *device) return device->used_by; } =20 -static inline void dt_device_set_protected(struct dt_device_node *device) +static inline void dt_device_set_protected(struct dt_device_node *device, + bool protected) { - device->is_protected =3D true; + device->is_protected =3D protected; } =20 static inline bool dt_device_is_protected(const struct dt_device_node *dev= ice) --=20 2.51.2 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 10:02:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 10:02:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290199.1569862 (Exim 4.92) (envelope-from ) id 1wFUPJ-0003U3-LX; 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Update the internal copy_guest() len argument to >> unsigned long accordingly. >> >> Change the type for local variable size in copy_guest() to avoid >> compilation error because of type mismatch. >> >> raw_* wrappers above copy_guest() keep returning unsigned long to >> avoid type narrowing; it is not an issue for raw_*'s len argument >> to remain 'unsigned int' since the assignment to copy_guest()'s wider >> unsigned long parameter is safe and there is no raw_* users who >> are using a value bigger than what can fit into 'unsigned int'. >> >> Reported-by: Jan Beulich >> Signed-off-by: Oleksii Kurochko > > Actually: You say "fix" in the subject. How about sorting out a correct > Fixes: tag then? I will add then before Reported-by: Fixes: 2986481b3d9e6 ("xen/arm: guest_copy: Extend the prototype to pass the vCPU") Fixes: 5302bd490bea7 ("xen/arm: Introduce copy_to_guest_phys_flush_dcache") Fixes: d07b7369aa65b ("xen/common: dom0less: introduce common domain-build.c") From xen-devel-bounces@lists.xenproject.org Wed Apr 22 10:27:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 10:27:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290228.1569871 (Exim 4.92) (envelope-from ) id 1wFUnx-0007qK-He; Wed, 22 Apr 2026 10:27:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290228.1569871; Wed, 22 Apr 2026 10:27:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFUnx-0007qD-Ev; Wed, 22 Apr 2026 10:27:37 +0000 Received: by outflank-mailman (input) for mailman id 1290228; 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Both changes are just exporting functions from the same file. Thanks, Roger. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <61c33c15d046110b5c99490f54191facf18068e1.1776780944.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1776854237-43D6C3FF-4A741CE9/0/0 X-purgate-type: clean X-purgate-size: 1181 On 22.04.2026 11:44, Oleksii Kurochko wrote: > --- a/xen/common/Kconfig > +++ b/xen/common/Kconfig > @@ -29,6 +29,9 @@ config DOM0LESS_BOOT > config DOMAIN_BUILD_HELPERS > bool > > +config HAS_DOMAIN_TYPE > + bool > + > config GRANT_TABLE > bool "Grant table support" if EXPERT > default y Looks like I need to repeat my v1 comment: "Why here rather than where the bulk of the other HAS_* are?" They are (or at least are suppoosed to be) sorted, so that finding a particular entry (e.g. while checking for name clashes) is easy. > --- a/xen/include/xen/domain.h > +++ b/xen/include/xen/domain.h > @@ -13,6 +13,19 @@ struct guest_area { > void *map; > }; > > +#ifdef CONFIG_HAS_DOMAIN_TYPE > +enum __packed domain_type { > + DOMAIN_32BIT, > + DOMAIN_64BIT, > +}; > +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) > +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) > +#elif !defined(CONFIG_64BIT) > +/* On 32-bit-only platforms all domains are 32-bit. */ Btw, while this may be true in practice right now, it is not given. A 32-bit hypervisor can in principle be capable of running 64-bit guests. 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To: Bernhard Kaindl Cc: "Daniel P. Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , "xen-devel@lists.xenproject.org" , Julien Grall , Stefano Stabellini , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel References: <127e7a4e0bf360d7ffe8be94022840a353a307b2.1776787216.git.bernhard.kaindl@citrix.com> <170028cb-ce5c-4677-88e4-32f57f372fea@suse.com> <52c21d8a-f2ba-42e4-aa63-ddf65d460401@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776854912-4236CA53-BE5D1C75/0/0 X-purgate-type: clean X-purgate-size: 1235 On 22.04.2026 10:46, Bernhard Kaindl wrote: > Jan Beulich wrote at 10:20: >> On 22.04.2026 08:48, Jan Beulich wrote: >> >>> As indicated above, I'm not convinced though that we really want to >>> alter file->size. I'd instead add 1 in the few instances of >>> "efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size))". Sadly the adding of 1 >>> is conditional in read_section(), so maybe a "need_to_increment" >>> boolean wants adding next to the need_to_free one? Then a small helper >>> function may be warranted for those few instances of freeing cfg.addr. >> >> Actually, no separate flag looks to be needed. If for the cfg file we set >> ->need_to_free, we know we allocated the one extra byte. > > No, also cfg->need_to_free is always set when AllocatePages was successful, > xen/common/efi/boot.c, read_file(), lines 862 to 867: > > ret = efi_bs->AllocatePages(AllocateMaxAddress, EfiLoaderData, > PFN_UP(size + (file == &cfg)), &file->addr); > if ( EFI_ERROR(ret) ) > goto fail; > > file->need_to_free = true; Of course. And for the cfg file (and only that) it means there's one more byte allocated. So cfg file buffer freeing can uniformly add 1. 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This also allows to avoid the need to allocate and destroy > rangesets for each device. > > Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform > (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() > macro to free a rangeset and set the pointer to NULL. While this obviously has advantatges when multiple PCI devices are assigned to a single domain (ie: for the hardware domain), it's actually consuming more memory in the domU case if a single device is assigned to the domain, and it has more than one vCPU. I'm not saying it's bad per-se, but it's not obviously such an improvement IMO. With the current approach we know Xen will allocate an amount of rangesets that's bound to the amount of PCI devices (nr_rangesets = nr_pci_devs * NR_BARS), but with this approach the amount of allocated rangesets depends on the number of vCPUs, and hence it's no longer bound by the hardware anymore. I assume that this will change further to support SR-IOV devices that might have even more VF BARs per PF, so I have to look at further patches. > Amends: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") > Signed-off-by: Mykyta Poturai > Signed-off-by: Stewart Hildebrand > --- > v2->v3: > * synced with BAR write with memory decoding enabled series[1] > * add Amends tag > * remove unused variable i due to rebasing over 998060dd9101 ("vPCI: > move vpci_init_capabilities() to a separate file") > * enclose entire struct vpci_vcpu inside #ifdef __XEN__ > * s/bar_mem/mem/ > * use ARRAY_SIZE > * put init/destroy in functions > * only allocate for domains with vPCI and idle domain > * replace 'if ( !mem ) continue;' with ASSERT > > v1->v2 > * new patch > > [1]: https://patchew.org/Xen/20260406191203.97662-1-stewart.hildebrand@amd.com/ > --- > xen/common/domain.c | 5 +++ > xen/drivers/vpci/header.c | 67 ++++++++++++++------------------------ > xen/drivers/vpci/vpci.c | 34 ++++++++++++++++--- > xen/include/xen/rangeset.h | 7 ++++ > xen/include/xen/vpci.h | 10 ++++-- > 5 files changed, 73 insertions(+), 50 deletions(-) > > diff --git a/xen/common/domain.c b/xen/common/domain.c > index bb9e210c28..5ef7db8f09 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -455,6 +455,8 @@ static int vcpu_teardown(struct vcpu *v) > */ > static void vcpu_destroy(struct vcpu *v) > { > + vpci_vcpu_destroy(v); > + > free_vcpu_struct(v); > } > > @@ -512,6 +514,9 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) > if ( arch_vcpu_create(v) != 0 ) > goto fail_sched; > > + if ( vpci_vcpu_init(v) ) > + goto fail_sched; > + > d->vcpu[vcpu_id] = v; > if ( vcpu_id != 0 ) > { > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 5d5ba5c016..5bfb541b6a 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -196,6 +196,7 @@ bool vpci_process_pending(struct vcpu *v) > for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > { > struct vpci_bar *bar = &header->bars[i]; > + struct rangeset *mem = v->vpci.mem[i]; > struct map_data data = { > .d = v->domain, > .map = v->vpci.cmd & PCI_COMMAND_MEMORY, > @@ -203,10 +204,10 @@ bool vpci_process_pending(struct vcpu *v) > }; > int rc; > > - if ( rangeset_is_empty(bar->mem) ) > + if ( rangeset_is_empty(mem) ) > continue; > > - rc = rangeset_consume_ranges(bar->mem, map_range, &data); > + rc = rangeset_consume_ranges(mem, map_range, &data); > > if ( rc == -ERESTART ) > { > @@ -224,8 +225,8 @@ bool vpci_process_pending(struct vcpu *v) > > /* Clean all the rangesets */ > for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > - if ( !rangeset_is_empty(header->bars[i].mem) ) > - rangeset_purge(header->bars[i].mem); > + if ( !rangeset_is_empty(v->vpci.mem[i]) ) > + rangeset_purge(v->vpci.mem[i]); > > v->vpci.pdev = NULL; > > @@ -260,13 +261,14 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, > for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > { > struct vpci_bar *bar = &header->bars[i]; > + struct rangeset *mem = current->vpci.mem[i]; > struct map_data data = { .d = d, .map = true, .bar = bar }; > > - if ( rangeset_is_empty(bar->mem) ) > + if ( rangeset_is_empty(mem) ) > continue; > > - while ( (rc = rangeset_consume_ranges(bar->mem, map_range, > - &data)) == -ERESTART ) > + while ( (rc = rangeset_consume_ranges(mem, map_range, &data)) == > + -ERESTART ) > { > /* > * It's safe to drop and reacquire the lock in this context > @@ -331,13 +333,13 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > { > struct vpci_bar *bar = &header->bars[i]; > + struct rangeset *mem = current->vpci.mem[i]; > unsigned long start = PFN_DOWN(bar->addr); > unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); > unsigned long start_guest = PFN_DOWN(bar->guest_addr); > unsigned long end_guest = PFN_DOWN(bar->guest_addr + bar->size - 1); > > - if ( !bar->mem ) > - continue; > + ASSERT(mem); > > if ( !MAPPABLE_BAR(bar) || > (rom_only ? bar->type != VPCI_BAR_ROM > @@ -354,7 +356,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > continue; > } > > - ASSERT(rangeset_is_empty(bar->mem)); > + ASSERT(rangeset_is_empty(mem)); > > /* > * Make sure that the guest set address has the same page offset > @@ -369,7 +371,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > return -EINVAL; > } > > - rc = rangeset_add_range(bar->mem, start_guest, end_guest); > + rc = rangeset_add_range(mem, start_guest, end_guest); > if ( rc ) > { > printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", > @@ -380,12 +382,12 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > /* Check for overlap with the already setup BAR ranges. */ > for ( j = 0; j < i; j++ ) > { > - struct vpci_bar *prev_bar = &header->bars[j]; > + struct rangeset *prev_mem = current->vpci.mem[j]; > > - if ( rangeset_is_empty(prev_bar->mem) ) > + if ( rangeset_is_empty(prev_mem) ) > continue; > > - rc = rangeset_remove_range(prev_bar->mem, start_guest, end_guest); > + rc = rangeset_remove_range(prev_mem, start_guest, end_guest); > if ( rc ) > { > gprintk(XENLOG_WARNING, > @@ -395,7 +397,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > } > } > > - rc = pci_sanitize_bar_memory(bar->mem); > + rc = pci_sanitize_bar_memory(mem); > if ( rc ) > { > gprintk(XENLOG_WARNING, > @@ -412,14 +414,14 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + > vmsix_table_size(pdev->vpci, i) - 1); > > - for ( j = 0; j < ARRAY_SIZE(header->bars); j++ ) > + for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) You make a non-trivial use of current in vpci_modify_bars(), maybe you should consider introducing a local variable for it: struct *vcpu curr = current; current expands to a call to get_cpu_info(9, which is better to avoid doing repeatedly, specially in the context above which is used as a loop upper bound. > { > - const struct vpci_bar *bar = &header->bars[j]; > + struct rangeset *mem = current->vpci.mem[j]; > > - if ( rangeset_is_empty(bar->mem) ) > + if ( rangeset_is_empty(mem) ) > continue; > > - rc = rangeset_remove_range(bar->mem, start, end); > + rc = rangeset_remove_range(mem, start, end); > if ( rc ) > { > gprintk(XENLOG_WARNING, > @@ -469,8 +471,9 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > for ( j = 0; j < ARRAY_SIZE(header->bars); j++) > { > const struct vpci_bar *bar = &header->bars[j]; > + struct rangeset *mem = current->vpci.mem[j]; > > - if ( !rangeset_overlaps_range(bar->mem, start, end) || > + if ( !rangeset_overlaps_range(mem, start, end) || > /* > * If only the ROM enable bit is toggled check against > * other BARs in the same device for overlaps, but not > @@ -481,7 +484,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > bar->type == VPCI_BAR_ROM) ) > continue; > > - rc = rangeset_remove_range(bar->mem, start, end); > + rc = rangeset_remove_range(mem, start, end); > if ( rc ) > { > gprintk(XENLOG_WARNING, > @@ -734,18 +737,6 @@ static void cf_check rom_write( > } > } > > -static int bar_add_rangeset(const struct pci_dev *pdev, struct vpci_bar *bar, > - unsigned int i) > -{ > - char str[32]; > - > - snprintf(str, sizeof(str), "%pp:BAR%u", &pdev->sbdf, i); > - > - bar->mem = rangeset_new(pdev->domain, str, RANGESETF_no_print); > - > - return !bar->mem ? -ENOMEM : 0; > -} > - > int vpci_init_header(struct pci_dev *pdev) > { > uint16_t cmd; > @@ -856,10 +847,6 @@ int vpci_init_header(struct pci_dev *pdev) > else > bars[i].type = VPCI_BAR_MEM32; > > - rc = bar_add_rangeset(pdev, &bars[i], i); > - if ( rc ) > - goto fail; > - > rc = pci_size_mem_bar(pdev->sbdf, reg, &addr, &size, > (i == num_bars - 1) ? PCI_BAR_LAST : 0); > if ( rc < 0 ) > @@ -913,12 +900,6 @@ int vpci_init_header(struct pci_dev *pdev) > 4, rom); > if ( rc ) > rom->type = VPCI_BAR_EMPTY; > - else > - { > - rc = bar_add_rangeset(pdev, rom, num_bars); > - if ( rc ) > - goto fail; > - } > } > else if ( !is_hwdom ) > { > diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c > index 0ac9ec8b04..d069ca6d9c 100644 > --- a/xen/drivers/vpci/vpci.c > +++ b/xen/drivers/vpci/vpci.c > @@ -24,6 +24,35 @@ > > #ifdef __XEN__ > > +void vpci_vcpu_destroy(struct vcpu *v) > +{ > + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) > + return; > + > + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) > + RANGESET_DESTROY(v->vpci.mem[i]); > +} > + > +int vpci_vcpu_init(struct vcpu *v) > +{ > + unsigned int i; > + > + if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) > + return 0; > + > + for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) > + { > + char str[32]; > + > + snprintf(str, sizeof(str), "%pv:BAR%u", v, i); > + v->vpci.mem[i] = rangeset_new(v->domain, str, RANGESETF_no_print); > + if ( !v->vpci.mem[i] ) > + return -ENOMEM; > + } > + > + return 0; > +} > + > #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT > static int assign_virtual_sbdf(struct pci_dev *pdev) > { > @@ -89,8 +118,6 @@ struct vpci_register *vpci_get_register(const struct vpci *vpci, > > void vpci_deassign_device(struct pci_dev *pdev) > { > - unsigned int i; > - > ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); > > if ( !has_vpci(pdev->domain) || !pdev->vpci ) > @@ -116,9 +143,6 @@ void vpci_deassign_device(struct pci_dev *pdev) > } > spin_unlock(&pdev->vpci->lock); > > - for ( i = 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) > - rangeset_destroy(pdev->vpci->header.bars[i].mem); > - > xfree(pdev->vpci); > pdev->vpci = NULL; > } > diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h > index 817505badf..f01e00ec92 100644 > --- a/xen/include/xen/rangeset.h > +++ b/xen/include/xen/rangeset.h > @@ -40,6 +40,13 @@ struct rangeset *rangeset_new( > void rangeset_destroy( > struct rangeset *r); > > +/* Destroy a rangeset, and zero the pointer to it. */ > +#define RANGESET_DESTROY(r) \ > + ({ \ > + rangeset_destroy(r); \ > + (r) = NULL; \ You want to use a construct similar to what XFREE() does: #define RANGESET_DESTROY(r) do { \ struct rangeset *_r_ = (r); \ (r) = NULL; \ rangeset_destroy(_r_); \ } while ( false ) After the GhostRace vulnerability we NULL the variable before freeing the data associated with it. Thanks, Roger. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Lf38PclPFbhwnndJt4hEU5mvK5/JY5FXa2Aj7XiGrZrCLXhf02QrWxEumYjRyBGKXM5+sAHS8C1f5kLMwz7XMx5rGcR7yhyNZZc4NzymptmWeul2eMlU0As99b6qA6llzodjcPIQ/+Rz4cYW7kFH6i6VkVnTrxYIGQeNNvsXj2n/oqLvA5QG2Ll/Eqk68KPI3Zr8o9ewCj66PfsmV3SoFmFOiaUUh25h92/DNI7E1FmVe7CSmcOrQLVC5T8xuBFltrta5Um58mTQQO/d1jQjTWO0C2gpgx+RLEnyQ8Uq9gXzli37zHzJUwq+6LNJzPMa953twle4isRfSqzdnuHsmNzt8IaOJEMeqq3KnQPw/87Jf9THbDjgYYrjzOn3hAYzKYBrf/G2OLhefKTPqeuIgrG2eYWZpM7J2Whaav/plJC9urjj2xgCgxyEXkww/CfI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:23:01.3741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff57c5a4-383c-4bb5-525a-08dea06183a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6753 X-purgate-ID: tlsNG-c1860d/1776856994-38567DB1-45CDB93E/0/0 X-purgate-type: clean X-purgate-size: 2273 On 22/04/2026 11:33, Oleksii Moisieiev wrote: > In pl011_init_postirq(), two code paths could reach the > interrupt-unmask write to IMSC without a handler being registered: > > - When no valid IRQ number was provided (uart->irq <= 0), the original > positive-condition guard (if uart->irq > 0) skipped the irqaction > setup but still fell through to the IMSC write, unmasking > RTI|OEI|BEI|PEI|FEI|TXI|RXI with no handler installed. > > - When setup_irq() returned an error, only an error message was > printed and execution continued to the IMSC write, arming all > hardware interrupt lines with no handler to service them. On > platforms where the GIC receives these asserted lines, the result > is either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure pl011_init_postirq() to use early returns: return > immediately when no valid IRQ is provided, and return after logging > the error when setup_irq() fails. The interrupt-enable write to IMSC > is only reached when IRQ registration succeeds. > > Signed-off-by: Oleksii Moisieiev > --- > > Changes in v3: > - clear pending error interrupts before setup_irq for pl011 > > xen/drivers/char/pl011.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) > > diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c > index 5f9913367d..9e308f4936 100644 > --- a/xen/drivers/char/pl011.c > +++ b/xen/drivers/char/pl011.c > @@ -150,18 +150,24 @@ static void __init pl011_init_postirq(struct serial_port *port) > struct pl011 *uart = port->uart; > int rc; > > - if ( uart->irq > 0 ) > - { > - uart->irqaction.handler = pl011_interrupt; > - uart->irqaction.name = "pl011"; > - uart->irqaction.dev_id = port; > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); > - } > + /* Don't unmask interrupts if no valid irq was provided */ > + if ( uart->irq <= 0 ) uart->irq is unsigned, so it should be compared to 0. Can be fixed on commit. Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:26:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:26:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290301.1569917 (Exim 4.92) (envelope-from ) id 1wFVjE-0003Hx-J1; Wed, 22 Apr 2026 11:26:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290301.1569917; Wed, 22 Apr 2026 11:26:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVjE-0003Hq-FC; Wed, 22 Apr 2026 11:26:48 +0000 Received: by outflank-mailman (input) for mailman id 1290301; Wed, 22 Apr 2026 11:26:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVjD-0003Hk-7c for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:26:47 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFVjC-00AoP0-Ki for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <9200d75d-1f5a-441c-9e69-a1764eeed81b@amd.com> Date: Wed, 22 Apr 2026 13:26:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/4] xen/drivers/char/cadence-uart: fix IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBA:EE_|PH7PR12MB6977:EE_ X-MS-Office365-Filtering-Correlation-Id: ac9f5c77-7278-4ae2-5fda-08dea06205d6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: ph6PHYBDVbYcZaNyJuXdzqj0SDaSRbnUEnPfqG+D7Dnozt/ZWf172poTasf+gYOZSbOV2QpwbgASEOplIcX9V0fU07MgCSqEDBhHPF3mYPMQUhQBfOjBL6pQFSna95h4CuwYKsekgWNkV2unL7hDH6DXcSMGImePrebS1UTXi5KMlatDKhUxR7uy0fteXIe0FI191MaPQPW8JQZBF97d93DGOKtF5YoOAdywpVNiFk5lh76zZ+efRhNbCTC7VqU5NybT5FVonLy4DN4EIT5U+baHdDbOosikXB+qa4pKers9hJbWvi25iqi0R+COg45Mxkk9UaGiIeOgi4Q9kMVFCdXKnvhxpsTJRoTsmnj4RBj+uwaKtjl5pplsbHJNCbJMmXeYpuLUm5Geg/hEiCM0SQNNNjYenZMNLnwjVBDatfWou+4ETF9pLxIppfuZvPBLQWHsNFbRreb6s+qVw/YFDSOKpAS39SfSK0CuGa8P8eUdXHu/yYZguvxX0ZrH46MHjx9iQzTvcQ3o42Mc0pwgkbq2Vf7wHh0QAhydCHhZve1hxoUBwE3c9Gpwyn9Nsdu4nMYDOqWBEmcaf7CHaXXcl5wtAZ4QxmqK78dQxlQNJzqspO0LiQGuL/HvnOWGmFN8LJlbyTpDU3G4uAxdrYGJDYftBFk/ifRoAE9SzR4ZCWJMqob7vn4gDDfNVViOINbmDzvO0ylDLNQTVhaV8yAEuhB7R2ZjLGX9vneFMMCt9Hknbau+8NCwhlYwR0IDePUh98xvUacS19PDWp0Q2c2ZgA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: z41JlxH8iIhA7kpleMFgCoJPlVnYVWYsNeA8sJsrlbfUkAdaT6RmMCzb1WMwIagR1x4Ea1+DlF36sTqo0+n4lNP0mleWMLDAgoCGkAV2NqpPt7Km/8aYh7mBqhC1LBBQJcSAVsoufUxnz/Mg4R9oKx1JgESHrCPFJoMLo9MaPV4uG+plVIVULhfhGNO2jAzonNI46vDsCxcU8w2PKGMHZtu6JEgJM1dnLB2/6fVthwu80H9cNf25S5AAupP949RuqzS/KLqx+2OuOzggucnZHKkSyveQi28JSbdY/8VYGWUgYfiXQf2czNYcQGLxTZDs8rCnYZjZYAOFZ/xg9Utas+2+RCI0gk72jo7yPGq6zJHjrjCEECChGKXlvTM9HOh7j/UQdiUjO92jKqPNid6Jq8830VyvPNsu3ULIWA4iCQJh8xP1aAmPl51YUEJmRTPC X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:26:39.7930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac9f5c77-7278-4ae2-5fda-08dea06205d6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6977 X-purgate-ID: tlsNG-4011c0/1776857206-CF1728B7-0E295FA9/0/0 X-purgate-type: clean X-purgate-size: 1032 On 22/04/2026 11:33, Oleksii Moisieiev wrote: > In cuart_init_postirq(), two code paths could reach the > interrupt-enable write to IER without a handler being registered: > > - When no valid IRQ number was provided (uart->irq <= 0), the original > positive-condition guard (if uart->irq > 0) skipped the irqaction > setup but still fell through to the IER write, enabling the receive > data interrupt with no handler installed. > > - When setup_irq() returned an error, only an error message was > printed and execution continued to the IER write, arming the > receive hardware interrupt line with no handler to service it. On > platforms where the GIC receives this asserted line, the result is > either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure cuart_init_postirq() to use early returns in both error > paths. > > Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:27:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:27:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290309.1569925 (Exim 4.92) (envelope-from ) id 1wFVje-0003hl-Pt; Wed, 22 Apr 2026 11:27:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290309.1569925; Wed, 22 Apr 2026 11:27:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVje-0003he-Mi; Wed, 22 Apr 2026 11:27:14 +0000 Received: by outflank-mailman (input) for mailman id 1290309; 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Wed, 22 Apr 2026 11:27:06 +0000 Received: from l14 (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: anthony.perard) by mail2.vates.fr (Postfix) with ESMTPSA id 8550E8109B; Wed, 22 Apr 2026 13:27:05 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=8ZWCJ8XJGt/kkm5qvDNUOLmiI7V87axTpQnRjjcZ+cg=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=gPjWNnsecyvqLtewSXYvFuUw4uCwhPYhF/WX9TyNLZFeCzvEDLiQNC7lBVDIrdvLQvIWqr60R QbErDWDppi6g1wFPnJTIqv9kCfE9KF7JrsQipB+IokYiAZD+eYskEh8LOnE32wrj8pOvz/Ud2zn 4yb3m+Jlh5JmNqFpS+znfPZcFX+vSmj3Bt2LNnRbD5KpCTC9CivorNW+adPuluspZqymwkq9L4F xGg1dxe0AVJ4KvaHnQO3gcv0zmbTowfRVhxLo6Cvw7Nt372U6LI4msJ3Vz2vf31l4Ym/5TfKbB6 BFpVH8Esx86cQ+ZO823As8pXIaKSS3UCIZFIDafjg9PQ== X-Zone-Loop: b66acdbdfb35d9c841289f9d34cb577c64089a752c08 x-campaign-type: default x-transaction-id: ee6e6152-d5b6-4c3b-b821-0fb8b826899b x-swg-uid: 01-37bc3583-9b50-43ef-8bde-189d1569f1fe X-Mailer: Sweego Message-ID: <1776857226.8631fc262581453bbf619ec5b2062170.19db4f19bfb000f373@vates.tech> x-swg-bid: 1776857226.8631fc262581453bbf619ec5b2062170.19db4f19bfb000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Wed, 22 Apr 2026 13:27:05 +0200 From: Anthony PERARD To: Roger Pau =?iso-8859-1?Q?Monn=E9?= Cc: Jan Beulich , xen-devel@lists.xenproject.org Subject: Re: [PATCH] tools/xenpm: fix FreeBSD build References: <20260421153224.36368-1-roger.pau@citrix.com> <2204fbae-be5b-4f56-ad2a-cd5692db81cb@suse.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.257d.d1266fe5980cbbd5.19db4f199d2.c29e57fdea891acb=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776857225686 X-purgate-ID: tlsNG-42698a/1776857231-7E573F3B-72E6A5C3/0/0 X-purgate-type: clean X-purgate-size: 2244 ---=Part.257d.d1266fe5980cbbd5.19db4f199d2.c29e57fdea891acb=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Wed, Apr 22, 2026 at 11:16:48AM +0200, Roger Pau Monn=C3=A9 wrote: > On Wed, Apr 22, 2026 at 09:15:56AM +0200, Jan Beulich wrote: > > On 21=2E04=2E2026 17:51, Roger Pau Monn=C3=A9 wrote: > > > On Tue, Apr 21, 2026 at 05:35:57PM +0200, Jan Beulich wrote: > > >> On 21=2E04=2E2026 17:32, Roger Pau Monne wrote: > > >>> --- a/tools/misc/xenpm=2Ec > > >>> +++ b/tools/misc/xenpm=2Ec > > >>> @@ -1377,7 +1377,7 @@ static int fetch_dts_temp(xc_interface *xch,= uint32_t cpu, bool package, int *te > > >>> { > > >>> case 0: > > >>> /* This CPU isn't online or can't query this MSR */ > > >>> - errno =3D ENODATA; > > >>> + errno =3D ENODEV; > > >>> return -1; > > >> > > >> "No such device", however, isn't quite what we want to convey here= =2E If no > > >> better error code can be found that's available on FreeBSD and Linu= x, I'm > > >> inclined to suggest that we stick to ENODATA where available=2E > > >=20 > > > Seems like a lot of complexity, for very limited usefulness=2E > >=20 > > What's complex about > >=20 > > #ifndef ENODATA > > # define ENODATA ENODEV > > #endif > >=20 > > (perhaps with a brief comment)? >=20 > IMO it's best if we can avoid instances of ENODATA in the toolstack > code base, specially if it's individual ones like this that can be > fixed=2E Otherwise new instances might appear elsewhere, and we don't > want to be adding this bodge everywhere if avoidable=2E >=20 > If we had a sizable usage of ENODATA in the code base I would indeed > recommend such define approach=2E Yeah, let's just use ENODEV on every platform in this case=2E We already have ENODATA translated to ENOENT in libxl (for privcmd), so let's not add a different translation here=2E So patch looks fine to me as is: Acked-by: Anthony PERARD As for the error message, patch welcome ;-)=2E Thanks, -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vate= s=2Etech ---=Part.257d.d1266fe5980cbbd5.19db4f199d2.c29e57fdea891acb=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290320.1569934 (Exim 4.92) (envelope-from ) id 1wFVq9-0005vg-Ea; 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pr=C Message-ID: Date: Wed, 22 Apr 2026 13:33:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/4] xen/drivers/char: fix exynos4210 IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|DM4PR12MB6567:EE_ X-MS-Office365-Filtering-Correlation-Id: ce3230aa-e574-4ab3-15e3-08dea063061d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: wN7UL2JSiWaKFIBppSRlKmH5usD/3AECyqBkL2Epk+qOH4VqcznrarrqlnvWri05w2EXCpq341cHXA2j3Ha2HemYiOy3M6QlSaO05+957vUuxEXGI7P8R7trq9J9qwFHxB2DWQ5ZlC3vd1lIkowJ7GBL7MNilyFWJiuS9luYLeCgvBM63JLlt49W+tbFx+VpO7RgLQtzCFapaf2M88yG/HE0cM5c/ffLz+Ot8NZ+t8tVrG1fC+cr64ITQZfUjzDIo3G+2VxMVyJqEM4ju/CEaKbkNPjOypnyA27UPBavIq9rfj1ynXjE2NsX3RhisXGIKTKJn2aB5jtgfJ+zrXY5HlULqmLzMy1OG8tDEoeV+bRRyFFkun6VIrGmWAu54iUrNCWKUidqJClPNkmwk76TR2Kj6UJO168VOnxQ1iCfnq11XN0nETS0kqbzn9/iXPnwICT0LzT8uyvEa8Da7U4T5kXvoqU4kjgKeTl8kbt1WhLYoNoq2lkeB4rbavThf8KzmCHnWBYHmmbCSZnl2rz2qbMRWZ2/S8YJsmfIX9aVtGc5bc0kyaOTVa14WecfJQ+subAbHnT+u3tPCNLS/z6KB6WiL327qH2uZaufdrC7odSVwicLxOnZWuOTIs9oGGCWAn2CU3usEB3KM1cJv+siwLFBMeEK1/mf8JI+R/hkRvtFqpS/X7u4AKAaPOjGpwFuiswEUlf+scitxmaBflb8gE7uaUhH7n6lHKhpfd7G/+mRm0Z2W1vIqSQi1ad6Z8QtbKNo22J18xSIOAgtLlqxhQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gOY9cAUEhhUubEFeArgXUGNPxoEg0YmSKprzybe4ZRA2cCxzNcwVgAKX6kV5MqQYxrOqBXYUwgGgItoTqCgbzkMwYheQFEQUdLL2gNwVFXyHCZoYrktvyPWk72WAkkegsMKSiYdoDyVhz/0fmgmhnfK3OiRc8ch1pc8UTE9tFyqL9eOsclA+3Zi7sQzTSEeNOSpVdrt7oY+jMEIdvXWpaYSHFirEBxYr6vLe//gFi1tWqg4RgkvtCVrAGtd2V1bJUrrz2pR81HwOxsxXduCj62ERyH0DSf0UxI28V9/jSgLEXa5Bpu9Rd3q06nYGgBCK7iQzk8slpkLHFl1X04S4KHcRN7T9yAPBeMXiXi47BDQgO0v/N/VZb9zQBW3FwWcLXjcmicKKRO/fUGTqP+d8gwQcaKa7CZUcaTeVFZJAvX1zy9/goM67gKAYQGg4s5// X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:33:49.7532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ce3230aa-e574-4ab3-15e3-08dea063061d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6567 X-purgate-ID: tlsNG-bad1c0/1776857635-43B78A53-EB5491FD/0/0 X-purgate-type: clean X-purgate-size: 1806 On 22/04/2026 11:33, Oleksii Moisieiev wrote: > In exynos4210_uart_init_postirq(), when setup_irq() returns an error > the failure was only logged via dprintk() and execution continued, > unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled > receive and transmit interrupt lines with no handler registered. On > platforms where the GIC receives these asserted lines, the result is > either repeated spurious-interrupt warnings or an unhandled interrupt > fault. > > Add an early return in the setup_irq() error branch so that the > interrupt-enable writes to UINTM and UMCON are skipped when IRQ > registration fails. > > Signed-off-by: Oleksii Moisieiev > --- > > Changes in v3: > - skip clearing pending interrupts if setup_irq was failed because > according to the 13.4.1.13 of the RM: it must be cleared after > cleaning interrupt pending in INTC. > > xen/drivers/char/exynos4210-uart.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c > index 58901df554..2e5860ea2b 100644 > --- a/xen/drivers/char/exynos4210-uart.c > +++ b/xen/drivers/char/exynos4210-uart.c > @@ -199,8 +199,12 @@ static void __init exynos4210_uart_init_postirq(struct serial_port *port) > uart->irqaction.dev_id = port; > > if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > + { > dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %d\n", > uart->irq); > + /* Don't enable interrupts if irq setup was failed */ NIT: Not sure why this comment differs from one patch to another. Preferably they should all be the same. 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pr=C Message-ID: Date: Wed, 22 Apr 2026 13:36:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] xen/drivers/char: fix SCIF IRQ registration failure propagation To: Oleksii Moisieiev , "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Stefano Stabellini , "Volodymyr Babchuk" References: <519488a3f63d3bb6af9a6fb794b85e9960710b23.1776850201.git.oleksii_moisieiev@epam.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <519488a3f63d3bb6af9a6fb794b85e9960710b23.1776850201.git.oleksii_moisieiev@epam.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|SJ2PR12MB9116:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e47876f-1a7d-4f8c-6c12-08dea063632d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: R3Z6fM0n1XGPDtJbsur+sVkuh9siU2QWDJXYKFOB/zugbRPtVV3u5WQeweXex0aIkNtb75jATxqL/DW3oMCUReCaAw+feZ4F6+xXhV3ObDXh68qQ/IoXRkenvRYpUkwcnTlUQRYEeU0r30LoW3WEk+WaYMtrJqHEUYeXMdneHZB0W+9Xcd23Dyh5Pf9te6K20gUKexrO5CsTbcjmXCLaT8ykeFMW/Ni9wL6R+/g+00VgkELzDEwZgs3qi/q4YuyXrX8xsKICKtEmfXityqBiFsXFpHFvbcZfVv+/6KaKLSUuVXQ6pv6lli0Wb9VgClCIjmmnp6vRGOG2T5er031tyJO/A+4rdnwZImcNUnRJMDZbLdSIWk0cLtyGwTo8lOzEAYB2Ww69+VX6Nsce48iByX8jWjUAPekhOLHmXQoTz3b1Er7h493PMo6k79HkDQ9T X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:36:25.8873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e47876f-1a7d-4f8c-6c12-08dea063632d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9116 X-purgate-ID: tlsNG-33051d/1776857794-A1B7C938-E11713F6/0/0 X-purgate-type: clean X-purgate-size: 3274 On 22/04/2026 11:33, Oleksii Moisieiev wrote: > In scif_uart_init_postirq(), when setup_irq() returns an error the > failure was only logged via dprintk() and execution continued, > unconditionally writing TIE|RIE|REIE into the Serial Control Register > (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, > RX data ready, receive error) with no handler registered to service > them. On platforms where the GIC receives these asserted lines, the > result is either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > The fix adds an early return inside the error branch. The > interrupt-enable write to SCSCR is skipped entirely when no handler is > registered. > > SCIF TX continues to operate correctly after this change. The Xen > serial framework never calls serial_async_transmit() for SCIF, so > port->txbuf is always NULL. This causes __serial_putc() to take the > synchronous finite-capacity path, which polls the SCFSR_TDFE hardware > flag directly and does not depend on the interrupt mechanism. RX > wouldn't work if irq wasn't registered. > > As a secondary clean-up, the hardware error-flag clearing sequence is > moved to before the setup_irq() call so that error bits accumulated > since init_preirq() are cleared unconditionally, regardless of whether > IRQ registration succeeds. > > Signed-off-by: Oleksii Moisieiev > --- > > (no changes since v2) > > Changes in v2: > - Extend fix to pl011, cadence-uart and exynos4210 > - fix typo in patch 1 description > > xen/drivers/char/scif-uart.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c > index 888821a3b8..673a2d3800 100644 > --- a/xen/drivers/char/scif-uart.c > +++ b/xen/drivers/char/scif-uart.c > @@ -187,16 +187,24 @@ static void __init scif_uart_init_postirq(struct serial_port *port) > uart->irqaction.name = "scif_uart"; > uart->irqaction.dev_id = port; > > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", > - uart->irq); > - > /* Clear all errors */ > if ( scif_readw(uart, params->status_reg) & params->error_mask ) > scif_writew(uart, params->status_reg, ~params->error_mask); > if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) > scif_writew(uart, params->overrun_reg, ~params->overrun_mask); > > + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > + { > + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", > + uart->irq); > + /* > + * If the IRQ handler could not be installed (setup_irq failed), > + * do not enable TX/RX or error interrupts. Serial transmit will > + * fall back to polling mode. > + */ As mentioned before, why do these comments differ depending on the patch. I would suggest to just add: /* Don't enable interrupts if irq handler was not set. Fall back to polling */ Other than that: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:36:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:36:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290335.1569952 (Exim 4.92) (envelope-from ) id 1wFVsw-0006lE-58; Wed, 22 Apr 2026 11:36:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290335.1569952; Wed, 22 Apr 2026 11:36:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVsw-0006l4-1x; Wed, 22 Apr 2026 11:36:50 +0000 Received: by outflank-mailman (input) for mailman id 1290335; Wed, 22 Apr 2026 11:36:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVsu-0006kP-Kv for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 04:36:46 -0700 (PDT) MIME-Version: 1.0 References: <1036add9199c6304eb649854024c74dd0f0192cc.1776266307.git.bertrand.marquis@arm.com> In-Reply-To: <1036add9199c6304eb649854024c74dd0f0192cc.1776266307.git.bertrand.marquis@arm.com> From: Jens Wiklander Date: Wed, 22 Apr 2026 13:36:34 +0200 X-Gm-Features: AQROBzAOXCNcY7bb7hC9K-lRPBfgdi3ML2NV-noLI-5or5WRnEjH5_DjKHBVsdk Message-ID: Subject: Re: [PATCH 3/6] xen/arm: ffa: Tighten notification parameter validation To: Bertrand Marquis Cc: xen-devel@lists.xenproject.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1776857807-6DF6ACF5-CAA67ECE/0/0 X-purgate-type: clean X-purgate-size: 6539 Hi Bertand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > The notification handlers still validate overlapping subsets of their > inputs. BIND, UNBIND, and SET each decode caller and destination IDs > locally, GET still accepts a non-zero receiver vCPU ID and reserved flag > bits, and SET still accepts non-zero NS-virtual flags. BIND also treats > unsupported non-zero flag encodings as a supported-feature failure > instead of as malformed input. > > Add ffa_notif_parse_params() and use it to centralize the common > caller/destination and non-zero bitmap checks for BIND, UNBIND, and SET. > Also reject malformed GET and SET requests locally before touching > cached state or forwarding anything to the SPMC. Keep BIND limited to > global notifications and reject unsupported non-zero flag encodings with > INVALID_PARAMETERS. > > - add a shared parameter parser for notification caller/destination > validation > - wire BIND and UNBIND through the shared parser and reject unsupported > bind flag encodings with INVALID_PARAMETERS > - reject non-zero receiver vCPU and reserved flag bits in > FFA_NOTIFICATION_GET > - reject non-zero flags in the NS-virtual FFA_NOTIFICATION_SET path > > Functional impact: malformed notification requests are rejected > consistently earlier in the mediator. > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa_notif.c | 61 +++++++++++++++++++++++++++++------- > 1 file changed, 50 insertions(+), 11 deletions(-) > > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index d15119409a25..491db3b04df5 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -42,21 +42,40 @@ static void inject_notif_pending(struct domain *d) > d); > } > > +static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller_i= d, > + uint16_t dest_id, uint32_t bitmap_= lo, > + uint32_t bitmap_hi) Nit: I would have picked ffa_notif_validate_params() or ffa_notif_check_params(), but that might be more a matter of taste. Anyway, looks good: Reviewed-by: Jens Wiklander Cheers, Jens > +{ > + if ( caller_id !=3D dom_id || dest_id =3D=3D dom_id || !dest_id ) > + return FFA_RET_INVALID_PARAMETERS; > + > + if ( !bitmap_lo && !bitmap_hi ) > + return FFA_RET_INVALID_PARAMETERS; > + > + return FFA_RET_OK; > +} > + > int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) > { > struct domain *d =3D current->domain; > + struct ffa_ctx *ctx =3D d->arch.tee; > + int32_t ret; > uint32_t src_dst =3D get_user_reg(regs, 1); > uint32_t flags =3D get_user_reg(regs, 2); > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); > + uint16_t caller_id =3D src_dst & GENMASK(15, 0); > + uint16_t dest_id =3D src_dst >> 16; > > - if ( (src_dst & GENMASK(15, 0)) !=3D ffa_get_vm_id(d) ) > + if ( flags ) /* Only global notifications are supported */ > return FFA_RET_INVALID_PARAMETERS; > > - if ( flags ) /* Only global notifications are supported */ > - return FFA_RET_DENIED; > + ret =3D ffa_notif_parse_params(ctx->ffa_id, caller_id, dest_id, bitm= ap_lo, > + bitmap_hi); > + if ( ret ) > + return ret; > > - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) > + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, > bitmap_lo, bitmap_hi); > > @@ -66,16 +85,22 @@ int32_t ffa_handle_notification_bind(struct cpu_user_= regs *regs) > int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) > { > struct domain *d =3D current->domain; > + struct ffa_ctx *ctx =3D d->arch.tee; > + int32_t ret; > uint32_t src_dst =3D get_user_reg(regs, 1); > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); > + uint16_t caller_id =3D src_dst & GENMASK(15, 0); > + uint16_t dest_id =3D src_dst >> 16; > > - if ( (src_dst & GENMASK(15, 0)) !=3D ffa_get_vm_id(d) ) > - return FFA_RET_INVALID_PARAMETERS; > + ret =3D ffa_notif_parse_params(ctx->ffa_id, caller_id, dest_id, bitm= ap_lo, > + bitmap_hi); > + if ( ret ) > + return ret; > > - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) > - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bit= map_lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitm= ap_lo, > + bitmap_hi); > > return FFA_RET_NOT_SUPPORTED; > } > @@ -142,6 +167,12 @@ void ffa_handle_notification_get(struct cpu_user_reg= s *regs) > return; > } > > + if ( recv >> 16 || (flags & GENMASK(31, 4)) ) > + { > + ffa_set_regs_error(regs, FFA_RET_INVALID_PARAMETERS); > + return; > + } > + > if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | > FFA_NOTIF_FLAG_BITMAP_SPM )) ) > { > @@ -204,11 +235,19 @@ int32_t ffa_handle_notification_set(struct cpu_user= _regs *regs) > uint32_t flags =3D get_user_reg(regs, 2); > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); > + uint16_t caller_id =3D src_dst >> 16; > + uint16_t dest_id =3D src_dst & GENMASK(15, 0); > + int32_t ret; > + > + ret =3D ffa_notif_parse_params(ffa_get_vm_id(d), caller_id, dest_id, > + bitmap_lo, bitmap_hi); > + if ( ret ) > + return ret; > > - if ( (src_dst >> 16) !=3D ffa_get_vm_id(d) ) > + if ( flags ) > return FFA_RET_INVALID_PARAMETERS; > > - if ( FFA_ID_IS_SECURE(src_dst & GENMASK(15, 0)) && fw_notif_enabled = ) > + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bit= map_lo, > bitmap_hi); > > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:38:45 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:38:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290354.1569961 (Exim 4.92) (envelope-from ) id 1wFVum-0008C8-Ft; Wed, 22 Apr 2026 11:38:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290354.1569961; Wed, 22 Apr 2026 11:38:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFVum-0008C1-D4; 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Store information needed to > map/unmap BARs in struct vpci_map_task. Allow queueing of BAR map/unmap > operations in a list, thus making it possible to perform multiple p2m > operations associated with single PCI device. I would replace "single PCI device" with "single PCI config space register access", it's more specific. > This is preparatory work for further changes that need to perform > multiple unmap/map operations before returning to guest. > > At the moment, only a single operation will be queued. However, when > multiple operations are queued, there is a check in modify_bars() to > skip BARs already in the requested state that will no longer be > accurate. Remove this check in preparation of upcoming changes. > > Signed-off-by: Stewart Hildebrand > Message-ID: <20260406191203.97662-3-stewart.hildebrand@amd.com> I think you also need to add your SoB if you add it to your series. > --- > v2->v3: > * new patch in this series, borrowed from [1] > > [1]: https://patchew.org/Xen/20260406191203.97662-1-stewart.hildebrand@amd.com/20260406191203.97662-3-stewart.hildebrand@amd.com/ > --- > xen/common/domain.c | 5 +- > xen/drivers/vpci/header.c | 227 ++++++++++++++++++++++++++----------- > xen/drivers/vpci/vpci.c | 28 +---- > xen/include/xen/rangeset.h | 7 -- > xen/include/xen/vpci.h | 21 ++-- > 5 files changed, 179 insertions(+), 109 deletions(-) > > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 5ef7db8f09..b1931be987 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -455,8 +455,6 @@ static int vcpu_teardown(struct vcpu *v) > */ > static void vcpu_destroy(struct vcpu *v) > { > - vpci_vcpu_destroy(v); > - > free_vcpu_struct(v); > } > > @@ -514,8 +512,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) > if ( arch_vcpu_create(v) != 0 ) > goto fail_sched; > > - if ( vpci_vcpu_init(v) ) > - goto fail_sched; > + vpci_vcpu_init(v); > > d->vcpu[vcpu_id] = v; > if ( vcpu_id != 0 ) > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 5bfb541b6a..451cdd3a6f 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > > #include > > @@ -35,7 +36,7 @@ > > struct map_data { > struct domain *d; > - const struct vpci_bar *bar; > + const struct vpci_bar_map *bar; > bool map; > }; > > @@ -174,32 +175,20 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, > ASSERT_UNREACHABLE(); > } > > -bool vpci_process_pending(struct vcpu *v) > +static int vpci_process_map_task(const struct pci_dev *pdev, > + struct vpci_map_task *task) > { > - const struct pci_dev *pdev = v->vpci.pdev; > - struct vpci_header *header = NULL; > unsigned int i; > > - if ( !pdev ) > - return false; > - > - read_lock(&v->domain->pci_lock); > - > - if ( !pdev->vpci || (v->domain != pdev->domain) ) > - { > - v->vpci.pdev = NULL; > - read_unlock(&v->domain->pci_lock); > - return false; > - } > + ASSERT(rw_is_locked(&pdev->domain->pci_lock)); > > - header = &pdev->vpci->header; > - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) > { > - struct vpci_bar *bar = &header->bars[i]; > - struct rangeset *mem = v->vpci.mem[i]; > + struct vpci_bar_map *bar = &task->bars[i]; > + struct rangeset *mem = bar->mem; > struct map_data data = { > - .d = v->domain, > - .map = v->vpci.cmd & PCI_COMMAND_MEMORY, > + .d = pdev->domain, > + .map = task->cmd & PCI_COMMAND_MEMORY, > .bar = bar, > }; > int rc; > @@ -210,58 +199,116 @@ bool vpci_process_pending(struct vcpu *v) > rc = rangeset_consume_ranges(mem, map_range, &data); > > if ( rc == -ERESTART ) > - { > - read_unlock(&v->domain->pci_lock); > - return true; > - } > + return rc; > > if ( rc ) > { > spin_lock(&pdev->vpci->lock); > /* Disable memory decoding unconditionally on failure. */ > - modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY, > - false); > + modify_decoding(pdev, task->cmd & ~PCI_COMMAND_MEMORY, false); > spin_unlock(&pdev->vpci->lock); > > - /* Clean all the rangesets */ > - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > - if ( !rangeset_is_empty(v->vpci.mem[i]) ) > - rangeset_purge(v->vpci.mem[i]); > + if ( !is_hardware_domain(pdev->domain) ) > + domain_crash(pdev->domain); > + > + return rc; > + } > + } > + > + spin_lock(&pdev->vpci->lock); > + modify_decoding(pdev, task->cmd, task->rom_only); > + spin_unlock(&pdev->vpci->lock); > + > + return 0; > +} > + > +static void destroy_map_task(struct vpci_map_task *task) > +{ > + unsigned int i; > + > + if ( !task ) > + { > + ASSERT_UNREACHABLE(); > + return; > + } > + > + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) > + rangeset_destroy(task->bars[i].mem); > + > + xvfree(task); > +} > + > +static void clear_map_queue(struct vcpu *v) > +{ > + struct vpci_map_task *task; > + > + while ( (task = list_first_entry_or_null(&v->vpci.task_queue, > + struct vpci_map_task, > + next)) != NULL ) > + { > + list_del(&task->next); > + destroy_map_task(task); > + } > +} > + > +bool vpci_process_pending(struct vcpu *v) > +{ > + const struct pci_dev *pdev = v->vpci.pdev; > + struct vpci_map_task *task; > > - v->vpci.pdev = NULL; > + if ( !pdev ) > + return false; > > + read_lock(&v->domain->pci_lock); > + > + if ( !pdev->vpci || (v->domain != pdev->domain) ) > + { > + clear_map_queue(v); > + v->vpci.pdev = NULL; > + read_unlock(&v->domain->pci_lock); > + return false; > + } > + > + while ( (task = list_first_entry_or_null(&v->vpci.task_queue, > + struct vpci_map_task, > + next)) != NULL ) > + { > + int rc = vpci_process_map_task(pdev, task); > + > + if ( rc == -ERESTART ) > + { > read_unlock(&v->domain->pci_lock); > + return true; > + } > > - if ( !is_hardware_domain(v->domain) ) > - domain_crash(v->domain); > + list_del(&task->next); > + destroy_map_task(task); > > - return false; > + if ( rc ) > + { > + clear_map_queue(v); > + break; > } > } > v->vpci.pdev = NULL; > > - spin_lock(&pdev->vpci->lock); > - modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only); > - spin_unlock(&pdev->vpci->lock); > - > read_unlock(&v->domain->pci_lock); > > return false; > } > > static int __init apply_map(struct domain *d, const struct pci_dev *pdev, > - uint16_t cmd) > + struct vpci_map_task *task) > { > - struct vpci_header *header = &pdev->vpci->header; > int rc = 0; > unsigned int i; > > ASSERT(rw_is_write_locked(&d->pci_lock)); > > - for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) > { > - struct vpci_bar *bar = &header->bars[i]; > - struct rangeset *mem = current->vpci.mem[i]; > + struct vpci_bar_map *bar = &task->bars[i]; > + struct rangeset *mem = bar->mem; > struct map_data data = { .d = d, .map = true, .bar = bar }; > > if ( rangeset_is_empty(mem) ) > @@ -281,15 +328,52 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, > } > } > if ( !rc ) > - modify_decoding(pdev, cmd, false); > + modify_decoding(pdev, task->cmd, false); > > return rc; > } > > -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, > + uint16_t cmd, bool rom_only) > +{ > + struct vpci_map_task *task; > + unsigned int i; > + > + task = xvzalloc(struct vpci_map_task); > + > + if ( !task ) > + return NULL; > + > + for ( i = 0; i < ARRAY_SIZE(task->bars); i++ ) > + { > + if ( !MAPPABLE_BAR(&pdev->vpci->header.bars[i]) ) > + continue; > + > + task->bars[i].mem = rangeset_new(pdev->domain, NULL, > + RANGESETF_no_print); > + > + if ( !task->bars[i].mem ) > + { > + destroy_map_task(task); > + return NULL; > + } > + > + task->bars[i].addr = pdev->vpci->header.bars[i].addr; > + task->bars[i].guest_addr = pdev->vpci->header.bars[i].guest_addr; > + } > + > + task->cmd = cmd; > + task->rom_only = rom_only; > + > + return task; > +} > + > +static void defer_map(const struct pci_dev *pdev, struct vpci_map_task *task) > { > struct vcpu *curr = current; > > + ASSERT(!curr->vpci.pdev || curr->vpci.pdev == pdev); > + > /* > * FIXME: when deferring the {un}map the state of the device should not > * be trusted. For example the enable bit is toggled after the device > @@ -297,8 +381,8 @@ static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > * started for the same device if the domain is not well-behaved. > */ > curr->vpci.pdev = pdev; > - curr->vpci.cmd = cmd; > - curr->vpci.rom_only = rom_only; > + list_add_tail(&task->next, &curr->vpci.task_queue); > + > /* > * Raise a scheduler softirq in order to prevent the guest from resuming > * execution with pending mapping operations, to trigger the invocation > @@ -313,11 +397,17 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > struct pci_dev *tmp; > const struct domain *d; > const struct vpci_msix *msix = pdev->vpci->msix; > + struct vpci_map_task *task; > unsigned int i, j; > int rc; > > ASSERT(rw_is_write_locked(&pdev->domain->pci_lock)); > > + task = alloc_map_task(pdev, cmd, rom_only); > + > + if ( !task ) > + return -ENOMEM; > + > /* > * Create a rangeset per BAR that represents the current device memory > * region and compare it against all the currently active BAR memory > @@ -333,19 +423,18 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > for ( i = 0; i < ARRAY_SIZE(header->bars); i++ ) > { > struct vpci_bar *bar = &header->bars[i]; > - struct rangeset *mem = current->vpci.mem[i]; > + struct rangeset *mem = task->bars[i].mem; > unsigned long start = PFN_DOWN(bar->addr); > unsigned long end = PFN_DOWN(bar->addr + bar->size - 1); > unsigned long start_guest = PFN_DOWN(bar->guest_addr); > unsigned long end_guest = PFN_DOWN(bar->guest_addr + bar->size - 1); > > - ASSERT(mem); > + if ( !mem ) > + continue; > > if ( !MAPPABLE_BAR(bar) || > (rom_only ? bar->type != VPCI_BAR_ROM > - : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) || > - /* Skip BARs already in the requested state. */ > - bar->enabled == !!(cmd & PCI_COMMAND_MEMORY) ) > + : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) ) > continue; > > if ( !pci_check_bar(pdev, _mfn(start), _mfn(end)) ) > @@ -368,7 +457,8 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > gprintk(XENLOG_G_WARNING, > "%pp: can't map BAR%u - offset mismatch: %#lx vs %#lx\n", > &pdev->sbdf, i, bar->guest_addr, bar->addr); > - return -EINVAL; > + rc = -EINVAL; > + goto fail; > } > > rc = rangeset_add_range(mem, start_guest, end_guest); > @@ -376,13 +466,13 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > { > printk(XENLOG_G_WARNING "Failed to add [%lx, %lx]: %d\n", > start_guest, end_guest, rc); > - return rc; > + goto fail; > } > > /* Check for overlap with the already setup BAR ranges. */ > for ( j = 0; j < i; j++ ) > { > - struct rangeset *prev_mem = current->vpci.mem[j]; > + struct rangeset *prev_mem = task->bars[j].mem; > > if ( rangeset_is_empty(prev_mem) ) > continue; > @@ -393,7 +483,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > gprintk(XENLOG_WARNING, > "%pp: failed to remove overlapping range [%lx, %lx]: %d\n", > &pdev->sbdf, start_guest, end_guest, rc); > - return rc; > + goto fail; > } > } > > @@ -403,7 +493,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > gprintk(XENLOG_WARNING, > "%pp: failed to sanitize BAR#%u memory: %d\n", > &pdev->sbdf, i, rc); > - return rc; > + goto fail; > } > } > > @@ -414,9 +504,9 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + > vmsix_table_size(pdev->vpci, i) - 1); > > - for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) > + for ( j = 0; j < ARRAY_SIZE(task->bars); j++ ) > { > - struct rangeset *mem = current->vpci.mem[j]; > + struct rangeset *mem = task->bars[j].mem; > > if ( rangeset_is_empty(mem) ) > continue; > @@ -427,7 +517,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > gprintk(XENLOG_WARNING, > "%pp: failed to remove MSIX table [%lx, %lx]: %d\n", > &pdev->sbdf, start, end, rc); > - return rc; > + goto fail; > } > } > } > @@ -471,7 +561,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > for ( j = 0; j < ARRAY_SIZE(header->bars); j++) > { > const struct vpci_bar *bar = &header->bars[j]; > - struct rangeset *mem = current->vpci.mem[j]; > + struct rangeset *mem = task->bars[j].mem; > > if ( !rangeset_overlaps_range(mem, start, end) || > /* > @@ -490,7 +580,7 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > gprintk(XENLOG_WARNING, > "%pp: failed to remove [%lx, %lx]: %d\n", > &pdev->sbdf, start, end, rc); > - return rc; > + goto fail; > } > } > } > @@ -513,12 +603,19 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > * will always be to establish mappings and process all the BARs. > */ > ASSERT((cmd & PCI_COMMAND_MEMORY) && !rom_only); > - return apply_map(pdev->domain, pdev, cmd); > + rc = apply_map(pdev->domain, pdev, task); > + destroy_map_task(task); > + return rc; > } > > - defer_map(pdev, cmd, rom_only); > + defer_map(pdev, task); > > return 0; > + > + fail: > + destroy_map_task(task); > + > + return rc; > } > > static void cf_check cmd_write( > diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c > index d069ca6d9c..ce9fb5b357 100644 > --- a/xen/drivers/vpci/vpci.c > +++ b/xen/drivers/vpci/vpci.c > @@ -24,33 +24,9 @@ > > #ifdef __XEN__ > > -void vpci_vcpu_destroy(struct vcpu *v) > +void vpci_vcpu_init(struct vcpu *v) > { > - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) > - return; > - > - for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) > - RANGESET_DESTROY(v->vpci.mem[i]); > -} > - > -int vpci_vcpu_init(struct vcpu *v) > -{ > - unsigned int i; > - > - if ( !has_vpci(v->domain) && !is_idle_domain(v->domain) ) > - return 0; > - > - for ( i = 0; i < ARRAY_SIZE(v->vpci.mem); i++ ) > - { > - char str[32]; > - > - snprintf(str, sizeof(str), "%pv:BAR%u", v, i); > - v->vpci.mem[i] = rangeset_new(v->domain, str, RANGESETF_no_print); > - if ( !v->vpci.mem[i] ) > - return -ENOMEM; > - } > - > - return 0; > + INIT_LIST_HEAD(&v->vpci.task_queue); > } > > #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT > diff --git a/xen/include/xen/rangeset.h b/xen/include/xen/rangeset.h > index f01e00ec92..817505badf 100644 > --- a/xen/include/xen/rangeset.h > +++ b/xen/include/xen/rangeset.h > @@ -40,13 +40,6 @@ struct rangeset *rangeset_new( > void rangeset_destroy( > struct rangeset *r); > > -/* Destroy a rangeset, and zero the pointer to it. */ > -#define RANGESET_DESTROY(r) \ > - ({ \ > - rangeset_destroy(r); \ > - (r) = NULL; \ > - }) You introduce this in the previous patch, and removing it in the next patch? Please try to avoid such spurious usage, it's not good to waste effort reviewing newly introduced code that's to be removed by a patch in the same series. Unless very special cases, we usually recommend submitters to attempt to make sure code introduced in a patch series is consistent, so that we don't end up in a situation like this where you are removing a lot of code that was introduced by the previous patch. You likely want to split the changes slightly differently here, maybe the previous patch should introduce the non-functional changes, like the change to use mem instead of bar->mem or similar, and one patch that introduces the usage of the linked-list task queue. > - > /* > * Set a limit on the number of ranges that may exist in set @r. > * NOTE: This must be called while @r is empty. > diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h > index b55bacbe6e..e34f7abe6d 100644 > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -19,8 +19,7 @@ > */ > #define VPCI_MAX_VIRT_DEV (PCI_SLOT(~0) + 1) > > -void vpci_vcpu_destroy(struct vcpu *v); > -int vpci_vcpu_init(struct vcpu *v); > +void vpci_vcpu_init(struct vcpu *v); > > /* Assign vPCI to device by adding handlers. */ > int __must_check vpci_assign_device(struct pci_dev *pdev); > @@ -155,14 +154,23 @@ struct vpci { > }; > > #ifdef __XEN__ > -struct vpci_vcpu { > +struct vpci_map_task { > /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ > - const struct pci_dev *pdev; > - struct rangeset *mem[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; > + struct list_head next; > + struct vpci_bar_map { > + uint64_t addr; > + uint64_t guest_addr; > + struct rangeset *mem; > + } bars[ARRAY_SIZE(((struct vpci_header *)NULL)->bars)]; I'm a bit puzzled (possibly missing something), but why are you keeping this vpci_bar_map array here? AFAICT map tasks are allocated on-demand after this change (by using {alloc,destroy}_map_task()). Thanks, Roger. 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pr=C Message-ID: <6c02e12a-e091-4416-980b-5a7a24ba71d8@amd.com> Date: Wed, 22 Apr 2026 13:42:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] xen/dom0less: introduce next_phandle in struct kernel_info To: Oleksii Kurochko , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , Andrew Cooper , Anthony PERARD , "Jan Beulich" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <4a9d79a9ef2bf25e904c9f49ddef7d5a3f3a4ac2.1776780944.git.oleksii.kurochko@gmail.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <4a9d79a9ef2bf25e904c9f49ddef7d5a3f3a4ac2.1776780944.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|MW6PR12MB8950:EE_ X-MS-Office365-Filtering-Correlation-Id: 447daf32-85ea-4dde-70ff-08dea06447f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|13003099007|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kSBXeR025ufhbY7/pzFham5FQbdaT2vzOnvVIj/9fJ5HU1pHdiWPdeAA4MnW5T0aa2Oaj2YvqisQ1TzYk5vwFWn8aDj592fl6elmjGyHXq/Lw66nPF89HNST5L7ATxS9Nl7OUAPsrPvHMILVUvMw5aD0712A5WcQKFdqdxZ6m5QFfdVSZPL7Hb2Sjztcf0dXR7ip8HcCurDeKxJucZHOL/8rT1HuHTd5kFYOoCvk/V4i5XS8+bFcsdhqT5fTFErVkfhLjbwX8REFJMpXKB0b69Y1aHIR1W2EBl6oTkVMHC+jFsQYoApaAlGobvrBvpMpu17QCRcKBgnas4aLEYh0vLDVhsbdoWN3A70tkmqpH0NnIXvK4RPMw9EEYtBDOn1aS6kLLBuZuCeuniFztnXiiMAqbLkkI/5S5RbhVzNK/qmeB0QqzYtcE6Kd9DO0AUn3 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:42:49.6558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 447daf32-85ea-4dde-70ff-08dea06447f2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8950 X-purgate-ID: tlsNG-d62444/1776858177-B5E6BFF4-2E385CF7/10/73395122804 X-purgate-type: spam X-purgate-size: 6758 On 22/04/2026 11:44, Oleksii Kurochko wrote: > There are cases where it is necessary to know the next available phandle > number in order to generate phandles for guest device nodes. > > When a partial FDT (pfdt) is provided, special care is needed during > initialization of next_phandle, as the pfdt may already contain a dummy > interrupt controller node with a phandle assigned to it. next_phandle > must therefore be initialized to one past the highest phandle already > present in the pfdt, to avoid collisions. > > Since next_phandle may be needed for the very first guest node generated, > domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). > The new call site also aligns better with the existing comment stating > that domain_handle_dtb_boot_module() must be called before the rest of > the device tree is generated. > > Introduce alloc_phandle() to ensure that phandles allocated for guest > nodes do not overlap the Xen-reserved phandle range. This helper will > be used by subsequent patches (by RISC-V at the moment). > > Signed-off-by: Oleksii Kurochko > --- > Here is an example of generated guest DTB: > cpus { > ... > cpu@0 { > ... > interrupt-controller { > compatible = "riscv,cpu-intc"; > #interrupt-cells = <0x1>; > interrupt-controller; > phandle = <0xfdea>; > }; > }; > }; > > /soc/imsics@28000000 { > > interrupts-extended = <0xfdea 0x9 >; > > phandle = <0xfdeb>; > }; > > /soc/aplic@d000000 { > ... > msi-parent = <0xfdeb>; > phandle = <0x1>; > }; > > Note that phandle is generated in this example not by get_next_free_phandle(). > > For non RISC-V people, APLIC is an interrupt controller (something like GIC in > Arm), IMSIC it is interrupt controller which provides MSI and connects to > each CPU. > > [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt > --- > Changes in v2: > - s/free_phandle/next_phandle. > - s/get_next_free_phandle/alloc_phandle. > --- > xen/common/device-tree/dom0less-build.c | 44 ++++++++++++++++++------- > xen/include/xen/fdt-domain-build.h | 6 ++++ > xen/include/xen/fdt-kernel.h | 3 ++ > 3 files changed, 41 insertions(+), 12 deletions(-) > > diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c > index 840d14419da2..ca3ac84a3ef3 100644 > --- a/xen/common/device-tree/dom0less-build.c > +++ b/xen/common/device-tree/dom0less-build.c > @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, > if ( res < 0 ) > goto out; > > + /* > + * Find the highest phandle in the partial FDT so next_phandle starts > + * above it, avoiding collisions with pfdt's own phandle assignments. > + */ > + res = fdt_generate_phandle(pfdt, &kinfo->next_phandle); > + if ( res ) > + { > + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; > + goto out; > + } > + > + if ( kinfo->next_phandle >= GUEST_PHANDLE_GIC ) > + { > + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); > + res = -EOVERFLOW; > + goto out; > + } > + > for ( node_next = fdt_first_subnode(pfdt, 0); > node_next > 0; > node_next = fdt_next_subnode(pfdt, node_next) ) > @@ -459,6 +477,8 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) > BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); > > kinfo->phandle_intc = GUEST_PHANDLE_GIC; > + kinfo->next_phandle = 1; > + BUILD_BUG_ON(GUEST_PHANDLE_GIC == 1); I'm not sure that we need this. It does not seem to be useful. If you want to keep it though, I think you want to compare to next_phandle, not opencoding it's initial value. > > #ifdef CONFIG_GRANT_TABLE > kinfo->gnttab_start = GUEST_GNTTAB_BASE; > @@ -499,6 +519,18 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) > if ( ret ) > goto err; > > + /* > + * domain_handle_dtb_boot_module() must be called before the rest of the > + * device tree is generated because it sets phandle_intc and next_phandle, > + * which subsequent node generation depends on. > + */ > + if ( kinfo->dtb ) > + { > + ret = domain_handle_dtb_boot_module(d, kinfo); > + if ( ret ) > + goto err; > + } > + > ret = make_chosen_node(kinfo); > if ( ret ) > goto err; > @@ -516,18 +548,6 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) > if ( ret ) > goto err; > > - /* > - * domain_handle_dtb_boot_module has to be called before the rest of > - * the device tree is generated because it depends on the value of > - * the field phandle_intc. > - */ > - if ( kinfo->dtb ) > - { > - ret = domain_handle_dtb_boot_module(d, kinfo); > - if ( ret ) > - goto err; > - } > - > ret = make_intc_domU_node(kinfo); > if ( ret ) > goto err; > diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h > index 1d9e77df0eb3..a604f3983fe6 100644 > --- a/xen/include/xen/fdt-domain-build.h > +++ b/xen/include/xen/fdt-domain-build.h > @@ -63,6 +63,12 @@ int find_unallocated_memory(const struct kernel_info *kinfo, > unsigned long e_gfn, > void *data)); > > +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ > +static inline uint32_t alloc_phandle(struct kernel_info *kinfo) > +{ > + return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; > +} > + > #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ > > /* > diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h > index aa977a50f4fc..438adfe3855b 100644 > --- a/xen/include/xen/fdt-kernel.h > +++ b/xen/include/xen/fdt-kernel.h > @@ -44,6 +44,9 @@ struct kernel_info { > /* Interrupt controller phandle */ > uint32_t phandle_intc; > > + /* Next free phandle available for assigning to guest device nodes */ I would mention not to use this value directly but rather obtain from alloc_phandle. This value should only really be used by alloc_phandle. ~Michal > + uint32_t next_phandle; > + > /* loader to use for this kernel */ > void (*load)(struct kernel_info *info); > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:45:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:45:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290377.1569978 (Exim 4.92) (envelope-from ) id 1wFW1E-0001qo-HD; Wed, 22 Apr 2026 11:45:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290377.1569978; Wed, 22 Apr 2026 11:45:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFW1E-0001qh-EB; Wed, 22 Apr 2026 11:45:24 +0000 Received: by outflank-mailman (input) for mailman id 1290377; Wed, 22 Apr 2026 11:45:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFW1D-0001qa-8S for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:45:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFW1C-0072Du-L9 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:45:22 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8b4c8-e002-0a2a0a5209dd-0a2a45018634-36 for ; Wed, 22 Apr 2026 13:45:22 +0200 Received: from [209.85.167.50] (helo=mail-lf1-f50.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8b4d2-c1f2-0a2a45010019-d155a732e9b8-3 for ; Wed, 22 Apr 2026 13:45:22 +0200 Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-5a62f43b76aso490940e87.3 for ; Wed, 22 Apr 2026 04:45:22 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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If so, maybe the patch subject should > then reflect this? At least. for now - yes. I will add Linux kernel to the patch subject. > >> --- /dev/null >> +++ b/xen/arch/riscv/kernel.c >> @@ -0,0 +1,230 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> + >> +#define IMAGE64_MAGIC_V2 0x05435352 /* Magic number 2, le, "RSC\x05" */ >> + >> +static void __init place_modules(struct kernel_info *info, paddr_t kernbase, >> + paddr_t kernend) >> +{ >> + const struct boot_module *mod = info->bd.initrd; >> + const struct membanks *banks = kernel_info_get_mem_const(info); >> + const paddr_t initrd_len = ROUNDUP(mod ? mod->size : 0, >> + KERNEL_LOAD_ADDR_ALIGNMENT); >> + const paddr_t dtb_len = ROUNDUP(fdt_totalsize(info->fdt), >> + KERNEL_LOAD_ADDR_ALIGNMENT); >> + const paddr_t modsize = initrd_len + dtb_len; >> + int bi; > > Please can variables used for array indexing be of unsigned types? The use ... > >> + BUG_ON(modsize < initrd_len); >> + >> + /* >> + * Place modules as high in RAM as possible, scanning banks from >> + * last to first so that the end of the last bank is preferred. >> + */ >> + for ( bi = banks->nr_banks - 1; bi >= 0; bi-- ) > > ... here can easily be replaced: > > for ( bi = banks->nr_banks; bi-- > 0; ) > > Or you could have > > unsigned int bi = banks->nr_banks; > ... > while ( bi-- > 0 ) > > . I will use while() form. > >> + { >> + const struct membank *bank = &banks->bank[bi]; >> + const paddr_t bank_end = bank->start + bank->size; >> + paddr_t modbase; >> + >> + if ( modsize > bank->size ) >> + continue; >> + >> + modbase = ROUNDDOWN(bank_end - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); >> + >> + if ( modbase < bank->start ) >> + continue; >> + >> + /* >> + * If the kernel resides in this bank, ensure modules do not >> + * overlap with it. >> + */ >> + if ( (kernbase >= bank->start) && (kernbase < bank_end) && >> + (modbase < ROUNDUP(kernend, KERNEL_LOAD_ADDR_ALIGNMENT)) && >> + (modbase + modsize > kernbase) ) >> + continue; > > Can't this be had with only two comparisons? Same bank or not doesn't really > matter - if it's different banks, there'll be no overlap anyway. So all you > need here is that the module range doesn't overlap the kernel range, entirely > independent of the bank. > > What is dependent on the bank is that the bank may fit both kernel and module > even if there is an overlap as per your current calculation: You may be able > to place the module below the kernel if it doesn't fit above. I will drop the first check and update the comment: /* * If modules would overlap the kernel, try placing them below it. */ if ( (modbase < ROUNDUP(kernend, KERNEL_LOAD_ADDR_ALIGNMENT)) && (modbase + modsize > kernbase) ) { modbase = ROUNDDOWN(kernbase - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); if ( modbase < bank->start ) continue; } >> +static paddr_t __init kernel_image_place(struct kernel_info *info) >> +{ >> + paddr_t load_addr = INVALID_PADDR; >> + uint64_t image_size = info->image.image_size ?: info->image.len; >> + const struct membanks *banks = kernel_info_get_mem_const(info); >> + unsigned int nr_banks = banks->nr_banks; >> + unsigned int bi; >> + >> + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); >> + >> + /* >> + * At the moment, RISC-V's Linux kernel should be always position >> + * independent based on "Per-MMU execution" of boot.rst: >> + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution >> + * >> + * But just for the case when RISC-V's Linux kernel isn't position >> + * independent it is needed to take load address from >> + * info->image.start. >> + * >> + * If `start` is zero, the Image is position independent. >> + */ >> + if ( likely(!info->image.start) ) >> + { >> + for ( bi = 0; bi != nr_banks; bi++ ) >> + { >> + const struct membank *bank = &banks->bank[bi]; >> + paddr_t bank_start = bank->start; >> + /* >> + * According to boot.rst kernel load address should be properly >> + * aligned: >> + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location >> + * >> + * As Image in this case is PIC we can ignore >> + * info->image.text_offset. >> + */ >> + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); >> + paddr_t bank_end = bank_start + bank->size; >> + paddr_t bank_size; >> + >> + if ( aligned_start > bank_end ) >> + continue; >> + >> + bank_size = bank_end - aligned_start; >> + >> + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); >> + >> + if ( image_size <= bank_size ) >> + { >> + load_addr = aligned_start; >> + break; >> + } >> + } >> + } >> + else >> + { >> + load_addr = info->image.start + info->image.text_offset; > > Why does stuff ahead of text_offset not need loading? Here we just calculating only a place where kernel will be loaded. The full kernel image will be loaded in kernel_image_load(). > >> + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); >> + >> + for ( bi = 0; bi != nr_banks; bi++ ) >> + { >> + const struct membank *bank = &banks->bank[bi]; >> + paddr_t bank_start = bank->start; >> + paddr_t bank_end = bank_start + bank->size; >> + >> + if ( (load_addr >= bank_start) && (load_addr < bank_end) && >> + (bank_end - load_addr) >= image_size ) > > Do we have to fear overflow? (If so, shouldn't such an image be rejected > rather than an attempt being made to place it?) If not, simply: Just for a case. As a user may control load_addr and image_size it could be some combination which will lead to overflow here. > > if ( (load_addr >= bank_start) && > (load_addr + image_size <= bank_end) ) I will add the following: /* * Reject a malformed image before the loop to avoid wrapping * load_addr + image_size in the per-bank check below. * * image_size covers the kernel from _start (placed at load_addr = * start + text_offset) through _end. The alignment gap * [start, load_addr) is padding and need not lie within a bank. */ if ( image_size > (paddr_t)-1 - load_addr ) bi = nr_banks; else for ( bi = 0; bi != nr_banks; bi++ ) { const struct membank *bank = &banks->bank[bi]; paddr_t bank_start = bank->start; paddr_t bank_end = bank_start + bank->size; if ( (load_addr >= bank_start) && (load_addr + image_size <= bank_end) ) break; } > > Also, does image_size really only cover space starting from .text_offset, > rather than from .start? image_size covers total memory the kernel occupies at runtime. > >> +static void __init kernel_image_load(struct kernel_info *info) >> +{ >> + int rc; >> + paddr_t load_addr = kernel_image_place(info); >> + paddr_t paddr = info->image.kernel_addr; >> + paddr_t len = info->image.len; >> + paddr_t effective_size = info->image.image_size ?: len; >> + void *kernel; >> + >> + place_modules(info, load_addr, load_addr + effective_size); >> + >> + printk("Loading Image from %"PRIpaddr" to %"PRIpaddr"-%"PRIpaddr"\n", >> + paddr, load_addr, load_addr + effective_size); > > As on earlier occasions: Please represent ranges as mathematical ones, to > disambiguate whether the bounds (the upper one in particular) are inclusive > or exclusive. I will change to "... [%"PRIpaddr",%"PRIpaddr")\n". > >> +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, >> + paddr_t size) >> +{ >> +#ifdef CONFIG_RISCV_64 >> + return kernel_image64_probe(info, addr, size); >> +#else >> + return -EOPNOTSUPP; > > Better #error, as you have it elsewhere (iirc)? Makes sense use: # error "Only 64-bit RISC-V is supported" Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:47:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:47:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290390.1569989 (Exim 4.92) (envelope-from ) id 1wFW3B-0002Rf-Vs; Wed, 22 Apr 2026 11:47:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290390.1569989; Wed, 22 Apr 2026 11:47:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFW3B-0002RY-Ru; Wed, 22 Apr 2026 11:47:25 +0000 Received: by outflank-mailman (input) for mailman id 1290390; Wed, 22 Apr 2026 11:47:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFW3A-0002RP-DT for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Wed, 22 Apr 2026 13:46:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() To: Oleksii Kurochko , CC: Stefano Stabellini , Julien Grall , Bertrand Marquis , "Volodymyr Babchuk" , Andrew Cooper , Anthony PERARD , "Jan Beulich" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <2617586205ec7b07a302fcb8dd9dd39f3eb2c5ed.1776780944.git.oleksii.kurochko@gmail.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <2617586205ec7b07a302fcb8dd9dd39f3eb2c5ed.1776780944.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A106:EE_|LV0PR12MB999070:EE_ X-MS-Office365-Filtering-Correlation-Id: c5c07f73-50af-4478-aff8-08dea064e800 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4byrWqZdr+vjTnAH95hbjQnJvvS6muMBDSHY0cvj3P1YMNpCw+gAO/noHCY4Nbs/GNderUyCoQmR0OGVEsxoDrkd5g9XMMOLpulNDDsahRIiSc+SlgsNeHbmriot6Oo8l1EBmoSf8/9NdvdxtZtFh6J+6Q7o1mG5A/nP5GuDkZ+jsW+A411kzhUJ/V4FDeNIeEhi8JQEQ6L0z3kj/fQu+y6lvqTmBC9Fg4ENQnh6ThE5gHRayx4pm29087fR0jDH9Nctc1VpklNrzwUV6nJTn+yGACpy2LJC+f+P/uTS/RGVA2TMyqxwNnboi6wyLP9lJ483DKqGWRy+Zy3RlIm4ixS250QjLCf45TwWIKy/FZHOiFhSwSAXEtJaGjbyAbwdK53HUJGrrunILXpYkqmQvyq+8zzOGH3fN7C3wDa95dYelJgzyX3oHg3gHGC8zuZa X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 11:47:18.2273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5c07f73-50af-4478-aff8-08dea064e800 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A106.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV0PR12MB999070 X-purgate-ID: tlsNG-d62444/1776858443-B7C74FF4-341877B3/10/73395122804 X-purgate-type: spam X-purgate-size: 431 On 22/04/2026 11:44, Oleksii Kurochko wrote: > There are two reasons of this change: > 1. Align prototype with what other make_*_node() are passed. > 2. A follow-up RISC-V patch will call get_next_free_phandle() inside > make_cpus_node(), requiring mutable access to kinfo->free_phandle. > > Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:51:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:51:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290399.1570002 (Exim 4.92) (envelope-from ) id 1wFW77-0004dU-Ge; Wed, 22 Apr 2026 11:51:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290399.1570002; Wed, 22 Apr 2026 11:51:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFW77-0004dM-CG; Wed, 22 Apr 2026 11:51:29 +0000 Received: by outflank-mailman (input) for mailman id 1290399; Wed, 22 Apr 2026 11:51:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFW75-0004dG-IR for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:51:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFW74-007LX8-VN for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:51:26 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8b63e-bab6-0a2a0a5309dd-0a2a45019628-0 for ; Wed, 22 Apr 2026 13:51:26 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8b63e-c1f2-0a2a45010019-d1558031e5c5-3 for ; Wed, 22 Apr 2026 13:51:26 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso55412125e9.1 for ; Wed, 22 Apr 2026 04:51:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 22 Apr 2026 04:51:26 -0700 (PDT) Message-ID: Date: Wed, 22 Apr 2026 13:51:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Marek Marczykowski , Daniel Smith , Bernhard Kaindl From: Jan Beulich Subject: [PATCH] EFI: adjust cfg file buffer freeing Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776858686-BF87AFF4-9F281D5D/0/0 X-purgate-type: clean X-purgate-size: 2423 The boot services FreePages() needs passing the size. Since we allocated one more byte to put a trailing nul there, we also need to bump the size passed there. Make a small helper function to centralize this. Note that there's no permanent memory leak because of the oversight: The allocation is done using EfiLoaderData, and all memory of that type is later reclaimed anyway. Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") Reported-by: Bernhard Kaindl Signed-off-by: Jan Beulich --- This is an alternative proposal to https://lists.xen.org/archives/html/xen-devel/2026-04/msg01044.html. --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -778,6 +778,16 @@ static void __init efi_relocate_esrt(EFI */ #include "efi-boot.h" +static void __init free_cfg(void) +{ + if ( !cfg.need_to_free ) + return; + + /* One extra byte was allocated to put a nul character there. */ + efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size + 1)); + cfg.need_to_free = false; +} + void __init noreturn blexit(const CHAR16 *str) { if ( str ) @@ -787,8 +797,7 @@ void __init noreturn blexit(const CHAR16 if ( !efi_bs ) efi_arch_halt(); - if ( cfg.need_to_free ) - efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); + free_cfg(); if ( kernel.need_to_free ) efi_bs->FreePages(kernel.addr, PFN_UP(kernel.size)); if ( ramdisk.need_to_free ) @@ -1557,11 +1566,7 @@ void EFIAPI __init noreturn efi_start(EF name.s = get_value(&cfg, "global", "chain"); if ( !name.s ) break; - if ( cfg.need_to_free ) - { - efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); - cfg.need_to_free = false; - } + free_cfg(); if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) ) { PrintStr(L"Chained configuration file '"); @@ -1631,11 +1636,7 @@ void EFIAPI __init noreturn efi_start(EF efi_arch_cfg_file_late(loaded_image, dir_handle, section.s); - if ( cfg.need_to_free ) - { - efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); - cfg.need_to_free = false; - } + free_cfg(); if ( dir_handle ) dir_handle->Close(dir_handle); From xen-devel-bounces@lists.xenproject.org Wed Apr 22 11:57:53 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 11:57:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290407.1570010 (Exim 4.92) (envelope-from ) id 1wFWDE-0005X5-3c; Wed, 22 Apr 2026 11:57:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290407.1570010; Wed, 22 Apr 2026 11:57:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWDD-0005WG-WF; Wed, 22 Apr 2026 11:57:48 +0000 Received: by outflank-mailman (input) for mailman id 1290407; Wed, 22 Apr 2026 11:57:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWDC-0005Vw-Ns for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 11:57:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFWDB-00Fegp-Q1 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:57:45 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8b7b3-e002-0a2a0a5209dd-0a2a4506e848-16 for ; Wed, 22 Apr 2026 13:57:45 +0200 Received: from [209.85.221.54] (helo=mail-wr1-f54.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8b7b9-7371-0a2a45060019-d155dd36c8e4-3 for ; Wed, 22 Apr 2026 13:57:45 +0200 Received: by mail-wr1-f54.google.com with SMTP id ffacd0b85a97d-43d77f6092eso3683383f8f.2 for ; Wed, 22 Apr 2026 04:57:45 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776859065-51361D75-6307B915/0/0 X-purgate-type: clean X-purgate-size: 5046 On 22.04.2026 13:45, Oleksii Kurochko wrote: > On 4/21/26 10:57 AM, Jan Beulich wrote: >> On 10.04.2026 17:54, Oleksii Kurochko wrote: >>> +static paddr_t __init kernel_image_place(struct kernel_info *info) >>> +{ >>> + paddr_t load_addr = INVALID_PADDR; >>> + uint64_t image_size = info->image.image_size ?: info->image.len; >>> + const struct membanks *banks = kernel_info_get_mem_const(info); >>> + unsigned int nr_banks = banks->nr_banks; >>> + unsigned int bi; >>> + >>> + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); >>> + >>> + /* >>> + * At the moment, RISC-V's Linux kernel should be always position >>> + * independent based on "Per-MMU execution" of boot.rst: >>> + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution >>> + * >>> + * But just for the case when RISC-V's Linux kernel isn't position >>> + * independent it is needed to take load address from >>> + * info->image.start. >>> + * >>> + * If `start` is zero, the Image is position independent. >>> + */ >>> + if ( likely(!info->image.start) ) >>> + { >>> + for ( bi = 0; bi != nr_banks; bi++ ) >>> + { >>> + const struct membank *bank = &banks->bank[bi]; >>> + paddr_t bank_start = bank->start; >>> + /* >>> + * According to boot.rst kernel load address should be properly >>> + * aligned: >>> + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location >>> + * >>> + * As Image in this case is PIC we can ignore >>> + * info->image.text_offset. >>> + */ >>> + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); >>> + paddr_t bank_end = bank_start + bank->size; >>> + paddr_t bank_size; >>> + >>> + if ( aligned_start > bank_end ) >>> + continue; >>> + >>> + bank_size = bank_end - aligned_start; >>> + >>> + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); >>> + >>> + if ( image_size <= bank_size ) >>> + { >>> + load_addr = aligned_start; >>> + break; >>> + } >>> + } >>> + } >>> + else >>> + { >>> + load_addr = info->image.start + info->image.text_offset; >> >> Why does stuff ahead of text_offset not need loading? > > Here we just calculating only a place where kernel will be loaded. The > full kernel image will be loaded in kernel_image_load(). Okay, but if you calculate an address where the full image won't fit, how are things going to work? >>> + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); >>> + >>> + for ( bi = 0; bi != nr_banks; bi++ ) >>> + { >>> + const struct membank *bank = &banks->bank[bi]; >>> + paddr_t bank_start = bank->start; >>> + paddr_t bank_end = bank_start + bank->size; >>> + >>> + if ( (load_addr >= bank_start) && (load_addr < bank_end) && >>> + (bank_end - load_addr) >= image_size ) >> >> Do we have to fear overflow? (If so, shouldn't such an image be rejected >> rather than an attempt being made to place it?) If not, simply: > > Just for a case. As a user may control load_addr and image_size it could > be some combination which will lead to overflow here. > >> >> if ( (load_addr >= bank_start) && >> (load_addr + image_size <= bank_end) ) > > I will add the following: > /* > * Reject a malformed image before the loop to avoid wrapping > * load_addr + image_size in the per-bank check below. > * > * image_size covers the kernel from _start (placed at load_addr = > * start + text_offset) through _end. The alignment gap > * [start, load_addr) is padding and need not lie within a bank. > */ > if ( image_size > (paddr_t)-1 - load_addr ) > bi = nr_banks; > else > for ( bi = 0; bi != nr_banks; bi++ ) > { > const struct membank *bank = &banks->bank[bi]; > paddr_t bank_start = bank->start; > paddr_t bank_end = bank_start + bank->size; > > if ( (load_addr >= bank_start) && > (load_addr + image_size <= bank_end) ) > break; > } Please consider getting away without "else" (and hence with one level less of indentation): bi = image_size <= (paddr_t)-1 - load_addr ? 0 : nr_banks; for ( ; bi != nr_banks; bi++ ) ... >> Also, does image_size really only cover space starting from .text_offset, >> rather than from .start? > > image_size covers total memory the kernel occupies at runtime. Which emphasizes the remark further up. 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Since we allocated > one more byte to put a trailing nul there, we also need to bump the size > passed there. Make a small helper function to centralize this. > > Note that there's no permanent memory leak because of the oversight: The > allocation is done using EfiLoaderData, and all memory of that type is > later reclaimed anyway. This depends on -mapbs at a minimum. > > Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") > Reported-by: Bernhard Kaindl > Signed-off-by: Jan Beulich > --- > This is an alternative proposal to > https://lists.xen.org/archives/html/xen-devel/2026-04/msg01044.html. One thing this patch does not do is fix the boundary passed to efi_arch_flush_dcache_area(). I find it hard to believe that cache maintenance is actually needed, but given it is present in the code currently it needs to stay correct. Or, if it's not needed, it should be dropped in a separate patch. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 22 12:05:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 12:05:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290435.1570029 (Exim 4.92) (envelope-from ) id 1wFWKG-00087c-7x; Wed, 22 Apr 2026 12:05:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290435.1570029; Wed, 22 Apr 2026 12:05:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWKG-00087V-3r; Wed, 22 Apr 2026 12:05:04 +0000 Received: by outflank-mailman (input) for mailman id 1290435; Wed, 22 Apr 2026 12:05:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWKF-00087L-33 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 12:05:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFWKE-00Fgde-Fv for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 14:05:02 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8b96d-e002-0a2a0a5209dd-0a2a4506a970-8 for ; Wed, 22 Apr 2026 14:05:02 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8b96e-7371-0a2a45060019-d1558035a469-3 for ; Wed, 22 Apr 2026 14:05:02 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4891f625344so36969845e9.0 for ; Wed, 22 Apr 2026 05:05:02 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 22 Apr 2026 05:05:01 -0700 (PDT) Message-ID: <5854f2f8-21b6-4462-a9bb-86345a436f6f@suse.com> Date: Wed, 22 Apr 2026 14:04:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] vpci: Use pervcpu ranges for BAR mapping To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , Stewart Hildebrand , Mykyta Poturai References: <51223761a1f2b8f1e901062d1e59dad934300f0e.1775742115.git.mykyta_poturai@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1776859502-52777D75-11245440/0/0 X-purgate-type: clean X-purgate-size: 1021 On 22.04.2026 13:00, Roger Pau Monné wrote: > On Thu, Apr 09, 2026 at 02:01:33PM +0000, Mykyta Poturai wrote: >> @@ -412,14 +414,14 @@ int vpci_modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) >> unsigned long end = PFN_DOWN(vmsix_table_addr(pdev->vpci, i) + >> vmsix_table_size(pdev->vpci, i) - 1); >> >> - for ( j = 0; j < ARRAY_SIZE(header->bars); j++ ) >> + for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) > > You make a non-trivial use of current in vpci_modify_bars(), maybe you > should consider introducing a local variable for it: > > struct *vcpu curr = current; Without any intention to negate this, ... > current expands to a call to get_cpu_info(9, which is better to avoid > doing repeatedly, specially in the context above which is used as a > loop upper bound. ... I'd like to point out that "current" isn't evaluated when used by ARRAY_SIZE() (resolving to two uses of sizeof()). Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 22 12:12:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 12:12:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290445.1570036 (Exim 4.92) (envelope-from ) id 1wFWRh-0001ww-UQ; Wed, 22 Apr 2026 12:12:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290445.1570036; Wed, 22 Apr 2026 12:12:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWRh-0001wp-Rq; Wed, 22 Apr 2026 12:12:45 +0000 Received: by outflank-mailman (input) for mailman id 1290445; Wed, 22 Apr 2026 12:12:44 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWRg-0001wj-AQ for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 12:12:44 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFWRf-000T04-K3 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 14:12:43 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8bb35-e002-0a2a0a5209dd-0a2a450ae5da-26 for ; Wed, 22 Apr 2026 14:12:43 +0200 Received: from [209.85.221.46] (helo=mail-wr1-f46.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8ba87-56b3-0a2a450a0019-d155dd2eac0f-3 for ; Wed, 22 Apr 2026 14:09:43 +0200 Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-43d70b3e159so2711879f8f.0 for ; Wed, 22 Apr 2026 05:09:43 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <77234acb-4539-4efe-9c30-03cb7a389912@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-4011c0/1776859783-CE9768B7-8B7D92DB/13/0 X-purgate-type: clean X-purgate-size: 1419 On 22.04.2026 13:59, Andrew Cooper wrote: > On 22/04/2026 12:51 pm, Jan Beulich wrote: >> The boot services FreePages() needs passing the size. Since we allocated >> one more byte to put a trailing nul there, we also need to bump the size >> passed there. Make a small helper function to centralize this. >> >> Note that there's no permanent memory leak because of the oversight: The >> allocation is done using EfiLoaderData, and all memory of that type is >> later reclaimed anyway. > > This depends on -mapbs at a minimum. But that's affecting only EfiBootServices{Code,Data}, isn't it? >> Fixes: df75f77092c1 ("EFI: avoid OOB config file reads") >> Reported-by: Bernhard Kaindl >> Signed-off-by: Jan Beulich >> --- >> This is an alternative proposal to >> https://lists.xen.org/archives/html/xen-devel/2026-04/msg01044.html. > > One thing this patch does not do is fix the boundary passed to > efi_arch_flush_dcache_area(). Deliberately so, and I commented to this effect in reply to Bernhard's patch. I do think ... > I find it hard to believe that cache maintenance is actually needed, but > given it is present in the code currently it needs to stay correct. > > Or, if it's not needed, it should be dropped in a separate patch. ... this is the way to go, but it'll need input from Arm folks (as requested there). Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 22 12:33:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 12:33:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290464.1570045 (Exim 4.92) (envelope-from ) id 1wFWlT-0005tO-Es; Wed, 22 Apr 2026 12:33:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290464.1570045; Wed, 22 Apr 2026 12:33:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWlT-0005tH-CN; Wed, 22 Apr 2026 12:33:11 +0000 Received: by outflank-mailman (input) for mailman id 1290464; Wed, 22 Apr 2026 12:33:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFWlR-0005t8-Ir for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 12:33:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFWlQ-00B3a9-LA for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 14:33:08 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8bff8-bab6-0a2a0a5309dd-0a2a45039e06-32 for ; Wed, 22 Apr 2026 14:33:08 +0200 Received: from [209.85.128.44] (helo=mail-wm1-f44.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8c004-672d-0a2a45030019-d155802cace9-3 for ; Wed, 22 Apr 2026 14:33:08 +0200 Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-488a14c31eeso42416665e9.0 for ; Wed, 22 Apr 2026 05:33:08 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5d1e06a0fcaee4520bf79d58199e447194f84fe8.1776172526.git.bernhard.kaindl@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-33051d/1776861188-2AD63938-3B0C9AC6/0/0 X-purgate-type: clean X-purgate-size: 2360 On 14.04.2026 15:22, Bernhard Kaindl wrote: > Allow an allocation to proceed when free, unclaimed memory can cover a > claims shortfall. > > In preparation for NUMA-aware claims, refactor this check into a > reusable helper so the same logic can be applied to NUMA nodes. > > Suggested-by: Jan Beulich > Signed-off-by: Bernhard Kaindl > > --- > > Changes since v4: Extracted into a dedicated patch and merged the > formerly separate functions into one, as suggested by Jan Beulich. I did ask for the splitting out, no question. I can't find anything towards the functional change though in my v4 replies, and with that being the main aspect here I think Suggested-by: would credit me for something I didn't do or say. > --- a/xen/common/page_alloc.c > +++ b/xen/common/page_alloc.c > @@ -868,6 +868,42 @@ static void check_and_stop_scrub(struct page_info *head) > } > } > > +/* > + * Allow the request when unclaimed pages suffice, or when a refcounted > + * domain's outstanding claims cover the shortfall. Nit: It's not the domain which is refcounted here (the refcounting there is something entirely different), but the allocation. > + */ > +static bool claims_permit_request(const struct domain *d, > + unsigned long avail_pages, > + unsigned long competing_claims, > + unsigned int memflags, > + unsigned long requested_pages) I think it is good practice to have the main input parameter(s) first. That would be "requested_pages" here plus perhaps "memflags". The rest is auxiliary data to perform the needed calculation. May I further suggest to drop _pages everywhere? I'm further not happy about "competing" in the parameter name: This includes claims for this very domain as well, and if there's no other claim then there's nothing "competing" at all. > +{ > + unsigned long unclaimed_pages; > + > + ASSERT(spin_is_locked(&heap_lock)); > + ASSERT(avail_pages >= competing_claims); > + > + /* Start from the free pages not already claimed by other domains. */ > + unclaimed_pages = avail_pages - competing_claims; This could easily be the initializer of the variable. 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Wed, 22 Apr 2026 05:45:51 -0700 (PDT) MIME-Version: 1.0 References: <5b9ce4a4a3927ce2287ec4db7f864174f53b8f17.1776266307.git.bertrand.marquis@arm.com> In-Reply-To: <5b9ce4a4a3927ce2287ec4db7f864174f53b8f17.1776266307.git.bertrand.marquis@arm.com> From: Jens Wiklander Date: Wed, 22 Apr 2026 14:45:40 +0200 X-Gm-Features: AQROBzCGOIBzjZ3Xfz9x00948t7ArGxeMrG9x-UdM514xcfd3fZvVtFJbdnI6yE Message-ID: Subject: Re: [PATCH 4/6] xen/arm: ffa: Preserve secure notification state when polling SPMC To: Bertrand Marquis Cc: xen-devel@lists.xenproject.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1776861953-51F6BD75-2D8E3FA1/0/0 X-purgate-type: clean X-purgate-size: 7755 Hi Bertrand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > Secure pending state is latched when the SPMC raises the schedule > receiver interrupt, but Xen currently clears that latch too aggressively. > Guest FFA_NOTIFICATION_INFO_GET consumes secure_pending even though it > only reports pending state, and secure FFA_NOTIFICATION_GET only clears > the latch when both SP and SPM bitmaps are requested together. This can > drop a pending indication before the receiver retrieves secure > notifications, or keep INFO_GET reporting stale secure pending state > after a successful GET. > > Keep secure_pending as a latched indication until secure notifications > are actually retrieved. Guest FFA_NOTIFICATION_INFO_GET now reports the > latched state without clearing it, while a successful secure > FFA_NOTIFICATION_GET clears the latch regardless of which secure bitmap > flags were requested. Also protect secure_pending with notif_lock, > serialize SPMC INFO_GET polling behind notif_info_lock, and preserve the > caller-visible INFO_GET success width. > > Functional impact: guest INFO_GET preserves the secure pending > indication until secure notifications are retrieved, and successful > secure GET clears the guest-visible pending latch. > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa_notif.c | 54 +++++++++++++++++++++++------------- > 1 file changed, 35 insertions(+), 19 deletions(-) > > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index 491db3b04df5..fff00ca2baec 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -18,6 +18,7 @@ > > static bool __ro_after_init fw_notif_enabled; > static unsigned int __ro_after_init notif_sri_irq; > +static DEFINE_SPINLOCK(notif_info_lock); > > static void inject_notif_pending(struct domain *d) > { > @@ -109,6 +110,7 @@ void ffa_handle_notification_info_get(struct cpu_user= _regs *regs) > { > struct domain *d =3D current->domain; > struct ffa_ctx *ctx =3D d->arch.tee; > + uint32_t fid =3D get_user_reg(regs, 0); > bool notif_pending; > > if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) > @@ -117,7 +119,10 @@ void ffa_handle_notification_info_get(struct cpu_use= r_regs *regs) > return; > } > > - notif_pending =3D test_and_clear_bool(ctx->notif.secure_pending); > + spin_lock(&ctx->notif.notif_lock); > + notif_pending =3D ctx->notif.secure_pending; > + spin_unlock(&ctx->notif.notif_lock); > + > if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > { > notif_pending |=3D test_and_clear_bool(ctx->notif.vm_pending); > @@ -131,7 +136,9 @@ void ffa_handle_notification_info_get(struct cpu_user= _regs *regs) > if ( notif_pending ) > { > /* A pending global notification for the guest */ > - ffa_set_regs(regs, FFA_SUCCESS_64, 0, > + ffa_set_regs(regs, > + smccc_is_conv_64(fid) ? FFA_SUCCESS_64 : FFA_SUCCES= S_32, > + 0, > 1U << FFA_NOTIF_INFO_GET_ID_COUNT_SHIFT, ffa_get_vm= _id(d), > 0, 0, 0, 0); > } > @@ -154,6 +161,8 @@ void ffa_handle_notification_get(struct cpu_user_regs= *regs) > uint32_t w5 =3D 0; > uint32_t w6 =3D 0; > uint32_t w7 =3D 0; > + uint32_t secure_flags =3D flags & ( FFA_NOTIF_FLAG_BITMAP_SP | > + FFA_NOTIF_FLAG_BITMAP_SPM ); > > if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) > { > @@ -173,27 +182,16 @@ void ffa_handle_notification_get(struct cpu_user_re= gs *regs) > return; > } > > - if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | > - FFA_NOTIF_FLAG_BITMAP_SPM )) ) > + if ( fw_notif_enabled && secure_flags ) > { > struct arm_smccc_1_2_regs arg =3D { > .a0 =3D FFA_NOTIFICATION_GET, > .a1 =3D recv, > - .a2 =3D flags & ( FFA_NOTIF_FLAG_BITMAP_SP | > - FFA_NOTIF_FLAG_BITMAP_SPM ), > + .a2 =3D secure_flags, > }; > struct arm_smccc_1_2_regs resp; > int32_t e; > > - /* > - * Clear secure pending if both FFA_NOTIF_FLAG_BITMAP_SP and > - * FFA_NOTIF_FLAG_BITMAP_SPM are set since secure world can't ha= ve > - * any more pending notifications. > - */ > - if ( ( flags & FFA_NOTIF_FLAG_BITMAP_SP ) && > - ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) ) > - ACCESS_ONCE(ctx->notif.secure_pending) =3D false; > - > arm_smccc_1_2_smc(&arg, &resp); > e =3D ffa_get_ret_code(&resp); > if ( e ) > @@ -210,6 +208,10 @@ void ffa_handle_notification_get(struct cpu_user_reg= s *regs) > > if ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) > w6 =3D resp.a6; > + > + spin_lock(&ctx->notif.notif_lock); > + ctx->notif.secure_pending =3D false; > + spin_unlock(&ctx->notif.notif_lock); > } > > if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > @@ -354,7 +356,10 @@ static void notif_vm_pend_intr(uint16_t vm_id) > * guarantees that the data structure isn't freed while we're access= ing > * it. > */ > - ACCESS_ONCE(ctx->notif.secure_pending) =3D true; > + spin_lock(&ctx->notif.notif_lock); > + ctx->notif.secure_pending =3D true; > + spin_unlock(&ctx->notif.notif_lock); > + > inject_notif_pending(d); > > out_unlock: > @@ -373,11 +378,18 @@ static void notif_sri_action(void *unused) > unsigned int n; > int32_t res; > > - do { > + if ( !fw_notif_enabled ) > + return; Can this ever happen? Am I missing something? Cheers, Jens > + > + spin_lock(¬if_info_lock); > + > + do > + { > arm_smccc_1_2_smc(&arg, &resp); > res =3D ffa_get_ret_code(&resp); > if ( res ) > { > + spin_unlock(¬if_info_lock); > if ( res !=3D FFA_RET_NO_DATA && printk_ratelimit() ) > printk(XENLOG_WARNING > "ffa: notification info get failed: error %d\n", = res); > @@ -391,7 +403,7 @@ static void notif_sri_action(void *unused) > id_pos =3D 0; > for ( n =3D 0; n < list_count; n++ ) > { > - unsigned int count =3D ((ids_count >> 2 * n) & 0x3) + 1; > + unsigned int count =3D ((ids_count >> (2 * n)) & 0x3) + 1; > uint16_t vm_id =3D get_id_from_resp(&resp, id_pos); > > notif_vm_pend_intr(vm_id); > @@ -399,7 +411,9 @@ static void notif_sri_action(void *unused) > id_pos +=3D count; > } > > - } while (resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG); > + } while ( resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG ); > + > + spin_unlock(¬if_info_lock); > } > > static DECLARE_TASKLET(notif_sri_tasklet, notif_sri_action, NULL); > @@ -486,6 +500,7 @@ int ffa_notif_domain_init(struct domain *d) > int32_t res; > > spin_lock_init(&ctx->notif.notif_lock); > + ctx->notif.secure_pending =3D false; > ctx->notif.hyp_pending =3D 0; > > if ( fw_notif_enabled ) > @@ -503,6 +518,7 @@ void ffa_notif_domain_destroy(struct domain *d) > struct ffa_ctx *ctx =3D d->arch.tee; > > spin_lock(&ctx->notif.notif_lock); > + ctx->notif.secure_pending =3D false; > ctx->notif.hyp_pending =3D 0; > spin_unlock(&ctx->notif.notif_lock); > > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 12:48:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 12:48:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290490.1570064 (Exim 4.92) (envelope-from ) id 1wFX0U-0000hl-W5; Wed, 22 Apr 2026 12:48:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290490.1570064; Wed, 22 Apr 2026 12:48:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFX0U-0000he-TD; Wed, 22 Apr 2026 12:48:42 +0000 Received: by outflank-mailman (input) for mailman id 1290490; Wed, 22 Apr 2026 12:48:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFX0T-0000hY-Lv for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 12:48:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFX0T-000aYZ-2h for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 14:48:41 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8c3a6-bab6-0a2a0a5309dd-0a2a4508882a-8 for ; Wed, 22 Apr 2026 14:48:40 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8c3a8-63b5-0a2a45080019-d1558033cc7a-3 for ; Wed, 22 Apr 2026 14:48:40 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-48984d29fe3so45381575e9.0 for ; Wed, 22 Apr 2026 05:48:40 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c1860d/1776862120-C2B74DB1-9FB3C687/0/0 X-purgate-type: clean X-purgate-size: 4882 On 14.04.2026 15:22, Bernhard Kaindl wrote: > Replace d->outstanding_pages with d->global_claims and add > d->node_claims as the aggregate of the domain's node-specific claims. > > Keep the allocator hot path efficient and report the combined claims > state using the two new fields. The truly new field (node_claims) is in fact dead code (as per Misra's definition of the term). It therefore doesn't feel quite right that it is being introduced without (really) being used. > @@ -552,8 +552,7 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) > /* > * Two locks are needed here: > * - d->page_alloc_lock: protects accesses to d->{tot,max,extra}_pages. > - * - heap_lock: protects accesses to d->outstanding_pages, total_avail_pages > - * and outstanding_claims. > + * - heap_lock: Protects accesses to the claims and avail_pages state. > */ > nrspin_lock(&d->page_alloc_lock); > spin_lock(&heap_lock); By removing the use of d-> from the bullet point, you make the result appear to all be only global state. Imo the fields still wants mentioning like it was before. > @@ -561,13 +560,13 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages) > /* pages==0 means "unset" the claim. */ > if ( pages == 0 ) > { > - deduct_global_claims(d, d->outstanding_pages); > + deduct_global_claims(d, d->global_claims); > ret = 0; > goto out; > } > > - /* only one active claim per domain please */ > - if ( d->outstanding_pages ) > + /* Reject updating global claims and we can't update node claims */ > + if ( d->global_claims || d->node_claims ) > { > ret = -EINVAL; > goto out; Is there anything wrong with the original comment (apart from style)? Especially the new "we can't" feels misleading - if we indeed can't, this is something that could be fixed. Isn't more like we may not fiddle with node claims here? Plus mentioning node claims when they aren't a thing yet is somewhat odd, too. Remember: Patches in a series may go if with arbitrarily large gaps in between. > @@ -891,7 +890,7 @@ static bool claims_permit_request(const struct domain *d, > unsigned int memflags, > unsigned long requested_pages) > { > - unsigned long unclaimed_pages; > + unsigned long unclaimed_pages, applicable_claims; > > ASSERT(spin_is_locked(&heap_lock)); > ASSERT(avail_pages >= competing_claims); > @@ -910,11 +909,13 @@ static bool claims_permit_request(const struct domain *d, > if ( !d || (memflags & MEMF_no_refcount) ) > return false; > > + applicable_claims = d->global_claims; > + > /* > * Allow the request to proceed when combination of unclaimed pages and the > * claims held by the domain cover the shortfall for the requested_pages. > */ > - return requested_pages <= unclaimed_pages + d->outstanding_pages; > + return requested_pages <= unclaimed_pages + applicable_claims; > } I don't follow what use these two hunks are here. > @@ -1112,18 +1113,16 @@ static struct page_info *alloc_heap_pages( > total_avail_pages -= request; > ASSERT(total_avail_pages >= 0); > > - if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) ) > + if ( d && d->global_claims && !(memflags & MEMF_no_refcount) ) > { > /* > * Adjust claims in the same locked region where total_avail_pages is > * adjusted, not doing so would lead to a window where the amount of > * free memory (avail - claimed) would be incorrect. > * > - * Note that by adjusting the claimed amount here it's possible for > - * pages to fail to be assigned to the claiming domain while already > - * having been subtracted from d->outstanding_pages. Such claimed > - * amount is then lost, as the pages that fail to be assigned to the > - * domain are freed without replenishing the claim. This is fine given > + * Note, after redeeming claims for the allocation here, assign_pages() > + * could fail. The domain looses The redeemed claims as the not assigned Nit: ... loses the ... > + * pages are freed without replenishing the claim. This is fine given > * claims are only to be used during physmap population as part of > * domain build, and any failure in assign_pages() there will result in > * the domain being destroyed before creation is finished. Losing part I'm not convinced this comment needs fiddling with. There's nothing obviously wrong, and I don't see an obvious improvement from the changes. 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Wed, 22 Apr 2026 05:52:44 -0700 (PDT) Message-ID: Date: Wed, 22 Apr 2026 14:52:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Teddy Astie From: Jan Beulich Subject: [PATCH] x86/HVM: drop dead code from HVM_PARAM_IDENT_PT setting Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776862365-CDF6BD75-E5E30AD8/0/0 X-purgate-type: clean X-purgate-size: 666 The setting of d->arch.hvm.params[] will uniformly happen at the bottom of hvm_set_param(), hence as per Misra's classification redundantly doing so earlier is "dead code". Signed-off-by: Jan Beulich --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -4242,10 +4242,7 @@ static int hvm_set_param(struct domain * * capabilities. Short circuit the pause if possible. */ if ( paging_mode_shadow(d) || !using_vmx() ) - { - d->arch.hvm.params[index] = value; break; - } /* * Update GUEST_CR3 in each VMCS to point at identity map. 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1776864132-45F698B7-B7A7B868/0/0 X-purgate-type: clean X-purgate-size: 8132 Hi Bertrand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > VM-to-VM notifications need receiver-side bind state so Xen can validate > which sender owns each notification bit. Non-secure BIND and UNBIND > requests currently have no local state and cannot enforce that contract. > > Add per-bit VM notification binding state to struct ffa_ctx_notif and > use it to handle non-secure BIND and UNBIND requests when > CONFIG_FFA_VM_TO_VM is enabled. The update helper validates the whole > request under notif_lock before mutating anything, denies bind or > unbind when a bit is pending, rejects rebinding to a different sender, > and keeps rebinding to the same sender idempotent. > > Promote vm_pending to a bitmap so the bind logic can reason per > notification ID, use that bitmap directly when reporting pending state, > and initialize and clear the new VM notification state during domain > init and teardown. > > Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, Xen tracks VM > notification bindings locally and validates non-secure bind and unbind > requests against that state. > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa_notif.c | 97 ++++++++++++++++++++++++++++++---- > xen/arch/arm/tee/ffa_private.h | 15 ++++-- > 2 files changed, 99 insertions(+), 13 deletions(-) > > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index fff00ca2baec..4def701f0130 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -56,6 +56,54 @@ static int32_t ffa_notif_parse_params(uint16_t dom_id,= uint16_t caller_id, > return FFA_RET_OK; > } > > +static int32_t ffa_notif_update_vm_binding(struct ffa_ctx *ctx, > + uint16_t dest_id, uint64_t bi= tmap, > + bool bind) > +{ > + unsigned int id; > + int32_t ret =3D FFA_RET_OK; > + > + spin_lock(&ctx->notif.notif_lock); > + > + for ( id =3D 0; id < FFA_NUM_VM_NOTIF; id++ ) > + { > + if ( !(bitmap & BIT(id, ULL)) ) > + continue; > + > + if ( ctx->notif.vm_pending & BIT(id, ULL) ) > + { > + ret =3D FFA_RET_DENIED; > + goto out_unlock; > + } > + > + if ( bind ) > + { > + if ( ctx->notif.vm_bind[id] !=3D 0 && > + ctx->notif.vm_bind[id] !=3D dest_id ) > + { > + ret =3D FFA_RET_DENIED; > + goto out_unlock; > + } > + } > + else if ( ctx->notif.vm_bind[id] !=3D dest_id ) > + { > + ret =3D FFA_RET_DENIED; > + goto out_unlock; > + } > + } > + > + for ( id =3D 0; id < FFA_NUM_VM_NOTIF; id++ ) > + { > + if ( bitmap & BIT(id, ULL) ) > + ctx->notif.vm_bind[id] =3D bind ? dest_id : 0; > + } > + > +out_unlock: > + spin_unlock(&ctx->notif.notif_lock); > + > + return ret; > +} > + > int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) > { > struct domain *d =3D current->domain; > @@ -76,11 +124,21 @@ int32_t ffa_handle_notification_bind(struct cpu_user= _regs *regs) > if ( ret ) > return ret; > > - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > - return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, > - bitmap_lo, bitmap_hi); > + if ( FFA_ID_IS_SECURE(dest_id) ) > + { > + if ( fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags= , > + bitmap_lo, bitmap_hi); > > - return FFA_RET_NOT_SUPPORTED; > + return FFA_RET_NOT_SUPPORTED; > + } > + > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + return FFA_RET_NOT_SUPPORTED; > + > + return ffa_notif_update_vm_binding(ctx, dest_id, > + ((uint64_t)bitmap_hi << 32) | bit= map_lo, > + true); > } > > int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) > @@ -99,11 +157,21 @@ int32_t ffa_handle_notification_unbind(struct cpu_us= er_regs *regs) > if ( ret ) > return ret; > > - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitm= ap_lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(dest_id) ) > + { > + if ( fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, > + bitmap_lo, bitmap_hi); > > - return FFA_RET_NOT_SUPPORTED; > + return FFA_RET_NOT_SUPPORTED; > + } > + > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + return FFA_RET_NOT_SUPPORTED; > + > + return ffa_notif_update_vm_binding(ctx, dest_id, > + ((uint64_t)bitmap_hi << 32) | bit= map_lo, > + false); > } > > void ffa_handle_notification_info_get(struct cpu_user_regs *regs) > @@ -125,9 +193,10 @@ void ffa_handle_notification_info_get(struct cpu_use= r_regs *regs) > > if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > { > - notif_pending |=3D test_and_clear_bool(ctx->notif.vm_pending); > - > spin_lock(&ctx->notif.notif_lock); > + if ( ctx->notif.vm_pending ) > + notif_pending =3D true; > + > if ( ctx->notif.hyp_pending ) > notif_pending =3D true; > spin_unlock(&ctx->notif.notif_lock); > @@ -497,10 +566,14 @@ void ffa_notif_init(void) > int ffa_notif_domain_init(struct domain *d) > { > struct ffa_ctx *ctx =3D d->arch.tee; > + unsigned int i; > int32_t res; > > spin_lock_init(&ctx->notif.notif_lock); > ctx->notif.secure_pending =3D false; > + ctx->notif.vm_pending =3D 0; > + for ( i =3D 0; i < FFA_NUM_VM_NOTIF; i++ ) > + ctx->notif.vm_bind[i] =3D 0; > ctx->notif.hyp_pending =3D 0; > > if ( fw_notif_enabled ) > @@ -516,9 +589,13 @@ int ffa_notif_domain_init(struct domain *d) > void ffa_notif_domain_destroy(struct domain *d) > { > struct ffa_ctx *ctx =3D d->arch.tee; > + unsigned int i; > > spin_lock(&ctx->notif.notif_lock); > ctx->notif.secure_pending =3D false; > + ctx->notif.vm_pending =3D 0; > + for ( i =3D 0; i < FFA_NUM_VM_NOTIF; i++ ) > + ctx->notif.vm_bind[i] =3D 0; Why not memset(ctx->notif.vm_bind, 0, sizeof(ctx->notif.vm_bind)? > ctx->notif.hyp_pending =3D 0; > spin_unlock(&ctx->notif.notif_lock); > > diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat= e.h > index 5693772481ed..6d83afb3d00a 100644 > --- a/xen/arch/arm/tee/ffa_private.h > +++ b/xen/arch/arm/tee/ffa_private.h > @@ -236,6 +236,11 @@ > #define FFA_NOTIF_INFO_GET_ID_COUNT_MASK 0x1F > > #define FFA_NOTIF_RX_BUFFER_FULL BIT(0, U) > +#define FFA_NUM_VM_NOTIF 64U > + > +#if FFA_NUM_VM_NOTIF > 64 > +#error "FFA_NUM_VM_NOTIF must be <=3D 64" > +#endif BUILD_BUG_ON(FFA_NUM_VM_NOTIF > 64) ? Cheers, Jens > > /* Feature IDs used with FFA_FEATURES */ > #define FFA_FEATURE_NOTIF_PEND_INTR 0x1U > @@ -334,10 +339,14 @@ struct ffa_ctx_notif { > bool secure_pending; > > /* > - * True if domain is reported by FFA_NOTIFICATION_INFO_GET to have > - * pending notifications from VMs (including framework ones). > + * Bitmap of pending notifications from VMs (including framework one= s). > + */ > + uint64_t vm_pending; > + > + /* > + * Source endpoint bound to each VM notification ID (0 means unbound= ). > */ > - bool vm_pending; > + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; > > /* > * Lock protecting the hypervisor-managed notification state. > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 13:23:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 13:23:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290538.1570099 (Exim 4.92) (envelope-from ) id 1wFXXq-0008WV-8y; Wed, 22 Apr 2026 13:23:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290538.1570099; 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Wed, 22 Apr 2026 06:23:47 -0700 (PDT) Message-ID: Date: Wed, 22 Apr 2026 16:23:45 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 2/2] plat/rcar: Add region id support for PCI To: Mykyta Poturai , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: Content-Language: en-US From: Oleksandr Tyshchenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1776864228-BFE7BFF4-D12484CF/0/0 X-purgate-type: clean X-purgate-size: 5774 On 4/21/26 10:57, Mykyta Poturai wrote: Hello Mykyta > With Region ID enabled, all CPU memory accesses need to have rgid bits > set in the physical address. This creates a problem for PCI BAR > accesses, as it would require all BARs to be 64bit. Implement fixup_bar > callback to add rgid bits to the address before mapping it to the > guests. For context. When Region ID support is enabled, the RGID value is encoded in the upper bits of physical addresses for both RAM and device MMIO in host device tree. From Xen's perspective, these are just regular physical addresses, and ideally Xen should not need to be RGID-aware at all. But I understand what this series is trying to solve. It is worth mentioning that when Region ID support is enabled, there will be no 32-bit addresses in the host device tree anymore, since encoding the RGID effectively moves every address beyond the 4GB boundary (unless the RGID is 0). This might break any code in Xen that relies on 32-bit address space for some reason, e.g. HOST_ITS_WORKAROUND_32BIT_ADDR which requires 32-bit addresses for in-memory data structures (refer gicv3_its_enable_quirk_gen4()). > > Add Kconfig options to enable region id support and set the rgid value > and physical address space size. > > Signed-off-by: Mykyta Poturai > --- > xen/arch/arm/pci/pci-host-rcar4.c | 15 +++++++++++++++ > xen/arch/arm/platforms/Kconfig | 21 +++++++++++++++++++++ > 2 files changed, 36 insertions(+) > > diff --git a/xen/arch/arm/pci/pci-host-rcar4.c b/xen/arch/arm/pci/pci-host-rcar4.c > index e1e8eb0ee1..50400c04c4 100644 > --- a/xen/arch/arm/pci/pci-host-rcar4.c > +++ b/xen/arch/arm/pci/pci-host-rcar4.c > @@ -43,6 +43,12 @@ struct rcar4_pcie_priv { > DECLARE_BITMAP(osid_regs, NUM_OSID_REGS); > }; > > +#define ULL(X) _AC(X, ULL) > +#define MADDR_RGID(a) (ULL(a) << CONFIG_RCAR_PA_BITS) > +#define MADDR_PA_MASK ((1ULL << CONFIG_RCAR_PA_BITS) - 1) NIT: MADDR_PA_MASK is defined but never used ... > + > +#define MADDR_ENCODE_RGID(a) (MADDR_RGID(CONFIG_RCAR_RGID) | (a)) > + > /* > * PCI host bridges often have different ways to access the root and child > * bus config spaces: > @@ -61,6 +67,14 @@ static int __init rcar4_child_cfg_reg_index(struct dt_device_node *np) > return dt_property_match_string(np, "reg-names", "config"); > } > > +static void rcar4_pcie_fixup_bar(struct pci_host_bridge *bridge, > + unsigned int bar_num, > + paddr_t *addr) > +{ > + if ( IS_ENABLED(CONFIG_RCAR_REGION_ID_SUPPORT) ) > + *addr = MADDR_ENCODE_RGID(*addr); > +} > + > /* ECAM ops */ > static const struct pci_ecam_ops rcar4_pcie_ops = { > .bus_shift = 20, > @@ -71,6 +85,7 @@ static const struct pci_ecam_ops rcar4_pcie_ops = { > .write = pci_generic_config_write, > .need_p2m_hwdom_mapping = pci_ecam_need_p2m_hwdom_mapping, > .init_bus_range = pci_generic_init_bus_range, > + .fixup_bar = rcar4_pcie_fixup_bar, > } > }; > > diff --git a/xen/arch/arm/platforms/Kconfig b/xen/arch/arm/platforms/Kconfig > index 888d0b85d5..db096952c8 100644 > --- a/xen/arch/arm/platforms/Kconfig > +++ b/xen/arch/arm/platforms/Kconfig > @@ -64,6 +64,27 @@ config NO_PLAT > > endchoice > > +menu "RCar Region ID Support" > + visible if RCAR4 > + > +config RCAR_REGION_ID_SUPPORT > + bool "Renesas Region ID support for R-Car Gen4 platforms" if EXPERT > + depends on RCAR4 > + help > + Enable experimental Region ID support for R-Car Gen4 platforms > + > +config RCAR_RGID > + int "Region ID encoded in physical address" > + depends on RCAR_REGION_ID_SUPPORT > + default 0 > + > +config RCAR_PA_BITS > + int "Physical address space size" > + depends on RCAR_REGION_ID_SUPPORT > + default 36 Options RCAR_RGID and RCAR_PA_BITS lack range constraints. A misconfigured options might cause undefined shift behavior at compile time. However, I see a valid request in a separate email to consider using a firmware table to pass these values, so just ignore this comment. ***** I was wondering whether the RGID could be extracted at runtime from an address that already carries it. Do addresses in the host device tree (e.g., device MMIO ranges, host bridge windows, etc) already contain RGID bits? If so, then in rcar4_pcie_fixup_bar() you could obtain the RGID from the bridge instance that is already passed as a parameter. Something like below: #define MADDR_GET_RGID(addr) ((addr) >> CONFIG_RCAR_PA_BITS) paddr_t rgid = MADDR_GET_RGID(bridge->some_hw_addr_as_it_is_specified_in_dt); *addr = (rgid << CONFIG_RCAR_PA_BITS) | (*addr & MADDR_PA_MASK); This would eliminate CONFIG_RCAR_RGID entirely by deducing it from existing platform data rather than requiring it to be passed explicitly via the device tree. As for CONFIG_RCAR_PA_BITS, I think it could remain as-is since it is constant across an SoC generation, unless I am mistaken. As far as I am aware, on Gen4 the RGID occupies 4 bits (0–15) starting at bit 36, and on Gen5 it occupies 5 bits (0–31) starting at bit 43. Since Xen can identify the hardware it is running on (thanks to the compatible string), the appropriate #define-s could be applied. Would the above approach work, or is it better to pass all these values explicitly? Please note, I am not 100% sure whether this is the right and reliable approach, but it should be considered. > + > +endmenu > + > config ALL64_PLAT > bool > default (ALL_PLAT && ARM_64) From xen-devel-bounces@lists.xenproject.org Wed Apr 22 13:30:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 13:30:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290565.1570126 (Exim 4.92) (envelope-from ) id 1wFXeU-0002Zp-Fe; Wed, 22 Apr 2026 13:30:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290565.1570126; Wed, 22 Apr 2026 13:30:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFXeU-0002ZE-Cd; Wed, 22 Apr 2026 13:30:02 +0000 Received: by outflank-mailman (input) for mailman id 1290565; Wed, 22 Apr 2026 13:30:01 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFXeS-0002P1-UD for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:30:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFXeS-00BEmx-An for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 15:30:00 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8cd43-2eae-0a2a0a5409dd-0a2a4509e23a-32 for ; Wed, 22 Apr 2026 15:30:00 +0200 Received: from [209.85.208.178] (helo=mail-lj1-f178.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8cd57-2497-0a2a45090019-d155d0b2a8ef-3 for ; Wed, 22 Apr 2026 15:30:00 +0200 Received: by mail-lj1-f178.google.com with SMTP id 38308e7fff4ca-38dd9f0fdc6so67959481fa.0 for ; Wed, 22 Apr 2026 06:30:00 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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This helper will >> be used by subsequent patches (by RISC-V at the moment). >> >> Signed-off-by: Oleksii Kurochko >> --- >> Here is an example of generated guest DTB: >> cpus { >> ... >> cpu@0 { >> ... >> interrupt-controller { >> compatible = "riscv,cpu-intc"; >> #interrupt-cells = <0x1>; >> interrupt-controller; >> phandle = <0xfdea>; >> }; >> }; >> }; >> >> /soc/imsics@28000000 { >> >> interrupts-extended = <0xfdea 0x9 >; >> >> phandle = <0xfdeb>; >> }; >> >> /soc/aplic@d000000 { >> ... >> msi-parent = <0xfdeb>; >> phandle = <0x1>; >> }; >> >> Note that phandle is generated in this example not by get_next_free_phandle(). >> >> For non RISC-V people, APLIC is an interrupt controller (something like GIC in >> Arm), IMSIC it is interrupt controller which provides MSI and connects to >> each CPU. >> >> [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt >> --- >> Changes in v2: >> - s/free_phandle/next_phandle. >> - s/get_next_free_phandle/alloc_phandle. >> --- >> xen/common/device-tree/dom0less-build.c | 44 ++++++++++++++++++------- >> xen/include/xen/fdt-domain-build.h | 6 ++++ >> xen/include/xen/fdt-kernel.h | 3 ++ >> 3 files changed, 41 insertions(+), 12 deletions(-) >> >> diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c >> index 840d14419da2..ca3ac84a3ef3 100644 >> --- a/xen/common/device-tree/dom0less-build.c >> +++ b/xen/common/device-tree/dom0less-build.c >> @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, >> if ( res < 0 ) >> goto out; >> >> + /* >> + * Find the highest phandle in the partial FDT so next_phandle starts >> + * above it, avoiding collisions with pfdt's own phandle assignments. >> + */ >> + res = fdt_generate_phandle(pfdt, &kinfo->next_phandle); >> + if ( res ) >> + { >> + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; >> + goto out; >> + } >> + >> + if ( kinfo->next_phandle >= GUEST_PHANDLE_GIC ) >> + { >> + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); >> + res = -EOVERFLOW; >> + goto out; >> + } >> + >> for ( node_next = fdt_first_subnode(pfdt, 0); >> node_next > 0; >> node_next = fdt_next_subnode(pfdt, node_next) ) >> @@ -459,6 +477,8 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) >> BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); >> >> kinfo->phandle_intc = GUEST_PHANDLE_GIC; >> + kinfo->next_phandle = 1; >> + BUILD_BUG_ON(GUEST_PHANDLE_GIC == 1); > I'm not sure that we need this. It does not seem to be useful. If you want to > keep it though, I think you want to compare to next_phandle, not opencoding it's > initial value. Agree, alloc_phandle() will catch that. I will drop that. >> >> +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ >> +static inline uint32_t alloc_phandle(struct kernel_info *kinfo) >> +{ >> + return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; >> +} >> + >> #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ >> >> /* >> diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h >> index aa977a50f4fc..438adfe3855b 100644 >> --- a/xen/include/xen/fdt-kernel.h >> +++ b/xen/include/xen/fdt-kernel.h >> @@ -44,6 +44,9 @@ struct kernel_info { >> /* Interrupt controller phandle */ >> uint32_t phandle_intc; >> >> + /* Next free phandle available for assigning to guest device nodes */ > I would mention not to use this value directly but rather obtain from > alloc_phandle. This value should only really be used by alloc_phandle. /* * Next free phandle for guest device nodes; do not access directly, use * alloc_phandle(). */ uint32_t next_phandle; Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 22 13:38:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 13:38:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290575.1570136 (Exim 4.92) (envelope-from ) id 1wFXmR-0004dl-6D; Wed, 22 Apr 2026 13:38:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290575.1570136; Wed, 22 Apr 2026 13:38:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFXmR-0004de-3L; Wed, 22 Apr 2026 13:38:15 +0000 Received: by outflank-mailman (input) for mailman id 1290575; Wed, 22 Apr 2026 13:38:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFXmO-0004dX-VQ for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:38:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFXmO-000dtP-5W for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 15:38:12 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8cf3f-e002-0a2a0a5209dd-0a2a4505c518-12 for ; Wed, 22 Apr 2026 15:38:12 +0200 Received: from [209.85.208.174] (helo=mail-lj1-f174.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8cf43-aaa8-0a2a45050019-d155d0aee531-3 for ; Wed, 22 Apr 2026 15:38:11 +0200 Received: by mail-lj1-f174.google.com with SMTP id 38308e7fff4ca-38ce8a5bc20so59390661fa.1 for ; Wed, 22 Apr 2026 06:38:11 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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They are (or at least are suppoosed to > be) sorted, so that finding a particular entry (e.g. while checking for > name clashes) is easy. Sorry, old version of this patch. I put it through the other HAS_* in this file just after HAS_DOM0LESS. > >> --- a/xen/include/xen/domain.h >> +++ b/xen/include/xen/domain.h >> @@ -13,6 +13,19 @@ struct guest_area { >> void *map; >> }; >> >> +#ifdef CONFIG_HAS_DOMAIN_TYPE >> +enum __packed domain_type { >> + DOMAIN_32BIT, >> + DOMAIN_64BIT, >> +}; >> +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) >> +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) >> +#elif !defined(CONFIG_64BIT) >> +/* On 32-bit-only platforms all domains are 32-bit. */ > > Btw, while this may be true in practice right now, it is not given. A > 32-bit hypervisor can in principle be capable of running 64-bit guests. Agree that it could be. Do you prefer to change this comment to "At the moment ... are expected to be 32-bit."? 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-bad1c0/1776865279-43F7EA53-DE008AD3/0/0 X-purgate-type: clean X-purgate-size: 1000 On 22.04.2026 15:16, Bernhard Kaindl wrote: > Jan Beulich wrote: > PS: Gitweb finds this commit for adding the function: > > https://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=0d6a3c755374f04f6dd25373da28291a8f35bede > > efi: introduce efi_arch_flush_dcache_area > > Objects loaded by FileHandle->Read need to be flushed from dcache, > otherwise copy_from_paddr will read stale data when copying the kernel, > causing a failure to boot. I.e. irrelevant to the cfg file buffer. So what we could do there to make things less questionable (as to ordering) is if ( file == &cfg ) file->str[file->size] = 0; else efi_arch_flush_dcache_area(file->ptr, file->size); > Introduce efi_arch_flush_dcache_area and call it from read_file. > > This commit introduces no functional changes on x86. > > Reported-by: Mark Rutland > Signed-off-by: Stefano Stabellini Stefano, any thoughts? Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 22 13:44:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 13:44:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290597.1570153 (Exim 4.92) (envelope-from ) id 1wFXs0-0006j7-26; Wed, 22 Apr 2026 13:44:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290597.1570153; Wed, 22 Apr 2026 13:44:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFXrz-0006j0-Vj; Wed, 22 Apr 2026 13:43:59 +0000 Received: by outflank-mailman (input) for mailman id 1290597; Wed, 22 Apr 2026 13:43:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFXrz-0006iu-10 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:43:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFXry-00F0FH-EA for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 15:43:58 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8d07f-e002-0a2a0a5209dd-0a2a4502e1be-34 for ; Wed, 22 Apr 2026 15:43:58 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8d09e-af86-0a2a45020019-d1558035d57d-3 for ; Wed, 22 Apr 2026 15:43:58 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-488ba840146so50403095e9.1 for ; Wed, 22 Apr 2026 06:43:58 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776865438-82175161-BEB70187/0/0 X-purgate-type: clean X-purgate-size: 1009 On 22.04.2026 15:38, Oleksii Kurochko wrote: > On 4/22/26 12:37 PM, Jan Beulich wrote: >> On 22.04.2026 11:44, Oleksii Kurochko wrote: >>> --- a/xen/include/xen/domain.h >>> +++ b/xen/include/xen/domain.h >>> @@ -13,6 +13,19 @@ struct guest_area { >>> void *map; >>> }; >>> >>> +#ifdef CONFIG_HAS_DOMAIN_TYPE >>> +enum __packed domain_type { >>> + DOMAIN_32BIT, >>> + DOMAIN_64BIT, >>> +}; >>> +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) >>> +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) >>> +#elif !defined(CONFIG_64BIT) >>> +/* On 32-bit-only platforms all domains are 32-bit. */ >> >> Btw, while this may be true in practice right now, it is not given. A >> 32-bit hypervisor can in principle be capable of running 64-bit guests. > > Agree that it could be. > > Do you prefer to change this comment to "At the moment ... are expected > to be 32-bit."? Something like this, yes, please. I wouldn't mind "expected" to be omitted. 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AFNElJ9HkMUBDgd/jEIT6Dp/xIysJPPJpZmXjw7p5QkQnLNWUMehUj5J1rxOtpKFFukXLVPadXIButDtmUE=@lists.xenproject.org X-Gm-Message-State: AOJu0Yzj425ArSBULMctZc+tS1ifPp8Q0y7/icv4/W0lkZEJTD9eEhJT 05aw43WMvRWP9LayyDDwCtNLQv1UaRHWlu/sHEkYX0bpbrVChVaIvryf X-Gm-Gg: AeBDiesYRlswOIwO5rsBbN99tigNqCFzboh83ImnD+wWDctyzWjfADW+Qe2wwV41LO6 Rgwr7QKlJ45DJ7aj6WOV72XAxS2l6Qx82/2Ngyt50LE/SAtBYtbYvaJbNfHJBBnUbjHf9e+pIyy Xdl4amz+uBhedy2MHQa0vXq2XvUAFt0Xxm2W5EMIgksvCxt2VGhnPo34bdu0Oore4NRrTUN421z Z6ISX2wY+Kn3DQdJFisJhI/83psIMp4IV0WngqVbQI+I8ouF5fvgn+bWxBwuR4VJMME6zXjWKfh cEd3SDxoJiHooUsqXAnrRwl4PW0xq4a3D+ZijlcbhgRMviBdRadbKvWoH1+ei8UisbBvEs1I9vo KWpJZyqf4xdDrLMdE0zcEUsdPCV2M0gGWgiqNhyaFQZ4eQQWskPbM6n+lJ9h1KcqudNNwbf17Fj m4mCTWgMq7ImTYH0fArKViI41uAMnvnvbOBnYHWyyCAk9i4E9sNNXjvZ+X9AWN05a7iQ4W8PFT0 a03mAi+Cn/zvw== X-Received: by 2002:a05:6512:3c8f:b0:5a2:c3e4:6c1 with SMTP id 2adb3069b0e04-5a4172e2556mr8658269e87.34.1776865640795; Wed, 22 Apr 2026 06:47:20 -0700 (PDT) Message-ID: <14562fd3-a29c-4a53-8778-79818467695f@gmail.com> Date: Wed, 22 Apr 2026 15:47:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/12] xen/riscv: add kernel loading support To: Jan Beulich Cc: Romain Caritey , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <29ec8e444792caa925ba92cdc406ef8c0b3bd678.1775836193.git.oleksii.kurochko@gmail.com> <6af89a34-3bf1-40cb-a4c5-e9a16ee31295@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1776865641-E97A6443-16740444/10/73395122804 X-purgate-type: spam X-purgate-size: 5595 On 4/22/26 1:57 PM, Jan Beulich wrote: > On 22.04.2026 13:45, Oleksii Kurochko wrote: >> On 4/21/26 10:57 AM, Jan Beulich wrote: >>> On 10.04.2026 17:54, Oleksii Kurochko wrote: >>>> +static paddr_t __init kernel_image_place(struct kernel_info *info) >>>> +{ >>>> + paddr_t load_addr = INVALID_PADDR; >>>> + uint64_t image_size = info->image.image_size ?: info->image.len; >>>> + const struct membanks *banks = kernel_info_get_mem_const(info); >>>> + unsigned int nr_banks = banks->nr_banks; >>>> + unsigned int bi; >>>> + >>>> + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); >>>> + >>>> + /* >>>> + * At the moment, RISC-V's Linux kernel should be always position >>>> + * independent based on "Per-MMU execution" of boot.rst: >>>> + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution >>>> + * >>>> + * But just for the case when RISC-V's Linux kernel isn't position >>>> + * independent it is needed to take load address from >>>> + * info->image.start. >>>> + * >>>> + * If `start` is zero, the Image is position independent. >>>> + */ >>>> + if ( likely(!info->image.start) ) >>>> + { >>>> + for ( bi = 0; bi != nr_banks; bi++ ) >>>> + { >>>> + const struct membank *bank = &banks->bank[bi]; >>>> + paddr_t bank_start = bank->start; >>>> + /* >>>> + * According to boot.rst kernel load address should be properly >>>> + * aligned: >>>> + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location >>>> + * >>>> + * As Image in this case is PIC we can ignore >>>> + * info->image.text_offset. >>>> + */ >>>> + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); >>>> + paddr_t bank_end = bank_start + bank->size; >>>> + paddr_t bank_size; >>>> + >>>> + if ( aligned_start > bank_end ) >>>> + continue; >>>> + >>>> + bank_size = bank_end - aligned_start; >>>> + >>>> + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); >>>> + >>>> + if ( image_size <= bank_size ) >>>> + { >>>> + load_addr = aligned_start; >>>> + break; >>>> + } >>>> + } >>>> + } >>>> + else >>>> + { >>>> + load_addr = info->image.start + info->image.text_offset; >>> >>> Why does stuff ahead of text_offset not need loading? >> >> Here we just calculating only a place where kernel will be loaded. The >> full kernel image will be loaded in kernel_image_load(). > > Okay, but if you calculate an address where the full image won't fit, > how are things going to work? If the full image won't fit than the necessary bank won't be found in for() loop below and so this kernel will be rejected. I expect that in the case when info->image.start is not 0 (so isn't Image isn't PIC) Image want to be specifically load to info->image.start + info->image.text_offset. Is it wrong statement? ~ Oleksii > >>>> + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); >>>> + >>>> + for ( bi = 0; bi != nr_banks; bi++ ) >>>> + { >>>> + const struct membank *bank = &banks->bank[bi]; >>>> + paddr_t bank_start = bank->start; >>>> + paddr_t bank_end = bank_start + bank->size; >>>> + >>>> + if ( (load_addr >= bank_start) && (load_addr < bank_end) && >>>> + (bank_end - load_addr) >= image_size ) >>> >>> Do we have to fear overflow? (If so, shouldn't such an image be rejected >>> rather than an attempt being made to place it?) If not, simply: >> >> Just for a case. As a user may control load_addr and image_size it could >> be some combination which will lead to overflow here. >> >>> >>> if ( (load_addr >= bank_start) && >>> (load_addr + image_size <= bank_end) ) >> >> I will add the following: >> /* >> * Reject a malformed image before the loop to avoid wrapping >> * load_addr + image_size in the per-bank check below. >> * >> * image_size covers the kernel from _start (placed at load_addr = >> * start + text_offset) through _end. The alignment gap >> * [start, load_addr) is padding and need not lie within a bank. >> */ >> if ( image_size > (paddr_t)-1 - load_addr ) >> bi = nr_banks; >> else >> for ( bi = 0; bi != nr_banks; bi++ ) >> { >> const struct membank *bank = &banks->bank[bi]; >> paddr_t bank_start = bank->start; >> paddr_t bank_end = bank_start + bank->size; >> >> if ( (load_addr >= bank_start) && >> (load_addr + image_size <= bank_end) ) >> break; >> } > > Please consider getting away without "else" (and hence with one level > less of indentation): > > bi = image_size <= (paddr_t)-1 - load_addr ? 0 : nr_banks; > for ( ; bi != nr_banks; bi++ ) > ... > >>> Also, does image_size really only cover space starting from .text_offset, >>> rather than from .start? >> >> image_size covers total memory the kernel occupies at runtime. > > Which emphasizes the remark further up. > > Jan From xen-devel-bounces@lists.xenproject.org Wed Apr 22 13:54:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 13:54:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290618.1570171 (Exim 4.92) (envelope-from ) id 1wFY29-00016u-4e; Wed, 22 Apr 2026 13:54:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290618.1570171; Wed, 22 Apr 2026 13:54:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFY29-00016n-1y; Wed, 22 Apr 2026 13:54:29 +0000 Received: by outflank-mailman (input) for mailman id 1290618; Wed, 22 Apr 2026 13:54:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFY27-00016h-Fw for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 13:54:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFY26-007oGY-Ss for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 15:54:26 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8d30f-bab6-0a2a0a5309dd-0a2a4507dea8-12 for ; Wed, 22 Apr 2026 15:54:26 +0200 Received: from [209.85.128.54] (helo=mail-wm1-f54.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8d312-229c-0a2a45070019-d1558036c96e-3 for ; Wed, 22 Apr 2026 15:54:26 +0200 Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-488b8bc6bc9so38983125e9.3 for ; Wed, 22 Apr 2026 06:54:26 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <14562fd3-a29c-4a53-8778-79818467695f@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776866066-16E67C48-D2063E84/0/0 X-purgate-type: clean X-purgate-size: 3450 On 22.04.2026 15:47, Oleksii Kurochko wrote: > On 4/22/26 1:57 PM, Jan Beulich wrote: >> On 22.04.2026 13:45, Oleksii Kurochko wrote: >>> On 4/21/26 10:57 AM, Jan Beulich wrote: >>>> On 10.04.2026 17:54, Oleksii Kurochko wrote: >>>>> +static paddr_t __init kernel_image_place(struct kernel_info *info) >>>>> +{ >>>>> + paddr_t load_addr = INVALID_PADDR; >>>>> + uint64_t image_size = info->image.image_size ?: info->image.len; >>>>> + const struct membanks *banks = kernel_info_get_mem_const(info); >>>>> + unsigned int nr_banks = banks->nr_banks; >>>>> + unsigned int bi; >>>>> + >>>>> + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); >>>>> + >>>>> + /* >>>>> + * At the moment, RISC-V's Linux kernel should be always position >>>>> + * independent based on "Per-MMU execution" of boot.rst: >>>>> + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution >>>>> + * >>>>> + * But just for the case when RISC-V's Linux kernel isn't position >>>>> + * independent it is needed to take load address from >>>>> + * info->image.start. >>>>> + * >>>>> + * If `start` is zero, the Image is position independent. >>>>> + */ >>>>> + if ( likely(!info->image.start) ) >>>>> + { >>>>> + for ( bi = 0; bi != nr_banks; bi++ ) >>>>> + { >>>>> + const struct membank *bank = &banks->bank[bi]; >>>>> + paddr_t bank_start = bank->start; >>>>> + /* >>>>> + * According to boot.rst kernel load address should be properly >>>>> + * aligned: >>>>> + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location >>>>> + * >>>>> + * As Image in this case is PIC we can ignore >>>>> + * info->image.text_offset. >>>>> + */ >>>>> + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); >>>>> + paddr_t bank_end = bank_start + bank->size; >>>>> + paddr_t bank_size; >>>>> + >>>>> + if ( aligned_start > bank_end ) >>>>> + continue; >>>>> + >>>>> + bank_size = bank_end - aligned_start; >>>>> + >>>>> + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); >>>>> + >>>>> + if ( image_size <= bank_size ) >>>>> + { >>>>> + load_addr = aligned_start; >>>>> + break; >>>>> + } >>>>> + } >>>>> + } >>>>> + else >>>>> + { >>>>> + load_addr = info->image.start + info->image.text_offset; >>>> >>>> Why does stuff ahead of text_offset not need loading? >>> >>> Here we just calculating only a place where kernel will be loaded. The >>> full kernel image will be loaded in kernel_image_load(). >> >> Okay, but if you calculate an address where the full image won't fit, >> how are things going to work? > > If the full image won't fit than the necessary bank won't be found in > for() loop below and so this kernel will be rejected. > > I expect that in the case when info->image.start is not 0 (so isn't > Image isn't PIC) Image want to be specifically load to info->image.start > + info->image.text_offset. Is it wrong statement? I don't know, but the adding in of .text_offset looks questionable to me. I simply don't know why such offsetting would be wanted / needed. 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Wed, 22 Apr 2026 07:04:14 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Jens Wiklander Date: Wed, 22 Apr 2026 16:04:02 +0200 X-Gm-Features: AQROBzD4LaPZwDV8-tF5y0H9VSwgHEF2ba1iT0SZO4NQVav6K5VQ7LXkYN-XrMI Message-ID: Subject: Re: [PATCH 6/6] xen/arm: ffa: Deliver VM-to-VM notifications locally To: Bertrand Marquis Cc: xen-devel@lists.xenproject.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1776866656-80F7E161-D52F125B/0/0 X-purgate-type: clean X-purgate-size: 13283 Hi Bertrand, On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis wrote: > > VM notification binding and pending tracking exist for non-secure > endpoints, but FFA_NOTIFICATION_SET still only forwards secure > destinations to the SPMC. Non-secure VMs therefore cannot receive > notifications from other VMs. Local NPI delivery also needs explicit > re-arm tracking so repeated raises are not lost while the interrupt is > already pending. > > Add a local VM notification delivery path for non-secure destinations. > notification_set_vm() resolves the destination endpoint, verifies that > every requested bit is bound to the sender, sets the receiver's > vm_pending bitmap under notif_lock, and raises an NPI only when the > receiver transitions from no local pending notifications to some. > > Track whether a local NPI is already armed with notif_irq_raised, clear > that state once both VM and hypervisor pending bitmaps are drained, and > roll back newly-added VM pending bits if no destination vCPU is online. > Also expose firmware notification availability so FFA_FEATURES only > advertises notification support when it is actually provided by the > firmware or by CONFIG_FFA_VM_TO_VM. > > Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, non-secure > FFA_NOTIFICATION_SET delivers VM-to-VM notifications locally and keeps > NPI delivery reliable across repeated raises. > > Signed-off-by: Bertrand Marquis > --- > xen/arch/arm/tee/ffa.c | 24 +++++-- > xen/arch/arm/tee/ffa_notif.c | 126 +++++++++++++++++++++++++++++++-- > xen/arch/arm/tee/ffa_private.h | 11 ++- > 3 files changed, 147 insertions(+), 14 deletions(-) > > diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c > index 1fe33f26454a..7fe021049cba 100644 > --- a/xen/arch/arm/tee/ffa.c > +++ b/xen/arch/arm/tee/ffa.c > @@ -39,8 +39,13 @@ > * o FFA_MSG_SEND_DIRECT_REQ: > * - only supported from a VM to an SP > * o FFA_NOTIFICATION_*: > + * - only supported when firmware notifications are enabled or VM-to-V= M > + * support is built in > * - only supports global notifications, that is, per vCPU notificatio= ns > - * are not supported > + * are not supported and secure per-vCPU notification information is > + * not forwarded > + * - the source endpoint ID reported for a notification may no longer > + * exist by the time the receiver consumes it > * - doesn't support signalling the secondary scheduler of pending > * notification for secure partitions > * - doesn't support notifications for Xen itself > @@ -245,6 +250,8 @@ static void handle_features(struct cpu_user_regs *reg= s) > uint32_t a1 =3D get_user_reg(regs, 1); > struct domain *d =3D current->domain; > struct ffa_ctx *ctx =3D d->arch.tee; > + bool notif_supported =3D IS_ENABLED(CONFIG_FFA_VM_TO_VM) || > + ffa_notif_fw_enabled(); > > /* > * FFA_FEATURES defines w2 as input properties only for specific > @@ -343,10 +350,16 @@ static void handle_features(struct cpu_user_regs *r= egs) > > break; > case FFA_FEATURE_NOTIF_PEND_INTR: > - ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); > + if ( notif_supported ) > + ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); > + else > + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > break; > case FFA_FEATURE_SCHEDULE_RECV_INTR: > - ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0); > + if ( notif_supported ) > + ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, = 0); > + else > + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > break; > case FFA_PARTITION_INFO_GET_REGS: > if ( ACCESS_ONCE(ctx->guest_vers) >=3D FFA_VERSION_1_2 ) > @@ -361,7 +374,10 @@ static void handle_features(struct cpu_user_regs *re= gs) > case FFA_NOTIFICATION_SET: > case FFA_NOTIFICATION_INFO_GET_32: > case FFA_NOTIFICATION_INFO_GET_64: > - ffa_set_regs_success(regs, 0, 0); > + if ( notif_supported ) > + ffa_set_regs_success(regs, 0, 0); > + else > + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > break; > default: > ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index 4def701f0130..e77321244926 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -20,7 +20,12 @@ static bool __ro_after_init fw_notif_enabled; > static unsigned int __ro_after_init notif_sri_irq; > static DEFINE_SPINLOCK(notif_info_lock); > > -static void inject_notif_pending(struct domain *d) > +bool ffa_notif_fw_enabled(void) > +{ > + return fw_notif_enabled; > +} > + > +static bool inject_notif_pending(struct domain *d) > { > struct vcpu *v; > > @@ -34,13 +39,15 @@ static void inject_notif_pending(struct domain *d) > if ( is_vcpu_online(v) ) > { > vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); > - return; > + return true; > } > } > > if ( printk_ratelimit() ) > printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs off= line\n", > d); > + > + return false; > } > > static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller_i= d, > @@ -104,6 +111,73 @@ out_unlock: > return ret; > } > > +/* > + * Deliver a VM-to-VM notification. ctx->notif.notif_lock protects > + * vm_bind/vm_pending so callers must not hold it already. > + */ > +static int32_t notification_set_vm(uint16_t dst_id, uint16_t src_id, > + uint32_t flags, uint64_t bitmap) > +{ > + struct domain *dst_d; > + struct ffa_ctx *dst_ctx; > + unsigned int id; > + int32_t ret; > + uint64_t prev_bitmap =3D 0; > + uint64_t new_bitmap; > + bool inject =3D false; > + > + if ( flags ) > + return FFA_RET_INVALID_PARAMETERS; > + > + ret =3D ffa_endpoint_domain_lookup(dst_id, &dst_d, &dst_ctx); > + if ( ret ) > + return ret; > + > + ret =3D FFA_RET_OK; > + > + spin_lock(&dst_ctx->notif.notif_lock); > + > + for ( id =3D 0; id < FFA_NUM_VM_NOTIF; id++ ) > + { > + if ( !(bitmap & BIT(id, ULL)) ) > + continue; > + > + if ( dst_ctx->notif.vm_bind[id] !=3D src_id ) > + { > + ret =3D FFA_RET_DENIED; > + goto out_unlock; > + } > + } > + > + prev_bitmap =3D dst_ctx->notif.vm_pending; > + dst_ctx->notif.vm_pending |=3D bitmap; > + if ( !dst_ctx->notif.notif_irq_raised && > + (dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) ) > + { > + dst_ctx->notif.notif_irq_raised =3D true; > + inject =3D true; > + } > + > +out_unlock: > + spin_unlock(&dst_ctx->notif.notif_lock); > + > + new_bitmap =3D bitmap & ~prev_bitmap; > + if ( ret =3D=3D FFA_RET_OK && inject && new_bitmap && > + !inject_notif_pending(dst_d) ) > + { > + spin_lock(&dst_ctx->notif.notif_lock); > + dst_ctx->notif.vm_pending &=3D ~new_bitmap; There's a window above when dst_ctx->notif.notif_lock is unlocked. What if another CPU has modified dst_ctx->notif.vm_pending during that window? Cheers, Jens > + if ( !(dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) = ) > + dst_ctx->notif.notif_irq_raised =3D false; > + spin_unlock(&dst_ctx->notif.notif_lock); > + ret =3D FFA_RET_DENIED; > + } > + > + rcu_unlock_domain(dst_d); > + > + return ret; > +} > + > int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) > { > struct domain *d =3D current->domain; > @@ -285,6 +359,8 @@ void ffa_handle_notification_get(struct cpu_user_regs= *regs) > > if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > { > + bool pending; > + > spin_lock(&ctx->notif.notif_lock); > > if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pendi= ng ) > @@ -293,6 +369,18 @@ void ffa_handle_notification_get(struct cpu_user_reg= s *regs) > ctx->notif.hyp_pending =3D 0; > } > > + if ( (flags & FFA_NOTIF_FLAG_BITMAP_VM) && ctx->notif.vm_pending= ) > + { > + w4 =3D (uint32_t)(ctx->notif.vm_pending & GENMASK(31, 0)); > + w5 =3D (uint32_t)((ctx->notif.vm_pending >> 32) & GENMASK(31= , 0)); > + ctx->notif.vm_pending =3D 0; > + } > + > + pending =3D (ctx->notif.hyp_pending !=3D 0) || > + (ctx->notif.vm_pending !=3D 0); > + if ( !pending ) > + ctx->notif.notif_irq_raised =3D false; > + > spin_unlock(&ctx->notif.notif_lock); > } > > @@ -318,9 +406,17 @@ int32_t ffa_handle_notification_set(struct cpu_user_= regs *regs) > if ( flags ) > return FFA_RET_INVALID_PARAMETERS; > > - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) > - return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bit= map_lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(dest_id) ) > + { > + if ( fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, > + bitmap_lo, bitmap_hi); > + } > + else if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + { > + return notification_set_vm(dest_id, caller_id, flags, > + ((uint64_t)bitmap_hi << 32) | bitmap_= lo); > + } > > return FFA_RET_NOT_SUPPORTED; > } > @@ -330,6 +426,7 @@ void ffa_raise_rx_buffer_full(struct domain *d) > { > struct ffa_ctx *ctx =3D d->arch.tee; > uint32_t prev_bitmap; > + bool inject =3D false; > > if ( !ctx ) > return; > @@ -337,10 +434,23 @@ void ffa_raise_rx_buffer_full(struct domain *d) > spin_lock(&ctx->notif.notif_lock); > prev_bitmap =3D ctx->notif.hyp_pending; > ctx->notif.hyp_pending |=3D FFA_NOTIF_RX_BUFFER_FULL; > + if ( !ctx->notif.notif_irq_raised && > + (ctx->notif.vm_pending || ctx->notif.hyp_pending) ) > + { > + ctx->notif.notif_irq_raised =3D true; > + inject =3D true; > + } > spin_unlock(&ctx->notif.notif_lock); > > - if ( !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) ) > - inject_notif_pending(d); > + if ( inject && !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) && > + !inject_notif_pending(d) ) > + { > + spin_lock(&ctx->notif.notif_lock); > + ctx->notif.hyp_pending &=3D ~FFA_NOTIF_RX_BUFFER_FULL; > + if ( !(ctx->notif.vm_pending || ctx->notif.hyp_pending) ) > + ctx->notif.notif_irq_raised =3D false; > + spin_unlock(&ctx->notif.notif_lock); > + } > } > #endif > > @@ -572,6 +682,7 @@ int ffa_notif_domain_init(struct domain *d) > spin_lock_init(&ctx->notif.notif_lock); > ctx->notif.secure_pending =3D false; > ctx->notif.vm_pending =3D 0; > + ctx->notif.notif_irq_raised =3D false; > for ( i =3D 0; i < FFA_NUM_VM_NOTIF; i++ ) > ctx->notif.vm_bind[i] =3D 0; > ctx->notif.hyp_pending =3D 0; > @@ -594,6 +705,7 @@ void ffa_notif_domain_destroy(struct domain *d) > spin_lock(&ctx->notif.notif_lock); > ctx->notif.secure_pending =3D false; > ctx->notif.vm_pending =3D 0; > + ctx->notif.notif_irq_raised =3D false; > for ( i =3D 0; i < FFA_NUM_VM_NOTIF; i++ ) > ctx->notif.vm_bind[i] =3D 0; > ctx->notif.hyp_pending =3D 0; > diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat= e.h > index 6d83afb3d00a..5bb19bd11dd0 100644 > --- a/xen/arch/arm/tee/ffa_private.h > +++ b/xen/arch/arm/tee/ffa_private.h > @@ -344,13 +344,17 @@ struct ffa_ctx_notif { > uint64_t vm_pending; > > /* > - * Source endpoint bound to each VM notification ID (0 means unbound= ). > + * Tracks whether an NPI has been raised for local pending notificat= ions. > + * Protected by notif_lock. > */ > - uint16_t vm_bind[FFA_NUM_VM_NOTIF]; > + bool notif_irq_raised; > > /* > - * Lock protecting the hypervisor-managed notification state. > + * Source endpoint bound to each VM notification ID (0 means unbound= ). > */ > + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; > + > + /* Lock protecting local notification state. */ > spinlock_t notif_lock; > > /* > @@ -493,6 +497,7 @@ void ffa_notif_init(void); > void ffa_notif_init_interrupt(void); > int ffa_notif_domain_init(struct domain *d); > void ffa_notif_domain_destroy(struct domain *d); > +bool ffa_notif_fw_enabled(void); > > int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs); > int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs); > -- > 2.53.0 > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 14:08:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 14:08:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290641.1570190 (Exim 4.92) (envelope-from ) id 1wFYFK-0004Xz-Gd; Wed, 22 Apr 2026 14:08:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290641.1570190; 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boundary="-=Part.25bc.af5ba2750434f175.19db584d979.3ffb772d6e87de25=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776866875773 X-purgate-ID: tlsNG-42698a/1776866884-7EB70F3B-8430A055/0/0 X-purgate-type: clean X-purgate-size: 2991 ---=Part.25bc.af5ba2750434f175.19db584d979.3ffb772d6e87de25=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Wed, Apr 08, 2026 at 04:40:46PM -0700, dmukhin@ford=2Ecom wrote: > From: Denis Mukhin =20 >=20 > Add a new symbol DOMID_ANY to improve the readability of the code=2E >=20 > Update all relevant domid_alloc() call sites and harden the domid_alloc(= ) > input value check=2E >=20 > Also, fix problem with passing invalid domain IDs in > XEN_DOMCTL_createdomain: turns out libxl__domain_make() (toolstack) > uses 0xffff as domain ID=2E >=20 > Amends: 2d5065060710 ("xen/domain: unify domain ID allocation") > Signed-off-by: Denis Mukhin > --- > Changes since v6: > - fixed libxl_domid_valid_guest() check in libxl_create=2Ec > - Link to v6: https://lore=2Ekernel=2Eorg/xen-devel/20260307025451=2E314= 8078-2-dmukhin@ford=2Ecom/ > - CI: https://gitlab=2Ecom/xen-project/people/dmukhin/xen/-/pipelines/24= 38790748 Unfortunattly, this patch breaks tests in tools/tests, see https://gitlab=2Ecom/xen-project/hardware/xen-staging/-/pipelines/2471= 684142 The tests produces this: Running /usr/lib/xen/tests/test-mem-claim Memory claims tests Free pages: 3059012, Oustanding claims: 0 Domain create failure: 17 - File exists FAILED: /usr/lib/xen/tests/test-mem-claim Running /usr/lib/xen/tests/test-paging-mempool Paging mempool tests Domain create failure: 17 - File exists FAILED: /usr/lib/xen/tests/test-paging-mempool Running /usr/lib/xen/tests/test-resource XENMEM_acquire_resource tests Test x86 PV Domain create failure: 17 - File exists Test x86 PVH Domain create failure: 17 - File exists FAILED: /usr/lib/xen/tests/test-resource Running /usr/lib/xen/tests/test-tsx TSX tests Host: RTM 0, HLE 0, TSX_FORCE_ABORT 0, RTM_ALWAYS_ABORT 0, TSX_CTRL = 0 Got 16 CPUs Testing MSR_TSX_FORCE_ABORT consistency Testing MSR_TSX_CTRL consistency Testing MSR_MCU_OPT_CTRL consistency Testing RTM behaviour Got #UD Testing PV default/max policies Max: RTM 0, HLE 0, TSX_FORCE_ABORT 0, RTM_ALWAYS_ABORT 0, TSX_CTRL 0 Def: RTM 0, HLE 0, TSX_FORCE_ABORT 0, RTM_ALWAYS_ABORT 0, TSX_CTRL 0 Testing HVM default/max policies Max: RTM 0, HLE 0, TSX_FORCE_ABORT 0, RTM_ALWAYS_ABORT 0, TSX_CTRL 0 Def: RTM 0, HLE 0, TSX_FORCE_ABORT 0, RTM_ALWAYS_ABORT 0, TSX_CTRL 0 Testing PV guest Domain create failure: 17 - File exists Testing HVM guest Domain create failure: 17 - File exists FAILED: /usr/lib/xen/tests/test-tsx At least, the domid test passes :-) Running /usr/lib/xen/tests/test-domid PASSED -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vate= s=2Etech ---=Part.25bc.af5ba2750434f175.19db584d979.3ffb772d6e87de25=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 14:19:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 14:19:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290656.1570199 (Exim 4.92) (envelope-from ) id 1wFYQb-0006vK-HG; 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Recalculate BAR sizes before mapping VFs to account > for possible changes in the system page size register. Also force VFs to > always use emulated reads for command register, this is needed to > prevent some drivers accidentally unmapping BARs. Discovery of VFs is > done by Dom0, which must register them with Xen. > > Signed-off-by: Roger Pau Monné > Signed-off-by: Stewart Hildebrand > Signed-off-by: Mykyta Poturai > --- > v2->v3: > * rework adding VFs with multiple mapping operations support > * use private.h > * style fixes > * fixup cleanup_sriov > * emulate command register read for VFs > > v1->v2: > * switch to VF discovery by Xen > * fix sequential vpci_modify_bars calls > * move documentation changes to a separate commit > --- > xen/drivers/vpci/Makefile | 1 + > xen/drivers/vpci/header.c | 6 +- > xen/drivers/vpci/private.h | 1 + > xen/drivers/vpci/sriov.c | 314 +++++++++++++++++++++++++++++++++++++ > xen/include/xen/vpci.h | 7 +- > 5 files changed, 327 insertions(+), 2 deletions(-) > create mode 100644 xen/drivers/vpci/sriov.c > > diff --git a/xen/drivers/vpci/Makefile b/xen/drivers/vpci/Makefile > index 9793a4f9b0..8b0e3c03a7 100644 > --- a/xen/drivers/vpci/Makefile > +++ b/xen/drivers/vpci/Makefile > @@ -1,3 +1,4 @@ > obj-y += cap.o > obj-y += vpci.o header.o rebar.o > +obj-y += sriov.o > obj-$(CONFIG_HAS_PCI_MSI) += msi.o msix.o > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 451cdd3a6f..a36285672e 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -869,7 +869,8 @@ int vpci_init_header(struct pci_dev *pdev) > * PCI_COMMAND_PARITY, PCI_COMMAND_SERR, and PCI_COMMAND_FAST_BACK. > */ > rc = vpci_add_register_mask(pdev->vpci, > - is_hwdom ? vpci_hw_read16 : guest_cmd_read, > + is_hwdom && !pdev->info.is_virtfn > + ? vpci_hw_read16 : guest_cmd_read, Why are you using the guest command register handler for VFs? A hardware domain should still be able to read the native VF hardware value, as it knows it's a VF. Otherwise this needs a comment explaining why it's needed. > cmd_write, PCI_COMMAND, 2, header, 0, 0, > is_hwdom ? 0 > : PCI_COMMAND_RSVDP_MASK | > @@ -900,6 +901,9 @@ int vpci_init_header(struct pci_dev *pdev) > > header->guest_cmd = cmd; > > + if ( pdev->info.is_virtfn ) > + return vpci_vf_init_header(pdev); > + > /* Disable memory decoding before sizing. */ > if ( !is_hwdom || (cmd & PCI_COMMAND_MEMORY) ) > pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); > diff --git a/xen/drivers/vpci/private.h b/xen/drivers/vpci/private.h > index f012fd160d..8e0043ddbe 100644 > --- a/xen/drivers/vpci/private.h > +++ b/xen/drivers/vpci/private.h > @@ -45,6 +45,7 @@ typedef struct { > REGISTER_VPCI_CAPABILITY(PCI_EXT_CAP_ID_##name, name, finit, fclean, true) > > int __must_check vpci_init_header(struct pci_dev *pdev); > +int __must_check vpci_vf_init_header(struct pci_dev *pdev); > > int vpci_init_capabilities(struct pci_dev *pdev, bool ext_only); > void vpci_cleanup_capabilities(struct pci_dev *pdev, bool ext_only); > diff --git a/xen/drivers/vpci/sriov.c b/xen/drivers/vpci/sriov.c > new file mode 100644 > index 0000000000..ec6a7b84d5 > --- /dev/null > +++ b/xen/drivers/vpci/sriov.c > @@ -0,0 +1,314 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Handlers for accesses to the SR-IOV capability structure. > + * > + * Copyright (C) 2026 Citrix Systems R&D > + */ > + > +#include > +#include Newline here ... > +#include ... and here preferably. > +#include "private.h" > + > +static int vf_init_bars(const struct pci_dev *vf_pdev) For sanity sake, vf_pdev shouldn't be const here. We modify it, it's just that the modified fields are different allocations (pdev->vpci). > +{ > + int vf_idx; > + unsigned int i; > + const struct pci_dev *pf_pdev = vf_pdev->pf_pdev; > + struct vpci_bar *bars = vf_pdev->vpci->header.bars; > + struct vpci_bar *physfn_vf_bars = pf_pdev->vpci->sriov->vf_bars; > + unsigned int sriov_pos = pci_find_ext_capability(pf_pdev, > + PCI_EXT_CAP_ID_SRIOV); > + uint16_t offset = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_OFFSET); > + uint16_t stride = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_STRIDE); > + > + vf_idx = vf_pdev->sbdf.sbdf - (pf_pdev->sbdf.sbdf + offset); > + if ( vf_idx < 0 ) > + return -EINVAL; > + > + if ( stride ) > + { > + if ( vf_idx % stride ) > + return -EINVAL; > + vf_idx /= stride; > + } > + > + /* > + * Set up BARs for this VF out of PF's VF BARs taking into account > + * the index of the VF. > + */ > + for ( i = 0; i < PCI_SRIOV_NUM_BARS; i++ ) > + { > + bars[i].addr = physfn_vf_bars[i].addr + vf_idx * physfn_vf_bars[i].size; You only want to set .addr if the BAR is populated? IOW: if the BAR is of type VPCI_BAR_MEM{32,64_LO}. Otherwise we are populating the .addr field with junk. > + bars[i].guest_addr = bars[i].addr; > + bars[i].size = physfn_vf_bars[i].size; > + bars[i].type = physfn_vf_bars[i].type; > + bars[i].prefetchable = physfn_vf_bars[i].prefetchable; > + } > + > + return 0; > +} > + > +static int map_vfs(const struct pci_dev *pf_pdev, uint16_t cmd) > +{ > + struct pci_dev *vf_pdev; > + int rc; > + > + ASSERT(rw_is_write_locked(&pf_pdev->domain->pci_lock)); > + > + list_for_each_entry(vf_pdev, &pf_pdev->vf_list, vf_list) > + { > + rc = vpci_modify_bars(vf_pdev, cmd, false); > + if ( rc ) > + { > + gprintk(XENLOG_ERR, "failed to %s VF %pp: %d\n", > + (cmd & PCI_COMMAND_MEMORY) ? "map" : "unmap", > + &vf_pdev->sbdf, rc); > + return rc; > + } > + > + vf_pdev->vpci->header.guest_cmd &= ~PCI_COMMAND_MEMORY; > + vf_pdev->vpci->header.guest_cmd |= (cmd & PCI_COMMAND_MEMORY); You shouldn't be modifying the guest_cmd here, the hardware domain should see the native VF command register. Hardware domain knows it's a VF. > + } > + > + return 0; > +} > + > +static int size_vf_bars(const struct pci_dev *pf_pdev, unsigned int sriov_pos, > + uint64_t *vf_rlen) > +{ > + struct vpci_bar *bars; > + unsigned int i; > + int rc = 0; > + > + ASSERT(rw_is_write_locked(&pf_pdev->domain->pci_lock)); > + ASSERT(!pf_pdev->info.is_virtfn); > + ASSERT(pf_pdev->vpci->sriov); > + > + /* Read BARs for VFs out of PF's SR-IOV extended capability. */ > + bars = pf_pdev->vpci->sriov->vf_bars; You can do the initialization at variable definition. > + /* Set the BARs addresses and size. */ > + for ( i = 0; i < PCI_SRIOV_NUM_BARS; i += rc ) > + { > + unsigned int idx = sriov_pos + PCI_SRIOV_BAR + i * 4; > + uint32_t bar; > + uint64_t addr, size; > + > + bar = pci_conf_read32(pf_pdev->sbdf, idx); > + > + rc = pci_size_mem_bar(pf_pdev->sbdf, idx, &addr, &size, > + PCI_BAR_VF | > + ((i == PCI_SRIOV_NUM_BARS - 1) ? PCI_BAR_LAST > + : 0)); > + > + /* > + * Update vf_rlen on the PF. According to the spec the size of > + * the BARs can change if the system page size register is > + * modified, so always update rlen when enabling VFs. > + */ > + vf_rlen[i] = size; > + > + if ( !size ) > + { > + bars[i].type = VPCI_BAR_EMPTY; > + continue; > + } > + > + bars[i].addr = addr; > + bars[i].guest_addr = addr; > + bars[i].size = size; > + bars[i].prefetchable = bar & PCI_BASE_ADDRESS_MEM_PREFETCH; > + > + switch ( rc ) > + { > + case 1: > + bars[i].type = VPCI_BAR_MEM32; > + break; > + > + case 2: > + bars[i].type = VPCI_BAR_MEM64_LO; > + bars[i + 1].type = VPCI_BAR_MEM64_HI; > + break; > + > + default: > + ASSERT_UNREACHABLE(); While ASSERT_UNREACHABLE() is fine here, you still need to make sure the code makes progress on non-debug builds, and hence rc should be set to 1 so that the loop moves into processing the next BAR. > + } > + } > + > + rc = rc > 0 ? 0 : rc; This will only take into account the return code of the last pci_size_mem_bar() call. It might be best to either properly accumulate errors, or simply make the function void, seeing as the only caller ignores the return value. > + > + return rc; > +} > + > +static void cf_check control_write(const struct pci_dev *pdev, unsigned int reg, > + uint32_t val, void *data) > +{ > + unsigned int sriov_pos = reg - PCI_SRIOV_CTRL; > + struct vpci_sriov *sriov = pdev->vpci->sriov; > + uint16_t control = pci_conf_read16(pdev->sbdf, reg); > + bool mem_enabled = control & PCI_SRIOV_CTRL_MSE; > + bool new_mem_enabled = val & PCI_SRIOV_CTRL_MSE; > + bool enabled = control & PCI_SRIOV_CTRL_VFE; > + bool new_enabled = val & PCI_SRIOV_CTRL_VFE; > + int rc; > + > + ASSERT(!pdev->info.is_virtfn); > + > + if ( new_enabled == enabled && new_mem_enabled == mem_enabled ) > + { > + pci_conf_write16(pdev->sbdf, reg, val); > + return; > + } > + > + if ( mem_enabled && !new_mem_enabled ) > + map_vfs(pdev, 0); > + > + if ( !enabled && new_enabled ) > + { > + size_vf_bars(pdev, sriov_pos, (uint64_t *)data); > + > + /* > + * Only update the number of active VFs when enabling, when > + * disabling use the cached value in order to always remove the same > + * number of VFs that were active. > + */ > + sriov->num_vfs = pci_conf_read16(pdev->sbdf, > + sriov_pos + PCI_SRIOV_NUM_VF); > + } > + > + if ( !mem_enabled && new_mem_enabled ) > + { > + rc = map_vfs(pdev, PCI_COMMAND_MEMORY); > + > + if ( rc ) > + map_vfs(pdev, 0); > + } > + > + pci_conf_write16(pdev->sbdf, reg, val); > +} > + > +int vpci_vf_init_header(struct pci_dev *vf_pdev) > +{ > + const struct pci_dev *pf_pdev; > + unsigned int sriov_pos; > + int rc = 0; > + uint16_t ctrl; > + > + ASSERT(rw_is_write_locked(&vf_pdev->domain->pci_lock)); > + > + if ( !vf_pdev->info.is_virtfn ) > + return 0; > + > + pf_pdev = vf_pdev->pf_pdev; > + ASSERT(pf_pdev); > + > + rc = vf_init_bars(vf_pdev); > + if ( rc ) > + return rc; > + > + sriov_pos = pci_find_ext_capability(pf_pdev, PCI_EXT_CAP_ID_SRIOV); > + ctrl = pci_conf_read16(pf_pdev->sbdf, sriov_pos + PCI_SRIOV_CTRL); > + > + if ( (pf_pdev->domain == vf_pdev->domain) && (ctrl & PCI_SRIOV_CTRL_MSE) ) > + { > + rc = vpci_modify_bars(vf_pdev, PCI_COMMAND_MEMORY, false); > + if ( rc ) > + return rc; > + > + vf_pdev->vpci->header.guest_cmd |= PCI_COMMAND_MEMORY; > + } > + > + return rc; > +} > + > +static int cf_check init_sriov(struct pci_dev *pdev) > +{ > + unsigned int pos; > + > + ASSERT(!pdev->info.is_virtfn); > + > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); > + > + if ( !pos ) > + return 0; > + > + if ( xsm_resource_setup_pci(XSM_PRIV, pdev->sbdf.bdf) ) > + { > + printk(XENLOG_ERR > + "%pp: SR-IOV configuration unsupported for unpriv %pd\n", > + &pdev->sbdf, pdev->domain); > + return -EACCES; > + } > + > + pdev->vpci->sriov = xzalloc(struct vpci_sriov); > + if ( !pdev->vpci->sriov ) > + return -ENOMEM; > + > + /* > + * We need to modify vf_rlen in control_write but we can't do it cleanly > + * from pdev because write callback only accepts const pdev. Moving vf_rlen > + * inside of struct vpci_sriov is also not possible because it is used > + * before vpci init. So pass it here as additional data to not require > + * dropping const in control_write. > + */ > + return vpci_add_register(pdev->vpci, vpci_hw_read16, control_write, > + pos + PCI_SRIOV_CTRL, 2, &pdev->physfn.vf_rlen); > +} > + > +static int cf_check cleanup_sriov(const struct pci_dev *pdev, bool hide) > +{ > + unsigned int pos; > + int rc; > + > + if ( !pdev->vpci->sriov ) > + return 0; > + > + ASSERT(!pdev->info.is_virtfn); > + ASSERT(list_empty(&pdev->vf_list)); > + > + if ( !hide ) > + { > + XFREE(pdev->vpci->sriov); > + return 0; > + } > + > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); You need to rework this a bit, after some recent changes access to the ECAM space could disappear if dom0 signals that it's not OK to use whatever memory range Xen was using. Hence the position of the SR-IOV capability needs to be cached at init time, so it can be removed here regardless of whether access to ECAM has been lost/revoked. > + rc = vpci_remove_registers(pdev->vpci, pos + PCI_SRIOV_CTRL, 2); > + if ( rc ) > + { > + printk(XENLOG_ERR "%pd %pp: fail to remove SRIOV handlers rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); > + ASSERT_UNREACHABLE(); > + return rc; > + } > + XFREE(pdev->vpci->sriov); > + > + /* > + * Unprivileged domains have a deny by default register access policy, no > + * need to add any further handlers for them. > + */ > + if ( !is_hardware_domain(pdev->domain) ) > + return 0; > + > + rc = vpci_add_register(pdev->vpci, vpci_hw_read16, NULL, > + pos + PCI_SRIOV_CTRL, 2, NULL); > + if ( rc ) > + printk(XENLOG_ERR "%pd %pp: fail to add SRIOV ctrl handler rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); > + > + return rc; > +} > + > +REGISTER_VPCI_EXTCAP(SRIOV, init_sriov, cleanup_sriov); > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * tab-width: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h > index e34f7abe6d..fc8a943abe 100644 > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -84,7 +84,6 @@ struct vpci { > * upon to know whether BARs are mapped into the guest p2m. > */ > bool bars_mapped : 1; > - /* FIXME: currently there's no support for SR-IOV. */ You want to add a note to CHANGELOG also to note the SR-IOV support addition. Thanks, Roger. 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> >> > >> - for ( j = 0; j < ARRAY_SIZE(header->bars); j++ ) > >> + for ( j = 0; j < ARRAY_SIZE(current->vpci.mem); j++ ) > > > > You make a non-trivial use of current in vpci_modify_bars(), maybe you > > should consider introducing a local variable for it: > > > > struct *vcpu curr = current; > > Without any intention to negate this, ... > > > current expands to a call to get_cpu_info(9, which is better to avoid > > doing repeatedly, specially in the context above which is used as a > > loop upper bound. > > ... I'd like to point out that "current" isn't evaluated when used by > ARRAY_SIZE() (resolving to two uses of sizeof()). Oh indeed, this is just for getting the type. Thanks, Roger. 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Wed, 22 Apr 2026 07:23:50 -0700 (PDT) Message-ID: <92df43ee-10d5-44a2-95db-40ba6d50be79@suse.com> Date: Wed, 22 Apr 2026 16:23:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7] xen/domain: introduce DOMID_ANY To: Anthony PERARD , dmukhin@ford.com Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org References: <20260408234046.1314021-1-dmukhin@ford.com> <1776866876.8631fc262581453bbf619ec5b2062170.19db584dbc0000f373@vates.tech> Content-Language: en-US From: Juergen Gross Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <1776866876.8631fc262581453bbf619ec5b2062170.19db584dbc0000f373@vates.tech> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------ZVvIS81M8DFT0VBmW25XLMYd" X-purgate-ID: tlsNG-d25034/1776867831-F6809CF5-889F0C03/0/0 X-purgate-type: clean X-purgate-size: 10226 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------ZVvIS81M8DFT0VBmW25XLMYd Content-Type: multipart/mixed; boundary="------------dNXgFXAAhol0vXtEpcV0ui5x"; protected-headers="v1" From: Juergen Gross To: Anthony PERARD , dmukhin@ford.com Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org Message-ID: <92df43ee-10d5-44a2-95db-40ba6d50be79@suse.com> Subject: Re: [PATCH v7] xen/domain: introduce DOMID_ANY References: <20260408234046.1314021-1-dmukhin@ford.com> <1776866876.8631fc262581453bbf619ec5b2062170.19db584dbc0000f373@vates.tech> In-Reply-To: <1776866876.8631fc262581453bbf619ec5b2062170.19db584dbc0000f373@vates.tech> Autocrypt-Gossip: addr=jbeulich@suse.com; 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmno2fUFAwAAAAAACgkQsN6d1ii/Ey9J Nwf9GYln88oVVwRdAHk/fn7SF9hVVGc3zQLVPva0nVj6JS/4iXIQuHAWUiFO66ncPCI/sX8R55Zj AmVTTDf/0zv/2TWxLf+PmRsMMrHt3efjV6wQxRcLdT6SQh4/Y85eLpKwDm0sJeeGGyKbkPUp6Q9T cIMO0yAHafdTO/ga7siBEJa24h5nXFHNxK5a6OYG7qmlY4iTEOCZyQvB3GP5MboNgettQBO1vAOh 4xviXHt3Nf4iMVPFmBcxn6NLxfvDPsDhvv4F5FLxGDbv7wUbfNTNmZLMxiXXRbf/TOQ5w1MAkpWL dZieY7/1nn9JIGZIPalD5Q4EmmvEmvxZt/loaGG7aw== =WWWh -----END PGP SIGNATURE----- --------------ZVvIS81M8DFT0VBmW25XLMYd-- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 14:32:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 14:32:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290699.1570225 (Exim 4.92) (envelope-from ) id 1wFYdE-0002qd-3Z; Wed, 22 Apr 2026 14:32:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290699.1570225; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-16d1c6/1776868365-90071D75-C9B08113/10/73395122804 X-purgate-type: spam X-purgate-size: 4634 On 4/22/26 3:54 PM, Jan Beulich wrote: > On 22.04.2026 15:47, Oleksii Kurochko wrote: >> On 4/22/26 1:57 PM, Jan Beulich wrote: >>> On 22.04.2026 13:45, Oleksii Kurochko wrote: >>>> On 4/21/26 10:57 AM, Jan Beulich wrote: >>>>> On 10.04.2026 17:54, Oleksii Kurochko wrote: >>>>>> +static paddr_t __init kernel_image_place(struct kernel_info *info) >>>>>> +{ >>>>>> + paddr_t load_addr = INVALID_PADDR; >>>>>> + uint64_t image_size = info->image.image_size ?: info->image.len; >>>>>> + const struct membanks *banks = kernel_info_get_mem_const(info); >>>>>> + unsigned int nr_banks = banks->nr_banks; >>>>>> + unsigned int bi; >>>>>> + >>>>>> + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); >>>>>> + >>>>>> + /* >>>>>> + * At the moment, RISC-V's Linux kernel should be always position >>>>>> + * independent based on "Per-MMU execution" of boot.rst: >>>>>> + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution >>>>>> + * >>>>>> + * But just for the case when RISC-V's Linux kernel isn't position >>>>>> + * independent it is needed to take load address from >>>>>> + * info->image.start. >>>>>> + * >>>>>> + * If `start` is zero, the Image is position independent. >>>>>> + */ >>>>>> + if ( likely(!info->image.start) ) >>>>>> + { >>>>>> + for ( bi = 0; bi != nr_banks; bi++ ) >>>>>> + { >>>>>> + const struct membank *bank = &banks->bank[bi]; >>>>>> + paddr_t bank_start = bank->start; >>>>>> + /* >>>>>> + * According to boot.rst kernel load address should be properly >>>>>> + * aligned: >>>>>> + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location >>>>>> + * >>>>>> + * As Image in this case is PIC we can ignore >>>>>> + * info->image.text_offset. >>>>>> + */ >>>>>> + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); >>>>>> + paddr_t bank_end = bank_start + bank->size; >>>>>> + paddr_t bank_size; >>>>>> + >>>>>> + if ( aligned_start > bank_end ) >>>>>> + continue; >>>>>> + >>>>>> + bank_size = bank_end - aligned_start; >>>>>> + >>>>>> + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); >>>>>> + >>>>>> + if ( image_size <= bank_size ) >>>>>> + { >>>>>> + load_addr = aligned_start; >>>>>> + break; >>>>>> + } >>>>>> + } >>>>>> + } >>>>>> + else >>>>>> + { >>>>>> + load_addr = info->image.start + info->image.text_offset; >>>>> >>>>> Why does stuff ahead of text_offset not need loading? >>>> >>>> Here we just calculating only a place where kernel will be loaded. The >>>> full kernel image will be loaded in kernel_image_load(). >>> >>> Okay, but if you calculate an address where the full image won't fit, >>> how are things going to work? >> >> If the full image won't fit than the necessary bank won't be found in >> for() loop below and so this kernel will be rejected. >> >> I expect that in the case when info->image.start is not 0 (so isn't >> Image isn't PIC) Image want to be specifically load to info->image.start >> + info->image.text_offset. Is it wrong statement? > > I don't know, but the adding in of .text_offset looks questionable to me. > I simply don't know why such offsetting would be wanted / needed. In the /Documentation/arch/riscv/boot-image-header.rst: This header format is compliant with PE/COFF header and largely inspired from ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common header in future. Than if to look at the comment near text_offset it is mentioned that: /* Image load offset, little endian */ So it is basically Image load offset and that is why I expect it should be added to calculation of load_addr. Considering that boot image header is based on Arm64 I assume that an explanation regarding text_offset for Arm64 (/Documentation/arch/arm64/booting.rst:) should be true for RISC-V: ``` The Image must be placed text_offset bytes from a 2MB aligned base address anywhere in usable system RAM and called there. The region between the 2 MB aligned base address and the start of the image has no special significance to the kernel, and may be used for other purposes. At least image_size bytes from the start of the image must be free for use by the kernel. ``` ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 22 14:35:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 14:35:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290710.1570234 (Exim 4.92) (envelope-from ) id 1wFYg7-0003QA-KG; Wed, 22 Apr 2026 14:35:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290710.1570234; Wed, 22 Apr 2026 14:35:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFYg7-0003Q3-HG; Wed, 22 Apr 2026 14:35:47 +0000 Received: by outflank-mailman (input) for mailman id 1290710; Wed, 22 Apr 2026 14:35:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFYg6-0003Px-Qe for xen-devel@lists.xenproject.org; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a4187ebf2asm4493897e87.80.2026.04.22.07.38.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Apr 2026 07:38:51 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776868732; x=1777473532; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=SQRMRHTjpS2tKlDulaUwvlqdBl8ZjW8ncPDYcuyZIlc=; b=MGH6x7jTJ/hNDhD7CByfgwZIYsK4hpXc0J2417+BmcmgKCoGq5r6cipTM4nqSDCiGR vfgWjA+ds/veLwZG1x3wGVbyhWvUGYQmMWSCnQLn6gTqPosmmB1It6Z5FbMM+2PGRmHK lEgRlQlDQBegx3L8a9D3DeMfESF4o2mTos7GTc39lqj6wl+H9ncfRu2QtHoKXt5VPITg mxeB87DWEPU9nzTzs0oXpmrpM8UU03rsjriC87+qXS9xH+8f8cVBOuZXAEpQExr5vgYc ELhyGJm48PUyZitBizMkJKWAjEDLYDuyY13jVd+rjf9RfEBOkCvdtKVrCxjOo9KJ/kq+ HsAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776868732; x=1777473532; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=SQRMRHTjpS2tKlDulaUwvlqdBl8ZjW8ncPDYcuyZIlc=; b=kVMFYrNwVG1jRPjWKAKvn8eai1ZLmHKdKUi3KS4zYF8/wie0IOSwg39bdBx9EH2p+r GgPJcOi4aLwDb5p/QFD2DXZi00GVysPTYikN0ZdWILYPWDjoOldkOtWGFB4AXL/KxIhP ov0cCL/sb/5VMCT0RE6K+uWXUv7WminUSlrZaZsqj2ozkNXkFbKtROIJF85Fgnu9JXeE j+v/6kZ+dVSJJr7LF3sQJ2jLlGCLXjEgNizZB9SvX61VZQJEP95KNNyNGINKn8GNkHHo zc0AadDJk/OncJPT+ernD3PRlGiD4353Wr6ZxuhlvRUb5ZUB1NaMD3DZvK9Ys7thUNrY +TMw== X-Forwarded-Encrypted: i=1; AFNElJ8WDMVLRiIgRz3ZIbNRZLZlooN4bO5Yz8YiACY7IUSrUG7bMbnvkFDEjNqeIBFd8RQx5mazAYaxbGI=@lists.xenproject.org X-Gm-Message-State: AOJu0Yw2RxUQ1BQNOpo186PqnL/H1AIijPCinTRb2qB6zZt1xMMt5OQy kcy/g3ewtUE83VChy/N3pN1Dm72z0L7PRWLEXlUyjLtjlKLWofUiKE5f X-Gm-Gg: AeBDieuKR7a57lC7JCXZ3uNwQKRbcUx85Kpg4NvRCahxRGHCBK0+CIpH0IWMXUwBUdT fIQ1GLI9KNARdR2P+UNaOebkOytW2T9QbX6XHg7LqMF3B6pX5fZxi7KHfMomDNluGe3b6Rt7jGx mmJ2O01KovfTJBjqis4Ndm5itDwQx5E0+fBugQMbz7tlWopkqDu7AvsmWgc+UMo5wWZXZeGT2Zn iOfVvULcH6B6E/YB6zH+RMGYrSMWMksOkpyMTm6CiDNNlYPp74cyJ8et3+lB6IDvndadla6K+vC UTIjdhrKa0HzR9fmf/g7ifEJo1DnvfNpON8cIfPcDO6FYUDHJQNXTqzj1VJy3AyDG/JsLXq1mkb DRZyKMKFvWXAErtePD0Sm6lVAm/er8Us8zVjOUNFY750RZGYSpRDFjmwmWHvzPuAIhGIZ+ZXkL/ bUvEfWIkWfqTPEUvPaG3FjqpZjNck2nJVs5NfL5CbZymJOydYUbXB6XhppuGepaYHvewsfpD1P0 uwnAxWcn5pk7g== X-Received: by 2002:a05:6512:692:b0:5a4:2bf:28b9 with SMTP id 2adb3069b0e04-5a4172ea032mr9070160e87.43.1776868732241; Wed, 22 Apr 2026 07:38:52 -0700 (PDT) Message-ID: <37332fde-7996-4370-b126-9faa62e39ac5@gmail.com> Date: Wed, 22 Apr 2026 16:38:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/12] xen: introduce domain-layout.h with common domain_use_host_layout() To: Jan Beulich Cc: Romain Caritey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <2057380b431df202adedf852ad492dd0f156f863.1775836193.git.oleksii.kurochko@gmail.com> <702045f6-a342-4662-9eaa-76f7be1df8fa@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <702045f6-a342-4662-9eaa-76f7be1df8fa@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-720697/1776868733-80F7E161-1A6DC50D/10/73395122804 X-purgate-type: spam X-purgate-size: 1908 On 4/21/26 11:20 AM, Jan Beulich wrote: > On 10.04.2026 17:54, Oleksii Kurochko wrote: >> --- /dev/null >> +++ b/xen/include/xen/domain-layout.h >> @@ -0,0 +1,28 @@ >> +#ifndef __XEN_DOMAIN_LAYOUT_H__ >> +#define __XEN_DOMAIN_LAYOUT_H__ >> + >> +#include >> +#include >> +#include >> + >> +/* >> + * Is a domain using the host memory layout? >> + * >> + * domain_use_host_layout() is always False for PV guests. >> + * >> + * Direct-mapped domains (autotranslated domains with memory allocated >> + * contiguously and mapped 1:1 so that GFN == MFN) are always using the >> + * host memory layout to avoid address clashes. > > What is "to avoid address clashes" about? If GFN == MFN, how could there > be clashes? > >> + * The hardware domain will use the host layout (regardless of >> + * direct-mapped) because some OS may rely on specific address ranges >> + * for the devices. PV Dom0, like any other PV guests, has >> + * domain_use_host_layout() returning False. > > This last sentence is somewhat redundant and somewhat in conflict with > what is said further up. If you did s/guests/domains (including Dom0)/ > there, imo this sentence would best be dropped from down here. I will change the comment to: /* * Is a domain using the host memory layout? * * domain_use_host_layout() is always False for PV domains (including Dom0). * * Direct-mapped domains (autotranslated domains with memory allocated * contiguously and mapped 1:1 so that GFN == MFN) must use the host * memory layout since GFN == MFN by definition. * * The hardware domain will use the host layout (regardless of * direct-mapped) because some OS may rely on specific address ranges * for the devices. */ > > With these adjustments: > Acked-by: Jan Beulich Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 22 14:52:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 14:52:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290734.1570253 (Exim 4.92) (envelope-from ) id 1wFYvv-00081f-43; Wed, 22 Apr 2026 14:52:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290734.1570253; Wed, 22 Apr 2026 14:52:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFYvv-00081Y-13; Wed, 22 Apr 2026 14:52:07 +0000 Received: by outflank-mailman (input) for mailman id 1290734; Wed, 22 Apr 2026 14:52:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFYvt-00081S-Cl for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 14:52:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFYvs-00FD4E-PN for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 16:52:04 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8e085-bab6-0a2a0a5309dd-0a2a4506cadc-24 for ; Wed, 22 Apr 2026 16:52:04 +0200 Received: from [209.85.208.54] (helo=mail-ed1-f54.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8e094-7371-0a2a45060019-d155d036b050-3 for ; Wed, 22 Apr 2026 16:52:04 +0200 Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-67389cf78b0so9926077a12.2 for ; Wed, 22 Apr 2026 07:52:04 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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xen-devel@lists.xenproject.org Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org Message-ID: <560b6d87-87d0-4c6c-ac66-cd0d8a429792@suse.com> Subject: Re: [PATCH v7] xen/domain: introduce DOMID_ANY References: <20260408234046.1314021-1-dmukhin@ford.com> In-Reply-To: <20260408234046.1314021-1-dmukhin@ford.com> Autocrypt-Gossip: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 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08:01:31 -0700 (PDT) MIME-Version: 1.0 References: <459cf46204e86ed3a2ffd79ae649b1a2051f5204.1775812563.git.mykola_kvach@epam.com> In-Reply-To: From: Mykola Kvach Date: Wed, 22 Apr 2026 18:00:00 +0300 X-Gm-Features: AQROBzD7bgypQk-e0GQKP_KOPKEgD-zypoZyZJU9-IiXfPHN04O4Kyn5ASiX8NY Message-ID: Subject: Re: [PATCH] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown To: "Orzel, Michal" Cc: xen-devel@lists.xenproject.org, Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1776870092-24CB8F3B-BDF2C1CA/0/0 X-purgate-type: clean X-purgate-size: 2165 Hi Michal, Thank you for the review. On Mon, Apr 20, 2026 at 11:38=E2=80=AFAM Orzel, Michal wrote: > > Hmm, this landed in my junk folder. > > On 10/04/2026 11:36, Mykola Kvach wrote: > > From: Mykola Kvach > > > > The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. > > > > Per IHI0048B.b section 2.3.1, clearing IRQBypDisGrp{0,1} and > > FIQBypDisGrp{0,1} selects bypass rather than deasserted interrupt > > outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 > > show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs > > instead of fully disabling the interface. > > > > Fix this by reading GICC_CTLR, setting the bypass-disable bits, and > > clearing both group-enable bits before writing the value back. Keep the > > existing GICC_CTL_ENABLE definition for the init path and use a separat= e > > mask for the shutdown-side group-enable handling. > IIUC we don't need to worry about not setting the bypass-disable bits in = cpu > init (we only set group 0 and EOI) because they are relevant only when th= e bit 0 > is disabled i.e. the path this patch changes? Yes, that is my understanding as well. In cpu_init(), Xen enables the CPU interface by programming GICC_CTL_ENABLE | GICC_CTL_EOI. In that state, the GIC CPU interface drives the interrupt outputs, so leaving the bypass-disable bits clear does not cause fallback to the legacy bypass path. The issue is specific to cpu_disable(): once the group-enable bits are cleared, leaving the bypass-disable bits clear can select the legacy IRQ/FIQ bypass inputs instead of fully deasserting the outputs. > > > > > Section 2.3.2 also states that wakeup event signals remain available > > even when both GIC interrupt signaling and interrupt bypass are > > disabled, so disabling bypass does not break the power-management use > > case, i.e. suspend modes. > > > > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > > Signed-off-by: Mykola Kvach > Reviewed-by: Michal Orzel > > ~Michal > Best regards, Mykola From xen-devel-bounces@lists.xenproject.org Wed Apr 22 15:36:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 15:36:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290771.1570270 (Exim 4.92) (envelope-from ) id 1wFZcI-0007bW-FV; Wed, 22 Apr 2026 15:35:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290771.1570270; Wed, 22 Apr 2026 15:35:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFZcI-0007bP-Ct; Wed, 22 Apr 2026 15:35:54 +0000 Received: by outflank-mailman (input) for mailman id 1290771; Wed, 22 Apr 2026 15:35:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFZcH-0007bJ-2E for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 15:35:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFZcG-000yiV-Ed for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 17:35:52 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8ead4-5cb7-0a2a0a5109dd-0a2a450ccc52-2 for ; Wed, 22 Apr 2026 17:35:52 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8ead7-62f1-0a2a450c0019-a0658308dfdc-3 for ; Wed, 22 Apr 2026 17:35:52 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id 84C56429A6B6; Wed, 22 Apr 2026 11:35:04 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 1/1] xen/mm: normalize page count types to unsigned long Date: Wed, 22 Apr 2026 16:33:23 +0100 Message-Id: <6fd2be46d934688b19b5c84c53c745230cd345d6.1776871968.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1776872152-F48F9CF5-A9757B97/0/0 X-purgate-type: clean X-purgate-size: 2296 The current use of long for total_avail_pages and outstanding_claims creates an unnecessary mix of signed and unsigned types during page allocation calculations. This necessitates awkward constructs like '+ 0UL' to satisfy type matching in macros such as min(). Address this by normalizing `total_avail_pages` and `outstanding_claims` from `long` to `unsigned long`. As a direct consequence of making `total_avail_pages` unsigned, the post-decrement assertions checking for `>= 0` are no longer logically sound. Adjust those assertions to pre-decrement checks. No functional change intended. Suggested-by: Jan Beulich Signed-off-by: Bernhard Kaindl --- xen/common/page_alloc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index b1edef87124f..541a2171c4c5 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -484,10 +484,11 @@ static heap_by_zone_and_order_t *_heap[MAX_NUMNODES]; static unsigned long node_need_scrub[MAX_NUMNODES]; static unsigned long *avail[MAX_NUMNODES]; -static long total_avail_pages; +static unsigned long total_avail_pages; static DEFINE_SPINLOCK(heap_lock); -static long outstanding_claims; /* total outstanding claims by all domains */ +/* total outstanding claims by all domains */ +static unsigned long outstanding_claims; static unsigned long avail_heap_pages( unsigned int zone_lo, unsigned int zone_hi, unsigned int node) @@ -1047,8 +1048,8 @@ static struct page_info *alloc_heap_pages( ASSERT(avail[node][zone] >= request); avail[node][zone] -= request; + ASSERT(total_avail_pages >= request); total_avail_pages -= request; - ASSERT(total_avail_pages >= 0); if ( d && d->outstanding_pages && !(memflags & MEMF_no_refcount) ) { @@ -1240,8 +1241,8 @@ static int reserve_offlined_page(struct page_info *head) continue; avail[node][zone]--; + ASSERT(total_avail_pages > 0); total_avail_pages--; - ASSERT(total_avail_pages >= 0); page_list_add_tail(cur_head, test_bit(_PGC_broken, &cur_head->count_info) ? -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 15:36:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 15:36:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290786.1570280 (Exim 4.92) (envelope-from ) id 1wFZcg-0007yb-N5; Wed, 22 Apr 2026 15:36:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290786.1570280; Wed, 22 Apr 2026 15:36:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFZcg-0007yU-Jy; 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Wed, 22 Apr 2026 15:36:11 +0000 Received: from l14 (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: anthony.perard) by mail2.vates.fr (Postfix) with ESMTPSA id 2831486AED; Wed, 22 Apr 2026 17:36:11 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=RMdXDWOqjRmmYJbO94LXDJeVD1bT0MotR/jczO+vBFE=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=krs/lAxNHtWD8ZJgDDGLFYOnomQICeAtF94DmZa1aPaJkEFiyVFUHhRNJVvmPTO372sG8CDqz HckFfaFvameSep0MqPHGmt6FZ8cIdtTlT4xWFwiliJp10jeAjVlCv7k4FUZLCrgYDj01HoZ6V3Y KWph8BR4sW5tV3BU7ZwfA7EP40t0euxpbvFfD9bSrv5oRVtXIdRQwSYAeiUJ1vEyHE1x3HBs5eM lHxpOGGXO+48kOWjKsfYAV2m5TRW+qauLVH3c9O9e6L12T8RvbSQiGkW8T5UIeu7THtGCSrASom COzjjAyBb8QfnWwNVFwX+0Bh8Wk0cDr/TOrPzdkcAIfw== X-Zone-Loop: 23a0342a037226df6fbbd9eddedb8f8340e888be72aa x-campaign-type: default x-transaction-id: f2a89e3a-cd6c-44b1-b4f0-833cb43b91dc x-swg-uid: 01-57b12bd8-2ebe-466c-8c31-5786b712f82e X-Mailer: Sweego Message-ID: <1776872171.8631fc262581453bbf619ec5b2062170.19db5d5a953000f373@vates.tech> x-swg-bid: 1776872171.8631fc262581453bbf619ec5b2062170.19db5d5a953000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Wed, 22 Apr 2026 17:36:10 +0200 From: Anthony PERARD To: Marek =?iso-8859-1?Q?Marczykowski-G=F3recki?= Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?iso-8859-1?Q?Monn=E9?= Subject: Re: [PATCH test-artifacts v3 09/13] Add trigger-test job, to run test on a Linux built from a branch/tag References: <9893108225500bb841a39918942bc9267e62b6af.1774999132.git-series.marmarek@invisiblethingslab.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.25e8.5edc5adbba897eb8.19db5d5a70b.50242c239d631519=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776872171276 X-purgate-ID: tlsNG-d62444/1776872176-BE667FF4-526ECA59/0/0 X-purgate-type: clean X-purgate-size: 3235 ---=Part.25e8.5edc5adbba897eb8.19db5d5a70b.50242c239d631519=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Wed, Apr 15, 2026 at 07:40:19PM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > On Wed, Apr 15, 2026 at 01:44:47PM +0000, Anthony PERARD wrote: > > On Wed, Apr 01, 2026 at 01:21:59AM +0200, Marek Marczykowski-G=C3=B3re= cki wrote: > > > +trigger-test: > > > + stage: deploy > > > + trigger: > > > + project: $TEST_TRIGGER_REPO > > > + branch: $TEST_TRIGGER_BRANCH > > > + strategy: mirror > > > + variables: > > > + ARTIFACTS_REPO: $CI_PROJECT_PATH > > > + ARTIFACTS_BRANCH: $CI_COMMIT_REF_NAME > > > + LINUX_JOB_X86_64: linux-git-x86_64 > > > + LINUX_JOB_ARM64: linux-git-arm64 > > > + BUILD_FOR_TESTS_ONLY: 1 > >=20 > > Can we add this? > > inherit: > > variables: false > >=20 > > Otherwise, as I understand, the triggered pipeline will also use the > > global variables, like TEST_TRIGGER_REPO, LINUX_GIT_VERSION, =2E=2E=2E= Or I > > could be wrong because we don't set a default value and the are only > > manual/scheduled pipeline variable=2E > >=20 > > https://docs=2Egitlab=2Ecom/ci/yaml/#trigger > > > CI/CD variables defined in a top-level variables section (globally) = or > > > in the trigger job are forwarded to the downstream pipeline as trigg= er > > > variables=2E > >=20 > > https://docs=2Egitlab=2Ecom/ci/pipelines/downstream_pipelines/#prevent= -default-variables-from-being-passed >=20 > Hm, yes, inherit:variables:false might be needed if we'd want to avoid > passing those variables=2E But, TBH I'm not sure if we want to avoid tha= t > - it might be useful at some point to get LINUX_GIT_VERSION there, for > example=2E=20 I've run a test and I don't see LINUX_GIT_VERSION value in the trigger pipeline, only the default value=2E See https://gitlab=2Ecom/xen-project/people/anthonyper/xen/-/jobs/14042314= 690/viewer $ echo triggered by ${LINUX_GIT_URL} and ${LINUX_GIT_VERSION}; triggered by and $ env REGISTRY=3Dregistry=2Egitlab=2Ecom/xen-project/people/anthonyper/test-= artifacts XEN_REGISTRY=3Dregistry=2Egitlab=2Ecom/xen-project/xen LINUX_GIT_VERSION=3D LINUX_GIT_URL=3D TEST_TRIGGER_REPO=3D TEST_TRIGGER_BRANCH=3D ARTIFACTS_REPO=3Dxen-project/people/anthonyper/test-artifacts LINUX_JOB_X86_64=3Dlinux-git-x86_64 =2E=2E=2E So, the triggered pipeline got the value of the variable as set in `=2Egitlab-ci=2Eyml` `variables` section, and the values of the variables set in the trigger job=2E But the value set via push-variable are missing= =2E So far, the triggered pipeline doesn't get the useful variable values, beside the needed ones=2E And my main issue would be with the REGISTRY or XEN_REGISTRY variables, if we rename one into the other, the triggered pipeline could fail=2E So I think we should use inherit:variables:false, and explicitly passthrough the variables we want=2E Cheers, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.25e8.5edc5adbba897eb8.19db5d5a70b.50242c239d631519=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 15:42:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 15:42:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290813.1570288 (Exim 4.92) (envelope-from ) id 1wFZiI-0001lC-9d; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Oc1uVOBCzJ63As0KrTlvKToA+U2miAplnBg2moy27bBIcEh/AD0RIx9k6bT6PrIydGqAujFD5Kg3wMGx043QiZrWTNeU9HRUwZo6aYzyzSem75eWQ2/BSrbtKfvCJOi/NZ1bvarCGtqiOad7GsnP6EsXamrBvaQksOz2/7YoJz05R+gQXNxMWlAgLEcdlswMNuXU8vm/i4BRIr1V6wwJT7xStoReaMuvjhxkb446Gl/EyAbSXHGeEoboozb4OKx0GUZA5XQXlA2B3lBaMh9S72YihpWfL8VOX02jiLg6SPEfGM9zRIEcfKycVlfAYAdJ9kAhDnniSOXS0eDHc3nPSErM2sT6Aae33DHRudveI5j8lH/kSNzzjdllvGVFXwze8vyZh13dSgsjpVqR9klPa7p0aulIWLRVSFvmxERdeuC5IuoZHziqptw8/ljF+9S4 X-OriginatorOrg: elektrobit.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2026 15:41:55.7375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b4cb2b-5c16-447c-29dc-08dea085af14 X-MS-Exchange-CrossTenant-Id: e764c36b-012e-4216-910d-8fd16283182d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e764c36b-012e-4216-910d-8fd16283182d;Ip=[4.79.107.243];Helo=[usbth1es003.ebgroup.elektrobit.com] X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TreatMessagesAsInternal-BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR08MB9525 X-purgate-ID: tlsNG-33051d/1776872524-2957F938-7C658F50/0/0 X-purgate-type: clean X-purgate-size: 243 > How about you add the _view suffix for these? I think it would help=0A= > disambiguate them and also read better than the current _altp2m suffix on= es.=0A= =0A= I think that makes sense, I'll make that change. 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X-Originating-IP: [37.26.189.201] Date: Wed, 22 Apr 2026 17:58:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: iommu@lists.linux.dev, "linux-kernel@vger.kernel.org" Cc: Xen-devel From: Teddy Astie Subject: How to express "externally managed" IOMMU domains for VFIO/IOMMUFD ? X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.25ec.d120997fac5ce7ce.19db5ea652d.e879bb6dc3eb451b=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776873530670 X-purgate-ID: tlsNG-42698a/1776873536-05D6FF3B-608975BF/0/0 X-purgate-type: clean X-purgate-size: 1364 ---=Part.25ec.d120997fac5ce7ce.19db5ea652d.e879bb6dc3eb451b=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hello, On Xen, for PV-IOMMU [1], we have IOMMU support in Dom0, which in=20 particular allows using VFIO and IOMMUFD from Dom0=2E However, its interactions with PCI Passthrough are unclear, and it would= =20 be preferable to let the kernel handle some of this logic=2E That would=20 for instance avoid situations where toolstack causes Xen and Linux to go= =20 out of sync on where devices belong=2E On Xen, we have a dedicated hypercalls for moving a device into another=20 guest (so it no longer belongs in Dom0, at far as DMA is concerned)=2E But it looks like there are no way to describe that idea of "attach that= =20 device to this VM" nor "the device is in a VM"; which makes that=20 impracticable=2E There may be things that could be done with the vIOMMU objects, but=20 there would be no "parent domain" in such case, as said earlier it=20 doesn't exist in the IOMMU subsystem=2E What is expected to be done instead ? Teddy [1] https://www=2Eyoutube=2Ecom/watch?v=3DpLMGRgEJ-Eg -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.25ec.d120997fac5ce7ce.19db5ea652d.e879bb6dc3eb451b=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 16:06:56 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 16:06:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290857.1570315 (Exim 4.92) (envelope-from ) id 1wFa6D-0007AX-Kq; Wed, 22 Apr 2026 16:06:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290857.1570315; Wed, 22 Apr 2026 16:06:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFa6D-0007AQ-Hm; Wed, 22 Apr 2026 16:06:49 +0000 Received: by outflank-mailman (input) for mailman id 1290857; Wed, 22 Apr 2026 16:06:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFa6B-0007AK-CV for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 16:06:47 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFa6A-0013Mu-EE for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 18:06:46 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e8f206-bab6-0a2a0a5309dd-0a2a45068d9c-18 for ; Wed, 22 Apr 2026 18:06:46 +0200 Received: from [209.85.167.42] (helo=mail-lf1-f42.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e8f215-7371-0a2a45060019-d155a72ab80b-3 for ; Wed, 22 Apr 2026 18:06:46 +0200 Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-59e5aa4ca41so5568350e87.2 for ; Wed, 22 Apr 2026 09:06:46 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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I can rename it to gstage_modes or p2m_modes to make it better suite file scope. >> --- a/xen/include/public/arch-riscv.h >> +++ b/xen/include/public/arch-riscv.h >> @@ -56,6 +56,11 @@ typedef struct vcpu_guest_context vcpu_guest_context_t; >> DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); >> >> struct xen_arch_domainconfig { >> + /* >> + * G-stage MMU mode for the guest (e.g. "sv39", "sv48", "sv57"). >> + * Must be set; an empty string is invalid. >> + */ >> + char gstage_mode[8]; >> }; > > I have to say that I find it odd to use a string literal for this purpose. > Specifying the number of wanted address bits would feel more natural. Plus > the strings named aren't valid G-stage modes afaict - they lack the x4. I will change it to unsigned char gstage_mode and put there on of the value of HGATP_MODE_SV39X4, HGATP_MODE_SV48X4. Or just address bits as you suggested will be fine too. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Wed Apr 22 16:19:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 16:19:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290878.1570325 (Exim 4.92) (envelope-from ) id 1wFaHx-0001Ya-Pf; Wed, 22 Apr 2026 16:18:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290878.1570325; Wed, 22 Apr 2026 16:18:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFaHx-0001YT-Mc; Wed, 22 Apr 2026 16:18:57 +0000 Received: by outflank-mailman (input) for mailman id 1290878; Wed, 22 Apr 2026 16:18:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFaHw-0001Xv-Dv for xen-devel@lists.xenproject.org; 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The branch offset helper sign-extends the decoded immediate by shifting it left into bit 31 and back again. Doing the left shift in the signed domain trips UBSAN on negative offsets, so switch the intermediate to uint32_t and cast back to int32_t only for the final right shift. (XEN) alternatives: Patching with alt table 00000a00005e7298 -> 00000a00005e8894 (XEN) ================================================================================ (XEN) UBSAN: Undefined behaviour in arch/arm/arm64/insn.c:232:15 (XEN) left shift of 66621055 by 6 places cannot be represented in type 'int' (XEN) Xen WARN at common/ubsan/ubsan.c:176 (XEN) ----[ Xen-4.21.0 arm64 debug=y ubsan=y Not tainted ]---- (XEN) CPU: 0 (XEN) PC: 00000a00003432e0 ubsan.c#ubsan_epilogue+0x14/0xec (XEN) LR: 00000a0000344a58 (XEN) SP: 00000a000061fbd0 (XEN) CPSR: 00000000400002c9 MODE:64-bit EL2h (Hypervisor, handler) Edgar E. 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Iglesias" To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com, edgar.iglesias@amd.com Subject: [PATCH v1 1/1] arm64/insn: Avoid undefined behaviour in branch offset decode Date: Wed, 22 Apr 2026 18:45:06 +0200 Message-ID: <20260422164506.2234095-2-edgar.iglesias@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260422164506.2234095-1-edgar.iglesias@amd.com> References: <20260422164506.2234095-1-edgar.iglesias@amd.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA3P292CA0069.ESPP292.PROD.OUTLOOK.COM (2603:10a6:250:49::9) To PH8PR12MB6771.namprd12.prod.outlook.com (2603:10b6:510:1c6::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR12MB6771:EE_|PH8PR12MB7231:EE_ X-MS-Office365-Filtering-Correlation-Id: 26160dec-af7b-4d6d-b262-08dea08e8ddf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|56012099003|22082099003|18002099003; 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Perform the left shift in uint32_t and cast to int32_t only for the final right shift to avoid UBSAN failures on negative offsets. Fixes: 6dbf3f0e3074 ("xen/arm: arm64: Add helpers to decode and encode branch instructions") Signed-off-by: Edgar E. Iglesias --- xen/arch/arm/arm64/insn.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/insn.c b/xen/arch/arm/arm64/insn.c index 81f7914610..6b97a84ba7 100644 --- a/xen/arch/arm/arm64/insn.c +++ b/xen/arch/arm/arm64/insn.c @@ -225,22 +225,22 @@ u32 __kprobes aarch64_insn_gen_nop(void) */ int32_t aarch64_get_branch_offset(uint32_t insn) { - int32_t imm; + uint32_t imm; if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) { imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn); - return (imm << 6) >> 4; + return (int32_t)(imm << 6) >> 4; } if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || aarch64_insn_is_bcond(insn)) { imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn); - return (imm << 13) >> 11; + return (int32_t)(imm << 13) >> 11; } if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) { imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn); - return (imm << 18) >> 16; + return (int32_t)(imm << 18) >> 16; } /* Unhandled instruction */ -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 22 17:00:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 17:00:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1290937.1570359 (Exim 4.92) (envelope-from ) id 1wFavZ-0001Gv-8r; Wed, 22 Apr 2026 16:59:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1290937.1570359; Wed, 22 Apr 2026 16:59:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFavZ-0001Go-5y; Wed, 22 Apr 2026 16:59:53 +0000 Received: by outflank-mailman (input) for mailman id 1290937; Wed, 22 Apr 2026 16:59:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFavX-0001Gi-Cx for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 16:59:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFavW-001Hpq-Pz for xen-devel@lists.xenproject.org; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=RYW9LEhTjgrrty/Kgi/iBI7ELi7kv90yjoE0T2nBmwo=; h=from:subject:date:message-id:to:cc:mime-version:content-type:feedback-id; b=NvhoYzIQDvS9yJ0ocD/Jm33hoy5MMidIdf9ggu2ulh3p3I766Uno3mz7EM3n1irVF42zijL1g sMX+VD3QgrZwLTlAu2BscANFN3LAXulY27nu08DMnwEB0+DDEkSanVhhyJ//JqdqMd/ygIoLlFQ WqaO9YfYii9yXwPXGohFV6Oq2q9f5uqbnyqKmUYnrM5gr06bMpvyOLF7AXmHzIGbpQ6w1JZ3vDQ c8rR1tvVeWJZZ3sAbMdsGCXiX9q9FEvqCdyOQhq9DJ0USPwtezWRIlzCbRBo75IDsmiUNpmG/3Q plDhd/OdX1yGxTUdQ8so1gSHEDuyOCCvjOBYaFM+gWlQ== X-Zone-Loop: 1cf038f0cfac31ff9d52a162034aab7002f8486a3398 x-campaign-type: default x-transaction-id: 923cbf1c-426c-489d-9b5d-9383b5133609 x-swg-uid: 01-8f7c7fb4-76b1-4cac-a66e-d138f73c7fcb X-Mailer: Sweego Message-ID: <1776877188.8631fc262581453bbf619ec5b2062170.19db6223737000f373@vates.tech> x-swg-bid: 1776877188.8631fc262581453bbf619ec5b2062170.19db6223737000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Teddy Astie To: xen-devel@lists.xenproject.org Cc: Teddy Astie , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] x86/amd: Drop allow_unsafe parameter, tune down XSA-9 mitigations Date: Wed, 22 Apr 2026 18:58:06 +0200 MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.25f9.4f43d121d0e65c6c.19db6223500.165d7aa55d327c7c=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776877188352 X-purgate-ID: tlsNG-720697/1776877190-80B78161-84CD3524/0/0 X-purgate-type: clean X-purgate-size: 5218 ---=Part.25f9.4f43d121d0e65c6c.19db6223500.165d7aa55d327c7c=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable XSA-9 mitigations prevents Xen from properly running if a affected CPU is detected=2E While the vulnerability has no mitigations (aside not runni= ng 64-bits PV guests), it's only outcome is a DoS=2E There is no real point in preventing Xen from working here and it would be preferable to just log the vulnerability to the user so it can act appropriately=2E Also reword the errata message regarding that it only affects PV64 guests= =2E Signed-off-by: Teddy Astie --- It's hard to tell whether or not we would want to drop allow_unsafe, but currently, Xen is allowed to boot with XSA-304 mitigations disabled (intentionnaly) which has a similar outcome than this one=2E >From a user standpoint, preventing the system to boot or starting guests i= s too extreme and would be in practice seen as a bug, even if it's justified policy which can be overriden=2E docs/misc/xen-command-line=2Epandoc | 12 ------------ xen/arch/x86/cpu/amd=2Ec | 21 +++++---------------- xen/arch/x86/domain=2Ec | 14 -------------- xen/arch/x86/include/asm/amd=2Eh | 2 -- 4 files changed, 5 insertions(+), 44 deletions(-) diff --git a/docs/misc/xen-command-line=2Epandoc b/docs/misc/xen-command-l= ine=2Epandoc index 6c77129732=2E=2E04d206f919 100644 --- a/docs/misc/xen-command-line=2Epandoc +++ b/docs/misc/xen-command-line=2Epandoc @@ -133,18 +133,6 @@ resume=2E `s3_mode` instructs Xen to set up the boot time (option `vga=3D`) video mode during S3 resume=2E =20 -### allow_unsafe (x86) -> `=3D ` - -> Default: `false` - -Force boot on potentially unsafe systems=2E By default Xen will refuse -to boot on systems with the following errata: - -* AMD Erratum 121=2E Processors with this erratum are subject to a guest - triggerable Denial of Service=2E Override only if you trust all of - your PV guests=2E - ### altp2m (Intel) > `=3D ` =20 diff --git a/xen/arch/x86/cpu/amd=2Ec b/xen/arch/x86/cpu/amd=2Ec index 712734a6e7=2E=2Ef1f4a25754 100644 --- a/xen/arch/x86/cpu/amd=2Ec +++ b/xen/arch/x86/cpu/amd=2Ec @@ -20,10 +20,6 @@ =20 #include "cpu=2Eh" =20 -/* 1 =3D allow, 0 =3D don't allow guest creation, -1 =3D don't allow boot= */ -int8_t __read_mostly opt_allow_unsafe; -boolean_param("allow_unsafe", opt_allow_unsafe); - /* Signal whether the ACPI C1E quirk is required=2E */ bool __read_mostly amd_acpi_c1e_quirk; bool __ro_after_init amd_legacy_ssbd; @@ -1205,19 +1201,12 @@ static void cf_check init_amd(struct cpuinfo_x86 *= c) if (c->family =3D=3D 0x10) __clear_bit(X86_FEATURE_MONITOR, c->x86_capability); =20 - if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121)) - opt_allow_unsafe =3D 1; - else if (opt_allow_unsafe < 0) - panic("Xen will not boot on this CPU for security reasons" - "Pass \"allow_unsafe\" if you're trusting all your" - " (PV) guest kernels=2E\n"); - else if (!opt_allow_unsafe && c =3D=3D &boot_cpu_data) + if (cpu_has_amd_erratum(c, AMD_ERRATUM_121)) + { printk(KERN_WARNING - "*** Xen will not allow creation of DomU-s on" - " this CPU for security reasons=2E ***\n" - KERN_WARNING - "*** Pass \"allow_unsafe\" if you're trusting" - " all your (PV) guest kernels=2E ***\n"); + "*** This CPU is affected with erratum 121" + " 64-bits PV guests are able to cause a DoS (XSA-9) ***\n"); + } =20 if (c->family =3D=3D 0x16 && c->model <=3D 0xf) { if (c =3D=3D &boot_cpu_data) { diff --git a/xen/arch/x86/domain=2Ec b/xen/arch/x86/domain=2Ec index 1d458f1372=2E=2E1d3b99cd50 100644 --- a/xen/arch/x86/domain=2Ec +++ b/xen/arch/x86/domain=2Ec @@ -833,20 +833,6 @@ int arch_domain_create(struct domain *d, =20 spin_lock_init(&d->arch=2Ee820_lock); =20 - if ( d->domain_id && cpu_has_amd_erratum(&boot_cpu_data, AMD_ERRATUM_= 121) ) - { - if ( !opt_allow_unsafe ) - { - printk(XENLOG_G_ERR - "%pd: will not create domU on this CPU for security re= asons\n", - d); - return -EPERM; - } - printk(XENLOG_G_WARNING - "%pd: may compromise security on this CPU\n", - d); - } - emflags =3D config->arch=2Eemulation_flags; =20 if ( is_hardware_domain(d) && is_pv_domain(d) ) diff --git a/xen/arch/x86/include/asm/amd=2Eh b/xen/arch/x86/include/asm/a= md=2Eh index d21df0741a=2E=2Ed8d9cd175e 100644 --- a/xen/arch/x86/include/asm/amd=2Eh +++ b/xen/arch/x86/include/asm/amd=2Eh @@ -74,8 +74,6 @@ struct cpuinfo_x86; int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, =2E= =2E=2E); =20 -extern int8_t opt_allow_unsafe; - void fam10h_check_enable_mmcfg(void); void check_enable_amd_mmconf_dmi(void); =20 --=20 2=2E52=2E0 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.25f9.4f43d121d0e65c6c.19db6223500.165d7aa55d327c7c=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 22 19:42:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 19:42:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291076.1570393 (Exim 4.92) (envelope-from ) id 1wFdSz-0003tD-Nh; Wed, 22 Apr 2026 19:42:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291076.1570393; Wed, 22 Apr 2026 19:42:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFdSz-0003t6-KW; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d25034/1776886951-6D56FCF5-86CEAA84/0/0 X-purgate-type: clean X-purgate-size: 3035 On 4/22/26 12:33, Oleksii Moisieiev wrote: Hello Oleksii > In cuart_init_postirq(), two code paths could reach the > interrupt-enable write to IER without a handler being registered: > > - When no valid IRQ number was provided (uart->irq <= 0), the original > positive-condition guard (if uart->irq > 0) skipped the irqaction > setup but still fell through to the IER write, enabling the receive > data interrupt with no handler installed. > > - When setup_irq() returned an error, only an error message was > printed and execution continued to the IER write, arming the > receive hardware interrupt line with no handler to service it. On > platforms where the GIC receives this asserted line, the result is > either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure cuart_init_postirq() to use early returns in both error > paths. > > Signed-off-by: Oleksii Moisieiev > --- > > Changes in v3: > - clear pending error interrupts before setup_irq call for cadence uart > - change uart->irq <= 0 to uart->irq == 0 since irq is unsigned Reviewed-by: Oleksandr Tyshchenko with NIT (could probably be fixed on commit) ... > > xen/drivers/char/cadence-uart.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) > > diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uart.c > index b2f379833f..8961d39de1 100644 > --- a/xen/drivers/char/cadence-uart.c > +++ b/xen/drivers/char/cadence-uart.c > @@ -72,19 +72,25 @@ static void __init cuart_init_postirq(struct serial_port *port) > struct cuart *uart = port->uart; > int rc; > > - if ( uart->irq > 0 ) > - { > - uart->irqaction.handler = cuart_interrupt; > - uart->irqaction.name = "cadence-uart"; > - uart->irqaction.dev_id = port; > - if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > - printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->irq); > - } > + /* Don't unmask interrupts if no valid irq was provided */ > + if ( uart->irq == 0 ) > + return; > + > + uart->irqaction.handler = cuart_interrupt; > + uart->irqaction.name = "cadence-uart"; > + uart->irqaction.dev_id = port; > > /* Clear pending error interrupts */ > cuart_write(uart, R_UART_RTRIG, 1); > cuart_write(uart, R_UART_CISR, ~0); > > + if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) > + { > + printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->irq); ... the format specifier should be %u instead of %d since the value is unsigned. > + /* Do not unmask interrupts if irq handler wasn't set */ > + return; > + } > + > /* Unmask interrupts */ > cuart_write(uart, R_UART_IDR, ~0); > cuart_write(uart, R_UART_IER, UART_SR_INTR_RTRIG); From xen-devel-bounces@lists.xenproject.org Wed Apr 22 20:55:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 20:55:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291140.1570401 (Exim 4.92) (envelope-from ) id 1wFear-0006SS-Tn; Wed, 22 Apr 2026 20:54:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291140.1570401; Wed, 22 Apr 2026 20:54:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFear-0006SL-R2; Wed, 22 Apr 2026 20:54:45 +0000 Received: by outflank-mailman (input) for mailman id 1291140; Wed, 22 Apr 2026 20:54:44 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFeaq-0006Rw-Cm for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 20:54:44 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFeap-00H3E8-Pf for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 22:54:43 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e93593-e002-0a2a0a5209dd-0a2a45018b5e-0 for ; Wed, 22 Apr 2026 22:54:43 +0200 Received: from [209.85.221.51] (helo=mail-wr1-f51.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e93593-c1f2-0a2a45010019-d155dd33c161-3 for ; Wed, 22 Apr 2026 22:54:43 +0200 Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-43eb05b1875so3504329f8f.3 for ; Wed, 22 Apr 2026 13:54:43 -0700 (PDT) Received: from pumpkin (82-69-66-36.dsl.in-addr.zen.co.uk. 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Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky , kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Subject: Re: [PATCH 1/3] x86/asm, x86/boot: Expose inline memcmp Message-ID: <20260422215441.4204c142@pumpkin> In-Reply-To: <20260422-pvh-kasan-inline-v1-1-7e6194344c92@igalia.com> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> <20260422-pvh-kasan-inline-v1-1-7e6194344c92@igalia.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-d62444/1776891283-BFC74FF4-37BD296C/0/0 X-purgate-type: clean X-purgate-size: 2483 On Wed, 22 Apr 2026 17:07:45 -0300 Mauricio Faria de Oliveira wrote: > Move the inline memcmp function, currently only available to boot code > (boot/string.c), into the header with similar inline string functions > (include/asm/string.h) so it may be reused. This needs a comment/warning that it is incompatible with normal memcmp() because it only returns 0/1 not -1/0/1. Most callers don't care. David > > Add a _SETUP guard in string.h so not to include the 32/64-bit specific > string headers in boot/ code (16-bit, real mode) and avoid build errors. > > Signed-off-by: Mauricio Faria de Oliveira > --- > arch/x86/boot/string.c | 6 ++---- > arch/x86/include/asm/string.h | 11 +++++++++++ > 2 files changed, 13 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c > index b25c6a9303b7314d5caf5c9306239811705294fe..bbee78637b349e42e9281d8df50d89d48f4490b9 100644 > --- a/arch/x86/boot/string.c > +++ b/arch/x86/boot/string.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include "ctype.h" > #include "string.h" > > @@ -31,10 +32,7 @@ > > int memcmp(const void *s1, const void *s2, size_t len) > { > - bool diff; > - asm("repe cmpsb" > - : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); > - return diff; > + return __inline_memcmp(s1, s2, len); > } > > /* > diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h > index 9cb5aae7fba9ffcf0f5af8f939d30467750ccaa9..736a6f6a31f0a68281b4f17415aba0fcd95dc228 100644 > --- a/arch/x86/include/asm/string.h > +++ b/arch/x86/include/asm/string.h > @@ -2,11 +2,13 @@ > #ifndef _ASM_X86_STRING_H > #define _ASM_X86_STRING_H > > +#ifndef _SETUP > #ifdef CONFIG_X86_32 > # include > #else > # include > #endif > +#endif > > static __always_inline void *__inline_memcpy(void *to, const void *from, size_t len) > { > @@ -29,4 +31,13 @@ static __always_inline void *__inline_memset(void *s, int v, size_t n) > return ret; > } > > +static __always_inline int __inline_memcmp(const void *s1, const void *s2, size_t len) > +{ > + bool diff; > + > + asm("repe cmpsb" > + : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); > + return diff; > +} > + > #endif /* _ASM_X86_STRING_H */ > From xen-devel-bounces@lists.xenproject.org Wed Apr 22 22:02:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 22 Apr 2026 22:02:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291219.1570410 (Exim 4.92) (envelope-from ) id 1wFfec-0000DM-Ja; Wed, 22 Apr 2026 22:02:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291219.1570410; Wed, 22 Apr 2026 22:02:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFfec-0000DF-H2; Wed, 22 Apr 2026 22:02:42 +0000 Received: by outflank-mailman (input) for mailman id 1291219; Wed, 22 Apr 2026 22:02:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFfeb-0000D9-DA for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 22:02:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFfea-00CMMP-QA for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 00:02:40 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e9456b-2eae-0a2a0a5409dd-0a2a450ca3b6-18 for ; Thu, 23 Apr 2026 00:02:40 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e9457f-62f1-0a2a450c0019-ac6904fe9f98-3 for ; Thu, 23 Apr 2026 00:02:40 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 14C2461334; Wed, 22 Apr 2026 22:02:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 84666C19425; Wed, 22 Apr 2026 22:02:38 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776895358; bh=eVqQbhtcmM6jxGXcwZAWX+7cU7dFEViGdbj3XrFpMfI=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=KXPm/YAkF+EWCndYuDOVyTtmRkH99JTl8+MfrluMxcDpLi/LfTZ0QN7g0xHO7hvda +CMXRUvclh4UnQG+UGAyeVPSuriNPkuEETGHAQtdcJnk5Om/b4n5S75NtGDzSPJj0y 1iAydKabdDoF+BNPsunrHPoV81RDff+OCQqe9bzmnJyx2lLW8Rc0NFIxE1UwTNX5qi MGI3IpzG0oW8X0HlulQB+2U4OvC3m3ErzLWecagh/VUSKAnJMoiy8oPZHyS1AtThZh EorK23wz+xUOgI42pZfVlPFBhqb9vMD3MJy2yMBmrVPGbJ9EURbVh1DbYOYMASHvEB NPTENeL0uLgXw== Date: Wed, 22 Apr 2026 15:02:37 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: "Edgar E. Iglesias" cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, Volodymyr_Babchuk@epam.com Subject: Re: [PATCH v1 1/1] arm64/insn: Avoid undefined behaviour in branch offset decode In-Reply-To: <20260422164506.2234095-2-edgar.iglesias@amd.com> Message-ID: References: <20260422164506.2234095-1-edgar.iglesias@amd.com> <20260422164506.2234095-2-edgar.iglesias@amd.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-d25034/1776895360-F4C07CF5-2527E894/0/0 X-purgate-type: clean X-purgate-size: 1717 On Wed, 22 Apr 2026, Edgar E. Iglesias wrote: > Branch offset decoding sign-extends the immediate by shifting it left into > bit 31 and back. Perform the left shift in uint32_t and cast to int32_t > only for the final right shift to avoid UBSAN failures on negative offsets. > > Fixes: 6dbf3f0e3074 ("xen/arm: arm64: Add helpers to decode and encode branch instructions") > Signed-off-by: Edgar E. Iglesias Reviewed-by: Stefano Stabellini > --- > xen/arch/arm/arm64/insn.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/arm64/insn.c b/xen/arch/arm/arm64/insn.c > index 81f7914610..6b97a84ba7 100644 > --- a/xen/arch/arm/arm64/insn.c > +++ b/xen/arch/arm/arm64/insn.c > @@ -225,22 +225,22 @@ u32 __kprobes aarch64_insn_gen_nop(void) > */ > int32_t aarch64_get_branch_offset(uint32_t insn) > { > - int32_t imm; > + uint32_t imm; > > if (aarch64_insn_is_b(insn) || aarch64_insn_is_bl(insn)) { > imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_26, insn); > - return (imm << 6) >> 4; > + return (int32_t)(imm << 6) >> 4; > } > > if (aarch64_insn_is_cbz(insn) || aarch64_insn_is_cbnz(insn) || > aarch64_insn_is_bcond(insn)) { > imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_19, insn); > - return (imm << 13) >> 11; > + return (int32_t)(imm << 13) >> 11; > } > > if (aarch64_insn_is_tbz(insn) || aarch64_insn_is_tbnz(insn)) { > imm = aarch64_insn_decode_immediate(AARCH64_INSN_IMM_14, insn); > - return (imm << 18) >> 16; > + return (int32_t)(imm << 18) >> 16; > } > > /* Unhandled instruction */ > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Thu Apr 23 04:57:08 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 04:57:08 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291541.1570420 (Exim 4.92) (envelope-from ) id 1wFm7P-000217-Ov; Thu, 23 Apr 2026 04:56:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291541.1570420; Thu, 23 Apr 2026 04:56:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFm7P-00020x-K9; Thu, 23 Apr 2026 04:56:51 +0000 Received: by outflank-mailman (input) for mailman id 1291541; Thu, 23 Apr 2026 04:56:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFm7O-000206-8R for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 21:56:47 -0700 (PDT) MIME-Version: 1.0 References: <459cf46204e86ed3a2ffd79ae649b1a2051f5204.1775812563.git.mykola_kvach@epam.com> <1E7985CB-EE4C-4769-B23C-EDEF2E75EF08@arm.com> In-Reply-To: <1E7985CB-EE4C-4769-B23C-EDEF2E75EF08@arm.com> From: Mykola Kvach Date: Thu, 23 Apr 2026 07:56:36 +0300 X-Gm-Features: AQROBzA_6YhCxBiY5UFhFwOcd474jGOjYElGn8qjtn5rBjcCecKWeG4-BJWo4LQ Message-ID: Subject: Re: [PATCH] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown To: Luca Fancellu Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1776920208-F40FDCF5-12E222B6/0/0 X-purgate-type: clean X-purgate-size: 2793 Hi Luca, Thank you for the review. On Mon, Apr 20, 2026 at 2:42=E2=80=AFPM Luca Fancellu wrote: > > Hi Mykola, > > > On 10 Apr 2026, at 10:36, Mykola Kvach wrote: > > > > From: Mykola Kvach > > > > The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. > > > > Per IHI0048B.b section 2.3.1, clearing IRQBypDisGrp{0,1} and > > FIQBypDisGrp{0,1} selects bypass rather than deasserted interrupt > > outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 > > show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs > > instead of fully disabling the interface. > > > > Fix this by reading GICC_CTLR, setting the bypass-disable bits, and > > clearing both group-enable bits before writing the value back. Keep the > > existing GICC_CTL_ENABLE definition for the init path and use a separat= e > > mask for the shutdown-side group-enable handling. > > > > Section 2.3.2 also states that wakeup event signals remain available > > even when both GIC interrupt signaling and interrupt bypass are > > disabled, so disabling bypass does not break the power-management use > > case, i.e. suspend modes. > > > > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > > Signed-off-by: Mykola Kvach > > --- > > xen/arch/arm/gic-v2.c | 7 ++++++- > > xen/arch/arm/include/asm/gic.h | 21 +++++++++++++++++++-- > > 2 files changed, 25 insertions(+), 3 deletions(-) > > > > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > > index b23e72a3d0..22aa25bad0 100644 > > --- a/xen/arch/arm/gic-v2.c > > +++ b/xen/arch/arm/gic-v2.c > > @@ -408,7 +408,12 @@ static void gicv2_cpu_init(void) > > > > static void gicv2_cpu_disable(void) > > { > > - writel_gicc(0x0, GICC_CTLR); > > + uint32_t ctlr =3D readl_gicc(GICC_CTLR); > > + > > + ctlr |=3D GICC_CTL_BYP_DIS_MASK; > > If the GIC v2 implementation includes the Security Extensions, the bit 7-= 8 > are reserved, but now we are unconditionally writing on them. You are right. I had assumed that, since these bits are reserved in that view, writing them would be harmless. However, the specification does not say that they are WI, so this is not something the patch should rely on. Looking at it again, there may be a similar layout-dependent issue in cpu_init() as well, since the current write there also forces all other bits to zero apart from the ones explicitly set. I will rework this patch accordingly so that cpu_disable() only updates the bits that are architecturally defined for the current GICC_CTLR layout, and I will take another look at the init path separately. Best regards, Mykola > > Cheers, > Luca > From xen-devel-bounces@lists.xenproject.org Thu Apr 23 05:13:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 05:13:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291549.1570429 (Exim 4.92) (envelope-from ) id 1wFmNX-0006E4-0n; Thu, 23 Apr 2026 05:13:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291549.1570429; Thu, 23 Apr 2026 05:13:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFmNW-0006Dx-U3; Thu, 23 Apr 2026 05:13:30 +0000 Received: by outflank-mailman (input) for mailman id 1291549; Thu, 23 Apr 2026 05:13:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFmNW-0006Dr-5k for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 22:13:27 -0700 (PDT) MIME-Version: 1.0 References: <5b16e00e-9a4d-4a18-8a5e-dde10b42a043@suse.com> <5fb9b5ee-ee71-49ec-b545-62c8ec27fc15@suse.com> <425cdc68-5e25-4e01-b5d9-6469e2d08abb@suse.com> In-Reply-To: From: Mykola Kvach Date: Thu, 23 Apr 2026 08:13:15 +0300 X-Gm-Features: AQROBzDLgaf4ettKLUBXexSNAAtxl3rUW9JKJ58G8GEbqkXZa-IOfnnF7Sg4TzQ Message-ID: Subject: Re: [PATCH v3] xen/arm: vpsci: ignore upper 32 bits for SMC32 PSCI arguments To: Bertrand Marquis Cc: Jan Beulich , Mykola Kvach , Stefano Stabellini , Julien Grall , Michal Orzel , Volodymyr Babchuk , "xen-devel@lists.xenproject.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1776921208-2BD6C3FF-85B1205F/0/0 X-purgate-type: clean X-purgate-size: 7695 Hi Bertrand, On Wed, Apr 15, 2026 at 3:31=E2=80=AFPM Bertrand Marquis wrote: > > Hi Jan and Mykola, > > > On 1 Apr 2026, at 14:24, Jan Beulich wrote: > > > > On 01.04.2026 11:51, Mykola Kvach wrote: > >> On Wed, Apr 1, 2026 at 12:22=E2=80=AFPM Jan Beulich wrote: > >>> On 01.04.2026 10:49, Mykola Kvach wrote: > >>>> On Wed, Apr 1, 2026 at 11:14=E2=80=AFAM Jan Beulich wrote: > >>>>> On 01.04.2026 09:13, Mykola Kvach wrote: > >>>>>> On Wed, Apr 1, 2026 at 9:29=E2=80=AFAM Jan Beulich wrote: > >>>>>>> On 31.03.2026 20:31, Mykola Kvach wrote: > >>>>>>>> From: Mykola Kvach > >>>>>>>> > >>>>>>>> SMCCC DEN0028G, section 3.1, states that for AArch64 SMC/HVC cal= ls > >>>>>>>> using Wn, only the least significant 32 bits are significant and= the > >>>>>>>> upper 32 bits must be ignored by the implementation. > >>>>>>>> > >>>>>>>> So for SMC32 PSCI calls, Xen must not treat non-zero upper bits = in the > >>>>>>>> argument registers as an error. Instead, they should be discarde= d when > >>>>>>>> decoding the arguments. > >>>>>>>> > >>>>>>>> Arm ARM DDI 0487J.a (D1-5406) also notes that the upper 32 bits = may be > >>>>>>>> implementation defined when entering from AArch32. Xen zeros the= m on > >>>>>>>> entry, but that guarantee is only relevant for 32-bit domains. > >>>>>>>> > >>>>>>>> Update PSCI v0.2+ CPU_ON, CPU_SUSPEND, AFFINITY_INFO and SYSTEM_= SUSPEND > >>>>>>>> to read SMC32 arguments via PSCI_ARG32(), while keeping the SMC6= 4 > >>>>>>>> handling unchanged. > >>>>>>>> > >>>>>>>> No functional change is intended for PSCI 0.1. > >>>>>>>> > >>>>>>>> Suggested-by: Julien Grall > >>>>>>>> Signed-off-by: Mykola Kvach > >>>>>>>> Reviewed-by: Bertrand Marquis > >>>>>>> > >>>>>>> I thought I might as well include this in my next commit sweep, b= ut isn't > >>>>>>> this R-b being invalidated by ... > >>>>>>> > >>>>>>>> --- > >>>>>>>> v3: > >>>>>>>> - use PSCI_ARG_CONV for SYSTEM_SUSPEND > >>>>>>> > >>>>>>> ... this change. That's ... > >>>>>>> > >>>>>>>> @@ -422,14 +427,8 @@ bool do_vpsci_0_2_call(struct cpu_user_regs= *regs, uint32_t fid) > >>>>>>>> case PSCI_1_0_FN32_SYSTEM_SUSPEND: > >>>>>>>> case PSCI_1_0_FN64_SYSTEM_SUSPEND: > >>>>>>>> { > >>>>>>>> - register_t epoint =3D PSCI_ARG(regs, 1); > >>>>>>>> - register_t cid =3D PSCI_ARG(regs, 2); > >>>>>>>> - > >>>>>>>> - if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND ) > >>>>>>>> - { > >>>>>>>> - epoint &=3D GENMASK(31, 0); > >>>>>>>> - cid &=3D GENMASK(31, 0); > >>>>>>>> - } > >>>>>>>> + register_t epoint =3D PSCI_ARG_CONV(regs, 1, is_conv_64= ); > >>>>>>>> + register_t cid =3D PSCI_ARG_CONV(regs, 2, is_conv_64); > >>>>>>>> > >>>>>>>> perfc_incr(vpsci_system_suspend); > >>>>>>>> PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint,= cid)); > >>>>>>> > >>>>>>> ... this hunk aiui, which is far from merely cosmetic imo. While > >>>>>> > >>>>>> Nobody said that the change had to be purely cosmetic in order to = keep > >>>>>> the tag. I understood it differently from the official Xen > >>>>>> documentation pages. > >>>>>> > >>>>>>> behavior looks to remain the same for PSCI_1_0_FN32_SYSTEM_SUSPEN= D, it > >>>>>> > >>>>>> Exactly. If the changes are not substantial, I do not see a reason= to > >>>>>> drop the tag ... > >>>>>> > >>>>>>> clearly changes for PSCI_1_0_FN64_SYSTEM_SUSPEND. That may be int= ended > >>>>>>> and for the better, but the change clearly wasn't reviewed by Ber= trand, > >>>>>>> nor - when offering the R-b - did he ask for this extra change. > >>>>>> > >>>>>> ... and this is also how I understood the Xen patch submission > >>>>>> guidelines [1], which say: > >>>>>> > >>>>>> "Note that if there are several revisions of a patch, you ought to > >>>>>> copy tags that have accumulated during the review. For example, if > >>>>>> person A and person B added a Reviewed-by: tag to v1 of your patch= , > >>>>>> include it into v2 of your patch. If you make substantial changes > >>>>>> after certain tags were already applied, you will want to consider > >>>>>> which ones are no longer applicable (and may require re-providing)= ." > >>>>>> > >>>>>> So my understanding was that tags should normally be kept across > >>>>>> revisions, unless the changes are substantial enough to make them = no > >>>>>> longer applicable. > >>>>> > >>>>> Maybe our understanding of "substantial" differs. To me that's anyt= hing > >>>>> changing functionality. Style adjustments, typo corrections, and al= ike > >>>>> generally aren't substantial (albeit even then there may be excepti= ons). > >>>> > >>>> Thanks for clarifying what you consider substantial. > >>>> > >>>> Even under that interpretation, I do not see a functionality change > >>>> here. "Refactoring" seems like the more accurate term in this case: > >>>> the internal form changes, but the intended external behavior does > >>>> not. > >>>> > >>>> It may be that we are using "functional change" in slightly differen= t > >>>> senses here. > >>>> > >>>> For v3, the switch to PSCI_ARG_CONV() in SYSTEM_SUSPEND was meant to > >>>> make this case consistent with the helper-based argument decoding us= ed > >>>> elsewhere, not to change behavior. > >>>> > >>>> In particular, I do not see a functional change for > >>>> PSCI_1_0_FN64_SYSTEM_SUSPEND: v2 used PSCI_ARG(regs, 1/2), and in v3 > >>>> PSCI_ARG_CONV(regs, 1/2, is_conv_64) should resolve to the same thin= g > >>>> when is_conv_64 is true. > >>> > >>> Isn't the whole point of the patch to alter behavior when is_conv_64 = is > >>> false? For that case PSCI_1_0_FN64_SYSTEM_SUSPEND behavior looks to > >>> change in v3, when it didn't in v2. Whereas for > >>> PSCI_1_0_FN32_SYSTEM_SUSPEND the v3 change indeed only eliminates ope= n- > >>> coding, which one may or may not regard as "substantial". > >> > >> I think the point I was trying to make is slightly narrower: in this > >> code path, is_conv_64 is derived directly from fid via > >> smccc_is_conv_64(fid) before the switch (fid). > >> > >> So for PSCI_1_0_FN64_SYSTEM_SUSPEND, I do not see how > >> is_conv_64 =3D=3D false could arise here: if we are in the FN64 case, > >> the function ID already encodes the 64-bit convention. > >> > >> Conversely, if is_conv_64 is false here, then this cannot be the > >> FN64 case. > > > > Ah, I see. To figure that out, I would have had to do a proper review. = I > > was after committing only, which ought to be an entirely mechanical ste= p. > > > >> On that basis, I do not see a behavioral change for the FN64 > >> SYSTEM_SUSPEND case in v3. > > > > I agree (now). I'm still not going to pick up that patch, but rather > > leave it to the Arm maintainers. While not as clear cut as it first > > seemed to me, I still consider it within the grey area. > > Sorry for the delay, this felt through in my filters as it was reviewed-b= y already. > > I am ok with the changes done which make sense (mask is now done > directly). > > Reviewed-by: Bertrand Marquis Thank you for taking another look. With your Reviewed-by in place, and since I do not expect any further changes from my side, I believe this patch should now be ready for the Arm maintainers to pick up. Best regards, Mykola > > Cheers > Bertrand > > > > > Jan > > From xen-devel-bounces@lists.xenproject.org Thu Apr 23 06:02:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 06:02:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291561.1570438 (Exim 4.92) (envelope-from ) id 1wFn8v-0000An-Dc; Thu, 23 Apr 2026 06:02:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291561.1570438; Thu, 23 Apr 2026 06:02:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFn8v-0000Ag-AX; Thu, 23 Apr 2026 06:02:29 +0000 Received: by outflank-mailman (input) for mailman id 1291561; Thu, 23 Apr 2026 06:02:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFn8t-0000Aa-OE for xen-devel@lists.xenproject.org; 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Wed, 22 Apr 2026 23:02:25 -0700 (PDT) MIME-Version: 1.0 References: <7c20230fcd388ebe398ce19a21a1cd3c2c73d5fa.1775839987.git.mykola_kvach@epam.com> <9cd3e2f1-1b6f-4946-86c2-ff72f34ba138@amd.com> In-Reply-To: <9cd3e2f1-1b6f-4946-86c2-ff72f34ba138@amd.com> From: Mykola Kvach Date: Thu, 23 Apr 2026 09:02:14 +0300 X-Gm-Features: AQROBzCNmduihI4PEKZsBSneyCVeFzRWeRZvzdf9Oyv5svjzLUrGsGIoBl9eQsg Message-ID: Subject: Re: [PATCH v2] arm/gicv3: Decode cacheability fields before comparing To: "Orzel, Michal" Cc: xen-devel@lists.xenproject.org, Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Mykyta Poturai Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1776924146-2B979C48-5202E71C/0/0 X-purgate-type: clean X-purgate-size: 4396 Hi Michal, Thank you for the review. On Mon, Apr 13, 2026 at 12:28=E2=80=AFPM Orzel, Michal wrote: > > > > On 10/04/2026 19:34, Mykola Kvach wrote: > > From: Mykola Kvach > > > > GITS_BASER_INNER_CACHEABILITY_MASK and > > GICR_PROPBASER_INNER_CACHEABILITY_MASK are shifted masks. Comparing the > > masked but unshifted values against GIC_BASER_CACHE_nC, which is an > > unshifted enum value, leads to incorrect detection of non-cacheable > > GITS_CBASER command queue, GITS_BASER tables, and GICR_PROPBASER > > mappings. > > > > Use MASK_EXTR() to decode these cacheability fields before comparing > > against GIC_BASER_CACHE_nC, so the backing memory is flushed when > > required. > > > > Fixes: 8ed8d21373be ("ARM: GICv3 ITS: map ITS command buffer") > > Fixes: 05238012b86d ("ARM: GICv3 ITS: allocate device and collection ta= ble") > > Fixes: c9b939863c89 ("ARM: GICv3: allocate LPI pending and property tab= le") > > Signed-off-by: Mykyta Poturai > > Signed-off-by: Mykola Kvach > > --- > > Changes in v2: > > - use MASK_EXTR() instead of open-coding the BASER field shift > > - fix the analogous PROPBASER cacheability comparison in > > gicv3_lpi_set_proptable() > > - fix the CBASER command queue cacheability check as well > > --- > > xen/arch/arm/gic-v3-its.c | 6 ++++-- > > xen/arch/arm/gic-v3-lpi.c | 3 ++- > > 2 files changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > > index 9ba068c46f..e87465d2ff 100644 > > --- a/xen/arch/arm/gic-v3-its.c > > +++ b/xen/arch/arm/gic-v3-its.c > > @@ -424,7 +424,8 @@ static void *its_map_cbaser(struct host_its *its) > > * If the command queue memory is mapped as uncached, we need to f= lush > > * it on every access. > > */ > > - if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) > You don't seem to mention this change. This one does not compare to > GIC_BASER_CACHE_nC and checks against 0, which means we are on the safe s= ide. If > you still want to change it, then you should also look few lines above wh= ere we > have: > if ( (reg & GITS_BASER_SHAREABILITY_MASK) =3D=3D 0 ) > > > + if ( MASK_EXTR(reg, GITS_BASER_INNER_CACHEABILITY_MASK) <=3D > > + GIC_BASER_CACHE_nC ) > This is a functional change. Previously we where comparing against 0 and = now you > compare against <=3D 1 You are right, the CBASER hunk is not fixing the same shifted-mask comparison bug as the BASER/PROPBASER hunks. My intention was to also handle InnerCache =3D=3D 0b001, which is Normal Inner Non-cacheable, so the command queue should need flushing in that case as well. I agree this is a separate functional change. I will drop the CBASER hunk from this patch to keep it focused on the BASER/PROPBASER shifted-mask fix. I will send the CBASER change separately with a dedicated explanation. Best regards, Mykola > > ~Michal > > > { > > its->flags |=3D HOST_ITS_FLUSH_CMD_QUEUE; > > printk(XENLOG_WARNING "using non-cacheable ITS command queue\n= "); > > @@ -496,7 +497,8 @@ retry: > > } > > attr =3D regc & BASER_ATTR_MASK; > > } > > - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER_CA= CHE_nC ) > > + if ( MASK_EXTR(regc, GITS_BASER_INNER_CACHEABILITY_MASK) <=3D > > + GIC_BASER_CACHE_nC ) > > clean_and_invalidate_dcache_va_range(buffer, table_size); > > > > /* If the host accepted our page size, we are done. */ > > diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c > > index de5052e5cf..9ee338edc2 100644 > > --- a/xen/arch/arm/gic-v3-lpi.c > > +++ b/xen/arch/arm/gic-v3-lpi.c > > @@ -351,7 +351,8 @@ static int gicv3_lpi_set_proptable(void __iomem * r= dist_base) > > } > > > > /* Remember that we have to flush the property table if non-cachea= ble. */ > > - if ( (reg & GICR_PROPBASER_INNER_CACHEABILITY_MASK) <=3D GIC_BASER= _CACHE_nC ) > > + if ( MASK_EXTR(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK) <=3D > > + GIC_BASER_CACHE_nC ) > > { > > lpi_data.flags |=3D LPI_PROPTABLE_NEEDS_FLUSHING; > > /* Update the redistributors knowledge about the attributes. *= / > From xen-devel-bounces@lists.xenproject.org Thu Apr 23 06:21:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 06:21:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291095.1570456 (Exim 4.92) (envelope-from ) id 1wFnRI-0004Gj-H4; Thu, 23 Apr 2026 06:21:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291095.1570456; Thu, 23 Apr 2026 06:21:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFnRI-0004F0-BW; Thu, 23 Apr 2026 06:21:28 +0000 Received: by outflank-mailman (input) for mailman id 1291095; Wed, 22 Apr 2026 20:08:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFdsA-0007sT-Sp for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 20:08:36 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFdsA-008j3F-61 for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 22:08:34 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e92ab5-2eae-0a2a0a5409dd-0a2a4503e434-14 for ; Wed, 22 Apr 2026 22:08:34 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e92abf-672d-0a2a45030019-d561b3388958-3 for ; Wed, 22 Apr 2026 22:08:32 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wFdrj-000QN6-Os; Wed, 22 Apr 2026 22:08:07 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:Content-Transfer-Encoding:Content-Type:MIME-Version: Message-Id:Date:Subject:From:Sender:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=fOcKShGpyamYd19c2wC1bpR06ZCKPaumZuCXRyi0A2k=; b=WCjRkL064rCYl0/d/6M6kNKAwK qbbjwO6GJiq1i+9WUkZ4U5PPwSVlVII+oSEVdi0oixTOxG15dArpwdMl4PWTAfLGuJAv2h6aUnjYg Qo928sjxfInUKrtFZ4k61psYYigIJuJD+Rb1YTE9F88lwX0geRJTlWe5BAbigLh6zs79CIpmriXki /cll629FxBfJ40wBfx4tQBGG5hDsepJxIZYEkDXUUNfvp6IZD/45rEE5A3jmegFFn1vlbkmLHRnj1 o8tYO4CHVtspI2ssvKbEZPf/bO7FX7vQkwPLWxKd7DwFfGHr01ONcqSHvJHYR4Qz5dDWlTSq4yx6z ccoLukYg==; From: Mauricio Faria de Oliveira Subject: [PATCH 0/3] x86/pvh: fix unbootable VMs again (PVH + KASAN) Date: Wed, 22 Apr 2026 17:07:44 -0300 Message-Id: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJAq6WkC/x3MMQqAMAxA0atIZgMaxIJXEYeoqQYllhaKIN7d4 viG/x9IElUSDNUDUbImvaygrStYdrZNUNdioIb6piPCkHc8OLGh2qkm2IvnxTnfzuSgZCGK1/t fjtP7frOSTJRiAAAA X-Change-ID: 20260422-pvh-kasan-inline-6efac77f1b27 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-33051d/1776888513-A3161938-613DC583/0/0 X-purgate-type: clean X-purgate-size: 5364 The issue of unbootable VMs with CONFIG_PVH due to CONFIG_KASAN is back. Booting directly from vmlinux (instead of bzImage) now fails with gcc-14/15 (but works with gcc-12/13) if CONFIG_KASAN_GENERIC is set, on Ubuntu 25.10. The PVH code is required/supposed not to hit the KASAN memory access check in the kernel entry point as KASAN has not yet been setup, or an exception is hit and the boot fails. This was previously described and addressed with __builtin_mem{cmp,set}(): - commit 661362e3dcab ("xen, pvh: fix unbootable VMs (PVH + KASAN - AMD_MEM_ENCRYPT)") - commit 416a33c9afce ("x86/cpu: fix unbootable VMs by inlining memcmp() in hypervisor_cpuid_base()") - commit fbe5a6dfe492 ("xen, pvh: fix unbootable VMs by inlining memset() in xen_prepare_pvh()") However, even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. So, that does not really fix the issue unconditionally, as it's being seen (details below). In order to address this, it's required to switch to inline implementations that do not depend on the compiler. There's such a memset in and memcmp in 'boot/string.c', now exposed in too. Use them instead of builtins in PVH entry. Testing: - Booting from vmlinux (fixed) and bzImage (still works) using allnoconfig + CONFIG_PVH + CONFIG_KASAN with gcc-12/13/14/15. - Building allyesconfig (check for issues with ). Details/Debugging: - Only CONFIG_PVH (works): make allnoconfig ./scripts/config \ -e 64BIT -e HYPERVISOR_GUEST -e PVH \ -e SERIAL_8250 -e SERIAL_8250_CONSOLE make olddefconfig make -j$(nproc) vmlinux qemu-system-x86_64 \ -accel kvm -nodefaults -nographic -serial stdio \ -kernel vmlinux -append 'console=ttyS0' ... SeaBIOS (version ...) Booting from ROM... Linux version ... ... - With CONFIG_KASAN (fails) ./scripts/config -e KASAN make olddefconfig make -j$(nproc) vmlinux qemu-system-x86_64 \ -accel kvm -nodefaults -nographic -serial stdio \ -kernel vmlinux -append 'console=ttyS0' ... SeaBIOS (version ...) Booting from ROM... - Debugging: Enable debug info and rebuild. QEMU: enable and wait for GDB, stop rebooting, remain running. qemu-system-x86_64 \ -s -S -no-reboot -no-shutdown \ gdb vmlinux (gdb) target remote localhost:1234 ... (gdb) c ... Thread 2 received signal SIGQUIT, Quit. ... (gdb) info threads Id Target Id Frame 1 Thread 1.1 (CPU#0 [running]) bytes_is_nonzero ( start=0xfffffbfff031eebe , size=1) at .../linux/mm/kasan/generic.c:98 * 2 Thread 1.2 (CPU#1 [halted ]) 0x00000000000fd0a9 in ?? () ... (gdb) thr 1 ... (gdb) bt #0 bytes_is_nonzero (start=0xfffffbfff031eebe , size=1) at .../linux/mm/kasan/generic.c:98 #1 memory_is_nonzero (start=0xfffffbfff031eebe, end=0xfffffbfff031eebf) at .../linux/mm/kasan/generic.c:115 #2 memory_is_poisoned_n (addr=0xffffffff818f75f0, size=8) at .../linux/mm/kasan/generic.c:140 #3 memory_is_poisoned (addr=0xffffffff818f75f0, size=8) at .../linux/mm/kasan/generic.c:172 #4 check_region_inline (addr=0xffffffff818f75f0, size=8, write=false, ret_ip=18446744071585002062) at .../linux/mm/kasan/generic.c:191 #5 kasan_check_range (addr=addr@entry=0xffffffff818f75f0, size=size@entry=8, write=write@entry=false, ret_ip=18446744071585002062) at .../linux/mm/kasan/generic.c:200 #6 0xffffffff813eb283 in __asan_loadN (addr=addr@entry=0xffffffff818f75f0, size=size@entry=8) at .../linux/mm/kasan/generic.c:278 #7 0xffffffff815df24e in memcmp (cs=cs@entry=0xffffffff818f75f0, ct=ct@entry=0x1be2fe4, count=, count@entry=12) at .../linux/lib/string.c:683 #8 0xffffffff81ba2323 in cpuid_base_hypervisor (sig=0xffffffff818f75f0 "XenVMMXenVMM", leaves=2) at .../linux/arch/x86/include/asm/cpuid/api.h:206 #9 xen_cpuid_base () at .../linux/arch/x86/include/asm/xen/hypervisor.h:46 #10 xen_prepare_pvh () at .../linux/arch/x86/platform/pvh/enlighten.c:119 #11 0x0000000001ba2588 in ?? () #12 0x0000000000000000 in ?? () (gdb) Frames #7-#8 show the non-builtin memcmp() (lib/string.c) was called even with __builtin_memcmp() being used in cpuid_base_hypervisor(). Signed-off-by: Mauricio Faria de Oliveira --- Mauricio Faria de Oliveira (3): x86/asm, x86/boot: Expose inline memcmp x86/cpuid: fix unbootable VMs by really inlining memcmp() in hypervisor_cpuid_base() x86/pvh: fix unbootable VMs by really inlining memset() in xen_prepare_pvh() arch/x86/boot/string.c | 6 ++---- arch/x86/include/asm/cpuid/api.h | 2 +- arch/x86/include/asm/string.h | 11 +++++++++++ arch/x86/platform/pvh/enlighten.c | 3 ++- 4 files changed, 16 insertions(+), 6 deletions(-) --- base-commit: 6596a02b207886e9e00bb0161c7fd59fea53c081 change-id: 20260422-pvh-kasan-inline-6efac77f1b27 Best regards, -- Mauricio Faria de Oliveira From xen-devel-bounces@lists.xenproject.org Thu Apr 23 06:21:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 06:21:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291094.1570450 (Exim 4.92) (envelope-from ) id 1wFnRI-0004BT-7b; Thu, 23 Apr 2026 06:21:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291094.1570450; Thu, 23 Apr 2026 06:21:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFnRI-0004BJ-4f; Thu, 23 Apr 2026 06:21:28 +0000 Received: by outflank-mailman (input) for mailman id 1291094; Wed, 22 Apr 2026 20:08:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFdsB-0007sW-Uv for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 20:08:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFdsB-008IiL-Bq for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 22:08:35 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e92ac1-2eae-0a2a0a5409dd-0a2a4507c2ea-6 for ; Wed, 22 Apr 2026 22:08:35 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e92ac2-229c-0a2a45070019-d561b338b3d2-3 for ; Wed, 22 Apr 2026 22:08:35 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wFdrw-000QN6-VY; Wed, 22 Apr 2026 22:08:20 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=ugLYSHBb5Q9RwOF8EB3ofOp/JXnqmVAR7KYDCMKM5ok=; b=eA7Kx7ySJ0fQcyxXseR3wwYRQu BaEOoFBaNOeh2tfFgcRa50/ij6NjkDTNHHLPE/MI4ZVUjkoRfNxSHFT67t5yp85A1LceddlEU1pgW xktLdlpLLYEu6lKePNxiWQb5UERyLw64kBiutUmbe3ozGTvFOf1C3nsFc2RKL6wnDxtMhbooPjHey OE1+WLBHxqaAOcceUEPEgpjPgilanir0vWxXJ1ZR2lw0UHtCgaK7Fs7+6lhmZejMVzzuJCtPq5bcN PDxEaalcmUl8q1AYY5W10ZTFDQ4HUSsdZbRGOohFirJk5AE4JeizDZRrtyCwdzA3WDpFQJvqwi9J0 0siPg/ow==; From: Mauricio Faria de Oliveira Date: Wed, 22 Apr 2026 17:07:47 -0300 Subject: [PATCH 3/3] x86/pvh: fix unbootable VMs by really inlining memset() in xen_prepare_pvh() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260422-pvh-kasan-inline-v1-3-7e6194344c92@igalia.com> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> In-Reply-To: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-ef75cf/1776888515-AC961C48-D89686DA/0/0 X-purgate-type: clean X-purgate-size: 1428 Even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. This particular one (still) generated the inline implementation as expected (at least in these compiler versions), but this is not guaranteed to remain the case, as seen with the previous commit. Switch the builtin to the inline implementation to prevent a similar issue. Fixes: fbe5a6dfe492 ("xen, pvh: fix unbootable VMs by inlining memset() in xen_prepare_pvh()") Signed-off-by: Mauricio Faria de Oliveira --- arch/x86/platform/pvh/enlighten.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/platform/pvh/enlighten.c b/arch/x86/platform/pvh/enlighten.c index f2053cbe9b0ce3d2178938269607c652ae8f528e..cb442cbd9d828619421babb281bfe9759edbca8a 100644 --- a/arch/x86/platform/pvh/enlighten.c +++ b/arch/x86/platform/pvh/enlighten.c @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -129,7 +130,7 @@ void __init xen_prepare_pvh(void) * This must not compile to "call memset" because memset() may be * instrumented. */ - __builtin_memset(&pvh_bootparams, 0, sizeof(pvh_bootparams)); + __inline_memset(&pvh_bootparams, 0, sizeof(pvh_bootparams)); hypervisor_specific_init(xen_guest); -- 2.51.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 06:21:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 06:21:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291093.1570446 (Exim 4.92) (envelope-from ) id 1wFnRI-00048N-0r; Thu, 23 Apr 2026 06:21:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291093.1570446; Thu, 23 Apr 2026 06:21:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFnRH-00048G-Tm; Thu, 23 Apr 2026 06:21:27 +0000 Received: by outflank-mailman (input) for mailman id 1291093; Wed, 22 Apr 2026 20:08:35 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFdsA-0007sU-TR for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 20:08:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFdsA-001TrF-6p for xen-devel@lists.xenproject.org; Wed, 22 Apr 2026 22:08:34 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e92aa5-bab6-0a2a0a5309dd-0a2a450ca2b4-20 for ; Wed, 22 Apr 2026 22:08:34 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e92ac0-62f1-0a2a450c0019-d561b338b1ee-3 for ; Wed, 22 Apr 2026 22:08:33 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wFdro-000QN6-2I; Wed, 22 Apr 2026 22:08:11 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=CG+f99gT7Cze+FGPfBLcF87S5O/36isH7njf38xR63Q=; b=OKwd6A5xLH1bJcdBLDOnv8XZ2i lWl1UWUVu3h86BrLtoFeWCBfpU2bihQEf8FeBcOQ56n6T2kTO/ZzQUVxOh60BnBY8zmH4WsOo9sj2 pj1egl1mFkGBZBpZjIrH6aFWFOXTkaJNPiNANr8YsKfqigBdRd3T9/vUw8gN8237zaR//pMRs3Aaw VocJZgfgNK8hun7DHMiw8Y1CSA9E1pK4stZ9xNZkDaLwX+fuBeO+TdkzZwpK5qP8ojYf4hbMqpRir CmX0EGP6b5coLgijMwibBWxbpOAG/HMpmCvfk0rdAWbiuJqQjaebumMcZrYfQB7G1OFqOqKt1X4HB i0BgXmbA==; From: Mauricio Faria de Oliveira Date: Wed, 22 Apr 2026 17:07:45 -0300 Subject: [PATCH 1/3] x86/asm, x86/boot: Expose inline memcmp MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260422-pvh-kasan-inline-v1-1-7e6194344c92@igalia.com> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> In-Reply-To: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-d25034/1776888514-6E776CF5-316B6DE4/0/0 X-purgate-type: clean X-purgate-size: 2108 Move the inline memcmp function, currently only available to boot code (boot/string.c), into the header with similar inline string functions (include/asm/string.h) so it may be reused. Add a _SETUP guard in string.h so not to include the 32/64-bit specific string headers in boot/ code (16-bit, real mode) and avoid build errors. Signed-off-by: Mauricio Faria de Oliveira --- arch/x86/boot/string.c | 6 ++---- arch/x86/include/asm/string.h | 11 +++++++++++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c index b25c6a9303b7314d5caf5c9306239811705294fe..bbee78637b349e42e9281d8df50d89d48f4490b9 100644 --- a/arch/x86/boot/string.c +++ b/arch/x86/boot/string.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "ctype.h" #include "string.h" @@ -31,10 +32,7 @@ int memcmp(const void *s1, const void *s2, size_t len) { - bool diff; - asm("repe cmpsb" - : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); - return diff; + return __inline_memcmp(s1, s2, len); } /* diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 9cb5aae7fba9ffcf0f5af8f939d30467750ccaa9..736a6f6a31f0a68281b4f17415aba0fcd95dc228 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -2,11 +2,13 @@ #ifndef _ASM_X86_STRING_H #define _ASM_X86_STRING_H +#ifndef _SETUP #ifdef CONFIG_X86_32 # include #else # include #endif +#endif static __always_inline void *__inline_memcpy(void *to, const void *from, size_t len) { @@ -29,4 +31,13 @@ static __always_inline void *__inline_memset(void *s, int v, size_t n) return ret; } +static __always_inline int __inline_memcmp(const void *s1, const void *s2, size_t len) +{ + bool diff; + + asm("repe cmpsb" + : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); + return diff; +} + #endif /* _ASM_X86_STRING_H */ -- 2.51.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 06:21:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 06:21:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291096.1570463 (Exim 4.92) (envelope-from ) id 1wFnRI-0004LE-Nc; Thu, 23 Apr 2026 06:21:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291096.1570463; Thu, 23 Apr 2026 06:21:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFnRI-0004Is-J6; Thu, 23 Apr 2026 06:21:28 +0000 Received: by outflank-mailman (input) for mailman id 1291096; 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From: Mauricio Faria de Oliveira Date: Wed, 22 Apr 2026 17:07:46 -0300 Subject: [PATCH 2/3] x86/cpuid: fix unbootable VMs by really inlining memcmp() in hypervisor_cpuid_base() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260422-pvh-kasan-inline-v1-2-7e6194344c92@igalia.com> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> In-Reply-To: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-33051d/1776888513-A1D7B938-99EF6E98/0/0 X-purgate-type: clean X-purgate-size: 1412 Even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. The existing code is broken with gcc-14/15 but not gcc-12/13 (Ubuntu 25.10) and vmlinux no longer boots with CONFIG_PVH if CONFIG_KASAN_GENERIC is set. For testing purposes, if the size argument is reduced from 12 to 8 then the compiler decides to use the inline implementation; that shows results vary. Switch the builtin to the inline implementation to address it. Fixes: 416a33c9afce ("x86/cpu: fix unbootable VMs by inlining memcmp() in hypervisor_cpuid_base()") Signed-off-by: Mauricio Faria de Oliveira --- arch/x86/include/asm/cpuid/api.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h index 44fa82e1267ce98c7f5f92f69b58f79e235f7261..c3bd1e51067346e817240b484dc0d0e5f02dcc4f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -203,7 +203,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves) * from PVH early boot code before instrumentation is set up * and memcmp() itself may be instrumented. */ - if (!__builtin_memcmp(sig, signature, 12) && + if (!__inline_memcmp(sig, signature, 12) && (leaves == 0 || ((eax - base) >= leaves))) return base; } -- 2.51.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 07:04:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 07:04:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291616.1570482 (Exim 4.92) (envelope-from ) id 1wFo7A-0006iV-Qc; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +rtKFzmECy7qsGsOapfbHuQyq5I2Kc3g/WnSADp5rIGQLsx0Z0RjJsrluwi+v0PjL6HnInO6CsBmyAhe8zyOAaJtF9VCKqkhnoNb0QTmBo4YS1zw2mg9cPyOFGIpnrzGLwzUeZDUfOfD9P5SVnQFfYotqCZf0GWUmfYoCRCcsoNqC1FHBIx4g+lM89VqHcRc2SpGUi1cwJcZ2qE14mifYgekZOFDfrgL21NCPpfR5zB9hFQrA3fzbzgH6oqMox/o+4fXMzG6qCOmkFSsbmRUmA9na3ZwXICogiCJ0OBeGzMdj/ZC2VeQwxp7RUnzu2lFI4PjjBhR6FsmdrDsue/GpIDrz/ScR++bhViKyzjJqensAS6JQtPyceyQljXHCVVJn5d77vyUQmgBjLpPeE3NSFlFNt7m3z6uuu5v8MY3YljsWKOh0zbsR9Ky5LFVtYAI X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:04:33.7731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50547a52-443b-4721-1c35-08dea10692ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.55.251];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8784 X-purgate-ID: tlsNG-33051d/1776927881-2A766938-17B3421E/0/0 X-purgate-type: clean X-purgate-size: 1374 On 27/02/2026 07:50, Jan Beulich wrote: > On 26.02.2026 18:14, Andrew Cooper wrote: >> On 26/02/2026 4:28 pm, Jan Beulich wrote: >>> --- a/xen/arch/arm/Makefile >>> +++ b/xen/arch/arm/Makefile >>> @@ -15,7 +15,9 @@ obj-$(CONFIG_HAS_ALTERNATIVE) += alterna >>> obj-y += cpuerrata.o >>> obj-y += cpufeature.o >>> obj-y += decode.o >>> -obj-y += device.o >>> +device-y := device.init.o >>> +device-$(CONFIG_OVERLAY_DTB) := device.o >>> +obj-y += $(device-y) >> >> I know we've argued over this before and not come to a conclusion, but I >> still firmly believe this to be an anti-pattern we should expunge. >> >> obj-y += $(if $(CONFIG_OVERLAY_DTB),device.o,device.init.o) > > Whereas I think this one (in its adjusted form to really only accept 'y') > is, firmly believing that the "lists everywhere" approach is the more > readable and, more importantly, more scalable one. The form you suggest > quickly gets to its limits when multiple CONFIG_* need dealing with. I must admit that I prefer Andrew approach. It took me less time to understand what the line does compared to your solution. I don't want to get involved in a discussion about consistency here (for me we can use both depending on number of CONFIG_ options), but with the line changed to what Andrew suggests: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 23 07:30:18 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 07:30:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291634.1570491 (Exim 4.92) (envelope-from ) id 1wFoVo-0003Iy-QD; Thu, 23 Apr 2026 07:30:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291634.1570491; Thu, 23 Apr 2026 07:30:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFoVo-0003Ir-NN; Thu, 23 Apr 2026 07:30:12 +0000 Received: by outflank-mailman (input) for mailman id 1291634; Thu, 23 Apr 2026 07:30:12 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ff87A9wlcgNGHmL1pv/O40m9siU+aIWxOq1j+ZJH3W+h0Qy9DaqUGY3iwfIZlyfgHy44hCslYru IICH7J7CgAY/vGYemcZ8oy0nlDcz5zXXF+hmScMSWIKeG7Z12VqszxCCwENB0qg7GLHKMJO1Xeu uJjRWC9TDTrqogbsiqF42w2HRZPSLLB/r1mxe1LauGMU9Rl6hKKJhf19Z5PdiX00uEXwM+93mTr lmcqjx8653W+5vzwJ8X83y2TJoP4WJD/CZflwzNGT9pA== X-Zone-Loop: d3851645cb241673af1114c93b68980cf4cb5268568b x-campaign-type: default x-transaction-id: 0bd0b6ba-738f-4205-b0b9-758db9041adf x-swg-uid: 01-fcc5ed98-0882-498a-90a8-e7fca6a33735 X-Mailer: Sweego Message-ID: <1776929646.8631fc262581453bbf619ec5b2062170.19db942a614000f373@vates.tech> x-swg-bid: 1776929646.8631fc262581453bbf619ec5b2062170.19db942a614000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 23 Apr 2026 09:34:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 2/2] vtd: Replace macros with bitfield To: Jan Beulich Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <815edfd0db90859a4ce270d833d9d721ff66e31c.1775814143.git.teddy.astie@vates.tech> <3182da144d0cb998c9ae897b55285b7e408cd972.1775814143.git.teddy.astie@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2641.95305ad117c55529.19db942a372.78ef5b47f81d8135=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776929645426 X-purgate-ID: tlsNG-720697/1776929647-8137C161-C1214151/0/0 X-purgate-type: clean X-purgate-size: 3044 ---=Part.2641.95305ad117c55529.19db942a372.78ef5b47f81d8135=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 20/04/2026 =C3=A0 15:54, Jan Beulich a =C3=A9crit=C2=A0: > On 10=2E04=2E2026 12:09, Teddy Astie wrote: >> Replace macros with bitfield to allow simplyfing the code and be >> less error prone when manipulating PTEs=2E >> >> It also has the effect of directly exposing the mfn in the pte struct >> instead of derivating it from the raw pte value using dma_pte_addr()=2E >> >> Signed-off-by: Teddy Astie >> --- >> It allows nicer constructs like >> >> new=2Esnp =3D iommu_snoop; >> >> instead of >> >> if ( iommu_snoop ) >> dma_set_pte_snp(new); >> >> A lot of simplifications could be done afterward when switching the >> logic from maddrs to mfns i=2Ee remove many maddr-mfn conversions=2E >=20 > There's no real open question here, so it's not quite clear why this is > marked RFC=2E We did do the same on the AMD side a while back, at least > partly (I don't think we got all of it converted yet), so doing the > conversion here surely is a good thing=2E The slightly larger =2E=2E=2E >=20 >> bloat-o-meter (along with the previous change) >> >> add/remove: 0/0 grow/shrink: 7/3 up/down: 227/-45 (182) >> Function old new delta >> addr_to_dma_page_maddr 949 1058 +109 >> vtd_dump_page_table_level 197 233 +36 >> fill_qpt 1151 1178 +27 >> print_vtd_entries 486 504 +18 >> domain_context_mapping_one 2098 2114 +16 >> intel_iommu_map_page 909 921 +12 >> intel_iommu_unmap_page 731 740 +9 >> intel_iommu_lookup_page 185 176 -9 >> queue_free_pt 442 425 -17 >> vtd_dump_page_table_level=2Ecold 86 67 -19 >> Total: Before=3D18446744073715636162, After=3D18446744073715636344, chg= +0=2E00% >=20 > =2E=2E=2E code size shouldn't be much of a concern, albeit you may want = to at > least mention the (presumed) reason for some of the bigger increases, > after comparing the generated code=2E >=20 > (As an aside, the two values after Total: look entirely bogus=2E) >=20 >> I guess using mfns 'everywhere' would improve the bloat-o-meter picture= =2E >=20 > It's not quite clear to me what you mean here=2E >=20 There are many mfn<->maddr conversions done at various places which can=20 be eliminated=2E I guess some of the "bloat" is coming from there=2E I may try in another patch to adjust some of the types to make that better= =2E > Jan >=20 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.2641.95305ad117c55529.19db942a372.78ef5b47f81d8135=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 07:38:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 07:38:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291660.1570518 (Exim 4.92) (envelope-from ) id 1wFodk-0006TD-0m; Thu, 23 Apr 2026 07:38:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291660.1570518; Thu, 23 Apr 2026 07:38:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFodj-0006T6-U8; Thu, 23 Apr 2026 07:38:23 +0000 Received: by outflank-mailman (input) for mailman id 1291660; Thu, 23 Apr 2026 07:38:22 +0000 Received: from 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Thu, 23 Apr 2026 08:08:54 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931736; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CPBzawWX2g0dpZag7OUw1T+x+kMtwYFiewTeIGA7K/o=; b=bht6oFQjCvijEG82j7+TrxXWjGaD7mp+mdMIov/n+lxBL47Za6FGF+G2DeJv0kc4g1hXwU wIsx39JIy7PnXyx7dAOoAdc/R2Gs0H6lbb1yIgmnItARlIpJZX5NNHGyP2RDZSSe+JPPIf j+3ek9l4qkwpkJUpmuULoeQIIxxPaxs= Authentication-Results: smtp-out2.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=Qkirx6S0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931735; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CPBzawWX2g0dpZag7OUw1T+x+kMtwYFiewTeIGA7K/o=; b=Qkirx6S0tb+jXp7zMwAk9P/B47ZppVQUjk5pHDIFa9gOKi1rchok6xyGUPpYPhuDy78tbV EIUtUhdqBmCNSBKa9H5blHujl0jRkqUC/DJoc7CKeWBGTlmFUH4ydEY4IDyjnrqvkPbE3P D7hQrwWx+chtG36WrLnCufWz2C69nIo= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Juergen Gross , Anthony PERARD , Julien Grall Subject: [PATCH 2/4] tools/xenstored: add support for "all domains" node permission Date: Thu, 23 Apr 2026 10:08:38 +0200 Message-ID: <20260423080840.530547-3-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423080840.530547-1-jgross@suse.com> References: <20260423080840.530547-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; 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Add a new feature bit for indicating the support of DOMID_ANY. Signed-off-by: Juergen Gross --- docs/man/xl.cfg.5.pod.in | 4 ++++ tools/xenstored/core.c | 19 ++++++++++++++----- tools/xenstored/domain.c | 16 ++++++++++++++-- tools/xenstored/domain.h | 3 ++- xen/include/public/io/xs_wire.h | 2 ++ 5 files changed, 36 insertions(+), 8 deletions(-) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 2f77016ecf..d34951edb9 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -746,6 +746,10 @@ Xenstore supports to set watches with a limited depth (depth 0 matches only the watched node, depth 1 matches the node and its direct children, etc.). +=item B<0x00000008> + +Xenstore supports the B node access permission. + =back The features supported by the running Xenstore instance can be retrieved diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index f92fca6e9e..5a621f53ba 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -882,6 +882,16 @@ static int write_node(struct connection *conn, struct node *node, return ret; } +/* Check one node permission to match a connection. */ +static bool perm_allows_conn(const struct connection *conn, + const struct xs_permissions *p) +{ + if (p->id == conn->id || (conn->target && p->id == conn->target->id)) + return true; + + return p->id == DOMID_ANY; +} + unsigned int perm_for_conn(struct connection *conn, const struct node_perms *perms) { @@ -889,14 +899,13 @@ unsigned int perm_for_conn(struct connection *conn, unsigned int mask = XS_PERM_READ|XS_PERM_WRITE|XS_PERM_OWNER; /* Owners and tools get it all... */ - if (!domain_is_unprivileged(conn) || perms->p[0].id == conn->id - || (conn->target && perms->p[0].id == conn->target->id)) + if (!domain_is_unprivileged(conn) || + perm_allows_conn(conn, perms->p)) return (XS_PERM_READ|XS_PERM_WRITE|XS_PERM_OWNER) & mask; for (i = 1; i < perms->num; i++) if (!(perms->p[i].perms & XS_PERM_IGNORE) && - (perms->p[i].id == conn->id || - (conn->target && perms->p[i].id == conn->target->id))) + perm_allows_conn(conn, perms->p + i)) return perms->p[i].perms & mask; return perms->p[0].perms & mask; @@ -1832,7 +1841,7 @@ static int do_set_perms(const void *ctx, struct connection *conn, if (!xenstore_strings_to_perms(perms.p, perms.num, permstr)) return errno; - if (domain_alloc_permrefs(&perms)) + if (domain_alloc_permrefs(conn, &perms)) return ENOMEM; if (perms.p[0].perms & XS_PERM_IGNORE) return ENOENT; diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index 00875d6b5c..0bd2a1891a 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -44,7 +44,8 @@ #endif #define XENSTORE_FEATURES (XENSTORE_SERVER_FEATURE_ERROR | \ - XENSTORE_SERVER_FEATURE_WATCHDEPTH) + XENSTORE_SERVER_FEATURE_WATCHDEPTH | \ + XENSTORE_SERVER_FEATURE_DOMID_ANY) static xenmanage_handle *xm_handle; xengnttab_handle **xgt_handle; @@ -1754,8 +1755,12 @@ static bool chk_domain_generation(unsigned int domid, uint64_t gen) * Allocate all missing struct domain referenced by a permission set. * Any permission entries for not existing domains will be marked to be * ignored. + * An DOMID_ANY entry will be marked to be ignored, if the writing + * domain doesn't have the XENSTORE_SERVER_FEATURE_DOMID_ANY enabled. Note + * that Xen tools will never set DOMID_ANY for a guest owned node. */ -int domain_alloc_permrefs(struct node_perms *perms) +int domain_alloc_permrefs(const struct connection *conn, + struct node_perms *perms) { unsigned int i, domid; struct domain *d; @@ -1763,6 +1768,12 @@ int domain_alloc_permrefs(struct node_perms *perms) for (i = 0; i < perms->num; i++) { domid = perms->p[i].id; + if (domid == DOMID_ANY) { + if (!(conn->domain->features & + XENSTORE_SERVER_FEATURE_DOMID_ANY)) + perms->p[i].perms |= XS_PERM_IGNORE; + continue; + } d = find_domain_struct(domid); if (!d) { if (xenmanage_get_domain_info(xm_handle, domid, NULL, @@ -1788,6 +1799,7 @@ int domain_adjust_node_perms(struct node *node) for (i = 1; i < node->hdr.num_perms; i++) { if ((perms[i].perms & XS_PERM_IGNORE) || + perms[i].id == DOMID_ANY || chk_domain_generation(perms[i].id, node->hdr.generation)) continue; diff --git a/tools/xenstored/domain.h b/tools/xenstored/domain.h index b1cfb5cd82..7dad4849a0 100644 --- a/tools/xenstored/domain.h +++ b/tools/xenstored/domain.h @@ -116,7 +116,8 @@ const char *get_implicit_path(const struct connection *conn); */ int domain_adjust_node_perms(struct node *node); -int domain_alloc_permrefs(struct node_perms *perms); +int domain_alloc_permrefs(const struct connection *conn, + struct node_perms *perms); /* Quota manipulation */ int domain_nbentry_inc(struct connection *conn, unsigned int domid); diff --git a/xen/include/public/io/xs_wire.h b/xen/include/public/io/xs_wire.h index 2e763bc877..d6533a8452 100644 --- a/xen/include/public/io/xs_wire.h +++ b/xen/include/public/io/xs_wire.h @@ -126,6 +126,8 @@ struct xenstore_domain_interface { #define XENSTORE_SERVER_FEATURE_ERROR 2 /* The XS_WATCH command can be used with a parameter */ #define XENSTORE_SERVER_FEATURE_WATCHDEPTH 4 +/* The capability to use DOMID_ANY for node permissions */ +#define XENSTORE_SERVER_FEATURE_DOMID_ANY 8 /* Valid values for the connection field */ #define XENSTORE_CONNECTED 0 /* the steady-state */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 08:09:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 08:09:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291707.1570554 (Exim 4.92) (envelope-from ) id 1wFp7G-0005mr-8S; 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Signed-off-by: Denis Mukhin Signed-off-by: Juergen Gross --- This is based on Denis Mukhin's patch "xen/domain: introduce DOMID_ANY". As my series is another use case for DOMID_ANY and it is a backport candidate, I've split out the definition of DOMID_ANY from Denis' patch in order to make progress for my series. --- xen/include/public/xen.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index b12fd10e63..f35a6f21f0 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -608,6 +608,13 @@ DEFINE_XEN_GUEST_HANDLE(mmuext_op_t); /* DOMID_INVALID is used to identify pages with unknown owner. */ #define DOMID_INVALID xen_mk_uint(0x7FF4) +/* + * DOMID_ANY is used to signal no specific domain ID requested. + * Handler should pick a valid ID, or handle it as a broadcast value + * depending on the context. + */ +#define DOMID_ANY xen_mk_uint(0x7FF5) + /* Idle domain. */ #define DOMID_IDLE xen_mk_uint(0x7FFF) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 08:09:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 08:09:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291706.1570546 (Exim 4.92) (envelope-from ) id 1wFp7C-0005ZG-1v; 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dkim=pass header.d=suse.com header.s=susede1 header.b=dwG7Y5Wm DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931724; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=W1IJxzbrwQvZUomJgk2VyUnqUajgTY2+LEjFkzuFZnU=; b=dwG7Y5Wmtnqh3PUaooY8fQr/2/J6i8fyMJYHFYLxx7KSrWr7Ao2cVH/tmrDfDKrAhsOPSm IIlaabc247ChEudFQNZQu/wMubS9aWapA39qrZ+CxwcRbWUgS46kP2+Zr/w0hiBSLY2bLh zisKNrt+WQkrP7GHleJRAexp5j1V0+I= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Juergen Gross , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH 0/4] tools/xenstore: fix issue related to XSA-417 Date: Thu, 23 Apr 2026 10:08:36 +0200 Message-ID: <20260423080840.530547-1-jgross@suse.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_DN_SOME(0.00)[]; FROM_HAS_DN(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCPT_COUNT_SEVEN(0.00)[10]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.com:dkim,suse.com:mid]; RCVD_TLS_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DKIM_TRACE(0.00)[suse.com:+] X-Rspamd-Queue-Id: 24EF45BD17 X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: X-purgate-ID: tlsNG-d25034/1776931726-6DD6BCF5-714F34B4/0/0 X-purgate-type: clean X-purgate-size: 2836 There is one corner case of XSA-417 which wasn't handled completely with the patches back then. The XSA-417 fixes tried to solve the problem, that a new domU would inherit access permissions to access Xenstore entries with that domid listed in the access rights. In order not to make it easy for a domU to query existence of a domid, adding permission for a non-existing domain is not rejected by Xenstore. The XSA-417 patches solved that problem by adding a flag to a permission entry referencing a not existing domain, indicating that the permission should not be effective for Xenstore. One corner case was not handled: Consider guest 1 and guest 2 running. Guest 1 adds guest 2 to be able to access a Xenstore entry. Now guest 2 is removed from the system and a new guest 3 with the same domid as guest 2 had is being created. When guest 3 would try now to access the Xenstore entry, it would fail, as Xenstore would see that the Xenstore entry is older than guest 3. But if guest 1 is modifying the permissions of the Xenstore entry again, e.g. by adding another domain, the permission entry for guest 2 would lose its "special flag", resulting in guest 3 now really gaining access to the Xenstore entry. This series is fixing this problem by the following means: - In order to allow guests to know that a Xenstore entry permission might have gone stale, allow unprivileged guests to receive @releaseDomain watch events. This doesn't open a security hole, as the only knowledge which can by gathered from that change is that a domain is gone, not that a domain with a specific domid is existing. - When a domain is removed, remove all permissions relating to this domain from all Xenstore entries. Note that this issue was discussed by the Xen security team and we decided not to issue an XSA, as there are no known use cases where one unprivileged guest would grant access to its Xenstore nodes to more than one other unprivileged guests. We decided to delay this patch series until the watch depth feature has been committed, as with that feature available it is now possible for a guest to handle the death of a specific domain in a sane way. Juergen Gross (4): xen/public: introduce DOMID_ANY tools/xenstored: add support for "all domains" node permission tools/xenstored: allow @releaseDomain watch for all domains tools/xenstored: remove permissions related to dead domain docs/man/xl.cfg.5.pod.in | 4 ++ tools/xenstored/core.c | 45 ++++++++++++++----- tools/xenstored/domain.c | 77 +++++++++++++++++++++------------ tools/xenstored/domain.h | 3 +- xen/include/public/io/xs_wire.h | 2 + xen/include/public/xen.h | 7 +++ 6 files changed, 99 insertions(+), 39 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 08:09:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 08:09:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291715.1570573 (Exim 4.92) (envelope-from ) id 1wFp7T-0006OJ-Sd; Thu, 23 Apr 2026 08:09:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291715.1570573; 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dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931746; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UsqG9+X/SlnL7BdCX9NqfxTSD27zTpZHRZjBmI+WZ58=; b=sOcM2DmO3hCcSkkSOQqMDHZYE7hbZLXGjCFTeAxkZHtd2fSEBs7jJH1udglCJDU4Xc1oEf bRFKKGOf8H7wUjbiLqbNGg2lyNFRyMFDwZTfpc7g+EEmdsP+y0Hf2gbpJy8OYnFhhxOT+Z VLReKxDQvom9d3+23Tx3fShk69h33+o= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931746; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UsqG9+X/SlnL7BdCX9NqfxTSD27zTpZHRZjBmI+WZ58=; b=sOcM2DmO3hCcSkkSOQqMDHZYE7hbZLXGjCFTeAxkZHtd2fSEBs7jJH1udglCJDU4Xc1oEf bRFKKGOf8H7wUjbiLqbNGg2lyNFRyMFDwZTfpc7g+EEmdsP+y0Hf2gbpJy8OYnFhhxOT+Z VLReKxDQvom9d3+23Tx3fShk69h33+o= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Juergen Gross , Julien Grall , Anthony PERARD Subject: [PATCH 4/4] tools/xenstored: remove permissions related to dead domain Date: Thu, 23 Apr 2026 10:08:40 +0200 Message-ID: <20260423080840.530547-5-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423080840.530547-1-jgross@suse.com> References: <20260423080840.530547-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_FIVE(0.00)[5]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: X-purgate-ID: tlsNG-16d1c6/1776931746-50767D75-5A35755B/0/0 X-purgate-type: clean X-purgate-size: 3648 Wit unprivileged domains now capable to use the @releaseDomain watch, there is no reason not to remove any node permissions which relate to a domain which has been removed. This resolves a complex scenario where a new domain could inherit the permissions of an old one with the same domid. Signed-off-by: Juergen Gross --- tools/xenstored/domain.c | 61 ++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 25 deletions(-) diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index 0bd2a1891a..6fbb5c061a 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -569,24 +569,10 @@ static int domain_tree_remove_sub(const void *ctx, struct connection *conn, struct node *node, void *arg) { struct domain *domain = arg; - int ret = WALK_TREE_OK; - - if (node->perms[0].id != domain->domid) - return WALK_TREE_OK; + bool node_changed = false; + unsigned int i; - if (keep_orphans) { - domain_nbentry_dec(NULL, domain->domid); - node->perms[0].id = priv_domid; - node->acc.memory = 0; - domain_nbentry_inc(NULL, priv_domid); - if (write_node_raw(NULL, node->name, node, NODE_MODIFY, true)) { - /* That's unfortunate. We only can try to continue. */ - syslog(LOG_ERR, - "error when moving orphaned node %s to dom0\n", - node->name); - } else - trace("orphaned node %s moved to dom0\n", node->name); - } else { + if (node->perms[0].id == domain->domid && !keep_orphans) { if (rm_node(NULL, ctx, node->name)) { /* That's unfortunate. We only can try to continue. */ syslog(LOG_ERR, @@ -596,10 +582,38 @@ static int domain_tree_remove_sub(const void *ctx, struct connection *conn, trace("orphaned node %s deleted\n", node->name); /* Skip children in all cases in order to avoid more errors. */ - ret = WALK_TREE_SKIP_CHILDREN; + return WALK_TREE_SKIP_CHILDREN; } - return domain->acc_val[ACC_NODES] ? ret : WALK_TREE_SUCCESS_STOP; + if (node->perms[0].id == domain->domid) { + domain_nbentry_dec(NULL, domain->domid); + node->perms[0].id = priv_domid; + node->acc.memory = 0; + domain_nbentry_inc(NULL, priv_domid); + trace("moving orphaned node %s to dom0\n", node->name); + node_changed = true; + } + + for (i = 1; i < node->hdr.num_perms; i++) { + if (node->perms[i].id != domain->domid) + continue; + memmove(node->perms + i, node->perms + i + 1, + sizeof(*node->perms) * (node->hdr.num_perms - i - 1)); + node->hdr.num_perms--; + i--; + node_changed = true; + } + + if (node_changed) { + if (write_node_raw(NULL, node->name, node, NODE_MODIFY, true)) { + /* That's unfortunate. We only can try to continue. */ + syslog(LOG_ERR, + "error when writing modified node %s\n", + node->name); + } + } + + return WALK_TREE_OK; } static void domain_tree_remove(struct domain *domain) @@ -607,12 +621,9 @@ static void domain_tree_remove(struct domain *domain) int ret; struct walk_funcs walkfuncs = { .enter = domain_tree_remove_sub }; - if (domain->acc_val[ACC_NODES]) { - ret = walk_node_tree(domain, NULL, "/", &walkfuncs, domain); - if (ret == WALK_TREE_ERROR_STOP) - syslog(LOG_ERR, - "error when looking for orphaned nodes\n"); - } + ret = walk_node_tree(domain, NULL, "/", &walkfuncs, domain); + if (ret == WALK_TREE_ERROR_STOP) + syslog(LOG_ERR, "error when looking for orphaned nodes\n"); walk_node_tree(domain, NULL, "@releaseDomain", &walkfuncs, domain); walk_node_tree(domain, NULL, "@introduceDomain", &walkfuncs, domain); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 08:09:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 08:09:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291716.1570581 (Exim 4.92) (envelope-from ) id 1wFp7V-0006eB-37; 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Thu, 23 Apr 2026 08:09:00 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931741; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mye3eCQVSlEbkJEnkWGbsqAfuNKV6b0HpEvbptC1tVQ=; b=sPZf6KqqJRs24isDTQ3Kms4qAjjRhGoIKm66ukA1cIV1y945/3NRA2RegytzyEVa9AQLuD FP0D0BomlwISbMcjxjjIXLVllHLi3lcs3GIFIeyIzdeerDPIR+46fB8fWFlU3ciME2ASqt AuzhPVG3swBKXn6zCZFHFdUpe05mjE0= Authentication-Results: smtp-out1.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=AgfXxE44 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776931740; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mye3eCQVSlEbkJEnkWGbsqAfuNKV6b0HpEvbptC1tVQ=; b=AgfXxE44EPVmap4ZnIVWJtN9LpKEhQY9msq5nMBi1S9lBSMXtQBiigKT45Y5QpJDKvQFhM tKI0BRllurFsX1ml8neyfELHMKsl+9wJk9GM56MwN0LIklNoQhTa4WdpfUXgy8qMN8RwZL P2Uxz4krBpnib2eAupPqs2A36OL7wjc= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Juergen Gross , Julien Grall , Anthony PERARD Subject: [PATCH 3/4] tools/xenstored: allow @releaseDomain watch for all domains Date: Thu, 23 Apr 2026 10:08:39 +0200 Message-ID: <20260423080840.530547-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260423080840.530547-1-jgross@suse.com> References: <20260423080840.530547-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; 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This is problematic for guests which want to give other domains access to Xenstore entries, as they have no simple way to tell when such a domain is stopped. Allow @releaseDomain to be usable by all domains as the default. Signed-off-by: Juergen Gross --- tools/xenstored/core.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 5a621f53ba..421f227ff1 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -2279,19 +2279,19 @@ struct connection *get_connection_by_id(unsigned int conn_id) } /* We create initial nodes manually. */ -static void manual_node(const char *name, const char *child) +static void manual_node_perms(const char *name, const char *child, + struct xs_permissions *perms, + unsigned int n_perms) { struct node *node; - struct xs_permissions perms = { .id = priv_domid, - .perms = XS_PERM_NONE }; node = talloc_zero(NULL, struct node); if (!node) barf_perror("Could not allocate initial node %s", name); node->name = name; - node->perms = &perms; - node->hdr.num_perms = 1; + node->perms = perms; + node->hdr.num_perms = n_perms; node->children = (char *)child; if (child) node->hdr.childlen = strlen(child) + 1; @@ -2301,6 +2301,14 @@ static void manual_node(const char *name, const char *child) talloc_free(node); } +static void manual_node(const char *name, const char *child) +{ + struct xs_permissions perms = { .id = priv_domid, + .perms = XS_PERM_NONE }; + + manual_node_perms(name, child, &perms, 1); +} + static unsigned int hash_from_key_fn(const void *k) { const char *str = k; @@ -2320,6 +2328,11 @@ static int keys_equal_fn(const void *key1, const void *key2) void setup_structure(bool live_update) { + struct xs_permissions perms[] = { + { .id = priv_domid, .perms = XS_PERM_NONE }, + { .id = DOMID_ANY, .perms = XS_PERM_READ }, + }; + nodes = create_hashtable(NULL, "nodes", hash_from_key_fn, keys_equal_fn, HASHTABLE_FREE_KEY | HASHTABLE_FREE_VALUE); if (!nodes) @@ -2331,7 +2344,8 @@ void setup_structure(bool live_update) manual_node("/", "tool"); manual_node("/tool", "xenstored"); manual_node("/tool/xenstored", NULL); - manual_node("@releaseDomain", NULL); + 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=?utf-8?B?YXJvNFFvczJEc3JVVHEwR212RE5HWklDWC9aaE5neGl1aElSajBtc00vbEJo?= =?utf-8?Q?wBZi83mZDA+0dyzk=3D?= X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-Network-Message-Id: 24b6265c-69c0-47f4-354d-08dea1121193 X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 08:26:51.0917 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iLfu0s85nvQAqVp+5ayElY2bq8DKH/GujakxgVPnpdB+RnpBCYxUshJlHyAM/bqRIWBHMyAKgoDdROXoDTZcLC9o6yf70avccGR1XfABRbA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0301MB6640 X-purgate-ID: tlsNG-d62444/1776932815-BD468FF4-53531E52/0/0 X-purgate-type: clean X-purgate-size: 2235 Hi Michal, Oleksandr Thank you for the fast review. Well, I don't know why the commit differs :). I haven't copied it, just wrote from scratch. I see that overall it looks good. I can post v4 with nits fixed from you and Oleksandr, or they will be fixed on commit. Which way is more convenient for you? -- Oleksii. On 22/04/2026 14:33, Orzel, Michal wrote: > > On 22/04/2026 11:33, Oleksii Moisieiev wrote: >> In exynos4210_uart_init_postirq(), when setup_irq() returns an error >> the failure was only logged via dprintk() and execution continued, >> unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled >> receive and transmit interrupt lines with no handler registered. On >> platforms where the GIC receives these asserted lines, the result is >> either repeated spurious-interrupt warnings or an unhandled interrupt >> fault. >> >> Add an early return in the setup_irq() error branch so that the >> interrupt-enable writes to UINTM and UMCON are skipped when IRQ >> registration fails. >> >> Signed-off-by: Oleksii Moisieiev >> --- >> >> Changes in v3: >> - skip clearing pending interrupts if setup_irq was failed because >> according to the 13.4.1.13 of the RM: it must be cleared after >> cleaning interrupt pending in INTC. >> >> xen/drivers/char/exynos4210-uart.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c >> index 58901df554..2e5860ea2b 100644 >> --- a/xen/drivers/char/exynos4210-uart.c >> +++ b/xen/drivers/char/exynos4210-uart.c >> @@ -199,8 +199,12 @@ static void __init exynos4210_uart_init_postirq(struct serial_port *port) >> uart->irqaction.dev_id = port; >> >> if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 ) >> + { >> dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %d\n", >> uart->irq); >> + /* Don't enable interrupts if irq setup was failed */ > NIT: Not sure why this comment differs from one patch to another. Preferably > they should all be the same. > > Reviewed-by: Michal Orzel > > ~Michal > From xen-devel-bounces@lists.xenproject.org Thu Apr 23 08:30:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 08:30:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291779.1570610 (Exim 4.92) (envelope-from ) id 1wFpRe-0005m4-BK; Thu, 23 Apr 2026 08:29:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291779.1570610; Thu, 23 Apr 2026 08:29:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFpRe-0005lw-6Z; Thu, 23 Apr 2026 08:29:58 +0000 Received: by outflank-mailman (input) for mailman id 1291779; Thu, 23 Apr 2026 08:29:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFpRb-0005lq-Uc for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6NshDjRGfDoaWzKP7uQgYXe2obu0y9Wun+FD+BmMWkvjVl4ScqG8AIoTku5V+3OWmeUwb/DssP4AVPh8l/xL/swys2d1SEEItEXFBiIdi7+MIe1On/1ZNPu7GO/mqhbRMVtrex5hcyUPEAiw4F7jCr6TxB1vQhCbcjAC01GJ/SrOLPCQLQCuvil1PbnGoQXkswnBHObd92ozL/zOJegd2alyszNNU2MlR55XKVVlLWwBtB5yQpskf4D6qXY9f5D0JHikl6VlJTlASHx4spmRmwMpXZ6WUEEep8wTz+3IRsQ8rGfeHkO3oideCfwyJr/xhs0bc/ofswq5fZRpjyeI+LOGzdHFGWSZBUOv3qpNuv0S7xsJhNmkZ9w89j4dVrQ6zIUIV1tfE7H8a1jBWMe3gLu/QyqdGPxubRYMv3aeJ4Yk1BHj9pm+4iRxGKVnqci8 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 08:29:43.0570 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97c11ee4-a3c1-4e21-12af-08dea112784e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.55.251];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF00016159.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9148 X-purgate-ID: tlsNG-d25034/1776932992-F5E0ECF5-733113F7/0/0 X-purgate-type: clean X-purgate-size: 437 On 23/04/2026 10:26, Oleksii Moisieiev wrote: > Hi Michal, Oleksandr > > Thank you for the fast review. Well, I don't know why the commit differs > :). I haven't copied it, just wrote from scratch. > > I see that overall it looks good. I can post v4 with nits fixed from you > and Oleksandr, or they will be fixed on commit. > > Which way is more convenient for you? Please send a respin with tags kept. ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 23 09:06:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 09:06:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291811.1570618 (Exim 4.92) (envelope-from ) id 1wFq1K-0004oH-Vg; Thu, 23 Apr 2026 09:06:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291811.1570618; Thu, 23 Apr 2026 09:06:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFq1K-0004oA-SJ; Thu, 23 Apr 2026 09:06:50 +0000 Received: by outflank-mailman (input) for mailman id 1291811; Thu, 23 Apr 2026 09:06:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFq1K-0004o4-BD for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 09:06:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFq1J-006Fvy-OM for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 11:06:49 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e9e123-e002-0a2a0a5209dd-0a2a4507d61e-18 for ; Thu, 23 Apr 2026 11:06:49 +0200 Received: from [185.255.28.34] (helo=prod-mta-13.swg-srv.net) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69e9e129-229c-0a2a45070019-b9ff1c22a1a9-3 for ; Thu, 23 Apr 2026 11:06:49 +0200 Received: from mail2.vates.fr ([37.26.189.201] mail2.vates.fr) (Authenticated sender: 8631fc262581453bbf619ec5b2062170/smtp/7773de5a-2839-4720-82ee-e06722ae1d3e) by prod-mta-13.swg-srv.net (ZoneMTA - prod-mta-13) with ESMTPSA id 19db99780f2000f373.003 for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Thu, 23 Apr 2026 09:06:47 +0000 Received: from [192.168.1.18] (88-175-170-134.subs.proxad.net [88.175.170.134]) (Authenticated sender: teddy.astie) by mail2.vates.fr (Postfix) with ESMTPSA id 9BA8F8751B; Thu, 23 Apr 2026 11:06:46 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=go9+WX/P6oqYtEySQytKG8V8SBsCctPOIK9GQzP43hU=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=e7Eh3i5a5Vd2t6iXmZLTZlrnoFEmBNCL0TJaHpzZGRe9QHqKzc0nlR4Zpc8QtI2JuoVN+QQEc cfclA/dZXhk3+4cyk38/f2uRWuPnSB+RmpDjy5xGTM3ZSrNaCJoVqm3oFFbJidYHEpWEeH7Xj9I XGEYZsoEfNC4NPnJig7zhCJ6oubiiANKTXF5fs1ziclAvfwsMQpn+cfs+bsQ7oQpll8hNseTlFo lPwXAHQVoIop1gwBfBsYXXyvQjU6GkvoKPfLEWMiBapumv/tNLWBQaqe/GL5T6N7HHZ7OuINjYd FYD0tFaC7QtopeHXrRLN235BjaV8FhZOqQ0/1P4ew/tQ== X-Zone-Loop: 2fa8092623fdedff30b0dab6bdbda7c872af21492609 x-campaign-type: default x-transaction-id: 88636dab-3b3e-4762-bfa6-1782a7694db7 x-swg-uid: 01-421f5041-9174-4bec-b48c-7ada9737acc7 X-Mailer: Sweego Message-ID: <1776935207.8631fc262581453bbf619ec5b2062170.19db99780f2000f373@vates.tech> x-swg-bid: 1776935207.8631fc262581453bbf619ec5b2062170.19db99780f2000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 23 Apr 2026 11:06:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: How to express "externally managed" IOMMU domains for VFIO/IOMMUFD ? To: "Tian, Kevin" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" Cc: Xen-devel References: <1776873531.8631fc262581453bbf619ec5b2062170.19db5ea67ab000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.268f.f9401862dbe5e1bb.19db9977f45.39413018467b706c=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776935206726 X-purgate-ID: tlsNG-ef75cf/1776935209-AC961C48-18066BAD/0/0 X-purgate-type: clean X-purgate-size: 3219 ---=Part.268f.f9401862dbe5e1bb.19db9977f45.39413018467b706c=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hello and thanks for your response=2E Le 23/04/2026 =C3=A0 10:05, Tian, Kevin a =C3=A9crit=C2=A0: >> From: Teddy Astie >> Sent: Wednesday, April 22, 2026 11:59 PM >> >> Hello, >> >> On Xen, for PV-IOMMU [1], we have IOMMU support in Dom0, which in >> particular allows using VFIO and IOMMUFD from Dom0=2E >> >> However, its interactions with PCI Passthrough are unclear, and it woul= d >=20 > VFIO manages PCI passthrough=2E since it's already allowed which part of > interaction is unclear? >=20 AIUI, VFIO has no real knowledge of what is a "virtual machine" (at=20 least not in a way that would suffice for us), hence don't really PCI=20 Passthrough on its own=2E For instance, the DMA remapping aspect of QEMU's PCI Passthrough is=20 implemented by keeping the VFIO DMA mappings in sync with "guest=20 memory", however, we can't really do that in our case as we don't have=20 full control and view of guest memory=2E >> be preferable to let the kernel handle some of this logic=2E That would >> for instance avoid situations where toolstack causes Xen and Linux to g= o >> out of sync on where devices belong=2E >=20 > what is 'some of this logic' and what is the exact out-of-sync scenario? >=20 In the sense of letting the kernel handle the PCI Passthrough lifecycle=2E For now, the userland ("toolstack") is performing passthrough-related=20 operations on behalf of the kernel, i=2Ee move a device into the guest=2E= =20 That causes a problem where the Linux IOMMU subsystem thinks the device=20 is in a specific IOMMU domain, while it's actually not=2E That causes in particular Linux IOMMU logic to misbehave, and the device= =20 to eventually DMA in the wrong places=2E The idea isn't really to "fix" this specific case, but more to provide a= =20 alternative where the kernel orchestrate PCI Passthrough instead=2E So the= =20 logic would be now orchestrated in one place instead=2E >> >> On Xen, we have a dedicated hypercalls for moving a device into another >> guest (so it no longer belongs in Dom0, at far as DMA is concerned)=2E >> >> But it looks like there are no way to describe that idea of "attach tha= t >> device to this VM" nor "the device is in a VM"; which makes that >> impracticable=2E >> >> There may be things that could be done with the vIOMMU objects, but >> there would be no "parent domain" in such case, as said earlier it >> doesn't exist in the IOMMU subsystem=2E >> >> What is expected to be done instead ? >> >> Teddy >> >> [1] https://www=2Eyoutube=2Ecom/watch?v=3DpLMGRgEJ-Eg >> >=20 > It'd be much easier to collect comments if you can put plain words > to explain the problem rather than expecting other folks to watch > the video first=2E=2E=2E The video is more to additional context, it's not really directly=20 related to this issue=2E Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.268f.f9401862dbe5e1bb.19db9977f45.39413018467b706c=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 09:49:44 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 09:49:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291844.1570627 (Exim 4.92) (envelope-from ) id 1wFqgb-0005ZZ-3v; Thu, 23 Apr 2026 09:49:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291844.1570627; Thu, 23 Apr 2026 09:49:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFqgb-0005ZS-0R; Thu, 23 Apr 2026 09:49:29 +0000 Received: by outflank-mailman (input) for mailman id 1291844; Thu, 23 Apr 2026 09:49:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFqgZ-0005ZM-IT for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 09:49:27 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFqgY-00Agg1-Hf for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 11:49:26 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e9eb1f-2eae-0a2a0a5409dd-0a2a4503cf0a-10 for ; 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Thu, 23 Apr 2026 02:49:24 -0700 (PDT) MIME-Version: 1.0 References: <7053b8c14bbe50cc855dad0a82cde2bb10153d2b.1776266307.git.bertrand.marquis@arm.com> <6D745E55-2BBB-49CC-AE8D-D75E9704ED8D@arm.com> In-Reply-To: <6D745E55-2BBB-49CC-AE8D-D75E9704ED8D@arm.com> From: Jens Wiklander Date: Thu, 23 Apr 2026 11:49:11 +0200 X-Gm-Features: AQROBzDm2dIYwSRJuUDGevnOpJbu4Yy5WlH3ly2sG0PK-aUkmJjRxt1ggz8smZI Message-ID: Subject: Re: [PATCH 2/6] xen/arm: ffa: Track hypervisor notifications in a bitmap To: Bertrand Marquis Cc: "xen-devel@lists.xenproject.org" , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1776937766-A3D6B938-3F5D9061/0/0 X-purgate-type: clean X-purgate-size: 5467 Hi Bertrand, On Thu, Apr 23, 2026 at 9:30=E2=80=AFAM Bertrand Marquis wrote: > > Hi Jens, > > Thanks a lot for the review. > > > On 22 Apr 2026, at 11:34, Jens Wiklander wr= ote: > > > > Hi Bertrand, > > > > On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis > > wrote: > >> > >> Hypervisor notifications are currently tracked with a dedicated > >> buff_full_pending boolean. That state only represents a single HYP > >> notification bit and keeps HYP bitmap handling tied to single-purpose > >> bookkeeping. > >> > >> Replace the boolean with a hypervisor notification bitmap protected by > >> notif_lock. INFO_GET reports pending when the bitmap is non-zero, GET > >> returns and clears the HYP bitmap under the lock, and RX-buffer-full > >> sets FFA_NOTIF_RX_BUFFER_FULL in the bitmap instead of updating > >> separate state. > >> > >> Initialize and clear the bitmap during domain lifecycle handling, and > >> use ctx->ffa_id for bitmap create and destroy so the notification stat= e > >> stays tied to the cached FF-A endpoint ID. > >> > >> No functional changes. > >> > >> Signed-off-by: Bertrand Marquis > >> --- > >> xen/arch/arm/tee/ffa_notif.c | 46 ++++++++++++++++++++++++++-------- > >> xen/arch/arm/tee/ffa_private.h | 9 +++++-- > >> 2 files changed, 43 insertions(+), 12 deletions(-) > >> > >> diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif= .c > >> index 07bc5cb3a430..d15119409a25 100644 > >> --- a/xen/arch/arm/tee/ffa_notif.c > >> +++ b/xen/arch/arm/tee/ffa_notif.c > >> @@ -94,8 +94,15 @@ void ffa_handle_notification_info_get(struct cpu_us= er_regs *regs) > >> > >> notif_pending =3D test_and_clear_bool(ctx->notif.secure_pending); > >> if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > >> + { > >> notif_pending |=3D test_and_clear_bool(ctx->notif.vm_pending); > >> > >> + spin_lock(&ctx->notif.notif_lock); > >> + if ( ctx->notif.hyp_pending ) > >> + notif_pending =3D true; > >> + spin_unlock(&ctx->notif.notif_lock); > > > > Isn't this a functional change? Before this patch, we didn't consider > > ctx->notif.buff_full_pending here. Am I missing something? > > We did consider it implicitly through vm_pending. > > This patch makes that cleaner by using hyp_pending for the Hypervisor > framework notification itself. Previously, RX-buffer-full was made visibl= e > indirectly via vm_pending, and FFA_NOTIFICATION_INFO_GET > cleared that summary state. > > As a result, the guest-visible pending indication could be lost before > the Hypervisor notification was actually retrieved with > FFA_NOTIFICATION_GET. > > With this change, the pending state is tracked in hyp_pending and is only > cleared when the Hypervisor notifications are retrieved through > FFA_NOTIFICATION_GET. > > I will reword the commit message to make that clearer. Thanks > > > > >> + } > >> + > >> if ( notif_pending ) > >> { > >> /* A pending global notification for the guest */ > >> @@ -174,12 +181,17 @@ void ffa_handle_notification_get(struct cpu_user= _regs *regs) > >> w6 =3D resp.a6; > >> } > >> > >> - if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && > >> - flags & FFA_NOTIF_FLAG_BITMAP_HYP && > >> - test_and_clear_bool(ctx->notif.buff_full_pending) ) > >> + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > >> { > >> - ACCESS_ONCE(ctx->notif.vm_pending) =3D false; > >> - w7 =3D FFA_NOTIF_RX_BUFFER_FULL; > >> + spin_lock(&ctx->notif.notif_lock); > >> + > >> + if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pe= nding ) > >> + { > >> + w7 =3D ctx->notif.hyp_pending; > >> + ctx->notif.hyp_pending =3D 0; > >> + } > >> + > >> + spin_unlock(&ctx->notif.notif_lock); > >> } > >> > >> ffa_set_regs(regs, FFA_SUCCESS_32, 0, w2, w3, w4, w5, w6, w7); > >> @@ -207,12 +219,17 @@ int32_t ffa_handle_notification_set(struct cpu_u= ser_regs *regs) > >> void ffa_raise_rx_buffer_full(struct domain *d) > >> { > >> struct ffa_ctx *ctx =3D d->arch.tee; > >> + uint32_t prev_bitmap; > >> > >> if ( !ctx ) > >> return; > >> > >> - ACCESS_ONCE(ctx->notif.buff_full_pending) =3D true; > >> - if ( !test_and_set_bool(ctx->notif.vm_pending) ) > >> + spin_lock(&ctx->notif.notif_lock); > >> + prev_bitmap =3D ctx->notif.hyp_pending; > >> + ctx->notif.hyp_pending |=3D FFA_NOTIF_RX_BUFFER_FULL; > >> + spin_unlock(&ctx->notif.notif_lock); > >> + > >> + if ( !(prev_bitmap & FFA_NOTIF_RX_BUFFER_FULL) ) > > > > Do we need to check for FFA_NOTIF_RX_BUFFER_FULL? Isn't !prev_bitmap > > more accurate, if any other bit would ever be used in the bitmap? > > I would keep the bit-specific check here, if that is OK with you. > > This function is about raising the RX buffer full notification, > so I think it is clearer to check whether that bit was newly > pended rather than whether the whole Hypervisor bitmap > was previously empty. > > Using !prev_bitmap would also make the condition depend on > unrelated Hypervisor notifications being pending. > > Tell me if you are ok with that. I see your point, it's fine. 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2002:a05:6820:160c:b0:696:1413:496a with SMTP id 006d021491bc7-69614134ab7mr2707120eaf.17.1776943259378; Thu, 23 Apr 2026 04:20:59 -0700 (PDT) MIME-Version: 1.0 References: <263B26DA-15D5-43A6-90D8-AA42AF8C391B@arm.com> In-Reply-To: <263B26DA-15D5-43A6-90D8-AA42AF8C391B@arm.com> From: Jens Wiklander Date: Thu, 23 Apr 2026 13:20:48 +0200 X-Gm-Features: AQROBzCa-RtBTHXQqjokdyCc5gBlsx7zks-BOcWWP7X4as4jQ1SAxO4LuMKKhLs Message-ID: Subject: Re: [PATCH 6/6] xen/arm: ffa: Deliver VM-to-VM notifications locally To: Bertrand Marquis Cc: "xen-devel@lists.xenproject.org" , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1776943261-06772F3B-06E98B4A/0/0 X-purgate-type: clean X-purgate-size: 9436 Hi Bertrand, On Thu, Apr 23, 2026 at 10:17=E2=80=AFAM Bertrand Marquis wrote: > > Hi Jens, > > > On 22 Apr 2026, at 16:04, Jens Wiklander wr= ote: > > > > Hi Bertrand, > > > > On Fri, Apr 17, 2026 at 3:41=E2=80=AFPM Bertrand Marquis > > wrote: > >> > >> VM notification binding and pending tracking exist for non-secure > >> endpoints, but FFA_NOTIFICATION_SET still only forwards secure > >> destinations to the SPMC. Non-secure VMs therefore cannot receive > >> notifications from other VMs. Local NPI delivery also needs explicit > >> re-arm tracking so repeated raises are not lost while the interrupt is > >> already pending. > >> > >> Add a local VM notification delivery path for non-secure destinations. > >> notification_set_vm() resolves the destination endpoint, verifies that > >> every requested bit is bound to the sender, sets the receiver's > >> vm_pending bitmap under notif_lock, and raises an NPI only when the > >> receiver transitions from no local pending notifications to some. > >> > >> Track whether a local NPI is already armed with notif_irq_raised, clea= r > >> that state once both VM and hypervisor pending bitmaps are drained, an= d > >> roll back newly-added VM pending bits if no destination vCPU is online= . > >> Also expose firmware notification availability so FFA_FEATURES only > >> advertises notification support when it is actually provided by the > >> firmware or by CONFIG_FFA_VM_TO_VM. > >> > >> Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, non-secure > >> FFA_NOTIFICATION_SET delivers VM-to-VM notifications locally and keeps > >> NPI delivery reliable across repeated raises. > >> > >> Signed-off-by: Bertrand Marquis > >> --- > >> xen/arch/arm/tee/ffa.c | 24 +++++-- > >> xen/arch/arm/tee/ffa_notif.c | 126 +++++++++++++++++++++++++++++++-- > >> xen/arch/arm/tee/ffa_private.h | 11 ++- > >> 3 files changed, 147 insertions(+), 14 deletions(-) > >> > >> diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c > >> index 1fe33f26454a..7fe021049cba 100644 > >> --- a/xen/arch/arm/tee/ffa.c > >> +++ b/xen/arch/arm/tee/ffa.c > >> @@ -39,8 +39,13 @@ > >> * o FFA_MSG_SEND_DIRECT_REQ: > >> * - only supported from a VM to an SP > >> * o FFA_NOTIFICATION_*: > >> + * - only supported when firmware notifications are enabled or VM-t= o-VM > >> + * support is built in > >> * - only supports global notifications, that is, per vCPU notificat= ions > >> - * are not supported > >> + * are not supported and secure per-vCPU notification information= is > >> + * not forwarded > >> + * - the source endpoint ID reported for a notification may no long= er > >> + * exist by the time the receiver consumes it > >> * - doesn't support signalling the secondary scheduler of pending > >> * notification for secure partitions > >> * - doesn't support notifications for Xen itself > >> @@ -245,6 +250,8 @@ static void handle_features(struct cpu_user_regs *= regs) > >> uint32_t a1 =3D get_user_reg(regs, 1); > >> struct domain *d =3D current->domain; > >> struct ffa_ctx *ctx =3D d->arch.tee; > >> + bool notif_supported =3D IS_ENABLED(CONFIG_FFA_VM_TO_VM) || > >> + ffa_notif_fw_enabled(); > >> > >> /* > >> * FFA_FEATURES defines w2 as input properties only for specific > >> @@ -343,10 +350,16 @@ static void handle_features(struct cpu_user_regs= *regs) > >> > >> break; > >> case FFA_FEATURE_NOTIF_PEND_INTR: > >> - ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); > >> + if ( notif_supported ) > >> + ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, = 0); > >> + else > >> + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > >> break; > >> case FFA_FEATURE_SCHEDULE_RECV_INTR: > >> - ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0= ); > >> + if ( notif_supported ) > >> + ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_I= D, 0); > >> + else > >> + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > >> break; > >> case FFA_PARTITION_INFO_GET_REGS: > >> if ( ACCESS_ONCE(ctx->guest_vers) >=3D FFA_VERSION_1_2 ) > >> @@ -361,7 +374,10 @@ static void handle_features(struct cpu_user_regs = *regs) > >> case FFA_NOTIFICATION_SET: > >> case FFA_NOTIFICATION_INFO_GET_32: > >> case FFA_NOTIFICATION_INFO_GET_64: > >> - ffa_set_regs_success(regs, 0, 0); > >> + if ( notif_supported ) > >> + ffa_set_regs_success(regs, 0, 0); > >> + else > >> + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > >> break; > >> default: > >> ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > >> diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif= .c > >> index 4def701f0130..e77321244926 100644 > >> --- a/xen/arch/arm/tee/ffa_notif.c > >> +++ b/xen/arch/arm/tee/ffa_notif.c > >> @@ -20,7 +20,12 @@ static bool __ro_after_init fw_notif_enabled; > >> static unsigned int __ro_after_init notif_sri_irq; > >> static DEFINE_SPINLOCK(notif_info_lock); > >> > >> -static void inject_notif_pending(struct domain *d) > >> +bool ffa_notif_fw_enabled(void) > >> +{ > >> + return fw_notif_enabled; > >> +} > >> + > >> +static bool inject_notif_pending(struct domain *d) > >> { > >> struct vcpu *v; > >> > >> @@ -34,13 +39,15 @@ static void inject_notif_pending(struct domain *d) > >> if ( is_vcpu_online(v) ) > >> { > >> vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); > >> - return; > >> + return true; > >> } > >> } > >> > >> if ( printk_ratelimit() ) > >> printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs o= ffline\n", > >> d); > >> + > >> + return false; > >> } > >> > >> static int32_t ffa_notif_parse_params(uint16_t dom_id, uint16_t caller= _id, > >> @@ -104,6 +111,73 @@ out_unlock: > >> return ret; > >> } > >> > >> +/* > >> + * Deliver a VM-to-VM notification. ctx->notif.notif_lock protects > >> + * vm_bind/vm_pending so callers must not hold it already. > >> + */ > >> +static int32_t notification_set_vm(uint16_t dst_id, uint16_t src_id, > >> + uint32_t flags, uint64_t bitmap) > >> +{ > >> + struct domain *dst_d; > >> + struct ffa_ctx *dst_ctx; > >> + unsigned int id; > >> + int32_t ret; > >> + uint64_t prev_bitmap =3D 0; > >> + uint64_t new_bitmap; > >> + bool inject =3D false; > >> + > >> + if ( flags ) > >> + return FFA_RET_INVALID_PARAMETERS; > >> + > >> + ret =3D ffa_endpoint_domain_lookup(dst_id, &dst_d, &dst_ctx); > >> + if ( ret ) > >> + return ret; > >> + > >> + ret =3D FFA_RET_OK; > >> + > >> + spin_lock(&dst_ctx->notif.notif_lock); > >> + > >> + for ( id =3D 0; id < FFA_NUM_VM_NOTIF; id++ ) > >> + { > >> + if ( !(bitmap & BIT(id, ULL)) ) > >> + continue; > >> + > >> + if ( dst_ctx->notif.vm_bind[id] !=3D src_id ) > >> + { > >> + ret =3D FFA_RET_DENIED; > >> + goto out_unlock; > >> + } > >> + } > >> + > >> + prev_bitmap =3D dst_ctx->notif.vm_pending; > >> + dst_ctx->notif.vm_pending |=3D bitmap; > >> + if ( !dst_ctx->notif.notif_irq_raised && > >> + (dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) ) > >> + { > >> + dst_ctx->notif.notif_irq_raised =3D true; > >> + inject =3D true; > >> + } > >> + > >> +out_unlock: > >> + spin_unlock(&dst_ctx->notif.notif_lock); > >> + > >> + new_bitmap =3D bitmap & ~prev_bitmap; > >> + if ( ret =3D=3D FFA_RET_OK && inject && new_bitmap && > >> + !inject_notif_pending(dst_d) ) > >> + { > >> + spin_lock(&dst_ctx->notif.notif_lock); > >> + dst_ctx->notif.vm_pending &=3D ~new_bitmap; > > > > There's a window above when dst_ctx->notif.notif_lock is unlocked. > > What if another CPU has modified dst_ctx->notif.vm_pending during that > > window? > > You are right, there is a race in that window. Thanks for the finding :-) > > I think the simplest fix is to keep notif_lock held across the injection > attempt, so we do not expose partially updated notification state while t= he > interrupt delivery is still in progress. > > I do not think we should roll the pending bits back on injection failure, > though. In practice the cases where we fail to inject are cases where the > target cannot currently take the notification anyway, and dropping the > pending state would be worse than keeping it pending and not marking the = IRQ > as raised. > > So my plan would be to keep the pending state, only mark notif_irq_raised > when we actually inject, and keep the existing debug print for the cases = we > can detect. > > If that approach looks OK to you, I will update this patch accordingly. > > The same issue exists in patch 2 for the RX-buffer-full path, so I will f= ix > it there as well for the same reason. Sounds good. Cheers, Jens From xen-devel-bounces@lists.xenproject.org Thu Apr 23 11:29:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 11:29:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1291960.1570664 (Exim 4.92) (envelope-from ) id 1wFsFA-0004CU-S9; Thu, 23 Apr 2026 11:29:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1291960.1570664; Thu, 23 Apr 2026 11:29:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFsFA-0004CN-OE; Thu, 23 Apr 2026 11:29:16 +0000 Received: by outflank-mailman (input) for mailman id 1291960; Thu, 23 Apr 2026 11:29:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFsF9-0004CH-1u for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 11:29:15 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> Acked-by: Jan Beulich Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 23 13:50:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 13:50:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292121.1570693 (Exim 4.92) (envelope-from ) id 1wFuSH-0002pM-8U; Thu, 23 Apr 2026 13:50:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292121.1570693; Thu, 23 Apr 2026 13:50:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFuSH-0002pF-5W; Thu, 23 Apr 2026 13:50:57 +0000 Received: by outflank-mailman (input) for mailman id 1292121; Thu, 23 Apr 2026 13:50:56 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFuSG-0002p9-8z for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 13:50:56 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFuSF-00BPby-Lr for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 15:50:55 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea23b3-2eae-0a2a0a5409dd-0a2a4502bfee-22 for ; Thu, 23 Apr 2026 15:50:55 +0200 Received: from [209.85.208.169] (helo=mail-lj1-f169.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea23bf-af86-0a2a45020019-d155d0a9b9b8-3 for ; Thu, 23 Apr 2026 15:50:55 +0200 Received: by mail-lj1-f169.google.com with SMTP id 38308e7fff4ca-38e7b8e3f38so55808571fa.3 for ; Thu, 23 Apr 2026 06:50:55 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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So a second bank is added above that MMIO >> region (starting at 8 GiB) to provide the remaining RAM; the gap between >> the two banks also exercises code paths handling discontiguous memory. >> For Sv32 guests (34-bit GPA, 16 GiB addressable), bank0 provides 2 GB >> (2–4 GB) and the first 8 GB of bank1 (8–16 GB) is accessible. >> >> Extended regions are useful for RISC-V: they could be used to provide a >> "space" for Linux to map grant mappings. >> >> Despite the fact that for every guest MMU mode the GPA could be up >> to 56 bits wide (except Sv32 whose GPA is 34 bits), the combined size >> of both banks is limited to 1018 GB as it is more than enough for most >> use cases. >> >> Add inclusion of asm/guest-layout.h to asm/domain.h to make dom0less >> common code build happy. >> >> Signed-off-by: Oleksii Kurochko > > Again pretty hesitantly: I suppose beucase of hard-coded layout, right? > Acked-by: Jan Beulich Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 23 13:59:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 13:59:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292137.1570702 (Exim 4.92) (envelope-from ) id 1wFua0-0003ta-Vy; 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Thu, 23 Apr 2026 06:58:54 -0700 (PDT) Message-ID: <166ff356-2f48-4bb6-bb76-96c0f66ba9be@gmail.com> Date: Thu, 23 Apr 2026 16:58:52 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] xen/arm: smmuv3: Add support for removing devices To: Mykyta Poturai , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Rahul Singh References: Content-Language: en-US From: Oleksandr Tyshchenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1776952735-2B57BC48-F0C72AAC/0/0 X-purgate-type: clean X-purgate-size: 7445 On 4/22/26 12:57, Mykyta Poturai wrote: Hello Mykyta > Allow for removing devices from SMMUv3. arm_smmu_deassign_dev handles > most of the work by disabling ATS and zeroing STEs. Additionally, unset > the dt_device_is_protected flag and free no longer needed smmu_master. > Free iommu_fwspec for PCI devices only, for DT devices it is handled by > generic IOMMU layer. > > Rework dt_device_set_protected to accept a boolean parameter, update > callsites. > > Signed-off-by: Mykyta Poturai > --- > Tested on QEMU with SRIOV series[1] by repeatedly enabling/disabling > VFs. > > [1]: https://patchew.org/Xen/cover.1772806036.git.mykyta._5Fpoturai@epam.com/ > > V2->V3: > * free fwspec for pci devices > * remove testing note from commit message > > V1->V2: > * check for phantom functions > * simplify pci/dt device split > * improve error handling > * don't try to free master for unprotected devices > * rework dt_device_set_protected Thanks, this looks much better now. Mostly looks ok to me, but I have several comments. > --- > xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 +- > xen/drivers/passthrough/arm/smmu-v3.c | 65 +++++++++++++++++++++++- > xen/drivers/passthrough/arm/smmu.c | 4 +- > xen/include/xen/device_tree.h | 5 +- > 4 files changed, 70 insertions(+), 6 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > index fa9ab9cb13..0648f9b407 100644 > --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c > +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > @@ -1367,7 +1367,7 @@ static int ipmmu_add_device(u8 devfn, struct device *dev) > } > > /* Let Xen know that the master device is protected by an IOMMU. */ > - dt_device_set_protected(dev_to_dt(dev)); > + dt_device_set_protected(dev_to_dt(dev), true); > } > #ifdef CONFIG_HAS_PCI > if ( dev_is_pci(dev) ) > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index bf153227db..a46c421399 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -1493,6 +1493,68 @@ static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct device *dev, > static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, > struct device *dev); > > +static int arm_smmu_remove_device(u8 devfn, struct device *dev) Inconsistent devfn type: arm_smmu_remove_device() uses u8, but int (*remove_device)(uint8_t devfn, device_t *dev); uses uint8_t. > +{ > + struct arm_smmu_master *master; > + struct iommu_fwspec *fwspec; > + struct domain *d = NULL; > + > + fwspec = dev_iommu_fwspec_get(dev); > + if ( !fwspec ) > + return -ENODEV; > + > + master = dev_iommu_priv_get(dev); > + if ( !master ) > + return -ENODEV; > + > + if ( IS_ENABLED(CONFIG_HAS_PCI) && dev_is_pci(dev) ) > + { > + struct pci_dev *pdev = dev_to_pci(dev); arm_smmu_assign_dev() has ASSERT(pcidevs_locked()) in its PCI path, while arm_smmu_remove_device() does not. pci_remove_device() holds pcidevs_lock() before calling iommu_remove_device(). So, I would add the same assertion here to document the requirement and guard against future callers. > + > + /* Ignore calls for phantom functions */ > + if ( devfn != pdev->devfn ) > + return 0; > + > + d = pdev->domain; > + } > + else > + { > + if ( !dt_device_is_protected(dev_to_dt(dev)) ) > + { > + dev_err(dev, "Not added to SMMUv3\n"); > + return -ENODEV; > + } > + > + dt_device_set_protected(dev_to_dt(dev), false); > + if ( master->domain && master->domain->d ) > + d = master->domain->d; Unless I am mistaken, for DT devices, the deassign logic is unreachable dead code. iommu_remove_dt_device() returns -EBUSY if the device is still assigned, guaranteeing master->domain == NULL. This means that ... > + } > + > + if ( d ) > + { ... this block only has effect for PCI. I would consider adding a comment and ASSERT, something like: /* * For DT devices, iommu_remove_dt_device() returns -EBUSY if the * device is still assigned, so d is always NULL on the DT path. */ ASSERT(dev_is_pci(dev)); the rest looks good > + int ret = arm_smmu_deassign_dev(d, devfn, dev); > + /* This should never fail because we already checked the domain */ > + ASSERT(!ret); > + } > + > + arm_smmu_disable_pasid(master); > + > + dev_info(dev, "Removed master device (SMMUv3 %s StreamIds %u)\n", > + dev_name(fwspec->iommu_dev), fwspec->num_ids); > + > + xfree(master); > + dev_iommu_priv_set(dev, NULL); > + > + /* > + * For DT devices the fwspec is freed by iommu subsystem, but for PCI > + * devices we need to free it here > + */ > + if ( IS_ENABLED(CONFIG_HAS_PCI) && dev_is_pci(dev) ) > + iommu_fwspec_free(dev); > + > + return 0; > +} > + > static int arm_smmu_add_device(u8 devfn, struct device *dev) > { > int i, ret; > @@ -1571,7 +1633,7 @@ static int arm_smmu_add_device(u8 devfn, struct device *dev) > } > > /* Let Xen know that the master device is protected by an IOMMU. */ > - dt_device_set_protected(dev_to_dt(dev)); > + dt_device_set_protected(dev_to_dt(dev), true); > } > > dev_info(dev, "Added master device (SMMUv3 %s StreamIds %u)\n", > @@ -2867,6 +2929,7 @@ static const struct iommu_ops arm_smmu_iommu_ops = { > .unmap_page = arm_iommu_unmap_page, > .dt_xlate = arm_smmu_dt_xlate, > .add_device = arm_smmu_add_device, > + .remove_device = arm_smmu_remove_device, > }; > > static __init int arm_smmu_dt_init(struct dt_device_node *dev, > diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c > index d63c901551..4d2f71f152 100644 > --- a/xen/drivers/passthrough/arm/smmu.c > +++ b/xen/drivers/passthrough/arm/smmu.c > @@ -825,7 +825,7 @@ static int arm_smmu_dt_add_device_legacy(struct arm_smmu_device *smmu, > if ( !dev_is_pci(dev) ) > { > /* Xen: Let Xen know that the device is protected by an SMMU */ > - dt_device_set_protected(dev_node); > + dt_device_set_protected(dev_node, true); > } > > for (i = 0; i < fwspec->num_ids; ++i) { > @@ -862,7 +862,7 @@ static int arm_smmu_dt_remove_device_legacy(struct arm_smmu_device *smmu, > > if ( !dev_is_pci(dev) ) > /* Protected by dt_host_lock and dtdevs_lock as caller holds these locks. */ > - dev_node->is_protected = false; > + dt_device_set_protected(dev_node, false); > > kfree(master); > return 0; > diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h > index 06d7643622..76ae1e674a 100644 > --- a/xen/include/xen/device_tree.h > +++ b/xen/include/xen/device_tree.h > @@ -300,9 +300,10 @@ static inline domid_t dt_device_used_by(const struct dt_device_node *device) > return device->used_by; > } > > -static inline void dt_device_set_protected(struct dt_device_node *device) > +static inline void dt_device_set_protected(struct dt_device_node *device, > + bool protected) > { > - device->is_protected = true; > + device->is_protected = protected; > } > > static inline bool dt_device_is_protected(const struct dt_device_node *device) From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:46:42 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:46:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292188.1570715 (Exim 4.92) (envelope-from ) id 1wFvK4-0003A8-E0; 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boundary="-=Part.2738.9a73b4bc15a7d56d.19dbace74b2.a262829cedf10721=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955585714 X-purgate-ID: tlsNG-720697/1776955589-81971161-4D35BBA0/0/0 X-purgate-type: clean X-purgate-size: 3394 ---=Part.2738.9a73b4bc15a7d56d.19dbace74b2.a262829cedf10721=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable This series adds new 'hotplug' option for PCI device passthrough=2E The current mechanism for device passthrough uses QMP device_add command to hot-plug PCI devices to the guest Qemu instance=2E This is an issue for guests running on Q35 chipset (preliminary support posted at [1]) since th= e Q35 PCI root bus does not support hotplug=2E Devices could be hotplugged t= o a secondary PCI bus but Xen only support 1 PCI bus for now=2E The 'hotplug' option allows to control how devices are attached to the guest, either by using the legacy QMP mechanism (this is the default) or b= y passing them directly to the Qemu command line using xen-pci-passthrough device=2E Example usage in cfg file: pci =3D [ "00:03=2E0,seize=3D1,hotplug=3D0" ] Since Qemu -device option accepts parameters in json format, this patchset adds a new internal function libxl__device_pci_get_qapi_json() th= at generates the device json object used for both QMP hotplug and command lin= e passing=2E Also, to handle the assignable PCI device list, the function libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and is made available from libxl=2Eh for access in libxl_dm=2Ec=2E 2 other functi= ons are also exported internally: libxl__pciback_dev_is_assigned() and libxl__device_pci_assignable_add()=2E This has been successfully tested on Xen 4=2E22-dev and Qemu 10=2E0 runnin= g Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk=2E Disabling the hotplug mechanism might be made mandatory for Q35 machines later, once Q35 support is merged upstream=2E [1] https://lore=2Ekernel=2Eorg/xen-devel/20260313163455=2E790692-1-thierr= y=2Eescande@vates=2Etech/ Changes in v2: - Add support for YAJL json parser Changes in v3: - Move code block of device command line parameters creation - Better handling of pci device assignation Changes in v4: - Split the refactoring parts of the 2nd patch - Extend libxl__json_object_to_json() and use it to generate the qapi jso= n string Thierry Escande (6): xl: Add an hotplug option for PCI device passthrough libxl: Refactor some PCI device handling functions libxl: Add libxl__device_pci_get_qapi_json() internal API libxl: Extend libxl__json_object_to_json() prototype libxl: Allow PCI device passthrough using -device Qemu command line docs: provide description for pci hotplug option docs/man/xl-pci-configuration=2E5=2Epod | 17 +++++++++ docs/man/xl=2Ecfg=2E5=2Epod=2Ein | 6 +++ tools/include/libxl=2Eh | 1 + tools/libs/light/libxl_dm=2Ec | 33 +++++++++++++++++ tools/libs/light/libxl_internal=2Eh | 12 +++++- tools/libs/light/libxl_json=2Ec | 11 +++++- tools/libs/light/libxl_pci=2Ec | 57 ++++++++++++++++++++--------- tools/libs/light/libxl_types=2Eidl | 1 + tools/libs/util/libxlu_pci=2Ec | 2 + tools/xl/xl_parse=2Ec | 5 +++ 10 files changed, 123 insertions(+), 22 deletions(-) --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.2738.9a73b4bc15a7d56d.19dbace74b2.a262829cedf10721=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:48:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:48:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292200.1570724 (Exim 4.92) (envelope-from ) id 1wFvLY-00048Y-Qs; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=Wjam52wM4t5fu8hd5y0BF/RarPoTPN27K7lgxJnMIPI=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=UZduqRR20nwRJmiN9CcpTBgYdRxY2oZ63RhcjSjxBUSE3gyUhca5N6EDDIuQFEzT0l9bJJzq7 NYfe8UcRluB5nwDXlSNgDBRK2GZQf6pX28WO0eFVp8F1sVwMhO7RhvQabr9Y/coGItlW6OWE5sk Kn+GUqC967J8h1T2lxlgtFtFyr/nZgztBs/KbKE7HP9sP+mdrbS122dpnlpSyO5sE8mrd87/JQh 0GFUnXUu3G6upzV0mHZt5Ldvpe+2lENmqmUpozUiOplIc3jfm0ev32LxfHSLQjqtDF2vdlJINAN rW1Qj+9aFxKHI3MUqtK6RkInReVvMR8YGcEmziAGb4Vg== X-Zone-Loop: f71bce721eb1bad744635f2c584ac4462fc4330cfc57 x-campaign-type: default x-transaction-id: e97d7f08-8e9c-4c73-ba48-479999152184 x-swg-uid: 01-264f490e-ffd8-46f0-b60b-b9301dad5ed6 X-Mailer: Sweego Message-ID: <1776955678.8631fc262581453bbf619ec5b2062170.19dbacfe0b3000f373@vates.tech> x-swg-bid: 1776955678.8631fc262581453bbf619ec5b2062170.19dbacfe0b3000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 23 Apr 2026 16:47:57 +0200 From: Anthony PERARD To: Jason Andryuk Cc: Thierry Escande , xen-devel@lists.xenproject.org, Jan Beulich Subject: Re: [PATCH v2] install.sh: Preserve symlinks in destination file system References: <20260319165047.900047-1-thierry.escande@vates.tech> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.273b.47cdd80120cedfb4.19dbacfde1a.a3521e772715a28a=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955678234 X-purgate-ID: tlsNG-d62444/1776955683-BE265FF4-3B696FE4/0/0 X-purgate-type: clean X-purgate-size: 1262 ---=Part.273b.47cdd80120cedfb4.19dbacfde1a.a3521e772715a28a=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Mar 20, 2026 at 10:04:18AM -0400, Jason Andryuk wrote: > On 2026-03-19 12:50, Thierry Escande wrote: > > In various distros (i=2Ee=2E Debian), /lib is a symbolic link=2E The t= ar > > command in install=2Esh replaces the /lib symlink with a directory and > > results in a non-functioning system=2E This has been introduced by the > > installation of the systemd watchdog sleep script in /lib/systemd=2E > >=20 > > This patch adds the tar option --dereference (-h for short) to preserv= e > > symlinks when extracting the dist archive=2E > >=20 > > Fixes: e54a6cd6a1f3 ("systemd: Add hooks to stop/start xen-watchdog on= suspend/resume") > > Signed-off-by: Thierry Escande >=20 > Reviewed-by: Jason Andryuk > Tested-by: Jason Andryuk Acked-by: Anthony PERARD Thanks, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.273b.47cdd80120cedfb4.19dbacfde1a.a3521e772715a28a=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:50:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:50:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292209.1570733 (Exim 4.92) (envelope-from ) id 1wFvOC-0005dF-7D; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=KBWl2590AHjYullwyX+MHp2jMCGp9Bq1kRreRVpo7Hg=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=WV6T6gNn1hnYPsrUiEqoyfOcYYLe4YLq9YH7IiQ0T3gUFOA8uCYDlOzTXzvgPECDmejRAyAjQ 5DVIE++Bg24jVUcdgY/GTjIBOTRMy5mYYvc/XfQoSUhqE4ldCggb1IqHLfX6TmLu3nZLALamwxy DAAMcnuNrxZnWY46LWnYgsU3/KJLDGBeQ1lPdJO41mv1mbsEBlEB8wYJA1iEzgnPmCTIzV6UUvK vqE+Ci8hgKLgyYEUiV4vcMf5p0K8qUd+B7lQA4ybQwHYdVKEAPo8Svs1Wc9n6QAHzOvHyOKgZ+x 5oMk9gCnu4k5VKPf+lJ3OjdodLXhpO2nHGJRuidfrRfw== X-Zone-Loop: 5d4489ed720da88da7d6f913bcc746860a10914d2ca1 x-campaign-type: default x-transaction-id: 948046c6-d1f6-40fb-8274-2ede3dbe1a5e x-swg-uid: 01-d4d72bf3-db56-47c3-ba66-fc4655f3a1ae X-Mailer: Sweego Message-ID: <1776955844.8631fc262581453bbf619ec5b2062170.19dbad2669e000f373@vates.tech> x-swg-bid: 1776955844.8631fc262581453bbf619ec5b2062170.19dbad2669e000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Thierry Escande To: xen-devel@lists.xenproject.org Cc: Thierry Escande , Anthony PERARD , Juergen Gross , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [RFC PATCH v4 1/6] xl: Add an hotplug option for PCI device passthrough Date: Thu, 23 Apr 2026 16:50:26 +0200 In-Reply-To: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> References: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> MIME-Version: 1.0 Content-Transfert-Encoding: 8bit X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.273d.964768495393517d.19dbad26532.9289b73646f62651=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955843890 X-purgate-ID: tlsNG-bad1c0/1776955846-416B0A53-F48FF569/0/0 X-purgate-type: clean X-purgate-size: 3610 ---=Part.273d.964768495393517d.19dbad26532.9289b73646f62651=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable This patch adds a boolean option to the PCI device configuration table named hotplug=2E This will allow to control how devices are attached to the guest, either by using the legacy QMP mechanism (this will be the default) or by passing them directly to the Qemu command line using xen-pci-passthrough device=2E Sample use in xl=2Ecfg file: pci =3D [ "00:03=2E0,seize=3D1,hotplug=3D0" ] If not specified, the default behavior is to use hotplug via QMP=2E This will be needed for Q35 support in guests since the Q35 PCI root bus doesn't support hotplugging and Xen only support 1 PCI bus for now=2E Signed-off-by: Thierry Escande --- v2: no change v3: no change v4: - Reword commit message --- tools/libs/light/libxl_types=2Eidl | 1 + tools/libs/util/libxlu_pci=2Ec | 2 ++ tools/xl/xl_parse=2Ec | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/tools/libs/light/libxl_types=2Eidl b/tools/libs/light/libxl_t= ypes=2Eidl index a7893460f0=2E=2Eaca0e93793 100644 --- a/tools/libs/light/libxl_types=2Eidl +++ b/tools/libs/light/libxl_types=2Eidl @@ -922,6 +922,7 @@ libxl_device_pci =3D Struct("device_pci", [ ("seize", bool), ("rdm_policy", libxl_rdm_reserve_policy), ("name", string), + ("hotplug", bool), ]) =20 libxl_device_rdm =3D Struct("device_rdm", [ diff --git a/tools/libs/util/libxlu_pci=2Ec b/tools/libs/util/libxlu_pci= =2Ec index 294482c6d7=2E=2Ef6440c878b 100644 --- a/tools/libs/util/libxlu_pci=2Ec +++ b/tools/libs/util/libxlu_pci=2Ec @@ -192,6 +192,8 @@ int xlu_pci_parse_spec_string(XLU_Config *cfg, libxl_d= evice_pci *pci, name_present =3D true; pci->name =3D strdup(val); if (!pci->name) ret =3D ERROR_NOMEM; + } else if (!strcmp(key, "hotplug")) { + pci->hotplug =3D atoi(val); } else { XLU__PCI_ERR(cfg, "Unknown PCI_SPEC_STRING option: %s", key); ret =3D ERROR_INVAL; diff --git a/tools/xl/xl_parse=2Ec b/tools/xl/xl_parse=2Ec index 48c72dce9c=2E=2E7ea2a76662 100644 --- a/tools/xl/xl_parse=2Ec +++ b/tools/xl/xl_parse=2Ec @@ -1361,6 +1361,7 @@ void parse_config_data(const char *config_source, int pci_msitranslate =3D 0; int pci_permissive =3D 0; int pci_seize =3D 0; + int pci_hotplug =3D 1; int i, e; int num_llc_colors; int num_xs_quota; @@ -1699,6 +1700,9 @@ void parse_config_data(const char *config_source, if (!xlu_cfg_get_long (config, "pci_seize", &l, 0)) pci_seize =3D l; =20 + if (!xlu_cfg_get_long (config, "pci_hotplug", &l, 0)) + pci_hotplug =3D l; + if (!xlu_cfg_get_string(config, "rdm", &buf, 0)) { libxl_rdm_reserve rdm; if (!xlu_rdm_parse(config, &rdm, buf)) { @@ -1720,6 +1724,7 @@ void parse_config_data(const char *config_source, pci->power_mgmt =3D pci_power_mgmt; pci->permissive =3D pci_permissive; pci->seize =3D pci_seize; + pci->hotplug =3D pci_hotplug; /* * Like other pci option, the per-device policy always follow= s * the global policy by default=2E --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.273d.964768495393517d.19dbad26532.9289b73646f62651=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:50:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:50:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292210.1570742 (Exim 4.92) (envelope-from ) id 1wFvOI-0005rz-F9; Thu, 23 Apr 2026 14:50:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292210.1570742; Thu, 23 Apr 2026 14:50:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFvOI-0005rq-BY; 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Thu, 23 Apr 2026 14:50:48 +0000 Received: from xps13-debian.gpn.vates.fr (lfbn-mon-1-1130-120.w90-48.abo.wanadoo.fr [90.48.233.120]) (Authenticated sender: thierry.escande) by mail2.vates.fr (Postfix) with ESMTPSA id 80BBC86015; Thu, 23 Apr 2026 16:50:47 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=M4JVSGAFCQr9BGBfFiKi3POaf5wdzET+5BsITsVx5po=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=JqaJMKPNH1YviJrycRVKp5fNbXqNKJjiwyZNJbjd2b8LCfhQJhFwPKaL3cLCsMg/EyhK2JxRF j7zY26MvTbPeCm68d5UEolMWCx8XLdKOX/hOPn64HXivTX5kHVj56AIkVdzo2GF0QaWg9RLdsp4 F2YgRUSLFrUHgUS4zVAclHTZhGi8dULf29EHWn5JhImjd60FDEKpnOse3LRAncVJ8r8FwkpxdLZ 5TAvaN9oCNEkO78Z4y2kEs9vmYltYq0qSCoGivPl4PrDlgxGjJ0sRc/MAz95NRlWWKKz2z5HoAo j/F0kOk2gHsT5ItNzrXcW7RZ4M3VqP7jXsxqdF+9U9Nw== X-Zone-Loop: aaaeb6fda2177d8d3162e1ec5b3b614a674890ebc939 x-campaign-type: default x-transaction-id: fbf8b3c8-c264-4d38-bb08-a34e8c008020 x-swg-uid: 01-1d701107-8de0-4714-af1e-fe5806389a5c X-Mailer: Sweego Message-ID: <1776955848.8631fc262581453bbf619ec5b2062170.19dbad2753f000f373@vates.tech> x-swg-bid: 1776955848.8631fc262581453bbf619ec5b2062170.19dbad2753f000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Thierry Escande To: xen-devel@lists.xenproject.org Cc: Thierry Escande , Anthony PERARD , Juergen Gross , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [RFC PATCH v4 2/6] libxl: Refactor some PCI device handling functions Date: Thu, 23 Apr 2026 16:50:27 +0200 In-Reply-To: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> References: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> MIME-Version: 1.0 Content-Transfert-Encoding: 8bit X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.273e.6a96a3d650ac5123.19dbad273e8.28185d46eb971784=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955847657 X-purgate-ID: tlsNG-42698a/1776955852-0415DF3B-4715CB71/0/0 X-purgate-type: clean X-purgate-size: 5517 ---=Part.273e.6a96a3d650ac5123.19dbad273e8.28185d46eb971784=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable In order to support the new hotplug=3D0 option for PCI device passthrough, 3 functions used to manage the assignable PCI device list need to be made available from outside of libxl_pci=2Ec=2E This patch renames the function pciback_dev_is_assigned() as libxl__pciback_dev_is_assigned() and make it available internally=2E libxl__device_pci_assignable_add() is also exported internally=2E Finaly, libxl_pci_assignable() is renamed as libxl_device_pci_assignable() to match with other libxl_device_pci_*() APIs and exported in libxl=2Eh=2E Signed-off-by: Thierry Escande --- v4: new patch --- tools/include/libxl=2Eh | 1 + tools/libs/light/libxl_internal=2Eh | 5 +++++ tools/libs/light/libxl_pci=2Ec | 18 +++++++++--------- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/tools/include/libxl=2Eh b/tools/include/libxl=2Eh index 7c098edab6=2E=2Eefd2664a90 100644 --- a/tools/include/libxl=2Eh +++ b/tools/include/libxl=2Eh @@ -2666,6 +2666,7 @@ int libxl_device_pci_assignable_add(libxl_ctx *ctx, = libxl_device_pci *pci, int r int libxl_device_pci_assignable_remove(libxl_ctx *ctx, libxl_device_pci *= pci, int rebind); libxl_device_pci *libxl_device_pci_assignable_list(libxl_ctx *ctx, int *n= um); void libxl_device_pci_assignable_list_free(libxl_device_pci *list, int nu= m); +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci); =20 /* CPUID handling */ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* = str); diff --git a/tools/libs/light/libxl_internal=2Eh b/tools/libs/light/libxl_= internal=2Eh index b65e0064b9=2E=2Ee87500bf55 100644 --- a/tools/libs/light/libxl_internal=2Eh +++ b/tools/libs/light/libxl_internal=2Eh @@ -1729,6 +1729,11 @@ _hidden int libxl__device_pci_setdefault(libxl__gc = *gc, uint32_t domid, libxl_device_pci *pci, bool hotp= lug); _hidden bool libxl__is_igd_vga_passthru(libxl__gc *gc, const libxl_domain_config *d_conf= ig); +_hidden int libxl__pciback_dev_is_assigned(libxl__gc *gc, + libxl_device_pci *pci); +_hidden int libxl__device_pci_assignable_add(libxl__gc *gc, + libxl_device_pci *pci, + int rebind); =20 /* from libxl_dtdev */ =20 diff --git a/tools/libs/light/libxl_pci=2Ec b/tools/libs/light/libxl_pci= =2Ec index 49d272d0de=2E=2E5551abe0a2 100644 --- a/tools/libs/light/libxl_pci=2Ec +++ b/tools/libs/light/libxl_pci=2Ec @@ -686,7 +686,7 @@ out: return rc; } =20 -static int pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) +int libxl__pciback_dev_is_assigned(libxl__gc *gc, libxl_device_pci *pci) { char * spath; int rc; @@ -755,9 +755,9 @@ static int pciback_dev_unassign(libxl__gc *gc, libxl_d= evice_pci *pci) return 0; } =20 -static int libxl__device_pci_assignable_add(libxl__gc *gc, - libxl_device_pci *pci, - int rebind) +int libxl__device_pci_assignable_add(libxl__gc *gc, + libxl_device_pci *pci, + int rebind) { libxl_ctx *ctx =3D libxl__gc_owner(gc); unsigned dom, bus, dev, func; @@ -798,7 +798,7 @@ static int libxl__device_pci_assignable_add(libxl__gc = *gc, } =20 /* Check to see if it's already assigned to pciback */ - rc =3D pciback_dev_is_assigned(gc, pci); + rc =3D libxl__pciback_dev_is_assigned(gc, pci); if ( rc < 0 ) { return ERROR_FAIL; } @@ -913,7 +913,7 @@ static int libxl__device_pci_assignable_remove(libxl__= gc *gc, } =20 /* Unbind from pciback */ - if ( (rc =3D pciback_dev_is_assigned(gc, pci)) < 0 ) { + if ( (rc =3D libxl__pciback_dev_is_assigned(gc, pci)) < 0 ) { return ERROR_FAIL; } else if ( rc ) { pciback_dev_unassign(gc, pci); @@ -1509,7 +1509,7 @@ int libxl_device_pci_add(libxl_ctx *ctx, uint32_t do= mid, return AO_INPROGRESS; } =20 -static bool libxl_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) +bool libxl_device_pci_assignable(libxl_ctx *ctx, libxl_device_pci *pci) { libxl_device_pci *pcis; int num; @@ -1572,13 +1572,13 @@ void libxl__device_pci_add(libxl__egc *egc, uint32= _t domid, rc =3D libxl__device_pci_setdefault(gc, domid, pci, !starting); if (rc) goto out; =20 - if (pci->seize && !pciback_dev_is_assigned(gc, pci)) { + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pci)) { rc =3D libxl__device_pci_assignable_add(gc, pci, 1); if ( rc ) goto out; } =20 - if (!libxl_pci_assignable(ctx, pci)) { + if (!libxl_device_pci_assignable(ctx, pci)) { LOGD(ERROR, domid, "PCI device %x:%x:%x=2E%x is not assignable", pci->domain, pci->bus, pci->dev, pci->func); rc =3D ERROR_FAIL; --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.273e.6a96a3d650ac5123.19dbad273e8.28185d46eb971784=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:50:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:50:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292211.1570750 (Exim 4.92) (envelope-from ) id 1wFvON-00069G-Lz; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=KwW4d6fYi0KChvPkn7IffskRpGMBiOLh4S1NpTCLRGk=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=HE2coy3cU39TschWJRYdYq8wFbpLpp7h7EjePCUoWR0rV4oUOEoTjHY1F1hLx3ZX0I+TrptgP XA0G66L6CEBkO+Q1+Y0G6Ong8tZjL4GIBC97sd2Lrg8J0rPC/LXZtgBl0S8n9YDK9IMU3VEwPO9 IG38nZWhW7OPBEwspGaKDcvTvj4PN02VOoNzMTq63ftvcs33D3u2MdAzAIGJOVY1lU8hSre4PAd TrziJSI8psId/HM8NyUYBY9Zw1smMaGAxuwFDED7Q4fHh0ua9FeAm58JkoFn+N/btW7BZb4wXfx yYkAqQ9X/JrZB53lB7GYo1k5x5CTgm+g7p1xsa89I/RQ== X-Zone-Loop: 0eb424bdcabf1d73c22e5a825d30e8e81a2beb9141bf x-campaign-type: default x-transaction-id: ad9a1c9a-cb6a-4453-b392-fd440a969e31 x-swg-uid: 01-527627f9-4b39-4f05-b98a-58bfae657f9f X-Mailer: Sweego Message-ID: <1776955852.8631fc262581453bbf619ec5b2062170.19dbad285c5000f373@vates.tech> x-swg-bid: 1776955852.8631fc262581453bbf619ec5b2062170.19dbad285c5000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Thierry Escande To: xen-devel@lists.xenproject.org Cc: Thierry Escande , Anthony PERARD , Juergen Gross , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [RFC PATCH v4 3/6] libxl: Add libxl__device_pci_get_qapi_json() internal API Date: Thu, 23 Apr 2026 16:50:28 +0200 In-Reply-To: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> References: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> MIME-Version: 1.0 Content-Transfert-Encoding: 8bit X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.273f.2e8038414fb5c485.19dbad2845c.4007b31644528610=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955851868 X-purgate-ID: tlsNG-4011c0/1776955857-8127B8B7-A442E7B6/0/0 X-purgate-type: clean X-purgate-size: 3366 ---=Part.273f.2e8038414fb5c485.19dbad2845c.4007b31644528610=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable This function generates the qapi json object for a PCI device to be passthrough'd to a guest=2E With the new option hotplug=3D0 for PCI passthrough, device parameters will be passed using Qemu -device command line option=2E Since -device accepts qapi json string, this new function will be used to do so=2E The code that generates the json object comes from pci_add_qmp_device_add() which now also uses this new function=2E Signed-off-by: Thierry Escande --- v4: new patch --- tools/libs/light/libxl_internal=2Eh | 2 ++ tools/libs/light/libxl_pci=2Ec | 26 ++++++++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/tools/libs/light/libxl_internal=2Eh b/tools/libs/light/libxl_= internal=2Eh index e87500bf55=2E=2Eb6d764ad00 100644 --- a/tools/libs/light/libxl_internal=2Eh +++ b/tools/libs/light/libxl_internal=2Eh @@ -1734,6 +1734,8 @@ _hidden int libxl__pciback_dev_is_assigned(libxl__gc= *gc, _hidden int libxl__device_pci_assignable_add(libxl__gc *gc, libxl_device_pci *pci, int rebind); +_hidden libxl__json_object *libxl__device_pci_get_qapi_json(libxl__gc *gc= , + libxl_device_pci= *pci); =20 /* from libxl_dtdev */ =20 diff --git a/tools/libs/light/libxl_pci=2Ec b/tools/libs/light/libxl_pci= =2Ec index 5551abe0a2=2E=2E5004ca47d9 100644 --- a/tools/libs/light/libxl_pci=2Ec +++ b/tools/libs/light/libxl_pci=2Ec @@ -1098,16 +1098,10 @@ out: pci_add_dm_done(egc, pas, rc); /* must be last */ } =20 -static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +libxl__json_object *libxl__device_pci_get_qapi_json(libxl__gc *gc, + libxl_device_pci *pci= ) { - STATE_AO_GC(pas->aodev->ao); libxl__json_object *args =3D NULL; - int rc; - - /* Convenience aliases */ - libxl_domid domid =3D pas->domid; - libxl_device_pci *pci =3D &pas->pci; - libxl__ev_qmp *const qmp =3D &pas->qmp; =20 libxl__qmp_param_add_string(gc, &args, "driver", "xen-pci-passthrough"); @@ -1134,6 +1128,22 @@ static void pci_add_qmp_device_add(libxl__egc *egc,= pci_add_state *pas) if (pci->permissive) libxl__qmp_param_add_bool(gc, &args, "permissive", true); =20 + return args; +} + +static void pci_add_qmp_device_add(libxl__egc *egc, pci_add_state *pas) +{ + STATE_AO_GC(pas->aodev->ao); + libxl__json_object *args =3D NULL; + int rc =3D 0; + + /* Convenience aliases */ + libxl_domid domid =3D pas->domid; + libxl_device_pci *pci =3D &pas->pci; + libxl__ev_qmp *const qmp =3D &pas->qmp; + + args =3D libxl__device_pci_get_qapi_json(gc, pci); + qmp->ao =3D pas->aodev->ao; qmp->domid =3D domid; qmp->payload_fd =3D -1; --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.273f.2e8038414fb5c485.19dbad2845c.4007b31644528610=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:51:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:51:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292212.1570757 (Exim 4.92) (envelope-from ) id 1wFvOO-0006C1-3C; Thu, 23 Apr 2026 14:51:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292212.1570757; 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boundary="-=Part.2740.c5deada9ef7a8812.19dbad290c4.414c53236d9cbe01=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955855045 X-purgate-ID: tlsNG-4011c0/1776955857-46D708B7-FA9CBAE9/0/0 X-purgate-type: clean X-purgate-size: 3323 ---=Part.2740.c5deada9ef7a8812.19dbad290c4.414c53236d9cbe01=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable The function libxl__json_object_to_json() returns a json object as string in a pretty format=2E With support for the new PCI device passthrough option hotplug=3D0, the function will be used to generate the json string passed to qemu -device command line parameter, but the string needs to be in plain format, i=2Ee=2E without carriage return or ta= b characters=2E This patch adds a 'pretty' parameter to the function to control the output string format=2E Signed-off-by: Thierry Escande --- v4: new patch --- tools/libs/light/libxl_internal=2Eh | 5 +++-- tools/libs/light/libxl_json=2Ec | 11 +++++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/tools/libs/light/libxl_internal=2Eh b/tools/libs/light/libxl_= internal=2Eh index b6d764ad00=2E=2Eb87959e44a 100644 --- a/tools/libs/light/libxl_internal=2Eh +++ b/tools/libs/light/libxl_internal=2Eh @@ -2270,10 +2270,11 @@ _hidden libxl__json_object *libxl__json_parse(libx= l__gc *gc_opt, const char *s); =20 /* `args` may be NULL */ _hidden char *libxl__json_object_to_json(libxl__gc *gc, - const libxl__json_object *args); + const libxl__json_object *args, + bool pretty); /* Always return a valid string, but invalid json on error=2E */ #define JSON(o) \ - (libxl__json_object_to_json(gc, (o)) ? : "") + (libxl__json_object_to_json(gc, (o), true) ? : "= ") =20 /* Based on /local/domain/$domid/dm-version xenstore key */ _hidden int libxl__device_model_version_running(libxl__gc *gc, uint32_t d= omid); diff --git a/tools/libs/light/libxl_json=2Ec b/tools/libs/light/libxl_json= =2Ec index 68f36901c2=2E=2Ec566ec83ff 100644 --- a/tools/libs/light/libxl_json=2Ec +++ b/tools/libs/light/libxl_json=2Ec @@ -1527,7 +1527,8 @@ out: #endif =20 char *libxl__json_object_to_json(libxl__gc *gc, - const libxl__json_object *args) + const libxl__json_object *args, + bool pretty) { #ifdef HAVE_LIBJSONC const char *buf; @@ -1542,7 +1543,9 @@ char *libxl__json_object_to_json(libxl__gc *gc, if (rc) goto out; =20 - buf =3D json_object_to_json_string_ext(root, JSON_C_TO_STRING_PRETTY)= ; + buf =3D json_object_to_json_string_ext(root, pretty ? + JSON_C_TO_STRING_PRETTY : + JSON_C_TO_STRING_PLAIN); if (!buf) goto out; =20 @@ -1566,6 +1569,10 @@ out: if (!hand) return NULL; =20 +#if HAVE_YAJL_V2 + yajl_gen_config(hand, yajl_gen_beautify, pretty); +#endif + rc =3D libxl__json_object_to_yajl_gen(gc, hand, args); if (rc) goto out; --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.2740.c5deada9ef7a8812.19dbad290c4.414c53236d9cbe01=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:51:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:51:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292216.1570769 (Exim 4.92) (envelope-from ) id 1wFvOT-0006ie-Cq; Thu, 23 Apr 2026 14:51:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292216.1570769; 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a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=Z1+eytwSMTKXppL/bkeDgKPsP7+rKwCxiKHDiZ0OLRs=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=alK7gqYGRD+HqkxLviBMDg+XTAToMGJ0ZzJFEK03pnOlIpiM5UyHAYHjDYW4SXKwBvTN9Yodn uGnH11u28ynt9a4jAwuuD5cYd0gxwkwjoeyYvJ+ybEeUyPJcEFqOtcVvBZ0wa3GH6RhBul/6dMR CkHF0y0tj/9HTvvsgNzALNXc0UFYIaZ+tIWpVUXPnDCcLnvr4qsLE89V4n8iEiWAWVpRuDECOab YzZOXYiBVFIvBsa4DfoAy94d+0nvssebwUoupPDPt/Yh2Rs8X81+X4J6G8LEDtcB01P780VLw0Q zROQ3+Od2J3hCHe0CYci2M5p3qxI6dQAacq7PvtgZCMg== X-Zone-Loop: 6538666f2d8b81dc348812ba600f25a9bba8957c5f5e x-campaign-type: default x-transaction-id: f53b331b-f1f9-4a35-91a8-33d1289c8542 x-swg-uid: 01-c33a206f-094b-4b05-a72d-b019a2809139 X-Mailer: Sweego Message-ID: <1776955859.8631fc262581453bbf619ec5b2062170.19dbad2a232000f373@vates.tech> x-swg-bid: 1776955859.8631fc262581453bbf619ec5b2062170.19dbad2a232000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Thierry Escande To: xen-devel@lists.xenproject.org Cc: Thierry Escande , Anthony PERARD , Juergen Gross , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [RFC PATCH v4 5/6] libxl: Allow PCI device passthrough using -device Qemu command line Date: Thu, 23 Apr 2026 16:50:30 +0200 In-Reply-To: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> References: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> MIME-Version: 1.0 Content-Transfert-Encoding: 8bit X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2741.19abcf34cab5d289.19dbad2a0c7.3e37f28d3be2e66=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955859143 X-purgate-ID: tlsNG-ef75cf/1776955863-AE36CC48-15548791/0/0 X-purgate-type: clean X-purgate-size: 5173 ---=Part.2741.19abcf34cab5d289.19dbad2a0c7.3e37f28d3be2e66=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable This change makes use of the new option 'hotplug' for host PCI devices passthrough'd to the guest=2E If hotplug=3D0 is used in the pci device configuration table, the device will be attached to the guest using the Qemu command line as '-device xen-pci-passthrough,hostaddr=3D=2E=2E=2E' The host device configuration is passed to the -device option as a json array, just like it's done for hotplug using QMP=2E The json array is created by using libxl__device_pci_get_qapi_json() introduced by the previous patch=2E Then, instead of sending the 'device_add' command, the device_add callback is called to perform the 'query-pci' check to make sure the passthrough'd device is present=2E In the same way at shutdown, the device is not removed using QMP and only the pci_remove_done() function is called=2E As with QMP, the use of the 'hotplug=3D0' option honors the 'seize' option by adding the PCI device to the assignable list if needed=2E This mimics what is done in libxl__device_pci_add() with regards to seize option and the assignable PCI device list=2E This allows to display a proper error message if the device is not assignable before Qemu starts=2E Signed-off-by: Thierry Escande --- Changes in v2: - Add support for YAJL json parser Changes in v3: - Move code block for device command line parameters creation to a correct place=2E - Better handling of PCI device assignation check to display the correct error message if the device is not assignable=2E Changes in v4: - Move function refactoring parts into their own patches - Use libxl__json_object_to_json() that can now return plain json strings --- tools/libs/light/libxl_dm=2Ec | 33 +++++++++++++++++++++++++++++++++ tools/libs/light/libxl_pci=2Ec | 13 ++++++++++++- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/tools/libs/light/libxl_dm=2Ec b/tools/libs/light/libxl_dm=2Ec index 511ec76a65=2E=2Efb0aeea640 100644 --- a/tools/libs/light/libxl_dm=2Ec +++ b/tools/libs/light/libxl_dm=2Ec @@ -1798,6 +1798,39 @@ static int libxl__build_device_model_args_new(libxl= __gc *gc, break; } =20 + if (guest_config->num_pcidevs) { + libxl_device_pci *pci; + libxl__json_object *qmp_json; + char *json_str; + + for (i =3D 0; i < guest_config->num_pcidevs; i++) { + pci =3D &guest_config->pcidevs[i]; + + if (pci->hotplug) + continue; + + if (pci->seize && !libxl__pciback_dev_is_assigned(gc, pci= )) { + rc =3D libxl__device_pci_assignable_add(gc, pci, 1); + if (rc) + return rc; + } + + if (!libxl_device_pci_assignable(libxl__gc_owner(gc), pci= )) { + LOGD(ERROR, guest_domid, "PCI device %x:%x:%x=2E%x is= not assignable", + pci->domain, pci->bus, pci->dev, pci->func); + return ERROR_FAIL; + } + + qmp_json =3D libxl__device_pci_get_qapi_json(gc, pci); + + json_str =3D libxl__json_object_to_json(gc, qmp_json, fal= se); + if (!json_str) + return ERROR_NOMEM; + + flexarray_vappend(dm_args, "-device", json_str, NULL); + } + } + if (state->dm_runas) { if (qemu_opts->have_runwith_user) { flexarray_append_pair(dm_args, "-run-with", diff --git a/tools/libs/light/libxl_pci=2Ec b/tools/libs/light/libxl_pci= =2Ec index 5004ca47d9=2E=2Ef5216f6b33 100644 --- a/tools/libs/light/libxl_pci=2Ec +++ b/tools/libs/light/libxl_pci=2Ec @@ -1148,7 +1148,10 @@ static void pci_add_qmp_device_add(libxl__egc *egc,= pci_add_state *pas) qmp->domid =3D domid; qmp->payload_fd =3D -1; qmp->callback =3D pci_add_qmp_device_add_cb; - rc =3D libxl__ev_qmp_send(egc, qmp, "device_add", args); + if (pci->hotplug) + rc =3D libxl__ev_qmp_send(egc, qmp, "device_add", args); + else + pci_add_qmp_device_add_cb(egc, qmp, NULL, 0); if (rc) goto out; return; =20 @@ -1830,6 +1833,14 @@ static void do_pci_remove(libxl__egc *egc, pci_remo= ve_state *prs) libxl_domain_type type =3D libxl__domain_type(gc, domid); libxl_device_pci *pci =3D &prs->pci; int rc, num; + + /* Passthrough'd device has been passed to Qemu command line so there= is + * no need to remove it via QMP */ + if (!pci->hotplug) { + pci_remove_done(egc, prs, 0); + return; + } + pcis =3D libxl_device_pci_list(ctx, domid, &num); if (!pcis) { rc =3D ERROR_FAIL; --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.2741.19abcf34cab5d289.19dbad2a0c7.3e37f28d3be2e66=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 14:51:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 14:51:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292217.1570774 (Exim 4.92) (envelope-from ) id 1wFvOT-0006mY-PS; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=ekNR1/eBd9VQKAzJYZOyOmAkA2MA78ZmCGizisZKN0M=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=C3PVivYSKPbRBKJNckmf7OY89A4QHKYhJKt8lwoqIB0Ut8UDzwOR2MYKSjCMx4Uz5C7vJ48NG RNfewvskrxW+RavVx0H7fBBIRiXzhL/JApXOk8rSWUGrCrB7FnMnbCADFfU1QkKrAl4sP8hszA/ 0BVQD1ZIZwTKit5DtsAIZH6bvpsoDyjSA6kDJEg5+WopJqDbIqUtGYxMbOT8QFZbD1WG+ZOG0Gy tJxMTSlOfPss5N7XcpQqkscmsY7ZU4EweXK6/0z48mM4Memu5gjXuRQDZ+QIOyhcghtbucLtzQ4 4jKOj9BK7EfJbQ+BgPUzh+NrXmM1S0by22zR9HwXYmyw== X-Zone-Loop: da510dc4bdea08aa68329b8112877095630cd5904ffc x-campaign-type: default x-transaction-id: 2fcc7fec-678c-437b-9538-7259920244f3 x-swg-uid: 01-82fc978a-d581-44e4-9ea4-7620336eb78e X-Mailer: Sweego Message-ID: <1776955863.8631fc262581453bbf619ec5b2062170.19dbad2afcd000f373@vates.tech> x-swg-bid: 1776955863.8631fc262581453bbf619ec5b2062170.19dbad2afcd000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Thierry Escande To: xen-devel@lists.xenproject.org Cc: Thierry Escande , Anthony PERARD , Juergen Gross , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= Subject: [RFC PATCH v4 6/6] docs: provide description for pci hotplug option Date: Thu, 23 Apr 2026 16:50:31 +0200 In-Reply-To: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> References: <1776955586.8631fc262581453bbf619ec5b2062170.19dbace7684000f373@vates.tech> MIME-Version: 1.0 Content-Transfert-Encoding: 8bit X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2742.424e6f0f84fb42ae.19dbad2ae7d.85e0adc7420a1022=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776955862653 X-purgate-ID: tlsNG-ef75cf/1776955864-AD165C48-992AB3EE/0/0 X-purgate-type: clean X-purgate-size: 2304 ---=Part.2742.424e6f0f84fb42ae.19dbad2ae7d.85e0adc7420a1022=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable This patch adds description for the 'hotplug' PCI option, allowing devices to be attached to the guest using the legacy QMP hotplug mechanism or by passing them to the Qemu command line using '-device'=2E Signed-off-by: Thierry Escande --- v2: no change v3: no change v4: no change --- docs/man/xl-pci-configuration=2E5=2Epod | 17 +++++++++++++++++ docs/man/xl=2Ecfg=2E5=2Epod=2Ein | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/docs/man/xl-pci-configuration=2E5=2Epod b/docs/man/xl-pci-con= figuration=2E5=2Epod index 0691f06ad3=2E=2E8b664173cb 100644 --- a/docs/man/xl-pci-configuration=2E5=2Epod +++ b/docs/man/xl-pci-configuration=2E5=2Epod @@ -166,6 +166,23 @@ dom0 without confirmation=2E Please use with care=2E =20 =3Dback =20 +=3Ditem B=3DI + +=3Dover 4 + +=3Ditem Description + +Tells L to use QMP hotplug mechanism to attach assignable device t= o +the guest, or to pass it via Qemu command line using +'B<-device xen-pci-passthrough,=2E=2E=2E>'=2E The default is to use the l= egacy QMP +mechanism=2E + +=3Ditem Default Value + +1 + +=3Dback + =3Ditem B=3DI =20 =3Dover 4 diff --git a/docs/man/xl=2Ecfg=2E5=2Epod=2Ein b/docs/man/xl=2Ecfg=2E5=2Epo= d=2Ein index 2f77016ecf=2E=2E09f59f9b9c 100644 --- a/docs/man/xl=2Ecfg=2E5=2Epod=2Ein +++ b/docs/man/xl=2Ecfg=2E5=2Epod=2Ein @@ -1236,6 +1236,12 @@ B<(HVM only)> Changes the default value of B for all PCI devices passed through to this VM=2E See B above=2E =20 +=3Ditem B + +B<(HVM only)> Changes the default value of B for all PCI +devices passed through to this VM=2E See L for +more details=2E + =3Ditem B =20 Enable graphics device PCI passthrough=2E This option makes an assigned --=20 2=2E53=2E0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.2742.424e6f0f84fb42ae.19dbad2ae7d.85e0adc7420a1022=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 15:03:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 15:03:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292277.1570787 (Exim 4.92) (envelope-from ) id 1wFvaK-0001yA-OU; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=u2ZCrL3FKsedINaHM/L0MISkunileTPXOhM7WtGyyCI=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=GxUqq3pqEIxr19DoVYDsunJvab8rKl3IEgwhSvufk8DsZb30nKexNHbGYcZgiT9KRiYue3RS9 wctewyYP+PfriuYmIVGdCpCU7D9LFAOtDxjuQKtDBzDqJJ9VHEz3uFhWH2TTmsMEw97MyDEMzzp A9DBXNvxHDvBfduqup/W0S/nnD7brl/qgg3/7UIHam6oiQebu/7ft4hbK5URoIi6z/2JgIQQ07l 71UQwkMyO3USpqYPi4A932qDaDCbVnCNphb3Qx1JnCfBarrhdMiq04lG34bDTvuptaK8PLKb4X3 yr070KX2k1Ue9/Jx8oTjT26G4JKvelj6+XqHptTjKVZA== X-Zone-Loop: e65913d91b9bd9cf5a914c69dd43cca2b55168f4778c x-campaign-type: default x-transaction-id: d0af0e29-cfb6-4b71-8d0d-06da5f935818 x-swg-uid: 01-5586f84c-bb51-4f02-9023-2cf5e956083e X-Mailer: Sweego Message-ID: <1776956594.8631fc262581453bbf619ec5b2062170.19dbaddd9f8000f373@vates.tech> x-swg-bid: 1776956594.8631fc262581453bbf619ec5b2062170.19dbaddd9f8000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 23 Apr 2026 17:03:12 +0200 From: Anthony PERARD To: Elliott Mitchell Cc: xen-devel@lists.xenproject.org Subject: Re: [PATCH] tools: remove setup_physical_bridge_port() function References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.274c.307635f7b96b90a8.19dbaddd0db.5c662c9c97ee5fde=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776956592347 X-purgate-ID: tlsNG-c201ff/1776956598-E13A0443-1747D564/0/0 X-purgate-type: clean X-purgate-size: 897 ---=Part.274c.307635f7b96b90a8.19dbaddd0db.5c662c9c97ee5fde=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Mon, Mar 16, 2026 at 01:11:42PM -0700, Elliott Mitchell wrote: > Only the setup_virtual_bridge_port() function was used=2E As such merge > that with _setup_bridge_port() and leave that as the remaining function= =2E >=20 > Signed-off-by: Elliott Mitchell Do you mind if I add the following to the commit message? The last user of setup_physical_bridge_port() was removed in 9fabe55939a8 ("tools/hotplug: Remove network-*")=2E With that: Acked-by: Anthony PERARD Thanks, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.274c.307635f7b96b90a8.19dbaddd0db.5c662c9c97ee5fde=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 15:20:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 15:20:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292301.1570797 (Exim 4.92) (envelope-from ) id 1wFvqb-0005eQ-3v; Thu, 23 Apr 2026 15:20:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292301.1570797; Thu, 23 Apr 2026 15:20:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFvqa-0005eJ-Vy; Thu, 23 Apr 2026 15:20:08 +0000 Received: by outflank-mailman (input) for mailman id 1292301; Thu, 23 Apr 2026 15:20:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wFvqY-0005YN-P0 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 15:20:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFvqY-004Oa5-5o for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 17:20:06 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea38a1-2eae-0a2a0a5409dd-0a2a4505d6ec-28 for ; Thu, 23 Apr 2026 17:20:06 +0200 Received: from [209.85.208.169] (helo=mail-lj1-f169.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea38a5-aaa8-0a2a45050019-d155d0a9e077-3 for ; Thu, 23 Apr 2026 17:20:06 +0200 Received: by mail-lj1-f169.google.com with SMTP id 38308e7fff4ca-38e9653b580so72752781fa.2 for ; Thu, 23 Apr 2026 08:20:06 -0700 (PDT) Received: from [192.168.1.6] (user-109-243-69-121.play-internet.pl. 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This is an issue for > guests running on Q35 chipset (preliminary support posted at [1]) since the > Q35 PCI root bus does not support hotplug. Devices could be hotplugged to > a secondary PCI bus but Xen only support 1 PCI bus for now. > > The 'hotplug' option allows to control how devices are attached to the > guest, either by using the legacy QMP mechanism (this is the default) or by > passing them directly to the Qemu command line using xen-pci-passthrough > device. > > Example usage in cfg file: > pci = [ "00:03.0,seize=1,hotplug=0" ] > > Since Qemu -device option accepts parameters in json format, this > patchset adds a new internal function libxl__device_pci_get_qapi_json() that > generates the device json object used for both QMP hotplug and command line > passing. > > Also, to handle the assignable PCI device list, the function > libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and is > made available from libxl.h for access in libxl_dm.c. 2 other functions are > also exported internally: libxl__pciback_dev_is_assigned() and > libxl__device_pci_assignable_add(). > > This has been successfully tested on Xen 4.22-dev and Qemu 10.0 running > Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk. > Disabling the hotplug mechanism might be made mandatory for Q35 machines > later, once Q35 support is merged upstream. > > [1] https://lore.kernel.org/xen-devel/20260313163455.790692-1-thierry.escande@vates.tech/ > > Changes in v2: > - Add support for YAJL json parser > > Changes in v3: > - Move code block of device command line parameters creation > - Better handling of pci device assignation > > Changes in v4: > - Split the refactoring parts of the 2nd patch > - Extend libxl__json_object_to_json() and use it to generate the qapi json > string > > Thierry Escande (6): > xl: Add an hotplug option for PCI device passthrough > libxl: Refactor some PCI device handling functions > libxl: Add libxl__device_pci_get_qapi_json() internal API > libxl: Extend libxl__json_object_to_json() prototype > libxl: Allow PCI device passthrough using -device Qemu command line > docs: provide description for pci hotplug option > > docs/man/xl-pci-configuration.5.pod | 17 +++++++++ > docs/man/xl.cfg.5.pod.in | 6 +++ > tools/include/libxl.h | 1 + > tools/libs/light/libxl_dm.c | 33 +++++++++++++++++ > tools/libs/light/libxl_internal.h | 12 +++++- > tools/libs/light/libxl_json.c | 11 +++++- > tools/libs/light/libxl_pci.c | 57 ++++++++++++++++++++--------- > tools/libs/light/libxl_types.idl | 1 + > tools/libs/util/libxlu_pci.c | 2 + > tools/xl/xl_parse.c | 5 +++ > 10 files changed, 123 insertions(+), 22 deletions(-) > I think we also want to add an item to CHANGELOG.md that it is possible to passthrough PCI device via QEMU command line. Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Thu Apr 23 15:59:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 15:59:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292354.1570826 (Exim 4.92) (envelope-from ) id 1wFwSD-0003AS-5i; Thu, 23 Apr 2026 15:59:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292354.1570826; Thu, 23 Apr 2026 15:59:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwSD-0003AL-1d; Thu, 23 Apr 2026 15:59:01 +0000 Received: by outflank-mailman (input) for mailman id 1292354; Thu, 23 Apr 2026 15:58:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwSB-0003AF-D4 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 15:58:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFwS9-001RvN-U8 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 17:58:58 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea41a6-e002-0a2a0a5209dd-0a2a450bc83c-32 for ; Thu, 23 Apr 2026 17:58:57 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea41c0-212f-0a2a450b0019-d561b338e004-3 for ; Thu, 23 Apr 2026 17:58:56 +0200 Received: from maestria.local.igalia.com ([192.168.10.14] helo=mail.igalia.com) by fanzine2.igalia.com with esmtps (Cipher TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wFwRl-001AbI-Gv; Thu, 23 Apr 2026 17:58:32 +0200 Received: from webmail.service.igalia.com ([192.168.21.45]) by mail.igalia.com with esmtp (Exim) id 1wFwRi-002EgO-KM; Thu, 23 Apr 2026 17:58:32 +0200 Received: from localhost ([127.0.0.1] helo=webmail.igalia.com) by webmail.service.igalia.com with esmtp (Exim 4.98.2) (envelope-from ) id 1wFwRh-00000000VIN-47KH; Thu, 23 Apr 2026 17:58:30 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Content-Transfer-Encoding:Content-Type:Message-ID:References:In-Reply-To:Subject:Cc:To:From:Date:MIME-Version" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:Message-ID:References: In-Reply-To:Subject:Cc:To:From:Date:MIME-Version:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=xdei9ZM7WTccU6AfBRlzsKRTYKtjrdEquFKjWHLZr4Y=; b=iTiYf3Nzj5Np2xldc79/j65JLs VjsDJrQ0MdOSXjVwmYndAMc5CnAJyL/qhkfzeFgVSH9oP/iuNoZrJlGwDBRnoNdn3tdnvoys5Ergx QAYzIVZiJU5wlHxM9zjXdUkms7dq3RA9wS1oGADO5CXHpkPzA7wmZrUNtIjQS/xz/3bTCsTFqLiGj bl7gSF67h3l35cYri9xNAn8Sb6Vod1++ofxhxBe3pltxcKtmqMDZ5odZ8Umc1pGyQ23Zw3xEWfuAF yjtpFRvwqnJ0LAc/o5PN2wHBjE3lHZtIU2q72C4U67i5xCkmksAu0QlUoCXis2FXMEERxuMVFGHWa ZvBmMFsQ==; MIME-Version: 1.0 Date: Thu, 23 Apr 2026 12:58:30 -0300 From: Mauricio Faria de Oliveira To: David Laight Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky , kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Subject: Re: [PATCH 1/3] x86/asm, x86/boot: Expose inline memcmp In-Reply-To: <20260422215441.4204c142@pumpkin> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> <20260422-pvh-kasan-inline-v1-1-7e6194344c92@igalia.com> <20260422215441.4204c142@pumpkin> Message-ID: <324ef97b16f52e0ccc72f6381d1b5dd2@igalia.com> X-Sender: mfo@igalia.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Report: NO, Score=-2.2, Tests=ALL_TRUSTED=-3,BAYES_50=0.8 X-Spam-Score: -21 X-Spam-Bar: -- X-purgate-ID: tlsNG-42698a/1776959937-05D6FF3B-89058958/0/0 X-purgate-type: clean X-purgate-size: 3135 On 2026-04-22 17:54, David Laight wrote: > On Wed, 22 Apr 2026 17:07:45 -0300 > Mauricio Faria de Oliveira wrote: > >> Move the inline memcmp function, currently only available to boot code >> (boot/string.c), into the header with similar inline string functions >> (include/asm/string.h) so it may be reused. > > This needs a comment/warning that it is incompatible with normal memcmp() > because it only returns 0/1 not -1/0/1. > Most callers don't care. Thanks for catching and suggesting this. I can also change it to -1/0/1 in a later patch, to keep v2 only a fix and split a behavior change, with something like this (lightly tested): static __always_inline int __inline_memcmp(const void *s1, const void *s2, size_t len) { bool above, below; asm("repe cmpsb" : "+S" (s1), "+D" (s2), "+c" (len), "=@cca" (above), "=@ccb" (below)); return above - below; } cheers, > > David > > >> >> Add a _SETUP guard in string.h so not to include the 32/64-bit specific >> string headers in boot/ code (16-bit, real mode) and avoid build errors. >> >> Signed-off-by: Mauricio Faria de Oliveira >> --- >> arch/x86/boot/string.c | 6 ++---- >> arch/x86/include/asm/string.h | 11 +++++++++++ >> 2 files changed, 13 insertions(+), 4 deletions(-) >> >> diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c >> index b25c6a9303b7314d5caf5c9306239811705294fe..bbee78637b349e42e9281d8df50d89d48f4490b9 100644 >> --- a/arch/x86/boot/string.c >> +++ b/arch/x86/boot/string.c >> @@ -15,6 +15,7 @@ >> #include >> #include >> #include >> +#include >> #include "ctype.h" >> #include "string.h" >> >> @@ -31,10 +32,7 @@ >> >> int memcmp(const void *s1, const void *s2, size_t len) >> { >> - bool diff; >> - asm("repe cmpsb" >> - : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); >> - return diff; >> + return __inline_memcmp(s1, s2, len); >> } >> >> /* >> diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h >> index 9cb5aae7fba9ffcf0f5af8f939d30467750ccaa9..736a6f6a31f0a68281b4f17415aba0fcd95dc228 100644 >> --- a/arch/x86/include/asm/string.h >> +++ b/arch/x86/include/asm/string.h >> @@ -2,11 +2,13 @@ >> #ifndef _ASM_X86_STRING_H >> #define _ASM_X86_STRING_H >> >> +#ifndef _SETUP >> #ifdef CONFIG_X86_32 >> # include >> #else >> # include >> #endif >> +#endif >> >> static __always_inline void *__inline_memcpy(void *to, const void *from, size_t len) >> { >> @@ -29,4 +31,13 @@ static __always_inline void *__inline_memset(void *s, int v, size_t n) >> return ret; >> } >> >> +static __always_inline int __inline_memcmp(const void *s1, const void *s2, size_t len) >> +{ >> + bool diff; >> + >> + asm("repe cmpsb" >> + : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); >> + return diff; >> +} >> + >> #endif /* _ASM_X86_STRING_H */ >> -- Mauricio From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:01:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:01:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292366.1570833 (Exim 4.92) (envelope-from ) id 1wFwUW-0005Dt-Gb; Thu, 23 Apr 2026 16:01:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292366.1570833; Thu, 23 Apr 2026 16:01:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwUW-0005Dm-Dh; Thu, 23 Apr 2026 16:01:24 +0000 Received: by outflank-mailman (input) for mailman id 1292366; Thu, 23 Apr 2026 16:01:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwUV-0005De-9S for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 16:01:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wFwUU-004ruX-Lb for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 18:01:22 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea4248-2eae-0a2a0a5409dd-0a2a450ba496-42 for ; Thu, 23 Apr 2026 18:01:22 +0200 Received: from [209.85.208.49] (helo=mail-ed1-f49.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea4252-212f-0a2a450b0019-d155d031cc9e-3 for ; Thu, 23 Apr 2026 18:01:22 +0200 Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-678a1642a81so249340a12.0 for ; Thu, 23 Apr 2026 09:01:22 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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Peter Anvin" , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> <20260422-pvh-kasan-inline-v1-2-7e6194344c92@igalia.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <20260422-pvh-kasan-inline-v1-2-7e6194344c92@igalia.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------ic78VdLEcBJ5ydvhV0E0ZuV9" X-purgate-ID: tlsNG-42698a/1776960082-24AB5F3B-DC605153/0/0 X-purgate-type: clean X-purgate-size: 7309 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------ic78VdLEcBJ5ydvhV0E0ZuV9 Content-Type: multipart/mixed; boundary="------------oUcxIFxMLsDxx0Ywcue6L02I"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Mauricio Faria de Oliveira , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Message-ID: Subject: Re: [PATCH 2/3] x86/cpuid: fix unbootable VMs by really inlining memcmp() in hypervisor_cpuid_base() References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> <20260422-pvh-kasan-inline-v1-2-7e6194344c92@igalia.com> In-Reply-To: <20260422-pvh-kasan-inline-v1-2-7e6194344c92@igalia.com> --------------oUcxIFxMLsDxx0Ywcue6L02I Content-Type: multipart/mixed; boundary="------------c4u0C8tAi4Irszf1o7RDgbLt" --------------c4u0C8tAi4Irszf1o7RDgbLt Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: base64 T24gMjIuMDQuMjYgMjI6MDcsIE1hdXJpY2lvIEZhcmlhIGRlIE9saXZlaXJhIHdyb3RlOg0K PiBFdmVuIHdpdGggX19idWlsdGluIHRoZSBjb21waWxlciBtYXkgZGVjaWRlIHRvIHVzZSB0 aGUgb3V0IG9mIGxpbmUgZnVuY3Rpb24NCj4gaW5zdGVhZCBvZiB0aGUgaW5saW5lIGltcGxl bWVudGF0aW9uLg0KPiANCj4gVGhlIGV4aXN0aW5nIGNvZGUgaXMgYnJva2VuIHdpdGggZ2Nj LTE0LzE1IGJ1dCBub3QgZ2NjLTEyLzEzIChVYnVudHUgMjUuMTApDQo+IGFuZCB2bWxpbnV4 IG5vIGxvbmdlciBib290cyB3aXRoIENPTkZJR19QVkggaWYgQ09ORklHX0tBU0FOX0dFTkVS SUMgaXMgc2V0Lg0KPiANCj4gRm9yIHRlc3RpbmcgcHVycG9zZXMsIGlmIHRoZSBzaXplIGFy Z3VtZW50IGlzIHJlZHVjZWQgZnJvbSAxMiB0byA4IHRoZW4gdGhlDQo+IGNvbXBpbGVyIGRl Y2lkZXMgdG8gdXNlIHRoZSBpbmxpbmUgaW1wbGVtZW50YXRpb247IHRoYXQgc2hvd3MgcmVz dWx0cyB2YXJ5Lg0KPiANCj4gU3dpdGNoIHRoZSBidWlsdGluIHRvIHRoZSBpbmxpbmUgaW1w bGVtZW50YXRpb24gdG8gYWRkcmVzcyBpdC4NCj4gDQo+IEZpeGVzOiA0MTZhMzNjOWFmY2Ug KCJ4ODYvY3B1OiBmaXggdW5ib290YWJsZSBWTXMgYnkgaW5saW5pbmcgbWVtY21wKCkgaW4g aHlwZXJ2aXNvcl9jcHVpZF9iYXNlKCkiKQ0KPiBTaWduZWQtb2ZmLWJ5OiBNYXVyaWNpbyBG YXJpYSBkZSBPbGl2ZWlyYSA8bWZvQGlnYWxpYS5jb20+DQoNClJldmlld2VkLWJ5OiBKdWVy Z2VuIEdyb3NzIDxqZ3Jvc3NAc3VzZS5jb20+DQoNCg0KSnVlcmdlbg0K --------------c4u0C8tAi4Irszf1o7RDgbLt Content-Type: application/pgp-keys; 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Peter Anvin" , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> <20260422-pvh-kasan-inline-v1-3-7e6194344c92@igalia.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <20260422-pvh-kasan-inline-v1-3-7e6194344c92@igalia.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------Kv9C1D7bZKvIbKJ9eg5VEh4P" X-purgate-ID: tlsNG-c201ff/1776960116-2B961443-E36E6B2B/0/0 X-purgate-type: clean X-purgate-size: 7157 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------Kv9C1D7bZKvIbKJ9eg5VEh4P Content-Type: multipart/mixed; boundary="------------DZ3PNP0k2SgWR8Urff2c36wG"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Mauricio Faria de Oliveira , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. 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FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; TAGGED_RCPT(0.00)[]; FREEMAIL_CC(0.00)[suse.com,gmail.com,xenproject.org]; RCVD_TLS_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Spam-Flag: NO X-purgate-ID: tlsNG-42698a/1776960439-7E971F3B-BF777008/0/0 X-purgate-type: clean X-purgate-size: 725 Signed-off-by: Juergen Gross --- CHANGELOG.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index bb41d89997..ce46020dbd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) ### Added - Support for per-domain Xenstore quota in C xenstored (includes xenstore-stubdom), libxl and xl. + - Support for Xenstore watch depth feature in C xenstored (includes + xenstore-stubdom). - On x86: - Support for Bus Lock Threshold on AMD Zen5 and later CPUs, used by Xen to mitigate (by rate-limiting) the system wide impact of an HVM guest -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:11:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:11:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292396.1570860 (Exim 4.92) (envelope-from ) id 1wFweI-0008MZ-UM; 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Instead, clear the GIF when injecting a VMEXIT to match what hardware does. Fixes: 9a779e4fc161 ("Implement SVM specific part for Nested Virtualization") Signed-off-by: Ross Lagerwall --- xen/arch/x86/hvm/svm/nestedsvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c index ef6fa5d23b67..f89b087a1155 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -733,9 +733,9 @@ nsvm_vcpu_vmexit_inject(struct vcpu *v, struct cpu_user_regs *regs, struct vmcb_struct *vmcb = v->arch.hvm.svm.vmcb; if ( vmcb->_vintr.fields.vgif_enable ) - ASSERT(vmcb->_vintr.fields.vgif == 0); + vmcb->_vintr.fields.vgif = 0; else - ASSERT(svm->ns_gif == 0); + nestedsvm_vcpu_clgi(v); ns_vmcb = nv->nv_vvmcx; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:11:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:11:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292399.1570870 (Exim 4.92) (envelope-from ) id 1wFweZ-0000Dj-75; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5910da64-d40a-494e-bc72-08dea1530161 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2026 16:11:41.0640 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Z0kNf7Kr0nte2/Oa7exV9hEqVI06snm+PTCOzTeJoRZmIp0hgWsfKKOh3OvBGZ0FemFD59weZp6+NWOdZX6yBwpr/4nmIUbeQuMqXyzHVrg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6752 X-purgate-ID: tlsNG-42698a/1776960705-7E971F3B-C2EEDB92/0/0 X-purgate-type: clean X-purgate-size: 2596 This series fixes a common bug pattern found in several Xen UART drivers: when setup_irq() fails during post-IRQ initialization, drivers log the error but continue executing and unconditionally unmask hardware interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Patch 1, originally submitted as a standalone fix in v1, addresses the issue in the SCIF driver and moves the hardware error-flag clearing sequence to before the setup_irq() call so that stale error bits are cleared unconditionally. Patches 2-4 apply the same early-return fix to the pl011, cadence-uart, and exynos4210-uart drivers. The pl011 and cadence-uart drivers additionally had a positive-condition IRQ guard (if uart->irq > 0) that could fall through to the interrupt unmask even when no valid IRQ was provided. Both are restructured to use the early-return idiom. Changes in v4: - update comment for setup_irq - add R-b - change %d to %u in printk since irq is unsigned - fix uart->irq <=3D 0 to uart->irq =3D=3D 0 since it's unsigned - update %d to %u in printk since irq is unsigned - add r-b - fix %d to %u since irq is unsigned in cadence uart - add R-b - update comment on setup_irq - change %d to %u since irq is unsigned in exynos - add r-b Changes in v3: - clear pending error interrupts before setup_irq for pl011 - clear pending error interrupts before setup_irq call for cadence uart - change uart->irq <=3D 0 to uart->irq =3D=3D 0 since irq is unsigned - skip clearing pending interrupts if setup_irq was failed because according to the 13.4.1.13 of the RM: it must be cleared after cleaning interrupt pending in INTC. Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description Oleksii Moisieiev (4): xen/drivers/char: fix SCIF IRQ registration failure propagation xen/drivers/char/pl011: fix IRQ registration failure propagation xen/drivers/char/cadence-uart: fix IRQ registration failure propagation xen/drivers/char: fix exynos4210 IRQ registration failure propagation xen/drivers/char/cadence-uart.c | 22 ++++++++++++++-------- xen/drivers/char/exynos4210-uart.c | 6 +++++- xen/drivers/char/pl011.c | 22 ++++++++++++++-------- xen/drivers/char/scif-uart.c | 12 ++++++++---- 4 files changed, 41 insertions(+), 21 deletions(-) --=20 2.43.0 base-commit: 077dcf9841ad7df4e63c718249d8ac95f8a709ff branch: amoi_dfmea_scifv4= From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:11:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:11:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292400.1570875 (Exim 4.92) (envelope-from ) id 1wFweZ-0000HL-Gp; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 41ec653e-e4d1-4ea1-7d66-08dea153019e X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2026 16:11:41.4272 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0J8Rc+1ri7W8MxDXAN/dMcHe5M3c6aZ8/XWRDXG5jdMvF66n3rxMPVxTXeTQb7KjH7KIz447Eae9eFqL4bNUomnBGHU3CvvSXndtlqLFVO8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6752 X-purgate-ID: tlsNG-42698a/1776960705-7D364F3B-5D38FF89/0/0 X-purgate-type: clean X-purgate-size: 3024 In scif_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally writing TIE|RIE|REIE into the Serial Control Register (SCSCR). This armed all three hardware interrupt lines (TX FIFO empty, RX data ready, receive error) with no handler registered to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. The fix adds an early return inside the error branch. The interrupt-enable write to SCSCR is skipped entirely when no handler is registered. SCIF TX continues to operate correctly after this change. The Xen serial framework never calls serial_async_transmit() for SCIF, so port->txbuf is always NULL. This causes __serial_putc() to take the synchronous finite-capacity path, which polls the SCFSR_TDFE hardware flag directly and does not depend on the interrupt mechanism. RX wouldn't work if irq wasn't registered. As a secondary clean-up, the hardware error-flag clearing sequence is moved to before the setup_irq() call so that error bits accumulated since init_preirq() are cleared unconditionally, regardless of whether IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel --- Changes in v4: - update comment for setup_irq - add R-b - change %d to %u in printk since irq is unsigned Changes in v2: - Extend fix to pl011, cadence-uart and exynos4210 - fix typo in patch 1 description xen/drivers/char/scif-uart.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 888821a3b8..350d5f14b9 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -187,16 +187,20 @@ static void __init scif_uart_init_postirq(struct seri= al_port *port) uart->irqaction.name =3D "scif_uart"; uart->irqaction.dev_id =3D port; =20 - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n", - uart->irq); - /* Clear all errors */ if ( scif_readw(uart, params->status_reg) & params->error_mask ) scif_writew(uart, params->status_reg, ~params->error_mask); if ( scif_readw(uart, params->overrun_reg) & params->overrun_mask ) scif_writew(uart, params->overrun_reg, ~params->overrun_mask); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %u\n", + uart->irq); + /* Do not unmask interrupts if irq handler wasn't set */ + return; + } + /* Enable TX/RX and Error Interrupts */ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | params->irq_flags); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:11:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:11:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292401.1570888 (Exim 4.92) (envelope-from ) id 1wFwea-0000hA-PS; Thu, 23 Apr 2026 16:11:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292401.1570888; Thu, 23 Apr 2026 16:11:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwea-0000gS-Lg; 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b=M2hiLI07lsdQ6DeREGtirNKT4/3FwVaOSCFgtesrJCrAqbImotKbNvnEffZetXhYM05TnHYILBXWPkPnTrbxmaPL1FaECaOs/+bg5YCHXvv+/kXMtUh7fC75uQ1tY/DUmw69f0MwI2OyAMmVgdSNaFfcjkBW3J+FIkZtM8enKiTuz1GIAO3MUM2EWTpKepPRy3qixItiEwGD0UujljqiwcIKBB/33uda1rHDrTGPiDf1CHZZRhrZTfxh/SiBOC1wr29mOFmj7YVZy2c3vZAhHdRCoyXF4jzfcUerLHiLXkc1CDdL6cWVXuJIrH5IpYDk/81Jx7tFp02P41+1ESqTKA== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Michal Orzel , Stefano Stabellini , Volodymyr Babchuk , Oleksii Moisieiev Subject: [PATCH v4 2/4] xen/drivers/char/pl011: fix IRQ registration failure propagation Thread-Topic: [PATCH v4 2/4] xen/drivers/char/pl011: fix IRQ registration failure propagation Thread-Index: AQHc0zvfp867h1iE6UiP0oRgFR3PCw== Date: Thu, 23 Apr 2026 16:11:41 +0000 Message-ID: <7a3d7e4b73ca1c144ce7687b8494f2a0eb862383.1776960679.git.oleksii_moisieiev@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 11a4c04b-3f44-4545-e675-08dea15301f1 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2026 16:11:41.9102 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nCHoJKpAKYqVftbJFQxwpMTkEuXvJhev6mUPG/T3PGTR2AWmuw0EJ/RnR/0+Q2MRR1rA+KBe09hvEGluLcpIo9fCWb+AkVx6B9DKOpc3hMQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6752 X-purgate-ID: tlsNG-42698a/1776960705-05165F3B-ED63BCAD/0/0 X-purgate-type: clean X-purgate-size: 2815 In pl011_init_postirq(), two code paths could reach the interrupt-unmask write to IMSC without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IMSC write, unmasking RTI|OEI|BEI|PEI|FEI|TXI|RXI with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IMSC write, arming all hardware interrupt lines with no handler to service them. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure pl011_init_postirq() to use early returns: return immediately when no valid IRQ is provided, and return after logging the error when setup_irq() fails. The interrupt-enable write to IMSC is only reached when IRQ registration succeeds. Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel --- Changes in v4: - fix uart->irq <=3D 0 to uart->irq =3D=3D 0 since it's unsigned - update %d to %u in printk since irq is unsigned - add r-b Changes in v3: - clear pending error interrupts before setup_irq for pl011 xen/drivers/char/pl011.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 5f9913367d..a336241033 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -150,18 +150,24 @@ static void __init pl011_init_postirq(struct serial_p= ort *port) struct pl011 *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) - { - uart->irqaction.handler =3D pl011_interrupt; - uart->irqaction.name =3D "pl011"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate pl011 IRQ %d\n", uart->irq); - } + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq =3D=3D 0 ) + return; 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b=HzSRWcStkC+977OP+ovidXBXVczUZZCw016bvMl5gf7y7C8XyUFJCU3GNqtN+zLK9X98uQpKIRr8GL6j4RVySl0xNuPwl4jGgumCoTXIzGz7U5ZEpvaadlcFnasMI7P1sDwsyjY7ewG+tAshweXpDI4H6/JJgrUXJ1SnT56hPUOOV0GdlIo2rg9UUdxl4UQOhVYh1sW66lr/2zHOBx7DsgAKSr1QM4iV6bAJEQBsz1S+ssUAdec0DoQ/7+Tu/48mjll+RD+JsrlPnyXQSyU4u3YGQGhoAytfsJb9AXCp/4HPnT/YsCZJ1UzGB1/LncqTdWH1OfH8yZSzxug0oPNfyg== From: Oleksii Moisieiev To: "xen-devel@lists.xenproject.org" CC: Bertrand Marquis , Julien Grall , Michal Orzel , Stefano Stabellini , Volodymyr Babchuk , Oleksii Moisieiev Subject: [PATCH v4 4/4] xen/drivers/char: fix exynos4210 IRQ registration failure propagation Thread-Topic: [PATCH v4 4/4] xen/drivers/char: fix exynos4210 IRQ registration failure propagation Thread-Index: AQHc0zvfSaMcr5qlbkezhiXMQevBTg== Date: Thu, 23 Apr 2026 16:11:42 +0000 Message-ID: <68ce483d6e42a4f7504fb73e5d20fe922f0c22b6.1776960679.git.oleksii_moisieiev@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f122a687-49d6-4e8c-e04a-08dea1530244 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2026 16:11:42.4981 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SyP9VIEDA3wOFNpX11xewcI+jGgGx690b65XjIbY6HjOMJ7Oo6BVnzl/toOc8vXvO6rPKPB5radTyAlKCv4JxaaWSCICMZE+dUsZ2PM0yhA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6752 X-purgate-ID: tlsNG-42698a/1776960706-07979F3B-924B5D52/0/0 X-purgate-type: clean X-purgate-size: 1917 In exynos4210_uart_init_postirq(), when setup_irq() returns an error the failure was only logged via dprintk() and execution continued, unconditionally clearing UINTM and setting UMCON_INT_EN. This enabled receive and transmit interrupt lines with no handler registered. On platforms where the GIC receives these asserted lines, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Add an early return in the setup_irq() error branch so that the interrupt-enable writes to UINTM and UMCON are skipped when IRQ registration fails. Signed-off-by: Oleksii Moisieiev Reviewed-by: Michal Orzel --- Changes in v4: - update comment on setup_irq - change %d to %u since irq is unsigned in exynos - add r-b Changes in v3: - skip clearing pending interrupts if setup_irq was failed because according to the 13.4.1.13 of the RM: it must be cleared after cleaning interrupt pending in INTC. xen/drivers/char/exynos4210-uart.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos42= 10-uart.c index 58901df554..7addc11c2c 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -199,8 +199,12 @@ static void __init exynos4210_uart_init_postirq(struct= serial_port *port) uart->irqaction.dev_id =3D port; =20 if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %d\n"= , + { + dprintk(XENLOG_ERR, "Failed to allocated exynos4210_uart IRQ %u\n"= , uart->irq); + /* Do not unmask interrupts if irq handler wasn't set */ + return; + } =20 /* Unmask interrupts */ exynos4210_write(uart, UINTM, ~UINTM_ALLI); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 16:12:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 16:12:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292413.1570906 (Exim 4.92) (envelope-from ) id 1wFwem-0001Vj-Cz; Thu, 23 Apr 2026 16:12:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292413.1570906; Thu, 23 Apr 2026 16:12:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwem-0001VW-7u; Thu, 23 Apr 2026 16:12:00 +0000 Received: by outflank-mailman (input) for mailman id 1292413; Thu, 23 Apr 2026 16:11:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wFwel-0001Sy-2A for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU5PR03MB10263.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 301c4b89-c713-4158-644d-08dea153021b X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2026 16:11:42.2002 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PmwOBkVQ0B4+RR4dLsLU9a71VTZJNIakFLnZvuJUm6jjeiMqxmrBmbQzMDpdwXLAxdopvH7KJlUJOSS5bcs6uQtlm8SonX8a9hdIqp/yCPg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6752 X-purgate-ID: tlsNG-33051d/1776960718-2B161938-A244AA8A/0/0 X-purgate-type: clean X-purgate-size: 2817 In cuart_init_postirq(), two code paths could reach the interrupt-enable write to IER without a handler being registered: - When no valid IRQ number was provided (uart->irq <=3D 0), the original positive-condition guard (if uart->irq > 0) skipped the irqaction setup but still fell through to the IER write, enabling the receive data interrupt with no handler installed. - When setup_irq() returned an error, only an error message was printed and execution continued to the IER write, arming the receive hardware interrupt line with no handler to service it. On platforms where the GIC receives this asserted line, the result is either repeated spurious-interrupt warnings or an unhandled interrupt fault. Restructure cuart_init_postirq() to use early returns in both error paths. Signed-off-by: Oleksii Moisieiev Reviewed-by: Oleksandr Tyshchenko --- Changes in v4: - fix %d to %u since irq is unsigned in cadence uart - add R-b Changes in v3: - clear pending error interrupts before setup_irq call for cadence uart - change uart->irq <=3D 0 to uart->irq =3D=3D 0 since irq is unsigned xen/drivers/char/cadence-uart.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uar= t.c index b2f379833f..0f1c3dd461 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -72,19 +72,25 @@ static void __init cuart_init_postirq(struct serial_por= t *port) struct cuart *uart =3D port->uart; int rc; =20 - if ( uart->irq > 0 ) - { - uart->irqaction.handler =3D cuart_interrupt; - uart->irqaction.name =3D "cadence-uart"; - uart->irqaction.dev_id =3D port; - if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) - printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart= ->irq); - } + /* Don't unmask interrupts if no valid irq was provided */ + if ( uart->irq =3D=3D 0 ) + return; + + uart->irqaction.handler =3D cuart_interrupt; + uart->irqaction.name =3D "cadence-uart"; + uart->irqaction.dev_id =3D port; =20 /* Clear pending error interrupts */ cuart_write(uart, R_UART_RTRIG, 1); cuart_write(uart, R_UART_CISR, ~0); =20 + if ( (rc =3D setup_irq(uart->irq, 0, &uart->irqaction)) !=3D 0 ) + { + printk("ERROR: Failed to allocate cadence-uart IRQ %u\n", uart->ir= q); + /* Do not unmask interrupts if irq handler wasn't set */ + return; + } + /* Unmask interrupts */ cuart_write(uart, R_UART_IDR, ~0); cuart_write(uart, R_UART_IER, UART_SR_INTR_RTRIG); --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 17:52:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 17:52:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292523.1570947 (Exim 4.92) (envelope-from ) id 1wFyDs-0002YL-JR; Thu, 23 Apr 2026 17:52:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292523.1570947; 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boundary="-=Part.27a4.39131a8643359abe.19dbb788311.650115a9ec2631f4=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1776966730513 X-purgate-ID: tlsNG-ebf023/1776966736-4B3673FF-38DAFA4B/0/0 X-purgate-type: clean X-purgate-size: 4499 ---=Part.27a4.39131a8643359abe.19dbb788311.650115a9ec2631f4=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 4/23/26 17:20, Oleksii Kurochko wrote: >=20 > On 4/23/26 4:46 PM, Thierry Escande wrote: >> This series adds new 'hotplug' option for PCI device passthrough=2E >> >> The current mechanism for device passthrough uses QMP device_add comman= d >> to hot-plug PCI devices to the guest Qemu instance=2E This is an issue = for >> guests running on Q35 chipset (preliminary support posted at [1]) >> since the >> Q35 PCI root bus does not support hotplug=2E Devices could be hotplugge= d to >> a secondary PCI bus but Xen only support 1 PCI bus for now=2E >> >> The 'hotplug' option allows to control how devices are attached to the >> guest, either by using the legacy QMP mechanism (this is the default) >> or by >> passing them directly to the Qemu command line using xen-pci-passthroug= h >> device=2E >> >> Example usage in cfg file: >> =C2=A0 pci =3D [ "00:03=2E0,seize=3D1,hotplug=3D0" ] >> >> Since Qemu -device option accepts parameters in json format, this >> patchset adds a new internal function >> libxl__device_pci_get_qapi_json() that >> generates the device json object used for both QMP hotplug and command >> line >> passing=2E >> >> Also, to handle the assignable PCI device list, the function >> libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and = is >> made available from libxl=2Eh for access in libxl_dm=2Ec=2E 2 other >> functions are >> also exported internally: libxl__pciback_dev_is_assigned() and >> libxl__device_pci_assignable_add()=2E >> >> This has been successfully tested on Xen 4=2E22-dev and Qemu 10=2E0 run= ning >> Debian VMs in both Bios and UEFI mode with a passthrough'd nvme disk=2E >> Disabling the hotplug mechanism might be made mandatory for Q35 machine= s >> later, once Q35 support is merged upstream=2E >> >> [1] https://lore=2Ekernel=2Eorg/xen-devel/20260313163455=2E790692-1- >> thierry=2Eescande@vates=2Etech/ >> >> Changes in v2: >> =C2=A0 - Add support for YAJL json parser >> >> Changes in v3: >> =C2=A0 - Move code block of device command line parameters creation >> =C2=A0 - Better handling of pci device assignation >> >> Changes in v4: >> =C2=A0 - Split the refactoring parts of the 2nd patch >> =C2=A0 - Extend libxl__json_object_to_json() and use it to generate the >> qapi json >> =C2=A0=C2=A0=C2=A0 string >> >> Thierry Escande (6): >> =C2=A0=C2=A0 xl: Add an hotplug option for PCI device passthrough >> =C2=A0=C2=A0 libxl: Refactor some PCI device handling functions >> =C2=A0=C2=A0 libxl: Add libxl__device_pci_get_qapi_json() internal API >> =C2=A0=C2=A0 libxl: Extend libxl__json_object_to_json() prototype >> =C2=A0=C2=A0 libxl: Allow PCI device passthrough using -device Qemu com= mand line >> =C2=A0=C2=A0 docs: provide description for pci hotplug option >> >> =C2=A0 docs/man/xl-pci-configuration=2E5=2Epod | 17 +++++++++ >> =C2=A0 docs/man/xl=2Ecfg=2E5=2Epod=2Ein=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 6 +++ >> =C2=A0 tools/include/libxl=2Eh=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 1 + >> =C2=A0 tools/libs/light/libxl_dm=2Ec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 | 33 +++++++++++++++++ >> =C2=A0 tools/libs/light/libxl_internal=2Eh=C2=A0=C2=A0 | 12 +++++- >> =C2=A0 tools/libs/light/libxl_json=2Ec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 | 11 +++++- >> =C2=A0 tools/libs/light/libxl_pci=2Ec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 57 ++++++++++++++++++++--------- >> =C2=A0 tools/libs/light/libxl_types=2Eidl=C2=A0=C2=A0=C2=A0 |=C2=A0 1 + >> =C2=A0 tools/libs/util/libxlu_pci=2Ec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0 2 + >> =C2=A0 tools/xl/xl_parse=2Ec=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 5 +++ >> =C2=A0 10 files changed, 123 insertions(+), 22 deletions(-) >> >=20 > I think we also want to add an item to CHANGELOG=2Emd that it is possibl= e > to passthrough PCI device via QEMU command line=2E Sure, will do=2E Thanks, Thierry > Thanks=2E >=20 > ~ Oleksii -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vat= es solutions web: https://vates=2Etech ---=Part.27a4.39131a8643359abe.19dbb788311.650115a9ec2631f4=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 23 19:05:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 19:05:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292580.1570956 (Exim 4.92) (envelope-from ) id 1wFzMZ-0005mj-Le; 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Introduce two Gitlab macOS build jobs that reproduce the ones present on CirrusCI. According to the "Community programs" Gitlab documentation [0] we get 50,000 compute minutes per month. The arm64 job takes ~1m 15s, and the x86_64 one ~2m. I think it's likely enough given the amount of minutes we have available. We might need to reconsider if we add more tasks that consume compute minutes. [0] https://docs.gitlab.com/subscriptions/community_programs/#gitlab-for-open-source Signed-off-by: Roger Pau Monné --- Example jobs at: https://gitlab.com/xen-project/hardware/xen-staging/-/jobs/14064832403 https://gitlab.com/xen-project/hardware/xen-staging/-/jobs/14064832402 --- automation/gitlab-ci/build.yaml | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml index eff96beaa5c3..463ed2f96d86 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -815,3 +815,33 @@ debian-13-riscv64-gcc-randconfig: KBUILD_DEFCONFIG: tiny64_defconfig RANDCONFIG: y <<: *riscv-fixed-randconfig + +# macOS build jobs +.macos-26: + <<: *build + tags: + - saas-macos-medium-m1 + image: macos-26-xcode-26 + variables: + HOMEBREW_NO_AUTO_UPDATE: 1 + HOSTCC: clang + HYPERVISOR_ONLY: y + <<: *gcc + script: + - brew install ${CROSS_COMPILE}gcc ${CROSS_COMPILE}binutils + - alias nproc="sysctl -n hw.ncpu" + - ./automation/scripts/build 2>&1 | tee build.log + +macos-26-x86_64: + extends: + - .macos-26 + variables: + XEN_TARGET_ARCH: x86_64 + CROSS_COMPILE: x86_64-elf- + +macos-26-arm64: + extends: + - .macos-26 + variables: + XEN_TARGET_ARCH: arm64 + CROSS_COMPILE: aarch64-elf- -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 20:04:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 20:04:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292629.1570997 (Exim 4.92) (envelope-from ) id 1wG0He-0007wY-2O; Thu, 23 Apr 2026 20:04:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292629.1570997; Thu, 23 Apr 2026 20:04:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hd-0007wC-TN; Thu, 23 Apr 2026 20:04:21 +0000 Received: by outflank-mailman (input) for mailman id 1292629; Thu, 23 Apr 2026 20:04:21 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hd-0007ic-3T for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 20:04:21 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wG0Hc-008AbV-GX for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 22:04:20 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea7b23-bab6-0a2a0a5309dd-0a2a4507ec64-26 for ; Thu, 23 Apr 2026 22:04:20 +0200 Received: from [209.85.221.42] (helo=mail-wr1-f42.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea7b44-229c-0a2a45070019-d155dd2aa98d-3 for ; Thu, 23 Apr 2026 22:04:20 +0200 Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-43d75312379so5163604f8f.1 for ; Thu, 23 Apr 2026 13:04:20 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Signed-off-by: Edwin Török Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_common.h | 13 +++++++ tools/libs/guest/xg_sr_save.c | 66 +++++++++++++-------------------- 2 files changed, 39 insertions(+), 40 deletions(-) diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_common.h index f1573aefcb..77312bae9c 100644 --- a/tools/libs/guest/xg_sr_common.h +++ b/tools/libs/guest/xg_sr_common.h @@ -209,6 +209,18 @@ static inline int update_blob(struct xc_sr_blob *blob, return 0; } +struct xc_sr_context_save_buffers +{ + xen_pfn_t batch_pfns[MAX_BATCH_SIZE]; + xen_pfn_t mfns[MAX_BATCH_SIZE]; + xen_pfn_t types[MAX_BATCH_SIZE]; + int errors[MAX_BATCH_SIZE]; + void *guest_data[MAX_BATCH_SIZE]; + void *local_pages[MAX_BATCH_SIZE]; + struct iovec iov[MAX_BATCH_SIZE + 2]; /* headers + data */ + uint64_t rec_pfns[MAX_BATCH_SIZE]; +}; + struct xc_sr_context { xc_interface *xch; @@ -244,6 +256,7 @@ struct xc_sr_context unsigned long *deferred_pages; unsigned long nr_deferred_pages; xc_hypercall_buffer_t dirty_bitmap_hbuf; + struct xc_sr_context_save_buffers *buffers; } save; struct /* Restore data. */ diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 1700d81905..64014dcdbd 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -87,16 +87,16 @@ static int write_checkpoint_record(struct xc_sr_context *ctx) static int write_batch(struct xc_sr_context *ctx) { xc_interface *xch = ctx->xch; - xen_pfn_t *mfns = NULL, *types = NULL; + xen_pfn_t *mfns, *types; void *guest_mapping = NULL; - void **guest_data = NULL; - void **local_pages = NULL; - int *errors = NULL, rc = -1; + void **guest_data; + void **local_pages; + int *errors, rc = -1; unsigned int i, p, nr_pages = 0, nr_pages_mapped = 0; unsigned int nr_pfns = ctx->save.nr_batch_pfns; void *page, *orig_page; - uint64_t *rec_pfns = NULL; - struct iovec *iov = NULL; int iovcnt = 0; + uint64_t *rec_pfns; + struct iovec *iov; int iovcnt = 0; struct { struct xc_sr_rhdr rec; struct xc_sr_rec_page_data_header page_data; @@ -106,26 +106,24 @@ static int write_batch(struct xc_sr_context *ctx) }; assert(nr_pfns != 0); + assert(nr_pfns <= MAX_BATCH_SIZE); + assert(ctx->save.buffers); /* Mfns of the batch pfns. */ - mfns = malloc(nr_pfns * sizeof(*mfns)); + mfns = ctx->save.buffers->mfns; /* Types of the batch pfns. */ - types = malloc(nr_pfns * sizeof(*types)); + types = ctx->save.buffers->types; /* Errors from attempting to map the gfns. */ - errors = malloc(nr_pfns * sizeof(*errors)); + errors = ctx->save.buffers->errors; /* Pointers to page data to send. Mapped gfns or local allocations. */ - guest_data = calloc(nr_pfns, sizeof(*guest_data)); + guest_data = ctx->save.buffers->guest_data; + memset(guest_data, 0, sizeof(*guest_data) * nr_pfns); /* Pointers to locally allocated pages. Need freeing. */ - local_pages = calloc(nr_pfns, sizeof(*local_pages)); + local_pages = ctx->save.buffers->local_pages; + memset(local_pages, 0, sizeof(*local_pages) * nr_pfns); /* iovec[] for writev(). */ - iov = malloc((nr_pfns + 2) * sizeof(*iov)); - - if ( !mfns || !types || !errors || !guest_data || !local_pages || !iov ) - { - ERROR("Unable to allocate arrays for a batch of %u pages", - nr_pfns); - goto err; - } + iov = ctx->save.buffers->iov; + rec_pfns = ctx->save.buffers->rec_pfns; for ( i = 0; i < nr_pfns; ++i ) { @@ -211,14 +209,6 @@ static int write_batch(struct xc_sr_context *ctx) } } - rec_pfns = malloc(nr_pfns * sizeof(*rec_pfns)); - if ( !rec_pfns ) - { - ERROR("Unable to allocate %zu bytes of memory for page data pfn list", - nr_pfns * sizeof(*rec_pfns)); - goto err; - } - hdrs.rec.length = sizeof(hdrs.page_data); hdrs.rec.length += nr_pfns * sizeof(*rec_pfns); hdrs.rec.length += nr_pages * PAGE_SIZE; @@ -261,17 +251,13 @@ static int write_batch(struct xc_sr_context *ctx) rc = ctx->save.nr_batch_pfns = 0; err: - free(rec_pfns); if ( guest_mapping ) xenforeignmemory_unmap(xch->fmem, guest_mapping, nr_pages_mapped); for ( i = 0; local_pages && i < nr_pfns; ++i ) + { free(local_pages[i]); - free(iov); - free(local_pages); - free(guest_data); - free(errors); - free(types); - free(mfns); + local_pages[i] = NULL; + } return rc; } @@ -799,18 +785,18 @@ static int setup(struct xc_sr_context *ctx) dirty_bitmap = xc_hypercall_buffer_alloc_pages( xch, dirty_bitmap, NRPAGES(bitmap_size(ctx->save.p2m_size))); - ctx->save.batch_pfns = malloc(MAX_BATCH_SIZE * - sizeof(*ctx->save.batch_pfns)); ctx->save.deferred_pages = bitmap_alloc(ctx->save.p2m_size); + ctx->save.buffers = calloc(1, sizeof(*ctx->save.buffers)); - if ( !ctx->save.batch_pfns || !dirty_bitmap || !ctx->save.deferred_pages ) + if ( !dirty_bitmap || !ctx->save.deferred_pages || !ctx->save.buffers) { - ERROR("Unable to allocate memory for dirty bitmaps, batch pfns and" - " deferred pages"); + ERROR("Unable to allocate memory for dirty bitmaps, deferred pages" + " and various batch buffers"); rc = -1; errno = ENOMEM; goto err; } + ctx->save.batch_pfns = ctx->save.buffers->batch_pfns; rc = 0; @@ -834,7 +820,7 @@ static void cleanup(struct xc_sr_context *ctx) xc_hypercall_buffer_free_pages(xch, dirty_bitmap, NRPAGES(bitmap_size(ctx->save.p2m_size))); free(ctx->save.deferred_pages); - free(ctx->save.batch_pfns); + free(ctx->save.buffers); } /* -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 20:04:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 20:04:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292626.1570973 (Exim 4.92) (envelope-from ) id 1wG0Hc-0007Sb-3q; Thu, 23 Apr 2026 20:04:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292626.1570973; Thu, 23 Apr 2026 20:04:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hc-0007SQ-10; Thu, 23 Apr 2026 20:04:20 +0000 Received: by outflank-mailman (input) for mailman id 1292626; Thu, 23 Apr 2026 20:04:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Ha-0007FJ-J6 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 20:04:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wG0HZ-005MS0-W8 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 22:04:18 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea7b40-5cb7-0a2a0a5109dd-0a2a4505d46e-4 for ; Thu, 23 Apr 2026 22:04:17 +0200 Received: from [209.85.221.45] (helo=mail-wr1-f45.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea7b41-aaa8-0a2a45050019-d155dd2ddde8-3 for ; Thu, 23 Apr 2026 22:04:17 +0200 Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-43d6fbd0954so5585381f8f.1 for ; Thu, 23 Apr 2026 13:04:17 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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There's no much sense to split the header in 2 pieces, it will just take more time and space to reassemble them in the final buffer. This also avoids truncating combined_length to 32 bit in case of 64 bit machines potentially avoiding following record_length check. The function become more coherent with following read_record function. Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/libs/guest/xg_sr_common.c b/tools/libs/guest/xg_sr_common.c index 7ccdc3b1f6..86c148c62f 100644 --- a/tools/libs/guest/xg_sr_common.c +++ b/tools/libs/guest/xg_sr_common.c @@ -59,11 +59,11 @@ int write_split_record(struct xc_sr_context *ctx, struct xc_sr_record *rec, static const char zeroes[(1u << REC_ALIGN_ORDER) - 1] = { 0 }; xc_interface *xch = ctx->xch; - typeof(rec->length) combined_length = rec->length + sz; + size_t combined_length = rec->length + sz; size_t record_length = ROUNDUP(combined_length, REC_ALIGN_ORDER); + struct xc_sr_rhdr rhdr = { rec->type, combined_length }; struct iovec parts[] = { - { &rec->type, sizeof(rec->type) }, - { &combined_length, sizeof(combined_length) }, + { &rhdr, sizeof(rhdr) }, { rec->data, rec->length }, { buf, sz }, { (void *)zeroes, record_length - combined_length }, -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 20:04:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 20:04:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292627.1570978 (Exim 4.92) (envelope-from ) id 1wG0Hc-0007U9-BY; Thu, 23 Apr 2026 20:04:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292627.1570978; Thu, 23 Apr 2026 20:04:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hc-0007Tz-7U; Thu, 23 Apr 2026 20:04:20 +0000 Received: by outflank-mailman (input) for mailman id 1292627; Thu, 23 Apr 2026 20:04:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hb-0007Le-Cq for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 20:04:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wG0Ha-008AbV-Pj for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 22:04:18 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea7b42-bab6-0a2a0a5309dd-0a2a4506bad4-0 for ; Thu, 23 Apr 2026 22:04:18 +0200 Received: from [209.85.221.43] (helo=mail-wr1-f43.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea7b42-7371-0a2a45060019-d155dd2bf07e-3 for ; Thu, 23 Apr 2026 22:04:18 +0200 Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-43d73422431so6043904f8f.2 for ; Thu, 23 Apr 2026 13:04:18 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Reduce number of pieces passed to writev. Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_save.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 3b2c5222e4..1700d81905 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -97,9 +97,12 @@ static int write_batch(struct xc_sr_context *ctx) void *page, *orig_page; uint64_t *rec_pfns = NULL; struct iovec *iov = NULL; int iovcnt = 0; - struct xc_sr_rec_page_data_header hdr = { 0 }; - struct xc_sr_record rec = { - .type = REC_TYPE_PAGE_DATA, + struct { + struct xc_sr_rhdr rec; + struct xc_sr_rec_page_data_header page_data; + } hdrs = { + { .type = REC_TYPE_PAGE_DATA }, + { 0 }, }; assert(nr_pfns != 0); @@ -115,7 +118,7 @@ static int write_batch(struct xc_sr_context *ctx) /* Pointers to locally allocated pages. Need freeing. */ local_pages = calloc(nr_pfns, sizeof(*local_pages)); /* iovec[] for writev(). */ - iov = malloc((nr_pfns + 4) * sizeof(*iov)); + iov = malloc((nr_pfns + 2) * sizeof(*iov)); if ( !mfns || !types || !errors || !guest_data || !local_pages || !iov ) { @@ -216,28 +219,22 @@ static int write_batch(struct xc_sr_context *ctx) goto err; } - hdr.count = nr_pfns; + hdrs.rec.length = sizeof(hdrs.page_data); + hdrs.rec.length += nr_pfns * sizeof(*rec_pfns); + hdrs.rec.length += nr_pages * PAGE_SIZE; - rec.length = sizeof(hdr); - rec.length += nr_pfns * sizeof(*rec_pfns); - rec.length += nr_pages * PAGE_SIZE; + hdrs.page_data.count = nr_pfns; for ( i = 0; i < nr_pfns; ++i ) rec_pfns[i] = ((uint64_t)(types[i]) << 32) | ctx->save.batch_pfns[i]; - iov[0].iov_base = &rec.type; - iov[0].iov_len = sizeof(rec.type); + iov[0].iov_base = &hdrs; + iov[0].iov_len = sizeof(hdrs); - iov[1].iov_base = &rec.length; - iov[1].iov_len = sizeof(rec.length); + iov[1].iov_base = rec_pfns; + iov[1].iov_len = nr_pfns * sizeof(*rec_pfns); - iov[2].iov_base = &hdr; - iov[2].iov_len = sizeof(hdr); - - iov[3].iov_base = rec_pfns; - iov[3].iov_len = nr_pfns * sizeof(*rec_pfns); - - iovcnt = 4; + iovcnt = 2; if ( nr_pages ) { -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 20:04:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 20:04:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292628.1570991 (Exim 4.92) (envelope-from ) id 1wG0Hd-0007tN-N9; Thu, 23 Apr 2026 20:04:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292628.1570991; Thu, 23 Apr 2026 20:04:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hd-0007tG-KF; Thu, 23 Apr 2026 20:04:21 +0000 Received: by outflank-mailman (input) for mailman id 1292628; Thu, 23 Apr 2026 20:04:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Hc-0007Ru-0Z for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 20:04:20 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wG0Hb-005MUL-Dg for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 22:04:19 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea7b25-2eae-0a2a0a5409dd-0a2a45019a8a-26 for ; Thu, 23 Apr 2026 22:04:19 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea7b43-c1f2-0a2a45010019-d155802fbddc-3 for ; Thu, 23 Apr 2026 22:04:19 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-488b0046078so63848575e9.1 for ; Thu, 23 Apr 2026 13:04:19 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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The implementation in tools/libs/store/xs.c already use this signature and method. Signed-off-by: Frediano Ziglio --- tools/libs/ctrl/xc_private.c | 26 +++++--------------------- tools/libs/ctrl/xc_private.h | 2 +- 2 files changed, 6 insertions(+), 22 deletions(-) diff --git a/tools/libs/ctrl/xc_private.c b/tools/libs/ctrl/xc_private.c index bb0f81d6f3..946fc307aa 100644 --- a/tools/libs/ctrl/xc_private.c +++ b/tools/libs/ctrl/xc_private.c @@ -635,7 +635,7 @@ int write_exact(int fd, const void *data, size_t size) /* * MiniOS's libc doesn't know about writev(). Implement it as multiple write()s. */ -int writev_exact(int fd, const struct iovec *iov, int iovcnt) +int writev_exact(int fd, struct iovec *iov, int iovcnt) { int rc, i; @@ -649,9 +649,8 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) return 0; } #else -int writev_exact(int fd, const struct iovec *iov, int iovcnt) +int writev_exact(int fd, struct iovec *iov, int iovcnt) { - struct iovec *local_iov = NULL; int rc = 0, iov_idx = 0, saved_errno = 0; ssize_t len; @@ -686,23 +685,9 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) len -= iov[iov_idx++].iov_len; else { - /* Partial write of iov[iov_idx]. Copy iov so we can adjust - * element iov_idx and resubmit the rest. */ - if ( !local_iov ) - { - local_iov = malloc(iovcnt * sizeof(*iov)); - if ( !local_iov ) - { - saved_errno = ENOMEM; - rc = -1; - goto out; - } - - iov = memcpy(local_iov, iov, iovcnt * sizeof(*iov)); - } - - local_iov[iov_idx].iov_base += len; - local_iov[iov_idx].iov_len -= len; + /* Partial write of iov[iov_idx]. */ + iov[iov_idx].iov_base += len; + iov[iov_idx].iov_len -= len; break; } } @@ -711,7 +696,6 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) saved_errno = 0; out: - free(local_iov); errno = saved_errno; return rc; } diff --git a/tools/libs/ctrl/xc_private.h b/tools/libs/ctrl/xc_private.h index b5892ae8dc..3af996e900 100644 --- a/tools/libs/ctrl/xc_private.h +++ b/tools/libs/ctrl/xc_private.h @@ -383,7 +383,7 @@ int xc_flush_mmu_updates(xc_interface *xch, struct xc_mmu *mmu); /* Return 0 on success; -1 on error setting errno. */ int read_exact(int fd, void *data, size_t size); /* EOF => -1, errno=0 */ int write_exact(int fd, const void *data, size_t size); -int writev_exact(int fd, const struct iovec *iov, int iovcnt); +int writev_exact(int fd, struct iovec *iov, int iovcnt); int xc_ffs8(uint8_t x); int xc_ffs16(uint16_t x); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 23 20:04:27 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 23 Apr 2026 20:04:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1292625.1570965 (Exim 4.92) (envelope-from ) id 1wG0Ha-0007FW-R1; Thu, 23 Apr 2026 20:04:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1292625.1570965; Thu, 23 Apr 2026 20:04:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Ha-0007FP-NS; Thu, 23 Apr 2026 20:04:18 +0000 Received: by outflank-mailman (input) for mailman id 1292625; Thu, 23 Apr 2026 20:04:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG0Ha-0007FE-4i for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 20:04:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wG0HZ-008AbV-B5 for xen-devel@lists.xenproject.org; Thu, 23 Apr 2026 22:04:17 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ea7b23-bab6-0a2a0a5309dd-0a2a4507ec64-24 for ; Thu, 23 Apr 2026 22:04:17 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ea7b41-229c-0a2a45070019-d1558034bde0-3 for ; Thu, 23 Apr 2026 22:04:17 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-488b0046078so63848315e9.1 for ; Thu, 23 Apr 2026 13:04:17 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Avoid possible allocation sending data with writev. Reduce number of allocations sending memory state. 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This will also make it easier to then change of_map_id() to correctly account for specifier cells. Reviewed-by: Rob Herring (Arm) Reviewed-by: Frank Li Acked-by: Marc Zyngier Acked-by: Bjorn Helgaas Signed-off-by: Robin Murphy Signed-off-by: Vijayanand Jitta --- drivers/cdx/cdx_msi.c | 3 +-- drivers/iommu/of_iommu.c | 4 +--- drivers/irqchip/irq-gic-its-msi-parent.c | 2 +- drivers/of/base.c | 38 ++++++++++++++++++++++++++++++++ drivers/of/irq.c | 3 +-- drivers/pci/controller/dwc/pci-imx6.c | 6 ++--- drivers/pci/controller/pcie-apple.c | 3 +-- drivers/xen/grant-dma-ops.c | 3 +-- include/linux/of.h | 18 +++++++++++++++ 9 files changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 91b95422b263..63b3544ec997 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -128,8 +128,7 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_id(parent->of_node, cdx_dev->msi_dev_id, "msi-map", "msi-map-mask", - NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 6b989a62def2..a511ecf21fcd 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -48,9 +48,7 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct of_phandle_args iommu_spec = { .args_count = 1 }; int err; - err = of_map_id(master_np, *id, "iommu-map", - "iommu-map-mask", &iommu_spec.np, - iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index d36b278ae66c..b63343a227a9 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -180,7 +180,7 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u struct device_node *msi_ctrl __free(device_node) = NULL; - return of_map_id(dev->of_node, dev->id, "msi-map", "msi-map-mask", &msi_ctrl, dev_id); + return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index 57420806c1a2..ae04487bd614 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2201,3 +2201,41 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } EXPORT_SYMBOL_GPL(of_map_id); + +/** + * of_map_iommu_id - Translate an ID using "iommu-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the iommu-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_iommu_id); + +/** + * of_map_msi_id - Translate an ID using "msi-map" bindings. + * @np: root complex device node. + * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform + * stream/device ID) used as the lookup key in the msi-map table. + * @target: optional pointer to a target device node. + * @id_out: optional pointer to receive the translated ID. + * + * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * + * Return: 0 on success or a standard error code on failure. + */ +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); +} +EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 6367c67732d2..e37c1b3f8736 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -817,8 +817,7 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_id(parent_dev->of_node, id_in, "msi-map", - "msi-map-mask", msi_np, &id_out)) + if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) break; if (!of_check_msi_parent(parent_dev->of_node, msi_np)) break; diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index a5b8d0b71677..bff8289f804a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1144,8 +1144,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) u32 sid = 0; target = NULL; - err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", - &target, &sid_i); + err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); if (target) { of_node_put(target); } else { @@ -1158,8 +1157,7 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) } target = NULL; - err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", - &target, &sid_m); + err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); /* * err_m target diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index 2d92fc79f6dd..a0937b7b3c4d 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -764,8 +764,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_id(port->pcie->dev->of_node, rid, "iommu-map", - "iommu-map-mask", NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); if (err) return err; diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index c2603e700178..1b7696b2d762 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -325,8 +325,7 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_id(np, rid, "iommu-map", "iommu-map-mask", &iommu_spec.np, - iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index be6ec4916adf..fe841f3cc747 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -465,6 +465,12 @@ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, struct device_node **target, u32 *id_out); +int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + +int of_map_msi_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out); + phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); struct kimage; @@ -934,6 +940,18 @@ static inline int of_map_id(const struct device_node *np, u32 id, return -EINVAL; } +static inline int of_map_iommu_id(const struct device_node *np, u32 id, + struct device_node **target, u32 *id_out) +{ + return -EINVAL; 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This typically does happen to be the case, but is not actually enforced (and the PCI msi-map binding even explicitly states support for 0 or 1 cells) - as a result we've now ended up with dodgy DTs out in the field which depend on this behaviour to map a 1-cell specifier for a 2-cell provider, despite that being bogus per the bindings themselves. Since there is some potential use[1] in being able to map at least single input IDs to multi-cell output specifiers (and properly support 0-cell outputs as well), add support for properly parsing and using the target nodes' #cells values, albeit with the unfortunate complication of still having to work around expectations of the old behaviour too. -- Robin. Unlike single #{}-cell, it is complex to establish a linear relation between input 'id' and output specifier for multi-cell properties, thus it is always expected that len never going to be > 1. These changes have been tested on QEMU for the arm64 architecture. Since, this would also need update in dt-schema, raised PR[2] for the same. [1] https://lore.kernel.org/all/20250627-video_cb-v3-0-51e18c0ffbce@quicinc.com/ [2] PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184 V14: - Updated Patch 2 ("of: Factor arguments passed to of_map_id() into a struct") to fix below two issues in of_msi_xlate() that were introduced by the API refactoring: 1) The refactoring changed of_map_id()'s dual-purpose **target parameter to an explicit filter_np parameter. In of_msi_xlate(), this caused of_map_msi_id() to return 0 (pass-through) instead of -ENODEV when a node has no msi-map, terminating the device hierarchy walk prematurely before reaching the root complex node that has the msi-map. This broke MSI allocation for PCIe endpoint devices (e.g., wcn7850 Wi-Fi on ARM64). 2) Additionally, fsl_mc_get_msi_id() passes msi_np == NULL to of_msi_xlate(), which would dereference NULL with the new API. Link to v13: https://patch.msgid.link/20260408-parse_iommu_cells-v13-0-fa921e92661b@oss.qualcomm.com V13: - Fix bad_map handling in of_map_id(): 'cells' is re-initialized to 0 on each loop iteration, so the !bad_map guard was insufficient, cells stayed 0 for all entries after the first. Fix by explicitly setting cells=1 when bad_map is true on every iteration. - Collected Acked-by from Frank Li. Link to v12: https://patch.msgid.link/20260331-parse_iommu_cells-v12-0-decfd305eea9@oss.qualcomm.com V12: - Call of_node_put() unconditionally in imx_pcie_add_lut_by_rid() thereby addressing comments from Bjorn Helgaas. Link to v11: https://lore.kernel.org/r/20260325-parse_iommu_cells-v11-0-1fefa5c0e82c@oss.qualcomm.com V11: - Added explicit filter_np parameter to of_map_id() and of_map_msi_id() per Dmitry Baryshkov's review feedback, making the filter explicit instead of overloading arg->np as both input filter and output parameter. - Removed of_node_put() from inside of_map_id(), making the caller responsible for reference management. Updated of_msi_xlate() to properly handle reference counting. - Collected ACKed by tags, and fixed minor typos. Link to v10: https://lore.kernel.org/r/20260309-parse_iommu_cells-v10-0-c62fcaa5a1d8@oss.qualcomm.com V10: - Move of_map_iommu_id()/of_map_msi_id() from include/linux/of.h to drivers/of/base.c as out-of-line helpers per feedback from Marc Zyngier and Rob Herring. - Add kernel-doc to document both helpers for discoverability and usage clarity. - Fix of_map_msi_id() wrapper and all its callers (cdx_msi.c, irq-gic-its-msi-parent.c, drivers/of/irq.c) to correctly use the new struct of_phandle_args-based API with proper of_node_put() handling as per feeback from Dmitry. Link to v9: https://lore.kernel.org/r/20260301-parse_iommu_cells-v9-0-4d1bceecc5e1@oss.qualcomm.com V9: - Updated TO/CC list based on feedback to include all relevant maintainers. - No functional changes to the patches themselves. Link to V8: https://lore.kernel.org/all/20260226074245.3098486-1-vijayanand.jitta@oss.qualcomm.com/ V8: - Removed mentions of of_map_args from commit message to match code. Link to V7: https://lore.kernel.org/all/20260210101157.2145113-1-vijayanand.jitta@oss.qualcomm.com/ V7: - Removed of_map_id_args structure and replaced it with of_phandle_args as suggested by Dmitry. Link to V6: https://lore.kernel.org/all/20260121055400.937856-1-vijayanand.jitta@oss.qualcomm.com/ V6: - Fixed build error reported by kernel test bot. Link to V5: https://lore.kernel.org/all/20260118181125.1436036-1-vijayanand.jitta@oss.qualcomm.com/ V5: - Fixed Build Warnings. - Raised PR for iommu-map dtschema: https://github.com/devicetree-org/dt-schema/pull/184 Link to V4: https://lore.kernel.org/all/20251231114257.2382820-1-vijayanand.jitta@oss.qualcomm.com/ V4: - Added Reviewed-by tag. - Resolved warnings reported by kernel test bot, minor code reorganization. Link to V3: https://lore.kernel.org/all/20251221213602.2413124-1-vijayanand.jitta@oss.qualcomm.com/ V3: - Added Reviewed-by tag. - Updated of_map_id_args struct as a wrapper to of_phandle_args and added comment description as suggested by Rob Herring. Link to V2: https://lore.kernel.org/all/20251204095530.8627-1-vijayanand.jitta@oss.qualcomm.com/ V2: - Incorporated the patches from Robin that does the clean implementation. - Dropped the patches the were adding multi-map support from this series as suggested. V1: https://lore.kernel.org/all/cover.1762235099.git.charan.kalla@oss.qualcomm.com/ RFC: https://lore.kernel.org/all/20250928171718.436440-1-charan.kalla@oss.qualcomm.com/#r Signed-off-by: Vijayanand Jitta --- To: Nipun Gupta To: Nikhil Agarwal To: Joerg Roedel To: Will Deacon To: Robin Murphy To: Lorenzo Pieralisi To: Marc Zyngier To: Thomas Gleixner To: Rob Herring To: Saravana Kannan To: Richard Zhu To: Lucas Stach To: Krzysztof Wilczyński To: Manivannan Sadhasivam To: Bjorn Helgaas To: Frank Li To: Sascha Hauer To: Pengutronix Kernel Team To: Fabio Estevam To: Juergen Gross To: Stefano Stabellini To: Oleksandr Tyshchenko Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: iommu@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: imx@lists.linux.dev Cc: xen-devel@lists.xenproject.org --- Charan Teja Kalla (1): of: Factor arguments passed to of_map_id() into a struct Robin Murphy (2): of: Add convenience wrappers for of_map_id() of: Respect #{iommu,msi}-cells in maps drivers/cdx/cdx_msi.c | 8 +- drivers/iommu/of_iommu.c | 6 +- drivers/irqchip/irq-gic-its-msi-parent.c | 11 +- drivers/of/base.c | 215 ++++++++++++++++++++++++------- drivers/of/irq.c | 31 ++++- drivers/pci/controller/dwc/pci-imx6.c | 34 +++-- drivers/pci/controller/pcie-apple.c | 6 +- drivers/xen/grant-dma-ops.c | 5 +- include/linux/of.h | 30 ++++- 9 files changed, 257 insertions(+), 89 deletions(-) --- base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31 change-id: 20260301-parse_iommu_cells-1c33768aebba Best regards, -- Vijayanand Jitta From xen-devel-bounces@lists.xenproject.org Fri Apr 24 05:57:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 05:57:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293120.1571027 (Exim 4.92) (envelope-from ) id 1wG9Xz-0006bJ-QX; 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a=ed25519-sha256; t=1777010232; l=18518; i=vijayanand.jitta@oss.qualcomm.com; s=20260301; h=from:subject:message-id; bh=wiBZojo0J7hwv8jza/KpZ8506QAT1cjvfjOKCApa6Wo=; b=dyovb5BdIrhkPQF+mCNMCfJmyuhdwXIWnaGvQc+aQdZ99bljLMJtwDkhvB5KUss3szckMv8f+ cAYk+DkjlsABxrXW1TO23901phEgBZxg3zuTMcERkBMPC35ZqHH7vUK X-Developer-Key: i=vijayanand.jitta@oss.qualcomm.com; a=ed25519; pk=Lpi7Cs3wHe8KZtqvyci7FTOLzsKpEHKGCaPNZw+1zRI= X-Proofpoint-GUID: ZePjOCX1nqGqpO9EZqWxtPVuH3_xmaUk X-Authority-Analysis: v=2.4 cv=R98z39RX c=1 sm=1 tr=0 ts=69eb065b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=8AirrxEcAAAA:8 a=VwQbUJbxAAAA:8 a=YNKo5iN9BcXwmsqDYIQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=ST-jHhOKWsTCqRlWije3:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI0MDA1MSBTYWx0ZWRfXzqAYPTzUZcrl R8HFEgTMp2V2QnHeWMCtedydkW5Gra6JiN0c3tdqgF8258H9bj78xDdPYFhR/FcSbX31LPhx12Z CIUo1Sv8fbvA/murojvB9atFiu3pJw9Rga5g8DY1G4zftQf68ce0e98Aa4VNpztli7VNumvNBF+ y954QV9CtsXV+c5DBQVeVGSffH1JtkOw9ZJ1+z2mWMbJe8OyldZ6TWjZgNMXcjq4M1X7ULhPUZ0 5Hv5r/unHCYa/Nh76YhFMOshuuRSvGNc1Z5aBL+7kP+hvpapqvZ58JUSeNm6YKYaqo5gT6GpfzB t5dloAs/nXgBr49nbTTi6AinWlUKWM85aJBo4kln/Y5unus7FSbWTUACFtxxYcUpdE2QLFqkKJq 4db0y+rkbbAa52SWFfw8RrMFoSOmzmCQgT/o8h7ThMAmFsycBIJZajBVOiJsRJ+GdGR7U54LGxD 1Iv3w7Pc3Td3E/5bbBw== X-Proofpoint-ORIG-GUID: ZePjOCX1nqGqpO9EZqWxtPVuH3_xmaUk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604240051 X-purgate-ID: tlsNG-16d1c6/1777010268-5357ED75-6D7A8B1E/0/0 X-purgate-type: clean X-purgate-size: 18579 From: Charan Teja Kalla Change of_map_id() to take a pointer to struct of_phandle_args instead of passing target device node and translated IDs separately. Update all callers accordingly. Add an explicit filter_np parameter to of_map_id() and of_map_msi_id() to separate the filter input from the output. Previously, the target parameter served dual purpose: as an input filter (if non-NULL, only match entries targeting that node) and as an output (receiving the matched node with a reference held). Now filter_np is the explicit input filter and arg->np is the pure output. Previously, of_map_id() would call of_node_put() on the matched node when a filter was provided, making reference ownership inconsistent. Remove this internal of_node_put() call so that of_map_id() now always transfers ownership of the matched node reference to the caller via arg->np. Callers are now consistently responsible for releasing this reference with of_node_put(arg->np) when done. Acked-by: Frank Li Suggested-by: Rob Herring (Arm) Suggested-by: Dmitry Baryshkov Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta --- drivers/cdx/cdx_msi.c | 7 ++-- drivers/iommu/of_iommu.c | 4 +- drivers/irqchip/irq-gic-its-msi-parent.c | 11 ++++-- drivers/of/base.c | 68 +++++++++++++++++--------------- drivers/of/irq.c | 30 +++++++++++--- drivers/pci/controller/dwc/pci-imx6.c | 32 +++++++-------- drivers/pci/controller/pcie-apple.c | 5 ++- drivers/xen/grant-dma-ops.c | 4 +- include/linux/of.h | 14 ++++--- 9 files changed, 104 insertions(+), 71 deletions(-) diff --git a/drivers/cdx/cdx_msi.c b/drivers/cdx/cdx_msi.c index 63b3544ec997..6924e07c7528 100644 --- a/drivers/cdx/cdx_msi.c +++ b/drivers/cdx/cdx_msi.c @@ -121,22 +121,23 @@ static int cdx_msi_prepare(struct irq_domain *msi_domain, struct device *dev, int nvec, msi_alloc_info_t *info) { + struct of_phandle_args msi_spec = {}; struct cdx_device *cdx_dev = to_cdx_device(dev); struct device *parent = cdx_dev->cdx->dev; struct msi_domain_info *msi_info; - u32 dev_id; int ret; /* Retrieve device ID from requestor ID using parent device */ - ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &dev_id); + ret = of_map_msi_id(parent->of_node, cdx_dev->msi_dev_id, NULL, &msi_spec); if (ret) { dev_err(dev, "of_map_id failed for MSI: %d\n", ret); return ret; } + of_node_put(msi_spec.np); #ifdef GENERIC_MSI_DOMAIN_OPS /* Set the device Id to be passed to the GIC-ITS */ - info->scratchpad[0].ul = dev_id; + info->scratchpad[0].ul = msi_spec.args[0]; #endif msi_info = msi_get_domain_info(msi_domain->parent); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index a511ecf21fcd..a18bb60f6f3d 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -45,10 +45,10 @@ static int of_iommu_configure_dev_id(struct device_node *master_np, struct device *dev, const u32 *id) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; int err; - err = of_map_iommu_id(master_np, *id, &iommu_spec.np, iommu_spec.args); + err = of_map_iommu_id(master_np, *id, &iommu_spec); if (err) return err; diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c index b63343a227a9..dd5f84b6470a 100644 --- a/drivers/irqchip/irq-gic-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -152,6 +152,8 @@ static int its_v5_pci_msi_prepare(struct irq_domain *domain, struct device *dev, static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u32 *dev_id, phys_addr_t *pa) { + struct device_node *msi_ctrl __free(device_node) = NULL; + struct of_phandle_args msi_spec = {}; struct of_phandle_iterator it; int ret; @@ -178,9 +180,12 @@ static int of_pmsi_get_msi_info(struct irq_domain *domain, struct device *dev, u } } - struct device_node *msi_ctrl __free(device_node) = NULL; - - return of_map_msi_id(dev->of_node, dev->id, &msi_ctrl, dev_id); + ret = of_map_msi_id(dev->of_node, dev->id, NULL, &msi_spec); + if (!ret) { + msi_ctrl = msi_spec.np; + *dev_id = msi_spec.args[0]; + } + return ret; } static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, diff --git a/drivers/of/base.c b/drivers/of/base.c index ae04487bd614..b3d002015192 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2102,36 +2102,37 @@ int of_find_last_cache_level(unsigned int cpu) * @id: device ID to map. * @map_name: property name of the map to use. * @map_mask_name: optional property name of the mask to use. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional device node to filter matches by, or NULL to match any. + * If non-NULL, only map entries targeting this node will be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] will contain the translated ID. If a map entry was + * matched, @arg->np will be set to the target node with a reference + * held that the caller must release with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that - * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or - * @id_out may be NULL if only the other is required. If @target points to - * a non-NULL device node pointer, only entries targeting that node will be - * matched; if it points to a NULL value, it will receive the device node of - * the first matching target phandle, with a reference held. + * ID, as per the "iommu-map" and "msi-map" bindings. * * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; int map_len; const __be32 *map = NULL; - if (!np || !map_name || (!target && !id_out)) + if (!np || !map_name || !arg) return -EINVAL; map = of_get_property(np, map_name, &map_len); if (!map) { - if (target) + if (filter_np) return -ENODEV; /* Otherwise, no map implies no translation */ - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } @@ -2173,18 +2174,14 @@ int of_map_id(const struct device_node *np, u32 id, if (!phandle_node) return -ENODEV; - if (target) { - if (*target) - of_node_put(phandle_node); - else - *target = phandle_node; - - if (*target != phandle_node) - continue; + if (filter_np && filter_np != phandle_node) { + of_node_put(phandle_node); + continue; } - if (id_out) - *id_out = masked_id - id_base + out_base; + arg->np = phandle_node; + arg->args[0] = masked_id - id_base + out_base; + arg->args_count = 1; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", np, map_name, map_mask, id_base, out_base, @@ -2193,11 +2190,11 @@ int of_map_id(const struct device_node *np, u32 id, } pr_info("%pOF: no %s translation for id 0x%x on %pOF\n", np, map_name, - id, target && *target ? *target : NULL); + id, filter_np); /* Bypasses translation */ - if (id_out) - *id_out = id; + arg->args[0] = id; + arg->args_count = 1; return 0; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2207,17 +2204,19 @@ EXPORT_SYMBOL_GPL(of_map_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", target, id_out); + return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2226,16 +2225,21 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * @np: root complex device node. * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the msi-map table. - * @target: optional pointer to a target device node. - * @id_out: optional pointer to receive the translated ID. + * @filter_np: optional MSI controller node to filter matches by, or NULL + * to match any. If non-NULL, only map entries targeting this node will + * be matched. + * @arg: pointer to a &struct of_phandle_args for the result. On success, + * @arg->args[0] contains the translated ID. If a map entry was matched, + * @arg->np holds a reference to the target node that the caller must + * release with of_node_put(). * * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", target, id_out); + return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/drivers/of/irq.c b/drivers/of/irq.c index e37c1b3f8736..4040467742c4 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -796,19 +796,22 @@ static int of_check_msi_parent(struct device_node *dev_node, struct device_node /** * of_msi_xlate - map a MSI ID and find relevant MSI controller node * @dev: device for which the mapping is to be done. - * @msi_np: Pointer to target MSI controller node + * @msi_np: Pointer to target MSI controller node, or NULL if the caller + * only needs the translated ID without receiving the controller node. + * If non-NULL and pointing to a non-NULL node, only entries targeting + * that node will be matched. If non-NULL and pointing to NULL, it will + * receive the first matching target node with a reference held. * @id_in: Device ID. * * Walk up the device hierarchy looking for devices with a "msi-map" * or "msi-parent" property. If found, apply the mapping to @id_in. - * If @msi_np points to a non-NULL device node pointer, only entries targeting - * that node will be matched; if it points to a NULL value, it will receive the - * device node of the first matching target phandle, with a reference held. * * Returns: The mapped MSI id. */ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) { + struct device_node *local_np = NULL; + struct device_node **np = msi_np ?: &local_np; struct device *parent_dev; u32 id_out = id_in; @@ -817,11 +820,26 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in) * "msi-map" or an "msi-parent" property. */ for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) { - if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &id_out)) + struct of_phandle_args msi_spec = {}; + + if (!of_map_msi_id(parent_dev->of_node, id_in, *np, &msi_spec)) { + /* + * Pass-through result: no msi-map on this node (or no + * matching entry). Keep walking up the hierarchy. + */ + if (!msi_spec.np) + continue; + id_out = msi_spec.args[0]; + if (!*np) + *np = msi_spec.np; + else + of_node_put(msi_spec.np); break; - if (!of_check_msi_parent(parent_dev->of_node, msi_np)) + } + if (!of_check_msi_parent(parent_dev->of_node, np)) break; } + of_node_put(local_np); return id_out; } EXPORT_SYMBOL_GPL(of_msi_xlate); diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index bff8289f804a..c0544d9c0921 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1137,30 +1137,32 @@ static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) { + struct of_phandle_args iommu_spec = {}; + struct of_phandle_args msi_spec = {}; struct device *dev = imx_pcie->pci->dev; - struct device_node *target; u32 sid_i, sid_m; int err_i, err_m; u32 sid = 0; - target = NULL; - err_i = of_map_iommu_id(dev->of_node, rid, &target, &sid_i); - if (target) { - of_node_put(target); - } else { + err_i = of_map_iommu_id(dev->of_node, rid, &iommu_spec); + if (!err_i) + sid_i = iommu_spec.args[0]; + of_node_put(iommu_spec.np); + if (!err_i && !iommu_spec.np) { /* - * "target == NULL && err_i == 0" means RID out of map range. - * Use 1:1 map RID to streamID. Hardware can't support this - * because the streamID is only 6 bits + * "iommu_spec.np == NULL && err_i == 0" means RID out of map + * range. Use 1:1 map RID to streamID. Hardware can't support + * this because the streamID is only 6 bits. */ err_i = -EINVAL; } - target = NULL; - err_m = of_map_msi_id(dev->of_node, rid, &target, &sid_m); - + err_m = of_map_msi_id(dev->of_node, rid, NULL, &msi_spec); + if (!err_m) + sid_m = msi_spec.args[0]; + of_node_put(msi_spec.np); /* - * err_m target + * err_m msi_spec.np * 0 NULL RID out of range. Use 1:1 map RID to * streamID, Current hardware can't * support it, so return -EINVAL. @@ -1168,10 +1170,8 @@ static int imx_pcie_add_lut_by_rid(struct imx_pcie *imx_pcie, u32 rid) * 0 != NULL Get correct streamID from RID * != 0 != NULL Invalid combination */ - if (!err_m && !target) + if (!err_m && !msi_spec.np) return -EINVAL; - else if (target) - of_node_put(target); /* Find streamID map entry for RID in msi-map */ /* * msi-map iommu-map diff --git a/drivers/pci/controller/pcie-apple.c b/drivers/pci/controller/pcie-apple.c index a0937b7b3c4d..c2cffc0659f4 100644 --- a/drivers/pci/controller/pcie-apple.c +++ b/drivers/pci/controller/pcie-apple.c @@ -755,6 +755,7 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d { u32 sid, rid = pci_dev_id(pdev); struct apple_pcie_port *port; + struct of_phandle_args iommu_spec = {}; int idx, err; port = apple_pcie_get_port(pdev); @@ -764,10 +765,12 @@ static int apple_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_d dev_dbg(&pdev->dev, "added to bus %s, index %d\n", pci_name(pdev->bus->self), port->idx); - err = of_map_iommu_id(port->pcie->dev->of_node, rid, NULL, &sid); + err = of_map_iommu_id(port->pcie->dev->of_node, rid, &iommu_spec); if (err) return err; + of_node_put(iommu_spec.np); + sid = iommu_spec.args[0]; mutex_lock(&port->pcie->lock); idx = bitmap_find_free_region(port->sid_map, port->sid_map_sz, 0); diff --git a/drivers/xen/grant-dma-ops.c b/drivers/xen/grant-dma-ops.c index 1b7696b2d762..2aa1a772a0ff 100644 --- a/drivers/xen/grant-dma-ops.c +++ b/drivers/xen/grant-dma-ops.c @@ -319,13 +319,13 @@ static int xen_dt_grant_init_backend_domid(struct device *dev, struct device_node *np, domid_t *backend_domid) { - struct of_phandle_args iommu_spec = { .args_count = 1 }; + struct of_phandle_args iommu_spec = {}; if (dev_is_pci(dev)) { struct pci_dev *pdev = to_pci_dev(dev); u32 rid = PCI_DEVID(pdev->bus->number, pdev->devfn); - if (of_map_iommu_id(np, rid, &iommu_spec.np, iommu_spec.args)) { + if (of_map_iommu_id(np, rid, &iommu_spec)) { dev_dbg(dev, "Cannot translate ID\n"); return -ESRCH; } diff --git a/include/linux/of.h b/include/linux/of.h index fe841f3cc747..8548cd9eb4f1 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -463,13 +463,13 @@ bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + struct of_phandle_args *arg); int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out); + const struct device_node *filter_np, struct of_phandle_args *arg); phys_addr_t of_dma_get_max_cpu_address(struct device_node *np); @@ -935,19 +935,21 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag static inline int of_map_id(const struct device_node *np, u32 id, const char *map_name, const char *map_mask_name, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_iommu_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + struct of_phandle_args *arg) { return -EINVAL; } static inline int of_map_msi_id(const struct device_node *np, u32 id, - struct device_node **target, u32 *id_out) + const struct device_node *filter_np, + struct of_phandle_args *arg) { return -EINVAL; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 05:58:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 05:58:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293128.1571037 (Exim 4.92) (envelope-from ) id 1wG9YA-00073e-8e; Fri, 24 Apr 2026 05:58:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293128.1571037; Fri, 24 Apr 2026 05:58:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wG9YA-00073V-5c; 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Thu, 23 Apr 2026 22:57:55 -0700 (PDT) From: Vijayanand Jitta Date: Fri, 24 Apr 2026 11:26:10 +0530 Subject: [PATCH v14 3/3] of: Respect #{iommu,msi}-cells in maps MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260424-parse_iommu_cells-v14-3-fd02f11b6c38@oss.qualcomm.com> References: <20260424-parse_iommu_cells-v14-0-fd02f11b6c38@oss.qualcomm.com> In-Reply-To: <20260424-parse_iommu_cells-v14-0-fd02f11b6c38@oss.qualcomm.com> To: Nipun Gupta , Nikhil Agarwal , Joerg Roedel , Will Deacon , Robin Murphy , Marc Zyngier , Lorenzo Pieralisi , Thomas Gleixner , Saravana Kannan , Richard Zhu , Lucas Stach , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Prakash Gupta , Vikash Garodia Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, linux-arm-msm@vger.kernel.org, Vijayanand Jitta , Charan Teja Kalla X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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This typically does happen to be the case, but is not actually enforced (and the PCI msi-map binding even explicitly states support for 0 or 1 cells) - as a result we've now ended up with dodgy DTs out in the field which depend on this behaviour to map a 1-cell specifier for a 2-cell provider, despite that being bogus per the bindings themselves. Since there is some potential use in being able to map at least single input IDs to multi-cell output specifiers (and properly support 0-cell outputs as well), add support for properly parsing and using the target nodes' #cells values, albeit with the unfortunate complication of still having to work around expectations of the old behaviour too. Since there are multi-cell output specifiers, the callers of of_map_id() may need to get the exact cell output value for further processing. Update of_map_id() to set args_count in the output to reflect the actual number of output specifier cells. Signed-off-by: Robin Murphy Signed-off-by: Charan Teja Kalla Signed-off-by: Vijayanand Jitta --- drivers/of/base.c | 157 +++++++++++++++++++++++++++++++++++++++++------------ include/linux/of.h | 6 +- 2 files changed, 125 insertions(+), 38 deletions(-) diff --git a/drivers/of/base.c b/drivers/of/base.c index b3d002015192..2554e4f1a181 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -2096,18 +2096,48 @@ int of_find_last_cache_level(unsigned int cpu) return cache_level; } +/* + * Some DTs have an iommu-map targeting a 2-cell IOMMU node while + * specifying only 1 cell. Fortunately they all consist of value '1' + * as the 2nd cell entry with the same target, so check for that pattern. + * + * Example: + * IOMMU node: + * #iommu-cells = <2>; + * + * Device node: + * iommu-map = <0x0000 &smmu 0x0000 0x1>, + * <0x0100 &smmu 0x0100 0x1>; + */ +static bool of_check_bad_map(const __be32 *map, int len) +{ + __be32 phandle = map[1]; + + if (len % 4) + return false; + for (int i = 0; i < len; i += 4) { + if (map[i + 1] != phandle || map[i + 3] != cpu_to_be32(1)) + return false; + } + return true; +} + /** * of_map_id - Translate an ID through a downstream mapping. * @np: root complex device node. * @id: device ID to map. * @map_name: property name of the map to use. + * @cells_name: property name of target specifier cells. * @map_mask_name: optional property name of the mask to use. * @filter_np: optional device node to filter matches by, or NULL to match any. * If non-NULL, only map entries targeting this node will be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] will contain the translated ID. If a map entry was - * matched, @arg->np will be set to the target node with a reference - * held that the caller must release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * as defined by @cells_name in the target node, and + * @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np will be set + * to the target node with a reference held that the caller must release + * with of_node_put(). * * Given a device ID, look up the appropriate implementation-defined * platform ID and/or the target device which receives transactions on that @@ -2116,17 +2146,19 @@ int of_find_last_cache_level(unsigned int cpu) * Return: 0 on success or a standard error code on failure. */ int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { u32 map_mask, masked_id; - int map_len; + int map_bytes, map_len, offset = 0; + bool bad_map = false; const __be32 *map = NULL; if (!np || !map_name || !arg) return -EINVAL; - map = of_get_property(np, map_name, &map_len); + map = of_get_property(np, map_name, &map_bytes); if (!map) { if (filter_np) return -ENODEV; @@ -2136,11 +2168,9 @@ int of_map_id(const struct device_node *np, u32 id, return 0; } - if (!map_len || map_len % (4 * sizeof(*map))) { - pr_err("%pOF: Error: Bad %s length: %d\n", np, - map_name, map_len); - return -EINVAL; - } + if (map_bytes % sizeof(*map)) + goto err_map_len; + map_len = map_bytes / sizeof(*map); /* The default is to select all bits. */ map_mask = 0xffffffff; @@ -2153,39 +2183,84 @@ int of_map_id(const struct device_node *np, u32 id, of_property_read_u32(np, map_mask_name, &map_mask); masked_id = map_mask & id; - for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) { + + while (offset < map_len) { struct device_node *phandle_node; - u32 id_base = be32_to_cpup(map + 0); - u32 phandle = be32_to_cpup(map + 1); - u32 out_base = be32_to_cpup(map + 2); - u32 id_len = be32_to_cpup(map + 3); + u32 id_base, phandle, id_len, id_off, cells = 0; + const __be32 *out_base; + + if (map_len - offset < 2) + goto err_map_len; + + id_base = be32_to_cpup(map + offset); if (id_base & ~map_mask) { - pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores id-base (0x%x)\n", - np, map_name, map_name, - map_mask, id_base); + pr_err("%pOF: Invalid %s translation - %s (0x%x) ignores id-base (0x%x)\n", + np, map_name, map_mask_name, map_mask, id_base); return -EFAULT; } - if (masked_id < id_base || masked_id >= id_base + id_len) - continue; - + phandle = be32_to_cpup(map + offset + 1); phandle_node = of_find_node_by_phandle(phandle); if (!phandle_node) return -ENODEV; + if (bad_map) { + cells = 1; + } else if (of_property_read_u32(phandle_node, cells_name, &cells)) { + pr_err("%pOF: missing %s property\n", phandle_node, cells_name); + of_node_put(phandle_node); + return -EINVAL; + } + + if (map_len - offset < 3 + cells) { + of_node_put(phandle_node); + goto err_map_len; + } + + if (offset == 0 && cells == 2) { + bad_map = of_check_bad_map(map, map_len); + if (bad_map) { + pr_warn_once("%pOF: %s mismatches target %s, assuming extra cell of 0\n", + np, map_name, cells_name); + cells = 1; + } + } + + out_base = map + offset + 2; + offset += 3 + cells; + + id_len = be32_to_cpup(map + offset - 1); + if (id_len > 1 && cells > 1) { + /* + * With 1 output cell we reasonably assume its value + * has a linear relationship to the input; with more, + * we'd need help from the provider to know what to do. + */ + pr_err("%pOF: Unsupported %s - cannot handle %d-ID range with %d-cell output specifier\n", + np, map_name, id_len, cells); + of_node_put(phandle_node); + return -EINVAL; + } + id_off = masked_id - id_base; + if (masked_id < id_base || id_off >= id_len) { + of_node_put(phandle_node); + continue; + } + if (filter_np && filter_np != phandle_node) { of_node_put(phandle_node); continue; } arg->np = phandle_node; - arg->args[0] = masked_id - id_base + out_base; - arg->args_count = 1; + for (int i = 0; i < cells; i++) + arg->args[i] = id_off + be32_to_cpu(out_base[i]); + arg->args_count = cells; pr_debug("%pOF: %s, using mask %08x, id-base: %08x, out-base: %08x, length: %08x, id: %08x -> %08x\n", - np, map_name, map_mask, id_base, out_base, - id_len, id, masked_id - id_base + out_base); + np, map_name, map_mask, id_base, be32_to_cpup(out_base), + id_len, id, id_off + be32_to_cpup(out_base)); return 0; } @@ -2196,6 +2271,10 @@ int of_map_id(const struct device_node *np, u32 id, arg->args[0] = id; arg->args_count = 1; return 0; + +err_map_len: + pr_err("%pOF: Error: Bad %s length: %d\n", np, map_name, map_bytes); + return -EINVAL; } EXPORT_SYMBOL_GPL(of_map_id); @@ -2205,18 +2284,21 @@ EXPORT_SYMBOL_GPL(of_map_id); * @id: Requester ID of the device (e.g. PCI RID/BDF or a platform * stream/device ID) used as the lookup key in the iommu-map table. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "iommu-map" and "iommu-map-mask". + * Convenience wrapper around of_map_id() using "iommu-map", "#iommu-cells", + * and "iommu-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_iommu_id(const struct device_node *np, u32 id, struct of_phandle_args *arg) { - return of_map_id(np, id, "iommu-map", "iommu-map-mask", NULL, arg); + return of_map_id(np, id, "iommu-map", "#iommu-cells", "iommu-map-mask", NULL, arg); } EXPORT_SYMBOL_GPL(of_map_iommu_id); @@ -2229,17 +2311,20 @@ EXPORT_SYMBOL_GPL(of_map_iommu_id); * to match any. If non-NULL, only map entries targeting this node will * be matched. * @arg: pointer to a &struct of_phandle_args for the result. On success, - * @arg->args[0] contains the translated ID. If a map entry was matched, - * @arg->np holds a reference to the target node that the caller must - * release with of_node_put(). + * @arg->args_count will be set to the number of output specifier cells + * and @arg->args[0..args_count-1] will contain the translated output + * specifier values. If a map entry was matched, @arg->np holds a + * reference to the target node that the caller must release with + * of_node_put(). * - * Convenience wrapper around of_map_id() using "msi-map" and "msi-map-mask". + * Convenience wrapper around of_map_id() using "msi-map", "#msi-cells", + * and "msi-map-mask". * * Return: 0 on success or a standard error code on failure. */ int of_map_msi_id(const struct device_node *np, u32 id, const struct device_node *filter_np, struct of_phandle_args *arg) { - return of_map_id(np, id, "msi-map", "msi-map-mask", filter_np, arg); + return of_map_id(np, id, "msi-map", "#msi-cells", "msi-map-mask", filter_np, arg); } EXPORT_SYMBOL_GPL(of_map_msi_id); diff --git a/include/linux/of.h b/include/linux/of.h index 8548cd9eb4f1..51ac8539f2c3 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -462,7 +462,8 @@ const char *of_prop_next_string(const struct property *prop, const char *cur); bool of_console_check(const struct device_node *dn, char *name, int index); int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg); int of_map_iommu_id(const struct device_node *np, u32 id, @@ -934,7 +935,8 @@ static inline void of_property_clear_flag(struct property *p, unsigned long flag } static inline int of_map_id(const struct device_node *np, u32 id, - const char *map_name, const char *map_mask_name, + const char *map_name, const char *cells_name, + const char *map_mask_name, const struct device_node *filter_np, struct of_phandle_args *arg) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 06:34:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 06:34:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293166.1571046 (Exim 4.92) (envelope-from ) id 1wGA7H-0000Ah-U4; Fri, 24 Apr 2026 06:34:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293166.1571046; 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These regions may be marked >> no-map in DT and therefore are not part of the kernel linear map. >> In such cases, pfn_valid() still returns true, but phys_to_virt() >> is not valid and cache maintenance via arch_sync_dma_* will fault. >> >> Prevent this by excluding devices with a private DMA memory pool >> (dev->dma_mem) from the arch_sync_dma_* fast path, and always >> fall back to xen_dma_sync_* for those devices to avoid invalid >> phys_to_virt() conversions for no-map DMA memory while preserving the >> existing fast path for normal, linear-mapped RAM. > >I think this is the same sort of weirdness the other two CC threads are >dealing with.. We already have two different flags indicating the >cache flush should be skipped, it would make more sense to have the >swiotlb mangle the flags, just like for cc. > >https://lore.kernel.org/r/20260420061415.3650870-1-aneesh.kumar@kernel.org > >Then you know that the swiotlb was used and it should flow down to >here. Xen fully implements dev->dma_ops and does not leak hypervisor-specific semantics outside of it. The issue is that the existing DMA attribute model only distinguishes between "CPU sync required" and "no sync required at all". Xen needs a third case: CPU cache sync must be skipped, but platform-level DMA synchronization remains mandatory. This is not a generic DMA extension but a constraint of Xen's DMA model when mapping private or foreign memory that is not CPU-mapped. > >> * physical address to use is returned. >> @@ -262,7 +267,8 @@ static dma_addr_t xen_swiotlb_map_phys(struct device *dev, phys_addr_t phys, >> >> done: >> if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { >> - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr)))) { >> + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr))) && >> + !dev_has_private_dma_pool(dev)) { > >Also this pfn_valid() is totally bogus. Unless DMA_ATTR_MMIO the phys >must have a struct page, be pfn_valid, etc. > >This is why you are getting into trouble here, beacuse swiotlb created >a non-struct page address and passed it to lower layers without >setting something like DMA_ATTR_MMIO.. See above. xen swiotlb maybe a bit misleading, it is not kind of linux swiotlb. Juergen, Stefano, Please help correct if I am wrong or I may miss something. Thanks, Peng > >Jason > From xen-devel-bounces@lists.xenproject.org Fri Apr 24 07:01:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 07:01:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293194.1571064 (Exim 4.92) (envelope-from ) id 1wGAXN-0008A3-AC; Fri, 24 Apr 2026 07:01:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293194.1571064; Fri, 24 Apr 2026 07:01:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGAXN-00089w-6M; Fri, 24 Apr 2026 07:01:17 +0000 Received: by outflank-mailman (input) for mailman id 1293194; Fri, 24 Apr 2026 07:01:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGAXL-00089q-Sz for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 07:01:16 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGAXL-006jNo-6R for xen-devel@lists.xenproject.org; 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These regions may be marked >> no-map in DT and therefore are not part of the kernel linear map. >> In such cases, pfn_valid() still returns true, but phys_to_virt() >> is not valid and cache maintenance via arch_sync_dma_* will fault. >> >> Prevent this by excluding devices with a private DMA memory pool >> (dev->dma_mem) from the arch_sync_dma_* fast path, and always >> fall back to xen_dma_sync_* for those devices to avoid invalid >> phys_to_virt() conversions for no-map DMA memory while preserving the >> existing fast path for normal, linear-mapped RAM. >> >> Signed-off-by: Peng Fan >> --- >> drivers/xen/swiotlb-xen.c | 17 +++++++++++++---- >> 1 file changed, 13 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c >> index 2cbf2b588f5b20cfbf9e83a8339dc22092c9559a..b1445df99d9a8f1d18a83b8c413bada6e5579209 100644 >> --- a/drivers/xen/swiotlb-xen.c >> +++ b/drivers/xen/swiotlb-xen.c >> @@ -195,6 +195,11 @@ xen_swiotlb_free_coherent(struct device *dev, size_t size, void *vaddr, >> } >> #endif /* CONFIG_X86 */ >> +static inline bool dev_has_private_dma_pool(struct device *dev) >> +{ >> + return dev && dev->dma_mem; >> +} >> + > >I don't think this will compile on x86. My bad, I only tried the build for ARM64. I use below changes, if it looks good. #ifdef CONFIG_ARM64 static inline bool dev_has_private_dma_pool(struct device *dev) { return dev && dev->dma_mem; } #else static inline bool dev_has_private_dma_pool(struct device *dev) { return false; } #endif Thanks, Peng > > >Juergen From xen-devel-bounces@lists.xenproject.org Fri Apr 24 07:49:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 07:49:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293215.1571074 (Exim 4.92) (envelope-from ) id 1wGBIM-0001Gr-SF; Fri, 24 Apr 2026 07:49:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293215.1571074; Fri, 24 Apr 2026 07:49:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGBIM-0001Gj-LP; Fri, 24 Apr 2026 07:49:50 +0000 Received: by outflank-mailman (input) for mailman id 1293215; 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This also allows to avoid the need to allocate and destroy > > rangesets for each device. > > > > Move the rangesets from struct vpci_bar to struct vpci_vcpu and perform > > (de-)allocation with vcpu (de-)allocation. Introduce RANGESET_DESTROY() > > macro to free a rangeset and set the pointer to NULL. > > > > Amends: 622bdd962822 ("vpci/header: handle p2m range sets per BAR") > > Signed-off-by: Mykyta Poturai > > Signed-off-by: Stewart Hildebrand > > --- > > It seems a bit awkward to introduce various vpci vcpu alloc/dealloc > > functions here only to undo most of it in the next patch. Thoughts on > > folding the next patch into this one? > > > > v3->v4: > > * no change > > There are some complexities here due to the patch being part of two series. > Once Mykyta re-submits the SR-IOV series, we'll have two (likely diverging) > v4-s. Already here ... > > > v2->v3: > > * new patch in this series, borrowed from [1] > > * add Amends tag > > * remove unused variable i due to rebasing over 998060dd9101 ("vPCI: > > move vpci_init_capabilities() to a separate file") > > * enclose entire struct vpci_vcpu inside #ifdef __XEN__ > > * s/bar_mem/mem/ > > * use ARRAY_SIZE > > * put init/destroy in functions > > * only allocate for domains with vPCI and idle domain > > * replace 'if ( !mem ) continue;' with ASSERT > > ... the v3 there has one more item on this ChangeLog list ("* synced with > BAR write with memory decoding enabled series[1]"), albeit maybe (now that I > read it again) this merely is the counterpart of the first bullet point here. > It would be clearer if there the other series' title was supplied verbatim > and in quotes. Indeed. I reviewed the one from Mykyta part of the SR-IOV series. I see both Jan and myself made similar comments, I'm also a bit concerned about the claim that moving to per-vCPU ranges is better than using per-pdev ranges, see the comments on the SR-IOV series. Overall however it seems to me for the SR-IOV series we will need to allocate mapping tasks on demand, so we will neither have per-vCPU or per-pdev per-allocated tasks (that include the rangeset). I think we need a pre-series that introduce the map queueing plus the on-demand allocation of tasks in a clean way (iow: there's no need to introduce per-vCPU tasks if they need to be replaced with runtime allocation tasks for the SR-IOV support). Then both this series and the SR-IOV one should be rebased over that work. Thanks, Roger. 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-c201ff/1777017680-E95A7443-AC0616D6/10/73395122804 X-purgate-type: spam X-purgate-size: 883 On 4/23/26 6:07 PM, Juergen Gross wrote: > Signed-off-by: Juergen Gross > --- > CHANGELOG.md | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/CHANGELOG.md b/CHANGELOG.md > index bb41d89997..ce46020dbd 100644 > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) > ### Added > - Support for per-domain Xenstore quota in C xenstored (includes > xenstore-stubdom), libxl and xl. > + - Support for Xenstore watch depth feature in C xenstored (includes > + xenstore-stubdom). > - On x86: > - Support for Bus Lock Threshold on AMD Zen5 and later CPUs, used by Xen to > mitigate (by rate-limiting) the system wide impact of an HVM guest Acked-by: Oleksii Kurochko Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Fri Apr 24 08:38:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 08:38:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293282.1571091 (Exim 4.92) (envelope-from ) id 1wGC3C-0005c1-Qh; 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This will allow hardware domain to reposition > BARs without affecting the memory decoding bit. > > Signed-off-by: Stewart Hildebrand > --- > This also lays some groundwork to allow domUs to toggle the guest view > without affecting hardware, a step toward addressing the FIXME in [1]. > > [1] https://lore.kernel.org/xen-devel/20250814160358.95543-4-roger.pau@citrix.com/ The deferred toggling of the command register bits seems overly complex IMO. It would be much simpler if domUs simply don't get to play with the real decoding bits. For the hardware domain we could toggle the decoding bits ahead of the mapping operations, so that we don't have to defer the toggling after mappings have been sorted. Long term we should aim to remove the cmd field from vpci_map_task struct. I don't mind if you want to pick the patch in [1] in your series, as we could then drop the cmd field and possibly simplify some of the logic in this patch by no longer requiring the deferred write to the command register? > v3->v4: > * rebase on dynamically allocated map queue > > v2->v3: > * use bool > * switch to task->map in more places > > v1->v2: > * new patch > --- > xen/drivers/vpci/header.c | 43 +++++++++++++++++++++------------------ > xen/include/xen/vpci.h | 1 + > 2 files changed, 24 insertions(+), 20 deletions(-) > > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 146915e28c50..20fe380552f4 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -117,11 +117,12 @@ static int cf_check map_range( > * BAR's enable bit has changed with the memory decoding bit already enabled. > * If rom_only is not set then it's the memory decoding bit that changed. > */ > -static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd, > - bool rom_only) > +static void modify_decoding(const struct pci_dev *pdev, > + struct vpci_map_task *task) task wants to be const here, unless further patches require modifying task inside of modify_decoding(). Thanks, Roger. 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If > firmware initializes a 32-bit BAR to a bad address, Linux may try to > write a new address to the 32-bit BAR without disabling memory decoding. > Since Xen refuses such writes, the BAR (and thus PCI device) will be > non-functional. > > Allow the hardware domain to issue 32-bit BAR writes with memory > decoding enabled. This increases the compatibility of PVH dom0 with more > hardware. > > Note that Linux aims at disabling memory decoding before writing 64-bit > BARs. Continue to refuse 64-bit BAR writes in Xen while those BARs are > mapped for now to avoid mapping half-updated BARs in p2m. While Linux does the disabling for 64bit BARs, I wonder if at some we will need to handle 64bit BAR writes anyway for other OSes, specially with domU support. > Resolves: https://gitlab.com/xen-project/xen/-/issues/197 > Signed-off-by: Stewart Hildebrand > --- > v3->v4: > * rebase on dynamically allocated map queue > > v2->v3: > * minor tweaks for fixed number of map/unmap slots > > v1->v2: > * rework on top of queued BAR map/unmap operation machinery > > RFC->v1: > * keep memory decoding enabled in hardware > * allow write while memory decoding is enabled for 32-bit BARs only > * rework BAR mapping machinery to support unmap-then-map operation > --- > xen/drivers/vpci/header.c | 32 +++++++++++++++++++++++--------- > 1 file changed, 23 insertions(+), 9 deletions(-) > > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 20fe380552f4..dc4f585b4e40 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -670,6 +670,7 @@ static void cf_check bar_write( > { > struct vpci_bar *bar = data; > bool hi = false; > + uint16_t cmd = 0; > > ASSERT(is_hardware_domain(pdev->domain)); > > @@ -683,19 +684,29 @@ static void cf_check bar_write( > val &= PCI_BASE_ADDRESS_MEM_MASK; > > /* > - * Xen only cares whether the BAR is mapped into the p2m, so allow BAR > - * writes as long as the BAR is not mapped into the p2m. > + * Allow 64-bit BAR writes only when the BAR is not mapped in p2m. Always > + * allow 32-bit BAR writes. > */ > if ( bar->enabled ) > { > - /* If the value written is the current one avoid printing a warning. */ > - if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) > - gprintk(XENLOG_WARNING, > - "%pp: ignored BAR %zu write while mapped\n", > - &pdev->sbdf, bar - pdev->vpci->header.bars + hi); > - return; > - } > + if ( bar->type == VPCI_BAR_MEM32 ) > + { > + if ( val == bar->addr ) > + return; > > + cmd = pci_conf_read16(pdev->sbdf, PCI_COMMAND); > + modify_bars(pdev, cmd, false, false); > + } > + else > + { > + /* If the value written is the same avoid printing a warning. */ > + if ( val != (uint32_t)(bar->addr >> (hi ? 32 : 0)) ) > + gprintk(XENLOG_WARNING, > + "%pp: ignored BAR %zu write while mapped\n", > + &pdev->sbdf, bar - pdev->vpci->header.bars + hi); > + return; > + } > + } > > /* > * Update the cached address, so that when memory decoding is enabled > @@ -715,6 +726,9 @@ static void cf_check bar_write( > } > > pci_conf_write32(pdev->sbdf, reg, val); I don't think it matters a lot, but here we are changing the position of the BAR in the host memory map while the mappings are still active. > + > + if ( bar->enabled ) > + modify_bars(pdev, cmd, false, true); > } > > static void cf_check guest_mem_bar_write(const struct pci_dev *pdev, As it's in context here - we possibly want to do something similar with guest writes now that we can? While we might not have a user-case for domUs ATM, I think it's vest if we also fix that use case at the same time that dom0 is fixed (unless there's something that prevents it). Thanks, Roger. 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Add new host bridge op "fixup_bar" that allows > platforms to modify BAR addresses before they are mapped. > > Because x86 don't have support for PCI Host Bridge drivers, add another > level of indirection in form of platform_pci_fixup_bar() function, that > will call host bridge op on ARM and do nothing on x86. > > Signed-off-by: Mykyta Poturai > --- > xen/arch/arm/include/asm/pci.h | 3 +++ > xen/arch/arm/include/asm/vpci.h | 9 +++++++++ > xen/arch/arm/vpci.c | 12 ++++++++++++ > xen/arch/x86/include/asm/vpci.h | 6 ++++++ > xen/drivers/vpci/header.c | 2 ++ > 5 files changed, 32 insertions(+) > > diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.h > index 7c3211823f..398a4eb746 100644 > --- a/xen/arch/arm/include/asm/pci.h > +++ b/xen/arch/arm/include/asm/pci.h > @@ -80,6 +80,9 @@ struct pci_ops { > void (*init_bus_range)(struct dt_device_node *dev, > struct pci_host_bridge *bridge, > struct pci_config_window *cfg); > + void (*fixup_bar)(struct pci_host_bridge *bridge, > + unsigned int bar_num, > + paddr_t *addr); > }; > > /* > diff --git a/xen/arch/arm/include/asm/vpci.h b/xen/arch/arm/include/asm/vpci.h > index 0cc6f5a105..f5c817a51c 100644 > --- a/xen/arch/arm/include/asm/vpci.h > +++ b/xen/arch/arm/include/asm/vpci.h > @@ -16,6 +16,10 @@ struct vpci_arch_msix_entry { > > int domain_vpci_init(struct domain *d); > unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d); > + > +void platform_pci_fixup_bar(const struct pci_dev *pdev, unsigned int bar_num, > + paddr_t *addr); > + > #else > static inline int domain_vpci_init(struct domain *d) > { > @@ -26,6 +30,11 @@ static inline unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) > { > return 0; > } > + > +static inline void platform_pci_fixup_bar(const struct pci_dev *pdev, > + unsigned int bar_num, > + paddr_t *addr) > +{} > #endif /* CONFIG_HAS_VPCI */ > > #endif /* ARM_VPCI_H */ > diff --git a/xen/arch/arm/vpci.c b/xen/arch/arm/vpci.c > index d41aa383a8..ec6efec22e 100644 > --- a/xen/arch/arm/vpci.c > +++ b/xen/arch/arm/vpci.c > @@ -189,6 +189,18 @@ unsigned int domain_vpci_get_num_mmio_handlers(struct domain *d) > return 1; > } > > +void platform_pci_fixup_bar(const struct pci_dev *pdev, > + unsigned int bar_num, > + paddr_t *addr) > +{ > + struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->sbdf.seg, pdev->sbdf.bus); > + > + if ( bridge->ops->fixup_bar ) > + { > + bridge->ops->fixup_bar(bridge, bar_num, addr); > + } > +} > + > /* > * Local variables: > * mode: C > diff --git a/xen/arch/x86/include/asm/vpci.h b/xen/arch/x86/include/asm/vpci.h > index c501ff1709..a05b70abbf 100644 > --- a/xen/arch/x86/include/asm/vpci.h > +++ b/xen/arch/x86/include/asm/vpci.h > @@ -16,6 +16,12 @@ struct vpci_arch_msix_entry { > int pirq; > }; > > +/* X86 does not require PCI BAR modifications */ > +static inline void platform_pci_fixup_bar(const struct pci_dev *pdev, > + unsigned int bar_num, > + paddr_t *addr) > +{} > + > #endif /* X86_VPCI_H */ > > /* > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index a760d8c32f..d89e43354c 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -882,6 +882,8 @@ int vpci_init_header(struct pci_dev *pdev) > bars[i].size = size; > bars[i].prefetchable = val & PCI_BASE_ADDRESS_MEM_PREFETCH; > > + platform_pci_fixup_bar(pdev, i, &bars[i].addr); You do this for vpci_init_header(), but don't you also need to do it for bar_write(), in case dom0 decides to relocate the BAR? Also - I would assume that both the firmware and dom0 are aware of this limitation, and hence wonder why you need this fixup in Xen? Thanks, Roger. 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While the vulnerability has no mitigations (aside not running > 64-bits PV guests), it's only outcome is a DoS. > > There is no real point in preventing Xen from working here and it would > be preferable to just log the vulnerability to the user so it can act > appropriately. > > Also reword the errata message regarding that it only affects PV64 guests. > > Signed-off-by: Teddy Astie > --- > It's hard to tell whether or not we would want to drop allow_unsafe, but > currently, Xen is allowed to boot with XSA-304 mitigations disabled > (intentionnaly) which has a similar outcome than this one. > > From a user standpoint, preventing the system to boot or starting guests is > too extreme and would be in practice seen as a bug, even if it's justified > policy which can be overriden. > > docs/misc/xen-command-line.pandoc | 12 ------------ > xen/arch/x86/cpu/amd.c | 21 +++++---------------- > xen/arch/x86/domain.c | 14 -------------- > xen/arch/x86/include/asm/amd.h | 2 -- > 4 files changed, 5 insertions(+), 44 deletions(-) > > diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc > index 6c77129732..04d206f919 100644 > --- a/docs/misc/xen-command-line.pandoc > +++ b/docs/misc/xen-command-line.pandoc > @@ -133,18 +133,6 @@ resume. > `s3_mode` instructs Xen to set up the boot time (option `vga=`) video > mode during S3 resume. > > -### allow_unsafe (x86) > -> `= ` > - > -> Default: `false` > - > -Force boot on potentially unsafe systems. By default Xen will refuse > -to boot on systems with the following errata: > - > -* AMD Erratum 121. Processors with this erratum are subject to a guest > - triggerable Denial of Service. Override only if you trust all of > - your PV guests. > - > ### altp2m (Intel) > > `= ` > > diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c > index 712734a6e7..f1f4a25754 100644 > --- a/xen/arch/x86/cpu/amd.c > +++ b/xen/arch/x86/cpu/amd.c > @@ -20,10 +20,6 @@ > > #include "cpu.h" > > -/* 1 = allow, 0 = don't allow guest creation, -1 = don't allow boot */ > -int8_t __read_mostly opt_allow_unsafe; > -boolean_param("allow_unsafe", opt_allow_unsafe); > - > /* Signal whether the ACPI C1E quirk is required. */ > bool __read_mostly amd_acpi_c1e_quirk; > bool __ro_after_init amd_legacy_ssbd; > @@ -1205,19 +1201,12 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) > if (c->family == 0x10) > __clear_bit(X86_FEATURE_MONITOR, c->x86_capability); > > - if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121)) > - opt_allow_unsafe = 1; > - else if (opt_allow_unsafe < 0) > - panic("Xen will not boot on this CPU for security reasons" > - "Pass \"allow_unsafe\" if you're trusting all your" > - " (PV) guest kernels.\n"); > - else if (!opt_allow_unsafe && c == &boot_cpu_data) > + if (cpu_has_amd_erratum(c, AMD_ERRATUM_121)) > + { > printk(KERN_WARNING > - "*** Xen will not allow creation of DomU-s on" > - " this CPU for security reasons. ***\n" > - KERN_WARNING > - "*** Pass \"allow_unsafe\" if you're trusting" > - " all your (PV) guest kernels. ***\n"); > + "*** This CPU is affected with erratum 121" > + " 64-bits PV guests are able to cause a DoS (XSA-9) ***\n"); We try to avoid splitting log messages, so that people can grep easily for them. I would also add a add_taint(TAINT_MACHINE_INSECURE); here. I wonder however if an update of the advisory would also be needed, as we are modifying the applied fix, and hence the text in the advisory no longer matches the code in Xen. Thanks, Roger. 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While the vulnerability has no mitigations (aside not running > 64-bits PV guests), it's only outcome is a DoS. > > There is no real point in preventing Xen from working here and it would > be preferable to just log the vulnerability to the user so it can act > appropriately. > > Also reword the errata message regarding that it only affects PV64 guests. > > Signed-off-by: Teddy Astie > --- > It's hard to tell whether or not we would want to drop allow_unsafe, but > currently, Xen is allowed to boot with XSA-304 mitigations disabled > (intentionnaly) which has a similar outcome than this one. > > From a user standpoint, preventing the system to boot or starting guests is > too extreme and would be in practice seen as a bug, even if it's justified > policy which can be overriden. There is a lot of history here, including for why the panic() is actually completely unreachable. I actually have a very similar patch, from almost certainly more than a decade ago.  The difference is that now I'm a maintainer and in a better position to say that this logic really shouldn't have been taken; certainly not in this form. Perhaps an easier justification is that there have been issues like AMD erratum #121 prior (e.g. Pentium LOCK CMPXCHG) and post (Zen1 has a related errata, can't remember it off the top of my head) that went unaddressed. There is a reason why most OSes blanket disallow using the page leading into the non-canonical region.  It's rife with bugs. ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Apr 24 09:33:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 09:33:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293360.1571144 (Exim 4.92) (envelope-from ) id 1wGCuU-0003t5-18; Fri, 24 Apr 2026 09:33:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293360.1571144; Fri, 24 Apr 2026 09:33:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGCuT-0003sy-TU; Fri, 24 Apr 2026 09:33:17 +0000 Received: by outflank-mailman (input) for mailman id 1293360; Fri, 24 Apr 2026 09:33:16 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGCuS-0003ss-3E for xen-devel@lists.xenproject.org; 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> >> u32 irq_traced[4] = { 0 }; > >> > >> - if ( max_cstate > 0 && power && > >> + if ( max_cstate() > 0 && power && > >> (next_state = cpuidle_current_governor->select(power)) > 0 ) > >> { > >> unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 > >> - : max_cstate; > >> + : max_cstate(); > >> > >> do { > >> cx = &power->states[next_state]; > >> } while ( (cx->type > max_state || > >> cx->entry_method == ACPI_CSTATE_EM_NONE || > >> (cx->entry_method == ACPI_CSTATE_EM_FFH && > >> - cx->type == max_cstate && > >> + cx->type == max_allowed_cstate && > > > > I'm afraid I'm missing why this uses max_allowed_cstate instead of > > max_state. > > max_allowed_cstate is what needs using along with ... > > >> (cx->address & MWAIT_SUBSTATE_MASK) > max_csubstate)) && > > ... max_csubstate, as both are driven by the "max_cstate=" command line > option. Renaming max_csubstate to max_allowed_csubstate would be an > option, but would incure yet more churn. > > >> --- a/xen/arch/x86/cpu/mwait-idle.c > >> +++ b/xen/arch/x86/cpu/mwait-idle.c > >> @@ -1045,15 +1045,16 @@ static void cf_check mwait_idle(void) > >> u64 before, after; > >> u32 exp = 0, pred = 0, irq_traced[4] = { 0 }; > >> > >> - if (max_cstate > 0 && power && > >> + if (max_cstate() > 0 && power && > >> (next_state = cpuidle_current_governor->select(power)) > 0) { > >> unsigned int max_state = sched_has_urgent_vcpu() ? ACPI_STATE_C1 > >> - : max_cstate; > >> + : max_cstate(); > >> > >> do { > >> cx = &power->states[next_state]; > >> - } while ((cx->type > max_state || (cx->type == max_cstate && > >> - MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > >> + } while ((cx->type > max_state || > >> + (cx->type == max_allowed_cstate && > > > > Indentation is weird for the above line IMO, you should use hard 3 > > tabs plus spaces afterwards, like the surrounding indentation? > > Ouch, indeed. > > >> + MWAIT_HINT2SUBSTATE(cx->address) > max_csubstate)) && > >> --next_state); > >> if (!next_state) > >> cx = NULL; > > > > Seeing max_cstate() is used in multiple places here, you might want to > > introduce a local max_cstate variable? > > Except that Misra doesn't like such naming, and any other name would feel > odd to use. > > >> --- a/xen/include/xen/acpi.h > >> +++ b/xen/include/xen/acpi.h > >> @@ -142,30 +142,33 @@ int acpi_gsi_to_irq (u32 gsi, unsigned i > >> > >> #ifdef CONFIG_ACPI_CSTATE > >> /* > >> - * max_cstate sets the highest legal C-state. > >> - * max_cstate = 0: C0 okay, but not C1 > >> - * max_cstate = 1: C1 okay, but not C2 > >> - * max_cstate = 2: C2 okay, but not C3 etc. > >> - > >> - * max_csubstate sets the highest legal C-state sub-state. Only applies to the > >> - * highest legal C-state. > >> - * max_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E > >> - * max_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 > >> - * max_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 > >> - * max_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 > >> + * max_{allowed,usable}_cstate sets the highest allowed / usable C-state, where > >> + * "allowed" is command line / sysctl based. > > > > Hm, this is a bit misleading, because max_usable_cstate is also > > command line based (plus system errata). What about: > > > > "max_{allowed,usable}_cstate sets the highest allowed / usable C-state. > > max_usable_cstate can only be set from the command line, while > > max_allowed_cstate can be set from both command line and systcl." > > Well. While I think I get your point, what I'm trying to get across is that > max_usable_cstate is internally controlled (bounded by command line setting > of max_allowed_cstate, but possibly forced lower than that internally). So > maybe > > "max_{allowed,usable}_cstate sets the highest allowed / usable C-state. > max_usable_cstate, while affected by the command line, is internally driven, > whereas max_allowed_cstate can be set from both command line and systcl." > > ? Sure LGTM. > >> + * max_*_cstate = 0: C0 okay, but not C1 > >> + * max_*_cstate = 1: C1 okay, but not C2 > >> + * max_*_cstate = 2: C2 okay, but not C3 etc. > >> + * > >> + * max_csubstate sets the highest allowed C-state sub-state. Only applies to > >> + * the highest allowed C-state. > >> + * max_allowed_cstate = 1, max_csubstate = 0 ==> C0, C1 okay, but not C1E > >> + * max_allowed_cstate = 1, max_csubstate = 1 ==> C0, C1 and C1E okay, but not C2 > >> + * max_allowed_cstate = 2, max_csubstate = 0 ==> C0, C1, C1E, C2 okay, but not C3 > >> + * max_allowed_cstate = 2, max_csubstate = 1 ==> C0, C1, C1E, C2 okay, but not C3 > >> */ > >> > >> -extern unsigned int max_cstate; > >> +extern unsigned int max_usable_cstate; > >> +extern unsigned int max_allowed_cstate; > >> extern unsigned int max_csubstate; > >> > >> +#define max_cstate() min(max_usable_cstate, max_allowed_cstate) > > > > I would be tempted to drop the ending parenthesis so that you don't > > need to adjust callers, but that's likely misleading, as then it would > > need to be uppercase MAX_CSTATE. > > I deliberately want to have the parentheses, to make sure all uses of > max_cstate (without the parentheses) have been covered (by converting in > whatever appropriate way). Which extends to possible backports. In a > subsequent, not to be backported commit we could drop them again if so > desired. > > >> static inline unsigned int acpi_get_cstate_limit(void) > >> { > >> - return max_cstate; > >> + return max_allowed_cstate; > >> } > >> static inline void acpi_set_cstate_limit(unsigned int new_limit) > >> { > >> - max_cstate = new_limit; > >> - return; > >> + max_allowed_cstate = new_limit; > > > > Do we want to check the new limit doesn't exceed max_usable_cstate and > > return -ERANGE or similar on failure? > > > > After this change it's a bit weird to silently ignore invalid values > > IMO. > > I disagree. Those values may be valid, just not usable (i.e. they are > still a valid upper bound, but we'd never go as high up). If people wanted > to use the same settings across their fleet, undue (and confusing) errors > might result on some of their systems if we did as you suggest. Plus we > have always accepted arbitrarily large (and hence entirely meaningless) > values anyway. OK, fair enough. With the minor above adjustments (indentation and comment): Reviewed-by: Roger Pau Monné Thanks, Roger. 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X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A61.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6219 X-purgate-ID: tlsNG-ef75cf/1777028480-15458C48-7776A1F2/0/0 X-purgate-type: clean X-purgate-size: 1101 Hi Mykola, > On 2 Apr 2026, at 11:45, Mykola Kvach wrote: >=20 > From: Mykola Kvach >=20 > init_tee_secondary() was marked __init and freed after boot. Calling it > from the CPU hotplug/resume path then executed discarded code, which > could crash Xen. Drop __init so the TEE mediator secondary init can run > safely on hotplugged and resumed CPUs. >=20 > Signed-off-by: Mykola Kvach > --- > xen/arch/arm/tee/tee.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/xen/arch/arm/tee/tee.c b/xen/arch/arm/tee/tee.c > index 8501443c8e..00e561fc78 100644 > --- a/xen/arch/arm/tee/tee.c > +++ b/xen/arch/arm/tee/tee.c > @@ -128,7 +128,7 @@ static int __init tee_init(void) >=20 > presmp_initcall(tee_init); >=20 > -void __init init_tee_secondary(void) > +void init_tee_secondary(void) > { > if ( cur_mediator && cur_mediator->ops->init_secondary ) > cur_mediator->ops->init_secondary(); >=20 Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Fri Apr 24 12:06:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 12:06:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293485.1571175 (Exim 4.92) (envelope-from ) id 1wGFIn-0004Sd-4s; Fri, 24 Apr 2026 12:06:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293485.1571175; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SETvcFEHrStvT1tcrZlaS2PpL73BzlblkQohvgtI1vYEmBxlUGO0d0uKwfliFbePhKFdGOl9gPjfI55dR8MAbNcTVl09QbvzgzyDjzLDs6Q3VQoUKIuh6phaN8ibNmAaAtI1JpHW1M2BmJRh3GKZ5GUe++VpGeI9W8If8Yt6v+UBNEw99HgurbZd5D+k8bD/K5dycOlRfxFrViUoWWf0ta+q7NQOc3n9jfPLoAujMSyojR2kfqxi/jPuXJ33CoKFVOco/tr7g81v/WsHUr5kgAig/SCo2WJf14V6kgFGPliyJAhcedOvUFh19CreOEpBgHO0oIjRZCn6m3K/LzSQbYojRViS4NbSC9kfHgRRFWF6JP6t4rV1OtRoar8uvhlkZEWXe/gHoxpIRJ4ZalXaizK0OZQIBMI35rmiuA6+6Ipk4O+W1n0GUdmW4efD/1j3 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 12:06:25.7974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 924ba69d-5177-44e9-58ff-08dea1f9e8dd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000199.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7551 X-purgate-ID: tlsNG-16d1c6/1777032390-90A7ED75-D8E74183/0/0 X-purgate-type: clean X-purgate-size: 560 Hi Mykola, > On 2 Apr 2026, at 11:45, Mykola Kvach wrote: >=20 > From: Mykola Kvach >=20 > The FF-A notification SRI interrupt handler was not correctly tied to > CPU hotplug and suspend/resume. As a result, CPUs going offline and > back online could end up with stale or missing handlers, breaking > delivery of FF-A notifications. >=20 > Signed-off-by: Mykola Kvach > --- >=20 Looks ok to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Fri Apr 24 13:36:23 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 13:36:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293556.1571184 (Exim 4.92) (envelope-from ) id 1wGGhW-0001wb-Ea; Fri, 24 Apr 2026 13:36:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293556.1571184; Fri, 24 Apr 2026 13:36:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGhW-0001wT-BQ; Fri, 24 Apr 2026 13:36:10 +0000 Received: by outflank-mailman (input) for mailman id 1293556; Fri, 24 Apr 2026 13:36:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGhU-0001wN-MH for xen-devel@lists.xenproject.org; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a5241f6583sm3649078e87.39.2026.04.24.06.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Apr 2026 06:36:58 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777037819; x=1777642619; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=0NnGgV5M3igXJCiYnxgULWkuy2e7zrxF4KNcDwNtdnc=; b=ekDjR4ftQ8AAi0XD/AGNmQ9aU0qs7MGjv5RuyYUWMX1ewbvGdq8m8yH0fY91LNDWBn jfdA75G+OSkCRB0OYmuFe6Nros5n8aSVLw+nusEX/v0YRuCwrdjCRxEf0z1FRgGBFbxZ tz8Wq5c6At+VLSH7bBIOEPuYtbDAWvmASL6ulQZQRl2W6uvd/GTMvGcBvBZfxRxpERPE NXQ7n1AmOk5kaH9w3KJCq94jgHv5w3DN6pacHo6AHj/LgDQOZO+SDYRar5zfV7PmGqXE Mlwwf1AFLzNGhx3IOuILRnWdzDhMcVITbG42wsfWjgRcrr1E8TS4b4+qcoTqcWWJy3zt urDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777037819; x=1777642619; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=0NnGgV5M3igXJCiYnxgULWkuy2e7zrxF4KNcDwNtdnc=; b=CSc3Au8H7Tqf3zIBkL9m7dzkZjurV41NliyYixMYJlwoSQl9Uijdu7iitiS4PalLZR G3KYviVr48QWwdZh3SUI7YZCAQ8c+pnv4iiP2V/GwRuwFlTP+5xNFWdiuCLFY5fMW+UJ fKmxabrdXkY9MouXa9Cs0F0AQ3YrzbNGKl6R4/ijeQ/jE5mbS/8jFEi4cWPxjkh/4ZSF OFmJtlM8GwZl9v2xYhvDY8r/aZUe9mkQ55Eux6d8ioyTUrPCy1qp7k+hf1dvu7Bv8AXN yOPJU3lbf8Iq2E87RNDcRo5Z74zCG+woSVKe4aIea03a2RX8Z7dwG8LRb747H7lmP+rU A/Fw== X-Gm-Message-State: AOJu0Ywz2mdifGlFjzVegAAYxGitaBDH8eGLfmM6XqNbjQcsPKxV/RWy kURS+2i2N8hp+LNGYS8PqQm4ud1mNdBXrgvgCk5WbxRWkC/2DUg68OLvoz2y5Q== X-Gm-Gg: AeBDies3YjhS0kEGgZBIrpgcFQP0hNTOOLnltq8REGUhx7pniBh/X+/ArmAyIiI7e1B xh52L+EWt+Sp6GszjSF291zf91lxOfAYyuStZk0KXuvVK3f8XE7ZAVG7seQ0q2mwHoOa4h53a82 afrGqVwmUs17GlGwq1VAL4quI+5b/6H6SrbnO8MuSqHc0SmvIZot3VkDDSUa8N4QP4tOqouQBN1 MtlDYxsQ/Kk37iO4nEPolHxbHgRvTf//bW89cP1+t0qt9viY3xPS8av/TOCJisIC2/y8v4WceQu 1VXt7cbNz8trNpN+elSJRPXR+ubCGoqvrrlCF++PFtdyRjD4XLrAd6rhHYe947ojtwzdbFcsIBs 4NyoGdMraIfl6fVZimGWVWzeLs62/z+CGQCdee31/iBegUBwmAMAt9vTi488QMI/TTqC9EWpZn1 YpKJa2w0L17h5+GSGlZ2L9pnAtHYgNSpvVJdac3SyqI33E0la0/Ta800rYdVAfvzuDf6TMuZCBx ooT X-Received: by 2002:ac2:4e0a:0:b0:5a4:1672:59d0 with SMTP id 2adb3069b0e04-5a4172c9267mr9627765e87.19.1777037818744; Fri, 24 Apr 2026 06:36:58 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Volodymyr Babchuk Subject: [PATCH v3 0/3] dom0less: various updates Date: Fri, 24 Apr 2026 15:36:48 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1777037820-C0766DB1-20CA3D03/10/73395122804 X-purgate-type: spam X-purgate-size: 3979 This patch series introduces a new field to track not-yet-used phandles as there are some use cases where RISC-V needs to know which phandle number could be used for generating a device tree node. For example, on the RISC-V side in make_cpus_node() [1] it is necessary to know which phandle number is unused to use it for device tree node generation. Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandles for imsic and riscv,cpu-intc are generated in this example not by get_next_free_phandle(), that is why they have such big numbers. For non-RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC is an interrupt controller that provides MSI and connects to each CPU. So (based on the DTS above) for APLIC, kinfo->phandle_intc is reused, which will also be re-used for the device node's interrupt property. For all others, I just introduced GUEST_PHANDLE_LAST [2] and used it for generation [3]. But I expect that it could be useful for other architectures too so I just moved it to common and re-use pfdt to understand what the maximum used phandle is. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt [2] https://lore.kernel.org/xen-devel/ccd6d21b224b478c88ca5f2fdd2d1dd507671510.1773157782.git.oleksii.kurochko@gmail.com/ [3] https://lore.kernel.org/xen-devel/fd64b8526a23e9d7775b9b48c5a933b0673c4fba.1773157782.git.oleksii.kurochko@gmail.com/ ************************************* Another thing introduced in this patch series is moving domain type to common code as several architectures (ARM and RISC-V for now) use them and it looks pretty architecture-independent. Also, is_64bit_domain() is used by dom0less common code, so I found it useful also to move is_{32,64}bit_domain macros to common code. ************************************* And the last thing is changing the prototype of make_cpus_node() to be aligned with other make_*_node() and since RISC-V will need access to the free_phandle field (even if it will be moved to kinfo->arch.free_phandle) and for the reason that this ->free_phandle is updated in make_*_node(), the kinfo argument is passed as non-const. CI: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2471778654 --- Changes in v3: - Rebase on top of staging. - Address the comments. --- Changes in v2: - Address the comments from ML. --- Oleksii Kurochko (3): xen/dom0less: introduce next_phandle in struct kernel_info xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() xen: introduce CONFIG_HAS_DOMAIN_TYPE xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 +-- xen/arch/arm/dom0less-build.c | 14 -------- xen/arch/arm/domain_build.c | 17 +++++----- xen/arch/arm/include/asm/domain.h | 12 ------- xen/arch/arm/include/asm/kernel.h | 4 --- xen/arch/arm/kernel.c | 16 ++++----- xen/common/Kconfig | 3 ++ xen/common/device-tree/dom0less-build.c | 45 ++++++++++++++++++------- xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++ xen/include/xen/fdt-domain-build.h | 17 +++++++++- xen/include/xen/fdt-kernel.h | 11 ++++++ xen/include/xen/sched.h | 4 +++ 14 files changed, 98 insertions(+), 65 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 13:37:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 13:37:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293570.1571202 (Exim 4.92) (envelope-from ) id 1wGGiO-0002fX-2E; Fri, 24 Apr 2026 13:37:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293570.1571202; Fri, 24 Apr 2026 13:37:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGiN-0002fM-Uk; Fri, 24 Apr 2026 13:37:03 +0000 Received: by outflank-mailman (input) for mailman id 1293570; Fri, 24 Apr 2026 13:37:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wGGiM-0002Rg-6C for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 13:37:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGGiL-000jjh-JA for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 15:37:01 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69eb71fa-5cb7-0a2a0a5109dd-0a2a4509da28-20 for ; Fri, 24 Apr 2026 15:37:01 +0200 Received: from [209.85.167.46] (helo=mail-lf1-f46.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69eb71fd-2497-0a2a45090019-d155a72eac6f-3 for ; Fri, 24 Apr 2026 15:37:01 +0200 Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-5a0faa0d15cso7756722e87.0 for ; Fri, 24 Apr 2026 06:37:01 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a5241f6583sm3649078e87.39.2026.04.24.06.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Apr 2026 06:36:59 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777037820; x=1777642620; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YeUlz7Qpf2B9MkICZ3XhoDDRV4QPAj1kbAZBfKIlP24=; b=AYM3+x8i1CyqgPAV+spfNGgmteZh8NLrT9c2BjeeihffZ9QTlsoLIgD/jm1G2RZjSp 8dW3nUGFGmz8bpFRF7GPNXoJvS1aSZgeYx/8cxilkHsDZp8vPEskvmpWNhyCWEUfT3kf scMnDXECjyj7uDUeD2Yxyzz5dUDSMfLBI7w5UISBUeXvZqYTGHOA7OZMs31Ux/Smv6Qa y9ddyFuhHEZW6H2NP+UnGQfCPQTWom4d9hd9YK68qLRL/UVXE9JHd6RqMsVRJBS5Bdg7 42+/VQQ6up5FMHQ0b7O4mpmO8NMOlXeOa7XYY3qJkZc9GVWQ0ff7A8iHN5S3LLodMfbb qHzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777037820; x=1777642620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YeUlz7Qpf2B9MkICZ3XhoDDRV4QPAj1kbAZBfKIlP24=; b=oyNe639n0aOTOeoVrmtbHDHoAWR+1ylrLIMzFrtv0zexG9o52rizYs2raQpgEoE/hG OxI//jpc2qvrk06oPw7ls4hzvDC/+/cvWIonEkK1RW4Ypkp62aH67XEIQByDxcdEhpiT KS/7Pj6sslUzxoXoUVnpGjT7gYL80LbE7uoW/QPxXJI3qqhh4HCUVvEAAEJsk2NGNeCJ Oqa6YEHcQFWbYlWNU1DK2bUEylD+3vCzYDXlXoPvI85TxTBMhmne6I4Pkdfw8cup1kCe TombQfs9fgXnjU/lW//AxV8MylZYi19VUlL/H8xPLGa5tVyK/mrqzIgiCSPt52Kp7xJJ e/Uw== X-Gm-Message-State: AOJu0Yw8MiTY5pSozOQgwefTNr7lXN2RApB3jF1qqJulxKG7SzWf+RWX gn8BdeZK3jXEYM1e0C08QN7YntxZIuzvU7oKiTIrBa4HtwSe/emYfl/Au41ZkA== X-Gm-Gg: AeBDievO15GWn7UwZ5s8C9HgaTJtvtVBgPX3/6Yf+l4pi74SqD8XSi+59AWsBoc6FmW HH/2JB/eIjpQUuZAeAwKSu9oxi5yYjD+Wub6viUutzw33sG5oET9qiRGWQQ8GmIMSYLn+EAXyt1 UIkPQiYHZHqrs03xrGThv6epNF93Wi5+Ui0qX0P8QhUBaeIpzqGYcMwFzpqFXNFY+2/XohYJMbX +tncqWnXZ4xxz3ghrW/K7ueuOUymn1tdlMlzIL8wSzZv/XMA+Ce2/effljEIjJeJLLlrtRxhmuK pWhQRx5ORtyeDd0F+zq0drY7Jfr6TAPzA5WatnN7XKFTeGF3ki3AgvaiV3ys+Dv/xw0DTjjDEqd 2rE8Ifj1JMeW4dEw63G8d71N4yy2VQIiJ8HAyYzyIr10RvPG0CaPEDJ5pbwH5NVM7CWpEbeQTBu tEUsLSdW2P0g08KTFLFlXGAw3fSudIBD0/MeJMCLusrMvqWClvl+tJJNEJgx3D5FwZT1j9lByN/ g8S X-Received: by 2002:a05:6512:1302:b0:5a3:fe60:471c with SMTP id 2adb3069b0e04-5a4172cb33amr11125558e87.16.1777037820163; Fri, 24 Apr 2026 06:37:00 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 1/3] xen/dom0less: introduce next_phandle in struct kernel_info Date: Fri, 24 Apr 2026 15:36:49 +0200 Message-ID: <5e3ffb41fab84b5f1b59ea81e6d267def89e2d65.1776957840.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777037821-92971A53-E7173810/10/73395122804 X-purgate-type: spam X-purgate-size: 6206 There are cases where it is necessary to know the next available phandle number in order to generate phandles for guest device nodes. When a partial FDT (pfdt) is provided, special care is needed during initialization of next_phandle, as the pfdt may already contain a dummy interrupt controller node with a phandle assigned to it. next_phandle must therefore be initialized to one past the highest phandle already present in the pfdt, to avoid collisions. Since next_phandle may be needed for the very first guest node generated, domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). The new call site also aligns better with the existing comment stating that domain_handle_dtb_boot_module() must be called before the rest of the device tree is generated. Introduce alloc_phandle() to ensure that phandles allocated for guest nodes do not overlap the Xen-reserved phandle range. This helper will be used by subsequent patches (by RISC-V at the moment). Signed-off-by: Oleksii Kurochko --- Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandle is generated in this example not by get_next_free_phandle(). For non RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC it is interrupt controller which provides MSI and connects to each CPU. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt --- Changes in v3: - Drop BUG_ON(GUEST_PHANDLE_GIC == 1). - Update the comment above declaration of next_phandle field of srtuct kernel_info. --- Changes in v2: - s/free_phandle/next_phandle. - s/get_next_free_phandle/alloc_phandle. --- --- xen/common/device-tree/dom0less-build.c | 43 ++++++++++++++++++------- xen/include/xen/fdt-domain-build.h | 6 ++++ xen/include/xen/fdt-kernel.h | 6 ++++ 3 files changed, 43 insertions(+), 12 deletions(-) diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 840d14419da2..9787ee264975 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, if ( res < 0 ) goto out; + /* + * Find the highest phandle in the partial FDT so next_phandle starts + * above it, avoiding collisions with pfdt's own phandle assignments. + */ + res = fdt_generate_phandle(pfdt, &kinfo->next_phandle); + if ( res ) + { + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; + goto out; + } + + if ( kinfo->next_phandle >= GUEST_PHANDLE_GIC ) + { + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); + res = -EOVERFLOW; + goto out; + } + for ( node_next = fdt_first_subnode(pfdt, 0); node_next > 0; node_next = fdt_next_subnode(pfdt, node_next) ) @@ -459,6 +477,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); kinfo->phandle_intc = GUEST_PHANDLE_GIC; + kinfo->next_phandle = 1; #ifdef CONFIG_GRANT_TABLE kinfo->gnttab_start = GUEST_GNTTAB_BASE; @@ -499,6 +518,18 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; + /* + * domain_handle_dtb_boot_module() must be called before the rest of the + * device tree is generated because it sets phandle_intc and next_phandle, + * which subsequent node generation depends on. + */ + if ( kinfo->dtb ) + { + ret = domain_handle_dtb_boot_module(d, kinfo); + if ( ret ) + goto err; + } + ret = make_chosen_node(kinfo); if ( ret ) goto err; @@ -516,18 +547,6 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - /* - * domain_handle_dtb_boot_module has to be called before the rest of - * the device tree is generated because it depends on the value of - * the field phandle_intc. - */ - if ( kinfo->dtb ) - { - ret = domain_handle_dtb_boot_module(d, kinfo); - if ( ret ) - goto err; - } - ret = make_intc_domU_node(kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 886a85381651..fd2ba01ff0f4 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -63,6 +63,12 @@ int find_unallocated_memory(const struct kernel_info *kinfo, unsigned long e_gfn, void *data)); +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ +static inline uint32_t alloc_phandle(struct kernel_info *kinfo) +{ + return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 33a60597bb4d..4d0467bb396a 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -44,6 +44,12 @@ struct kernel_info { /* Interrupt controller phandle */ uint32_t phandle_intc; + /* + * Next free phandle for guest device nodes; do not access directly, use + * alloc_phandle(). + */ + uint32_t next_phandle; + /* loader to use for this kernel */ void (*load)(struct kernel_info *info); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 13:37:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 13:37:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293571.1571211 (Exim 4.92) (envelope-from ) id 1wGGiP-0002tQ-7q; Fri, 24 Apr 2026 13:37:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293571.1571211; Fri, 24 Apr 2026 13:37:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGiP-0002tG-4i; Fri, 24 Apr 2026 13:37:05 +0000 Received: by outflank-mailman (input) for mailman id 1293571; Fri, 24 Apr 2026 13:37:04 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wGGiN-0002dY-RT for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 13:37:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGGiN-00EP0d-88 for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 15:37:03 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69eb71e7-2eae-0a2a0a5409dd-0a2a450bc858-42 for ; Fri, 24 Apr 2026 15:37:03 +0200 Received: from [209.85.167.47] (helo=mail-lf1-f47.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69eb71fe-212f-0a2a450b0019-d155a72fa495-3 for ; Fri, 24 Apr 2026 15:37:03 +0200 Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5a10d130b37so7847646e87.0 for ; Fri, 24 Apr 2026 06:37:03 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Align prototype with what other make_*_node() are passed. 2. A follow-up RISC-V patch will call get_next_free_phandle() inside make_cpus_node(), requiring mutable access to kinfo->free_phandle. Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel --- Look at the footer to the prev. patch to understand why phandle is needed inside cpu node. --- Changes in v3: - Add Reviewed-by: Michal Orzel . --- Changes in v2: - Properly initialize local variable fdt in Arm's make_cpus_node(). --- --- xen/arch/arm/domain_build.c | 5 +++-- xen/common/device-tree/dom0less-build.c | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6c17a84b2633..a3ff70102376 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1163,7 +1163,7 @@ int __init make_psci_node(void *fdt) return res; } -int __init make_cpus_node(const struct domain *d, void *fdt) +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) { int res; const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); @@ -1177,6 +1177,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) /* Keep the compiler happy with -Og */ bool clock_valid = false; uint64_t mpidr_aff; + void *fdt = kinfo->fdt; dt_dprintk("Create cpus node\n"); @@ -1625,7 +1626,7 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo, if ( res ) return res; - res = make_cpus_node(d, kinfo->fdt); + res = make_cpus_node(d, kinfo); if ( res ) return res; diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 9787ee264975..6d6882a34b5a 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -534,7 +534,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - ret = make_cpus_node(d, kinfo->fdt); + ret = make_cpus_node(d, kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index fd2ba01ff0f4..0d40d8cfa105 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -25,7 +25,7 @@ int construct_domain(struct domain *d, struct kernel_info *kinfo); int construct_hwdom(struct kernel_info *kinfo, const struct dt_device_node *node); int make_chosen_node(const struct kernel_info *kinfo); -int make_cpus_node(const struct domain *d, void *fdt); +int make_cpus_node(const struct domain *d, struct kernel_info *kinfo); int make_hypervisor_node(struct domain *d, const struct kernel_info *kinfo, int addrcells, int sizecells); int make_memory_node(const struct kernel_info *kinfo, int addrcells, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 13:37:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 13:37:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293572.1571220 (Exim 4.92) (envelope-from ) id 1wGGiQ-00037w-HM; Fri, 24 Apr 2026 13:37:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293572.1571220; Fri, 24 Apr 2026 13:37:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGiQ-00037m-Dh; Fri, 24 Apr 2026 13:37:06 +0000 Received: by outflank-mailman (input) for mailman id 1293572; Fri, 24 Apr 2026 13:37:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wGGiP-0002tN-BN for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 13:37:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGGiO-00EP4D-OV for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 15:37:04 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69eb71e8-e002-0a2a0a5209dd-0a2a4504ab34-34 for ; Fri, 24 Apr 2026 15:37:04 +0200 Received: from [209.85.167.42] (helo=mail-lf1-f42.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69eb7200-1dec-0a2a45040019-d155a72ae9d4-3 for ; Fri, 24 Apr 2026 15:37:04 +0200 Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-5a62f43b76aso2954889e87.3 for ; Fri, 24 Apr 2026 06:37:04 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a5241f6583sm3649078e87.39.2026.04.24.06.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Apr 2026 06:37:02 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777037823; x=1777642623; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=faxicMWV0pyOsr9LCBEsD50TaZnCHvDt9RPH9o+wZSY=; b=gnW5SaxfUqA5z44hed2+oJPnTyMvWxoKkVjd+k+QuKu/U4yrJ5TGLpI3hhWJRN+aJz z3aYmvu+0x/OrgCi4URxmkG07ASTsocHQeA97u1mXD2q+1YFyT4KR6cdtf8W1aG3xURT Se+nmov+EA881D92OxSgonXHcnlJirzFrYlxC696DMpCZdcH1F7a+f4h16RgdjrndTmx m7S2r+SzLvTt62Vx3NFwcjtMDPlD94Mry4QcT9/sPrZZkhgTYJtdA2VlC7lKsns4HB9/ Clcge+rmo5scP9//mMUCqgY4SX9le9jfsiqCb5kz0XoNLQyBRZBh3oQO6K9Ti7vHsyO+ 6daw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777037823; x=1777642623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=faxicMWV0pyOsr9LCBEsD50TaZnCHvDt9RPH9o+wZSY=; b=le0oslk7A5EeUL/F3AG/kTyXhLjb8gqfprOQEk4ECvp17WRRuDVGiuii+dlBUWaPPU i8vArOQdde1GsyzNGHoDCIUiz4mWxArR3Oo0b2YoC23ZabMNsiaJVyBUrWj1IBFe8ujM DT9H7N5l4cFeMsng9PrFhE7gJerAkx/kk9aB3UyFPEyP8No9OQzLV3oQH+uAJEMgyMpH JJvVBTEQrF0ciZNthaLOuxII1CPfCXvZ7oRxqHRAvdSmnHjG3rcFhQhahECjG1oo3veP DvjTggf5EC2t+Xw0n+BP4vdYjXFhHMyoXIXTqsEA02J3XL5tRp9ZEohHkA/DqKhD7/bU +CNA== X-Gm-Message-State: AOJu0YyRL4muV+fHWqR9Y/8TPnjWcDKrR3gfiTEQZN9TwhGi62lj7g9M qmmTbFxiku754d4D0rbINGoRjBqaVYRY8JUqX81FnUqDJcLZ2X41tZo9aDh9hg== X-Gm-Gg: AeBDievMsd0u/0DypvFvUuW0uvNdL69z9+hGs2ZwWJ18/ZbrhjM0bXwssSkTK8JRE6q 0klCfMQTR/B9wGCp1GKuCJsfNHMru4dcDMXAQKqJgilN2L1NeeZtFOuP7J+8ESNqZfESvdUqdgt OGw7F+iAbgknWW0TmPGHC74p9gSgaGUzusEq1TUQS4Ce8+KTJENH7LY5HlWiG9JtsoePoNP46Mz jdUgGAv3iniJ2W93qhlge7QPIq1yU59y0pkfmOffddHlfelSx+KFbGrPZxtA8STwUkAwpoBSbt4 bI8CGu/7Lc9eWyanZaJlA9vJOPMW6QvfDZu3zXSyUh/SPaiWSDXpeT/SBjjQKj0w3JDDaja/tQ3 hzN5YRUEkBEYQPYK37cEajtAecAi4eTLpjeT8OZGHWWMKGPA1QreRQcbPQwjUahWblN91sbdmwG qWFId51wuS70F4QgLGXemk1qLy2vzT43PvKkd8auuwVwRRfluX+D1tJxHiJR1nHAElewWPvad1J T49 X-Received: by 2002:a05:6512:154b:20b0:5a3:ff44:f01b with SMTP id 2adb3069b0e04-5a4172e3131mr7107204e87.34.1777037823257; Fri, 24 Apr 2026 06:37:03 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v3 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE Date: Fri, 24 Apr 2026 15:36:51 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1777037824-2B5683FF-798A559E/10/73395122804 X-purgate-type: spam X-purgate-size: 11153 As domain type is part of common code now there is no any reason to have architecture-specific set_domain_type() functions so it is dropped. Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE for consistency. Also, drop and add some parentheses to be aligned with the similar if() below. x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no longer builds, the fallback is currently only relevant for arm32. Signed-off-by: Oleksii Kurochko --- Changes in v3: - Sort properly HAS_DOMAIN_TYPE in xen/common/Kconfig. - Update the comment above is_*bit_domain() macros. --- Changes in v2: - Update the commit message. - Move HAS_DOMAIN_TYPE to xen/common/Kconfig. - Return set_domain_type(), move it to xen/fdt-domain-build.h and make it static inline. - s/CONFIG_ARM_64/CONFIG_HAS_DOMAIN for the places where kinfo->type is used. - Drop parantethes around cpu_has_el1_32 in if() and add around (kinfo->type == DOMAIN_32BIT) to be consistent with the similar check below. - Fix comment code style. - Add __packed to definition of enum domain_type --- --- xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 ++-- xen/arch/arm/dom0less-build.c | 14 -------------- xen/arch/arm/domain_build.c | 12 +++++------- xen/arch/arm/include/asm/domain.h | 12 ------------ xen/arch/arm/include/asm/kernel.h | 4 ---- xen/arch/arm/kernel.c | 16 ++++++++-------- xen/common/Kconfig | 3 +++ xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++++++++ xen/include/xen/fdt-domain-build.h | 9 +++++++++ xen/include/xen/fdt-kernel.h | 5 +++++ xen/include/xen/sched.h | 4 ++++ 13 files changed, 50 insertions(+), 49 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..79622b46a10d 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -7,6 +7,7 @@ config ARM_64 def_bool y depends on !ARM_32 select 64BIT + select HAS_DOMAIN_TYPE select HAS_FAST_MULTIPLY select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c index 8720d126c97d..9e9a29eb1e78 100644 --- a/xen/arch/arm/arm64/domctl.c +++ b/xen/arch/arm/arm64/domctl.c @@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type) return -EINVAL; if ( domain_tot_pages(d) != 0 ) return -EBUSY; - if ( d->arch.type == type ) + if ( d->type == type ) return 0; - d->arch.type = type; + d->type = type; if ( is_64bit_domain(d) ) for_each_vcpu(d, v) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f73c65e5151 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) return 0; } -/* TODO: make arch.type generic ? */ -#ifdef CONFIG_ARM_64 -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* type must be set before allocate memory */ - d->arch.type = kinfo->arch.type; -} -#else -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* Nothing to do */ -} -#endif - int __init init_vuart(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index a3ff70102376..ad665cd3c045 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1771,15 +1771,15 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) BUG_ON(d->vcpu[0] == NULL); BUG_ON(v->is_initialised); -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) + if ( !cpu_has_el1_32 && (kinfo->type == DOMAIN_32BIT) ) { printk("Platform does not support 32-bit domain\n"); return -EINVAL; } - if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) ) + if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) ) { printk("SVE is not available for 32-bit domain\n"); return -EINVAL; @@ -1893,10 +1893,8 @@ int __init construct_hwdom(struct kernel_info *kinfo, iommu_hwdom_init(d); -#ifdef CONFIG_ARM_64 - /* type must be set before allocate_memory */ - d->arch.type = kinfo->arch.type; -#endif + set_domain_type(d, kinfo); + find_gnttab_region(d, kinfo); if ( is_domain_direct_mapped(d) ) allocate_memory_11(d, kinfo); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..e51baa0557bd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -18,18 +18,6 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; -#ifdef CONFIG_ARM_64 -enum domain_type { - DOMAIN_32BIT, - DOMAIN_64BIT, -}; -#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT) -#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT) -#else -#define is_32bit_domain(d) (1) -#define is_64bit_domain(d) (0) -#endif - /* * Is the domain using the host memory layout? * diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h index 7c3b7fde5b64..21f4273fa1b5 100644 --- a/xen/arch/arm/include/asm/kernel.h +++ b/xen/arch/arm/include/asm/kernel.h @@ -10,10 +10,6 @@ struct arch_kernel_info { -#ifdef CONFIG_ARM_64 - enum domain_type type; -#endif - /* Enable pl011 emulation */ bool vpl011; }; diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 7544fd50a20f..9395b5af8745 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -100,8 +100,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) const struct membanks *mem = kernel_info_get_mem(info); paddr_t load_addr; -#ifdef CONFIG_ARM_64 - if ( (info->arch.type == DOMAIN_64BIT) && (info->zimage.start == 0) ) +#ifdef CONFIG_HAS_DOMAIN_TYPE + if ( (info->type == DOMAIN_64BIT) && (info->zimage.start == 0) ) return mem->bank[0].start + info->zimage.text_offset; #endif @@ -268,14 +268,14 @@ int __init kernel_uimage_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE switch ( uimage.arch ) { case IH_ARCH_ARM: - info->arch.type = DOMAIN_32BIT; + info->type = DOMAIN_32BIT; break; case IH_ARCH_ARM64: - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; break; default: printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch); @@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, info->load = kernel_zimage_load; - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; return 0; } @@ -396,8 +396,8 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 - info->arch.type = DOMAIN_32BIT; +#ifdef CONFIG_HAS_DOMAIN_TYPE + info->type = DOMAIN_32BIT; #endif return 0; diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 0a20aa0a1249..5ff71480eebe 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -128,6 +128,9 @@ config HAS_DEVICE_TREE_DISCOVERY config HAS_DOM0LESS bool +config HAS_DOMAIN_TYPE + bool + config HAS_DIT # Data Independent Timing bool diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h index faaf660424b2..4118dec76c0a 100644 --- a/xen/include/xen/dom0less-build.h +++ b/xen/include/xen/dom0less-build.h @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, int make_intc_domU_node(struct kernel_info *kinfo); int make_arch_nodes(struct kernel_info *kinfo); -void set_domain_type(struct domain *d, struct kernel_info *kinfo); - int init_intc_phandle(struct kernel_info *kinfo, const char *name, const int node_next, const void *pfdt); diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 93c0fd00c1d7..8c898afe74fc 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -13,6 +13,19 @@ struct guest_area { void *map; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE +enum __packed domain_type { + DOMAIN_32BIT, + DOMAIN_64BIT, +}; +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) +#elif !defined(CONFIG_64BIT) +/* At the moment on 32-bit-only platforms all domains are 32-bit. */ +#define is_32bit_domain(d) (true) +#define is_64bit_domain(d) (false) +#endif + #include typedef union { diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 0d40d8cfa105..bc7744270c8f 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -7,6 +7,7 @@ #include #include #include +#include #include struct domain; @@ -69,6 +70,14 @@ static inline uint32_t alloc_phandle(struct kernel_info *kinfo) return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; } +static inline void set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ +#ifdef CONFIG_HAS_DOMAIN_TYPE + /* Type must be set before allocate memory */ + d->type = kinfo->type; +#endif +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 4d0467bb396a..86a37a13048b 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -9,6 +9,7 @@ #include #include +#include #include #if __has_include() @@ -65,6 +66,10 @@ struct kernel_info { } zimage; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + #if __has_include() struct arch_kernel_info arch; #endif diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..00db1da12f21 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -386,6 +386,10 @@ struct domain { domid_t domain_id; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + unsigned int max_vcpus; uint64_t unique_id; /* Unique domain identifier */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Fri Apr 24 13:44:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 13:44:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1293610.1571229 (Exim 4.92) (envelope-from ) id 1wGGpQ-0006B4-EA; Fri, 24 Apr 2026 13:44:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1293610.1571229; Fri, 24 Apr 2026 13:44:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGpQ-0006Ax-BH; Fri, 24 Apr 2026 13:44:20 +0000 Received: by outflank-mailman (input) for mailman id 1293610; Fri, 24 Apr 2026 13:44:19 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGGpO-0006Ap-JT for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 13:44:19 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGGpO-00Assh-0C for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 15:44:18 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69eb73a7-e002-0a2a0a5209dd-0a2a45058eba-40 for ; Fri, 24 Apr 2026 15:44:17 +0200 Received: from [209.85.219.42] (helo=mail-qv1-f42.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69eb73b0-aaa8-0a2a45050019-d155db2ab144-3 for ; Fri, 24 Apr 2026 15:44:17 +0200 Received: by mail-qv1-f42.google.com with SMTP id 6a1803df08f44-89fc4147f2eso87346046d6.3 for ; Fri, 24 Apr 2026 06:44:17 -0700 (PDT) Received: from ziepe.ca (crbknf0213w-47-54-130-67.pppoe-dynamic.high-speed.nl.bellaliant.net. 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These regions may be marked > >> no-map in DT and therefore are not part of the kernel linear map. > >> In such cases, pfn_valid() still returns true, but phys_to_virt() > >> is not valid and cache maintenance via arch_sync_dma_* will fault. > >> > >> Prevent this by excluding devices with a private DMA memory pool > >> (dev->dma_mem) from the arch_sync_dma_* fast path, and always > >> fall back to xen_dma_sync_* for those devices to avoid invalid > >> phys_to_virt() conversions for no-map DMA memory while preserving the > >> existing fast path for normal, linear-mapped RAM. > > > >I think this is the same sort of weirdness the other two CC threads are > >dealing with.. We already have two different flags indicating the > >cache flush should be skipped, it would make more sense to have the > >swiotlb mangle the flags, just like for cc. > > > >https://lore.kernel.org/r/20260420061415.3650870-1-aneesh.kumar@kernel.org > > > >Then you know that the swiotlb was used and it should flow down to > >here. > > Xen fully implements dev->dma_ops and does not leak hypervisor-specific > semantics outside of it. It may have its own re-implementation but the same remarks apply. The flags in attrs should be correct and you should not be putting random boolean checks all over the place to make up for incorrect flags. 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When multiple cores / > threads are present (and to come back online) in a package, for package > scope MSRs this may be covered by APs doing the writes, but we can't rely > on that. > > Signed-off-by: Jan Beulich > > --- a/xen/arch/x86/acpi/power.c > +++ b/xen/arch/x86/acpi/power.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -299,6 +300,7 @@ static int enter_state(u32 state) > acpi_sleep_post(state); > if ( hvm_cpu_up() ) > BUG(); > + mwait_idle_resume(); > cpufreq_add_cpu(0); > > enable_cpu: > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -1680,6 +1680,28 @@ static int __init mwait_idle_probe(void) > return 0; > } > > +static void mwait_idle_cpu_tweak(unsigned int cpu) > +{ > + if (icpu->auto_demotion_disable_flags) > + on_selected_cpus(cpumask_of(cpu), auto_demotion_disable, NULL, 1); > + > + if (icpu->byt_auto_demotion_disable_flag) > + on_selected_cpus(cpumask_of(cpu), byt_auto_demotion_disable, NULL, 1); > + > + switch (icpu->c1e_promotion) { > + case C1E_PROMOTION_DISABLE: > + on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); > + break; > + > + case C1E_PROMOTION_ENABLE: > + on_selected_cpus(cpumask_of(cpu), c1e_promotion_enable, NULL, 1); > + break; > + > + case C1E_PROMOTION_PRESERVE: > + break; > + } > +} > + > static int cf_check mwait_idle_cpu_init( > struct notifier_block *nfb, unsigned long action, void *hcpu) > { > @@ -1762,24 +1784,7 @@ static int cf_check mwait_idle_cpu_init( > dev->count++; > } > > - if (icpu->auto_demotion_disable_flags) > - on_selected_cpus(cpumask_of(cpu), auto_demotion_disable, NULL, 1); > - > - if (icpu->byt_auto_demotion_disable_flag) > - on_selected_cpus(cpumask_of(cpu), byt_auto_demotion_disable, NULL, 1); > - > - switch (icpu->c1e_promotion) { > - case C1E_PROMOTION_DISABLE: > - on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); > - break; > - > - case C1E_PROMOTION_ENABLE: > - on_selected_cpus(cpumask_of(cpu), c1e_promotion_enable, NULL, 1); > - break; I'm possibly missing some context here, but why do we use on_selected_cpus and the CPU_ONLINE hook? Won't it be easier to use CPU_STARTING and avoid the use of on_selected_cpus(), as CPU_STARTING runs in the context of the CPU being onlined. Thanks, Roger. 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Clean up the code so that > BYT/CHT-specifics do not show up in the common 'struct idle_cpu' data > structure. > > Remove the 'byt_auto_demotion_disable_flag' flag from 'struct idle_cpu', > because a better coding pattern is to avoid very case-specific fields like > 'bool byt_auto_demotion_disable_flag' in a common data structure, which is > used for all platforms, not only BYT/CHT. The code is just more readable > when common data structures contain only commonly used fields. > > Instead, match BYT/CHT in the 'intel_idle_init_cstates_icpu()' function, > and introduce a small helper to take care of BYT/CHT auto-demotion. This > is consistent with how platform-specific things are done for other > platforms. > > No intended functional changes. > > Inspired by (and description largely taken from) Linux'es c93d13b661a6 > ("intel_idle: clean up BYT/CHT auto demotion disable"). > > Signed-off-by: Jan Beulich > > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -104,7 +104,6 @@ struct idle_cpu { > * Indicate which enable bits to clear here. > */ > unsigned long auto_demotion_disable_flags; > - bool byt_auto_demotion_disable_flag; > enum c1e_promotion c1e_promotion; > }; > > @@ -1144,7 +1143,7 @@ static void cf_check auto_demotion_disab > wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits); > } > > -static void cf_check byt_auto_demotion_disable(void *dummy) > +static void byt_cht_auto_demotion_disable(void) > { > wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0); > wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); > @@ -1195,13 +1194,11 @@ static const struct idle_cpu idle_cpu_sn > static const struct idle_cpu idle_cpu_byt = { > .state_table = byt_cstates, > .c1e_promotion = C1E_PROMOTION_DISABLE, > - .byt_auto_demotion_disable_flag = true, > }; > > static const struct idle_cpu idle_cpu_cht = { > .state_table = cht_cstates, > .c1e_promotion = C1E_PROMOTION_DISABLE, > - .byt_auto_demotion_disable_flag = true, > }; > > static const struct idle_cpu idle_cpu_ivb = { > @@ -1680,14 +1677,11 @@ static int __init mwait_idle_probe(void) > return 0; > } > > -static void mwait_idle_cpu_tweak(unsigned int cpu) > +static void mwait_idle_cpu_tweak(unsigned int cpu, bool bsp) > { > if (icpu->auto_demotion_disable_flags) > on_selected_cpus(cpumask_of(cpu), auto_demotion_disable, NULL, 1); > > - if (icpu->byt_auto_demotion_disable_flag) > - on_selected_cpus(cpumask_of(cpu), byt_auto_demotion_disable, NULL, 1); > - > switch (icpu->c1e_promotion) { > case C1E_PROMOTION_DISABLE: > on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); > @@ -1700,12 +1694,24 @@ static void mwait_idle_cpu_tweak(unsigne > case C1E_PROMOTION_PRESERVE: > break; > } > + > + /* Pkg-scope MSRs on 1-socket-only systems need writing only once. */ > + if (!bsp) > + return; > + > + switch (boot_cpu_data.vfm) { > + case INTEL_ATOM_SILVERMONT: > + case INTEL_ATOM_AIRMONT: > + byt_cht_auto_demotion_disable(); > + break; > + } > } > > static int cf_check mwait_idle_cpu_init( > struct notifier_block *nfb, unsigned long action, void *hcpu) > { > unsigned int cpu = (unsigned long)hcpu, cstate; > + static bool first; I think you want to init first = true here, so that after the first call to mwait_idle_cpu_tweak() it gets set to false for future calls? Thanks, Roger. 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By implication, subsequent updates now need doing to the copy. Shouldn't the aim here be to move the myriad of per-arch cpuidle_state arrays to the init section, so we can get rid of them after boot? Overall I wonder whether we would rather attempt to sya in-sync with what Linux does, simply because it's then easier to pick updates fro Linux, and less likely to introduce bugs as part of the modification needs to adapt the Linux code into our fork. Not saying the change is bad, just wondering whether in general we would better try to keep the code bases as similar as feasible. Thanks, Roger. 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(idle_cpu_adl{,_l} can also become const in the > first place.) > > Signed-off-by: Jan Beulich Oh, OK, that's what I was missing from the previous patch, then for this and the previous: Acked-by: Roger Pau Monné Albeit I'm still concerned whether us diverging (further?) from Linux would causes more work when picking up upstream changes. FWIW, I would also consider squashing this into the previous patch. Thanks, Roger. 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The driver version is implicitly defined by the > hypervisor version, making this constant redundant. > > Remove the constant to eliminate potential confusion about version > tracking. > > Signed-off-by: Artem Bityutskiy > Reviewed-by: Andy Shevchenko > Link: https://patch.msgid.link/20251215111229.132705-1-dedekind1@gmail.com > Signed-off-by: Rafael J. Wysocki > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 25ff69011ddf > > Adjust description to fit our code base. > > Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné Thanks, Roger. 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The parameter does not support any > other platform. For example, Meteor Lake has a similar C1/C1E limitation, > but the parameter does not support Meteor Lake. This indicates that the > parameter is not very useful. > > Generally, independent C1 and C1E are important for server platforms where > low latency is key. However, they are not as important for client platforms, > like Alder Lake, where C1E providing better energy savings is generally > preferred. > > The parameter was originally introduced for Sapphire Rapids Xeon: > da0e58c038e6 intel_idle: add 'preferred_cstates' module argument > > Later it was added to Alder Lake: > d1cf8bbfed1ed ("intel_idle: Add AlderLake support") > > But it was removed from Sapphire Rapids when firmware fixed the C1/C1E > limitation: > 1548fac47a114 ("intel_idle: make SPR C1 and C1E be independent") > > So Alder Lake is the only platform left where this parameter has any effect. > Remove this parameter to simplify the driver and reduce maintenance burden. > > Signed-off-by: Artem Bityutskiy > Link: https://patch.msgid.link/20251215111300.132803-1-dedekind1@gmail.com > Signed-off-by: Rafael J. Wysocki > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a36dc37b5672 > Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné Thanks, Roger. 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(Note that some were __ro_after_init already.) > > Signed-off-by: Jan Beulich I wonder if we could also move all the cstate tables to .init section, as after boot we would only use one of those. Anyway, for the change here: Acked-by: Roger Pau Monné Thanks, Roger. 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The goal is to have good enough defaults for most users. > > However, C-state characteristics, such as exit latency and residency, can > vary between different variants of the same CPU model and BIOS settings. > Moreover, different platform usage models and user preferences may benefit > from different C-state target_residency values. > > Provide a way for users to adjust the C-states table via a module parameter > "table". The general format is: > "state1:latency1:target_residency1,state2:latency2:target_residency2,..." > > In other words, represent each C-state by its name, exit latency (in > microseconds), and target residency (in microseconds), separated by colons. > Separate multiple C-states by commas. > > For example, suppose a CPU has 3 C-states with the following > characteristics: > C1: exit_latency=1, target_residency=2 > C1E: exit_latency=10, target_residency=10 > C6: exit_latency=100, target_residency=500 > > Users can specify a custom C-states table as follows: > > 1. intel_idle.table="C1:2:2,C1E:5:20,C6:150:600" > Result: C1: exit_latency=2, target_residency=2 > C1E: exit_latency=5, target_residency=20 > C6: exit_latency=150, target_residency=600 > 2. intel_idle.table="C6::400" > Result: C1: exit_latency=1, target_residency=2 (unchanged) > C1E: exit_latency=10, target_residency=10 (unchanged) > C6: exit_latency=100, target_residency=400 > (only target_residency changed) > > Signed-off-by: Artem Bityutskiy > Link: https://patch.msgid.link/20251216080402.156988-3-dedekind1@gmail.com > Signed-off-by: Rafael J. Wysocki > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 111f77a23348 > > Add __init to get_cmdline_field(). Put cmdline_table_str[] in .init.data. > Other adjustments to fit our env. > > Signed-off-by: Jan Beulich > --- > For the initial attempt, I've left the new option as a standalone one. It > may be worth integrating with "mwait-idle", but I think much of the > parsing would then want doing differently. It'll then likely be much > harder to apply future Linux changes there. > > --- a/docs/misc/xen-command-line.pandoc > +++ b/docs/misc/xen-command-line.pandoc > @@ -1928,6 +1928,23 @@ Print boot time MTRR state. > Use the MWAIT idle driver (with model specific C-state knowledge) instead > of the ACPI based one. > > +### mwait-idle.table (x86) The .table suffix is kind of weird, as we don't use it elsewhere. It might feel more natural given the naming of the existing command line options to use mwait-idle-table? > +> `= ` > + > + Define the C-states table from a user input string. Expected format is > + 'name:latency:residency', where: > + - name: The C-state name. > + - latency: The C-state exit latency in us. > + - residency: The C-state target residency in us. > + > + Multiple C-states can be defined by separating them with commas: > + 'name1:latency1:residency1,name2:latency2:residency2' > + > + Example: intel_idle.table=C1:1:1,C1E:5:10,C6:100:600 s/intel_idle/mwait-idle/ in the line above. > + > + To leave latency or residency unchanged, use an empty field, for example: > + 'C1:1:1,C1E::10' - leaves C1E latency unchanged. > + > ### nmi (x86) > > `= ignore | dom0 | fatal` > > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -70,6 +70,11 @@ > static __initdata bool opt_mwait_idle = true; > boolean_param("mwait-idle", opt_mwait_idle); > > +/* The maximum allowed length for the 'table' module parameter */ > +#define MAX_CMDLINE_TABLE_LEN 256 > +static char cmdline_table_str[MAX_CMDLINE_TABLE_LEN] __initdata; > +string_param("mwait-idle.table", cmdline_table_str); > + > static unsigned int mwait_substates; > > #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF > @@ -122,6 +127,9 @@ struct cpuidle_state { > */ > #define CPUIDLE_FLAG_IBRS 0x20000 > > +/* C-states data from the 'mwait-idle.table' cmdline parameter */ > +static struct cpuidle_state cmdline_states[ACPI_PROCESSOR_MAX_POWER] __initdata; > + > /* > * MWAIT takes an 8-bit "hint" in EAX "suggesting" > * the C-state (top nibble) and sub-state (bottom nibble) > @@ -1546,6 +1554,161 @@ static void __init mwait_idle_state_tabl > } > } > > + /** > + * get_cmdline_field - Get the current field from a cmdline string. > + * @args: The cmdline string to get the current field from. > + * @field: Pointer to the current field upon return. > + * @sep: The fields separator character. > + * > + * Examples: > + * Input: args="C1:1:1,C1E:2:10", sep=':' > + * Output: field="C1", return "1:1,C1E:2:10" > + * Input: args="C1:1:1,C1E:2:10", sep=',' > + * Output: field="C1:1:1", return "C1E:2:10" > + * Ipnut: args="::", sep=':' > + * Output: field="", return ":" > + * > + * Return: The continuation of the cmdline string after the field or NULL. > + */ > +static char *__init get_cmdline_field(char *args, char **field, char sep) > +{ > + unsigned int i; > + > + for (i = 0; args[i] && !isspace(args[i]); i++) { > + if (args[i] == sep) > + break; > + } > + > + *field = args; > + > + if (args[i] != sep) > + return NULL; > + > + args[i] = '\0'; > + return args + i + 1; > +} > + > +/** > + * cmdline_table_adjust - Adjust the C-states table with data from cmdline. > + * > + * Adjust the C-states table with data from the 'mwait-idle.table' parameter > + * (if specified). > + */ > +static void __init cmdline_table_adjust(void) > +{ > + char *args = cmdline_table_str; > + struct cpuidle_state *state; > + unsigned int i, state_count; > + > + if (args[0] == '\0') > + /* The 'mwait-idle.table' module parameter was not specified */ > + return; > + > + /* Create a copy of the C-states table */ > + for (i = 0; > + i < ARRAY_SIZE(cmdline_states) && icpu.state_table[i].name[0]; > + i++) > + cmdline_states[i] = icpu.state_table[i]; > + > + state_count = i; > + > + /* > + * Adjust the C-states table copy with data from the 'mwait-idle.table' > + * module parameter. > + */ > + while (args) { > + char *fields, *name, *val; > + > + /* > + * Get the next C-state definition, which is expected to be > + * '::'. Treat "empty" > + * fields as unchanged. For example, > + * '::' leaves the latency unchanged. > + */ > + args = get_cmdline_field(args, &fields, ','); > + > + /* name */ > + fields = get_cmdline_field(fields, &name, ':'); > + if (!fields) > + goto error; > + > + /* Find the C-state by its name */ > + state = NULL; > + for (i = 0; i < state_count; i++) { > + if (!strcmp(name, cmdline_states[i].name)) { > + state = &cmdline_states[i]; > + break; > + } > + } > + > + if (!state) { > + printk(XENLOG_ERR PREFIX "C-state '%s' was not found\n", > + name); > + continue; > + } > + > + /* Latency */ > + fields = get_cmdline_field(fields, &val, ':'); > + if (!fields) > + goto error; > + > + if (*val) { > + const char *end; > + unsigned long n = simple_strtoul(val, &end, 0); > + > + state->exit_latency = n; > + if (*end || state->exit_latency != n) > + goto error; > + } > + > + /* Target residency */ > + fields = get_cmdline_field(fields, &val, ':'); > + > + if (*val) { > + const char *end; > + unsigned long n = simple_strtoul(val, &end, 0); > + > + state->target_residency = n; > + if (*end || state->target_residency != n) > + goto error; > + } > + > + /* > + * Allow for 3 more fields, but ignore them. Helps to make > + * possible future extensions of the cmdline format backward > + * compatible. > + */ > + for (i = 0; fields && i < 3; i++) { > + fields = get_cmdline_field(fields, &val, ':'); > + if (!fields) > + break; > + } This seems a bit arbitrary for my taste. I would rather ignore the extra fields (and print a message about it), and proceed with the next state. > + > + if (fields) { > + printk(XENLOG_ERR PREFIX > + "Too many fields for C-state '%s'\n", > + state->name); > + goto error; > + } > + > + printk(XENLOG_INFO PREFIX > + "C-state from cmdline: name=%s, latency=%u, residency=%u\n", > + state->name, state->exit_latency, state->target_residency); > + } > + > + /* Copy the adjusted C-states table back */ > + for (i = 0; i < state_count; i++) > + icpu.state_table[i] = cmdline_states[i]; > + > + printk(XENLOG_INFO PREFIX > + "Adjusted C-states with data from 'mwait-idle.table'\n"); > + return; > + > + error: > + printk(PREFIX XENLOG_ERR maybe? Thanks, Roger. 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X-MS-Exchange-CrossTenant-Network-Message-Id: 368f3e49-7f1d-4c2f-63ef-08dea235db8f X-MS-Exchange-CrossTenant-AuthSource: CH7PR03MB7860.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 19:15:33.5835 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: KqMjB8LN2bjdPigusJcPMTd1M1t3Kn4vtPllbMfbDs2kWEz3EOWcS4lYcb9cc9xxU+4lZ5ru49nmQMbjOeNFuA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR03MB5223 X-purgate-ID: tlsNG-d25034/1777058138-F4AF8CF5-437507FE/0/0 X-purgate-type: clean X-purgate-size: 2780 On Thu, Mar 12, 2026 at 05:58:21PM +0100, Jan Beulich wrote: > From: Artem Bityutskiy > > Add validation for C-states specified via the "table=" module parameter. > Treat this module parameter as untrusted input and validate it thoroughly. > > Signed-off-by: Artem Bityutskiy > Link: https://patch.msgid.link/20251216080402.156988-4-dedekind1@gmail.com > Signed-off-by: Rafael J. Wysocki > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git be6a150829b3 > > Add __init to validate_cmdline_cstate(). Other adjustments to fit our env. > > Signed-off-by: Jan Beulich > > --- a/xen/arch/x86/cpu/mwait-idle.c > +++ b/xen/arch/x86/cpu/mwait-idle.c > @@ -72,6 +72,11 @@ boolean_param("mwait-idle", opt_mwait_id > > /* The maximum allowed length for the 'table' module parameter */ > #define MAX_CMDLINE_TABLE_LEN 256 > +/* Maximum allowed C-state latency */ > +#define MAX_CMDLINE_LATENCY_US (5 * 1000 /* USEC_PER_MSEC */) > +/* Maximum allowed C-state target residency */ > +#define MAX_CMDLINE_RESIDENCY_US (100 * 1000 /* USEC_PER_MSEC */) > + > static char cmdline_table_str[MAX_CMDLINE_TABLE_LEN] __initdata; > string_param("mwait-idle.table", cmdline_table_str); > > @@ -1589,6 +1594,41 @@ static char *__init get_cmdline_field(ch > } > > /** > + * validate_cmdline_cstate - Validate a C-state from cmdline. > + * @state: The C-state to validate. > + * @prev_state: The previous C-state in the table or NULL. > + * > + * Return: 0 if the C-state is valid or -EINVAL otherwise. Hm, I know we picked this up from upstream, but this function would better return a boolean, rather than 0 or -EINVAL. > + */ > +static int __init validate_cmdline_cstate(struct cpuidle_state *state, > + struct cpuidle_state *prev_state) > +{ > + if (state->exit_latency == 0) > + /* Exit latency 0 can only be used for the POLL state */ > + return -EINVAL; > + > + if (state->exit_latency > MAX_CMDLINE_LATENCY_US) > + return -EINVAL; > + > + if (state->target_residency > MAX_CMDLINE_RESIDENCY_US) > + return -EINVAL; > + > + if (state->target_residency < state->exit_latency) > + return -EINVAL; > + > + if (!prev_state) > + return 0; > + > + if (state->exit_latency <= prev_state->exit_latency) > + return -EINVAL; > + > + if (state->target_residency <= prev_state->target_residency) > + return -EINVAL; I'm not an expert on C-states, but isn't this checking against the previous value kind of defeating part of the purpose of the command line? Also, it might help to also write down those limits in the command line documentation. Thanks, Roger. From xen-devel-bounces@lists.xenproject.org Fri Apr 24 23:15:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 23:15:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294053.1571318 (Exim 4.92) (envelope-from ) id 1wGPkD-0001q8-7q; Fri, 24 Apr 2026 23:15:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294053.1571318; Fri, 24 Apr 2026 23:15:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGPkD-0001q1-4g; Fri, 24 Apr 2026 23:15:33 +0000 Received: by outflank-mailman (input) for mailman id 1294053; Fri, 24 Apr 2026 23:15:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGPkB-0001pv-OU for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 23:15:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGPk9-006D7V-4u for xen-devel@lists.xenproject.org; Sat, 25 Apr 2026 01:15:30 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ebf97f-e002-0a2a0a5209dd-0a2a4505c674-10 for ; Sat, 25 Apr 2026 01:15:30 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ebf990-aaa8-0a2a45050019-aceafc1f88bc-3 for ; Sat, 25 Apr 2026 01:15:30 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 45D0940E34; Fri, 24 Apr 2026 23:15:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C07AFC2BCB0; Fri, 24 Apr 2026 23:15:27 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777072528; bh=oLKd9v1uv4DZICMQa7d2btuR4XwM6ccabR4xaT/WOVs=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=XrPZzhd8gqlvrlhRjmnvzAkOWZkp7z6h07lMvp5hKcGz2ymBYWeuskWexLTk/f31O LWy0Qw1ac3KdNU5L9jgjuwuMaJczlwjZsBakurn2EdLA/NMWleOOtC0YQZL80rcAcO Ze/NnKmoOiwyvgqozVTwRkegiEKMzTYEoeMtFeWMHAfcstN99SpNUeNOjNkuqIez7Q c3FVWzCw6j7A0I1bSGqDXrPbaAGxSRBFRK+UjpjrOQ//ixN19sidlBr9aXUHma5jG0 9M03z7bet+WE23nU59UaAAYS21fRjHRVO/RwaKbHp59RtagmqRqsqzyxVRnhV5mkfw LisnYBy+gfI+w== Date: Fri, 24 Apr 2026 16:15:26 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: Peng Fan cc: =?UTF-8?Q?J=C3=BCrgen_Gro=C3=9F?= , Stefano Stabellini , Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Peng Fan Subject: Re: [PATCH RFC] xen/swiotlb: avoid arch_sync_dma_* on per-device DMA memory In-Reply-To: Message-ID: References: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1721512358-1777072528=:6871" X-purgate-ID: tlsNG-c201ff/1777072530-E85AF443-C6FB816D/0/0 X-purgate-type: clean X-purgate-size: 2710 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1721512358-1777072528=:6871 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Fri, 24 Apr 2026, Peng Fan wrote: > Hi Juergen, > > On Mon, Apr 20, 2026 at 02:19:34PM +0200, Jürgen Groß wrote: > >On 15.04.26 17:08, Peng Fan (OSS) wrote: > >> From: Peng Fan > >> > >> On ARM64, arch_sync_dma_for_{cpu,device}() assumes that the > >> physical address passed in refers to normal RAM that is part of the > >> kernel linear(direct) mapping, as it unconditionally derives a CPU > >> virtual address via phys_to_virt(). > >> > >> With Xen swiotlb, devices may use per-device coherent DMA memory, > >> such as reserved-memory regions described by 'shared-dma-pool', > >> which are assigned to dev->dma_mem. These regions may be marked > >> no-map in DT and therefore are not part of the kernel linear map. > >> In such cases, pfn_valid() still returns true, but phys_to_virt() > >> is not valid and cache maintenance via arch_sync_dma_* will fault. > >> > >> Prevent this by excluding devices with a private DMA memory pool > >> (dev->dma_mem) from the arch_sync_dma_* fast path, and always > >> fall back to xen_dma_sync_* for those devices to avoid invalid > >> phys_to_virt() conversions for no-map DMA memory while preserving the > >> existing fast path for normal, linear-mapped RAM. > >> > >> Signed-off-by: Peng Fan > >> --- > >> drivers/xen/swiotlb-xen.c | 17 +++++++++++++---- > >> 1 file changed, 13 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c > >> index 2cbf2b588f5b20cfbf9e83a8339dc22092c9559a..b1445df99d9a8f1d18a83b8c413bada6e5579209 100644 > >> --- a/drivers/xen/swiotlb-xen.c > >> +++ b/drivers/xen/swiotlb-xen.c > >> @@ -195,6 +195,11 @@ xen_swiotlb_free_coherent(struct device *dev, size_t size, void *vaddr, > >> } > >> #endif /* CONFIG_X86 */ > >> +static inline bool dev_has_private_dma_pool(struct device *dev) > >> +{ > >> + return dev && dev->dma_mem; > >> +} > >> + > > > >I don't think this will compile on x86. > > My bad, I only tried the build for ARM64. I use below changes, if it looks > good. > > #ifdef CONFIG_ARM64 > static inline bool dev_has_private_dma_pool(struct device *dev) > { > return dev && dev->dma_mem; > } > #else > static inline bool dev_has_private_dma_pool(struct device *dev) > { > return false; > } > #endif Please use CONFIG_DMA_DECLARE_COHERENT --8323329-1721512358-1777072528=:6871-- From xen-devel-bounces@lists.xenproject.org Fri Apr 24 23:26:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 24 Apr 2026 23:26:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294063.1571328 (Exim 4.92) (envelope-from ) id 1wGPub-0003UR-4h; Fri, 24 Apr 2026 23:26:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294063.1571328; Fri, 24 Apr 2026 23:26:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGPub-0003UK-1l; Fri, 24 Apr 2026 23:26:17 +0000 Received: by outflank-mailman (input) for mailman id 1294063; Fri, 24 Apr 2026 23:26:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGPuZ-0003UE-87 for xen-devel@lists.xenproject.org; Fri, 24 Apr 2026 23:26:15 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGPuY-00GAmQ-AX for xen-devel@lists.xenproject.org; Sat, 25 Apr 2026 01:26:14 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ebfbb4-e002-0a2a0a5209dd-0a2a450698c6-28 for ; Sat, 25 Apr 2026 01:26:14 +0200 Received: from [172.105.4.254] (helo=tor.source.kernel.org) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ebfc15-7371-0a2a45060019-ac6904fec59a-3 for ; Sat, 25 Apr 2026 01:26:13 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id B16F7600AE; Fri, 24 Apr 2026 23:26:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 21CDAC19425; Fri, 24 Apr 2026 23:26:12 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:cc:Subject:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777073172; bh=kyRqrvgm9QqjIN/vVRy0hj3rI8A+watg1fyfjslJQIM=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=UwwfIxM4JV7wubgaeaYSQkjbGQNgnAwrfN/4+zeuwVqFMOA0LSHbOKzFln0vWgY0G bTiMyd3Q10e9NYCZ3UyicG+k31XBupmLmYGtAsO7td/GNnFlQsspxbnwVXzZ+pKqdE zo/Of9k44IjrCFYqr4wIBJq+oj/q+SXjdtLG1BQuG4rbL+cG7SwhouCa5FO9YiecFI bbK5zj0gbiAy7TzPZILS8p7hCtGThM+owN4VxQwqb6UyJHlUWffG11Smcaiy7m+1Ed lmeBvIX4Jvcr8aG3uOoa4h8iThbEMi9TIRzn/b963ZpF+40oQTde0yCyYn9/4HZANp 4aPZHgoN81vOw== Date: Fri, 24 Apr 2026 16:26:11 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: "Peng Fan (OSS)" cc: Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , xen-devel@lists.xenproject.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Peng Fan , michal.orzel@amd.com Subject: Re: [PATCH RFC] xen/swiotlb: avoid arch_sync_dma_* on per-device DMA memory In-Reply-To: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> Message-ID: References: <20260415-xen-swiotlb-v1-1-de24eda3c0fd@nxp.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-purgate-ID: tlsNG-16d1c6/1777073174-91079D75-C62A58CB/0/0 X-purgate-type: clean X-purgate-size: 4208 +Michal On Wed, 15 Apr 2026, Peng Fan (OSS) wrote: > From: Peng Fan > > On ARM64, arch_sync_dma_for_{cpu,device}() assumes that the > physical address passed in refers to normal RAM that is part of the > kernel linear(direct) mapping, as it unconditionally derives a CPU > virtual address via phys_to_virt(). > > With Xen swiotlb, devices may use per-device coherent DMA memory, > such as reserved-memory regions described by 'shared-dma-pool', > which are assigned to dev->dma_mem. These regions may be marked > no-map in DT and therefore are not part of the kernel linear map. > In such cases, pfn_valid() still returns true, but phys_to_virt() > is not valid and cache maintenance via arch_sync_dma_* will fault. > > Prevent this by excluding devices with a private DMA memory pool > (dev->dma_mem) from the arch_sync_dma_* fast path, and always > fall back to xen_dma_sync_* for those devices to avoid invalid > phys_to_virt() conversions for no-map DMA memory while preserving the > existing fast path for normal, linear-mapped RAM. This might not work either: the Xen side implementation is xen/common/grant_table.c:_cache_flush. Could you please check? From looking at the code, page_get_owner_and_reference might return NULL for pages part of reserved-memory regions marked as no-map. In which case, the Xen hypercall should return -EPERM. > Signed-off-by: Peng Fan > --- > drivers/xen/swiotlb-xen.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c > index 2cbf2b588f5b20cfbf9e83a8339dc22092c9559a..b1445df99d9a8f1d18a83b8c413bada6e5579209 100644 > --- a/drivers/xen/swiotlb-xen.c > +++ b/drivers/xen/swiotlb-xen.c > @@ -195,6 +195,11 @@ xen_swiotlb_free_coherent(struct device *dev, size_t size, void *vaddr, > } > #endif /* CONFIG_X86 */ > > +static inline bool dev_has_private_dma_pool(struct device *dev) > +{ > + return dev && dev->dma_mem; > +} > + > /* > * Map a single buffer of the indicated size for DMA in streaming mode. The > * physical address to use is returned. > @@ -262,7 +267,8 @@ static dma_addr_t xen_swiotlb_map_phys(struct device *dev, phys_addr_t phys, > > done: > if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { > - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr)))) { > + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dev_addr))) && > + !dev_has_private_dma_pool(dev)) { > arch_sync_dma_for_device(phys, size, dir); > arch_sync_dma_flush(); > } else { > @@ -289,7 +295,8 @@ static void xen_swiotlb_unmap_phys(struct device *hwdev, dma_addr_t dev_addr, > BUG_ON(dir == DMA_NONE); > > if (!dev_is_dma_coherent(hwdev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) { > - if (pfn_valid(PFN_DOWN(dma_to_phys(hwdev, dev_addr)))) { > + if (pfn_valid(PFN_DOWN(dma_to_phys(hwdev, dev_addr))) && > + !dev_has_private_dma_pool(hwdev)) { > arch_sync_dma_for_cpu(paddr, size, dir); > arch_sync_dma_flush(); > } else { > @@ -312,7 +319,8 @@ xen_swiotlb_sync_single_for_cpu(struct device *dev, dma_addr_t dma_addr, > struct io_tlb_pool *pool; > > if (!dev_is_dma_coherent(dev)) { > - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr)))) { > + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr))) && > + !dev_has_private_dma_pool(dev)) { > arch_sync_dma_for_cpu(paddr, size, dir); > arch_sync_dma_flush(); > } else { > @@ -337,7 +345,8 @@ xen_swiotlb_sync_single_for_device(struct device *dev, dma_addr_t dma_addr, > __swiotlb_sync_single_for_device(dev, paddr, size, dir, pool); > > if (!dev_is_dma_coherent(dev)) { > - if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr)))) { > + if (pfn_valid(PFN_DOWN(dma_to_phys(dev, dma_addr))) && > + !dev_has_private_dma_pool(dev)) { > arch_sync_dma_for_device(paddr, size, dir); > arch_sync_dma_flush(); > } else { > > --- > base-commit: 66672af7a095d89f082c5327f3b15bc2f93d558e > change-id: 20260415-xen-swiotlb-34a198b6c1d6 > > Best regards, > -- > Peng Fan > From xen-devel-bounces@lists.xenproject.org Sun Apr 26 13:30:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 26 Apr 2026 13:30:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294558.1571337 (Exim 4.92) (envelope-from ) id 1wGzZB-0001bD-45; Sun, 26 Apr 2026 13:30:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294558.1571337; Sun, 26 Apr 2026 13:30:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGzZA-0001b5-WF; Sun, 26 Apr 2026 13:30:33 +0000 Received: by outflank-mailman (input) for mailman id 1294558; Sun, 26 Apr 2026 13:30:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wGzZ9-0001az-5V for xen-devel@lists.xenproject.org; Sun, 26 Apr 2026 13:30:32 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wGzZ6-009you-S5 for xen-devel@lists.xenproject.org; Sun, 26 Apr 2026 15:30:30 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ee1370-bab6-0a2a0a5309dd-0a2a4506cf36-14 for ; Sun, 26 Apr 2026 15:30:30 +0200 Received: from [209.85.160.182] (helo=mail-qt1-f182.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ee1375-7371-0a2a45060019-d155a0b6f1f8-3 for ; Sun, 26 Apr 2026 15:30:30 +0200 Received: by mail-qt1-f182.google.com with SMTP id d75a77b69052e-50d87610513so102256751cf.3 for ; Sun, 26 Apr 2026 06:30:29 -0700 (PDT) Received: from ziepe.ca (crbknf0213w-47-54-130-67.pppoe-dynamic.high-speed.nl.bellaliant.net. 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Message-ID: <20260426133027.GB3501894@ziepe.ca> References: <1776873531.8631fc262581453bbf619ec5b2062170.19db5ea67ab000f373@vates.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-16d1c6/1777210230-51F6BD75-66902853/0/0 X-purgate-type: clean X-purgate-size: 970 On Thu, Apr 23, 2026 at 08:01:50AM +0000, Tian, Kevin wrote: > > On Xen, we have a dedicated hypercalls for moving a device into another > > guest (so it no longer belongs in Dom0, at far as DMA is concerned). > > > > But it looks like there are no way to describe that idea of "attach that > > device to this VM" nor "the device is in a VM"; which makes that > > impracticable. > > > > There may be things that could be done with the vIOMMU objects, but > > there would be no "parent domain" in such case, as said earlier it > > doesn't exist in the IOMMU subsystem. > > > > What is expected to be done instead ? > > > > Teddy > > > > [1] https://www.youtube.com/watch?v=pLMGRgEJ-Eg > > > > It'd be much easier to collect comments if you can put plain words > to explain the problem rather than expecting other folks to watch > the video first... It sounds like CC and pkvm to me so I think it should re-use those mechanisms.. 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On > platforms where the GIC receives this asserted line, the result is > either repeated spurious-interrupt warnings or an unhandled > interrupt fault. > > Restructure cuart_init_postirq() to use early returns in both error > paths. > > Signed-off-by: Oleksii Moisieiev > Reviewed-by: Oleksandr Tyshchenko Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 27 06:51:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 06:51:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294667.1571355 (Exim 4.92) (envelope-from ) id 1wHFo5-00050O-2P; Mon, 27 Apr 2026 06:51:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294667.1571355; Mon, 27 Apr 2026 06:51:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHFo4-00050G-Up; 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pr=C Message-ID: Date: Mon, 27 Apr 2026 08:50:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] xen/dom0less: introduce next_phandle in struct kernel_info To: Oleksii Kurochko , CC: Romain Caritey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <5e3ffb41fab84b5f1b59ea81e6d267def89e2d65.1776957840.git.oleksii.kurochko@gmail.com> From: "Orzel, Michal" Content-Language: pl In-Reply-To: <5e3ffb41fab84b5f1b59ea81e6d267def89e2d65.1776957840.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615D:EE_|BL1PR12MB5899:EE_ X-MS-Office365-Filtering-Correlation-Id: bcc9954f-8555-42de-21b7-08dea42952f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: S2pvlNU7yyDpwfhHwQmnM1gH76dGsrMeh3FKdhC1Bl8LmyxqWVhzzGT1QOMv4Of1ETSNjqTWg4YAfbN0MHhkeB6mZj4ML1Jfg2dPYbyokvO1FhpXuZ0p/Mq8tvzJ15ATEjIFOWNGRCftxGpSDPf+YiZpYsKc3x8srbXrvCfcoWvnaRT3JVTc7iWvET4O3BkzSUPQD1k1hh1KvTr9rvZUsvYPd7+NNpmAcK6Xf9VU2KDO9zWbQIXD5KZ5gg7puxuGcndgvkOMsDfyzynB3mWySzW/OhoqhAdxbm/+ai0yazQCnDNYkN7yNgbj3pmRfagO3L4mK/YcjI8mm2EPxyyH5FSPvIoL4suwMiYUZslBRWl1Dz6ZKHr5CU4bdxwlEK6VAFk1W07SSHrEfYwN3oozqMPLVeuEXbUtS/rhzHOHooVvwZnQfGJLwomOcVpaY//l X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 06:50:52.3932 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bcc9954f-8555-42de-21b7-08dea42952f0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MW1PEPF0001615D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5899 X-purgate-ID: tlsNG-4011c0/1777272658-8047C8B7-B2A4323A/10/73395122804 X-purgate-type: spam X-purgate-size: 1212 On 24-Apr-26 3:36 PM, Oleksii Kurochko wrote: > There are cases where it is necessary to know the next available phandle > number in order to generate phandles for guest device nodes. > > When a partial FDT (pfdt) is provided, special care is needed during > initialization of next_phandle, as the pfdt may already contain a dummy > interrupt controller node with a phandle assigned to it. next_phandle > must therefore be initialized to one past the highest phandle already > present in the pfdt, to avoid collisions. > > Since next_phandle may be needed for the very first guest node generated, > domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). > The new call site also aligns better with the existing comment stating > that domain_handle_dtb_boot_module() must be called before the rest of > the device tree is generated. > > Introduce alloc_phandle() to ensure that phandles allocated for guest > nodes do not overlap the Xen-reserved phandle range. This helper will > be used by subsequent patches (by RISC-V at the moment). > > Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 27 08:20:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 08:20:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294691.1571380 (Exim 4.92) (envelope-from ) id 1wHHCZ-0008G1-S3; Mon, 27 Apr 2026 08:20:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294691.1571380; Mon, 27 Apr 2026 08:20:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHHCZ-0008Ft-Mu; Mon, 27 Apr 2026 08:20:23 +0000 Received: by outflank-mailman (input) for mailman id 1294691; Mon, 27 Apr 2026 08:20:22 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHHCY-0008Fm-By for xen-devel@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EAS/lDF4dA3JhuEufD3uxWrhgqbQALUQi62tw3zU24/wz4EAM/turOqZABjla3Je0W/vu0VpglPq6sJRnmVG0j1jyVDx+G+651dXpcKiiDEwYVcigTavTVbjd067AwkxFrZJ3x6K3NsIqhRkneIPUkaYv+arhslr++omtQFnmEUdnkmZxRP+xrbK/fCgqTEv4MwZjbz1EoLWVMzVQAjcbPhGsGxQ0kzmasMqJHqj1NxMRwDUkcwfkNdOz2tvRlxCW2usNIOuMp2/SC8pGhBfG03nt5XDXyXjYtxzx0lk+pjbiDZUioEFC9LzJmnG0GLYJ8HxiJ0ueYM3DN0m8F/iW2CktPj8NUrJVvzTVnTsNJI0wwoP8XsGIY8iAiEY33x8m4F4LtlSUoWqj4fwoyhANkyjiCc9LnqaorL/2MyPs+9xZpI+QLM/OOS3QjjR8PPz X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 08:20:16.1808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0114b0cc-1af8-4af8-07ec-08dea435cfff X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001A5.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: FRZPR08MB11925 X-purgate-ID: tlsNG-720697/1777278020-B3B60161-55A93EFD/0/0 X-purgate-type: clean X-purgate-size: 1131 Hi Mykola, > On 2 Apr 2026, at 12:45, Mykola Kvach wrote: >=20 > From: Mykola Kvach >=20 > init_tee_secondary() was marked __init and freed after boot. Calling it > from the CPU hotplug/resume path then executed discarded code, which > could crash Xen. Drop __init so the TEE mediator secondary init can run > safely on hotplugged and resumed CPUs. >=20 > Signed-off-by: Mykola Kvach Reviewed-by: Bertrand Marquis Cheers Bertrand > --- > xen/arch/arm/tee/tee.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/xen/arch/arm/tee/tee.c b/xen/arch/arm/tee/tee.c > index 8501443c8e..00e561fc78 100644 > --- a/xen/arch/arm/tee/tee.c > +++ b/xen/arch/arm/tee/tee.c > @@ -128,7 +128,7 @@ static int __init tee_init(void) >=20 > presmp_initcall(tee_init); >=20 > -void __init init_tee_secondary(void) > +void init_tee_secondary(void) > { > if ( cur_mediator && cur_mediator->ops->init_secondary ) > cur_mediator->ops->init_secondary(); > --=20 > 2.43.0 >=20 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 08:22:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 08:22:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294704.1571392 (Exim 4.92) (envelope-from ) id 1wHHED-0000Nb-93; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: l++/Kcw4GfDl8et0QmeGjAtJE/y/wv4KEVNcjwMv411UUUStTGYYsIrIwTOlII8InUxd0fnONTrXl02XMD7Dv7FSmgwKbt6Ij53s+o7cTbLs4rpJvC5Fd/hLuoNDQUj/0NEn/j8GRc0I/dupwGes0NkgRkOyAFlfFB5wTJ+bmHWTjPPuwWyIFQEjzsecbwRZCK+8J8povUH+297puP19u3I9bus6BJdmJ2v9MTLjUgwxbsUq4q54+pgKgDgIyFLaqjcKzNRxcWBsjRROhHx/CSgdStaEaFtojTKeMY0PjblGiHklV1ABMi5xUvtZZCW/jyjkpkGVutr5iq7A7uRwXCVsz32KpcgivwtgKib2+4vmkVYjib//m1mdqPZekt7p3SqflhyIYOBPXZV0G8HkzwcmYUAnCkBOa5KVg6Axj1e5kVy5UJNn8Hngd3+nghX7 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 08:21:57.9128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f18a5699-1eba-4bfd-5d31-08dea4360c9f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B93.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6209 X-purgate-ID: tlsNG-4011c0/1777278122-47B7F8B7-0C60E4A3/0/0 X-purgate-type: clean X-purgate-size: 4192 Hi Mykola, > On 2 Apr 2026, at 12:45, Mykola Kvach wrote: >=20 > From: Mykola Kvach >=20 > The FF-A notification SRI interrupt handler was not correctly tied to > CPU hotplug and suspend/resume. As a result, CPUs going offline and > back online could end up with stale or missing handlers, breaking > delivery of FF-A notifications. >=20 > Signed-off-by: Mykola Kvach This will probably need a rebase if the harden notification and VM to VM no= tification serie in FF-A is merged first. Anyway, changes look good so: Reviewed-by: Bertrand Marquis Cheers Bertrand > --- > xen/arch/arm/tee/ffa_notif.c | 63 ++++++++++++++++++++++++++++-------- > 1 file changed, 50 insertions(+), 13 deletions(-) >=20 > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index 186e726412..513c399594 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -360,10 +360,28 @@ static int32_t ffa_notification_bitmap_destroy(uint= 16_t vm_id) > return ffa_simple_call(FFA_NOTIFICATION_BITMAP_DESTROY, vm_id, 0, 0, = 0); > } >=20 > -void ffa_notif_init_interrupt(void) > +static DEFINE_PER_CPU_READ_MOSTLY(struct irqaction, sri_irq); > + > +static int request_sri_irq(void) > { > int ret; > + struct irqaction *sri_action =3D &this_cpu(sri_irq); > + > + sri_action->name =3D "FF-A notif"; > + sri_action->handler =3D notif_irq_handler; > + sri_action->dev_id =3D NULL; > + sri_action->free_on_release =3D 0; > + > + ret =3D setup_irq(notif_sri_irq, 0, sri_action); > + if ( ret ) > + printk(XENLOG_ERR "ffa: setup_irq irq %u failed: error %d\n", > + notif_sri_irq, ret); >=20 > + return ret; > +} > + > +void ffa_notif_init_interrupt(void) > +{ > if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI ) > { > /* > @@ -376,14 +394,36 @@ void ffa_notif_init_interrupt(void) > * pending, while the SPMC in the secure world will not notice th= at > * the interrupt was lost. > */ > - ret =3D request_irq(notif_sri_irq, 0, notif_irq_handler, "FF-A n= otif", > - NULL); > - if ( ret ) > - printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\= n", > - notif_sri_irq, ret); > + request_sri_irq(); > } > } >=20 > +static void deinit_ffa_notif_interrupt(void) > +{ > + if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI ) > + release_irq(notif_sri_irq, NULL); > +} > + > +static int cpu_ffa_notif_callback(struct notifier_block *nfb, > + unsigned long action, > + void *hcpu) > +{ > + switch ( action ) > + { > + case CPU_DYING: > + deinit_ffa_notif_interrupt(); > + break; > + default: > + break; > + } > + > + return NOTIFY_DONE; > +} > + > +static struct notifier_block cpu_ffa_notif_nfb =3D { > + .notifier_call =3D cpu_ffa_notif_callback, > +}; > + > void ffa_notif_init(void) > { > const struct arm_smccc_1_2_regs arg =3D { > @@ -392,7 +432,6 @@ void ffa_notif_init(void) > }; > struct arm_smccc_1_2_regs resp; > unsigned int irq; > - int ret; >=20 > /* Only enable fw notification if all ABIs we need are supported */ > if ( ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) && > @@ -408,13 +447,11 @@ void ffa_notif_init(void) > notif_sri_irq =3D irq; > if ( irq >=3D NR_GIC_SGI ) > irq_set_type(irq, IRQ_TYPE_EDGE_RISING); > - ret =3D request_irq(irq, 0, notif_irq_handler, "FF-A notif", NUL= L); > - if ( ret ) > - { > - printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\= n", > - irq, ret); > + > + if ( request_sri_irq() ) > return; > - } > + > + register_cpu_notifier(&cpu_ffa_notif_nfb); > fw_notif_enabled =3D true; > } > } > --=20 > 2.43.0 >=20 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 08:43:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 08:43:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294717.1571414 (Exim 4.92) (envelope-from ) id 1wHHYe-0003Vc-0z; Mon, 27 Apr 2026 08:43:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294717.1571414; Mon, 27 Apr 2026 08:43:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHHYd-0003VV-Ti; Mon, 27 Apr 2026 08:43:11 +0000 Received: by outflank-mailman (input) for mailman id 1294717; Mon, 27 Apr 2026 08:43:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHHYb-0003VP-VK for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 08:43:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHHYb-00EztE-By for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:43:09 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef219d-5cb7-0a2a0a5109dd-0a2a450cc00a-0 for ; Mon, 27 Apr 2026 10:43:09 +0200 Received: from [209.85.167.43] (helo=mail-lf1-f43.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef219c-62f1-0a2a450c0019-d155a72bac60-3 for ; Mon, 27 Apr 2026 10:43:09 +0200 Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-5a0faa0d15cso9676813e87.0 for ; Mon, 27 Apr 2026 01:43:09 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Comparing the masked but unshifted values against GIC_BASER_CACHE_nC, which is an unshifted enum value, leads to incorrect detection of non-cacheable GITS_BASER tables and GICR_PROPBASER mappings. Use MASK_EXTR() to decode these cacheability fields before comparing against GIC_BASER_CACHE_nC, so the backing memory is flushed when required. Fixes: 05238012b86d ("ARM: GICv3 ITS: allocate device and collection table") Fixes: c9b939863c89 ("ARM: GICv3: allocate LPI pending and property table") Signed-off-by: Mykyta Poturai Signed-off-by: Mykola Kvach --- Changes in v3: - drop CBASER command queue hunk (separate functional change, not the same shifted-mask bug) Changes in v2: - use MASK_EXTR() instead of open-coding the BASER field shift - fix the analogous PROPBASER cacheability comparison in gicv3_lpi_set_proptable() - fix the CBASER command queue cacheability check as well --- xen/arch/arm/gic-v3-its.c | 3 ++- xen/arch/arm/gic-v3-lpi.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index e38aa87117..9005ce8ce5 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -496,7 +496,8 @@ retry: } attr = regc & BASER_ATTR_MASK; } - if ( (regc & GITS_BASER_INNER_CACHEABILITY_MASK) <= GIC_BASER_CACHE_nC ) + if ( MASK_EXTR(regc, GITS_BASER_INNER_CACHEABILITY_MASK) <= + GIC_BASER_CACHE_nC ) clean_and_invalidate_dcache_va_range(buffer, table_size); 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If only there wasn't the error > handling after copy_to_guest(): Dropping the paging lock ahead of that > call, we rely solely on the P2M lock to also guard the changing of > d->arch.hvm.dirty_vram.sh and what it points to. Question is why dropping > the paging lock (but continuing to hold the P2M lock) is necessary there > in the first place. I wouldn't spend a lot of time trying to optimize this, we already know HVM shadow is ATM not very optimized, and generally recommend HAP. If we could turn the p2m lock into read-mode, maybe at the expense of expanding the paging locked region that would likely be slightly better? Thanks, Roger. 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pr=C Message-ID: <71ae72eb-3424-4d41-afb7-9f1462e84aaf@amd.com> Date: Mon, 27 Apr 2026 11:21:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] xen: introduce CONFIG_HAS_DOMAIN_TYPE To: Oleksii Kurochko , CC: Romain Caritey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: From: "Orzel, Michal" Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E0:EE_|MW4PR12MB6730:EE_ X-MS-Office365-Filtering-Correlation-Id: b8c5cb0a-74c7-48c6-58bd-08dea43e6228 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: t3lugM+UK3uwOXdLoAdM3vi+OB5mDx07AXk3YIgFafhgjvOQO6S0TJcLBVubrD013hWMhFjnDI/qqx4aQt3TRfVJ93lm3lTGU3+vtXqx9fmb87Jh3iCdqkXne02tys55pWnHJEntX/u4W/9vqDCzmrePyJiRm3/eEFtziPLTPMDkLOiQy6klzHBHyTVz5MKu2msVBCTWNlOIzNb8wTpKoHBWDtb0EBh4erQ9B8R2tTgRvwp/QJSFt/akqvlNkG/1gc0HWiEqX0HO7q5PihPjQPWl27D6HwQ5XKrc/+Q+TocmssreH+u2m54LVKTrfDr1+LpqmVyrkk8l31mcMHELzwgMc6cZqcS2slBKlsUTNFPsk/aqKgr+09VPeOGyOQ8t12VwxSSJfHcDXvksrs6M7xVL04Ma5lOQ8uw47IGGjAFMCwhRxlmEhigZoLoWwR/Q4yq85b9yG2RLZBrb8jyg1LIB3yt+0nfQ2qO7blrL9frF8irTQ3aXN7JKFu2EIzVDXr7kSgA62B6Lc1Q7rsyRBAVqORYiNRILtrvmuTLvIIXcsvAbbNc5g5uuXpkceXDuskUM1RaboIAkmInm+B7TeXBJqFCSVovqHeh2bSCV7HYj2F569sXhhkIA92TJ13a19k6zRc8IWDP1TM1kamdhUj68fkAxqTNaoM0MNzC8ZyovuwcCx7HTV5Xx6RI3MHPlZKyRrj91QeU9lN9QqObrzC3urX7d/rz6Vkxk1CJALwa6P186lhPINc1aXi2YzdCy8b3GmFZ7M++4Whl0O+E3lQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P/KOPCUG9dYLl5q7rIE5O+XXMgbMw6pDAR4OTRIXFVm9EodTVDraJgwxSqEvN8ddpvUOWNj6QjeTr1uRXOZMREU8qYmOV8ZlBlkm0AVI3YLVaJ55JoArhEXUe3FQAlThkBuAYBddF73uVCOY8HM+RrrBtotzM+PWFGTo5Yv0pVSSG2ekbg2wXk3QTruBoJXwwYTgsNwJ8ab6m2YNQe0biGLhFckby44GJY0z9yu3iDexwK8NmevRIu5+qjCVpwlO5Pajh82F39BC1cPdAu0W7oMK4W6nbGMEvW7hn+ZdtJTDxTIcqsMcdx4OOgAJBjzA3vPWvCbgLjhz7BQ7rxtSUpahrPx7A+eax6IdVoWCYFpEJ4SWxPckRUOC6ZpGs7Z0dzVb80ZMcbVvAKK0GsUQ8T8TdxImXmrCBjru+1gINYamtve4kRbxC6NHTDou3GEh X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 09:21:37.4479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8c5cb0a-74c7-48c6-58bd-08dea43e6228 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E0.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6730 X-purgate-ID: tlsNG-4011c0/1777281704-453638B7-31460ADA/10/73395122804 X-purgate-type: spam X-purgate-size: 873 On 24-Apr-26 3:36 PM, Oleksii Kurochko wrote: > As domain type is part of common code now there is no any reason NIT: remove "any" after "no" > to have architecture-specific set_domain_type() functions so > it is dropped. > > Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE > for consistency. Also, drop and add some parentheses to be aligned > with the similar if() below. > > x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as > x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no > longer builds, the fallback is currently only relevant for arm32. > > Signed-off-by: Oleksii Kurochko You don't seem to remove enum domain_type type from struct arch_domain which is now unused. With that removed: Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 27 09:28:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 09:28:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294746.1571441 (Exim 4.92) (envelope-from ) id 1wHIGZ-0001ca-PR; Mon, 27 Apr 2026 09:28:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294746.1571441; Mon, 27 Apr 2026 09:28:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHIGZ-0001cT-Ma; Mon, 27 Apr 2026 09:28:35 +0000 Received: by outflank-mailman (input) for mailman id 1294746; Mon, 27 Apr 2026 09:28:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHIGY-0001cN-6J for xen-devel@lists.xenproject.org; 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(The opposite isn't true, > because of _sh_propagate() setting the field to a valid value without > setting a bit in the bitmap.) As a consequence > - setting the field to a valid value right after having allocated zero- > filled space is pointless, > - copying the the all empty bitmap to the output array is pointless; with Double 'the'? > the output array also having been allocated zero-filled, not even a > memset() is needed there, > - after restoring bitmap contents when dealing with copy_to_guest() having > failed, the field needs setting to a valid value again. > > Furthermore invoking NOW() in perhaps many loop iterations of the main > loop is wasteful, too. Record whether any bit was set, and record a new > ->last_dirty only once, after the loop. Then use the same NOW() value also > for the subsequent check. > > Signed-off-by: Jan Beulich > > --- a/xen/arch/x86/mm/shadow/hvm.c > +++ b/xen/arch/x86/mm/shadow/hvm.c > @@ -1087,18 +1087,18 @@ int shadow_track_dirty_vram(struct domai > if ( (dirty_vram->dirty_bitmap = xzalloc_array(uint8_t, dirty_size)) == NULL ) > goto out_sl1ma; > > - dirty_vram->last_dirty = NOW(); > + dirty_vram->last_dirty = -1; > > /* Tell the caller that this time we could not track dirty bits. */ > rc = -ENODATA; > } > - else if ( dirty_vram->last_dirty == -1 ) > - /* still completely clean, just copy our empty bitmap */ > - memcpy(dirty_bitmap, dirty_vram->dirty_bitmap, dirty_size); > - else > + /* Nothing to do when the bitmap is still completely clean. */ > + else if ( dirty_vram->last_dirty != -1 ) > { > mfn_t map_mfn = INVALID_MFN; > void *map_sl1p = NULL; > + bool any_dirty = false; > + s_time_t now; > > /* Iterate over VRAM to track dirty bits. */ > for ( i = 0; i < nr_frames; i++ ) > @@ -1174,16 +1174,20 @@ int shadow_track_dirty_vram(struct domai > if ( dirty ) > { > dirty_vram->dirty_bitmap[i / 8] |= 1 << (i % 8); > - dirty_vram->last_dirty = NOW(); > + any_dirty = true; > } > } > > + now = NOW(); > + if ( any_dirty ) > + dirty_vram->last_dirty = now; I'm a bit confused with the setting of ->last_dirty here ... > + > if ( map_sl1p ) > unmap_domain_page(map_sl1p); > > memcpy(dirty_bitmap, dirty_vram->dirty_bitmap, dirty_size); > memset(dirty_vram->dirty_bitmap, 0, dirty_size); ... as here the bitmap is zeroed, and hence ->last_dirty should be set to -1? > - if ( dirty_vram->last_dirty + SECONDS(2) < NOW() ) > + if ( dirty_vram->last_dirty + SECONDS(2) < now ) > { > /* > * Was clean for more than two seconds, try to disable guest > @@ -1216,6 +1220,7 @@ int shadow_track_dirty_vram(struct domai > paging_lock(d); > for ( i = 0; i < dirty_size; i++ ) > dirty_vram->dirty_bitmap[i] |= dirty_bitmap[i]; > + dirty_vram->last_dirty = NOW(); I think this is doesn't deserve a 'Fixes:' tag because the setting of ->last_dirty unconditionally to NOW() regardless of whether the bitmap is zeroed? Thanks, Roger. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Q/dwaMsFK09PxRs7GbW+gn8N42PRGKxurBHLFI01noiowJbgOmCobtarcKauhu3fVG/prjAGT/q34sbUaynMwxRfjxPcJ1/bNX2fiYGvQ5GEqZ0YXIrsG8uv0WKyIlCkqUWTVrSMkFTzg3QSHySr3/cLnN2g84Iub4SuKWgHfbsY1d6t9EHxVfid7q+6ZEU/IWHCOy8FhsfmfCyjYAftMROvHnjwuZ+s69IrVfSAXZ65XeOeK1AXSB2UhUXDFsIJncvKI12nlVio7QY07gzqWycSxEvKJlwQ5AnAt/Fo+cN7CAm69omxIqVQtf/iDcAheFPfm7ifdMec0DEE36BHMcwbAru6ChSsQ8FC9VJPO2xnpFG1WR5JIa6oCugqZOldq2HY4fpVGmist1njZIbffxlHPSDDrnhHweeL6ID5w7EG+JtoKm4RGy2E0TlLFPkd X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 09:29:44.0311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40dad48f-4153-4309-cc09-08dea43f8435 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9218 X-purgate-ID: tlsNG-c201ff/1777282192-E13A0443-DC5A69E3/0/0 X-purgate-type: clean X-purgate-size: 905 On 27-Apr-26 10:37 AM, Mykola Kvach wrote: > From: Mykola Kvach > > GITS_BASER_INNER_CACHEABILITY_MASK and > GICR_PROPBASER_INNER_CACHEABILITY_MASK are shifted masks. Comparing the > masked but unshifted values against GIC_BASER_CACHE_nC, which is an > unshifted enum value, leads to incorrect detection of non-cacheable > GITS_BASER tables and GICR_PROPBASER mappings. > > Use MASK_EXTR() to decode these cacheability fields before comparing > against GIC_BASER_CACHE_nC, so the backing memory is flushed when > required. > > Fixes: 05238012b86d ("ARM: GICv3 ITS: allocate device and collection table") > Fixes: c9b939863c89 ("ARM: GICv3: allocate LPI pending and property table") > Signed-off-by: Mykyta Poturai > Signed-off-by: Mykola Kvach Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Mon Apr 27 09:30:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 09:30:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294762.1571459 (Exim 4.92) (envelope-from ) id 1wHIIE-0003VM-Ee; Mon, 27 Apr 2026 09:30:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294762.1571459; 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This may in particular > help with possible future locking changes. > > Signed-off-by: Jan Beulich Acked-by: Roger Pau Monné Thanks, Roger. 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The implementation in tools/libs/store/xs.c already use this signature and method. Signed-off-by: Frediano Ziglio --- tools/libs/ctrl/xc_private.c | 26 +++++--------------------- tools/libs/ctrl/xc_private.h | 2 +- 2 files changed, 6 insertions(+), 22 deletions(-) diff --git a/tools/libs/ctrl/xc_private.c b/tools/libs/ctrl/xc_private.c index bb0f81d6f389..946fc307aabd 100644 --- a/tools/libs/ctrl/xc_private.c +++ b/tools/libs/ctrl/xc_private.c @@ -635,7 +635,7 @@ int write_exact(int fd, const void *data, size_t size) /* * MiniOS's libc doesn't know about writev(). Implement it as multiple write()s. */ -int writev_exact(int fd, const struct iovec *iov, int iovcnt) +int writev_exact(int fd, struct iovec *iov, int iovcnt) { int rc, i; @@ -649,9 +649,8 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) return 0; } #else -int writev_exact(int fd, const struct iovec *iov, int iovcnt) +int writev_exact(int fd, struct iovec *iov, int iovcnt) { - struct iovec *local_iov = NULL; int rc = 0, iov_idx = 0, saved_errno = 0; ssize_t len; @@ -686,23 +685,9 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) len -= iov[iov_idx++].iov_len; else { - /* Partial write of iov[iov_idx]. Copy iov so we can adjust - * element iov_idx and resubmit the rest. */ - if ( !local_iov ) - { - local_iov = malloc(iovcnt * sizeof(*iov)); - if ( !local_iov ) - { - saved_errno = ENOMEM; - rc = -1; - goto out; - } - - iov = memcpy(local_iov, iov, iovcnt * sizeof(*iov)); - } - - local_iov[iov_idx].iov_base += len; - local_iov[iov_idx].iov_len -= len; + /* Partial write of iov[iov_idx]. */ + iov[iov_idx].iov_base += len; + iov[iov_idx].iov_len -= len; break; } } @@ -711,7 +696,6 @@ int writev_exact(int fd, const struct iovec *iov, int iovcnt) saved_errno = 0; out: - free(local_iov); errno = saved_errno; return rc; } diff --git a/tools/libs/ctrl/xc_private.h b/tools/libs/ctrl/xc_private.h index b5892ae8dc1e..3af996e9002e 100644 --- a/tools/libs/ctrl/xc_private.h +++ b/tools/libs/ctrl/xc_private.h @@ -383,7 +383,7 @@ int xc_flush_mmu_updates(xc_interface *xch, struct xc_mmu *mmu); /* Return 0 on success; -1 on error setting errno. */ int read_exact(int fd, void *data, size_t size); /* EOF => -1, errno=0 */ int write_exact(int fd, const void *data, size_t size); -int writev_exact(int fd, const struct iovec *iov, int iovcnt); +int writev_exact(int fd, struct iovec *iov, int iovcnt); int xc_ffs8(uint8_t x); int xc_ffs16(uint16_t x); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 10:54:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 10:54:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294782.1571521 (Exim 4.92) (envelope-from ) id 1wHJbN-0006qz-Qf; Mon, 27 Apr 2026 10:54:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294782.1571521; Mon, 27 Apr 2026 10:54:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbN-0006qH-NL; Mon, 27 Apr 2026 10:54:09 +0000 Received: by outflank-mailman (input) for mailman id 1294782; Mon, 27 Apr 2026 10:54:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbM-0006Ur-QL for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:54:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHJbM-00FJ4k-6s for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 12:54:08 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef404d-2eae-0a2a0a5409dd-0a2a4506aba4-14 for ; Mon, 27 Apr 2026 12:54:08 +0200 Received: from [209.85.128.47] (helo=mail-wm1-f47.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef404f-7371-0a2a45060019-d155802fe164-3 for ; Mon, 27 Apr 2026 12:54:08 +0200 Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso140739775e9.3 for ; Mon, 27 Apr 2026 03:54:08 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Signed-off-by: Edwin Török Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_common.h | 13 +++++++ tools/libs/guest/xg_sr_save.c | 66 +++++++++++++-------------------- 2 files changed, 39 insertions(+), 40 deletions(-) diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_common.h index ec42b4a9e535..f84c47800098 100644 --- a/tools/libs/guest/xg_sr_common.h +++ b/tools/libs/guest/xg_sr_common.h @@ -211,6 +211,18 @@ static inline int update_blob(struct xc_sr_blob *blob, return 0; } +struct xc_sr_context_save_buffers +{ + xen_pfn_t batch_pfns[MAX_BATCH_SIZE]; + xen_pfn_t mfns[MAX_BATCH_SIZE]; + xen_pfn_t types[MAX_BATCH_SIZE]; + int errors[MAX_BATCH_SIZE]; + void *guest_data[MAX_BATCH_SIZE]; + void *local_pages[MAX_BATCH_SIZE]; + struct iovec iov[MAX_BATCH_SIZE + 2]; /* headers + data */ + uint64_t rec_pfns[MAX_BATCH_SIZE]; +}; + struct xc_sr_context { xc_interface *xch; @@ -246,6 +258,7 @@ struct xc_sr_context unsigned long *deferred_pages; unsigned long nr_deferred_pages; xc_hypercall_buffer_t dirty_bitmap_hbuf; + struct xc_sr_context_save_buffers *buffers; } save; struct /* Restore data. */ diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 8c4e760f8d0a..7d8055a3f9e8 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -86,16 +86,16 @@ static int write_checkpoint_record(struct xc_sr_context *ctx) static int write_batch(struct xc_sr_context *ctx) { xc_interface *xch = ctx->xch; - xen_pfn_t *mfns = NULL, *types = NULL; + xen_pfn_t *mfns, *types; void *guest_mapping = NULL; - void **guest_data = NULL; - void **local_pages = NULL; - int *errors = NULL, rc = -1; + void **guest_data; + void **local_pages; + int *errors, rc = -1; unsigned int i, p, nr_pages = 0, nr_pages_mapped = 0; unsigned int nr_pfns = ctx->save.nr_batch_pfns; void *page, *orig_page; - uint64_t *rec_pfns = NULL; - struct iovec *iov = NULL; int iovcnt = 0; + uint64_t *rec_pfns; + struct iovec *iov; int iovcnt = 0; struct { struct xc_sr_rhdr rec; struct xc_sr_rec_page_data_header page_data; @@ -105,26 +105,24 @@ static int write_batch(struct xc_sr_context *ctx) }; assert(nr_pfns != 0); + assert(nr_pfns <= MAX_BATCH_SIZE); + assert(ctx->save.buffers); /* Mfns of the batch pfns. */ - mfns = malloc(nr_pfns * sizeof(*mfns)); + mfns = ctx->save.buffers->mfns; /* Types of the batch pfns. */ - types = malloc(nr_pfns * sizeof(*types)); + types = ctx->save.buffers->types; /* Errors from attempting to map the gfns. */ - errors = malloc(nr_pfns * sizeof(*errors)); + errors = ctx->save.buffers->errors; /* Pointers to page data to send. Mapped gfns or local allocations. */ - guest_data = calloc(nr_pfns, sizeof(*guest_data)); + guest_data = ctx->save.buffers->guest_data; + memset(guest_data, 0, sizeof(*guest_data) * nr_pfns); /* Pointers to locally allocated pages. Need freeing. */ - local_pages = calloc(nr_pfns, sizeof(*local_pages)); + local_pages = ctx->save.buffers->local_pages; + memset(local_pages, 0, sizeof(*local_pages) * nr_pfns); /* iovec[] for writev(). */ - iov = malloc((nr_pfns + 2) * sizeof(*iov)); - - if ( !mfns || !types || !errors || !guest_data || !local_pages || !iov ) - { - ERROR("Unable to allocate arrays for a batch of %u pages", - nr_pfns); - goto err; - } + iov = ctx->save.buffers->iov; + rec_pfns = ctx->save.buffers->rec_pfns; for ( i = 0; i < nr_pfns; ++i ) { @@ -210,14 +208,6 @@ static int write_batch(struct xc_sr_context *ctx) } } - rec_pfns = malloc(nr_pfns * sizeof(*rec_pfns)); - if ( !rec_pfns ) - { - ERROR("Unable to allocate %zu bytes of memory for page data pfn list", - nr_pfns * sizeof(*rec_pfns)); - goto err; - } - hdrs.rec.length = sizeof(hdrs.page_data); hdrs.rec.length += nr_pfns * sizeof(*rec_pfns); hdrs.rec.length += nr_pages * PAGE_SIZE; @@ -267,17 +257,13 @@ static int write_batch(struct xc_sr_context *ctx) rc = ctx->save.nr_batch_pfns = 0; err: - free(rec_pfns); if ( guest_mapping ) xenforeignmemory_unmap(xch->fmem, guest_mapping, nr_pages_mapped); for ( i = 0; local_pages && i < nr_pfns; ++i ) + { free(local_pages[i]); - free(iov); - free(local_pages); - free(guest_data); - free(errors); - free(types); - free(mfns); + local_pages[i] = NULL; + } return rc; } @@ -805,18 +791,18 @@ static int setup(struct xc_sr_context *ctx) dirty_bitmap = xc_hypercall_buffer_alloc_pages( xch, dirty_bitmap, NRPAGES(bitmap_size(ctx->save.p2m_size))); - ctx->save.batch_pfns = malloc(MAX_BATCH_SIZE * - sizeof(*ctx->save.batch_pfns)); ctx->save.deferred_pages = bitmap_alloc(ctx->save.p2m_size); + ctx->save.buffers = calloc(1, sizeof(*ctx->save.buffers)); - if ( !ctx->save.batch_pfns || !dirty_bitmap || !ctx->save.deferred_pages ) + if ( !dirty_bitmap || !ctx->save.deferred_pages || !ctx->save.buffers) { - ERROR("Unable to allocate memory for dirty bitmaps, batch pfns and" - " deferred pages"); + ERROR("Unable to allocate memory for dirty bitmaps, deferred pages" + " and various batch buffers"); rc = -1; errno = ENOMEM; goto err; } + ctx->save.batch_pfns = ctx->save.buffers->batch_pfns; rc = 0; @@ -840,7 +826,7 @@ static void cleanup(struct xc_sr_context *ctx) xc_hypercall_buffer_free_pages(xch, dirty_bitmap, NRPAGES(bitmap_size(ctx->save.p2m_size))); free(ctx->save.deferred_pages); - free(ctx->save.batch_pfns); + free(ctx->save.buffers); } /* -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 10:54:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 10:54:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294776.1571467 (Exim 4.92) (envelope-from ) id 1wHJbH-0005Wv-69; Mon, 27 Apr 2026 10:54:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294776.1571467; Mon, 27 Apr 2026 10:54:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbH-0005Wo-2w; Mon, 27 Apr 2026 10:54:03 +0000 Received: by outflank-mailman (input) for mailman id 1294776; Mon, 27 Apr 2026 10:54:02 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbG-0005Wi-An for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:54:02 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHJbF-00FJ1T-5F for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 12:54:01 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef4044-2eae-0a2a0a5409dd-0a2a450895ee-24 for ; Mon, 27 Apr 2026 12:54:01 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef4048-63b5-0a2a45080019-d155802ef010-3 for ; Mon, 27 Apr 2026 12:54:01 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-488d2079582so119218975e9.2 for ; Mon, 27 Apr 2026 03:54:01 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Avoid possible allocation sending data with writev. Reduce number of allocations sending memory state. Changes since v1: - add commit to cache up to 4 pages in hypercall; - add other 2 commits reducing chunks passed to write/writev. Edwin Török (2): tools/libs/guest: allocate various migration arrays just once tools/lib/call: cache up to 4 pages in hypercall bounce buffers Frediano Ziglio (5): xenguest: Reduce number of parts in write_split_record xenguest: Reduce number of I/O vectors in write_batch xenguest: Allows writev_exact to change iov array xenguest: Reduce number of I/O vectors in write_batch xenguest: Use a single write_exact in write_headers tools/libs/call/buffer.c | 28 +++--- tools/libs/call/core.c | 3 +- tools/libs/call/private.h | 8 +- tools/libs/ctrl/xc_private.c | 26 ++---- tools/libs/ctrl/xc_private.h | 2 +- tools/libs/guest/xg_sr_common.c | 6 +- tools/libs/guest/xg_sr_common.h | 13 +++ tools/libs/guest/xg_sr_save.c | 147 +++++++++++++++----------------- 8 files changed, 114 insertions(+), 119 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 10:54:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 10:54:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294783.1571531 (Exim 4.92) (envelope-from ) id 1wHJbP-00077p-8A; Mon, 27 Apr 2026 10:54:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294783.1571531; Mon, 27 Apr 2026 10:54:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbP-00077X-2u; Mon, 27 Apr 2026 10:54:11 +0000 Received: by outflank-mailman (input) for mailman id 1294783; Mon, 27 Apr 2026 10:54:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbN-0006pf-SB for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:54:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHJbN-004Ir6-8B for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 12:54:09 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef4051-5cb7-0a2a0a5109dd-0a2a4503c4b8-0 for ; Mon, 27 Apr 2026 12:54:09 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef4051-672d-0a2a45030019-d1558033c86d-3 for ; Mon, 27 Apr 2026 12:54:09 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4891e5b9c1fso84864145e9.2 for ; Mon, 27 Apr 2026 03:54:09 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Eventually it'd be good if the memory pool from xmalloc_tlsf.c was reused here, but for now make it handle the commonly encountered sizes (so far up to 4 pages). Signed-off-by: Edwin Török Signed-off-by: Frediano Ziglio --- tools/libs/call/buffer.c | 28 +++++++++++++++++----------- tools/libs/call/core.c | 3 ++- tools/libs/call/private.h | 8 +++++--- 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/tools/libs/call/buffer.c b/tools/libs/call/buffer.c index 2579b8c71986..15d2f98a6b71 100644 --- a/tools/libs/call/buffer.c +++ b/tools/libs/call/buffer.c @@ -56,13 +56,13 @@ static void *cache_alloc(xencall_handle *xcall, size_t nr_pages) if ( xcall->buffer_current_allocations > xcall->buffer_maximum_allocations ) xcall->buffer_maximum_allocations = xcall->buffer_current_allocations; - if ( nr_pages > 1 ) + if ( nr_pages > ARRAY_SIZE(xcall->buffer_cache) ) { xcall->buffer_cache_toobig++; } - else if ( xcall->buffer_cache_nr > 0 ) + else if ( xcall->buffer_cache_nr[nr_pages-1] > 0 ) { - p = xcall->buffer_cache[--xcall->buffer_cache_nr]; + p = xcall->buffer_cache[nr_pages-1][--xcall->buffer_cache_nr[nr_pages-1]]; xcall->buffer_cache_hits++; } else @@ -84,10 +84,10 @@ static int cache_free(xencall_handle *xcall, void *p, size_t nr_pages) xcall->buffer_total_releases++; xcall->buffer_current_allocations--; - if ( nr_pages == 1 && - xcall->buffer_cache_nr < BUFFER_CACHE_SIZE ) + if ( nr_pages && nr_pages < ARRAY_SIZE(xcall->buffer_cache) && + xcall->buffer_cache_nr[nr_pages-1] < BUFFER_CACHE_SIZE ) { - xcall->buffer_cache[xcall->buffer_cache_nr++] = p; + xcall->buffer_cache[nr_pages-1][xcall->buffer_cache_nr[nr_pages-1]++] = p; rc = 1; } @@ -108,17 +108,23 @@ void buffer_release_cache(xencall_handle *xcall) DBGPRINTF("current allocations:%d maximum allocations:%d", xcall->buffer_current_allocations, xcall->buffer_maximum_allocations); - DBGPRINTF("cache current size:%d", - xcall->buffer_cache_nr); + for ( unsigned i = 0; i < ARRAY_SIZE(xcall->buffer_cache_nr); ++i ) + { + DBGPRINTF("cache current size[%u pages]:%d", i+1, + xcall->buffer_cache_nr[i]); + } DBGPRINTF("cache hits:%d misses:%d toobig:%d", xcall->buffer_cache_hits, xcall->buffer_cache_misses, xcall->buffer_cache_toobig); - while ( xcall->buffer_cache_nr > 0 ) + for ( unsigned i = 0; i < ARRAY_SIZE(xcall->buffer_cache_nr); ++i ) { - p = xcall->buffer_cache[--xcall->buffer_cache_nr]; - osdep_free_pages(xcall, p, 1); + while ( xcall->buffer_cache_nr[i] > 0 ) + { + p = xcall->buffer_cache[i][--xcall->buffer_cache_nr[i]]; + osdep_free_pages(xcall, p, i + 1); + } } cache_unlock(xcall); diff --git a/tools/libs/call/core.c b/tools/libs/call/core.c index 02c4f8e1aefa..dd8877c1a0bd 100644 --- a/tools/libs/call/core.c +++ b/tools/libs/call/core.c @@ -14,6 +14,7 @@ */ #include +#include #include "private.h" @@ -44,7 +45,7 @@ xencall_handle *xencall_open(xentoollog_logger *logger, unsigned open_flags) xentoolcore__register_active_handle(&xcall->tc_ah); xcall->flags = open_flags; - xcall->buffer_cache_nr = 0; + memset(xcall->buffer_cache_nr, 0, sizeof(xcall->buffer_cache_nr)); xcall->buffer_total_allocations = 0; xcall->buffer_total_releases = 0; diff --git a/tools/libs/call/private.h b/tools/libs/call/private.h index 9c3aa432efe2..8e6a20897534 100644 --- a/tools/libs/call/private.h +++ b/tools/libs/call/private.h @@ -31,13 +31,15 @@ struct xencall_handle { Xentoolcore__Active_Handle tc_ah; /* - * A simple cache of unused, single page, hypercall buffers + * A simple cache of unused, small, hypercall buffers + * buffer_cache[i]'s size is (i+1) pages * * Protected by a global lock. */ #define BUFFER_CACHE_SIZE 4 - int buffer_cache_nr; - void *buffer_cache[BUFFER_CACHE_SIZE]; +#define BUFFER_CACHE_NRPAGES 4 + int buffer_cache_nr[BUFFER_CACHE_NRPAGES]; + void *buffer_cache[BUFFER_CACHE_NRPAGES][BUFFER_CACHE_SIZE]; /* * Hypercall buffer statistics. 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Reduce number of pieces passed to writev. Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_save.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 3b2c5222e429..1700d819051a 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -97,9 +97,12 @@ static int write_batch(struct xc_sr_context *ctx) void *page, *orig_page; uint64_t *rec_pfns = NULL; struct iovec *iov = NULL; int iovcnt = 0; - struct xc_sr_rec_page_data_header hdr = { 0 }; - struct xc_sr_record rec = { - .type = REC_TYPE_PAGE_DATA, + struct { + struct xc_sr_rhdr rec; + struct xc_sr_rec_page_data_header page_data; + } hdrs = { + { .type = REC_TYPE_PAGE_DATA }, + { 0 }, }; assert(nr_pfns != 0); @@ -115,7 +118,7 @@ static int write_batch(struct xc_sr_context *ctx) /* Pointers to locally allocated pages. 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This potentially exceed Linux maximum (1024). Also some implementation (MiniOS) emulate writev with multiple write calls. Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_save.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 1700d819051a..62a39dfecc7a 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -240,13 +240,20 @@ static int write_batch(struct xc_sr_context *ctx) { for ( i = 0; i < nr_pfns; ++i ) { - if ( guest_data[i] ) + if ( !guest_data[i] ) + continue; + + if ( iov[iovcnt-1].iov_base + iov[iovcnt-1].iov_len != guest_data[i] ) { iov[iovcnt].iov_base = guest_data[i]; iov[iovcnt].iov_len = PAGE_SIZE; iovcnt++; - --nr_pages; } + else + { + iov[iovcnt-1].iov_len += PAGE_SIZE; + } + --nr_pages; } } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 10:54:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 10:54:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294781.1571509 (Exim 4.92) (envelope-from ) id 1wHJbM-0006SW-Kt; Mon, 27 Apr 2026 10:54:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294781.1571509; Mon, 27 Apr 2026 10:54:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbM-0006S6-Cq; Mon, 27 Apr 2026 10:54:08 +0000 Received: by outflank-mailman (input) for mailman id 1294781; Mon, 27 Apr 2026 10:54:07 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbL-0006HQ-OI for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:54:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHJbL-004Ir6-5F for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 12:54:07 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef404f-5cb7-0a2a0a5109dd-0a2a4502c732-0 for ; Mon, 27 Apr 2026 12:54:07 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef404e-af86-0a2a45020019-d155802eb0af-3 for ; Mon, 27 Apr 2026 12:54:07 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-483487335c2so98602365e9.2 for ; Mon, 27 Apr 2026 03:54:07 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_save.c | 37 +++++++++++++++++------------------ 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/tools/libs/guest/xg_sr_save.c b/tools/libs/guest/xg_sr_save.c index 62a39dfecc7a..8c4e760f8d0a 100644 --- a/tools/libs/guest/xg_sr_save.c +++ b/tools/libs/guest/xg_sr_save.c @@ -10,17 +10,22 @@ static int write_headers(struct xc_sr_context *ctx, uint16_t guest_type) { xc_interface *xch = ctx->xch; int32_t xen_version = xc_version(xch, XENVER_version, NULL); - struct xc_sr_ihdr ihdr = { - .marker = IHDR_MARKER, - .id = htonl(IHDR_ID), - .version = htonl(3), - .options = htons(IHDR_OPT_LITTLE_ENDIAN), - }; - struct xc_sr_dhdr dhdr = { - .type = guest_type, - .page_shift = XC_PAGE_SHIFT, - .xen_major = (xen_version >> 16) & 0xffff, - .xen_minor = (xen_version) & 0xffff, + struct { + struct xc_sr_ihdr ihdr; + struct xc_sr_dhdr dhdr; + } hdrs = { + { + .marker = IHDR_MARKER, + .id = htonl(IHDR_ID), + .version = htonl(3), + .options = htons(IHDR_OPT_LITTLE_ENDIAN), + }, + { + .type = guest_type, + .page_shift = XC_PAGE_SHIFT, + .xen_major = (xen_version >> 16) & 0xffff, + .xen_minor = (xen_version) & 0xffff, + }, }; if ( xen_version < 0 ) @@ -29,15 +34,9 @@ static int write_headers(struct xc_sr_context *ctx, uint16_t guest_type) return -1; } - if ( write_exact(ctx->fd, &ihdr, sizeof(ihdr)) ) - { - PERROR("Unable to write Image Header to stream"); - return -1; - } - - if ( write_exact(ctx->fd, &dhdr, sizeof(dhdr)) ) + if ( write_exact(ctx->fd, &hdrs, sizeof(hdrs)) ) { - PERROR("Unable to write Domain Header to stream"); + PERROR("Unable to write Headers to stream"); return -1; } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 10:54:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 10:54:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294777.1571476 (Exim 4.92) (envelope-from ) id 1wHJbI-0005ju-CO; Mon, 27 Apr 2026 10:54:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294777.1571476; Mon, 27 Apr 2026 10:54:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbI-0005jn-9h; Mon, 27 Apr 2026 10:54:04 +0000 Received: by outflank-mailman (input) for mailman id 1294777; Mon, 27 Apr 2026 10:54:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHJbH-0005d1-M0 for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 10:54:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHJbH-004Inu-2U for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 12:54:03 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef4047-5cb7-0a2a0a5109dd-0a2a4506ab9a-28 for ; Mon, 27 Apr 2026 12:54:03 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef404a-7371-0a2a45060019-d1558031b8af-3 for ; Mon, 27 Apr 2026 12:54:02 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488a88aeec9so125694715e9.2 for ; Mon, 27 Apr 2026 03:54:02 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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There's no much sense to split the header in 2 pieces, it will just take more time and space to reassemble them in the final buffer. This also avoids truncating combined_length to 32 bit in case of 64 bit machines potentially avoiding following record_length check. The function become more coherent with following read_record function. Signed-off-by: Frediano Ziglio --- tools/libs/guest/xg_sr_common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/libs/guest/xg_sr_common.c b/tools/libs/guest/xg_sr_common.c index 7ccdc3b1f6aa..86c148c62f3e 100644 --- a/tools/libs/guest/xg_sr_common.c +++ b/tools/libs/guest/xg_sr_common.c @@ -59,11 +59,11 @@ int write_split_record(struct xc_sr_context *ctx, struct xc_sr_record *rec, static const char zeroes[(1u << REC_ALIGN_ORDER) - 1] = { 0 }; xc_interface *xch = ctx->xch; - typeof(rec->length) combined_length = rec->length + sz; + size_t combined_length = rec->length + sz; size_t record_length = ROUNDUP(combined_length, REC_ALIGN_ORDER); + struct xc_sr_rhdr rhdr = { rec->type, combined_length }; struct iovec parts[] = { - { &rec->type, sizeof(rec->type) }, - { &combined_length, sizeof(combined_length) }, + { &rhdr, sizeof(rhdr) }, { rec->data, rec->length }, { buf, sz }, { (void *)zeroes, record_length - combined_length }, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 11:38:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 11:38:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294848.1571548 (Exim 4.92) (envelope-from ) id 1wHKHl-0006qZ-F7; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=hrWP7PDOax19ipthmTHj5VA87kpS9207hOAXZ+9QQII=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=qZZCIgtUIxp43hXoj9Ud6chhyFjqMORWIUDH/I37nPLrXtYhuHMNfXuCx2BfrtNydeoqojodV 60EtvVOLc2fHTcHcG8ApbS866IIRTpB23tedXu31LhblJchguwuLPRFh4wNA9aMSvFhKyW4OZEV gWDYrICba+EdCfqtzc+k3r74/VY5BbpKg8dVXjNSaVhdPzyIob8mItOPHTOjaLFwsNqncHv+J1G KwCr6Ag0vi59bMuNk+ZWZ+x28jsaMkR6BXkBQqGmGQ3TRdHOCnwxtLwQWeXyTIqseNYicfcsDeU ssACWTlWAbvIflezu3XfQD77g34M0fwuhwLlgnTPrHXw== X-Zone-Loop: 492a10de2d9539b7d5598e7f4b37dac5a76e200bbdf9 x-campaign-type: default x-transaction-id: b805f4ec-9786-4370-b7af-896787cb240a x-swg-uid: 01-893d04e9-0ece-4f91-8421-830e938dd535 X-Mailer: Sweego Message-ID: <1777289871.8631fc262581453bbf619ec5b2062170.19dcebb4015000f373@vates.tech> x-swg-bid: 1777289871.8631fc262581453bbf619ec5b2062170.19dcebb4015000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Mon, 27 Apr 2026 13:37:50 +0200 From: Anthony PERARD To: Frediano Ziglio Cc: xen-devel@lists.xenproject.org, Frediano Ziglio , Jan Beulich , Andrew Cooper , Roger Pau =?iso-8859-1?Q?Monn=E9?= , Teddy Astie , Juergen Gross Subject: Re: [PATCH v2 0/7] Minor xenguest optimisations References: <20260427105338.99792-1-frediano.ziglio@cloud.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260427105338.99792-1-frediano.ziglio@cloud.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2943.c447f66c6a72a997.19dcebb3dbc.51a878fbab5a8cc9=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777289870780 X-purgate-ID: tlsNG-33051d/1777289872-A2F62938-9DE6C680/0/0 X-purgate-type: clean X-purgate-size: 1452 ---=Part.2943.c447f66c6a72a997.19dcebb3dbc.51a878fbab5a8cc9=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Mon, Apr 27, 2026 at 11:53:25AM +0100, Frediano Ziglio wrote: > Edwin T=C3=B6r=C3=B6k (2): > tools/libs/guest: allocate various migration arrays just once > tools/lib/call: cache up to 4 pages in hypercall bounce buffers >=20 > Frediano Ziglio (5): > xenguest: Reduce number of parts in write_split_record > xenguest: Reduce number of I/O vectors in write_batch > xenguest: Allows writev_exact to change iov array > xenguest: Reduce number of I/O vectors in write_batch > xenguest: Use a single write_exact in write_headers Hi Frediano, When you will resend the patch, could you change the prefix? "xenguest" to me is a XenServer / XCP-ng binary that happen to live in the xen repo, not something that exist upstream=2E There's plenty of better way to prefix those commits, looking at the history of the lib: libs/guest libs/xg tools/libs/guest tools/xg tools/libxg tools/libs/guest I think I prefer "libs/guest"=2E And looks like there's one patch that doesn't touch libxenguest at all, yet it is prefix with "xenguest:"=2E Cheers, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.2943.c447f66c6a72a997.19dcebb3dbc.51a878fbab5a8cc9=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 12:47:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 12:47:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294863.1571564 (Exim 4.92) (envelope-from ) id 1wHLMb-0007RE-Fn; Mon, 27 Apr 2026 12:47:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294863.1571564; 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boundary="-=Part.2953.2ae372a6068e561c.19dcefa6ff4.4de407b991a5f481=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777294012405 X-purgate-ID: tlsNG-4011c0/1777294018-453638B7-9F98EF3C/0/0 X-purgate-type: clean X-purgate-size: 3014 ---=Part.2953.2ae372a6068e561c.19dcefa6ff4.4de407b991a5f481=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Apr 23, 2026 at 04:46:10PM +0200, Thierry Escande wrote: > This series adds new 'hotplug' option for PCI device passthrough=2E >=20 > The current mechanism for device passthrough uses QMP device_add command > to hot-plug PCI devices to the guest Qemu instance=2E This is an issue f= or > guests running on Q35 chipset (preliminary support posted at [1]) since = the > Q35 PCI root bus does not support hotplug=2E Devices could be hotplugged= to > a secondary PCI bus but Xen only support 1 PCI bus for now=2E >=20 > The 'hotplug' option allows to control how devices are attached to the > guest, either by using the legacy QMP mechanism (this is the default) or= by > passing them directly to the Qemu command line using xen-pci-passthrough > device=2E Hi Thierry, I don't like this new "hotplug" option=2E It is just an implementation detail on how the device is added to QEMU=2E It is just going to be confusing for users=2E Because in both case, the device is "cold-plugged", it just happen to be inserted after QEMU thing it is fully configured, but the guest hasn't really started yet=2E It is likely that we implemented the pci passthrough this way because it worked and because we could reuse the same code path for real hotplug as well=2E So, for the patch that is really needed (adding the device on the command line), we could do just for the Q35 machine, or we could do that for all guests=2E For the second option, probably the best one, but we are going to try to find out if everything work as expected, especially Linux stubdomain=2E > Example usage in cfg file: > pci =3D [ "00:03=2E0,seize=3D1,hotplug=3D0" ] >=20 > Since Qemu -device option accepts parameters in json format, this > patchset adds a new internal function libxl__device_pci_get_qapi_json() = that > generates the device json object used for both QMP hotplug and command l= ine > passing=2E >=20 > Also, to handle the assignable PCI device list, the function > libxl_pci_assignable() is renamed as libxl_device_pci_assignable() and i= s I though you were renaming a public API function, but the original one was static with the wrong name=2E (function prefixed with "libxl_", one underscore, are in the public API, private one to libxl are prefixed with "libxl__"=2E) > made available from libxl=2Eh for access in libxl_dm=2Ec=2E 2 other func= tions are If you only mean to use a function internally, add it to libxl_internal=2Eh, I don't want to expose more functions to the API without a good reason=2E `xl pci-assignable-list` already work, so I don't think exposing a new function is useful=2E Cheers, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.2953.2ae372a6068e561c.19dcefa6ff4.4de407b991a5f481=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:29:31 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:29:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294870.1571574 (Exim 4.92) (envelope-from ) id 1wHM1Q-0004Qg-EO; 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Also, drop and add some parentheses to be aligned >> with the similar if() below. >> >> x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as >> x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no >> longer builds, the fallback is currently only relevant for arm32. >> >> Signed-off-by: Oleksii Kurochko > You don't seem to remove enum domain_type type from struct arch_domain which is > now unused. With that removed: Oh, right. I dropped it only from struct kernel_info. I will drop it. > Reviewed-by: Michal Orzel Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:54:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:54:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294881.1571584 (Exim 4.92) (envelope-from ) id 1wHMQA-0008VV-BI; Mon, 27 Apr 2026 13:54:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294881.1571584; Mon, 27 Apr 2026 13:54:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHMQA-0008VO-8W; Mon, 27 Apr 2026 13:54:46 +0000 Received: by outflank-mailman (input) for mailman id 1294881; Mon, 27 Apr 2026 13:54:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHMQ9-0008VH-8B for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 13:54:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHMQ8-00G6M2-JF for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 15:54:44 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef6a97-5cb7-0a2a0a5109dd-0a2a450a90a8-44 for ; Mon, 27 Apr 2026 15:54:44 +0200 Received: from [185.255.28.34] (helo=prod-mta-13.swg-srv.net) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef6aa4-56b3-0a2a450a0019-b9ff1c22a053-3 for ; Mon, 27 Apr 2026 15:54:44 +0200 Received: from mail2.vates.fr ([37.26.189.201] mail2.vates.fr) (Authenticated sender: 8631fc262581453bbf619ec5b2062170/smtp/7773de5a-2839-4720-82ee-e06722ae1d3e) by prod-mta-13.swg-srv.net (ZoneMTA - prod-mta-13) with ESMTPSA id 19dcf387bbd000f373.007 for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 27 Apr 2026 13:54:38 +0000 Received: from julian.home (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: julian.vetter@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id E2539865DE; Mon, 27 Apr 2026 15:54:37 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=0Ab05w3Cc3n+I13wVZW7ebdwmBh1B9H+TUWiPdGq5RY=; h=from:subject:date:message-id:to:cc:mime-version:content-type:feedback-id; b=hUZJV/UxG/DXY7Q8EauK9ziJ/o9/vaV6aUCIfgtk68BL0l3v6s2/G1pEdAuXVPRdvdxJB159Z A6J+WWvEfq5RZ36PbaC1wVuiVi/IhFh1r4LaRc2nCZYdY0ctugGRkRiuaMpV2cloOG+H49gu8Gj 65qzISNWtIegMzUBEAl9NoUTfwSo583o5GPGpGKWlCwJWrbI9sVg/6rknwDeYu5y/1GrSymbdej lOgSRKAH3RDrVKlVBt5EVayww+OC+O0Rj9DUYVtVPuxC0SdOuEjBtjNCztQ531SfVtbJSJsACd3 IsR0z/WBrJl6hQ4a7ymOxZV0wNMgxFdeLFeppj3e63lw== X-Zone-Loop: 56a54a6456f57479f343e5543d2972b35cf9f7d82bab x-campaign-type: default x-transaction-id: 1c3fc14c-551e-4a61-9226-e3a507f66146 x-swg-uid: 01-e1e72c33-c0fb-4343-b56d-cab55ec8025f X-Mailer: Sweego Message-ID: <1777298078.8631fc262581453bbf619ec5b2062170.19dcf387bbd000f373@vates.tech> x-swg-bid: 1777298078.8631fc262581453bbf619ec5b2062170.19dcf387bbd000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 0/9] x86/hvm: Add Extended MSI destination ID support Date: Mon, 27 Apr 2026 15:53:57 +0200 MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2972.abfc823cf368011e.19dcf3879c2.a24ad5d5067271c8=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298078147 X-purgate-ID: tlsNG-4011c0/1777298084-80A7F8B7-40F03E11/0/0 X-purgate-type: clean X-purgate-size: 4541 ---=Part.2972.abfc823cf368011e.19dcf3879c2.a24ad5d5067271c8=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Thank you very much Roger and Jan for your feedback! I have addressed your feedback, see below=2E For me there is only one question, I'm not sure if this is what you had in mind Roger when you wrote: "Retrofitting the new interface into the old one seems weird=2E I would do it the other way around - implement the old bind domctl on top of an interface that's more suited for the new DM op=2E" It requires some preparatory work=2E But I tried to make the restructunring diffs as easy to review as possible by splitting the refactoring into mutliple steps=2E Signed-off-by: Julian Vetter --- Changes in v4: - Replaced the v3 approach of extending the XEN_DOMCTL_bind_pt_irq gflags ABI (XEN_DOMCTL_VMSI_X86_EXT_DEST_ID_MASK / VMSI_X86_FULL_DEST) with raw MSI addr + data storage throughout=2E pt_irq_bind_msi() now accepts the raw address + data values and decodes the destination internally=2E No public domctl ABI changes - As suggested by Roger, replaced XEN_DMOP_enable_ext_dest_id (v3 patch 6, a separate call before domain start) with a flags byte from the existing pad[3] field of XEN_DMOP_create_ioreq_server=2E The new XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID flag lets each server signal support at registration time and allows the feature to be levelled across all servers before arch_domain_creation_finished() - Redirect xc_domain_{update,unbind}_msi_irq() in libxenctrl to use the new DM ops, and reject PT_IRQ_TYPE_MSI in XEN_DOMCTL_{bind,unbind}_pt_irq (as suggested by Jan) - Add three preparatory no-functional-change commits (patches 2-4) that wrap the restart block in braces, extract pt_irq_dpci_setup(), and extract the PT_IRQ_TYPE_MSI case body into pt_irq_bind_msi(), making the interface change in patch 5 reviewable as a clean diff - Rework ioapic_check() to validate named fields (base_address, APIC ID width, ioregsel range) instead of rejecting any non-zero reserved bits, which would have falsely rejected RTEs carrying extended destination IDs --- Julian Vetter (9): x86/vioapic: Add ioapic_check() to validate IO-APIC state before restore x86/passthrough: Wrap pt_irq_create_bind() restart block in braces x86/passthrough: Extract pt_irq_dpci_setup() from pt_irq_create_bind() x86/passthrough: Extract PT_IRQ_TYPE_MSI body into pt_irq_bind_msi() x86/passthrough: Introduce pt_irq_bind_msi() as canonical MSI bind path x86/hvm: Support extended destination IDs in virtual MSI and IO-APIC x86/dmop: Add XEN_DMOP_{bind,unbind}_pt_msi_irq DM ops hvm/ioreq: Negotiate extended destination ID support per ioreq server x86/cpuid: Advertise XEN_HVM_CPUID_EXT_DEST_ID when device model opts in tools/include/xendevicemodel=2Eh | 34 +- tools/libs/ctrl/xc_devicemodel_compat=2Ec | 2 +- tools/libs/ctrl/xc_domain=2Ec | 52 ++-- tools/libs/devicemodel/core=2Ec | 41 ++- xen/arch/arm/ioreq=2Ec | 5 + xen/arch/x86/cpuid=2Ec | 13 + xen/arch/x86/domain=2Ec | 10 + xen/arch/x86/domctl=2Ec | 10 +- xen/arch/x86/hvm/dm=2Ec | 68 ++++ xen/arch/x86/hvm/ioreq=2Ec | 37 +++ xen/arch/x86/hvm/irq=2Ec | 9 +- xen/arch/x86/hvm/vioapic=2Ec | 50 ++- xen/arch/x86/hvm/vmsi=2Ec | 54 +--- xen/arch/x86/include/asm/hvm/domain=2Eh | 9 + xen/arch/x86/include/asm/hvm/hvm=2Eh | 4 +- xen/arch/x86/include/asm/hvm/irq=2Eh | 4 +- xen/arch/x86/include/asm/hvm/vioapic=2Eh | 12 + xen/arch/x86/include/asm/msi=2Eh | 18 +- xen/common/ioreq=2Ec | 13 +- xen/drivers/passthrough/x86/hvm=2Ec | 396 ++++++++++++++---------- xen/include/public/arch-x86/hvm/save=2Eh | 21 +- xen/include/public/hvm/dm_op=2Eh | 53 +++- xen/include/xen/iommu=2Eh | 3 + xen/include/xen/ioreq=2Eh | 27 ++ xen/include/xlat=2Elst | 2 + 25 files changed, 703 insertions(+), 244 deletions(-) --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2972.abfc823cf368011e.19dcf3879c2.a24ad5d5067271c8=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:54:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:54:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294885.1571611 (Exim 4.92) (envelope-from ) id 1wHMQK-0000lW-6V; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=W6jJeFHlnxQriqm4ULKsDBrsDCyMY1Q7f5BSbeqFbcU=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=V7MxvOhePlTFu45csDwAzNIlBwj54zD+mZNspe3ooRDnNb5AyX7Qu1vPEOindNXbMjQCxspVG BkQjfF8uKrVMOwqV/NiheLAvajnQIL1i/qliFazKjprdmeXKwdsZPNXrBg+bV7XVpeUK8hqBDEF uhCALt/jO8nrTolasJuOoP9CuPXRL+6Tbda7JirHiNuWgAnR+OFAcdRC/RtZV2s50UqlUTvPUF4 peKDnnVabv6hFmS4Wx1OgTu2Zi7AdK0lPwAzwL7uFVIqxZ+JI2j4UGYmadWhW0jHQ4vWgBUvWnC /iW6tuIL/Jyrc3s3uMgP6cEXplgkorQIVwhwxb61xFEA== X-Zone-Loop: 6aeb684b3b03ddb97f269851a8e054cfd1874d6a8e8b x-campaign-type: default x-transaction-id: daa0c376-b8c0-4fc2-a6f0-daf148b1cec6 x-swg-uid: 01-695e8fc4-0d06-4f19-b360-195d6f63116c X-Mailer: Sweego Message-ID: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387f6f000f373@vates.tech> x-swg-bid: 1777298079.8631fc262581453bbf619ec5b2062170.19dcf387f6f000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 3/9] x86/passthrough: Extract pt_irq_dpci_setup() from pt_irq_create_bind() Date: Mon, 27 Apr 2026 15:54:00 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2975.a3c70ac1ac8036d.19dcf387e09.478a393e5b10a835=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298079241 X-purgate-ID: tlsNG-4011c0/1777298094-47F798B7-C02DFD8C/0/0 X-purgate-type: clean X-purgate-size: 4749 ---=Part.2975.a3c70ac1ac8036d.19dcf387e09.478a393e5b10a835=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable The setup preamble in pt_irq_create_bind(), lazily allocating hvm_irq_dpci, looking up the struct pirq, and spinning until any pending hvm_dirq_assist softirq has drained, is needed by pt_irq_bind_msi() as well=2E Extract it into a static helper pt_irq_dpci_setup() that returns with d->event_lock write-locked on success=2E Replace the open-coded goto restart loop with a do { } while (true) loop and a continue, making the retry structure explicit without a label=2E No functional change=2E Signed-off-by: Julian Vetter --- Changes in v4: - New patch - Split out as a preparatory no-functional-change step to make the diff in patch 5 (pt_irq_bind_msi() interface change) easier to review --- xen/drivers/passthrough/x86/hvm=2Ec | 54 +++++++++++++++++++++++-------- 1 file changed, 40 insertions(+), 14 deletions(-) diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index 691fa1b2c7=2E=2E19463c3406 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -217,18 +217,22 @@ static struct vcpu *vector_hashing_dest(const struct= domain *d, return dest; } =20 -int pt_irq_create_bind( - struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) +/* + * Acquire d->event_lock (write), lazily allocate hvm_irq_dpci if needed,= look + * up the struct pirq for @pirq, and drain any pending hvm_dirq_assist so= ftirq + * on it before returning=2E Returns 0 with d->event_lock held on success= , + * negative errno otherwise (lock not held)=2E + */ +static int pt_irq_dpci_setup(struct domain *d, unsigned int pirq, + struct hvm_irq_dpci **hvm_irq_dpci_out, + struct hvm_pirq_dpci **pirq_dpci_out, + struct pirq **info_out) { struct hvm_irq_dpci *hvm_irq_dpci; struct hvm_pirq_dpci *pirq_dpci; struct pirq *info; - int rc, pirq =3D pt_irq_bind->machine_irq; =20 - if ( pirq < 0 || pirq >=3D d->nr_pirqs ) - return -EINVAL; - - restart: + do { write_lock(&d->event_lock); =20 @@ -238,10 +242,11 @@ int pt_irq_create_bind( unsigned int i; =20 /* - * NB: the hardware domain doesn't use a hvm_irq_dpci struct = because - * it's only allowed to identity map GSIs, and so the data co= ntained in - * that struct (used to map guest GSIs into machine GSIs and = perform - * interrupt routing) is completely useless to it=2E + * NB: the hardware domain doesn't use a hvm_irq_dpci struct + * because it's only allowed to identity map GSIs, and so the + * data contained in that struct (used to map guest GSIs into + * machine GSIs and perform interrupt routing) is completely + * useless to it=2E */ hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); if ( hvm_irq_dpci =3D=3D NULL ) @@ -269,15 +274,36 @@ int pt_irq_create_bind( * We MUST check for this condition as the softirq could be sched= uled * and hasn't run yet=2E Note that this code replaced tasklet_kil= l which * would have spun forever and would do the same thing (wait to f= lush out - * outstanding hvm_dirq_assist calls=2E + * outstanding hvm_dirq_assist calls)=2E */ if ( pt_pirq_softirq_active(pirq_dpci) ) { write_unlock(&d->event_lock); cpu_relax(); - goto restart; + continue; } - } + + *hvm_irq_dpci_out =3D hvm_irq_dpci; + *pirq_dpci_out =3D pirq_dpci; + *info_out =3D info; + return 0; + } while ( true ); +} + +int pt_irq_create_bind( + struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) +{ + struct hvm_irq_dpci *hvm_irq_dpci; + struct hvm_pirq_dpci *pirq_dpci; + struct pirq *info; + int rc, pirq =3D pt_irq_bind->machine_irq; + + if ( pirq < 0 || pirq >=3D d->nr_pirqs ) + return -EINVAL; + + rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &info); + if ( rc ) + return rc; =20 switch ( pt_irq_bind->irq_type ) { --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2975.a3c70ac1ac8036d.19dcf387e09.478a393e5b10a835=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:54:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:54:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294883.1571603 (Exim 4.92) (envelope-from ) id 1wHMQI-0000WX-0H; Mon, 27 Apr 2026 13:54:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294883.1571603; Mon, 27 Apr 2026 13:54:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHMQH-0000WO-SW; Mon, 27 Apr 2026 13:54:53 +0000 Received: by outflank-mailman (input) for mailman id 1294883; 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Mon, 27 Apr 2026 13:54:39 +0000 Received: from julian.home (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: julian.vetter@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id ACC1187586; Mon, 27 Apr 2026 15:54:38 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=M55ILyTYc2aw6HFK62qDDTDBBSTPjeQAoqU+/EWfFok=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=FhbavZ+jHbvlW71qdtQXujHX8KzmjJBkryM7txqtNTjytUph05GuHbiRzPk5o8kXzH1yYqteV 1hIBO1mo1Z4/8CFHx+CxjCll1qGgAOog89FkMtXuRczuZtkNOz6D81Xhrs49RWT2bjxP9EwgiiI ZWL1j/4jpp/MHez9eMZBmf6lX66aKUSUk/XPjhx0XlGaf0aXaLkM0PTPmcYKRNGViXZf5wi+M5W LdKhVjBwZPx679g6GgdyGfbcIrW81hVbBFIm/6Qq+PW0qMPAS9QhWeZZcvVbLhTvOVcqpSlqDpi o/5Yupelezw4o85V01j4zS6Rbmj4+AnwFTS7hSmwPlvQ== X-Zone-Loop: a4445c9258778274922d4e8b326bffba7c04a0539124 x-campaign-type: default x-transaction-id: f79cca4a-7e5a-41ee-8d3f-74f172fd813a x-swg-uid: 01-6e7e7490-5a7b-4903-9675-9c25475a6e66 X-Mailer: Sweego Message-ID: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387e25000f373@vates.tech> x-swg-bid: 1777298079.8631fc262581453bbf619ec5b2062170.19dcf387e25000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 2/9] x86/passthrough: Wrap pt_irq_create_bind() restart block in braces Date: Mon, 27 Apr 2026 15:53:59 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2974.6d24ae21874b484b.19dcf387cc9.7f8b3253be24fb72=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298078922 X-purgate-ID: tlsNG-4011c0/1777298091-CFB7F8B7-1FB5AF6C/0/0 X-purgate-type: clean X-purgate-size: 4613 ---=Part.2974.6d24ae21874b484b.19dcf387cc9.7f8b3253be24fb72=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Enclose the restart/retry block in pt_irq_create_bind() in an explicit compound statement to prepare for its extraction into a helper function=2E No functional change=2E Signed-off-by: Julian Vetter --- Changes in v4: - New patch - Split out as a preparatory no-functional-change step to make the diff in patch 5 (pt_irq_bind_msi() interface change) easier to review --- xen/drivers/passthrough/x86/hvm=2Ec | 80 ++++++++++++++++--------------- 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index b73bb55055=2E=2E691fa1b2c7 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -229,52 +229,54 @@ int pt_irq_create_bind( return -EINVAL; =20 restart: - write_lock(&d->event_lock); - - hvm_irq_dpci =3D domain_get_irq_dpci(d); - if ( !hvm_irq_dpci && !is_hardware_domain(d) ) { - unsigned int i; + write_lock(&d->event_lock); =20 - /* - * NB: the hardware domain doesn't use a hvm_irq_dpci struct beca= use - * it's only allowed to identity map GSIs, and so the data contai= ned in - * that struct (used to map guest GSIs into machine GSIs and perf= orm - * interrupt routing) is completely useless to it=2E - */ - hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); - if ( hvm_irq_dpci =3D=3D NULL ) + hvm_irq_dpci =3D domain_get_irq_dpci(d); + if ( !hvm_irq_dpci && !is_hardware_domain(d) ) + { + unsigned int i; + + /* + * NB: the hardware domain doesn't use a hvm_irq_dpci struct = because + * it's only allowed to identity map GSIs, and so the data co= ntained in + * that struct (used to map guest GSIs into machine GSIs and = perform + * interrupt routing) is completely useless to it=2E + */ + hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); + if ( hvm_irq_dpci =3D=3D NULL ) + { + write_unlock(&d->event_lock); + return -ENOMEM; + } + for ( i =3D 0; i < NR_HVM_DOMU_IRQS; i++ ) + INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]); + + hvm_domain_irq(d)->dpci =3D hvm_irq_dpci; + } + + info =3D pirq_get_info(d, pirq); + if ( !info ) { write_unlock(&d->event_lock); return -ENOMEM; } - for ( i =3D 0; i < NR_HVM_DOMU_IRQS; i++ ) - INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]); - - hvm_domain_irq(d)->dpci =3D hvm_irq_dpci; - } - - info =3D pirq_get_info(d, pirq); - if ( !info ) - { - write_unlock(&d->event_lock); - return -ENOMEM; - } - pirq_dpci =3D pirq_dpci(info); + pirq_dpci =3D pirq_dpci(info); =20 - /* - * A crude 'while' loop with us dropping the spinlock and giving - * the softirq_dpci a chance to run=2E - * We MUST check for this condition as the softirq could be scheduled - * and hasn't run yet=2E Note that this code replaced tasklet_kill wh= ich - * would have spun forever and would do the same thing (wait to flush= out - * outstanding hvm_dirq_assist calls=2E - */ - if ( pt_pirq_softirq_active(pirq_dpci) ) - { - write_unlock(&d->event_lock); - cpu_relax(); - goto restart; + /* + * A crude 'while' loop with us dropping the spinlock and giving + * the softirq_dpci a chance to run=2E + * We MUST check for this condition as the softirq could be sched= uled + * and hasn't run yet=2E Note that this code replaced tasklet_kil= l which + * would have spun forever and would do the same thing (wait to f= lush out + * outstanding hvm_dirq_assist calls=2E + */ + if ( pt_pirq_softirq_active(pirq_dpci) ) + { + write_unlock(&d->event_lock); + cpu_relax(); + goto restart; + } } =20 switch ( pt_irq_bind->irq_type ) --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2974.6d24ae21874b484b.19dcf387cc9.7f8b3253be24fb72=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:54:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:54:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294882.1571593 (Exim 4.92) (envelope-from ) id 1wHMQG-0000II-IG; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=dvcC1iisULiPGWL7tx4WZYzH+K5ni031hXxYUXeM9FA=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=nndc5iGA0DiGhtyIMk+zUdFKEvRAZcfMef0krlgqTReFVE8KCTMfzyDGLs5muIK6t/oE0cpyW jG4XX+kZNeRbrXdsdkobcC+1mlLW1WAoawQKEB/uExnAIBG7cNI5/jHL0z5DkXq6x9Y8oWeDE5T dieOm4qOzeQYUyBPKfdJSGlrEdMsnuOq8FoMz2ton8J9c69kv+RGR8Q1nqO0TRXcY/9ZLilHkBa nxYJUL1OdNyvkSt84TNZYD83mTstQJXA/y7AHyz0AFPe5tEoUvZwuoxW3L/qfgWRRHqBJAPwSeT pj0u8Zgn5LRuHOsxmZdXNGGiFjESbJltSPLH178rklNQ== X-Zone-Loop: 5f20e55a77209d63970ab23c5d2a2c0c952228caec54 x-campaign-type: default x-transaction-id: ad1e73c4-1169-40cf-a79e-c5e95a7fd737 x-swg-uid: 01-252a6e3d-1633-4718-85f7-c25b1dcf860e X-Mailer: Sweego Message-ID: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387cf6000f373@vates.tech> x-swg-bid: 1777298079.8631fc262581453bbf619ec5b2062170.19dcf387cf6000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 1/9] x86/vioapic: Add ioapic_check() to validate IO-APIC state before restore Date: Mon, 27 Apr 2026 15:53:58 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2973.a4b8ae2b085a49c6.19dcf387b7f.2f2b4e9391e281cb=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298078591 X-purgate-ID: tlsNG-4011c0/1777298089-47D788B7-C3FFF285/0/0 X-purgate-type: clean X-purgate-size: 3106 ---=Part.2973.a4b8ae2b085a49c6.19dcf387b7f.2f2b4e9391e281cb=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Register a check callback for the IOAPIC HVM save/restore entry, following the pattern established by vpic_check() for the virtual PIC=2E The function first verifies the target domain actually has a virtual IO-APIC, returning -ENODEV otherwise=2E It then validates individual fields of the saved state: the base_address must be non-zero (as 0 is never valid for the IO-APIC MMIO window), the APIC ID must fit within its 4-bit hardware field, and ioregsel must address a defined register=2E Signed-off-by: Julian Vetter --- Changes in v4: - Replaced the reserved-bit loop from v3 (iterating all redirection table entries and rejecting any with non-zero reserved fields) with targeted named-field validation (base_address !=3D 0, APIC ID < 0xF, and ioregsel addresses a defined register) - The extended-destination migration safety check (refusing to restore IO-APIC state with ext_dest_id bits set on a domain that does not advertise XEN_HVM_CPUID_EXT_DEST_ID) is added in patch 8, once the flag exists --- xen/arch/x86/hvm/vioapic=2Ec | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec index 7c725f9e47=2E=2E43fb165f84 100644 --- a/xen/arch/x86/hvm/vioapic=2Ec +++ b/xen/arch/x86/hvm/vioapic=2Ec @@ -594,6 +594,32 @@ int vioapic_get_trigger_mode(const struct domain *d, = unsigned int gsi) return vioapic->redirtbl[pin]=2Efields=2Etrig_mode; } =20 +static int cf_check ioapic_check(const struct domain *d, hvm_domain_conte= xt_t *h) +{ + const HVM_SAVE_TYPE(IOAPIC) *s; + + if ( !has_vioapic(d) ) + return -ENODEV; + + s =3D hvm_get_entry(IOAPIC, h); + if ( !s ) + return -ENODATA; + + /* base_address of 0 is never valid for the IO-APIC MMIO window=2E */ + if ( !s->base_address ) + return -EINVAL; + + /* IO-APIC APIC ID is a 4-bit field=2E */ + if ( s->id > 0xf ) + return -EINVAL; + + /* ioregsel must address a defined register=2E */ + if ( s->ioregsel > VIOAPIC_REG_RTE0 + (ARRAY_SIZE(s->redirtbl) - 1) *= 2 + 1 ) + return -EINVAL; + + return 0; +} + static int cf_check ioapic_save(struct vcpu *v, hvm_domain_context_t *h) { const struct domain *d =3D v->domain; @@ -630,7 +656,7 @@ static int cf_check ioapic_load(struct domain *d, hvm_= domain_context_t *h) return 0; } =20 -HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, NULL, ioapic_load, 1, +HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_check, ioapic_load,= 1, HVMSR_PER_DOM); =20 void vioapic_reset(struct domain *d) --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2973.a4b8ae2b085a49c6.19dcf387b7f.2f2b4e9391e281cb=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:54:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:54:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294886.1571621 (Exim 4.92) (envelope-from ) id 1wHMQM-00012H-HF; Mon, 27 Apr 2026 13:54:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294886.1571621; Mon, 27 Apr 2026 13:54:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHMQM-00011y-C0; Mon, 27 Apr 2026 13:54:58 +0000 Received: by outflank-mailman (input) for mailman id 1294886; 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Mon, 27 Apr 2026 13:54:39 +0000 Received: from julian.home (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: julian.vetter@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id 59D328716C; Mon, 27 Apr 2026 15:54:39 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=L3geqFZf2EA0sdCca0SSrDfeFYuV7PuXhnEkcbG81vc=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=OEv/MLjvvtXXXRwgAcQUWiyCFjyihrh1lRj6bZdpWasH4YNwJpMGB8pv2xmeULxLMyWnaea0W tPZ81AfBaEgJgf30Qmvzr9HRGZV8BMu3QP2tNnl1/icRJ6R2nu1iOzmc8LsdyqP9tPlMjrotAbe GmzUkuKeJjlN5jxSl4cHPz8v80p90lnx9EDALP/RDa5RzKIKkclrv6C00FZfPJRB+xwUKUxrsgm erDGzBWqppQIryCGwluBtQUcy2a5n6xanqy2g8kzoIQcUR7f5qFdGuuIFSMm8WiF84TdXNw+kmV FjFzcfDcS1RGTkakuGKwULalcYMNLW7gitO0/fnmCCgw== X-Zone-Loop: 893a72aec607dea6480c80f879ab4fcedcd53e6c2117 x-campaign-type: default x-transaction-id: 5defd13e-2120-4dbf-b2ab-a7f7caa0a973 x-swg-uid: 01-2f1486f1-d81c-47e9-8cb7-5f95c3d6f325 X-Mailer: Sweego Message-ID: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf3880b0000f373@vates.tech> x-swg-bid: 1777298079.8631fc262581453bbf619ec5b2062170.19dcf3880b0000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 4/9] x86/passthrough: Extract PT_IRQ_TYPE_MSI body into pt_irq_bind_msi() Date: Mon, 27 Apr 2026 15:54:01 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2976.44099caa86af48ff.19dcf387f5c.f3342a2cfd05b8f2=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298079580 X-purgate-ID: tlsNG-4011c0/1777298096-8127B8B7-32EBBA09/0/0 X-purgate-type: clean X-purgate-size: 13956 ---=Part.2976.44099caa86af48ff.19dcf387f5c.f3342a2cfd05b8f2=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable No functional change: move the PT_IRQ_TYPE_MSI case of pt_irq_create_bind() into a new static helper pt_irq_bind_msi() taking the same gvec/gflags/gta= ble parameters=2E Restructure pt_irq_create_bind() so the MSI case delegates t= o the helper and pt_irq_dpci_setup() is called inside each case rather than shar= ed=2E Signed-off-by: Julian Vetter --- Changes in v4: - New patch - Split out as a preparatory no-functional-change step so that the interface change in patch 5 (switching pt_irq_bind_msi() from gvec + gflags to raw MSI addr + data) shows as a clean diff against an already-extracted helper, rather than being tangled with the 'case PT_IRQ_TYPE_MSI' code --- xen/drivers/passthrough/x86/hvm=2Ec | 255 ++++++++++++++++-------------- 1 file changed, 140 insertions(+), 115 deletions(-) diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index 19463c3406=2E=2Eeff1e8a79e 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -290,161 +290,186 @@ static int pt_irq_dpci_setup(struct domain *d, uns= igned int pirq, } while ( true ); } =20 -int pt_irq_create_bind( - struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) +static int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, + uint8_t gvec, uint32_t gflags, uint64_t gtabl= e, + bool unmasked) { struct hvm_irq_dpci *hvm_irq_dpci; struct hvm_pirq_dpci *pirq_dpci; struct pirq *info; - int rc, pirq =3D pt_irq_bind->machine_irq; + uint8_t dest, delivery_mode; + bool dest_mode; + int dest_vcpu_id, rc; + const struct vcpu *vcpu; =20 - if ( pirq < 0 || pirq >=3D d->nr_pirqs ) + if ( machine_irq >=3D (unsigned int)d->nr_pirqs ) return -EINVAL; =20 - rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &info); + rc =3D pt_irq_dpci_setup(d, machine_irq, &hvm_irq_dpci, &pirq_dpci, &= info); if ( rc ) return rc; =20 - switch ( pt_irq_bind->irq_type ) + if ( !(pirq_dpci->flags & HVM_IRQ_DPCI_MAPPED) ) { - case PT_IRQ_TYPE_MSI: - { - uint8_t dest, delivery_mode; - bool dest_mode; - int dest_vcpu_id; - const struct vcpu *vcpu; - uint32_t gflags =3D pt_irq_bind->u=2Emsi=2Egflags & - ~XEN_DOMCTL_VMSI_X86_UNMASKED; - - if ( !(pirq_dpci->flags & HVM_IRQ_DPCI_MAPPED) ) + pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MACH_MSI = | + HVM_IRQ_DPCI_GUEST_MSI; + pirq_dpci->gmsi=2Egvec =3D gvec; + pirq_dpci->gmsi=2Egflags =3D gflags; + /* + * 'pt_irq_bind_msi' can be called after 'pt_irq_destroy_bind'=2E + * The 'pirq_cleanup_check' which would free the structure is onl= y + * called if the event channel for the PIRQ is active=2E However + * OS-es that use event channels usually bind PIRQs to eventds + * and unbind them before calling 'pt_irq_destroy_bind' - with th= e + * result that we re-use the 'dpci' structure=2E This can be + * reproduced with unloading and loading the driver for a device= =2E + * + * As such on every 'pt_irq_bind_msi' call we MUST set it=2E + */ + pirq_dpci->dom =3D d; + /* bind after hvm_irq_dpci is setup to avoid race with irq handle= r */ + rc =3D pirq_guest_bind(d->vcpu[0], info, 0); + if ( rc =3D=3D 0 && gtable ) { - pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MACH_= MSI | - HVM_IRQ_DPCI_GUEST_MSI; - pirq_dpci->gmsi=2Egvec =3D pt_irq_bind->u=2Emsi=2Egvec; - pirq_dpci->gmsi=2Egflags =3D gflags; - /* - * 'pt_irq_create_bind' can be called after 'pt_irq_destroy_b= ind'=2E - * The 'pirq_cleanup_check' which would free the structure is= only - * called if the event channel for the PIRQ is active=2E Howe= ver - * OS-es that use event channels usually bind PIRQs to eventd= s - * and unbind them before calling 'pt_irq_destroy_bind' - wit= h the - * result that we re-use the 'dpci' structure=2E This can be - * reproduced with unloading and loading the driver for a dev= ice=2E - * - * As such on every 'pt_irq_create_bind' call we MUST set it= =2E - */ - pirq_dpci->dom =3D d; - /* bind after hvm_irq_dpci is setup to avoid race with irq ha= ndler*/ - rc =3D pirq_guest_bind(d->vcpu[0], info, 0); - if ( rc =3D=3D 0 && pt_irq_bind->u=2Emsi=2Egtable ) - { - rc =3D msixtbl_pt_register(d, info, pt_irq_bind->u=2Emsi= =2Egtable); - if ( unlikely(rc) ) - { - pirq_guest_unbind(d, info); - /* - * Between 'pirq_guest_bind' and before 'pirq_guest_u= nbind' - * an interrupt can be scheduled=2E No more of them a= re going - * to be scheduled but we must deal with the one that= may be - * in the queue=2E - */ - pt_pirq_softirq_reset(pirq_dpci); - } - } + rc =3D msixtbl_pt_register(d, info, gtable); if ( unlikely(rc) ) { - pirq_dpci->gmsi=2Egflags =3D 0; - pirq_dpci->gmsi=2Egvec =3D 0; - pirq_dpci->dom =3D NULL; - pirq_dpci->flags =3D 0; - if ( !info->evtchn ) - pirq_cleanup_check(info, d); - write_unlock(&d->event_lock); - return rc; + pirq_guest_unbind(d, info); + /* + * Between 'pirq_guest_bind' and before 'pirq_guest_unbin= d' + * an interrupt can be scheduled=2E No more of them are g= oing + * to be scheduled but we must deal with the one that may= be + * in the queue=2E + */ + pt_pirq_softirq_reset(pirq_dpci); } } - else + if ( unlikely(rc) ) { - uint32_t mask =3D HVM_IRQ_DPCI_MACH_MSI | HVM_IRQ_DPCI_GUEST_= MSI; - - if ( (pirq_dpci->flags & mask) !=3D mask ) - { - write_unlock(&d->event_lock); - return -EBUSY; - } - - /* If pirq is already mapped as vmsi, update guest data/addr= =2E */ - if ( pirq_dpci->gmsi=2Egvec !=3D pt_irq_bind->u=2Emsi=2Egvec = || - pirq_dpci->gmsi=2Egflags !=3D gflags ) - { - /* Directly clear pending EOIs before enabling new MSI in= fo=2E */ - pirq_guest_eoi(info); - - pirq_dpci->gmsi=2Egvec =3D pt_irq_bind->u=2Emsi=2Egvec; - pirq_dpci->gmsi=2Egflags =3D gflags; - } + pirq_dpci->gmsi=2Egflags =3D 0; + pirq_dpci->gmsi=2Egvec =3D 0; + pirq_dpci->dom =3D NULL; + pirq_dpci->flags =3D 0; + if ( !info->evtchn ) + pirq_cleanup_check(info, d); + write_unlock(&d->event_lock); + return rc; } - /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ - dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK); - dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM_M= ASK; - delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, - XEN_DOMCTL_VMSI_X86_DELIV_MASK); - - dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); - pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; - write_unlock(&d->event_lock); + } + else + { + uint32_t mask =3D HVM_IRQ_DPCI_MACH_MSI | HVM_IRQ_DPCI_GUEST_MSI; =20 - pirq_dpci->gmsi=2Eposted =3D false; - vcpu =3D (dest_vcpu_id >=3D 0) ? d->vcpu[dest_vcpu_id] : NULL; - if ( iommu_intpost ) + if ( (pirq_dpci->flags & mask) !=3D mask ) { - if ( delivery_mode =3D=3D dest_LowestPrio ) - vcpu =3D vector_hashing_dest(d, dest, dest_mode, - pirq_dpci->gmsi=2Egvec); - if ( vcpu ) - pirq_dpci->gmsi=2Eposted =3D true; + write_unlock(&d->event_lock); + return -EBUSY; } - if ( vcpu && is_iommu_enabled(d) ) - hvm_migrate_pirq(pirq_dpci, vcpu); =20 - /* Use interrupt posting if it is supported=2E */ - if ( iommu_intpost ) + /* If pirq is already mapped as vmsi, update guest data/addr=2E *= / + if ( pirq_dpci->gmsi=2Egvec !=3D gvec || pirq_dpci->gmsi=2Egflags= !=3D gflags ) { - rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egvec)= ; + /* Directly clear pending EOIs before enabling new MSI info= =2E */ + pirq_guest_eoi(info); =20 - if ( rc ) - { - pt_irq_destroy_bind(d, pt_irq_bind); - return rc; - } + pirq_dpci->gmsi=2Egvec =3D gvec; + pirq_dpci->gmsi=2Egflags =3D gflags; } + } + /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ + dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, XEN_DOMCTL_VMSI_X86_DEST= _ID_MASK); + dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM_MASK; + delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, + XEN_DOMCTL_VMSI_X86_DELIV_MASK); + + dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); + pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; + write_unlock(&d->event_lock); =20 - if ( pt_irq_bind->u=2Emsi=2Egflags & XEN_DOMCTL_VMSI_X86_UNMASKED= ) + pirq_dpci->gmsi=2Eposted =3D false; + vcpu =3D (dest_vcpu_id >=3D 0) ? d->vcpu[dest_vcpu_id] : NULL; + if ( iommu_intpost ) + { + if ( delivery_mode =3D=3D dest_LowestPrio ) + vcpu =3D vector_hashing_dest(d, dest, dest_mode, + pirq_dpci->gmsi=2Egvec); + if ( vcpu ) + pirq_dpci->gmsi=2Eposted =3D true; + } + if ( vcpu && is_iommu_enabled(d) ) + hvm_migrate_pirq(pirq_dpci, vcpu); + + /* Use interrupt posting if it is supported=2E */ + if ( iommu_intpost ) + { + struct xen_domctl_bind_pt_irq bind =3D { + =2Emachine_irq =3D machine_irq, + =2Eirq_type =3D PT_IRQ_TYPE_MSI, + }; + + rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egvec); + if ( rc ) { - unsigned long flags; - struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &flag= s); + pt_irq_destroy_bind(d, &bind); + return rc; + } + } =20 - if ( !desc ) - { - pt_irq_destroy_bind(d, pt_irq_bind); - return -EINVAL; - } + if ( unmasked ) + { + struct xen_domctl_bind_pt_irq bind =3D { + =2Emachine_irq =3D machine_irq, + =2Eirq_type =3D PT_IRQ_TYPE_MSI, + }; + unsigned long flags; + struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &flags); =20 - guest_mask_msi_irq(desc, false); - spin_unlock_irqrestore(&desc->lock, flags); + if ( !desc ) + { + pt_irq_destroy_bind(d, &bind); + return -EINVAL; } =20 - break; + guest_mask_msi_irq(desc, false); + spin_unlock_irqrestore(&desc->lock, flags); } =20 + return 0; +} + +int pt_irq_create_bind( + struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) +{ + int rc, pirq =3D pt_irq_bind->machine_irq; + + if ( pirq < 0 || pirq >=3D d->nr_pirqs ) + return -EINVAL; + + switch ( pt_irq_bind->irq_type ) + { + case PT_IRQ_TYPE_MSI: + return pt_irq_bind_msi(d, pirq, + pt_irq_bind->u=2Emsi=2Egvec, + pt_irq_bind->u=2Emsi=2Egflags & + ~XEN_DOMCTL_VMSI_X86_UNMASKED, + pt_irq_bind->u=2Emsi=2Egtable, + !!(pt_irq_bind->u=2Emsi=2Egflags & + XEN_DOMCTL_VMSI_X86_UNMASKED)); + case PT_IRQ_TYPE_PCI: case PT_IRQ_TYPE_MSI_TRANSLATE: { + struct hvm_irq_dpci *hvm_irq_dpci; + struct hvm_pirq_dpci *pirq_dpci; + struct pirq *info; struct dev_intx_gsi_link *digl =3D NULL; struct hvm_girq_dpci_mapping *girq =3D NULL; unsigned int guest_gsi; =20 + rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &inf= o); + if ( rc ) + return rc; + /* * Mapping GSIs for the hardware domain is different than doing i= t for * an unpriviledged guest, the hardware domain is only allowed to --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2976.44099caa86af48ff.19dcf387f5c.f3342a2cfd05b8f2=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:55:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:55:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294889.1571630 (Exim 4.92) (envelope-from ) id 1wHMQO-0001KV-VF; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=iXxqoGxWiDqr4wezd1/rHSPOjUm9gs8Ti7iAAL7JzQ4=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=KRLggbHsezbkl30Wio7c3vxBzbxTfcAT9MPRwgm5CnGTaJp4yC4UIWtfxBE3KvV2kUalsbNbh cYS6x47t7+At5S8VcRMDvPaQq10zEScgG9PH5ZkMhMr77mdjWS1OJpRpP1LAAq/+xgNzzrw46Ud vQdWnqTp/qIA9kS96qO3RYgfIh3hTtcymQB/p3mwZZxmA7bRzu50yc/Hh4iLWio9aIiM0myrHzK sct+IQsGINiuXkiD8YPJOKspmlmDkc+/p7F7moYlWhCA2j6C5LTNFEHzGunEVMwtrWR6cV6NlQh ib3UeFsxHaKUC0Vjwz0TCw7dJy1/a9R0wok2wwbEJxmA== X-Zone-Loop: 92d47e58cf816b7c30188e3e6a77384382b0c1f3b100 x-campaign-type: default x-transaction-id: 0ea4ac49-5797-492a-bcca-465b27a2a169 x-swg-uid: 01-340cdd04-0173-4aaa-b58f-8876ee026364 X-Mailer: Sweego Message-ID: <1777298080.8631fc262581453bbf619ec5b2062170.19dcf3882f5000f373@vates.tech> x-swg-bid: 1777298080.8631fc262581453bbf619ec5b2062170.19dcf3882f5000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 5/9] x86/passthrough: Introduce pt_irq_bind_msi() as canonical MSI bind path Date: Mon, 27 Apr 2026 15:54:02 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2977.62d2d69c803d43dd.19dcf3880a1.e118eb93d909cefe=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298079905 X-purgate-ID: tlsNG-4011c0/1777298098-44B678B7-A3DEA6B3/0/0 X-purgate-type: clean X-purgate-size: 16764 ---=Part.2977.62d2d69c803d43dd.19dcf3880a1.e118eb93d909cefe=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Change pt_irq_bind_msi() to accept raw MSI address and data values instead of pre-decoded gvec/gflags=2E Add msi_addr_to_gflags() to decode the destination ID and delivery attributes, including the Extended Destination ID bits from address[11:5] per Intel convention=2E Update pt_irq_create_bind() to call pt_irq_bind_msi() via the existing gvec/gflags interface so domctl-based callers continue to work=2E Signed-off-by: Julian Vetter --- Changes in v4: - As suggested by Roger replace the v3 approach (v3 patches 2+4) of extending the gflags ABI with XEN_DOMCTL_VMSI_X86_EXT_DEST_ID_MASK and XEN_DOMCTL_VMSI_X86_FULL_DEST() so callers could pass extended bits through XEN_DOMCTL_bind_pt_irq=2E pt_irq_bind_msi() now accepts raw MSI address + data and decodes the destination internally via msi_addr_to_gflags() - Replace the gmsi=2Egvec + gmsi=2Egflags fields in struct hvm_pirq_dpci with gmsi=2Eaddr + gmsi=2Edata - Replace msi_gflags() (v3 vmsi=2Ec helper that packed the extended destination bits into gflags) with msi_addr_to_gflags() which decodes the raw MSI address directly - pt_irq_create_bind() now rejects PT_IRQ_TYPE_MSI with -EOPNOTSUPP and all callers are redirected through the DM op path in patch 7 - As suggested by Roger adapt the comment in msi=2Eh in regards to the extended destination encoding since it's not part of any specification --- xen/arch/x86/hvm/vmsi=2Ec | 50 ++++++------------ xen/arch/x86/include/asm/hvm/irq=2Eh | 4 +- xen/arch/x86/include/asm/msi=2Eh | 18 ++++++- xen/drivers/passthrough/x86/hvm=2Ec | 83 ++++++++++++++++++------------ xen/include/xen/iommu=2Eh | 3 ++ 5 files changed, 86 insertions(+), 72 deletions(-) diff --git a/xen/arch/x86/hvm/vmsi=2Ec b/xen/arch/x86/hvm/vmsi=2Ec index 27b1f089e2=2E=2E2a4b97e2e1 100644 --- a/xen/arch/x86/hvm/vmsi=2Ec +++ b/xen/arch/x86/hvm/vmsi=2Ec @@ -43,6 +43,7 @@ #include #include #include +#include =20 static void vmsi_inj_irq( struct vlapic *target, @@ -107,12 +108,12 @@ int vmsi_deliver( =20 void vmsi_deliver_pirq(struct domain *d, const struct hvm_pirq_dpci *pirq= _dpci) { - uint32_t flags =3D pirq_dpci->gmsi=2Egflags; - int vector =3D pirq_dpci->gmsi=2Egvec; - uint8_t dest =3D (uint8_t)flags; - bool dest_mode =3D flags & XEN_DOMCTL_VMSI_X86_DM_MASK; - uint8_t delivery_mode =3D MASK_EXTR(flags, XEN_DOMCTL_VMSI_X86_DELIV_= MASK); - bool trig_mode =3D flags & XEN_DOMCTL_VMSI_X86_TRIG_MASK; + uint32_t dest =3D MSI_ADDR_DEST(pirq_dpci->gmsi=2Eaddr); + bool dest_mode =3D pirq_dpci->gmsi=2Eaddr & MSI_ADDR_DESTMODE_MASK; + uint8_t delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Edata, + MSI_DATA_DELIVERY_MODE_MASK); + bool trig_mode =3D pirq_dpci->gmsi=2Edata & MSI_DATA_TRIGGER_MASK; + int vector =3D pirq_dpci->gmsi=2Edata & MSI_DATA_VECTOR_MASK; =20 HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "msi: dest=3D%x dest_mode=3D%x delivery_mode=3D%x " @@ -793,27 +794,6 @@ void msix_write_completion(struct vcpu *v) } =20 #ifdef CONFIG_HAS_VPCI -static unsigned int msi_gflags(uint16_t data, uint64_t addr, bool masked) -{ - /* - * We need to use the DOMCTL constants here because the output of thi= s - * function is used as input to pt_irq_create_bind, which also takes = the - * input from the DOMCTL itself=2E - */ - return MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DEST_ID_MASK), - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK) | - MASK_INSR(MASK_EXTR(addr, MSI_ADDR_REDIRECTION_MASK), - XEN_DOMCTL_VMSI_X86_RH_MASK) | - MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DESTMODE_MASK), - XEN_DOMCTL_VMSI_X86_DM_MASK) | - MASK_INSR(MASK_EXTR(data, MSI_DATA_DELIVERY_MODE_MASK), - XEN_DOMCTL_VMSI_X86_DELIV_MASK) | - MASK_INSR(MASK_EXTR(data, MSI_DATA_TRIGGER_MASK), - XEN_DOMCTL_VMSI_X86_TRIG_MASK) | - /* NB: by default MSI vectors are bound masked=2E */ - (masked ? 0 : XEN_DOMCTL_VMSI_X86_UNMASKED); -} - static void vpci_mask_pirq(struct domain *d, int pirq, bool mask) { unsigned long flags; @@ -850,17 +830,17 @@ static int vpci_msi_update(const struct pci_dev *pde= v, uint32_t data, { uint8_t vector =3D MASK_EXTR(data, MSI_DATA_VECTOR_MASK); uint8_t vector_mask =3D 0xff >> (8 - fls(vectors) + 1); - struct xen_domctl_bind_pt_irq bind =3D { - =2Emachine_irq =3D pirq + i, - =2Eirq_type =3D PT_IRQ_TYPE_MSI, - =2Eu=2Emsi=2Egvec =3D (vector & ~vector_mask) | - ((vector + i) & vector_mask), - =2Eu=2Emsi=2Egflags =3D msi_gflags(data, address, (mask >> i)= & 1), - }; - int rc =3D pt_irq_create_bind(pdev->domain, &bind); + uint8_t gvec =3D (vector & ~vector_mask) | ((vector + i) & vector= _mask); + uint32_t msi_data =3D (data & ~MSI_DATA_VECTOR_MASK) | gvec; + int rc =3D pt_irq_bind_msi(pdev->domain, pirq + i, + address, msi_data, 0, !((mask >> i) & 1)= ); =20 if ( rc ) { + struct xen_domctl_bind_pt_irq bind =3D { + =2Eirq_type =3D PT_IRQ_TYPE_MSI, + =2Emachine_irq =3D pirq + i, + }; gdprintk(XENLOG_ERR, "%pp: failed to bind PIRQ %u: %d\n", &pdev->sbdf, pirq + i, rc); while ( bind=2Emachine_irq-- > pirq ) diff --git a/xen/arch/x86/include/asm/hvm/irq=2Eh b/xen/arch/x86/include/a= sm/hvm/irq=2Eh index 77595fb3f4=2E=2Ec50eee9996 100644 --- a/xen/arch/x86/include/asm/hvm/irq=2Eh +++ b/xen/arch/x86/include/asm/hvm/irq=2Eh @@ -120,8 +120,8 @@ struct dev_intx_gsi_link { #define HVM_IRQ_DPCI_TRANSLATE (1u << _HVM_IRQ_DPCI_TRANSLATE_SHIFT= ) =20 struct hvm_gmsi_info { - uint32_t gvec; - uint32_t gflags; + uint64_t addr; /* raw MSI address (0xfeexxxxx, includes ext dest I= D) */ + uint32_t data; /* raw MSI data (vector, delivery mode, trigger mod= e) */ int dest_vcpu_id; /* -1 :multi-dest, non-negative: dest_vcpu_id */ bool posted; /* directly deliver to guest via VT-d PI? */ }; diff --git a/xen/arch/x86/include/asm/msi=2Eh b/xen/arch/x86/include/asm/m= si=2Eh index 00059d4a3a=2E=2E93aaf20e27 100644 --- a/xen/arch/x86/include/asm/msi=2Eh +++ b/xen/arch/x86/include/asm/msi=2Eh @@ -51,8 +51,22 @@ #define MSI_ADDR_REDIRECTION_MASK (1 << MSI_ADDR_REDIRECTION_SHIFT) =20 #define MSI_ADDR_DEST_ID_SHIFT 12 -#define MSI_ADDR_DEST_ID_MASK 0x00ff000 -#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MS= I_ADDR_DEST_ID_MASK) +#define MSI_ADDR_DEST_ID_UPPER_BITS 8 +#define MSI_ADDR_DEST_ID_MASK 0x00ff000 +#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & MSI= _ADDR_DEST_ID_MASK) + +/* + * Intel convention: in physical destination mode bits 11:5 of the MSI + * address carry APIC ID bits [14:8] (the "Extended Destination ID"), + * extending the addressable range from 8 to 15 bits=2E + */ +#define MSI_ADDR_EXT_DEST_ID_MASK 0x0000fe0 + +/* Extract the combined 15-bit destination ID from an MSI address=2E */ +#define MSI_ADDR_DEST(addr) \ + (MASK_EXTR((addr), MSI_ADDR_DEST_ID_MASK) | \ + (MASK_EXTR((addr), MSI_ADDR_EXT_DEST_ID_MASK) << \ + MSI_ADDR_DEST_ID_UPPER_BITS)) =20 /* MAX fixed pages reserved for mapping MSIX tables=2E */ #define FIX_MSIX_MAX_PAGES 512 diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index eff1e8a79e=2E=2E026534530f 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -290,14 +291,15 @@ static int pt_irq_dpci_setup(struct domain *d, unsig= ned int pirq, } while ( true ); } =20 -static int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, - uint8_t gvec, uint32_t gflags, uint64_t gtabl= e, - bool unmasked) +int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, + uint64_t msi_addr, uint32_t msi_data, + uint64_t gtable, bool unmasked) { struct hvm_irq_dpci *hvm_irq_dpci; struct hvm_pirq_dpci *pirq_dpci; struct pirq *info; - uint8_t dest, delivery_mode; + uint8_t gvec, delivery_mode; + uint32_t dest; bool dest_mode; int dest_vcpu_id, rc; const struct vcpu *vcpu; @@ -313,8 +315,8 @@ static int pt_irq_bind_msi(struct domain *d, uint32_t = machine_irq, { pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MACH_MSI = | HVM_IRQ_DPCI_GUEST_MSI; - pirq_dpci->gmsi=2Egvec =3D gvec; - pirq_dpci->gmsi=2Egflags =3D gflags; + pirq_dpci->gmsi=2Eaddr =3D msi_addr; + pirq_dpci->gmsi=2Edata =3D msi_data; /* * 'pt_irq_bind_msi' can be called after 'pt_irq_destroy_bind'=2E * The 'pirq_cleanup_check' which would free the structure is onl= y @@ -346,8 +348,8 @@ static int pt_irq_bind_msi(struct domain *d, uint32_t = machine_irq, } if ( unlikely(rc) ) { - pirq_dpci->gmsi=2Egflags =3D 0; - pirq_dpci->gmsi=2Egvec =3D 0; + pirq_dpci->gmsi=2Eaddr =3D 0; + pirq_dpci->gmsi=2Edata =3D 0; pirq_dpci->dom =3D NULL; pirq_dpci->flags =3D 0; if ( !info->evtchn ) @@ -367,20 +369,22 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, } =20 /* If pirq is already mapped as vmsi, update guest data/addr=2E *= / - if ( pirq_dpci->gmsi=2Egvec !=3D gvec || pirq_dpci->gmsi=2Egflags= !=3D gflags ) + if ( pirq_dpci->gmsi=2Eaddr !=3D msi_addr || + pirq_dpci->gmsi=2Edata !=3D msi_data ) { /* Directly clear pending EOIs before enabling new MSI info= =2E */ pirq_guest_eoi(info); =20 - pirq_dpci->gmsi=2Egvec =3D gvec; - pirq_dpci->gmsi=2Egflags =3D gflags; + pirq_dpci->gmsi=2Eaddr =3D msi_addr; + pirq_dpci->gmsi=2Edata =3D msi_data; } } + /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ - dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, XEN_DOMCTL_VMSI_X86_DEST= _ID_MASK); - dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM_MASK; - delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, - XEN_DOMCTL_VMSI_X86_DELIV_MASK); + gvec =3D msi_data & MSI_DATA_VECTOR_MASK; + dest =3D MSI_ADDR_DEST(msi_addr); + dest_mode =3D msi_addr & MSI_ADDR_DESTMODE_MASK; + delivery_mode =3D MASK_EXTR(msi_data, MSI_DATA_DELIVERY_MODE_MASK); =20 dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; @@ -391,8 +395,7 @@ static int pt_irq_bind_msi(struct domain *d, uint32_t = machine_irq, if ( iommu_intpost ) { if ( delivery_mode =3D=3D dest_LowestPrio ) - vcpu =3D vector_hashing_dest(d, dest, dest_mode, - pirq_dpci->gmsi=2Egvec); + vcpu =3D vector_hashing_dest(d, dest, dest_mode, gvec); if ( vcpu ) pirq_dpci->gmsi=2Eposted =3D true; } @@ -407,7 +410,7 @@ static int pt_irq_bind_msi(struct domain *d, uint32_t = machine_irq, =2Eirq_type =3D PT_IRQ_TYPE_MSI, }; =20 - rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egvec); + rc =3D hvm_pi_update_irte(vcpu, info, gvec); if ( rc ) { pt_irq_destroy_bind(d, &bind); @@ -417,15 +420,15 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, =20 if ( unmasked ) { - struct xen_domctl_bind_pt_irq bind =3D { - =2Emachine_irq =3D machine_irq, - =2Eirq_type =3D PT_IRQ_TYPE_MSI, - }; unsigned long flags; struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &flags); =20 if ( !desc ) { + struct xen_domctl_bind_pt_irq bind =3D { + =2Emachine_irq =3D machine_irq, + =2Eirq_type =3D PT_IRQ_TYPE_MSI, + }; pt_irq_destroy_bind(d, &bind); return -EINVAL; } @@ -448,13 +451,29 @@ int pt_irq_create_bind( switch ( pt_irq_bind->irq_type ) { case PT_IRQ_TYPE_MSI: - return pt_irq_bind_msi(d, pirq, - pt_irq_bind->u=2Emsi=2Egvec, - pt_irq_bind->u=2Emsi=2Egflags & - ~XEN_DOMCTL_VMSI_X86_UNMASKED, + { + uint32_t gflags =3D pt_irq_bind->u=2Emsi=2Egflags; + uint64_t msi_addr; + uint32_t msi_data; + + msi_addr =3D MSI_ADDR_HEADER | + MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DEST_I= D_MASK), + MSI_ADDR_DEST_ID_MASK) | + (gflags & XEN_DOMCTL_VMSI_X86_RH_MASK ? + MSI_ADDR_REDIRECTION_LOWPRI : MSI_ADDR_REDIRECTION_CP= U) | + (gflags & XEN_DOMCTL_VMSI_X86_DM_MASK ? + MSI_ADDR_DESTMODE_LOGIC : MSI_ADDR_DESTMODE_PHYS); + msi_data =3D pt_irq_bind->u=2Emsi=2Egvec | + MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DELIV_= MASK), + MSI_DATA_DELIVERY_MODE_MASK) | + (gflags & XEN_DOMCTL_VMSI_X86_TRIG_MASK ? + MSI_DATA_TRIGGER_LEVEL : 0); + + return pt_irq_bind_msi(d, pt_irq_bind->machine_irq, + msi_addr, msi_data, pt_irq_bind->u=2Emsi=2Egtable, - !!(pt_irq_bind->u=2Emsi=2Egflags & - XEN_DOMCTL_VMSI_X86_UNMASKED)); + !!(gflags & XEN_DOMCTL_VMSI_X86_UNMASKED))= ; + } =20 case PT_IRQ_TYPE_PCI: case PT_IRQ_TYPE_MSI_TRANSLATE: @@ -617,7 +636,6 @@ int pt_irq_create_bind( } =20 default: - write_unlock(&d->event_lock); return -EOPNOTSUPP; } =20 @@ -858,11 +876,10 @@ static int cf_check _hvm_dpci_msi_eoi( int vector =3D (long)arg; =20 if ( (pirq_dpci->flags & HVM_IRQ_DPCI_MACH_MSI) && - (pirq_dpci->gmsi=2Egvec =3D=3D vector) ) + ((pirq_dpci->gmsi=2Edata & MSI_DATA_VECTOR_MASK) =3D=3D vector) = ) { - unsigned int dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK); - bool dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86= _DM_MASK; + unsigned int dest =3D MSI_ADDR_DEST(pirq_dpci->gmsi=2Eaddr); + bool dest_mode =3D pirq_dpci->gmsi=2Eaddr & XEN_DOMCTL_VMSI_X86_D= M_MASK; =20 if ( vlapic_match_dest(vcpu_vlapic(current), NULL, 0, dest, dest_mode) ) diff --git a/xen/include/xen/iommu=2Eh b/xen/include/xen/iommu=2Eh index 37c4a1dc82=2E=2E4672d114e3 100644 --- a/xen/include/xen/iommu=2Eh +++ b/xen/include/xen/iommu=2Eh @@ -222,6 +222,9 @@ int pt_irq_create_bind(struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind); int pt_irq_destroy_bind(struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind)= ; +int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, + uint64_t msi_addr, uint32_t msi_data, + uint64_t gtable, bool unmasked); =20 struct hvm_irq_dpci *domain_get_irq_dpci(const struct domain *d); void free_hvm_irq_dpci(struct hvm_irq_dpci *dpci); --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2977.62d2d69c803d43dd.19dcf3880a1.e118eb93d909cefe=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:55:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:55:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294892.1571638 (Exim 4.92) (envelope-from ) id 1wHMQQ-0001ZS-7i; Mon, 27 Apr 2026 13:55:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294892.1571638; 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boundary="-=Part.2978.cda3961f8565fd1b.19dcf3882da.97da3e9ea573027c=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298080474 X-purgate-ID: tlsNG-4011c0/1777298100-CE7758B7-776BBBC2/0/0 X-purgate-type: clean X-purgate-size: 7578 ---=Part.2978.cda3961f8565fd1b.19dcf3882da.97da3e9ea573027c=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Add IO_APIC_REDIR_DEST_MASK and IO_APIC_REDIR_EXT_DEST_MASK for the standard and extended destination fields of the IO-APIC RTE, and a VIOAPIC_RTE_DEST() helper that extracts the combined 15-bit destination ID=2E Extend the IO-APIC RTE save/restore struct with an ext_dest_id field so migration preserves the extended bits=2E Use the newly defined masks to extract the full 15-bit destination ID from guest MSI addresses and IO-APIC RTEs=2E In hvm_inject_msi() combine the standard bits [19:12] with the extended bits [11:5] of the MSI address into a 15-bit destination ID for LAPIC delivery=2E Widen the dest parameter of vmsi_deliver() and hvm_girq_dest_2_vcpu_id() from uint8_t to uint32_t to accommodate the larger range=2E In vioapic_deliver() read the combined 15-bit destination using the VIOAPIC_RTE_DEST() macro=2E Extend ioapic_check() to check for extended destination bits set in a domain that does not advertise XEN_HVM_CPUID_EXT_DEST_ID and refuse to restore the IO-APIC state, preventing silent interrupt misrouting after live migration=2E Signed-off-by: Julian Vetter --- Changes in v4: - Corresponds to v3 patch 3, but adapted for the new raw-addr/data storage introduced in patch 5: - In v3, vmsi_deliver_pirq() extracted the full destination from gflags via XEN_DOMCTL_VMSI_X86_FULL_DEST(), and msi_gflags() packed the extended address bits into gflags - In v4 both helpers are gone=2E vmsi_deliver_pirq() reads pirq_dpci->gmsi=2Eaddr and pirq_dpci->gmsi=2Edata directly using the standard MSI masks - Moved the IO-APIC masks and VIOAPIC_RTE_DEST() helper (previously in v3 patch 2) into this patch - Added ioapic_check() ext destination safety check (refusing migration with ext_dest_id bits set when XEN_HVM_CPUID_EXT_DEST_ID is not advertised) --- xen/arch/x86/hvm/irq=2Ec | 9 ++++++++- xen/arch/x86/hvm/vioapic=2Ec | 2 +- xen/arch/x86/hvm/vmsi=2Ec | 4 ++-- xen/arch/x86/include/asm/hvm/hvm=2Eh | 4 ++-- xen/arch/x86/include/asm/hvm/vioapic=2Eh | 12 ++++++++++++ xen/include/public/arch-x86/hvm/save=2Eh | 4 +++- 6 files changed, 28 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/hvm/irq=2Ec b/xen/arch/x86/hvm/irq=2Ec index 5f64361113=2E=2Eb43adf8b96 100644 --- a/xen/arch/x86/hvm/irq=2Ec +++ b/xen/arch/x86/hvm/irq=2Ec @@ -374,7 +374,14 @@ int hvm_set_pci_link_route(struct domain *d, u8 link,= u8 isa_irq) int hvm_inject_msi(struct domain *d, uint64_t addr, uint32_t data) { uint32_t tmp =3D (uint32_t) addr; - uint8_t dest =3D (tmp & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_S= HIFT; + /* + * Standard MSI destination address bits 19:12 carry the 8-bit APIC I= D=2E + * When XEN_HVM_CPUID_EXT_DEST_ID is enabled, bits 11:5 carry APIC ID= bits + * [14:8], extending the addressable range to 15 bits=2E Guests that = do not + * use extended IDs leave these bits at zero, so the combined extract= ion is + * safe regardless=2E + */ + uint32_t dest =3D MSI_ADDR_DEST(tmp); uint8_t dest_mode =3D !!(tmp & MSI_ADDR_DESTMODE_MASK); uint8_t delivery_mode =3D (data & MSI_DATA_DELIVERY_MODE_MASK) >> MSI_DATA_DELIVERY_MODE_SHIFT; diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec index 43fb165f84=2E=2E527cc770b7 100644 --- a/xen/arch/x86/hvm/vioapic=2Ec +++ b/xen/arch/x86/hvm/vioapic=2Ec @@ -411,7 +411,7 @@ static void ioapic_inj_irq( =20 static void vioapic_deliver(struct hvm_vioapic *vioapic, unsigned int pin= ) { - uint16_t dest =3D vioapic->redirtbl[pin]=2Efields=2Edest_id; + uint32_t dest =3D VIOAPIC_RTE_DEST(vioapic->redirtbl[pin]=2Ebits); uint8_t dest_mode =3D vioapic->redirtbl[pin]=2Efields=2Edest_mode; uint8_t delivery_mode =3D vioapic->redirtbl[pin]=2Efields=2Edelivery_= mode; uint8_t vector =3D vioapic->redirtbl[pin]=2Efields=2Evector; diff --git a/xen/arch/x86/hvm/vmsi=2Ec b/xen/arch/x86/hvm/vmsi=2Ec index 2a4b97e2e1=2E=2E7b338c4ddc 100644 --- a/xen/arch/x86/hvm/vmsi=2Ec +++ b/xen/arch/x86/hvm/vmsi=2Ec @@ -67,7 +67,7 @@ static void vmsi_inj_irq( =20 int vmsi_deliver( struct domain *d, int vector, - uint8_t dest, uint8_t dest_mode, + uint32_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t trig_mode) { struct vlapic *target; @@ -126,7 +126,7 @@ void vmsi_deliver_pirq(struct domain *d, const struct = hvm_pirq_dpci *pirq_dpci) } =20 /* Return value, -1 : multi-dests, non-negative value: dest_vcpu_id */ -int hvm_girq_dest_2_vcpu_id(struct domain *d, uint8_t dest, uint8_t dest_= mode) +int hvm_girq_dest_2_vcpu_id(struct domain *d, uint32_t dest, uint8_t dest= _mode) { int dest_vcpu_id =3D -1, w =3D 0; struct vcpu *v; diff --git a/xen/arch/x86/include/asm/hvm/hvm=2Eh b/xen/arch/x86/include/a= sm/hvm/hvm=2Eh index e7c1364802=2E=2E884dd44c81 100644 --- a/xen/arch/x86/include/asm/hvm/hvm=2Eh +++ b/xen/arch/x86/include/asm/hvm/hvm=2Eh @@ -294,11 +294,11 @@ uint64_t hvm_get_guest_time_fixed(const struct vcpu = *v, uint64_t at_tsc); =20 int vmsi_deliver( struct domain *d, int vector, - uint8_t dest, uint8_t dest_mode, + uint32_t dest, uint8_t dest_mode, uint8_t delivery_mode, uint8_t trig_mode); struct hvm_pirq_dpci; void vmsi_deliver_pirq(struct domain *d, const struct hvm_pirq_dpci *pirq= _dpci); -int hvm_girq_dest_2_vcpu_id(struct domain *d, uint8_t dest, uint8_t dest_= mode); +int hvm_girq_dest_2_vcpu_id(struct domain *d, uint32_t dest, uint8_t dest= _mode); =20 enum hvm_intblk hvm_interrupt_blocked(struct vcpu *v, struct hvm_intack intack); diff --git a/xen/arch/x86/include/asm/hvm/vioapic=2Eh b/xen/arch/x86/inclu= de/asm/hvm/vioapic=2Eh index 68af6dce79=2E=2E4499208bad 100644 --- a/xen/arch/x86/include/asm/hvm/vioapic=2Eh +++ b/xen/arch/x86/include/asm/hvm/vioapic=2Eh @@ -32,6 +32,18 @@ #define VIOAPIC_EDGE_TRIG 0 #define VIOAPIC_LEVEL_TRIG 1 =20 +/* + * Extract the destination ID from a 64-bit IO-APIC RTE, including the + * extended bits (55:49) used when XEN_HVM_CPUID_EXT_DEST_ID is advertise= d=2E + */ +#define IO_APIC_REDIR_DEST_MASK (0xffULL << 56) +#define IO_APIC_REDIR_EXT_DEST_MASK (0x7fULL << 49) + +#define VIOAPIC_RTE_DEST(rte) \ + (MASK_EXTR((rte), IO_APIC_REDIR_DEST_MASK) | \ + (MASK_EXTR((rte), IO_APIC_REDIR_EXT_DEST_MASK) << \ + MSI_ADDR_DEST_ID_UPPER_BITS)) + #define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000U #define VIOAPIC_MEM_LENGTH 0x100 =20 diff --git a/xen/include/public/arch-x86/hvm/save=2Eh b/xen/include/public= /arch-x86/hvm/save=2Eh index 9c4bfc7ebd=2E=2E483097d940 100644 --- a/xen/include/public/arch-x86/hvm/save=2Eh +++ b/xen/include/public/arch-x86/hvm/save=2Eh @@ -359,7 +359,9 @@ union vioapic_redir_entry uint8_t trig_mode:1; uint8_t mask:1; uint8_t reserve:7; - uint8_t reserved[4]; + uint8_t reserved[3]; + uint8_t reserved2:1; + uint8_t ext_dest_id:7; uint8_t dest_id; } fields; }; --=20 2=2E53=2E0 -- Julian Vetter | Vates Hypervisor & Kernel Developer XCP-ng & Xen Orch= estra - Vates solutions web: https://vates=2Etech ---=Part.2978.cda3961f8565fd1b.19dcf3882da.97da3e9ea573027c=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 13:55:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 13:55:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1294894.1571648 (Exim 4.92) (envelope-from ) id 1wHMQS-0001sW-KS; Mon, 27 Apr 2026 13:55:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1294894.1571648; Mon, 27 Apr 2026 13:55:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHMQS-0001sF-GV; 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Mon, 27 Apr 2026 13:54:41 +0000 Received: from julian.home (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: julian.vetter@vates.tech) by mail2.vates.fr (Postfix) with ESMTPSA id 8F2F687780; Mon, 27 Apr 2026 15:54:40 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=fb9qQ4Oy3R3zTDsEr6x8vu/WfuHkFi3ghUo/wdwnt1Y=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=IqwssKnDVxCJpbbQKCAEJjw4WT4LRnOG6hBMv78r7DaF+EwglVun2Z4rVGSyinJbW9H5LWfIN u2Mp05URK1ubnDHLmDz+PU39UuJZE1jkBsUFOqsVOV/Jjozz2F06FsZHdlPhHBsVrJ5a2Hl7Teh Yj8Dm2SWQtBTdhVhz44cBS3AlMg5fjYXDQJb6w9za/OXGYkHLPGfqTTdAcde/Lw2FEQTUMekmI4 X5p+koV1STvyieat9302NP3R6RL9OMvZlB2GGqkKTwmBPWEaj/ePhzrDqGP06NQreObh1oXcTDt zBHHvA51gUGra5t0nu8DKBBaG+vePt+LbJrELn+vNClg== X-Zone-Loop: 336f26e275b72a81053cef767e6ae18783a3e15c6e95 x-campaign-type: default x-transaction-id: 7c916762-bf9c-427c-8786-b205dece7fff x-swg-uid: 01-04adf360-3bb4-4464-8ed0-3dde4819b018 X-Mailer: Sweego Message-ID: <1777298081.8631fc262581453bbf619ec5b2062170.19dcf388597000f373@vates.tech> x-swg-bid: 1777298081.8631fc262581453bbf619ec5b2062170.19dcf388597000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 7/9] x86/dmop: Add XEN_DMOP_{bind,unbind}_pt_msi_irq DM ops Date: Mon, 27 Apr 2026 15:54:04 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2979.83d4fb820ba3c81.19dcf38841e.d33788981f0c79f2=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298080799 X-purgate-ID: tlsNG-4011c0/1777298102-469768B7-12D4CAB3/0/0 X-purgate-type: clean X-purgate-size: 16262 ---=Part.2979.83d4fb820ba3c81.19dcf38841e.d33788981f0c79f2=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Add two DM ops for MSI passthrough IRQs=2E These new DM ops take the raw MSI address and data fields rather than pre-decoded gflags values=2E Xen decodes the destination ID via msi_addr_to_gflags(), including any extended destination bits in address[11:5]=2E This means the device model does not need to understand the extended destination ID encoding, and simply forwards the MSI address it observes from the guest=2E With these DM ops in place, redirect xc_domain_update_msi_irq() and xc_domain_unbind_msi_irq() in libxenctrl to use xendevicemodel_bind_pt_msi_irq() / xendevicemodel_unbind_pt_msi_irq() via xch->dmod=2E The gflags/gvec arguments are translated to the raw MSI address and data words at the libxc level using the standard x86 MSI address format=2E Reject the PT_IRQ_TYPE_MSI sub-case in XEN_DOMCTL_bind_pt_irq and XEN_DOMCTL_unbind_pt_irq: all callers now go through the DM op path, so the domctl sub-case is fully obsolete=2E Signed-off-by: Julian Vetter --- Changes in v4: - Corresponds to v3 patch 5, but with feedback from Jan - Redirect xc_domain_{update,unbind}_msi_irq() in libxenctrl to call xendevicemodel_{un}bind_pt_msi_irq() via xch->dmod, translating the existing gflags/gvec arguments to raw MSI address and data in libxc - As suggested by Jan, reject the PT_IRQ_TYPE_MSI sub-case in XEN_DOMCTL_{bind,unbind}_pt_irq with -EOPNOTSUPP -> All callers now go through the DM op path, making the domctl sub-case fully obsolete - Added the xlat=2Elst entry for dm_op_unbind_pt_msi_irq (v3 added only th= e bind entry) --- tools/include/xendevicemodel=2Eh | 31 ++++++++++++++ tools/libs/ctrl/xc_domain=2Ec | 52 +++++++++++------------ tools/libs/devicemodel/core=2Ec | 38 +++++++++++++++++ xen/arch/x86/domctl=2Ec | 10 ++++- xen/arch/x86/hvm/dm=2Ec | 68 +++++++++++++++++++++++++++++++ xen/drivers/passthrough/x86/hvm=2Ec | 1 - xen/include/public/hvm/dm_op=2Eh | 37 +++++++++++++++++ xen/include/xlat=2Elst | 2 + 8 files changed, 208 insertions(+), 31 deletions(-) diff --git a/tools/include/xendevicemodel=2Eh b/tools/include/xendevicemod= el=2Eh index 227e7fd810=2E=2Ef15b35fa33 100644 --- a/tools/include/xendevicemodel=2Eh +++ b/tools/include/xendevicemodel=2Eh @@ -375,6 +375,37 @@ int xendevicemodel_nr_vcpus( */ int xendevicemodel_restrict(xendevicemodel_handle *dmod, domid_t domid); =20 +/** + * This function binds a passthrough physical IRQ to a guest MSI vector + * using raw MSI address/data fields=2E Unlike XEN_DOMCTL_bind_pt_irq, + * this interface supports extended (15-bit) destination IDs by having + * Xen decode the MSI address internally=2E + * + * @parm dmod a handle to an open devicemodel interface=2E + * @parm domid the domain id to be serviced=2E + * @parm machine_irq the physical IRQ number (pirq)=2E + * @parm msi_addr the MSI address (includes ext=2E dest=2E ID bits [11:5]= )=2E + * @parm msi_data the MSI data word (bits [7:0] are the guest vector)=2E + * @parm gtable the MSI-X table base GFN, or 0 for plain MSI=2E + * @parm unmasked if non-zero, leave the IRQ unmasked after binding=2E + * @return 0 on success, -1 on failure=2E + */ +int xendevicemodel_bind_pt_msi_irq( + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq, + uint64_t msi_addr, uint32_t msi_data, uint64_t gtable, int unmasked); + +/** + * This function unbinds a passthrough physical IRQ previously bound + * with xendevicemodel_bind_pt_msi_irq=2E + * + * @parm dmod a handle to an open devicemodel interface=2E + * @parm domid the domain id to be serviced=2E + * @parm machine_irq the physical IRQ number (pirq)=2E + * @return 0 on success, -1 on failure=2E + */ +int xendevicemodel_unbind_pt_msi_irq( + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq); + #endif /* XENDEVICEMODEL_H */ =20 /* diff --git a/tools/libs/ctrl/xc_domain=2Ec b/tools/libs/ctrl/xc_domain=2Ec index 01c0669c88=2E=2E7e3b7a0dc6 100644 --- a/tools/libs/ctrl/xc_domain=2Ec +++ b/tools/libs/ctrl/xc_domain=2Ec @@ -1677,6 +1677,21 @@ int xc_deassign_dt_device( =20 =20 =20 +static void xc_msi_gflags_to_addr_data(uint32_t gvec, uint32_t gflags, + uint64_t *msi_addr, uint32_t *msi= _data) +{ + *msi_addr =3D 0xfee00000U | + ((uint64_t)((gflags & XEN_DOMCTL_VMSI_X86_DEST_ID_MASK) << 12)) | + (gflags & XEN_DOMCTL_VMSI_X86_RH_MASK ? (1U << 3) : 0) | + (gflags & XEN_DOMCTL_VMSI_X86_DM_MASK ? (1U << 2) : 0); + + *msi_data =3D (gvec & 0xff) | + (uint32_t)(((gflags & XEN_DOMCTL_VMSI_X86_DELIV_MASK) >> + (/* shift of XEN_DOMCTL_VMSI_X86_DELIV_MASK */ 12 - + /* MSI data delivery shift */ 8))) | + (gflags & XEN_DOMCTL_VMSI_X86_TRIG_MASK ? (1U << 15) : 0); +} + int xc_domain_update_msi_irq( xc_interface *xch, uint32_t domid, @@ -1685,22 +1700,15 @@ int xc_domain_update_msi_irq( uint32_t gflags, uint64_t gtable) { - int rc; - struct xen_domctl_bind_pt_irq *bind; - struct xen_domctl domctl =3D {}; - - domctl=2Ecmd =3D XEN_DOMCTL_bind_pt_irq; - domctl=2Edomain =3D domid; + uint64_t msi_addr; + uint32_t msi_data; + int unmasked =3D !!(gflags & XEN_DOMCTL_VMSI_X86_UNMASKED); =20 - bind =3D &(domctl=2Eu=2Ebind_pt_irq); - bind->irq_type =3D PT_IRQ_TYPE_MSI; - bind->machine_irq =3D pirq; - bind->u=2Emsi=2Egvec =3D gvec; - bind->u=2Emsi=2Egflags =3D gflags; - bind->u=2Emsi=2Egtable =3D gtable; + xc_msi_gflags_to_addr_data(gvec, gflags, &msi_addr, &msi_data); =20 - rc =3D do_domctl(xch, &domctl); - return rc; + return xendevicemodel_bind_pt_msi_irq(xch->dmod, domid, pirq, + msi_addr, msi_data, gtable, + unmasked); } =20 int xc_domain_unbind_msi_irq( @@ -1710,21 +1718,7 @@ int xc_domain_unbind_msi_irq( uint32_t pirq, uint32_t gflags) { - int rc; - struct xen_domctl_bind_pt_irq *bind; - struct xen_domctl domctl =3D {}; - - domctl=2Ecmd =3D XEN_DOMCTL_unbind_pt_irq; - domctl=2Edomain =3D domid; - - bind =3D &(domctl=2Eu=2Ebind_pt_irq); - bind->irq_type =3D PT_IRQ_TYPE_MSI; - bind->machine_irq =3D pirq; - bind->u=2Emsi=2Egvec =3D gvec; - bind->u=2Emsi=2Egflags =3D gflags; - - rc =3D do_domctl(xch, &domctl); - return rc; + return xendevicemodel_unbind_pt_msi_irq(xch->dmod, domid, pirq); } =20 /* Pass-through: binds machine irq to guests irq */ diff --git a/tools/libs/devicemodel/core=2Ec b/tools/libs/devicemodel/core= =2Ec index 8e619eeb0a=2E=2Eadf2c41a96 100644 --- a/tools/libs/devicemodel/core=2Ec +++ b/tools/libs/devicemodel/core=2Ec @@ -645,6 +645,44 @@ int xendevicemodel_nr_vcpus( return 0; } =20 +int xendevicemodel_bind_pt_msi_irq( + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq, + uint64_t msi_addr, uint32_t msi_data, uint64_t gtable, int unmasked) +{ + struct xen_dm_op op; + struct xen_dm_op_bind_pt_msi_irq *data; + + memset(&op, 0, sizeof(op)); + + op=2Eop =3D XEN_DMOP_bind_pt_msi_irq; + data =3D &op=2Eu=2Ebind_pt_msi_irq; + + data->machine_irq =3D machine_irq; + data->data =3D msi_data; + data->addr =3D msi_addr; + data->gtable =3D gtable; + if ( unmasked ) + data->flags |=3D XEN_DMOP_MSI_FLAG_UNMASKED; + + return xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); +} + +int xendevicemodel_unbind_pt_msi_irq( + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq) +{ + struct xen_dm_op op; + struct xen_dm_op_unbind_pt_msi_irq *data; + + memset(&op, 0, sizeof(op)); + + op=2Eop =3D XEN_DMOP_unbind_pt_msi_irq; + data =3D &op=2Eu=2Eunbind_pt_msi_irq; + + data->machine_irq =3D machine_irq; + + return xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); +} + int xendevicemodel_restrict(xendevicemodel_handle *dmod, domid_t domid) { return osdep_xendevicemodel_restrict(dmod, domid); diff --git a/xen/arch/x86/domctl=2Ec b/xen/arch/x86/domctl=2Ec index bfbc35c08b=2E=2Ed80a33fe40 100644 --- a/xen/arch/x86/domctl=2Ec +++ b/xen/arch/x86/domctl=2Ec @@ -574,6 +574,14 @@ long arch_do_domctl( if ( !is_hvm_domain(d) ) break; =20 + /* + * PT_IRQ_TYPE_MSI is obsoleted by XEN_DMOP_bind_pt_msi_irq, whic= h + * passes raw MSI address/data so Xen can decode extended destina= tion + * ID bits=2E Device models must use the DM op path instead=2E + */ + if ( bind->irq_type =3D=3D PT_IRQ_TYPE_MSI ) + break; + ret =3D xsm_bind_pt_irq(XSM_HOOK, d, bind); if ( ret ) break; @@ -602,7 +610,7 @@ long arch_do_domctl( int irq =3D domain_pirq_to_irq(d, bind->machine_irq); =20 ret =3D -EINVAL; - if ( !is_hvm_domain(d) ) + if ( !is_hvm_domain(d) || bind->irq_type =3D=3D PT_IRQ_TYPE_MSI ) break; =20 ret =3D -EPERM; diff --git a/xen/arch/x86/hvm/dm=2Ec b/xen/arch/x86/hvm/dm=2Ec index 3b53471af0=2E=2Eac70cb6405 100644 --- a/xen/arch/x86/hvm/dm=2Ec +++ b/xen/arch/x86/hvm/dm=2Ec @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -350,6 +352,8 @@ int dm_op(const struct dmop_args *op_args) [XEN_DMOP_relocate_memory] =3D sizeof(struct xen= _dm_op_relocate_memory), [XEN_DMOP_pin_memory_cacheattr] =3D sizeof(struct xen= _dm_op_pin_memory_cacheattr), [XEN_DMOP_nr_vcpus] =3D sizeof(struct xen= _dm_op_nr_vcpus), + [XEN_DMOP_bind_pt_msi_irq] =3D sizeof(struct xen= _dm_op_bind_pt_msi_irq), + [XEN_DMOP_unbind_pt_msi_irq] =3D sizeof(struct xen= _dm_op_unbind_pt_msi_irq), }; =20 rc =3D rcu_lock_remote_domain_by_id(op_args->domid, &d); @@ -607,6 +611,68 @@ int dm_op(const struct dmop_args *op_args) break; } =20 + case XEN_DMOP_bind_pt_msi_irq: + { + const struct xen_dm_op_bind_pt_msi_irq *data =3D + &op=2Eu=2Ebind_pt_msi_irq; + int irq; + + rc =3D -EINVAL; + if ( data->pad || (data->flags & ~XEN_DMOP_MSI_FLAG_UNMASKED) ) + break; + + irq =3D domain_pirq_to_irq(d, data->machine_irq); + + rc =3D -EPERM; + if ( irq <=3D 0 || !irq_access_permitted(current->domain, irq) ) + break; + + rc =3D -ESRCH; + if ( is_iommu_enabled(d) ) + { + read_lock(&d->pci_lock); + rc =3D pt_irq_bind_msi(d, data->machine_irq, data->addr, data= ->data, + data->gtable, + !!(data->flags & XEN_DMOP_MSI_FLAG_UNMAS= KED)); + read_unlock(&d->pci_lock); + } + if ( rc < 0 ) + printk(XENLOG_G_ERR + "XEN_DMOP_bind_pt_msi_irq: pt_irq_bind_msi failed (%ld= ) for %pd\n", + rc, d); + break; + } + + case XEN_DMOP_unbind_pt_msi_irq: + { + const struct xen_dm_op_unbind_pt_msi_irq *data =3D + &op=2Eu=2Eunbind_pt_msi_irq; + struct xen_domctl_bind_pt_irq bind =3D { + =2Emachine_irq =3D data->machine_irq, + =2Eirq_type =3D PT_IRQ_TYPE_MSI, + }; + int irq; + + irq =3D domain_pirq_to_irq(d, bind=2Emachine_irq); + + rc =3D -EPERM; + if ( irq <=3D 0 || !irq_access_permitted(current->domain, irq) ) + break; + + rc =3D -ESRCH; + if ( is_iommu_enabled(d) ) + { + read_lock(&d->pci_lock); + rc =3D pt_irq_destroy_bind(d, &bind); + read_unlock(&d->pci_lock); + } + if ( rc < 0 ) + printk(XENLOG_G_ERR + "XEN_DMOP_unbind_pt_msi_irq: pt_irq_destroy_bind faile= d (%ld) for %pd\n", + rc, d); + break; + } + default: rc =3D ioreq_server_dm_op(&op, d, &const_op); break; @@ -643,6 +709,8 @@ CHECK_dm_op_remote_shutdown; CHECK_dm_op_relocate_memory; CHECK_dm_op_pin_memory_cacheattr; CHECK_dm_op_nr_vcpus; +CHECK_dm_op_bind_pt_msi_irq; +CHECK_dm_op_unbind_pt_msi_irq; =20 int compat_dm_op( domid_t domid, unsigned int nr_bufs, XEN_GUEST_HANDLE_PARAM(void) buf= s) diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index 026534530f=2E=2E6fb4f8b7dc 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/xen/include/public/hvm/dm_op=2Eh b/xen/include/public/hvm/dm_= op=2Eh index 2bf0fdc1ae=2E=2E43571b7713 100644 --- a/xen/include/public/hvm/dm_op=2Eh +++ b/xen/include/public/hvm/dm_op=2Eh @@ -444,6 +444,41 @@ struct xen_dm_op_nr_vcpus { }; typedef struct xen_dm_op_nr_vcpus xen_dm_op_nr_vcpus_t; =20 +#define XEN_DMOP_bind_pt_msi_irq 21 +#define XEN_DMOP_unbind_pt_msi_irq 22 + +struct xen_dm_op_bind_pt_msi_irq { + /* IN - physical IRQ (pirq) */ + uint32_t machine_irq; + /* IN - MSI data word (bits [7:0] are the guest vector) */ + uint32_t data; + /* IN - flags */ + uint32_t flags; +#define XEN_DMOP_MSI_FLAG_UNMASKED (1u << 0) + uint32_t pad; + /* IN - MSI address (includes extended destination ID in bits [11:5])= */ + uint64_aligned_t addr; + /* IN - MSI-X table base GFN, 0 for plain MSI */ + uint64_aligned_t gtable; +}; + +typedef struct xen_dm_op_bind_pt_msi_irq xen_dm_op_bind_pt_msi_irq_t; + +struct xen_dm_op_unbind_pt_msi_irq { + /* IN - physical IRQ (pirq) */ + uint32_t machine_irq; +}; +typedef struct xen_dm_op_unbind_pt_msi_irq xen_dm_op_unbind_pt_msi_irq_t; + +/* + * XEN_DMOP_enable_ext_dest_id: Signal to Xen that this device model will= use + * XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings, passing raw= MSI + * address/data fields=2E Once called, Xen will advertise + * XEN_HVM_CPUID_EXT_DEST_ID to the guest=2E Must be called before the gu= est + * starts=2E + */ +#define XEN_DMOP_enable_ext_dest_id 23 + struct xen_dm_op { uint32_t op; uint32_t pad; @@ -468,6 +503,8 @@ struct xen_dm_op { xen_dm_op_relocate_memory_t relocate_memory; xen_dm_op_pin_memory_cacheattr_t pin_memory_cacheattr; xen_dm_op_nr_vcpus_t nr_vcpus; + xen_dm_op_bind_pt_msi_irq_t bind_pt_msi_irq; + xen_dm_op_unbind_pt_msi_irq_t unbind_pt_msi_irq; } u; }; =20 diff --git a/xen/include/xlat=2Elst b/xen/include/xlat=2Elst index 9d08dcc4bb=2E=2E6dc5f5796a 100644 --- a/xen/include/xlat=2Elst +++ b/xen/include/xlat=2Elst @@ -98,6 +98,7 @@ ? grant_entry_v2 grant_table=2Eh =20 ! dm_op_buf hvm/dm_op=2Eh +? dm_op_bind_pt_msi_irq hvm/dm_op=2Eh ? dm_op_create_ioreq_server hvm/dm_op=2Eh ? dm_op_destroy_ioreq_server hvm/dm_op=2Eh ? dm_op_get_ioreq_server_info hvm/dm_op=2Eh @@ -116,6 +117,7 @@ ? dm_op_set_pci_intx_level hvm/dm_op=2Eh ? dm_op_set_pci_link_route hvm/dm_op=2Eh ? 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x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 8/9] hvm/ioreq: Negotiate extended destination ID support per ioreq server Date: Mon, 27 Apr 2026 15:54:05 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.297a.584af6cfdad57c37.19dcf388578.dac24e8c4e346718=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298081144 X-purgate-ID: tlsNG-4011c0/1777298105-47D788B7-61B6E7A8/0/0 X-purgate-type: clean X-purgate-size: 19021 ---=Part.297a.584af6cfdad57c37.19dcf388578.dac24e8c4e346718=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Add a per-server capability flag in XEN_DMOP_create_ioreq_server to signal extended destination ID support=2E Repurpose the first byte of the existing pad[3] as a flags field, and define XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID (bit 0) for a server to signal it will use XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings=2E Track the flag in struct ioreq_server ext_dest_id=2E hvm_ext_dest_id_enabled() returns true only if all registered ioreq servers have opted in and at least one server is present=2E A single server without the flag is sufficient to suppress the feature=2E Lock the feature at domain creation time: arch_domain_creation_finished() computes the levelled result into struct hvm_domain=2Eext_dest_id using OR to preserve any value previously restored from an HVM save record=2E After creation_finished, arch_ioreq_server_create_check() rejects new servers that lack XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID if the feature was already advertised to the guest=2E Persist the locked state in a new HVM_SAVE_TYPE(EXT_DEST_ID) record so that migration preserves the guest-visible CPUID bit independently of when the device model re-registers its ioreq servers on the destination host=2E On restore, ioapic_check() uses d->arch=2Ehvm=2Eext_dest_id (restored from the EXT_DEST_ID record) rather than the per-server dynamic check, since the DM has not yet re-registered its servers at that point=2E Update xendevicemodel_create_ioreq_server() in libxendevicemodel to accept the new flags parameter, remove xendevicemodel_enable_ext_dest_id(), and fix the xc_hvm_create_ioreq_server() compat wrapper to pass zero flags=2E Signed-off-by: Julian Vetter --- Changes in v4: - As suggested by Roger, replaced XEN_DMOP_enable_ext_dest_id (v3 patch 6), a separate DM op the device model had to call before starting vCPUs, with a flags byte repurposed from the existing pad[3] field of xen_dm_op_create_ioreq_server - New XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID flag (bit 0) lets each ioreq server signal support at registration time - As suggested by Roger level the feature across all ioreq servers=2E XEN_HVM_CPUID_EXT_DEST_ID is only advertised when every server registered before arch_domain_creation_finished() sets the flag=2E A single server without the flag suppresses the feature for the whole domain! - Lock the levelled result at domain creation time and enforce it for servers registered afterwards, preventing a late opt-out from breaking guests that already see the feature in CPUID - Persist the locked flag via HVM_SAVE_TYPE(EXT_DEST_ID) so that live migration preserves the guest-visible CPUID bit independently of when the device model registers its ioreq servers on the destination host --- tools/include/xendevicemodel=2Eh | 3 +- tools/libs/ctrl/xc_devicemodel_compat=2Ec | 2 +- tools/libs/devicemodel/core=2Ec | 3 +- xen/arch/arm/ioreq=2Ec | 5 ++++ xen/arch/x86/domain=2Ec | 10 +++++++ xen/arch/x86/hvm/ioreq=2Ec | 37 +++++++++++++++++++++++++ xen/arch/x86/hvm/vioapic=2Ec | 20 +++++++++++++ xen/arch/x86/include/asm/hvm/domain=2Eh | 9 ++++++ xen/common/ioreq=2Ec | 13 +++++++-- xen/drivers/passthrough/x86/hvm=2Ec | 13 +++++++++ xen/include/public/arch-x86/hvm/save=2Eh | 17 +++++++++++- xen/include/public/hvm/dm_op=2Eh | 16 +++++++++-- xen/include/xen/ioreq=2Eh | 27 ++++++++++++++++++ 13 files changed, 165 insertions(+), 10 deletions(-) diff --git a/tools/include/xendevicemodel=2Eh b/tools/include/xendevicemod= el=2Eh index f15b35fa33=2E=2Ebc6764bd58 100644 --- a/tools/include/xendevicemodel=2Eh +++ b/tools/include/xendevicemodel=2Eh @@ -44,12 +44,13 @@ int xendevicemodel_close(xendevicemodel_handle *dmod); * @parm domid the domain id to be serviced * @parm handle_bufioreq how should the IOREQ Server handle buffered * requests (HVM_IOREQSRV_BUFIOREQ_*)? + * @parm flags bitmask of XEN_DMOP_IOREQ_SERVER_* capability flags=2E * @parm id pointer to an ioservid_t to receive the IOREQ Server id=2E * @return 0 on success, -1 on failure=2E */ int xendevicemodel_create_ioreq_server( xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq, - ioservid_t *id); + uint8_t flags, ioservid_t *id); =20 /** * This function retrieves the necessary information to allow an diff --git a/tools/libs/ctrl/xc_devicemodel_compat=2Ec b/tools/libs/ctrl/x= c_devicemodel_compat=2Ec index a46011cd17=2E=2E91366e250c 100644 --- a/tools/libs/ctrl/xc_devicemodel_compat=2Ec +++ b/tools/libs/ctrl/xc_devicemodel_compat=2Ec @@ -11,7 +11,7 @@ int xc_hvm_create_ioreq_server( ioservid_t *id) { return xendevicemodel_create_ioreq_server(xch->dmod, domid, - handle_bufioreq, id); + handle_bufioreq, 0, id); } =20 int xc_hvm_get_ioreq_server_info( diff --git a/tools/libs/devicemodel/core=2Ec b/tools/libs/devicemodel/core= =2Ec index adf2c41a96=2E=2E49b9bf8a13 100644 --- a/tools/libs/devicemodel/core=2Ec +++ b/tools/libs/devicemodel/core=2Ec @@ -167,7 +167,7 @@ static int xendevicemodel_op( =20 int xendevicemodel_create_ioreq_server( xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq, - ioservid_t *id) + uint8_t flags, ioservid_t *id) { struct xen_dm_op op; struct xen_dm_op_create_ioreq_server *data; @@ -179,6 +179,7 @@ int xendevicemodel_create_ioreq_server( data =3D &op=2Eu=2Ecreate_ioreq_server; =20 data->handle_bufioreq =3D handle_bufioreq; + data->flags =3D flags; =20 rc =3D xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); if (rc) diff --git a/xen/arch/arm/ioreq=2Ec b/xen/arch/arm/ioreq=2Ec index b4211f0159=2E=2Ed45228717a 100644 --- a/xen/arch/arm/ioreq=2Ec +++ b/xen/arch/arm/ioreq=2Ec @@ -201,6 +201,11 @@ void arch_ioreq_domain_init(struct domain *d) { } =20 +int arch_ioreq_server_create_check(const struct domain *d, uint8_t flags) +{ + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/x86/domain=2Ec b/xen/arch/x86/domain=2Ec index 1d458f1372=2E=2E68ff315460 100644 --- a/xen/arch/x86/domain=2Ec +++ b/xen/arch/x86/domain=2Ec @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1106,7 +1107,16 @@ int arch_domain_soft_reset(struct domain *d) void arch_domain_creation_finished(struct domain *d) { if ( is_hvm_domain(d) ) + { + /* + * Lock the extended destination ID state=2E OR preserves any val= ue + * already restored from an HVM save record (migration path)=2E F= or a + * fresh domain, ext_dest_id starts false and the dynamic check + * supplies the levelled result across all registered ioreq serve= rs=2E + */ + d->arch=2Ehvm=2Eext_dest_id |=3D hvm_ext_dest_id_enabled(d); hvm_domain_creation_finished(d); + } } =20 #ifdef CONFIG_COMPAT diff --git a/xen/arch/x86/hvm/ioreq=2Ec b/xen/arch/x86/hvm/ioreq=2Ec index a5fa97e149=2E=2E894a63c522 100644 --- a/xen/arch/x86/hvm/ioreq=2Ec +++ b/xen/arch/x86/hvm/ioreq=2Ec @@ -19,6 +19,7 @@ =20 #include #include +#include #include #include =20 @@ -325,6 +326,42 @@ void arch_ioreq_domain_init(struct domain *d) register_portio_handler(d, 0xcf8, 4, hvm_access_cf8); } =20 +int arch_ioreq_server_create_check(const struct domain *d, uint8_t flags) +{ + if ( !is_hvm_domain(d) || !d->creation_finished ) + return 0; + + if ( d->arch=2Ehvm=2Eext_dest_id && + !(flags & XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID) ) + return -EPERM; + + return 0; +} + +static int cf_check ext_dest_id_save(struct vcpu *v, hvm_domain_context_t= *h) +{ + struct hvm_hw_ext_dest_id s =3D { + =2Eenabled =3D v->domain->arch=2Ehvm=2Eext_dest_id, + }; + + return hvm_save_entry(EXT_DEST_ID, 0, h, &s); +} + +static int cf_check ext_dest_id_load(struct domain *d, hvm_domain_context= _t *h) +{ + struct hvm_hw_ext_dest_id s; + + if ( hvm_load_entry(EXT_DEST_ID, h, &s) ) + return -EINVAL; + + d->arch=2Ehvm=2Eext_dest_id =3D s=2Eenabled; + + return 0; +} + +HVM_REGISTER_SAVE_RESTORE(EXT_DEST_ID, ext_dest_id_save, NULL, + ext_dest_id_load, 1, HVMSR_PER_DOM); + /* * Local variables: * mode: C diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec index 527cc770b7=2E=2E7d037a53e1 100644 --- a/xen/arch/x86/hvm/vioapic=2Ec +++ b/xen/arch/x86/hvm/vioapic=2Ec @@ -24,6 +24,7 @@ * Ported to xen by using virtual IRQ line=2E */ =20 +#include #include #include #include @@ -597,6 +598,7 @@ int vioapic_get_trigger_mode(const struct domain *d, u= nsigned int gsi) static int cf_check ioapic_check(const struct domain *d, hvm_domain_conte= xt_t *h) { const HVM_SAVE_TYPE(IOAPIC) *s; + unsigned int i; =20 if ( !has_vioapic(d) ) return -ENODEV; @@ -617,6 +619,24 @@ static int cf_check ioapic_check(const struct domain = *d, hvm_domain_context_t *h if ( s->ioregsel > VIOAPIC_REG_RTE0 + (ARRAY_SIZE(s->redirtbl) - 1) *= 2 + 1 ) return -EINVAL; =20 + /* + * If any RTE uses extended destination ID bits, the EXT_DEST_ID save + * record must have been loaded first (restoring d->arch=2Ehvm=2Eext_= dest_id)=2E + * The ioreq server re-registration by the DM happens later, so use t= he + * domain-level locked flag rather than the per-server dynamic check= =2E + */ + for ( i =3D 0; i < ARRAY_SIZE(s->redirtbl); i++ ) + { + if ( s->redirtbl[i]=2Efields=2Eext_dest_id && !d->arch=2Ehvm=2Eex= t_dest_id ) + { + printk(XENLOG_G_ERR "HVM restore: %pd IO-APIC RTE %u has " + "extended destination ID bits set but " + "EXT_DEST_ID is not enabled\n", + d, i); + return -EINVAL; + } + } + return 0; } =20 diff --git a/xen/arch/x86/include/asm/hvm/domain=2Eh b/xen/arch/x86/includ= e/asm/hvm/domain=2Eh index abf9bc448d=2E=2E895b2e12ba 100644 --- a/xen/arch/x86/include/asm/hvm/domain=2Eh +++ b/xen/arch/x86/include/asm/hvm/domain=2Eh @@ -102,6 +102,15 @@ struct hvm_domain { =20 bool is_s3_suspended; =20 + /* + * True when XEN_HVM_CPUID_EXT_DEST_ID was advertised to the guest=2E= Locked + * at domain creation time once every registered ioreq server has opt= ed in + * via XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID=2E Persisted in HVM save/res= tore so + * migration preserves the guest-visible state independently of when = the + * device model re-registers its ioreq servers on the destination hos= t=2E + */ + bool ext_dest_id; + /* Compatibility setting for a bug in x2APIC LDR */ bool bug_x2apic_ldr_vcpu_id; =20 diff --git a/xen/common/ioreq=2Ec b/xen/common/ioreq=2Ec index f5fd30ce12=2E=2E56a7eb8282 100644 --- a/xen/common/ioreq=2Ec +++ b/xen/common/ioreq=2Ec @@ -641,7 +641,7 @@ static void ioreq_server_deinit(struct ioreq_server *s= ) } =20 static int ioreq_server_create(struct domain *d, int bufioreq_handling, - ioservid_t *id) + uint8_t flags, ioservid_t *id) { struct ioreq_server *s; unsigned int i; @@ -683,6 +683,8 @@ static int ioreq_server_create(struct domain *d, int b= ufioreq_handling, goto fail; } =20 + s->ext_dest_id =3D flags & XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID; + if ( id ) *id =3D i; =20 @@ -1350,11 +1352,16 @@ int ioreq_server_dm_op(struct xen_dm_op *op, struc= t domain *d, bool *const_op) *const_op =3D false; =20 rc =3D -EINVAL; - if ( data->pad[0] || data->pad[1] || data->pad[2] ) + if ( data->flags & ~XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID || + data->pad[0] || data->pad[1] ) + break; + + rc =3D arch_ioreq_server_create_check(d, data->flags); + if ( rc ) break; =20 rc =3D ioreq_server_create(d, data->handle_bufioreq, - &data->id); + data->flags, &data->id); break; } =20 diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrough= /x86/hvm=2Ec index 6fb4f8b7dc=2E=2Ef7f7c02076 100644 --- a/xen/drivers/passthrough/x86/hvm=2Ec +++ b/xen/drivers/passthrough/x86/hvm=2Ec @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -455,6 +456,18 @@ int pt_irq_create_bind( uint64_t msi_addr; uint32_t msi_data; =20 + /* + * Refuse the old MSI bind path when extended destination IDs are + * in use=2E The caller must use XEN_DMOP_bind_pt_msi_irq instead= , + * which passes the raw MSI address so Xen can decode the extende= d + * bits=2E This old path only carries an 8-bit destination ID and + * would silently misroute interrupts to vCPUs with APIC IDs > 25= 5=2E + */ + if ( hvm_ext_dest_id_enabled(d) ) + { + return -EPERM; + } + msi_addr =3D MSI_ADDR_HEADER | MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DEST_I= D_MASK), MSI_ADDR_DEST_ID_MASK) | diff --git a/xen/include/public/arch-x86/hvm/save=2Eh b/xen/include/public= /arch-x86/hvm/save=2Eh index 483097d940=2E=2Edd70ce18c6 100644 --- a/xen/include/public/arch-x86/hvm/save=2Eh +++ b/xen/include/public/arch-x86/hvm/save=2Eh @@ -627,12 +627,27 @@ struct hvm_msr { =20 #define CPU_MSR_CODE 20 =20 +/* + * HVM_SAVE_TYPE(EXT_DEST_ID): domain-level extended MSI destination ID s= tate=2E + * + * Records whether the extended destination ID feature was enabled for th= is + * domain at the time guest vCPUs were started=2E This allows migration t= o + * preserve the setting across hosts without relying on the device model = to + * re-register its ioreq servers before the guest's first CPUID query=2E + */ +struct hvm_hw_ext_dest_id { + uint8_t enabled; + uint8_t pad[7]; +}; + +DECLARE_HVM_SAVE_TYPE(EXT_DEST_ID, 21, struct hvm_hw_ext_dest_id); + /* Range 22 - 34 (inclusive) reserved for Amazon */ =20 /* * Largest type-code in use */ -#define HVM_SAVE_CODE_MAX 20 +#define HVM_SAVE_CODE_MAX 21 =20 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */ =20 diff --git a/xen/include/public/hvm/dm_op=2Eh b/xen/include/public/hvm/dm_= op=2Eh index 43571b7713=2E=2E73f33b3c46 100644 --- a/xen/include/public/hvm/dm_op=2Eh +++ b/xen/include/public/hvm/dm_op=2Eh @@ -39,18 +39,28 @@ typedef uint16_t ioservid_t; * XEN_DMOP_create_ioreq_server: Instantiate a new IOREQ Server for a * secondary emulator=2E * - * The handed back is unique for target domain=2E The valur of + * The handed back is unique for target domain=2E The value of * should be one of HVM_IOREQSRV_BUFIOREQ_* defined in - * hvm_op=2Eh=2E If the value is HVM_IOREQSRV_BUFIOREQ_OFF then the buff= ered + * hvm_op=2Eh=2E If the value is HVM_IOREQSRV_BUFIOREQ_OFF then the buffe= red * ioreq ring will not be allocated and hence all emulation requests to * this server will be synchronous=2E + * + * If contains XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID, the server will + * use XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings, passing + * raw MSI address/data fields so Xen can decode extended destination ID + * bits=2E Once any server sets this flag, Xen will advertise + * XEN_HVM_CPUID_EXT_DEST_ID to the guest=2E Must be set before the guest + * vCPUs are started=2E */ #define XEN_DMOP_create_ioreq_server 1 =20 struct xen_dm_op_create_ioreq_server { /* IN - should server handle buffered ioreqs */ uint8_t handle_bufioreq; - uint8_t pad[3]; + /* IN - server capability flags */ + uint8_t flags; +#define XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID (1u << 0) + uint8_t pad[2]; /* OUT - server id */ ioservid_t id; }; diff --git a/xen/include/xen/ioreq=2Eh b/xen/include/xen/ioreq=2Eh index e86f0869fa=2E=2Eec78b63942 100644 --- a/xen/include/xen/ioreq=2Eh +++ b/xen/include/xen/ioreq=2Eh @@ -54,9 +54,35 @@ struct ioreq_server { evtchn_port_t bufioreq_evtchn; struct rangeset *range[NR_IO_RANGE_TYPES]; bool enabled; + bool ext_dest_id; uint8_t bufioreq_handling; }; =20 +/* + * Return true if every registered ioreq server has opted in to extended + * destination IDs (XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID) and at least one + * server exists=2E A single server without the flag is enough to suppres= s + * XEN_HVM_CPUID_EXT_DEST_ID, preventing misrouted interrupts=2E + */ +static inline bool hvm_ext_dest_id_enabled(const struct domain *d) +{ + unsigned int i; + bool found =3D false; + + for ( i =3D 0; i < MAX_NR_IOREQ_SERVERS; i++ ) + { + const struct ioreq_server *s =3D d->ioreq_server=2Eserver[i]; + + if ( !s ) + continue; + if ( !s->ext_dest_id ) + return false; + found =3D true; + } + + return found; +} + static inline paddr_t ioreq_mmio_first_byte(const ioreq_t *p) { return unlikely(p->df) ? @@ -137,6 +163,7 @@ bool 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<1777298082.8631fc262581453bbf619ec5b2062170.19dcf3888b2000f373@vates.tech> x-swg-bid: 1777298082.8631fc262581453bbf619ec5b2062170.19dcf3888b2000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] From: Julian Vetter To: xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Teddy Astie , Julian Vetter Subject: [PATCH v4 9/9] x86/cpuid: Advertise XEN_HVM_CPUID_EXT_DEST_ID when device model opts in Date: Mon, 27 Apr 2026 15:54:06 +0200 In-Reply-To: <20260427135406.1281424-1-julian.vetter@vates.tech> References: <20260427135406.1281424-1-julian.vetter@vates.tech> MIME-Version: 1.0 X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.297b.fbc1bfd9f0ae3bc.19dcf3886b4.b9ec472d3f1c7cf3=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777298081460 X-purgate-ID: tlsNG-4011c0/1777298107-819868B7-9B2F6A6C/0/0 X-purgate-type: clean X-purgate-size: 3537 ---=Part.297b.fbc1bfd9f0ae3bc.19dcf3886b4.b9ec472d3f1c7cf3=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Set the XEN_HVM_CPUID_EXT_DEST_ID bit in the HVM hypervisor CPUID leaf based on the domain-level ext_dest_id flag, which is locked at domain creation time by taking the AND across all registered ioreq servers that set XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID=2E This guarantees that the bit is only advertised when every active device model will use XEN_DMOP_bind_pt_msi_irq for passthrough MSIs, so Xen can decode the extended destination bits from the raw MSI address internally=2E After creation_finished the locked d->arch=2Ehvm=2Eext_dest_id is used directly, providing a stable and migration-safe value independent of whether ioreq servers have been re-registered yet=2E Before creation_finished the dynamic per-server check is used so toolstack queries during domain setup reflect the current state=2E An old device model that never sets XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID will keep the bit clear, preserving backwards compatibility with guests that only use 8-bit APIC destination IDs=2E A device model that opts in enables support for x2APIC destination IDs above 255=2E Signed-off-by: Julian Vetter --- Changes in v4: - Corresponds to v3 patch 7, updated for the new negotiation mechanism introduced in patch 8=2E The bit now reflects the levelled result computed at arch_domain_creation_finished() - Before creation_finished(): the dynamic hvm_ext_dest_id_enabled() check is used (so toolstack CPUID queries during domain setup see the current state) - After creation_finished(): the locked d->arch=2Ehvm=2Eext_dest_id is= used directly for migration-safe value that does not depend on whether ioreq servers have been re-registered on the destination host yet --- xen/arch/x86/cpuid=2Ec | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/xen/arch/x86/cpuid=2Ec b/xen/arch/x86/cpuid=2Ec index 6e9b15c9c3=2E=2E828aaa9f5b 100644 --- a/xen/arch/x86/cpuid=2Ec +++ b/xen/arch/x86/cpuid=2Ec @@ -1,3 +1,4 @@ +#include #include #include #include @@ -148,6 +149,18 @@ static void cpuid_hypervisor_leaves(const struct vcpu= *v, uint32_t leaf, res->a |=3D XEN_HVM_CPUID_DOMID_PRESENT; res->c =3D d->domain_id; =20 + /* + * Advertise extended destination ID support=2E Once domain creat= ion has + * finished the locked domain flag is authoritative (ensuring a + * consistent view across migration, before the device model + * re-registers its ioreq servers on the destination)=2E Before + * creation_finished the dynamic per-server check is used so that + * toolstack queries during domain setup reflect the current stat= e=2E + */ + if ( d->creation_finished ? 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ac8675518f30b467b204b36589b42707c9958735726f x-campaign-type: default x-transaction-id: b01bb53b-b52c-425b-8aa2-57df1fd9b60f x-swg-uid: 01-f1549c0f-3b67-4b23-82ec-f235ee9cba72 X-Mailer: Sweego Message-ID: <1777302748.8631fc262581453bbf619ec5b2062170.19dcf7fbe13000f373@vates.tech> x-swg-bid: 1777302748.8631fc262581453bbf619ec5b2062170.19dcf7fbe13000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Mon, 27 Apr 2026 17:12:27 +0200 From: Anthony PERARD To: Marek =?iso-8859-1?Q?Marczykowski-G=F3recki?= Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Stefano Stabellini , Roger Pau =?iso-8859-1?Q?Monn=E9?= Subject: Re: [PATCH test-artifacts v3 03/13] Add debian rootfs artifact References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.29c1.d93e4a476c499e31.19dcf7fbb9a.2d346ab1c18c0856=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777302748058 X-purgate-ID: tlsNG-ebf023/1777302750-32E743FF-0C64F532/0/0 X-purgate-type: clean X-purgate-size: 4271 ---=Part.29c1.d93e4a476c499e31.19dcf7fbb9a.2d346ab1c18c0856=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Wed, Apr 15, 2026 at 07:59:34PM +0200, Marek Marczykowski-G=C3=B3recki w= rote: > On Wed, Apr 15, 2026 at 11:50:38AM +0000, Anthony PERARD wrote: > > > diff --git a/scripts/debian-rootfs=2Esh b/scripts/debian-rootfs=2Esh > > > new file mode 100755 > > > index 000000000000=2E=2E7cb8a96e39c0 > > > --- /dev/null > > > +++ b/scripts/debian-rootfs=2Esh > > =2E=2E=2E > > > +PKGS=3D( > > > + # System > > > + bridge-utils > > > + dropbear > > > + udev > > > + systemd-sysv > > > + iproute2 > > > + inetutils-ping > > > + util-linux > > > + cpio > >=20 > > Is `cpio` going to be used in dom0? The alpine rootfs don't have it=2E >=20 > Alpine does have it, via busybox=2E That said, I don't see it used in an= y > current test=2E Turns out I'm actually using `cpio` on the Alpine rootfs=2E But the only reason is to work around a very slow download of the rootfs via the UEFI firmware (and grub) of the machine=2E I just boot with a smaller rootfs, then after Linux is started, I download the rootfs that only has the xentool and extract it with `cpio`=2E (loading the full rootfs over netboot takes about 15min on that machine) > > > +# don't need persistent logging, avoid journal flush service > > > +rmdir var/log/journal > >=20 > > I think this would better be done with: > >=20 > > cat >> /etc/systemd/journald=2Econf=2Ed/storage=2Econf < > [Journal] > > Storage=3Dvolatile > > EOF > >=20 > > because I think systemd intend to change the behavior in future releas= e, > > and we are more explicit with a config file=2E >=20 > +1=20 >=20 > > > +# Create rootfs > > > +cd / > > > +{ > > > + PATHS=3D"bin etc home init lib lib64 mnt opt root sbin srv tmp = usr var" > > > + find $PATHS -print0 > > > + echo -ne "dev\0proc\0run\0sys\0" > > > +} | cpio -0 -H newc -o | gzip > "${COPYDIR}/rootfs=2Ecpio=2Egz" > >=20 > > You should add "-R0:0" to the `cpio` command, like we do for the alpin= e > > rootfs=2E >=20 > Hm, I'm not sure if that's a good idea=2E There are a few intentionally > non-root files in Debian=2E Right now that is: >=20 > -rw-r----- 1 root 42 496 Apr 1 01:08 etc/gshadow > -rw-r----- 1 root 42 564 Apr 1 01:08 etc/shadow > -rw-r----- 1 root 42 444 Apr 1 01:08 etc/gshadow- > -rw-r----- 1 root 42 565 Apr 1 01:08 etc/shadow- > -rwxr-sr-x 1 root 42 31256 Apr 19 2025 usr/bin/expiry > -rwxr-sr-x 1 root 42 113848 Apr 19 2025 usr/bin/chage > -rwsr-xr-- 1 root printadm 51272 Mar 8 2025 usr/lib/dbus-1=2E= 0/dbus-daemon-launch-helper > -rwxr-sr-x 1 root 42 43256 Jun 29 2025 usr/sbin/unix_chk= pwd > drwxr-xr-x 2 systemd- systemd- 0 Apr 1 01:08 var/lib/systemd/n= etwork > drwxr-xr-x 2 42 root 0 Apr 1 01:07 var/lib/apt/lists= /auxfiles > drwx------ 2 42 root 0 Apr 1 01:07 var/lib/apt/lists= /partial > drwxrwsr-x 2 root mem 0 Sep 8 2025 var/mail > -rw-rw-r-- 1 root 43 0 Sep 8 2025 var/log/wtmp > -rw-rw-r-- 1 root 43 0 Sep 8 2025 var/log/lastlog > -rw-rw---- 1 root 43 0 Sep 8 2025 var/log/btmp > -rw-r----- 1 root adm 31508 Apr 1 01:08 var/log/apt/term= =2Elog > drwx------ 2 42 root 0 Apr 1 01:08 var/cache/apt/arc= hives/partial >=20 > While it _might_ not explode right now if we reset it to root, it may > cause issues in the future (for example APT likes to run downloads as > unprivileged user, with write access only to > /var/lib/apt/lists/partial)=2E Ah, right, "-R0:0" probably only make sense when we build Xen as a build user=2E So, with the change to journald config: Reviewed-by: Anthony PERARD Cheers, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.29c1.d93e4a476c499e31.19dcf7fbb9a.2d346ab1c18c0856=--- From xen-devel-bounces@lists.xenproject.org Mon Apr 27 15:27:20 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 15:27:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295016.1571711 (Exim 4.92) (envelope-from ) id 1wHNrd-0002tj-3R; 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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c0354sm737076355e9.11.2026.04.27.08.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 08:34:34 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777304076; x=1777908876; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M/P5e4xXherIeaejZwj9DdoItZcrKaqfgLMdEPxMeGI=; b=IXF9hNbYg0XEuMVt+TzOvTbAdjKfju9/Ln05E2+qXMeMdkJk8D8yY27AwOGAPcuhs0 a/KDq6MGQlzDAATD9UI5tofMJIcFos8duZNHsorcuGNIG9PCsMGP0H2we3EKYPP4aJ45 tLo4YwVnU1tBoVj+64kdc+2/4OtubFTPXt4ifpmlX0FXbwJ1bcNSPc9m1uahnoRjsxV7 17WZI1n0k7XEm0DnOU3S9b8PzGsyWjdVLQjQULO4PdKDiMMfwBtTMk3YmrgsF8zKPB4h hbDQkeBK/80NEGKeX53EIkloa9ryCw+7ckQm+TZilXmEQmOoAfXwfLFhcDA7fI9dMeLR Mpeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777304076; x=1777908876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=M/P5e4xXherIeaejZwj9DdoItZcrKaqfgLMdEPxMeGI=; b=HjMac7tvkvIOJqSdDjJ7ps9h4AFrnutszJJyF2MnewelpjlUxbvYeVzhXe4EghUBF7 gSBYvdiZ0diOybkNKIJlsWlvLnxqg5nUGv4IHkjeNP/BqynmwjGaPUAYXM/rGqSSEv+/ 0d8mDD6oiQCas1lrYEO8u/GVhsnRQSiqDyOEGIylwSIIHMUzLghqqhZVYbZ8l1FllgEp uWA6Uzc02FViO7RCDACbNT1CTr/SHFyzSsSd/fr51VMdlUinx6iU1/Upou9kY+iI2iHW ID9+9HKciuL2WV3pGCQ5KgAeecZ2i2PGa3vk3BU193abaC1OwqJzxMumzYFtLxEQ2V6B ASlg== X-Gm-Message-State: AOJu0YxC8Q0elGcXhWt1zlbjDrXeJ5pAFuNetBuu0groeCSC52sEmXFg PQVvaZcQrkH3vQ0UcO0TWKcwS3zK6dEJZnAaXXMBQur1HYsVooNszIWSa8AImQ== X-Gm-Gg: AeBDievG+1aGB9yHMD6jtazcl1oG7lyoHXr/0PI2JJRmTfDnVcSnGDCYgf0GuuWHVUa dFW98KQw4OL3hb0qvdRlr0mlYAhFs0MzDw5qGHiMS3eTPxeVzQfBDXWKzRt4HxL2aXOJoWbMjyY lrzj1OdaJWo1fb/wiDBNJTZcTBIR7U5ua5yB4vtdbAQv1bvLQbLc9KxV2cPTgZjqfgq8zkDDHl3 YX9xCYPc3p16yHn941Tv9smJ5/7GDlgyoDj0hhDrGe9qHkkeT8E6ubgxkp96lOevQ4gE57Qqzww sbcoaMlHTVL3OvmC9uzT+yZ7rk12zZNOu1jnLyafLFX7rqUR6Yoy24gGyiVMhKDMw6ryBtvPABB TuOhirNrjQKQrLLQtcdmtvwZNSWGvJqclnhNs0QNaUZ4StMv/r0rNv2ne9THA1VQAqNbpZImk3E rMroa/QWzbxFUuuhRBqzGar8pQ47ef7QdjBPn+Zp9KmSFwyOLhBNWxN5ey6ucQCp0mPhKQu0fCl lIq X-Received: by 2002:a05:600c:1907:b0:489:201c:dc46 with SMTP id 5b1f17b1804b1-489201cdf13mr426972005e9.12.1777304075162; Mon, 27 Apr 2026 08:34:35 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 1/3] xen/dom0less: introduce next_phandle in struct kernel_info Date: Mon, 27 Apr 2026 17:34:23 +0200 Message-ID: <3822f12057ecc9d51b314308b0e32a85e83a7558.1777296786.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1777304076-3A776DB1-10E9FD48/10/73395122804 X-purgate-type: spam X-purgate-size: 6329 There are cases where it is necessary to know the next available phandle number in order to generate phandles for guest device nodes. When a partial FDT (pfdt) is provided, special care is needed during initialization of next_phandle, as the pfdt may already contain a dummy interrupt controller node with a phandle assigned to it. next_phandle must therefore be initialized to one past the highest phandle already present in the pfdt, to avoid collisions. Since next_phandle may be needed for the very first guest node generated, domain_handle_dtb_boot_module() is moved earlier in prepare_dtb_domU(). The new call site also aligns better with the existing comment stating that domain_handle_dtb_boot_module() must be called before the rest of the device tree is generated. Introduce alloc_phandle() to ensure that phandles allocated for guest nodes do not overlap the Xen-reserved phandle range. This helper will be used by subsequent patches (by RISC-V at the moment). Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel --- Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandle is generated in this example not by get_next_free_phandle(). For non RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC it is interrupt controller which provides MSI and connects to each CPU. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt --- Changes in v4: - Add Reviewed-by: Michal Orzel --- Changes in v3: - Drop BUG_ON(GUEST_PHANDLE_GIC == 1). - Update the comment above declaration of next_phandle field of srtuct kernel_info. --- Changes in v2: - s/free_phandle/next_phandle. - s/get_next_free_phandle/alloc_phandle. --- xen/common/device-tree/dom0less-build.c | 43 ++++++++++++++++++------- xen/include/xen/fdt-domain-build.h | 6 ++++ xen/include/xen/fdt-kernel.h | 6 ++++ 3 files changed, 43 insertions(+), 12 deletions(-) diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 840d14419da2..9787ee264975 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -389,6 +389,24 @@ static int __init domain_handle_dtb_boot_module(struct domain *d, if ( res < 0 ) goto out; + /* + * Find the highest phandle in the partial FDT so next_phandle starts + * above it, avoiding collisions with pfdt's own phandle assignments. + */ + res = fdt_generate_phandle(pfdt, &kinfo->next_phandle); + if ( res ) + { + res = (res == -FDT_ERR_NOPHANDLES) ? -EOVERFLOW : -EINVAL; + goto out; + } + + if ( kinfo->next_phandle >= GUEST_PHANDLE_GIC ) + { + dprintk(XENLOG_ERR, "Phandle allocation overlaps Xen reserved range\n"); + res = -EOVERFLOW; + goto out; + } + for ( node_next = fdt_first_subnode(pfdt, 0); node_next > 0; node_next = fdt_next_subnode(pfdt, node_next) ) @@ -459,6 +477,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) BUILD_BUG_ON(DOMU_DTB_SIZE > SZ_2M); kinfo->phandle_intc = GUEST_PHANDLE_GIC; + kinfo->next_phandle = 1; #ifdef CONFIG_GRANT_TABLE kinfo->gnttab_start = GUEST_GNTTAB_BASE; @@ -499,6 +518,18 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; + /* + * domain_handle_dtb_boot_module() must be called before the rest of the + * device tree is generated because it sets phandle_intc and next_phandle, + * which subsequent node generation depends on. + */ + if ( kinfo->dtb ) + { + ret = domain_handle_dtb_boot_module(d, kinfo); + if ( ret ) + goto err; + } + ret = make_chosen_node(kinfo); if ( ret ) goto err; @@ -516,18 +547,6 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - /* - * domain_handle_dtb_boot_module has to be called before the rest of - * the device tree is generated because it depends on the value of - * the field phandle_intc. - */ - if ( kinfo->dtb ) - { - ret = domain_handle_dtb_boot_module(d, kinfo); - if ( ret ) - goto err; - } - ret = make_intc_domU_node(kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 886a85381651..fd2ba01ff0f4 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -63,6 +63,12 @@ int find_unallocated_memory(const struct kernel_info *kinfo, unsigned long e_gfn, void *data)); +/* Return 0 (invalid phandle) if the Xen-reserved range has been reached */ +static inline uint32_t alloc_phandle(struct kernel_info *kinfo) +{ + return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 33a60597bb4d..4d0467bb396a 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -44,6 +44,12 @@ struct kernel_info { /* Interrupt controller phandle */ uint32_t phandle_intc; + /* + * Next free phandle for guest device nodes; do not access directly, use + * alloc_phandle(). + */ + uint32_t next_phandle; + /* loader to use for this kernel */ void (*load)(struct kernel_info *info); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 15:34:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 15:34:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295028.1571746 (Exim 4.92) (envelope-from ) id 1wHNyq-0005LS-RF; Mon, 27 Apr 2026 15:34:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295028.1571746; Mon, 27 Apr 2026 15:34:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHNyq-0005LF-O7; Mon, 27 Apr 2026 15:34:40 +0000 Received: by outflank-mailman (input) for mailman id 1295028; Mon, 27 Apr 2026 15:34:39 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHNyp-0004sz-IL for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 15:34:39 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHNyo-00GEYf-V8 for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 17:34:38 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8201-bab6-0a2a0a5309dd-0a2a4506eb28-18 for ; Mon, 27 Apr 2026 17:34:38 +0200 Received: from [209.85.128.42] (helo=mail-wm1-f42.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef820e-7371-0a2a45060019-d155802ab08e-3 for ; Mon, 27 Apr 2026 17:34:38 +0200 Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-483487335c2so102261365e9.2 for ; Mon, 27 Apr 2026 08:34:38 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Change the guard around access of kinfo->type to CONFIG_HAS_DOMAIN_TYPE for consistency. Also, drop and add some parentheses to be aligned with the similar if() below. x86 with CONFIG_64BIT=y shouldn't use is_{32,64}bit_domain() as x86 doesn't have support of CONFIG_HAS_DOMAIN_TYPE. Since x86_32 Xen no longer builds, the fallback is currently only relevant for arm32. Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel --- Changes in v4: - Drop enum domain_type type; from Arm's struct arch_domain. - Add Reviewed-by: Michal Orzel . --- Changes in v3: - Sort properly HAS_DOMAIN_TYPE in xen/common/Kconfig. - Update the comment above is_*bit_domain() macros. --- Changes in v2: - Update the commit message. - Move HAS_DOMAIN_TYPE to xen/common/Kconfig. - Return set_domain_type(), move it to xen/fdt-domain-build.h and make it static inline. - s/CONFIG_ARM_64/CONFIG_HAS_DOMAIN for the places where kinfo->type is used. - Drop parantethes around cpu_has_el1_32 in if() and add around (kinfo->type == DOMAIN_32BIT) to be consistent with the similar check below. - Fix comment code style. - Add __packed to definition of enum domain_type --- xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 ++-- xen/arch/arm/dom0less-build.c | 14 -------------- xen/arch/arm/domain_build.c | 12 +++++------- xen/arch/arm/include/asm/domain.h | 16 ---------------- xen/arch/arm/include/asm/kernel.h | 4 ---- xen/arch/arm/kernel.c | 16 ++++++++-------- xen/common/Kconfig | 3 +++ xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++++++++ xen/include/xen/fdt-domain-build.h | 9 +++++++++ xen/include/xen/fdt-kernel.h | 5 +++++ xen/include/xen/sched.h | 4 ++++ 13 files changed, 50 insertions(+), 53 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2f2b501fdac4..79622b46a10d 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -7,6 +7,7 @@ config ARM_64 def_bool y depends on !ARM_32 select 64BIT + select HAS_DOMAIN_TYPE select HAS_FAST_MULTIPLY select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c index 8720d126c97d..9e9a29eb1e78 100644 --- a/xen/arch/arm/arm64/domctl.c +++ b/xen/arch/arm/arm64/domctl.c @@ -21,10 +21,10 @@ static long switch_mode(struct domain *d, enum domain_type type) return -EINVAL; if ( domain_tot_pages(d) != 0 ) return -EBUSY; - if ( d->arch.type == type ) + if ( d->type == type ) return 0; - d->arch.type = type; + d->type = type; if ( is_64bit_domain(d) ) for_each_vcpu(d, v) diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f73c65e5151 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -237,20 +237,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) return 0; } -/* TODO: make arch.type generic ? */ -#ifdef CONFIG_ARM_64 -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* type must be set before allocate memory */ - d->arch.type = kinfo->arch.type; -} -#else -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* Nothing to do */ -} -#endif - int __init init_vuart(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index a3ff70102376..ad665cd3c045 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1771,15 +1771,15 @@ int __init construct_domain(struct domain *d, struct kernel_info *kinfo) BUG_ON(d->vcpu[0] == NULL); BUG_ON(v->is_initialised); -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain */ - if ( !(cpu_has_el1_32) && kinfo->arch.type == DOMAIN_32BIT ) + if ( !cpu_has_el1_32 && (kinfo->type == DOMAIN_32BIT) ) { printk("Platform does not support 32-bit domain\n"); return -EINVAL; } - if ( is_sve_domain(d) && (kinfo->arch.type == DOMAIN_32BIT) ) + if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) ) { printk("SVE is not available for 32-bit domain\n"); return -EINVAL; @@ -1893,10 +1893,8 @@ int __init construct_hwdom(struct kernel_info *kinfo, iommu_hwdom_init(d); -#ifdef CONFIG_ARM_64 - /* type must be set before allocate_memory */ - d->arch.type = kinfo->arch.type; -#endif + set_domain_type(d, kinfo); + find_gnttab_region(d, kinfo); if ( is_domain_direct_mapped(d) ) allocate_memory_11(d, kinfo); diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index ffe5d0d9f0a6..b24f02d269be 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -18,18 +18,6 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; -#ifdef CONFIG_ARM_64 -enum domain_type { - DOMAIN_32BIT, - DOMAIN_64BIT, -}; -#define is_32bit_domain(d) ((d)->arch.type == DOMAIN_32BIT) -#define is_64bit_domain(d) ((d)->arch.type == DOMAIN_64BIT) -#else -#define is_32bit_domain(d) (1) -#define is_64bit_domain(d) (0) -#endif - /* * Is the domain using the host memory layout? * @@ -62,10 +50,6 @@ struct paging_domain { struct arch_domain { -#ifdef CONFIG_ARM_64 - enum domain_type type; -#endif - #ifdef CONFIG_ARM64_SVE /* max SVE encoded vector length */ uint8_t sve_vl; diff --git a/xen/arch/arm/include/asm/kernel.h b/xen/arch/arm/include/asm/kernel.h index 7c3b7fde5b64..21f4273fa1b5 100644 --- a/xen/arch/arm/include/asm/kernel.h +++ b/xen/arch/arm/include/asm/kernel.h @@ -10,10 +10,6 @@ struct arch_kernel_info { -#ifdef CONFIG_ARM_64 - enum domain_type type; -#endif - /* Enable pl011 emulation */ bool vpl011; }; diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 7544fd50a20f..9395b5af8745 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -100,8 +100,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) const struct membanks *mem = kernel_info_get_mem(info); paddr_t load_addr; -#ifdef CONFIG_ARM_64 - if ( (info->arch.type == DOMAIN_64BIT) && (info->zimage.start == 0) ) +#ifdef CONFIG_HAS_DOMAIN_TYPE + if ( (info->type == DOMAIN_64BIT) && (info->zimage.start == 0) ) return mem->bank[0].start + info->zimage.text_offset; #endif @@ -268,14 +268,14 @@ int __init kernel_uimage_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 +#ifdef CONFIG_HAS_DOMAIN_TYPE switch ( uimage.arch ) { case IH_ARCH_ARM: - info->arch.type = DOMAIN_32BIT; + info->type = DOMAIN_32BIT; break; case IH_ARCH_ARM64: - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; break; default: printk(XENLOG_ERR "Unsupported uImage arch type %d\n", uimage.arch); @@ -345,7 +345,7 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, info->load = kernel_zimage_load; - info->arch.type = DOMAIN_64BIT; + info->type = DOMAIN_64BIT; return 0; } @@ -396,8 +396,8 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, info->load = kernel_zimage_load; -#ifdef CONFIG_ARM_64 - info->arch.type = DOMAIN_32BIT; +#ifdef CONFIG_HAS_DOMAIN_TYPE + info->type = DOMAIN_32BIT; #endif return 0; diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 0a20aa0a1249..5ff71480eebe 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -128,6 +128,9 @@ config HAS_DEVICE_TREE_DISCOVERY config HAS_DOM0LESS bool +config HAS_DOMAIN_TYPE + bool + config HAS_DIT # Data Independent Timing bool diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h index faaf660424b2..4118dec76c0a 100644 --- a/xen/include/xen/dom0less-build.h +++ b/xen/include/xen/dom0less-build.h @@ -57,8 +57,6 @@ int init_vuart(struct domain *d, struct kernel_info *kinfo, int make_intc_domU_node(struct kernel_info *kinfo); int make_arch_nodes(struct kernel_info *kinfo); -void set_domain_type(struct domain *d, struct kernel_info *kinfo); - int init_intc_phandle(struct kernel_info *kinfo, const char *name, const int node_next, const void *pfdt); diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 93c0fd00c1d7..8c898afe74fc 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -13,6 +13,19 @@ struct guest_area { void *map; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE +enum __packed domain_type { + DOMAIN_32BIT, + DOMAIN_64BIT, +}; +#define is_32bit_domain(d) ((d)->type == DOMAIN_32BIT) +#define is_64bit_domain(d) ((d)->type == DOMAIN_64BIT) +#elif !defined(CONFIG_64BIT) +/* At the moment on 32-bit-only platforms all domains are 32-bit. */ +#define is_32bit_domain(d) (true) +#define is_64bit_domain(d) (false) +#endif + #include typedef union { diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index 0d40d8cfa105..bc7744270c8f 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -7,6 +7,7 @@ #include #include #include +#include #include struct domain; @@ -69,6 +70,14 @@ static inline uint32_t alloc_phandle(struct kernel_info *kinfo) return kinfo->next_phandle >= GUEST_PHANDLE_GIC ? 0 : kinfo->next_phandle++; } +static inline void set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ +#ifdef CONFIG_HAS_DOMAIN_TYPE + /* Type must be set before allocate memory */ + d->type = kinfo->type; +#endif +} + #endif /* __XEN_FDT_DOMAIN_BUILD_H__ */ /* diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 4d0467bb396a..86a37a13048b 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -9,6 +9,7 @@ #include #include +#include #include #if __has_include() @@ -65,6 +66,10 @@ struct kernel_info { } zimage; }; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + #if __has_include() struct arch_kernel_info arch; #endif diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h index 212c7d765c3e..00db1da12f21 100644 --- a/xen/include/xen/sched.h +++ b/xen/include/xen/sched.h @@ -386,6 +386,10 @@ struct domain { domid_t domain_id; +#ifdef CONFIG_HAS_DOMAIN_TYPE + enum domain_type type; +#endif + unsigned int max_vcpus; uint64_t unique_id; /* Unique domain identifier */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 15:34:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 15:34:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295027.1571734 (Exim 4.92) (envelope-from ) id 1wHNyp-0004wP-LA; Mon, 27 Apr 2026 15:34:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295027.1571734; Mon, 27 Apr 2026 15:34:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHNyp-0004w1-Ew; Mon, 27 Apr 2026 15:34:39 +0000 Received: by outflank-mailman (input) for mailman id 1295027; Mon, 27 Apr 2026 15:34:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHNyn-0004hb-Ql for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 15:34:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHNyn-00GEYf-7e for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 17:34:37 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8208-bab6-0a2a0a5309dd-0a2a4503b6ae-12 for ; Mon, 27 Apr 2026 17:34:37 +0200 Received: from [209.85.128.41] (helo=mail-wm1-f41.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef820d-672d-0a2a45030019-d1558029e86d-3 for ; Mon, 27 Apr 2026 17:34:37 +0200 Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-488ff90d6c7so89008875e9.2 for ; Mon, 27 Apr 2026 08:34:37 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Align prototype with what other make_*_node() are passed. 2. A follow-up RISC-V patch will call get_next_free_phandle() inside make_cpus_node(), requiring mutable access to kinfo->free_phandle. Signed-off-by: Oleksii Kurochko Reviewed-by: Michal Orzel --- Look at the footer to the prev. patch to understand why phandle is needed inside cpu node. --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - Add Reviewed-by: Michal Orzel . --- Changes in v2: - Properly initialize local variable fdt in Arm's make_cpus_node(). --- xen/arch/arm/domain_build.c | 5 +++-- xen/common/device-tree/dom0less-build.c | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6c17a84b2633..a3ff70102376 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1163,7 +1163,7 @@ int __init make_psci_node(void *fdt) return res; } -int __init make_cpus_node(const struct domain *d, void *fdt) +int __init make_cpus_node(const struct domain *d, struct kernel_info *kinfo) { int res; const struct dt_device_node *cpus = dt_find_node_by_path("/cpus"); @@ -1177,6 +1177,7 @@ int __init make_cpus_node(const struct domain *d, void *fdt) /* Keep the compiler happy with -Og */ bool clock_valid = false; uint64_t mpidr_aff; + void *fdt = kinfo->fdt; dt_dprintk("Create cpus node\n"); @@ -1625,7 +1626,7 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo, if ( res ) return res; - res = make_cpus_node(d, kinfo->fdt); + res = make_cpus_node(d, kinfo); if ( res ) return res; diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c index 9787ee264975..6d6882a34b5a 100644 --- a/xen/common/device-tree/dom0less-build.c +++ b/xen/common/device-tree/dom0less-build.c @@ -534,7 +534,7 @@ static int __init prepare_dtb_domU(struct domain *d, struct kernel_info *kinfo) if ( ret ) goto err; - ret = make_cpus_node(d, kinfo->fdt); + ret = make_cpus_node(d, kinfo); if ( ret ) goto err; diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index fd2ba01ff0f4..0d40d8cfa105 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -25,7 +25,7 @@ int construct_domain(struct domain *d, struct kernel_info *kinfo); int construct_hwdom(struct kernel_info *kinfo, const struct dt_device_node *node); int make_chosen_node(const struct kernel_info *kinfo); -int make_cpus_node(const struct domain *d, void *fdt); +int make_cpus_node(const struct domain *d, struct kernel_info *kinfo); int make_hypervisor_node(struct domain *d, const struct kernel_info *kinfo, int addrcells, int sizecells); int make_memory_node(const struct kernel_info *kinfo, int addrcells, -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 15:34:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 15:34:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295025.1571720 (Exim 4.92) (envelope-from ) id 1wHNyo-0004hq-Qj; Mon, 27 Apr 2026 15:34:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295025.1571720; Mon, 27 Apr 2026 15:34:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHNyo-0004hj-My; Mon, 27 Apr 2026 15:34:38 +0000 Received: by outflank-mailman (input) for mailman id 1295025; Mon, 27 Apr 2026 15:34:37 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHNyn-0004gz-Dx for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 15:34:37 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHNym-00EOQ0-8o for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 17:34:36 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef81ee-5cb7-0a2a0a5109dd-0a2a4502c8e0-32 for ; Mon, 27 Apr 2026 17:34:36 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef820c-af86-0a2a45020019-d1558035a419-3 for ; Mon, 27 Apr 2026 17:34:36 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4891f625344so93940075e9.0 for ; Mon, 27 Apr 2026 08:34:36 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c0354sm737076355e9.11.2026.04.27.08.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 08:34:33 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777304075; x=1777908875; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=eA/7bZB0EQlEtV31qKIh/nBHzxk7MFpmf1h7BISbWxY=; b=iwI2Jm8irtLbIJIRJJbblMRm2YDeCLSBvEtw1xZQuJCljkUmz8HeU04ZrHb3TOJNV2 o5QmqXt9iF6mVNXzgnBKflNcVFSGSj799A0H6gdoa51/nbuEbpre11hnjblY8YAZSkzA rr14xsN03eBvhncCuatsDiTUrecosOO/G78AcSkKaWT6mKdwygmxIDh/2Nr+/5s/JubP rdiH4c0r8KBLGLZAmycKs8UHMzUHI3UDPdaLBPb2DeEeXrnNpGFEryiODz/JPuR6qhK9 5h9IFhdhE7XS6jWbFl7fWSnQJbr9H2aqIqoltJDefyLUC4xVpCO5KiCtp+KVlNMfWXHi Ydng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777304075; x=1777908875; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=eA/7bZB0EQlEtV31qKIh/nBHzxk7MFpmf1h7BISbWxY=; b=Y2m/MpWoIE5JWBM7IPPzKrUkdUs1gneYZs7vpqsoKKXyCNMm1rvDdr76siqoQUZye9 vBm90lbK7XLX+ZwHeZPQOg6Ylqsymj+Zd1VFlqLb98uujJH99j4ZcEfeQJl6P062RrIV V9KkA32TAbhFfndl4t279ldiCYM3Q2plO+U8B85C/2gNPhChEVJ95TE3R/vyuJ9hY/tP bqBOlMQEq1WgDH1Gn6LfwBRti5mY/5DdeQgb0Hhn9xbg8jNvrilMkY+L6+/y8sFVtuqD n2PEmzqdw5zGGiJ/pSFpm04PGmMLbzpLXnw1bpvKwR7cAyDLgLf+pzSvLtKS56QUq4gz V5Og== X-Gm-Message-State: AOJu0YwmFLoj55ynmzJviZfDFLYV4oS0zwdKVi7peP7SweBhNW0YYIMJ Z7YungPOiX6AVNW60IsdhLsQSzbK3PlWIMWQRscDDjn9Rn2snAPD6sOkEd0+cg== X-Gm-Gg: AeBDiesW477jKSZ2pCMHIVwa6Irx6OHi+XZHiZ9IVg47kdLSoR8fegxgtQlqm0RyoWh P2BwmN1WoGD1b00wMGEAfz94sWy73bdHk35JUiO6+ek9XKjfE4uUIUBHHpvDSoa3RBAFmQPOMuQ 3DT4BTu6h7KVGvqhD1NmvWMCtS62Uaqbem83QPiKJpAbPWYVKYgrozjSIAI9uCDD84AkyT21XFn e+tC/vqwvwxSVTlhLqhUzfrKmzWxDoKalX9/N94sg1UkUxyrZOD2Qxiag3uSGL1ofXPtA2PYnvT 8H3dMJ/r00eyx9ter01zktgWboMw3czDMNUIBGxpVnwYdaE/zwmlx6SXUUnsrTyntNGmdK3ZLoz Vq5SsBU+vSXnSPA+w5Vx6SM6CkMddFuaA8emwmTLchAqnpoptWoTADr22/YfdLe3oos+nozpthT OL6b1C0Ufw+XitzaHaBL4VgjWmbHG7a4QmGM0bQ9hZaVd1j7keLv79kQZsimJgBDSkbL064rDVv PBs X-Received: by 2002:a05:600c:3ba0:b0:486:faa8:9e4 with SMTP id 5b1f17b1804b1-488fb8b91a7mr565248145e9.12.1777304073960; Mon, 27 Apr 2026 08:34:33 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Volodymyr Babchuk Subject: [PATCH v4 0/3] dom0less: various updates Date: Mon, 27 Apr 2026 17:34:22 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1777304076-B316D161-4B878CAC/10/73395122804 X-purgate-type: spam X-purgate-size: 4093 This patch series introduces a new field to track not-yet-used phandles as there are some use cases where RISC-V needs to know which phandle number could be used for generating a device tree node. For example, on the RISC-V side in make_cpus_node() [1] it is necessary to know which phandle number is unused to use it for device tree node generation. Here is an example of generated guest DTB: cpus { ... cpu@0 { ... interrupt-controller { compatible = "riscv,cpu-intc"; #interrupt-cells = <0x1>; interrupt-controller; phandle = <0xfdea>; }; }; }; /soc/imsics@28000000 { interrupts-extended = <0xfdea 0x9 >; phandle = <0xfdeb>; }; /soc/aplic@d000000 { ... msi-parent = <0xfdeb>; phandle = <0x1>; }; Note that phandles for imsic and riscv,cpu-intc are generated in this example not by get_next_free_phandle(), that is why they have such big numbers. For non-RISC-V people, APLIC is an interrupt controller (something like GIC in Arm), IMSIC is an interrupt controller that provides MSI and connects to each CPU. So (based on the DTS above) for APLIC, kinfo->phandle_intc is reused, which will also be re-used for the device node's interrupt property. For all others, I just introduced GUEST_PHANDLE_LAST [2] and used it for generation [3]. But I expect that it could be useful for other architectures too so I just moved it to common and re-use pfdt to understand what the maximum used phandle is. [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt [2] https://lore.kernel.org/xen-devel/ccd6d21b224b478c88ca5f2fdd2d1dd507671510.1773157782.git.oleksii.kurochko@gmail.com/ [3] https://lore.kernel.org/xen-devel/fd64b8526a23e9d7775b9b48c5a933b0673c4fba.1773157782.git.oleksii.kurochko@gmail.com/ ************************************* Another thing introduced in this patch series is moving domain type to common code as several architectures (ARM and RISC-V for now) use them and it looks pretty architecture-independent. Also, is_64bit_domain() is used by dom0less common code, so I found it useful also to move is_{32,64}bit_domain macros to common code. ************************************* And the last thing is changing the prototype of make_cpus_node() to be aligned with other make_*_node() and since RISC-V will need access to the free_phandle field (even if it will be moved to kinfo->arch.free_phandle) and for the reason that this ->free_phandle is updated in make_*_node(), the kinfo argument is passed as non-const. CI: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2482499536 --- Changes in v4: - Rebase on top of staging. - Add Review-by for patch 1 and 3. - Address the comments. --- Changes in v3: - Rebase on top of staging. - Address the comments. --- Changes in v2: - Address the comments from ML. --- Oleksii Kurochko (3): xen/dom0less: introduce next_phandle in struct kernel_info xen/dom0less: pass kernel_info struct instead of fdt to make_cpus_node() xen: introduce CONFIG_HAS_DOMAIN_TYPE xen/arch/arm/Kconfig | 1 + xen/arch/arm/arm64/domctl.c | 4 +-- xen/arch/arm/dom0less-build.c | 14 -------- xen/arch/arm/domain_build.c | 17 +++++----- xen/arch/arm/include/asm/domain.h | 16 --------- xen/arch/arm/include/asm/kernel.h | 4 --- xen/arch/arm/kernel.c | 16 ++++----- xen/common/Kconfig | 3 ++ xen/common/device-tree/dom0less-build.c | 45 ++++++++++++++++++------- xen/include/xen/dom0less-build.h | 2 -- xen/include/xen/domain.h | 13 +++++++ xen/include/xen/fdt-domain-build.h | 17 +++++++++- xen/include/xen/fdt-kernel.h | 11 ++++++ xen/include/xen/sched.h | 4 +++ 14 files changed, 98 insertions(+), 69 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 16:11:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 16:11:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295067.1571783 (Exim 4.92) (envelope-from ) id 1wHOYa-00056S-Ec; Mon, 27 Apr 2026 16:11:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295067.1571783; Mon, 27 Apr 2026 16:11:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYa-00056L-BX; Mon, 27 Apr 2026 16:11:36 +0000 Received: by outflank-mailman (input) for mailman id 1295067; Mon, 27 Apr 2026 16:11:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYY-0004yN-Mu for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 16:11:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHOYY-002114-3j for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 18:11:34 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8a9f-e002-0a2a0a5209dd-0a2a4508d42e-38 for ; Mon, 27 Apr 2026 18:11:34 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef8ab5-63b5-0a2a45080019-d561b3389cea-3 for ; Mon, 27 Apr 2026 18:11:34 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wHOYJ-00305I-Ut; Mon, 27 Apr 2026 18:11:19 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=L3Sr9rY5U1mD/3546TE+xOT1mBFRY3YzwAzYlEgEGo8=; b=fgk9vBXil4XOQk4uEvi1ffSPD/ Ddejad/dkDzfLbOfDpVRwlSEL8l+83x9REQxqLJE5P0P7Zcnblttj3wKgaJIAgeJCuLMvDs93QHmB yQ+8cMrD8LBhVzy/NBcad2ZndJY56E3kRvhPzpN7oMsiaqahalL2FvucTDUE+/VAJG7Nok8J+9uK5 gMyGYvmDSEuR69SyjaV4wxkHe+wyJio9QLxsqdNfI3WH6dtxol/474EbFFs+fVkEMzTnbI0Gx7IAh I93hGl9HcJZRK/+jDv8TvrqkYWVAG/lKWWRB0AHOwLqdPC5dlQ6PqZhywGCh4b3rXOuhjgZT6H5b6 Ql97rhvQ==; From: Mauricio Faria de Oliveira Date: Mon, 27 Apr 2026 13:10:59 -0300 Subject: [PATCH v2 3/3] x86/pvh: fix unbootable VMs by really inlining memset() in xen_prepare_pvh() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260427-pvh-kasan-inline-v2-3-2c57b8dcff6a@igalia.com> References: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> In-Reply-To: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-c1860d/1777306294-C176EDB1-24BE70D9/0/0 X-purgate-type: clean X-purgate-size: 1474 Even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. This particular one (still) generated the inline implementation as expected (at least in these compiler versions), but this is not guaranteed to remain the case, as seen with the previous commit. Switch the builtin to the inline implementation to prevent a similar issue. Fixes: fbe5a6dfe492 ("xen, pvh: fix unbootable VMs by inlining memset() in xen_prepare_pvh()") Signed-off-by: Mauricio Faria de Oliveira Reviewed-by: Juergen Gross --- arch/x86/platform/pvh/enlighten.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/platform/pvh/enlighten.c b/arch/x86/platform/pvh/enlighten.c index f2053cbe9b0ce3d2178938269607c652ae8f528e..cb442cbd9d828619421babb281bfe9759edbca8a 100644 --- a/arch/x86/platform/pvh/enlighten.c +++ b/arch/x86/platform/pvh/enlighten.c @@ -8,6 +8,7 @@ #include #include #include +#include #include @@ -129,7 +130,7 @@ void __init xen_prepare_pvh(void) * This must not compile to "call memset" because memset() may be * instrumented. */ - __builtin_memset(&pvh_bootparams, 0, sizeof(pvh_bootparams)); + __inline_memset(&pvh_bootparams, 0, sizeof(pvh_bootparams)); hypervisor_specific_init(xen_guest); -- 2.51.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 16:11:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 16:11:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295065.1571761 (Exim 4.92) (envelope-from ) id 1wHOYW-0004VC-0j; Mon, 27 Apr 2026 16:11:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295065.1571761; Mon, 27 Apr 2026 16:11:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYV-0004UP-T0; Mon, 27 Apr 2026 16:11:31 +0000 Received: by outflank-mailman (input) for mailman id 1295065; Mon, 27 Apr 2026 16:11:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYU-0004Ro-QP for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 16:11:31 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHOYT-002114-PU for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 18:11:29 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8ab0-e002-0a2a0a5209dd-0a2a450688dc-4 for ; Mon, 27 Apr 2026 18:11:29 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef8ab0-7371-0a2a45060019-d561b338d974-3 for ; Mon, 27 Apr 2026 18:11:28 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wHOYA-00305I-Nh; Mon, 27 Apr 2026 18:11:10 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=n3ajKxuTrRUfsiVj5FBK8xcgDaSM+ZE9NLMVQk1nTrI=; b=QxsK4/f792XfNJZnw4R/py56Gm O+k4W/mihmFFVTUUZMfQ0nUdEg1WrfuqVZJxD3rPNqi2E+ytoTDyLexvIR3OCaQ/+pmWsRuUxFr4T aNisP+xzF1BD6JdDL1oaYcc+61KIfukuaFd0wFL+ZQnbvU0l5ugtrNZa/vAiOm1d6mVfMzqpTW9t0 dbS1QpK4yuAJPUmhTrvHjpw4cV+9EBagVyLamVRWDWm4F/CzeGTpRN+hRtmtP3P9HtOvJuDOJSzwy XhFHlnU3CLZ91x/hLBoIYlN5b9n1z1U5lML0P7HUP4GuJZCIhoyhSma7jlgvvI9FjN0pCsM8yA3rF Lk1TaFVw==; From: Mauricio Faria de Oliveira Date: Mon, 27 Apr 2026 13:10:57 -0300 Subject: [PATCH v2 1/3] x86/asm, x86/boot: Expose inline memcmp MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260427-pvh-kasan-inline-v2-1-2c57b8dcff6a@igalia.com> References: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> In-Reply-To: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-16d1c6/1777306289-91587D75-83C6BB67/0/0 X-purgate-type: clean X-purgate-size: 2327 Move the inline memcmp function, currently only available to boot code (boot/string.c), into the header with similar inline string functions (include/asm/string.h) so it may be reused. Add a _SETUP guard in string.h so not to include the 32/64-bit specific string headers in boot/ code (16-bit, real mode) and avoid build errors. Note: this memcmp() only returns 0/1, not -1/0/1 as regular memcmp(), as reported by David Laight. This should be addressed separately. Signed-off-by: Mauricio Faria de Oliveira --- arch/x86/boot/string.c | 6 ++---- arch/x86/include/asm/string.h | 12 ++++++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c index b25c6a9303b7314d5caf5c9306239811705294fe..bbee78637b349e42e9281d8df50d89d48f4490b9 100644 --- a/arch/x86/boot/string.c +++ b/arch/x86/boot/string.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "ctype.h" #include "string.h" @@ -31,10 +32,7 @@ int memcmp(const void *s1, const void *s2, size_t len) { - bool diff; - asm("repe cmpsb" - : "=@ccnz" (diff), "+D" (s1), "+S" (s2), "+c" (len)); - return diff; + return __inline_memcmp(s1, s2, len); } /* diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h index 9cb5aae7fba9ffcf0f5af8f939d30467750ccaa9..ae6c1f4fda858bd8370647557529d98c23305a53 100644 --- a/arch/x86/include/asm/string.h +++ b/arch/x86/include/asm/string.h @@ -2,11 +2,13 @@ #ifndef _ASM_X86_STRING_H #define _ASM_X86_STRING_H +#ifndef _SETUP #ifdef CONFIG_X86_32 # include #else # include #endif +#endif static __always_inline void *__inline_memcpy(void *to, const void *from, size_t len) { @@ -29,4 +31,14 @@ static __always_inline void *__inline_memset(void *s, int v, size_t n) return ret; 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From: Mauricio Faria de Oliveira Date: Mon, 27 Apr 2026 13:10:58 -0300 Subject: [PATCH v2 2/3] x86/cpuid: fix unbootable VMs by really inlining memcmp() in hypervisor_cpuid_base() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260427-pvh-kasan-inline-v2-2-2c57b8dcff6a@igalia.com> References: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> In-Reply-To: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-720697/1777306289-89EC0161-13F85792/0/0 X-purgate-type: clean X-purgate-size: 1458 Even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. The existing code is broken with gcc-14/15 but not gcc-12/13 (Ubuntu 25.10) and vmlinux no longer boots with CONFIG_PVH if CONFIG_KASAN_GENERIC is set. For testing purposes, if the size argument is reduced from 12 to 8 then the compiler decides to use the inline implementation; that shows results vary. Switch the builtin to the inline implementation to address it. Fixes: 416a33c9afce ("x86/cpu: fix unbootable VMs by inlining memcmp() in hypervisor_cpuid_base()") Signed-off-by: Mauricio Faria de Oliveira Reviewed-by: Juergen Gross --- arch/x86/include/asm/cpuid/api.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h index 44fa82e1267ce98c7f5f92f69b58f79e235f7261..c3bd1e51067346e817240b484dc0d0e5f02dcc4f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -203,7 +203,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves) * from PVH early boot code before instrumentation is set up * and memcmp() itself may be instrumented. */ - if (!__builtin_memcmp(sig, signature, 12) && + if (!__inline_memcmp(sig, signature, 12) && (leaves == 0 || ((eax - base) >= leaves))) return base; } -- 2.51.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 16:11:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 16:11:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295066.1571774 (Exim 4.92) (envelope-from ) id 1wHOYY-0004sD-6p; Mon, 27 Apr 2026 16:11:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295066.1571774; Mon, 27 Apr 2026 16:11:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYY-0004s6-3n; Mon, 27 Apr 2026 16:11:34 +0000 Received: by outflank-mailman (input) for mailman id 1295066; Mon, 27 Apr 2026 16:11:33 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOYU-0004Rn-R2 for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 16:11:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHOYT-005zON-Mx for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 18:11:29 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8ab0-5cb7-0a2a0a5109dd-0a2a4504bcd2-2 for ; Mon, 27 Apr 2026 18:11:29 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef8ab0-1dec-0a2a45040019-d561b3389644-3 for ; Mon, 27 Apr 2026 18:11:29 +0200 Received: from 186-249-145-131.shared.desktop.com.br ([186.249.145.131] helo=[192.168.1.66]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wHOY5-00305I-Tl; Mon, 27 Apr 2026 18:11:05 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Cc:To:Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject:From" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Cc:To:Content-Transfer-Encoding:Content-Type:MIME-Version: Message-Id:Date:Subject:From:Sender:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: In-Reply-To:References:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=gy93+YTuH8qqT2Cs7yYAisUzlA9SSxiG/wPDUCdgZNM=; b=s4dS23AEjRC4u6ydWlDMr7Wstw vWMSp8m3hwPPjm4zhbYwJjl0SqWK2bUyKpDOdxO6s7FFyT0L5gjMM4Un6O6o1s6pyuhgHI5rq8yjD lUbaOJYrQsU+hEUNVIo/jJQUXvRKxi5a1rJY4mw+b/RKzFdkr7rd7IIrFOWoKy5HRgzdBPTrDTHTo VN+h0tzCXpywZ6JRunVYUvNDGqNUcl45iNboQv3iB597lDFn5nsSnIKh6/xhlz7rMwKo/RGcfHODx 8upsoNcOJJR/YBvA8b2Nm3kPXVAZmdEsnGtUbA1VyEa+yX4wrevzoXYxb9UOwsUkYt8y3uHDi+VNl CyL/+SnA==; From: Mauricio Faria de Oliveira Subject: [PATCH v2 0/3] x86/pvh: fix unbootable VMs again (PVH + KASAN) Date: Mon, 27 Apr 2026 13:10:56 -0300 Message-Id: <20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJCK72kC/32NQQrCMBBFr1Jm7Ugzhoa68h7SRYyTZrCmJZGgl N7d2AO4fA/++ytkTsIZzs0KiYtkmWMFOjTggo0jo9wrA7XUtZoIlxLwYbONKHGSyNixt84Yr25 koM6WxF7ee/I6VA6SX3P67A9F/eyfWFHYouFO9fqktevpIqOdxB7d/IRh27YvLI8rLrEAAAA= X-Change-ID: 20260422-pvh-kasan-inline-6efac77f1b27 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Mauricio Faria de Oliveira X-Mailer: b4 0.14.2 X-purgate-ID: tlsNG-ebf023/1777306289-297793FF-18E73E25/0/0 X-purgate-type: clean X-purgate-size: 5611 The issue of unbootable VMs with CONFIG_PVH due to CONFIG_KASAN is back. Booting directly from vmlinux (instead of bzImage) now fails with gcc-14/15 (but works with gcc-12/13) if CONFIG_KASAN_GENERIC is set, on Ubuntu 25.10. The PVH code is required/supposed not to hit the KASAN memory access check in the kernel entry point as KASAN has not yet been setup, or an exception is hit and the boot fails. This was previously described and addressed with __builtin_mem{cmp,set}(): - commit 661362e3dcab ("xen, pvh: fix unbootable VMs (PVH + KASAN - AMD_MEM_ENCRYPT)") - commit 416a33c9afce ("x86/cpu: fix unbootable VMs by inlining memcmp() in hypervisor_cpuid_base()") - commit fbe5a6dfe492 ("xen, pvh: fix unbootable VMs by inlining memset() in xen_prepare_pvh()") However, even with __builtin the compiler may decide to use the out of line function instead of the inline implementation. So, that does not really fix the issue unconditionally, as it's being seen (details below). In order to address this, it's required to switch to inline implementations that do not depend on the compiler. There's such a memset in and memcmp in 'boot/string.c', now exposed in too. Use them instead of builtins in PVH entry. Testing: - Booting from vmlinux (fixed) and bzImage (still works) using allnoconfig + CONFIG_PVH + CONFIG_KASAN with gcc-12/13/14/15. - Building allyesconfig (check for issues with ). Details/Debugging: - Only CONFIG_PVH (works): make allnoconfig ./scripts/config \ -e 64BIT -e HYPERVISOR_GUEST -e PVH \ -e SERIAL_8250 -e SERIAL_8250_CONSOLE make olddefconfig make -j$(nproc) vmlinux qemu-system-x86_64 \ -accel kvm -nodefaults -nographic -serial stdio \ -kernel vmlinux -append 'console=ttyS0' ... SeaBIOS (version ...) Booting from ROM... Linux version ... ... - With CONFIG_KASAN (fails) ./scripts/config -e KASAN make olddefconfig make -j$(nproc) vmlinux qemu-system-x86_64 \ -accel kvm -nodefaults -nographic -serial stdio \ -kernel vmlinux -append 'console=ttyS0' ... SeaBIOS (version ...) Booting from ROM... - Debugging: Enable debug info and rebuild. QEMU: enable and wait for GDB, stop rebooting, remain running. qemu-system-x86_64 \ -s -S -no-reboot -no-shutdown \ gdb vmlinux (gdb) target remote localhost:1234 ... (gdb) c ... Thread 2 received signal SIGQUIT, Quit. ... (gdb) info threads Id Target Id Frame 1 Thread 1.1 (CPU#0 [running]) bytes_is_nonzero ( start=0xfffffbfff031eebe , size=1) at .../linux/mm/kasan/generic.c:98 * 2 Thread 1.2 (CPU#1 [halted ]) 0x00000000000fd0a9 in ?? () ... (gdb) thr 1 ... (gdb) bt #0 bytes_is_nonzero (start=0xfffffbfff031eebe , size=1) at .../linux/mm/kasan/generic.c:98 #1 memory_is_nonzero (start=0xfffffbfff031eebe, end=0xfffffbfff031eebf) at .../linux/mm/kasan/generic.c:115 #2 memory_is_poisoned_n (addr=0xffffffff818f75f0, size=8) at .../linux/mm/kasan/generic.c:140 #3 memory_is_poisoned (addr=0xffffffff818f75f0, size=8) at .../linux/mm/kasan/generic.c:172 #4 check_region_inline (addr=0xffffffff818f75f0, size=8, write=false, ret_ip=18446744071585002062) at .../linux/mm/kasan/generic.c:191 #5 kasan_check_range (addr=addr@entry=0xffffffff818f75f0, size=size@entry=8, write=write@entry=false, ret_ip=18446744071585002062) at .../linux/mm/kasan/generic.c:200 #6 0xffffffff813eb283 in __asan_loadN (addr=addr@entry=0xffffffff818f75f0, size=size@entry=8) at .../linux/mm/kasan/generic.c:278 #7 0xffffffff815df24e in memcmp (cs=cs@entry=0xffffffff818f75f0, ct=ct@entry=0x1be2fe4, count=, count@entry=12) at .../linux/lib/string.c:683 #8 0xffffffff81ba2323 in cpuid_base_hypervisor (sig=0xffffffff818f75f0 "XenVMMXenVMM", leaves=2) at .../linux/arch/x86/include/asm/cpuid/api.h:206 #9 xen_cpuid_base () at .../linux/arch/x86/include/asm/xen/hypervisor.h:46 #10 xen_prepare_pvh () at .../linux/arch/x86/platform/pvh/enlighten.c:119 #11 0x0000000001ba2588 in ?? () #12 0x0000000000000000 in ?? () (gdb) Frames #7-#8 show the non-builtin memcmp() (lib/string.c) was called even with __builtin_memcmp() being used in cpuid_base_hypervisor(). Signed-off-by: Mauricio Faria de Oliveira --- Changes in v2: - Add comment about the return value of __inline_memcmp() in patch 1. - Add 'Reviewed-by: Juergen Gross' in patches 2 and 3. - Link to v1: https://lore.kernel.org/r/20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com --- Mauricio Faria de Oliveira (3): x86/asm, x86/boot: Expose inline memcmp x86/cpuid: fix unbootable VMs by really inlining memcmp() in hypervisor_cpuid_base() x86/pvh: fix unbootable VMs by really inlining memset() in xen_prepare_pvh() arch/x86/boot/string.c | 6 ++---- arch/x86/include/asm/cpuid/api.h | 2 +- arch/x86/include/asm/string.h | 12 ++++++++++++ arch/x86/platform/pvh/enlighten.c | 3 ++- 4 files changed, 17 insertions(+), 6 deletions(-) --- base-commit: 6596a02b207886e9e00bb0161c7fd59fea53c081 change-id: 20260422-pvh-kasan-inline-6efac77f1b27 Best regards, -- Mauricio Faria de Oliveira From xen-devel-bounces@lists.xenproject.org Mon Apr 27 16:20:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 16:20:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295096.1571792 (Exim 4.92) (envelope-from ) id 1wHOgd-0006fv-7X; Mon, 27 Apr 2026 16:19:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295096.1571792; Mon, 27 Apr 2026 16:19:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOgd-0006fo-4E; Mon, 27 Apr 2026 16:19:55 +0000 Received: by outflank-mailman (input) for mailman id 1295096; Mon, 27 Apr 2026 16:19:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOgb-0006fi-SL for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 16:19:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHOgb-0022RI-1r for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 18:19:53 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69ef8c89-e002-0a2a0a5209dd-0a2a4509da96-48 for ; Mon, 27 Apr 2026 18:19:52 +0200 Received: from [213.97.179.56] (helo=fanzine2.igalia.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef8bb8-2497-0a2a45090019-d561b3389ec4-3 for ; Mon, 27 Apr 2026 18:15:52 +0200 Received: from maestria.local.igalia.com ([192.168.10.14] helo=mail.igalia.com) by fanzine2.igalia.com with esmtps (Cipher TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1wHOcP-0030BR-8k; Mon, 27 Apr 2026 18:15:32 +0200 Received: from webmail.service.igalia.com ([192.168.21.45]) by mail.igalia.com with esmtp (Exim) id 1wHOcM-006FYL-5M; Mon, 27 Apr 2026 18:15:32 +0200 Received: from localhost ([127.0.0.1] helo=webmail.igalia.com) by webmail.service.igalia.com with esmtp (Exim 4.98.2) (envelope-from ) id 1wHOcL-00000001Xic-26r1; Mon, 27 Apr 2026 18:15:29 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20170329 header.d=igalia.com header.i="@igalia.com" header.h="Content-Transfer-Encoding:Content-Type:Message-ID:References:In-Reply-To:Subject:Cc:To:From:Date:MIME-Version" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:Message-ID:References: In-Reply-To:Subject:Cc:To:From:Date:MIME-Version:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=0hYtNd1REaY7kPCVbF2AopZlByE4arJJCzMU7znjs7M=; b=FzN665rF4Chi+Kn8bLsYY10JrN cLD1jzVU/NkX/HndGO2QsiR1is0dFg/s9MCH+xY0EQVAskpRBh/Gx9ybBJsJEEWbTuUcBj45La9xQ 1Tp+ccQ6WNLoWMssA2kR0KJ15yeQlareX110uxJSfLt6A4iwo6kpCoETJuCJxZ4o/hMCPaZ8Ex+9b OKBf8NlH9V3+ys/Or4m8j8E8Z5yCqiSQOC3jvAUaUJBqsQm3n0neHAer9x7HSkRyNW/9gvRx/ZRz7 3VubcrpqQN85xtMlIeLMKkvSqNaUjCuMXmzdWFT6ZUYnTbN5bFFAes+xnFa3B31BlrsYFtt54ZLUg BLlEvSRg==; MIME-Version: 1.0 Date: Mon, 27 Apr 2026 13:15:29 -0300 From: Mauricio Faria de Oliveira To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Juergen Gross , Alexey Dobriyan , Boris Ostrovsky Cc: kernel-dev@igalia.com, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Subject: Re: [PATCH 0/3] x86/pvh: fix unbootable VMs again (PVH + KASAN) In-Reply-To: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> References: <20260422-pvh-kasan-inline-v1-0-7e6194344c92@igalia.com> Message-ID: <56145b8c64a645a2d4a7c6b74776779d@igalia.com> X-Sender: mfo@igalia.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Report: NO, Score=-2.2, Tests=ALL_TRUSTED=-3,BAYES_50=0.8 X-Spam-Score: -21 X-Spam-Bar: -- X-purgate-ID: tlsNG-bad1c0/1777306552-9357BA53-BC9582FF/0/0 X-purgate-type: clean X-purgate-size: 1483 On 2026-04-22 17:07, Mauricio Faria de Oliveira wrote: > The issue of unbootable VMs with CONFIG_PVH due to CONFIG_KASAN is back. > > Booting directly from vmlinux (instead of bzImage) now fails with gcc-14/15 > (but works with gcc-12/13) if CONFIG_KASAN_GENERIC is set, on Ubuntu 25.10. > > The PVH code is required/supposed not to hit the KASAN memory access check > in the kernel entry point as KASAN has not yet been setup, or an exception > is hit and the boot fails. > > This was previously described and addressed with __builtin_mem{cmp,set}(): > - commit 661362e3dcab ("xen, pvh: fix unbootable VMs (PVH + KASAN - AMD_MEM_ENCRYPT)") > - commit 416a33c9afce ("x86/cpu: fix unbootable VMs by inlining memcmp() in hypervisor_cpuid_base()") > - commit fbe5a6dfe492 ("xen, pvh: fix unbootable VMs by inlining memset() in xen_prepare_pvh()") > > However, even with __builtin the compiler may decide to use the out of line > function instead of the inline implementation. So, that does not really fix > the issue unconditionally, as it's being seen (details below). > > In order to address this, it's required to switch to inline implementations > that do not depend on the compiler. > > There's such a memset in and memcmp in 'boot/string.c', now > exposed in too. Use them instead of builtins in PVH entry. [...] v2: https://lore.kernel.org/r/20260427-pvh-kasan-inline-v2-0-2c57b8dcff6a@igalia.com -- Mauricio From xen-devel-bounces@lists.xenproject.org Mon Apr 27 16:23:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 16:23:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295107.1571800 (Exim 4.92) (envelope-from ) id 1wHOji-0008EL-Oa; Mon, 27 Apr 2026 16:23:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295107.1571800; Mon, 27 Apr 2026 16:23:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHOji-0008EE-Lo; Mon, 27 Apr 2026 16:23:06 +0000 Received: by outflank-mailman (input) for mailman id 1295107; Mon, 27 Apr 2026 16:23:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) 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List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310218; bh=Gdo90UdOw5JDNcbBc6CTpgqBoS99tJWdzzhKt47HDkg=; h=From:To:Cc:Subject:Date:From; b=U2+LLE02v2RJdGrHn64GqYJdP4+hDdO9CRQcGon9U+fg19LBxhX5PBepS5h9HJCqe szqGGe/Sn0Ja8ufrVfKBRayklpg7ZNqhD3AjlJFyhWTD2cy+E9nyVtxoXvU6RVePwS nC/EKNFwPrGycTqEuaSwxvd9NLoS3iznsIjTk0KPgTVc+veLovfoR+uQQZvkXu6BEL XY5HSP+s8CkmcaZnZCCWlv0qtPkuKqPRoos+3EvmYxD3lbF+eVbofOW/u0ribOc9N6 46gB4iCE7qS4DHXiu+LbPED9AO2rWWkmtG0xffEU92OaQJ+vWiy9PumgjbDE3AiKLE isfjlgjrnrghg== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 0/9] uaccess: Convert small fixed size copy_{to/from}_user() to scoped user access Date: Mon, 27 Apr 2026 19:13:41 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=7253; i=chleroy@kernel.org; h=from:subject:message-id; bh=Gdo90UdOw5JDNcbBc6CTpgqBoS99tJWdzzhKt47HDkg=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxkaMinl/6P42P3bc0Qj3v7nk1G4YbGg/rEse+BPv 7e7BNgWdJSyMIhxMciKKbIc/8+9a0bXl9T8qbv0YeawMoEMYeDiFICJRDExMmwV0vIK89sWnHjX Y4WN3O+gaTyvmP0m2koKTvi9YNORsocM/wPkn2xoM0q8N63lWvLNy/m/speGuG7LLGiQ1I6bVSB dxgQA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1777310221-3B97DDB1-9AAA5415/0/0 X-purgate-type: clean X-purgate-size: 7255 A lot of copy_from_user() and copy_to_user() perform copies of small fixed size pieces of data between kernel and userspace, and don't care about partial copies. copy_from_user() and copy_to_user() are big functions optimised for copying large amount of data, with cache management, etc ... This is often overkill for small copies that could just be inlined instead. What makes things a bit more tricky is that those copy functions are designed to handle partial copies in case of page fault. But among the 6000 callers of those functions, only 2% really care about the quantity of no-copied data that those functions return. All other ones fails as soon as the returned value is not 0, returning -EACCESS. So first step in this series is to introduce variants called copy_from_user_partial() and copy_to_user_partial() which will be called by the 2% users that care about the partial copy, then the original copy_from_user() and copy_to_user() are changed to return -EFAULT when the copy fails. Then the second step is to implement copy of small fixed-size data with scoped user access instead of calling the arch specific heavy user copy functions. Patch 5, can be split in different patches for each archicture or subsystem, but let's get a first feedback and agree on the principle. Christophe Leroy (CS GROUP) (9): uaccess: Split check_zeroed_user() out of usercopy.c uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery x86/umip: Be stricter in fixup_umip_exception() uaccess: Introduce copy_{to/from}_user_partial() uaccess: Switch to copy_{to/from}_user_partial() when relevant uaccess: Change copy_{to/from}_user to return -EFAULT x86: Add unsafe_copy_from_user() arm64: Add unsafe_copy_from_user() uaccess: Convert small fixed size copy_{to/from}_user() to scoped user access arch/alpha/Kconfig | 1 + arch/alpha/kernel/osf_sys.c | 4 +- arch/alpha/kernel/termios.c | 2 +- arch/arc/include/asm/uaccess.h | 3 - arch/arc/kernel/disasm.c | 2 +- arch/arm/include/asm/uaccess.h | 2 - arch/arm64/include/asm/gcs.h | 2 +- arch/arm64/include/asm/uaccess.h | 30 +++-- arch/arm64/kernel/signal32.c | 2 +- arch/csky/Kconfig | 1 + arch/hexagon/include/asm/uaccess.h | 3 - arch/loongarch/include/asm/uaccess.h | 3 - arch/m68k/include/asm/uaccess.h | 3 - arch/microblaze/include/asm/uaccess.h | 2 - arch/mips/include/asm/uaccess.h | 3 - arch/mips/kernel/rtlx.c | 8 +- arch/mips/kernel/vpe.c | 2 +- arch/nios2/include/asm/uaccess.h | 2 - arch/openrisc/include/asm/uaccess.h | 2 - arch/parisc/include/asm/uaccess.h | 3 - arch/powerpc/Kconfig | 1 + arch/powerpc/kvm/book3s_64_mmu_hv.c | 4 +- arch/powerpc/kvm/book3s_64_mmu_radix.c | 4 +- arch/powerpc/kvm/book3s_hv.c | 2 +- arch/riscv/Kconfig | 1 + arch/riscv/kernel/signal.c | 2 +- arch/s390/include/asm/idals.h | 8 +- arch/s390/include/asm/uaccess.h | 3 - arch/sh/include/asm/uaccess.h | 2 - arch/sparc/include/asm/uaccess_32.h | 3 - arch/sparc/include/asm/uaccess_64.h | 2 - arch/sparc/kernel/termios.c | 2 +- arch/um/include/asm/uaccess.h | 3 - arch/um/kernel/process.c | 2 +- arch/x86/Kconfig | 1 + arch/x86/include/asm/uaccess.h | 29 ++++- arch/x86/kernel/umip.c | 2 +- arch/x86/lib/insn-eval.c | 2 +- arch/x86/um/signal.c | 2 +- arch/xtensa/include/asm/uaccess.h | 2 - drivers/android/binder_alloc.c | 2 +- drivers/comedi/comedi_fops.c | 4 +- drivers/dma/idxd/cdev.c | 2 +- drivers/firmware/efi/test/efi_test.c | 2 +- drivers/fsi/fsi-scom.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +- drivers/gpu/drm/i915/i915_gem.c | 4 +- drivers/hwtracing/intel_th/msu.c | 2 +- drivers/misc/ibmvmc.c | 2 +- drivers/misc/vmw_vmci/vmci_host.c | 2 +- drivers/most/most_cdev.c | 2 +- drivers/net/ieee802154/ca8210.c | 4 +- drivers/net/wireless/ath/wil6210/debugfs.c | 2 +- .../intel/iwlwifi/pcie/gen1_2/trans.c | 2 +- drivers/net/wireless/ti/wlcore/debugfs.c | 2 +- drivers/ps3/ps3-lpm.c | 2 +- drivers/s390/crypto/zcrypt_api.h | 4 +- drivers/spi/spidev.c | 2 +- .../staging/media/atomisp/pci/atomisp_cmd.c | 8 +- drivers/tty/tty_ioctl.c | 14 +-- drivers/tty/vt/vc_screen.c | 4 +- drivers/usb/gadget/function/f_hid.c | 4 +- drivers/usb/gadget/function/f_printer.c | 2 +- drivers/vfio/vfio_iommu_type1.c | 4 +- drivers/xen/xenbus/xenbus_dev_frontend.c | 2 +- fs/namespace.c | 2 +- fs/ocfs2/dlmfs/dlmfs.c | 2 +- fs/proc/base.c | 4 +- include/asm-generic/uaccess.h | 2 - include/linux/bpfptr.h | 2 +- include/linux/sockptr.h | 4 +- include/linux/uaccess.h | 107 ++++++++++++++---- ipc/msg.c | 8 +- ipc/sem.c | 8 +- ipc/shm.c | 18 +-- kernel/regset.c | 2 +- kernel/sys.c | 4 +- lib/Kconfig | 3 + lib/Makefile | 4 +- lib/kfifo.c | 8 +- lib/{usercopy.c => usercheck.c} | 22 ---- lib/usercopy.c | 66 ----------- mm/kasan/kasan_test_c.c | 4 +- mm/memory.c | 2 +- net/x25/af_x25.c | 2 +- rust/helpers/uaccess.c | 6 +- sound/pci/emu10k1/emufx.c | 4 +- sound/pci/rme9652/hdsp.c | 6 +- sound/soc/intel/avs/probes.c | 6 +- sound/soc/sof/compress.c | 12 +- sound/soc/sof/sof-client-probes.c | 6 +- 92 files changed, 269 insertions(+), 288 deletions(-) copy lib/{usercopy.c => usercheck.c} (73%) -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:17:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:17:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295126.1571819 (Exim 4.92) (envelope-from ) id 1wHPa8-00077U-SX; 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Mon, 27 Apr 2026 19:17:15 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef9a19-2497-0a2a45090019-aceafc1fae06-3 for ; Mon, 27 Apr 2026 19:17:14 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 12679437DE; Mon, 27 Apr 2026 17:17:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AC974C2BCB5; Mon, 27 Apr 2026 17:16:59 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310232; bh=745VKRe61Lf8afs4o89V2mPmcfGcqMzEwAyCkwUFzR4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ccnzw+capg6i/qeCJEEZZnJkaeh2P8NEABjGdQ84B8/8ElHQuhaIfwHK4KyIZjuzW fShA2udW2NQ0Ct7kJfcn/Kb043ljqkq7hTjPsRqwiNPGH9FmgvMogRNjEATWGrG26g 6zW5qtX0OAMj+t+S60HkjDsyGYMrisyc3m/7o9VPvVvQnsaPOrT5y+ZTzyh8Xto7fx AWFGU9d3c0Mo3tNoddRUR02dQmZ5LMWSNNkmTWtszo39IueJ4zsAp4+3T5NcIhGntz oVxgjUbjxhRTuJF8KweLMZaWvhi+rfu1/RR3XrUIQOPEazAae4t8SpoXJ0czDjJbhT 7qOjNG8l7cqnA== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 1/9] uaccess: Split check_zeroed_user() out of usercopy.c Date: Mon, 27 Apr 2026 19:13:42 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; 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That commit added function check_zeroed_user() into the same file. Move that function into a new file named usercheck.c, so that next patch can change usercopy.c build to a conditional build. Signed-off-by: Christophe Leroy (CS GROUP) --- lib/Makefile | 1 + lib/{usercopy.c => usercheck.c} | 22 ------------ lib/usercopy.c | 62 --------------------------------- 3 files changed, 1 insertion(+), 84 deletions(-) copy lib/{usercopy.c => usercheck.c} (73%) diff --git a/lib/Makefile b/lib/Makefile index f33a24bf1c19..7c0334d7675b 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -59,6 +59,7 @@ obj-y += bcd.o sort.o parser.o debug_locks.o random32.o \ percpu-refcount.o rhashtable.o base64.o \ once.o refcount.o rcuref.o usercopy.o errseq.o bucket_locks.o \ generic-radix-tree.o bitmap-str.o +obj-y += usercheck.o obj-y += string_helpers.o obj-y += hexdump.o obj-$(CONFIG_TEST_HEXDUMP) += test_hexdump.o diff --git a/lib/usercopy.c b/lib/usercheck.c similarity index 73% copy from lib/usercopy.c copy to lib/usercheck.c index b00a3a957de6..15b0d9a18435 100644 --- a/lib/usercopy.c +++ b/lib/usercheck.c @@ -2,32 +2,10 @@ #include #include #include -#include -#include #include -#include -#include #include #include -/* out-of-line parts */ - -#if !defined(INLINE_COPY_FROM_USER) -unsigned long _copy_from_user(void *to, const void __user *from, unsigned long n) -{ - return _inline_copy_from_user(to, from, n); -} -EXPORT_SYMBOL(_copy_from_user); -#endif - -#if !defined(INLINE_COPY_TO_USER) -unsigned long _copy_to_user(void __user *to, const void *from, unsigned long n) -{ - return _inline_copy_to_user(to, from, n); -} -EXPORT_SYMBOL(_copy_to_user); -#endif - /** * check_zeroed_user: check if a userspace buffer only contains zero bytes * @from: Source address, in userspace. diff --git a/lib/usercopy.c b/lib/usercopy.c index b00a3a957de6..7a93f56d81dd 100644 --- a/lib/usercopy.c +++ b/lib/usercopy.c @@ -1,14 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 -#include -#include #include -#include -#include -#include -#include -#include #include -#include /* out-of-line parts */ @@ -27,57 +19,3 @@ unsigned long _copy_to_user(void __user *to, const void *from, unsigned long n) } EXPORT_SYMBOL(_copy_to_user); #endif - -/** - * check_zeroed_user: check if a userspace buffer only contains zero bytes - * @from: Source address, in userspace. - * @size: Size of buffer. - * - * This is effectively shorthand for "memchr_inv(from, 0, size) == NULL" for - * userspace addresses (and is more efficient because we don't care where the - * first non-zero byte is). - * - * Returns: - * * 0: There were non-zero bytes present in the buffer. - * * 1: The buffer was full of zero bytes. - * * -EFAULT: access to userspace failed. - */ -int check_zeroed_user(const void __user *from, size_t size) -{ - unsigned long val; - uintptr_t align = (uintptr_t) from % sizeof(unsigned long); - - if (unlikely(size == 0)) - return 1; - - from -= align; - size += align; - - if (!user_read_access_begin(from, size)) - return -EFAULT; - - unsafe_get_user(val, (unsigned long __user *) from, err_fault); - if (align) - val &= ~aligned_byte_mask(align); - - while (size > sizeof(unsigned long)) { - if (unlikely(val)) - goto done; - - from += sizeof(unsigned long); - size -= sizeof(unsigned long); - - unsafe_get_user(val, (unsigned long __user *) from, err_fault); - } - - if (size < sizeof(unsigned long)) - val &= aligned_byte_mask(size); - -done: - user_read_access_end(); - return (val == 0); -err_fault: - user_read_access_end(); - return -EFAULT; -} -EXPORT_SYMBOL(check_zeroed_user); -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:17:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:17:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295138.1571829 (Exim 4.92) (envelope-from ) id 1wHPaT-0007hv-9Y; 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s=k20201202; t=1777310252; bh=2A3pp34TaOBrBLCc7n3D/0VUADnJLMBU+ywYlmILDq0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZa57++f4J+GqwvmN6cOlz8Y1H7GNDryi4ZRD+CJk+hBQU7Iobf+tE7/GXYinO2zm iEth1up0MDkLOAxzQiz5mqcfHR3P06TXmSl3XzIFaDPQuFHo3UkJmapo/kW88jy3aQ 3aznlfwGIxcYhdaW4V5tVjatVhcyAHWEKfRp+CGH8zAHmw+dzciaz6iCaNPprV57bn 8osxBss4ioepFyLm+2kR+UIAIIrgH8FbX9Dl39gcSvCHEwtnH4JUk+pOBX2jvh7BG3 7M8Bd9CW5MVAHSPSRYqg08B9eeC3kSJm80fJ6QSe91ed2+rsgDjp3uvvAKjOOY8v3a 6k1/LUiGGTPUw== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery Date: Mon, 27 Apr 2026 19:13:43 +0200 Message-ID: <9fe875d2f55af59c12708336c571a46038528678.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=18999; i=chleroy@kernel.org; h=from:subject:message-id; bh=2A3pp34TaOBrBLCc7n3D/0VUADnJLMBU+ywYlmILDq0=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxl942rk7qV/z0wpsopc/EjgrOKra6+/qq3zDzp1o 3Cx5MQvcR2lLAxiXAyyYoosx/9z75rR9SU1f+oufZg5rEwgQxi4OAVgIuKajAx/ndKvMf5+vP6+ 0DUOzaI/8u977T8/tn8jYyzy8FHU4dqzDP9dp5oyP1vg/Kml4FbUFMnSvxpN1/NNNGPF159+JNd bVcIDAA== X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1777310254-2BD6C3FF-6F0ACA7D/0/0 X-purgate-type: clean X-purgate-size: 19001 Among the 21 architectures supported by the kernel, 16 define both INLINE_COPY_TO_USER and INLINE_COPY_FROM_USER while the 5 other ones don't define any of the two. To simplify and reduce risk of mistakes, convert them to a single kconfig item named CONFIG_ARCH_WANTS_NOINLINE_COPY which will be selected by the 5 architectures that don't want inlined copy. To minimise complication in a later patch, also remove ifdefery and replace it with IS_ENABLED(). Signed-off-by: Christophe Leroy (CS GROUP) --- arch/alpha/Kconfig | 1 + arch/arc/include/asm/uaccess.h | 3 --- arch/arm/include/asm/uaccess.h | 2 -- arch/arm64/include/asm/uaccess.h | 3 --- arch/csky/Kconfig | 1 + arch/hexagon/include/asm/uaccess.h | 3 --- arch/loongarch/include/asm/uaccess.h | 3 --- arch/m68k/include/asm/uaccess.h | 3 --- arch/microblaze/include/asm/uaccess.h | 2 -- arch/mips/include/asm/uaccess.h | 3 --- arch/nios2/include/asm/uaccess.h | 2 -- arch/openrisc/include/asm/uaccess.h | 2 -- arch/parisc/include/asm/uaccess.h | 3 --- arch/powerpc/Kconfig | 1 + arch/riscv/Kconfig | 1 + arch/s390/include/asm/uaccess.h | 3 --- arch/sh/include/asm/uaccess.h | 2 -- arch/sparc/include/asm/uaccess_32.h | 3 --- arch/sparc/include/asm/uaccess_64.h | 2 -- arch/um/include/asm/uaccess.h | 3 --- arch/x86/Kconfig | 1 + arch/xtensa/include/asm/uaccess.h | 2 -- include/asm-generic/uaccess.h | 2 -- include/linux/uaccess.h | 32 ++++++++++++--------------- lib/Kconfig | 3 +++ lib/Makefile | 3 ++- lib/usercopy.c | 4 ---- rust/helpers/uaccess.c | 2 +- 28 files changed, 25 insertions(+), 70 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 7b7dafe7d9df..65e533cead6b 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -11,6 +11,7 @@ config ALPHA select ARCH_NO_PREEMPT select ARCH_NO_SG_CHAIN select ARCH_USE_CMPXCHG_LOCKREF + select ARCH_WANTS_NOINLINE_COPY_USER select FORCE_PCI select PCI_DOMAINS if PCI select PCI_SYSCALL if PCI diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h index 1e8809ea000a..e8b161b37a03 100644 --- a/arch/arc/include/asm/uaccess.h +++ b/arch/arc/include/asm/uaccess.h @@ -628,9 +628,6 @@ static inline unsigned long __clear_user(void __user *to, unsigned long n) return res; } -#define INLINE_COPY_TO_USER -#define INLINE_COPY_FROM_USER - #define __clear_user __clear_user #include diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index d6ae80b5df36..7280c162bb71 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -616,8 +616,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) } #define __clear_user(addr, n) (memset((void __force *)addr, 0, n), 0) #endif -#define INLINE_COPY_TO_USER -#define INLINE_COPY_FROM_USER static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) { diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index b0c83a08dda9..1e20ec91b56f 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -456,9 +456,6 @@ do { \ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ } while (0) -#define INLINE_COPY_TO_USER -#define INLINE_COPY_FROM_USER - extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n) { diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index 4331313a42ff..d010d7eb47bf 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -40,6 +40,7 @@ config CSKY select ARCH_NEED_CMPXCHG_1_EMU select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace) select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT + select ARCH_WANTS_NOINLINE_COPY_USER select COMMON_CLK select CLKSRC_MMIO select CSKY_MPINTC if CPU_CK860 diff --git a/arch/hexagon/include/asm/uaccess.h b/arch/hexagon/include/asm/uaccess.h index bff77efc0d9a..4bf863217636 100644 --- a/arch/hexagon/include/asm/uaccess.h +++ b/arch/hexagon/include/asm/uaccess.h @@ -26,9 +26,6 @@ unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n); unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n); -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - __kernel_size_t __clear_user_hexagon(void __user *dest, unsigned long count); #define __clear_user(a, s) __clear_user_hexagon((a), (s)) diff --git a/arch/loongarch/include/asm/uaccess.h b/arch/loongarch/include/asm/uaccess.h index 438269313e78..72a04ac88549 100644 --- a/arch/loongarch/include/asm/uaccess.h +++ b/arch/loongarch/include/asm/uaccess.h @@ -292,9 +292,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) return __copy_user((__force void *)to, from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - /* * __clear_user: - Zero a block of memory in user space, with less checking. * @addr: Destination address, in user space. diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h index 64914872a5c9..20e249a6ad07 100644 --- a/arch/m68k/include/asm/uaccess.h +++ b/arch/m68k/include/asm/uaccess.h @@ -377,9 +377,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) return __constant_copy_to_user(to, from, n); return __generic_copy_to_user(to, from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ type *__gk_dst = (type *)(dst); \ diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index 3aab2f17e046..3355f541e12a 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h @@ -250,8 +250,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) { return __copy_tofrom_user(to, (__force const void __user *)from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER /* * Copy a null terminated string from userspace. diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index c0cede273c7c..8714caefbac8 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -433,9 +433,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) return __cu_len_r; } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - extern __kernel_size_t __bzero(void __user *addr, __kernel_size_t size); /* diff --git a/arch/nios2/include/asm/uaccess.h b/arch/nios2/include/asm/uaccess.h index 6ccc9a232c23..46d7312a1c96 100644 --- a/arch/nios2/include/asm/uaccess.h +++ b/arch/nios2/include/asm/uaccess.h @@ -57,8 +57,6 @@ extern unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n); -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER extern long strncpy_from_user(char *__to, const char __user *__from, long __len); diff --git a/arch/openrisc/include/asm/uaccess.h b/arch/openrisc/include/asm/uaccess.h index d6500a374e18..c84effde867a 100644 --- a/arch/openrisc/include/asm/uaccess.h +++ b/arch/openrisc/include/asm/uaccess.h @@ -218,8 +218,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long size) { return __copy_tofrom_user((__force void *)to, from, size); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER extern unsigned long __clear_user(void __user *addr, unsigned long size); diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h index 6c531d2c847e..1dd6a1dd653f 100644 --- a/arch/parisc/include/asm/uaccess.h +++ b/arch/parisc/include/asm/uaccess.h @@ -197,7 +197,4 @@ unsigned long __must_check raw_copy_to_user(void __user *dst, const void *src, unsigned long len); unsigned long __must_check raw_copy_from_user(void *dst, const void __user *src, unsigned long len); -#define INLINE_COPY_TO_USER -#define INLINE_COPY_FROM_USER - #endif /* __PARISC_UACCESS_H */ diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index e93df95b79e7..6816f402fe3d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -187,6 +187,7 @@ config PPC select ARCH_WANT_LD_ORPHAN_WARN select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP if PPC_RADIX_MMU select ARCH_WANTS_MODULES_DATA_IN_VMALLOC if PPC_BOOK3S_32 || PPC_8xx + select ARCH_WANTS_NOINLINE_COPY_USER select ARCH_WEAK_RELEASE_ACQUIRE select AUDIT_ARCH_COMPAT_GENERIC select BINFMT_ELF diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d235396c4514..492b920c1a51 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -88,6 +88,7 @@ config RISCV select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP select ARCH_WANTS_NO_INSTR + select ARCH_WANTS_NOINLINE_COPY_USER if MMU select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE select ARCH_WEAK_RELEASE_ACQUIRE if ARCH_USE_QUEUED_SPINLOCKS select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h index dff035372601..2e0472c20da0 100644 --- a/arch/s390/include/asm/uaccess.h +++ b/arch/s390/include/asm/uaccess.h @@ -30,9 +30,6 @@ void debug_user_asce(int exit); #define uaccess_kmsan_or_inline __always_inline #endif -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - static uaccess_kmsan_or_inline __must_check unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long size) { diff --git a/arch/sh/include/asm/uaccess.h b/arch/sh/include/asm/uaccess.h index a79609eb14be..0cd75308e6d3 100644 --- a/arch/sh/include/asm/uaccess.h +++ b/arch/sh/include/asm/uaccess.h @@ -95,8 +95,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) { return __copy_user((__force void *)to, from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER /* * Clear the area and return remaining number of bytes diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h index 43284b6ec46a..e01f43c6421c 100644 --- a/arch/sparc/include/asm/uaccess_32.h +++ b/arch/sparc/include/asm/uaccess_32.h @@ -190,9 +190,6 @@ static inline unsigned long raw_copy_from_user(void *to, const void __user *from return __copy_user((__force void __user *) to, from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - static inline unsigned long __clear_user(void __user *addr, unsigned long size) { unsigned long ret; diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h index b825a5dd0210..62ee0b074fec 100644 --- a/arch/sparc/include/asm/uaccess_64.h +++ b/arch/sparc/include/asm/uaccess_64.h @@ -231,8 +231,6 @@ unsigned long __must_check raw_copy_from_user(void *to, unsigned long __must_check raw_copy_to_user(void __user *to, const void *from, unsigned long size); -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER unsigned long __must_check raw_copy_in_user(void __user *to, const void __user *from, diff --git a/arch/um/include/asm/uaccess.h b/arch/um/include/asm/uaccess.h index 0df9ea4abda8..1e14260c7f0f 100644 --- a/arch/um/include/asm/uaccess.h +++ b/arch/um/include/asm/uaccess.h @@ -27,9 +27,6 @@ static inline int __access_ok(const void __user *ptr, unsigned long size); #define __access_ok __access_ok #define __clear_user __clear_user -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER - #include static inline int __access_ok(const void __user *ptr, unsigned long size) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f3f7cb01d69d..c1e58d8c6864 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -143,6 +143,7 @@ config X86 select ARCH_WANTS_CLOCKSOURCE_READ_INLINE if X86_64 select ARCH_WANTS_DYNAMIC_TASK_STRUCT select ARCH_WANTS_NO_INSTR + select ARCH_WANTS_NOINLINE_COPY_USER select ARCH_WANT_GENERAL_HUGETLB select ARCH_WANT_HUGE_PMD_SHARE if X86_64 select ARCH_WANT_LD_ORPHAN_WARN diff --git a/arch/xtensa/include/asm/uaccess.h b/arch/xtensa/include/asm/uaccess.h index 56aec6d504fe..f9e1623a7be9 100644 --- a/arch/xtensa/include/asm/uaccess.h +++ b/arch/xtensa/include/asm/uaccess.h @@ -237,8 +237,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) prefetch(from); return __xtensa_copy_user((__force void *)to, from, n); } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER /* * We need to return the number of bytes not cleared. Our memset() diff --git a/include/asm-generic/uaccess.h b/include/asm-generic/uaccess.h index b276f783494c..fb33a71fd24e 100644 --- a/include/asm-generic/uaccess.h +++ b/include/asm-generic/uaccess.h @@ -91,8 +91,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) memcpy((void __force *)to, from, n); return 0; } -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER #endif /* CONFIG_UACCESS_MEMCPY */ /* diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index 56328601218c..bd1201c81d94 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -83,8 +83,8 @@ * with that. They should not be used directly; they are used to implement * the 6 functions (copy_{to,from}_user(), __copy_{to,from}_user_inatomic()) * that are used instead. Out of those, __... ones are inlined. Plain - * copy_{to,from}_user() might or might not be inlined. If you want them - * inlined, have asm/uaccess.h define INLINE_COPY_{TO,FROM}_USER. + * copy_{to,from}_user() might or might not be inlined. If you don't want them + * inlined, select CONFIG_ARCH_WANTS_NOINLINE_COPY_USER. * * NOTE: only copy_from_user() zero-pads the destination in case of short copy. * Neither __copy_from_user() nor __copy_from_user_inatomic() zero anything @@ -157,8 +157,8 @@ __copy_to_user(void __user *to, const void *from, unsigned long n) } /* - * Architectures that #define INLINE_COPY_TO_USER use this function - * directly in the normal copy_to/from_user(), the other ones go + * Architectures that don't select CONFIG_ARCH_WANTS_NOINLINE_COPY_USER use + * this function directly in the normal copy_to/from_user(), the other ones go * through an extern _copy_to/from_user(), which expands the same code * here. */ @@ -190,10 +190,9 @@ _inline_copy_from_user(void *to, const void __user *from, unsigned long n) memset(to + (n - res), 0, res); return res; } -#ifndef INLINE_COPY_FROM_USER + extern __must_check unsigned long _copy_from_user(void *, const void __user *, unsigned long); -#endif static inline __must_check unsigned long _inline_copy_to_user(void __user *to, const void *from, unsigned long n) @@ -207,21 +206,19 @@ _inline_copy_to_user(void __user *to, const void *from, unsigned long n) } return n; } -#ifndef INLINE_COPY_TO_USER + extern __must_check unsigned long _copy_to_user(void __user *, const void *, unsigned long); -#endif static __always_inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) { if (!check_copy_size(to, n, false)) return n; -#ifdef INLINE_COPY_FROM_USER - return _inline_copy_from_user(to, from, n); -#else - return _copy_from_user(to, from, n); -#endif + if (IS_ENABLED(ARCH_WANTS_NOINLINE_COPY_USER)) + return _copy_from_user(to, from, n); + else + return _inline_copy_from_user(to, from, n); } static __always_inline unsigned long __must_check @@ -230,11 +227,10 @@ copy_to_user(void __user *to, const void *from, unsigned long n) if (!check_copy_size(from, n, true)) return n; -#ifdef INLINE_COPY_TO_USER - return _inline_copy_to_user(to, from, n); -#else - return _copy_to_user(to, from, n); -#endif + if (IS_ENABLED(ARCH_WANTS_NOINLINE_COPY_USER)) + return _copy_to_user(to, from, n); + else + return _inline_copy_to_user(to, from, n); } #ifndef copy_mc_to_kernel diff --git a/lib/Kconfig b/lib/Kconfig index 00a9509636c1..a2e07d4dd2bf 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -68,6 +68,9 @@ config ARCH_HAS_STRNCPY_FROM_USER config ARCH_HAS_STRNLEN_USER bool +config ARCH_WANTS_NOINLINE_COPY_USER + bool + config GENERIC_STRNCPY_FROM_USER def_bool !ARCH_HAS_STRNCPY_FROM_USER diff --git a/lib/Makefile b/lib/Makefile index 7c0334d7675b..f4d577910671 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -57,9 +57,10 @@ obj-y += bcd.o sort.o parser.o debug_locks.o random32.o \ list_sort.o uuid.o iov_iter.o clz_ctz.o \ bsearch.o find_bit.o llist.o lwq.o memweight.o kfifo.o \ percpu-refcount.o rhashtable.o base64.o \ - once.o refcount.o rcuref.o usercopy.o errseq.o bucket_locks.o \ + once.o refcount.o rcuref.o errseq.o bucket_locks.o \ generic-radix-tree.o bitmap-str.o obj-y += usercheck.o +obj-$(CONFIG_ARCH_WANTS_NOINLINE_COPY_USER) += usercopy.o obj-y += string_helpers.o obj-y += hexdump.o obj-$(CONFIG_TEST_HEXDUMP) += test_hexdump.o diff --git a/lib/usercopy.c b/lib/usercopy.c index 7a93f56d81dd..d2deb4b0a3c5 100644 --- a/lib/usercopy.c +++ b/lib/usercopy.c @@ -4,18 +4,14 @@ /* out-of-line parts */ -#if !defined(INLINE_COPY_FROM_USER) unsigned long _copy_from_user(void *to, const void __user *from, unsigned long n) { return _inline_copy_from_user(to, from, n); } EXPORT_SYMBOL(_copy_from_user); -#endif -#if !defined(INLINE_COPY_TO_USER) unsigned long _copy_to_user(void __user *to, const void *from, unsigned long n) { return _inline_copy_to_user(to, from, n); } EXPORT_SYMBOL(_copy_to_user); -#endif diff --git a/rust/helpers/uaccess.c b/rust/helpers/uaccess.c index d9625b9ee046..01de4fbbcc84 100644 --- a/rust/helpers/uaccess.c +++ b/rust/helpers/uaccess.c @@ -14,7 +14,7 @@ rust_helper_copy_to_user(void __user *to, const void *from, unsigned long n) return copy_to_user(to, from, n); } -#ifdef INLINE_COPY_FROM_USER +#ifndef CONFIG_ARCH_WANTS_NOINLINE_COPY_USER __rust_helper unsigned long rust_helper__copy_from_user(void *to, const void __user *from, unsigned long n) { -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:18:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:18:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295148.1571838 (Exim 4.92) (envelope-from ) id 1wHPap-0008Fj-Iy; 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s=k20201202; t=1777310275; bh=W5kkD2qOaf9p6y+JEmiY6YQ2keZoelr0Bif5djAA9uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dWIdgH61f3FZjJK5/4M8qA2Z3PdTv2PxzuZWcauBhk9DdVxbBkauIdrH8T66hguCp RKByLYUodinjcBlbYhttuH2LGK1CACi5Chox46drqrLCValqYMs6iS6hvWfa8xjP86 SRX8mzMn7HjzzZ5PMWVnIWvrJFLR/iyEIDn4Oi2BFSrDeboqSnIrX7WfhL6Ub+tY2g I0hH+wNzy6c//f0TkDzcuax+fX8WXY8rTh4FJ51XM25PFd/tzjClOdpIOdXk4NjGqA oBIlgUIOAdKFgg5RvdKRR4Lqk1Q+lbng1I1sXXDqtORIX/zFE6g7Yv8vrz97KbzGDV XrdmpG3tF9W3Q== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 3/9] x86/umip: Be stricter in fixup_umip_exception() Date: Mon, 27 Apr 2026 19:13:44 +0200 Message-ID: <9e8e43d4f81d8f8b6f68311f1c6f859d718d36e4.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1000; i=chleroy@kernel.org; h=from:subject:message-id; bh=W5kkD2qOaf9p6y+JEmiY6YQ2keZoelr0Bif5djAA9uo=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxnda1Jdur5TX+RgO1P4hHufdruHR358Lz3BYPORx G8pRRuZOkpZGMS4GGTFFFmO/+feNaPrS2r+1F36MHNYmUCGMHBxCsBE9kkxMjTtX+zW2RH44ELN UZ/TjtH3Kj+Uzdh01e2y7qEZTgrchx8y/E9kjcpJ3dj/tNZwXUT0XHGmyS9k3dX75mj427u7JaY VMwMA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1777310277-896CC161-549AF82A/0/0 X-purgate-type: clean X-purgate-size: 1002 fixup_umip_exception() calls copy_to_user() and checks whether the returned value is strictly positive. A subsequent patch will change the return of copy_to_user() to return -EFAULT in case of error. Change the test to checking that the result is not 0. At the time being copy_to_user() return an unsigned value so 'strictly positive' is the same as 'not 0'. Signed-off-by: Christophe Leroy (CS GROUP) --- arch/x86/kernel/umip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c index 3ce99cbcf187..dfff28ea1dea 100644 --- a/arch/x86/kernel/umip.c +++ b/arch/x86/kernel/umip.c @@ -409,7 +409,7 @@ bool fixup_umip_exception(struct pt_regs *regs) return false; nr_copied = copy_to_user(uaddr, dummy_data, dummy_data_size); - if (nr_copied > 0) { + if (nr_copied) { /* * If copy fails, send a signal and tell caller that * fault was fixed up. -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:18:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:18:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295154.1571845 (Exim 4.92) (envelope-from ) id 1wHPbB-0000Tl-Nv; Mon, 27 Apr 2026 17:18:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295154.1571845; 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Mon, 27 Apr 2026 19:18:19 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 8B93C440C2; Mon, 27 Apr 2026 17:18:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08C06C2BCF4; Mon, 27 Apr 2026 17:17:56 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310297; bh=G/2eQ9TI5TAejE5IgsfdvVcfACCawPpecEdM1VXM32k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JDwlcHynPBKJgZEQOCWtilxNz5OJTbEC9ImCjJuQT3RnOoZjD4+90hMORF2q1smV0 ZZwStmTz2ZWfCFTglmd/E7DTmKQiqUkyq6DoW4QkOcmP8LtfpYhN9V4ZMaLV1xjKUX qf/gxqJdT3gAPMXuYRhHcRDH0KM3YGUgvPXpdKncm5DePPHjb0VOG6buq4s8MreRM+ EZo8pRxSQAzQ5kujjD1AkNCv3dgeUm7ZrfC1oOr8cnbPHFYMiYdejiO8B5iigWhrca 1OgKQbcauQ7QAB8qeF6Zf8CM71cpuIXWBUm7GSS+m87r+rFbtJTWOdD0Mn8qIs0Vfn 3JDYXNLvVgu3g== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 4/9] uaccess: Introduce copy_{to/from}_user_partial() Date: Mon, 27 Apr 2026 19:13:45 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1585; i=chleroy@kernel.org; h=from:subject:message-id; bh=G/2eQ9TI5TAejE5IgsfdvVcfACCawPpecEdM1VXM32k=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxmjMKmwhcOl/KmCyQK3t3e2vTXauaOc++38fue5J 1/fnLd3d0cpC4MYF4OsmCLL8f/cu2Z0fUnNn7pLH2YOKxPIEAYuTgGYyD5HRoZnIqUtqi/uzJzx /elrrqTduXsuSM05kFXcMu1CQyFnzPFOhv/RJewtZeu89EsObX+ieXizf2Xo8RNCJwMOumbxCC5 Mr+EBAA== X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777310299-490B3A53-41D4CE8E/0/0 X-purgate-type: clean X-purgate-size: 1587 Today there are approximately 3000 calls for copy_to_user() and 3000 calls to copy_from_user(). The majority of callers of copy_{to/from}_user() don't care about the return value, they only check whether it is 0 or not, and when it is not 0 they handle it as a -EACCES. In order to allow better optimisation of copy_{to/from}_user() when the size of the copy is known at build time, create new fonctions named copy_{to/from}_user_partial() to be used by the few callers that are interested in partial copies and need to now how many bytes remain at the end of the copy. For the time being it is just the same as copy_{to/from}_user(). Signed-off-by: Christophe Leroy (CS GROUP) --- include/linux/uaccess.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index bd1201c81d94..2d37173782b3 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -221,6 +221,8 @@ copy_from_user(void *to, const void __user *from, unsigned long n) return _inline_copy_from_user(to, from, n); } +#define copy_from_user_partial copy_from_user + static __always_inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) { @@ -233,6 +235,8 @@ copy_to_user(void __user *to, const void *from, unsigned long n) return _inline_copy_to_user(to, from, n); } +#define copy_to_user_partial copy_to_user + #ifndef copy_mc_to_kernel /* * Without arch opt-in this generic copy_mc_to_kernel() will not handle -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:18:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:18:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295161.1571856 (Exim 4.92) (envelope-from ) id 1wHPbR-0000sh-5P; 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Mon, 27 Apr 2026 19:18:34 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef9a69-229c-0a2a45070019-aceafc1fbfe4-3 for ; Mon, 27 Apr 2026 19:18:34 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id CA32543766; Mon, 27 Apr 2026 17:18:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31802C2BCF4; Mon, 27 Apr 2026 17:18:17 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310312; bh=ykb2AFsFlD4OWf31v2pDwxXHhaD6RIAaFdGo66PLJJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VVYqWJ9y3YbZh7SD1t9FZfVCwwasAh9H5TbUiJGW0WBLo8QeGfk22g4AfRfUPPWqU Aoc8LlWA/aSMgy9dc9PmA3AGYLZUU5W7rwnOfj07vTIJFBwTSF9yiiM4DvkX1/MBQu db67uJWBEaWIGjEVq27JeF6TjgL+v+lGhLnh5fqlRmMpg7nUlTADncH5wD5lENeOzx AnSeuD99A4n/GOBDGHS6YE5DsSz3FUwz6A+06zvkQMMGJou23G/4wgzSuudbgGF0+O Dmr1a73NapDMfoHC1BZSTwINTaDSDCQgyzzeSi4wB6M2kWQzSVBg/2nN/ihP2WWDMt aSuTg8ZLqpxJg== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 5/9] uaccess: Switch to copy_{to/from}_user_partial() when relevant Date: Mon, 27 Apr 2026 19:13:46 +0200 Message-ID: <289b424e243ba2c4139ea04009cf8b9c448a87ff.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=54038; i=chleroy@kernel.org; h=from:subject:message-id; bh=ykb2AFsFlD4OWf31v2pDwxXHhaD6RIAaFdGo66PLJJQ=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxnT8I410Uhy0qp/RVcua12akXn97Jr7B907GK1ex fMIJG+93FHKwiDGxSArpshy/D/3rhldX1Lzp+7Sh5nDygQyhIGLUwAmYtrO8D+j/Q7HhgvHVxxp 95Tc/nBGsdAKdauVyxVmaezQe2149M4LRoa79udnSurd+iisF/Rta6/v3KKjtnV8bRpT1XZWfDZ UYGEHAA== X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1777310314-14450C48-12FBA062/0/0 X-purgate-type: clean X-purgate-size: 54040 In a subsequent patch, copy_{to/from}_user() will be modified to return -EFAULT when copy fails. Among the 6000 calls to copy_{to/from}_user(), around 2% rely on copy_{to/from}_user() doing partial copies and returning amount of not copied bytes. Change those users to copy_{to/from}_user_partial(). This change was done based on whether callers assign the returned value to a variable or just check whether the return value is 0 or not. Several of them only use it for debug to print the amount of bytes not copied. Those could maybe be changed to stop reporting that amount and not be converted to partial copy. Some not trivial handling might have been unecessarily converted. This is not a problem and they can be converted back later for better performance. The callers where located with following commands then reviewed one by one: sed -i s/"return copy_to_user("/"return copy_to_user_partial("/g `git grep -l "return copy_to_user("` sed -i s/" = copy_to_user("/" = copy_to_user_partial("/g `git grep -l " = copy_to_user("` sed -i s/" += copy_to_user("/" += copy_to_user_partial("/g `git grep -l " += copy_to_user("` sed -i s/" -= copy_to_user("/" -= copy_to_user_partial("/g `git grep -l " -= copy_to_user("` Then the same was done with copy_from_user(). During the review, patterns like the following were rejected and kept as is: - return copy_to_user(osf_stat, &tmp, sizeof(tmp)) ? -EFAULT : 0; + return copy_to_user_partial(osf_stat, &tmp, sizeof(tmp)) ? -EFAULT : 0; Signed-off-by: Christophe Leroy (CS GROUP) --- arch/alpha/kernel/osf_sys.c | 4 ++-- arch/alpha/kernel/termios.c | 2 +- arch/arc/kernel/disasm.c | 2 +- arch/arm64/include/asm/gcs.h | 2 +- arch/arm64/kernel/signal32.c | 2 +- arch/mips/kernel/rtlx.c | 8 ++++---- arch/mips/kernel/vpe.c | 2 +- arch/powerpc/kvm/book3s_64_mmu_hv.c | 4 ++-- arch/powerpc/kvm/book3s_64_mmu_radix.c | 4 ++-- arch/powerpc/kvm/book3s_hv.c | 2 +- arch/riscv/kernel/signal.c | 2 +- arch/s390/include/asm/idals.h | 8 ++++---- arch/sparc/kernel/termios.c | 2 +- arch/um/kernel/process.c | 2 +- arch/x86/lib/insn-eval.c | 2 +- arch/x86/um/signal.c | 2 +- drivers/android/binder_alloc.c | 2 +- drivers/comedi/comedi_fops.c | 4 ++-- drivers/dma/idxd/cdev.c | 2 +- drivers/firmware/efi/test/efi_test.c | 2 +- drivers/fsi/fsi-scom.c | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 4 ++-- drivers/gpu/drm/i915/i915_gem.c | 4 ++-- drivers/hwtracing/intel_th/msu.c | 2 +- drivers/misc/ibmvmc.c | 2 +- drivers/misc/vmw_vmci/vmci_host.c | 2 +- drivers/most/most_cdev.c | 2 +- drivers/net/ieee802154/ca8210.c | 4 ++-- drivers/net/wireless/ath/wil6210/debugfs.c | 2 +- .../wireless/intel/iwlwifi/pcie/gen1_2/trans.c | 2 +- drivers/net/wireless/ti/wlcore/debugfs.c | 2 +- drivers/ps3/ps3-lpm.c | 2 +- drivers/s390/crypto/zcrypt_api.h | 4 ++-- drivers/spi/spidev.c | 2 +- .../staging/media/atomisp/pci/atomisp_cmd.c | 8 ++++---- drivers/tty/tty_ioctl.c | 14 +++++++------- drivers/tty/vt/vc_screen.c | 4 ++-- drivers/usb/gadget/function/f_hid.c | 4 ++-- drivers/usb/gadget/function/f_printer.c | 2 +- drivers/vfio/vfio_iommu_type1.c | 4 ++-- drivers/xen/xenbus/xenbus_dev_frontend.c | 2 +- fs/namespace.c | 2 +- fs/ocfs2/dlmfs/dlmfs.c | 2 +- fs/proc/base.c | 4 ++-- include/linux/bpfptr.h | 2 +- include/linux/sockptr.h | 4 ++-- ipc/msg.c | 8 ++++---- ipc/sem.c | 8 ++++---- ipc/shm.c | 18 +++++++++--------- kernel/regset.c | 2 +- kernel/sys.c | 4 ++-- lib/kfifo.c | 8 ++++---- mm/kasan/kasan_test_c.c | 4 ++-- mm/memory.c | 2 +- net/x25/af_x25.c | 2 +- rust/helpers/uaccess.c | 4 ++-- sound/pci/emu10k1/emufx.c | 4 ++-- sound/pci/rme9652/hdsp.c | 6 +++--- sound/soc/intel/avs/probes.c | 6 +++--- sound/soc/sof/compress.c | 12 ++++++------ sound/soc/sof/sof-client-probes.c | 6 +++--- 62 files changed, 122 insertions(+), 122 deletions(-) diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c index 7b6543d2cca3..c8ea39fdbb9f 100644 --- a/arch/alpha/kernel/osf_sys.c +++ b/arch/alpha/kernel/osf_sys.c @@ -944,7 +944,7 @@ get_tv32(struct timespec64 *o, struct timeval32 __user *i) static inline long put_tv32(struct timeval32 __user *o, struct timespec64 *i) { - return copy_to_user(o, &(struct timeval32){ + return copy_to_user_partial(o, &(struct timeval32){ .tv_sec = i->tv_sec, .tv_usec = i->tv_nsec / NSEC_PER_USEC}, sizeof(struct timeval32)); @@ -953,7 +953,7 @@ put_tv32(struct timeval32 __user *o, struct timespec64 *i) static inline long put_tv_to_tv32(struct timeval32 __user *o, struct __kernel_old_timeval *i) { - return copy_to_user(o, &(struct timeval32){ + return copy_to_user_partial(o, &(struct timeval32){ .tv_sec = i->tv_sec, .tv_usec = i->tv_usec}, sizeof(struct timeval32)); diff --git a/arch/alpha/kernel/termios.c b/arch/alpha/kernel/termios.c index a4c29a22edf7..a3693c29a0fd 100644 --- a/arch/alpha/kernel/termios.c +++ b/arch/alpha/kernel/termios.c @@ -52,5 +52,5 @@ int kernel_termios_to_user_termio(struct termio __user *termio, v.c_cc[_VEOL2] = termios->c_cc[VEOL2]; v.c_cc[_VSWTC] = termios->c_cc[VSWTC]; - return copy_to_user(termio, &v, sizeof(struct termio)); + return copy_to_user_partial(termio, &v, sizeof(struct termio)); } diff --git a/arch/arc/kernel/disasm.c b/arch/arc/kernel/disasm.c index ccc7e8c39eb3..a3ef9d079e7f 100644 --- a/arch/arc/kernel/disasm.c +++ b/arch/arc/kernel/disasm.c @@ -34,7 +34,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state, /* This fetches the upper part of the 32 bit instruction * in both the cases of Little Endian or Big Endian configurations. */ if (userspace) { - bytes_not_copied = copy_from_user(ins_buf, + bytes_not_copied = copy_from_user_partial(ins_buf, (const void __user *) addr, 8); if (bytes_not_copied > 6) goto fault; diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index 8fa0707069e8..7ee23a8130b0 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -139,7 +139,7 @@ static inline u64 get_user_gcs(unsigned long __user *addr, int *err) /* Ensure previous GCS operation are visible before we read the page */ gcsb_dsync(); - ret = copy_from_user(&load, addr, sizeof(load)); + ret = copy_from_user_partial(&load, addr, sizeof(load)); if (ret != 0) *err = ret; return load; diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c index bb3b526ff43f..7016d2a3bb76 100644 --- a/arch/arm64/kernel/signal32.c +++ b/arch/arm64/kernel/signal32.c @@ -53,7 +53,7 @@ static inline int put_sigset_t(compat_sigset_t __user *uset, sigset_t *set) cset.sig[0] = set->sig[0] & 0xffffffffull; cset.sig[1] = set->sig[0] >> 32; - return copy_to_user(uset, &cset, sizeof(*uset)); + return copy_to_user_partial(uset, &cset, sizeof(*uset)); } static inline int get_sigset_t(sigset_t *set, diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 18c509c59f33..bc468064194d 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c @@ -262,13 +262,13 @@ ssize_t rtlx_read(int index, void __user *buff, size_t count) /* then how much from the read pointer onwards */ fl = min(count, (size_t)lx->buffer_size - lx->lx_read); - failed = copy_to_user(buff, lx->lx_buffer + lx->lx_read, fl); + failed = copy_to_user_partial(buff, lx->lx_buffer + lx->lx_read, fl); if (failed) goto out; /* and if there is anything left at the beginning of the buffer */ if (count - fl) - failed = copy_to_user(buff + fl, lx->lx_buffer, count - fl); + failed = copy_to_user_partial(buff + fl, lx->lx_buffer, count - fl); out: count -= failed; @@ -304,13 +304,13 @@ ssize_t rtlx_write(int index, const void __user *buffer, size_t count) /* first bit from write pointer to the end of the buffer, or count */ fl = min(count, (size_t) rt->buffer_size - rt->rt_write); - failed = copy_from_user(rt->rt_buffer + rt->rt_write, buffer, fl); + failed = copy_from_user_partial(rt->rt_buffer + rt->rt_write, buffer, fl); if (failed) goto out; /* if there's any left copy to the beginning of the buffer */ if (count - fl) - failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl); + failed = copy_from_user_partial(rt->rt_buffer, buffer + fl, count - fl); out: count -= failed; diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index b05ee21a1d67..5a8d72d6c80c 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -854,7 +854,7 @@ static ssize_t vpe_write(struct file *file, const char __user *buffer, return -ENOMEM; } - count -= copy_from_user(v->pbuffer + v->len, buffer, count); + count -= copy_from_user_partial(v->pbuffer + v->len, buffer, count); if (!count) return -EFAULT; diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index 2ccb3d138f46..1c43c7b8e801 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -2028,7 +2028,7 @@ static ssize_t debugfs_htab_read(struct file *file, char __user *buf, n = p->chars_left; if (n > len) n = len; - r = copy_to_user(buf, p->buf + p->buf_index, n); + r = copy_to_user_partial(buf, p->buf + p->buf_index, n); n -= r; p->chars_left -= n; p->buf_index += n; @@ -2068,7 +2068,7 @@ static ssize_t debugfs_htab_read(struct file *file, char __user *buf, p->chars_left = n; if (n > len) n = len; - r = copy_to_user(buf, p->buf, n); + r = copy_to_user_partial(buf, p->buf, n); n -= r; p->chars_left -= n; p->buf_index = n; diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c index 933fc7cb9afc..0a27e018d27b 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_radix.c +++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c @@ -1307,7 +1307,7 @@ static ssize_t debugfs_radix_read(struct file *file, char __user *buf, n = p->chars_left; if (n > len) n = len; - r = copy_to_user(buf, p->buf + p->buf_index, n); + r = copy_to_user_partial(buf, p->buf + p->buf_index, n); n -= r; p->chars_left -= n; p->buf_index += n; @@ -1407,7 +1407,7 @@ static ssize_t debugfs_radix_read(struct file *file, char __user *buf, p->chars_left = n; if (n > len) n = len; - r = copy_to_user(buf, p->buf, n); + r = copy_to_user_partial(buf, p->buf, n); n -= r; p->chars_left -= n; p->buf_index = n; diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 61dbeea317f3..4c7a8f687c99 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -2916,7 +2916,7 @@ static ssize_t debugfs_timings_read(struct file *file, char __user *buf, return 0; if (len > p->buflen - pos) len = p->buflen - pos; - n = copy_to_user(buf, p->buf + pos, len); + n = copy_to_user_partial(buf, p->buf + pos, len); if (n) { if (n == len) return -EFAULT; diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 59784dc117e4..4630dbad7428 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -139,7 +139,7 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) * Copy the whole vector content from user space datap. Use * copy_from_user to prevent information leak. */ - return copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); + return copy_from_user_partial(current->thread.vstate.datap, datap, riscv_v_vsize); } static long save_cfiss_state(struct pt_regs *regs, void __user *sc_cfi) diff --git a/arch/s390/include/asm/idals.h b/arch/s390/include/asm/idals.h index 06e1ec2afd5a..d86f4eb1ce42 100644 --- a/arch/s390/include/asm/idals.h +++ b/arch/s390/include/asm/idals.h @@ -301,14 +301,14 @@ static inline size_t idal_buffer_to_user(struct idal_buffer *ib, void __user *to BUG_ON(count > ib->size); for (i = 0; count > IDA_BLOCK_SIZE; i++) { vaddr = dma64_to_virt(ib->data[i]); - left = copy_to_user(to, vaddr, IDA_BLOCK_SIZE); + left = copy_to_user_partial(to, vaddr, IDA_BLOCK_SIZE); if (left) return left + count - IDA_BLOCK_SIZE; to = (void __user *)to + IDA_BLOCK_SIZE; count -= IDA_BLOCK_SIZE; } vaddr = dma64_to_virt(ib->data[i]); - return copy_to_user(to, vaddr, count); + return copy_to_user_partial(to, vaddr, count); } /* @@ -323,14 +323,14 @@ static inline size_t idal_buffer_from_user(struct idal_buffer *ib, const void __ BUG_ON(count > ib->size); for (i = 0; count > IDA_BLOCK_SIZE; i++) { vaddr = dma64_to_virt(ib->data[i]); - left = copy_from_user(vaddr, from, IDA_BLOCK_SIZE); + left = copy_from_user_partial(vaddr, from, IDA_BLOCK_SIZE); if (left) return left + count - IDA_BLOCK_SIZE; from = (void __user *)from + IDA_BLOCK_SIZE; count -= IDA_BLOCK_SIZE; } vaddr = dma64_to_virt(ib->data[i]); - return copy_from_user(vaddr, from, count); + return copy_from_user_partial(vaddr, from, count); } #endif diff --git a/arch/sparc/kernel/termios.c b/arch/sparc/kernel/termios.c index ee64965c27cd..db9c07b7d5ee 100644 --- a/arch/sparc/kernel/termios.c +++ b/arch/sparc/kernel/termios.c @@ -27,7 +27,7 @@ int kernel_termios_to_user_termio(struct termio __user *termio, v.c_cc[_VMIN] = termios->c_cc[VMIN]; v.c_cc[_VTIME] = termios->c_cc[VTIME]; } - return copy_to_user(termio, &v, sizeof(struct termio)); + return copy_to_user_partial(termio, &v, sizeof(struct termio)); } int user_termios_to_kernel_termios(struct ktermios *k, diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c index 63b38a3f73f7..d41625dfa00b 100644 --- a/arch/um/kernel/process.c +++ b/arch/um/kernel/process.c @@ -252,7 +252,7 @@ EXPORT_SYMBOL(uml_strdup); int copy_from_user_proc(void *to, void __user *from, int size) { - return copy_from_user(to, from, size); + return copy_from_user_partial(to, from, size); } int singlestepping(void) diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c index e03eeec55cfe..e7cb03ab26f1 100644 --- a/arch/x86/lib/insn-eval.c +++ b/arch/x86/lib/insn-eval.c @@ -1512,7 +1512,7 @@ int insn_fetch_from_user(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE]) if (insn_get_effective_ip(regs, &ip)) return -EINVAL; - not_copied = copy_from_user(buf, (void __user *)ip, MAX_INSN_SIZE); + not_copied = copy_from_user_partial(buf, (void __user *)ip, MAX_INSN_SIZE); return MAX_INSN_SIZE - not_copied; } diff --git a/arch/x86/um/signal.c b/arch/x86/um/signal.c index 2934e170b0fe..e0fab7c1625b 100644 --- a/arch/x86/um/signal.c +++ b/arch/x86/um/signal.c @@ -40,7 +40,7 @@ static int copy_sc_from_user(struct pt_regs *regs, /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; - err = copy_from_user(&sc, from, sizeof(sc)); + err = copy_from_user_partial(&sc, from, sizeof(sc)); if (err) return err; diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index e4488ad86a65..8ba9c57b489c 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -1346,7 +1346,7 @@ binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc, buffer_offset, &pgoff); size = min_t(size_t, bytes, PAGE_SIZE - pgoff); kptr = kmap_local_page(page) + pgoff; - ret = copy_from_user(kptr, from, size); + ret = copy_from_user_partial(kptr, from, size); kunmap_local(kptr); if (ret) return bytes - size + ret; diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index c09bbe04be6c..272fdc54fb81 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -2659,7 +2659,7 @@ static unsigned int comedi_buf_copy_to_user(struct comedi_subdevice *s, unsigned int copy_amount = min(n, PAGE_SIZE - offset); unsigned int uncopied; - uncopied = copy_to_user(dest, buf_page_list[page].virt_addr + + uncopied = copy_to_user_partial(dest, buf_page_list[page].virt_addr + offset, copy_amount); copy_amount -= uncopied; n -= copy_amount; @@ -2687,7 +2687,7 @@ static unsigned int comedi_buf_copy_from_user(struct comedi_subdevice *s, unsigned int copy_amount = min(n, PAGE_SIZE - offset); unsigned int uncopied; - uncopied = copy_from_user(buf_page_list[page].virt_addr + + uncopied = copy_from_user_partial(buf_page_list[page].virt_addr + offset, src, copy_amount); copy_amount -= uncopied; n -= copy_amount; diff --git a/drivers/dma/idxd/cdev.c b/drivers/dma/idxd/cdev.c index 0366c7cf3502..ac79bab6d6c3 100644 --- a/drivers/dma/idxd/cdev.c +++ b/drivers/dma/idxd/cdev.c @@ -751,7 +751,7 @@ int idxd_copy_cr(struct idxd_wq *wq, ioasid_t pasid, unsigned long addr, * to addr in the mm. */ kthread_use_mm(mm); - left = copy_to_user((void __user *)addr + status_size, cr + status_size, + left = copy_to_user_partial((void __user *)addr + status_size, cr + status_size, len - status_size); /* * Copy status only after the rest of completion record is copied diff --git a/drivers/firmware/efi/test/efi_test.c b/drivers/firmware/efi/test/efi_test.c index d54d6a671326..43b280ceb955 100644 --- a/drivers/firmware/efi/test/efi_test.c +++ b/drivers/firmware/efi/test/efi_test.c @@ -133,7 +133,7 @@ copy_ucs2_to_user_len(efi_char16_t __user *dst, efi_char16_t *src, size_t len) if (!src) return 0; - return copy_to_user(dst, src, len); + return copy_to_user_partial(dst, src, len); } static long efi_runtime_get_variable(unsigned long arg) diff --git a/drivers/fsi/fsi-scom.c b/drivers/fsi/fsi-scom.c index bb4d3700c934..370ec75b20e6 100644 --- a/drivers/fsi/fsi-scom.c +++ b/drivers/fsi/fsi-scom.c @@ -332,7 +332,7 @@ static ssize_t scom_read(struct file *filep, char __user *buf, size_t len, return rc; } - rc = copy_to_user(buf, &val, len); + rc = copy_to_user_partial(buf, &val, len); if (rc) dev_dbg(dev, "copy to user failed:%d\n", rc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 2409ac72b166..712605ec7ecc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1346,7 +1346,7 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); - r = copy_from_user(data, buf, write_size); + r = copy_from_user_partial(data, buf, write_size); write_size -= r; diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 656a499b2706..3f5b450a914a 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -114,7 +114,7 @@ int intel_sseu_copy_eumask_to_user(void __user *to, } } - return copy_to_user(to, eu_mask, len); + return copy_to_user_partial(to, eu_mask, len); } /** @@ -146,7 +146,7 @@ int intel_sseu_copy_ssmask_to_user(void __user *to, } } - return copy_to_user(to, ss_mask, len); + return copy_to_user_partial(to, ss_mask, len); } static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a432daf8038a..c1c2e762498f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -291,7 +291,7 @@ gtt_user_read(struct io_mapping *mapping, io_mapping_unmap_atomic(vaddr); if (unwritten) { vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); - unwritten = copy_to_user(user_data, + unwritten = copy_to_user_partial(user_data, (void __force *)vaddr + offset, length); io_mapping_unmap(vaddr); @@ -525,7 +525,7 @@ ggtt_write(struct io_mapping *mapping, io_mapping_unmap_atomic(vaddr); if (unwritten) { vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); - unwritten = copy_from_user((void __force *)vaddr + offset, + unwritten = copy_from_user_partial((void __force *)vaddr + offset, user_data, length); io_mapping_unmap(vaddr); } diff --git a/drivers/hwtracing/intel_th/msu.c b/drivers/hwtracing/intel_th/msu.c index a82cf74f39ad..9b97b71b44f1 100644 --- a/drivers/hwtracing/intel_th/msu.c +++ b/drivers/hwtracing/intel_th/msu.c @@ -1457,7 +1457,7 @@ static unsigned long msc_win_to_user(void *data, void *src, size_t len) struct msc_win_to_user_struct *u = data; unsigned long ret; - ret = copy_to_user(u->buf + u->offset, src, len); + ret = copy_to_user_partial(u->buf + u->offset, src, len); u->offset += len - ret; return ret; diff --git a/drivers/misc/ibmvmc.c b/drivers/misc/ibmvmc.c index beb18c34f20d..e1d99354dd29 100644 --- a/drivers/misc/ibmvmc.c +++ b/drivers/misc/ibmvmc.c @@ -1112,7 +1112,7 @@ static ssize_t ibmvmc_write(struct file *file, const char *buffer, while (c > 0) { bytes = min_t(size_t, c, vmc_buffer->size); - bytes -= copy_from_user(buf, p, bytes); + bytes -= copy_from_user_partial(buf, p, bytes); if (!bytes) { ret = -EFAULT; goto out; diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index b71ca1bf0a20..bd502edbc173 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -213,7 +213,7 @@ static int drv_cp_harray_to_user(void __user *user_buf_uva, *user_buf_size = array_size * sizeof(*handles); if (*user_buf_size) - *retval = copy_to_user(user_buf_uva, + *retval = copy_to_user_partial(user_buf_uva, vmci_handle_arr_get_handles (handle_array), *user_buf_size); diff --git a/drivers/most/most_cdev.c b/drivers/most/most_cdev.c index 5df508d8d60a..969c865ccbef 100644 --- a/drivers/most/most_cdev.c +++ b/drivers/most/most_cdev.c @@ -265,7 +265,7 @@ comp_read(struct file *filp, char __user *buf, size_t count, loff_t *offset) count, mbo->processed_length - c->mbo_offs); - not_copied = copy_to_user(buf, + not_copied = copy_to_user_partial(buf, mbo->virt_address + c->mbo_offs, to_copy); diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index ed4178155a5d..d474a008c73e 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -2460,7 +2460,7 @@ static ssize_t ca8210_test_int_user_write( return -EBADE; } - ret = copy_from_user(command, in_buf, len); + ret = copy_from_user_partial(command, in_buf, len); if (ret) { dev_err( &priv->spi->dev, @@ -2548,7 +2548,7 @@ static ssize_t ca8210_test_int_user_read( cmdlen = fifo_buffer[1]; bytes_not_copied = cmdlen + 2; - bytes_not_copied = copy_to_user(buf, fifo_buffer, bytes_not_copied); + bytes_not_copied = copy_to_user_partial(buf, fifo_buffer, bytes_not_copied); if (bytes_not_copied > 0) { dev_err( &priv->spi->dev, diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c index b8cb736a7185..f2130248fb7f 100644 --- a/drivers/net/wireless/ath/wil6210/debugfs.c +++ b/drivers/net/wireless/ath/wil6210/debugfs.c @@ -659,7 +659,7 @@ static ssize_t wil_read_file_ioblob(struct file *file, char __user *user_buf, wil_memcpy_fromio_32(buf, (const void __iomem *) wil_blob->blob.data + aligned_pos, aligned_count); - ret = copy_to_user(user_buf, buf + unaligned_bytes, count); + ret = copy_to_user_partial(user_buf, buf + unaligned_bytes, count); wil_mem_access_unlock(wil); wil_pm_runtime_put(wil); diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c index a05f60f9224b..66ddaa0d8e36 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c @@ -3060,7 +3060,7 @@ static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, if (*size > buf_size_left) *size = buf_size_left; - *size -= copy_to_user(user_buf, buf, *size); + *size -= copy_to_user_partial(user_buf, buf, *size); *bytes_copied += *size; if (buf_size_left == *size) diff --git a/drivers/net/wireless/ti/wlcore/debugfs.c b/drivers/net/wireless/ti/wlcore/debugfs.c index bbfd2725215b..d359baea5100 100644 --- a/drivers/net/wireless/ti/wlcore/debugfs.c +++ b/drivers/net/wireless/ti/wlcore/debugfs.c @@ -1088,7 +1088,7 @@ static ssize_t dev_mem_read(struct file *file, mutex_unlock(&wl->mutex); if (ret == 0) { - ret = copy_to_user(user_buf, buf, bytes); + ret = copy_to_user_partial(user_buf, buf, bytes); if (ret < bytes) { bytes -= ret; *ppos += bytes; diff --git a/drivers/ps3/ps3-lpm.c b/drivers/ps3/ps3-lpm.c index f8d8f607134a..5a2b150cda49 100644 --- a/drivers/ps3/ps3-lpm.c +++ b/drivers/ps3/ps3-lpm.c @@ -999,7 +999,7 @@ int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf, return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL; } - result = copy_to_user(buf, lpm_priv->tb_cache, tmp); + result = copy_to_user_partial(buf, lpm_priv->tb_cache, tmp); if (result) { dev_dbg(sbd_core(), "%s:%u: 0x%llx bytes at 0x%p\n", diff --git a/drivers/s390/crypto/zcrypt_api.h b/drivers/s390/crypto/zcrypt_api.h index 6ef8850a42df..61a5de90c354 100644 --- a/drivers/s390/crypto/zcrypt_api.h +++ b/drivers/s390/crypto/zcrypt_api.h @@ -185,7 +185,7 @@ static inline unsigned long z_copy_from_user(bool userspace, unsigned long n) { if (likely(userspace)) - return copy_from_user(to, from, n); + return copy_from_user_partial(to, from, n); memcpy(to, (void __force *)from, n); return 0; } @@ -196,7 +196,7 @@ static inline unsigned long z_copy_to_user(bool userspace, unsigned long n) { if (likely(userspace)) - return copy_to_user(to, from, n); + return copy_to_user_partial(to, from, n); memcpy((void __force *)to, from, n); return 0; } diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 638221178384..5b42fabcf4c4 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -157,7 +157,7 @@ spidev_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) if (status > 0) { unsigned long missing; - missing = copy_to_user(buf, spidev->rx_buffer, status); + missing = copy_to_user_partial(buf, spidev->rx_buffer, status); if (missing == status) status = -EFAULT; else diff --git a/drivers/staging/media/atomisp/pci/atomisp_cmd.c b/drivers/staging/media/atomisp/pci/atomisp_cmd.c index fec369575d88..10a7aff375a9 100644 --- a/drivers/staging/media/atomisp/pci/atomisp_cmd.c +++ b/drivers/staging/media/atomisp/pci/atomisp_cmd.c @@ -1491,7 +1491,7 @@ int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, } for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { - ret = copy_from_user(tab->coordinates_x[i], + ret = copy_from_user_partial(tab->coordinates_x[i], config->coordinates_x[i], config->height * config->width * sizeof(*config->coordinates_x[i])); @@ -1502,7 +1502,7 @@ int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, atomisp_css_morph_table_free(tab); return -EFAULT; } - ret = copy_from_user(tab->coordinates_y[i], + ret = copy_from_user_partial(tab->coordinates_y[i], config->coordinates_y[i], config->height * config->width * sizeof(*config->coordinates_y[i])); @@ -1709,7 +1709,7 @@ int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag, config->exp_id = s3a_buf->s3a_data->exp_id; config->isp_config_id = s3a_buf->s3a_data->isp_config_id; - ret = copy_to_user(config->data, asd->params.s3a_user_stat->data, + ret = copy_to_user_partial(config->data, asd->params.s3a_user_stat->data, asd->params.s3a_output_bytes); if (ret) { dev_err(isp->dev, "copy to user failed: copied %lu bytes\n", @@ -2031,7 +2031,7 @@ static unsigned int long copy_from_compatible(void *to, const void *from, unsigned long n, bool from_user) { if (from_user) - return copy_from_user(to, (void __user *)from, n); + return copy_from_user_partial(to, (void __user *)from, n); else memcpy(to, from, n); return 0; diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index 90c70d8d14e3..cdc274c0ff81 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -388,29 +388,29 @@ __weak int kernel_termios_to_user_termio(struct termio __user *termio, v.c_lflag = termios->c_lflag; v.c_line = termios->c_line; memcpy(v.c_cc, termios->c_cc, NCC); - return copy_to_user(termio, &v, sizeof(struct termio)); + return copy_to_user_partial(termio, &v, sizeof(struct termio)); } #ifdef TCGETS2 __weak int user_termios_to_kernel_termios(struct ktermios *k, struct termios2 __user *u) { - return copy_from_user(k, u, sizeof(struct termios2)); + return copy_from_user_partial(k, u, sizeof(struct termios2)); } __weak int kernel_termios_to_user_termios(struct termios2 __user *u, struct ktermios *k) { - return copy_to_user(u, k, sizeof(struct termios2)); + return copy_to_user_partial(u, k, sizeof(struct termios2)); } __weak int user_termios_to_kernel_termios_1(struct ktermios *k, struct termios __user *u) { - return copy_from_user(k, u, sizeof(struct termios)); + return copy_from_user_partial(k, u, sizeof(struct termios)); } __weak int kernel_termios_to_user_termios_1(struct termios __user *u, struct ktermios *k) { - return copy_to_user(u, k, sizeof(struct termios)); + return copy_to_user_partial(u, k, sizeof(struct termios)); } #else @@ -418,12 +418,12 @@ __weak int kernel_termios_to_user_termios_1(struct termios __user *u, __weak int user_termios_to_kernel_termios(struct ktermios *k, struct termios __user *u) { - return copy_from_user(k, u, sizeof(struct termios)); + return copy_from_user_partial(k, u, sizeof(struct termios)); } __weak int kernel_termios_to_user_termios(struct termios __user *u, struct ktermios *k) { - return copy_to_user(u, k, sizeof(struct termios)); + return copy_to_user_partial(u, k, sizeof(struct termios)); } #endif /* TCGETS2 */ diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c index 4d2d46c95fef..e54c708149c3 100644 --- a/drivers/tty/vt/vc_screen.c +++ b/drivers/tty/vt/vc_screen.c @@ -450,7 +450,7 @@ vcs_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) */ console_unlock(); - ret = copy_to_user(buf, con_buf + skip, this_round); + ret = copy_to_user_partial(buf, con_buf + skip, this_round); console_lock(); if (ret) { @@ -630,7 +630,7 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) * in the write data from userspace safely. */ console_unlock(); - ret = copy_from_user(con_buf, buf, this_round); + ret = copy_from_user_partial(con_buf, buf, this_round); console_lock(); if (ret) { diff --git a/drivers/usb/gadget/function/f_hid.c b/drivers/usb/gadget/function/f_hid.c index c5a12a6760ea..f22dd3697a46 100644 --- a/drivers/usb/gadget/function/f_hid.c +++ b/drivers/usb/gadget/function/f_hid.c @@ -349,7 +349,7 @@ static ssize_t f_hidg_intout_read(struct file *file, char __user *buffer, spin_unlock_irqrestore(&hidg->read_spinlock, flags); /* copy to user outside spinlock */ - count -= copy_to_user(buffer, req->buf + list->pos, count); + count -= copy_to_user_partial(buffer, req->buf + list->pos, count); list->pos += count; /* @@ -410,7 +410,7 @@ static ssize_t f_hidg_ssreport_read(struct file *file, char __user *buffer, spin_unlock_irqrestore(&hidg->read_spinlock, flags); if (tmp_buf != NULL) { - count -= copy_to_user(buffer, tmp_buf, count); + count -= copy_to_user_partial(buffer, tmp_buf, count); kfree(tmp_buf); } else { count = -ENOMEM; diff --git a/drivers/usb/gadget/function/f_printer.c b/drivers/usb/gadget/function/f_printer.c index e4f7828ae75d..4fbed987b639 100644 --- a/drivers/usb/gadget/function/f_printer.c +++ b/drivers/usb/gadget/function/f_printer.c @@ -525,7 +525,7 @@ printer_read(struct file *fd, char __user *buf, size_t len, loff_t *ptr) else size = len; - size -= copy_to_user(buf, current_rx_buf, size); + size -= copy_to_user_partial(buf, current_rx_buf, size); bytes_copied += size; len -= size; buf += size; diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c index c8151ba54de3..ad74a891aa80 100644 --- a/drivers/vfio/vfio_iommu_type1.c +++ b/drivers/vfio/vfio_iommu_type1.c @@ -3173,7 +3173,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct vfio_iommu *iommu, vaddr = dma->vaddr + offset; if (write) { - *copied = copy_to_user((void __user *)vaddr, data, + *copied = copy_to_user_partial((void __user *)vaddr, data, count) ? 0 : count; if (*copied && iommu->dirty_page_tracking) { unsigned long pgshift = __ffs(iommu->pgsize_bitmap); @@ -3186,7 +3186,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct vfio_iommu *iommu, (offset >> pgshift) + 1); } } else - *copied = copy_from_user(data, (void __user *)vaddr, + *copied = copy_from_user_partial(data, (void __user *)vaddr, count) ? 0 : count; if (kthread) kthread_unuse_mm(mm); diff --git a/drivers/xen/xenbus/xenbus_dev_frontend.c b/drivers/xen/xenbus/xenbus_dev_frontend.c index 61db6932a9d2..b1db90dac1d1 100644 --- a/drivers/xen/xenbus/xenbus_dev_frontend.c +++ b/drivers/xen/xenbus/xenbus_dev_frontend.c @@ -150,7 +150,7 @@ static ssize_t xenbus_file_read(struct file *filp, while (i < len) { size_t sz = min_t(size_t, len - i, rb->len - rb->cons); - ret = copy_to_user(ubuf + i, &rb->msg[rb->cons], sz); + ret = copy_to_user_partial(ubuf + i, &rb->msg[rb->cons], sz); i += sz - ret; rb->cons += sz - ret; diff --git a/fs/namespace.c b/fs/namespace.c index fe919abd2f01..27afb73fef20 100644 --- a/fs/namespace.c +++ b/fs/namespace.c @@ -4033,7 +4033,7 @@ static void *copy_mount_options(const void __user * data) if (!copy) return ERR_PTR(-ENOMEM); - left = copy_from_user(copy, data, PAGE_SIZE); + left = copy_from_user_partial(copy, data, PAGE_SIZE); /* * Not all architectures have an exact copy_from_user(). Resort to diff --git a/fs/ocfs2/dlmfs/dlmfs.c b/fs/ocfs2/dlmfs/dlmfs.c index 5821e33df78f..97c0b391b98e 100644 --- a/fs/ocfs2/dlmfs/dlmfs.c +++ b/fs/ocfs2/dlmfs/dlmfs.c @@ -255,7 +255,7 @@ static ssize_t dlmfs_file_write(struct file *filp, if (!count) return 0; - bytes_left = copy_from_user(lvb_buf, buf, count); + bytes_left = copy_from_user_partial(lvb_buf, buf, count); count -= bytes_left; if (count) user_dlm_write_lvb(inode, lvb_buf, count); diff --git a/fs/proc/base.c b/fs/proc/base.c index d9acfa89c894..49577662ae70 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -278,7 +278,7 @@ static ssize_t get_mm_proctitle(struct mm_struct *mm, char __user *buf, len -= pos; if (len > count) len = count; - len -= copy_to_user(buf, page+pos, len); + len -= copy_to_user_partial(buf, page+pos, len); if (!len) len = -EFAULT; ret = len; @@ -359,7 +359,7 @@ static ssize_t get_mm_cmdline(struct mm_struct *mm, char __user *buf, got = access_remote_vm(mm, pos, page, size, FOLL_ANON); if (got <= 0) break; - got -= copy_to_user(buf, page, got); + got -= copy_to_user_partial(buf, page, got); if (unlikely(!got)) { if (!len) len = -EFAULT; diff --git a/include/linux/bpfptr.h b/include/linux/bpfptr.h index f6e0795db484..e4444d0f0cfe 100644 --- a/include/linux/bpfptr.h +++ b/include/linux/bpfptr.h @@ -50,7 +50,7 @@ static inline int copy_from_bpfptr_offset(void *dst, bpfptr_t src, size_t offset, size_t size) { if (!bpfptr_is_kernel(src)) - return copy_from_user(dst, src.user + offset, size); + return copy_from_user_partial(dst, src.user + offset, size); return copy_from_kernel_nofault(dst, src.kernel + offset, size); } diff --git a/include/linux/sockptr.h b/include/linux/sockptr.h index 3e6c8e9d67ae..52ddddfe728d 100644 --- a/include/linux/sockptr.h +++ b/include/linux/sockptr.h @@ -45,7 +45,7 @@ static inline int copy_from_sockptr_offset(void *dst, sockptr_t src, size_t offset, size_t size) { if (!sockptr_is_kernel(src)) - return copy_from_user(dst, src.user + offset, size); + return copy_from_user_partial(dst, src.user + offset, size); memcpy(dst, src.kernel + offset, size); return 0; } @@ -111,7 +111,7 @@ static inline int copy_to_sockptr_offset(sockptr_t dst, size_t offset, const void *src, size_t size) { if (!sockptr_is_kernel(dst)) - return copy_to_user(dst.user + offset, src, size); + return copy_to_user_partial(dst.user + offset, src, size); memcpy(dst.kernel + offset, src, size); return 0; } diff --git a/ipc/msg.c b/ipc/msg.c index 62996b97f0ac..39848238219d 100644 --- a/ipc/msg.c +++ b/ipc/msg.c @@ -322,7 +322,7 @@ copy_msqid_to_user(void __user *buf, struct msqid64_ds *in, int version) { switch (version) { case IPC_64: - return copy_to_user(buf, in, sizeof(*in)); + return copy_to_user_partial(buf, in, sizeof(*in)); case IPC_OLD: { struct msqid_ds out; @@ -355,7 +355,7 @@ copy_msqid_to_user(void __user *buf, struct msqid64_ds *in, int version) out.msg_lspid = in->msg_lspid; out.msg_lrpid = in->msg_lrpid; - return copy_to_user(buf, &out, sizeof(out)); + return copy_to_user_partial(buf, &out, sizeof(out)); } default: return -EINVAL; @@ -712,7 +712,7 @@ static int copy_compat_msqid_to_user(void __user *buf, struct msqid64_ds *in, v.msg_qbytes = in->msg_qbytes; v.msg_lspid = in->msg_lspid; v.msg_lrpid = in->msg_lrpid; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } else { struct compat_msqid_ds v; memset(&v, 0, sizeof(v)); @@ -725,7 +725,7 @@ static int copy_compat_msqid_to_user(void __user *buf, struct msqid64_ds *in, v.msg_qbytes = in->msg_qbytes; v.msg_lspid = in->msg_lspid; v.msg_lrpid = in->msg_lrpid; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } } diff --git a/ipc/sem.c b/ipc/sem.c index 6cdf862b1f5c..3b56086ba07d 100644 --- a/ipc/sem.c +++ b/ipc/sem.c @@ -1196,7 +1196,7 @@ static unsigned long copy_semid_to_user(void __user *buf, struct semid64_ds *in, { switch (version) { case IPC_64: - return copy_to_user(buf, in, sizeof(*in)); + return copy_to_user_partial(buf, in, sizeof(*in)); case IPC_OLD: { struct semid_ds out; @@ -1209,7 +1209,7 @@ static unsigned long copy_semid_to_user(void __user *buf, struct semid64_ds *in, out.sem_ctime = in->sem_ctime; out.sem_nsems = in->sem_nsems; - return copy_to_user(buf, &out, sizeof(out)); + return copy_to_user_partial(buf, &out, sizeof(out)); } default: return -EINVAL; @@ -1759,7 +1759,7 @@ static int copy_compat_semid_to_user(void __user *buf, struct semid64_ds *in, v.sem_ctime = lower_32_bits(in->sem_ctime); v.sem_ctime_high = upper_32_bits(in->sem_ctime); v.sem_nsems = in->sem_nsems; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } else { struct compat_semid_ds v; memset(&v, 0, sizeof(v)); @@ -1767,7 +1767,7 @@ static int copy_compat_semid_to_user(void __user *buf, struct semid64_ds *in, v.sem_otime = in->sem_otime; v.sem_ctime = in->sem_ctime; v.sem_nsems = in->sem_nsems; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } } diff --git a/ipc/shm.c b/ipc/shm.c index a95dae447707..1eb53c3df3b9 100644 --- a/ipc/shm.c +++ b/ipc/shm.c @@ -853,7 +853,7 @@ static inline unsigned long copy_shmid_to_user(void __user *buf, struct shmid64_ { switch (version) { case IPC_64: - return copy_to_user(buf, in, sizeof(*in)); + return copy_to_user_partial(buf, in, sizeof(*in)); case IPC_OLD: { struct shmid_ds out; @@ -868,7 +868,7 @@ static inline unsigned long copy_shmid_to_user(void __user *buf, struct shmid64_ out.shm_lpid = in->shm_lpid; out.shm_nattch = in->shm_nattch; - return copy_to_user(buf, &out, sizeof(out)); + return copy_to_user_partial(buf, &out, sizeof(out)); } default: return -EINVAL; @@ -905,7 +905,7 @@ static inline unsigned long copy_shminfo_to_user(void __user *buf, struct shminf { switch (version) { case IPC_64: - return copy_to_user(buf, in, sizeof(*in)); + return copy_to_user_partial(buf, in, sizeof(*in)); case IPC_OLD: { struct shminfo out; @@ -920,7 +920,7 @@ static inline unsigned long copy_shminfo_to_user(void __user *buf, struct shminf out.shmseg = in->shmseg; out.shmall = in->shmall; - return copy_to_user(buf, &out, sizeof(out)); + return copy_to_user_partial(buf, &out, sizeof(out)); } default: return -EINVAL; @@ -1359,7 +1359,7 @@ static int copy_compat_shminfo_to_user(void __user *buf, struct shminfo64 *in, info.shmmni = in->shmmni; info.shmseg = in->shmseg; info.shmall = in->shmall; - return copy_to_user(buf, &info, sizeof(info)); + return copy_to_user_partial(buf, &info, sizeof(info)); } else { struct shminfo info; memset(&info, 0, sizeof(info)); @@ -1368,7 +1368,7 @@ static int copy_compat_shminfo_to_user(void __user *buf, struct shminfo64 *in, info.shmmni = in->shmmni; info.shmseg = in->shmseg; info.shmall = in->shmall; - return copy_to_user(buf, &info, sizeof(info)); + return copy_to_user_partial(buf, &info, sizeof(info)); } } @@ -1384,7 +1384,7 @@ static int put_compat_shm_info(struct shm_info *ip, info.shm_swp = ip->shm_swp; info.swap_attempts = ip->swap_attempts; info.swap_successes = ip->swap_successes; - return copy_to_user(uip, &info, sizeof(info)); + return copy_to_user_partial(uip, &info, sizeof(info)); } static int copy_compat_shmid_to_user(void __user *buf, struct shmid64_ds *in, @@ -1404,7 +1404,7 @@ static int copy_compat_shmid_to_user(void __user *buf, struct shmid64_ds *in, v.shm_nattch = in->shm_nattch; v.shm_cpid = in->shm_cpid; v.shm_lpid = in->shm_lpid; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } else { struct compat_shmid_ds v; memset(&v, 0, sizeof(v)); @@ -1417,7 +1417,7 @@ static int copy_compat_shmid_to_user(void __user *buf, struct shmid64_ds *in, v.shm_nattch = in->shm_nattch; v.shm_cpid = in->shm_cpid; v.shm_lpid = in->shm_lpid; - return copy_to_user(buf, &v, sizeof(v)); + return copy_to_user_partial(buf, &v, sizeof(v)); } } diff --git a/kernel/regset.c b/kernel/regset.c index b2871fa68b2a..29c6d19c3465 100644 --- a/kernel/regset.c +++ b/kernel/regset.c @@ -70,7 +70,7 @@ int copy_regset_to_user(struct task_struct *target, ret = regset_get_alloc(target, regset, size, &buf); if (ret > 0) - ret = copy_to_user(data, buf, ret) ? -EFAULT : 0; + ret = copy_to_user_partial(data, buf, ret) ? -EFAULT : 0; kvfree(buf); return ret; } diff --git a/kernel/sys.c b/kernel/sys.c index 62e842055cc9..8e1ce8c26884 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -1343,7 +1343,7 @@ static int override_release(char __user *release, size_t len) v = LINUX_VERSION_PATCHLEVEL + 60; copy = clamp_t(size_t, len, 1, sizeof(buf)); copy = scnprintf(buf, copy, "2.6.%u%s", v, rest); - ret = copy_to_user(release, buf, copy + 1); + ret = copy_to_user_partial(release, buf, copy + 1); } return ret; } @@ -1567,7 +1567,7 @@ SYSCALL_DEFINE2(getrlimit, unsigned int, resource, struct rlimit __user *, rlim) ret = do_prlimit(current, resource, NULL, &value); if (!ret) - ret = copy_to_user(rlim, &value, sizeof(*rlim)) ? -EFAULT : 0; + ret = copy_to_user_partial(rlim, &value, sizeof(*rlim)) ? -EFAULT : 0; return ret; } diff --git a/lib/kfifo.c b/lib/kfifo.c index 2633f9cc336c..00c19a321aae 100644 --- a/lib/kfifo.c +++ b/lib/kfifo.c @@ -203,11 +203,11 @@ static unsigned long kfifo_copy_from_user(struct __kfifo *fifo, } l = min(len, size - off); - ret = copy_from_user(fifo->data + off, from, l); + ret = copy_from_user_partial(fifo->data + off, from, l); if (unlikely(ret)) ret = DIV_ROUND_UP(ret + len - l, esize); else { - ret = copy_from_user(fifo->data, from + l, len - l); + ret = copy_from_user_partial(fifo->data, from + l, len - l); if (unlikely(ret)) ret = DIV_ROUND_UP(ret, esize); } @@ -263,11 +263,11 @@ static unsigned long kfifo_copy_to_user(struct __kfifo *fifo, void __user *to, } l = min(len, size - off); - ret = copy_to_user(to, fifo->data + off, l); + ret = copy_to_user_partial(to, fifo->data + off, l); if (unlikely(ret)) ret = DIV_ROUND_UP(ret + len - l, esize); else { - ret = copy_to_user(to + l, fifo->data, len - l); + ret = copy_to_user_partial(to + l, fifo->data, len - l); if (unlikely(ret)) ret = DIV_ROUND_UP(ret, esize); } diff --git a/mm/kasan/kasan_test_c.c b/mm/kasan/kasan_test_c.c index 32d06cbf6a31..a4d19fc1068a 100644 --- a/mm/kasan/kasan_test_c.c +++ b/mm/kasan/kasan_test_c.c @@ -2169,9 +2169,9 @@ static void copy_user_test_oob(struct kunit *test) usermem = (char __user *)useraddr; KUNIT_EXPECT_KASAN_FAIL(test, - unused = copy_from_user(kmem, usermem, size + 1)); + unused = copy_from_user_partial(kmem, usermem, size + 1)); KUNIT_EXPECT_KASAN_FAIL_READ(test, - unused = copy_to_user(usermem, kmem, size + 1)); + unused = copy_to_user_partial(usermem, kmem, size + 1)); KUNIT_EXPECT_KASAN_FAIL(test, unused = __copy_from_user(kmem, usermem, size + 1)); KUNIT_EXPECT_KASAN_FAIL_READ(test, diff --git a/mm/memory.c b/mm/memory.c index ea6568571131..5a2f7543a2da 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -7529,7 +7529,7 @@ long copy_folio_from_user(struct folio *dst_folio, kaddr = kmap_local_page(subpage); if (!allow_pagefault) pagefault_disable(); - rc = copy_from_user(kaddr, usr_src + i * PAGE_SIZE, PAGE_SIZE); + rc = copy_from_user_partial(kaddr, usr_src + i * PAGE_SIZE, PAGE_SIZE); if (!allow_pagefault) pagefault_enable(); kunmap_local(kaddr); diff --git a/net/x25/af_x25.c b/net/x25/af_x25.c index af8762b24039..7327c98b206a 100644 --- a/net/x25/af_x25.c +++ b/net/x25/af_x25.c @@ -471,7 +471,7 @@ static int x25_getsockopt(struct socket *sock, int level, int optname, goto out; val = test_bit(X25_Q_BIT_FLAG, &x25_sk(sk)->flags); - rc = copy_to_user(optval, &val, len) ? -EFAULT : 0; + rc = copy_to_user_partial(optval, &val, len) ? -EFAULT : 0; out: return rc; } diff --git a/rust/helpers/uaccess.c b/rust/helpers/uaccess.c index 01de4fbbcc84..710e07cd60ae 100644 --- a/rust/helpers/uaccess.c +++ b/rust/helpers/uaccess.c @@ -5,13 +5,13 @@ __rust_helper unsigned long rust_helper_copy_from_user(void *to, const void __user *from, unsigned long n) { - return copy_from_user(to, from, n); + return copy_from_user_partial(to, from, n); } __rust_helper unsigned long rust_helper_copy_to_user(void __user *to, const void *from, unsigned long n) { - return copy_to_user(to, from, n); + return copy_to_user_partial(to, from, n); } #ifndef CONFIG_ARCH_WANTS_NOINLINE_COPY_USER diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c index 08e0556bf161..3941bf9666a9 100644 --- a/sound/pci/emu10k1/emufx.c +++ b/sound/pci/emu10k1/emufx.c @@ -739,10 +739,10 @@ static int copy_gctl_to_user(struct snd_emu10k1 *emu, _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst; if (emu->support_tlv) - return copy_to_user(&_dst[idx], src, sizeof(*src)); + return copy_to_user_partial(&_dst[idx], src, sizeof(*src)); octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst; - return copy_to_user(&octl[idx], src, sizeof(*octl)); + return copy_to_user_partial(&octl[idx], src, sizeof(*octl)); } static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i, diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c index 31cc2d91c8d2..d5842d8a8509 100644 --- a/sound/pci/rme9652/hdsp.c +++ b/sound/pci/rme9652/hdsp.c @@ -4541,7 +4541,7 @@ static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) static inline int copy_u32_le(void __user *dest, void __iomem *src) { u32 val = readl(src); - return copy_to_user(dest, &val, 4); + return copy_to_user_partial(dest, &val, 4); } static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) @@ -4551,7 +4551,7 @@ static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __i rms_low = readl(src_low); rms_high = readl(src_high); rms = ((u64)rms_high << 32) | rms_low; - return copy_to_user(dest, &rms, 8); + return copy_to_user_partial(dest, &rms, 8); } static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) @@ -4561,7 +4561,7 @@ static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __i rms_low = readl(src_low) & 0xffffff00; rms_high = readl(src_high) & 0xffffff00; rms = ((u64)rms_high << 32) | rms_low; - return copy_to_user(dest, &rms, 8); + return copy_to_user_partial(dest, &rms, 8); } static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) diff --git a/sound/soc/intel/avs/probes.c b/sound/soc/intel/avs/probes.c index 099119ad28b3..bc2871d3e18c 100644 --- a/sound/soc/intel/avs/probes.c +++ b/sound/soc/intel/avs/probes.c @@ -244,10 +244,10 @@ static int avs_probe_compr_copy(struct snd_soc_component *comp, struct snd_compr n = rtd->buffer_size - offset; if (count < n) { - ret = copy_to_user(buf, ptr, count); + ret = copy_to_user_partial(buf, ptr, count); } else { - ret = copy_to_user(buf, ptr, n); - ret += copy_to_user(buf + n, rtd->dma_area, count - n); + ret = copy_to_user_partial(buf, ptr, n); + ret += copy_to_user_partial(buf + n, rtd->dma_area, count - n); } if (ret) diff --git a/sound/soc/sof/compress.c b/sound/soc/sof/compress.c index 93f2376585db..d54be8a188ec 100644 --- a/sound/soc/sof/compress.c +++ b/sound/soc/sof/compress.c @@ -324,10 +324,10 @@ static int sof_compr_copy_playback(struct snd_compr_runtime *rtd, n = rtd->buffer_size - offset; if (count < n) { - ret = copy_from_user(ptr, buf, count); + ret = copy_from_user_partial(ptr, buf, count); } else { - ret = copy_from_user(ptr, buf, n); - ret += copy_from_user(rtd->dma_area, buf + n, count - n); + ret = copy_from_user_partial(ptr, buf, n); + ret += copy_from_user_partial(rtd->dma_area, buf + n, count - n); } return count - ret; @@ -345,10 +345,10 @@ static int sof_compr_copy_capture(struct snd_compr_runtime *rtd, n = rtd->buffer_size - offset; if (count < n) { - ret = copy_to_user(buf, ptr, count); + ret = copy_to_user_partial(buf, ptr, count); } else { - ret = copy_to_user(buf, ptr, n); - ret += copy_to_user(buf + n, rtd->dma_area, count - n); + ret = copy_to_user_partial(buf, ptr, n); + ret += copy_to_user_partial(buf + n, rtd->dma_area, count - n); } return count - ret; diff --git a/sound/soc/sof/sof-client-probes.c b/sound/soc/sof/sof-client-probes.c index 124f55508159..4c5f4f016ff8 100644 --- a/sound/soc/sof/sof-client-probes.c +++ b/sound/soc/sof/sof-client-probes.c @@ -184,10 +184,10 @@ static int sof_probes_compr_copy(struct snd_soc_component *component, n = rtd->buffer_size - offset; if (count < n) { - ret = copy_to_user(buf, ptr, count); + ret = copy_to_user_partial(buf, ptr, count); } else { - ret = copy_to_user(buf, ptr, n); - ret += copy_to_user(buf + n, rtd->dma_area, count - n); + ret = copy_to_user_partial(buf, ptr, n); + ret += copy_to_user_partial(buf + n, rtd->dma_area, count - n); } if (ret) -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:18:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:18:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295169.1571864 (Exim 4.92) (envelope-from ) id 1wHPbd-0001KN-ID; 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d=kernel.org; s=k20201202; t=1777310325; bh=x+yz+Ptlr8yUKihbRCrYsj2OzN4+HDHdWj3mTkeeywo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YS9v5orti9jIm2coPKy7cH4iQCLjTYOH2T4kGrmAKw1lk2UpD8UcWDut4XHtMo5CX 290KHU3PNOVzMmnTKEL1o/OfzgOnzBVsJnbuGicRbc3HqjVsrjLo1DZ4Ncwz6tafWZ SG8/hG1Ct8pUgSHrDrW4chwaJ34uCldA2tlOQo4bI8M4kMxsW5bP0OLNOAC7BeTwPk Mil/pgBJA2/iCGWwmbEh5WNZZrQ4Md/gtqmnREocwFdhobkWjiqhIB30lRO/GV15k3 DZOePxOSt4vdcYmGqKSVWX7R1FegGyxqEmqkjMUEcFWkKzHsBpXNo8/6bbP3EGANbq KZwGUUWEURiLg== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 6/9] uaccess: Change copy_{to/from}_user to return -EFAULT Date: Mon, 27 Apr 2026 19:13:47 +0200 Message-ID: <1a55107abe15dd78450888e2b5327c3a56af29b7.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2416; i=chleroy@kernel.org; h=from:subject:message-id; bh=x+yz+Ptlr8yUKihbRCrYsj2OzN4+HDHdWj3mTkeeywo=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxkjryH88LzkjscmK202zhcwuOPhcJTlidTVNdtCP 9vs/VPG2lHKwiDGxSArpshy/D/3rhldX1Lzp+7Sh5nDygQyhIGLUwAm0nCN4b9/yT75hpDtr4zk 9XPfORmtVO2p/XH+8bFg730PPNfMvn6dkWHDjsJSC09Vr9bDobdrxTgfMm1ckveKR+Rkud3skLM HLXgA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1777310327-CEB778B7-CD0BDB58/0/0 X-purgate-type: clean X-purgate-size: 2418 Now that copy_{to/from}_user_partial() are used by callers which expect partial copy with number of not copied bytes as return value, change copy_{to/from}_user() to return an int, and return -EFAULT when the copy is not complete. Signed-off-by: Christophe Leroy (CS GROUP) --- include/linux/uaccess.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index 2d37173782b3..33b7d0f5f808 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -211,7 +211,7 @@ extern __must_check unsigned long _copy_to_user(void __user *, const void *, unsigned long); static __always_inline unsigned long __must_check -copy_from_user(void *to, const void __user *from, unsigned long n) +copy_from_user_common(void *to, const void __user *from, unsigned long n, bool partial) { if (!check_copy_size(to, n, false)) return n; @@ -221,10 +221,20 @@ copy_from_user(void *to, const void __user *from, unsigned long n) return _inline_copy_from_user(to, from, n); } -#define copy_from_user_partial copy_from_user +static __always_inline unsigned long __must_check +copy_from_user_partial(void *to, const void __user *from, unsigned long n) +{ + return copy_from_user_common(to, from, n, true); +} + +static __always_inline int __must_check +copy_from_user(void *to, const void __user *from, unsigned long n) +{ + return copy_from_user_common(to, from, n, false) ? -EFAULT : 0; +} static __always_inline unsigned long __must_check -copy_to_user(void __user *to, const void *from, unsigned long n) +copy_to_user_common(void __user *to, const void *from, unsigned long n, bool partial) { if (!check_copy_size(from, n, true)) return n; @@ -235,7 +245,17 @@ copy_to_user(void __user *to, const void *from, unsigned long n) return _inline_copy_to_user(to, from, n); } -#define copy_to_user_partial copy_to_user +static __always_inline unsigned long __must_check +copy_to_user_partial(void __user *to, const void *from, unsigned long n) +{ + return copy_to_user_common(to, from, n, true); +} + +static __always_inline int __must_check +copy_to_user(void __user *to, const void *from, unsigned long n) +{ + return copy_to_user_common(to, from, n, false) ? -EFAULT : 0; +} #ifndef copy_mc_to_kernel /* -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:19:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:19:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295177.1571873 (Exim 4.92) (envelope-from ) id 1wHPbr-0001rR-O9; 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Mon, 27 Apr 2026 19:19:01 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69ef9a83-212f-0a2a450b0019-aceafc1f93f0-3 for ; Mon, 27 Apr 2026 19:19:01 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 9368940C54; Mon, 27 Apr 2026 17:18:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59C90C2BCB4; Mon, 27 Apr 2026 17:18:46 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310339; bh=VVuQn2YnZFi2JH9uh9hmEqXb1BpygsXabSyFGnhBvmI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kdO2kRaqrKnrRzE/uOUoSc+QuIvBLF9bEcfUYb9jTJLWJk0AT883/0gLUkpYyvhxW JwKLSaa6O8znPG+ygzo4nQLM8J0f65SbAuU342P7t8CFNHOEuyufyC86uU6TKB6BuB gSew3oyOMPJ8ALphDrpzU/JPmVzf88NlkSTCpSsq0dGpC1oXnkppqU6so9I0ayHunG vmD6szQq9NnauXryTPXCD0GLKF95gnwZ47owOPgIM468cdafyYqaGorVn/T0ZUPF41 utCUjd396YBehKkYMEmrRy4GP6QkmxuYFD7L2LBro+x9SzGKxh5BvzwrXlX1jpWNJG /RZq8/R9DjgcA== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() Date: Mon, 27 Apr 2026 19:13:48 +0200 Message-ID: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2390; i=chleroy@kernel.org; h=from:subject:message-id; bh=VVuQn2YnZFi2JH9uh9hmEqXb1BpygsXabSyFGnhBvmI=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxljeGSBfXj99HCNy2WTVFXXC9z/Hmi+//aE1/MbC +50nw1Q6ChlYRDjYpAVU2Q5/p9714yuL6n5U3fpw8xhZQIZwsDFKQAT2djH8D+e3yYgNP/F6xtd z9QNXjIccVycwR574E38S3tWp2uq95Yy/M9xKJ2hYJCUJV9391rVwmlfl7x6GzD19bqwZeyVdgF fZ3MAAA== X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1777310341-7FB78F3B-73370ACE/0/0 X-purgate-type: clean X-purgate-size: 2392 At the time being, x86 and arm64 are missing unsafe_copy_from_user(). Add it. Signed-off-by: Christophe Leroy (CS GROUP) --- arch/x86/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 3a0dd3c2b233..10c458ffa399 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -598,7 +598,7 @@ _label: \ * We want the unsafe accessors to always be inlined and use * the error labels - thus the macro games. */ -#define unsafe_copy_loop(dst, src, len, type, label) \ +#define unsafe_put_loop(dst, src, len, type, label) \ while (len >= sizeof(type)) { \ unsafe_put_user(*(type *)(src),(type __user *)(dst),label); \ dst += sizeof(type); \ @@ -611,10 +611,29 @@ do { \ char __user *__ucu_dst = (_dst); \ const char *__ucu_src = (_src); \ size_t __ucu_len = (_len); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ +} while (0) + +#define unsafe_get_loop(dst, src, len, type, label) \ + while (len >= sizeof(type)) { \ + unsafe_get_user(*(type __user *)(src),(type *)(dst),label); \ + dst += sizeof(type); \ + src += sizeof(type); \ + len -= sizeof(type); \ + } + +#define unsafe_copy_from_user(_dst,_src,_len,label) \ +do { \ + char *__ucu_dst = (_dst); \ + const char __user *__ucu_src = (_src); \ + size_t __ucu_len = (_len); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ } while (0) #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:19:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:19:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295187.1571882 (Exim 4.92) (envelope-from ) id 1wHPc4-0002N3-0M; Mon, 27 Apr 2026 17:19:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295187.1571882; Mon, 27 Apr 2026 17:19:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHPc3-0002Mw-Sv; Mon, 27 Apr 2026 17:19:15 +0000 Received: by outflank-mailman (input) for mailman id 1295187; Mon, 27 Apr 2026 17:19:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHPc2-0002Lo-DM for xen-devel@lists.xenproject.org; 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dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310352; bh=vbZIj5I8a11ig9c375SeIMkNInKGe+jckYb8HPag1tw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lp9wELlrvJvoeuCK0/zMI5UANnrsQ+T4se/gBOunN8iQDrEi1RstW5G65/9vUEPmI U9UXqoktuU7EViGdT+8yzDZHjl2N0E5vd9veY8uQePuAD9x0oGHf4CotQwSmAD24go gSXTECesL9+kQmgNOk7myjSgr8UboLxcnh/OrEADTLSIqRqZRx4YwXDl6QWc3wVNsO sB/2ZwfKCyhos7Vj9aXXCgNggtmoXoIYLpWXmI9TjsLctEcOG8w3vDT/K6+fVh16nS /UcGgkCV5vp5qC1VRJeMqVPGsaV7+wscOAZaxlqKS8j4DsLjsIu1iQmtuFIX3tL+zm kvFBNXQR3j5iw== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 8/9] arm64: Add unsafe_copy_from_user() Date: Mon, 27 Apr 2026 19:13:49 +0200 Message-ID: <5b09e58a84c9edcfe5724db5cd57e45d96a96bfa.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2498; i=chleroy@kernel.org; h=from:subject:message-id; bh=vbZIj5I8a11ig9c375SeIMkNInKGe+jckYb8HPag1tw=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxmbKDOhb/vkF5+62Iv+nzi0lmWmkWf+tSO3HK9yP D89hV+LoaOUhUGMi0FWTJHl+H/uXTO6vqTmT92lDzOHlQlkCAMXpwBMJCKWkeGFnFP5dUbGE1cO pXr18eg3ndoc9ubDcl2tYxbdt9o1nmkyMvQuDCp+FV4TvfDP3c6+r/YFCyvUNTZlcrea/2SZ/OM dBwcA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1777310353-312463FF-237AE988/0/0 X-purgate-type: clean X-purgate-size: 2500 At the time being, x86 and arm64 are missing unsafe_copy_from_user(). Add it. Signed-off-by: Christophe Leroy (CS GROUP) --- arch/arm64/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 1e20ec91b56f..adfdb52cd82b 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -437,7 +437,7 @@ static inline void user_access_restore(unsigned long enabled) { } * We want the unsafe accessors to always be inlined and use * the error labels - thus the macro games. */ -#define unsafe_copy_loop(dst, src, len, type, label) \ +#define unsafe_put_loop(dst, src, len, type, label) \ while (len >= sizeof(type)) { \ unsafe_put_user(*(type *)(src),(type __user *)(dst),label); \ dst += sizeof(type); \ @@ -450,10 +450,29 @@ do { \ char __user *__ucu_dst = (_dst); \ const char *__ucu_src = (_src); \ size_t __ucu_len = (_len); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ +} while (0) + +#define unsafe_get_loop(dst, src, len, type, label) \ + while (len >= sizeof(type)) { \ + unsafe_get_user(*(type __user *)(src),(type *)(dst),label); \ + dst += sizeof(type); \ + src += sizeof(type); \ + len -= sizeof(type); \ + } + +#define unsafe_copy_from_user(_dst,_src,_len,label) \ +do { \ + char *__ucu_dst = (_dst); \ + const char __user *__ucu_src = (_src); \ + size_t __ucu_len = (_len); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ } while (0) extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n); -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 17:19:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 17:19:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295196.1571891 (Exim 4.92) (envelope-from ) id 1wHPcG-0002qN-61; Mon, 27 Apr 2026 17:19:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295196.1571891; Mon, 27 Apr 2026 17:19:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHPcG-0002qG-3I; Mon, 27 Apr 2026 17:19:28 +0000 Received: by outflank-mailman (input) for mailman id 1295196; Mon, 27 Apr 2026 17:19:27 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHPcF-0002pV-0A for xen-devel@lists.xenproject.org; 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dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777310364; bh=xblTv37x9V4gU3cvmA9ILfz6xXNOv0sNe2zU9C6a5nw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k8kV5Zhk7HZbxy8X7mxqUL5UgTTJPPuuLtSKHKOe5PwbIiNodL9/7ESxRbcOMv4dB NN/pd897F5mMQZv6MW+RM/3mikWvqmJGQCtupbd6YHiobStaCQu79RRkwt3Bs1rL/A WmXtcy3vIzgejB2MGSu6MrKJ33itreKKdFlemNypyCUExoUHGXA1bHbqFqaNX4ujdd iXZiXWTV/w69yfgs2V8e+zdWAilhhtsvDDxzPIT8CbbievjXPmrPwVloE5aoqLKmYP ca2+sf92YJQm2mLHcpyNlGd6mMQP6QhUed6Hx8vk/CloBjO7tSgz4fayv+CeXka+Fz NwGM6tvALNVmQ== From: "Christophe Leroy (CS GROUP)" To: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: "Christophe Leroy (CS GROUP)" , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: [RFC PATCH v1 9/9] uaccess: Convert small fixed size copy_{to/from}_user() to scoped user access Date: Mon, 27 Apr 2026 19:13:50 +0200 Message-ID: <8780eb2ef80575931a339e5225bc80eb13e9be6c.1777306795.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3638; i=chleroy@kernel.org; h=from:subject:message-id; bh=xblTv37x9V4gU3cvmA9ILfz6xXNOv0sNe2zU9C6a5nw=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS+nxlr/n9yu2DE7uwkCZGbl0uCp6Y1JLvZTPpz+P/PY xNqPMoaOkpZGMS4GGTFFFmO/+feNaPrS2r+1F36MHNYmUCGMHBxCsBE9HwZ/ns82Ho9PV2Q+7Pp 5fqvs6O/v3YN+3EgL+Wk4b/co1rlkZ8YGVZxmDl7XFiUcmPSTPW14WGSHT6/1u4pcTY2cjD0U7P bzAkA X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1777310366-BCC6CFF4-9C02882D/0/0 X-purgate-type: clean X-purgate-size: 3640 copy_{to/from}_user() is a heavy function optimised for copy of large blocs of memory between user and kernel space. When the number of bytes to be copied is known at build time and small, using scoped user access removes the burden of that optimisation. Signed-off-by: Christophe Leroy (CS GROUP) --- include/linux/uaccess.h | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index 33b7d0f5f808..3ac544527af2 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -50,6 +50,8 @@ #define mask_user_address(src) (src) #endif +#define SMALL_COPY_USER 64 + /* * Architectures should provide two primitives (raw_copy_{to,from}_user()) * and get rid of their private instances of copy_{to,from}_user() and @@ -191,6 +193,9 @@ _inline_copy_from_user(void *to, const void __user *from, unsigned long n) return res; } +static __always_inline __must_check unsigned long +_small_copy_from_user(void *to, const void __user *from, unsigned long n); + extern __must_check unsigned long _copy_from_user(void *, const void __user *, unsigned long); @@ -207,6 +212,9 @@ _inline_copy_to_user(void __user *to, const void *from, unsigned long n) return n; } +static __always_inline __must_check unsigned long +_small_copy_to_user(void __user *to, const void *from, unsigned long n); + extern __must_check unsigned long _copy_to_user(void __user *, const void *, unsigned long); @@ -215,6 +223,8 @@ copy_from_user_common(void *to, const void __user *from, unsigned long n, bool p { if (!check_copy_size(to, n, false)) return n; + if (!partial && __builtin_constant_p(n) && n <= SMALL_COPY_USER) + return _small_copy_from_user(to, from, n); if (IS_ENABLED(ARCH_WANTS_NOINLINE_COPY_USER)) return _copy_from_user(to, from, n); else @@ -239,6 +249,8 @@ copy_to_user_common(void __user *to, const void *from, unsigned long n, bool par if (!check_copy_size(from, n, true)) return n; + if (!partial && __builtin_constant_p(n) && n <= SMALL_COPY_USER) + return _small_copy_to_user(to, from, n); if (IS_ENABLED(ARCH_WANTS_NOINLINE_COPY_USER)) return _copy_to_user(to, from, n); else @@ -838,6 +850,41 @@ for (bool done = false; !done; done = true) \ #define scoped_user_rw_access(uptr, elbl) \ scoped_user_rw_access_size(uptr, sizeof(*(uptr)), elbl) +static __always_inline __must_check unsigned long +_small_copy_from_user(void *to, const void __user *from, unsigned long n) +{ + might_fault(); + instrument_copy_from_user_before(to, from, n); + scoped_user_read_access_size(from, n, failed) { + /* + * Ensure that bad access_ok() speculation will not lead + * to nasty side effects *after* the copy is finished: + */ + if (!can_do_masked_user_access()) + barrier_nospec(); + unsafe_copy_from_user(to, from, n, failed); + } + instrument_copy_from_user_after(to, from, n, 0); + return 0; +failed: + instrument_copy_from_user_after(to, from, n, n); + return n; +} + +static __always_inline __must_check unsigned long +_small_copy_to_user(void __user *to, const void *from, unsigned long n) +{ + might_fault(); + if (should_fail_usercopy()) + return n; + instrument_copy_to_user(to, from, n); + scoped_user_write_access_size(to, n, failed) + unsafe_copy_to_user(to, from, n, failed); + return 0; +failed: + return n; +} + /** * get_user_inline - Read user data inlined * @val: The variable to store the value read from user memory -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 18:21:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 18:21:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295218.1571900 (Exim 4.92) (envelope-from ) id 1wHQaG-0005Zo-QW; Mon, 27 Apr 2026 18:21:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295218.1571900; Mon, 27 Apr 2026 18:21:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHQaG-0005Zh-N2; Mon, 27 Apr 2026 18:21:28 +0000 Received: by outflank-mailman (input) for mailman id 1295218; Mon, 27 Apr 2026 18:21:28 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHQaG-0005Zb-1i for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 18:21:28 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHQaE-00DKp2-OU for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 20:21:26 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69efa912-2eae-0a2a0a5409dd-0a2a4509a59e-40 for ; Mon, 27 Apr 2026 20:21:26 +0200 Received: from [172.234.252.31] (helo=sea.source.kernel.org) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69efa924-2497-0a2a45090019-aceafc1fc93a-3 for ; Mon, 27 Apr 2026 20:21:26 +0200 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 46E9540246; Mon, 27 Apr 2026 18:20:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3CCCFC2BCB5; Mon, 27 Apr 2026 18:20:40 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:Subject:To:Cc:References:From:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777314053; bh=fSfdZ5/fBIJBn92+lTQ8RknrFiSruKk4Zm5FPbyuhQI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=J2scZpbKenpOejPaCkxdr8Fr6c4RornKyxLjF0dKFYhSlw+matCdj3SDWlLeqEo9E a373XI9Iold2YwxLkAFI1OVkbxbR9JLgxu/comiCZJeBJjQK8IiPFbF3a0OQIu5zFJ z32D8XDVz5Fo00XfpR09lc3WO+fPx7ont3FOA+TL4jxGM7w1J5Z2cHWcv2Vi05coRU 6lIPjD/Eh4XtMiOh4PUlJfQ+hbcnF50oIaF0Y5is14Jb9Uy7pNbq6e4WVWxwPn3QZF F5175xYuXBtUSK+HvgeuPZTDTXog5e6524IUP62vgqpWl/U/vR5Pqvo+DbOYeGkne+ cSOzK+yVIhXWw== Message-ID: <63a4d0f6-0eb3-48cd-9f98-bf7b223b2606@kernel.org> Date: Mon, 27 Apr 2026 20:20:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() To: Yury Norov Cc: Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org References: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> Content-Language: fr-FR From: "Christophe Leroy (CS GROUP)" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777314086-408AFA53-AF96D79F/0/0 X-purgate-type: clean X-purgate-size: 3340 Le 27/04/2026 à 19:58, Yury Norov a écrit : > On Mon, Apr 27, 2026 at 07:13:48PM +0200, Christophe Leroy (CS GROUP) wrote: >> At the time being, x86 and arm64 are missing unsafe_copy_from_user(). > > No, they don't. They (should) rely on a generic implementation from > linux/uaccess.h, like every other arch, except for PPC and RISCV. > > But they #define arch_unsafe_get_user, and the unsafe_copy_from_user() > becomes undefined conditionally on that. > > So please, fix that bug instead of introducing another arch flavor. > We'd always choose generic version, unless there's strong evidence > that arch one is better. But they both implement the exact same unsafe_copy_to_user(). What is the difference here ? Should that function become generic too ? Christophe > > > Thanks, > Yury > >> Add it. >> >> Signed-off-by: Christophe Leroy (CS GROUP) >> --- >> arch/x86/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- >> 1 file changed, 24 insertions(+), 5 deletions(-) >> >> diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h >> index 3a0dd3c2b233..10c458ffa399 100644 >> --- a/arch/x86/include/asm/uaccess.h >> +++ b/arch/x86/include/asm/uaccess.h >> @@ -598,7 +598,7 @@ _label: \ >> * We want the unsafe accessors to always be inlined and use >> * the error labels - thus the macro games. >> */ >> -#define unsafe_copy_loop(dst, src, len, type, label) \ >> +#define unsafe_put_loop(dst, src, len, type, label) \ >> while (len >= sizeof(type)) { \ >> unsafe_put_user(*(type *)(src),(type __user *)(dst),label); \ >> dst += sizeof(type); \ >> @@ -611,10 +611,29 @@ do { \ >> char __user *__ucu_dst = (_dst); \ >> const char *__ucu_src = (_src); \ >> size_t __ucu_len = (_len); \ >> - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ >> - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ >> - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ >> - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ >> + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ >> + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ >> + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ >> + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ >> +} while (0) >> + >> +#define unsafe_get_loop(dst, src, len, type, label) \ >> + while (len >= sizeof(type)) { \ >> + unsafe_get_user(*(type __user *)(src),(type *)(dst),label); \ >> + dst += sizeof(type); \ >> + src += sizeof(type); \ >> + len -= sizeof(type); \ >> + } >> + >> +#define unsafe_copy_from_user(_dst,_src,_len,label) \ >> +do { \ >> + char *__ucu_dst = (_dst); \ >> + const char __user *__ucu_src = (_src); \ >> + size_t __ucu_len = (_len); \ >> + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ >> + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ >> + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ >> + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ >> } while (0) >> >> #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT >> -- >> 2.49.0 >> From xen-devel-bounces@lists.xenproject.org Mon Apr 27 18:52:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 18:52:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295227.1571920 (Exim 4.92) (envelope-from ) id 1wHR4V-0001ud-Hh; Mon, 27 Apr 2026 18:52:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295227.1571920; Mon, 27 Apr 2026 18:52:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHR4V-0001tn-CQ; Mon, 27 Apr 2026 18:52:43 +0000 Received: by outflank-mailman (input) for mailman id 1295227; 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b=pmvWhp/oxEcxQMryFRvqYtTB0A/GaOLun2mURAQK9jJXjqt4Nrc84ZfAfdVzaosEdXMWAP59oi4+UbMy4mec1KbzWHAyoF57I8DflvmrAbfhIb57bYv5qY2FGaPKUQk1zJRQQp9CqnyFj5VocFwyiXwUgS9FNTnrrFLeiZOJ1G9JrF4fAHR8lxFNj5/FwsIq3FU1ajVbQb2H+3//9zc7t+U20kMXMalri61t8NRsJ5k3/mDo4BdG+GEoyoHOcMDJdBMl8UX3LCr93JIqZbyQOPZZ1D/mW+4NjIfkYIV4DzD/8KPPzEEOg0Q59M3wKfLfO1wJ1sZJFQP38+wbciAclw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Date: Mon, 27 Apr 2026 14:39:16 -0400 From: Yury Norov To: "Christophe Leroy (CS GROUP)" Cc: Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery Message-ID: References: <9fe875d2f55af59c12708336c571a46038528678.1777306795.git.chleroy@kernel.org> Content-Type: text/plain; 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Can you name it CONFIG_OUTLINE_USERCOPY, or similar? > selected by the 5 architectures that don't want inlined copy. > > To minimise complication in a later patch, also remove > ifdefery and replace it with IS_ENABLED(). > > Signed-off-by: Christophe Leroy (CS GROUP) Andrew has taken my consolidation patch for INLINE_COPY_USER: https://lore.kernel.org/all/20260427085814.7ca0b134603b8d5813e23396@linux-foundation.org/ Please base your series on top of it. I'm not sure this patch is relevant to the goal of your series. Maybe send it separately? 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charset="utf-8" X-purgate-ID: tlsNG-bad1c0/1777313250-414B1A53-90F3E03D/0/0 X-purgate-type: clean X-purgate-size: 871 On Mon, Apr 27, 2026 at 07:13:46PM +0200, Christophe Leroy (CS GROUP) wrote: > diff --git a/rust/helpers/uaccess.c b/rust/helpers/uaccess.c > index 01de4fbbcc84..710e07cd60ae 100644 > --- a/rust/helpers/uaccess.c > +++ b/rust/helpers/uaccess.c > @@ -5,13 +5,13 @@ > __rust_helper unsigned long > rust_helper_copy_from_user(void *to, const void __user *from, unsigned long n) > { > - return copy_from_user(to, from, n); > + return copy_from_user_partial(to, from, n); > } > > __rust_helper unsigned long > rust_helper_copy_to_user(void __user *to, const void *from, unsigned long n) > { > - return copy_to_user(to, from, n); > + return copy_to_user_partial(to, from, n); > } No Rust code uses the return value for anything other than comparing it with zero, so you can keep these as copy_[from|to]_user() without issues. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?6ev31P6fGlLQLOmFhG9wf+2ZENF2CJrasImnLdTMkk4B07wVpIqdqcEhUwVr?= =?us-ascii?Q?VcuKpfWBww+Qglw6NKPvrbqw/iKodwZS6hoQ2ezn6gKQJTXowcVzIMKKmPVI?= =?us-ascii?Q?CaGe2PzzTfbrd+1/kBuQd5inX41eLfMXGSMB4El+/BGeY7LidWaO2U6MXIZl?= =?us-ascii?Q?To5KMHCCmaxaSW+0abx+uHxslGaDNGAxlD0ajEnVCyj2PyGw8gfavgZvUBeC?= =?us-ascii?Q?31Pn2vGdNJPTEao0o8nkBbqzRysmZBZFRsyFAwtcHiF+LMJewEDkGWcf3C7D?= =?us-ascii?Q?MhvHUO7rY2T4Gp8yOxYlhdkCQq0m4ykawDCJw9P3w79tbrFqeU7DKZcc6Svj?= =?us-ascii?Q?gpUdDiMP1u+wbi6ktqsa2/SBsCawL8yd85/gdX8JeS4P5U//2zVMdqlbS5oF?= =?us-ascii?Q?Om8kn23qHMWd1W0xp+L9zqhhURuKBI3C8K6/P0P2OiLTdsZ7lPLULvDBkdZf?= =?us-ascii?Q?UKjydMyY/3pcrF3sadi8xEKK6PbOoyabovH4OGdbUvrwD7GG4qRTd8pK59oC?= =?us-ascii?Q?snIKpVz1xKnwCa6xY5VnFP5/u/JjDPLADrD/WslKg8YXRFtCzAtBrdImcj0f?= =?us-ascii?Q?8yOAh4lyWUDPVX2WM00ySuZhGhvO+v6NJ73vz9XlsUfOsWyYZ9DOEzjUfhbH?= =?us-ascii?Q?0YLtM7C7LxhLfanXFKSW+D7acdbl8uANIv2lLYjkqPUxgpfNe8f+7W2LB5Nn?= =?us-ascii?Q?7Np0MclwQhDcY1GLCNhmF+qQmAOMVCLRhyHjLhLWkRHgj+alwIysbQ3EuYLN?= =?us-ascii?Q?5yHcsNNjsFo0wDyhRUVx5wyCMlW+Z4NGoPr32ydxiktuCQaON6kbvoanfM01?= =?us-ascii?Q?VM4/fS2+speM2tcePSAnjiQa5qjOFuYZ0VtZfeGTBIZ1yXD2cHpN1ixZN0Rz?= =?us-ascii?Q?L/dQY0op7e/9Yk5F3A4lFGTivTaixUSEIjTezh3qI+wT/tBYEl0Z0XCO2hjU?= =?us-ascii?Q?sFOU7EJ1CIL6HbyGijpDH3Yp4I8rMW9VuNbKDzbyWnaJJg9tVdo0/XIJrdAh?= =?us-ascii?Q?vVKIJZb+31gwlMVE1kXLTM4rt1jmj4rcA1rNCuw4fD++YKU0KqxirVrsn6kC?= =?us-ascii?Q?lZa0X05s4hYIlo7g4DALYttelKqcNX1HEGU6vO71rQrVfydGtRIQzA8hZ8rQ?= =?us-ascii?Q?O80VU2eqMYB7eYpBItWytqLFV33JZ/cuulFCjhdnG06CQcNI6/4ovyhT3Aa8?= =?us-ascii?Q?PiZXBZphvtTKhhJqQ1c7RRKZs8niebQgxVT+NqLMFlyPhkta2YjjpBXgNIIx?= =?us-ascii?Q?h+iPSpkL/BZ7G18/IWgE5T5t9GEq5s5xWwSmey7027/BRYe03neS8L78GvQZ?= =?us-ascii?Q?5ceRI/ymV7A6xiSGKp4h0GdJvHPIvbvLvAXTNPJXPyEy/lkYzUg06m/F5Ppx?= =?us-ascii?Q?Ucqpyqpi7uPkJEjc3424leqnNg3d1TwAm//hlnXAadNRP0K+njbmTw4CpTe2?= =?us-ascii?Q?4HHWlSZ9YpBEw+Ohv14Uf9RwjiFvVAghctOlWmh5sz2AhDjQMGMs8VSWcPgV?= =?us-ascii?Q?CT54kkzGd7BsoQ2aPoLVEhjPxQJKnRuZKDOQB6HL77e6jo+Karv0u6QI8scU?= =?us-ascii?Q?/P+zWIUoY7Vp26Mnav/FMyG/vDm64Qhe7JrRNaXxdZN6cKMY0RccPxeEvM6K?= =?us-ascii?Q?cokd+q0bbXdS3sEK+pM8MrC/A2+EernBjELOWvLW6UNcdosIRiZXx3jxfYAW?= =?us-ascii?Q?NoTKA/lHF00/AFzSuUQZeA/Bt64WCRihJQrbIN0bhLrfQCWWaLbXoiNjdnxt?= =?us-ascii?Q?OgQB96s+EfSA5RhJu/4bwnEHg5Lb6TZfXmPjZN7/WMw6zB/yunPn?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 33128524-511f-440c-0040-08dea486a4e3 X-MS-Exchange-CrossTenant-AuthSource: CY8PR12MB8300.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 17:58:53.4408 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DFLDrWxkcKDSdWjcRZ0FWTXyKov5/udW2ySQZAiU/0h1WJYCpRdFgW8eHZBY8qsOSQ9+hnLtwBfn4bjMnIR9OQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4352 X-purgate-ID: tlsNG-bad1c0/1777312750-484A9A53-2BCE8B9B/0/0 X-purgate-type: clean X-purgate-size: 3028 On Mon, Apr 27, 2026 at 07:13:48PM +0200, Christophe Leroy (CS GROUP) wrote: > At the time being, x86 and arm64 are missing unsafe_copy_from_user(). No, they don't. They (should) rely on a generic implementation from linux/uaccess.h, like every other arch, except for PPC and RISCV. But they #define arch_unsafe_get_user, and the unsafe_copy_from_user() becomes undefined conditionally on that. So please, fix that bug instead of introducing another arch flavor. We'd always choose generic version, unless there's strong evidence that arch one is better. Thanks, Yury > Add it. > > Signed-off-by: Christophe Leroy (CS GROUP) > --- > arch/x86/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h > index 3a0dd3c2b233..10c458ffa399 100644 > --- a/arch/x86/include/asm/uaccess.h > +++ b/arch/x86/include/asm/uaccess.h > @@ -598,7 +598,7 @@ _label: \ > * We want the unsafe accessors to always be inlined and use > * the error labels - thus the macro games. > */ > -#define unsafe_copy_loop(dst, src, len, type, label) \ > +#define unsafe_put_loop(dst, src, len, type, label) \ > while (len >= sizeof(type)) { \ > unsafe_put_user(*(type *)(src),(type __user *)(dst),label); \ > dst += sizeof(type); \ > @@ -611,10 +611,29 @@ do { \ > char __user *__ucu_dst = (_dst); \ > const char *__ucu_src = (_src); \ > size_t __ucu_len = (_len); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > +} while (0) > + > +#define unsafe_get_loop(dst, src, len, type, label) \ > + while (len >= sizeof(type)) { \ > + unsafe_get_user(*(type __user *)(src),(type *)(dst),label); \ > + dst += sizeof(type); \ > + src += sizeof(type); \ > + len -= sizeof(type); \ > + } > + > +#define unsafe_copy_from_user(_dst,_src,_len,label) \ > +do { \ > + char *__ucu_dst = (_dst); \ > + const char __user *__ucu_src = (_src); \ > + size_t __ucu_len = (_len); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > } while (0) > > #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT > -- > 2.49.0 > From xen-devel-bounces@lists.xenproject.org Mon Apr 27 19:02:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 19:02:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295253.1571936 (Exim 4.92) (envelope-from ) id 1wHRDp-0004yz-BS; Mon, 27 Apr 2026 19:02:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295253.1571936; Mon, 27 Apr 2026 19:02:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHRDp-0004ys-8o; Mon, 27 Apr 2026 19:02:21 +0000 Received: by outflank-mailman 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21:01:21 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=s31663417 header.d=gmx.de header.i="deller@gmx.de" header.h="X-UI-Sender-Class:Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Content-Type:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmx.de; s=s31663417; t=1777316482; x=1777921282; i=deller@gmx.de; bh=Zt1qoBiZgQM1t1btlI0mC79addHEa7yO7OT0uaav6JI=; h=X-UI-Sender-Class:Message-ID:Date:MIME-Version:Subject:To:Cc: References:From:In-Reply-To:Content-Type: Content-Transfer-Encoding:cc:content-transfer-encoding: content-type:date:from:message-id:mime-version:reply-to:subject: to; b=pvJKKcq2bvRAhsxjqAkSqPCTHz+c9uXutnBUNfweFC5C6v6Q3EgeOKe/MJanf1Ba sAehF4t5/xUIpLJRVOl0YNFM0UY2s1ZtmOUE+OxOPa2dZ4N+GaoaNXUJVeKbqUObc zWTti5uW04mbR8LXlYdWXdzH0idgP2vWBzyha8fXbLatDwnhl5ulQbpKW/B/LIbfq m9Sk/0zz5Hq5YiFn5LKjsXeE3bvcDSyAbbuH306N8cXcn/B+mqRHa0DLJIfFBgcYb SPUzS1OgVVxqH7BapIrTRFMwx269SyWfjiAxp4nbh+xegJyY+50MN5oyqjtATSzbv OtP1eu9OBKhkgrJwaA== X-UI-Sender-Class: 724b4f7f-cbec-4199-ad4e-598c01a50d3a Message-ID: <844ee1e8-e7e2-40ef-a2b1-b7a6b6a44cb2@gmx.de> Date: Mon, 27 Apr 2026 21:01:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v1 0/9] uaccess: Convert small fixed size copy_{to/from}_user() to scoped user access To: "Christophe Leroy (CS GROUP)" , Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner Cc: linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, 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Content-Language: en-US From: Helge Deller Autocrypt: addr=deller@gmx.de; keydata= xsFNBF3Ia3MBEAD3nmWzMgQByYAWnb9cNqspnkb2GLVKzhoH2QD4eRpyDLA/3smlClbeKkWT HLnjgkbPFDmcmCz5V0Wv1mKYRClAHPCIBIJgyICqqUZo2qGmKstUx3pFAiztlXBANpRECgwJ r+8w6mkccOM9GhoPU0vMaD/UVJcJQzvrxVHO8EHS36aUkjKd6cOpdVbCt3qx8cEhCmaFEO6u CL+k5AZQoABbFQEBocZE1/lSYzaHkcHrjn4cQjc3CffXnUVYwlo8EYOtAHgMDC39s9a7S90L 69l6G73lYBD/Br5lnDPlG6dKfGFZZpQ1h8/x+Qz366Ojfq9MuuRJg7ZQpe6foiOtqwKym/zV dVvSdOOc5sHSpfwu5+BVAAyBd6hw4NddlAQUjHSRs3zJ9OfrEx2d3mIfXZ7+pMhZ7qX0Axlq Lq+B5cfLpzkPAgKn11tfXFxP+hcPHIts0bnDz4EEp+HraW+oRCH2m57Y9zhcJTOJaLw4YpTY GRUlF076vZ2Hz/xMEvIJddRGId7UXZgH9a32NDf+BUjWEZvFt1wFSW1r7zb7oGCwZMy2LI/G aHQv/N0NeFMd28z+deyxd0k1CGefHJuJcOJDVtcE1rGQ43aDhWSpXvXKDj42vFD2We6uIo9D 1VNre2+uAxFzqqf026H6cH8hin9Vnx7p3uq3Dka/Y/qmRFnKVQARAQABzRxIZWxnZSBEZWxs ZXIgPGRlbGxlckBnbXguZGU+wsGRBBMBCAA7AhsDBQsJCAcCBhUKCQgLAgQWAgMBAh4BAheA FiEERUSCKCzZENvvPSX4Pl89BKeiRgMFAl3J1zsCGQEACgkQPl89BKeiRgNK7xAAg6kJTPje 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for > copying large amount of data, with cache management, etc ...=20 They take care of much more: alignments, exception handling (e.g. if userp= age is read-only and kernel writes to it), various rules when to return faults (e.g. sometime reading from page0 is allowed for other arches not), and much more. I've seen so many strange things during the last few years, and you would need to get it right if you want to "make small" versions of those functions. > This is often overkill for small copies that could just be inlined > instead. Isn't put_user() and get_user() for that ? And if you inline you need to take care of faults as well, so indirectly you will add more fault handlers (or fault pointers) to the generated code= , effectively making the kernel bigger. > What makes things a bit more tricky is that those copy functions > are designed to handle partial copies in case of page fault. But among > the 6000 callers of those functions, only 2% really care about the > quantity of no-copied data that those functions return. All other ones > fails as soon as the returned value is not 0, returning -EACCESS. >=20 > So first step in this series is to introduce variants called > copy_from_user_partial() and copy_to_user_partial() which will be > called by the 2% users that care about the partial copy, then the > original copy_from_user() and copy_to_user() are changed to return > -EFAULT when the copy fails. >=20 > Then the second step is to implement copy of small fixed-size data > with scoped user access instead of calling the arch specific heavy > user copy functions. I'm not against your idea or your patch, but I wonder if you really gain much from it. Have you done some size or speed comparisons ? Helge > Patch 5, can be split in different patches for each archicture or > subsystem, but let's get a first feedback and agree on the principle. >=20 > Christophe Leroy (CS GROUP) (9): > uaccess: Split check_zeroed_user() out of usercopy.c > uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce > ifdefery > x86/umip: Be stricter in fixup_umip_exception() > uaccess: Introduce copy_{to/from}_user_partial() > uaccess: Switch to copy_{to/from}_user_partial() when relevant > uaccess: Change copy_{to/from}_user to return -EFAULT > x86: Add unsafe_copy_from_user() > arm64: Add unsafe_copy_from_user() > uaccess: Convert small fixed size copy_{to/from}_user() to scoped use= r > access >=20 > arch/alpha/Kconfig | 1 + > arch/alpha/kernel/osf_sys.c | 4 +- > arch/alpha/kernel/termios.c | 2 +- > arch/arc/include/asm/uaccess.h | 3 - > arch/arc/kernel/disasm.c | 2 +- > arch/arm/include/asm/uaccess.h | 2 - > arch/arm64/include/asm/gcs.h | 2 +- > arch/arm64/include/asm/uaccess.h | 30 +++-- > arch/arm64/kernel/signal32.c | 2 +- > arch/csky/Kconfig | 1 + > arch/hexagon/include/asm/uaccess.h | 3 - > arch/loongarch/include/asm/uaccess.h | 3 - > arch/m68k/include/asm/uaccess.h | 3 - > arch/microblaze/include/asm/uaccess.h | 2 - > arch/mips/include/asm/uaccess.h | 3 - > arch/mips/kernel/rtlx.c | 8 +- > arch/mips/kernel/vpe.c | 2 +- > arch/nios2/include/asm/uaccess.h | 2 - > arch/openrisc/include/asm/uaccess.h | 2 - > arch/parisc/include/asm/uaccess.h | 3 - > arch/powerpc/Kconfig | 1 + > arch/powerpc/kvm/book3s_64_mmu_hv.c | 4 +- > arch/powerpc/kvm/book3s_64_mmu_radix.c | 4 +- > arch/powerpc/kvm/book3s_hv.c | 2 +- > arch/riscv/Kconfig | 1 + > arch/riscv/kernel/signal.c | 2 +- > arch/s390/include/asm/idals.h | 8 +- > arch/s390/include/asm/uaccess.h | 3 - > arch/sh/include/asm/uaccess.h | 2 - > arch/sparc/include/asm/uaccess_32.h | 3 - > arch/sparc/include/asm/uaccess_64.h | 2 - > arch/sparc/kernel/termios.c | 2 +- > arch/um/include/asm/uaccess.h | 3 - > arch/um/kernel/process.c | 2 +- > arch/x86/Kconfig | 1 + > arch/x86/include/asm/uaccess.h | 29 ++++- > arch/x86/kernel/umip.c | 2 +- > arch/x86/lib/insn-eval.c | 2 +- > arch/x86/um/signal.c | 2 +- > arch/xtensa/include/asm/uaccess.h | 2 - > drivers/android/binder_alloc.c | 2 +- > drivers/comedi/comedi_fops.c | 4 +- > drivers/dma/idxd/cdev.c | 2 +- > drivers/firmware/efi/test/efi_test.c | 2 +- > drivers/fsi/fsi-scom.c | 2 +- > .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_sseu.c | 4 +- > drivers/gpu/drm/i915/i915_gem.c | 4 +- > drivers/hwtracing/intel_th/msu.c | 2 +- > drivers/misc/ibmvmc.c | 2 +- > drivers/misc/vmw_vmci/vmci_host.c | 2 +- > drivers/most/most_cdev.c | 2 +- > drivers/net/ieee802154/ca8210.c | 4 +- > drivers/net/wireless/ath/wil6210/debugfs.c | 2 +- > .../intel/iwlwifi/pcie/gen1_2/trans.c | 2 +- > drivers/net/wireless/ti/wlcore/debugfs.c | 2 +- > drivers/ps3/ps3-lpm.c | 2 +- > drivers/s390/crypto/zcrypt_api.h | 4 +- > drivers/spi/spidev.c | 2 +- > .../staging/media/atomisp/pci/atomisp_cmd.c | 8 +- > drivers/tty/tty_ioctl.c | 14 +-- > drivers/tty/vt/vc_screen.c | 4 +- > drivers/usb/gadget/function/f_hid.c | 4 +- > drivers/usb/gadget/function/f_printer.c | 2 +- > drivers/vfio/vfio_iommu_type1.c | 4 +- > drivers/xen/xenbus/xenbus_dev_frontend.c | 2 +- > fs/namespace.c | 2 +- > fs/ocfs2/dlmfs/dlmfs.c | 2 +- > fs/proc/base.c | 4 +- > include/asm-generic/uaccess.h | 2 - > include/linux/bpfptr.h | 2 +- > include/linux/sockptr.h | 4 +- > include/linux/uaccess.h | 107 ++++++++++++++---- > ipc/msg.c | 8 +- > ipc/sem.c | 8 +- > ipc/shm.c | 18 +-- > kernel/regset.c | 2 +- > kernel/sys.c | 4 +- > lib/Kconfig | 3 + > lib/Makefile | 4 +- > lib/kfifo.c | 8 +- > lib/{usercopy.c =3D> usercheck.c} | 22 ---- > lib/usercopy.c | 66 ----------- > mm/kasan/kasan_test_c.c | 4 +- > mm/memory.c | 2 +- > net/x25/af_x25.c | 2 +- > rust/helpers/uaccess.c | 6 +- > sound/pci/emu10k1/emufx.c | 4 +- > sound/pci/rme9652/hdsp.c | 6 +- > sound/soc/intel/avs/probes.c | 6 +- > sound/soc/sof/compress.c | 12 +- > sound/soc/sof/sof-client-probes.c | 6 +- > 92 files changed, 269 insertions(+), 288 deletions(-) > copy lib/{usercopy.c =3D> usercheck.c} (73%) >=20 From xen-devel-bounces@lists.xenproject.org Mon Apr 27 19:09:58 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 19:09:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295263.1571944 (Exim 4.92) (envelope-from ) id 1wHRL6-0006EC-2K; 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Mon, 27 Apr 2026 12:09:48 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ8NPsvz8QQkqW/e17SMSetiTbQPYiRboKuze0JPmCyF4O9iejTAV5DqGBXpiWVJGm/CaIRecYwOXAs=@lists.xenproject.org X-Received: by 2002:a17:907:9495:b0:ba3:a8ef:3597 with SMTP id a640c23a62f3a-bb80443c92emr2812866b.25.1777316502372; Mon, 27 Apr 2026 12:01:42 -0700 (PDT) MIME-Version: 1.0 References: <289b424e243ba2c4139ea04009cf8b9c448a87ff.1777306795.git.chleroy@kernel.org> In-Reply-To: <289b424e243ba2c4139ea04009cf8b9c448a87ff.1777306795.git.chleroy@kernel.org> From: Linus Torvalds Date: Mon, 27 Apr 2026 12:01:23 -0700 X-Gmail-Original-Message-ID: X-Gm-Features: AVHnY4JOOuu1ghb35GF5M7sO3SAfkj4A7WtLiFNY579kWyh92WWRKfW5QE_KjRI Message-ID: Subject: Re: [RFC PATCH v1 5/9] uaccess: Switch to copy_{to/from}_user_partial() when relevant To: "Christophe Leroy (CS GROUP)" Cc: Yury Norov , Andrew Morton , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: multipart/mixed; boundary="000000000000c765e2065075bee2" X-purgate-ID: tlsNG-bad1c0/1777316989-42B70A53-89EDEDB8/0/0 X-purgate-type: clean X-purgate-size: 10570 --000000000000c765e2065075bee2 Content-Type: text/plain; charset="UTF-8" On Mon, 27 Apr 2026 at 10:18, Christophe Leroy (CS GROUP) wrote: > > In a subsequent patch, copy_{to/from}_user() will be modified to > return -EFAULT when copy fails. Please don't do this. This is a maintenance nightmare, and changes pretty much three decades of semantics, and will cause *very* subtle backporting issues if somebody happens to rely on the old / new behavior. I understand the reasoning for the change, but I really don't think the pain of creating yet another user copy interface is worth it. We already have a lot of different versions of user copies for different reasons, and while they all tend to have a good reason (and some not-so-good, but historical reasons) for existing, this one doesn't seem worth it. The main - perhaps only - reason for this "partial" version is that you want to do that "automatically inlined and optimized fixed-sized case". But here's the thing: I think you can already do that. Yes, it requires some improvements to unsafe_copy_from_user(), but *that* interface doesn't have three decades of history associated with it, _and_ you're extending on that one anyway in this series. "unsafe_copy_from_user()" is very odd, is meant only for small simple copies that can be inlined and it's special-cased for 'objtool' anyway (because objtool would have complained about an out-of-line call, although it could have been special-cased other ways). In other words: unsafe_copy_from_user() is *very* close to what you want for that "Oh, I noticed that it's a small fixed-size copy, so I want to special-case copy-from-user for that". The _only_ issue with unsafe_copy_from_user() is that you can't see that there were partial successes. But if *that* was fixed, then this whole "create a new copy_from_user interface" issue would just go away. So please - let's just change unsafe_copy_from_user() to be usable for the partial case. And the thing is, all the existing unsafe_copy_from_user() implementations already effectively *have* the "how much did I not copy" internally, and they actually do extra work to hide it, ie they have things like that int _i; that is "how many bytes have I copied" in the powerpc implementation, or the x86 code does size_t __ucu_len = (_len); where that "ucu_len" is updated as you go along and is literally the "how many bytes are left to copy" return value that is missing from this interface. So what I would suggest is - introduce a new user accessor helper that is used for *both* unsafe_copy_to/from_user() *and* the "inline small constant-sized normal copy_to/from_user()" calls - it's the same thing as the existing unsafe_copy_to/from_user() implementation, except it exposes how many bytes are left to be copied to the exception label. IOW, it would look something like #define unsafe_copy_to_user_outlen(_dst,_src,_len,label)... which is exactly the same as the current unsafe_copy_to_user(), *except* it changes "_len" as it does along. And then you use that for both the "real" unsafe_copy_user and for the "small constant values" case. Just as an example, attached is a completely stupid rough draft of a patch that does this for x86 and only for unsafe_copy_to_user(). And I made a very very hacky change to kernel/sys.c to see what the code generation looks like. This is what it results in on x86 with clang (with all the magic .section data edited out): ... edited out the code to generate the times ... this is the actual user copy: # HERE! movabsq $81985529216486895, %rcx # imm = 0x123456789ABCDEF cmpq %rcx, %rbx cmovaq %rcx, %rbx stac movq %r13, (%rbx) # exception to .LBB45_8 movq %r14, 8(%rbx) # exception to .LBB45_8 movq %r15, 16(%rbx) # exception to .LBB45_8 movq %rax, 24(%rbx) # exception to .LBB45_8 clac .LBB45_6: movq jiffies(%rip), %rdi callq jiffies_64_to_clock_t .LBB45_7: addq $16, %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 retq .LBB45_8: clac movq $-14, %rax jmp .LBB45_7 and notice how the compiler noticed that the 'outlen' isn't actually used, and turned the exception label into just a "return -EFAULT" and never actually generated any code for updating remaining lengths? That actually looks pretty much optimal for a 32-byte user copy. And it didn't involve changing the semantics at all. Just to check, I changed that "times()" system call to return the number of bytes uncopied instead (to emulate the "I actually want to know what's left" case), and it generated this: # HERE! movabsq $81985529216486895, %rcx # imm = 0x123456789ABCDEF cmpq %rcx, %rbx cmovaq %rcx, %rbx stac movl $32, %ecx movq %r13, (%rbx) # exception to .LBB45_7 movl $24, %ecx movq %r15, 8(%rbx) # exception to .LBB45_7 movl $16, %ecx movq %r14, 16(%rbx) # exception to .LBB45_7 movl $8, %ecx movq %rax, 24(%rbx) # exception to .LBB45_7 clac xorl %ecx, %ecx .LBB45_8: movq %rcx, %rax addq $16, %rsp popq %rbx popq %r12 popq %r13 popq %r14 popq %r15 retq .LBB45_6: movq jiffies(%rip), %rdi jmp jiffies_64_to_clock_t # TAILCALL .LBB45_7: clac jmp .LBB45_8 so it all seems to work - although obviously the above is *not* the normal case. NOTE NOTE NOTE! The attached patch is entirely untested. I obviously did some "test code generation" with it, but I only *looked* at the result, and maybe it has some fundamental problem that I just didn't notice. So treat this as a "how about this approach" patch, not as anything more serious than that. And the kerrnel/sys.c hack is very obviously just that: a complate hack for testing. A real patch would do that "for small constant-sized copies, turn copy_to_user() automatically into "_small_copy_to_user()". The attached is *not* a real patch. Treat it with the contempt it deserves. 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They (should) rely on a generic implementation from > > linux/uaccess.h, like every other arch, except for PPC and RISCV. > > > > But they #define arch_unsafe_get_user, and the unsafe_copy_from_user() > > becomes undefined conditionally on that. > > > > So please, fix that bug instead of introducing another arch flavor. > > We'd always choose generic version, unless there's strong evidence > > that arch one is better. > > But they both implement the exact same unsafe_copy_to_user(). What is the > difference here ? > > Should that function become generic too ? This is what Linus said when added x86 implementation for copy_from_user() in c512c69187197: Note that it only does this [arch version] for the copying _to_ user space, and we still don't have a unsafe version of copy_from_user(). That's partly because we have no current users of it, but also partly because the copy_from_user() case is slightly different and cannot efficiently be implemented in terms of a unsafe_get_user() loop (because gcc can't do asm goto with outputs). In the unsafe_copy_to_user case, arch versions were justified. Just as said, I'm not against arch version for unsafe_copy_from_user(), but it should be explained very well. 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Can you name it > CONFIG_OUTLINE_USERCOPY, or similar? You can't swap the "in" for "out" like this.  "out of line" is the opposite of "inline" in this context, while "outline" means something different and unrelated. ~Andrew From xen-devel-bounces@lists.xenproject.org Mon Apr 27 20:48:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 20:48:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295312.1571980 (Exim 4.92) (envelope-from ) id 1wHSsB-00071H-Vv; Mon, 27 Apr 2026 20:48:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295312.1571980; Mon, 27 Apr 2026 20:48:07 +0000 Received: from [127.0.0.1] (helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHSsB-00071A-TE; Mon, 27 Apr 2026 20:48:07 +0000 Received: by outflank-mailman (input) for mailman id 1295312; Mon, 27 Apr 2026 20:48:06 +0000 Received: from [195.190.135.10] (helo=mx.expurgate.net) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHSsA-000714-Gp for xen-devel@lists.xenproject.org; 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Date: Mon, 27 Apr 2026 16:47:53 -0400 From: Yury Norov To: Andrew Cooper Cc: "Christophe Leroy (CS GROUP)" , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery Message-ID: References: <9fe875d2f55af59c12708336c571a46038528678.1777306795.git.chleroy@kernel.org> Content-Type: text/plain; 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Can you name it > > CONFIG_OUTLINE_USERCOPY, or similar? > > You can't swap the "in" for "out" like this. "out of line" is the > opposite of "inline" in this context, while "outline" means something > different and unrelated. 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Mon, 27 Apr 2026 14:29:18 -0700 (PDT) Date: Mon, 27 Apr 2026 22:29:14 +0100 From: David Laight To: Linus Torvalds Cc: "Christophe Leroy (CS GROUP)" , Yury Norov , Andrew Morton , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 5/9] uaccess: Switch to copy_{to/from}_user_partial() when relevant Message-ID: <20260427222914.1cb2dd3b@pumpkin> In-Reply-To: References: <289b424e243ba2c4139ea04009cf8b9c448a87ff.1777306795.git.chleroy@kernel.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ebf023/1777325359-3224E3FF-05D4547D/0/0 X-purgate-type: clean X-purgate-size: 7506 On Mon, 27 Apr 2026 12:01:23 -0700 Linus Torvalds wrote: > On Mon, 27 Apr 2026 at 10:18, Christophe Leroy (CS GROUP) > wrote: > > > > In a subsequent patch, copy_{to/from}_user() will be modified to > > return -EFAULT when copy fails. > > Please don't do this. > > This is a maintenance nightmare, and changes pretty much three decades > of semantics, and will cause *very* subtle backporting issues if > somebody happens to rely on the old / new behavior. > > I understand the reasoning for the change, but I really don't think > the pain of creating yet another user copy interface is worth it. > > We already have a lot of different versions of user copies for > different reasons, and while they all tend to have a good reason (and > some not-so-good, but historical reasons) for existing, this one > doesn't seem worth it. > > The main - perhaps only - reason for this "partial" version is that > you want to do that "automatically inlined and optimized fixed-sized > case". > > But here's the thing: I think you can already do that. Yes, it > requires some improvements to unsafe_copy_from_user(), but *that* > interface doesn't have three decades of history associated with it, > _and_ you're extending on that one anyway in this series. > > "unsafe_copy_from_user()" is very odd, is meant only for small simple > copies that can be inlined and it's special-cased for 'objtool' anyway > (because objtool would have complained about an out-of-line call, > although it could have been special-cased other ways). > > In other words: unsafe_copy_from_user() is *very* close to what you > want for that "Oh, I noticed that it's a small fixed-size copy, so I > want to special-case copy-from-user for that". > > The _only_ issue with unsafe_copy_from_user() is that you can't see > that there were partial successes. But if *that* was fixed, then this > whole "create a new copy_from_user interface" issue would just go > away. > > So please - let's just change unsafe_copy_from_user() to be usable for > the partial case. > > And the thing is, all the existing unsafe_copy_from_user() > implementations already effectively *have* the "how much did I not > copy" internally, and they actually do extra work to hide it, ie they > have things like that > > int _i; > > that is "how many bytes have I copied" in the powerpc implementation, > or the x86 code does > > size_t __ucu_len = (_len); > > where that "ucu_len" is updated as you go along and is literally the > "how many bytes are left to copy" return value that is missing from > this interface. > > So what I would suggest is > > - introduce a new user accessor helper that is used for *both* > unsafe_copy_to/from_user() *and* the "inline small constant-sized > normal copy_to/from_user()" calls > > - it's the same thing as the existing unsafe_copy_to/from_user() > implementation, except it exposes how many bytes are left to be copied > to the exception label. I think there is a slight difference in that the normal copy_to_user() will determine the exact offset of the error by retrying with byte copies. There is also the issue of misaligned copies. Then there is the 'bugbear' of hardened user copies. Chasing down the stack to find whether the kernel buffer crosses a stack frame is probably more expensive than the copy for the typically small copies that will use on-stack buffers. David > > IOW, it would look something like > > #define unsafe_copy_to_user_outlen(_dst,_src,_len,label)... > > which is exactly the same as the current unsafe_copy_to_user(), > *except* it changes "_len" as it does along. > > And then you use that for both the "real" unsafe_copy_user and for the > "small constant values" case. > > Just as an example, attached is a completely stupid rough draft of a > patch that does this for x86 and only for unsafe_copy_to_user(). > > And I made a very very hacky change to kernel/sys.c to see what the > code generation looks like. > > This is what it results in on x86 with clang (with all the magic > .section data edited out): > > ... edited out the code to generate the times > ... this is the actual user copy: > # HERE! > movabsq $81985529216486895, %rcx # imm = 0x123456789ABCDEF > cmpq %rcx, %rbx > cmovaq %rcx, %rbx > stac > movq %r13, (%rbx) # exception to .LBB45_8 > movq %r14, 8(%rbx) # exception to .LBB45_8 > movq %r15, 16(%rbx) # exception to .LBB45_8 > movq %rax, 24(%rbx) # exception to .LBB45_8 > clac > .LBB45_6: > movq jiffies(%rip), %rdi > callq jiffies_64_to_clock_t > .LBB45_7: > addq $16, %rsp > popq %rbx > popq %r12 > popq %r13 > popq %r14 > popq %r15 > retq > .LBB45_8: > clac > movq $-14, %rax > jmp .LBB45_7 > > and notice how the compiler noticed that the 'outlen' isn't actually > used, and turned the exception label into just a "return -EFAULT" and > never actually generated any code for updating remaining lengths? > > That actually looks pretty much optimal for a 32-byte user copy. > > And it didn't involve changing the semantics at all. > > Just to check, I changed that "times()" system call to return the > number of bytes uncopied instead (to emulate the "I actually want to > know what's left" case), and it generated this: > > # HERE! > movabsq $81985529216486895, %rcx # imm = 0x123456789ABCDEF > cmpq %rcx, %rbx > cmovaq %rcx, %rbx > stac > movl $32, %ecx > movq %r13, (%rbx) # exception to .LBB45_7 > movl $24, %ecx > movq %r15, 8(%rbx) # exception to .LBB45_7 > movl $16, %ecx > movq %r14, 16(%rbx) # exception to .LBB45_7 > movl $8, %ecx > movq %rax, 24(%rbx) # exception to .LBB45_7 > clac > xorl %ecx, %ecx > .LBB45_8: > movq %rcx, %rax > addq $16, %rsp > popq %rbx > popq %r12 > popq %r13 > popq %r14 > popq %r15 > retq > .LBB45_6: > movq jiffies(%rip), %rdi > jmp jiffies_64_to_clock_t # TAILCALL > .LBB45_7: > clac > jmp .LBB45_8 > > so it all seems to work - although obviously the above is *not* the normal case. > > NOTE NOTE NOTE! The attached patch is entirely untested. I obviously > did some "test code generation" with it, but I only *looked* at the > result, and maybe it has some fundamental problem that I just didn't > notice. So treat this as a "how about this approach" patch, not as > anything more serious than that. > > And the kerrnel/sys.c hack is very obviously just that: a complate > hack for testing. > > A real patch would do that "for small constant-sized copies, turn > copy_to_user() automatically into "_small_copy_to_user()". > > The attached is *not* a real patch. Treat it with the contempt it deserves. > > Linus From xen-devel-bounces@lists.xenproject.org Mon Apr 27 21:39:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 21:39:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295336.1571998 (Exim 4.92) (envelope-from ) id 1wHTg7-0006yX-PC; Mon, 27 Apr 2026 21:39:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295336.1571998; Mon, 27 Apr 2026 21:39:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHTg7-0006yQ-Mg; Mon, 27 Apr 2026 21:39:43 +0000 Received: by outflank-mailman (input) for mailman id 1295336; Mon, 27 Apr 2026 21:39:41 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHTg5-0006yK-Km for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 21:39:41 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHTg4-00FA7s-4K for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 23:39:40 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69efd71e-2eae-0a2a0a5409dd-0a2a450b933e-38 for ; Mon, 27 Apr 2026 23:39:39 +0200 Received: from [209.85.218.50] (helo=mail-ej1-f50.google.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69efd79b-212f-0a2a450b0019-d155da32adb0-3 for ; Mon, 27 Apr 2026 23:39:39 +0200 Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-bb3c4d8cc29so236178166b.1 for ; Mon, 27 Apr 2026 14:39:39 -0700 (PDT) Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com. 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Mon, 27 Apr 2026 14:39:38 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ/ziLJN+XJyMzJtU4t+0+lcJ2KyxkSExJTbykm0CWE8m0TmUdoIwwdUYext8s1hDSZ2/kEZ0nw2n9Q=@lists.xenproject.org X-Received: by 2002:a05:6402:5216:b0:679:1f4f:9d30 with SMTP id 4fb4d7f45d1cf-679bb04c1a2mr179970a12.4.1777325976937; Mon, 27 Apr 2026 14:39:36 -0700 (PDT) MIME-Version: 1.0 References: <289b424e243ba2c4139ea04009cf8b9c448a87ff.1777306795.git.chleroy@kernel.org> <20260427222914.1cb2dd3b@pumpkin> In-Reply-To: <20260427222914.1cb2dd3b@pumpkin> From: Linus Torvalds Date: Mon, 27 Apr 2026 14:39:20 -0700 X-Gmail-Original-Message-ID: X-Gm-Features: AVHnY4I-AxqvQRk42MegvhKMp_z4sSEpEzhzpgw2GyV2bV8dezSPoI0JTlwB18Y Message-ID: Subject: Re: [RFC PATCH v1 5/9] uaccess: Switch to copy_{to/from}_user_partial() when relevant To: David Laight Cc: "Christophe Leroy (CS GROUP)" , Yury Norov , Andrew Morton , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-purgate-ID: tlsNG-42698a/1777325979-7E36CF3B-AAE2FA5E/0/0 X-purgate-type: clean X-purgate-size: 484 On Mon, 27 Apr 2026 at 14:29, David Laight wrote: > > I think there is a slight difference in that the normal copy_to_user() > will determine the exact offset of the error by retrying with byte copies. I have this dim memory that we decided that you can't reply on byte exactness anyway, because not all architectures gave that guarantee for the user copies. But that thing came up many years ago, I might mis-remember. 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pr=C Message-ID: Date: Mon, 27 Apr 2026 18:00:08 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] xen/public: introduce DOMID_ANY To: Juergen Gross , CC: , Andrew Cooper , "Anthony PERARD" , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-2-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260423080840.530547-2-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|SA3PR12MB7949:EE_ X-MS-Office365-Filtering-Correlation-Id: e4e673d9-ac56-46a4-df56-08dea4a85a47 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|56012099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6qhYfyLJqKV6/ElPs6ZtHz7Xm/2UW8PToSmuV3GWJIo00VoYNZ3WT2+TBtSuMw7UusWFOAkybMpTVvNA3FUwCETWT32G+3mwSyZ0vgoS6EB3i1+uOsbvPrrD1v9KxbZUG7inLqzDhFuT+thUNtUrunzPx+gsl/MzIgD04PMNOPegM6KA84U6uo4MiU+7UwiIZWZlPmMMJc2j0PVKjuuhkgHANu60w7eeKTAZTtfCPbBM7eED5wCCAgvMKeaAYPSk48fUtioGD8B1xTaqdeAXNRvEQsoY76t96Yh9MM8SaHtJhhhfmi92HEVkiJDm+jOF4q4Lz9H02WyE9I/TVPNuG9Iq7w31EOETzSKMr6kOxhZG+dwi7WuNyGFgfMp6xbPlqM0JcVfOHr0NCt5jbbTk10PDVGlayVDPVouAYNDlxIznWH0nHhjoGOPho/ynfCz0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 22:00:10.8506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4e673d9-ac56-46a4-df56-08dea4a85a47 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7949 X-purgate-ID: tlsNG-d62444/1777327219-BEA61FF4-B9284E80/0/0 X-purgate-type: clean X-purgate-size: 1311 On 2026-04-23 04:08, Juergen Gross wrote: > Add DOMID_ANY to xen/include/public/xen.h meant to be a wildcard for > domids. > > Signed-off-by: Denis Mukhin > Signed-off-by: Juergen Gross > --- > This is based on Denis Mukhin's patch "xen/domain: introduce DOMID_ANY". > As my series is another use case for DOMID_ANY and it is a backport > candidate, I've split out the definition of DOMID_ANY from Denis' > patch in order to make progress for my series. I think we probably want Denis as the Author, since this is an unmodified piece of his patch. > --- > xen/include/public/xen.h | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h > index b12fd10e63..f35a6f21f0 100644 > --- a/xen/include/public/xen.h > +++ b/xen/include/public/xen.h > @@ -608,6 +608,13 @@ DEFINE_XEN_GUEST_HANDLE(mmuext_op_t); > /* DOMID_INVALID is used to identify pages with unknown owner. */ > #define DOMID_INVALID xen_mk_uint(0x7FF4) > > +/* > + * DOMID_ANY is used to signal no specific domain ID requested. > + * Handler should pick a valid ID, or handle it as a broadcast value Maybe s/broadcast/wildcard/? Either way: Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Mon Apr 27 22:00:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 22:00:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295350.1572017 (Exim 4.92) (envelope-from ) id 1wHU0V-0003DC-Od; Mon, 27 Apr 2026 22:00:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295350.1572017; Mon, 27 Apr 2026 22:00:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0V-0003D5-LE; Mon, 27 Apr 2026 22:00:47 +0000 Received: by outflank-mailman (input) for mailman id 1295350; Mon, 27 Apr 2026 22:00:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0U-00039Q-Mm for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 22:00:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHU0U-005yAH-3e for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Mon, 27 Apr 2026 18:00:37 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] tools/xenstored: add support for "all domains" node permission To: Juergen Gross , CC: , Anthony PERARD , "Julien Grall" References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-3-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260423080840.530547-3-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002326:EE_|DS4PR12MB9588:EE_ X-MS-Office365-Filtering-Correlation-Id: 933944a8-c0b8-4f39-3f16-08dea4a86c0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: PVENZ9JHF7a0j/FDc+51aRqQ+1v1MIe6RFMECw7BWzQT2xpBtpueYuWuWCvagHcqREOT0MHIJ7JGhOoyUKOKiml7CHhGHKrDOY7bsNYIOyGB+Pc8r/zmIYJhfzqzaQ9VeTZsMCJ3lHvvsYBk10NwhOHlL5ZycOJcn3L1UWHI+Rrx0ZULGH+FxhqiEu3/HDXCE8X+5AUi2JQAiGHCZoQs+56RcIXupZ6aGtzncUN3MEgl3+DinNP4gKWkst+QYVO/PyB3ykWabszCTkZ/uVr0CSjPzm74FOF/bdr0xX5UuczxAy4Qa+sDFSRcsUySxpi9FArtJX8T1QF/KBtgiEvh0344FJ6mhqF71JpJO+plktY+bQmlxvOECnq5xbOkTN0E4+uHU96MSEK1PTP1RiSENBnyurCMj7QHKi6RQq3Gyzvkf5DnxWshP10deE/Jgg8WBDrdoDU2tCzxRQVbsQLAq9CxCGYwfYR1hrd0tedZhg5y7LKxPiJF/tmmTvS+KLTia7xHomYXermdom4lnCZzpc2JrlY3D4nGinegK5UvOtsnfBMNXyUEuBVFHlA0aC5LZeS4lzQrsSZvxFEJHFEKjq+v9wCU59x5R6Ayj4D0F/YHdFo5KS8CG7DnFMpbr6DP25JpOwZ4mjEV4xyv18hXY8RXS6+VZyqBRocKd1NU/dapyT2pPCJPkz0PtnqtFrXy2tUddzhEGj5X5ib3HXxVgf04kL8MTEJeZA/6+X7zHImhew8TxXxEyBW3iQQISA1VVcaO/wGis661dJr89F1HhA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vJ/E3e67BORGzMxIes60C3xdqZf88N8fYj3OZoO/VM/Bs1kzzUI+eh94ze08PExLDqmDqUTncnqH2E2E90wgIka+daGhuMwHkvbRnPxGn7wVxUghxyS/lBnJrk2SmhxgvzMPrLC5bvlX4UW40n2IlQBZz0/r/h4lNlvNRibkB2LMS3Nu8zd7zr9m2kLiIioYeYZgV7EiZkhB8/iQcplFG+PDni5xahMghKuwbkDPOyADWkm9/clNy/Kw4IVjt3uQeZEewC/1muteUm21Yp+wBRuoknt2JLzK0sIH6AhgDZyQYLdqambKyUaJgsZBwYiJ++tXoUGZ8+gkLEO8JtCDHvaOVyu5k1RTn137eDSgNXYD/ygaZoXOt0orJxtcgbfBSBOwX8ZyuDmrr3tl9E8qqv0DulwN1tovz8pbagdINOUKzl9cZ3Um2/a497k0xVou X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 22:00:40.6182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 933944a8-c0b8-4f39-3f16-08dea4a86c0e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002326.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9588 X-purgate-ID: tlsNG-16d1c6/1777327245-91985D75-C5AC291C/0/0 X-purgate-type: clean X-purgate-size: 1166 On 2026-04-23 04:08, Juergen Gross wrote: > Add support for using DOMID_ANY in node permissions to indicate that > all domains are allowed to access the node. > > Add a new feature bit for indicating the support of DOMID_ANY. > > Signed-off-by: Juergen Gross > @@ -1754,8 +1755,12 @@ static bool chk_domain_generation(unsigned int domid, uint64_t gen) > * Allocate all missing struct domain referenced by a permission set. > * Any permission entries for not existing domains will be marked to be > * ignored. > + * An DOMID_ANY entry will be marked to be ignored, if the writing a/An/A/ > + * domain doesn't have the XENSTORE_SERVER_FEATURE_DOMID_ANY enabled. Note > + * that Xen tools will never set DOMID_ANY for a guest owned node. I'm not sure about stating "Xen tools will never" here since it may change in the future, and will not be updated. Maybe "Note that Xen tools don't currently set DOMID_ANY for a guest owned node, and they aren't expected in the future."? But maybe just drop it since I'm not seeing much value. Reviewed-by: Jason Andryuk Thanks, Jason From xen-devel-bounces@lists.xenproject.org Mon Apr 27 22:01:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 22:01:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295354.1572026 (Exim 4.92) (envelope-from ) id 1wHU0h-0003Xt-W8; Mon, 27 Apr 2026 22:00:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295354.1572026; Mon, 27 Apr 2026 22:00:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0h-0003Xk-Sr; Mon, 27 Apr 2026 22:00:59 +0000 Received: by outflank-mailman (input) for mailman id 1295354; Mon, 27 Apr 2026 22:00:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0g-0003Wv-EZ for xen-devel@lists.xenproject.org; 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pr=C Message-ID: Date: Mon, 27 Apr 2026 18:00:44 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] tools/xenstored: allow @releaseDomain watch for all domains To: Juergen Gross , CC: , Julien Grall , Anthony PERARD References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-4-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260423080840.530547-4-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002320:EE_|DS0PR12MB8766:EE_ X-MS-Office365-Filtering-Correlation-Id: 733dd991-4a5c-43ef-cc02-08dea4a87276 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: F4cbfXilUVYQdEV+xSYM8nZOwJ2SxQYIt8NJb698N5OKMbL3bgmMFSn50ZavYWjhbUgxxbZQA1rgkXsUYUKfIkhOSKyY8QpBwe4+fXRUbrygTR4SBB4c7qmD0epqAOdb9VbJ70yOSFUjJMSEXXH/S8JtThxlvy7v9tSfadA/oingyO8Lz+j7/U28T2MSHMxOf0IIW4h2JzKuNX0YvVBdHmstWle7/62eNkdDVMIQW9bYdITaDpjCygyIJ4dAmtqT1jL2f1Lhe/tga+dSzi20y9sdv0MHwsj3Q9F/fu2XeG6WRdqnn3KaIGFq1sog+VJZ1YuSGakw0uwzsyLu8q+vNv9bu3RxDuw+X1R3IZ+pNpZ+88ObeejrfvOnATWCbqdQiqV/4P8LT7AwKuuDoWOyR04FkbSmLuQJvHUB7qFf2//+TIbXO2oHWHB6ejR7Ji87 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 22:00:51.4211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 733dd991-4a5c-43ef-cc02-08dea4a87276 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8766 X-purgate-ID: tlsNG-c1860d/1777327257-C1161DB1-564C5364/0/0 X-purgate-type: clean X-purgate-size: 454 On 2026-04-23 04:08, Juergen Gross wrote: > Currently the @releaseDomain watch is allowed for dom0 only. This is > problematic for guests which want to give other domains access to > Xenstore entries, as they have no simple way to tell when such a > domain is stopped. > > Allow @releaseDomain to be usable by all domains as the default. > > Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Mon Apr 27 22:01:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 22:01:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295356.1572034 (Exim 4.92) (envelope-from ) id 1wHU0n-0003p8-76; Mon, 27 Apr 2026 22:01:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295356.1572034; Mon, 27 Apr 2026 22:01:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0n-0003p1-4H; Mon, 27 Apr 2026 22:01:05 +0000 Received: by outflank-mailman (input) for mailman id 1295356; Mon, 27 Apr 2026 22:01:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHU0l-0003o1-OM for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 22:01:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHU0j-00EGTi-Ja for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 00:01:03 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69efdc95-5cb7-0a2a0a5109dd-0a2a4504d5aa-18 for ; Tue, 28 Apr 2026 00:01:03 +0200 Received: from [209.85.218.52] (helo=mail-ej1-f52.google.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69efdbea-1dec-0a2a45040019-d155da34c8a0-3 for ; Mon, 27 Apr 2026 23:58:02 +0200 Received: by mail-ej1-f52.google.com with SMTP id a640c23a62f3a-ba7a1cc0380so1770652066b.2 for ; Mon, 27 Apr 2026 14:58:02 -0700 (PDT) Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com. 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Mon, 27 Apr 2026 14:58:01 -0700 (PDT) X-Forwarded-Encrypted: i=1; AFNElJ+Tvq2sxnlgoDfMFkefIWXA3V0QyYTpuG6hxj5AaFAaoc34Tf/CS+F7UJeZlVF3PR92w5i/6mF0z/c=@lists.xenproject.org X-Received: by 2002:a05:6402:35c2:b0:677:270f:6f4b with SMTP id 4fb4d7f45d1cf-679bb04a8a7mr185115a12.1.1777326742385; Mon, 27 Apr 2026 14:52:22 -0700 (PDT) MIME-Version: 1.0 References: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> <63a4d0f6-0eb3-48cd-9f98-bf7b223b2606@kernel.org> In-Reply-To: From: Linus Torvalds Date: Mon, 27 Apr 2026 14:52:05 -0700 X-Gmail-Original-Message-ID: X-Gm-Features: AVHnY4LQUFWo9ODz4M3q2vZC9Gn8nsdYr95Nd4ky5ERVHHxIyN_9ZXY5zjebfdc Message-ID: Subject: Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() To: Yury Norov Cc: "Christophe Leroy (CS GROUP)" , Andrew Morton , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-purgate-ID: tlsNG-ebf023/1777327082-2B7693FF-D1506192/13/0 X-purgate-type: clean X-purgate-size: 759 On Mon, 27 Apr 2026 at 12:19, Yury Norov wrote: > > This is what Linus said when added x86 implementation for copy_from_user() > in c512c69187197: Note that some things have happily changed in the six+ years since... > That's partly because we have no current users of it, but also partly > because the copy_from_user() case is slightly different and cannot > efficiently be implemented in terms of a unsafe_get_user() loop (because > gcc can't do asm goto with outputs). now everybody can do asm goto with outputs. Yes, it's disabled on older versions, so it's not *always* available, but all modern versions do it. And if you care about performance, you won't be using an old compiler. Linus From xen-devel-bounces@lists.xenproject.org Mon Apr 27 22:15:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 22:15:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295377.1572044 (Exim 4.92) (envelope-from ) id 1wHUEG-0006Vs-FV; Mon, 27 Apr 2026 22:15:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295377.1572044; Mon, 27 Apr 2026 22:15:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHUEG-0006Vl-Cd; Mon, 27 Apr 2026 22:15:00 +0000 Received: by outflank-mailman (input) for mailman id 1295377; Mon, 27 Apr 2026 22:15:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHUEF-0006Vf-T8 for xen-devel@lists.xenproject.org; Mon, 27 Apr 2026 22:15:00 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHUEE-00Gz9h-SF for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <9624178e-7596-4395-adca-7cedc58aafb9@amd.com> Date: Mon, 27 Apr 2026 18:14:45 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] tools/xenstored: remove permissions related to dead domain To: Juergen Gross , CC: , Julien Grall , Anthony PERARD References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-5-jgross@suse.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20260423080840.530547-5-jgross@suse.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|DS0PR12MB8442:EE_ X-MS-Office365-Filtering-Correlation-Id: 53a1d0c5-1e52-4117-a059-08dea4aa660f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ir3z/IKUxaaxxgf5l8uBQeKuLyEGqt/bXH2dRT+xEoO7vRN+Fjcmr8eY7R4Cjvi3ITsuHwZTnwBMAsc82S0thFequFgC5YlgLzswGe61sBmlWQRWyN6U1svSWHYproI83I7WtZEDK0iIeB0rwdMm4g0PrWuLU1ZWix1luevt7HXNvRE3/usHfAWQRu/uHPQ3arCOkYPjMsJOnaMbGJ5ZH+gS1F16S+oJMkcx2DOiy4+KBh8fIBvQE4QvMO5O234HZ2e7t4NNV6G3wIJ4fedWgwDDNFzFOYzKYE56MHYwuENk2dYjokofjKpdwcKIm3lhKtC5brqdV+vbepPt8vik2vA7l0VmJF2cB6jGXpt0BsDze/HjBga+381MSlugcVpHNktkLR/mdSeC9YQPy73p41CvdMhI1DE65fkS1PmFM4QWefJXTc2GmVkYmXTE5Pz4 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Apr 2026 22:14:49.6228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53a1d0c5-1e52-4117-a059-08dea4aa660f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8442 X-purgate-ID: tlsNG-33051d/1777328098-A2378938-D5F372B5/0/0 X-purgate-type: clean X-purgate-size: 908 On 2026-04-23 04:08, Juergen Gross wrote: > Wit unprivileged domains now capable to use the @releaseDomain watch, s/Wit/With/ > there is no reason not to remove any node permissions which relate to > a domain which has been removed. > > This resolves a complex scenario where a new domain could inherit the > permissions of an old one with the same domid. > > Signed-off-by: Juergen Gross > > - return domain->acc_val[ACC_NODES] ? ret : WALK_TREE_SUCCESS_STOP; > + if (node->perms[0].id == domain->domid) { > + domain_nbentry_dec(NULL, domain->domid); > + node->perms[0].id = priv_domid; > + node->acc.memory = 0; > + domain_nbentry_inc(NULL, priv_domid); > + trace("moving orphaned node %s to dom0\n", node->name); Since you are touching this, maybe s/dom0/dom%u/ and priv_domid? Reviewed-by: Jason Andryuk Thanks, Jason From xen-devel-bounces@lists.xenproject.org Mon Apr 27 22:30:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 27 Apr 2026 22:30:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295386.1572053 (Exim 4.92) (envelope-from ) id 1wHUTI-0001dM-Qu; Mon, 27 Apr 2026 22:30:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295386.1572053; Mon, 27 Apr 2026 22:30:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHUTI-0001dF-M8; Mon, 27 Apr 2026 22:30:32 +0000 Received: by outflank-mailman (input) for mailman id 1295386; Mon, 27 Apr 2026 22:30:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHUTH-0001d9-1y for xen-devel@lists.xenproject.org; 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Date: Mon, 27 Apr 2026 18:30:16 -0400 From: Yury Norov To: Linus Torvalds Cc: "Christophe Leroy (CS GROUP)" , Andrew Morton , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() Message-ID: References: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> <63a4d0f6-0eb3-48cd-9f98-bf7b223b2606@kernel.org> Content-Type: text/plain; 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And if you care about performance, you > won't be using an old compiler. The minimal GCC version is 8.1, and asm goto with outputs is supported since GCC-11. That would brake the build, if we just switch to using it without "CC_IS_GCC && (GCC_VERSION >= 110100)" guard. Is it worth to maintain 2 version of the function? I don't know... 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This is planned but > implies modifications in the hypervisor and the firmwares, mainly for the > support of multiple PCI buses. Why do you need multi bus support to expose PCIe capabilities? I'm not seeing the relation between those two. You could still expose a single bus on the MCFG table. > In order to create a Q35 guest, a new domain config option has been added, > named 'device_model_machine'. Possible values are: > - "i440" - i440 emulation (default) > - "q35" - emulate a Q35 machine > > If the option is omitted it defaults to "i440", not impacting existing domain > configuration files. > > DSDT files for Q35 and i440 are largely similar so the existing file dsdt.asl > has been split with i440 and q35 specific parts put in seperated files. > > The PCIe MMCONFIG area is configured by hvmloader and its base address and size > are set in Xen using a new pair of hypercalls HVMOP_get|set_ecam_space. I guess I will see how that looks like in the series, but the setting of the ECAM region would better be done by the toolstack. Setting it in hvmloader is possibly not the best placement, because it doesn't run for PVH guests (and we will want ECAM support for PVH at some point), and there's also a vague plan/intention to get rid of hvmloader even for HVM guests eventually. > Access > to the MMCONFIG area from a guest is trapped by Xen and transfered to the > emulator as XEN_DMOP_IO_RANGE_PCI ioreq type. Thanks for doing this bit, IIRC from when this was last posted this was the biggest shortcoming of the series when originally submitted. Thanks, Roger. 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pr=C From: Michal Orzel To: CC: Michal Orzel , Nicola Vetrini , Doug Goldstein , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Luca Fancellu Subject: [PATCH v2] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info Date: Tue, 28 Apr 2026 10:02:18 +0200 Message-ID: <20260428080218.19371-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CB:EE_|IA1PR12MB6649:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c31b70e-15a4-47c1-b5af-08dea4fc7d96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|56012099003|18002099003|13003099007; X-Microsoft-Antispam-Message-Info: g9NMIZZEWmc32O0VujoxJOqMVJDClbwQcyiOxTKnoOqtRQgNJGOU77VEQk7NTmIDiGFxTiV5CVVJ5bNWQ1JlRx7hGvNGT83zMNTs47M7MU/TPh3d+e/XVK6ZfTW69rDHCw3e0DLLnoJ3gFe3uA1aFxK/6hs7jT6YfvatFnQH/2lndQnlJsjijzKnX3gRALEh2IMgkTkLs5cY3S8xQQd9SHhKYyHir1WbqBZLLFRoJPLjnJU3VWBqPYm+7lVPH6W4uWnkQ7GazVy4oNfOtfey3+ZTyuSJZhvJ3DDBMHEW66Nylwoe9YEOwnhPPl3UkyDJtJzEtQfpJdrdUGOqomNKJ+8s9Ye1DD9f0FAgr3g2+wGDGVUZ360npco0Wqj+LDfR2Bis2uNuEzEZY0UByJE9u1YKtu89/h86sC69Tg+bbBtqb7YjAiCprO6ovYPp/UI46f17mwnVOH+aAJvCqulAgBOqqQ0LgOWrAWEfGhaI4zlkHgq1gatoPZG3oWqVPWHOswqzezsR4A6K/bY+d3LrxGA/NXk6zWdZVF6g/SAAbcbc9oEoU6lmeLdH/IPUqvNBbT8DuGJgMkJ4oejBHgOxAf4pMoo3E4XyyAdlO9e/1kcLA/qNJnnL9Ig2BsXwTWKWqB49Jke2F5smK5UkBoREdxdAjBk0xFxzxn+740WyoxpgaA0lgzH1eZPaJMkSD80eqxP+ytpf+g9XN9ahNIQIDRPBEARLbDgpmzcP30H/0Pv3cYBxEmcgTrPW0TdNIqS8nW1DjqtzOCS5sN9XkSjt1A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(56012099003)(18002099003)(13003099007);DIR:OUT;SFP:1101; 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This fails for overlays using phandle-based targeting (target = <&label>) because DTC compiles these as unresolved fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to manually modify the dtbo (even for hwdom) to switch from target to target-phandle by manually inspecting also the host DTB. Introduce overlay_get_target_path() which directly handles the two targeting cases that occur before fixup resolution: - target-path: the string property is returned directly. - target = <&label>: the label is found in the overlay's __fixups__ node, then resolved to a path via the base DTB's __symbols__ node. Libfdt fdt_for_each_property_offset() violates MISRA R20.7. Despite libfdt being excluded from the analysis, this causes ECLAIR scan to report a regression because the violation introduced by a macro is reported at the call site. Deviate R20.7 for libfdt.h. Reviewed-by: Luca Fancellu Acked-by: Stefano Stabellini Signed-off-by: Michal Orzel --- In my pre-push testing I realized ECLAIR allcode reported a violation related to the use of fdt_for_each_property_offset. Libfdt is excluded from analysis but this does not apply to e.g. macros used in other places. Changes in v2: - strip out from series that is ready to be committed - deviate 20.7 for libfdt.h. Discussed with Nicole. https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2484326830 --- .../eclair_analysis/ECLAIR/deviations.ecl | 1 + xen/common/device-tree/dt-overlay.c | 65 +++++++++++++++++-- 2 files changed, 60 insertions(+), 6 deletions(-) diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl index 30c323906924..5f0b73062474 100644 --- a/automation/eclair_analysis/ECLAIR/deviations.ecl +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl @@ -631,6 +631,7 @@ not in scope for compliance are allowed, as that is imported code." -file_tag+={acpi_cpu_idle, "^xen/arch/x86/acpi/cpu_idle\\.c$"} -config=MC3A2.R20.7,reports+={safe, "any_area(any_loc(file(gnu_efi_include)||any_exp(macro(^NextMemoryDescriptor$))))"} -config=MC3A2.R20.7,reports+={safe, "any_area(any_loc(file(acpi_cpu_idle)))"} +-config=MC3A2.R20.7,reports+={safe, "any_area(any_loc(any_exp(file(^xen/include/xen/libfdt/libfdt.h$))))"} -doc_end -doc_begin="To avoid compromising readability, the macros alternative_(v)?call[0-9] are allowed diff --git a/xen/common/device-tree/dt-overlay.c b/xen/common/device-tree/dt-overlay.c index f203e189f5ff..fd171333c6d7 100644 --- a/xen/common/device-tree/dt-overlay.c +++ b/xen/common/device-tree/dt-overlay.c @@ -286,6 +286,63 @@ static unsigned int overlay_node_count(const void *overlay_fdt) return num_overlay_nodes; } +/* + * Resolve the target path for an overlay fragment. + * + * This is called before fdt_overlay_apply(), so phandle-based targets + * (target = <&label>) are still unresolved (compiled as 0xffffffff by DTC). + * Handle the two cases that actually occur: + * - target-path property: the path string is used directly, + * - target = <&label>: the label is looked up in the overlay's __fixups__ + * node, then resolved to a path via the base DTB's __symbols__ node. + * + * Returns a pointer into the FDT on success, NULL on failure. + */ +static const char *overlay_get_target_path(const void *fdt, const void *fdto, + int fragment) +{ + const char *path, *fragment_name; + int fixups_off, symbols_off, property; + int fragment_name_len; + + /* Try target-path first (string-based targeting) */ + path = fdt_getprop(fdto, fragment, "target-path", NULL); + if ( path ) + return path; + + /* Phandle-based target: resolve via __fixups__ and __symbols__ */ + fixups_off = fdt_path_offset(fdto, "/__fixups__"); + if ( fixups_off < 0 ) + return NULL; + + symbols_off = fdt_path_offset(fdt, "/__symbols__"); + if ( symbols_off < 0 ) + return NULL; + + fragment_name = fdt_get_name(fdto, fragment, &fragment_name_len); + if ( !fragment_name ) + return NULL; + + fdt_for_each_property_offset(property, fdto, fixups_off) + { + const char *val, *label, *p; + int val_len; + + val = fdt_getprop_by_offset(fdto, property, &label, &val_len); + if ( !val || !val_len || (val[val_len - 1] != '\0') ) + continue; + + /* Match entries of the form "/:target:0" */ + for ( p = val; p < (val + val_len); p += (strlen(p) + 1) ) + if ( p[0] == '/' && + !strncmp(p + 1, fragment_name, fragment_name_len) && + !strcmp(p + 1 + fragment_name_len, ":target:0") ) + return fdt_getprop(fdt, symbols_off, label, NULL); + } + + return NULL; +} + /* * overlay_get_nodes_info gets full name with path for all the nodes which * are in one level of __overlay__ tag. This is useful when checking node for @@ -298,7 +355,6 @@ static int overlay_get_nodes_info(const void *fdto, char **nodes_full_path) fdt_for_each_subnode(fragment, fdto, 0) { - int target; int overlay; int subnode; const char *target_path; @@ -307,11 +363,8 @@ static int overlay_get_nodes_info(const void *fdto, char **nodes_full_path) if ( overlay < 0 ) continue; - target = fdt_overlay_target_offset(device_tree_flattened, fdto, - fragment, &target_path); - if ( target < 0 ) - return target; - + target_path = overlay_get_target_path(device_tree_flattened, fdto, + fragment); if ( target_path == NULL ) return -EINVAL; -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 08:06:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 08:06:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295440.1572080 (Exim 4.92) (envelope-from ) id 1wHdT0-0004ON-Bp; Tue, 28 Apr 2026 08:06:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295440.1572080; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lXbVpWpgWQWfh0Jt7Fg4SmY+s+w//FrtSSaWOAN+zGudCQl/dXrKjwcIW4q2VXHNQn5osNFH2kOu8FT2G9jiWHLqmVpfg00SvesI/Un7J/7mmB71rFgAOkA5PNBq4yIEIaiyiLByzfZKcytlHX3j31+q1zq7cqJC83fVBncwyA7mZ/0waiPFbgi2EaUx1WTzp8+Va4O84N0sAtGn9GnRL57M1lzzQb4YdK+4EwUeV8yjzmJ13tqHlNbpZNlSCEKTzCcMXGkiSRGYubaK+c/9K85Q7cX0qV8bkViXu3WiloSASFemo2bDHHhH6BLQU1zqwJEWRbTDJQ0/NvciyNI7nBCIi0AK0cNRkGd5B8z46Jpv2ubOc2Cvvu+EMG1ElydAj6f9j4vUgA3qWpAb7tg4HHxbd2FnE0PGOIQr+uFldtgBzMwT7IwpdUMMhWp63swQ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 08:10:16.4373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 765c2d5b-6ee6-4a71-a3ed-08dea4fd94e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D5.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7623 X-purgate-ID: tlsNG-ebf023/1777363821-3184D3FF-3BCDF3A3/0/0 X-purgate-type: clean X-purgate-size: 1580 On 28-Apr-26 10:05, Luca Fancellu wrote: > > >> On 28 Apr 2026, at 09:02, Michal Orzel wrote: >> >> overlay_get_nodes_info() is called before fdt_overlay_apply() to extract >> target paths from the overlay. This fails for overlays using phandle-based >> targeting (target = <&label>) because DTC compiles these as unresolved >> fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to >> return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to >> manually modify the dtbo (even for hwdom) to switch from target to >> target-phandle by manually inspecting also the host DTB. >> >> Introduce overlay_get_target_path() which directly handles the two >> targeting cases that occur before fixup resolution: >> - target-path: the string property is returned directly. >> - target = <&label>: the label is found in the overlay's __fixups__ >> node, then resolved to a path via the base DTB's __symbols__ node. >> >> Libfdt fdt_for_each_property_offset() violates MISRA R20.7. Despite >> libfdt being excluded from the analysis, this causes ECLAIR scan to >> report a regression because the violation introduced by a macro is >> reported at the call site. Deviate R20.7 for libfdt.h. >> >> Reviewed-by: Luca Fancellu >> Acked-by: Stefano Stabellini >> Signed-off-by: Michal Orzel > > NIT: shouldn’t these be in chronological order? Yes, they should. It's b4 that messes things up. Anyway, to be done on commit. ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 28 08:14:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 08:14:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295459.1572099 (Exim 4.92) (envelope-from ) id 1wHda6-0006lC-ES; Tue, 28 Apr 2026 08:14:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295459.1572099; Tue, 28 Apr 2026 08:14:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHda6-0006l5-AF; Tue, 28 Apr 2026 08:14:10 +0000 Received: by outflank-mailman (input) for mailman id 1295459; Tue, 28 Apr 2026 08:14:09 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHda4-0006kz-QJ for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 08:14:09 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHda3-00BEh9-PA for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 10:14:07 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f06c4d-5cb7-0a2a0a5109dd-0a2a450a8020-12 for ; Tue, 28 Apr 2026 10:14:07 +0200 Received: from [170.10.133.124] (helo=us-smtp-delivery-124.mimecast.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f06c4e-56b3-0a2a450a0019-aa0a857c6839-3 for ; Tue, 28 Apr 2026 10:14:07 +0200 Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-638-8LCRAHWHN-681PVBa1sDpg-1; Tue, 28 Apr 2026 04:14:02 -0400 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id CE3EC1800451; Tue, 28 Apr 2026 08:13:57 +0000 (UTC) Received: from localhost (unknown [10.44.24.6]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 13AC8195608E; Tue, 28 Apr 2026 08:13:53 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mimecast20190719 header.d=redhat.com header.i="@redhat.com" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777364046; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Qd0r1ayC5mBpEHAxJW+wuu997v0hBPTSLNCW1+ff5s=; b=BdlgkJdreuBusFwI0uNbIfkYpaofjAhJkT8UJSNIt60tcGsBRm1Ql171+qwfuS30wbWwJ4 VXLs+biMJ9LQtQD2fRzbeyRQtFsqaajimkwtMpiyd8QfpFui0HOlsC1BfyIPFd1jJUnvc3 hyfErmPMwYsex/0uwrrsrU0PNIImBLE= X-MC-Unique: 8LCRAHWHN-681PVBa1sDpg-1 X-Mimecast-MFC-AGG-ID: 8LCRAHWHN-681PVBa1sDpg_1777364039 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Jan Kiszka , Phil Dennis-Jordan , Richard Henderson , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Mark Cave-Ayland , Samuel Tardieu , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Rikalo , Laurent Vivier , Thomas Huth , BALATON Zoltan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Akihiko Odaki , Dmitry Osipenko , "Michael S. Tsirkin" , Dmitry Fleytman , Stefano Stabellini , Anthony PERARD , "Edgar E. Iglesias" , Alistair Francis , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org (open list:Musicpal), qemu-ppc@nongnu.org (open list:sam460ex), xen-devel@lists.xenproject.org (open list:X86 Xen CPUs) Subject: [PULL 08/15] ui/console: return completion status from gfx_update callback Date: Tue, 28 Apr 2026 12:12:55 +0400 Message-ID: <20260428081303.990973-9-marcandre.lureau@redhat.com> In-Reply-To: <20260428081303.990973-1-marcandre.lureau@redhat.com> References: <20260428081303.990973-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mimecast-MFC-PROC-ID: PJGKQvBRH2XtP3Fvu266gg-QdLECtRhDLd-itFr5gmo_1777364039 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1777364047-81D808B7-2B14CF27/0/0 X-purgate-type: clean X-purgate-size: 32862 From: Marc-André Lureau Replace the two-field design (gfx_update void callback + gfx_update_async flag) with a single bool return value from gfx_update. Returning true means the update completed synchronously and graphic_hw_update_done() should be called by the console layer. Returning false means the update is deferred and the device will call graphic_hw_update_done() itself later (as done by QXL/SPICE and Apple GFX). This simplifies the interface and makes the async contract explicit at each call site rather than relying on a separate struct field. Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé --- hw/display/qxl.h | 2 +- include/ui/console.h | 11 ++++++++--- hw/arm/musicpal.c | 3 ++- hw/display/artist.c | 4 +++- hw/display/bcm2835_fb.c | 7 ++++--- hw/display/bochs-display.c | 6 ++++-- hw/display/cg3.c | 5 +++-- hw/display/dm163.c | 4 +++- hw/display/exynos4210_fimd.c | 6 ++++-- hw/display/g364fb.c | 9 ++++++--- hw/display/jazz_led.c | 6 ++++-- hw/display/macfb.c | 6 ++++-- hw/display/next-fb.c | 4 +++- hw/display/omap_lcdc.c | 14 ++++++++------ hw/display/pl110.c | 5 +++-- hw/display/qxl-render.c | 6 +++--- hw/display/qxl.c | 7 +++---- hw/display/ramfb-standalone.c | 4 +++- hw/display/sm501.c | 8 +++++--- hw/display/ssd0303.c | 10 ++++++---- hw/display/ssd0323.c | 11 ++++++----- hw/display/tcx.c | 6 ++++-- hw/display/vga.c | 4 +++- hw/display/virtio-gpu-base.c | 3 ++- hw/display/virtio-vga.c | 6 +++--- hw/display/vmware_vga.c | 7 ++++--- hw/display/xenfb.c | 6 ++++-- hw/display/xlnx_dp.c | 10 ++++++---- hw/vfio/display.c | 17 ++++++++++------- ui/console.c | 7 +------ hw/display/apple-gfx.m | 10 +++++----- 31 files changed, 128 insertions(+), 86 deletions(-) diff --git a/hw/display/qxl.h b/hw/display/qxl.h index e0a85a5ca49..ad8a9128785 100644 --- a/hw/display/qxl.h +++ b/hw/display/qxl.h @@ -187,7 +187,7 @@ int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext); /* qxl-render.c */ void qxl_render_resize(PCIQXLDevice *qxl); -void qxl_render_update(PCIQXLDevice *qxl); +bool qxl_render_update(PCIQXLDevice *qxl); int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext); void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie); void qxl_render_update_area_bh(void *opaque); diff --git a/include/ui/console.h b/include/ui/console.h index f04844263b9..0bc9e544fad 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -368,9 +368,14 @@ enum { typedef struct GraphicHwOps { int (*get_flags)(void *opaque); /* optional, default 0 */ void (*invalidate)(void *opaque); - void (*gfx_update)(void *opaque); - bool gfx_update_async; /* if true, calls graphic_hw_update_done() */ - void (*text_update)(void *opaque, console_ch_t *text); + /* + * Returns true if the update is handled synchronously, false if deferred + * and graphic_hw_update_done() will be called when ready (to resume waiting + * tasks/coroutines). + * Optional. + */ + bool (*gfx_update)(void *opaque); + void (*text_update)(void *opaque, uint32_t *text); void (*ui_info)(void *opaque, uint32_t head, QemuUIInfo *info); void (*gl_block)(void *opaque, bool block); } GraphicHwOps; diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 441a11100a3..ba88ed756e2 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -152,7 +152,7 @@ static inline void set_lcd_pixel32(musicpal_lcd_state *s, } } -static void lcd_refresh(void *opaque) +static bool lcd_refresh(void *opaque) { musicpal_lcd_state *s = opaque; int x, y, col; @@ -171,6 +171,7 @@ static void lcd_refresh(void *opaque) } dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); + return true; } static void lcd_invalidate(void *opaque) diff --git a/hw/display/artist.c b/hw/display/artist.c index 206f77afba1..a07508378c7 100644 --- a/hw/display/artist.c +++ b/hw/display/artist.c @@ -1311,7 +1311,7 @@ static void artist_draw_line(void *opaque, uint8_t *d, const uint8_t *src, } } -static void artist_update_display(void *opaque) +static bool artist_update_display(void *opaque) { ARTISTState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1326,6 +1326,8 @@ static void artist_update_display(void *opaque) if (first >= 0) { dpy_gfx_update(s->con, 0, first, s->width, last - first + 1); } + + return true; } static void artist_invalidate(void *opaque) diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index 75d7c0f8499..83c4c03c7ca 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -150,7 +150,7 @@ static bool fb_use_offsets(BCM2835FBConfig *config) config->yres_virtual > config->yres; } -static void fb_update_display(void *opaque) +static bool fb_update_display(void *opaque) { BCM2835FBState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -161,7 +161,7 @@ static void fb_update_display(void *opaque) uint32_t xoff = 0, yoff = 0; if (s->lock || !s->config.xres) { - return; + return true; } src_width = bcm2835_fb_get_pitch(&s->config); @@ -174,7 +174,7 @@ static void fb_update_display(void *opaque) switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 8: break; case 15: @@ -212,6 +212,7 @@ static void fb_update_display(void *opaque) } s->invalidate = false; + return true; } void bcm2835_fb_validate_config(BCM2835FBConfig *config) diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 5fb6b733cb5..8ef9b76cf85 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -198,7 +198,7 @@ static int bochs_display_get_mode(BochsDisplayState *s, return 0; } -static void bochs_display_update(void *opaque) +static bool bochs_display_update(void *opaque) { BochsDisplayState *s = opaque; DirtyBitmapSnapshot *snap = NULL; @@ -212,7 +212,7 @@ static void bochs_display_update(void *opaque) ret = bochs_display_get_mode(s, &mode); if (ret < 0) { /* no (valid) video mode */ - return; + return true; } if (memcmp(&s->mode, &mode, sizeof(mode)) != 0) { @@ -255,6 +255,8 @@ static void bochs_display_update(void *opaque) g_free(snap); } + + return true; } static const GraphicHwOps bochs_display_gfx_ops = { diff --git a/hw/display/cg3.c b/hw/display/cg3.c index 0a413fbb7ec..963bb3427a6 100644 --- a/hw/display/cg3.c +++ b/hw/display/cg3.c @@ -85,7 +85,7 @@ struct CG3State { uint8_t dac_index, dac_state; }; -static void cg3_update_display(void *opaque) +static bool cg3_update_display(void *opaque) { CG3State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -98,7 +98,7 @@ static void cg3_update_display(void *opaque) DirtyBitmapSnapshot *snap = NULL; if (surface_bits_per_pixel(surface) != 32) { - return; + return true; } width = s->width; height = s->height; @@ -154,6 +154,7 @@ static void cg3_update_display(void *opaque) qemu_irq_raise(s->irq); } g_free(snap); + return true; } static void cg3_invalidate_display(void *opaque) diff --git a/hw/display/dm163.c b/hw/display/dm163.c index 4feae912945..9ea62cb4f76 100644 --- a/hw/display/dm163.c +++ b/hw/display/dm163.c @@ -285,7 +285,7 @@ static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest, return dest; } -static void dm163_update_display(void *opaque) +static bool dm163_update_display(void *opaque) { DM163State *s = (DM163State *)opaque; DisplaySurface *surface = qemu_console_surface(s->console); @@ -300,6 +300,8 @@ static void dm163_update_display(void *opaque) } dest = update_display_of_row(s, dest, row); } + + return true; } static const GraphicHwOps dm163_ops = { diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 2d8fa7ee944..a91f04aaf79 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1270,7 +1270,7 @@ static void exynos4210_update_resolution(Exynos4210fimdState *s) } } -static void exynos4210_fimd_update(void *opaque) +static bool exynos4210_fimd_update(void *opaque) { Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; DisplaySurface *surface; @@ -1287,7 +1287,7 @@ static void exynos4210_fimd_update(void *opaque) if (!s || !s->console || !s->enabled || surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { - return; + return true; } global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; @@ -1348,6 +1348,8 @@ static void exynos4210_fimd_update(void *opaque) exynos4210_fimd_enable(s, false); } exynos4210_fimd_update_irq(s); + + return true; } static void exynos4210_fimd_reset(DeviceState *d) diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 50952e9934b..bd15f6f0acc 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -238,15 +238,16 @@ static void g364fb_draw_blank(G364State *s) s->blanked = 1; } -static void g364fb_update_display(void *opaque) +static bool g364fb_update_display(void *opaque) { G364State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); qemu_flush_coalesced_mmio_buffer(); - if (s->width == 0 || s->height == 0) - return; + if (s->width == 0 || s->height == 0) { + return true; + } if (s->width != surface_width(surface) || s->height != surface_height(surface)) { @@ -262,6 +263,8 @@ static void g364fb_update_display(void *opaque) } qemu_irq_raise(s->irq); + + return true; } static inline void g364fb_invalidate_display(void *opaque) diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c index 9d62e51bed9..7d1a020d4d9 100644 --- a/hw/display/jazz_led.c +++ b/hw/display/jazz_led.c @@ -144,7 +144,7 @@ static void draw_vertical_line(DisplaySurface *ds, } } -static void jazz_led_update_display(void *opaque) +static bool jazz_led_update_display(void *opaque) { LedState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -186,7 +186,7 @@ static void jazz_led_update_display(void *opaque) color_led = rgb_to_pixel32(0x00, 0xff, 0x00); break; default: - return; + return true; } /* display segments */ @@ -218,6 +218,8 @@ static void jazz_led_update_display(void *opaque) s->state = REDRAW_NONE; dpy_gfx_update_full(s->con); + + return true; } static void jazz_led_invalidate_display(void *opaque) diff --git a/hw/display/macfb.c b/hw/display/macfb.c index b8115c2be13..848c3c282bd 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -454,7 +454,7 @@ static gchar *macfb_mode_list(void) } -static void macfb_update_display(void *opaque) +static bool macfb_update_display(void *opaque) { MacfbState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -462,7 +462,7 @@ static void macfb_update_display(void *opaque) qemu_flush_coalesced_mmio_buffer(); if (s->width == 0 || s->height == 0) { - return; + return true; } if (s->width != surface_width(surface) || @@ -471,6 +471,8 @@ static void macfb_update_display(void *opaque) } macfb_draw_graphic(s); + + return true; } static void macfb_update_irq(MacfbState *s) diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c index 3d97702fce5..e758b223ef7 100644 --- a/hw/display/next-fb.c +++ b/hw/display/next-fb.c @@ -67,7 +67,7 @@ static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s, } } -static void nextfb_update(void *opaque) +static bool nextfb_update(void *opaque) { NeXTFbState *s = NEXTFB(opaque); int dest_width = 4; @@ -90,6 +90,8 @@ static void nextfb_update(void *opaque) s, &first, &last); dpy_gfx_update(s->con, 0, 0, s->cols, s->rows); + + return true; } static void nextfb_invalidate(void *opaque) diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index c41c65bb2e0..1e8385ebffb 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -197,7 +197,7 @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, } while (-- width != 0); } -static void omap_update_display(void *opaque) +static bool omap_update_display(void *opaque) { struct omap_lcd_panel_s *omap_lcd = opaque; DisplaySurface *surface; @@ -207,12 +207,12 @@ static void omap_update_display(void *opaque) hwaddr frame_base; if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { - return; + return true; } surface = qemu_console_surface(omap_lcd->con); if (!surface_bits_per_pixel(surface)) { - return; + return true; } frame_offset = 0; @@ -256,7 +256,7 @@ static void omap_update_display(void *opaque) default: /* Unsupported at the moment. */ - return; + return true; } /* Resolution */ @@ -278,7 +278,7 @@ static void omap_update_display(void *opaque) omap_lcd->sync_error = 1; omap_lcd_interrupts(omap_lcd); omap_lcd->enable = 0; - return; + return true; } /* Content */ @@ -291,7 +291,7 @@ static void omap_update_display(void *opaque) omap_lcd->dma->current_frame ^= 1; if (!surface_bits_per_pixel(surface)) { - return; + return true; } first = 0; @@ -323,6 +323,8 @@ static void omap_update_display(void *opaque) dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1); } omap_lcd->invalidate = 0; + + return true; } static void omap_invalidate_display(void *opaque) { diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 4cd62a98757..e134ac28eb6 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -210,7 +210,7 @@ static int pl110_enabled(PL110State *s) return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); } -static void pl110_update_display(void *opaque) +static bool pl110_update_display(void *opaque) { PL110State *s = (PL110State *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -221,7 +221,7 @@ static void pl110_update_display(void *opaque) int last; if (!pl110_enabled(s)) { - return; + return true; } if (s->cr & PL110_CR_BGR) @@ -306,6 +306,7 @@ static void pl110_update_display(void *opaque) dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); } s->invalidate = 0; + return true; } static void pl110_invalidate_display(void * opaque) diff --git a/hw/display/qxl-render.c b/hw/display/qxl-render.c index c6a9ac1da10..5b4f8842011 100644 --- a/hw/display/qxl-render.c +++ b/hw/display/qxl-render.c @@ -173,7 +173,7 @@ end: * callbacks are called by spice_server thread, deferring to bh called from the * io thread. */ -void qxl_render_update(PCIQXLDevice *qxl) +bool qxl_render_update(PCIQXLDevice *qxl) { QXLCookie *cookie; @@ -183,8 +183,7 @@ void qxl_render_update(PCIQXLDevice *qxl) qxl->mode == QXL_MODE_UNDEFINED) { qxl_render_update_area_unlocked(qxl); qemu_mutex_unlock(&qxl->ssd.lock); - graphic_hw_update_done(qxl->ssd.dcl.con); - return; + return true; } qxl->guest_primary.commands = 0; @@ -195,6 +194,7 @@ void qxl_render_update(PCIQXLDevice *qxl) qxl_set_rect_to_surface(qxl, &cookie->u.render.area); qxl_spice_update_area(qxl, 0, &cookie->u.render.area, NULL, 0, 1 /* clear_dirty_region */, QXL_ASYNC, cookie); + return false; } void qxl_render_update_area_bh(void *opaque) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index f8fd7ee0698..0a3c42c8ec2 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -122,7 +122,7 @@ static void qxl_reset_memslots(PCIQXLDevice *d); static void qxl_reset_surfaces(PCIQXLDevice *d); static void qxl_ring_set_dirty(PCIQXLDevice *qxl); -static void qxl_hw_update(void *opaque); +static bool qxl_hw_update(void *opaque); void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) { @@ -1144,7 +1144,6 @@ static const QXLInterface qxl_interface = { static const GraphicHwOps qxl_ops = { .gfx_update = qxl_hw_update, - .gfx_update_async = true, }; static void qxl_enter_vga_mode(PCIQXLDevice *d) @@ -1928,11 +1927,11 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_t events) /* graphics console */ -static void qxl_hw_update(void *opaque) +static bool qxl_hw_update(void *opaque) { PCIQXLDevice *qxl = opaque; - qxl_render_update(qxl); + return qxl_render_update(qxl); } static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, diff --git a/hw/display/ramfb-standalone.c b/hw/display/ramfb-standalone.c index f1958be32ad..27f0ba19f90 100644 --- a/hw/display/ramfb-standalone.c +++ b/hw/display/ramfb-standalone.c @@ -20,7 +20,7 @@ struct RAMFBStandaloneState { bool use_legacy_x86_rom; }; -static void display_update_wrapper(void *dev) +static bool display_update_wrapper(void *dev) { RAMFBStandaloneState *ramfb = RAMFB(dev); @@ -29,6 +29,8 @@ static void display_update_wrapper(void *dev) } else { ramfb_display_update(ramfb->con, ramfb->state); } + + return true; } static const GraphicHwOps wrapper_ops = { diff --git a/hw/display/sm501.c b/hw/display/sm501.c index a07aa9886f9..a3993ceba29 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -1716,7 +1716,7 @@ static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, } } -static void sm501_update_display(void *opaque) +static bool sm501_update_display(void *opaque) { SM501State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1740,7 +1740,7 @@ static void sm501_update_display(void *opaque) if (!((crt ? s->dc_crt_control : s->dc_panel_control) & SM501_DC_CRT_CONTROL_ENABLE)) { - return; + return true; } palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - @@ -1761,7 +1761,7 @@ static void sm501_update_display(void *opaque) default: qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" "invalid control register value.\n"); - return; + return true; } /* set up to draw hardware cursor */ @@ -1833,6 +1833,8 @@ static void sm501_update_display(void *opaque) if (y_start >= 0) { dpy_gfx_update(s->con, 0, y_start, width, y - y_start); } + + return true; } static const GraphicHwOps sm501_ops = { diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c index 87781438cd5..229856cc427 100644 --- a/hw/display/ssd0303.c +++ b/hw/display/ssd0303.c @@ -203,7 +203,7 @@ static int ssd0303_event(I2CSlave *i2c, enum i2c_event event) return 0; } -static void ssd0303_update_display(void *opaque) +static bool ssd0303_update_display(void *opaque) { ssd0303_state *s = (ssd0303_state *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -218,11 +218,11 @@ static void ssd0303_update_display(void *opaque) uint8_t mask; if (!s->redraw) - return; + return true; switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 15: dest_width = 2; break; @@ -237,7 +237,7 @@ static void ssd0303_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } dest_width *= MAGNIFY; memset(colortab, 0xff, dest_width); @@ -269,6 +269,8 @@ static void ssd0303_update_display(void *opaque) } s->redraw = 0; dpy_gfx_update(s->con, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY); + + return true; } static void ssd0303_invalidate_display(void * opaque) diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index af5ff4fecdc..67db16086c8 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -181,7 +181,7 @@ static uint32_t ssd0323_transfer(SSIPeripheral *dev, uint32_t data) return 0; } -static void ssd0323_update_display(void *opaque) +static bool ssd0323_update_display(void *opaque) { ssd0323_state *s = (ssd0323_state *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -197,11 +197,11 @@ static void ssd0323_update_display(void *opaque) int dest_width; if (!s->redraw) - return; + return true; switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 15: dest_width = 2; break; @@ -216,7 +216,7 @@ static void ssd0323_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } p = colortab; for (i = 0; i < 16; i++) { @@ -240,7 +240,7 @@ static void ssd0323_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } p += dest_width; } @@ -271,6 +271,7 @@ static void ssd0323_update_display(void *opaque) } s->redraw = 0; dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY); + return true; } static void ssd0323_invalidate_display(void * opaque) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index ea92a48400c..cedbf5c7acd 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -209,7 +209,7 @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, /* Fixed line length 1024 allows us to do nice tricks not possible on VGA... */ -static void tcx_update_display(void *opaque) +static bool tcx_update_display(void *opaque) { TCXState *ts = opaque; DisplaySurface *surface = qemu_console_surface(ts->con); @@ -257,9 +257,10 @@ static void tcx_update_display(void *opaque) ts->width, y - y_start); } g_free(snap); + return true; } -static void tcx24_update_display(void *opaque) +static bool tcx24_update_display(void *opaque) { TCXState *ts = opaque; DisplaySurface *surface = qemu_console_surface(ts->con); @@ -312,6 +313,7 @@ static void tcx24_update_display(void *opaque) ts->width, y - y_start); } g_free(snap); + return true; } static void tcx_invalidate_display(void *opaque) diff --git a/hw/display/vga.c b/hw/display/vga.c index 0d69a53f27a..776aa443246 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1783,7 +1783,7 @@ static void vga_draw_blank(VGACommonState *s, int full_update) #define GMODE_GRAPH 1 #define GMODE_BLANK 2 -static void vga_update_display(void *opaque) +static bool vga_update_display(void *opaque) { VGACommonState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1818,6 +1818,8 @@ static void vga_update_display(void *opaque) break; } } + + return true; } /* force a full display refresh */ diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index cb76302e2d8..94cf362d152 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -83,8 +83,9 @@ static void virtio_gpu_invalidate_display(void *opaque) { } -static void virtio_gpu_update_display(void *opaque) +static bool virtio_gpu_update_display(void *opaque) { + return true; } static void virtio_gpu_text_update(void *opaque, console_ch_t *chardata) diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index 5e087169f2f..f4713b91a66 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -19,15 +19,15 @@ static void virtio_vga_base_invalidate_display(void *opaque) } } -static void virtio_vga_base_update_display(void *opaque) +static bool virtio_vga_base_update_display(void *opaque) { VirtIOVGABase *vvga = opaque; VirtIOGPUBase *g = vvga->vgpu; if (g->enable) { - g->hw_ops->gfx_update(g); + return g->hw_ops->gfx_update(g); } else { - vvga->vga.hw_ops->gfx_update(&vvga->vga); + return vvga->vga.hw_ops->gfx_update(&vvga->vga); } } diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 2b95787ddfd..c84c84a445e 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1135,14 +1135,13 @@ static inline void vmsvga_check_size(struct vmsvga_state_s *s) } } -static void vmsvga_update_display(void *opaque) +static bool vmsvga_update_display(void *opaque) { struct vmsvga_state_s *s = opaque; if (!s->enable || !s->config) { /* in standard vga mode */ - s->vga.hw_ops->gfx_update(&s->vga); - return; + return s->vga.hw_ops->gfx_update(&s->vga); } vmsvga_check_size(s); @@ -1154,6 +1153,8 @@ static void vmsvga_update_display(void *opaque) s->invalidated = 0; dpy_gfx_update_full(s->vga.con); } + + return true; } static void vmsvga_reset(DeviceState *dev) diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index ba886a940ee..2e431e27be6 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -709,14 +709,14 @@ static void xenfb_send_refresh_period(struct XenFB *xenfb, int period) * Our screen might be inactive. When asked for * an update we know it is active. */ -static void xenfb_update(void *opaque) +static bool xenfb_update(void *opaque) { struct XenFB *xenfb = opaque; DisplaySurface *surface; int i; if (xenfb->c.xendev.be_state != XenbusStateConnected) - return; + return true; if (!xenfb->feature_update) { /* we don't get update notifications, thus use the @@ -770,6 +770,8 @@ static void xenfb_update(void *opaque) } xenfb->up_count = 0; xenfb->up_fullscreen = 0; + + return true; } static void xenfb_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index 7d037b46a35..50e6ef10984 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1252,12 +1252,12 @@ static inline void xlnx_dp_blend_surface(XlnxDPState *s) surface_height(s->g_plane.surface)); } -static void xlnx_dp_update_display(void *opaque) +static bool xlnx_dp_update_display(void *opaque) { XlnxDPState *s = XLNX_DP(opaque); if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { - return; + return true; } xlnx_dpdma_trigger_vsync_irq(s->dpdma); @@ -1272,14 +1272,14 @@ static void xlnx_dp_update_display(void *opaque) */ s->core_registers[DP_INT_STATUS] |= (1 << 21); xlnx_dp_update_irq(s); - return; + return true; } if (xlnx_dp_global_alpha_enabled(s)) { if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { s->core_registers[DP_INT_STATUS] |= (1 << 21); xlnx_dp_update_irq(s); - return; + return true; } xlnx_dp_blend_surface(s); } @@ -1288,6 +1288,8 @@ static void xlnx_dp_update_display(void *opaque) * XXX: We might want to update only what changed. */ dpy_gfx_update_full(s->console); + + return true; } static const GraphicHwOps xlnx_dp_gfx_ops = { diff --git a/hw/vfio/display.c b/hw/vfio/display.c index 5a42a6f7a29..4a9a58036e3 100644 --- a/hw/vfio/display.c +++ b/hw/vfio/display.c @@ -285,7 +285,7 @@ static void vfio_display_free_dmabufs(VFIOPCIDevice *vdev) } } -static void vfio_display_dmabuf_update(void *opaque) +static bool vfio_display_dmabuf_update(void *opaque) { VFIOPCIDevice *vdev = opaque; VFIODisplay *dpy = vdev->dpy; @@ -298,7 +298,7 @@ static void vfio_display_dmabuf_update(void *opaque) if (dpy->ramfb) { ramfb_display_update(dpy->con, dpy->ramfb); } - return; + return true; } width = qemu_dmabuf_get_width(primary->buf); @@ -340,6 +340,8 @@ static void vfio_display_dmabuf_update(void *opaque) if (free_bufs) { vfio_display_free_dmabufs(vdev); } + + return true; } static int vfio_display_get_flags(void *opaque) @@ -399,7 +401,7 @@ void vfio_display_reset(VFIOPCIDevice *vdev) dpy_gfx_update_full(vdev->dpy->con); } -static void vfio_display_region_update(void *opaque) +static bool vfio_display_region_update(void *opaque) { VFIOPCIDevice *vdev = opaque; VFIODisplay *dpy = vdev->dpy; @@ -414,18 +416,18 @@ static void vfio_display_region_update(void *opaque) if (ret < 0) { error_report("ioctl VFIO_DEVICE_QUERY_GFX_PLANE: %s", strerror(errno)); - return; + return true; } if (!plane.drm_format || !plane.size) { if (dpy->ramfb) { ramfb_display_update(dpy->con, dpy->ramfb); dpy->region.surface = NULL; } - return; + return true; } format = qemu_drm_format_to_pixman(plane.drm_format); if (!format) { - return; + return true; } if (dpy->region.buffer.size && @@ -476,11 +478,12 @@ static void vfio_display_region_update(void *opaque) dpy_gfx_update(dpy->con, 0, 0, surface_width(dpy->region.surface), surface_height(dpy->region.surface)); - return; + return true; err: vfio_region_exit(&dpy->region.buffer); vfio_region_finalize(&dpy->region.buffer); + return true; } static const GraphicHwOps vfio_display_region_ops = { diff --git a/ui/console.c b/ui/console.c index abb6cba2826..a608c29b843 100644 --- a/ui/console.c +++ b/ui/console.c @@ -136,15 +136,10 @@ void graphic_hw_update_done(QemuConsole *con) void graphic_hw_update(QemuConsole *con) { - bool async = false; if (!con) { return; } - if (con->hw_ops->gfx_update) { - con->hw_ops->gfx_update(con->hw); - async = con->hw_ops->gfx_update_async; - } - if (!async) { + if (!con->hw_ops->gfx_update || con->hw_ops->gfx_update(con->hw)) { graphic_hw_update_done(con); } } diff --git a/hw/display/apple-gfx.m b/hw/display/apple-gfx.m index e0a765fcb1f..77d80fb7cef 100644 --- a/hw/display/apple-gfx.m +++ b/hw/display/apple-gfx.m @@ -330,25 +330,25 @@ static void apple_gfx_render_frame_completed_bh(void *opaque) } } -static void apple_gfx_fb_update_display(void *opaque) +static bool apple_gfx_fb_update_display(void *opaque) { AppleGFXState *s = opaque; + bool done = true; assert(bql_locked()); if (s->new_frame_ready) { dpy_gfx_update_full(s->con); s->new_frame_ready = false; - graphic_hw_update_done(s->con); } else if (s->pending_frames > 0) { s->gfx_update_requested = true; - } else { - graphic_hw_update_done(s->con); + done = false; } + + return done; } static const GraphicHwOps apple_gfx_fb_ops = { .gfx_update = apple_gfx_fb_update_display, - .gfx_update_async = true, }; /* ------ Mouse cursor and display mode setting ------ */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 08:20:19 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 08:20:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295470.1572114 (Exim 4.92) (envelope-from ) id 1wHdfo-0008Js-7z; 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arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Tue, 28 Apr 2026 10:20:01 +0200 From: Nicola Vetrini To: Michal Orzel Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini , Julien Grall , Bertrand Marquis , Luca Fancellu Subject: Re: [PATCH v2] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info In-Reply-To: <20260428080218.19371-1-michal.orzel@amd.com> References: <20260428080218.19371-1-michal.orzel@amd.com> Message-ID: <2f9875a8a1f4d85ddceccb2d093a4951@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-42698a/1777364401-7FF7EF3B-BDC321F9/0/0 X-purgate-type: clean X-purgate-size: 3123 On 2026-04-28 10:02, Michal Orzel wrote: > overlay_get_nodes_info() is called before fdt_overlay_apply() to > extract > target paths from the overlay. This fails for overlays using > phandle-based > targeting (target = <&label>) because DTC compiles these as unresolved > fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to > return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to > manually modify the dtbo (even for hwdom) to switch from target to > target-phandle by manually inspecting also the host DTB. > > Introduce overlay_get_target_path() which directly handles the two > targeting cases that occur before fixup resolution: > - target-path: the string property is returned directly. > - target = <&label>: the label is found in the overlay's __fixups__ > node, then resolved to a path via the base DTB's __symbols__ node. > > Libfdt fdt_for_each_property_offset() violates MISRA R20.7. Despite > libfdt being excluded from the analysis, this causes ECLAIR scan to > report a regression because the violation introduced by a macro is > reported at the call site. Deviate R20.7 for libfdt.h. > > Reviewed-by: Luca Fancellu > Acked-by: Stefano Stabellini > Signed-off-by: Michal Orzel > --- > In my pre-push testing I realized ECLAIR allcode reported a violation > related to > the use of fdt_for_each_property_offset. Libfdt is excluded from > analysis but > this does not apply to e.g. macros used in other places. > > Changes in v2: > - strip out from series that is ready to be committed > - deviate 20.7 for libfdt.h. Discussed with Nicole. > > https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2484326830 > --- > .../eclair_analysis/ECLAIR/deviations.ecl | 1 + > xen/common/device-tree/dt-overlay.c | 65 +++++++++++++++++-- > 2 files changed, 60 insertions(+), 6 deletions(-) > > diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl > b/automation/eclair_analysis/ECLAIR/deviations.ecl > index 30c323906924..5f0b73062474 100644 > --- a/automation/eclair_analysis/ECLAIR/deviations.ecl > +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl > @@ -631,6 +631,7 @@ not in scope for compliance are allowed, as that is > imported code." > -file_tag+={acpi_cpu_idle, "^xen/arch/x86/acpi/cpu_idle\\.c$"} > -config=MC3A2.R20.7,reports+={safe, > "any_area(any_loc(file(gnu_efi_include)||any_exp(macro(^NextMemoryDescriptor$))))"} > -config=MC3A2.R20.7,reports+={safe, > "any_area(any_loc(file(acpi_cpu_idle)))"} > +-config=MC3A2.R20.7,reports+={safe, > "any_area(any_loc(any_exp(file(^xen/include/xen/libfdt/libfdt.h$))))"} > -doc_end > Nit: I think using a file_tag as above is better, but in any case use libfdt\\.h in the regex > -doc_begin="To avoid compromising readability, the macros > alternative_(v)?call[0-9] are allowed -- Nicola Vetrini, B.Sc. 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tlsNG-720697/1777367161-B3D67161-D0B8D5FE/0/0 X-purgate-type: clean X-purgate-size: 11277 On Fri, Mar 13, 2026 at 04:35:01PM +0000, Thierry Escande wrote: > In order to factorize the common parts between i440 and q35 dsdt files, > this patch splits dsdt.asl and put the i440 specific parts into > dsdt_i400.asl. > > This also makes use of #include directives instead of file > concatenations to build the asl files. > > Also, the anycpu asl files generation makes use of makefile pattern > rules to avoid duplication for i440 and q35. > > Becuase the LPC controller BDF (which differs between i440 and q35) must s/Becuase/Because/ > be set at device declaration, it is still set in dsdt.asl by checking > for a MACHINE_TYPE_I440 macro defined in dsdt_i400.asl. s/i400/i440/ > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/Makefile | 2 +- > tools/firmware/hvmloader/ovmf.c | 4 ++-- > tools/firmware/hvmloader/seabios.c | 4 ++-- > tools/firmware/hvmloader/util.c | 4 ++-- > tools/firmware/hvmloader/util.h | 4 ++-- > tools/libacpi/Makefile | 10 ++++----- > tools/libacpi/dsdt.asl | 25 ++++----------------- > tools/libacpi/dsdt_i440.asl | 36 ++++++++++++++++++++++++++++++ > 8 files changed, 53 insertions(+), 36 deletions(-) > create mode 100644 tools/libacpi/dsdt_i440.asl > > diff --git a/tools/firmware/hvmloader/Makefile b/tools/firmware/hvmloader/Makefile > index 21de72187d..bdc33a877f 100644 > --- a/tools/firmware/hvmloader/Makefile > +++ b/tools/firmware/hvmloader/Makefile > @@ -78,7 +78,7 @@ rombios.o: roms.inc > smbios.o: CFLAGS += -D__SMBIOS_DATE__="\"$(SMBIOS_REL_DATE)\"" > > ACPI_PATH = ../../libacpi > -DSDT_FILES += dsdt_anycpu_qemu_xen.c > +DSDT_FILES += dsdt_i440_anycpu_qemu_xen.c > ACPI_OBJS = $(patsubst %.c,%.o,$(DSDT_FILES)) build.o static_tables.o > $(ACPI_OBJS): CFLAGS += -iquote . -DLIBACPI_STDUTILS=\"$(CURDIR)/util.h\" > CFLAGS += -I$(ACPI_PATH) > diff --git a/tools/firmware/hvmloader/ovmf.c b/tools/firmware/hvmloader/ovmf.c > index 23610a0717..d264a50c73 100644 > --- a/tools/firmware/hvmloader/ovmf.c > +++ b/tools/firmware/hvmloader/ovmf.c > @@ -119,8 +119,8 @@ static void ovmf_load(const struct bios_config *config, > static void ovmf_acpi_build_tables(void) > { > struct acpi_config config = { > - .dsdt_anycpu = dsdt_anycpu_qemu_xen, > - .dsdt_anycpu_len = dsdt_anycpu_qemu_xen_len, > + .dsdt_anycpu = dsdt_i440_anycpu_qemu_xen, > + .dsdt_anycpu_len = dsdt_i440_anycpu_qemu_xen_len, > .dsdt_15cpu = NULL, > .dsdt_15cpu_len = 0 > }; > diff --git a/tools/firmware/hvmloader/seabios.c b/tools/firmware/hvmloader/seabios.c > index 444d118ddb..74b0406b5a 100644 > --- a/tools/firmware/hvmloader/seabios.c > +++ b/tools/firmware/hvmloader/seabios.c > @@ -90,8 +90,8 @@ static void seabios_acpi_build_tables(void) > { > uint32_t rsdp = (uint32_t)scratch_alloc(sizeof(struct acpi_20_rsdp), 0); > struct acpi_config config = { > - .dsdt_anycpu = dsdt_anycpu_qemu_xen, > - .dsdt_anycpu_len = dsdt_anycpu_qemu_xen_len, > + .dsdt_anycpu = dsdt_i440_anycpu_qemu_xen, > + .dsdt_anycpu_len = dsdt_i440_anycpu_qemu_xen_len, > .dsdt_15cpu = NULL, > .dsdt_15cpu_len = 0, > }; > diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c > index e651342681..f1ed1eb48d 100644 > --- a/tools/firmware/hvmloader/util.c > +++ b/tools/firmware/hvmloader/util.c > @@ -843,8 +843,8 @@ void hvmloader_acpi_build_tables(struct acpi_config *config, > s = xenstore_read("platform/device-model", ""); > if ( !strncmp(s, "qemu_xen", 9) ) > { > - config->dsdt_anycpu = dsdt_anycpu_qemu_xen; > - config->dsdt_anycpu_len = dsdt_anycpu_qemu_xen_len; > + config->dsdt_anycpu = dsdt_i440_anycpu_qemu_xen; > + config->dsdt_anycpu_len = dsdt_i440_anycpu_qemu_xen_len; > config->dsdt_15cpu = NULL; > config->dsdt_15cpu_len = 0; > } > diff --git a/tools/firmware/hvmloader/util.h b/tools/firmware/hvmloader/util.h > index 765a013ddd..3c5eeff5e7 100644 > --- a/tools/firmware/hvmloader/util.h > +++ b/tools/firmware/hvmloader/util.h > @@ -381,8 +381,8 @@ extern struct e820map memory_map; > bool check_overlap(uint64_t start, uint64_t size, > uint64_t reserved_start, uint64_t reserved_size); > > -extern const unsigned char dsdt_anycpu_qemu_xen[], dsdt_anycpu[], dsdt_15cpu[]; > -extern const int dsdt_anycpu_qemu_xen_len, dsdt_anycpu_len, dsdt_15cpu_len; > +extern const unsigned char dsdt_i440_anycpu_qemu_xen[], dsdt_anycpu[], dsdt_15cpu[]; > +extern const int dsdt_i440_anycpu_qemu_xen_len, dsdt_anycpu_len, dsdt_15cpu_len; While there you can make this unsigned int, like the dsdt_anycpu_len field. > > unsigned long acpi_pages_allocated(void); > > diff --git a/tools/libacpi/Makefile b/tools/libacpi/Makefile > index b21a64c6b4..d3d4bc9543 100644 > --- a/tools/libacpi/Makefile > +++ b/tools/libacpi/Makefile > @@ -11,7 +11,7 @@ endif > > MK_DSDT = $(ACPI_BUILD_DIR)/mk_dsdt > > -C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_anycpu_qemu_xen.c dsdt_pvh.c > +C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_i440_anycpu_qemu_xen.c dsdt_pvh.c > C_SRC-$(CONFIG_ARM_64) = dsdt_anycpu_arm.c > DSDT_FILES ?= $(C_SRC-y) > C_SRC = $(addprefix $(ACPI_BUILD_DIR)/, $(DSDT_FILES)) > @@ -39,18 +39,16 @@ $(H_SRC): $(ACPI_BUILD_DIR)/%.h: %.asl > $(MK_DSDT): mk_dsdt.c > $(HOSTCC) $(HOSTCFLAGS) $(MKDSDT_CFLAGS-y) $(CFLAGS_xeninclude) -D__XEN_TOOLS__ -o $@ mk_dsdt.c > > -$(ACPI_BUILD_DIR)/dsdt_anycpu_qemu_xen.asl: dsdt.asl dsdt_acpi_info.asl $(MK_DSDT) > +$(ACPI_BUILD_DIR)/dsdt_%_anycpu_qemu_xen.asl: dsdt_%.asl dsdt.asl dsdt_acpi_info.asl $(MK_DSDT) > # Remove last bracket > awk 'NR > 1 {print s} {s=$$0}' $< > $@.$(TMP_SUFFIX) > - cat dsdt_acpi_info.asl >> $@.$(TMP_SUFFIX) > $(MK_DSDT) --debug=$(debug) --dm-version qemu-xen >> $@.$(TMP_SUFFIX) > mv -f $@.$(TMP_SUFFIX) $@ > > # NB. awk invocation is a portable alternative to 'head -n -1' > -$(ACPI_BUILD_DIR)/dsdt_%cpu.asl: dsdt.asl dsdt_acpi_info.asl $(MK_DSDT) > +$(ACPI_BUILD_DIR)/dsdt_%cpu.asl: dsdt_i440.asl dsdt.asl dsdt_acpi_info.asl $(MK_DSDT) > # Remove last bracket > awk 'NR > 1 {print s} {s=$$0}' $< > $@.$(TMP_SUFFIX) > - cat dsdt_acpi_info.asl >> $@.$(TMP_SUFFIX) > $(MK_DSDT) --debug=$(debug) --maxcpu $* >> $@.$(TMP_SUFFIX) > mv -f $@.$(TMP_SUFFIX) $@ > > @@ -65,7 +63,7 @@ $(ACPI_BUILD_DIR)/dsdt_anycpu_arm.asl: $(MK_DSDT) > mv -f $@.$(TMP_SUFFIX) $@ > > $(C_SRC): $(ACPI_BUILD_DIR)/%.c: $(ACPI_BUILD_DIR)/%.asl > - $(IASL) -vs -p $(ACPI_BUILD_DIR)/$*.$(TMP_SUFFIX) -tc $< > + $(IASL) -vs -I $(CURDIR) -p $(ACPI_BUILD_DIR)/$*.$(TMP_SUFFIX) -tc $< > sed -e 's/AmlCode/$*/g' -e 's/_aml_code//g' $(ACPI_BUILD_DIR)/$*.hex > $@.$(TMP_SUFFIX) > echo "int $*_len=sizeof($*);" >> $@.$(TMP_SUFFIX) > mv -f $@.$(TMP_SUFFIX) $@ > diff --git a/tools/libacpi/dsdt.asl b/tools/libacpi/dsdt.asl > index 32b42f85ae..130826fdcc 100644 > --- a/tools/libacpi/dsdt.asl > +++ b/tools/libacpi/dsdt.asl > @@ -5,8 +5,6 @@ > * Copyright (c) 2004, Intel Corporation. > */ > > -DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > -{ > Name (\PMBS, 0x0C00) > Name (\PMLN, 0x08) > Name (\IOB1, 0x00) > @@ -199,7 +197,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > > Device (ISA) > { > - Name (_ADR, 0x00010000) /* device 1, fn 0 */ > + /* Error will be raised if the machine type is not defined */ > + #ifdef MACHINE_TYPE_I440 > + Name (_ADR, 0x00010000) /* device 1, fn 0 */ > + #endif I think we want the preprocessor directives not indented the same as asl code, like we do in C, iow: Device (ISA) { /* Error will be raised if the machine type is not defined */ #ifdef MACHINE_TYPE_I440 Name (_ADR, 0x00010000) /* device 1, fn 0 */ #endif Same with the includes and defines below. > > OperationRegion(PIRQ, PCI_Config, 0x60, 0x4) > Scope(\) { > @@ -329,23 +330,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > }) > } > > - Device (FDC0) > - { > - Name (_HID, EisaId ("PNP0700")) > - Method (_STA, 0, NotSerialized) > - { > - Return (0x0F) > - } > - > - Name (_CRS, ResourceTemplate () > - { > - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) > - IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) > - IRQNoFlags () {6} > - DMA (Compatibility, NotBusMaster, Transfer8) {2} > - }) > - } I need to look at the Q35 changes, but ff the only differences are the Name() method at the top and this, we might as well use an #ifdef here, and there's no need to split into so many separate files? I need to look at further patches. The ACPI table generation stuff could certainly do with an overall rework. > Device (UAR1) > { > Name (_HID, EisaId ("PNP0501")) > @@ -444,4 +428,3 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > Method(_PIC, 1) { > Store(Arg0, PICD) > } > -} > diff --git a/tools/libacpi/dsdt_i440.asl b/tools/libacpi/dsdt_i440.asl > new file mode 100644 > index 0000000000..e80c454ad9 > --- /dev/null > +++ b/tools/libacpi/dsdt_i440.asl > @@ -0,0 +1,36 @@ > +/* SPDX-License-Identifier: LGPL-2.1-only */ > +/****************************************************************************** > + * DSDT for Xen with Qemu device model (for i440 machine) > + * > + * Copyright (c) 2004, Intel Corporation. > + */ > + > +DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > +{ > + #define MACHINE_TYPE_I440 IMO we probably want to define this outside of the DefinitionBlock section, just after the copyright header. > + > + #include "dsdt.asl" > + > + Scope (\_SB.PCI0.ISA) > + { > + Device (FDC0) > + { > + Name (_HID, EisaId ("PNP0700")) > + > + Method (_STA, 0, NotSerialized) > + { > + Return (0x0F) > + } > + > + Name (_CRS, ResourceTemplate () > + { > + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) > + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) > + IRQNoFlags () {6} > + DMA (Compatibility, NotBusMaster, Transfer8) {2} > + }) > + } > + } > + > + #include "dsdt_acpi_info.asl" > +} > -- > 2.51.0 > > > > -- > Thierry Escande | Vates XCP-ng Developer > > XCP-ng & Xen Orchestra - Vates solutions > > web: https://vates.tech > From xen-devel-bounces@lists.xenproject.org Tue Apr 28 09:31:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 09:31:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295505.1572173 (Exim 4.92) (envelope-from ) id 1wHemf-0002mq-UY; Tue, 28 Apr 2026 09:31:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295505.1572173; Tue, 28 Apr 2026 09:31:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHemf-0002mj-RM; Tue, 28 Apr 2026 09:31:13 +0000 Received: by outflank-mailman (input) for mailman id 1295505; Tue, 28 Apr 2026 09:31:12 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHeme-0002mN-4e for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 09:31:12 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHemd-00Gybj-EG for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 11:31:11 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f07e57-2eae-0a2a0a5409dd-0a2a4502b842-48 for ; Tue, 28 Apr 2026 11:31:11 +0200 Received: from [209.85.208.44] (helo=mail-ed1-f44.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f07e5f-af86-0a2a45020019-d155d02cb111-3 for ; Tue, 28 Apr 2026 11:31:11 +0200 Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-678adefbd26so6416546a12.3 for ; Tue, 28 Apr 2026 02:31:11 -0700 (PDT) Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com. 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On Mon, 27 Apr 2026 at 19:18, Christophe Leroy (CS GROUP) wrote: > Today there are approximately 3000 calls for copy_to_user() and > 3000 calls to copy_from_user(). > > The majority of callers of copy_{to/from}_user() don't care about the > return value, they only check whether it is 0 or not, and when it is > not 0 they handle it as a -EACCES. I think the "a" can be dropped. > In order to allow better optimisation of copy_{to/from}_user() when > the size of the copy is known at build time, create new fonctions functions > named copy_{to/from}_user_partial() to be used by the few callers > that are interested in partial copies and need to now how many know > bytes remain at the end of the copy. > > For the time being it is just the same as copy_{to/from}_user(). > > Signed-off-by: Christophe Leroy (CS GROUP) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From xen-devel-bounces@lists.xenproject.org Tue Apr 28 09:36:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 09:36:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295517.1572181 (Exim 4.92) (envelope-from ) id 1wHerh-0003RL-KR; Tue, 28 Apr 2026 09:36:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295517.1572181; Tue, 28 Apr 2026 09:36:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHerh-0003RE-Hn; Tue, 28 Apr 2026 09:36:25 +0000 Received: by outflank-mailman (input) for mailman id 1295517; Tue, 28 Apr 2026 09:36:24 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHerg-0003R8-Ht for xen-devel@lists.xenproject.org; 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Message-ID: <82e4eb62-4226-40b6-a1ef-4711f29a5e4f@citrix.com> Date: Tue, 28 Apr 2026 10:36:09 +0100 User-Agent: Mozilla Thunderbird Cc: Andrew Cooper , "Christophe Leroy (CS GROUP)" , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery To: Yury Norov References: <9fe875d2f55af59c12708336c571a46038528678.1777306795.git.chleroy@kernel.org> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; 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Can you name it >>> CONFIG_OUTLINE_USERCOPY, or similar? >> You can't swap the "in" for "out" like this.  "out of line" is the >> opposite of "inline" in this context, while "outline" means something >> different and unrelated. > Check KASAN_OUTLINE vs KASAN_INLINE for example Then I suggest it gets corrected before more examples try to copy this non-english. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Apr 28 10:17:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 10:17:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295532.1572194 (Exim 4.92) (envelope-from ) id 1wHfUw-0001GO-KB; Tue, 28 Apr 2026 10:16:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295532.1572194; Tue, 28 Apr 2026 10:16:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfUw-0001GH-HH; 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b=cYThDGqSwE0+2ZYYNANFXZwQNPmlE1MR+sLRdN/7WzLv9ooE4VVt0jKLbao03d/gatn8PxkntU9ZWbXj+drinj0moxe68vsMznxCoNm3+KJD+6f72/o3jTlYGkhjT/QUyFEUogaEr82hJnEd+4AouuLXtj81iSKGJLpmOrjX4R1WmltOYJQEwB4bXnKEbPc9Aqst0Ym7eDBc+HFQt1SJapLlDhPWogM99+/c83WdrpNBkErwdUswLXGCV7xwthsUhkeAxc3twKj/Pog/kzfsqHFBU4yxxzSUWrXuOqDprFN4VCDYH4fQmNla1dHouKA21avR6FdLK4X3zfAqYkUoPg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; Message-ID: <4c96c478-aeb5-443c-a6ca-f23caf7d5430@epam.com> Date: Tue, 28 Apr 2026 12:16:52 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/23] xen/arm: smmuv3: Add support for stage-1 and nested stage translation To: Julien Grall , "xen-devel@lists.xenproject.org" Cc: Rahul Singh , Bertrand Marquis , Stefano Stabellini , Michal Orzel , Volodymyr Babchuk References: <56a7c116-4ecb-4dfc-a7dd-774d53041fe9@xen.org> <87a04781-5765-43b6-8b21-cb993609bd91@epam.com> Content-Language: en-US From: Milan Djokic In-Reply-To: Content-Type: text/plain; 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Add support for >>>> Stage-1 translation that is required to support nested stage >>>> translation. >>>> >>>> In true nested mode, both s1_cfg and s2_cfg will coexist. >>>> Let's remove the union. When nested stage translation is setup, both >>>> s1_cfg and s2_cfg are valid. >>>> >>>> We introduce a new smmu_domain abort field that will be set >>>> upon guest stage-1 configuration passing. If no guest stage-1 >>>> config has been attached, it is ignored when writing the STE. >>>> >>>> arm_smmu_write_strtab_ent() is modified to write both stage >>>> fields in the STE and deal with the abort field. >>>> >>>> Signed-off-by: Rahul Singh >>>> Signed-off-by: Milan Djokic >>>> --- >>>>    xen/drivers/passthrough/arm/smmu-v3.c | 93 ++++++++++++++++++++++ >>>> +---- >>>>    xen/drivers/passthrough/arm/smmu-v3.h |  9 +++ >>>>    2 files changed, 91 insertions(+), 11 deletions(-) >>>> >>>> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/ >>>> passthrough/arm/smmu-v3.c >>>> index 73cc4ef08f..f9c6837919 100644 >>>> --- a/xen/drivers/passthrough/arm/smmu-v3.c >>>> +++ b/xen/drivers/passthrough/arm/smmu-v3.c >>>> @@ -683,8 +683,10 @@ static void arm_smmu_write_strtab_ent(struct >>>> arm_smmu_master *master, u32 sid, >>>>         * 3. Update Config, sync >>>>         */ >>>>        u64 val = le64_to_cpu(dst[0]); >>>> -    bool ste_live = false; >>>> +    bool s1_live = false, s2_live = false, ste_live = false; >>>> +    bool abort, translate = false; >>>>        struct arm_smmu_device *smmu = NULL; >>>> +    struct arm_smmu_s1_cfg *s1_cfg = NULL; >>>>        struct arm_smmu_s2_cfg *s2_cfg = NULL; >>>>        struct arm_smmu_domain *smmu_domain = NULL; >>>>        struct arm_smmu_cmdq_ent prefetch_cmd = { >>>> @@ -699,30 +701,54 @@ static void arm_smmu_write_strtab_ent(struct >>>> arm_smmu_master *master, u32 sid, >>>>            smmu = master->smmu; >>>>        } >>>> -    if (smmu_domain) >>>> -        s2_cfg = &smmu_domain->s2_cfg; >>>> +    if (smmu_domain) { >>>> +        switch (smmu_domain->stage) { >>>> +        case ARM_SMMU_DOMAIN_NESTED: >>>> +            s1_cfg = &smmu_domain->s1_cfg; >>>> +            fallthrough; >>>> +        case ARM_SMMU_DOMAIN_S2: >>>> +            s2_cfg = &smmu_domain->s2_cfg; >>>> +            break; >>>> +        default: >>>> +            break; >>>> +        } >>>> +        translate = !!s1_cfg || !!s2_cfg; >>> >>> NIT: translate is a bool. So do you actually need the !!? >>> >> >> No, !! is not necessary here, will fix this. >> >>>> +    } >>>>        if (val & STRTAB_STE_0_V) { >>>>            switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { >>>>            case STRTAB_STE_0_CFG_BYPASS: >>>>                break; >>>> +        case STRTAB_STE_0_CFG_S1_TRANS: >>>> +            s1_live = true; >>>> +            break; >>>>            case STRTAB_STE_0_CFG_S2_TRANS: >>>> -            ste_live = true; >>>> +            s2_live = true; >>>> +            break; >>>> +        case STRTAB_STE_0_CFG_NESTED: >>>> +            s1_live = true; >>>> +            s2_live = true; >>>>                break; >>>>            case STRTAB_STE_0_CFG_ABORT: >>>> -            BUG_ON(!disable_bypass); >>> >>> I am not sure I understand why this was removed. Can you clarify? >>> >> >> Yes. With the stage-1 support, abort is controlled per guest smmu >> configuration, so abort state is valid and not controlled by the global >> disable_bypass, but with per-config smmu_domain->abort field instead. > > Are we ok to allow the guest to control the bit? For instance, what does > it mean if the guest decide to that no abort is necessary but the region > is not mapped in stage-2? > If the guest disables abort and translation is enabled, accesses to regions not mapped in stage-2 will still generate stage-2 translation faults. This won’t result in bypass. In nested mode, both stage-1 and stage-2 are programmed, so stage-2 is always active. However, missing or invalid stage-2 mappings can still occur, and in such cases generating a stage-2 fault is the expected behavior, and would typically indicate either an invalid access from the guest or a missing stage-2 mapping. > [...] > >> >> The original idea was to also allow stage-1-only support. But I'm not >> sure if stage-1-only usecase is useful or even valid for Xen.. I will >> update the patch series with the missing parts for stage-1-only support, >> pointed out by Luca, but the question remains if this is needed at all. >> If not, I can revert to original state where stage-2 was always required. > > By "stage-1 only" support, do you mean Xen would use the stage-1 in > replacement of the stage-2? Or do you mean the guest will use the > stage-1 page-table and there will be no isolation from Xen? > > If the former, then I believe the page tables don't have the exact same > format. Today, the page-tables are shared between the CPU and IOMMU, so > this would need to be duplicated. For now, I am not sure this is worth > to do. > > If the latter, this would require the guest to be directly mapped (i.e. > IPA == PA) but it would also open a big hole. So I would want to > understand the exact use case first. > The latter. In this case, the guest would configure stage-1 while stage-2 translation is not used, so there is no additional isolation enforced by Xen. This would only be intended for specific usecases with trusted domains. But yes, this opens a significant hole if used with untrusted guests. If there is no strong usecase, we could restrict the implementation to always require stage-2. > Cheers, > Best regards, Milan From xen-devel-bounces@lists.xenproject.org Tue Apr 28 10:18:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 10:18:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295543.1572203 (Exim 4.92) (envelope-from ) id 1wHfVv-0001zY-1W; Tue, 28 Apr 2026 10:17:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295543.1572203; Tue, 28 Apr 2026 10:17:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfVu-0001zR-V1; Tue, 28 Apr 2026 10:17:58 +0000 Received: by outflank-mailman (input) for mailman id 1295543; Tue, 28 Apr 2026 10:17:57 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfVt-0001zJ-JT for xen-devel@lists.xenproject.org; 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Date: Tue, 28 Apr 2026 12:17:49 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Thierry Escande Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Anthony PERARD , Alexey Gerasimenko Subject: Re: [PATCH 02/17] libacpi: new DSDT ACPI table for Q35 Message-ID: References: <20260313163455.790692-1-thierry.escande@vates.tech> <20260313163455.790692-3-thierry.escande@vates.tech> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260313163455.790692-3-thierry.escande@vates.tech> X-ClientProxiedBy: MR1P264CA0083.FRAP264.PROD.OUTLOOK.COM (2603:10a6:501:3f::23) To CH7PR03MB7860.namprd03.prod.outlook.com (2603:10b6:610:24e::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH7PR03MB7860:EE_|DS7PR03MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a483f4f-2f8c-4c9f-da7e-08dea50f688a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024|18002099003|56012099003|22082099003; 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It only contains the specific Q35 parts that differ from i440). > At the moment, these are: > > - BDF location of LPC Controller > - Minor changes related to FDC detection > - Addition of _OSC method to inform OSPM about PCIe features supported > > As we are still using 4 PCI router links and their corresponding > device/register addresses are same (offset 0x60), no need to change PCI > routing descriptions. > > Note that '15cpu' ACPI tables are only applicable to qemu-traditional > (which have no support for Q35), so we need to use 'anycpu' version only. Is the above statement fully accurate? It seems like 15cpu tables are used with rombios, so the dependency is not on qemu-trad, but rather rombios? If it's truly only dependent on qemu-trad then we should remove those, as we have removed qemu-trad. > > Signed-off-by: Alexey Gerasimenko If the first SoB if from Alexey, the From: should also match. > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/Makefile | 2 +- > tools/libacpi/Makefile | 2 +- > tools/libacpi/dsdt.asl | 3 + > tools/libacpi/dsdt_q35.asl | 130 ++++++++++++++++++++++++++++++ > 4 files changed, 135 insertions(+), 2 deletions(-) > create mode 100644 tools/libacpi/dsdt_q35.asl > > diff --git a/tools/firmware/hvmloader/Makefile b/tools/firmware/hvmloader/Makefile > index bdc33a877f..99f045efaa 100644 > --- a/tools/firmware/hvmloader/Makefile > +++ b/tools/firmware/hvmloader/Makefile > @@ -78,7 +78,7 @@ rombios.o: roms.inc > smbios.o: CFLAGS += -D__SMBIOS_DATE__="\"$(SMBIOS_REL_DATE)\"" > > ACPI_PATH = ../../libacpi > -DSDT_FILES += dsdt_i440_anycpu_qemu_xen.c > +DSDT_FILES += dsdt_i440_anycpu_qemu_xen.c dsdt_q35_anycpu_qemu_xen.c > ACPI_OBJS = $(patsubst %.c,%.o,$(DSDT_FILES)) build.o static_tables.o > $(ACPI_OBJS): CFLAGS += -iquote . -DLIBACPI_STDUTILS=\"$(CURDIR)/util.h\" > CFLAGS += -I$(ACPI_PATH) > diff --git a/tools/libacpi/Makefile b/tools/libacpi/Makefile > index d3d4bc9543..e6c4a3fd8b 100644 > --- a/tools/libacpi/Makefile > +++ b/tools/libacpi/Makefile > @@ -11,7 +11,7 @@ endif > > MK_DSDT = $(ACPI_BUILD_DIR)/mk_dsdt > > -C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_i440_anycpu_qemu_xen.c dsdt_pvh.c > +C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_i440_anycpu_qemu_xen.c dsdt_q35_anycpu_qemu_xen.c dsdt_pvh.c > C_SRC-$(CONFIG_ARM_64) = dsdt_anycpu_arm.c > DSDT_FILES ?= $(C_SRC-y) > C_SRC = $(addprefix $(ACPI_BUILD_DIR)/, $(DSDT_FILES)) > diff --git a/tools/libacpi/dsdt.asl b/tools/libacpi/dsdt.asl > index 130826fdcc..dc764881c9 100644 > --- a/tools/libacpi/dsdt.asl > +++ b/tools/libacpi/dsdt.asl > @@ -201,6 +201,9 @@ > #ifdef MACHINE_TYPE_I440 > Name (_ADR, 0x00010000) /* device 1, fn 0 */ > #endif > + #ifdef MACHINE_TYPE_Q35 > + Name (_ADR, 0x001f0000) /* device 31, fn 0 */ > + #endif You possibly want to do: #ifdef ... #elif defined(...) #else #error ... #endif But seeing the difference is only for the address, why not do: #define ISA_DEV_SBDF 0x00010000 ... Name (_ADR, ISA_DEV_SBDF) ... And avoid the ifdef mess? > > OperationRegion(PIRQ, PCI_Config, 0x60, 0x4) > Scope(\) { > diff --git a/tools/libacpi/dsdt_q35.asl b/tools/libacpi/dsdt_q35.asl > new file mode 100644 > index 0000000000..7cefe63506 > --- /dev/null > +++ b/tools/libacpi/dsdt_q35.asl > @@ -0,0 +1,130 @@ > +/* SPDX-License-Identifier: LGPL-2.1-only */ > +/****************************************************************************** > + * DSDT for Xen with Qemu device model (for Q35 machine) > + */ > + > +DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) > +{ > + #define MACHINE_TYPE_Q35 > + > + #include "dsdt.asl" > + > + Scope (\_SB.PCI0) > + { > + /* _OSC, modified from ASL sample in ACPI spec */ > + Name (SUPP, 0) /* PCI _OSC Support Field value */ > + Name (CTRL, 0) /* PCI _OSC Control Field value */ > + Method (_OSC, 4) { > + /* Create DWORD-addressable fields from the Capabilities Buffer */ > + CreateDWordField (Arg3, 0, CDW1) > + > + /* Switch by UUID. > + * Only PCI Host Bridge Device capabilities UUID used for now Comment style, in Xen we use: /* * Switch by UIID. * Only PCI Host Bridge Device capabilities UUID used for now. */ The opening and closing lines are standalone. Also missing a full stop on the last line. The rest of the comments below also need adjusting. > + */ > + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { > + /* Create DWORD-addressable fields from the Capabilities Buffer */ > + CreateDWordField (Arg3, 4, CDW2) > + CreateDWordField (Arg3, 8, CDW3) > + > + /* Save Capabilities DWORD2 & 3 */ > + Store (CDW2, SUPP) > + Store (CDW3, CTRL) > + > + /* Validate Revision DWORD */ > + If (LNotEqual (Arg1, One)) { > + /* Unknown revision */ > + /* Support and Control DWORDs will be returned anyway */ > + Or (CDW1, 0x08, CDW1) > + } > + > + /* Control field bits are: > + * bit 0 PCI Express Native Hot Plug control > + * bit 1 SHPC Native Hot Plug control > + * bit 2 PCI Express Native Power Management Events control > + * bit 3 PCI Express Advanced Error Reporting control > + * bit 4 PCI Express Capability Structure control > + */ > + > + /* Always allow native PME, AER (no dependencies) > + * Never allow SHPC (no SHPC controller in this system) > + * Do not allow PCIe Capability Structure control for now > + * Also, ACPI hotplug is used for now instead of PCIe > + * Native Hot Plug > + */ > + And (CTRL, 0x0C, CTRL) > + > + If (LNotEqual (CDW3, CTRL)) { > + /* Some of Capabilities bits were masked */ > + Or (CDW1, 0x10, CDW1) > + } > + /* Update DWORD3 in the buffer */ > + Store (CTRL, CDW3) This looks equal to the QEMU code FWIW. > + } Else { > + Or (CDW1, 4, CDW1) /* Unrecognized UUID */ > + } > + Return (Arg3) > + } > + /* end of _OSC */ > + } > + > + /**************************************************************** > + * LPC ISA bridge > + ****************************************************************/ I would use a normal one-line comment here: /* LPCI ISA Bridge */ Has any of this been picked up from the QEMU asl files? Asking because the above comment looks to be verbatim copied from the QEMU file, and we then need to carry their copyright notice, which is not done in this patch. > + > + Scope (\_SB.PCI0.ISA) AFAICT this is adding more content to the ISA device already defined in dsdt.asl? > + { > + /* > + LPC ISA bridge > + > + PCI Interrupt Routing Register 2 (PIRQE..PIRQH) cannot be > + used because of existing Xen IRQ limitations (4 PCI links > + only) > + */ Right, and PIRQA..PIRQD is already defined in the generic dsdt.asl. Might be worth mentioning, otherwise the block looks incomplete. > + > + /* LPC_I/O: I/O Decode Ranges Register */ > + OperationRegion (LPCD, PCI_Config, 0x80, 0x2) > + Field (LPCD, AnyAcc, NoLock, Preserve) { > + COMA, 3, > + , 1, > + COMB, 3, > + > + Offset(0x01), > + LPTD, 2, > + , 2, > + FDCD, 2 > + } > + > + /* LPC_EN: LPC I/F Enables Register */ > + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) > + Field(LPCE, AnyAcc, NoLock, Preserve) { > + CAEN, 1, > + CBEN, 1, > + LPEN, 1, > + FDEN, 1 > + } > + > + Device (FDC0) > + { > + Name (_HID, EisaId ("PNP0700")) > + Method (_STA, 0, NotSerialized) > + { > + Store (FDEN, Local0) > + If (LEqual (Local0, 0)) { > + Return (0x00) > + } Else { > + Return (0x0F) > + } > + } > + > + Name (_CRS, ResourceTemplate () > + { > + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) > + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) > + IRQNoFlags () {6} > + DMA (Compatibility, NotBusMaster, Transfer8) {2} > + }) > + } > + } This seem to match the blocks in QEMU, so it's likely fine. Thanks, Roger. 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pr=C Message-ID: Date: Tue, 28 Apr 2026 12:22:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info To: Nicola Vetrini CC: , Doug Goldstein , Stefano Stabellini , Julien Grall , Bertrand Marquis , Luca Fancellu References: <20260428080218.19371-1-michal.orzel@amd.com> <2f9875a8a1f4d85ddceccb2d093a4951@bugseng.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <2f9875a8a1f4d85ddceccb2d093a4951@bugseng.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E2:EE_|MW4PR12MB6705:EE_ X-MS-Office365-Filtering-Correlation-Id: 951c3eb8-d989-4d26-7a8c-08dea51001b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: zxCxn9KcpZLXzFhPFguHSDNoqd77NodQsEbqD0dv43MUZEem1P/z8bquExs5Rg+ig5YB3HhGszUL4pe0YEU2qAwVC1qi9VweO1rd/Qx72hSkJ0O9N12wI7G2S5s7Vwgv+fXAW/5T+toLY/j4smYZ/GibbT3JuB3BqnNzmQCIp86vEhvB7mW6c28k2+JXQsbCOvLfUQ2uGaSoPsDPRaozTXoJz7SpASbXbQPknCdaVr227hOzsENu9+rYQk54d0kRK+eAs5JDuaQb1IEv7aJx+NKhACFV1Y88UOpAnlMVHugZ5MWyW1J1omeEto55hBMW8EZJXUSEn3xNVrg+tjc19iohV0bFqsba7HW/thM2gZRPSJ5utTve/slE48VUx1he0FEc4gYKqwP8WWut+2HmixSC9AVu2kiteB2Xxxh0i5hJVln8t6AW//3bxuE49NhJ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 10:22:09.9663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 951c3eb8-d989-4d26-7a8c-08dea51001b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6705 X-purgate-ID: tlsNG-d62444/1777371737-BEE63FF4-3AC72EEB/0/0 X-purgate-type: clean X-purgate-size: 3063 On 28-Apr-26 10:20, Nicola Vetrini wrote: > On 2026-04-28 10:02, Michal Orzel wrote: >> overlay_get_nodes_info() is called before fdt_overlay_apply() to >> extract >> target paths from the overlay. This fails for overlays using >> phandle-based >> targeting (target = <&label>) because DTC compiles these as unresolved >> fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() to >> return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to >> manually modify the dtbo (even for hwdom) to switch from target to >> target-phandle by manually inspecting also the host DTB. >> >> Introduce overlay_get_target_path() which directly handles the two >> targeting cases that occur before fixup resolution: >> - target-path: the string property is returned directly. >> - target = <&label>: the label is found in the overlay's __fixups__ >> node, then resolved to a path via the base DTB's __symbols__ node. >> >> Libfdt fdt_for_each_property_offset() violates MISRA R20.7. Despite >> libfdt being excluded from the analysis, this causes ECLAIR scan to >> report a regression because the violation introduced by a macro is >> reported at the call site. Deviate R20.7 for libfdt.h. >> >> Reviewed-by: Luca Fancellu >> Acked-by: Stefano Stabellini >> Signed-off-by: Michal Orzel >> --- >> In my pre-push testing I realized ECLAIR allcode reported a violation >> related to >> the use of fdt_for_each_property_offset. Libfdt is excluded from >> analysis but >> this does not apply to e.g. macros used in other places. >> >> Changes in v2: >> - strip out from series that is ready to be committed >> - deviate 20.7 for libfdt.h. Discussed with Nicole. >> >> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2484326830 >> --- >> .../eclair_analysis/ECLAIR/deviations.ecl | 1 + >> xen/common/device-tree/dt-overlay.c | 65 +++++++++++++++++-- >> 2 files changed, 60 insertions(+), 6 deletions(-) >> >> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl >> b/automation/eclair_analysis/ECLAIR/deviations.ecl >> index 30c323906924..5f0b73062474 100644 >> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl >> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl >> @@ -631,6 +631,7 @@ not in scope for compliance are allowed, as that is >> imported code." >> -file_tag+={acpi_cpu_idle, "^xen/arch/x86/acpi/cpu_idle\\.c$"} >> -config=MC3A2.R20.7,reports+={safe, >> "any_area(any_loc(file(gnu_efi_include)||any_exp(macro(^NextMemoryDescriptor$))))"} >> -config=MC3A2.R20.7,reports+={safe, >> "any_area(any_loc(file(acpi_cpu_idle)))"} >> +-config=MC3A2.R20.7,reports+={safe, >> "any_area(any_loc(any_exp(file(^xen/include/xen/libfdt/libfdt.h$))))"} >> -doc_end >> > > Nit: I think using a file_tag as above is better, but in any case use > libfdt\\.h in the regex Ok. Provided I will do this on commit, may I convert this as your Rb/Ab? ~Michal From xen-devel-bounces@lists.xenproject.org Tue Apr 28 10:24:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 10:24:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295561.1572221 (Exim 4.92) (envelope-from ) id 1wHfcF-0004DN-2E; Tue, 28 Apr 2026 10:24:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295561.1572221; Tue, 28 Apr 2026 10:24:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfcE-0004DG-Vd; Tue, 28 Apr 2026 10:24:30 +0000 Received: by outflank-mailman (input) for mailman id 1295561; Tue, 28 Apr 2026 10:24:30 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfcE-0004DA-IN for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 10:24:30 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHfcD-00BlCj-VF for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 12:24:29 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f08acf-bab6-0a2a0a5309dd-0a2a4507cf68-38 for ; Tue, 28 Apr 2026 12:24:29 +0200 Received: from [162.55.131.47] (helo=support.bugseng.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f08adc-229c-0a2a45070019-a237832fa512-3 for ; Tue, 28 Apr 2026 12:24:29 +0200 Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) (Authenticated sender: nicola) by support.bugseng.com (Postfix) with ESMTPA id B1CD44EE3D42; Tue, 28 Apr 2026 12:24:27 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: bugseng.com; arc=none smtp.remote-ip=162.55.131.47 ARC-Seal: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; cv=none; t=1777371868; b=CH/97+DsIuWxZW5ffd8fASGrjevShkPy1KzHNkjIcF/ePLTRPZytaWhl+07xsRw8Xdax j1dL22yHLuVz3aZobB2UPfw9J+9JGCfC8qgHYA5/KlhY9b8UXzciEwjcnD4e0KvHTAE9o 3cJoXK+J73lpFBzSr6SbuYtJEv71xL6WOhUHJ9IKj9xVRYj9gKZx9lDVOh5isgxJ+r6y8 5idCWfvrWwc9t0DsLIwU+1nQfw7DQwvI8zMx+HvKIcyaNHpfL3gcVqQDf8naGxIj9l4HR 8blZr4FIR4qLelTcUvi1qIqMpCdHzPswWkWGozeqX9Yc93z66sj9S0eMQVwqdLH7lAr/C macUb715KVK2Mds0dqGmOGsvoSGVqyi5gHpMWQrZ/5dlxNTdnrVxPWgdUZRPgfgq/iwPe R+J8oyd7f1EjAdSATQMI+mjxBehGffLGSLviUZ1r/y4lsiWc59MjjiYvlmUAavcFkBfhu FDHqEBK0SBF7dCjmrM5etH8SFuALf7VGgzwXXshtkki+thlEG757C/cfApllg+Z8bs83f k4rk0uNGru4fsaXXwp1spSCgH5Vd/ARB27Px7mXYUIREWmx2aA5pGhOSjp7UoCsrGdgT8 T8DkxAHtgn8V7X1syfos1B9K4quuPJJEpvcox3Nr8T8U4lg/aQ75cH0H7BlAM5c= ARC-Message-Signature: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; c=relaxed/relaxed; t=1777371868; h=MIME-Version:Date:From:To:Cc:Subject:In-Reply-To:References: Message-ID:X-Sender:Organization:Content-Type: Content-Transfer-Encoding; bh=9Lr+2OIu4LkQzWwjA3WNC/sPDHGHa2sUBFGHqOf9eZ4=; b=4oExtKqj2ENbVPV8EkC5QpoFp8ph5JVLWSpWYDbxj/pb9rXkMmHswtK0V7fcpYZ458ug BDQpECCNs92APFFE64dYR21xFyRxOZyaR4tlPJdTqvr0FvPP7XIq/LS5q4iBMQ1SIjKAs xdoVzlveqaNDpncyE7U1YpChgu+UWSVJGCH1lKmvobAOFRQdv+4FJRYe3T/ciI4qrVS35 H3hUcQot1PLp1V2UJLcdc5jy48BhRZc/oh18dktnI/F4xXAVlnyps9XEGeuYLcpLe8e0C /4QBDgvBQi00FVYdqP66ENA3OhuM5rypDc9SbLwNoeAcR4dtg9ceb4SuPj0ea/UFR7CoW 0eSXJWWICPUWg50YBs71ctbFo78WD9/+foSWb2928sv49ju9KkWnvvFoGEn1nKl5CFHHx kKu8wvRun0qUUg4HLW3QO8iTObuf+Nch+m6A7mvQTFZxYXt4W2lfKWCvyR7zKLbqbklWS P+kl3VzxFTcje0hJ90RnPVN60PGZOpFS/cBEl3EhhrriFuspM4N0A9AaMnZZnbqFhxDae k2RhfuEFOXSHaeSm8VUOJjqH76/BGipcY8iYSAYYa4yL0KY5Ji5TXyvwy8wCPhCnmal2t ZbjcAa+UulErGN1CCFPJgFsPCieQ16FHEzkrXIzH69l1C6CsX1w1euCOIqrXQ3I= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Tue, 28 Apr 2026 12:24:27 +0200 From: Nicola Vetrini To: "Orzel, Michal" Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini , Julien Grall , Bertrand Marquis , Luca Fancellu Subject: Re: [PATCH v2] xen/dt-overlay: support phandle-based targeting in overlay_get_nodes_info In-Reply-To: References: <20260428080218.19371-1-michal.orzel@amd.com> <2f9875a8a1f4d85ddceccb2d093a4951@bugseng.com> Message-ID: X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1777371869-AC762C48-91C0AB94/0/0 X-purgate-type: clean X-purgate-size: 3411 On 2026-04-28 12:22, Orzel, Michal wrote: > On 28-Apr-26 10:20, Nicola Vetrini wrote: >> On 2026-04-28 10:02, Michal Orzel wrote: >>> overlay_get_nodes_info() is called before fdt_overlay_apply() to >>> extract >>> target paths from the overlay. This fails for overlays using >>> phandle-based >>> targeting (target = <&label>) because DTC compiles these as >>> unresolved >>> fixups (target = <0xffffffff>), causing fdt_overlay_target_offset() >>> to >>> return -FDT_ERR_BADPHANDLE. Prior to this change users were forced to >>> manually modify the dtbo (even for hwdom) to switch from target to >>> target-phandle by manually inspecting also the host DTB. >>> >>> Introduce overlay_get_target_path() which directly handles the two >>> targeting cases that occur before fixup resolution: >>> - target-path: the string property is returned directly. >>> - target = <&label>: the label is found in the overlay's __fixups__ >>> node, then resolved to a path via the base DTB's __symbols__ node. >>> >>> Libfdt fdt_for_each_property_offset() violates MISRA R20.7. Despite >>> libfdt being excluded from the analysis, this causes ECLAIR scan to >>> report a regression because the violation introduced by a macro is >>> reported at the call site. Deviate R20.7 for libfdt.h. >>> >>> Reviewed-by: Luca Fancellu >>> Acked-by: Stefano Stabellini >>> Signed-off-by: Michal Orzel >>> --- >>> In my pre-push testing I realized ECLAIR allcode reported a violation >>> related to >>> the use of fdt_for_each_property_offset. Libfdt is excluded from >>> analysis but >>> this does not apply to e.g. macros used in other places. >>> >>> Changes in v2: >>> - strip out from series that is ready to be committed >>> - deviate 20.7 for libfdt.h. Discussed with Nicole. >>> >>> https://gitlab.com/xen-project/people/morzel/xen/-/pipelines/2484326830 >>> --- >>> .../eclair_analysis/ECLAIR/deviations.ecl | 1 + >>> xen/common/device-tree/dt-overlay.c | 65 >>> +++++++++++++++++-- >>> 2 files changed, 60 insertions(+), 6 deletions(-) >>> >>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl >>> b/automation/eclair_analysis/ECLAIR/deviations.ecl >>> index 30c323906924..5f0b73062474 100644 >>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl >>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl >>> @@ -631,6 +631,7 @@ not in scope for compliance are allowed, as that >>> is >>> imported code." >>> -file_tag+={acpi_cpu_idle, "^xen/arch/x86/acpi/cpu_idle\\.c$"} >>> -config=MC3A2.R20.7,reports+={safe, >>> "any_area(any_loc(file(gnu_efi_include)||any_exp(macro(^NextMemoryDescriptor$))))"} >>> -config=MC3A2.R20.7,reports+={safe, >>> "any_area(any_loc(file(acpi_cpu_idle)))"} >>> +-config=MC3A2.R20.7,reports+={safe, >>> "any_area(any_loc(any_exp(file(^xen/include/xen/libfdt/libfdt.h$))))"} >>> -doc_end >>> >> >> Nit: I think using a file_tag as above is better, but in any case use >> libfdt\\.h in the regex > Ok. Provided I will do this on commit, may I convert this as your > Rb/Ab? > > ~Michal Yes, sure Reviewed-by: Nicola Vetrini -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 10:39:37 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 10:39:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295571.1572230 (Exim 4.92) (envelope-from ) id 1wHfqb-0006Ke-85; Tue, 28 Apr 2026 10:39:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295571.1572230; Tue, 28 Apr 2026 10:39:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfqb-0006KX-5D; Tue, 28 Apr 2026 10:39:21 +0000 Received: by outflank-mailman (input) for mailman id 1295571; Tue, 28 Apr 2026 10:39:20 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHfqZ-0006KR-VB for xen-devel@lists.xenproject.org; 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Possible values are > MACHINE_TYPE_I440 and MACHINE_TYPE_Q35 and stored in the global variable > machine_type. > > The machine_type variable will be used from multiple places in following > commits. Is this initialization something that OVMF or SeaBIOS also does? (maybe not for Xen ATM) Asking myself because as said earlier we want to possibly get rid of hvmloader, plus we will want ECAM support in PVH at some point. > Signed-off-by: Alexey Gerasimenko Same as previous patch, if the first SoB is from Alexey the From: (patch author) should also match. > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/hvmloader.c | 2 ++ > tools/firmware/hvmloader/pci_regs.h | 4 +++ > tools/firmware/hvmloader/util.c | 42 ++++++++++++++++++++++++++++ > tools/firmware/hvmloader/util.h | 11 ++++++++ > 4 files changed, 59 insertions(+) > > diff --git a/tools/firmware/hvmloader/hvmloader.c b/tools/firmware/hvmloader/hvmloader.c > index 6d23150fc9..626cc53649 100644 > --- a/tools/firmware/hvmloader/hvmloader.c > +++ b/tools/firmware/hvmloader/hvmloader.c > @@ -332,6 +332,8 @@ int main(void) > > init_hypercalls(); > > + init_pc_machine_type(); > + > memory_map_setup(); > > xenbus_setup(); > diff --git a/tools/firmware/hvmloader/pci_regs.h b/tools/firmware/hvmloader/pci_regs.h > index 7bf2d873ab..4d4dc0cd01 100644 > --- a/tools/firmware/hvmloader/pci_regs.h > +++ b/tools/firmware/hvmloader/pci_regs.h > @@ -107,6 +107,10 @@ > > #define PCI_INTEL_OPREGION 0xfc /* 4 bits */ > > +#define PCI_VENDOR_ID_INTEL 0x8086 > +#define PCI_DEVICE_ID_INTEL_82441 0x1237 > +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 In Xen we have a separate file for vendor and device IDs, called pci_ids.h. Maybe it would be better to use a similar approach in hvmloader, and keep pci_regs.h only containing PCI register offsets. > + > #endif /* __HVMLOADER_PCI_REGS_H__ */ > > /* > diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c > index f1ed1eb48d..f9116bea4d 100644 > --- a/tools/firmware/hvmloader/util.c > +++ b/tools/firmware/hvmloader/util.c > @@ -22,6 +22,7 @@ > #include "hypercall.h" > #include "ctype.h" > #include "vnuma.h" > +#include "pci_regs.h" > #include > #include > #include > @@ -648,6 +649,47 @@ void __bug(const char *file, int line) > crash(); > } > > +machine_type_t machine_type; > + > +void init_pc_machine_type(void) Since detection is done based on PCI device IDs, it might be better placed in pci.c, and so you don't need to include pci_regs.h in util.c. > +{ > + uint16_t vendor_id; > + uint16_t device_id; > + > + if ( machine_type != MACHINE_TYPE_UNDEFINED ) > + return; > + > + vendor_id = pci_readw(0, PCI_VENDOR_ID); > + device_id = pci_readw(0, PCI_DEVICE_ID); > + > + /* only Intel platforms are emulated currently */ > + if ( vendor_id != PCI_VENDOR_ID_INTEL ) > + goto error; > + > + switch ( device_id ) > + { > + case PCI_DEVICE_ID_INTEL_82441: > + machine_type = MACHINE_TYPE_I440; > + printf("Detected i440 chipset\n"); > + break; > + > + case PCI_DEVICE_ID_INTEL_Q35_MCH: > + machine_type = MACHINE_TYPE_Q35; > + printf("Detected Q35 chipset\n"); > + break; > + > + default: > + goto error; > + } > + > + return; > + > +error: > + printf("Unknown emulated chipset encountered, VID=%04Xh, DID=%04Xh\n", We don't usually use the h suffix in hex numbers in hvmloader, it's more common to prefix them with 0x, so I would recommend to use the %#06x formatter instead. Thanks, Roger. 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Modify acpi_enable_sci() function to support both i440 and Q35 > emulation. > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande Reviewed-by: Roger Pau Monné It's not great to add more stuff into hvmloader when we want to move out of it, but it's also not helpful to tie the Q35 addition to the removal of hvmloader. > --- > tools/firmware/hvmloader/hvmloader.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/tools/firmware/hvmloader/hvmloader.c b/tools/firmware/hvmloader/hvmloader.c > index 626cc53649..f6cc3fa4b9 100644 > --- a/tools/firmware/hvmloader/hvmloader.c > +++ b/tools/firmware/hvmloader/hvmloader.c > @@ -258,9 +258,24 @@ static const struct bios_config *detect_bios(void) > static void acpi_enable_sci(void) > { > uint8_t pm1a_cnt_val; > + uint8_t acpi_enable_val; > > -#define PIIX4_SMI_CMD_IOPORT 0xb2 > +#define SMI_CMD_IOPORT 0xb2 > #define PIIX4_ACPI_ENABLE 0xf1 > +#define ICH9_ACPI_ENABLE 0x02 > + > + switch ( machine_type ) > + { > + case MACHINE_TYPE_Q35: > + acpi_enable_val = ICH9_ACPI_ENABLE; > + break; > + case MACHINE_TYPE_I440: > + acpi_enable_val = PIIX4_ACPI_ENABLE; > + break; We might want to add a newline after the break statements. Thanks, Roger. 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The machine_type global variable is used > to select a proper table (i440/q35). > > As we are bound to the qemu-xen device model for Q35, there is no need > to initialize config->dsdt_15cpu/config->dsdt_15cpu_len fields. > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/util.c | 17 +++++++++++++++-- > tools/firmware/hvmloader/util.h | 2 ++ > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c > index f9116bea4d..45519ea583 100644 > --- a/tools/firmware/hvmloader/util.c > +++ b/tools/firmware/hvmloader/util.c > @@ -885,8 +885,21 @@ void hvmloader_acpi_build_tables(struct acpi_config *config, > s = xenstore_read("platform/device-model", ""); > if ( !strncmp(s, "qemu_xen", 9) ) Tying Q35 to xenstore seems a bit sub-optimal, as Q35 detection is done purely from the PCI config space. It would be better if we could avoid relying on the xenstore node, and hence also fixup at least ovmf_acpi_build_tables() and seabios_acpi_build_tables() to use the Q35 ACPI tables when Q35 is detected, regardless of the device-model xenstore node. > { > - config->dsdt_anycpu = dsdt_i440_anycpu_qemu_xen; > - config->dsdt_anycpu_len = dsdt_i440_anycpu_qemu_xen_len; > + switch ( machine_type ) > + { > + case MACHINE_TYPE_Q35: > + config->dsdt_anycpu = dsdt_q35_anycpu_qemu_xen; > + config->dsdt_anycpu_len = dsdt_q35_anycpu_qemu_xen_len; > + break; > + case MACHINE_TYPE_I440: > + config->dsdt_anycpu = dsdt_i440_anycpu_qemu_xen; > + config->dsdt_anycpu_len = dsdt_i440_anycpu_qemu_xen_len; > + break; > + default: > + /* Not likely to happen */ > + BUG(); > + } > + > config->dsdt_15cpu = NULL; > config->dsdt_15cpu_len = 0; > } > diff --git a/tools/firmware/hvmloader/util.h b/tools/firmware/hvmloader/util.h > index 2f37504aca..4641ca0c46 100644 > --- a/tools/firmware/hvmloader/util.h > +++ b/tools/firmware/hvmloader/util.h > @@ -393,7 +393,9 @@ bool check_overlap(uint64_t start, uint64_t size, > uint64_t reserved_start, uint64_t reserved_size); > > extern const unsigned char dsdt_i440_anycpu_qemu_xen[], dsdt_anycpu[], dsdt_15cpu[]; > +extern const unsigned char dsdt_q35_anycpu_qemu_xen[]; If I'm not mistaken, patch 2 introduces the dsdt_q35_anycpu_qemu_xen symbol to the hvmloader build, so that you can reference it here? At first I was going to comment that you are referencing a symbol not included in the patch, but I think such symbol was previously added to the build in patch 2 (and was unused there). > extern const int dsdt_i440_anycpu_qemu_xen_len, dsdt_anycpu_len, dsdt_15cpu_len; > +extern const int dsdt_q35_anycpu_qemu_xen_len; unsigned int would be better here. Thanks, Roger. From xen-devel-bounces@lists.xenproject.org Tue Apr 28 11:23:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 11:23:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295605.1572257 (Exim 4.92) (envelope-from ) id 1wHgWz-0006DF-Vp; Tue, 28 Apr 2026 11:23:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295605.1572257; Tue, 28 Apr 2026 11:23:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHgWz-0006D8-TA; Tue, 28 Apr 2026 11:23:09 +0000 Received: by outflank-mailman (input) for mailman id 1295605; Tue, 28 Apr 2026 11:21:23 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHgVH-00066P-1b for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 11:21:23 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHgVG-00FmF0-DT for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 13:21:22 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f09831-5cb7-0a2a0a5109dd-0a2a4507c0de-0 for ; Tue, 28 Apr 2026 13:21:21 +0200 Received: from [63.228.1.57] (helo=gate.crashing.org) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f09830-229c-0a2a45070019-3fe40139b344-1 for ; Tue, 28 Apr 2026 13:21:20 +0200 Received: from gate.crashing.org (localhost [127.0.0.1]) by gate.crashing.org (8.18.1/8.18.1/Debian-2) with ESMTP id 63SBKIxF1057213; Tue, 28 Apr 2026 06:20:18 -0500 Received: (from segher@localhost) by gate.crashing.org (8.18.1/8.18.1/Submit) id 63SBKHXo1057211; Tue, 28 Apr 2026 06:20:17 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Tue, 28 Apr 2026 06:20:17 -0500 From: Segher Boessenkool To: Yury Norov Cc: Linus Torvalds , "Christophe Leroy (CS GROUP)" , Andrew Morton , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@vger.kernel.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() Message-ID: References: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> <63a4d0f6-0eb3-48cd-9f98-bf7b223b2606@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-purgate-ID: tlsNG-ef75cf/1777375281-AF57BC48-53D8024A/0/0 X-purgate-type: clean X-purgate-size: 1592 Hi! On Mon, Apr 27, 2026 at 06:30:16PM -0400, Yury Norov wrote: > On Mon, Apr 27, 2026 at 02:52:05PM -0700, Linus Torvalds wrote: > > On Mon, 27 Apr 2026 at 12:19, Yury Norov wrote: > > > > > > This is what Linus said when added x86 implementation for copy_from_user() > > > in c512c69187197: > > > > Note that some things have happily changed in the six+ years since... > > > > > That's partly because we have no current users of it, but also partly > > > because the copy_from_user() case is slightly different and cannot > > > efficiently be implemented in terms of a unsafe_get_user() loop (because > > > gcc can't do asm goto with outputs). > > > > now everybody can do asm goto with outputs. > > > > Yes, it's disabled on older versions, so it's not *always* available, > > but all modern versions do it. And if you care about performance, you > > won't be using an old compiler. > > The minimal GCC version is 8.1, and asm goto with outputs is supported > since GCC-11. That would brake the build, if we just switch to using it > without "CC_IS_GCC && (GCC_VERSION >= 110100)" guard. > > Is it worth to maintain 2 version of the function? I don't know... GCC 11 was released five years and a day ago. The last GCC 11 release (that of 11.5) is not even two years ago though (but there will be no more!) So it would be not conservative at all to require GCC 11 as minimum now, some people might even call it a bit aggressive. But in a year (or maybe two) the lay of the land will be rather different. Segher From xen-devel-bounces@lists.xenproject.org Tue Apr 28 11:34:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 11:34:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295616.1572267 (Exim 4.92) (envelope-from ) id 1wHgi6-00084e-VO; Tue, 28 Apr 2026 11:34:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295616.1572267; Tue, 28 Apr 2026 11:34:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHgi6-00084X-Sh; Tue, 28 Apr 2026 11:34:38 +0000 Received: by outflank-mailman (input) for mailman id 1295616; Tue, 28 Apr 2026 11:34:38 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHgi6-00084R-2T for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 11:34:38 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHgi5-001Sf9-EX for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 13:34:37 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f09b49-bab6-0a2a0a5309dd-0a2a4502d562-10 for ; Tue, 28 Apr 2026 13:34:37 +0200 Received: from [63.228.1.57] (helo=gate.crashing.org) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f09b4c-af86-0a2a45020019-3fe401398880-1 for ; Tue, 28 Apr 2026 13:34:37 +0200 Received: from gate.crashing.org (localhost [127.0.0.1]) by gate.crashing.org (8.18.1/8.18.1/Debian-2) with ESMTP id 63SBY0U31059939; Tue, 28 Apr 2026 06:34:00 -0500 Received: (from segher@localhost) by gate.crashing.org (8.18.1/8.18.1/Submit) id 63SBY0B51059937; Tue, 28 Apr 2026 06:34:00 -0500 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Tue, 28 Apr 2026 06:34:00 -0500 From: Segher Boessenkool To: Andrew Cooper Cc: Yury Norov , "Christophe Leroy (CS GROUP)" , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, Yury Norov , linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@vger.kernel.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 2/9] uaccess: Convert INLINE_COPY_{TO/FROM}_USER to kconfig and reduce ifdefery Message-ID: References: <9fe875d2f55af59c12708336c571a46038528678.1777306795.git.chleroy@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-purgate-ID: tlsNG-720697/1777376077-8A0C7161-EBEE8F5C/0/0 X-purgate-type: clean X-purgate-size: 942 On Mon, Apr 27, 2026 at 09:39:33PM +0100, Andrew Cooper wrote: > On 27/04/2026 7:39 pm, Yury Norov wrote: > > On Mon, Apr 27, 2026 at 07:13:43PM +0200, Christophe Leroy (CS GROUP) wrote: > >> Among the 21 architectures supported by the kernel, 16 define both > >> INLINE_COPY_TO_USER and INLINE_COPY_FROM_USER while the 5 other ones > >> don't define any of the two. > >> > >> To simplify and reduce risk of mistakes, convert them to a single > >> kconfig item named CONFIG_ARCH_WANTS_NOINLINE_COPY which will be > > We've got a special word for it: outline. Can you name it > > CONFIG_OUTLINE_USERCOPY, or similar? > > You can't swap the "in" for "out" like this. "out of line" is the > opposite of "inline" in this context, while "outline" means something > different and unrelated. Yeah. Technically much more correct for it is inline vs. functional. Not that that term won't be misunderstood as well :-) Segher From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:00:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:00:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295631.1572276 (Exim 4.92) (envelope-from ) id 1wHh6y-0003uz-2j; Tue, 28 Apr 2026 12:00:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295631.1572276; Tue, 28 Apr 2026 12:00:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHh6x-0003us-VG; Tue, 28 Apr 2026 12:00:19 +0000 Received: by outflank-mailman (input) for mailman id 1295631; Tue, 28 Apr 2026 12:00:18 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHh6w-0003ui-4X for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 12:00:18 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHh6v-0085f6-GT for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:00:17 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0a151-2eae-0a2a0a5409dd-0a2a45068db6-0 for ; Tue, 28 Apr 2026 14:00:17 +0200 Received: from [209.85.167.54] (helo=mail-lf1-f54.google.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0a151-7371-0a2a45060019-d155a736e54b-3 for ; Tue, 28 Apr 2026 14:00:17 +0200 Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-5a2b636b944so15909019e87.1 for ; Tue, 28 Apr 2026 05:00:17 -0700 (PDT) Received: from EPUAKYIW02F7.. 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Per IHI0048B.b section 2.3.1, clearing the architected bypass-disable bits selects bypass rather than deasserted interrupt outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully disabling the interface. Fix this by reading GICC_CTLR, then setting the bypass-disable bits and clearing the group-enable bits that are architecturally defined for the current GICC_CTLR view before writing the value back. When Security Extensions are implemented Xen accesses the Non-secure copy of GICC_CTLR, where IRQBypDisGrp1 and FIQBypDisGrp1 are at bits [6:5] and bits [8:7] are reserved. Without Security Extensions there is no separate Secure/Non-secure CPU interface view, so disabling both group-enable bits affects the shared interface state. This is still appropriate for the CPU shutdown path, which is expected to stop normal interrupt delivery through the interface and rely only on the architecturally separate wakeup event signaling. Section 2.3.2 also states that wakeup event signals remain available even when both GIC interrupt signaling and interrupt bypass are disabled, so disabling bypass does not break the power-management use case, i.e. suspend modes. Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") Signed-off-by: Mykola Kvach --- Changes in v2: - derive the shutdown masks from the active GICC_CTLR layout - use the Non-secure GICC_CTLR layout when GICD_TYPER.SecurityExtn is set - stop writing reserved bits [8:7] on Security Extensions systems --- xen/arch/arm/gic-v2.c | 16 +++++++++++++++- xen/arch/arm/include/asm/gic.h | 25 +++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 014f955967..241c1ff5c5 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -408,7 +408,21 @@ static void gicv2_cpu_init(void) static void gicv2_cpu_disable(void) { - writel_gicc(0x0, GICC_CTLR); + uint32_t ctlr = readl_gicc(GICC_CTLR); + + if ( readl_gicd(GICD_TYPER) & GICD_TYPE_SEC ) + { + ctlr |= GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK; + ctlr &= ~GICC_CTL_ENABLE; + } + else + { + ctlr |= GICC_CTLR_BYPASS_DISABLE_GRP0_MASK | + GICC_CTLR_BYPASS_DISABLE_GRP1_MASK; + ctlr &= ~(GICC_CTL_ENABLE | GICC_CTL_ENABLE_GRP1); + } + + writel_gicc(ctlr, GICC_CTLR); } static void gicv2_hyp_init(void) diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 8e713aa477..ff22dea40d 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -102,8 +102,29 @@ #define GICD_TYPE_SEC 0x400 #define GICD_TYPER_DVIS (1U << 18) -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) +/* + * Xen runs in the Non-secure world. When Security Extensions are present, + * Xen accesses the Non-secure GICC_CTLR view, where bit[0] is EnableGrp1 + * and bits[6:5] are the Group 1 bypass-disable bits. Otherwise Xen sees the + * common GICC_CTLR layout, where bit[0] is EnableGrp0, bit[1] is EnableGrp1, + * bits[6:5] are the Group 0 bypass-disable bits, and bits[8:7] are the + * Group 1 bypass-disable bits. + */ +#define GICC_CTL_ENABLE (0x1 << 0) +#define GICC_CTL_ENABLE_GRP1 (0x1 << 1) +#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5) +#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6) +#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7) +#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8) + +#define GICC_CTLR_BYPASS_DISABLE_GRP0_MASK \ + (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0) +#define GICC_CTLR_BYPASS_DISABLE_GRP1_MASK \ + (GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1) +#define GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK \ + GICC_CTLR_BYPASS_DISABLE_GRP0_MASK + +#define GICC_CTL_EOI (0x1 << 9) #define GICC_IA_IRQ 0x03ff #define GICC_IA_CPU_MASK 0x1c00 -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:01:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:01:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295643.1572300 (Exim 4.92) (envelope-from ) id 1wHh8L-0004j4-K7; Tue, 28 Apr 2026 12:01:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1295643.1572300; Tue, 28 Apr 2026 12:01:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHh8L-0004iv-GY; Tue, 28 Apr 2026 12:01:45 +0000 Received: by outflank-mailman (input) for mailman id 1295643; Tue, 28 Apr 2026 12:01:43 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHh8J-0004QY-5G; Tue, 28 Apr 2026 12:01:43 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHh8I-004jWr-H2; Tue, 28 Apr 2026 14:01:42 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0a1a5-e002-0a2a0a5209dd-0a2a4501852e-6 for ; Tue, 28 Apr 2026 14:01:42 +0200 Received: from [104.130.215.37] (helo=mail.xenproject.org) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0a1a5-c1f2-0a2a45010019-6882d725b590-3 for ; Tue, 28 Apr 2026 14:01:42 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHh88-0064Zb-09; Tue, 28 Apr 2026 12:01:32 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wHh87-006n03-3A; Tue, 28 Apr 2026 12:01:31 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 483 v2 (CVE-2026-23556) - oxenstored keeps quota related use counts across domain destruction Message-Id: Date: Tue, 28 Apr 2026 12:01:31 +0000 X-purgate-ID: tlsNG-d62444/1777377702-BDA69FF4-96C8E755/0/0 X-purgate-type: clean X-purgate-size: 8700 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-23556 / XSA-483 version 2 oxenstored keeps quota related use counts across domain destruction UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= When oxenstored is tearing a domain down, the node data is cleaned up but the usage counts are leaked. When the domain ID is eventually reused, the new domain can create fewer nodes before beeing deemed to be over quota. IMPACT ====== Over an extended period of time, new domains will be able to create fewer and fewer nodes in xenstored, until they are eventually unable to operate at all. A buggy or malicious domain can speed this process up by deliberately hitting it's quota, and then rebooting. VULNERABLE SYSTEMS ================== All versions of Xen containing the XSA-419 fixes are vulnerable. Only systems configured to use oxenstored (Ocaml xenstored) are vulnerable. Systems configured to xenstored (C xenstored) are not vulnerable. MITIGATION ========== Performing a xenstore live update mitigates the issue. CREDITS ======= This issue was discovered by Andrii Sultanov of Vates. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa483.patch xen-unstable - Xen 4.18.x xsa483-4.17.patch Xen 4.17.x xsa483-xapi.patch XAPI oxenstored $ sha256sum xsa483* 4be3acc57dcd5e2719cab165729879757a1915c33b848a37623dd4a5f1157746 xsa483.patch 389b0411d855894adff6f640dcbd3358adc6d4cb9ddeedbcb9cb2c345af67d51 xsa483-4.17.patch ec191a1e158eddd22bfbd764f26f6b6a0b75b9fe0a223dc66da1c4a16ef73122 xsa483-xapi.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 28 Apr 2026 14:01:46 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHh8D-0064Zp-2a; Tue, 28 Apr 2026 12:01:37 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wHh8D-006n15-2O; Tue, 28 Apr 2026 12:01:37 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 484 v2 (CVE-2026-23557) - Xenstored DoS via XS_RESET_WATCHES command Message-Id: Date: Tue, 28 Apr 2026 12:01:37 +0000 X-purgate-ID: tlsNG-720697/1777377706-8256B161-7610114D/0/0 X-purgate-type: clean X-purgate-size: 11272 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-23557 / XSA-484 version 2 Xenstored DoS via XS_RESET_WATCHES command UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= Any guest can cause xenstored to crash by issuing a XS_RESET_WATCHES command within a transaction due to an assert() triggering. In case xenstored was built with NDEBUG #defined nothing bad will happen, as assert() is doing nothing in this case. Note that the default is not to define NDEBUG for xenstored builds even in release builds of Xen. IMPACT ====== Any unprivileged domain can cause xenstored to crash, causing a DoS (denial of service) for any Xenstore action. This will result in an inability to perform further domain administration on the host. VULNERABLE SYSTEMS ================== All Xen systems from Xen 4.2 onwards are vulnerable. Systems up to Xen 4.1 are not vulnerable. Systems using the C variant of xenstored or xenstore-stubdom built without NDEBUG are vulnerable. Systems using the OCaml variant of Xenstore (oxenstored), or the C variant (xenstored or xenstore-stubdom) built with NDEBUG defined are not vulnerable. MITIGATION ========== There is no known mitigation available. CREDITS ======= This issue was discovered by Andrii Sultanov of Vates. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa484.patch xen-unstable - Xen 4.18.x xsa484-4.17.patch Xen 4.17.x $ sha256sum xsa484* 77c489191d40acd807eb19344a0e1bbb67a04551e89aff726fbb2006f235aacf xsa484.patch 6c8d8146d136956c59ee77da6aa6340272d1ea670a6b0d9cf37fe759d4b96b19 xsa484-4.17.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 28 Apr 2026 14:01:49 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHh8H-0064a6-2y; Tue, 28 Apr 2026 12:01:41 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wHh8H-006n23-2q; Tue, 28 Apr 2026 12:01:41 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 485 v2 (CVE-2026-31786) - Linux kernel out of bounds read via Xen-related sysfs file Message-Id: Date: Tue, 28 Apr 2026 12:01:41 +0000 X-purgate-ID: tlsNG-c1860d/1777377709-38D63DB1-A0E3543C/0/0 X-purgate-type: clean X-purgate-size: 6361 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-31786 / XSA-485 version 2 Linux kernel out of bounds read via Xen-related sysfs file UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= The Linux sysfs file /sys/hypervisor/properties/buildid does not contain printable information, but a binary value of typically 16 or 20 bytes, which is not terminated by a zero byte. The kernel driver making this information available is using the sprintf() function for writing the data into the user readable buffer, resulting in a potential out of bounds read past the buildid retrieved from the Xen hypervisor. In rare cases even writing past the sysfs buffer of 4kB might happen, if no zero byte is found in the 4kB of data following the start of the buildid. This might result in users being capable to read kernel secrets or even overwrite kernel memory located after the sysfs buffer. IMPACT ====== Inside any Linux Xen domain information leaks, Denial of Service (DoS) and privilege escalation might be possible. VULNERABLE SYSTEMS ================== All Linux domains with a kernel version 4.13 or later are vulnerable. Domains up to kernel version 4.12 are not vulnerable. MITIGATION ========== There is no known mitigation available. CREDITS ======= This issue was discovered by Frediano Ziglio of XenServer. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. xsa485-linux.patch Linux $ sha256sum xsa485* c70b792093d7b314b8c476e39df88a62a2d98fb0efc6328590d0ad3266c77831 xsa485-linux.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of patches or mitigations is NOT permitted (except where all the affected systems and VMs are administered and used only by organisations which are members of the Xen Project Security Issues Predisclosure List). Specifically, deployment on public cloud systems is NOT permitted. This is because the patch needs to be applied to the guests. Deployment is permitted only AFTER the embargo ends. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 28 Apr 2026 14:01:57 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHh8N-0064aR-0U; Tue, 28 Apr 2026 12:01:47 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wHh8N-006n3C-0N; Tue, 28 Apr 2026 12:01:47 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 486 v2 (CVE-2026-23558) - grant table v2 race in status page mapping Message-Id: Date: Tue, 28 Apr 2026 12:01:47 +0000 X-purgate-ID: tlsNG-ebf023/1777377718-3144B3FF-30DF8368/0/0 X-purgate-type: clean X-purgate-size: 20327 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-23558 / XSA-486 version 2 grant table v2 race in status page mapping UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= The adjustments made for XSA-379 as well as those subsequently becoming XSA-387 still left a race window, when a HVM or PVH guest does a grant table version change from v2 to v1 in parallel with mapping the status page(s) via XENMEM_add_to_physmap. Some of the status pages may then be freed while mappings of them would still be inserted into the guest's secondary (P2M) page tables. IMPACT ====== Privilege escalation, information leaks, and Denial of Service (DoS) up to affecting the entire host cannot be excluded. VULNERABLE SYSTEMS ================== All Xen versions from 4.0 onwards are affected. Xen versions 3.4 and older are not affected. Only x86 HVM and PVH guests permitted to use grant table version 2 interfaces can leverage this vulnerability. x86 PV guests cannot leverage this vulnerability. On Arm, grant table v2 use is explicitly unsupported. MITIGATION ========== Using the "gnttab=max-ver:1" hypervisor command line option will avoid the vulnerability. Using the "max_grant_version=1" guest configuration option for HVM and PVH guests will also avoid the vulnerability. CREDITS ======= This issue was discovered by Claude Opus 4.6 and diagnosed as a security issue by Rafal Wojtczuk. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa486.patch xen-unstable - Xen 4.19.x xsa486-4.18.patch Xen 4.18.x - Xen 4.17.x $ sha256sum xsa486* 0bc1336f0d8de463e30a920bb900b0199a79b4cc19af72e64cfb60504fa6599d xsa486.patch 3fa23326a2761eba62e661fa052c1cd6b69041ea6752ed573ab240ebcdffedf8 xsa486-4.18.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches described above (or others which are substantially similar) is permitted during the embargo, even on public- facing systems with untrusted guest users and administrators. HOWEVER, deployment of the mitigation is NOT permitted (except where all the affected systems and VMs are administered and used only by organisations which are members of the Xen Project Security Issues Predisclosure List). Specifically, deployment on public cloud systems is NOT permitted. This is because restricting the available grant table version is a guest visible configuration change, which may lead to re-discovery of the issue. Deployment of this mitigation is permitted only AFTER the embargo ends. AND: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) For more information about permissible uses of embargoed information, consult the Xen Project community's agreed Security Policy: http://www.xenproject.org/security-policy.html -----BEGIN PGP SIGNATURE----- iQFABAEBCAAqFiEEI+MiLBRfRHX6gGCng/4UyVfoK9kFAmnwoQMMHHBncEB4ZW4u b3JnAAoJEIP+FMlX6CvZKXgH/1/L4sRCjLuuwnugfhgcfYdOwFfWEsBGhxsuYTHT 61mqh8Ft4asiPf0qSUJzcWCpfKCB8aGBAEWDj7Hle+yAgYZ22Inf4j2emfcehXiu hkKJ+2VgYs0C4xK1mOrPysxXha9pbyNvEHBJP794QitUYIzuJzeNAcKPmzR10rZ3 jEpyLC41sGiftIB/jq579Mrvz2cp02l2L77+zeWogl7ZMLPs+GbRoF1chTrIo9DU Rt9WJnF7hD+elk280nwO2N6OCgrEVRmSR6AjsGb3E6JGUmZYJ6ZTtEaV+2TBiCXH rfrJGwftJLp6a54RRDPjK709itzppJGPG/ur2rrIRxenRcY= =1e9B -----END PGP SIGNATURE----- --=separator Content-Type: application/octet-stream; name="xsa486.patch" Content-Disposition: attachment; filename="xsa486.patch" Content-Transfer-Encoding: base64 RnJvbTogSmFuIEJldWxpY2ggPGpiZXVsaWNoQHN1c2UuY29tPgpTdWJqZWN0 OiBnbnR0YWI6IHNwbGl0IGdudHRhYl9tYXBfZnJhbWUoKQoKSWYgYSBkb21h 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Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 487 v2 (CVE-2026-31787) - Linux kernel double free in Xen privcmd driver Message-Id: Date: Tue, 28 Apr 2026 12:01:52 +0000 X-purgate-ID: tlsNG-4011c0/1777377719-46D708B7-2E2A13BD/0/0 X-purgate-type: clean X-purgate-size: 6117 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-31787 / XSA-487 version 2 Linux kernel double free in Xen privcmd driver UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= The Linux kernel's privcmd driver can be abused to circumvent kernel lockdown (secure boot) by causing a double free of kernel memory. Note that this operation can be performed by root only, so any further impact on the system (like denial of service) is not security relevant. IMPACT ====== An administrator of a domain booted in secure mode is able to perform actions on the kernel which should not be possible in secure mode. VULNERABLE SYSTEMS ================== Linux PVH or HVM domains (x86 or Arm) from kernel 3.8 onwards are vulnerable. PV domains or non-Linux domains are not vulnerable. MITIGATION ========== There is no mitigation available. CREDITS ======= This issue was discovered by Atharva Vartak (@0xAth4rv). RESOLUTION ========== Applying the attached patch resolves this issue. xsa487-linux.patch Linux $ sha256sum xsa487* fc7ccf9697203c14ced4364d70175b463b08a17a7559fd8654a12b623b54e5bb xsa487-linux.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of patches or mitigations is NOT permitted (except where all the affected systems and VMs are administered and used only by organisations which are members of the Xen Project Security Issues Predisclosure List). Specifically, deployment on public cloud systems is NOT permitted. This is because the patch needs to be applied to the guest. Deployment is permitted only AFTER the embargo ends. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) For more information about permissible uses of embargoed information, consult the Xen Project community's agreed Security Policy: http://www.xenproject.org/security-policy.html -----BEGIN PGP SIGNATURE----- iQFABAEBCAAqFiEEI+MiLBRfRHX6gGCng/4UyVfoK9kFAmnwoQUMHHBncEB4ZW4u b3JnAAoJEIP+FMlX6CvZKRkH/A2DLI9IzMFrmuzksitp7G+MD/AWq3jJe93IAeU1 /QguHV7pQXFyhb1zWR/+DB4zt5tAcGIs75enob8njm3HZ/e5Ht6aSlYq+Rl5ZO6w kK4aUljpRUxPTOg/PHPKn2sTkZccQxXGxmara5PwhZf0uXb0BBB33dhWbkxQoAR/ FzHSFNHvJKZct/fmmavE38R4AVel0GC3Ufi1jQ44l85xBWtmWN4+ioEno4tDqKkk d9fmRfCoPta2zCL8DezC3y/LC7x8bbLeL1CMFchnVW+JjJOON22K2R/12dvBFUOF If+HuBOHviA02fDW86H+sKTn/KnCI1jNjgUto9tCIkdyvSI= =NY86 -----END PGP SIGNATURE----- --=separator Content-Type: application/octet-stream; name="xsa487-linux.patch" Content-Disposition: attachment; filename="xsa487-linux.patch" Content-Transfer-Encoding: base64 RnJvbSA1NTc3YzAwMzAxOGFiYjFhZDkyZGM0MDMyY2M3MWIxNzE4YTgzZGZh IE1vbiBTZXAgMTcgMDA6MDA6MDAgMjAwMQpGcm9tOiBKdWVyZ2VuIEdyb3Nz IDxqZ3Jvc3NAc3VzZS5jb20+CkRhdGU6IEZyaSwgMTAgQXByIDIwMjYgMDk6 MjA6MDQgKzAyMDAKU3ViamVjdDogW1BBVENIXSB4ZW4vcHJpdmNtZDogZml4 IGRvdWJsZSBmcmVlIHZpYSBWTUEgc3BsaXR0aW5nCgpwcml2Y21kX3ZtX29w cyBkZWZpbmVzIC5jbG9zZSAocHJpdmNtZF9jbG9zZSksIGJ1dCBuZWl0aGVy IC5tYXlfc3BsaXQKbm9yIC5vcGVuLiBXaGVuIHVzZXJzcGFjZSBkb2VzIGEg cGFydGlhbCBtdW5tYXAoKSBvbiBhIHByaXZjbWQgbWFwcGluZywKdGhlIGtl cm5lbCBzcGxpdHMgdGhlIFZNQSB2aWEgX19zcGxpdF92bWEoKS4gU2luY2Ug bWF5X3NwbGl0IGlzIE5VTEwsCnRoZSBzcGxpdCBpcyBhbGxvd2VkLiB2bV9h cmVhX2R1cCgpIGNvcGllcyB2bV9wcml2YXRlX2RhdGEgKGEgcGFnZXMKYXJy YXkgYWxsb2NhdGVkIGluIGFsbG9jX2VtcHR5X3BhZ2VzKCkpIGludG8gdGhl IG5ldyBWTUEgd2l0aG91dCBhbnkKZml4dXAsIGJlY2F1c2UgdGhlcmUgaXMg bm8gLm9wZW4gY2FsbGJhY2suCgpCb3RoIFZNQXMgbm93IHBvaW50IHRvIHRo ZSBzYW1lIHBhZ2VzIGFycmF5LiBXaGVuIHRoZSB1bm1hcHBlZCBwb3J0aW9u CmlzIGNsb3NlZCwgcHJpdmNtZF9jbG9zZSgpIGNhbGxzOgogICAgLSB4ZW5f dW5tYXBfZG9tYWluX2dmbl9yYW5nZSgpCiAgICAtIHhlbl9mcmVlX3VucG9w dWxhdGVkX3BhZ2VzKCkKICAgIC0ga3ZmcmVlKHBhZ2VzKQoKVGhlIHN1cnZp dmluZyBWTUEgc3RpbGwgaG9sZHMgdGhlIGRhbmdsaW5nIHBvaW50ZXIuIFdo ZW4gaXQgaXMgbGF0ZXIKZGVzdHJveWVkLCB0aGUgc2FtZSBzZXF1ZW5jZSBy dW5zIGFnYWluLCB3aGljaCBsZWFkcyB0byBhIGRvdWJsZSBmcmVlLgoKRml4 IHRoaXMgaXNzdWUgYnkgYWRkaW5nIGEgLm1heV9zcGxpdCBjYWxsYmFjayBk ZW55aW5nIHRoZSBWTUEgc3BsaXQuCgpUaGlzIGlzIFhTQS00ODcgLyBDVkUt MjAyNi0zMTc4NwoKRml4ZXM6IGQ3MWY1MTM5ODVjMiAoInhlbjogcHJpdmNt ZDogc3VwcG9ydCBhdXRvdHJhbnNsYXRlZCBwaHlzbWFwIGd1ZXN0cy4iKQpS ZXBvcnRlZC1ieTogQXRoYXJ2YSBWYXJ0YWsgPGF0aGFydmEuYS52YXJ0YWtA Z21haWwuY29tPgpTdWdnZXN0ZWQtYnk6IEF0aGFydmEgVmFydGFrIDxhdGhh cnZhLmEudmFydGFrQGdtYWlsLmNvbT4KU2lnbmVkLW9mZi1ieTogSnVlcmdl biBHcm9zcyA8amdyb3NzQHN1c2UuY29tPgpSZXZpZXdlZC1ieTogSmFuIEJl dWxpY2ggPGpiZXVsaWNoQHN1c2UuY29tPgotLS0KIGRyaXZlcnMveGVuL3By aXZjbWQuYyB8IDcgKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDcgaW5zZXJ0 aW9ucygrKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMveGVuL3ByaXZjbWQuYyBi L2RyaXZlcnMveGVuL3ByaXZjbWQuYwppbmRleCAxNWJhNTkyMjM2ZTguLjcy NWE0OWEwZWVlNyAxMDA2NDQKLS0tIGEvZHJpdmVycy94ZW4vcHJpdmNtZC5j CisrKyBiL2RyaXZlcnMveGVuL3ByaXZjbWQuYwpAQCAtMTYyMCw2ICsxNjIw LDEyIEBAIHN0YXRpYyB2b2lkIHByaXZjbWRfY2xvc2Uoc3RydWN0IHZtX2Fy ZWFfc3RydWN0ICp2bWEpCiAJa3ZmcmVlKHBhZ2VzKTsKIH0KIAorc3RhdGlj IGludCBwcml2Y21kX21heV9zcGxpdChzdHJ1Y3Qgdm1fYXJlYV9zdHJ1Y3Qg KmFyZWEsIHVuc2lnbmVkIGxvbmcgYWRkcikKK3sKKwkvKiBGb3JiaWQgc3Bs aXR0aW5nLCBhdm9pZHMgZG91YmxlIGZyZWUgdmlhIHByaXZjbWRfY2xvc2Uo KS4gKi8KKwlyZXR1cm4gLUVJTlZBTDsKK30KKwogc3RhdGljIHZtX2ZhdWx0 X3QgcHJpdmNtZF9mYXVsdChzdHJ1Y3Qgdm1fZmF1bHQgKnZtZikKIHsKIAlw cmludGsoS0VSTl9ERUJVRyAicHJpdmNtZF9mYXVsdDogdm1hPSVwICVseC0l bHgsIHBnb2ZmPSVseCwgdXY9JXBcbiIsCkBAIC0xNjMxLDYgKzE2MzcsNyBA QCBzdGF0aWMgdm1fZmF1bHRfdCBwcml2Y21kX2ZhdWx0KHN0cnVjdCB2bV9m YXVsdCAqdm1mKQogCiBzdGF0aWMgY29uc3Qgc3RydWN0IHZtX29wZXJhdGlv bnNfc3RydWN0IHByaXZjbWRfdm1fb3BzID0gewogCS5jbG9zZSA9IHByaXZj bWRfY2xvc2UsCisJLm1heV9zcGxpdCA9IHByaXZjbWRfbWF5X3NwbGl0LAog CS5mYXVsdCA9IHByaXZjbWRfZmF1bHQKIH07CiAKLS0gCjIuNTMuMAoK --=separator-- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:06:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:06:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1295923.1572485 (Exim 4.92) (envelope-from ) id 1wHhCZ-00079b-7O; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=YeqpqrGbiQeV318NZ/x97aB67b1RlTm1r4d5OxUH12A=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=VtQWe0UkIRR3/IhnOFPohbgPw/Q1/nmWRc8FlLSV/xBMh+S2E2ngV8cpGH9w4ezP7qSR5+j1y m2VXVEeBQioab+Nmkb+XK9Owpc2H3RI8DCP1f5NldIfUPU6h/BwTz2UyO2oQ4dPJQlr2K+GHu3h XXqZB8N/1b6Ztjsxpav4QVwE1pbzfWrLnUAmsL4nO6BeElbSjeLdHktzI+Fd0dbYysiHvKII9bB +X+dEaRWkFcLcyfuJhwyLi+jd4XoSioTJyz7MF5yMy5bJGK8ilWYorxXNQF1iZnZcguXzpNF+9+ hFlt8iq8smg9S/9p8pAeUrkCydolyXxPmnMlsXcIGzYA== X-Zone-Loop: e25d48730624bb1c42dc1816181bc6cda55610905932 x-campaign-type: default x-transaction-id: fb4994e6-a5e4-4197-bfc7-6e40279c01f5 x-swg-uid: 01-504940e1-7647-4dea-8492-c220cc86101b X-Mailer: Sweego Message-ID: <1777377961.8631fc262581453bbf619ec5b2062170.19dd3fb6660000f373@vates.tech> x-swg-bid: 1777377961.8631fc262581453bbf619ec5b2062170.19dd3fb6660000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 14:06:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/9] x86/vioapic: Add ioapic_check() to validate IO-APIC state before restore To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387cf6000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387cf6000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.66.5bdc74eb85b86f8c.19dd3fb649f.c8792f77bab4f20c=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777377961124 X-purgate-ID: tlsNG-ef75cf/1777377964-ACF66C48-DB87BBC4/0/0 X-purgate-type: clean X-purgate-size: 3491 ---=Part.66.5bdc74eb85b86f8c.19dd3fb649f.c8792f77bab4f20c=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Register a check callback for the IOAPIC HVM save/restore entry, > following the pattern established by vpic_check() for the virtual PIC=2E > The function first verifies the target domain actually has a virtual > IO-APIC, returning -ENODEV otherwise=2E It then validates individual > fields of the saved state: the base_address must be non-zero (as 0 is > never valid for the IO-APIC MMIO window), the APIC ID must fit within > its 4-bit hardware field, and ioregsel must address a defined register= =2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - Replaced the reserved-bit loop from v3 (iterating all redirection > table entries and rejecting any with non-zero reserved fields) with > targeted named-field validation (base_address !=3D 0, APIC ID < 0xF, = and > ioregsel addresses a defined register) > - The extended-destination migration safety check (refusing to restore > IO-APIC state with ext_dest_id bits set on a domain that does not > advertise XEN_HVM_CPUID_EXT_DEST_ID) is added in patch 8, once the > flag exists > --- > xen/arch/x86/hvm/vioapic=2Ec | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) >=20 > diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec > index 7c725f9e47=2E=2E43fb165f84 100644 > --- a/xen/arch/x86/hvm/vioapic=2Ec > +++ b/xen/arch/x86/hvm/vioapic=2Ec > @@ -594,6 +594,32 @@ int vioapic_get_trigger_mode(const struct domain *d= , unsigned int gsi) > return vioapic->redirtbl[pin]=2Efields=2Etrig_mode; > } > =20 > +static int cf_check ioapic_check(const struct domain *d, hvm_domain_con= text_t *h) > +{ > + const HVM_SAVE_TYPE(IOAPIC) *s; > + > + if ( !has_vioapic(d) ) > + return -ENODEV; > + > + s =3D hvm_get_entry(IOAPIC, h); > + if ( !s ) > + return -ENODATA; > + > + /* base_address of 0 is never valid for the IO-APIC MMIO window=2E = */ > + if ( !s->base_address ) > + return -EINVAL; > + > + /* IO-APIC APIC ID is a 4-bit field=2E */ > + if ( s->id > 0xf ) > + return -EINVAL; > + > + /* ioregsel must address a defined register=2E */ > + if ( s->ioregsel > VIOAPIC_REG_RTE0 + (ARRAY_SIZE(s->redirtbl) - 1)= * 2 + 1 ) you can rewrite it as s->ioregsel >=3D VIOAPIC_REG_RTE0 + ARRAY_SIZE(s->redirtbl) * 2 > + return -EINVAL; > + > + return 0; > +} > + > static int cf_check ioapic_save(struct vcpu *v, hvm_domain_context_t *= h) > { > const struct domain *d =3D v->domain; > @@ -630,7 +656,7 @@ static int cf_check ioapic_load(struct domain *d, hv= m_domain_context_t *h) > return 0; > } > =20 > -HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, NULL, ioapic_load, 1, > +HVM_REGISTER_SAVE_RESTORE(IOAPIC, ioapic_save, ioapic_check, ioapic_loa= d, 1, > HVMSR_PER_DOM); You think you can relax some of the checks in ioapic_load as you moved=20 some of them in ioapic_check=2E > =20 > void vioapic_reset(struct domain *d) Teddy -- | Vates XCP-ng & Xen Orchestra - Vates solutions web: https://vate= s=2Etech ---=Part.66.5bdc74eb85b86f8c.19dd3fb649f.c8792f77bab4f20c=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:26:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:26:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296104.1572494 (Exim 4.92) (envelope-from ) id 1wHhVs-0002fF-P3; Tue, 28 Apr 2026 12:26:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296104.1572494; Tue, 28 Apr 2026 12:26:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHhVs-0002f8-M6; Tue, 28 Apr 2026 12:26:04 +0000 Received: by outflank-mailman (input) for mailman id 1296104; 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Tue, 28 Apr 2026 05:26:01 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Mykola Kvach Date: Tue, 28 Apr 2026 15:25:49 +0300 X-Gm-Features: AVHnY4JSJekSk7U9pMZyuCzg9bO-oFUh_HBpZSmNEeMJ1AyyBIAN789klYwFL5c Message-ID: Subject: Ping: Re: [PATCH 0/4] xen/arm: ITS quirk handling fixes and board-specific matches To: Xen-devel Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1777379162-C2577DB1-4D8D0D21/0/0 X-purgate-type: clean X-purgate-size: 2254 Hi all, Gentle ping on this series. There are a few review comments that I can address in a v2, but one point seems to need maintainer guidance before I rework the series. In particular, there was a discussion around whether dma-noncoherent should remain an additive property handled separately from the ITS quirk table, or whether it should be modelled as part of the quirk matching machinery, which would likely require accumulating flags from all matching entries rather than keeping the current first-match semantics. Could maintainers please share their preference here? I am happy to prepare a v2 once the expected direction is clear. Thanks, Mykola On Wed, Mar 25, 2026 at 12:41=E2=80=AFPM Mykola Kvach wrote: > > From: Mykola Kvach > > This series cleans up ARM GICv3 ITS quirk handling and fixes the point at > which quirk-derived memory attributes become visible to the LPI setup pat= h. > > The first patch switches the quirk handling from per-entry init callbacks= to > declarative flags and folds in the DT dma-noncoherent property when deriv= ing > the effective ITS attributes. > > The second patch extends quirk matching with an optional platform callbac= k so > that boards sharing the same IIDR can still be distinguished reliably. Th= is > is then used by the third patch to add the Orange Pi 5 ITS quirk for > RK3588/RK3588S boards. > > Finally, the last patch moves ITS quirk discovery and validation earlier = in > the boot flow, before host LPI tables are initialized, so the boot CPU do= es > not allocate and program LPI data structures with default attributes when= the > platform requires different ones. > > Mykola Kvach (4): > xen/arm: its: collect quirk flags and honor dma-noncoherent > xen/arm: its: add platform match callback for ITS quirks > xen/arm: its: add Orange Pi 5 ITS quirk > xen/arm: its: pre-initialize ITS quirks before LPI setup > > xen/arch/arm/gic-v3-its.c | 129 +++++++++++++++++++------- > xen/arch/arm/gic-v3.c | 7 ++ > xen/arch/arm/include/asm/gic_v3_its.h | 5 + > 3 files changed, 107 insertions(+), 34 deletions(-) > > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:40:28 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:40:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296128.1572503 (Exim 4.92) (envelope-from ) id 1wHhjj-0005Um-Tx; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=9o7gVVzCtgiJq6Ow+DXx1i/e7S2Hj86E3t46w5H5dcQ=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=iipgfByd4fW+LAQTzE968w73nf2AoW+kTMoYGz8tb8lpKZ0AKr6rjvpeYsaRqqY1n7pty1yKJ pT1flPHiHXvsXj5p0I1LHesN3TevP2aLKJTSHJYzOPOCee0ILP6vogOyeukAcIvuCT9B3HDGeG2 diHtVLAx6dH/jxReWSXhf48Iz/942zsLDdPODrogz2ONMFCgnMpSG7noExF7r1l9SrohUO2Nni8 aZu0hdgHlM22yOmabOpWFCcmh90bacaWPa0JxI6abydBuIJDrQkCekipHnbL60QdlQecrwXjG13 x7lDWBw2Vbltp3N9VXhVQrtj0UCkNObh0PC8CNcqkvug== X-Zone-Loop: 70faca43bbf3c0363ce7eb759774e53e06203582dbcc x-campaign-type: default x-transaction-id: 9d21ec89-02a4-42f5-8b82-bf05a2fdde72 x-swg-uid: 01-63cc4a61-7a10-4e68-8b87-02ceab2da163 X-Mailer: Sweego Message-ID: <1777380015.8631fc262581453bbf619ec5b2062170.19dd41abd83000f373@vates.tech> x-swg-bid: 1777380015.8631fc262581453bbf619ec5b2062170.19dd41abd83000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 14:40:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/9] x86/passthrough: Wrap pt_irq_create_bind() restart block in braces To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387e25000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387e25000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.73.98a3d1c9318306da.19dd41abc0a.36ba62cfdaeb7ccc=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777380015115 X-purgate-ID: tlsNG-d62444/1777380021-B6A61FF4-4D680104/0/0 X-purgate-type: clean X-purgate-size: 5005 ---=Part.73.98a3d1c9318306da.19dd41abc0a.36ba62cfdaeb7ccc=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Enclose the restart/retry block in pt_irq_create_bind() in an explicit > compound statement to prepare for its extraction into a helper function= =2E > No functional change=2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - New patch > - Split out as a preparatory no-functional-change step to make the diff > in patch 5 (pt_irq_bind_msi() interface change) easier to review > --- > xen/drivers/passthrough/x86/hvm=2Ec | 80 ++++++++++++++++-------------= -- > 1 file changed, 41 insertions(+), 39 deletions(-) >=20 > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index b73bb55055=2E=2E691fa1b2c7 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -229,52 +229,54 @@ int pt_irq_create_bind( > return -EINVAL; > =20 > restart: > - write_lock(&d->event_lock); > - > - hvm_irq_dpci =3D domain_get_irq_dpci(d); > - if ( !hvm_irq_dpci && !is_hardware_domain(d) ) > { > - unsigned int i; > + write_lock(&d->event_lock); > =20 > - /* > - * NB: the hardware domain doesn't use a hvm_irq_dpci struct be= cause > - * it's only allowed to identity map GSIs, and so the data cont= ained in > - * that struct (used to map guest GSIs into machine GSIs and pe= rform > - * interrupt routing) is completely useless to it=2E > - */ > - hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); > - if ( hvm_irq_dpci =3D=3D NULL ) > + hvm_irq_dpci =3D domain_get_irq_dpci(d); > + if ( !hvm_irq_dpci && !is_hardware_domain(d) ) > + { > + unsigned int i; > + > + /* > + * NB: the hardware domain doesn't use a hvm_irq_dpci struc= t because > + * it's only allowed to identity map GSIs, and so the data = contained in > + * that struct (used to map guest GSIs into machine GSIs an= d perform > + * interrupt routing) is completely useless to it=2E > + */ > + hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); > + if ( hvm_irq_dpci =3D=3D NULL ) > + { > + write_unlock(&d->event_lock); > + return -ENOMEM; > + } > + for ( i =3D 0; i < NR_HVM_DOMU_IRQS; i++ ) > + INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]); > + > + hvm_domain_irq(d)->dpci =3D hvm_irq_dpci; > + } > + > + info =3D pirq_get_info(d, pirq); > + if ( !info ) > { > write_unlock(&d->event_lock); > return -ENOMEM; > } > - for ( i =3D 0; i < NR_HVM_DOMU_IRQS; i++ ) > - INIT_LIST_HEAD(&hvm_irq_dpci->girq[i]); > - > - hvm_domain_irq(d)->dpci =3D hvm_irq_dpci; > - } > - > - info =3D pirq_get_info(d, pirq); > - if ( !info ) > - { > - write_unlock(&d->event_lock); > - return -ENOMEM; > - } > - pirq_dpci =3D pirq_dpci(info); > + pirq_dpci =3D pirq_dpci(info); > =20 > - /* > - * A crude 'while' loop with us dropping the spinlock and giving > - * the softirq_dpci a chance to run=2E > - * We MUST check for this condition as the softirq could be schedul= ed > - * and hasn't run yet=2E Note that this code replaced tasklet_kill = which > - * would have spun forever and would do the same thing (wait to flu= sh out > - * outstanding hvm_dirq_assist calls=2E > - */ > - if ( pt_pirq_softirq_active(pirq_dpci) ) > - { > - write_unlock(&d->event_lock); > - cpu_relax(); > - goto restart; > + /* > + * A crude 'while' loop with us dropping the spinlock and givin= g > + * the softirq_dpci a chance to run=2E > + * We MUST check for this condition as the softirq could be sch= eduled > + * and hasn't run yet=2E Note that this code replaced tasklet_k= ill which > + * would have spun forever and would do the same thing (wait to= flush out > + * outstanding hvm_dirq_assist calls=2E > + */ > + if ( pt_pirq_softirq_active(pirq_dpci) ) > + { > + write_unlock(&d->event_lock); > + cpu_relax(); > + goto restart; > + } > } > =20 > switch ( pt_irq_bind->irq_type ) shows up as whitespace only changes (aside brackets) Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.73.98a3d1c9318306da.19dd41abc0a.36ba62cfdaeb7ccc=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 12:48:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 12:48:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296150.1572543 (Exim 4.92) (envelope-from ) id 1wHhrQ-0006iy-56; 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AFAICT this is a non-functional change. Should likely be mentioned in the commit message to avoid any doubts. > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/pci.c | 117 +++++++++++++++------------- > tools/firmware/hvmloader/pci_regs.h | 4 + > 2 files changed, 68 insertions(+), 53 deletions(-) > > diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c > index c41c8d946a..a76d051bdf 100644 > --- a/tools/firmware/hvmloader/pci.c > +++ b/tools/firmware/hvmloader/pci.c > @@ -84,12 +84,71 @@ static int find_next_rmrr(uint32_t base) > return next_rmrr; > } > > +static void class_specific_pci_device_setup(uint16_t vendor_id, > + uint16_t device_id, > + uint16_t class, It's a bit weird to pass the class value into the function, the value is only used inside the function itself, and hence could be fetched inside the function as the device BDF is provided as parameters? > + uint8_t bus, > + uint8_t devfn, uint8_t *vga_devfn) > +{ > + switch ( class ) > + { > + case PCI_CLASS_DISPLAY_VGA: > + /* If emulated VGA is found, preserve it as primary VGA. */ > + if ( (vendor_id == 0x1234) && (device_id == 0x1111) ) > + { > + *vga_devfn = devfn; > + virtual_vga = VGA_std; > + } > + else if ( (vendor_id == 0x1013) && (device_id == 0xb8) ) Since you introduce defines for the device classes, could you also introduce defines for the vendor and device IDs used here? > + { > + *vga_devfn = devfn; > + virtual_vga = VGA_cirrus; > + } > + else if ( virtual_vga == VGA_none ) > + { > + *vga_devfn = devfn; > + virtual_vga = VGA_pt; > + if ( vendor_id == 0x8086 ) This one is PCI_VENDOR_ID_INTEL, also a couple of more instances below. > + { > + igd_opregion_pgbase = mem_hole_alloc(IGD_OPREGION_PAGES); > + /* > + * Write the the OpRegion offset to give the opregion > + * address to the device model. The device model will trap > + * and map the OpRegion at the give address. > + */ > + pci_writel(*vga_devfn, PCI_INTEL_OPREGION, > + igd_opregion_pgbase << PAGE_SHIFT); > + } > + } > + break; Newlines after break statements. > + case PCI_CLASS_BRIDGE_OTHER: > + /* PIIX4 ACPI PM. Special device with special PCI config space. */ > + ASSERT((vendor_id == 0x8086) && (device_id == 0x7113)); > + pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */ > + pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */ > + pci_writew(devfn, 0x22, 0x0000); > + pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */ > + pci_writew(devfn, 0x3d, 0x0001); > + pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); > + pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */ > + break; > + case PCI_CLASS_STORAGE_IDE: > + if ( vendor_id == 0x8086 ) > + { > + /* Intel ICHs since PIIX3: enable IDE legacy mode. */ > + pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */ > + pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ > + } > + break; > + } > +} > + > void pci_setup(void) > { > uint8_t is_64bar, using_64bar, bar64_relocate = 0; > uint32_t devfn, bar_reg, cmd, bar_data, bar_data_upper; > uint64_t base, bar_sz, bar_sz_upper, mmio_total = 0; > - uint32_t vga_devfn = 256; > + uint8_t vga_devfn = 0xff; > uint16_t class, vendor_id, device_id; > unsigned int bar, pin, link, isa_irq; > uint8_t pci_devfn_decode_type[256] = {}; > @@ -170,57 +229,9 @@ void pci_setup(void) > ASSERT((devfn != PCI_ISA_DEVFN) || > ((vendor_id == 0x8086) && (device_id == 0x7000))); > > - switch ( class ) > - { > - case 0x0300: > - /* If emulated VGA is found, preserve it as primary VGA. */ > - if ( (vendor_id == 0x1234) && (device_id == 0x1111) ) > - { > - vga_devfn = devfn; > - virtual_vga = VGA_std; > - } > - else if ( (vendor_id == 0x1013) && (device_id == 0xb8) ) > - { > - vga_devfn = devfn; > - virtual_vga = VGA_cirrus; > - } > - else if ( virtual_vga == VGA_none ) > - { > - vga_devfn = devfn; > - virtual_vga = VGA_pt; > - if ( vendor_id == 0x8086 ) > - { > - igd_opregion_pgbase = mem_hole_alloc(IGD_OPREGION_PAGES); > - /* > - * Write the the OpRegion offset to give the opregion > - * address to the device model. The device model will trap > - * and map the OpRegion at the give address. > - */ > - pci_writel(vga_devfn, PCI_INTEL_OPREGION, > - igd_opregion_pgbase << PAGE_SHIFT); > - } > - } > - break; > - case 0x0680: > - /* PIIX4 ACPI PM. Special device with special PCI config space. */ > - ASSERT((vendor_id == 0x8086) && (device_id == 0x7113)); > - pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */ > - pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */ > - pci_writew(devfn, 0x22, 0x0000); > - pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */ > - pci_writew(devfn, 0x3d, 0x0001); > - pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); > - pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */ > - break; > - case 0x0101: > - if ( vendor_id == 0x8086 ) > - { > - /* Intel ICHs since PIIX3: enable IDE legacy mode. */ > - pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */ > - pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ > - } > - break; > - } > + class_specific_pci_device_setup(vendor_id, device_id, class, > + 0 /* virt_bus support TBD */, > + devfn, &vga_devfn); > > /* > * It is recommended that BAR programming be done whilst decode > @@ -583,7 +594,7 @@ void pci_setup(void) > ((pci_hi_mem_start & -pci_hi_mem_start) - 1)) + 1; > } > > - if ( vga_devfn != 256 ) > + if ( vga_devfn != 0xff ) > { > /* > * VGA registers live in I/O space so ensure that primary VGA > diff --git a/tools/firmware/hvmloader/pci_regs.h b/tools/firmware/hvmloader/pci_regs.h > index 4d4dc0cd01..c94278855b 100644 > --- a/tools/firmware/hvmloader/pci_regs.h > +++ b/tools/firmware/hvmloader/pci_regs.h > @@ -111,6 +111,10 @@ > #define PCI_DEVICE_ID_INTEL_82441 0x1237 > #define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 > > +#define PCI_CLASS_STORAGE_IDE 0x0101 > +#define PCI_CLASS_DISPLAY_VGA 0x0300 > +#define PCI_CLASS_BRIDGE_OTHER 0x0680 As mentioned in a previous patch, this would better be placed in a pci_ids.h header. Thanks, Roger. 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=0NwevG5QeWgAQyqGH8eMBN2pmsjZ9gFyStGUYXdDeA8=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=Tsmmw9dXAuAUYlYSpkt588n1MOCuy02d1+qTeG4q4zkY0NiUzXy2EuAGwCF8TUGv+3qDlfVni MTh4jEID99lgdgLzZ3jAJycsFMQ3VRKJ8veSZ2Vk01TRi3MyI/jfnY6/NsglT5RnS5nFYwAICV8 mLCe954ROA9uCgUqEN2w4NJLdZv3qgy9qLC4n1KW0DM0hUBpgBs1SAl6j3fIT1eQZhUqjdhICeg GJ/pjZV2tB68d8Np12EKmxnNIYzdpSc9pUIfQjktvTpjMSxRCa9Ej/Jah+DUuBbKc4Y7FDw20aD gXsbnhcNkQom19r13jbUlv5sOr1E+tqfNIlOiixmfOSw== X-Zone-Loop: 49b0996f75ed9ddff3de1659bbb4289a1471fb6ff5d0 x-campaign-type: default x-transaction-id: d7f393a3-ca66-4d7f-845b-7475ab891410 x-swg-uid: 01-933eaec2-d412-43fe-bd4b-93df7ede092d X-Mailer: Sweego Message-ID: <1777380807.8631fc262581453bbf619ec5b2062170.19dd426d216000f373@vates.tech> x-swg-bid: 1777380807.8631fc262581453bbf619ec5b2062170.19dd426d216000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 14:53:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/9] x86/passthrough: Extract pt_irq_dpci_setup() from pt_irq_create_bind() To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387f6f000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf387f6f000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.7b.b46d8b43660053ac.19dd426d007.cfc53a05fe197929=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777380806663 X-purgate-ID: tlsNG-42698a/1777380811-0556BF3B-57078A3D/0/0 X-purgate-type: clean X-purgate-size: 5274 ---=Part.7b.b46d8b43660053ac.19dd426d007.cfc53a05fe197929=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > The setup preamble in pt_irq_create_bind(), lazily allocating > hvm_irq_dpci, looking up the struct pirq, and spinning until any pending > hvm_dirq_assist softirq has drained, is needed by pt_irq_bind_msi() as > well=2E Extract it into a static helper pt_irq_dpci_setup() that returns > with d->event_lock write-locked on success=2E Replace the open-coded got= o > restart loop with a do { } while (true) loop and a continue, making the > retry structure explicit without a label=2E No functional change=2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - New patch > - Split out as a preparatory no-functional-change step to make the diff > in patch 5 (pt_irq_bind_msi() interface change) easier to review > --- > xen/drivers/passthrough/x86/hvm=2Ec | 54 +++++++++++++++++++++++------= -- > 1 file changed, 40 insertions(+), 14 deletions(-) >=20 > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index 691fa1b2c7=2E=2E19463c3406 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -217,18 +217,22 @@ static struct vcpu *vector_hashing_dest(const stru= ct domain *d, > return dest; > } > =20 > -int pt_irq_create_bind( > - struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) > +/* > + * Acquire d->event_lock (write), lazily allocate hvm_irq_dpci if neede= d, look > + * up the struct pirq for @pirq, and drain any pending hvm_dirq_assist = softirq > + * on it before returning=2E Returns 0 with d->event_lock held on succe= ss, > + * negative errno otherwise (lock not held)=2E > + */ > +static int pt_irq_dpci_setup(struct domain *d, unsigned int pirq, > + struct hvm_irq_dpci **hvm_irq_dpci_out, > + struct hvm_pirq_dpci **pirq_dpci_out, > + struct pirq **info_out) > { > struct hvm_irq_dpci *hvm_irq_dpci; > struct hvm_pirq_dpci *pirq_dpci; > struct pirq *info; > - int rc, pirq =3D pt_irq_bind->machine_irq; > =20 > - if ( pirq < 0 || pirq >=3D d->nr_pirqs ) > - return -EINVAL; > - > - restart: > + do > { > write_lock(&d->event_lock); > =20 > @@ -238,10 +242,11 @@ int pt_irq_create_bind( > unsigned int i; > =20 > /* > - * NB: the hardware domain doesn't use a hvm_irq_dpci struc= t because > - * it's only allowed to identity map GSIs, and so the data = contained in > - * that struct (used to map guest GSIs into machine GSIs an= d perform > - * interrupt routing) is completely useless to it=2E > + * NB: the hardware domain doesn't use a hvm_irq_dpci struc= t > + * because it's only allowed to identity map GSIs, and so t= he > + * data contained in that struct (used to map guest GSIs in= to > + * machine GSIs and perform interrupt routing) is completel= y > + * useless to it=2E > */ > hvm_irq_dpci =3D xzalloc(struct hvm_irq_dpci); > if ( hvm_irq_dpci =3D=3D NULL ) > @@ -269,15 +274,36 @@ int pt_irq_create_bind( > * We MUST check for this condition as the softirq could be sc= heduled > * and hasn't run yet=2E Note that this code replaced tasklet_= kill which > * would have spun forever and would do the same thing (wait t= o flush out > - * outstanding hvm_dirq_assist calls=2E > + * outstanding hvm_dirq_assist calls)=2E > */ > if ( pt_pirq_softirq_active(pirq_dpci) ) > { > write_unlock(&d->event_lock); > cpu_relax(); > - goto restart; > + continue; > } > - } > + > + *hvm_irq_dpci_out =3D hvm_irq_dpci; > + *pirq_dpci_out =3D pirq_dpci; > + *info_out =3D info; > + return 0; > + } while ( true ); I would prefer something like do { =2E=2E=2E } while (false); return 0; > +} > + > +int pt_irq_create_bind( > + struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) > +{ > + struct hvm_irq_dpci *hvm_irq_dpci; > + struct hvm_pirq_dpci *pirq_dpci; > + struct pirq *info; > + int rc, pirq =3D pt_irq_bind->machine_irq; > + > + if ( pirq < 0 || pirq >=3D d->nr_pirqs ) > + return -EINVAL; > + > + rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &info)= ; > + if ( rc ) > + return rc; > =20 > switch ( pt_irq_bind->irq_type ) > { The rest looks good to me=2E With the do { =2E=2E=2E } while (false); change: Reviewed-by: Teddy Astie -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.7b.b46d8b43660053ac.19dd426d007.cfc53a05fe197929=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 13:16:03 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 13:16:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296181.1572609 (Exim 4.92) (envelope-from ) id 1wHiHy-0003nj-Ou; Tue, 28 Apr 2026 13:15:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296181.1572609; Tue, 28 Apr 2026 13:15:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHiHy-0003nc-MK; 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This patch introduces support for the ICH9 LPC > bridge used in Q35 machine types, which resides at 00:1f.0. > > It also initializes PIRQA...{PIRQD, PIRQH} routing accordingly to the > emulated south bridge (either located on PCI_ISA_DEVFN or > PCI_ICH9_LPC_DEVFN). > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/config.h | 1 + > tools/firmware/hvmloader/pci.c | 34 ++++++++++++++++++++++++----- > tools/firmware/hvmloader/pci_regs.h | 1 + > 3 files changed, 31 insertions(+), 5 deletions(-) > > diff --git a/tools/firmware/hvmloader/config.h b/tools/firmware/hvmloader/config.h > index c159db30ee..baaed91c7f 100644 > --- a/tools/firmware/hvmloader/config.h > +++ b/tools/firmware/hvmloader/config.h > @@ -54,6 +54,7 @@ extern uint32_t *cpu_to_apicid; > > #define PCI_ISA_DEVFN 0x08 /* dev 1, fn 0 */ > #define PCI_ISA_IRQ_MASK 0x0c20U /* ISA IRQs 5,10,11 are PCI connected */ > +#define PCI_ICH9_LPC_DEVFN 0xf8 /* dev 31, fn 0 */ We should introduce a macro to generate BDFs more easily in the hvmloader context. Having them as plain numbers is not very friendly. > > #define ACPI_TIS_HDR_ADDRESS 0xFED40F00UL > > diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c > index a76d051bdf..91c7fd2171 100644 > --- a/tools/firmware/hvmloader/pci.c > +++ b/tools/firmware/hvmloader/pci.c > @@ -84,6 +84,10 @@ static int find_next_rmrr(uint32_t base) > return next_rmrr; > } > > +#define SCI_EN_IOPORT (ACPI_PM1A_EVT_BLK_ADDRESS_V1 + 0x30) > +#define GBL_SMI_EN (1 << 0) > +#define APMC_EN (1 << 5) > + > static void class_specific_pci_device_setup(uint16_t vendor_id, > uint16_t device_id, > uint16_t class, > @@ -140,6 +144,17 @@ static void class_specific_pci_device_setup(uint16_t vendor_id, > pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ > } > break; > + case PCI_CLASS_BRIDGE_ISA: > + /* LPC bridge */ > + if ( vendor_id == 0x8086 && device_id == 0x2918 ) If you don't add parentheses around the equal comparisons please also removing the existing ones when moving the code. Also device ID would batter be a constant with a proper name. > + { > + pci_writeb(devfn, 0x3c, 0x09); /* Hardcoded IRQ9 */ > + pci_writeb(devfn, 0x3d, 0x01); 0x3c and 0x3d are PCI_INTERRUPT_LINE and PCI_INTERRUPT_PIN respectively, let's please try to use the named constants when available (or when they can be introduced). > + pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); > + pci_writeb(devfn, 0x44, 0x80); /* enable PM io space */ > + outl(SCI_EN_IOPORT, inl(SCI_EN_IOPORT) | GBL_SMI_EN | APMC_EN); Most of the above looks like black magic. It's not like the context of this function is great, most of the existing stuff is poorly documented. Can we get a bit more comments about what's this supposed to do, and maybe a reference to the Intel specification that lists where those PCI config space registers are coming from? > + } > + break; > } > } > > @@ -152,6 +167,7 @@ void pci_setup(void) > uint16_t class, vendor_id, device_id; > unsigned int bar, pin, link, isa_irq; > uint8_t pci_devfn_decode_type[256] = {}; > + int is_running_on_q35 = (machine_type == MACHINE_TYPE_Q35); Maybe you can avoid that and instead simply store the BDF of the ISA device? unsigned int isa_bdf = (machine_type == MACHINE_TYPE_Q35) ? PCI_ICH9_LPC_DEVFN : PCI_ISA_DEVFN; Or if you really need it to be a boolean, let's make it: bool is_q35 = ... It makes no sense for it to be an int, and the naming could be shorter IMO. Thanks, Roger. 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Either IO, MMIO, ROM or a chipset-specific resource. > > One important new field is addr_mask, which tells which bits of the base > address can (should) be written. Different address types (ROM, MMIO BAR, > PCIEXBAR) will have different addr_mask values. > > For every assignable BAR range we store its size, PCI device BDF (devfn > actually) to which it belongs, BAR type (mem/io/mem64) and corresponding > register offset in device PCI conf space. > > Also, to reduce code complexity, all long mem/mem64 BAR flags checks are > replaced by simple bars[i] field probing, eg.: > - if ( (bar_reg == PCI_ROM_ADDRESS) || > - ((bar_data & PCI_BASE_ADDRESS_SPACE) == > - PCI_BASE_ADDRESS_SPACE_MEMORY) ) > + if ( bars[i].is_mem ) I think this is also supposed to be a non-functional change, just adding new fields and adjusting the code to make use of them? > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/pci.c | 58 ++++++++++++++++++++-------------- > 1 file changed, 35 insertions(+), 23 deletions(-) > > diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c > index 91c7fd2171..6e6720adae 100644 > --- a/tools/firmware/hvmloader/pci.c > +++ b/tools/firmware/hvmloader/pci.c > @@ -160,9 +160,10 @@ static void class_specific_pci_device_setup(uint16_t vendor_id, > > void pci_setup(void) > { > - uint8_t is_64bar, using_64bar, bar64_relocate = 0; > + uint8_t is_64bar, using_64bar, bar64_relocate = 0, is_mem; The newly introduce fields want to be booleans types. > uint32_t devfn, bar_reg, cmd, bar_data, bar_data_upper; > uint64_t base, bar_sz, bar_sz_upper, mmio_total = 0; > + uint64_t addr_mask; > uint8_t vga_devfn = 0xff; > uint16_t class, vendor_id, device_id; > unsigned int bar, pin, link, isa_irq; > @@ -176,10 +177,13 @@ void pci_setup(void) > > /* Create a list of device BARs in descending order of size. */ > struct bars { > - uint32_t is_64bar; > uint32_t devfn; > uint32_t bar_reg; > uint64_t bar_sz; > + uint64_t addr_mask; /* which bits of the base address can be written */ > + uint32_t bar_data; /* initial value - BAR flags here */ Hm, that's just storing the flags of the BAR, given that you already store the 64bit and memory flags, you just need the prefetch and ROM enabled booleans to have the full set, and then you can remove the bar_data field from the struct. > + uint8_t is_64bar; > + uint8_t is_mem; Use bool types please for the is_ fields. > } *bars = (struct bars *)scratch_start; > unsigned int i, nr_bars = 0; > uint64_t mmio_hole_size = 0; > @@ -278,13 +282,21 @@ void pci_setup(void) > bar_reg = PCI_ROM_ADDRESS; > > bar_data = pci_readl(devfn, bar_reg); > + > + is_mem = !!(((bar_data & PCI_BASE_ADDRESS_SPACE) == > + PCI_BASE_ADDRESS_SPACE_MEMORY) || > + (bar_reg == PCI_ROM_ADDRESS)); > + > if ( bar_reg != PCI_ROM_ADDRESS ) > { > - is_64bar = !!((bar_data & (PCI_BASE_ADDRESS_SPACE | > - PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == > - (PCI_BASE_ADDRESS_SPACE_MEMORY | > + is_64bar = !!(is_mem && > + ((bar_data & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == > PCI_BASE_ADDRESS_MEM_TYPE_64)); > + > pci_writel(devfn, bar_reg, ~0); > + > + addr_mask = is_mem ? PCI_BASE_ADDRESS_MEM_MASK > + : PCI_BASE_ADDRESS_IO_MASK; > } > else > { > @@ -292,15 +304,16 @@ void pci_setup(void) > pci_writel(devfn, bar_reg, > (bar_data | PCI_ROM_ADDRESS_MASK) & > ~PCI_ROM_ADDRESS_ENABLE); > + > + addr_mask = PCI_ROM_ADDRESS_MASK; > } > + > bar_sz = pci_readl(devfn, bar_reg); > pci_writel(devfn, bar_reg, bar_data); > > if ( bar_reg != PCI_ROM_ADDRESS ) > - bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) == > - PCI_BASE_ADDRESS_SPACE_MEMORY) ? > - PCI_BASE_ADDRESS_MEM_MASK : > - (PCI_BASE_ADDRESS_IO_MASK & 0xffff)); > + bar_sz &= is_mem ? PCI_BASE_ADDRESS_MEM_MASK : > + (PCI_BASE_ADDRESS_IO_MASK & 0xffff); > else > bar_sz &= PCI_ROM_ADDRESS_MASK; > if (is_64bar) { > @@ -314,6 +327,9 @@ void pci_setup(void) > if ( bar_sz == 0 ) > continue; > > + /* leave only memtype/enable bits etc */ > + bar_data &= ~addr_mask; > + > if ( !xenpci_bar_uc && > ((bar_data & PCI_BASE_ADDRESS_SPACE) == > PCI_BASE_ADDRESS_SPACE_MEMORY) && > @@ -359,16 +375,17 @@ void pci_setup(void) > if ( i != nr_bars ) > memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars)); > > - bars[i].is_64bar = is_64bar; > bars[i].devfn = devfn; > bars[i].bar_reg = bar_reg; > bars[i].bar_sz = bar_sz; > + bars[i].is_64bar = is_64bar; > + bars[i].is_mem = is_mem; > + bars[i].addr_mask = addr_mask; > + bars[i].bar_data = bar_data; > > if ( is_64bar && bar_sz > BAR_RELOC_THRESH ) > bar64_relocate = 1; > - else if ( ((bar_data & PCI_BASE_ADDRESS_SPACE) == > - PCI_BASE_ADDRESS_SPACE_MEMORY) || > - (bar_reg == PCI_ROM_ADDRESS) ) > + else if ( is_mem ) > mmio_total += bar_sz; > > nr_bars++; > @@ -531,10 +548,10 @@ void pci_setup(void) > using_64bar = bars[i].is_64bar && bar64_relocate && > (mmio_total > (mem_resource.max - mem_resource.base) || > bar_sz > BAR_RELOC_THRESH); > - bar_data = pci_readl(devfn, bar_reg); > > - if ( (bar_data & PCI_BASE_ADDRESS_SPACE) == > - PCI_BASE_ADDRESS_SPACE_MEMORY ) > + bar_data = bars[i].bar_data; > + > + if ( bars[i].is_mem ) > { > /* Mapping high memory if PCI device is 64 bits bar */ > if ( using_64bar ) { > @@ -544,11 +561,9 @@ void pci_setup(void) > if ( !pci_hi_mem_start ) > pci_hi_mem_start = high_mem_resource.base; > resource = &high_mem_resource; > - bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK; > } > else { > resource = &mem_resource; > - bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK; > } > if ( bar_sz <= BAR_RELOC_THRESH ) > mmio_total -= bar_sz; > @@ -556,7 +571,6 @@ void pci_setup(void) > else > { > resource = &io_resource; > - bar_data &= ~PCI_BASE_ADDRESS_IO_MASK; > } > > base = (resource->base + bar_sz - 1) & ~(uint64_t)(bar_sz - 1); > @@ -578,7 +592,7 @@ void pci_setup(void) > } > } > > - bar_data |= (uint32_t)base; > + bar_data |= (uint32_t) (base & bars[i].addr_mask); ^ unintended space? Thanks, Roger. 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------nltUoEkhYOgmBOpi0pCY6I7P" X-purgate-ID: tlsNG-bad1c0/1777383382-93374A53-85D6C04F/0/0 X-purgate-type: clean X-purgate-size: 9933 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------nltUoEkhYOgmBOpi0pCY6I7P Content-Type: multipart/mixed; boundary="------------jANO70Zjy6aUD1NmQqph0f3U"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Message-ID: Subject: Re: [PATCH 1/4] xen/public: introduce DOMID_ANY References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-2-jgross@suse.com> In-Reply-To: Autocrypt-Gossip: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJ3BBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AAIQkQoDSui/t3IH4WIQQ+pJkfkcoLMCa4X6CgNK6L+3cgfgn7AJ9DmMd0SMJE ePbc7/m22D2v04iu7ACffXTdZQhNl557tJuDXZSBxDmW/tLOwU0EWTecRBAIAIK5OMKMU5R2 Lk2bbjgX7vyQuCFFyKf9rC/4itNwhYWFSlKzVj3WJBDsoi2KvPm7AI+XB6NIkNAkshL5C0kd pcNd5Xo0jRR5/WE/bT7LyrJ0OJWS/qUit5eNNvsO+SxGAk28KRa1ieVLeZi9D03NL0+HIAtZ tecfqwgl3Y72UpLUyt+r7LQhcI/XR5IUUaD4C/chB4Vq2QkDKO7Q8+2HJOrFIjiVli4lU+Sf OBp64m//Y1xys++Z4ODoKh7tkh5DxiO3QBHG7bHK0CSQsJ6XUvPVYubAuy1XfSDzSeSBl//C v78Fclb+gi9GWidSTG/4hsEzd1fY5XwCZG/XJJY9M/sAAwUH/09Ar9W2U1Qm+DwZeP2ii3Ou 14Z9VlVVPhcEmR/AFykL9dw/OV2O/7cdi52+l00reUu6Nd4Dl8s4f5n8b1YFzmkVVIyhwjvU jxtPyUgDOt6DRa+RaDlXZZmxQyWcMv2anAgYWGVszeB8Myzsw8y7xhBEVV1S+1KloCzw4V8Z DSJrcsZlyMDoiTb7FyqxwQnM0f6qHxWbmOOnbzJmBqpNpFuDcz/4xNsymJylm6oXiucHQBAP Xb/cE1YNHpuaH4SRhIxwQilCYEznWowQphNAbJtEKOmcocY7EbSt8VjXTzmYENkIfkrHRyXQ dUm5AoL51XZljkCqNwrADGkTvkwsWSvCSQQYEQIACQUCWTecRAIbDAAKCRCgNK6L+3cgfuef AJ9wlZQNQUp0KwEf8Tl37RmcxCL4bQCcC5alCSMzUBJ5DBIcR4BY+CyQFAs= --------------jANO70Zjy6aUD1NmQqph0f3U Content-Type: multipart/mixed; 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnwt9UFAwAAAAAACgkQsN6d1ii/Ey/o YQf/aptfvUHNlJgz3tfSgx8JwLx6YZeraeTDo8sJEGNoXxAthkm0q98RVbQiy+p4sHBV55gEptnL HvX+nFJUfaOnjvKU7xwZPhmn+H5NHtlyzAHX6kkyX7nnsKeKRaR0zJmi/nf38fw+WEaS6RFqSGwd Jg0+b4DD8wbg+ffwxIDhrdn/NPsO9DB5nuKOn6UT/DoQdH0k962ZYN5dhMcT2i0CsBUEczaMQo65 tNk/eb6rcLqqmye2w6sc4Zny6ygqf38D1xFrw9Z30SF1vNR05yLB2v6Jhx6ut4Sur4aHOmczth7X yyLf+moFn9TFwM6lHXqc+rRiOkhwDY6o4RfyVIhZLg== =f82e -----END PGP SIGNATURE----- --------------nltUoEkhYOgmBOpi0pCY6I7P-- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 13:38:59 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 13:38:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296233.1572647 (Exim 4.92) (envelope-from ) id 1wHieM-0000U6-GL; Tue, 28 Apr 2026 13:38:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296233.1572647; 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Despite the fact that this series was submitted just one day after the deadline, it appears to provide useful functionality. If maintainers have time to review it, it would be great to include it in this release. Release-Acked-by: Oleksii Kurochko Thanks. ~ Oleksii From xen-devel-bounces@lists.xenproject.org Tue Apr 28 13:39:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 13:39:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296246.1572654 (Exim 4.92) (envelope-from ) id 1wHifK-0001CA-O8; Tue, 28 Apr 2026 13:39:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296246.1572654; Tue, 28 Apr 2026 13:39:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHifK-0001C3-LA; Tue, 28 Apr 2026 13:39:54 +0000 Received: by outflank-mailman (input) for mailman id 1296246; Tue, 28 Apr 2026 13:39:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHifJ-0001Bv-CW for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 13:39:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHifI-0056pj-Og for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 15:39:52 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0b891-bab6-0a2a0a5309dd-0a2a450ce652-38 for ; Tue, 28 Apr 2026 15:39:52 +0200 Received: from [209.85.208.54] (helo=mail-ed1-f54.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0b8a8-62f1-0a2a450c0019-d155d036f0a3-3 for ; Tue, 28 Apr 2026 15:39:52 +0200 Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-67929ff6dbfso4145827a12.2 for ; Tue, 28 Apr 2026 06:39:52 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------VZVPZuRWvvMMi3ADBV5BO30W" X-purgate-ID: tlsNG-d25034/1777383592-6DD6BCF5-D11B3E9F/0/0 X-purgate-type: clean X-purgate-size: 8031 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------VZVPZuRWvvMMi3ADBV5BO30W Content-Type: multipart/mixed; boundary="------------qUcR0Z8SQzp2enVRLCA2AQA0"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Anthony PERARD , Julien Grall Message-ID: <0748c0d3-78cd-457e-9e88-fbe19e58c73f@suse.com> Subject: Re: [PATCH 2/4] tools/xenstored: add support for "all domains" node permission References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-3-jgross@suse.com> In-Reply-To: --------------qUcR0Z8SQzp2enVRLCA2AQA0 Content-Type: multipart/mixed; boundary="------------5YUj0EbTPBHAtlQncae2B0OV" --------------5YUj0EbTPBHAtlQncae2B0OV Content-Type: text/plain; charset=UTF-8; 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmnwuKcFAwAAAAAACgkQsN6d1ii/Ey9h 8Af/aiTLS2Y7QTazYSFFe4mns+KVWf24wl4mi2eoO59pnep9ezd449/3FqKtWO9BXn4pq/Tu1W2n cs+ORkKy+e5Bhz+7u7rwMTBOfcAsRg7XjWtthYyDw/iPB5FUz21Waxqo3sSf2tR5G35Ar68Bze9a lg+76pveBBxZRTgpIqnr62gS85w3V4q/IPvMcEXgMIgOrpzw5iPzgUUSuxJmG8XGo6Pxmmy5LpUV KRMiDElGEpbXCzcG+e0tqRz+MXNNlSOyuZ79BFrQ3zAGBEdx5PHrgRDlJqaHN9w44UZxXMapUxKa xTVQatCcIxxTlmlRcVQZ6S1tdeJ7UpdvG0PCDVGIAA== =lF/7 -----END PGP SIGNATURE----- --------------VZVPZuRWvvMMi3ADBV5BO30W-- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 13:40:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 13:40:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296253.1572664 (Exim 4.92) (envelope-from ) id 1wHigA-0002et-1T; Tue, 28 Apr 2026 13:40:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296253.1572664; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------o3th2mmBF3o0jHFKSsKL0dsb" X-purgate-ID: tlsNG-d25034/1777383643-F600DCF5-97D3AD07/0/0 X-purgate-type: clean X-purgate-size: 7417 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------o3th2mmBF3o0jHFKSsKL0dsb Content-Type: multipart/mixed; boundary="------------R68zS0tOhHWv5jKo8JTl5mSa"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jason Andryuk , xen-devel@lists.xenproject.org Cc: dmukhin@ford.com, Julien Grall , Anthony PERARD Message-ID: Subject: Re: [PATCH 4/4] tools/xenstored: remove permissions related to dead domain References: <20260423080840.530547-1-jgross@suse.com> <20260423080840.530547-5-jgross@suse.com> <9624178e-7596-4395-adca-7cedc58aafb9@amd.com> In-Reply-To: <9624178e-7596-4395-adca-7cedc58aafb9@amd.com> --------------R68zS0tOhHWv5jKo8JTl5mSa Content-Type: multipart/mixed; boundary="------------0QiMXP0u0Wz6SCifY0nBIxoz" --------------0QiMXP0u0Wz6SCifY0nBIxoz Content-Type: text/plain; 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> break; > > + case HVMOP_set_ecam_space: { > + xen_hvm_ecam_space_t ecam; > + struct domain *d; > + > + if ( copy_from_guest( &ecam, guest_handle_cast(arg, xen_hvm_ecam_space_t), 1 ) ) ^ extra space, here and at the closing parenthesis. Line length is also past the 80 character limit, same below in HVMOP_get_ecam_space. > + return -EFAULT; This operation (and the matching get variant) needs an XSM check. > + > + d = rcu_lock_domain_by_any_id(ecam.domid); > + if ( d == NULL ) > + return -ESRCH; > + > + if ( d->arch.ecam_addr ) { Coding style, opening braces should be on a new line. > + rcu_unlock_domain(d); > + return -EFAULT; This would better return -EBUSY > + } You also need to check the padding fields are 0. > + > + if ( (ecam.size >> 28) || (!ecam.addr) ) { ^ the parenthesis here are unneeded. > + rcu_unlock_domain(d); > + return -EINVAL; > + } > + > + d->arch.ecam_addr = ecam.addr; > + d->arch.ecam_size = ecam.size; I'm a bit worried about a domain being able to set it's own ECAM hole, assessing all the side-effects of this might be complex. Won't the code here better check the region passed in the hypercall is indeed not mapped in the p2m, so that trapping of ECAM accesses works as expected? Also, how does the ECAM hole get setup on native? I assume there are some magic registers in the PCI config space of a platform device that the firmware uses to position the ECAM space? Are those trapped by QEMU, in which case won't it be better to do it the native way (iow: with the config space registers), and let QEMU forward it to Xen? It would then be QEMU the one to call HVMOP_set_ecam_space (or whatever hypercall we end up using). > + > + rcu_unlock_domain(d); > + break; > + } > + > + case HVMOP_get_ecam_space: { > + xen_hvm_ecam_space_t ecam; > + struct domain *d; > + > + if ( copy_from_guest( &ecam, guest_handle_cast(arg, xen_hvm_ecam_space_t), 1 ) ) > + return -EFAULT; > + > + d = rcu_lock_domain_by_any_id(ecam.domid); > + if ( d == NULL ) > + return -ESRCH; > + > + if ( ! d->arch.ecam_addr || ! d->arch.ecam_size ) { > + rcu_unlock_domain(d); > + return -EINVAL; > + } > + > + ecam.addr = d->arch.ecam_addr; > + ecam.size = d->arch.ecam_size; > + rc = __copy_to_guest(arg, &ecam, 1) ? -EFAULT : 0; > + > + rcu_unlock_domain(d); > + break; > + } > + > default: > rc = -ENOSYS; > break; > diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h > index ad7f6adb2c..24ec33fc4d 100644 > --- a/xen/arch/x86/include/asm/domain.h > +++ b/xen/arch/x86/include/asm/domain.h > @@ -476,6 +476,10 @@ struct arch_domain > > /* Emulated devices enabled bitmap. */ > uint32_t emulation_flags; > + > + /* PCI ECAM space emulation */ > + uint64_t ecam_addr; > + uint32_t ecam_size; This fields would better be in hvm_domain struct, and there you already have the mmcfg_regions list, which we should aim to use for the q35 introduced ECAM region. > } __cacheline_aligned; > > #ifdef CONFIG_HVM > diff --git a/xen/include/public/hvm/hvm_op.h b/xen/include/public/hvm/hvm_op.h > index e22adf0319..c84febc37c 100644 > --- a/xen/include/public/hvm/hvm_op.h > +++ b/xen/include/public/hvm/hvm_op.h > @@ -166,6 +166,17 @@ struct xen_hvm_get_mem_type { > typedef struct xen_hvm_get_mem_type xen_hvm_get_mem_type_t; > DEFINE_XEN_GUEST_HANDLE(xen_hvm_get_mem_type_t); > > +#define HVMOP_set_ecam_space 16 > +#define HVMOP_get_ecam_space 17 > +struct xen_hvm_ecam_space { > + domid_t domid; > + uint16_t pad[3]; /* align next field on 8-byte boundary */ > + uint64_t addr; > + uint32_t size; There's also a trailing uint32_t padding here on 64bit builds I think? FWIW, you could do: domid_t domid; uint16_t pad; uint32_t size uint64_t addr; As that would reduce the padding in the struct? Thanks, Roger. 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=Ge8VGVcz3F+F04cXtFUFi3xWtqCV+GSEWHSHeIeQDEE=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=F26OBvrf1QCrdsqpkmys9Wi8JgadVxsUnLCbhFyaG18tWVEgPCm77yazQQVELQqJc3WCRD5Po 8UWfZEs3G6fSTqeUMLOBfG0Qlgr2eL2Xkos2VNvZ782rKQumPa+CkBGsY/J9wpjjNSOBY378p41 fenSHcv5DmpycH6mxuiPqM1nw9P4QDY/gXbiVdGlRnSL4nhJuorCQ6Yqa+hx6sUYzkn8nHEjUzv QGsb/dNJRZNEgAlPcyNlWwZdLrd1Tf/9Xj/Pa074tl6g0IGtVKb1ww1OFb+VpUnEBj2TTFSrplP c9yW0UNHr/6fsNs20R9vClM9xKCvdDwo+Bbp+IpwQipg== X-Zone-Loop: 7498aa3db807c0daac240a4f993392f4fc55817a0e5d x-campaign-type: default x-transaction-id: 3894dfa1-d272-4ed6-bf22-966a174d2d94 x-swg-uid: 01-912ad003-8ff3-424c-a4a9-5df252209416 X-Mailer: Sweego Message-ID: <1777384886.8631fc262581453bbf619ec5b2062170.19dd4650f2c000f373@vates.tech> x-swg-bid: 1777384886.8631fc262581453bbf619ec5b2062170.19dd4650f2c000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 16:01:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/9] x86/passthrough: Extract PT_IRQ_TYPE_MSI body into pt_irq_bind_msi() To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298079.8631fc262581453bbf619ec5b2062170.19dcf3880b0000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298079.8631fc262581453bbf619ec5b2062170.19dcf3880b0000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.b5.57efd0fc27062d4d.19dd465068f.43f3625d62435cc9=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777384883856 X-purgate-ID: tlsNG-33051d/1777384892-28975938-554CAABD/0/0 X-purgate-type: clean X-purgate-size: 14899 ---=Part.b5.57efd0fc27062d4d.19dd465068f.43f3625d62435cc9=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > No functional change: move the PT_IRQ_TYPE_MSI case of pt_irq_create_bin= d() > into a new static helper pt_irq_bind_msi() taking the same gvec/gflags/g= table > parameters=2E Restructure pt_irq_create_bind() so the MSI case delegates= to the > helper and pt_irq_dpci_setup() is called inside each case rather than sh= ared=2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - New patch > - Split out as a preparatory no-functional-change step so that the > interface change in patch 5 (switching pt_irq_bind_msi() from gvec + > gflags to raw MSI addr + data) shows as a clean diff against an > already-extracted helper, rather than being tangled with the 'case > PT_IRQ_TYPE_MSI' code > --- > xen/drivers/passthrough/x86/hvm=2Ec | 255 ++++++++++++++++------------= -- > 1 file changed, 140 insertions(+), 115 deletions(-) >=20 > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index 19463c3406=2E=2Eeff1e8a79e 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -290,161 +290,186 @@ static int pt_irq_dpci_setup(struct domain *d, u= nsigned int pirq, > } while ( true ); > } > =20 > -int pt_irq_create_bind( > - struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) > +static int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, > + uint8_t gvec, uint32_t gflags, uint64_t gta= ble, > + bool unmasked) > { > struct hvm_irq_dpci *hvm_irq_dpci; > struct hvm_pirq_dpci *pirq_dpci; > struct pirq *info; > - int rc, pirq =3D pt_irq_bind->machine_irq; > + uint8_t dest, delivery_mode; > + bool dest_mode; > + int dest_vcpu_id, rc; > + const struct vcpu *vcpu; > =20 > - if ( pirq < 0 || pirq >=3D d->nr_pirqs ) > + if ( machine_irq >=3D (unsigned int)d->nr_pirqs ) is that (unsigned int) cast required ? > return -EINVAL; > =20 > - rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &info)= ; > + rc =3D pt_irq_dpci_setup(d, machine_irq, &hvm_irq_dpci, &pirq_dpci,= &info); > if ( rc ) > return rc; > =20 > - switch ( pt_irq_bind->irq_type ) > + if ( !(pirq_dpci->flags & HVM_IRQ_DPCI_MAPPED) ) > { > - case PT_IRQ_TYPE_MSI: > - { > - uint8_t dest, delivery_mode; > - bool dest_mode; > - int dest_vcpu_id; > - const struct vcpu *vcpu; > - uint32_t gflags =3D pt_irq_bind->u=2Emsi=2Egflags & > - ~XEN_DOMCTL_VMSI_X86_UNMASKED; > - > - if ( !(pirq_dpci->flags & HVM_IRQ_DPCI_MAPPED) ) > + pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MACH_MS= I | > + HVM_IRQ_DPCI_GUEST_MSI; > + pirq_dpci->gmsi=2Egvec =3D gvec; > + pirq_dpci->gmsi=2Egflags =3D gflags; > + /* > + * 'pt_irq_bind_msi' can be called after 'pt_irq_destroy_bind'= =2E > + * The 'pirq_cleanup_check' which would free the structure is o= nly > + * called if the event channel for the PIRQ is active=2E Howeve= r > + * OS-es that use event channels usually bind PIRQs to eventds > + * and unbind them before calling 'pt_irq_destroy_bind' - with = the > + * result that we re-use the 'dpci' structure=2E This can be > + * reproduced with unloading and loading the driver for a devic= e=2E > + * > + * As such on every 'pt_irq_bind_msi' call we MUST set it=2E > + */ > + pirq_dpci->dom =3D d; > + /* bind after hvm_irq_dpci is setup to avoid race with irq hand= ler */ > + rc =3D pirq_guest_bind(d->vcpu[0], info, 0); > + if ( rc =3D=3D 0 && gtable ) > { > - pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MAC= H_MSI | > - HVM_IRQ_DPCI_GUEST_MSI; > - pirq_dpci->gmsi=2Egvec =3D pt_irq_bind->u=2Emsi=2Egvec; > - pirq_dpci->gmsi=2Egflags =3D gflags; > - /* > - * 'pt_irq_create_bind' can be called after 'pt_irq_destroy= _bind'=2E > - * The 'pirq_cleanup_check' which would free the structure = is only > - * called if the event channel for the PIRQ is active=2E Ho= wever > - * OS-es that use event channels usually bind PIRQs to even= tds > - * and unbind them before calling 'pt_irq_destroy_bind' - w= ith the > - * result that we re-use the 'dpci' structure=2E This can b= e > - * reproduced with unloading and loading the driver for a d= evice=2E > - * > - * As such on every 'pt_irq_create_bind' call we MUST set i= t=2E > - */ > - pirq_dpci->dom =3D d; > - /* bind after hvm_irq_dpci is setup to avoid race with irq = handler*/ > - rc =3D pirq_guest_bind(d->vcpu[0], info, 0); > - if ( rc =3D=3D 0 && pt_irq_bind->u=2Emsi=2Egtable ) > - { > - rc =3D msixtbl_pt_register(d, info, pt_irq_bind->u=2Ems= i=2Egtable); > - if ( unlikely(rc) ) > - { > - pirq_guest_unbind(d, info); > - /* > - * Between 'pirq_guest_bind' and before 'pirq_guest= _unbind' > - * an interrupt can be scheduled=2E No more of them= are going > - * to be scheduled but we must deal with the one th= at may be > - * in the queue=2E > - */ > - pt_pirq_softirq_reset(pirq_dpci); > - } > - } > + rc =3D msixtbl_pt_register(d, info, gtable); > if ( unlikely(rc) ) > { > - pirq_dpci->gmsi=2Egflags =3D 0; > - pirq_dpci->gmsi=2Egvec =3D 0; > - pirq_dpci->dom =3D NULL; > - pirq_dpci->flags =3D 0; > - if ( !info->evtchn ) > - pirq_cleanup_check(info, d); > - write_unlock(&d->event_lock); > - return rc; > + pirq_guest_unbind(d, info); > + /* > + * Between 'pirq_guest_bind' and before 'pirq_guest_unb= ind' > + * an interrupt can be scheduled=2E No more of them are= going > + * to be scheduled but we must deal with the one that m= ay be > + * in the queue=2E > + */ > + pt_pirq_softirq_reset(pirq_dpci); > } > } > - else > + if ( unlikely(rc) ) > { > - uint32_t mask =3D HVM_IRQ_DPCI_MACH_MSI | HVM_IRQ_DPCI_GUES= T_MSI; > - > - if ( (pirq_dpci->flags & mask) !=3D mask ) > - { > - write_unlock(&d->event_lock); > - return -EBUSY; > - } > - > - /* If pirq is already mapped as vmsi, update guest data/add= r=2E */ > - if ( pirq_dpci->gmsi=2Egvec !=3D pt_irq_bind->u=2Emsi=2Egve= c || > - pirq_dpci->gmsi=2Egflags !=3D gflags ) > - { > - /* Directly clear pending EOIs before enabling new MSI = info=2E */ > - pirq_guest_eoi(info); > - > - pirq_dpci->gmsi=2Egvec =3D pt_irq_bind->u=2Emsi=2Egvec; > - pirq_dpci->gmsi=2Egflags =3D gflags; > - } > + pirq_dpci->gmsi=2Egflags =3D 0; > + pirq_dpci->gmsi=2Egvec =3D 0; > + pirq_dpci->dom =3D NULL; > + pirq_dpci->flags =3D 0; > + if ( !info->evtchn ) > + pirq_cleanup_check(info, d); > + write_unlock(&d->event_lock); > + return rc; > } > - /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ > - dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, > - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK); > - dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM= _MASK; > - delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, > - XEN_DOMCTL_VMSI_X86_DELIV_MASK); > - > - dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); > - pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; > - write_unlock(&d->event_lock); > + } > + else > + { > + uint32_t mask =3D HVM_IRQ_DPCI_MACH_MSI | HVM_IRQ_DPCI_GUEST_MS= I; > =20 > - pirq_dpci->gmsi=2Eposted =3D false; > - vcpu =3D (dest_vcpu_id >=3D 0) ? d->vcpu[dest_vcpu_id] : NULL; > - if ( iommu_intpost ) > + if ( (pirq_dpci->flags & mask) !=3D mask ) > { > - if ( delivery_mode =3D=3D dest_LowestPrio ) > - vcpu =3D vector_hashing_dest(d, dest, dest_mode, > - pirq_dpci->gmsi=2Egvec); > - if ( vcpu ) > - pirq_dpci->gmsi=2Eposted =3D true; > + write_unlock(&d->event_lock); > + return -EBUSY; > } > - if ( vcpu && is_iommu_enabled(d) ) > - hvm_migrate_pirq(pirq_dpci, vcpu); > =20 > - /* Use interrupt posting if it is supported=2E */ > - if ( iommu_intpost ) > + /* If pirq is already mapped as vmsi, update guest data/addr=2E= */ > + if ( pirq_dpci->gmsi=2Egvec !=3D gvec || pirq_dpci->gmsi=2Egfla= gs !=3D gflags ) > { > - rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egve= c); > + /* Directly clear pending EOIs before enabling new MSI info= =2E */ > + pirq_guest_eoi(info); > =20 > - if ( rc ) > - { > - pt_irq_destroy_bind(d, pt_irq_bind); > - return rc; > - } > + pirq_dpci->gmsi=2Egvec =3D gvec; > + pirq_dpci->gmsi=2Egflags =3D gflags; > } > + } > + /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ > + dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, XEN_DOMCTL_VMSI_X86_DE= ST_ID_MASK); > + dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM_MAS= K; > + delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, > + XEN_DOMCTL_VMSI_X86_DELIV_MASK); > + > + dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); > + pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; > + write_unlock(&d->event_lock); > =20 > - if ( pt_irq_bind->u=2Emsi=2Egflags & XEN_DOMCTL_VMSI_X86_UNMASK= ED ) > + pirq_dpci->gmsi=2Eposted =3D false; > + vcpu =3D (dest_vcpu_id >=3D 0) ? d->vcpu[dest_vcpu_id] : NULL; > + if ( iommu_intpost ) > + { > + if ( delivery_mode =3D=3D dest_LowestPrio ) > + vcpu =3D vector_hashing_dest(d, dest, dest_mode, > + pirq_dpci->gmsi=2Egvec); > + if ( vcpu ) > + pirq_dpci->gmsi=2Eposted =3D true; > + } > + if ( vcpu && is_iommu_enabled(d) ) > + hvm_migrate_pirq(pirq_dpci, vcpu); > + > + /* Use interrupt posting if it is supported=2E */ > + if ( iommu_intpost ) > + { > + struct xen_domctl_bind_pt_irq bind =3D { > + =2Emachine_irq =3D machine_irq, > + =2Eirq_type =3D PT_IRQ_TYPE_MSI, > + }; > + > + rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egvec); > + if ( rc ) > { > - unsigned long flags; > - struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &fl= ags); > + pt_irq_destroy_bind(d, &bind); > + return rc; > + } > + } > =20 > - if ( !desc ) > - { > - pt_irq_destroy_bind(d, pt_irq_bind); > - return -EINVAL; > - } > + if ( unmasked ) > + { > + struct xen_domctl_bind_pt_irq bind =3D { > + =2Emachine_irq =3D machine_irq, > + =2Eirq_type =3D PT_IRQ_TYPE_MSI, > + }; > + unsigned long flags; > + struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &flags)= ; > =20 > - guest_mask_msi_irq(desc, false); > - spin_unlock_irqrestore(&desc->lock, flags); > + if ( !desc ) > + { > + pt_irq_destroy_bind(d, &bind); > + return -EINVAL; > } > =20 > - break; > + guest_mask_msi_irq(desc, false); > + spin_unlock_irqrestore(&desc->lock, flags); > } > =20 > + return 0; > +} > + > +int pt_irq_create_bind( > + struct domain *d, const struct xen_domctl_bind_pt_irq *pt_irq_bind) > +{ > + int rc, pirq =3D pt_irq_bind->machine_irq; > + > + if ( pirq < 0 || pirq >=3D d->nr_pirqs ) > + return -EINVAL; > + > + switch ( pt_irq_bind->irq_type ) > + { > + case PT_IRQ_TYPE_MSI: > + return pt_irq_bind_msi(d, pirq, > + pt_irq_bind->u=2Emsi=2Egvec, > + pt_irq_bind->u=2Emsi=2Egflags & > + ~XEN_DOMCTL_VMSI_X86_UNMASKED, > + pt_irq_bind->u=2Emsi=2Egtable, > + !!(pt_irq_bind->u=2Emsi=2Egflags & > + XEN_DOMCTL_VMSI_X86_UNMASKED)); > + > case PT_IRQ_TYPE_PCI: > case PT_IRQ_TYPE_MSI_TRANSLATE: > { > + struct hvm_irq_dpci *hvm_irq_dpci; > + struct hvm_pirq_dpci *pirq_dpci; > + struct pirq *info; > struct dev_intx_gsi_link *digl =3D NULL; > struct hvm_girq_dpci_mapping *girq =3D NULL; > unsigned int guest_gsi; > =20 > + rc =3D pt_irq_dpci_setup(d, pirq, &hvm_irq_dpci, &pirq_dpci, &i= nfo); > + if ( rc ) > + return rc; > + > /* > * Mapping GSIs for the hardware domain is different than doin= g it for > * an unpriviledged guest, the hardware domain is only allowed= t Aside that, the rest looks good to me=2E with or without the cast change : Reviewed-by: Teddy Astie Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.b5.57efd0fc27062d4d.19dd465068f.43f3625d62435cc9=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:14:38 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:14:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296296.1572715 (Exim 4.92) (envelope-from ) id 1wHjCg-0000ed-BV; Tue, 28 Apr 2026 14:14:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296296.1572715; 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This would better be introduced with at least one user, as otherwise it's just unreachable code. And then I'm not convinced we should use hypercalls to set the ECAM position/size from hvmloader, if it can be done using the native registers and QEMU can forward those to Xen. Thanks, Roger. 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Tue, 28 Apr 2026 07:28:44 -0700 (PDT) MIME-Version: 1.0 References: <20260428081303.990973-1-marcandre.lureau@redhat.com> <20260428081303.990973-9-marcandre.lureau@redhat.com> In-Reply-To: <20260428081303.990973-9-marcandre.lureau@redhat.com> From: Stefan Hajnoczi Date: Tue, 28 Apr 2026 10:28:32 -0400 X-Gm-Features: AVHnY4Jmh-XBh9OrnMlY2iCW1hoL0ExMevskFSExN-SDnKJrlB8WX0t3_BRuqoI Message-ID: Subject: Re: [PULL 08/15] ui/console: return completion status from gfx_update callback To: marcandre.lureau@redhat.com Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, Jan Kiszka , Phil Dennis-Jordan , Richard Henderson , Helge Deller , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Gerd Hoffmann , Mark Cave-Ayland , Samuel Tardieu , =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Laurent Vivier , Thomas Huth , BALATON Zoltan , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Akihiko Odaki , Dmitry Osipenko , "Michael S. Tsirkin" , Dmitry Fleytman , Stefano Stabellini , Anthony PERARD , "Edgar E. Iglesias" , Alistair Francis , Alex Williamson , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "open list:Musicpal" , "open list:sam460ex" , "open list:X86 Xen CPUs" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1777386525-CE576D75-07B15094/0/0 X-purgate-type: clean X-purgate-size: 442 Hi Marc-Andr=C3=A9, This patch changes the .gfx_update callback prototype and fails to compile due to the following recently-merged commit: commit 5ef60a3787e8e0dccf30dae3704d4f5249160e7d Author: Yucai Liu <1486344514@qq.com> Date: Sun Apr 12 19:02:39 2026 +0800 hw/display: Add i.MX6UL LCDIF device model Please rebase on qemu.git/master, fix the build, and send another revision of this pull request. Thanks! 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Tue, 28 Apr 2026 07:29:20 -0700 (PDT) MIME-Version: 1.0 References: <20260428081303.990973-1-marcandre.lureau@redhat.com> <20260428081303.990973-9-marcandre.lureau@redhat.com> In-Reply-To: From: Stefan Hajnoczi Date: Tue, 28 Apr 2026 10:29:06 -0400 X-Gm-Features: AVHnY4JxfR5X49sh3f0xQOBGO5skCikVufW4qo03US3ycxLQlGj8SojUzT_-PqQ Message-ID: Subject: Re: [PULL 08/15] ui/console: return completion status from gfx_update callback To: marcandre.lureau@redhat.com Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, Jan Kiszka , Phil Dennis-Jordan , Richard Henderson , Helge Deller , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Gerd Hoffmann , Mark Cave-Ayland , Samuel Tardieu , =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Laurent Vivier , Thomas Huth , BALATON Zoltan , =?UTF-8?B?QWxleCBCZW5uw6ll?= , Akihiko Odaki , Dmitry Osipenko , "Michael S. Tsirkin" , Dmitry Fleytman , Stefano Stabellini , Anthony PERARD , "Edgar E. Iglesias" , Alistair Francis , Alex Williamson , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , "open list:Musicpal" , "open list:sam460ex" , "open list:X86 Xen CPUs" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1777386560-5377FD75-5B3FC1A3/0/0 X-purgate-type: clean X-purgate-size: 962 On Tue, Apr 28, 2026 at 10:28=E2=80=AFAM Stefan Hajnoczi wrote: > > Hi Marc-Andr=C3=A9, > This patch changes the .gfx_update callback prototype and fails to > compile due to the following recently-merged commit: > > commit 5ef60a3787e8e0dccf30dae3704d4f5249160e7d > Author: Yucai Liu <1486344514@qq.com> > Date: Sun Apr 12 19:02:39 2026 +0800 > > hw/display: Add i.MX6UL LCDIF device model For reference, here is the CI build failure: ../hw/display/imx6ul_lcdif.c:221:19: error: initialization of =E2=80=98_Boo= l (*)(void *)=E2=80=99 from incompatible pointer type =E2=80=98void (*)(void = *)=E2=80=99 [-Wincompatible-pointer-types] 221 | .gfx_update =3D imx6ul_lcdif_update_display, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ../hw/display/imx6ul_lcdif.c:221:19: note: (near initialization for =E2=80=98imx6ul_lcdif_graphic_ops.gfx_update=E2=80=99) https://gitlab.com/qemu-project/qemu/-/jobs/14124076225 Stefan From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296337.1572806 (Exim 4.92) (envelope-from ) id 1wHjVh-0006tW-Ad; Tue, 28 Apr 2026 14:34:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296337.1572806; Tue, 28 Apr 2026 14:34:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVh-0006sd-1W; Tue, 28 Apr 2026 14:34:01 +0000 Received: by outflank-mailman (input) for mailman id 1296337; Tue, 28 Apr 2026 14:33:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVf-0006cZ-Bm for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVe-000RTW-Nk for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:58 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c548-2eae-0a2a0a5409dd-0a2a4501d626-48 for ; Tue, 28 Apr 2026 16:33:58 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c556-c1f2-0a2a45010019-d155802ee026-3 for ; Tue, 28 Apr 2026 16:33:58 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-488b0e1b870so196655385e9.2 for ; Tue, 28 Apr 2026 07:33:58 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a774b6300sm19302145e9.16.2026.04.28.07.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 07:33:57 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777386838; x=1777991638; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bJSZfDZmsT3CIOe+qmGhvl/hB/yKGv3ZJ6HZqE/FbGU=; b=FPRkagivTRTkvPrr9DgTrmPJ6A5qzrmzZNs2fIZsLQ8ZPmxEPetYngzYCW0q2XyJ7z NUJ50SXTThw/w2DeUDz4rgRhLghew6Pl8X1DjZ2ejH6sJZG9l4h67h+amrKi1nzIUDlm cwHzpWA4Qq+DPQTe6Lxm9Uk1jLF1M5lvkcAUs77bfbOrCgWMaZEoG5XA5vH3ByfRjtZf d6fChtIOnjeISsNRZLrXz8uE/cK4hxv55dqA+4qYe5se10PD9Q2f8XtvU4nAAPTYq9dY ZyvPoPoSJABf7Mnh8VqYs2W9WZmjKlfIEMYBsKQt/Juu/RNHzLBLgnuG4OGTbYS0lYCy rQqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777386838; x=1777991638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=bJSZfDZmsT3CIOe+qmGhvl/hB/yKGv3ZJ6HZqE/FbGU=; b=PReBikdlPq6Yei4Ymis4ZBQ31q1qRImHjRDjc3+vk2lYEurIluSS+mnfcbAdhpXQa2 +jSyMTEVqANq9RkCImBLpYDq3BiRBInUbEFOudZBIIrGoEPowxp4HJy4VkwvrLPhaP6+ OdIgzAQqWd/7WNqycIH4JaQPb+iEtes9+89rSehTSkPSF2L6UMsTZcCR2s3jPKdh/5lz E69eyp9F6EpVAZ8Lw5KhpVFPmu6GhfNdhqFowNGC0ARP8QQ8waiwazWaE5KNKYHSUAsb 7AcrnMZMEmj4BogITD3uwOftxUMkcfGip58B3GOeedRvKAkLTXqZlvT02WeC37x9gkzg +m2Q== X-Gm-Message-State: AOJu0YyiMmXrqVt4dGs2niYM3I29CDM+lCTX82WHn1cRdxRG9Zjucwpe fjVJiuhJiz2AWKiW/xJcL7tEu1eYX6Z+ZAogQLmkgckWukbQDVo5aR41AcaiNg== X-Gm-Gg: AeBDieu3g/A6h1TG0H5/O5M/jDbJJgZ8aGFkcUqts8582EC6Ei5i3r/dUtz5wirWQAu GGxwPsfBcref1u97vsjInCf9jFqbWS2OylQ96zMvyFzjcNGzaLxkZE6xon63bPfuN9fsqhQ+P3s efiwrwWNllp0z/0+nwYxxQCELTwodCzM59GBQYZmg/Ah6Bugg5Dbi409ldX5EKJmcannK01YAEI gl8qJtNWF0dUBiD8QQpIqdA7xiXoSzF6evCrWebtkW8zkSAbPlBob8noE6TqTPXh37We5ISoqGr CNbPEkI6YPXLfq7FfLPuQMDAnQp0DK2w7W1C4yFxBW+mnzFW6nARX63iLsgDgU7pEzvfbfsFe2a Vd/z/VD1R2QL6t/oVoF/C4QK+l7SzsxL5nqO20jw1RI34XcuierutEoFmXrFAehyCQ8QBDmLUa7 sq8gdEnZOcnfQccCqByZQfYPqk7IhVOil7Gtc2UUqCwa04D0iTr5IsNY8TCwtt/YPav58V4zE54 lEG X-Received: by 2002:a05:600c:4f92:b0:489:19e9:b139 with SMTP id 5b1f17b1804b1-48a77ae54f4mr52698725e9.1.1777386837671; Tue, 28 Apr 2026 07:33:57 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 07/11] xen/riscv: add Linux kernel loading support Date: Tue, 28 Apr 2026 16:33:36 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1777386838-B727DFF4-D3108EBD/10/73395122804 X-purgate-type: spam X-purgate-size: 11996 Introduce support for loading a Linux kernel Image which is got by uncompressing of Image.gz on RISC-V. kernel_image_load() and place_modules() currently call panic() on failure rather than returning an error. This is because the common kernel_load() in common/device-tree/kernel.c does not expect a return code. Handling errors gracefully would require a separate refactor. The implementation is based on the Xen Arm kernel loading code. text_offset is available for both 32-bit and 64-bit Image, so fix that. Signed-off-by: Oleksii Kurochko --- Changes in v4: - Update the patch subject: add "... Linux kernel ...". - Make bi variable unsigned. And use while() instead of for(). - Update the condition which calculates overlapping of kernel with modules. - Reject a malformed image before the loop to avoid wrapping load_addr + image_size in the per-bankcheck below. - Use mathematical representation to print ranges. - Use #error instead of just returning unsupported. - Update the comment above stuct image in kernel_image64_probe(). --- --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/config.h | 13 ++ xen/arch/riscv/kernel.c | 242 ++++++++++++++++++++++++++++ xen/include/xen/fdt-kernel.h | 11 +- 4 files changed, 265 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/kernel.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index cfc3fdf7d208..eecdcbc76867 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -8,6 +8,7 @@ obj-y += guestcopy.o obj-y += imsic.o obj-y += intc.o obj-y += irq.o +obj-y += kernel.init.o obj-y += mm.o obj-y += p2m.o obj-y += paging.o diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index 0613de008b13..fd69057826e1 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -151,6 +151,19 @@ extern unsigned long phys_offset; /* = load_start - XEN_VIRT_START */ #endif +/* + * KERNEL_LOAD_ADDR_ALIGNMENT is defined based on paragraph of + * "Kernel location" of boot.rst: + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location + */ +#if defined(CONFIG_RISCV_32) +#define KERNEL_LOAD_ADDR_ALIGNMENT MB(4) +#elif defined(CONFIG_RISCV_64) +#define KERNEL_LOAD_ADDR_ALIGNMENT MB(2) +#else +#error "Define KERNEL_LOAD_ADDR_ALIGNMENT" +#endif + #endif /* ASM__RISCV__CONFIG_H */ /* * Local variables: diff --git a/xen/arch/riscv/kernel.c b/xen/arch/riscv/kernel.c new file mode 100644 index 000000000000..dd79f457732d --- /dev/null +++ b/xen/arch/riscv/kernel.c @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define IMAGE64_MAGIC_V2 0x05435352 /* Magic number 2, le, "RSC\x05" */ + +static void __init place_modules(struct kernel_info *info, paddr_t kernbase, + paddr_t kernend) +{ + const struct boot_module *mod = info->bd.initrd; + const struct membanks *banks = kernel_info_get_mem_const(info); + const paddr_t initrd_len = ROUNDUP(mod ? mod->size : 0, + KERNEL_LOAD_ADDR_ALIGNMENT); + const paddr_t dtb_len = ROUNDUP(fdt_totalsize(info->fdt), + KERNEL_LOAD_ADDR_ALIGNMENT); + const paddr_t modsize = initrd_len + dtb_len; + unsigned int bi = banks->nr_banks; + + BUG_ON(modsize < initrd_len); + + /* + * Place modules as high in RAM as possible, scanning banks from + * last to first so that the end of the last bank is preferred. + */ + while ( bi-- > 0 ) + { + const struct membank *bank = &banks->bank[bi]; + const paddr_t bank_end = bank->start + bank->size; + paddr_t modbase; + + if ( modsize > bank->size ) + continue; + + modbase = ROUNDDOWN(bank_end - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); + + if ( modbase < bank->start ) + continue; + + /* + * If modules would overlap the kernel, try placing them below it. + */ + if ( (modbase < ROUNDUP(kernend, KERNEL_LOAD_ADDR_ALIGNMENT)) && + (modbase + modsize > kernbase) ) + { + modbase = ROUNDDOWN(kernbase - modsize, KERNEL_LOAD_ADDR_ALIGNMENT); + if ( modbase < bank->start ) + continue; + } + + info->dtb_paddr = modbase; + info->initrd_paddr = modbase + dtb_len; + + return; + } + + panic("Unable to find suitable location for dtb+initrd\n"); +} + +static paddr_t __init kernel_image_place(struct kernel_info *info) +{ + paddr_t load_addr = INVALID_PADDR; + uint64_t image_size = info->image.image_size ?: info->image.len; + const struct membanks *banks = kernel_info_get_mem_const(info); + unsigned int nr_banks = banks->nr_banks; + unsigned int bi; + + dprintk(XENLOG_DEBUG, "nr_banks(%u)\n", nr_banks); + + /* + * At the moment, RISC-V's Linux kernel should be always position + * independent based on "Per-MMU execution" of boot.rst: + * https://docs.kernel.org/arch/riscv/boot.html#pre-mmu-execution + * + * But just for the case when RISC-V's Linux kernel isn't position + * independent it is needed to take load address from + * info->image.start. + * + * If `start` is zero, the Image is position independent. + */ + if ( likely(!info->image.start) ) + { + for ( bi = 0; bi != nr_banks; bi++ ) + { + const struct membank *bank = &banks->bank[bi]; + paddr_t bank_start = bank->start; + /* + * According to boot.rst kernel load address should be properly + * aligned: + * https://docs.kernel.org/arch/riscv/boot.html#kernel-location + * + * As Image in this case is PIC we can ignore + * info->image.text_offset. + */ + paddr_t aligned_start = ROUNDUP(bank_start, KERNEL_LOAD_ADDR_ALIGNMENT); + paddr_t bank_end = bank_start + bank->size; + paddr_t bank_size; + + if ( aligned_start > bank_end ) + continue; + + bank_size = bank_end - aligned_start; + + dprintk(XENLOG_DEBUG, "bank[%u].start=%"PRIpaddr"\n", bi, bank->start); + + if ( image_size <= bank_size ) + { + load_addr = aligned_start; + break; + } + } + } + else + { + load_addr = info->image.start + info->image.text_offset; + + WARN_ON(!IS_ALIGNED(load_addr, KERNEL_LOAD_ADDR_ALIGNMENT)); + + /* + * Reject a malformed image before the loop to avoid wrapping + * load_addr + image_size in the per-bank check below by setting + * bi = nr_banks. + * + * image_size covers the kernel from _start (placed at load_addr = + * start + text_offset) through _end. The alignment gap + * [start, load_addr) is padding and need not lie within a bank. + */ + bi = image_size <= (paddr_t)-1 - load_addr ? 0 : nr_banks; + for ( ; bi != nr_banks; bi++ ) + { + const struct membank *bank = &banks->bank[bi]; + paddr_t bank_start = bank->start; + paddr_t bank_end = bank_start + bank->size; + + if ( (load_addr >= bank_start) && + (load_addr + image_size <= bank_end) ) + break; + } + } + + if ( bi == nr_banks ) + panic("Failed to place kernel image in any memory bank\n"); + + info->entry = load_addr; + + return load_addr; +} + +static void __init kernel_image_load(struct kernel_info *info) +{ + int rc; + paddr_t load_addr = kernel_image_place(info); + paddr_t paddr = info->image.kernel_addr; + paddr_t len = info->image.len; + paddr_t effective_size = info->image.image_size ?: len; + void *kernel; + + place_modules(info, load_addr, load_addr + effective_size); + + printk("Loading Image from %"PRIpaddr" to [%"PRIpaddr",%"PRIpaddr")\n", + paddr, load_addr, load_addr + effective_size); + + kernel = ioremap_cache(paddr, len); + + if ( !kernel ) + panic("Unable to map kernel\n"); + + /* Move kernel to proper location in guest phys map */ + rc = copy_to_guest_phys(info->bd.d, load_addr, kernel, len); + + if ( rc ) + panic("Unable to copy kernel to proper guest location\n"); + + iounmap(kernel); +} + +/* Check if the image is a 64-bit Image */ +static int __init kernel_image64_probe(struct kernel_info *info, + paddr_t addr, paddr_t size) +{ + /* https://www.kernel.org/doc/Documentation/riscv/boot-image-header.rst */ + struct { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset, little endian */ + uint64_t image_size; /* Effective Image size, little endian */ + uint64_t flags; /* kernel flags, little endian */ + uint32_t version; /* Version of this header */ + uint32_t res1; /* Reserved */ + uint64_t res2; /* Reserved */ + uint64_t magic; /* Deprecated: Magic number, little endian, "RISCV" */ + uint32_t magic2; /* Magic number 2, little endian, "RSC\x05" */ + uint32_t res3; /* Reserved for PE COFF offset */ + } image; + uint64_t effective_size; + + if ( size < sizeof(image) ) + return -EINVAL; + + copy_from_paddr(&image, addr, sizeof(image)); + + /* Magic v1 is deprecated and may be removed. Only use v2 */ + if ( le32_to_cpu(image.magic2) != IMAGE64_MAGIC_V2 ) + return -EINVAL; + + effective_size = le64_to_cpu(image.image_size); + + if ( effective_size && size > effective_size ) + return -EINVAL; + + info->image.kernel_addr = addr; + /* Actual size in the binary file */ + info->image.len = size; + /* Total memory the kernel occupies at runtime */ + info->image.image_size = effective_size; + info->image.text_offset = le64_to_cpu(image.text_offset); + info->image.start = 0; + + info->load = kernel_image_load; + + return 0; +} + +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, + paddr_t size) +{ +#ifdef CONFIG_RISCV_64 + return kernel_image64_probe(info, addr, size); +#else +# error "Only 64-bit RISC-V is supported" +#endif +} diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 54be77aa191e..c69da642eba8 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -59,8 +59,15 @@ struct kernel_info { struct { paddr_t kernel_addr; paddr_t len; -#if defined(CONFIG_ARM_64) || defined(CONFIG_RISCV_64) - paddr_t text_offset; /* 64-bit Image only */ +#if defined(CONFIG_ARM_64) || defined(CONFIG_RISCV) + /* + * ARM: 64-bit Image only. + * RISC-V: both 32-bit and 64-bit Images. + */ + paddr_t text_offset; +#endif +#if defined(CONFIG_RISCV) + uint64_t image_size; /* Effective size of Image */ #endif paddr_t start; /* Must be 0 for 64-bit Image */ } image; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296336.1572796 (Exim 4.92) (envelope-from ) id 1wHjVf-0006du-Re; Tue, 28 Apr 2026 14:33:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296336.1572796; Tue, 28 Apr 2026 14:33:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVf-0006dm-OC; Tue, 28 Apr 2026 14:33:59 +0000 Received: by outflank-mailman (input) for mailman id 1296336; Tue, 28 Apr 2026 14:33:58 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVe-0006KX-3x for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:58 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVd-008e9B-Fy for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:57 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c549-e002-0a2a0a5209dd-0a2a450ab9ca-34 for ; Tue, 28 Apr 2026 16:33:57 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c555-56b3-0a2a450a0019-d155802ed89e-3 for ; Tue, 28 Apr 2026 16:33:57 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4891c00e7aeso88343765e9.2 for ; Tue, 28 Apr 2026 07:33:57 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a774b6300sm19302145e9.16.2026.04.28.07.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 07:33:56 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777386837; x=1777991637; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0p2rPrjn5OibxQ2M64WVzW16uHfFGsN8U9iQfuox9F0=; b=q6v3sotR/hyBodh/pDMvS1DuMVm/Yd1KxIgFhrgnKNAUp6sbkHGym9vcp/6uQxtwqm /eBPFrmyVJdrxFedaxIEQMdWr8lKOyCtkGrhyYehP/eZnxO3HPg6tjEJ4JgmmRck5U6E hK7pd660ayqk+nBfC0OCL6WvitbBlRWC/2pgr5qB9Z160LjDSIFpGrKjFoSV3mFGZkY3 5xn2+77UrS29iBW0zs+4ag/JwY8aSrPs6skzJwrAnwVlreyNAWkU4PrxAGlfEFS8dVlh xddDTE4SN3n4xxRj1M5Typ70MlNPlQbvzupZvABhDKZKp+k1SN6RgTy4sQzv3IP0vYlK noxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777386837; x=1777991637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0p2rPrjn5OibxQ2M64WVzW16uHfFGsN8U9iQfuox9F0=; b=HzjMas+ZwCR7enQcfC4acpo1yjxUFCkaJ35uca6yzWuw3gMDSKAGNAdUn7PpqBrP9X OVXGC+EnYY7TGEK89CU/oofMcoG3HOUp+9OpkNoR8T5r1/cbEnYkAfe2z9iaC0L66q5s kzsSkTpmVwoV0FnRB8qyumLItaw085F0CwWk90uA3QBi0mOPIV/yxHgI8Ipno7qjLXU7 DMaOk2/jLKD8ZvzkoLBFfefnj237dQyBNalwITlyUaECAUQXyL9BW2uTWXbFgMdB77N2 Gpp+tQF5CJIV7dEl6eWfQLmLbpQW8+YlRIe+1b+jO1K6wv6NqvFoYq1WCOcK6euFJbA8 TwMA== X-Gm-Message-State: AOJu0Yza4gdwr/Vy9SfBF7JjaeeNvu+bYvercHhPCJ2KkIUVK8Zfd8Ph qdyOGqttnjL8MOeJzP7AJbRJ0OoUr0JA5Kij0pQpGtN9cqECBlG8f3GTxYAPPg== X-Gm-Gg: AeBDieu2kHbF6Y+3HwMGqNuz16+z4F5238/FsaKIUXKscf45bj+I6clpMQLNlHud3uk xzXwp62/Pww/iP65vvK9hcHHo08oX/r1ZvGaYLdkJIeGgH/IpmGHdIHAKWCSq0W03HTkL9g2hZ4 AqG4Ocw7MQU2ntbI3Eaic7R0QsS4Us2gx/pDX3qMoDDh4EpqmHlnJItRpRCx3/NJR/3HBH+bV51 /PGNYuaUZw4XH73M6987kLRhxw9Rwn74G6j7D3fXnq32y1pFysFdJw6yHBOC7J9iBET6P/NNvJ5 gvdvVBhecS9mIenBN/pJZe1HUV2INzcN1lQZP6tLfLm6H+AYqrsnqzUvDb1xwn2DpQzwJH7Bgl9 e+tM/EleJV68U8Qd/cKjeVJSgVF0374gml4BFyg2D0pJRsNY4MM2nwhvnWYe/PB/2NVNDAvtWUN I3zn1aiO4AmnBxXQh7+QYAOh/BBm9+Axk3ysR49mY44LwvTQCoyqU79CYcPT/xPXLtYOh7rXxe3 389 X-Received: by 2002:a05:600c:1c20:b0:489:1aed:1658 with SMTP id 5b1f17b1804b1-48a77b241admr55613805e9.23.1777386836472; Tue, 28 Apr 2026 07:33:56 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 06/11] xen/riscv: implement copy_to_guest_phys() Date: Tue, 28 Apr 2026 16:33:35 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1777386837-467758B7-47A8CE3E/10/73395122804 X-purgate-type: spam X-purgate-size: 6519 Introduce copy_to_guest_phys() for RISC-V, based on the Arm implementation. Add a generic copy_guest() helper for copying to and from guest physical (and potentially virtual addresses in the future), and implement translate_get_page() to translate a guest physical address into a struct page_info via the domain p2m. Compared to the Arm code: - Drop COPY_flush_dcache(), as no such use cases exist on RISC-V. - Do not implement the linear mapping case, which is currently unused. - Use PAGE_OFFSET() to initialize the local offset variable in copy_guest(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Avoid using of min_t. (sync with Arm) - Add Acked-by: Jan Beulich . --- Changes in v3: - s/if (page == NULL)/if ( !page ). - Drop " - offset" for unmap_domain_page() inside copy_guest() function. unmap_domain_page() is expected to mask (or something similar) the page offset bits. - Change some types for functions as copy_to_guest_phys_cb function pointer prototype was changed too in the prev. commit. --- Changes in v2: - Use BIT() instead of open-coding. - Rename COPY_ipa to COPY_gpa. - Rename COPY_linear to COPY_gva. - Use BUG_ON(linear) instead if (lineer) + BUG_ON. - Rename arg liner to gva for translate_get_page(). - Update translate_get_page() to properly handling write argument. - Return unsigned int for copy_guest() and copy_to_guest_phys() as len function parameter is only 'unsigned int'. - Reformat function arguments for alignment --- --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/guestcopy.c | 116 ++++++++++++++++++++++ xen/arch/riscv/include/asm/guest_access.h | 7 ++ 3 files changed, 124 insertions(+) create mode 100644 xen/arch/riscv/guestcopy.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 04f02ad89cba..cfc3fdf7d208 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += domain.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += extable.o +obj-y += guestcopy.o obj-y += imsic.o obj-y += intc.o obj-y += irq.o diff --git a/xen/arch/riscv/guestcopy.c b/xen/arch/riscv/guestcopy.c new file mode 100644 index 000000000000..8a89212e0bea --- /dev/null +++ b/xen/arch/riscv/guestcopy.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include + +#define COPY_from_guest 0U +#define COPY_to_guest BIT(0, U) +#define COPY_gpa 0U +#define COPY_gva BIT(1, U) + +typedef union +{ + struct + { + struct vcpu *v; + } gva; + + struct + { + struct domain *d; + } gpa; +} copy_info_t; + +#define GVA_INFO(vcpu) ((copy_info_t) { .gva = { vcpu } }) +#define GPA_INFO(domain) ((copy_info_t) { .gpa = { domain } }) + +static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, + bool gva, bool write) +{ + p2m_type_t p2mt; + struct page_info *page; + + /* + * Not implemented yet. + * + * If gva == true, the operation will likely require a struct vcpu + * rather than just a struct domain. For this reason copy_info_t is + * already passed here instead of only struct domain. + */ + BUG_ON(gva); + + page = get_page_from_gfn(info.gpa.d, paddr_to_pfn(addr), &p2mt, P2M_ALLOC); + + if ( !page ) + return NULL; + + if ( write ? p2mt != p2m_ram_rw : !p2m_is_ram(p2mt) ) + { + put_page(page); + return NULL; + } + + return page; +} + +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, + copy_info_t info, unsigned int flags) +{ + unsigned int offset = PAGE_OFFSET(addr); + + BUILD_BUG_ON((sizeof(addr)) < sizeof(vaddr_t)); + BUILD_BUG_ON((sizeof(addr)) < sizeof(paddr_t)); + + while ( len ) + { + void *p; + unsigned long size = min(len, PAGE_SIZE + 0UL - offset); + struct page_info *page; + + page = translate_get_page(info, addr, flags & COPY_gva, + flags & COPY_to_guest); + if ( !page ) + return len; + + p = __map_domain_page(page); + p += offset; + if ( flags & COPY_to_guest ) + { + /* + * buf will be NULL when the caller request to zero the + * guest memory. + */ + if ( buf ) + memcpy(p, buf, size); + else + memset(p, 0, size); + } + else + memcpy(buf, p, size); + + unmap_domain_page(p); + put_page(page); + len -= size; + buf += size; + addr += size; + + /* + * After the first iteration, guest virtual address is correctly + * aligned to PAGE_SIZE. + */ + offset = 0; + } + + return 0; +} + +unsigned long copy_to_guest_phys(struct domain *d, paddr_t gpa, void *buf, + unsigned long len) +{ + return copy_guest(buf, gpa, len, GPA_INFO(d), + COPY_to_guest | COPY_gpa); +} diff --git a/xen/arch/riscv/include/asm/guest_access.h b/xen/arch/riscv/include/asm/guest_access.h index 7cd51fbbdead..8d679319ded0 100644 --- a/xen/arch/riscv/include/asm/guest_access.h +++ b/xen/arch/riscv/include/asm/guest_access.h @@ -2,6 +2,10 @@ #ifndef ASM__RISCV__GUEST_ACCESS_H #define ASM__RISCV__GUEST_ACCESS_H +#include + +struct domain; + unsigned long raw_copy_to_guest(void *to, const void *from, unsigned len); unsigned long raw_copy_from_guest(void *to, const void *from, unsigned len); unsigned long raw_clear_guest(void *to, unsigned int len); @@ -18,6 +22,9 @@ unsigned long raw_clear_guest(void *to, unsigned int len); #define guest_handle_okay(hnd, nr) (1) #define guest_handle_subrange_okay(hnd, first, last) (1) +unsigned long copy_to_guest_phys(struct domain *d, paddr_t gpa, void *buf, + unsigned long len); + #endif /* ASM__RISCV__GUEST_ACCESS_H */ /* * Local variables: -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296332.1572777 (Exim 4.92) (envelope-from ) id 1wHjVd-00068u-94; Tue, 28 Apr 2026 14:33:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296332.1572777; Tue, 28 Apr 2026 14:33:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVd-00068g-52; Tue, 28 Apr 2026 14:33:57 +0000 Received: by outflank-mailman (input) for mailman id 1296332; Tue, 28 Apr 2026 14:33:55 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVb-0005q2-KS for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:55 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVb-000RTW-06 for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:55 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c548-2eae-0a2a0a5409dd-0a2a4501d626-32 for ; Tue, 28 Apr 2026 16:33:54 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c552-c1f2-0a2a45010019-d1558030e130-3 for ; Tue, 28 Apr 2026 16:33:54 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-488a8ca4aadso159479825e9.3 for ; Tue, 28 Apr 2026 07:33:54 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. [109.243.69.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a774b6300sm19302145e9.16.2026.04.28.07.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 07:33:53 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777386834; x=1777991634; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HJckSt8P9RqMXs+Zl/HaWVhTtv7+MRR8ow5oSeYh3yY=; b=aJC1bUhZBM9AD45Wb3MiNlGtFtG7eDZCQM2oAj2ssWcEV7FEjGug8IPJsNKFKf73CZ 0rvc9jIDmDQMmruswVfd0sZ7ueWKE8bQVwK2y4lA0Y9faeRgVDGZAqZmyEySayLck4dX oWp+wB+IMLGN3WCrJwXbyGWRK9vdbCgon3Hh2n76fk6FlJ+UH4GO5+6q5JXLUMGzFffl XyFkwLm6N9nSI04U7oVBtzKuv4mvKt2205KD1Yzu0P2B44XT/J9D1gW9UWszsJzVWuKP ncriXmvR/E9xN2kKrDE+My20XvM7uvThOqO3N31Og7RY0n6AybjeIcdKYzs6I1YmO7+i UEjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777386834; x=1777991634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HJckSt8P9RqMXs+Zl/HaWVhTtv7+MRR8ow5oSeYh3yY=; b=RA67P6BElqwmNTG69n/r7QXsgAPYv0KtCf8IgnQr4yyvuA7C0KNuxI3aYvfBIDj2E6 4o5XIn5loUghxa9RLiMAYIYBTTLDO36Wubax6tfjeURJHiFAYRdrsiZEDMf7DUQiWrmG 1tRPaij6byl4BAT8P+zVJZwg5eOUKy0JurzWWb+moPtlWbKtBUwZ7BduY8zgYJK5shu9 cM59jUKny9IMD9ZflOxxP0UMui7NKT6VPlgtOOIDIlVo2FusS9e+QMcz3gm2HchFseaM XgzuUUaTuB75qjHHaGa8EtPYXtbo1Pyj1B+o++NXDBYKQ3KFDaWIR9LYdlK8oYnBli/0 nUeA== X-Gm-Message-State: AOJu0YxDTPtSSovlmWF6ItfOMXEfhWXT/qjS7Nvd6TJqD59HocWmXUUm i/bdN+hGjIlFnyemY+6P7fOlOFlsulmWQeqkDE5tH0S40foVyjx8z2WEeNYTdw== X-Gm-Gg: AeBDievu8oOpC2LX+h55udKrwlbZppy0Vhg5Z3gDOE8dwOttHsh+xIUiJeJh4275hRJ ijA9dgULWk97bJzt6gUa3Ppwm+/nKtb3YtDzQnaYrk6kWGwQek4OVxdrIWLdyndHFft3UNu9vVr pnNP1Pj3lgnI5Fku7f18sWrAZe/KYvlONqwwijNZss0Ad/x8ckgIwrgj/aJMc9sxYb7iX8yhbi2 DlE3Vd0SDbUtpbV4H06VOoa5U54aoiQR8eI8GnPOGqXQ+CV8tB6D7Ssm3orLj5vc0oEC1p/YMDh GYNVBj9B/ZTLTZJkdOfHGsHVXHErWV3SjZZtiz1+2nYoYl+xiKg+rVeF80H5X+aBOfG8zCWe8Bk RTOhA1alY+kmt0zwLsqglZckOjh7ocaXhGj4ZZlu0FS/v8/jUa9u9xl6NQdtuVdrnsE/7N6yqPZ 9KZwDN5XZC+8kIAHURd/1oRI3Q0mRUJAWmOwcoBzzUdO34POZBG2c8kab7BjMojkyAHJuKbGfWC HHVNuvHdvnVWZM= X-Received: by 2002:a05:600c:3b15:b0:488:9439:881a with SMTP id 5b1f17b1804b1-48a77ae5448mr61360215e9.2.1777386833911; Tue, 28 Apr 2026 07:33:53 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 04/11] xen: introduce domain-layout.h with common domain_use_host_layout() Date: Tue, 28 Apr 2026 16:33:33 +0200 Message-ID: <2577e757d32f85fb8b3308863e6d7a53d70636dc.1777303844.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1777386834-BC410FF4-DCFBBF00/10/73395122804 X-purgate-type: spam X-purgate-size: 5464 domain_use_host_layout() is not architecture-specific and may be needed on x86 [1]. Replace the ARM-specific macro in asm/domain.h with a common static inline in a new dedicated header, xen/domain-layout.h. xen/domain.h would be the natural home, but placing it there would require including xen/paging.h (for paging_mode_translate()) and xen/sched.h (for is_hardware_domain()), which would introduce circular dependencies. A separate header that callers opt into avoids this. Adjust the implementation to take paging_mode_translate() into account so it works correctly for all architectures, including x86. Some extra details about implementation [2] and [3]. [1] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602161038120.359097@ubuntu-linux-20-04-desktop/ [2] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602271742400.3148344@ubuntu-linux-20-04-desktop/ [3] https://lore.kernel.org/xen-devel/alpine.DEB.2.22.394.2602271750190.3148344@ubuntu-linux-20-04-desktop/ Suggested-by: Stefano Stabellini Signed-off-by: Oleksii Kurochko --- Changes in v4: - Update the comment above domain_use_host_layout(). --- Changes in v3: - Make argument of domain_use_host_layout() const. - Create a separate header to avoid circular heder dependecy and making domain_use_host_layour() as static inline. - Rework domain_use_host_layout() to be protected by paging_mode_translate(). - Update the commit message. --- Changes in v2: - Drop ifdef around defintion of domain_use_host_layout() as it was suggested generic version. It could be returned back when the real use case for it will appear. - Add Suggested-by: and update the commit message. - Make domain_use_host_layout() function instead of macros to avoid ciclular header dependecies. Look at more details in the commit message. --- --- xen/arch/arm/domain_build.c | 1 + xen/arch/arm/include/asm/domain.h | 14 -------------- xen/arch/arm/vgic-v3.c | 1 + xen/common/device-tree/domain-build.c | 1 + xen/include/xen/domain-layout.h | 27 +++++++++++++++++++++++++++ 5 files changed, 30 insertions(+), 14 deletions(-) create mode 100644 xen/include/xen/domain-layout.h diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index ad665cd3c045..1efddc60ef0a 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h index b24f02d269be..46a5cdc0c800 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -18,20 +18,6 @@ struct hvm_domain uint64_t params[HVM_NR_PARAMS]; }; -/* - * Is the domain using the host memory layout? - * - * Direct-mapped domain will always have the RAM mapped with GFN == MFN. - * To avoid any trouble finding space, it is easier to force using the - * host memory layout. - * - * The hardware domain will use the host layout regardless of - * direct-mapped because some OS may rely on a specific address ranges - * for the devices. - */ -#define domain_use_host_layout(d) (is_domain_direct_mapped(d) || \ - is_hardware_domain(d)) - struct vtimer { struct vcpu *v; int irq; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 77aab5c3c293..77517c303061 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree/domain-build.c index c51520ebadf9..6949203dacdc 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include diff --git a/xen/include/xen/domain-layout.h b/xen/include/xen/domain-layout.h new file mode 100644 index 000000000000..0532a27b44ce --- /dev/null +++ b/xen/include/xen/domain-layout.h @@ -0,0 +1,27 @@ +#ifndef __XEN_DOMAIN_LAYOUT_H__ +#define __XEN_DOMAIN_LAYOUT_H__ + +#include +#include +#include + +/* + * Is a domain using the host memory layout? + * + * domain_use_host_layout() is always False for PV domains (including Dom0). + * + * Direct-mapped domains (autotranslated domains with memory allocated + * contiguously and mapped 1:1 so that GFN == MFN) must use the host + * memory layout since GFN == MFN by definition. + * + * The hardware domain will use the host layout (regardless of + * direct-mapped) because some OS may rely on specific address ranges + * for the devices. + */ +static inline bool domain_use_host_layout(const struct domain *d) +{ + return paging_mode_translate(d) && + (is_domain_direct_mapped(d) || is_hardware_domain(d)); +} + +#endif /* __XEN_DOMAIN_LAYOUT_H__ */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296327.1572743 (Exim 4.92) (envelope-from ) id 1wHjVX-0005ET-5q; Tue, 28 Apr 2026 14:33:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296327.1572743; Tue, 28 Apr 2026 14:33:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVX-0005EM-1y; Tue, 28 Apr 2026 14:33:51 +0000 Received: by outflank-mailman (input) for mailman id 1296327; Tue, 28 Apr 2026 14:33:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVW-0005EG-Gj for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVV-000RTW-Nw for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:49 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c548-2eae-0a2a0a5409dd-0a2a4501d626-10 for ; Tue, 28 Apr 2026 16:33:49 +0200 Received: from [209.85.128.48] (helo=mail-wm1-f48.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c54d-c1f2-0a2a45010019-d1558030ccf7-3 for ; Tue, 28 Apr 2026 16:33:49 +0200 Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-48984d29fe3so139789325e9.0 for ; Tue, 28 Apr 2026 07:33:49 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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This patch series is rebased on top of [PATCH v3 0/3] dom0less: various updates as it could be some merge conflicts depends on which patch series will go first. CI: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2477740734 --- Changes in v4: - Move patch up, closer to other common/Arm related patches: - xen/dom0less: rename kernel_zimage_probe() to kernel_image_probe() - xen: move declaration of fw_unreserved_regions() to common header - xen: move domain_use_host_layout() to common header - xen: rename p2m_ipa_bits to p2m_gpa_bits - Merged to upstream/staging: xen/riscv: implement get_page_from_gfn() - Rebase this patch series on top of [PATCH v3 0/3] dom0less: various updates. - Address the comments from ML. --- Changes in v3: - Address the comments from ML. --- Changes in v2: - Address the comments from ML. - Introduce some new patches to make dom0less solution more architecture indepenent from terminology point of view. - Minor fixes. --- Oleksii Kurochko (11): xen: arm: fix len type for guest copy functions xen/dom0less: rename kernel_zimage_probe() to kernel_image_probe() xen: move declaration of fw_unreserved_regions() to common header xen: introduce domain-layout.h with common domain_use_host_layout() xen: rename p2m_ipa_bits to p2m_gpa_bits xen/riscv: implement copy_to_guest_phys() xen/riscv: add Linux kernel loading support xen/riscv: rework G-stage mode handling xen/riscv: introduce p2m_gpa_bits xen/riscv: add definition of guest RAM banks xen/riscv: enable DOMAIN_BUILD_HELPERS xen/arch/arm/domain_build.c | 1 + xen/arch/arm/guestcopy.c | 6 +- xen/arch/arm/include/asm/domain.h | 14 -- xen/arch/arm/include/asm/guest_access.h | 2 +- xen/arch/arm/include/asm/p2m.h | 2 + xen/arch/arm/include/asm/setup.h | 3 - xen/arch/arm/kernel.c | 48 ++--- xen/arch/arm/vgic-v3.c | 1 + xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/Makefile | 3 + xen/arch/riscv/dom0less-build.c | 70 +++++++ xen/arch/riscv/guestcopy.c | 116 +++++++++++ xen/arch/riscv/include/asm/config.h | 13 ++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/include/asm/guest-layout.h | 23 ++ xen/arch/riscv/include/asm/guest_access.h | 7 + xen/arch/riscv/include/asm/p2m.h | 21 +- xen/arch/riscv/kernel.c | 242 ++++++++++++++++++++++ xen/arch/riscv/p2m.c | 133 ++++++++---- xen/arch/riscv/vmid.c | 2 +- xen/common/device-tree/domain-build.c | 3 +- xen/common/device-tree/kernel.c | 2 +- xen/include/public/arch-riscv.h | 5 + xen/include/xen/bootinfo.h | 4 + xen/include/xen/domain-layout.h | 27 +++ xen/include/xen/fdt-domain-build.h | 2 +- xen/include/xen/fdt-kernel.h | 15 +- 27 files changed, 670 insertions(+), 97 deletions(-) create mode 100644 xen/arch/riscv/dom0less-build.c create mode 100644 xen/arch/riscv/guestcopy.c create mode 100644 xen/arch/riscv/include/asm/guest-layout.h create mode 100644 xen/arch/riscv/kernel.c create mode 100644 xen/include/xen/domain-layout.h -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296328.1572751 (Exim 4.92) (envelope-from ) id 1wHjVY-0005Rd-E6; Tue, 28 Apr 2026 14:33:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296328.1572751; Tue, 28 Apr 2026 14:33:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVY-0005RW-Ax; Tue, 28 Apr 2026 14:33:52 +0000 Received: by outflank-mailman (input) for mailman id 1296328; Tue, 28 Apr 2026 14:33:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVX-0005Hz-Hc for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:51 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVV-00H4ZK-Bv for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:50 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c541-5cb7-0a2a0a5109dd-0a2a45029a8e-46 for ; Tue, 28 Apr 2026 16:33:50 +0200 Received: from [209.85.128.51] (helo=mail-wm1-f51.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c54e-af86-0a2a45020019-d1558033ed58-3 for ; Tue, 28 Apr 2026 16:33:50 +0200 Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4891e86fabeso127801705e9.1 for ; Tue, 28 Apr 2026 07:33:50 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Update the internal copy_guest() len argument to unsigned long accordingly. Change the type for local variable size in copy_guest() to avoid compilation error because of type mismatch. raw_* wrappers above copy_guest() keep returning unsigned long to avoid type narrowing; it is not an issue for raw_*'s len argument to remain 'unsigned int' since the assignment to copy_guest()'s wider unsigned long parameter is safe and there is no raw_* users who are using a value bigger than what can fit into 'unsigned int'. Fixes: 2986481b3d9e6 ("xen/arm: guest_copy: Extend the prototype to pass the vCPU") Fixes: 5302bd490bea7 ("xen/arm: Introduce copy_to_guest_phys_flush_dcache") Fixes: d07b7369aa65b ("xen/common: dom0less: introduce common domain-build.c") Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in v4: - Add Fixes: tags. - Add "arm:" prefix to commit subject. - Add Reviewed-by: Jan Beulich . - Avoid using of min_t. --- Changes in v3: - Correct the declaration of copy_to_guest_phys_cb() instead of return 'unsigned int' to be in sync with len argument, the type of len argument is changed on 'unsigned long' as initrd could be pretty big and also its size is stroed in 'paddr_t' which is 'unsigned long'. - Update copy_guest() prototype to avoid trancation bug for len argument. - Revert prototype changes for raw_* wrappers above copy_guest() as they should keep returning unsigned long to avoid type narrowing; it is not an issue for raw_*'s len argument to remain 'unsigned int' since the assignment to copy_guest()'s wider unsigned long parameter is safe. - Change the type for local variable size in copy_guest() to avoid compilation error because of type mismatch. - Add Reported-by: Jan Beulich --- Changes in v2: - New patch. --- --- xen/arch/arm/guestcopy.c | 6 +++--- xen/arch/arm/include/asm/guest_access.h | 2 +- xen/include/xen/fdt-domain-build.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/guestcopy.c b/xen/arch/arm/guestcopy.c index fdb06422b8e9..86f1c9d0e318 100644 --- a/xen/arch/arm/guestcopy.c +++ b/xen/arch/arm/guestcopy.c @@ -53,7 +53,7 @@ static struct page_info *translate_get_page(copy_info_t info, uint64_t addr, return page; } -static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, +static unsigned long copy_guest(void *buf, uint64_t addr, unsigned long len, copy_info_t info, unsigned int flags) { /* XXX needs to handle faults */ @@ -65,7 +65,7 @@ static unsigned long copy_guest(void *buf, uint64_t addr, unsigned int len, while ( len ) { void *p; - unsigned int size = min(len, (unsigned int)PAGE_SIZE - offset); + unsigned long size = min(len, PAGE_SIZE + 0UL - offset); struct page_info *page; page = translate_get_page(info, addr, flags & COPY_linear, @@ -136,7 +136,7 @@ unsigned long raw_copy_from_guest(void *to, const void __user *from, unsigned long copy_to_guest_phys_flush_dcache(struct domain *d, paddr_t gpa, void *buf, - unsigned int len) + unsigned long len) { return copy_guest(buf, gpa, len, GPA_INFO(d), COPY_to_guest | COPY_ipa | COPY_flush_dcache); diff --git a/xen/arch/arm/include/asm/guest_access.h b/xen/arch/arm/include/asm/guest_access.h index 18c88b70d7ec..c13cbec55b65 100644 --- a/xen/arch/arm/include/asm/guest_access.h +++ b/xen/arch/arm/include/asm/guest_access.h @@ -14,7 +14,7 @@ unsigned long raw_clear_guest(void *to, unsigned int len); unsigned long copy_to_guest_phys_flush_dcache(struct domain *d, paddr_t gpa, void *buf, - unsigned int len); + unsigned long len); int access_guest_memory_by_gpa(struct domain *d, paddr_t gpa, void *buf, uint32_t size, bool is_write); diff --git a/xen/include/xen/fdt-domain-build.h b/xen/include/xen/fdt-domain-build.h index bc7744270c8f..6ad9e8fd1642 100644 --- a/xen/include/xen/fdt-domain-build.h +++ b/xen/include/xen/fdt-domain-build.h @@ -48,7 +48,7 @@ static inline int get_allocation_size(paddr_t size) typedef unsigned long (*copy_to_guest_phys_cb)(struct domain *d, paddr_t gpa, void *buf, - unsigned int len); + unsigned long len); void initrd_load(struct kernel_info *kinfo, copy_to_guest_phys_cb cb); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296333.1572782 (Exim 4.92) (envelope-from ) id 1wHjVd-0006CN-KB; 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No functional changes. Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in v4: - Nothing changed only rebase. --- Changes in v3: - Introduce #define p2m_gpa_bits p2m_ipa_bits for Arm instead of renaming of p2m_ipa_bits to p2m_gpa_bits to keep Arm part of changes clearer and keep using Arm-specific terminolgy inside Arm code. --- Changes in v2: - New patch. --- --- xen/arch/arm/include/asm/p2m.h | 2 ++ xen/common/device-tree/domain-build.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..7957dbd96e57 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -14,6 +14,8 @@ /* Holds the bit size of IPAs in p2m tables. */ extern unsigned int p2m_ipa_bits; +#define p2m_gpa_bits p2m_ipa_bits + #define MAX_VMID_8_BIT (1UL << 8) #define MAX_VMID_16_BIT (1UL << 16) diff --git a/xen/common/device-tree/domain-build.c b/xen/common/device-tree/domain-build.c index 6949203dacdc..2a760b007b57 100644 --- a/xen/common/device-tree/domain-build.c +++ b/xen/common/device-tree/domain-build.c @@ -221,7 +221,7 @@ int __init find_unallocated_memory(const struct kernel_info *kinfo, } start = 0; - end = (1ULL << p2m_ipa_bits) - 1; + end = (1ULL << p2m_gpa_bits) - 1; res = rangeset_report_ranges(unalloc_mem, PFN_DOWN(start), PFN_DOWN(end), cb, free_regions); if ( res ) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296331.1572769 (Exim 4.92) (envelope-from ) id 1wHjVb-0005th-TE; Tue, 28 Apr 2026 14:33:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296331.1572769; Tue, 28 Apr 2026 14:33:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVb-0005ta-PJ; Tue, 28 Apr 2026 14:33:55 +0000 Received: by outflank-mailman (input) for mailman id 1296331; Tue, 28 Apr 2026 14:33:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVa-0005fQ-Ie for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:54 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVZ-008e9B-Ur for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:53 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c540-e002-0a2a0a5209dd-0a2a4503cd3a-28 for ; Tue, 28 Apr 2026 16:33:53 +0200 Received: from [209.85.128.52] (helo=mail-wm1-f52.google.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c551-672d-0a2a45030019-d1558034d159-3 for ; Tue, 28 Apr 2026 16:33:53 +0200 Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4891cd41959so98298555e9.3 for ; Tue, 28 Apr 2026 07:33:53 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Signed-off-by: Oleksii Kurochko --- Changes in v2-v4: - Nothing changed. Only rebase. --- --- xen/arch/arm/include/asm/setup.h | 3 --- xen/include/xen/bootinfo.h | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/setup.h index 899e33925ca4..0d29b46ea52b 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -43,9 +43,6 @@ int acpi_make_efi_nodes(void *fdt, struct membank tbl_add[]); void create_dom0(void); void discard_initial_modules(void); -void fw_unreserved_regions(paddr_t s, paddr_t e, - void (*cb)(paddr_t ps, paddr_t pe), - unsigned int first); void init_pdx(void); void setup_mm(void); diff --git a/xen/include/xen/bootinfo.h b/xen/include/xen/bootinfo.h index f834f1957155..dbf492c2e36e 100644 --- a/xen/include/xen/bootinfo.h +++ b/xen/include/xen/bootinfo.h @@ -210,4 +210,8 @@ static inline struct membanks *membanks_xzalloc(unsigned int nr, return banks; } +void fw_unreserved_regions(paddr_t s, paddr_t e, + void (*cb)(paddr_t ps, paddr_t pe), + unsigned int first); + #endif /* XEN_BOOTINFO_H */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296329.1572760 (Exim 4.92) (envelope-from ) id 1wHjVa-0005fk-Mm; Tue, 28 Apr 2026 14:33:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296329.1572760; Tue, 28 Apr 2026 14:33:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVa-0005fc-IH; Tue, 28 Apr 2026 14:33:54 +0000 Received: by outflank-mailman (input) for mailman id 1296329; Tue, 28 Apr 2026 14:33:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVZ-0005Yo-0t for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:33:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVY-002Kdm-D9 for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:33:52 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c54a-bab6-0a2a0a5309dd-0a2a450cd3a8-18 for ; Tue, 28 Apr 2026 16:33:52 +0200 Received: from [209.85.128.50] (helo=mail-wm1-f50.google.com) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c550-62f1-0a2a450c0019-d1558032e53e-3 for ; Tue, 28 Apr 2026 16:33:52 +0200 Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso120333005e9.1 for ; Tue, 28 Apr 2026 07:33:52 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Other architectures supported by Xen, such as RISC-V, do not use the zImage format and instead rely on other kernel image types (e.g. Image or compressed Image variants: Image.gz, etc). Using "zimage" in the name is therefore misleading in architecture-independent code. Rename kernel_zimage_probe() to kernel_image_probe() and update the associated structure field from "zimage" to "image" to reflect that the code handles generic kernel images rather than the zImage format specifically. No functional change intended. Reported-by: Jan Beulich Signed-off-by: Oleksii Kurochko --- Changes in v3-4: - Nothing changed. Only rebase. --- Changes in v2: - new patch. --- --- xen/arch/arm/kernel.c | 48 ++++++++++++++++----------------- xen/common/device-tree/kernel.c | 2 +- xen/include/xen/fdt-kernel.h | 4 +-- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 9395b5af8745..a5554714cd7b 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -101,8 +101,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) paddr_t load_addr; #ifdef CONFIG_HAS_DOMAIN_TYPE - if ( (info->type == DOMAIN_64BIT) && (info->zimage.start == 0) ) - return mem->bank[0].start + info->zimage.text_offset; + if ( (info->type == DOMAIN_64BIT) && (info->image.start == 0) ) + return mem->bank[0].start + info->image.text_offset; #endif /* @@ -111,19 +111,19 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) * and above 32MiB. Load it as high as possible within these * constraints, while also avoiding the DTB. */ - if ( info->zimage.start == 0 ) + if ( info->image.start == 0 ) { paddr_t load_end; load_end = mem->bank[0].start + mem->bank[0].size; load_end = MIN(mem->bank[0].start + MB(128), load_end); - load_addr = load_end - info->zimage.len; + load_addr = load_end - info->image.len; /* Align to 2MB */ load_addr &= ~((2 << 20) - 1); } else - load_addr = info->zimage.start; + load_addr = info->image.start; return load_addr; } @@ -131,8 +131,8 @@ static paddr_t __init kernel_zimage_place(struct kernel_info *info) static void __init kernel_zimage_load(struct kernel_info *info) { paddr_t load_addr = kernel_zimage_place(info); - paddr_t paddr = info->zimage.kernel_addr; - paddr_t len = info->zimage.len; + paddr_t paddr = info->image.kernel_addr; + paddr_t len = info->image.len; void *kernel; int rc; @@ -215,7 +215,7 @@ int __init kernel_uimage_probe(struct kernel_info *info, return -EOPNOTSUPP; } - info->zimage.start = be32_to_cpu(uimage.load); + info->image.start = be32_to_cpu(uimage.load); info->entry = be32_to_cpu(uimage.ep); /* @@ -224,20 +224,20 @@ int __init kernel_uimage_probe(struct kernel_info *info, * independent image. That means Xen is free to load such an image at * any valid address. */ - if ( info->zimage.start == 0 ) + if ( info->image.start == 0 ) printk(XENLOG_INFO "No load address provided. Xen will decide where to load it.\n"); else printk(XENLOG_INFO "Provided load address: %"PRIpaddr" and entry address: %"PRIpaddr"\n", - info->zimage.start, info->entry); + info->image.start, info->entry); /* * If the image supports position independent execution, then user cannot * provide an entry point as Xen will load such an image at any appropriate * memory address. Thus, we need to return error. */ - if ( (info->zimage.start == 0) && (info->entry != 0) ) + if ( (info->image.start == 0) && (info->entry != 0) ) { printk(XENLOG_ERR "Entry point cannot be non zero for PIE image.\n"); @@ -257,13 +257,13 @@ int __init kernel_uimage_probe(struct kernel_info *info, if ( rc ) return rc; - info->zimage.kernel_addr = mod->start; - info->zimage.len = mod->size; + info->image.kernel_addr = mod->start; + info->image.len = mod->size; } else { - info->zimage.kernel_addr = addr + sizeof(uimage); - info->zimage.len = len; + info->image.kernel_addr = addr + sizeof(uimage); + info->image.len = len; } info->load = kernel_zimage_load; @@ -289,7 +289,7 @@ int __init kernel_uimage_probe(struct kernel_info *info, * Thus, Xen uses uimage.load attribute to determine the load address and * zimage.text_offset is ignored. */ - info->zimage.text_offset = 0; + info->image.text_offset = 0; #endif return 0; @@ -338,10 +338,10 @@ static int __init kernel_zimage64_probe(struct kernel_info *info, if ( (end - start) > size ) return -EINVAL; - info->zimage.kernel_addr = addr; - info->zimage.len = end - start; - info->zimage.text_offset = zimage.text_offset; - info->zimage.start = 0; + info->image.kernel_addr = addr; + info->image.len = end - start; + info->image.text_offset = zimage.text_offset; + info->image.start = 0; info->load = kernel_zimage_load; @@ -389,10 +389,10 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, } } - info->zimage.kernel_addr = addr; + info->image.kernel_addr = addr; - info->zimage.start = start; - info->zimage.len = end - start; + info->image.start = start; + info->image.len = end - start; info->load = kernel_zimage_load; @@ -403,7 +403,7 @@ static int __init kernel_zimage32_probe(struct kernel_info *info, return 0; } -int __init kernel_zimage_probe(struct kernel_info *info, paddr_t addr, +int __init kernel_image_probe(struct kernel_info *info, paddr_t addr, paddr_t size) { int rc; diff --git a/xen/common/device-tree/kernel.c b/xen/common/device-tree/kernel.c index 28096121a52d..cfa27464f0fc 100644 --- a/xen/common/device-tree/kernel.c +++ b/xen/common/device-tree/kernel.c @@ -235,7 +235,7 @@ int __init kernel_probe(struct kernel_info *info, if ( rc && rc != -EINVAL ) return rc; - rc = kernel_zimage_probe(info, mod->start, mod->size); + rc = kernel_image_probe(info, mod->start, mod->size); return rc; } diff --git a/xen/include/xen/fdt-kernel.h b/xen/include/xen/fdt-kernel.h index 86a37a13048b..54be77aa191e 100644 --- a/xen/include/xen/fdt-kernel.h +++ b/xen/include/xen/fdt-kernel.h @@ -63,7 +63,7 @@ struct kernel_info { paddr_t text_offset; /* 64-bit Image only */ #endif paddr_t start; /* Must be 0 for 64-bit Image */ - } zimage; + } image; }; #ifdef CONFIG_HAS_DOMAIN_TYPE @@ -133,7 +133,7 @@ void kernel_load(struct kernel_info *info); int kernel_decompress(struct boot_module *mod, uint32_t offset); -int kernel_zimage_probe(struct kernel_info *info, paddr_t addr, paddr_t size); +int kernel_image_probe(struct kernel_info *info, paddr_t addr, paddr_t size); /* * uImage isn't really used nowadays thereby leave kernel_uimage_probe() -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296342.1572814 (Exim 4.92) (envelope-from ) id 1wHjVi-0007B1-ON; Tue, 28 Apr 2026 14:34:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296342.1572814; Tue, 28 Apr 2026 14:34:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVi-0007AP-J5; Tue, 28 Apr 2026 14:34:02 +0000 Received: by outflank-mailman (input) for mailman id 1296342; Tue, 28 Apr 2026 14:34:01 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVh-0006r9-1d for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:34:01 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVg-008e9B-D6 for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:34:00 +0200 Received: from [10.42.69.1] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c556-e002-0a2a0a5209dd-0a2a4501afa6-6 for ; Tue, 28 Apr 2026 16:34:00 +0200 Received: from [209.85.128.49] (helo=mail-wm1-f49.google.com) by tlsNG-d62444.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c558-c1f2-0a2a45010019-d1558031a9e5-3 for ; Tue, 28 Apr 2026 16:34:00 +0200 Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-488b3f8fa2bso117452585e9.1 for ; Tue, 28 Apr 2026 07:34:00 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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Promote gstage_modes[] from a local __initconst variable inside gstage_mode_detect() to a file-scope static const array, and convert max_gstage_mode from an embedded struct (assigned by value) to a global const pointer into gstage_modes[]. This allows referencing both the mode identifier and the mode name after init without copying the descriptor. Remove get_max_supported_mode(); its callers now dereference max_gstage_mode->mode directly. Change struct p2m_domain::mode from an embedded gstage_mode_desc to a const pointer into gstage_modes[], so each domain shares the descriptor rather than carrying its own copy. Adjust the gstage_modes[] entries in three ways: - Use lowercase names without the "x4" suffix (e.g. "sv39" instead of "Sv39x4"). The DT mmu-type binding [1] does not include the suffix, so the name can now be passed directly to the guest without transformation. The suffix is appended only in the diagnostic printk, where it remains informative. - Use "none" for Bare mode (HGATP_MODE_OFF) to match the DT binding. - Change paging_levels to represent the root page-table level index (i.e. total paging levels minus one) rather than the total count. P2M_ROOT_LEVEL() now returns the correct VPN index directly, without requiring callers to subtract one or use hardcoded offsets. Add gstage_mode to xen_arch_domainconfig so the toolstack can request a specific G-stage mode at domain creation time. Introduce find_gstage_mode() to resolve a mode descriptor by HGATP_MODE_*, capping the result at max_gstage_mode to prevent requesting a mode the hardware does not support. Update p2m_init() to accept a xen_domctl_createdomain pointer and call find_gstage_mode() instead of hardcoding Sv39x4. Add arch_parse_dom0less_node() in a new dom0less-build.c to read the "mmu-type" DT property from a guest domain node and store it in boot_domain::create_cfg.arch.gstage_mode, falling back to maximum supported mode when the property is absent. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v6.19-rc3#n82 Signed-off-by: Oleksii Kurochko --- Changes in v4: - Stray blank after * in declaration of find_gstage_mode(). - Refactor find_gstage_mode(). Now it is find_gstage_mode_by_bits(). - Add __ro_after_init for static local variable m in p2m_init. - s/ char gstage_mode[8];/unsigned char gstage_mode; in struct vcpu_guest_context. - s/modes/gstage_modes in p2m.c. - Introduce P2M_EXTRA_BITS_AT_LEVEL and re-use P2M_ROOT_EXTRA_BITS to encode magic constant 2. --- Changes in v3: - New patch. --- --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/dom0less-build.c | 70 ++++++++++++++++++ xen/arch/riscv/include/asm/p2m.h | 18 +++-- xen/arch/riscv/p2m.c | 120 +++++++++++++++++++++---------- xen/arch/riscv/vmid.c | 2 +- xen/include/public/arch-riscv.h | 5 ++ 6 files changed, 170 insertions(+), 46 deletions(-) create mode 100644 xen/arch/riscv/dom0less-build.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index eecdcbc76867..8f7fd625dddd 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,6 +1,7 @@ obj-y += aplic.o obj-y += cpufeature.o obj-y += domain.o +obj-$(CONFIG_DOM0LESS_BOOT) += dom0less-build.init.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o obj-y += extable.o diff --git a/xen/arch/riscv/dom0less-build.c b/xen/arch/riscv/dom0less-build.c new file mode 100644 index 000000000000..02782d0f9998 --- /dev/null +++ b/xen/arch/riscv/dom0less-build.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include + +int __init arch_parse_dom0less_node(struct dt_device_node *node, + struct boot_domain *bd) +{ + const char *mmu_type; + unsigned long bits; + const char *end; + + if ( dt_property_read_string(node, "mmu-type", &mmu_type) ) + { + dprintk(XENLOG_WARNING, "mmu-type property is missing in guest domain " + "node. %s will be used as fallback\n", max_gstage_mode->name); + + bits = P2M_GFN_LEVEL_SHIFT(max_gstage_mode->paging_levels + 1); + + goto out; + } + + if ( !strcasecmp(mmu_type, "riscv,none") ) + { + dprintk(XENLOG_ERR, "Bare mode isn't supported by Xen\n"); + + return -EOPNOTSUPP; + } + + if ( strncasecmp(mmu_type, "riscv,sv", 8) ) + { + dprintk(XENLOG_ERR, "mmu-type value \"%s\" is incorrect\n", mmu_type); + + return -EINVAL; + } + + bits = simple_strtoul(mmu_type + 8, &end, 10); + if ( (*end != '\0') || (end == mmu_type + 8) ) + { + dprintk(XENLOG_ERR, "mmu-type value \"%s\" is incorrect\n", mmu_type); + + return -EINVAL; + } + + out: + if ( bits > (UINT8_MAX - P2M_ROOT_EXTRA_BITS) ) + { + dprintk(XENLOG_ERR, "gstage addr bits value overflows uint8\n"); + + return -EINVAL; + } + /* + * The correct value of bits will be checked in p2m_init() by call of + * find_gstage_mode_by_bits(). + * + * As mmu-type property contains one of string: + * - riscv,sv32 + * - riscv,sv39 + * - riscv,sv48 + * - riscv,sv57 + * it is needed to add '+P2M_ROOT_EXTRA_BITS' as for G-stage mode GPAs + * are extended by P2M_ROOT_EXTRA_BITS. + */ + bd->create_cfg.arch.gstage_addr_bits = bits + P2M_ROOT_EXTRA_BITS; + + return 0; +} diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 54ea67990f06..638c60ddc2f7 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -13,7 +13,7 @@ #define P2M_ROOT_ORDER (ilog2(GSTAGE_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT) #define P2M_ROOT_PAGES BIT(P2M_ROOT_ORDER, U) -#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode.paging_levels) +#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode->paging_levels) /* * According to the RISC-V spec: @@ -32,10 +32,13 @@ */ #define P2M_LEVEL_ORDER(lvl) XEN_PT_LEVEL_ORDER(lvl) -#define P2M_ROOT_EXTRA_BITS(p2m, lvl) (2 * ((lvl) == P2M_ROOT_LEVEL(p2m))) +#define P2M_ROOT_EXTRA_BITS 2 + +#define P2M_LEVEL_EXTRA_BITS(p2m, lvl) \ + (P2M_ROOT_EXTRA_BITS * ((lvl) == P2M_ROOT_LEVEL(p2m))) #define P2M_PAGETABLE_ENTRIES(p2m, lvl) \ - (BIT(PAGETABLE_ORDER + P2M_ROOT_EXTRA_BITS(p2m, lvl), UL)) + (BIT(PAGETABLE_ORDER + P2M_LEVEL_EXTRA_BITS(p2m, lvl), UL)) #define P2M_TABLE_OFFSET(p2m, lvl) (P2M_PAGETABLE_ENTRIES(p2m, lvl) - 1UL) @@ -55,6 +58,8 @@ struct gstage_mode_desc { char name[8]; }; +extern const struct gstage_mode_desc *max_gstage_mode; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -68,7 +73,7 @@ struct p2m_domain { /* The root of the p2m tree. May be concatenated */ struct page_info *root; - struct gstage_mode_desc mode; + const struct gstage_mode_desc *mode; /* Back pointer to domain */ struct domain *domain; @@ -215,9 +220,10 @@ static inline bool arch_acquire_resource_check(struct domain *d) } void guest_mm_init(void); -unsigned char get_max_supported_mode(void); -int p2m_init(struct domain *d); +struct xen_domctl_createdomain; + +int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config); static inline void p2m_write_lock(struct p2m_domain *p2m) { diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index adcf292a7092..13846bee6a4f 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -45,12 +45,27 @@ struct p2m_pte_ctx { unsigned int level; /* Paging level at which the PTE resides. */ }; -static struct gstage_mode_desc __ro_after_init max_gstage_mode = { - .mode = HGATP_MODE_OFF, - .paging_levels = 0, - .name = "Bare", +/* Values should be sorted by ->mode in this array */ +static const struct gstage_mode_desc gstage_modes[] = { + /* + * Based on the RISC-V spec: + * Bare mode is always supported, regardless of SXLEN. + * When SXLEN=32, the only other valid setting for MODE is Sv32. + * When SXLEN=64, three paged virtual-memory schemes are defined: + * Sv39, Sv48, and Sv57. + */ + { HGATP_MODE_OFF, 0, "none" }, +#ifdef CONFIG_RISCV_32 + { HGATP_MODE_SV32X4, 1, "sv32" }, +#else + { HGATP_MODE_SV39X4, 2, "sv39" }, + { HGATP_MODE_SV48X4, 3, "sv48" }, + { HGATP_MODE_SV57X4, 4, "sv57" }, +#endif }; +const struct gstage_mode_desc * __ro_after_init max_gstage_mode = &gstage_modes[0]; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -63,11 +78,6 @@ static inline void p2m_free_metadata_page(struct p2m_domain *p2m, } } -unsigned char get_max_supported_mode(void) -{ - return max_gstage_mode.mode; -} - /* * If anything is changed here, it may also require updates to * p2m_{get,set}_type(). @@ -148,41 +158,24 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn) static void __init gstage_mode_detect(void) { - static const struct gstage_mode_desc modes[] __initconst = { - /* - * Based on the RISC-V spec: - * Bare mode is always supported, regardless of SXLEN. - * When SXLEN=32, the only other valid setting for MODE is Sv32. - * When SXLEN=64, three paged virtual-memory schemes are defined: - * Sv39, Sv48, and Sv57. - */ -#ifdef CONFIG_RISCV_32 - { HGATP_MODE_SV32X4, 2, "Sv32x4" } -#else - { HGATP_MODE_SV39X4, 3, "Sv39x4" }, - { HGATP_MODE_SV48X4, 4, "Sv48x4" }, - { HGATP_MODE_SV57X4, 5, "Sv57x4" }, -#endif - }; - - for ( unsigned int mode_idx = ARRAY_SIZE(modes); mode_idx-- > 0; ) + for ( unsigned int mode_idx = ARRAY_SIZE(gstage_modes); mode_idx-- > 0; ) { - unsigned long mode = modes[mode_idx].mode; + unsigned long mode = gstage_modes[mode_idx].mode; csr_write(CSR_HGATP, MASK_INSR(mode, HGATP_MODE_MASK)); if ( MASK_EXTR(csr_read(CSR_HGATP), HGATP_MODE_MASK) == mode ) { - max_gstage_mode = modes[mode_idx]; + max_gstage_mode = &gstage_modes[mode_idx]; break; } } - if ( max_gstage_mode.mode == HGATP_MODE_OFF ) + if ( max_gstage_mode->mode == HGATP_MODE_OFF ) panic("Xen expects that G-stage won't be Bare mode\n"); - printk("Max supported G-stage mode is %s\n", max_gstage_mode.name); + printk("Max supported G-stage mode is %sx4\n", max_gstage_mode->name); csr_write(CSR_HGATP, 0); @@ -283,7 +276,7 @@ static void clear_and_clean_page(struct page_info *page, bool clean_dcache) unsigned long construct_hgatp(const struct p2m_domain *p2m, uint16_t vmid) { return MASK_INSR(mfn_x(page_to_mfn(p2m->root)), HGATP_PPN_MASK) | - MASK_INSR(p2m->mode.mode, HGATP_MODE_MASK) | + MASK_INSR(p2m->mode->mode, HGATP_MODE_MASK) | MASK_INSR(vmid, HGATP_VMID_MASK); } @@ -331,8 +324,35 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m) return 0; } -int p2m_init(struct domain *d) +static const struct gstage_mode_desc *find_gstage_mode_by_bits( + unsigned char gpa_bits) +{ + ASSERT(gstage_modes[0].mode == HGATP_MODE_OFF); + + for ( unsigned int i = 1; i < ARRAY_SIZE(gstage_modes); i++ ) + { + unsigned int lvl = gstage_modes[i].paging_levels + 1; + unsigned int bits = P2M_GFN_LEVEL_SHIFT(lvl) + P2M_ROOT_EXTRA_BITS; + + if ( gpa_bits == bits ) + { + if ( gstage_modes[i].mode > max_gstage_mode->mode ) + return NULL; + return &gstage_modes[i]; + } + } + + return NULL; +} + +int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) { + /* + * TODO: This static is a temporary constraint: all guests must use the + * same MMU mode because p2m_gpa_bits is not yet per-domain. + * Drop this once per-domain p2m_gpa_bits is introduced. + */ + static const struct gstage_mode_desc __ro_after_init *m = &gstage_modes[0]; struct p2m_domain *p2m = p2m_get_hostp2m(d); /* @@ -341,6 +361,33 @@ int p2m_init(struct domain *d) */ p2m->domain = d; + if ( !config ) + { + dprintk(XENLOG_ERR, "NULL config is passed\n"); + return -EINVAL; + } + + p2m->mode = find_gstage_mode_by_bits(config->arch.gstage_addr_bits); + + if ( !p2m->mode ) + { + dprintk(XENLOG_ERR, + "Unsupported or unavailable gstage addr bits: %u\n", + config->arch.gstage_addr_bits); + + return -EINVAL; + } + + if ( m->mode == HGATP_MODE_OFF ) + m = p2m->mode; + + if ( m->mode != p2m->mode->mode ) + { + dprintk(XENLOG_ERR, + "Mode should be the same for all guests at the moment\n"); + return -EINVAL; + } + paging_domain_init(d); rwlock_init(&p2m->lock); @@ -362,11 +409,6 @@ int p2m_init(struct domain *d) # error "Add init of p2m->clean_dcache" #endif - /* TODO: don't hardcode used for a domain g-stage mode. */ - p2m->mode.mode = HGATP_MODE_SV39X4; - p2m->mode.paging_levels = 2; - safe_strcpy(p2m->mode.name, "Sv39x4"); - return 0; } @@ -1304,7 +1346,7 @@ static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn, { unsigned int level = P2M_ROOT_LEVEL(p2m); unsigned int gfn_limit_bits = - P2M_LEVEL_ORDER(level + 1) + P2M_ROOT_EXTRA_BITS(p2m, level); + P2M_LEVEL_ORDER(level + 1) + P2M_LEVEL_EXTRA_BITS(p2m, level); pte_t entry, *table; int rc; mfn_t mfn = INVALID_MFN; diff --git a/xen/arch/riscv/vmid.c b/xen/arch/riscv/vmid.c index 8fbcd500f24d..11c7e9d6d6c8 100644 --- a/xen/arch/riscv/vmid.c +++ b/xen/arch/riscv/vmid.c @@ -52,7 +52,7 @@ static DEFINE_PER_CPU(struct vmid_data, vmid_data); static unsigned int vmidlen_detect(void) { unsigned int vmid_bits; - unsigned char gstage_mode = get_max_supported_mode(); + unsigned char gstage_mode = max_gstage_mode->mode; /* * According to the RISC-V Privileged Architecture Spec: diff --git a/xen/include/public/arch-riscv.h b/xen/include/public/arch-riscv.h index 360d8e6871ba..da4cc0cbfcfb 100644 --- a/xen/include/public/arch-riscv.h +++ b/xen/include/public/arch-riscv.h @@ -56,6 +56,11 @@ typedef struct vcpu_guest_context vcpu_guest_context_t; DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); struct xen_arch_domainconfig { + /* + * G-stage GPA address width in bits. + * Valid values: 34 (sv32x4), 41 (sv39x4), 50 (sv48x4), 59 (sv57x4). + */ + unsigned char gstage_addr_bits; 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The variable is initialised to PADDR_BITS and narrowed in p2m_init() to the GPA width of the selected G-stage mode, allowing an external entity (e.g. an IOMMU) to restrict it further if needed. p2m_gpa_bits is a global rather than a per-domain value, which is acceptable for now because all domains are required to use the same G-stage MMU mode, as dom0less common code allocates it per all domains. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Update initialization of p2m_gpa_bits and the comment above. - Rework how p2m_gpa_bits is limited. - Update the commit message. --- Changes in v2: - New patch. --- --- xen/arch/riscv/include/asm/p2m.h | 3 +++ xen/arch/riscv/p2m.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 638c60ddc2f7..0d1dace1a0d8 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -47,6 +47,9 @@ #define P2M_LEVEL_MASK(p2m, lvl) \ (P2M_TABLE_OFFSET(p2m, lvl) << P2M_GFN_LEVEL_SHIFT(lvl)) +/* Holds the bit size of GPAs in p2m tables */ +extern unsigned int p2m_gpa_bits; + #define paddr_bits PADDR_BITS /* Get host p2m table */ diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 13846bee6a4f..b7c36a75f175 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -11,6 +11,8 @@ #include #include +#include + #include #include #include @@ -66,6 +68,12 @@ static const struct gstage_mode_desc gstage_modes[] = { const struct gstage_mode_desc * __ro_after_init max_gstage_mode = &gstage_modes[0]; +/* + * Set to the maximum configured support for GPA bits, so the number of GPA + * bits can be restricted by an external entity (e.g. IOMMU). + */ +unsigned int __ro_after_init p2m_gpa_bits = PADDR_BITS; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -354,6 +362,7 @@ int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) */ static const struct gstage_mode_desc __ro_after_init *m = &gstage_modes[0]; struct p2m_domain *p2m = p2m_get_hostp2m(d); + unsigned int gpa_bits; /* * "Trivial" initialisation is now complete. Set the backpointer so the @@ -409,6 +418,12 @@ int p2m_init(struct domain *d, const struct xen_domctl_createdomain *config) # error "Add init of p2m->clean_dcache" #endif + gpa_bits = P2M_GFN_LEVEL_SHIFT(p2m->mode->paging_levels + 1) + + P2M_ROOT_EXTRA_BITS; + + if ( gpa_bits < p2m_gpa_bits ) + p2m_gpa_bits = gpa_bits; + return 0; } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296346.1572831 (Exim 4.92) (envelope-from ) id 1wHjVl-0007kE-Gq; Tue, 28 Apr 2026 14:34:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296346.1572831; Tue, 28 Apr 2026 14:34:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVl-0007k0-D8; Tue, 28 Apr 2026 14:34:05 +0000 Received: by outflank-mailman (input) for mailman id 1296346; Tue, 28 Apr 2026 14:34:03 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVj-0007G6-Bo for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:34:03 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVi-008eCF-N5 for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:34:02 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c54f-e002-0a2a0a5209dd-0a2a45029ad4-34 for ; Tue, 28 Apr 2026 16:34:02 +0200 Received: from [209.85.128.53] (helo=mail-wm1-f53.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c55a-af86-0a2a45020019-d1558035cc99-3 for ; Tue, 28 Apr 2026 16:34:02 +0200 Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-48984d29fe3so139792575e9.0 for ; Tue, 28 Apr 2026 07:34:02 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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The reason for 2 banks is that there is typically always a use case for low memory under 4 GB, but the bank under 4 GB ends up being small because there are other things under 4 GB it can conflict with (interrupt controller, PCI BARs, etc.). So a second bank is added above that MMIO region (starting at 8 GiB) to provide the remaining RAM; the gap between the two banks also exercises code paths handling discontiguous memory. For Sv32 guests (34-bit GPA, 16 GiB addressable), bank0 provides 2 GB (2–4 GB) and the first 8 GB of bank1 (8–16 GB) is accessible. Extended regions are useful for RISC-V: they could be used to provide a "space" for Linux to map grant mappings. Despite the fact that for every guest MMU mode the GPA could be up to 56 bits wide (except Sv32 whose GPA is 34 bits), the combined size of both banks is limited to 1018 GB as it is more than enough for most use cases. Add inclusion of asm/guest-layout.h to asm/domain.h to make dom0less common code build happy. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Add Acked-by: Jan Beulich . --- Changes in v3: - Move GUEST_RAM*-related defines to asm/p2m.h instead of public header. --- Changes in v2: - New patch. --- --- xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/include/asm/guest-layout.h | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest-layout.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h index 6c48bf13111d..6044ce0feee0 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -7,6 +7,7 @@ #include #include +#include #include #include diff --git a/xen/arch/riscv/include/asm/guest-layout.h b/xen/arch/riscv/include/asm/guest-layout.h new file mode 100644 index 000000000000..68d95a09394c --- /dev/null +++ b/xen/arch/riscv/include/asm/guest-layout.h @@ -0,0 +1,23 @@ +#ifndef ASM_RISCV_GUEST_LAYOUT_H +#define ASM_RISCV_GUEST_LAYOUT_H + +#include + +#define GUEST_RAM_BANKS 2 + +/* + * The way to find the extended regions (to be exposed to the guest as unused + * address space) relies on the fact that the regions reserved for the RAM + * below are big enough to also accommodate such regions. + */ +#define GUEST_RAM0_BASE xen_mk_ullong(0x80000000) /* 2GB of low RAM @ 2GB */ +#define GUEST_RAM0_SIZE xen_mk_ullong(0x80000000) + +#define GUEST_RAM1_BASE xen_mk_ullong(0x0200000000) /* 1016 GB of RAM @ 8GB */ +#define GUEST_RAM1_SIZE xen_mk_ullong(0xFE00000000) + +/* TODO: allocate these all dynamically */ +#define GUEST_RAM_BANK_BASES { GUEST_RAM0_BASE, GUEST_RAM1_BASE } +#define GUEST_RAM_BANK_SIZES { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE } + +#endif /* ASM_RISCV_GUEST_LAYOUT_H */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 14:34:17 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 14:34:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296350.1572841 (Exim 4.92) (envelope-from ) id 1wHjVn-00082X-D4; Tue, 28 Apr 2026 14:34:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296350.1572841; Tue, 28 Apr 2026 14:34:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHjVn-00082A-3n; Tue, 28 Apr 2026 14:34:07 +0000 Received: by outflank-mailman (input) for mailman id 1296350; Tue, 28 Apr 2026 14:34:05 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wHjVl-0007k2-Jh for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 14:34:05 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHjVk-008eCF-VT for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 16:34:04 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0c54f-e002-0a2a0a5209dd-0a2a45029ad4-42 for ; Tue, 28 Apr 2026 16:34:04 +0200 Received: from [209.85.128.46] (helo=mail-wm1-f46.google.com) by tlsNG-720697.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0c55c-af86-0a2a45020019-d155802ec4ff-3 for ; Tue, 28 Apr 2026 16:34:04 +0200 Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-48a563e4ef7so80811895e9.0 for ; Tue, 28 Apr 2026 07:34:04 -0700 (PDT) Received: from fedora (user-109-243-69-121.play-internet.pl. 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So enable it. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Nothing changed. Only rebase. --- Changes in v3: - Add Acked-by: Jan Beulich . --- Changes in v2: - Move introduction of p2m_ipa_bits to separate patch. - Move to separate patch introduction of guest banks constansts. --- --- xen/arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index a5e87c1757f7..41426c205292 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -1,5 +1,6 @@ config RISCV def_bool y + select DOMAIN_BUILD_HELPERS select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME select GENERIC_UART_INIT -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 15:08:49 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 15:08:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296443.1572849 (Exim 4.92) (envelope-from ) id 1wHk3H-0000f6-VL; Tue, 28 Apr 2026 15:08:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296443.1572849; Tue, 28 Apr 2026 15:08:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHk3H-0000eF-SS; Tue, 28 Apr 2026 15:08:43 +0000 Received: by outflank-mailman (input) for mailman id 1296443; Tue, 28 Apr 2026 15:08:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHk3F-0000dY-TA for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 15:08:42 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHk3E-002A37-RW for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 17:08:40 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0cd66-2eae-0a2a0a5409dd-0a2a4506b508-22 for ; Tue, 28 Apr 2026 17:08:40 +0200 Received: from [170.10.133.124] (helo=us-smtp-delivery-124.mimecast.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0cd77-7371-0a2a45060019-aa0a857cbd4f-3 for ; Tue, 28 Apr 2026 17:08:40 +0200 Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-104-r7s6JQv5MNe2Zdx2qkUipg-1; Tue, 28 Apr 2026 11:08:34 -0400 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 133DF1955DBD; Tue, 28 Apr 2026 15:08:23 +0000 (UTC) Received: from localhost (unknown [10.44.24.6]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6C10F19560AB; Tue, 28 Apr 2026 15:08:18 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=mimecast20190719 header.d=redhat.com header.i="@redhat.com" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1777388919; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=twk5bN/c9zdW8WMPP3xJRHocmGhqop4Vir91q7y6U9w=; b=fZvNtB2/ILa3fu/JiTM+GKsKxPmZXj28jvoI8ohXMedbr1bkYdvq9ZjEVqtVppoo9UH18N aSkBEpfCV+FJljg54oByOfrUaMT0GNCYncjAXcYkAkKV+bc1LuQNFGRGt0g+jDU1DQNfgg HCYxfh1XAyu/rECa2wank6mfP6aqu4g= X-MC-Unique: r7s6JQv5MNe2Zdx2qkUipg-1 X-Mimecast-MFC-AGG-ID: r7s6JQv5MNe2Zdx2qkUipg_1777388904 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Cc: stefanha@gmail.com, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Jan Kiszka , Peter Maydell , Phil Dennis-Jordan , Richard Henderson , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Mark Cave-Ayland , Samuel Tardieu , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Rikalo , Jean-Christophe Dubois , Laurent Vivier , Thomas Huth , BALATON Zoltan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Akihiko Odaki , Dmitry Osipenko , "Michael S. Tsirkin" , Dmitry Fleytman , Stefano Stabellini , Anthony PERARD , "Edgar E. Iglesias" , Alistair Francis , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org (open list:Musicpal), qemu-ppc@nongnu.org (open list:sam460ex), xen-devel@lists.xenproject.org (open list:X86 Xen CPUs) Subject: [PULL v2 08/15] ui/console: return completion status from gfx_update callback Date: Tue, 28 Apr 2026 19:07:18 +0400 Message-ID: <20260428150726.1659814-9-marcandre.lureau@redhat.com> In-Reply-To: <20260428150726.1659814-1-marcandre.lureau@redhat.com> References: <20260428150726.1659814-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 X-Mimecast-MFC-PROC-ID: sjUX8DwUVZCFWnYgRkqZ3gnYgstR0aReOnVkYYln-Zg_1777388904 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1777388920-9087DD75-7BD5C48B/0/0 X-purgate-type: clean X-purgate-size: 34166 From: Marc-André Lureau Replace the two-field design (gfx_update void callback + gfx_update_async flag) with a single bool return value from gfx_update. Returning true means the update completed synchronously and graphic_hw_update_done() should be called by the console layer. Returning false means the update is deferred and the device will call graphic_hw_update_done() itself later (as done by QXL/SPICE and Apple GFX). This simplifies the interface and makes the async contract explicit at each call site rather than relying on a separate struct field. Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé --- hw/display/qxl.h | 2 +- include/ui/console.h | 11 ++++++++--- hw/arm/musicpal.c | 3 ++- hw/display/artist.c | 4 +++- hw/display/bcm2835_fb.c | 7 ++++--- hw/display/bochs-display.c | 6 ++++-- hw/display/cg3.c | 5 +++-- hw/display/dm163.c | 4 +++- hw/display/exynos4210_fimd.c | 6 ++++-- hw/display/g364fb.c | 9 ++++++--- hw/display/imx6ul_lcdif.c | 7 ++++--- hw/display/jazz_led.c | 6 ++++-- hw/display/macfb.c | 6 ++++-- hw/display/next-fb.c | 4 +++- hw/display/omap_lcdc.c | 14 ++++++++------ hw/display/pl110.c | 5 +++-- hw/display/qxl-render.c | 6 +++--- hw/display/qxl.c | 7 +++---- hw/display/ramfb-standalone.c | 4 +++- hw/display/sm501.c | 8 +++++--- hw/display/ssd0303.c | 10 ++++++---- hw/display/ssd0323.c | 11 ++++++----- hw/display/tcx.c | 6 ++++-- hw/display/vga.c | 4 +++- hw/display/virtio-gpu-base.c | 3 ++- hw/display/virtio-vga.c | 6 +++--- hw/display/vmware_vga.c | 7 ++++--- hw/display/xenfb.c | 6 ++++-- hw/display/xlnx_dp.c | 10 ++++++---- hw/vfio/display.c | 17 ++++++++++------- ui/console.c | 7 +------ hw/display/apple-gfx.m | 10 +++++----- 32 files changed, 132 insertions(+), 89 deletions(-) diff --git a/hw/display/qxl.h b/hw/display/qxl.h index e0a85a5ca49..ad8a9128785 100644 --- a/hw/display/qxl.h +++ b/hw/display/qxl.h @@ -187,7 +187,7 @@ int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext); /* qxl-render.c */ void qxl_render_resize(PCIQXLDevice *qxl); -void qxl_render_update(PCIQXLDevice *qxl); +bool qxl_render_update(PCIQXLDevice *qxl); int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext); void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie); void qxl_render_update_area_bh(void *opaque); diff --git a/include/ui/console.h b/include/ui/console.h index f04844263b9..0bc9e544fad 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -368,9 +368,14 @@ enum { typedef struct GraphicHwOps { int (*get_flags)(void *opaque); /* optional, default 0 */ void (*invalidate)(void *opaque); - void (*gfx_update)(void *opaque); - bool gfx_update_async; /* if true, calls graphic_hw_update_done() */ - void (*text_update)(void *opaque, console_ch_t *text); + /* + * Returns true if the update is handled synchronously, false if deferred + * and graphic_hw_update_done() will be called when ready (to resume waiting + * tasks/coroutines). + * Optional. + */ + bool (*gfx_update)(void *opaque); + void (*text_update)(void *opaque, uint32_t *text); void (*ui_info)(void *opaque, uint32_t head, QemuUIInfo *info); void (*gl_block)(void *opaque, bool block); } GraphicHwOps; diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 441a11100a3..ba88ed756e2 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -152,7 +152,7 @@ static inline void set_lcd_pixel32(musicpal_lcd_state *s, } } -static void lcd_refresh(void *opaque) +static bool lcd_refresh(void *opaque) { musicpal_lcd_state *s = opaque; int x, y, col; @@ -171,6 +171,7 @@ static void lcd_refresh(void *opaque) } dpy_gfx_update(s->con, 0, 0, 128*3, 64*3); + return true; } static void lcd_invalidate(void *opaque) diff --git a/hw/display/artist.c b/hw/display/artist.c index 206f77afba1..a07508378c7 100644 --- a/hw/display/artist.c +++ b/hw/display/artist.c @@ -1311,7 +1311,7 @@ static void artist_draw_line(void *opaque, uint8_t *d, const uint8_t *src, } } -static void artist_update_display(void *opaque) +static bool artist_update_display(void *opaque) { ARTISTState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1326,6 +1326,8 @@ static void artist_update_display(void *opaque) if (first >= 0) { dpy_gfx_update(s->con, 0, first, s->width, last - first + 1); } + + return true; } static void artist_invalidate(void *opaque) diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index 75d7c0f8499..83c4c03c7ca 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -150,7 +150,7 @@ static bool fb_use_offsets(BCM2835FBConfig *config) config->yres_virtual > config->yres; } -static void fb_update_display(void *opaque) +static bool fb_update_display(void *opaque) { BCM2835FBState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -161,7 +161,7 @@ static void fb_update_display(void *opaque) uint32_t xoff = 0, yoff = 0; if (s->lock || !s->config.xres) { - return; + return true; } src_width = bcm2835_fb_get_pitch(&s->config); @@ -174,7 +174,7 @@ static void fb_update_display(void *opaque) switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 8: break; case 15: @@ -212,6 +212,7 @@ static void fb_update_display(void *opaque) } s->invalidate = false; + return true; } void bcm2835_fb_validate_config(BCM2835FBConfig *config) diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 5fb6b733cb5..8ef9b76cf85 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -198,7 +198,7 @@ static int bochs_display_get_mode(BochsDisplayState *s, return 0; } -static void bochs_display_update(void *opaque) +static bool bochs_display_update(void *opaque) { BochsDisplayState *s = opaque; DirtyBitmapSnapshot *snap = NULL; @@ -212,7 +212,7 @@ static void bochs_display_update(void *opaque) ret = bochs_display_get_mode(s, &mode); if (ret < 0) { /* no (valid) video mode */ - return; + return true; } if (memcmp(&s->mode, &mode, sizeof(mode)) != 0) { @@ -255,6 +255,8 @@ static void bochs_display_update(void *opaque) g_free(snap); } + + return true; } static const GraphicHwOps bochs_display_gfx_ops = { diff --git a/hw/display/cg3.c b/hw/display/cg3.c index 0a413fbb7ec..963bb3427a6 100644 --- a/hw/display/cg3.c +++ b/hw/display/cg3.c @@ -85,7 +85,7 @@ struct CG3State { uint8_t dac_index, dac_state; }; -static void cg3_update_display(void *opaque) +static bool cg3_update_display(void *opaque) { CG3State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -98,7 +98,7 @@ static void cg3_update_display(void *opaque) DirtyBitmapSnapshot *snap = NULL; if (surface_bits_per_pixel(surface) != 32) { - return; + return true; } width = s->width; height = s->height; @@ -154,6 +154,7 @@ static void cg3_update_display(void *opaque) qemu_irq_raise(s->irq); } g_free(snap); + return true; } static void cg3_invalidate_display(void *opaque) diff --git a/hw/display/dm163.c b/hw/display/dm163.c index 4feae912945..9ea62cb4f76 100644 --- a/hw/display/dm163.c +++ b/hw/display/dm163.c @@ -285,7 +285,7 @@ static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest, return dest; } -static void dm163_update_display(void *opaque) +static bool dm163_update_display(void *opaque) { DM163State *s = (DM163State *)opaque; DisplaySurface *surface = qemu_console_surface(s->console); @@ -300,6 +300,8 @@ static void dm163_update_display(void *opaque) } dest = update_display_of_row(s, dest, row); } + + return true; } static const GraphicHwOps dm163_ops = { diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 2d8fa7ee944..a91f04aaf79 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1270,7 +1270,7 @@ static void exynos4210_update_resolution(Exynos4210fimdState *s) } } -static void exynos4210_fimd_update(void *opaque) +static bool exynos4210_fimd_update(void *opaque) { Exynos4210fimdState *s = (Exynos4210fimdState *)opaque; DisplaySurface *surface; @@ -1287,7 +1287,7 @@ static void exynos4210_fimd_update(void *opaque) if (!s || !s->console || !s->enabled || surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { - return; + return true; } global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; @@ -1348,6 +1348,8 @@ static void exynos4210_fimd_update(void *opaque) exynos4210_fimd_enable(s, false); } exynos4210_fimd_update_irq(s); + + return true; } static void exynos4210_fimd_reset(DeviceState *d) diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 50952e9934b..bd15f6f0acc 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -238,15 +238,16 @@ static void g364fb_draw_blank(G364State *s) s->blanked = 1; } -static void g364fb_update_display(void *opaque) +static bool g364fb_update_display(void *opaque) { G364State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); qemu_flush_coalesced_mmio_buffer(); - if (s->width == 0 || s->height == 0) - return; + if (s->width == 0 || s->height == 0) { + return true; + } if (s->width != surface_width(surface) || s->height != surface_height(surface)) { @@ -262,6 +263,8 @@ static void g364fb_update_display(void *opaque) } qemu_irq_raise(s->irq); + + return true; } static inline void g364fb_invalidate_display(void *opaque) diff --git a/hw/display/imx6ul_lcdif.c b/hw/display/imx6ul_lcdif.c index 33cd00fbe16..afcd0805ca4 100644 --- a/hw/display/imx6ul_lcdif.c +++ b/hw/display/imx6ul_lcdif.c @@ -152,7 +152,7 @@ static void imx6ul_lcdif_draw_line_xrgb8888(void *opaque, uint8_t *dst, } } -static void imx6ul_lcdif_update_display(void *opaque) +static bool imx6ul_lcdif_update_display(void *opaque) { IMX6ULLCDIFState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -167,7 +167,7 @@ static void imx6ul_lcdif_update_display(void *opaque) int src_width; if (!imx6ul_lcdif_is_running(s) || width == 0 || height == 0) { - return; + return true; } switch (FIELD_EX32(ctrl, CTRL, WORD_LENGTH)) { @@ -180,7 +180,7 @@ static void imx6ul_lcdif_update_display(void *opaque) fn = imx6ul_lcdif_draw_line_xrgb8888; break; default: - return; + return true; } if (surface_width(surface) != width || surface_height(surface) != height) { @@ -207,6 +207,7 @@ static void imx6ul_lcdif_update_display(void *opaque) } s->invalidate = false; + return true; } static void imx6ul_lcdif_invalidate_display(void *opaque) diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c index 9d62e51bed9..7d1a020d4d9 100644 --- a/hw/display/jazz_led.c +++ b/hw/display/jazz_led.c @@ -144,7 +144,7 @@ static void draw_vertical_line(DisplaySurface *ds, } } -static void jazz_led_update_display(void *opaque) +static bool jazz_led_update_display(void *opaque) { LedState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -186,7 +186,7 @@ static void jazz_led_update_display(void *opaque) color_led = rgb_to_pixel32(0x00, 0xff, 0x00); break; default: - return; + return true; } /* display segments */ @@ -218,6 +218,8 @@ static void jazz_led_update_display(void *opaque) s->state = REDRAW_NONE; dpy_gfx_update_full(s->con); + + return true; } static void jazz_led_invalidate_display(void *opaque) diff --git a/hw/display/macfb.c b/hw/display/macfb.c index b8115c2be13..848c3c282bd 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -454,7 +454,7 @@ static gchar *macfb_mode_list(void) } -static void macfb_update_display(void *opaque) +static bool macfb_update_display(void *opaque) { MacfbState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -462,7 +462,7 @@ static void macfb_update_display(void *opaque) qemu_flush_coalesced_mmio_buffer(); if (s->width == 0 || s->height == 0) { - return; + return true; } if (s->width != surface_width(surface) || @@ -471,6 +471,8 @@ static void macfb_update_display(void *opaque) } macfb_draw_graphic(s); + + return true; } static void macfb_update_irq(MacfbState *s) diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c index 3d97702fce5..e758b223ef7 100644 --- a/hw/display/next-fb.c +++ b/hw/display/next-fb.c @@ -67,7 +67,7 @@ static void nextfb_draw_line(void *opaque, uint8_t *d, const uint8_t *s, } } -static void nextfb_update(void *opaque) +static bool nextfb_update(void *opaque) { NeXTFbState *s = NEXTFB(opaque); int dest_width = 4; @@ -90,6 +90,8 @@ static void nextfb_update(void *opaque) s, &first, &last); dpy_gfx_update(s->con, 0, 0, s->cols, s->rows); + + return true; } static void nextfb_invalidate(void *opaque) diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index c41c65bb2e0..1e8385ebffb 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -197,7 +197,7 @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, } while (-- width != 0); } -static void omap_update_display(void *opaque) +static bool omap_update_display(void *opaque) { struct omap_lcd_panel_s *omap_lcd = opaque; DisplaySurface *surface; @@ -207,12 +207,12 @@ static void omap_update_display(void *opaque) hwaddr frame_base; if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { - return; + return true; } surface = qemu_console_surface(omap_lcd->con); if (!surface_bits_per_pixel(surface)) { - return; + return true; } frame_offset = 0; @@ -256,7 +256,7 @@ static void omap_update_display(void *opaque) default: /* Unsupported at the moment. */ - return; + return true; } /* Resolution */ @@ -278,7 +278,7 @@ static void omap_update_display(void *opaque) omap_lcd->sync_error = 1; omap_lcd_interrupts(omap_lcd); omap_lcd->enable = 0; - return; + return true; } /* Content */ @@ -291,7 +291,7 @@ static void omap_update_display(void *opaque) omap_lcd->dma->current_frame ^= 1; if (!surface_bits_per_pixel(surface)) { - return; + return true; } first = 0; @@ -323,6 +323,8 @@ static void omap_update_display(void *opaque) dpy_gfx_update(omap_lcd->con, 0, first, width, last - first + 1); } omap_lcd->invalidate = 0; + + return true; } static void omap_invalidate_display(void *opaque) { diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 4cd62a98757..e134ac28eb6 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -210,7 +210,7 @@ static int pl110_enabled(PL110State *s) return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR); } -static void pl110_update_display(void *opaque) +static bool pl110_update_display(void *opaque) { PL110State *s = (PL110State *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -221,7 +221,7 @@ static void pl110_update_display(void *opaque) int last; if (!pl110_enabled(s)) { - return; + return true; } if (s->cr & PL110_CR_BGR) @@ -306,6 +306,7 @@ static void pl110_update_display(void *opaque) dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1); } s->invalidate = 0; + return true; } static void pl110_invalidate_display(void * opaque) diff --git a/hw/display/qxl-render.c b/hw/display/qxl-render.c index c6a9ac1da10..5b4f8842011 100644 --- a/hw/display/qxl-render.c +++ b/hw/display/qxl-render.c @@ -173,7 +173,7 @@ end: * callbacks are called by spice_server thread, deferring to bh called from the * io thread. */ -void qxl_render_update(PCIQXLDevice *qxl) +bool qxl_render_update(PCIQXLDevice *qxl) { QXLCookie *cookie; @@ -183,8 +183,7 @@ void qxl_render_update(PCIQXLDevice *qxl) qxl->mode == QXL_MODE_UNDEFINED) { qxl_render_update_area_unlocked(qxl); qemu_mutex_unlock(&qxl->ssd.lock); - graphic_hw_update_done(qxl->ssd.dcl.con); - return; + return true; } qxl->guest_primary.commands = 0; @@ -195,6 +194,7 @@ void qxl_render_update(PCIQXLDevice *qxl) qxl_set_rect_to_surface(qxl, &cookie->u.render.area); qxl_spice_update_area(qxl, 0, &cookie->u.render.area, NULL, 0, 1 /* clear_dirty_region */, QXL_ASYNC, cookie); + return false; } void qxl_render_update_area_bh(void *opaque) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index f8fd7ee0698..0a3c42c8ec2 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -122,7 +122,7 @@ static void qxl_reset_memslots(PCIQXLDevice *d); static void qxl_reset_surfaces(PCIQXLDevice *d); static void qxl_ring_set_dirty(PCIQXLDevice *qxl); -static void qxl_hw_update(void *opaque); +static bool qxl_hw_update(void *opaque); void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) { @@ -1144,7 +1144,6 @@ static const QXLInterface qxl_interface = { static const GraphicHwOps qxl_ops = { .gfx_update = qxl_hw_update, - .gfx_update_async = true, }; static void qxl_enter_vga_mode(PCIQXLDevice *d) @@ -1928,11 +1927,11 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_t events) /* graphics console */ -static void qxl_hw_update(void *opaque) +static bool qxl_hw_update(void *opaque) { PCIQXLDevice *qxl = opaque; - qxl_render_update(qxl); + return qxl_render_update(qxl); } static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, diff --git a/hw/display/ramfb-standalone.c b/hw/display/ramfb-standalone.c index f1958be32ad..27f0ba19f90 100644 --- a/hw/display/ramfb-standalone.c +++ b/hw/display/ramfb-standalone.c @@ -20,7 +20,7 @@ struct RAMFBStandaloneState { bool use_legacy_x86_rom; }; -static void display_update_wrapper(void *dev) +static bool display_update_wrapper(void *dev) { RAMFBStandaloneState *ramfb = RAMFB(dev); @@ -29,6 +29,8 @@ static void display_update_wrapper(void *dev) } else { ramfb_display_update(ramfb->con, ramfb->state); } + + return true; } static const GraphicHwOps wrapper_ops = { diff --git a/hw/display/sm501.c b/hw/display/sm501.c index a07aa9886f9..a3993ceba29 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -1716,7 +1716,7 @@ static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width, } } -static void sm501_update_display(void *opaque) +static bool sm501_update_display(void *opaque) { SM501State *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1740,7 +1740,7 @@ static void sm501_update_display(void *opaque) if (!((crt ? s->dc_crt_control : s->dc_panel_control) & SM501_DC_CRT_CONTROL_ENABLE)) { - return; + return true; } palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE - @@ -1761,7 +1761,7 @@ static void sm501_update_display(void *opaque) default: qemu_log_mask(LOG_GUEST_ERROR, "sm501: update display" "invalid control register value.\n"); - return; + return true; } /* set up to draw hardware cursor */ @@ -1833,6 +1833,8 @@ static void sm501_update_display(void *opaque) if (y_start >= 0) { dpy_gfx_update(s->con, 0, y_start, width, y - y_start); } + + return true; } static const GraphicHwOps sm501_ops = { diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c index 87781438cd5..229856cc427 100644 --- a/hw/display/ssd0303.c +++ b/hw/display/ssd0303.c @@ -203,7 +203,7 @@ static int ssd0303_event(I2CSlave *i2c, enum i2c_event event) return 0; } -static void ssd0303_update_display(void *opaque) +static bool ssd0303_update_display(void *opaque) { ssd0303_state *s = (ssd0303_state *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -218,11 +218,11 @@ static void ssd0303_update_display(void *opaque) uint8_t mask; if (!s->redraw) - return; + return true; switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 15: dest_width = 2; break; @@ -237,7 +237,7 @@ static void ssd0303_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } dest_width *= MAGNIFY; memset(colortab, 0xff, dest_width); @@ -269,6 +269,8 @@ static void ssd0303_update_display(void *opaque) } s->redraw = 0; dpy_gfx_update(s->con, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY); + + return true; } static void ssd0303_invalidate_display(void * opaque) diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index af5ff4fecdc..67db16086c8 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -181,7 +181,7 @@ static uint32_t ssd0323_transfer(SSIPeripheral *dev, uint32_t data) return 0; } -static void ssd0323_update_display(void *opaque) +static bool ssd0323_update_display(void *opaque) { ssd0323_state *s = (ssd0323_state *)opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -197,11 +197,11 @@ static void ssd0323_update_display(void *opaque) int dest_width; if (!s->redraw) - return; + return true; switch (surface_bits_per_pixel(surface)) { case 0: - return; + return true; case 15: dest_width = 2; break; @@ -216,7 +216,7 @@ static void ssd0323_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } p = colortab; for (i = 0; i < 16; i++) { @@ -240,7 +240,7 @@ static void ssd0323_update_display(void *opaque) break; default: BADF("Bad color depth\n"); - return; + return true; } p += dest_width; } @@ -271,6 +271,7 @@ static void ssd0323_update_display(void *opaque) } s->redraw = 0; dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY); + return true; } static void ssd0323_invalidate_display(void * opaque) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index ea92a48400c..cedbf5c7acd 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -209,7 +209,7 @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, /* Fixed line length 1024 allows us to do nice tricks not possible on VGA... */ -static void tcx_update_display(void *opaque) +static bool tcx_update_display(void *opaque) { TCXState *ts = opaque; DisplaySurface *surface = qemu_console_surface(ts->con); @@ -257,9 +257,10 @@ static void tcx_update_display(void *opaque) ts->width, y - y_start); } g_free(snap); + return true; } -static void tcx24_update_display(void *opaque) +static bool tcx24_update_display(void *opaque) { TCXState *ts = opaque; DisplaySurface *surface = qemu_console_surface(ts->con); @@ -312,6 +313,7 @@ static void tcx24_update_display(void *opaque) ts->width, y - y_start); } g_free(snap); + return true; } static void tcx_invalidate_display(void *opaque) diff --git a/hw/display/vga.c b/hw/display/vga.c index 0d69a53f27a..776aa443246 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1783,7 +1783,7 @@ static void vga_draw_blank(VGACommonState *s, int full_update) #define GMODE_GRAPH 1 #define GMODE_BLANK 2 -static void vga_update_display(void *opaque) +static bool vga_update_display(void *opaque) { VGACommonState *s = opaque; DisplaySurface *surface = qemu_console_surface(s->con); @@ -1818,6 +1818,8 @@ static void vga_update_display(void *opaque) break; } } + + return true; } /* force a full display refresh */ diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index cb76302e2d8..94cf362d152 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -83,8 +83,9 @@ static void virtio_gpu_invalidate_display(void *opaque) { } -static void virtio_gpu_update_display(void *opaque) +static bool virtio_gpu_update_display(void *opaque) { + return true; } static void virtio_gpu_text_update(void *opaque, console_ch_t *chardata) diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index 5e087169f2f..f4713b91a66 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -19,15 +19,15 @@ static void virtio_vga_base_invalidate_display(void *opaque) } } -static void virtio_vga_base_update_display(void *opaque) +static bool virtio_vga_base_update_display(void *opaque) { VirtIOVGABase *vvga = opaque; VirtIOGPUBase *g = vvga->vgpu; if (g->enable) { - g->hw_ops->gfx_update(g); + return g->hw_ops->gfx_update(g); } else { - vvga->vga.hw_ops->gfx_update(&vvga->vga); + return vvga->vga.hw_ops->gfx_update(&vvga->vga); } } diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 2b95787ddfd..c84c84a445e 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1135,14 +1135,13 @@ static inline void vmsvga_check_size(struct vmsvga_state_s *s) } } -static void vmsvga_update_display(void *opaque) +static bool vmsvga_update_display(void *opaque) { struct vmsvga_state_s *s = opaque; if (!s->enable || !s->config) { /* in standard vga mode */ - s->vga.hw_ops->gfx_update(&s->vga); - return; + return s->vga.hw_ops->gfx_update(&s->vga); } vmsvga_check_size(s); @@ -1154,6 +1153,8 @@ static void vmsvga_update_display(void *opaque) s->invalidated = 0; dpy_gfx_update_full(s->vga.con); } + + return true; } static void vmsvga_reset(DeviceState *dev) diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c index ba886a940ee..2e431e27be6 100644 --- a/hw/display/xenfb.c +++ b/hw/display/xenfb.c @@ -709,14 +709,14 @@ static void xenfb_send_refresh_period(struct XenFB *xenfb, int period) * Our screen might be inactive. When asked for * an update we know it is active. */ -static void xenfb_update(void *opaque) +static bool xenfb_update(void *opaque) { struct XenFB *xenfb = opaque; DisplaySurface *surface; int i; if (xenfb->c.xendev.be_state != XenbusStateConnected) - return; + return true; if (!xenfb->feature_update) { /* we don't get update notifications, thus use the @@ -770,6 +770,8 @@ static void xenfb_update(void *opaque) } xenfb->up_count = 0; xenfb->up_fullscreen = 0; + + return true; } static void xenfb_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index 7d037b46a35..50e6ef10984 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1252,12 +1252,12 @@ static inline void xlnx_dp_blend_surface(XlnxDPState *s) surface_height(s->g_plane.surface)); } -static void xlnx_dp_update_display(void *opaque) +static bool xlnx_dp_update_display(void *opaque) { XlnxDPState *s = XLNX_DP(opaque); if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { - return; + return true; } xlnx_dpdma_trigger_vsync_irq(s->dpdma); @@ -1272,14 +1272,14 @@ static void xlnx_dp_update_display(void *opaque) */ s->core_registers[DP_INT_STATUS] |= (1 << 21); xlnx_dp_update_irq(s); - return; + return true; } if (xlnx_dp_global_alpha_enabled(s)) { if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) { s->core_registers[DP_INT_STATUS] |= (1 << 21); xlnx_dp_update_irq(s); - return; + return true; } xlnx_dp_blend_surface(s); } @@ -1288,6 +1288,8 @@ static void xlnx_dp_update_display(void *opaque) * XXX: We might want to update only what changed. */ dpy_gfx_update_full(s->console); + + return true; } static const GraphicHwOps xlnx_dp_gfx_ops = { diff --git a/hw/vfio/display.c b/hw/vfio/display.c index 5a42a6f7a29..4a9a58036e3 100644 --- a/hw/vfio/display.c +++ b/hw/vfio/display.c @@ -285,7 +285,7 @@ static void vfio_display_free_dmabufs(VFIOPCIDevice *vdev) } } -static void vfio_display_dmabuf_update(void *opaque) +static bool vfio_display_dmabuf_update(void *opaque) { VFIOPCIDevice *vdev = opaque; VFIODisplay *dpy = vdev->dpy; @@ -298,7 +298,7 @@ static void vfio_display_dmabuf_update(void *opaque) if (dpy->ramfb) { ramfb_display_update(dpy->con, dpy->ramfb); } - return; + return true; } width = qemu_dmabuf_get_width(primary->buf); @@ -340,6 +340,8 @@ static void vfio_display_dmabuf_update(void *opaque) if (free_bufs) { vfio_display_free_dmabufs(vdev); } + + return true; } static int vfio_display_get_flags(void *opaque) @@ -399,7 +401,7 @@ void vfio_display_reset(VFIOPCIDevice *vdev) dpy_gfx_update_full(vdev->dpy->con); } -static void vfio_display_region_update(void *opaque) +static bool vfio_display_region_update(void *opaque) { VFIOPCIDevice *vdev = opaque; VFIODisplay *dpy = vdev->dpy; @@ -414,18 +416,18 @@ static void vfio_display_region_update(void *opaque) if (ret < 0) { error_report("ioctl VFIO_DEVICE_QUERY_GFX_PLANE: %s", strerror(errno)); - return; + return true; } if (!plane.drm_format || !plane.size) { if (dpy->ramfb) { ramfb_display_update(dpy->con, dpy->ramfb); dpy->region.surface = NULL; } - return; + return true; } format = qemu_drm_format_to_pixman(plane.drm_format); if (!format) { - return; + return true; } if (dpy->region.buffer.size && @@ -476,11 +478,12 @@ static void vfio_display_region_update(void *opaque) dpy_gfx_update(dpy->con, 0, 0, surface_width(dpy->region.surface), surface_height(dpy->region.surface)); - return; + return true; err: vfio_region_exit(&dpy->region.buffer); vfio_region_finalize(&dpy->region.buffer); + return true; } static const GraphicHwOps vfio_display_region_ops = { diff --git a/ui/console.c b/ui/console.c index abb6cba2826..a608c29b843 100644 --- a/ui/console.c +++ b/ui/console.c @@ -136,15 +136,10 @@ void graphic_hw_update_done(QemuConsole *con) void graphic_hw_update(QemuConsole *con) { - bool async = false; if (!con) { return; } - if (con->hw_ops->gfx_update) { - con->hw_ops->gfx_update(con->hw); - async = con->hw_ops->gfx_update_async; - } - if (!async) { + if (!con->hw_ops->gfx_update || con->hw_ops->gfx_update(con->hw)) { graphic_hw_update_done(con); } } diff --git a/hw/display/apple-gfx.m b/hw/display/apple-gfx.m index e0a765fcb1f..77d80fb7cef 100644 --- a/hw/display/apple-gfx.m +++ b/hw/display/apple-gfx.m @@ -330,25 +330,25 @@ static void apple_gfx_render_frame_completed_bh(void *opaque) } } -static void apple_gfx_fb_update_display(void *opaque) +static bool apple_gfx_fb_update_display(void *opaque) { AppleGFXState *s = opaque; + bool done = true; assert(bql_locked()); if (s->new_frame_ready) { dpy_gfx_update_full(s->con); s->new_frame_ready = false; - graphic_hw_update_done(s->con); } else if (s->pending_frames > 0) { s->gfx_update_requested = true; - } else { - graphic_hw_update_done(s->con); + done = false; } + + return done; } static const GraphicHwOps apple_gfx_fb_ops = { .gfx_update = apple_gfx_fb_update_display, - .gfx_update_async = true, }; /* ------ Mouse cursor and display mode setting ------ */ -- 2.54.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 15:15:57 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 15:15:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296453.1572858 (Exim 4.92) (envelope-from ) id 1wHkA2-0002OG-P3; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=ecfl265qQUiRdYzmgGmvEv3ilzP58U075ntp6nhcQBg=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=kAUDdPV/o+dW9s1jDGJOBFWbxdruBH2IyByC14Mzyr46B4aSaXZRGbyU/Aa41gwd76ZtLtSXI 6jMBZNdYuMMzFhAwbIB4TTmHgri8DP6TsEi5AhvzZuyfqZ1fUGNbVCT1sEJx1EBrksk8Mxk0CpP ZeVDn0X6KnHNk92LtezLuFwAJxOAyOZvbZlli630HxN0lH6eDDUQBo0yjv9uytlIn7ksGkIvfCz zc46VCtugq+ctVW/l9AAmw87fXQChZE/66wKfdjTDkcPCj7gAL1sJ3V64fUCEgESI3XzMFmJtdN +U04EHkI83OaK1BGd+cYBNhkvhDR2NdDGwqo/VuBdPXw== X-Zone-Loop: 8072d6f56970f7b19306a65672f1b29cff4ff90832e6 x-campaign-type: default x-transaction-id: 19ecbb85-90a3-43f8-b87f-5b0d3318e6b6 x-swg-uid: 01-b60b17f6-6c4c-469b-936e-382cf3719e80 X-Mailer: Sweego Message-ID: <1777389336.8631fc262581453bbf619ec5b2062170.19dd4a8f919000f373@vates.tech> x-swg-bid: 1777389336.8631fc262581453bbf619ec5b2062170.19dd4a8f919000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 17:15:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/9] x86/passthrough: Introduce pt_irq_bind_msi() as canonical MSI bind path To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298080.8631fc262581453bbf619ec5b2062170.19dcf3882f5000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298080.8631fc262581453bbf619ec5b2062170.19dcf3882f5000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.e7.ea83ac1b51395593.19dd4a8f666.7bd1a80984b505c3=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777389336166 X-purgate-ID: tlsNG-d25034/1777389340-F600DCF5-C2A702E8/0/0 X-purgate-type: clean X-purgate-size: 17805 ---=Part.e7.ea83ac1b51395593.19dd4a8f666.7bd1a80984b505c3=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Change pt_irq_bind_msi() to accept raw MSI address and data values inste= ad > of pre-decoded gvec/gflags=2E Add msi_addr_to_gflags() to decode the > destination ID and delivery attributes, including the Extended Destinati= on > ID bits from address[11:5] per Intel convention=2E >=20 > Update pt_irq_create_bind() to call pt_irq_bind_msi() via the existing > gvec/gflags interface so domctl-based callers continue to work=2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - As suggested by Roger replace the v3 approach (v3 patches 2+4) of > extending the gflags ABI with XEN_DOMCTL_VMSI_X86_EXT_DEST_ID_MASK an= d > XEN_DOMCTL_VMSI_X86_FULL_DEST() so callers could pass extended bits > through XEN_DOMCTL_bind_pt_irq=2E pt_irq_bind_msi() now accepts raw M= SI > address + data and decodes the destination internally via > msi_addr_to_gflags() > - Replace the gmsi=2Egvec + gmsi=2Egflags fields in struct hvm_pirq_dpci > with gmsi=2Eaddr + gmsi=2Edata > - Replace msi_gflags() (v3 vmsi=2Ec helper that packed the extended > destination bits into gflags) with msi_addr_to_gflags() which decodes > the raw MSI address directly > - pt_irq_create_bind() now rejects PT_IRQ_TYPE_MSI with -EOPNOTSUPP and > all callers are redirected through the DM op path in patch 7 > - As suggested by Roger adapt the comment in msi=2Eh in regards to the > extended destination encoding since it's not part of any specificatio= n > --- > xen/arch/x86/hvm/vmsi=2Ec | 50 ++++++------------ > xen/arch/x86/include/asm/hvm/irq=2Eh | 4 +- > xen/arch/x86/include/asm/msi=2Eh | 18 ++++++- > xen/drivers/passthrough/x86/hvm=2Ec | 83 ++++++++++++++++++----------= -- > xen/include/xen/iommu=2Eh | 3 ++ > 5 files changed, 86 insertions(+), 72 deletions(-) >=20 > diff --git a/xen/arch/x86/hvm/vmsi=2Ec b/xen/arch/x86/hvm/vmsi=2Ec > index 27b1f089e2=2E=2E2a4b97e2e1 100644 > --- a/xen/arch/x86/hvm/vmsi=2Ec > +++ b/xen/arch/x86/hvm/vmsi=2Ec > @@ -43,6 +43,7 @@ > #include > #include > #include > +#include > =20 > static void vmsi_inj_irq( > struct vlapic *target, > @@ -107,12 +108,12 @@ int vmsi_deliver( > =20 > void vmsi_deliver_pirq(struct domain *d, const struct hvm_pirq_dpci *p= irq_dpci) > { > - uint32_t flags =3D pirq_dpci->gmsi=2Egflags; > - int vector =3D pirq_dpci->gmsi=2Egvec; > - uint8_t dest =3D (uint8_t)flags; > - bool dest_mode =3D flags & XEN_DOMCTL_VMSI_X86_DM_MASK; > - uint8_t delivery_mode =3D MASK_EXTR(flags, XEN_DOMCTL_VMSI_X86_DELI= V_MASK); > - bool trig_mode =3D flags & XEN_DOMCTL_VMSI_X86_TRIG_MASK; > + uint32_t dest =3D MSI_ADDR_DEST(pirq_dpci->gmsi=2Eaddr); > + bool dest_mode =3D pirq_dpci->gmsi=2Eaddr & MSI_ADDR_DESTMODE_MASK; > + uint8_t delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Edata, > + MSI_DATA_DELIVERY_MODE_MASK); > + bool trig_mode =3D pirq_dpci->gmsi=2Edata & MSI_DATA_TRIGGER_MASK; > + int vector =3D pirq_dpci->gmsi=2Edata & MSI_DATA_VECTOR_MASK; > =20 > HVM_DBG_LOG(DBG_LEVEL_IOAPIC, > "msi: dest=3D%x dest_mode=3D%x delivery_mode=3D%x " > @@ -793,27 +794,6 @@ void msix_write_completion(struct vcpu *v) > } > =20 > #ifdef CONFIG_HAS_VPCI > -static unsigned int msi_gflags(uint16_t data, uint64_t addr, bool maske= d) > -{ > - /* > - * We need to use the DOMCTL constants here because the output of t= his > - * function is used as input to pt_irq_create_bind, which also take= s the > - * input from the DOMCTL itself=2E > - */ > - return MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DEST_ID_MASK), > - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK) | > - MASK_INSR(MASK_EXTR(addr, MSI_ADDR_REDIRECTION_MASK), > - XEN_DOMCTL_VMSI_X86_RH_MASK) | > - MASK_INSR(MASK_EXTR(addr, MSI_ADDR_DESTMODE_MASK), > - XEN_DOMCTL_VMSI_X86_DM_MASK) | > - MASK_INSR(MASK_EXTR(data, MSI_DATA_DELIVERY_MODE_MASK), > - XEN_DOMCTL_VMSI_X86_DELIV_MASK) | > - MASK_INSR(MASK_EXTR(data, MSI_DATA_TRIGGER_MASK), > - XEN_DOMCTL_VMSI_X86_TRIG_MASK) | > - /* NB: by default MSI vectors are bound masked=2E */ > - (masked ? 0 : XEN_DOMCTL_VMSI_X86_UNMASKED); > -} > - > static void vpci_mask_pirq(struct domain *d, int pirq, bool mask) > { > unsigned long flags; > @@ -850,17 +830,17 @@ static int vpci_msi_update(const struct pci_dev *p= dev, uint32_t data, > { > uint8_t vector =3D MASK_EXTR(data, MSI_DATA_VECTOR_MASK); > uint8_t vector_mask =3D 0xff >> (8 - fls(vectors) + 1); > - struct xen_domctl_bind_pt_irq bind =3D { > - =2Emachine_irq =3D pirq + i, > - =2Eirq_type =3D PT_IRQ_TYPE_MSI, > - =2Eu=2Emsi=2Egvec =3D (vector & ~vector_mask) | > - ((vector + i) & vector_mask), > - =2Eu=2Emsi=2Egflags =3D msi_gflags(data, address, (mask >> = i) & 1), > - }; > - int rc =3D pt_irq_create_bind(pdev->domain, &bind); > + uint8_t gvec =3D (vector & ~vector_mask) | ((vector + i) & vect= or_mask); > + uint32_t msi_data =3D (data & ~MSI_DATA_VECTOR_MASK) | gvec; > + int rc =3D pt_irq_bind_msi(pdev->domain, pirq + i, > + address, msi_data, 0, !((mask >> i) & = 1)); > =20 > if ( rc ) > { > + struct xen_domctl_bind_pt_irq bind =3D { > + =2Eirq_type =3D PT_IRQ_TYPE_MSI, > + =2Emachine_irq =3D pirq + i, > + }; > gdprintk(XENLOG_ERR, "%pp: failed to bind PIRQ %u: %d\n", > &pdev->sbdf, pirq + i, rc); > while ( bind=2Emachine_irq-- > pirq ) > diff --git a/xen/arch/x86/include/asm/hvm/irq=2Eh b/xen/arch/x86/include= /asm/hvm/irq=2Eh > index 77595fb3f4=2E=2Ec50eee9996 100644 > --- a/xen/arch/x86/include/asm/hvm/irq=2Eh > +++ b/xen/arch/x86/include/asm/hvm/irq=2Eh > @@ -120,8 +120,8 @@ struct dev_intx_gsi_link { > #define HVM_IRQ_DPCI_TRANSLATE (1u << _HVM_IRQ_DPCI_TRANSLATE_SH= IFT) > =20 > struct hvm_gmsi_info { > - uint32_t gvec; > - uint32_t gflags; > + uint64_t addr; /* raw MSI address (0xfeexxxxx, includes ext dest= ID) */ > + uint32_t data; /* raw MSI data (vector, delivery mode, trigger m= ode) */ > int dest_vcpu_id; /* -1 :multi-dest, non-negative: dest_vcpu_id */ > bool posted; /* directly deliver to guest via VT-d PI? */ > }; > diff --git a/xen/arch/x86/include/asm/msi=2Eh b/xen/arch/x86/include/asm= /msi=2Eh > index 00059d4a3a=2E=2E93aaf20e27 100644 > --- a/xen/arch/x86/include/asm/msi=2Eh > +++ b/xen/arch/x86/include/asm/msi=2Eh > @@ -51,8 +51,22 @@ > #define MSI_ADDR_REDIRECTION_MASK (1 << MSI_ADDR_REDIRECTION_SHIFT) > =20 > #define MSI_ADDR_DEST_ID_SHIFT 12 > -#define MSI_ADDR_DEST_ID_MASK 0x00ff000 > -#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & = MSI_ADDR_DEST_ID_MASK) > +#define MSI_ADDR_DEST_ID_UPPER_BITS 8 > +#define MSI_ADDR_DEST_ID_MASK 0x00ff000 > +#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & M= SI_ADDR_DEST_ID_MASK) > + > +/* > + * Intel convention: in physical destination mode bits 11:5 of the MSI > + * address carry APIC ID bits [14:8] (the "Extended Destination ID"), > + * extending the addressable range from 8 to 15 bits=2E > + */ > +#define MSI_ADDR_EXT_DEST_ID_MASK 0x0000fe0 > + > +/* Extract the combined 15-bit destination ID from an MSI address=2E */ > +#define MSI_ADDR_DEST(addr) \ > + (MASK_EXTR((addr), MSI_ADDR_DEST_ID_MASK) | \ > + (MASK_EXTR((addr), MSI_ADDR_EXT_DEST_ID_MASK) << \ > + MSI_ADDR_DEST_ID_UPPER_BITS)) > =20 > /* MAX fixed pages reserved for mapping MSIX tables=2E */ > #define FIX_MSIX_MAX_PAGES 512 > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index eff1e8a79e=2E=2E026534530f 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -21,6 +21,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -290,14 +291,15 @@ static int pt_irq_dpci_setup(struct domain *d, uns= igned int pirq, > } while ( true ); > } > =20 > -static int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, > - uint8_t gvec, uint32_t gflags, uint64_t gta= ble, > - bool unmasked) > +int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, > + uint64_t msi_addr, uint32_t msi_data, > + uint64_t gtable, bool unmasked) > { > struct hvm_irq_dpci *hvm_irq_dpci; > struct hvm_pirq_dpci *pirq_dpci; > struct pirq *info; > - uint8_t dest, delivery_mode; > + uint8_t gvec, delivery_mode; > + uint32_t dest; > bool dest_mode; > int dest_vcpu_id, rc; > const struct vcpu *vcpu; > @@ -313,8 +315,8 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, > { > pirq_dpci->flags =3D HVM_IRQ_DPCI_MAPPED | HVM_IRQ_DPCI_MACH_M= SI | > HVM_IRQ_DPCI_GUEST_MSI; > - pirq_dpci->gmsi=2Egvec =3D gvec; > - pirq_dpci->gmsi=2Egflags =3D gflags; > + pirq_dpci->gmsi=2Eaddr =3D msi_addr; > + pirq_dpci->gmsi=2Edata =3D msi_data; > /* > * 'pt_irq_bind_msi' can be called after 'pt_irq_destroy_bind'= =2E > * The 'pirq_cleanup_check' which would free the structure is = only > @@ -346,8 +348,8 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, > } > if ( unlikely(rc) ) > { > - pirq_dpci->gmsi=2Egflags =3D 0; > - pirq_dpci->gmsi=2Egvec =3D 0; > + pirq_dpci->gmsi=2Eaddr =3D 0; > + pirq_dpci->gmsi=2Edata =3D 0; > pirq_dpci->dom =3D NULL; > pirq_dpci->flags =3D 0; > if ( !info->evtchn ) > @@ -367,20 +369,22 @@ static int pt_irq_bind_msi(struct domain *d, uint3= 2_t machine_irq, > } > =20 > /* If pirq is already mapped as vmsi, update guest data/addr= =2E */ > - if ( pirq_dpci->gmsi=2Egvec !=3D gvec || pirq_dpci->gmsi=2Egfla= gs !=3D gflags ) > + if ( pirq_dpci->gmsi=2Eaddr !=3D msi_addr || > + pirq_dpci->gmsi=2Edata !=3D msi_data ) > { > /* Directly clear pending EOIs before enabling new MSI inf= o=2E */ > pirq_guest_eoi(info); > =20 > - pirq_dpci->gmsi=2Egvec =3D gvec; > - pirq_dpci->gmsi=2Egflags =3D gflags; > + pirq_dpci->gmsi=2Eaddr =3D msi_addr; > + pirq_dpci->gmsi=2Edata =3D msi_data; > } > } > + > /* Calculate dest_vcpu_id for MSI-type pirq migration=2E */ > - dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, XEN_DOMCTL_VMSI_X86_DE= ST_ID_MASK); > - dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X86_DM_MAS= K; > - delivery_mode =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, > - XEN_DOMCTL_VMSI_X86_DELIV_MASK); > + gvec =3D msi_data & MSI_DATA_VECTOR_MASK; > + dest =3D MSI_ADDR_DEST(msi_addr); > + dest_mode =3D msi_addr & MSI_ADDR_DESTMODE_MASK; > + delivery_mode =3D MASK_EXTR(msi_data, MSI_DATA_DELIVERY_MODE_MASK); > =20 > dest_vcpu_id =3D hvm_girq_dest_2_vcpu_id(d, dest, dest_mode); > pirq_dpci->gmsi=2Edest_vcpu_id =3D dest_vcpu_id; > @@ -391,8 +395,7 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, > if ( iommu_intpost ) > { > if ( delivery_mode =3D=3D dest_LowestPrio ) > - vcpu =3D vector_hashing_dest(d, dest, dest_mode, > - pirq_dpci->gmsi=2Egvec); > + vcpu =3D vector_hashing_dest(d, dest, dest_mode, gvec); > if ( vcpu ) > pirq_dpci->gmsi=2Eposted =3D true; > } > @@ -407,7 +410,7 @@ static int pt_irq_bind_msi(struct domain *d, uint32_= t machine_irq, > =2Eirq_type =3D PT_IRQ_TYPE_MSI, > }; > =20 > - rc =3D hvm_pi_update_irte(vcpu, info, pirq_dpci->gmsi=2Egvec); > + rc =3D hvm_pi_update_irte(vcpu, info, gvec); > if ( rc ) > { > pt_irq_destroy_bind(d, &bind); > @@ -417,15 +420,15 @@ static int pt_irq_bind_msi(struct domain *d, uint3= 2_t machine_irq, > =20 > if ( unmasked ) > { > - struct xen_domctl_bind_pt_irq bind =3D { > - =2Emachine_irq =3D machine_irq, > - =2Eirq_type =3D PT_IRQ_TYPE_MSI, > - }; > unsigned long flags; > struct irq_desc *desc =3D pirq_spin_lock_irq_desc(info, &flags= ); > =20 > if ( !desc ) > { > + struct xen_domctl_bind_pt_irq bind =3D { > + =2Emachine_irq =3D machine_irq, > + =2Eirq_type =3D PT_IRQ_TYPE_MSI, > + }; > pt_irq_destroy_bind(d, &bind); > return -EINVAL; > } > @@ -448,13 +451,29 @@ int pt_irq_create_bind( > switch ( pt_irq_bind->irq_type ) > { > case PT_IRQ_TYPE_MSI: > - return pt_irq_bind_msi(d, pirq, > - pt_irq_bind->u=2Emsi=2Egvec, > - pt_irq_bind->u=2Emsi=2Egflags & > - ~XEN_DOMCTL_VMSI_X86_UNMASKED, > + { > + uint32_t gflags =3D pt_irq_bind->u=2Emsi=2Egflags; > + uint64_t msi_addr; > + uint32_t msi_data; > + > + msi_addr =3D MSI_ADDR_HEADER | > + MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DEST= _ID_MASK), > + MSI_ADDR_DEST_ID_MASK) | > + (gflags & XEN_DOMCTL_VMSI_X86_RH_MASK ? > + MSI_ADDR_REDIRECTION_LOWPRI : MSI_ADDR_REDIRECTION_= CPU) | > + (gflags & XEN_DOMCTL_VMSI_X86_DM_MASK ? > + MSI_ADDR_DESTMODE_LOGIC : MSI_ADDR_DESTMODE_PHYS); > + msi_data =3D pt_irq_bind->u=2Emsi=2Egvec | > + MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DELI= V_MASK), > + MSI_DATA_DELIVERY_MODE_MASK) | > + (gflags & XEN_DOMCTL_VMSI_X86_TRIG_MASK ? > + MSI_DATA_TRIGGER_LEVEL : 0); > + > + return pt_irq_bind_msi(d, pt_irq_bind->machine_irq, > + msi_addr, msi_data, > pt_irq_bind->u=2Emsi=2Egtable, > - !!(pt_irq_bind->u=2Emsi=2Egflags & > - XEN_DOMCTL_VMSI_X86_UNMASKED)); > + !!(gflags & XEN_DOMCTL_VMSI_X86_UNMASKED= )); > + } > =20 > case PT_IRQ_TYPE_PCI: > case PT_IRQ_TYPE_MSI_TRANSLATE: > @@ -617,7 +636,6 @@ int pt_irq_create_bind( > } > =20 > default: > - write_unlock(&d->event_lock); > return -EOPNOTSUPP; > } > =20 > @@ -858,11 +876,10 @@ static int cf_check _hvm_dpci_msi_eoi( > int vector =3D (long)arg; > =20 > if ( (pirq_dpci->flags & HVM_IRQ_DPCI_MACH_MSI) && > - (pirq_dpci->gmsi=2Egvec =3D=3D vector) ) > + ((pirq_dpci->gmsi=2Edata & MSI_DATA_VECTOR_MASK) =3D=3D vector= ) ) > { > - unsigned int dest =3D MASK_EXTR(pirq_dpci->gmsi=2Egflags, > - XEN_DOMCTL_VMSI_X86_DEST_ID_MASK)= ; > - bool dest_mode =3D pirq_dpci->gmsi=2Egflags & XEN_DOMCTL_VMSI_X= 86_DM_MASK; > + unsigned int dest =3D MSI_ADDR_DEST(pirq_dpci->gmsi=2Eaddr); > + bool dest_mode =3D pirq_dpci->gmsi=2Eaddr & XEN_DOMCTL_VMSI_X86= _DM_MASK; > =20 > if ( vlapic_match_dest(vcpu_vlapic(current), NULL, 0, dest, > dest_mode) ) > diff --git a/xen/include/xen/iommu=2Eh b/xen/include/xen/iommu=2Eh > index 37c4a1dc82=2E=2E4672d114e3 100644 > --- a/xen/include/xen/iommu=2Eh > +++ b/xen/include/xen/iommu=2Eh > @@ -222,6 +222,9 @@ int pt_irq_create_bind(struct domain *d, > const struct xen_domctl_bind_pt_irq *pt_irq_bin= d); > int pt_irq_destroy_bind(struct domain *d, > const struct xen_domctl_bind_pt_irq *pt_irq_bi= nd); > +int pt_irq_bind_msi(struct domain *d, uint32_t machine_irq, > + uint64_t msi_addr, uint32_t msi_data, > + uint64_t gtable, bool unmasked); > =20 > struct hvm_irq_dpci *domain_get_irq_dpci(const struct domain *d); > void free_hvm_irq_dpci(struct hvm_irq_dpci *dpci); There is a lot of bitwise manipulations there, and I wonder if using=20 bitfields could help here ? Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.e7.ea83ac1b51395593.19dd4a8f666.7bd1a80984b505c3=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 15:17:43 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 15:17:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296461.1572868 (Exim 4.92) (envelope-from ) id 1wHkBo-0002uZ-39; Tue, 28 Apr 2026 15:17:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296461.1572868; Tue, 28 Apr 2026 15:17:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHkBo-0002uS-0M; Tue, 28 Apr 2026 15:17:32 +0000 Received: by outflank-mailman (input) for mailman id 1296461; Tue, 28 Apr 2026 15:17:31 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHkBn-0002uK-8Z for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 15:17:31 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHkBm-00689m-2i; Tue, 28 Apr 2026 15:17:30 +0000 Received: from [2a02:8012:3a1:0:41a7:c05:58cb:6653] by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1wHkBm-006xf3-27; Tue, 28 Apr 2026 15:17:30 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=Szftq+YgYXu7Xtqxo3GkkEYoQPptF7lz71Be+Th/64g=; b=cfHdR8KUv4CV2gElmLaUuN2yGo gcGNBUTC7kneMCG9pUk5jMdb1ih4Xz3dh0eWLw8lIFlQtjLy2i9TMpN2I6lEwSxkELTUhtNiMAiak n9p1LL4hzi8NJatGfz7xusVA5hRVqEh4iRz+FgwylY3ubVdh4INfBhvzg0H7laWU86WU=; Message-ID: <8653c501-a990-48cf-9e38-0a6eb99a1cd7@xen.org> Date: Tue, 28 Apr 2026 16:17:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: gic-v3: Introduce CONFIG_GICV3_NR_LRS To: "Halder, Ayan Kumar" , Ayan Kumar Halder , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: <20260318140900.3795710-1-ayan.kumar.halder@amd.com> <83786d8b-d57a-4c79-8e8b-7115d4276568@xen.org> Content-Language: en-GB From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Ayan, On 18/04/2026 08:28, Halder, Ayan Kumar wrote: > > On 14/04/2026 03:06, Julien Grall wrote: >> Hi Ayan, > Hi Julien, >> >> On 18/03/2026 23:09, Ayan Kumar Halder wrote: >>> One key requirement of Xen functional safety is to reduce the number >>> of lines of code to be safety certified. Besides, a safety certified >>> Xen requires a static hardware configuration to be defined. This static >>> hardware configuration is described as per the test hardware/emulator >>> hardware configuration against which Xen is verified. >>> >>> Introduce GICV3_NR_LRS with the two aims in mind: >> >> Out of interest, why is this limited to GICv3? > > This was just my starting point of investigation. My intention is to > have as much as a static defined hardware configuration, so that the > code that cannot be tested on the hardware can be eliminated by one of > the many ways (DCE, Kconfig or actual code removal). > > The advantage of having a static defined configuration is that the > system integrator will have the full control on how to configure Xen for > a specific hardware platform. And we try to reduce as much as possible > any code that cannot be used due to hardware limitations. Thanks for the answer. I was asking because I wonder whether the name of config should be more generic so it can be used for GICV2. But I guess we can rename it afterwards. > >> >>> 1. User should set the number of GICV3 list registers as per the test >>> hardware so that the unwanted code can be removed using GCC's dead >>> code elimination or preprocessor's config. >> >> We discussed this offline, I am not fully convinced you can rely on >> dead code elimination to always remove the BUG() in >> gicv3_ich_read_lr(). If you want to rely on dead code eliminitation, >> then you will want to call a function which have a prototype defined >> but not implemented (similar to what we do for bitops with >> __bad_atomic_read()) which would fail a link time if the compiler >> didn't remove the code. > > If you are ok, we can break this into 2 patches > > 1. Introduce GICV3_NR_LRS and make sure it is used consistently in the > code. IOW, it should address the comments that Luca and you provided. > > 2. Implement a way for compiler to do DCE based on GICV3_NR_LRS. Yes please, so we can merge patch #1 earlier. > >> >>> 2. By doing #1, one can ensure that there is no untested code due to >>> unsupported hardware platform and thus there is no safety impact due >>> to untested code. >>> >>> However if the user does not set GICV3_NR_LRS, then it is set to 0. >>> Thus Xen will fallback to the default scenario (i.e. read the hardware >>> register to determine the number of LRS). >>> >>> 1. In gicv3_save_lrs()/gicv3_restore_lrs(), use the number of list >>> registers from GICV3_NR_LRS (if defined) instead of gicv3_info.nr_lrs. >>> This ensures that if the hardware does not support more than 4 LRs >>> (for example), the code accessing LR 4-15 is never reached. The >>> compiler can eliminate the unsupported cases as the switch case uses a >>> constant conditional. >>> >>> 2. RAZ/WI for the unsupported LRs. >>> >>> Signed-off-by: Ayan Kumar Halder >>> Signed-off-by: Michal Orzel >>> --- >>> Changelog: >>> >>> v1 - 1. s/lrs/LRS >>> 2. Implement RAZ/WI instead of panic >>> >>> Few comments which were not addressed >>> 1. Do "gicv3_info.nr_lrs to LRS" in gicv3_hyp_init() and keep the code >>> unchanged in gicv3_save_lrs()/gicv3_restore_lrs() -- This prevents the >>> compiler from doing dead code elimination as the switch condition cannot >>> be evaluated at compile time. >>> I am not sure how to get around this issue. >>> >>>   xen/arch/arm/Kconfig  |  9 +++++++++ >>>   xen/arch/arm/gic-v3.c | 14 ++++++++++++-- >>>   2 files changed, 21 insertions(+), 2 deletions(-) >>> >>> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig >>> index 2f2b501fda..6540013f97 100644 >>> --- a/xen/arch/arm/Kconfig >>> +++ b/xen/arch/arm/Kconfig >>> @@ -276,6 +276,15 @@ config PCI_PASSTHROUGH >>>     endmenu >>>   +config GICV3_NR_LRS >>> +    int "Number of GICv3 Link Registers supported" if EXPERT >> >> Supported by who? The hardware? Xen? Asking, because I could forsee an >> integrator wanted to limit the number of LRs to something smaller than >> what the HW supports (in a lot of cases, 2 LRs is sufficient). > > Ack > >  ... "Number of GICv3 Link Registers used" if EXPERT > > So it implies a decision to be taken by the system integrator. Does it > sound ok ? Either "used" or "allowed" would be fine. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Apr 28 15:27:32 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 15:27:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296473.1572888 (Exim 4.92) (envelope-from ) id 1wHkLP-00059r-0n; Tue, 28 Apr 2026 15:27:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296473.1572888; Tue, 28 Apr 2026 15:27:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHkLO-00059k-Tz; Tue, 28 Apr 2026 15:27:26 +0000 Received: by outflank-mailman (input) for mailman id 1296473; Tue, 28 Apr 2026 15:27:25 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHkLN-00058f-QM for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 15:27:25 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHkLN-00GbAa-65 for xen-devel@lists.xenproject.org; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=gPnfE3i2wg7zvoKVRWncxs/JqV5yt7VVIOEdHbdeNAs=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=HcULH9J4pFWUmnj+olzrS5AxKslmG9HFP/nD3BJP5HNFb17TG9JjZjDHGuWu47tM4emhecWE1 Mk2J9xynXbSYLNM/jsQq4UGHocLXOTjak12JBMqDCo8mNJJS2TpxDJ2sJjxVMU+Ilm/ZkY57J8u R3/7mHWpXaaWA4c4sqvDFHyMoGHd/GdTT5aOblgyIvzSccByyHMIZpoQdPiM+EB1ery4j/2kilf ISFTN53OsGV9laVZySdvT685d26J6WN5BDoEffmn3Srf9DstavghhyMe/FyCD24L+QlV1sBDo6O shnVGWgKc0zCp6CU2urNf0GGQDNkrT8MjJUpYtcJHd2g== X-Zone-Loop: 30834fa9f8c989e48159e538aa8a3c14ad691e20e635 x-campaign-type: default x-transaction-id: e521da65-7d7a-45ea-9a09-f9ab5b7d0766 x-swg-uid: 01-23f4bfb3-cba9-4a2e-aa80-ff8c7920cd41 X-Mailer: Sweego Message-ID: <1777390038.8631fc262581453bbf619ec5b2062170.19dd4b3af44000f373@vates.tech> x-swg-bid: 1777390038.8631fc262581453bbf619ec5b2062170.19dd4b3af44000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 17:27:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/9] x86/hvm: Support extended destination IDs in virtual MSI and IO-APIC To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298081.8631fc262581453bbf619ec5b2062170.19dcf388512000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298081.8631fc262581453bbf619ec5b2062170.19dcf388512000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.eb.c5d8ae115ac7e90e.19dd4b3ad47.d3c253bc4b53bd84=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777390038343 X-purgate-ID: tlsNG-d25034/1777390045-F7A10CF5-9860A5B3/0/0 X-purgate-type: clean X-purgate-size: 8425 ---=Part.eb.c5d8ae115ac7e90e.19dd4b3ad47.d3c253bc4b53bd84=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Add IO_APIC_REDIR_DEST_MASK and IO_APIC_REDIR_EXT_DEST_MASK for the > standard and extended destination fields of the IO-APIC RTE, and a > VIOAPIC_RTE_DEST() helper that extracts the combined 15-bit destination > ID=2E Extend the IO-APIC RTE save/restore struct with an ext_dest_id fie= ld > so migration preserves the extended bits=2E >=20 > Use the newly defined masks to extract the full 15-bit destination ID > from guest MSI addresses and IO-APIC RTEs=2E In hvm_inject_msi() combine > the standard bits [19:12] with the extended bits [11:5] of the MSI > address into a 15-bit destination ID for LAPIC delivery=2E Widen the des= t > parameter of vmsi_deliver() and hvm_girq_dest_2_vcpu_id() from uint8_t > to uint32_t to accommodate the larger range=2E In vioapic_deliver() read > the combined 15-bit destination using the VIOAPIC_RTE_DEST() macro=2E > Extend ioapic_check() to check for extended destination bits set in a > domain that does not advertise XEN_HVM_CPUID_EXT_DEST_ID and refuse to > restore the IO-APIC state, preventing silent interrupt misrouting after > live migration=2E >=20 > Signed-off-by: Julian Vetter > --- > Changes in v4: > - Corresponds to v3 patch 3, but adapted for the new raw-addr/data > storage introduced in patch 5: > - In v3, vmsi_deliver_pirq() extracted the full destination from > gflags via XEN_DOMCTL_VMSI_X86_FULL_DEST(), and msi_gflags() > packed the extended address bits into gflags > - In v4 both helpers are gone=2E vmsi_deliver_pirq() reads > pirq_dpci->gmsi=2Eaddr and pirq_dpci->gmsi=2Edata directly using = the > standard MSI masks > - Moved the IO-APIC masks and VIOAPIC_RTE_DEST() helper (previously in > v3 patch 2) into this patch > - Added ioapic_check() ext destination safety check (refusing migration > with ext_dest_id bits set when XEN_HVM_CPUID_EXT_DEST_ID is not > advertised) > --- > xen/arch/x86/hvm/irq=2Ec | 9 ++++++++- > xen/arch/x86/hvm/vioapic=2Ec | 2 +- > xen/arch/x86/hvm/vmsi=2Ec | 4 ++-- > xen/arch/x86/include/asm/hvm/hvm=2Eh | 4 ++-- > xen/arch/x86/include/asm/hvm/vioapic=2Eh | 12 ++++++++++++ > xen/include/public/arch-x86/hvm/save=2Eh | 4 +++- > 6 files changed, 28 insertions(+), 7 deletions(-) >=20 > diff --git a/xen/arch/x86/hvm/irq=2Ec b/xen/arch/x86/hvm/irq=2Ec > index 5f64361113=2E=2Eb43adf8b96 100644 > --- a/xen/arch/x86/hvm/irq=2Ec > +++ b/xen/arch/x86/hvm/irq=2Ec > @@ -374,7 +374,14 @@ int hvm_set_pci_link_route(struct domain *d, u8 lin= k, u8 isa_irq) > int hvm_inject_msi(struct domain *d, uint64_t addr, uint32_t data) > { > uint32_t tmp =3D (uint32_t) addr; > - uint8_t dest =3D (tmp & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID= _SHIFT; > + /* > + * Standard MSI destination address bits 19:12 carry the 8-bit APIC= ID=2E > + * When XEN_HVM_CPUID_EXT_DEST_ID is enabled, bits 11:5 carry APIC = ID bits > + * [14:8], extending the addressable range to 15 bits=2E Guests tha= t do not > + * use extended IDs leave these bits at zero, so the combined extra= ction is > + * safe regardless=2E > + */ > + uint32_t dest =3D MSI_ADDR_DEST(tmp); > uint8_t dest_mode =3D !!(tmp & MSI_ADDR_DESTMODE_MASK); > uint8_t delivery_mode =3D (data & MSI_DATA_DELIVERY_MODE_MASK) > >> MSI_DATA_DELIVERY_MODE_SHIFT; > diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec > index 43fb165f84=2E=2E527cc770b7 100644 > --- a/xen/arch/x86/hvm/vioapic=2Ec > +++ b/xen/arch/x86/hvm/vioapic=2Ec > @@ -411,7 +411,7 @@ static void ioapic_inj_irq( > =20 > static void vioapic_deliver(struct hvm_vioapic *vioapic, unsigned int = pin) > { > - uint16_t dest =3D vioapic->redirtbl[pin]=2Efields=2Edest_id; > + uint32_t dest =3D VIOAPIC_RTE_DEST(vioapic->redirtbl[pin]=2Ebits); > uint8_t dest_mode =3D vioapic->redirtbl[pin]=2Efields=2Edest_mode; > uint8_t delivery_mode =3D vioapic->redirtbl[pin]=2Efields=2Edelive= ry_mode; > uint8_t vector =3D vioapic->redirtbl[pin]=2Efields=2Evector; > diff --git a/xen/arch/x86/hvm/vmsi=2Ec b/xen/arch/x86/hvm/vmsi=2Ec > index 2a4b97e2e1=2E=2E7b338c4ddc 100644 > --- a/xen/arch/x86/hvm/vmsi=2Ec > +++ b/xen/arch/x86/hvm/vmsi=2Ec > @@ -67,7 +67,7 @@ static void vmsi_inj_irq( > =20 > int vmsi_deliver( > struct domain *d, int vector, > - uint8_t dest, uint8_t dest_mode, > + uint32_t dest, uint8_t dest_mode, > uint8_t delivery_mode, uint8_t trig_mode) > { > struct vlapic *target; > @@ -126,7 +126,7 @@ void vmsi_deliver_pirq(struct domain *d, const struc= t hvm_pirq_dpci *pirq_dpci) > } > =20 > /* Return value, -1 : multi-dests, non-negative value: dest_vcpu_id */ > -int hvm_girq_dest_2_vcpu_id(struct domain *d, uint8_t dest, uint8_t des= t_mode) > +int hvm_girq_dest_2_vcpu_id(struct domain *d, uint32_t dest, uint8_t de= st_mode) > { > int dest_vcpu_id =3D -1, w =3D 0; > struct vcpu *v; > diff --git a/xen/arch/x86/include/asm/hvm/hvm=2Eh b/xen/arch/x86/include= /asm/hvm/hvm=2Eh > index e7c1364802=2E=2E884dd44c81 100644 > --- a/xen/arch/x86/include/asm/hvm/hvm=2Eh > +++ b/xen/arch/x86/include/asm/hvm/hvm=2Eh > @@ -294,11 +294,11 @@ uint64_t hvm_get_guest_time_fixed(const struct vcp= u *v, uint64_t at_tsc); > =20 > int vmsi_deliver( > struct domain *d, int vector, > - uint8_t dest, uint8_t dest_mode, > + uint32_t dest, uint8_t dest_mode, > uint8_t delivery_mode, uint8_t trig_mode); > struct hvm_pirq_dpci; > void vmsi_deliver_pirq(struct domain *d, const struct hvm_pirq_dpci *p= irq_dpci); > -int hvm_girq_dest_2_vcpu_id(struct domain *d, uint8_t dest, uint8_t des= t_mode); > +int hvm_girq_dest_2_vcpu_id(struct domain *d, uint32_t dest, uint8_t de= st_mode); > =20 > enum hvm_intblk > hvm_interrupt_blocked(struct vcpu *v, struct hvm_intack intack); > diff --git a/xen/arch/x86/include/asm/hvm/vioapic=2Eh b/xen/arch/x86/inc= lude/asm/hvm/vioapic=2Eh > index 68af6dce79=2E=2E4499208bad 100644 > --- a/xen/arch/x86/include/asm/hvm/vioapic=2Eh > +++ b/xen/arch/x86/include/asm/hvm/vioapic=2Eh > @@ -32,6 +32,18 @@ > #define VIOAPIC_EDGE_TRIG 0 > #define VIOAPIC_LEVEL_TRIG 1 > =20 > +/* > + * Extract the destination ID from a 64-bit IO-APIC RTE, including the > + * extended bits (55:49) used when XEN_HVM_CPUID_EXT_DEST_ID is adverti= sed=2E > + */ > +#define IO_APIC_REDIR_DEST_MASK (0xffULL << 56) > +#define IO_APIC_REDIR_EXT_DEST_MASK (0x7fULL << 49) > + > +#define VIOAPIC_RTE_DEST(rte) \ > + (MASK_EXTR((rte), IO_APIC_REDIR_DEST_MASK) | \ > + (MASK_EXTR((rte), IO_APIC_REDIR_EXT_DEST_MASK) << \ > + MSI_ADDR_DEST_ID_UPPER_BITS)) > + We can probably simplify that by using vioapic_redir_entry=2Edest_id and= =20 vioapic_redir_entry=2Eext_dest_id directly instead of reparsing it from=20 vioapic_redir_entry=2Ebits=2E IOW, replace MASK_EXTR((rte), IO_APIC_REDIR_DEST_MASK) with=20 (rte)=2Edest_id and MASK_EXTR((rte), IO_APIC_REDIR_EXT_DEST_MASK) with=20 (rte)=2Eext_dest_id=2E So VIOAPIC_RTE_DEST() would now take=20 vioapic_redir_entry as parameter=2E > #define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000U > #define VIOAPIC_MEM_LENGTH 0x100 > > diff --git a/xen/include/public/arch-x86/hvm/save=2Eh=20 b/xen/include/public/arch-x86/hvm/save=2Eh > index 9c4bfc7ebd=2E=2E483097d940 100644 > --- a/xen/include/public/arch-x86/hvm/save=2Eh > +++ b/xen/include/public/arch-x86/hvm/save=2Eh > @@ -359,7 +359,9 @@ union vioapic_redir_entry > uint8_t trig_mode:1; > uint8_t mask:1; > uint8_t reserve:7; > - uint8_t reserved[4]; > + uint8_t reserved[3]; > + uint8_t reserved2:1; > + uint8_t ext_dest_id:7; > uint8_t dest_id; > } fields; > }; Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.eb.c5d8ae115ac7e90e.19dd4b3ad47.d3c253bc4b53bd84=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 16:03:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 16:03:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296497.1572897 (Exim 4.92) (envelope-from ) id 1wHktx-0003e1-Oj; Tue, 28 Apr 2026 16:03:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296497.1572897; Tue, 28 Apr 2026 16:03:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHktx-0003dr-M5; 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Tue, 28 Apr 2026 16:02:58 +0000 Received: from [192.168.1.18] (88-175-170-134.subs.proxad.net [88.175.170.134]) (Authenticated sender: teddy.astie) by mail2.vates.fr (Postfix) with ESMTPSA id 325B1863A7; Tue, 28 Apr 2026 18:02:57 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=12w3LkEq+Kroj056n13Prx1D9hkZQ8hYxXOBZTHQMeo=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=RLjcJA4lq3IXqJ2LQqCly7YKYWBphCKQLliTC16pW04/Gz3hhNZ0jRTHX3sNYBoe9z8kJqVjq cBBKMCiY5krUpfoTCPozYuBuy27+G2FB0uS9Fz6ZfJjER06yD2H53CP4iyy3oklToeJoM1N1FMb cWbqKSLpvr+HwEdO3+YLFeNPwqWatjMXnbYJw9HHaeyW6LLiXKbEyzLdRGlYOSeAYpRogT5Voap v5cg/Gy0hU54EGp1LJuSpjMavtGE2cfT9W4t7HMnNLieB4AwRLp1CpU9vV7HvXi2Lx1bMf1Xh7t Vvd9/vq8Eug9OraJyRZwkL3TCLMXKus5yez1FQ4rkz9Q== X-Zone-Loop: ee6846bbdc250569945b10afad823a926ebe30cedc7d x-campaign-type: default x-transaction-id: b64b5276-2205-47be-809e-73bc80efa3a5 x-swg-uid: 01-ba4ee1b5-8084-4983-85aa-eb0b3d659da7 X-Mailer: Sweego Message-ID: <1777392179.8631fc262581453bbf619ec5b2062170.19dd4d45724000f373@vates.tech> x-swg-bid: 1777392179.8631fc262581453bbf619ec5b2062170.19dd4d45724000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Tue, 28 Apr 2026 18:02:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 7/9] x86/dmop: Add XEN_DMOP_{bind,unbind}_pt_msi_irq DM ops To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298081.8631fc262581453bbf619ec5b2062170.19dcf388597000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298081.8631fc262581453bbf619ec5b2062170.19dcf388597000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.114.c353c9af6e1e11b1.19dd4d4510a.1ce65ceed8f475cd=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777392177418 X-purgate-ID: tlsNG-ef75cf/1777392185-AE772C48-5969ADAC/0/0 X-purgate-type: clean X-purgate-size: 17834 ---=Part.114.c353c9af6e1e11b1.19dd4d4510a.1ce65ceed8f475cd=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Add two DM ops for MSI passthrough IRQs=2E These new DM ops take the raw > MSI address and data fields rather than pre-decoded gflags values=2E Xen > decodes the destination ID via msi_addr_to_gflags(), including any > extended destination bits in address[11:5]=2E This means the device mode= l > does not need to understand the extended destination ID encoding, and > simply forwards the MSI address it observes from the guest=2E >=20 > With these DM ops in place, redirect xc_domain_update_msi_irq() and > xc_domain_unbind_msi_irq() in libxenctrl to use > xendevicemodel_bind_pt_msi_irq() / xendevicemodel_unbind_pt_msi_irq() > via xch->dmod=2E The gflags/gvec arguments are translated to the raw MSI > address and data words at the libxc level using the standard x86 MSI > address format=2E >=20 > Reject the PT_IRQ_TYPE_MSI sub-case in XEN_DOMCTL_bind_pt_irq and > XEN_DOMCTL_unbind_pt_irq: all callers now go through the DM op path, so > the domctl sub-case is fully obsolete=2E >=20 We probably want to reflect that on XEN_DOMCTL_{un}bind_pt_irq interface= =20 in domctl=2Eh (e=2Eg through a note saying that PT_IRQ_TYPE_MSI type is no= w=20 deprecated and unsupported)=2E > Signed-off-by: Julian Vetter > --- > Changes in v4: > - Corresponds to v3 patch 5, but with feedback from Jan > - Redirect xc_domain_{update,unbind}_msi_irq() in libxenctrl to call > xendevicemodel_{un}bind_pt_msi_irq() via xch->dmod, translating the > existing gflags/gvec arguments to raw MSI address and data in libxc > - As suggested by Jan, reject the PT_IRQ_TYPE_MSI sub-case in > XEN_DOMCTL_{bind,unbind}_pt_irq with -EOPNOTSUPP -> All callers now g= o > through the DM op path, making the domctl sub-case fully obsolete > - Added the xlat=2Elst entry for dm_op_unbind_pt_msi_irq (v3 added only = the > bind entry) > --- > tools/include/xendevicemodel=2Eh | 31 ++++++++++++++ > tools/libs/ctrl/xc_domain=2Ec | 52 +++++++++++------------ > tools/libs/devicemodel/core=2Ec | 38 +++++++++++++++++ > xen/arch/x86/domctl=2Ec | 10 ++++- > xen/arch/x86/hvm/dm=2Ec | 68 +++++++++++++++++++++++++++++= ++ > xen/drivers/passthrough/x86/hvm=2Ec | 1 - > xen/include/public/hvm/dm_op=2Eh | 37 +++++++++++++++++ > xen/include/xlat=2Elst | 2 + > 8 files changed, 208 insertions(+), 31 deletions(-) >=20 > diff --git a/tools/include/xendevicemodel=2Eh b/tools/include/xendevicem= odel=2Eh > index 227e7fd810=2E=2Ef15b35fa33 100644 > --- a/tools/include/xendevicemodel=2Eh > +++ b/tools/include/xendevicemodel=2Eh > @@ -375,6 +375,37 @@ int xendevicemodel_nr_vcpus( > */ > int xendevicemodel_restrict(xendevicemodel_handle *dmod, domid_t domid= ); > =20 > +/** > + * This function binds a passthrough physical IRQ to a guest MSI vector > + * using raw MSI address/data fields=2E Unlike XEN_DOMCTL_bind_pt_irq, > + * this interface supports extended (15-bit) destination IDs by having > + * Xen decode the MSI address internally=2E > + * "unlike XEN_DOMCTL_bind_pt_irq" feels a bit odd since that's not a=20 supported interface anymore for MSI=2E > + * @parm dmod a handle to an open devicemodel interface=2E > + * @parm domid the domain id to be serviced=2E > + * @parm machine_irq the physical IRQ number (pirq)=2E > + * @parm msi_addr the MSI address (includes ext=2E dest=2E ID bits [11:= 5])=2E > + * @parm msi_data the MSI data word (bits [7:0] are the guest vector)= =2E > + * @parm gtable the MSI-X table base GFN, or 0 for plain MSI=2E > + * @parm unmasked if non-zero, leave the IRQ unmasked after binding=2E > + * @return 0 on success, -1 on failure=2E > + */ > +int xendevicemodel_bind_pt_msi_irq( > + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq, > + uint64_t msi_addr, uint32_t msi_data, uint64_t gtable, int unmasked= ); > + > +/** > + * This function unbinds a passthrough physical IRQ previously bound > + * with xendevicemodel_bind_pt_msi_irq=2E > + * > + * @parm dmod a handle to an open devicemodel interface=2E > + * @parm domid the domain id to be serviced=2E > + * @parm machine_irq the physical IRQ number (pirq)=2E > + * @return 0 on success, -1 on failure=2E > + */ > +int xendevicemodel_unbind_pt_msi_irq( > + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq); > + > #endif /* XENDEVICEMODEL_H */ > =20 > /* > diff --git a/tools/libs/ctrl/xc_domain=2Ec b/tools/libs/ctrl/xc_domain= =2Ec > index 01c0669c88=2E=2E7e3b7a0dc6 100644 > --- a/tools/libs/ctrl/xc_domain=2Ec > +++ b/tools/libs/ctrl/xc_domain=2Ec > @@ -1677,6 +1677,21 @@ int xc_deassign_dt_device( > =20 > =20 > =20 > +static void xc_msi_gflags_to_addr_data(uint32_t gvec, uint32_t gflags, > + uint64_t *msi_addr, uint32_t *m= si_data) > +{ > + *msi_addr =3D 0xfee00000U | > + ((uint64_t)((gflags & XEN_DOMCTL_VMSI_X86_DEST_ID_MASK) << 12))= | > + (gflags & XEN_DOMCTL_VMSI_X86_RH_MASK ? (1U << 3) : 0) | > + (gflags & XEN_DOMCTL_VMSI_X86_DM_MASK ? (1U << 2) : 0); > + > + *msi_data =3D (gvec & 0xff) | > + (uint32_t)(((gflags & XEN_DOMCTL_VMSI_X86_DELIV_MASK) >> > + (/* shift of XEN_DOMCTL_VMSI_X86_DELIV_MASK */ 12 - > + /* MSI data delivery shift */ 8))) | > + (gflags & XEN_DOMCTL_VMSI_X86_TRIG_MASK ? (1U << 15) : 0); > +} > + > int xc_domain_update_msi_irq( > xc_interface *xch, > uint32_t domid, > @@ -1685,22 +1700,15 @@ int xc_domain_update_msi_irq( > uint32_t gflags, > uint64_t gtable) > { > - int rc; > - struct xen_domctl_bind_pt_irq *bind; > - struct xen_domctl domctl =3D {}; > - > - domctl=2Ecmd =3D XEN_DOMCTL_bind_pt_irq; > - domctl=2Edomain =3D domid; > + uint64_t msi_addr; > + uint32_t msi_data; > + int unmasked =3D !!(gflags & XEN_DOMCTL_VMSI_X86_UNMASKED); > =20 > - bind =3D &(domctl=2Eu=2Ebind_pt_irq); > - bind->irq_type =3D PT_IRQ_TYPE_MSI; > - bind->machine_irq =3D pirq; > - bind->u=2Emsi=2Egvec =3D gvec; > - bind->u=2Emsi=2Egflags =3D gflags; > - bind->u=2Emsi=2Egtable =3D gtable; > + xc_msi_gflags_to_addr_data(gvec, gflags, &msi_addr, &msi_data); > =20 > - rc =3D do_domctl(xch, &domctl); > - return rc; > + return xendevicemodel_bind_pt_msi_irq(xch->dmod, domid, pirq, > + msi_addr, msi_data, gtable, > + unmasked); > } > =20 > int xc_domain_unbind_msi_irq( > @@ -1710,21 +1718,7 @@ int xc_domain_unbind_msi_irq( > uint32_t pirq, > uint32_t gflags) > { > - int rc; > - struct xen_domctl_bind_pt_irq *bind; > - struct xen_domctl domctl =3D {}; > - > - domctl=2Ecmd =3D XEN_DOMCTL_unbind_pt_irq; > - domctl=2Edomain =3D domid; > - > - bind =3D &(domctl=2Eu=2Ebind_pt_irq); > - bind->irq_type =3D PT_IRQ_TYPE_MSI; > - bind->machine_irq =3D pirq; > - bind->u=2Emsi=2Egvec =3D gvec; > - bind->u=2Emsi=2Egflags =3D gflags; > - > - rc =3D do_domctl(xch, &domctl); > - return rc; > + return xendevicemodel_unbind_pt_msi_irq(xch->dmod, domid, pirq); > } > =20 > /* Pass-through: binds machine irq to guests irq */ > diff --git a/tools/libs/devicemodel/core=2Ec b/tools/libs/devicemodel/co= re=2Ec > index 8e619eeb0a=2E=2Eadf2c41a96 100644 > --- a/tools/libs/devicemodel/core=2Ec > +++ b/tools/libs/devicemodel/core=2Ec > @@ -645,6 +645,44 @@ int xendevicemodel_nr_vcpus( > return 0; > } > =20 > +int xendevicemodel_bind_pt_msi_irq( > + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq, > + uint64_t msi_addr, uint32_t msi_data, uint64_t gtable, int unmasked= ) > +{ > + struct xen_dm_op op; > + struct xen_dm_op_bind_pt_msi_irq *data; > + > + memset(&op, 0, sizeof(op)); > + > + op=2Eop =3D XEN_DMOP_bind_pt_msi_irq; > + data =3D &op=2Eu=2Ebind_pt_msi_irq; > + > + data->machine_irq =3D machine_irq; > + data->data =3D msi_data; > + data->addr =3D msi_addr; > + data->gtable =3D gtable; > + if ( unmasked ) > + data->flags |=3D XEN_DMOP_MSI_FLAG_UNMASKED; > + > + return xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); > +} > + > +int xendevicemodel_unbind_pt_msi_irq( > + xendevicemodel_handle *dmod, domid_t domid, uint32_t machine_irq) > +{ > + struct xen_dm_op op; > + struct xen_dm_op_unbind_pt_msi_irq *data; > + > + memset(&op, 0, sizeof(op)); > + > + op=2Eop =3D XEN_DMOP_unbind_pt_msi_irq; > + data =3D &op=2Eu=2Eunbind_pt_msi_irq; > + > + data->machine_irq =3D machine_irq; > + > + return xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); > +} > + I think we want to mark=20 xc_domain_update_msi_irq/xc_domain_unbind_msi_irq as deprecated since we= =20 implemented a newer (better) version of it in xendevicemodel; and the=20 old one is now a wrapper=2E > int xendevicemodel_restrict(xendevicemodel_handle *dmod, domid_t domid= ) > { > return osdep_xendevicemodel_restrict(dmod, domid); > diff --git a/xen/arch/x86/domctl=2Ec b/xen/arch/x86/domctl=2Ec > index bfbc35c08b=2E=2Ed80a33fe40 100644 > --- a/xen/arch/x86/domctl=2Ec > +++ b/xen/arch/x86/domctl=2Ec > @@ -574,6 +574,14 @@ long arch_do_domctl( > if ( !is_hvm_domain(d) ) > break; > =20 > + /* > + * PT_IRQ_TYPE_MSI is obsoleted by XEN_DMOP_bind_pt_msi_irq, wh= ich > + * passes raw MSI address/data so Xen can decode extended desti= nation > + * ID bits=2E Device models must use the DM op path instead=2E > + */ > + if ( bind->irq_type =3D=3D PT_IRQ_TYPE_MSI ) > + break; > + > ret =3D xsm_bind_pt_irq(XSM_HOOK, d, bind); > if ( ret ) > break; > @@ -602,7 +610,7 @@ long arch_do_domctl( > int irq =3D domain_pirq_to_irq(d, bind->machine_irq); > =20 > ret =3D -EINVAL; > - if ( !is_hvm_domain(d) ) > + if ( !is_hvm_domain(d) || bind->irq_type =3D=3D PT_IRQ_TYPE_MSI= ) > break; > =20 > ret =3D -EPERM; > diff --git a/xen/arch/x86/hvm/dm=2Ec b/xen/arch/x86/hvm/dm=2Ec > index 3b53471af0=2E=2Eac70cb6405 100644 > --- a/xen/arch/x86/hvm/dm=2Ec > +++ b/xen/arch/x86/hvm/dm=2Ec > @@ -7,6 +7,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > #include > @@ -350,6 +352,8 @@ int dm_op(const struct dmop_args *op_args) > [XEN_DMOP_relocate_memory] =3D sizeof(struct = xen_dm_op_relocate_memory), > [XEN_DMOP_pin_memory_cacheattr] =3D sizeof(struct = xen_dm_op_pin_memory_cacheattr), > [XEN_DMOP_nr_vcpus] =3D sizeof(struct = xen_dm_op_nr_vcpus), > + [XEN_DMOP_bind_pt_msi_irq] =3D sizeof(struct x= en_dm_op_bind_pt_msi_irq), > + [XEN_DMOP_unbind_pt_msi_irq] =3D sizeof(struct x= en_dm_op_unbind_pt_msi_irq), > }; > =20 > rc =3D rcu_lock_remote_domain_by_id(op_args->domid, &d); > @@ -607,6 +611,68 @@ int dm_op(const struct dmop_args *op_args) > break; > } > =20 > + case XEN_DMOP_bind_pt_msi_irq: > + { > + const struct xen_dm_op_bind_pt_msi_irq *data =3D > + &op=2Eu=2Ebind_pt_msi_irq; > + int irq; > + > + rc =3D -EINVAL; > + if ( data->pad || (data->flags & ~XEN_DMOP_MSI_FLAG_UNMASKED) ) > + break; > + > + irq =3D domain_pirq_to_irq(d, data->machine_irq); > + > + rc =3D -EPERM; > + if ( irq <=3D 0 || !irq_access_permitted(current->domain, irq) = ) > + break; > + > + rc =3D -ESRCH; > + if ( is_iommu_enabled(d) ) > + { > + read_lock(&d->pci_lock); > + rc =3D pt_irq_bind_msi(d, data->machine_irq, data->addr, da= ta->data, > + data->gtable, > + !!(data->flags & XEN_DMOP_MSI_FLAG_UNM= ASKED)); > + read_unlock(&d->pci_lock); > + } > + if ( rc < 0 ) > + printk(XENLOG_G_ERR > + "XEN_DMOP_bind_pt_msi_irq: pt_irq_bind_msi failed (%= ld) for %pd\n", > + rc, d); > + break; > + } > + > + case XEN_DMOP_unbind_pt_msi_irq: > + { > + const struct xen_dm_op_unbind_pt_msi_irq *data =3D > + &op=2Eu=2Eunbind_pt_msi_irq; > + struct xen_domctl_bind_pt_irq bind =3D { > + =2Emachine_irq =3D data->machine_irq, > + =2Eirq_type =3D PT_IRQ_TYPE_MSI, > + }; > + int irq; > + > + irq =3D domain_pirq_to_irq(d, bind=2Emachine_irq); > + > + rc =3D -EPERM; > + if ( irq <=3D 0 || !irq_access_permitted(current->domain, irq) = ) > + break; > + > + rc =3D -ESRCH; > + if ( is_iommu_enabled(d) ) > + { > + read_lock(&d->pci_lock); > + rc =3D pt_irq_destroy_bind(d, &bind); > + read_unlock(&d->pci_lock); > + } > + if ( rc < 0 ) > + printk(XENLOG_G_ERR > + "XEN_DMOP_unbind_pt_msi_irq: pt_irq_destroy_bind fai= led (%ld) for %pd\n", > + rc, d); > + break; > + } > + > default: > rc =3D ioreq_server_dm_op(&op, d, &const_op); > break; > @@ -643,6 +709,8 @@ CHECK_dm_op_remote_shutdown; > CHECK_dm_op_relocate_memory; > CHECK_dm_op_pin_memory_cacheattr; > CHECK_dm_op_nr_vcpus; > +CHECK_dm_op_bind_pt_msi_irq; > +CHECK_dm_op_unbind_pt_msi_irq; > =20 > int compat_dm_op( > domid_t domid, unsigned int nr_bufs, XEN_GUEST_HANDLE_PARAM(void) = bufs) > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index 026534530f=2E=2E6fb4f8b7dc 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -21,7 +21,6 @@ > #include > #include > #include > -#include > #include > #include > #include > diff --git a/xen/include/public/hvm/dm_op=2Eh b/xen/include/public/hvm/d= m_op=2Eh > index 2bf0fdc1ae=2E=2E43571b7713 100644 > --- a/xen/include/public/hvm/dm_op=2Eh > +++ b/xen/include/public/hvm/dm_op=2Eh > @@ -444,6 +444,41 @@ struct xen_dm_op_nr_vcpus { > }; > typedef struct xen_dm_op_nr_vcpus xen_dm_op_nr_vcpus_t; > =20 > +#define XEN_DMOP_bind_pt_msi_irq 21 > +#define XEN_DMOP_unbind_pt_msi_irq 22 > + > +struct xen_dm_op_bind_pt_msi_irq { > + /* IN - physical IRQ (pirq) */ > + uint32_t machine_irq; > + /* IN - MSI data word (bits [7:0] are the guest vector) */ > + uint32_t data; > + /* IN - flags */ > + uint32_t flags; > +#define XEN_DMOP_MSI_FLAG_UNMASKED (1u << 0) > + uint32_t pad; > + /* IN - MSI address (includes extended destination ID in bits [11:5= ]) */ > + uint64_aligned_t addr; > + /* IN - MSI-X table base GFN, 0 for plain MSI */ > + uint64_aligned_t gtable; > +}; > + > +typedef struct xen_dm_op_bind_pt_msi_irq xen_dm_op_bind_pt_msi_irq_t; > + > +struct xen_dm_op_unbind_pt_msi_irq { > + /* IN - physical IRQ (pirq) */ > + uint32_t machine_irq; > +}; > +typedef struct xen_dm_op_unbind_pt_msi_irq xen_dm_op_unbind_pt_msi_irq_= t; > + > +/* > + * XEN_DMOP_enable_ext_dest_id: Signal to Xen that this device model wi= ll use > + * XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings, passing r= aw MSI > + * address/data fields=2E Once called, Xen will advertise > + * XEN_HVM_CPUID_EXT_DEST_ID to the guest=2E Must be called before the = guest > + * starts=2E > + */ > +#define XEN_DMOP_enable_ext_dest_id 23 > + > struct xen_dm_op { > uint32_t op; > uint32_t pad; > @@ -468,6 +503,8 @@ struct xen_dm_op { > xen_dm_op_relocate_memory_t relocate_memory; > xen_dm_op_pin_memory_cacheattr_t pin_memory_cacheattr; > xen_dm_op_nr_vcpus_t nr_vcpus; > + xen_dm_op_bind_pt_msi_irq_t bind_pt_msi_irq; > + xen_dm_op_unbind_pt_msi_irq_t unbind_pt_msi_irq; > } u; > }; > =20 > diff --git a/xen/include/xlat=2Elst b/xen/include/xlat=2Elst > index 9d08dcc4bb=2E=2E6dc5f5796a 100644 > --- a/xen/include/xlat=2Elst > +++ b/xen/include/xlat=2Elst > @@ -98,6 +98,7 @@ > ? grant_entry_v2 grant_table=2Eh > =20 > ! dm_op_buf hvm/dm_op=2Eh > +? dm_op_bind_pt_msi_irq hvm/dm_op=2Eh > ? dm_op_create_ioreq_server hvm/dm_op=2Eh > ? dm_op_destroy_ioreq_server hvm/dm_op=2Eh > ? dm_op_get_ioreq_server_info hvm/dm_op=2Eh > @@ -116,6 +117,7 @@ > ? dm_op_set_pci_intx_level hvm/dm_op=2Eh > ? dm_op_set_pci_link_route hvm/dm_op=2Eh > ? dm_op_track_dirty_vram hvm/dm_op=2Eh > +? dm_op_unbind_pt_msi_irq hvm/dm_op=2Eh > =20 > ! hvm_altp2m_set_mem_access_multi hvm/hvm_op=2Eh > =20 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.114.c353c9af6e1e11b1.19dd4d4510a.1ce65ceed8f475cd=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 16:31:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 16:31:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296514.1572907 (Exim 4.92) (envelope-from ) id 1wHlL9-0008NB-T6; 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[85.223.209.22]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7b5acd00sm4244805e9.15.2026.04.28.09.31.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 09:31:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:In-Reply-To:From:Content-Language:References:Cc:To:Subject:User-Agent:MIME-Version:Date:Message-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777393873; x=1777998673; darn=lists.xenproject.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=csOwj0EBmE4ylOTZBavg92OZiArFyAaHzc333vZFscU=; b=nk3KVv2oSk7+E/ltydk9gBH6CziJ9dyKM3hWgGsYB+LDXrHaKVuiwutaJ8tEP4QfFn dcyHRXtjSmUoflZSnZsuCbIwxCWxDx8GIcRbgq7cYwLrDsqbpsjVFtvJeZegk1lHtoOi vlFTNmQg/NGEvIldCuTotCUxK9rW6I3WtjbrdvOPUKAzD81rWPZobw8/Tx+uqpTuRRVB Bus+6uj/jBMiON/86+rEwaWjKr8titQhJhVjmI52G5L+ZwJB170Z0d5bKg5sw/5X9sZq OqroHD34M2y1OBVo4dv8VWqpvhJ1zIRDS/chd0w3uIC9rA9dccRsjRjWLID1SiZ5lEAV FgFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777393873; x=1777998673; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=csOwj0EBmE4ylOTZBavg92OZiArFyAaHzc333vZFscU=; b=KSjb7dKRACKkl1UN3J3IozuftVqYD4GOOcGpCK0ufGfPpwlGvUOWLfhzs0ZjOVmwjA lfWU7KciqLrALrQjisxmKe/puglN1SsnN8z6wDVhgA4bnQOD7Rd0sK2B1S+PK90YxhdA AInnzCtjHKglzPYBaPWc5pMg1n7RT0v2paNICdyHnmNyaWLIK0vO0c3RNRsVv6f6+FKa UToxFXXhez8rn3r8wVz7BvSW4Yv+EU/I7TPEoPnM5a0BZ159PI3bDlqej7CzpzyBT2Ro 497hmAsViDVoogLh/YsRQ4iA3xusGUjuxHUDkAwvEnQEqc9CXBhjYmvDkctkNTvqXXC4 yw0g== X-Forwarded-Encrypted: i=1; AFNElJ85dgl0M/jFjQ71SaZ0MbESYnUqXlWQFMp0sq7LWAfSWX1AxS1qzRekPbwmyGPFLo2ctlZe1N+VcBw=@lists.xenproject.org X-Gm-Message-State: AOJu0YxLldav83eITa9wwZMl9A2Bo5VJlzeSK3NY4NMAL8emG6jj1uJq T8HbfYssvEQWuaII2rJizjjhAsiuGE+wxeIrVqKWd7RU6e4IjQGZAHH5YgMybg== X-Gm-Gg: AeBDieuskzBFLAi0SGXT/h/XDcy6XzTaPm4mdDfS+/FZP+sXos8/w0XcX4jT96AVs2d Z/4Z3rIlGyCWX0DGCZoHH2KgLMMC8z3xUbBPGE91jiOTNYvN7Y0OKj5/4rw86kvI7vuoWKPD3sY fog3LJEZ3xfqAapBIRiLstjZvKOK5ZJEKC/Lj9fphrL9SYNGM2mbx6jwpA6p/4akY94sC+gstOH 8jkoqa2zsbwRSM4NTZ6SjOvoRJBFRWPNxMyTV8cQoc0RFdi02R7/BXfWpSWQ+U7oxHAfY5Ji1ru 842Wf8M+74pr7B/0r2bHoSgm8NoG0soX+ekjywoScT3EvFiRtIpADUOkzbqeUrdNGaxcxRhde9N IMU3yUuoZ3QI6VudeTXECFp2fr+JenBg82niqaaoDBQT05B6g+tMNW7HaLzQ4BStzPtCvRreQ6G q0s8cP3dzC9tWRqYHsIw2EQBJ7hkS8d3F+h9Ix/dgqj11F9Pk6p9aHMbemb3ZqXuQcEw== X-Received: by 2002:a05:600c:c08f:b0:489:1b10:d896 with SMTP id 5b1f17b1804b1-48a7b4d165cmr5778515e9.0.1777393872946; Tue, 28 Apr 2026 09:31:12 -0700 (PDT) Message-ID: <6b78dcf3-7e4c-4568-a0fd-58d5c860e4fa@gmail.com> Date: Tue, 28 Apr 2026 19:31:09 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] xen/arm: its: pre-initialize ITS quirks before LPI setup To: Mykola Kvach , xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk References: Content-Language: en-US From: Oleksandr Tyshchenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-purgate-ID: tlsNG-ef75cf/1777393873-2B175C48-591AB5A5/0/0 X-purgate-type: clean X-purgate-size: 8219 On 3/25/26 12:38, Mykola Kvach wrote: Hello Mykola > From: Mykola Kvach > > In the current initialization flow, gicv3_init() calls gicv3_dist_init() > before gicv3_its_init(). > > When LPIs are supported, gicv3_dist_init() calls > gicv3_lpi_init_host_lpis(), which initializes host LPI state and allocates > the boot CPU pending table before ITS quirk flags are computed. Non-boot > CPUs allocate their pending tables later from the CPU_UP_PREPARE notifier, > while redistributor LPI programming happens separately in > gicv3_lpi_init_rdist(). > > This means the boot CPU LPI setup can observe default ITS memory attributes > before dma-noncoherent and other ITS quirks are applied. > > Introduce gicv3_its_preinit() and call it before gicv3_dist_init(). This > keeps the actual ITS hardware initialization in gicv3_its_init(), but moves > ITS discovery, quirk validation and quirk flag setup early enough for the > subsequent LPI initialization to use the correct attributes. Have you considered an alternative approach that might be less invasive? I am thinking of something the other way around: perhaps we could allocate the LPI pending table for the boot CPU later. Would a diff below work? --- xen/arch/arm/gic-v3-lpi.c | 9 +++++++++ xen/arch/arm/gic-v3.c | 2 ++ xen/arch/arm/include/asm/gic_v3_its.h | 6 ++++++ 3 files changed, 17 insertions(+) diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 9ee338edc2..61cc45d347 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -450,6 +450,15 @@ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) printk("GICv3: using at most %lu LPIs on the host.\n", MAX_NR_HOST_LPIS); + return rc; +} + +int gicv3_lpi_post_init_host_lpis(void) +{ + int rc; + + ASSERT(smp_processor_id() == 0); + /* Register the CPU notifier and allocate memory for the boot CPU */ register_cpu_notifier(&cpu_nfb); rc = gicv3_lpi_allocate_pendtable(smp_processor_id()); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 7f365cdbe9..8b9059c5c9 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1981,6 +1981,8 @@ static int __init gicv3_init(void) res = gicv3_its_init(); if ( res ) panic("GICv3: ITS: initialization failed: %d\n", res); + + gicv3_lpi_post_init_host_lpis(); } res = gicv3_cpu_init(); diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index fc5a84892c..288cc1d42f 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -156,6 +156,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); /* Initialize the host structures for LPIs and the host ITSes. */ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); +int gicv3_lpi_post_init_host_lpis(void); int gicv3_its_init(void); /* Store the physical address and ID for each redistributor as read from DT. */ @@ -245,6 +246,11 @@ static inline int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits) return 0; } +static inline int gicv3_lpi_post_init_host_lpis(void) +{ + return 0; +} + static inline int gicv3_its_init(void) { return 0; -- 2.34.1 > > Signed-off-by: Mykola Kvach > --- > TODO: Think about separating Redistributor/LPI attributes from ITS. > --- > xen/arch/arm/gic-v3-its.c | 36 +++++++++++++++++---------- > xen/arch/arm/gic-v3.c | 7 ++++++ > xen/arch/arm/include/asm/gic_v3_its.h | 5 ++++ > 3 files changed, 35 insertions(+), 13 deletions(-) > > diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c > index ee432088cd..0251d91630 100644 > --- a/xen/arch/arm/gic-v3-its.c > +++ b/xen/arch/arm/gic-v3-its.c > @@ -63,6 +63,7 @@ struct its_quirk { > uint32_t flags; > }; > > +/* TODO: Separate Redistributor/LPI attributes from ITS quirks. */ > static uint32_t __ro_after_init its_quirk_flags; > > static bool gicv3_its_match_quirk_gen4(const struct host_its *hw_its) > @@ -148,9 +149,15 @@ static uint32_t gicv3_its_collect_quirks(const struct host_its *hw_its, > return flags; > } > > -static void gicv3_its_enable_quirks(struct host_its *hw_its) > +static void gicv3_its_enable_quirks(void) > { > const struct its_quirk *quirk; > + const struct host_its *hw_its; > + > + if ( list_empty(&host_its_list) ) > + return; > + > + hw_its = list_first_entry(&host_its_list, struct host_its, entry); > > its_quirk_flags = gicv3_its_collect_quirks(hw_its, &quirk); > > @@ -603,16 +610,10 @@ static int gicv3_its_init_single_its(struct host_its *hw_its) > uint64_t reg; > int i, ret; > > - hw_its->its_base = ioremap_nocache(hw_its->addr, hw_its->size); > - if ( !hw_its->its_base ) > - return -ENOMEM; > - > ret = gicv3_disable_its(hw_its); > if ( ret ) > return ret; > > - gicv3_its_enable_quirks(hw_its); > - > reg = readq_relaxed(hw_its->its_base + GITS_TYPER); > hw_its->devid_bits = GITS_TYPER_DEVICE_ID_BITS(reg); > hw_its->evid_bits = GITS_TYPER_EVENT_ID_BITS(reg); > @@ -1161,6 +1162,11 @@ static void add_to_host_its_list(paddr_t addr, paddr_t size, > its_data->size = size; > its_data->dt_node = node; > > + its_data->its_base = ioremap_nocache(its_data->addr, its_data->size); > + if ( !its_data->its_base ) > + panic("GICv3: Cannot map ITS frame: 0x%lx, 0x%lx\n", > + its_data->addr, its_data->size); > + > printk("GICv3: Found ITS @0x%lx\n", addr); > > list_add_tail(&its_data->entry, &host_its_list); > @@ -1238,16 +1244,22 @@ static void gicv3_its_acpi_init(void) > > #endif > > -int gicv3_its_init(void) > +void __init gicv3_its_preinit(void) > { > - struct host_its *hw_its; > - int ret; > - > if ( acpi_disabled ) > gicv3_its_dt_init(dt_interrupt_controller); > else > gicv3_its_acpi_init(); > > + gicv3_its_validate_quirks(); > + gicv3_its_enable_quirks(); > +} > + > +int gicv3_its_init(void) > +{ > + struct host_its *hw_its; > + int ret; > + > list_for_each_entry(hw_its, &host_its_list, entry) > { > ret = gicv3_its_init_single_its(hw_its); > @@ -1255,8 +1267,6 @@ int gicv3_its_init(void) > return ret; > } > > - gicv3_its_validate_quirks(); > - > return 0; > } > > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c > index bc07f97c16..6e44d23d64 100644 > --- a/xen/arch/arm/gic-v3.c > +++ b/xen/arch/arm/gic-v3.c > @@ -1974,6 +1974,13 @@ static int __init gicv3_init(void) > > spin_lock(&gicv3.lock); > > + if ( gic_dist_supports_lpis() ) > + /* > + * Apply ITS quirks before gicv3_dist_init() sets up host LPIs, > + * so pending tables use the correct ITS memory attributes. > + */ > + gicv3_its_preinit(); > + > gicv3_dist_init(); > > if ( gic_dist_supports_lpis() ) > diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h > index fc5a84892c..e1d7522ea5 100644 > --- a/xen/arch/arm/include/asm/gic_v3_its.h > +++ b/xen/arch/arm/include/asm/gic_v3_its.h > @@ -156,6 +156,7 @@ int gicv3_lpi_init_rdist(void __iomem * rdist_base); > > /* Initialize the host structures for LPIs and the host ITSes. */ > int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits); > +void gicv3_its_preinit(void); > int gicv3_its_init(void); > > /* Store the physical address and ID for each redistributor as read from DT. */ > @@ -219,6 +220,10 @@ static inline int gicv3_its_deny_access(struct domain *d) > return 0; > } > > +static inline void gicv3_its_preinit(void) > +{ > +} > + > static inline bool gicv3_its_host_has_its(void) > { > return false; From xen-devel-bounces@lists.xenproject.org Tue Apr 28 16:35:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 16:35:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296524.1572915 (Exim 4.92) (envelope-from ) id 1wHlPc-0000bP-IJ; Tue, 28 Apr 2026 16:35:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296524.1572915; Tue, 28 Apr 2026 16:35:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHlPc-0000bI-Fi; Tue, 28 Apr 2026 16:35:52 +0000 Received: by outflank-mailman (input) for mailman id 1296524; Tue, 28 Apr 2026 16:35:51 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with 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hvm/ioreq: Negotiate extended destination ID support per ioreq server To: Julian Vetter , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Juergen Gross , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk References: <20260427135406.1281424-1-julian.vetter@vates.tech> <1777298081.8631fc262581453bbf619ec5b2062170.19dcf3886cc000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: <1777298081.8631fc262581453bbf619ec5b2062170.19dcf3886cc000f373@vates.tech> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.128.637cd1b16475e87d.19dd4f25531.aed7cbd50075e8bd=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777394144561 X-purgate-ID: tlsNG-c1860d/1777394149-C196DDB1-B7AE958C/0/0 X-purgate-type: clean X-purgate-size: 21257 ---=Part.128.637cd1b16475e87d.19dd4f25531.aed7cbd50075e8bd=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 27/04/2026 =C3=A0 15:57, Julian Vetter a =C3=A9crit=C2=A0: > Add a per-server capability flag in XEN_DMOP_create_ioreq_server to > signal extended destination ID support=2E Repurpose the first byte of th= e > existing pad[3] as a flags field, and define > XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID (bit 0) for a server to signal it will > use XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings=2E >=20 > Track the flag in struct ioreq_server ext_dest_id=2E > hvm_ext_dest_id_enabled() returns true only if all registered ioreq > servers have opted in and at least one server is present=2E A single > server without the flag is sufficient to suppress the feature=2E >=20 > Lock the feature at domain creation time: > arch_domain_creation_finished() computes the levelled result into struct > hvm_domain=2Eext_dest_id using OR to preserve any value previously > restored from an HVM save record=2E After creation_finished, > arch_ioreq_server_create_check() rejects new servers that lack > XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID if the feature was already advertised > to the guest=2E >=20 > Persist the locked state in a new HVM_SAVE_TYPE(EXT_DEST_ID) record so > that migration preserves the guest-visible CPUID bit independently of > when the device model re-registers its ioreq servers on the destination > host=2E >=20 > On restore, ioapic_check() uses d->arch=2Ehvm=2Eext_dest_id (restored fr= om > the EXT_DEST_ID record) rather than the per-server dynamic check, since > the DM has not yet re-registered its servers at that point=2E >=20 > Update xendevicemodel_create_ioreq_server() in libxendevicemodel to > accept the new flags parameter, remove > xendevicemodel_enable_ext_dest_id(), and fix the > xc_hvm_create_ioreq_server() compat wrapper to pass zero flags=2E >=20 > Signed-off-by: Julian Vetter That has somewhat already being discussed previously, but AFAIU,=20 extended destination ID is only meaningful when guest APIC IDs cannot be= =20 represented with the "non-extended" model which can only happen in=20 practice when having more than 128 vCPUs in the guest=2E I don't think we need to check for device model support unless the guest= =20 can have more than 128 vCPUs, where in such case it becomes mandatory=20 (unless some form of interrupt remapping is implemented)=2E So I would rather check if domain->max_vcpus is more than 128 and=20 require device models to implement support for extended destination ID=20 in these cases=2E In some way, that would imply that extended destination ID is only=20 exposed to guests with domain->max_vcpus > 128=2E Overall, what I propose would be to keep the new=20 XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID flag, and if d->max_vcpus > 128, we=20 require the device model to support XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID=2E > --- > Changes in v4: > - As suggested by Roger, replaced XEN_DMOP_enable_ext_dest_id (v3 patch > 6), a separate DM op the device model had to call before starting > vCPUs, with a flags byte repurposed from the existing pad[3] field of > xen_dm_op_create_ioreq_server > - New XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID flag (bit 0) lets each ioreq > server signal support at registration time > - As suggested by Roger level the feature across all ioreq servers=2E > XEN_HVM_CPUID_EXT_DEST_ID is only advertised when every server > registered before arch_domain_creation_finished() sets the flag=2E A > single server without the flag suppresses the feature for the whole > domain! > - Lock the levelled result at domain creation time and enforce it for > servers registered afterwards, preventing a late opt-out from breakin= g > guests that already see the feature in CPUID > - Persist the locked flag via HVM_SAVE_TYPE(EXT_DEST_ID) so that live > migration preserves the guest-visible CPUID bit independently of when > the device model registers its ioreq servers on the destination host > --- > tools/include/xendevicemodel=2Eh | 3 +- > tools/libs/ctrl/xc_devicemodel_compat=2Ec | 2 +- > tools/libs/devicemodel/core=2Ec | 3 +- > xen/arch/arm/ioreq=2Ec | 5 ++++ > xen/arch/x86/domain=2Ec | 10 +++++++ > xen/arch/x86/hvm/ioreq=2Ec | 37 +++++++++++++++++++++++= ++ > xen/arch/x86/hvm/vioapic=2Ec | 20 +++++++++++++ > xen/arch/x86/include/asm/hvm/domain=2Eh | 9 ++++++ > xen/common/ioreq=2Ec | 13 +++++++-- > xen/drivers/passthrough/x86/hvm=2Ec | 13 +++++++++ > xen/include/public/arch-x86/hvm/save=2Eh | 17 +++++++++++- > xen/include/public/hvm/dm_op=2Eh | 16 +++++++++-- > xen/include/xen/ioreq=2Eh | 27 ++++++++++++++++++ > 13 files changed, 165 insertions(+), 10 deletions(-) >=20 > diff --git a/tools/include/xendevicemodel=2Eh b/tools/include/xendevicem= odel=2Eh > index f15b35fa33=2E=2Ebc6764bd58 100644 > --- a/tools/include/xendevicemodel=2Eh > +++ b/tools/include/xendevicemodel=2Eh > @@ -44,12 +44,13 @@ int xendevicemodel_close(xendevicemodel_handle *dmod= ); > * @parm domid the domain id to be serviced > * @parm handle_bufioreq how should the IOREQ Server handle buffered > * requests (HVM_IOREQSRV_BUFIOREQ_*)? > + * @parm flags bitmask of XEN_DMOP_IOREQ_SERVER_* capability flags=2E > * @parm id pointer to an ioservid_t to receive the IOREQ Server id=2E > * @return 0 on success, -1 on failure=2E > */ > int xendevicemodel_create_ioreq_server( > xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq, > - ioservid_t *id); > + uint8_t flags, ioservid_t *id); > =20 > /** > * This function retrieves the necessary information to allow an > diff --git a/tools/libs/ctrl/xc_devicemodel_compat=2Ec b/tools/libs/ctrl= /xc_devicemodel_compat=2Ec > index a46011cd17=2E=2E91366e250c 100644 > --- a/tools/libs/ctrl/xc_devicemodel_compat=2Ec > +++ b/tools/libs/ctrl/xc_devicemodel_compat=2Ec > @@ -11,7 +11,7 @@ int xc_hvm_create_ioreq_server( > ioservid_t *id) > { > return xendevicemodel_create_ioreq_server(xch->dmod, domid, > - handle_bufioreq, id); > + handle_bufioreq, 0, id); > } > =20 > int xc_hvm_get_ioreq_server_info( > diff --git a/tools/libs/devicemodel/core=2Ec b/tools/libs/devicemodel/co= re=2Ec > index adf2c41a96=2E=2E49b9bf8a13 100644 > --- a/tools/libs/devicemodel/core=2Ec > +++ b/tools/libs/devicemodel/core=2Ec > @@ -167,7 +167,7 @@ static int xendevicemodel_op( > =20 > int xendevicemodel_create_ioreq_server( > xendevicemodel_handle *dmod, domid_t domid, int handle_bufioreq, > - ioservid_t *id) > + uint8_t flags, ioservid_t *id) > { > struct xen_dm_op op; > struct xen_dm_op_create_ioreq_server *data; > @@ -179,6 +179,7 @@ int xendevicemodel_create_ioreq_server( > data =3D &op=2Eu=2Ecreate_ioreq_server; > =20 > data->handle_bufioreq =3D handle_bufioreq; > + data->flags =3D flags; > =20 > rc =3D xendevicemodel_op(dmod, domid, 1, &op, sizeof(op)); > if (rc) > diff --git a/xen/arch/arm/ioreq=2Ec b/xen/arch/arm/ioreq=2Ec > index b4211f0159=2E=2Ed45228717a 100644 > --- a/xen/arch/arm/ioreq=2Ec > +++ b/xen/arch/arm/ioreq=2Ec > @@ -201,6 +201,11 @@ void arch_ioreq_domain_init(struct domain *d) > { > } > =20 > +int arch_ioreq_server_create_check(const struct domain *d, uint8_t flag= s) > +{ > + return 0; > +} > + > /* > * Local variables: > * mode: C > diff --git a/xen/arch/x86/domain=2Ec b/xen/arch/x86/domain=2Ec > index 1d458f1372=2E=2E68ff315460 100644 > --- a/xen/arch/x86/domain=2Ec > +++ b/xen/arch/x86/domain=2Ec > @@ -25,6 +25,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -1106,7 +1107,16 @@ int arch_domain_soft_reset(struct domain *d) > void arch_domain_creation_finished(struct domain *d) > { > if ( is_hvm_domain(d) ) > + { > + /* > + * Lock the extended destination ID state=2E OR preserves any v= alue > + * already restored from an HVM save record (migration path)=2E= For a > + * fresh domain, ext_dest_id starts false and the dynamic check > + * supplies the levelled result across all registered ioreq ser= vers=2E > + */ > + d->arch=2Ehvm=2Eext_dest_id |=3D hvm_ext_dest_id_enabled(d); > hvm_domain_creation_finished(d); > + } > } > =20 > #ifdef CONFIG_COMPAT > diff --git a/xen/arch/x86/hvm/ioreq=2Ec b/xen/arch/x86/hvm/ioreq=2Ec > index a5fa97e149=2E=2E894a63c522 100644 > --- a/xen/arch/x86/hvm/ioreq=2Ec > +++ b/xen/arch/x86/hvm/ioreq=2Ec > @@ -19,6 +19,7 @@ > =20 > #include > #include > +#include > #include > #include > =20 > @@ -325,6 +326,42 @@ void arch_ioreq_domain_init(struct domain *d) > register_portio_handler(d, 0xcf8, 4, hvm_access_cf8); > } > =20 > +int arch_ioreq_server_create_check(const struct domain *d, uint8_t flag= s) > +{ > + if ( !is_hvm_domain(d) || !d->creation_finished ) > + return 0; > + > + if ( d->arch=2Ehvm=2Eext_dest_id && > + !(flags & XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID) ) > + return -EPERM; > + > + return 0; > +} > + > +static int cf_check ext_dest_id_save(struct vcpu *v, hvm_domain_context= _t *h) > +{ > + struct hvm_hw_ext_dest_id s =3D { > + =2Eenabled =3D v->domain->arch=2Ehvm=2Eext_dest_id, > + }; > + > + return hvm_save_entry(EXT_DEST_ID, 0, h, &s); > +} > + > +static int cf_check ext_dest_id_load(struct domain *d, hvm_domain_conte= xt_t *h) > +{ > + struct hvm_hw_ext_dest_id s; > + > + if ( hvm_load_entry(EXT_DEST_ID, h, &s) ) > + return -EINVAL; > + > + d->arch=2Ehvm=2Eext_dest_id =3D s=2Eenabled; > + > + return 0; > +} > + > +HVM_REGISTER_SAVE_RESTORE(EXT_DEST_ID, ext_dest_id_save, NULL, > + ext_dest_id_load, 1, HVMSR_PER_DOM); > + > /* > * Local variables: > * mode: C > diff --git a/xen/arch/x86/hvm/vioapic=2Ec b/xen/arch/x86/hvm/vioapic=2Ec > index 527cc770b7=2E=2E7d037a53e1 100644 > --- a/xen/arch/x86/hvm/vioapic=2Ec > +++ b/xen/arch/x86/hvm/vioapic=2Ec > @@ -24,6 +24,7 @@ > * Ported to xen by using virtual IRQ line=2E > */ > =20 > +#include > #include > #include > #include > @@ -597,6 +598,7 @@ int vioapic_get_trigger_mode(const struct domain *d,= unsigned int gsi) > static int cf_check ioapic_check(const struct domain *d, hvm_domain_co= ntext_t *h) > { > const HVM_SAVE_TYPE(IOAPIC) *s; > + unsigned int i; > =20 > if ( !has_vioapic(d) ) > return -ENODEV; > @@ -617,6 +619,24 @@ static int cf_check ioapic_check(const struct domai= n *d, hvm_domain_context_t *h > if ( s->ioregsel > VIOAPIC_REG_RTE0 + (ARRAY_SIZE(s->redirtbl) - 1= ) * 2 + 1 ) > return -EINVAL; > =20 > + /* > + * If any RTE uses extended destination ID bits, the EXT_DEST_ID sa= ve > + * record must have been loaded first (restoring d->arch=2Ehvm=2Eex= t_dest_id)=2E > + * The ioreq server re-registration by the DM happens later, so use= the > + * domain-level locked flag rather than the per-server dynamic chec= k=2E > + */ > + for ( i =3D 0; i < ARRAY_SIZE(s->redirtbl); i++ ) > + { > + if ( s->redirtbl[i]=2Efields=2Eext_dest_id && !d->arch=2Ehvm=2E= ext_dest_id ) > + { > + printk(XENLOG_G_ERR "HVM restore: %pd IO-APIC RTE %u has " > + "extended destination ID bits set but " > + "EXT_DEST_ID is not enabled\n", > + d, i); > + return -EINVAL; > + } > + } > + > return 0; > } > =20 > diff --git a/xen/arch/x86/include/asm/hvm/domain=2Eh b/xen/arch/x86/incl= ude/asm/hvm/domain=2Eh > index abf9bc448d=2E=2E895b2e12ba 100644 > --- a/xen/arch/x86/include/asm/hvm/domain=2Eh > +++ b/xen/arch/x86/include/asm/hvm/domain=2Eh > @@ -102,6 +102,15 @@ struct hvm_domain { > =20 > bool is_s3_suspended; > =20 > + /* > + * True when XEN_HVM_CPUID_EXT_DEST_ID was advertised to the guest= =2E Locked > + * at domain creation time once every registered ioreq server has o= pted in > + * via XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID=2E Persisted in HVM save/r= estore so > + * migration preserves the guest-visible state independently of whe= n the > + * device model re-registers its ioreq servers on the destination h= ost=2E > + */ > + bool ext_dest_id; > + > /* Compatibility setting for a bug in x2APIC LDR */ > bool bug_x2apic_ldr_vcpu_id; > =20 > diff --git a/xen/common/ioreq=2Ec b/xen/common/ioreq=2Ec > index f5fd30ce12=2E=2E56a7eb8282 100644 > --- a/xen/common/ioreq=2Ec > +++ b/xen/common/ioreq=2Ec > @@ -641,7 +641,7 @@ static void ioreq_server_deinit(struct ioreq_server = *s) > } > =20 > static int ioreq_server_create(struct domain *d, int bufioreq_handling= , > - ioservid_t *id) > + uint8_t flags, ioservid_t *id) > { > struct ioreq_server *s; > unsigned int i; > @@ -683,6 +683,8 @@ static int ioreq_server_create(struct domain *d, int= bufioreq_handling, > goto fail; > } > =20 > + s->ext_dest_id =3D flags & XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID; > + > if ( id ) > *id =3D i; > =20 > @@ -1350,11 +1352,16 @@ int ioreq_server_dm_op(struct xen_dm_op *op, str= uct domain *d, bool *const_op) > *const_op =3D false; > =20 > rc =3D -EINVAL; > - if ( data->pad[0] || data->pad[1] || data->pad[2] ) > + if ( data->flags & ~XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID || > + data->pad[0] || data->pad[1] ) > + break; > + > + rc =3D arch_ioreq_server_create_check(d, data->flags); > + if ( rc ) > break; > =20 > rc =3D ioreq_server_create(d, data->handle_bufioreq, > - &data->id); > + data->flags, &data->id); > break; > } > =20 > diff --git a/xen/drivers/passthrough/x86/hvm=2Ec b/xen/drivers/passthrou= gh/x86/hvm=2Ec > index 6fb4f8b7dc=2E=2Ef7f7c02076 100644 > --- a/xen/drivers/passthrough/x86/hvm=2Ec > +++ b/xen/drivers/passthrough/x86/hvm=2Ec > @@ -21,6 +21,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -455,6 +456,18 @@ int pt_irq_create_bind( > uint64_t msi_addr; > uint32_t msi_data; > =20 > + /* > + * Refuse the old MSI bind path when extended destination IDs a= re > + * in use=2E The caller must use XEN_DMOP_bind_pt_msi_irq inste= ad, > + * which passes the raw MSI address so Xen can decode the exten= ded > + * bits=2E This old path only carries an 8-bit destination ID a= nd > + * would silently misroute interrupts to vCPUs with APIC IDs > = 255=2E > + */ > + if ( hvm_ext_dest_id_enabled(d) ) > + { > + return -EPERM; > + } > + > msi_addr =3D MSI_ADDR_HEADER | > MASK_INSR(MASK_EXTR(gflags, XEN_DOMCTL_VMSI_X86_DES= T_ID_MASK), > MSI_ADDR_DEST_ID_MASK) | > diff --git a/xen/include/public/arch-x86/hvm/save=2Eh b/xen/include/publ= ic/arch-x86/hvm/save=2Eh > index 483097d940=2E=2Edd70ce18c6 100644 > --- a/xen/include/public/arch-x86/hvm/save=2Eh > +++ b/xen/include/public/arch-x86/hvm/save=2Eh > @@ -627,12 +627,27 @@ struct hvm_msr { > =20 > #define CPU_MSR_CODE 20 > =20 > +/* > + * HVM_SAVE_TYPE(EXT_DEST_ID): domain-level extended MSI destination ID= state=2E > + * > + * Records whether the extended destination ID feature was enabled for = this > + * domain at the time guest vCPUs were started=2E This allows migration= to > + * preserve the setting across hosts without relying on the device mode= l to > + * re-register its ioreq servers before the guest's first CPUID query= =2E > + */ > +struct hvm_hw_ext_dest_id { > + uint8_t enabled; > + uint8_t pad[7]; > +}; > + > +DECLARE_HVM_SAVE_TYPE(EXT_DEST_ID, 21, struct hvm_hw_ext_dest_id); > + > /* Range 22 - 34 (inclusive) reserved for Amazon */ > =20 > /* > * Largest type-code in use > */ > -#define HVM_SAVE_CODE_MAX 20 > +#define HVM_SAVE_CODE_MAX 21 > =20 > #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */ > =20 > diff --git a/xen/include/public/hvm/dm_op=2Eh b/xen/include/public/hvm/d= m_op=2Eh > index 43571b7713=2E=2E73f33b3c46 100644 > --- a/xen/include/public/hvm/dm_op=2Eh > +++ b/xen/include/public/hvm/dm_op=2Eh > @@ -39,18 +39,28 @@ typedef uint16_t ioservid_t; > * XEN_DMOP_create_ioreq_server: Instantiate a new IOREQ Server for a > * secondary emulator=2E > * > - * The handed back is unique for target domain=2E The valur of > + * The handed back is unique for target domain=2E The value of > * should be one of HVM_IOREQSRV_BUFIOREQ_* defined = in > - * hvm_op=2Eh=2E If the value is HVM_IOREQSRV_BUFIOREQ_OFF then the bu= ffered > + * hvm_op=2Eh=2E If the value is HVM_IOREQSRV_BUFIOREQ_OFF then the buf= fered > * ioreq ring will not be allocated and hence all emulation requests t= o > * this server will be synchronous=2E > + * > + * If contains XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID, the server wi= ll > + * use XEN_DMOP_bind_pt_msi_irq for all passthrough MSI bindings, passi= ng > + * raw MSI address/data fields so Xen can decode extended destination I= D > + * bits=2E Once any server sets this flag, Xen will advertise > + * XEN_HVM_CPUID_EXT_DEST_ID to the guest=2E Must be set before the gue= st > + * vCPUs are started=2E > */ > #define XEN_DMOP_create_ioreq_server 1 > =20 > struct xen_dm_op_create_ioreq_server { > /* IN - should server handle buffered ioreqs */ > uint8_t handle_bufioreq; > - uint8_t pad[3]; > + /* IN - server capability flags */ > + uint8_t flags; > +#define XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID (1u << 0) > + uint8_t pad[2]; > /* OUT - server id */ > ioservid_t id; > }; > diff --git a/xen/include/xen/ioreq=2Eh b/xen/include/xen/ioreq=2Eh > index e86f0869fa=2E=2Eec78b63942 100644 > --- a/xen/include/xen/ioreq=2Eh > +++ b/xen/include/xen/ioreq=2Eh > @@ -54,9 +54,35 @@ struct ioreq_server { > evtchn_port_t bufioreq_evtchn; > struct rangeset *range[NR_IO_RANGE_TYPES]; > bool enabled; > + bool ext_dest_id; > uint8_t bufioreq_handling; > }; > =20 > +/* > + * Return true if every registered ioreq server has opted in to extende= d > + * destination IDs (XEN_DMOP_IOREQ_SERVER_EXT_DEST_ID) and at least one > + * server exists=2E A single server without the flag is enough to suppr= ess > + * XEN_HVM_CPUID_EXT_DEST_ID, preventing misrouted interrupts=2E > + */ > +static inline bool hvm_ext_dest_id_enabled(const struct domain *d) > +{ > + unsigned int i; > + bool found =3D false; > + > + for ( i =3D 0; i < MAX_NR_IOREQ_SERVERS; i++ ) > + { > + const struct ioreq_server *s =3D d->ioreq_server=2Eserver[i]; > + > + if ( !s ) > + continue; > + if ( !s->ext_dest_id ) > + return false; > + found =3D true; > + } > + > + return found; > +} > + > static inline paddr_t ioreq_mmio_first_byte(const ioreq_t *p) > { > return unlikely(p->df) ? > @@ -137,6 +163,7 @@ bool arch_ioreq_server_destroy_all(struct domain *d)= ; > bool arch_ioreq_server_get_type_addr(const struct domain *d, const ior= eq_t *p, > uint8_t *type, uint64_t *addr); > void arch_ioreq_domain_init(struct domain *d); > +int arch_ioreq_server_create_check(const struct domain *d, uint8_t flag= s); > =20 > #endif /* __XEN_IOREQ_H__ */ > =20 Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.128.637cd1b16475e87d.19dd4f25531.aed7cbd50075e8bd=--- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 17:03:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 17:03:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296550.1572937 (Exim 4.92) (envelope-from ) id 1wHlq6-0005Sr-Qf; Tue, 28 Apr 2026 17:03:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296550.1572937; Tue, 28 Apr 2026 17:03:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHlq6-0005Sk-NF; Tue, 28 Apr 2026 17:03:14 +0000 Received: by outflank-mailman (input) for mailman id 1296550; Tue, 28 Apr 2026 17:03:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHlq5-0005Sb-4V for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 17:03:13 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHlq4-009ilz-DV for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 19:03:12 +0200 Received: from [10.42.69.3] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0e844-bab6-0a2a0a5309dd-0a2a45038596-34 for ; Tue, 28 Apr 2026 19:03:12 +0200 Received: from [160.101.131.8] (helo=na1pdmzitismtp01.tibco.com) by tlsNG-33051d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0e84f-672d-0a2a45030019-a06583088560-3 for ; Tue, 28 Apr 2026 19:03:11 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp01.tibco.com (Postfix) with ESMTP id ED4804289E8D; Tue, 28 Apr 2026 13:02:20 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] docs: Add modern Sphinx design with bright and dark mode Date: Tue, 28 Apr 2026 18:02:39 +0100 Message-Id: <4e74ef79b0f1b60cc9b04d769f7a69333292c0e0.1777395235.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1777395792-2A567938-21A5DA1F/0/0 X-purgate-type: clean X-purgate-size: 34009 Add a modern Sphinx design with bright and dark mode using a lightweight theme with a clean design and a modern look and feel: https://sphinx-book-theme.readthedocs.io Use the current logos from xenproject.org, and add two addons to enhance documentation work: - Add support for Mermaid diagrams to render state diagrams, flowcharts, sequence diagrams, relationship/requirement diagrams, block diagrams, packet diagrams etc. for design documentation: https://mermaid.js.org (The NUMA design docs are a good example of using Mermaid diagrams, see b= elow) - Add support for using sphinx-autobuild: Auto-Renders the docs site on each change and refreshes the web browser: https://github.com/sphinx-doc/sphinx-autobuild#readme Example use: $ make -C docs sphinx-autobuild # Rebuilds and refreshes the browser: ... Serving on http://127.0.0.1:8000 Signed-off-by: Bernhard Kaindl --- Preview: https://bernhard-xen.readthedocs.io/en/modern-sphinx-theme Example Mermaid diagram documenting the proposed NUMA claims hypercall desi= gn: https://bernhard-xen.readthedocs.io/en/claim-sets-v3-design/guest-guide/dom= /DOMCTL_claim_memory.html --- .readthedocs.yaml | 9 +-- docs/.gitignore | 1 + docs/Makefile | 16 ++++- docs/_static/favicon-xen-32x32.png | Bin 0 -> 1841 bytes docs/_static/logo-xen-reverse.svg | 57 ++++++++++++++++ docs/_static/logo-xen.svg | 61 +++++++++++++++++ docs/conf.py | 102 ++++++++++++++++++++++++++--- docs/requirements.txt | 3 + 8 files changed, 236 insertions(+), 13 deletions(-) create mode 100644 docs/_static/favicon-xen-32x32.png create mode 100644 docs/_static/logo-xen-reverse.svg create mode 100644 docs/_static/logo-xen.svg create mode 100644 docs/requirements.txt diff --git a/.readthedocs.yaml b/.readthedocs.yaml index d3aff7662ebf..edf79dc3d4a1 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -9,10 +9,11 @@ build: tools: python: "latest" =20 - jobs: - post_install: - # Instead of needing a separate requirements.txt - - python -m pip install --upgrade --no-cache-dir sphinx-rtd-theme +python: + install: + # Avoids fragmentation of the dependencies across multiple files, + # and makes it easier to maintain the dependencies in one place. + - requirements: docs/requirements.txt =20 sphinx: configuration: docs/conf.py diff --git a/docs/.gitignore b/docs/.gitignore index c3ce50335ae6..80c3d14ede69 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,3 +1,4 @@ +/.sphinx/ /figs/*.png /html/ /man/xl.cfg.5.pod diff --git a/docs/Makefile b/docs/Makefile index 8e68300e3b44..797694c85af8 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -55,6 +55,20 @@ build: html txt pdf man-pages figs sphinx-html: sphinx-build -b html . sphinx/html =20 +.PHONY: .sphinx +.sphinx: + if [ ! -d .sphinx ]; then python -m venv .sphinx; fi + . .sphinx/bin/activate && pip install -r requirements.txt + +.PHONY: sphinx-build +sphinx-build: .sphinx + . .sphinx/bin/activate && $(MAKE) sphinx-html + +.PHONY: sphinx-autobuild +sphinx-autobuild: .sphinx + . .sphinx/bin/activate && sphinx-autobuild \ + --re-ignore '(html|man[0-9]?|pdf|txt|Makefile)' . sphinx/html + .PHONY: html html: $(DOC_HTML) html/index.html =20 @@ -76,7 +90,7 @@ pdf: $(DOC_PDF) clean: clean-man-pages $(MAKE) -C figs clean rm -rf .word_count *.aux *.dvi *.bbl *.blg *.glo *.idx *~ - rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core + rm -rf *.ilg *.log *.ind *.toc *.bak *.tmp core .sphinx rm -rf html txt pdf sphinx/html =20 .PHONY: distclean diff --git a/docs/_static/favicon-xen-32x32.png b/docs/_static/favicon-xen-= 32x32.png new file mode 100644 index 0000000000000000000000000000000000000000..a89c3082bbe7b3bf541cd576def= b34bf0e1b377a GIT binary patch literal 1841 zcmV-12hRA3P)Px*>q$gGR9HvFS7~q*MHK#eW_EXG6S9y12}wu-6k^alY6L)uJ50D?0@7GMf z*Zsct`dv-%0HTx%*7t0X`_pa*im9M}h$f2%xsMHe3|Nz;WDm03CdV6)L0pZVAfkFW{D~91ghw0x?1| zSP&V~4z0sdAPP-_IjUGul)<7X7Hb7`0GM)~=3DYOP>#%P7?u6h(y?m$t^KHRof1icBK z7}2(AH*}94is&Yf`pFSO%4AvYs|Dc!z}zlL(lKAlFWx+ggI8Cf&QbFaAwZDSybt;& zOoAwc`tB>XTCGpIuR{gE0?y%ZtRsYsaZ6LG;OD=3D-!HM#3L7{jKA>hzdj7CdyJD3d? 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They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions =3D [] +extensions =3D ["sphinx.ext.autosectionlabel"] + +try: + import sphinxcontrib.mermaid + + extensions.append("sphinxcontrib.mermaid") +except ImportError: + pass + + +def on_build_finished(app, exception): + if exception: + return + + common_install =3D """ + Alternatively, you can use pipx to install sphinx and the needed + extras in an isolated environment with:\n + pipx install sphinx + pipx runpip sphinx install -r docs/requirements.txt\n + Or, use `make -C docs sphinx-env-build` to build the documentation + in a suitable Python environment with all dependencies.\n""" + + # See https://sphinx-book-theme.readthedocs.io for more info: + if not sys.modules.get("sphinx_book_theme"): + sys.stderr.write(""" + To fix rendering the HTML theme, install `sphinx_book_theme` in + your Python venv. On Debian-based systems, you can install it with= :\n + sudo apt install python3-sphinx-book-theme""" + common_install) + + # See https://sphinxcontrib-mermaid-demo.readthedocs.io + # or https://github.com/mgaitan/sphinxcontrib-mermaid for more info: + if not sys.modules.get("sphinxcontrib.mermaid"): + sys.stderr.write(""" + To fix rendering mermaid diagrams, install `sphinxcontrib.mermaid`= in + your Python venv. On Debian-based systems, you can install it with= :\n + sudo apt install python3-sphinxcontrib-mermaid""" + common_ins= tall) + + # See https://github.com/sphinx-doc/sphinx-autobuild#readme for more i= nfo: + try: + import sphinx_autobuild + except ImportError: + print("The generated documentation is available at:") + print(f"file://{app.outdir}/index.html") + print("You can also serve it locally with:") + print(f" (cd {app.outdir}; python -m http.server)") + print("To auto-rebuild and auto-refresh on changes, install") + print("`sphinx-autobuild` in your Python venv and run:") + print(" sphinx-autobuild docs docs/sphinx/html") + print("Or simply use `make -C docs sphinx-autobuild` to build & se= rve") + + +def setup(app): + app.connect("build-finished", on_build_finished) + + +# Extension options + +# sphinxcontrib.mermaid +mermaid_init_js =3D """ +mermaid.initialize({ startOnLoad: true }); +""" + +# sphinx.ext.autosectionlabel +autosectionlabel_prefix_document =3D True =20 # Add any paths that contain templates here, relative to this directory. templates_path =3D ['_templates'] @@ -82,7 +145,7 @@ language =3D 'en' # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. -exclude_patterns =3D [u'sphinx/output', 'Thumbs.db', '.DS_Store'] +exclude_patterns =3D [u'sphinx/output', 'Thumbs.db', '.DS_Store', '.sphinx= '] =20 # The name of the Pygments (syntax highlighting) style to use. pygments_style =3D None @@ -93,15 +156,38 @@ highlight_language =3D 'none' # -- Options for HTML output ---------------------------------------------= ---- # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-fo= r-html-output =20 +html_title =3D f"Xen Hypervisor {version} Documentation" +html_logo =3D "_static/logo-xen.svg" +html_favicon =3D "_static/favicon-xen-32x32.png" + # The theme to use for HTML and HTML Help pages. See the documentation for # a list of builtin themes. # try: - import sphinx_rtd_theme - html_theme =3D 'sphinx_rtd_theme' - html_theme_path =3D [sphinx_rtd_theme.get_html_theme_path()] + import sphinx_book_theme + + html_theme =3D 'sphinx_book_theme' + # Theme options are theme-specific and customize the look and feel + # of a theme further. For a list of options available for each theme, + # see the documentation of that theme. e.g. for sphinx_book_theme, see + # https://sphinx-book-theme.readthedocs.io/en/latest/configure.html#op= tions + html_theme_options =3D { + "logo": { + "text": f"Xen Hypervisor {version}", + "image_light": html_logo, + "image_dark": "_static/logo-xen-reverse.svg", + }, + "home_page_in_toc": False, + # Depth of the table of contents tree to show in the right sidebar + "show_toc_level": 3, + "repository_url": "https://github.com/xen-project/xen", + "use_repository_button": True, + } except ImportError: - sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme = was not found. Make sure you have the theme installed to produce pretty HTM= L output. Falling back to the default theme.\n') + sys.stderr.write( + "sphinx_book_theme was not found, falling back to the default them= e.\n" + ) + =20 # Theme options are theme-specific and customize the look and feel of a th= eme # further. For a list of options available for each theme, see the @@ -112,7 +198,7 @@ except ImportError: # Add any paths that contain custom static files (such as style sheets) he= re, # relative to this directory. They are copied after the builtin static fil= es, # so a file named "default.css" will overwrite the builtin "default.css". -html_static_path =3D [] +html_static_path =3D ["_static"] =20 # Custom sidebar templates, must be a dictionary that maps document names # to template names. diff --git a/docs/requirements.txt b/docs/requirements.txt new file mode 100644 index 000000000000..0cec13235162 --- /dev/null +++ b/docs/requirements.txt @@ -0,0 +1,3 @@ +sphinx-book-theme=3D=3D1.2.0 +sphinxcontrib-mermaid=3D=3D2.0.1 +sphinx-autobuild=3D=3D2025.08.25 --=20 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 17:32:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 17:32:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296595.1572946 (Exim 4.92) (envelope-from ) id 1wHmHq-0001fg-4f; Tue, 28 Apr 2026 17:31:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296595.1572946; Tue, 28 Apr 2026 17:31:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHmHq-0001fZ-1F; Tue, 28 Apr 2026 17:31:54 +0000 Received: by outflank-mailman (input) for mailman id 1296595; Tue, 28 Apr 2026 17:31:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHmHp-0001fT-JO for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 17:31:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHmHo-000wxr-Vd for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 19:31:52 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0eeff-5cb7-0a2a0a5109dd-0a2a45048e42-2 for ; Tue, 28 Apr 2026 19:31:52 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0ef07-1dec-0a2a45040019-a06583098348-3 for ; Tue, 28 Apr 2026 19:31:52 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id 817CC81C9E98; Tue, 28 Apr 2026 13:30:51 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] docs: Hypervisor-Guide: Move Hyperlaunch design docs as needed Date: Tue, 28 Apr 2026 18:31:11 +0100 Message-Id: <3b943ee1ca93abdd70be30965146540975d91888.1777397318.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1777397512-2B7693FF-C1E6B427/0/0 X-purgate-type: clean X-purgate-size: 3710 In the Sphinx documentation, the Hyperlaunch Design Documents were stated as needing rearranging: They were put into the section that needs rearranging, so rearrange them as indicated inside the Hypervisor Guide which aims to describe the hypervisor for developers and people interested in the hypervisor. This also fixes the glitch where the "1 Hypervisor Design Document" was listed in the main menu sidebar and helps to clean up the main menu. Signed-off-by: Bernhard Kaindl --- docs/designs/index.rst | 15 +++++++++++++++ docs/designs/launch/hyperlaunch.rst | 4 ++-- docs/designs/launch/index.rst | 10 ++++++++++ docs/hypervisor-guide/index.rst | 12 ++++++++++-- docs/index.rst | 2 -- 5 files changed, 37 insertions(+), 6 deletions(-) create mode 100644 docs/designs/index.rst create mode 100644 docs/designs/launch/index.rst diff --git a/docs/designs/index.rst b/docs/designs/index.rst new file mode 100644 index 000000000000..ded12082c622 --- /dev/null +++ b/docs/designs/index.rst @@ -0,0 +1,15 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Design documents +================ + +Design documents and implementation details for the Xen hypervisor. + +These are intended for developers working on the Xen hypervisor, +and for those interested in the internal workings of Xen. + +.. toctree:: + :maxdepth: 2 + :numbered: 4 + + launch/index diff --git a/docs/designs/launch/hyperlaunch.rst b/docs/designs/launch/hyperlaunch.rst index 3bed36f97637..aa7c2798a380 100644 --- a/docs/designs/launch/hyperlaunch.rst +++ b/docs/designs/launch/hyperlaunch.rst @@ -2,8 +2,6 @@ Hyperlaunch Design Document ########################### -.. sectnum:: :depth: 4 - This post is a Request for Comment on the included v4 of a design document that describes Hyperlaunch: a new method of launching the Xen hypervisor, relating to dom0less and work from the Hyperlaunch project. We invite discussion of this @@ -13,6 +11,8 @@ Xen Development mailing list. .. contents:: :depth: 3 + :backlinks: entry + :local: Introduction diff --git a/docs/designs/launch/index.rst b/docs/designs/launch/index.rst new file mode 100644 index 000000000000..afd845296d30 --- /dev/null +++ b/docs/designs/launch/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: CC-BY-4.0 + +Hyperlaunch +=========== + +.. toctree:: + :maxdepth: 2 + + hyperlaunch + hyperlaunch-devicetree diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.rst index 520fe01554ab..9c8033305549 100644 --- a/docs/hypervisor-guide/index.rst +++ b/docs/hypervisor-guide/index.rst @@ -1,11 +1,19 @@ .. SPDX-License-Identifier: CC-BY-4.0 -Hypervisor documentation -======================== +Hypervisor Guide +================ + +The Hypervisor Guide provides an overview of the Xen hypervisor's +architecture and design, covering its core components, features, +and how it manages resources for :term:`guest` domains. + +It serves as a comprehensive reference for developers and users interested +in understanding the inner workings of the Xen hypervisor. .. toctree:: :maxdepth: 2 + ../designs/index code-coverage x86/index diff --git a/docs/index.rst b/docs/index.rst index bd87d736b9c3..6b04a077cebd 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -62,8 +62,6 @@ Documents in need of some rearranging. .. toctree:: :maxdepth: 2 - designs/launch/hyperlaunch - designs/launch/hyperlaunch-devicetree misc/xen-makefiles/makefiles misra/index fusa/index -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 18:05:48 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 18:05:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296645.1572976 (Exim 4.92) (envelope-from ) id 1wHmoT-0006g7-1V; Tue, 28 Apr 2026 18:05:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296645.1572976; Tue, 28 Apr 2026 18:05:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHmoS-0006es-RU; Tue, 28 Apr 2026 18:05:36 +0000 Received: by outflank-mailman (input) for mailman id 1296645; Tue, 28 Apr 2026 18:05:36 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHmoR-0006bn-Qp; Tue, 28 Apr 2026 18:05:35 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHmoR-00GyDs-1x; Tue, 28 Apr 2026 20:05:35 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0f6e5-2eae-0a2a0a5409dd-0a2a4509b6e4-12 for ; Tue, 28 Apr 2026 20:05:34 +0200 Received: from [104.130.215.37] (helo=mail.xenproject.org) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0f6ec-2497-0a2a45090019-6882d725cb18-3 for ; Tue, 28 Apr 2026 20:05:34 +0200 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1wHmoL-006BvQ-0v; Tue, 28 Apr 2026 18:05:29 +0000 Received: from andrewcoop by xenbits.xenproject.org with local (Exim 4.96) (envelope-from ) id 1wHmoL-007C43-0i; Tue, 28 Apr 2026 18:05:29 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.510 (Entity 5.510) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 489 v1 (CVE-2026-23559,CVE-2026-23560,CVE-2026-23561,CVE-2026-23562,CVE-2026-42486) - Multiple RBAC issues in XAPI Message-Id: Date: Tue, 28 Apr 2026 18:05:29 +0000 X-purgate-ID: tlsNG-bad1c0/1777399534-42573A53-1A14A799/0/0 X-purgate-type: clean X-purgate-size: 3984 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-23559,CVE-2026-23560,CVE-2026-23561,CVE-2026-23562,CVE-2026-42486 / XSA-489 Multiple RBAC issues in XAPI ISSUE DESCRIPTION ================= XAPI can configure different users with different roles, using Role Based Access Control. For more details, see: https://docs.xenserver.com/en-us/xencenter/current-release/rbac-overview.html#rbac-roles The pool-admin role is fully privileged. Notably, users with this role can also SSH into the host as root. The other administrator roles are pool-operator, vm-power-admin and vm-admin, each of which are authorised to configure and manage various aspects of the system. Some settings are inadequately restricted, and can be set by a lower privilege of administrator than expected. * CVE-2026-23559: A vm-admin can set VBD.other_config:backend-local and turn arbitrary files in dom0 into VDIs (virtual disks) and give said disks to a VM they control. This is an arbitrary read and/or modify of files in dom0. * CVE-2026-23560: A vm-admin can set VM.other-config:is_system_domain and mark a VM as a system domain. System domains are ignored and left running during certain other host/pool operations, and may be hidden from view in tooling. * CVE-2026-23561: A vm-admin can set VM.other_config:storage_driver_domain and mark a VM as the storage domain for a particular host storage connection (PBD). Shutting down the VM can cause the PBD to be erroneously marked as unplugged when it is not. * CVE-2026-23562: Configuration of PCI passthrough is normally restricted to the pool-admin role. However one API was missing this check, allowing a vm-admin access to unintended host hardware. * CVE-2026-42486: A vm-admin can set the VM.platform:hvm_serial parameter, which should be restricted to the pool-admin role, as it can allow arbitrary dom0 file write. IMPACT ====== An authenticated user already granted one of pool-operator, vm-power-admin or vm-admin can escalate their privilege to pool-admin. VULNERABLE SYSTEMS ================== Systems running all versions of XAPI are vulnerable. The vulnerability is only exposed if RBAC is configured for the pool, and certain users are assigned the not-fully-privileged administrator roles. MITIGATION ========== Disable any users (RBAC subjects) which have been configured with the vm-admin, vm-power-admin or pool-operator role. RESOLUTION ========== Fixes can be found in the following pull requests: https://github.com/xapi-project/xen-api/pull/7031 https://github.com/xapi-project/xen-api/pull/7032 https://github.com/xapi-project/xen-api/pull/7033 https://github.com/xapi-project/xen-api/pull/7039 NOTE REGARDING LACK OF EMBARGO ============================== These issues were disclosed in public. The researcher claimed 89 vulnerabilities. Analysis by the XAPI team concluded that only 5 were real vulnerabilities, with most being a failure to read the RBAC documentation, and several appearing to be AI hallucinations. The researcher also took active steps to prevent coordinated disclosure. Due to acting in bad faith, they are explicitly not credited. -----BEGIN PGP SIGNATURE----- iQFABAEBCAAqFiEEI+MiLBRfRHX6gGCng/4UyVfoK9kFAmnw9tkMHHBncEB4ZW4u b3JnAAoJEIP+FMlX6CvZgLUIAMgzABaje/RPPO7lwrp1ERZQhtqy/SPG2dYxE75a M6bytAbpj4Y9lgh8IB4QLXDSEfSgjWKxzSGcUi3DpvJI3uiQmSqvAE5XnfRfVHT/ h1eo0vQ3v8yz5++iiOl2Cq9Qvg9cvMFEXYz8X21+u63KlpOnXjUZ7VpYeRdrbCYs n6Id6QU4D/y+3EZne5Xs0JY6Dn8J8SM3ejNjP6OmMFJMoKgSf1nXarQhNcmgvR0G a+PRjUWgHAHqfdzjJsyBZLyNwPAQgUM2aDfPqGh8vr9YlE6sWwlxYEeSIGsWzAHu oE5iWmYq5O4FUTgf+1ye8PUNbGyzDsJCeGfWeAXvGobQ6aQ= =OEJh -----END PGP SIGNATURE----- --=separator-- From xen-devel-bounces@lists.xenproject.org Tue Apr 28 18:19:47 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 18:19:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296742.1573007 (Exim 4.92) (envelope-from ) id 1wHn1s-00021j-Dx; Tue, 28 Apr 2026 18:19:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296742.1573007; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM9PR03MB7526.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 273f55db-88db-4fba-9049-08dea552acd0 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Apr 2026 18:19:23.8377 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: loehAS8/n51UdIIV+V5xu9I3IFUs6oXMApDbh4WQ94jsoQuywpqpOI+2i8g/pZWkAH+RM5gWt4AZ3+PvM135wnfgubfrBbZpB2CsD6AUq88= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB7125 X-purgate-ID: tlsNG-c201ff/1777400366-E1BA4443-3D05F7DB/0/0 X-purgate-type: clean X-purgate-size: 1456 The statement 'return ERR_PTR(-ENOENT);' on the final line of the function 'hypfs_get_entry_rel()' is unreachable because the logic within the infinite loop 'for (;;)' provides all possible exit paths for the function. So there is no execution path to exit the loop and reach the final that statement. This unreachable code violates MISRA C Rule 2.1 which states: "A project shall not contain unreachable code". To fix that and potential compilers "control reaches end of non-void function" warning, mark the code path as unreachable using macro 'ASSERT_UNREACHABLE()'. Signed-off-by: Dmytro Prokopchuk --- Changes in v2: - add ASSERT_UNREACHABLE() before the final return statement instead of rem= oving it Test CI pipeline: https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2485661910 Link to v1: https://patchew.org/Xen/341811ced2943fb79d0235c27781c564c7bdaf02.1775749146= .git.dmytro._5Fprokopchuk1@epam.com/ --- xen/common/hypfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/common/hypfs.c b/xen/common/hypfs.c index cdf4ee0171..02fb234568 100644 --- a/xen/common/hypfs.c +++ b/xen/common/hypfs.c @@ -348,6 +348,7 @@ static struct hypfs_entry *hypfs_get_entry_rel(struct h= ypfs_entry_dir *dir, dir =3D container_of(entry, struct hypfs_entry_dir, e); } =20 + ASSERT_UNREACHABLE(); return ERR_PTR(-ENOENT); } =20 --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Tue Apr 28 18:35:10 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 18:35:10 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296760.1573027 (Exim 4.92) (envelope-from ) id 1wHnGn-00059r-P9; Tue, 28 Apr 2026 18:34:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296760.1573027; Tue, 28 Apr 2026 18:34:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHnGn-00059k-MS; Tue, 28 Apr 2026 18:34:53 +0000 Received: by outflank-mailman (input) for mailman id 1296760; Tue, 28 Apr 2026 18:34:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHnGm-00059e-Fq for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 18:34:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHnGl-009D8Q-JV for xen-devel@lists.xenproject.org; Tue, 28 Apr 2026 20:34:51 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f0fdc3-e002-0a2a0a5209dd-0a2a4507c9a2-6 for ; Tue, 28 Apr 2026 20:34:51 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f0fdca-229c-0a2a45070019-a0658309d5fe-3 for ; Tue, 28 Apr 2026 20:34:51 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id A25EA81995B5; Tue, 28 Apr 2026 14:33:49 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] docs: Format (void *) to fix reStructuredText emphasis warnings Date: Tue, 28 Apr 2026 19:34:28 +0100 Message-Id: <05b61bdfce381176a6c4b8844db1fba3fa0982ce.1777401225.git.bernhard.kaindl@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1777401291-AE16DC48-9705ED87/0/0 X-purgate-type: clean X-purgate-size: 2724 Fix warnings when rendering the Sphinx documentation because with reStructuredText, in the character sequence of '(void *)', the characters *) are seen as an emphasis start-string: WARNING: Inline emphasis start-string without end-string. [docutils] Fix this by formatting it with ``(void *)`` as an inline literal which can be used for monospaced code snippets like these that can contain any characters without any markup interpretation. Signed-off-by: Bernhard Kaindl --- Preview based on the new theme and design docs arrangement just submitted: https://bernhard-xen.readthedocs.io/en/void/misra/rules.html https://bernhard-xen.readthedocs.io/en/void/misra/deviations.html --- docs/misra/deviations.rst | 4 ++-- docs/misra/rules.rst | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst index b04830959694..c972d5b2ad49 100644 --- a/docs/misra/deviations.rst +++ b/docs/misra/deviations.rst @@ -366,13 +366,13 @@ Deviations related to MISRA C:2012 Rules: - Tagged as `safe` for ECLAIR. * - R11.1 - - The conversion from a function pointer to unsigned long or '(void *)' does + - The conversion from a function pointer to unsigned long or ``(void *)`` does not lose any information, provided that the target type has enough bits to store it. - Tagged as `safe` for ECLAIR. * - R11.1 - - Conversion from unsigned long or '(void *)' to a function pointer can + - Conversion from unsigned long or ``(void *)`` to a function pointer can restore full information, provided that the source type has enough bits to restore it. - Tagged as `safe` for ECLAIR. diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst index b3e929307d51..fc6fdfd313d0 100644 --- a/docs/misra/rules.rst +++ b/docs/misra/rules.rst @@ -430,9 +430,9 @@ maintainers if you want to suggest a change. and any other type - All conversions to integer types are permitted if the destination type has enough bits to hold the entire value. Conversions to bool - and void* are permitted. Conversions from 'void noreturn (*)(...)' - to 'void (*)(...)' are permitted. Conversions from unsigned long or - '(void *)' to a function pointer are permitted. + and ``void *`` are permitted. Conversions from ``void noreturn (*)(...)`` + to ``void (*)(...)`` are permitted. Conversions from unsigned long or + ``(void *)`` to a function pointer are permitted. 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Tue, 28 Apr 2026 11:42:54 -0700 (PDT) Message-ID: <20eaa31d-a105-440e-9add-968fc9786180@gmail.com> Date: Tue, 28 Apr 2026 21:42:53 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] xen/arm: its: collect quirk flags and honor dma-noncoherent To: Mykola Kvach , Volodymyr Babchuk Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel References: <5b68fa0a8403ea60db3047f6505876bc03a41f3f.1774431310.git.mykola_kvach@epam.com> <87bjgcvul6.fsf@epam.com> Content-Language: en-US From: Oleksandr Tyshchenko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777401775-93175A53-AA775135/0/0 X-purgate-type: clean X-purgate-size: 6634 On 3/25/26 17:47, Mykola Kvach wrote: > Hi Volodymyr, Hello Mykola and Volodymyr > > Thank you for the review. > > On Wed, Mar 25, 2026 at 4:42 PM Volodymyr Babchuk > wrote: >> >> Hi Mykola, >> >> Mykola Kvach writes: >> >>> From: Mykola Kvach >>> >>> Replace the per-quirk init callback with declarative flags in >>> struct its_quirk, and introduce gicv3_its_collect_quirks() to gather >>> the effective workaround flags from both the IIDR-matched quirk entry >>> and the "dma-noncoherent" device-tree property. >>> >>> This lets non-coherent platforms force non-cacheable ITS table >>> attributes even when no IIDR quirk entry matches. >>> >>> Signed-off-by: Mykola Kvach >>> --- >>> xen/arch/arm/gic-v3-its.c | 70 ++++++++++++++++++++++++--------------- >>> 1 file changed, 43 insertions(+), 27 deletions(-) >>> >>> diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c >>> index 9ba068c46f..00524b43a3 100644 >>> --- a/xen/arch/arm/gic-v3-its.c >>> +++ b/xen/arch/arm/gic-v3-its.c >>> @@ -57,71 +57,87 @@ struct its_device { >>> */ >>> struct its_quirk { >>> const char *desc; >>> - bool (*init)(struct host_its *hw_its); >>> uint32_t iidr; >>> uint32_t mask; >>> + uint32_t flags; >>> }; >>> >>> static uint32_t __ro_after_init its_quirk_flags; >>> >>> -static bool gicv3_its_enable_quirk_gen4(struct host_its *hw_its) >>> -{ >>> - its_quirk_flags |= HOST_ITS_WORKAROUND_NC_NS | >>> - HOST_ITS_WORKAROUND_32BIT_ADDR; >>> - >>> - return true; >>> -} >>> - >>> static const struct its_quirk its_quirks[] = { >>> { >>> - .desc = "R-Car Gen4", >>> - .iidr = 0x0201743b, >>> - .mask = 0xffffffffU, >>> - .init = gicv3_its_enable_quirk_gen4, >>> + .desc = "R-Car Gen4", >>> + .iidr = 0x0201743b, >>> + .mask = 0xffffffffU, >>> + .flags = HOST_ITS_WORKAROUND_NC_NS | >>> + HOST_ITS_WORKAROUND_32BIT_ADDR, >>> }, >>> { >>> /* Sentinel. */ >>> } >>> }; >>> >>> -static struct its_quirk* gicv3_its_find_quirk(uint32_t iidr) >>> +static const struct its_quirk *gicv3_its_find_quirk(uint32_t iidr) >>> { >>> - const struct its_quirk *quirks = its_quirks; >>> + const struct its_quirk *quirk = its_quirks; >>> >>> - for ( ; quirks->desc; quirks++ ) >>> + for ( ; quirk->desc; quirk++ ) >>> { >>> - if ( quirks->iidr == (quirks->mask & iidr) ) >>> - return (struct its_quirk *)quirks; >>> + if ( quirk->iidr != (quirk->mask & iidr) ) >>> + continue; >>> + >>> + return quirk; >>> } >>> >>> return NULL; >>> } >>> >>> -static void gicv3_its_enable_quirks(struct host_its *hw_its) >>> +static uint32_t gicv3_its_collect_quirks(const struct host_its *hw_its, >>> + const struct its_quirk **matched_quirk) >>> { >>> + const struct its_quirk *quirk; >>> + uint32_t flags = 0; >>> uint32_t iidr = readl_relaxed(hw_its->its_base + GITS_IIDR); >>> - const struct its_quirk *quirk = gicv3_its_find_quirk(iidr); >>> >>> - if ( quirk && quirk->init(hw_its) ) >>> + quirk = gicv3_its_find_quirk(iidr); >>> + if ( quirk ) >>> + flags |= quirk->flags; >>> + >>> + if ( hw_its->dt_node && >>> + dt_property_read_bool(hw_its->dt_node, "dma-noncoherent") ) >>> + flags |= HOST_ITS_WORKAROUND_NC_NS; >>> + >>> + if ( matched_quirk ) >>> + *matched_quirk = quirk; >>> + >>> + return flags; >>> +} >>> + >>> +static void gicv3_its_enable_quirks(struct host_its *hw_its) >>> +{ >>> + const struct its_quirk *quirk; >>> + >>> + its_quirk_flags = gicv3_its_collect_quirks(hw_its, &quirk); >>> + >>> + if ( quirk ) >>> printk("GICv3: enabling workaround for ITS: %s\n", quirk->desc); >>> } >>> >>> static void gicv3_its_validate_quirks(void) >>> { >>> - const struct its_quirk *quirk = NULL, *prev = NULL; >>> + uint32_t quirks, prev_quirks; >>> const struct host_its *hw_its; >>> >>> if ( list_empty(&host_its_list) ) >>> return; >>> >>> hw_its = list_first_entry(&host_its_list, struct host_its, entry); >>> - prev = gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GITS_IIDR)); >>> + prev_quirks = gicv3_its_collect_quirks(hw_its, NULL); >>> >>> - list_for_each_entry(hw_its, &host_its_list, entry) >>> + list_for_each_entry_continue(hw_its, &host_its_list, entry) >>> { >>> - quirk = gicv3_its_find_quirk(readl_relaxed(hw_its->its_base + GITS_IIDR)); >>> - BUG_ON(quirk != prev); >>> - prev = quirk; >>> + quirks = gicv3_its_collect_quirks(hw_its, NULL); >>> + BUG_ON(quirks != prev_quirks); >> >> I know it was in the previous version, but as you are already touching >> this... This is not Xen BUG(). This is a platform problem. So you need >> to panic here. Something like >> >> if (quirks != prev_quirks) >> panic("Different ITS instances has different quirks") > > Ack. > > I agree that a quirk mismatch is a platform problem. Yes, the current design uses global flags, making it unable to handle mixed quirks, leading to the failure on mismatch. Please note, I am not saying a panic() is wrong here and I am not requesting any changes here; I was just wondering why this is handled differently than the SMMUv3 driver. I am just thinking out loud. SMMUv3 driver handles feature mismatches by gracefully degrading. When it finds an SMMU device that does not support ARM_SMMU_FEAT_COHERENCY, it disables that feature for the entire platform (so the P2M code has to clean the cache when updating ptes). It does not panic. How the ITS and SMMUv3 drivers are different in that regard? Why could not we apply the same "worst-case" logic here? For example: - if any ITS device requires non-cacheable memory, then all ITS memory allocations should use non-cacheable memory. - if any ITS device requires 32-bit addresses, then all ITS memory allocations should be constrained to 32-bits. This would be consistent with the SMMU precedent and would allow the system to boot and function correctly, but with the performance characteristics of the worst ITS device in the system. Or I really missed something? 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pr=C Message-ID: <275c1e83-ddf3-4d1b-9777-cd6d56d357a3@amd.com> Date: Tue, 28 Apr 2026 16:05:54 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/7] vpci: add SR-IOV support for PVH Dom0 To: Mykyta Poturai , "xen-devel@lists.xenproject.org" CC: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "Daniel P. Smith" References: Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBC:EE_|DS0PR12MB8366:EE_ X-MS-Office365-Filtering-Correlation-Id: 894627f6-9595-4e1e-f467-08dea56191d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: SkFn9AmsvAxALFWwFf3u5yCqM8GPKibI113/OOLTtdveoI4wJ/oLtP4/iZ8yLQp1vX8lCoh7Vfb+b2xw+oF61VVxdTEynG4PnjL8FHf6M/rmv2J5JNHi9iVxt/sfaRAjSkQBSbd9XEOEC9M1+sJ4UPNmSU5Ns8jqt4orojNyOZcRXypnNMfZhr9IwACB8nhcx4vouHHk81NwHwdF00fdpYdN0jdM0L139gr3+YIzBf+eOfWHHrQwtTQl7HjVbDczalrQ6gGlD7HJABOq54xnubC78yS0iC50IqChX/VLFNcaOjIMl6+itvoIAmynVrqaSFiQhQvhk1FMCDVZgPDFLB81BnmXTFCe2ZQ6smqq7rhBBd61NvTLIVdwbn189541XnuaRrrxFaqVOApkA7ihKdjrkV/7V3+45ASEiJgatz4/fr+F9aSCXTlZJEPwo8ki27w9Y3o2AbAvnkybG/Die90fasQvcBWGksTbBGM+wMFXXONr/Mr/zJ9QRO6u/SotHu8sBkJiNak8A8K+ighxWTDAXi0+01GjanAtLlfqdT6Z0bdL+P5LJdYQ2I9JE9Pi07j+gLd3cSzK9Vf1uMzwhRAQaWMb08PH4iVn9d+IYFg3hYQKsfr/UW+kH48GlgrnjlXPTvIFnOcjXZFnoLKwlRuxuq6VazgseMiziM/kEqpCRzKp+zcJjsbKF5DBpTLUYTfTvGYy6TRr75yInBls4/13uYr1iPj9IWN0Iv/IP76CVtuNgN66Gm+l6OKY6ktjBpUMIRAxQQ7qnnnh5B/C4w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dmhf0mokdWGpkI+mmpUQ7GitauQav2GdIeAFiTte9uzaFO3289fQAcwyzJk+yKVczED1fojqj3hARYC0pWnmtrDtxhDpmuQfGkjlLtlzy/A5KfTxQWbhvOkSKpEZd/DRIiNvQBCLhkh6Pip3mw/L//I43nEjOaM+2kGZpPs6y+phIGkbju6kpJYlNuHXDS6rX55V9h6gRm/j9T9Z+TiOnk02GE/WhnF7XCPnBvzRC9qc7po2gu0qfYGucpefyNe65CGgzrWpdRXN9Boil65gAV6YCany5VUno8mNPqJ8IveXEHbE5WpYiUR5Pi/rhi5msuoz06FQoOqeZma3F5xO3nCj66N6ThP86Mkd7nnFyLEr1xyAp08hatHdMnFFynfp4crFn4USnkpBFGpRHe6IEk6abI0np8HbayDWc0L67vxEMjhUmTx9IXJVKDNGrLuY X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 20:06:00.9670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 894627f6-9595-4e1e-f467-08dea56191d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8366 X-purgate-ID: tlsNG-4011c0/1777406767-4576D8B7-54372D30/0/0 X-purgate-type: clean X-purgate-size: 15072 On 4/9/26 10:01, Mykyta Poturai wrote: > From: Stewart Hildebrand > > This code is expected to only be used by privileged domains, > unprivileged domains should not get access to the SR-IOV capability. > > Implement RW handlers for PCI_SRIOV_CTRL register to dynamically > map/unmap VF BARS. Recalculate BAR sizes before mapping VFs to account > for possible changes in the system page size register. Also force VFs to > always use emulated reads for command register, this is needed to > prevent some drivers accidentally unmapping BARs. Discovery of VFs is > done by Dom0, which must register them with Xen. > > Signed-off-by: Roger Pau Monné > Signed-off-by: Stewart Hildebrand > Signed-off-by: Mykyta Poturai > --- > v2->v3: > * rework adding VFs with multiple mapping operations support > * use private.h > * style fixes > * fixup cleanup_sriov > * emulate command register read for VFs Also noteworthy: switched back to no longer adding VFs within Xen. > > v1->v2: > * switch to VF discovery by Xen > * fix sequential vpci_modify_bars calls > * move documentation changes to a separate commit > --- > xen/drivers/vpci/Makefile | 1 + > xen/drivers/vpci/header.c | 6 +- > xen/drivers/vpci/private.h | 1 + > xen/drivers/vpci/sriov.c | 314 +++++++++++++++++++++++++++++++++++++ > xen/include/xen/vpci.h | 7 +- > 5 files changed, 327 insertions(+), 2 deletions(-) > create mode 100644 xen/drivers/vpci/sriov.c > > diff --git a/xen/drivers/vpci/Makefile b/xen/drivers/vpci/Makefile > index 9793a4f9b0..8b0e3c03a7 100644 > --- a/xen/drivers/vpci/Makefile > +++ b/xen/drivers/vpci/Makefile > @@ -1,3 +1,4 @@ > obj-y += cap.o > obj-y += vpci.o header.o rebar.o > +obj-y += sriov.o > obj-$(CONFIG_HAS_PCI_MSI) += msi.o msix.o > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index 451cdd3a6f..a36285672e 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -869,7 +869,8 @@ int vpci_init_header(struct pci_dev *pdev) > * PCI_COMMAND_PARITY, PCI_COMMAND_SERR, and PCI_COMMAND_FAST_BACK. > */ > rc = vpci_add_register_mask(pdev->vpci, > - is_hwdom ? vpci_hw_read16 : guest_cmd_read, > + is_hwdom && !pdev->info.is_virtfn > + ? vpci_hw_read16 : guest_cmd_read, > cmd_write, PCI_COMMAND, 2, header, 0, 0, > is_hwdom ? 0 > : PCI_COMMAND_RSVDP_MASK | > @@ -900,6 +901,9 @@ int vpci_init_header(struct pci_dev *pdev) > > header->guest_cmd = cmd; > > + if ( pdev->info.is_virtfn ) > + return vpci_vf_init_header(pdev); > + > /* Disable memory decoding before sizing. */ > if ( !is_hwdom || (cmd & PCI_COMMAND_MEMORY) ) > pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEMORY); > diff --git a/xen/drivers/vpci/private.h b/xen/drivers/vpci/private.h > index f012fd160d..8e0043ddbe 100644 > --- a/xen/drivers/vpci/private.h > +++ b/xen/drivers/vpci/private.h > @@ -45,6 +45,7 @@ typedef struct { > REGISTER_VPCI_CAPABILITY(PCI_EXT_CAP_ID_##name, name, finit, fclean, true) > > int __must_check vpci_init_header(struct pci_dev *pdev); > +int __must_check vpci_vf_init_header(struct pci_dev *pdev); > > int vpci_init_capabilities(struct pci_dev *pdev, bool ext_only); > void vpci_cleanup_capabilities(struct pci_dev *pdev, bool ext_only); > diff --git a/xen/drivers/vpci/sriov.c b/xen/drivers/vpci/sriov.c > new file mode 100644 > index 0000000000..ec6a7b84d5 > --- /dev/null > +++ b/xen/drivers/vpci/sriov.c > @@ -0,0 +1,314 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Handlers for accesses to the SR-IOV capability structure. > + * > + * Copyright (C) 2026 Citrix Systems R&D > + */ > + > +#include > +#include > +#include > +#include "private.h" Should "private.h" move up so it's first? > + > +static int vf_init_bars(const struct pci_dev *vf_pdev) > +{ > + int vf_idx; > + unsigned int i; > + const struct pci_dev *pf_pdev = vf_pdev->pf_pdev; > + struct vpci_bar *bars = vf_pdev->vpci->header.bars; > + struct vpci_bar *physfn_vf_bars = pf_pdev->vpci->sriov->vf_bars; > + unsigned int sriov_pos = pci_find_ext_capability(pf_pdev, > + PCI_EXT_CAP_ID_SRIOV); > + uint16_t offset = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_OFFSET); > + uint16_t stride = pci_conf_read16(pf_pdev->sbdf, > + sriov_pos + PCI_SRIOV_VF_STRIDE); > + > + vf_idx = vf_pdev->sbdf.sbdf - (pf_pdev->sbdf.sbdf + offset); > + if ( vf_idx < 0 ) > + return -EINVAL; > + > + if ( stride ) > + { > + if ( vf_idx % stride ) > + return -EINVAL; > + vf_idx /= stride; > + } > + > + /* > + * Set up BARs for this VF out of PF's VF BARs taking into account > + * the index of the VF. > + */ > + for ( i = 0; i < PCI_SRIOV_NUM_BARS; i++ ) > + { > + bars[i].addr = physfn_vf_bars[i].addr + vf_idx * physfn_vf_bars[i].size; > + bars[i].guest_addr = bars[i].addr; We don't want to leak the host address to domUs, i.e. you might consider doing something like: bars[i].guest_addr = is_hardware_domain(d) ? bars[i].addr : 0; > + bars[i].size = physfn_vf_bars[i].size; > + bars[i].type = physfn_vf_bars[i].type; > + bars[i].prefetchable = physfn_vf_bars[i].prefetchable; > + } > + > + return 0; > +} > + > +static int map_vfs(const struct pci_dev *pf_pdev, uint16_t cmd) > +{ > + struct pci_dev *vf_pdev; > + int rc; > + > + ASSERT(rw_is_write_locked(&pf_pdev->domain->pci_lock)); > + > + list_for_each_entry(vf_pdev, &pf_pdev->vf_list, vf_list) > + { > + rc = vpci_modify_bars(vf_pdev, cmd, false); > + if ( rc ) > + { > + gprintk(XENLOG_ERR, "failed to %s VF %pp: %d\n", > + (cmd & PCI_COMMAND_MEMORY) ? "map" : "unmap", > + &vf_pdev->sbdf, rc); > + return rc; > + } > + > + vf_pdev->vpci->header.guest_cmd &= ~PCI_COMMAND_MEMORY; > + vf_pdev->vpci->header.guest_cmd |= (cmd & PCI_COMMAND_MEMORY); > + } > + > + return 0; > +} > + > +static int size_vf_bars(const struct pci_dev *pf_pdev, unsigned int sriov_pos, > + uint64_t *vf_rlen) > +{ > + struct vpci_bar *bars; > + unsigned int i; > + int rc = 0; > + > + ASSERT(rw_is_write_locked(&pf_pdev->domain->pci_lock)); > + ASSERT(!pf_pdev->info.is_virtfn); > + ASSERT(pf_pdev->vpci->sriov); > + > + /* Read BARs for VFs out of PF's SR-IOV extended capability. */ > + bars = pf_pdev->vpci->sriov->vf_bars; > + /* Set the BARs addresses and size. */ > + for ( i = 0; i < PCI_SRIOV_NUM_BARS; i += rc ) > + { > + unsigned int idx = sriov_pos + PCI_SRIOV_BAR + i * 4; > + uint32_t bar; > + uint64_t addr, size; > + > + bar = pci_conf_read32(pf_pdev->sbdf, idx); > + > + rc = pci_size_mem_bar(pf_pdev->sbdf, idx, &addr, &size, > + PCI_BAR_VF | > + ((i == PCI_SRIOV_NUM_BARS - 1) ? PCI_BAR_LAST > + : 0)); > + > + /* > + * Update vf_rlen on the PF. According to the spec the size of > + * the BARs can change if the system page size register is > + * modified, so always update rlen when enabling VFs. > + */ > + vf_rlen[i] = size; > + > + if ( !size ) > + { > + bars[i].type = VPCI_BAR_EMPTY; > + continue; > + } > + > + bars[i].addr = addr; > + bars[i].guest_addr = addr; > + bars[i].size = size; > + bars[i].prefetchable = bar & PCI_BASE_ADDRESS_MEM_PREFETCH; > + > + switch ( rc ) > + { > + case 1: > + bars[i].type = VPCI_BAR_MEM32; > + break; > + > + case 2: > + bars[i].type = VPCI_BAR_MEM64_LO; > + bars[i + 1].type = VPCI_BAR_MEM64_HI; > + break; > + > + default: > + ASSERT_UNREACHABLE(); > + } > + } > + > + rc = rc > 0 ? 0 : rc; > + > + return rc; > +} > + > +static void cf_check control_write(const struct pci_dev *pdev, unsigned int reg, > + uint32_t val, void *data) > +{ > + unsigned int sriov_pos = reg - PCI_SRIOV_CTRL; > + struct vpci_sriov *sriov = pdev->vpci->sriov; > + uint16_t control = pci_conf_read16(pdev->sbdf, reg); > + bool mem_enabled = control & PCI_SRIOV_CTRL_MSE; > + bool new_mem_enabled = val & PCI_SRIOV_CTRL_MSE; > + bool enabled = control & PCI_SRIOV_CTRL_VFE; > + bool new_enabled = val & PCI_SRIOV_CTRL_VFE; > + int rc; > + > + ASSERT(!pdev->info.is_virtfn); > + > + if ( new_enabled == enabled && new_mem_enabled == mem_enabled ) > + { > + pci_conf_write16(pdev->sbdf, reg, val); > + return; > + } > + > + if ( mem_enabled && !new_mem_enabled ) > + map_vfs(pdev, 0); > + > + if ( !enabled && new_enabled ) > + { > + size_vf_bars(pdev, sriov_pos, (uint64_t *)data); > + > + /* > + * Only update the number of active VFs when enabling, when > + * disabling use the cached value in order to always remove the same > + * number of VFs that were active. > + */ > + sriov->num_vfs = pci_conf_read16(pdev->sbdf, > + sriov_pos + PCI_SRIOV_NUM_VF); > + } > + > + if ( !mem_enabled && new_mem_enabled ) > + { > + rc = map_vfs(pdev, PCI_COMMAND_MEMORY); > + > + if ( rc ) > + map_vfs(pdev, 0); > + } > + > + pci_conf_write16(pdev->sbdf, reg, val); > +} > + > +int vpci_vf_init_header(struct pci_dev *vf_pdev) > +{ > + const struct pci_dev *pf_pdev; > + unsigned int sriov_pos; > + int rc = 0; > + uint16_t ctrl; > + > + ASSERT(rw_is_write_locked(&vf_pdev->domain->pci_lock)); > + > + if ( !vf_pdev->info.is_virtfn ) > + return 0; > + > + pf_pdev = vf_pdev->pf_pdev; > + ASSERT(pf_pdev); > + > + rc = vf_init_bars(vf_pdev); > + if ( rc ) > + return rc; > + > + sriov_pos = pci_find_ext_capability(pf_pdev, PCI_EXT_CAP_ID_SRIOV); > + ctrl = pci_conf_read16(pf_pdev->sbdf, sriov_pos + PCI_SRIOV_CTRL); > + > + if ( (pf_pdev->domain == vf_pdev->domain) && (ctrl & PCI_SRIOV_CTRL_MSE) ) > + { > + rc = vpci_modify_bars(vf_pdev, PCI_COMMAND_MEMORY, false); > + if ( rc ) > + return rc; > + > + vf_pdev->vpci->header.guest_cmd |= PCI_COMMAND_MEMORY; > + } > + > + return rc; > +} > + > +static int cf_check init_sriov(struct pci_dev *pdev) > +{ > + unsigned int pos; > + > + ASSERT(!pdev->info.is_virtfn); > + > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); > + > + if ( !pos ) > + return 0; > + > + if ( xsm_resource_setup_pci(XSM_PRIV, pdev->sbdf.bdf) ) > + { > + printk(XENLOG_ERR > + "%pp: SR-IOV configuration unsupported for unpriv %pd\n", > + &pdev->sbdf, pdev->domain); > + return -EACCES; > + } > + > + pdev->vpci->sriov = xzalloc(struct vpci_sriov); Don't we prefer xvzalloc now? If so, changing this should be paired with a corresponding XVFREE in the cleanup handler. > + if ( !pdev->vpci->sriov ) > + return -ENOMEM; > + > + /* > + * We need to modify vf_rlen in control_write but we can't do it cleanly > + * from pdev because write callback only accepts const pdev. Moving vf_rlen > + * inside of struct vpci_sriov is also not possible because it is used > + * before vpci init. So pass it here as additional data to not require > + * dropping const in control_write. > + */ > + return vpci_add_register(pdev->vpci, vpci_hw_read16, control_write, > + pos + PCI_SRIOV_CTRL, 2, &pdev->physfn.vf_rlen); > +} > + > +static int cf_check cleanup_sriov(const struct pci_dev *pdev, bool hide) > +{ > + unsigned int pos; > + int rc; > + > + if ( !pdev->vpci->sriov ) > + return 0; > + > + ASSERT(!pdev->info.is_virtfn); > + ASSERT(list_empty(&pdev->vf_list)); > + > + if ( !hide ) > + { > + XFREE(pdev->vpci->sriov); > + return 0; > + } > + > + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); > + rc = vpci_remove_registers(pdev->vpci, pos + PCI_SRIOV_CTRL, 2); > + if ( rc ) > + { > + printk(XENLOG_ERR "%pd %pp: fail to remove SRIOV handlers rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); > + ASSERT_UNREACHABLE(); > + return rc; > + } > + XFREE(pdev->vpci->sriov); > + > + /* > + * Unprivileged domains have a deny by default register access policy, no > + * need to add any further handlers for them. > + */ > + if ( !is_hardware_domain(pdev->domain) ) > + return 0; > + > + rc = vpci_add_register(pdev->vpci, vpci_hw_read16, NULL, > + pos + PCI_SRIOV_CTRL, 2, NULL); > + if ( rc ) > + printk(XENLOG_ERR "%pd %pp: fail to add SRIOV ctrl handler rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); > + > + return rc; > +} > + > +REGISTER_VPCI_EXTCAP(SRIOV, init_sriov, cleanup_sriov); > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * tab-width: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h > index e34f7abe6d..fc8a943abe 100644 > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -84,7 +84,6 @@ struct vpci { > * upon to know whether BARs are mapped into the guest p2m. > */ > bool bars_mapped : 1; > - /* FIXME: currently there's no support for SR-IOV. */ > } header; > > /* MSI data. */ > @@ -145,6 +144,12 @@ struct vpci { > unsigned int nbars:3; > } rebar; > > + struct vpci_sriov { > + /* PF only */ > + struct vpci_bar vf_bars[PCI_SRIOV_NUM_BARS]; > + uint16_t num_vfs; > + } *sriov; > + > #ifdef CONFIG_HAS_VPCI_GUEST_SUPPORT > /* Guest SBDF of the device. */ > #define INVALID_GUEST_SBDF ((pci_sbdf_t){ .sbdf = ~0U }) From xen-devel-bounces@lists.xenproject.org Tue Apr 28 20:22:29 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 28 Apr 2026 20:22:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296845.1573054 (Exim 4.92) (envelope-from ) id 1wHowf-0004Em-Il; Tue, 28 Apr 2026 20:22:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296845.1573054; Tue, 28 Apr 2026 20:22:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHowf-0004Ef-Fm; Tue, 28 Apr 2026 20:22:13 +0000 Received: by outflank-mailman (input) for mailman id 1296845; Tue, 28 Apr 2026 20:22:11 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHowd-0004EZ-UF for xen-devel@lists.xenproject.org; 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bh=MeGrH7FFVtCqyv/NbgnvNcXlzgvwjVd3HPzbRlDpFcA=; b=XR0X/LFs+qjMVkkJXw12/NPWZHxnmWz3/JWRN5mzwxFw2ABmqQK8uiGkzQhBiMw/VQFb A1gqOlzmTR07Uo/fHugo/gUgtKtTgB98psyiaPoslfuGzfubminfX1++0SKolO/nIrsf0 IQoTCIFZAy3ft8w0IAdgiFYHSoFHhII61HAvmV2YsjZcJMcPRSaelGLdRZ5dzu1PBW/kG HDBGgLA40ru/Lu71sKz8IiNyxg0V4K2sAsqjCuhn4gzNI6kxLMF8uj09j5OkXpfro7BnA IWFxhbsAzvOvp+ZeceuboT/S9pL7V1N3c5yGNKMH4AoaknKDa/ck3oHJga5sroc+HQcYD eJ2yGg5oSm2Gly0k4LeWEzZxJ6kTcdFD/YjTM3FPiUGMQE7FW/dA1ImNTuBxWw4LdyMNy McSMnwY+mRW6iwdEwZzC2PoTtVgip7tu8qBqPtzakMMWqO56nJzeVT2HZjDGEsHqs6+tB 20/X2PUpTRoJwfAlTz7CGTF9QHcxZQK5K4WFEeX+GsiHtAHw3lhOzu6ZUWL3tF86bGi1/ /7yZnch+CM/Qe27cHb4sz85410uZjB9V8grepeJuJqqts+ejmuNoG8+gnuOi/CwKte1FW erine2Zim4qdXYQ02fDQr9ihsuqpKMFZnJ9SwIrbWJ9dyfE4d0qS0bIDBmXNFAI= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 MIME-Version: 1.0 Date: Tue, 28 Apr 2026 22:22:10 +0200 From: Nicola Vetrini To: Bernhard Kaindl Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: Re: [PATCH] docs: Format (void *) to fix reStructuredText emphasis warnings In-Reply-To: <05b61bdfce381176a6c4b8844db1fba3fa0982ce.1777401225.git.bernhard.kaindl@citrix.com> References: <05b61bdfce381176a6c4b8844db1fba3fa0982ce.1777401225.git.bernhard.kaindl@citrix.com> Message-ID: X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-720697/1777407731-82D6F161-4F702448/0/0 X-purgate-type: clean X-purgate-size: 3849 On 2026-04-28 20:34, Bernhard Kaindl wrote: > Fix warnings when rendering the Sphinx documentation because > with reStructuredText, in the character sequence of '(void *)', > the characters *) are seen as an emphasis start-string: > > WARNING: Inline emphasis start-string without end-string. [docutils] > > Fix this by formatting it with ``(void *)`` as an inline literal > which can be used for monospaced code snippets like these that > can contain any characters without any markup interpretation. > > Signed-off-by: Bernhard Kaindl Reviewed-by: Nicola Vetrini See nit below > --- > Preview based on the new theme and design docs arrangement just > submitted: > https://bernhard-xen.readthedocs.io/en/void/misra/rules.html > https://bernhard-xen.readthedocs.io/en/void/misra/deviations.html > --- > docs/misra/deviations.rst | 4 ++-- > docs/misra/rules.rst | 6 +++--- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst > index b04830959694..c972d5b2ad49 100644 > --- a/docs/misra/deviations.rst > +++ b/docs/misra/deviations.rst > @@ -366,13 +366,13 @@ Deviations related to MISRA C:2012 Rules: > - Tagged as `safe` for ECLAIR. > > * - R11.1 > - - The conversion from a function pointer to unsigned long or > '(void *)' does > + - The conversion from a function pointer to unsigned long or > ``(void *)`` does > not lose any information, provided that the target type has > enough bits > to store it. > - Tagged as `safe` for ECLAIR. > > * - R11.1 > - - Conversion from unsigned long or '(void *)' to a function > pointer can > + - Conversion from unsigned long or ``(void *)`` to a function > pointer can > restore full information, provided that the source type has > enough bits > to restore it. There are further instance below which should similarly be rendered with a monospaced font, as they are code e.g. The conversion from ‘void noreturn (*)(…)’ to ‘void (*)(…)’ is safe because the semantics of the ‘noreturn’ attribute Perhaps those don't cause warnings, but if we want to visualize this as code in a monospaced font, then it probably should be uniformly used in the document. We haven't been 100% consistent when writing these documents originally; partly due to the fact that different people were involved, but this could be an occasion to remedy that. But perhaps that is best done in a follow-up patch, so feel free to take my r-by for this patch. > - Tagged as `safe` for ECLAIR. > diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst > index b3e929307d51..fc6fdfd313d0 100644 > --- a/docs/misra/rules.rst > +++ b/docs/misra/rules.rst > @@ -430,9 +430,9 @@ maintainers if you want to suggest a change. > and any other type > - All conversions to integer types are permitted if the > destination > type has enough bits to hold the entire value. Conversions to > bool > - and void* are permitted. Conversions from 'void noreturn > (*)(...)' > - to 'void (*)(...)' are permitted. Conversions from unsigned > long or > - '(void *)' to a function pointer are permitted. > + and ``void *`` are permitted. Conversions from ``void noreturn > (*)(...)`` > + to ``void (*)(...)`` are permitted. Conversions from unsigned > long or > + ``(void *)`` to a function pointer are permitted. > Example:: > > unsigned long func_addr = (unsigned long)&some_function; -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296939.1573072 (Exim 4.92) (envelope-from ) id 1wHxiR-00084z-LT; Wed, 29 Apr 2026 05:44:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296939.1573072; Wed, 29 Apr 2026 05:44:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiR-00084s-Ia; Wed, 29 Apr 2026 05:44:07 +0000 Received: by outflank-mailman (input) for mailman id 1296939; Wed, 29 Apr 2026 05:44:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiQ-00084I-MM for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 05:44:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHxiQ-003p6b-21 for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 07:44:06 +0200 Received: from [10.42.69.10] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f19aa3-e002-0a2a0a5209dd-0a2a450ae8ea-2 for ; Wed, 29 Apr 2026 07:44:06 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-4011c0.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f19aa5-56b3-0a2a450a0019-d98c6eac86d2-1 for ; Wed, 29 Apr 2026 07:44:05 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 209DA2BCE; Tue, 28 Apr 2026 22:43:59 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3EAE33F62B; Tue, 28 Apr 2026 22:44:03 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441444; bh=D0cWhXb5cOQnh67SWhy+Xw1f5uxdZNslX4hyB6LTlbM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mP5yOT8W5xF9s2AHoIo0HBtQluRfUBB5R3yG9h/hpcntrzT1TI4lVdaFvPbZ22Ua2 mIvQ9MiuE5m5zwRgaUmg3JSK4ROlrF2xVxlIYmLWlag0x2D6lASoV+qnRQZWc/5ccr bsi8k3W4LWPaLtKHmF2ZECs1o56euNT4DIGSZ11A= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 1/6] xen/arm: ffa: Fix NPI injection when vcpu0 is offline Date: Wed, 29 Apr 2026 07:43:22 +0200 Message-ID: <2a36253fca9c23681fea0d5493faeb3044de558d.1776955622.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-4011c0/1777441446-4415A8B7-5EAC21DC/0/0 X-purgate-type: clean X-purgate-size: 3404 RX-buffer-full notifications currently inject the notification pending interrupt through vcpu0 only. Secure notification delivery already walks the domain's online vCPUs, but the RX-buffer-full path does not. When vcpu0 is offline, the notification remains pending and the guest never receives it. Extract the common notification injection path and reuse it from ffa_raise_rx_buffer_full(). The shared helper delivers the global notification to the first online vCPU and keeps the existing ratelimited debug message when none are online. Functional impact: RX-buffer-full notifications are delivered even when vcpu0 is offline. Fixes: 3935c705688e ("xen/arm: ffa: Add buffer full notification support") Signed-off-by: Bertrand Marquis Reviewed-by: Jens Wiklander --- Changes since v1: - add R-b from Jens --- xen/arch/arm/tee/ffa_notif.c | 45 ++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 186e72641237..07bc5cb3a430 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -19,6 +19,29 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; +static void inject_notif_pending(struct domain *d) +{ + struct vcpu *v; + + /* + * Since we're only delivering global notification, always + * deliver to the first online vCPU. It doesn't matter + * which we chose, as long as it's available. + */ + for_each_vcpu(d, v) + { + if ( is_vcpu_online(v) ) + { + vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); + return; + } + } + + if ( printk_ratelimit() ) + printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", + d); +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -190,7 +213,7 @@ void ffa_raise_rx_buffer_full(struct domain *d) ACCESS_ONCE(ctx->notif.buff_full_pending) = true; if ( !test_and_set_bool(ctx->notif.vm_pending) ) - vgic_inject_irq(d, d->vcpu[0], GUEST_FFA_NOTIF_PEND_INTR_ID, true); + inject_notif_pending(d); } #endif @@ -238,7 +261,6 @@ static void notif_vm_pend_intr(uint16_t vm_id) { struct ffa_ctx *ctx; struct domain *d; - struct vcpu *v; /* * vm_id == 0 means a notifications pending for Xen itself, but @@ -277,24 +299,7 @@ static void notif_vm_pend_intr(uint16_t vm_id) * it. */ ACCESS_ONCE(ctx->notif.secure_pending) = true; - - /* - * Since we're only delivering global notification, always - * deliver to the first online vCPU. It doesn't matter - * which we chose, as long as it's available. - */ - for_each_vcpu(d, v) - { - if ( is_vcpu_online(v) ) - { - vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, - true); - break; - } - } - if ( !v && printk_ratelimit() ) - printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", - d); + inject_notif_pending(d); out_unlock: rcu_unlock_domain(d); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296942.1573082 (Exim 4.92) (envelope-from ) id 1wHxiT-0008J8-Rw; Wed, 29 Apr 2026 05:44:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296942.1573082; Wed, 29 Apr 2026 05:44:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiT-0008Iz-P6; Wed, 29 Apr 2026 05:44:09 +0000 Received: by outflank-mailman (input) for mailman id 1296942; Wed, 29 Apr 2026 05:44:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiS-0008En-GJ for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 05:44:08 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHxiR-0078Bd-S1 for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 07:44:07 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f19a9f-5cb7-0a2a0a5109dd-0a2a4507ede2-12 for ; Wed, 29 Apr 2026 07:44:07 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f19aa6-229c-0a2a45070019-d98c6eacb28e-1 for ; Wed, 29 Apr 2026 07:44:07 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C745D328D; Tue, 28 Apr 2026 22:44:00 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB45A3F62B; Tue, 28 Apr 2026 22:44:04 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441446; bh=IvYNqDbera/Ke8I0F2UPOw6J8/rPOohK8qd0lYFvQZM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=inm5aBwxI6owTAxlvk6jPjRmOK55M16BCQgB5DNdQ/iBYs8C7yhJXqo06rL/wuu0w 43oOdT64yp7kACF+j41i1kQHlbRVvv4EqgZQTvdy37cPjUdw+/LfgDdi9feTyf7McC hYscRSAFQ+daJBvOFLXT3j5e/qQiKt/G4s4UbyaM= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 2/6] xen/arm: ffa: Track hypervisor notifications in a bitmap Date: Wed, 29 Apr 2026 07:43:23 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1777441447-AD364C48-2A5E094F/0/0 X-purgate-type: clean X-purgate-size: 6808 Hypervisor notifications are currently tracked with a dedicated buff_full_pending boolean. The old RX-buffer-full path also exposed a pending indication indirectly via vm_pending, so FFA_NOTIFICATION_INFO_GET could clear that summary before the guest retrieved the Hypervisor notification bitmap with FFA_NOTIFICATION_GET. Replace the single boolean with a Hypervisor notification bitmap protected by notif_lock. INFO_GET reports pending when hyp_pending is non-zero, GET returns and clears the HYP bitmap under the lock, and RX-buffer-full now keeps notif_lock held across the local NPI decision. notif_irq_raised is only set when an NPI is actually injected, and is cleared once the local pending state is consumed. Initialize and clear the bitmap during domain lifecycle handling, and use ctx->ffa_id for bitmap create and destroy so the notification state stays tied to the cached FF-A endpoint ID. If the local injection attempt fails because no vCPU is online, hyp_pending remains set and notif_irq_raised remains clear. This keeps the RX-buffer-full notification pending until the guest retrieves it, without publishing a successful local IRQ state too early. Functional impact: RX-buffer-full remains pending in hyp_pending until FFA_NOTIFICATION_GET, and failed local NPI injection no longer leaves Xen thinking the interrupt was already raised. Signed-off-by: Bertrand Marquis --- Changes since v1: - clarify that v1 exposed RX-buffer-full indirectly via vm_pending - document that v2 keeps the HYP pending indication until FFA_NOTIFICATION_GET - keep RX-buffer-full pending state stable across failed local NPI injection attempts --- xen/arch/arm/tee/ffa_notif.c | 56 ++++++++++++++++++++++++++-------- xen/arch/arm/tee/ffa_private.h | 15 +++++++-- 2 files changed, 56 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 07bc5cb3a430..a631481e3815 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -19,7 +19,7 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; -static void inject_notif_pending(struct domain *d) +static bool inject_notif_pending(struct domain *d) { struct vcpu *v; @@ -33,13 +33,15 @@ static void inject_notif_pending(struct domain *d) if ( is_vcpu_online(v) ) { vgic_inject_irq(d, v, GUEST_FFA_NOTIF_PEND_INTR_ID, true); - return; + return true; } } if ( printk_ratelimit() ) printk(XENLOG_G_DEBUG "%pd: ffa: can't inject NPI, all vCPUs offline\n", d); + + return false; } int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) @@ -94,8 +96,15 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) notif_pending = test_and_clear_bool(ctx->notif.secure_pending); if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + { notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); + spin_lock(&ctx->notif.notif_lock); + if ( ctx->notif.hyp_pending ) + notif_pending = true; + spin_unlock(&ctx->notif.notif_lock); + } + if ( notif_pending ) { /* A pending global notification for the guest */ @@ -174,12 +183,19 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) w6 = resp.a6; } - if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && - flags & FFA_NOTIF_FLAG_BITMAP_HYP && - test_and_clear_bool(ctx->notif.buff_full_pending) ) + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { - ACCESS_ONCE(ctx->notif.vm_pending) = false; - w7 = FFA_NOTIF_RX_BUFFER_FULL; + spin_lock(&ctx->notif.notif_lock); + + if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pending ) + { + w7 = ctx->notif.hyp_pending; + ctx->notif.hyp_pending = 0; + if ( !ctx->notif.vm_pending ) + ctx->notif.notif_irq_raised = false; + } + + spin_unlock(&ctx->notif.notif_lock); } ffa_set_regs(regs, FFA_SUCCESS_32, 0, w2, w3, w4, w5, w6, w7); @@ -211,9 +227,12 @@ void ffa_raise_rx_buffer_full(struct domain *d) if ( !ctx ) return; - ACCESS_ONCE(ctx->notif.buff_full_pending) = true; - if ( !test_and_set_bool(ctx->notif.vm_pending) ) - inject_notif_pending(d); + spin_lock(&ctx->notif.notif_lock); + ctx->notif.hyp_pending |= FFA_NOTIF_RX_BUFFER_FULL; + if ( !ctx->notif.notif_irq_raised && + inject_notif_pending(d) ) + ctx->notif.notif_irq_raised = true; + spin_unlock(&ctx->notif.notif_lock); } #endif @@ -426,12 +445,16 @@ void ffa_notif_init(void) int ffa_notif_domain_init(struct domain *d) { + struct ffa_ctx *ctx = d->arch.tee; int32_t res; + spin_lock_init(&ctx->notif.notif_lock); + ctx->notif.notif_irq_raised = false; + ctx->notif.hyp_pending = 0; + if ( fw_notif_enabled ) { - - res = ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_vcpus); + res = ffa_notification_bitmap_create(ctx->ffa_id, d->max_vcpus); if ( res ) return -ENOMEM; } @@ -441,10 +464,17 @@ int ffa_notif_domain_init(struct domain *d) void ffa_notif_domain_destroy(struct domain *d) { + struct ffa_ctx *ctx = d->arch.tee; + + spin_lock(&ctx->notif.notif_lock); + ctx->notif.notif_irq_raised = false; + ctx->notif.hyp_pending = 0; + spin_unlock(&ctx->notif.notif_lock); + /* * Call bitmap_destroy even if bitmap create failed as the SPMC will * return a DENIED error that we will ignore. */ if ( fw_notif_enabled ) - ffa_notification_bitmap_destroy(ffa_get_vm_id(d)); + ffa_notification_bitmap_destroy(ctx->ffa_id); } diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index c291f32b56ff..9ddda3f88986 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -340,9 +340,20 @@ struct ffa_ctx_notif { bool vm_pending; /* - * True if domain has buffer full notification pending + * Lock protecting the hypervisor-managed notification state. */ - bool buff_full_pending; + spinlock_t notif_lock; + + /* + * Tracks whether a local notification pending interrupt was raised. + * Protected by notif_lock. + */ + bool notif_irq_raised; + + /* + * Bitmap of pending hypervisor notifications (for HYP bitmap queries). + */ + uint32_t hyp_pending; }; struct ffa_ctx { -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296938.1573064 (Exim 4.92) (envelope-from ) id 1wHxiE-0007pg-GE; Wed, 29 Apr 2026 05:43:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296938.1573064; Wed, 29 Apr 2026 05:43:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiE-0007pX-BQ; Wed, 29 Apr 2026 05:43:54 +0000 Received: by outflank-mailman (input) for mailman id 1296938; Wed, 29 Apr 2026 05:43:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiD-0007oz-Hj for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 05:43:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHxiC-002HZP-EM for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 07:43:52 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f19a93-2eae-0a2a0a5409dd-0a2a45099eba-16 for ; Wed, 29 Apr 2026 07:43:51 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f19a97-2497-0a2a45090019-d98c6eacb2e2-1 for ; Wed, 29 Apr 2026 07:43:51 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 487A32BCE; Tue, 28 Apr 2026 22:43:45 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5F20F3F62B; Tue, 28 Apr 2026 22:43:49 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441430; bh=ZkzXf1I0vx36Gf7OT0TpzCtmfOpLa/wX5cHp8GKtXYQ=; h=From:To:Cc:Subject:Date:From; b=o7M6Qm9FMba1I5/874p2BsOS9w4XUG1FccIfjsYOIZ86cRsVo9ynejMq5VN9g0Tp8 oHKSyeAwcQgJLbqDU1xVkhAvYxs8RTaHYFyzPv5YpzXkc87DXne2xGa6ML3A6I2qim BAhgAkorP2WoEb1bZBldJMNMhbYPOTDPnCwoxOgg= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 0/6] xen/arm: ffa: Harden notifications and enable VM-to-VM delivery Date: Wed, 29 Apr 2026 07:43:21 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777441431-412B2A53-0932781D/0/0 X-purgate-type: clean X-purgate-size: 2600 This series hardens FF-A notification handling in the Arm FF-A mediator and completes local delivery for non-secure VM-to-VM notifications. Hardening and state handling (Patches 1-4): 1) Fix notification pending interrupt delivery when vcpu0 is offline by reusing a common global NPI injection helper. 2) Replace the single hypervisor notification boolean with a protected HYP bitmap and keep bitmap lifecycle tied to the cached endpoint ID. 3) Tighten notification parameter validation so malformed BIND, UNBIND, GET, and SET requests are rejected consistently before reaching cached state or the SPMC. 4) Preserve the secure pending indication until secure notifications are retrieved, protect the secure pending latch with notif_lock, serialize SPMC INFO_GET polling, and keep INFO_GET return width consistent with the caller. Local VM notification delivery (Patches 5-6): 1) Track non-secure VM notification bindings locally, promote pending state to a per-bit bitmap, and validate BIND/UNBIND requests against that state. 2) Deliver non-secure VM-to-VM notifications locally, track whether a local NPI is already armed, and only advertise notification support when firmware capabilities or CONFIG_FFA_VM_TO_VM actually provide it. Backward compatibility: v1.0/v1.1 guests remain compatible. Valid guest-visible notification behavior is preserved; the series only tightens malformed-request handling and enables local non-secure VM-to-VM delivery when CONFIG_FFA_VM_TO_VM is enabled. Gitlab branch with patches: https://gitlab.com/xen-project/people/bmarquis/xen-ffa/-/tree/vm-notif/v2?ref_type=heads CI pass result: https://gitlab.com/xen-project/people/bmarquis/xen-ffa/-/pipelines/2474955136 Changes since v1: - Keep pending notification state stable across failed local NPI injection. - Tighten local NPI armed-state tracking for Hypervisor and VM notifications. - Details in each commit message. Bertrand Marquis (6): xen/arm: ffa: Fix NPI injection when vcpu0 is offline xen/arm: ffa: Track hypervisor notifications in a bitmap xen/arm: ffa: Tighten notification parameter validation xen/arm: ffa: Preserve secure notification state when polling SPMC xen/arm: ffa: Track VM notification bindings locally xen/arm: ffa: Deliver VM-to-VM notifications locally xen/arch/arm/tee/ffa.c | 24 ++- xen/arch/arm/tee/ffa_notif.c | 371 +++++++++++++++++++++++++++------ xen/arch/arm/tee/ffa_private.h | 25 ++- 3 files changed, 345 insertions(+), 75 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296943.1573091 (Exim 4.92) (envelope-from ) id 1wHxiW-00006i-2k; Wed, 29 Apr 2026 05:44:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296943.1573091; Wed, 29 Apr 2026 05:44:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiV-00006Y-W4; Wed, 29 Apr 2026 05:44:11 +0000 Received: by outflank-mailman (input) for mailman id 1296943; Wed, 29 Apr 2026 05:44:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiU-0008JC-1u for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 05:44:10 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wHxiT-002HZP-Dd for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 07:44:09 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f19aa3-2eae-0a2a0a5409dd-0a2a450b8fc0-16 for ; Wed, 29 Apr 2026 07:44:09 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f19aa8-212f-0a2a450b0019-d98c6eacb3b4-1 for ; Wed, 29 Apr 2026 07:44:09 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8D80032E2; Tue, 28 Apr 2026 22:44:02 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A3CF93F62B; Tue, 28 Apr 2026 22:44:06 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441448; bh=xwgrVrb7mJ/jIKX+IuIaposJPSmY8HXotyRYbP0OwgU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R4gqe1tXR6ZmJbt735SB+/fEeuSChDwFV3wr4m9hqQ7XjqAE34+5l34M9aPpoFGvA 0UIyKw07aTfycMyWLMoS4reXep3eaX9oJ+VWxXhPA2CND7fijyielN8S2Yq+0wRbLQ l3y+wmL1lufVjK4ujVWuFjd6LgsFsWJQpmQ4a3OE= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 3/6] xen/arm: ffa: Tighten notification parameter validation Date: Wed, 29 Apr 2026 07:43:24 +0200 Message-ID: <9ad2fe8d75a13494536787fc6aa98eb6eb3e67c6.1776955622.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-42698a/1777441449-06772F3B-A0C9D0BA/0/0 X-purgate-type: clean X-purgate-size: 6031 The notification handlers still validate overlapping subsets of their inputs. BIND, UNBIND, and SET each decode caller and destination IDs locally, GET still accepts a non-zero receiver vCPU ID and reserved flag bits, and SET still accepts non-zero NS-virtual flags. BIND also treats unsupported non-zero flag encodings as a supported-feature failure instead of as malformed input. Add ffa_notif_validate_params() and use it to centralize the common caller/destination and non-zero bitmap checks for BIND, UNBIND, and SET. Also reject malformed GET and SET requests locally before touching cached state or forwarding anything to the SPMC. Keep BIND limited to global notifications and reject unsupported non-zero flag encodings with INVALID_PARAMETERS. - add a shared parameter validator for notification caller/destination checks - wire BIND and UNBIND through the shared helper and reject unsupported bind flag encodings with INVALID_PARAMETERS - reject non-zero receiver vCPU and reserved flag bits in FFA_NOTIFICATION_GET - reject non-zero flags in the NS-virtual FFA_NOTIFICATION_SET path Functional impact: malformed notification requests are rejected consistently earlier in the mediator. Signed-off-by: Bertrand Marquis Reviewed-by: Jens Wiklander --- Changes since v1: - rename helper to ffa_notif_validate_params() - add R-b from Jens --- xen/arch/arm/tee/ffa_notif.c | 61 +++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index a631481e3815..1260f98a77e9 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -44,21 +44,40 @@ static bool inject_notif_pending(struct domain *d) return false; } +static int32_t ffa_notif_validate_params(uint16_t dom_id, uint16_t caller_id, + uint16_t dest_id, uint32_t bitmap_lo, + uint32_t bitmap_hi) +{ + if ( caller_id != dom_id || dest_id == dom_id || !dest_id ) + return FFA_RET_INVALID_PARAMETERS; + + if ( !bitmap_lo && !bitmap_hi ) + return FFA_RET_INVALID_PARAMETERS; + + return FFA_RET_OK; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; + struct ffa_ctx *ctx = d->arch.tee; + int32_t ret; uint32_t src_dst = get_user_reg(regs, 1); uint32_t flags = get_user_reg(regs, 2); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst & GENMASK(15, 0); + uint16_t dest_id = src_dst >> 16; - if ( (src_dst & GENMASK(15, 0)) != ffa_get_vm_id(d) ) + if ( flags ) /* Only global notifications are supported */ return FFA_RET_INVALID_PARAMETERS; - if ( flags ) /* Only global notifications are supported */ - return FFA_RET_DENIED; + ret = ffa_notif_validate_params(ctx->ffa_id, caller_id, dest_id, + bitmap_lo, bitmap_hi); + if ( ret ) + return ret; - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, bitmap_lo, bitmap_hi); @@ -68,16 +87,22 @@ int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) { struct domain *d = current->domain; + struct ffa_ctx *ctx = d->arch.tee; + int32_t ret; uint32_t src_dst = get_user_reg(regs, 1); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst & GENMASK(15, 0); + uint16_t dest_id = src_dst >> 16; - if ( (src_dst & GENMASK(15, 0)) != ffa_get_vm_id(d) ) - return FFA_RET_INVALID_PARAMETERS; + ret = ffa_notif_validate_params(ctx->ffa_id, caller_id, dest_id, + bitmap_lo, bitmap_hi); + if ( ret ) + return ret; - if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, + bitmap_hi); return FFA_RET_NOT_SUPPORTED; } @@ -144,6 +169,12 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) return; } + if ( recv >> 16 || (flags & GENMASK(31, 4)) ) + { + ffa_set_regs_error(regs, FFA_RET_INVALID_PARAMETERS); + return; + } + if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | FFA_NOTIF_FLAG_BITMAP_SPM )) ) { @@ -208,11 +239,19 @@ int32_t ffa_handle_notification_set(struct cpu_user_regs *regs) uint32_t flags = get_user_reg(regs, 2); uint32_t bitmap_lo = get_user_reg(regs, 3); uint32_t bitmap_hi = get_user_reg(regs, 4); + uint16_t caller_id = src_dst >> 16; + uint16_t dest_id = src_dst & GENMASK(15, 0); + int32_t ret; + + ret = ffa_notif_validate_params(ffa_get_vm_id(d), caller_id, dest_id, + bitmap_lo, bitmap_hi); + if ( ret ) + return ret; - if ( (src_dst >> 16) != ffa_get_vm_id(d) ) + if ( flags ) return FFA_RET_INVALID_PARAMETERS; - if ( FFA_ID_IS_SECURE(src_dst & GENMASK(15, 0)) && fw_notif_enabled ) + if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo, bitmap_hi); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296944.1573097 (Exim 4.92) (envelope-from ) id 1wHxiW-0000Ds-Hu; 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Wed, 29 Apr 2026 07:44:11 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69f19aaa-2497-0a2a45090019-d98c6eaccf84-1 for ; Wed, 29 Apr 2026 07:44:10 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 493EA2BCE; Tue, 28 Apr 2026 22:44:04 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 690FD3F62B; Tue, 28 Apr 2026 22:44:08 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441449; bh=BJ9kpVORXjEmJR3F6tp4iMiyL0HijTQJTCH2Qdp2K1U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dj6lhwGKazFYUmEf7LGtDyFsmG0A361JkJGAE9N5HVdzJvD+KQzg3+ZBzE7DmoUYq JO1RFx81+xWGobW+Dc3V3X5dJIhufRaAijA9bbV2xns+fylDh+2sFygNibL5acWcqr 8CSNKBYnGab6q8daj0JizFr7UeppPqRxPohsDMh0= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 4/6] xen/arm: ffa: Preserve secure notification state when polling SPMC Date: Wed, 29 Apr 2026 07:43:25 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777441450-4377AA53-000CACC7/0/0 X-purgate-type: clean X-purgate-size: 7201 Secure pending state is latched when the SPMC raises the schedule receiver interrupt, but Xen currently clears that latch too aggressively. Guest FFA_NOTIFICATION_INFO_GET consumes secure_pending even though it only reports pending state, and secure FFA_NOTIFICATION_GET only clears the latch when both SP and SPM bitmaps are requested together. This can drop a pending indication before the receiver retrieves secure notifications, or keep INFO_GET reporting stale secure pending state after a successful GET. Keep secure_pending as a latched indication until secure notifications are actually retrieved. Guest FFA_NOTIFICATION_INFO_GET now reports the latched state without clearing it, while a successful secure FFA_NOTIFICATION_GET clears the latch regardless of which secure bitmap flags were requested. Also protect secure_pending with notif_lock, serialize SPMC INFO_GET polling behind notif_info_lock, and preserve the caller-visible INFO_GET success width. Functional impact: guest INFO_GET preserves the secure pending indication until secure notifications are retrieved, and successful secure GET clears the guest-visible pending latch. Signed-off-by: Bertrand Marquis --- Changes since v1: - drop the defensive fw_notif_enabled guard in notif_sri_action() --- xen/arch/arm/tee/ffa_notif.c | 51 ++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 19 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index 1260f98a77e9..e1cd852d1c53 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -18,6 +18,7 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; +static DEFINE_SPINLOCK(notif_info_lock); static bool inject_notif_pending(struct domain *d) { @@ -111,6 +112,7 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) { struct domain *d = current->domain; struct ffa_ctx *ctx = d->arch.tee; + uint32_t fid = get_user_reg(regs, 0); bool notif_pending; if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) @@ -119,7 +121,10 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) return; } - notif_pending = test_and_clear_bool(ctx->notif.secure_pending); + spin_lock(&ctx->notif.notif_lock); + notif_pending = ctx->notif.secure_pending; + spin_unlock(&ctx->notif.notif_lock); + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); @@ -133,7 +138,9 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) if ( notif_pending ) { /* A pending global notification for the guest */ - ffa_set_regs(regs, FFA_SUCCESS_64, 0, + ffa_set_regs(regs, + smccc_is_conv_64(fid) ? FFA_SUCCESS_64 : FFA_SUCCESS_32, + 0, 1U << FFA_NOTIF_INFO_GET_ID_COUNT_SHIFT, ffa_get_vm_id(d), 0, 0, 0, 0); } @@ -156,6 +163,8 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) uint32_t w5 = 0; uint32_t w6 = 0; uint32_t w7 = 0; + uint32_t secure_flags = flags & ( FFA_NOTIF_FLAG_BITMAP_SP | + FFA_NOTIF_FLAG_BITMAP_SPM ); if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) { @@ -175,27 +184,16 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) return; } - if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | - FFA_NOTIF_FLAG_BITMAP_SPM )) ) + if ( fw_notif_enabled && secure_flags ) { struct arm_smccc_1_2_regs arg = { .a0 = FFA_NOTIFICATION_GET, .a1 = recv, - .a2 = flags & ( FFA_NOTIF_FLAG_BITMAP_SP | - FFA_NOTIF_FLAG_BITMAP_SPM ), + .a2 = secure_flags, }; struct arm_smccc_1_2_regs resp; int32_t e; - /* - * Clear secure pending if both FFA_NOTIF_FLAG_BITMAP_SP and - * FFA_NOTIF_FLAG_BITMAP_SPM are set since secure world can't have - * any more pending notifications. - */ - if ( ( flags & FFA_NOTIF_FLAG_BITMAP_SP ) && - ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) ) - ACCESS_ONCE(ctx->notif.secure_pending) = false; - arm_smccc_1_2_smc(&arg, &resp); e = ffa_get_ret_code(&resp); if ( e ) @@ -212,6 +210,10 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) if ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) w6 = resp.a6; + + spin_lock(&ctx->notif.notif_lock); + ctx->notif.secure_pending = false; + spin_unlock(&ctx->notif.notif_lock); } if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) @@ -356,7 +358,10 @@ static void notif_vm_pend_intr(uint16_t vm_id) * guarantees that the data structure isn't freed while we're accessing * it. */ - ACCESS_ONCE(ctx->notif.secure_pending) = true; + spin_lock(&ctx->notif.notif_lock); + ctx->notif.secure_pending = true; + spin_unlock(&ctx->notif.notif_lock); + inject_notif_pending(d); out_unlock: @@ -375,11 +380,15 @@ static void notif_sri_action(void *unused) unsigned int n; int32_t res; - do { + spin_lock(¬if_info_lock); + + do + { arm_smccc_1_2_smc(&arg, &resp); res = ffa_get_ret_code(&resp); if ( res ) { + spin_unlock(¬if_info_lock); if ( res != FFA_RET_NO_DATA && printk_ratelimit() ) printk(XENLOG_WARNING "ffa: notification info get failed: error %d\n", res); @@ -393,7 +402,7 @@ static void notif_sri_action(void *unused) id_pos = 0; for ( n = 0; n < list_count; n++ ) { - unsigned int count = ((ids_count >> 2 * n) & 0x3) + 1; + unsigned int count = ((ids_count >> (2 * n)) & 0x3) + 1; uint16_t vm_id = get_id_from_resp(&resp, id_pos); notif_vm_pend_intr(vm_id); @@ -401,7 +410,9 @@ static void notif_sri_action(void *unused) id_pos += count; } - } while (resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG); + } while ( resp.a2 & FFA_NOTIF_INFO_GET_MORE_FLAG ); + + spin_unlock(¬if_info_lock); } static DECLARE_TASKLET(notif_sri_tasklet, notif_sri_action, NULL); @@ -489,6 +500,7 @@ int ffa_notif_domain_init(struct domain *d) spin_lock_init(&ctx->notif.notif_lock); ctx->notif.notif_irq_raised = false; + ctx->notif.secure_pending = false; ctx->notif.hyp_pending = 0; if ( fw_notif_enabled ) @@ -507,6 +519,7 @@ void ffa_notif_domain_destroy(struct domain *d) spin_lock(&ctx->notif.notif_lock); ctx->notif.notif_irq_raised = false; + ctx->notif.secure_pending = false; ctx->notif.hyp_pending = 0; spin_unlock(&ctx->notif.notif_lock); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296946.1573109 (Exim 4.92) (envelope-from ) id 1wHxiY-0000bp-OE; Wed, 29 Apr 2026 05:44:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296946.1573109; Wed, 29 Apr 2026 05:44:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiY-0000bc-LF; Wed, 29 Apr 2026 05:44:14 +0000 Received: by outflank-mailman (input) for mailman id 1296946; Wed, 29 Apr 2026 05:44:13 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiX-0000UH-Ev for xen-devel@lists.xenproject.org; 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dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441451; bh=HhDBJf0IfXGwpTjfY2ecC/WNtpLQx+0BHlKhp3zkvP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IyJIf0pObIJcvGsVV9rDtmrwWDUL7jn1OseYOkchfyR6ODE67oB/EJgwZ9Ktpy4AA KJsL3tzy0R1TvDrx8ZkjYsKpVD2BNVCDyQYY4zBvHUhbeEBO+CDCDUpKQQj8Rd1TqZ fGK6iiLEeIkfWb7lU9BUUmWksA0S19uJDoKnx5E8= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 5/6] xen/arm: ffa: Track VM notification bindings locally Date: Wed, 29 Apr 2026 07:43:26 +0200 Message-ID: <13a7b810346a31acb5b1407b51c17141aebb33f8.1776955622.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d25034/1777441452-6E169CF5-22CD8A8E/0/0 X-purgate-type: clean X-purgate-size: 7559 VM-to-VM notifications need receiver-side bind state so Xen can validate which sender owns each notification bit. Non-secure BIND and UNBIND requests currently have no local state and cannot enforce that contract. Add per-bit VM notification binding state to struct ffa_ctx_notif and use it to handle non-secure BIND and UNBIND requests when CONFIG_FFA_VM_TO_VM is enabled. The update helper validates the whole request under notif_lock before mutating anything, denies bind or unbind when a bit is pending, rejects rebinding to a different sender, and keeps rebinding to the same sender idempotent. Promote vm_pending to a bitmap so the bind logic can reason per notification ID, use that bitmap directly when reporting pending state, and initialize and clear the new VM notification state during domain init and teardown. Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, Xen tracks VM notification bindings locally and validates non-secure bind and unbind requests against that state. Signed-off-by: Bertrand Marquis --- Changes since v1: - use memset() to clear vm_bind[] in init/destroy - replace the file-scope #error check with BUILD_BUG_ON() --- xen/arch/arm/tee/ffa_notif.c | 96 ++++++++++++++++++++++++++++++---- xen/arch/arm/tee/ffa_private.h | 11 ++-- 2 files changed, 94 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index e1cd852d1c53..a841c8f8d747 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -58,6 +59,54 @@ static int32_t ffa_notif_validate_params(uint16_t dom_id, uint16_t caller_id, return FFA_RET_OK; } +static int32_t ffa_notif_update_vm_binding(struct ffa_ctx *ctx, + uint16_t dest_id, uint64_t bitmap, + bool bind) +{ + unsigned int id; + int32_t ret = FFA_RET_OK; + + spin_lock(&ctx->notif.notif_lock); + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( !(bitmap & BIT(id, ULL)) ) + continue; + + if ( ctx->notif.vm_pending & BIT(id, ULL) ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + + if ( bind ) + { + if ( ctx->notif.vm_bind[id] != 0 && + ctx->notif.vm_bind[id] != dest_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + else if ( ctx->notif.vm_bind[id] != dest_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( bitmap & BIT(id, ULL) ) + ctx->notif.vm_bind[id] = bind ? dest_id : 0; + } + +out_unlock: + spin_unlock(&ctx->notif.notif_lock); + + return ret; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -78,11 +127,21 @@ int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) if ( ret ) return ret; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, - bitmap_lo, bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, + bitmap_lo, bitmap_hi); - return FFA_RET_NOT_SUPPORTED; + return FFA_RET_NOT_SUPPORTED; + } + + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + return FFA_RET_NOT_SUPPORTED; + + return ffa_notif_update_vm_binding(ctx, dest_id, + ((uint64_t)bitmap_hi << 32) | bitmap_lo, + true); } int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) @@ -101,11 +160,21 @@ int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs) if ( ret ) return ret; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, + bitmap_lo, bitmap_hi); - return FFA_RET_NOT_SUPPORTED; + return FFA_RET_NOT_SUPPORTED; + } + + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + return FFA_RET_NOT_SUPPORTED; + + return ffa_notif_update_vm_binding(ctx, dest_id, + ((uint64_t)bitmap_hi << 32) | bitmap_lo, + false); } void ffa_handle_notification_info_get(struct cpu_user_regs *regs) @@ -127,9 +196,10 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs) if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { - notif_pending |= test_and_clear_bool(ctx->notif.vm_pending); - spin_lock(&ctx->notif.notif_lock); + if ( ctx->notif.vm_pending ) + notif_pending = true; + if ( ctx->notif.hyp_pending ) notif_pending = true; spin_unlock(&ctx->notif.notif_lock); @@ -498,9 +568,13 @@ int ffa_notif_domain_init(struct domain *d) struct ffa_ctx *ctx = d->arch.tee; int32_t res; + BUILD_BUG_ON(FFA_NUM_VM_NOTIF > 64); + spin_lock_init(&ctx->notif.notif_lock); ctx->notif.notif_irq_raised = false; ctx->notif.secure_pending = false; + ctx->notif.vm_pending = 0; + memset(ctx->notif.vm_bind, 0, sizeof(ctx->notif.vm_bind)); ctx->notif.hyp_pending = 0; if ( fw_notif_enabled ) @@ -520,6 +594,8 @@ void ffa_notif_domain_destroy(struct domain *d) spin_lock(&ctx->notif.notif_lock); ctx->notif.notif_irq_raised = false; ctx->notif.secure_pending = false; + ctx->notif.vm_pending = 0; + memset(ctx->notif.vm_bind, 0, sizeof(ctx->notif.vm_bind)); ctx->notif.hyp_pending = 0; spin_unlock(&ctx->notif.notif_lock); diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index 9ddda3f88986..78a0a9815d56 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -236,6 +236,7 @@ #define FFA_NOTIF_INFO_GET_ID_COUNT_MASK 0x1F #define FFA_NOTIF_RX_BUFFER_FULL BIT(0, U) +#define FFA_NUM_VM_NOTIF 64U /* Feature IDs used with FFA_FEATURES */ #define FFA_FEATURE_NOTIF_PEND_INTR 0x1U @@ -334,10 +335,14 @@ struct ffa_ctx_notif { bool secure_pending; /* - * True if domain is reported by FFA_NOTIFICATION_INFO_GET to have - * pending notifications from VMs (including framework ones). + * Bitmap of pending notifications from VMs (including framework ones). + */ + uint64_t vm_pending; + + /* + * Source endpoint bound to each VM notification ID (0 means unbound). */ - bool vm_pending; + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; /* * Lock protecting the hypervisor-managed notification state. -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 05:44:26 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 05:44:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1296949.1573118 (Exim 4.92) (envelope-from ) id 1wHxia-0000tZ-2t; Wed, 29 Apr 2026 05:44:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1296949.1573118; Wed, 29 Apr 2026 05:44:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHxiZ-0000tM-UR; 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Tue, 28 Apr 2026 22:44:07 -0700 (PDT) Received: from C3HXLD123V.arm.com (unknown [10.57.90.163]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DFC2A3F62B; Tue, 28 Apr 2026 22:44:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1777441453; bh=bzcppw7eOfYm4UiVzmHypcylvW+Izet9K8ImNObcrec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EcTW028WW95ZvmPZrEP3MQi38GiBXqEkA3YIIlkrpv8KntLoZC1veLBlB0VXu4Kbe YT+yJM9PfMnmtQOemAu3Zhn+PfCP/pyL+qjsE++Dckr70vKM1is21h6w5v4ncqXRKR Q2tLb0cg+i3tayPZilp/KryTowOReQLSLo4exmAk= From: Bertrand Marquis To: xen-devel@lists.xenproject.org Cc: Volodymyr Babchuk , Jens Wiklander , Stefano Stabellini , Julien Grall , Michal Orzel Subject: [PATCH v2 6/6] xen/arm: ffa: Deliver VM-to-VM notifications locally Date: Wed, 29 Apr 2026 07:43:27 +0200 Message-ID: <1ead2af7182a0501f16e7b4e9ad3e58ccd8f538c.1776955622.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1777441454-BDC64FF4-3CDC08FC/0/0 X-purgate-type: clean X-purgate-size: 9730 VM notification binding and pending tracking exist for non-secure endpoints, but FFA_NOTIFICATION_SET still only forwards secure destinations to the SPMC. Non-secure VMs therefore cannot receive notifications from other VMs. Local NPI delivery also needs explicit re-arm tracking so repeated raises are not lost while the interrupt is already pending. Add a local VM notification delivery path for non-secure destinations. notification_set_vm() resolves the destination endpoint, verifies that every requested bit is bound to the sender, sets the receiver's vm_pending bitmap under notif_lock, and raises an NPI only when local pending state is not already armed. Track whether a local NPI is already armed with notif_irq_raised, clear that state once both VM and hypervisor pending bitmaps are drained, and keep notif_lock held across the VM notification injection attempt. If no destination vCPU is online, leave the pending bits set and keep notif_irq_raised clear so delivery can be retried later. Also expose firmware notification availability so FFA_FEATURES only advertises notification support when it is actually provided by the firmware or by CONFIG_FFA_VM_TO_VM. Functional impact: when CONFIG_FFA_VM_TO_VM is enabled, non-secure FFA_NOTIFICATION_SET delivers VM-to-VM notifications locally and keeps NPI delivery reliable across repeated raises. Signed-off-by: Bertrand Marquis --- Changes since v1: - serialize notification_set_vm() state updates with the NPI attempt - keep pending VM notifications set when local injection fails --- xen/arch/arm/tee/ffa.c | 24 ++++++++-- xen/arch/arm/tee/ffa_notif.c | 82 ++++++++++++++++++++++++++++++++-- xen/arch/arm/tee/ffa_private.h | 17 ++++--- 3 files changed, 107 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c index 1fe33f26454a..7fe021049cba 100644 --- a/xen/arch/arm/tee/ffa.c +++ b/xen/arch/arm/tee/ffa.c @@ -39,8 +39,13 @@ * o FFA_MSG_SEND_DIRECT_REQ: * - only supported from a VM to an SP * o FFA_NOTIFICATION_*: + * - only supported when firmware notifications are enabled or VM-to-VM + * support is built in * - only supports global notifications, that is, per vCPU notifications - * are not supported + * are not supported and secure per-vCPU notification information is + * not forwarded + * - the source endpoint ID reported for a notification may no longer + * exist by the time the receiver consumes it * - doesn't support signalling the secondary scheduler of pending * notification for secure partitions * - doesn't support notifications for Xen itself @@ -245,6 +250,8 @@ static void handle_features(struct cpu_user_regs *regs) uint32_t a1 = get_user_reg(regs, 1); struct domain *d = current->domain; struct ffa_ctx *ctx = d->arch.tee; + bool notif_supported = IS_ENABLED(CONFIG_FFA_VM_TO_VM) || + ffa_notif_fw_enabled(); /* * FFA_FEATURES defines w2 as input properties only for specific @@ -343,10 +350,16 @@ static void handle_features(struct cpu_user_regs *regs) break; case FFA_FEATURE_NOTIF_PEND_INTR: - ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, GUEST_FFA_NOTIF_PEND_INTR_ID, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; case FFA_FEATURE_SCHEDULE_RECV_INTR: - ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, GUEST_FFA_SCHEDULE_RECV_INTR_ID, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; case FFA_PARTITION_INFO_GET_REGS: if ( ACCESS_ONCE(ctx->guest_vers) >= FFA_VERSION_1_2 ) @@ -361,7 +374,10 @@ static void handle_features(struct cpu_user_regs *regs) case FFA_NOTIFICATION_SET: case FFA_NOTIFICATION_INFO_GET_32: case FFA_NOTIFICATION_INFO_GET_64: - ffa_set_regs_success(regs, 0, 0); + if ( notif_supported ) + ffa_set_regs_success(regs, 0, 0); + else + ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); break; default: ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c index a841c8f8d747..b29d948a7110 100644 --- a/xen/arch/arm/tee/ffa_notif.c +++ b/xen/arch/arm/tee/ffa_notif.c @@ -21,6 +21,11 @@ static bool __ro_after_init fw_notif_enabled; static unsigned int __ro_after_init notif_sri_irq; static DEFINE_SPINLOCK(notif_info_lock); +bool ffa_notif_fw_enabled(void) +{ + return fw_notif_enabled; +} + static bool inject_notif_pending(struct domain *d) { struct vcpu *v; @@ -107,6 +112,55 @@ out_unlock: return ret; } +/* + * Deliver a VM-to-VM notification. ctx->notif.notif_lock protects + * vm_bind/vm_pending so callers must not hold it already. + */ +static int32_t notification_set_vm(uint16_t dst_id, uint16_t src_id, + uint32_t flags, uint64_t bitmap) +{ + struct domain *dst_d; + struct ffa_ctx *dst_ctx; + unsigned int id; + int32_t ret; + + if ( flags ) + return FFA_RET_INVALID_PARAMETERS; + + ret = ffa_endpoint_domain_lookup(dst_id, &dst_d, &dst_ctx); + if ( ret ) + return ret; + + ret = FFA_RET_OK; + + spin_lock(&dst_ctx->notif.notif_lock); + + for ( id = 0; id < FFA_NUM_VM_NOTIF; id++ ) + { + if ( !(bitmap & BIT(id, ULL)) ) + continue; + + if ( dst_ctx->notif.vm_bind[id] != src_id ) + { + ret = FFA_RET_DENIED; + goto out_unlock; + } + } + + dst_ctx->notif.vm_pending |= bitmap; + if ( !dst_ctx->notif.notif_irq_raised && + (dst_ctx->notif.vm_pending || dst_ctx->notif.hyp_pending) && + inject_notif_pending(dst_d) ) + dst_ctx->notif.notif_irq_raised = true; + +out_unlock: + spin_unlock(&dst_ctx->notif.notif_lock); + + rcu_unlock_domain(dst_d); + + return ret; +} + int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs) { struct domain *d = current->domain; @@ -288,6 +342,8 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) { + bool pending; + spin_lock(&ctx->notif.notif_lock); if ( (flags & FFA_NOTIF_FLAG_BITMAP_HYP) && ctx->notif.hyp_pending ) @@ -298,6 +354,18 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs) ctx->notif.notif_irq_raised = false; } + if ( (flags & FFA_NOTIF_FLAG_BITMAP_VM) && ctx->notif.vm_pending ) + { + w4 = (uint32_t)(ctx->notif.vm_pending & GENMASK(31, 0)); + w5 = (uint32_t)((ctx->notif.vm_pending >> 32) & GENMASK(31, 0)); + ctx->notif.vm_pending = 0; + } + + pending = (ctx->notif.hyp_pending != 0) || + (ctx->notif.vm_pending != 0); + if ( !pending ) + ctx->notif.notif_irq_raised = false; + spin_unlock(&ctx->notif.notif_lock); } @@ -323,9 +391,17 @@ int32_t ffa_handle_notification_set(struct cpu_user_regs *regs) if ( flags ) return FFA_RET_INVALID_PARAMETERS; - if ( FFA_ID_IS_SECURE(dest_id) && fw_notif_enabled ) - return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo, - bitmap_hi); + if ( FFA_ID_IS_SECURE(dest_id) ) + { + if ( fw_notif_enabled ) + return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, + bitmap_lo, bitmap_hi); + } + else if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) + { + return notification_set_vm(dest_id, caller_id, flags, + ((uint64_t)bitmap_hi << 32) | bitmap_lo); + } return FFA_RET_NOT_SUPPORTED; } diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h index 78a0a9815d56..923a071a9d7c 100644 --- a/xen/arch/arm/tee/ffa_private.h +++ b/xen/arch/arm/tee/ffa_private.h @@ -340,20 +340,18 @@ struct ffa_ctx_notif { uint64_t vm_pending; /* - * Source endpoint bound to each VM notification ID (0 means unbound). + * Tracks whether an NPI has been raised for local pending notifications. + * Protected by notif_lock. */ - uint16_t vm_bind[FFA_NUM_VM_NOTIF]; + bool notif_irq_raised; /* - * Lock protecting the hypervisor-managed notification state. + * Source endpoint bound to each VM notification ID (0 means unbound). */ - spinlock_t notif_lock; + uint16_t vm_bind[FFA_NUM_VM_NOTIF]; - /* - * Tracks whether a local notification pending interrupt was raised. - * Protected by notif_lock. - */ - bool notif_irq_raised; + /* Lock protecting local notification state. */ + spinlock_t notif_lock; /* * Bitmap of pending hypervisor notifications (for HYP bitmap queries). @@ -495,6 +493,7 @@ void ffa_notif_init(void); void ffa_notif_init_interrupt(void); int ffa_notif_domain_init(struct domain *d); void ffa_notif_domain_destroy(struct domain *d); +bool ffa_notif_fw_enabled(void); int32_t ffa_handle_notification_bind(struct cpu_user_regs *regs); int32_t ffa_handle_notification_unbind(struct cpu_user_regs *regs); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 06:41:33 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 06:41:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297003.1573128 (Exim 4.92) (envelope-from ) id 1wHybl-0003HJ-Ga; Wed, 29 Apr 2026 06:41:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297003.1573128; Wed, 29 Apr 2026 06:41:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wHybl-0003HC-CB; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HKif+WZoMjrEOXGC4r7IxoNsOlohGQ2iSZoAqjXA21zN+PhRKxbJ/b/hXGl5te5MIsVntKXIf1h6h+nr8dwj4R3ZbtFVEnKWcWfHUGzAPNpCBYnNh/vUUiiNUI3hdA3d0NOBINDMKC6ORe+DkmWOL0wfNDayU892gygEW9G3m2zpYq1xIP9hJrVYAtCX2Iq1Je29/62BLJKhicLvfMYqaSJdWiDhpOb5PbmQ4JBmzEMjKlALAhF+BC4gzTlK0vjBn41ajixRiYGHpa24zh9X1Sfv8YmC6BKeMlbFSC6uvU/wJTaRL4uKzx/AejXnWn0FgPknbUWF4bE95A0+JMJsBw5mMz74B4JQnk352W58CnFqVHBIEfSCbP6XMOyladlyGt+QFx903H36ocXLO3mXkr9009lx9pddUzPpvWOpsQj4OwL5UCWSHUa2DRgbooV6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 06:41:08.9339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 854828dd-c9a2-4509-083e-08dea5ba4bf1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9602 X-purgate-ID: tlsNG-bad1c0/1777444874-93F7EA53-A22CDC16/0/0 X-purgate-type: clean X-purgate-size: 4471 I committed the first two patches. I decided to wait with the third patch for Jan as he was the one with the most remarks. ~Michal On 27-Apr-26 17:34, Oleksii Kurochko wrote: > This patch series introduces a new field to track not-yet-used phandles as there > are some use cases where RISC-V needs to know which phandle number could > be used for generating a device tree node. > > For example, on the RISC-V side in make_cpus_node() [1] it is necessary to know > which phandle number is unused to use it for device tree node generation. > > Here is an example of generated guest DTB: > cpus { > ... > cpu@0 { > ... > interrupt-controller { > compatible = "riscv,cpu-intc"; > #interrupt-cells = <0x1>; > interrupt-controller; > phandle = <0xfdea>; > }; > }; > }; > > /soc/imsics@28000000 { > > interrupts-extended = <0xfdea 0x9 >; > > phandle = <0xfdeb>; > }; > > /soc/aplic@d000000 { > ... > msi-parent = <0xfdeb>; > phandle = <0x1>; > }; > > Note that phandles for imsic and riscv,cpu-intc are generated in this example > not by get_next_free_phandle(), that is why they have such big numbers. > > For non-RISC-V people, APLIC is an interrupt controller (something like GIC in > Arm), IMSIC is an interrupt controller that provides MSI and connects to > each CPU. > > So (based on the DTS above) for APLIC, kinfo->phandle_intc is reused, which > will also be re-used for the device node's interrupt property. For all others, I > just introduced GUEST_PHANDLE_LAST [2] and used it for generation [3]. But I expect > that it could be useful for other architectures too so I just moved it to common > and re-use pfdt to understand what the maximum used phandle is. > > [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/riscv%2Ccpu-intc.txt > [2] https://lore.kernel.org/xen-devel/ccd6d21b224b478c88ca5f2fdd2d1dd507671510.1773157782.git.oleksii.kurochko@gmail.com/ > [3] https://lore.kernel.org/xen-devel/fd64b8526a23e9d7775b9b48c5a933b0673c4fba.1773157782.git.oleksii.kurochko@gmail.com/ > ************************************* > > Another thing introduced in this patch series is moving domain type to common > code as several architectures (ARM and RISC-V for now) use them and it > looks pretty architecture-independent. Also, is_64bit_domain() is used by > dom0less common code, so I found it useful also to move is_{32,64}bit_domain > macros to common code. > > ************************************* > > And the last thing is changing the prototype of make_cpus_node() to be aligned > with other make_*_node() and since RISC-V will need access to the free_phandle field > (even if it will be moved to kinfo->arch.free_phandle) and for the reason that > this ->free_phandle is updated in make_*_node(), the kinfo argument is passed as > non-const. > > CI: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/2482499536 > > --- > Changes in v4: > - Rebase on top of staging. > - Add Review-by for patch 1 and 3. > - Address the comments. > --- > Changes in v3: > - Rebase on top of staging. > - Address the comments. > --- > Changes in v2: > - Address the comments from ML. > --- > > Oleksii Kurochko (3): > xen/dom0less: introduce next_phandle in struct kernel_info > xen/dom0less: pass kernel_info struct instead of fdt to > make_cpus_node() > xen: introduce CONFIG_HAS_DOMAIN_TYPE > > xen/arch/arm/Kconfig | 1 + > xen/arch/arm/arm64/domctl.c | 4 +-- > xen/arch/arm/dom0less-build.c | 14 -------- > xen/arch/arm/domain_build.c | 17 +++++----- > xen/arch/arm/include/asm/domain.h | 16 --------- > xen/arch/arm/include/asm/kernel.h | 4 --- > xen/arch/arm/kernel.c | 16 ++++----- > xen/common/Kconfig | 3 ++ > xen/common/device-tree/dom0less-build.c | 45 ++++++++++++++++++------- > xen/include/xen/dom0less-build.h | 2 -- > xen/include/xen/domain.h | 13 +++++++ > xen/include/xen/fdt-domain-build.h | 17 +++++++++- > xen/include/xen/fdt-kernel.h | 11 ++++++ > xen/include/xen/sched.h | 4 +++ > 14 files changed, 98 insertions(+), 69 deletions(-) > From xen-devel-bounces@lists.xenproject.org Wed Apr 29 07:23:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 07:23:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297022.1573168 (Exim 4.92) (envelope-from ) id 1wHzFu-00016x-R7; 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Wed, 29 Apr 2026 09:22:44 +0200 Received: from [160.101.131.9] (helo=na1pdmzitismtp02.tibco.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1b1c3-63b5-0a2a45080019-a0658309baa8-3 for ; Wed, 29 Apr 2026 09:22:44 +0200 Received: from debian.eng.citrite.net (unknown [10.113.40.46]) by na1pdmzitismtp02.tibco.com (Postfix) with ESMTP id AE9E081D7239; Wed, 29 Apr 2026 03:21:42 -0400 (EDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none From: Bernhard Kaindl To: xen-devel@lists.xenproject.org Cc: Bernhard Kaindl , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH] Improved reStructuredText formatting of Misra C Rules Date: Wed, 29 Apr 2026 08:22:13 +0100 Message-Id: X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-c1860d/1777447364-C0965DB1-8E1E7D20/0/0 X-purgate-type: clean X-purgate-size: 6351 Code blocks in the RFC rules can be converted as C syntax-highlighted pretty pieces of code using `.. code:: C` inline elements: https://docutils.sourceforge.io/docs/ref/rst/directives.html#code For reference, the current formatting used are 'Indented Literal Blocks': https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#toc-entry-23 In this example, docs/misra/rules.rst, line 128 starts an Indented Literal Block by ending the paragraph with "violations::" (note the :: at then end of the paragraph which is enables it): - Functions that are no-return due to calls to the `ASSERT_UNREACHABLE()` macro in debug build configurations are not considered violations:: static inline bool arch_vcpu_ioreq_completion(enum vio_completion completion) { ASSERT_UNREACHABLE(); return false; } Format such code blocks as C code blocks and apply ``function()`` around functions to make them inline linterals for monospace formatting. Also make some code blocks less wide to fit into the column of the table. Signed-off-by: Bernhard Kaindl --- Of course, this is only a 1st step, it may be extended further in further merges. Preview based on the theme update submitted yesterday: https://lists.xen.org/archives/html/xen-devel/2026-04/msg01375.html: https://bernhard-xen.readthedocs.io/en/misra-rules-format-rfc/misra/rules.html BTW: The way the ReadTheDocs (RTD) theme has another issue where it applies: 'td { white-space: nowrap; }' to all table data, preventing wrapping lines inside long table cells: https://xenbits.xen.org/docs/sphinx-unstable/misra/rules.html This mostly shows on xenbits for me, but this is a widely known RTD bug. The RTD Sphinx devs see this bug as a feature, and are unwilling to fix: https://github.com/readthedocs/sphinx_rtd_theme/issues/139 (example bug) There are workarounds, but to better address this 1st step, I propose to add a theme which does not appear to have this issue (and also has a more modern look and feel with auto dark mode support (can be switched to bright mode and darm mode directly as well): https://lists.xen.org/archives/html/xen-devel/2026-04/msg01375.html Signed-off-by: Bernhard Kaindl --- docs/misra/rules.rst | 43 ++++++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst index fc6fdfd313d0..82412e819846 100644 --- a/docs/misra/rules.rst +++ b/docs/misra/rules.rst @@ -115,20 +115,29 @@ maintainers if you want to suggest a change. - Required - A project shall not contain unreachable code - The following are allowed: - - Invariantly constant conditions, e.g. if(IS_ENABLED(CONFIG_HVM)) { S; } + - Invariantly constant conditions, e.g. + + .. code:: C + + if ( IS_ENABLED(CONFIG_HVM) ) { + S; + } + - Switch with a controlling value statically determined not to match one or more case statements - Functions that are intended to be referenced only from - assembly code (e.g. 'do_trap_fiq') - - asm-offsets.c, as they are not linked deliberately, because + assembly code (e.g. ``do_trap_fiq``) + - ``asm-offsets.c``, as they are not linked deliberately, because they are used to generate definitions for asm modules - Declarations without initializer are safe, as they are not executed - - Functions that are no-return due to calls to the `ASSERT_UNREACHABLE()` - macro in debug build configurations are not considered violations:: + - Functions that are no-return due to calls to the ``ASSERT_UNREACHABLE()`` + macro in debug build configurations are not considered violations: + + .. code:: C static inline bool - arch_vcpu_ioreq_completion(enum vio_completion completion) + arch_vcpu_ioreq_completion(int c) { ASSERT_UNREACHABLE(); return false; @@ -141,13 +150,13 @@ maintainers if you want to suggest a change. * - `Rule 3.1 `_ - Required - - The character sequences /* and // shall not be used within a + - The character sequences ``/*`` and ``//`` shall not be used within a comment - Comments containing URLs inside C-style block comments are safe * - `Rule 3.2 `_ - Required - - Line-splicing shall not be used in // comments + - Line-splicing shall not be used in ``//`` comments - * - `Rule 4.1 `_ @@ -207,16 +216,20 @@ maintainers if you want to suggest a change. Clashes between bitops functions and macro names are allowed because they are used for input validation and error handling. - Example:: + Example: - static inline void set_bit(int nr, volatile void *addr) + .. code:: C + + static inline void set_bit(int nr, volatile void *a) { - asm volatile ( "lock btsl %1,%0" - : "+m" (ADDR) : "Ir" (nr) : "memory"); + asm volatile ( "lock btsl %1,%0 " + : "+m" (a) + : "Ir" (nr) : "memory"); } - #define set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - set_bit(nr, addr); \ + + #define set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size();\ + set_bit(nr, addr); \ }) Clashes between grant table functions and macro names are allowed -- 2.39.5 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 07:34:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 07:34:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297051.1573177 (Exim 4.92) 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X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B8B.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB10619 X-purgate-ID: tlsNG-c201ff/1777450691-E17A6443-3003D9B7/0/0 X-purgate-type: clean X-purgate-size: 1760 Hi Mykola, > On 28 Apr 2026, at 12:57, Mykola Kvach wrote: >=20 > From: Mykola Kvach >=20 > The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. >=20 > Per IHI0048B.b section 2.3.1, clearing the architected bypass-disable > bits selects bypass rather than deasserted interrupt outputs when the > CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed > GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully > disabling the interface. >=20 > Fix this by reading GICC_CTLR, then setting the bypass-disable bits and > clearing the group-enable bits that are architecturally defined for the > current GICC_CTLR view before writing the value back. When Security > Extensions are implemented Xen accesses the Non-secure copy of > GICC_CTLR, where IRQBypDisGrp1 and FIQBypDisGrp1 are at bits [6:5] and > bits [8:7] are reserved. >=20 > Without Security Extensions there is no separate Secure/Non-secure CPU > interface view, so disabling both group-enable bits affects the shared > interface state. This is still appropriate for the CPU shutdown path, > which is expected to stop normal interrupt delivery through the interface > and rely only on the architecturally separate wakeup event signaling. >=20 > Section 2.3.2 also states that wakeup event signals remain available > even when both GIC interrupt signaling and interrupt bypass are > disabled, so disabling bypass does not break the power-management use > case, i.e. suspend modes. >=20 > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > Signed-off-by: Mykola Kvach Looks good to me Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 29 08:20:16 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 08:20:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297103.1573236 (Exim 4.92) (envelope-from ) id 1wI09O-0003Nl-4s; Wed, 29 Apr 2026 08:20:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297103.1573236; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GbwjqbxnugEvb3Y7uiqjopvWtjL3dIXhZcbtEoBwK93mDKY80dKyQ1mQ728W0RVai5hGg0wqRWLT1p89VVsibvpPpJ6kwoyrdHb0SQy6kry1ogPnrto2p1YnqyTTH7QkG3qlYmhu0OsKYILo7kz6easVEeLtTOASfEBAxunZs215rOkT5xyAo+f3Ef9DjkxzDXOB0QgHA/xx3Ipc919bElXtnyC7O0LuLdDoAba+fa8NkEahaI9aI7ablChaTYot4eJXPiimBrNCK+5KsBXsX8KFrHYLOlCeKURBjuoTqRCs/ajC2ZGjuThiGT/hoZmioeRdjQe3G0q3Iy0B8u7oPgpfA0tGpLo0L65V9OpVF/0karIWfEagw2wxWQYUUxer0J6cPG3hL9/I698oSmn3UwQr5zJCvZobUVXSu+QzBKPZZiO6CdPXG7oN9YNkPMOT X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 08:19:56.4995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d7a253f6-4747-4e16-75c2-08dea5c81911 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9354 X-purgate-ID: tlsNG-c201ff/1777450803-2AF6E443-1035E2C9/0/0 X-purgate-type: clean X-purgate-size: 4842 On 28-Apr-26 13:57, Mykola Kvach wrote: > From: Mykola Kvach > > The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. > > Per IHI0048B.b section 2.3.1, clearing the architected bypass-disable > bits selects bypass rather than deasserted interrupt outputs when the > CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed > GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully > disabling the interface. > > Fix this by reading GICC_CTLR, then setting the bypass-disable bits and > clearing the group-enable bits that are architecturally defined for the > current GICC_CTLR view before writing the value back. When Security > Extensions are implemented Xen accesses the Non-secure copy of > GICC_CTLR, where IRQBypDisGrp1 and FIQBypDisGrp1 are at bits [6:5] and > bits [8:7] are reserved. > > Without Security Extensions there is no separate Secure/Non-secure CPU > interface view, so disabling both group-enable bits affects the shared > interface state. This is still appropriate for the CPU shutdown path, > which is expected to stop normal interrupt delivery through the interface > and rely only on the architecturally separate wakeup event signaling. > > Section 2.3.2 also states that wakeup event signals remain available > even when both GIC interrupt signaling and interrupt bypass are > disabled, so disabling bypass does not break the power-management use > case, i.e. suspend modes. > > Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") > Signed-off-by: Mykola Kvach > > --- > Changes in v2: > - derive the shutdown masks from the active GICC_CTLR layout > - use the Non-secure GICC_CTLR layout when GICD_TYPER.SecurityExtn is set > - stop writing reserved bits [8:7] on Security Extensions systems > --- > xen/arch/arm/gic-v2.c | 16 +++++++++++++++- > xen/arch/arm/include/asm/gic.h | 25 +++++++++++++++++++++++-- > 2 files changed, 38 insertions(+), 3 deletions(-) > > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c > index 014f955967..241c1ff5c5 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -408,7 +408,21 @@ static void gicv2_cpu_init(void) > > static void gicv2_cpu_disable(void) > { > - writel_gicc(0x0, GICC_CTLR); > + uint32_t ctlr = readl_gicc(GICC_CTLR); > + > + if ( readl_gicd(GICD_TYPER) & GICD_TYPE_SEC ) > + { > + ctlr |= GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK; > + ctlr &= ~GICC_CTL_ENABLE; > + } > + else > + { > + ctlr |= GICC_CTLR_BYPASS_DISABLE_GRP0_MASK | > + GICC_CTLR_BYPASS_DISABLE_GRP1_MASK; > + ctlr &= ~(GICC_CTL_ENABLE | GICC_CTL_ENABLE_GRP1); > + } I don't understand why you want to set both G0 and G1, Bits 5-6 in the NS view control Group 1, while the same bits in the Secure/single-security-state view control Group 0. So in the latter case you don't need to set G1. Without security extensions all interrupts are G0 and with security extensions (NS access) all interrupts are G1. The spec guarantees the functional mapping. ~Michal > + > + writel_gicc(ctlr, GICC_CTLR); > } > > static void gicv2_hyp_init(void) > diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h > index 8e713aa477..ff22dea40d 100644 > --- a/xen/arch/arm/include/asm/gic.h > +++ b/xen/arch/arm/include/asm/gic.h > @@ -102,8 +102,29 @@ > #define GICD_TYPE_SEC 0x400 > #define GICD_TYPER_DVIS (1U << 18) > > -#define GICC_CTL_ENABLE 0x1 > -#define GICC_CTL_EOI (0x1 << 9) > +/* > + * Xen runs in the Non-secure world. When Security Extensions are present, > + * Xen accesses the Non-secure GICC_CTLR view, where bit[0] is EnableGrp1 > + * and bits[6:5] are the Group 1 bypass-disable bits. Otherwise Xen sees the > + * common GICC_CTLR layout, where bit[0] is EnableGrp0, bit[1] is EnableGrp1, > + * bits[6:5] are the Group 0 bypass-disable bits, and bits[8:7] are the > + * Group 1 bypass-disable bits. > + */ > +#define GICC_CTL_ENABLE (0x1 << 0) > +#define GICC_CTL_ENABLE_GRP1 (0x1 << 1) > +#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5) > +#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6) > +#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7) > +#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8) > + > +#define GICC_CTLR_BYPASS_DISABLE_GRP0_MASK \ > + (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0) > +#define GICC_CTLR_BYPASS_DISABLE_GRP1_MASK \ > + (GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1) > +#define GICC_NS_CTLR_BYPASS_DISABLE_GRP1_MASK \ > + GICC_CTLR_BYPASS_DISABLE_GRP0_MASK > + > +#define GICC_CTL_EOI (0x1 << 9) > > #define GICC_IA_IRQ 0x03ff > #define GICC_IA_CPU_MASK 0x1c00 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 08:41:02 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 08:41:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297112.1573245 (Exim 4.92) (envelope-from ) id 1wI0TP-0006iJ-ME; Wed, 29 Apr 2026 08:40:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297112.1573245; Wed, 29 Apr 2026 08:40:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI0TP-0006iC-JP; Wed, 29 Apr 2026 08:40:47 +0000 Received: by outflank-mailman (input) for mailman id 1297112; Wed, 29 Apr 2026 08:40:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI0TN-0006i4-E3 for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 08:40:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI0TL-001t9P-76 for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 10:40:44 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f1c40b-5cb7-0a2a0a5109dd-0a2a450584fa-12 for ; Wed, 29 Apr 2026 10:40:44 +0200 Received: from [209.85.218.47] (helo=mail-ej1-f47.google.com) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1c40c-aaa8-0a2a45050019-d155da2fb992-3 for ; Wed, 29 Apr 2026 10:40:44 +0200 Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-b936331786dso1613067566b.3 for ; Wed, 29 Apr 2026 01:40:44 -0700 (PDT) Received: from ?IPV6:2a00:12d0:af5d:ad01:5d3f:14e6:9bcb:5112? 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Possible options are 64MB, 128MB and > 256MB. Are such values inherited from the real q35 impleemntation? AFAICT the ACPI MCFG spec notes: "The size of the memory mapped configuration region is indicated by the start and end bus number fields in the Memory mapped Enhanced configuration space base address allocation structure as shown in Table 4-3. 0-255 is the range of allowed bus numbers supported for a given PCI Segment Group." So it's in principle possible to specify a MCFG that covers a single bus, and then it would have a size of 256 * 4K = 1M. Which avoids wasting 63M of MMIO space in the low MMIO hole that's already fairly tight on space. Is this limitation possibly inherited from the way the ECAM region position and size must be notified to the chipset? And further seeing the code below - I found the answer myself, it's because the chipset only supports negotiation those ECAM sizes. We could possibly expose a smaller region in MCFG, but doesn't seem like a good move. > As Xen is limited to the bus 0 currently, the lowest possible > setting is used (64MB), defined via PCI_MAX_MCFG_BUSES in > hvmloader/config.h. When multiple PCI buses support for Xen will be > implemented, PCI_MAX_MCFG_BUSES may be replaced by a calculation of the > number of buses according to PCI devices enumeration. > > The MMCONFIG entry is inserted into bars array in the same manner like > for any other BARs. In this case, the devfn field will point to MCH PCI > device and bar_reg will contain PCIEXBAR register offset. It will be > assigned a slot in the MMIO hole later in a very same way like for plain > PCI BARs, with respect to its size and alignment. At this point, the > actual base address and size of the ECAM space are passed to Xen using > the HVMOP_set_ecam_space hypercall. > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande > --- > tools/firmware/hvmloader/config.h | 4 +++ > tools/firmware/hvmloader/pci.c | 55 +++++++++++++++++++++++++++++ > tools/firmware/hvmloader/pci_regs.h | 7 ++++ > 3 files changed, 66 insertions(+) > > diff --git a/tools/firmware/hvmloader/config.h b/tools/firmware/hvmloader/config.h > index baaed91c7f..aa3158bca5 100644 > --- a/tools/firmware/hvmloader/config.h > +++ b/tools/firmware/hvmloader/config.h > @@ -55,6 +55,10 @@ extern uint32_t *cpu_to_apicid; > #define PCI_ISA_DEVFN 0x08 /* dev 1, fn 0 */ > #define PCI_ISA_IRQ_MASK 0x0c20U /* ISA IRQs 5,10,11 are PCI connected */ > #define PCI_ICH9_LPC_DEVFN 0xf8 /* dev 31, fn 0 */ > +#define PCI_MCH_DEVFN 0 /* bus 0, dev 0, func 0 */ > + > +/* possible values are: 64, 128, 256 */ > +#define PCI_MAX_MCFG_BUSES 64 > > #define ACPI_TIS_HDR_ADDRESS 0xFED40F00UL > > diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c > index 6e6720adae..54c23ffdd8 100644 > --- a/tools/firmware/hvmloader/pci.c > +++ b/tools/firmware/hvmloader/pci.c > @@ -413,6 +413,58 @@ void pci_setup(void) > pci_devfn_decode_type[devfn] |= PCI_COMMAND_MASTER; > } > > + /* > + * Calculate MMCONFIG area size and squeeze it into the bars array > + * for assigning a slot in the MMIO hole > + */ > + if ( is_running_on_q35 ) > + { > + /* disable PCIEXBAR decoding for now */ > + pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR, 0); > + pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR + 4, 0); > + > + switch ( PCI_MAX_MCFG_BUSES ) > + { > + case 64: > + bar_data = PCIEXBAR_64_BUSES | PCIEXBAR_ENABLE; > + bar_sz = MB(64); > + break; > + > + case 128: > + bar_data = PCIEXBAR_128_BUSES | PCIEXBAR_ENABLE; > + bar_sz = MB(128); > + break; > + > + case 256: > + bar_data = PCIEXBAR_256_BUSES | PCIEXBAR_ENABLE; > + bar_sz = MB(256); > + break; > + > + default: > + /* unsupported number of buses specified */ > + BUG(); > + } > + > + addr_mask = ~(bar_sz - 1); > + > + for ( i = 0; i < nr_bars; i++ ) > + if ( bars[i].bar_sz < bar_sz ) > + break; > + > + if ( i != nr_bars ) > + memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars)); > + > + bars[i].is_mem = 1; > + bars[i].devfn = PCI_MCH_DEVFN; > + bars[i].bar_reg = PCI_MCH_PCIEXBAR; > + bars[i].bar_sz = bar_sz; > + bars[i].addr_mask = addr_mask; > + bars[i].bar_data = bar_data; > + > + mmio_total += bar_sz; > + nr_bars++; > + } I think it might be best if the ECAM fake BAR is the first element in the bars array, so we ensure it's the first item to consume memory from the low MMIO hole. Not sure how that will work with the current sorting of the resources based on their size, but it's imperative for hvmloader to attempt to position ECAM ahead of the other device resources IMO. > + > if ( mmio_hole_size ) > { > uint64_t max_ram_below_4g = GB(4) - mmio_hole_size; > @@ -592,6 +644,9 @@ void pci_setup(void) > } > } > > + if ( bar_reg == PCI_MCH_PCIEXBAR ) > + hvm_set_ecam_space(base, bar_sz); As noted in a previous patch, it would be better if it's QEMU (as part of handling the PCI_MCH_PCIEXBAR writes) that notifies Xen of the ECAM window placement. Thanks, Roger. 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So there is no execution path to exit the loop and reach the > final that statement. > > This unreachable code violates MISRA C Rule 2.1 which states: "A project > shall not contain unreachable code". > > To fix that and potential compilers "control reaches end of non-void > function" warning, mark the code path as unreachable using macro > 'ASSERT_UNREACHABLE()'. > > Signed-off-by: Dmytro Prokopchuk > --- > Changes in v2: > - add ASSERT_UNREACHABLE() before the final return statement instead of removing it > Test CI pipeline: > https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2485661910 > Link to v1: > https://patchew.org/Xen/341811ced2943fb79d0235c27781c564c7bdaf02.1775749146.git.dmytro._5Fprokopchuk1@epam.com/ > --- > xen/common/hypfs.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/xen/common/hypfs.c b/xen/common/hypfs.c > index cdf4ee0171..02fb234568 100644 > --- a/xen/common/hypfs.c > +++ b/xen/common/hypfs.c > @@ -348,6 +348,7 @@ static struct hypfs_entry *hypfs_get_entry_rel(struct hypfs_entry_dir *dir, > dir = container_of(entry, struct hypfs_entry_dir, e); > } > > + ASSERT_UNREACHABLE(); > return ERR_PTR(-ENOENT); > } > No.  This is absurd. Not to mention that you are *definitely* not fixing the stated MISRA rule. ~Andrew From xen-devel-bounces@lists.xenproject.org Wed Apr 29 10:02:51 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 10:02:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297150.1573273 (Exim 4.92) (envelope-from ) id 1wI1kX-0002L4-VD; Wed, 29 Apr 2026 10:02:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297150.1573273; Wed, 29 Apr 2026 10:02:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI1kX-0002Kx-Pi; Wed, 29 Apr 2026 10:02:33 +0000 Received: by outflank-mailman (input) for mailman id 1297150; Wed, 29 Apr 2026 10:02:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI1k6-0002Iw-Bg for xen-devel@lists.xenproject.org; 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Date: Wed, 29 Apr 2026 12:01:54 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Thierry Escande Cc: xen-devel@lists.xenproject.org, Anthony PERARD , Juergen Gross , Alexey Gerasimenko Subject: Re: [PATCH 12/17] libxl: Q35 support (new option device_model_machine) Message-ID: References: <20260313163455.790692-1-thierry.escande@vates.tech> <20260313163455.790692-13-thierry.escande@vates.tech> Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260313163455.790692-13-thierry.escande@vates.tech> X-ClientProxiedBy: MR1P264CA0056.FRAP264.PROD.OUTLOOK.COM (2603:10a6:501:3e::20) To CH7PR03MB7860.namprd03.prod.outlook.com (2603:10b6:610:24e::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH7PR03MB7860:EE_|SA3PR03MB7320:EE_ X-MS-Office365-Filtering-Correlation-Id: c5b37e8b-6c5f-40a3-7864-08dea5d659d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|366016|18002099003|22082099003|56012099003; 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It has following possible values: > - "i440" - i440 emulation (default) > - "q35" - emulate a Q35 machine. By default, the storage interface is > AHCI. > > Note that omitting device_model_machine parameter means i440 system > by default, so the default behavior doesn't change for existing domain > config files. > > Setting device_model_machine to "q35" sends '-machine q35,accel=xen' > argument to QEMU. Unlike i440, there is no separated machine type to > enable/disable Xen platform device, it is controlled via a machine > property only. See 'libxl: Add xen-platform device for Q35 machine' > patch for a detailed description. Not an explicit objection to this patch, but I wonder what will we do for PVH when we start exposing PCI devices. We cannot provide a fully complete emulated Q35, but we do need to expose an MCFG for extended config space. The current naming "device_model_machine" won't work for PVH, as there's no device model there. But at the same time I wonder whether what we end up exposing to PVH would resemble any physical chipsets, or it's more likely going to be the minimum needed to make PVH guests happy to access the PCI config space (and hence we might end up emulating too little to match any chipset). Thanks, Roger. > > Signed-off-by: Alexey Gerasimenko > Signed-off-by: Thierry Escande > --- > tools/libs/light/libxl_dm.c | 16 ++++++++++------ > tools/libs/light/libxl_types.idl | 7 +++++++ > tools/xl/xl_parse.c | 14 ++++++++++++++ > 3 files changed, 31 insertions(+), 6 deletions(-) > > diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c > index 511ec76a65..36f2813cde 100644 > --- a/tools/libs/light/libxl_dm.c > +++ b/tools/libs/light/libxl_dm.c > @@ -1562,13 +1562,17 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, > flexarray_append(dm_args, b_info->extra_pv[i]); > break; > case LIBXL_DOMAIN_TYPE_HVM: > - if (!libxl_defbool_val(b_info->u.hvm.xen_platform_pci)) { > - /* Switching here to the machine "pc" which does not add > - * the xen-platform device instead of the default "xenfv" machine. > - */ > - machinearg = libxl__strdup(gc, "pc,accel=xen,suppress-vmdesc=on"); > + if (b_info->device_model_machine == LIBXL_DEVICE_MODEL_MACHINE_Q35) { > + machinearg = libxl__sprintf(gc, "q35,accel=xen"); > } else { > - machinearg = libxl__strdup(gc, "xenfv,suppress-vmdesc=on"); > + if (!libxl_defbool_val(b_info->u.hvm.xen_platform_pci)) { > + /* Switching here to the machine "pc" which does not add > + * the xen-platform device instead of the default "xenfv" machine. > + */ > + machinearg = libxl__strdup(gc, "pc,accel=xen,suppress-vmdesc=on"); > + } else { > + machinearg = libxl__strdup(gc, "xenfv,suppress-vmdesc=on"); > + } > } > if (b_info->u.hvm.mmio_hole_memkb) { > uint64_t max_ram_below_4g = (1ULL << 32) - > diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl > index d64a573ff3..f9cd881b66 100644 > --- a/tools/libs/light/libxl_types.idl > +++ b/tools/libs/light/libxl_types.idl > @@ -109,6 +109,12 @@ libxl_device_model_version = Enumeration("device_model_version", [ > (2, "QEMU_XEN"), # Upstream based qemu-xen device model > ]) > > +libxl_device_model_machine = Enumeration("device_model_machine", [ > + (0, "UNKNOWN"), > + (1, "I440"), > + (2, "Q35"), > + ]) > + > libxl_console_type = Enumeration("console_type", [ > (0, "UNKNOWN"), > (1, "SERIAL"), > @@ -613,6 +619,7 @@ libxl_domain_build_info = Struct("domain_build_info",[ > ("device_model_ssidref", uint32), > ("device_model_ssid_label", string), > ("device_model_user", string), > + ("device_model_machine", libxl_device_model_machine), This possibly wants to be inside the u.hvm sub-structure. I don't think we want to use it for PVH, not with this current naming at least. Thanks, Roger. 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> }; > > +/* > + * PCI Express Memory Mapped Configuration Description Table > + */ > +struct acpi_10_mcfg { > + struct acpi_header header; > + uint8_t reserved[8]; > + struct { > + uint64_t base_address; > + uint16_t pci_segment; > + uint8_t start_pci_bus_num; > + uint8_t end_pci_bus_num; > + uint32_t reserved; > + } entries[1]; > +}; > + > /* > * Table Signatures. > */ > @@ -457,6 +472,7 @@ struct acpi_20_slit { > #define ACPI_2_0_WAET_SIGNATURE ASCII32('W','A','E','T') > #define ACPI_2_0_SRAT_SIGNATURE ASCII32('S','R','A','T') > #define ACPI_2_0_SLIT_SIGNATURE ASCII32('S','L','I','T') > +#define ACPI_MCFG_SIGNATURE ASCII32('M','C','F','G') > > /* > * Table revision numbers. > @@ -472,6 +488,7 @@ struct acpi_20_slit { > #define ACPI_1_0_FADT_REVISION 0x01 > #define ACPI_2_0_SRAT_REVISION 0x01 > #define ACPI_2_0_SLIT_REVISION 0x01 > +#define ACPI_1_0_MCFG_REVISION 0x01 > > #pragma pack () > > diff --git a/tools/libacpi/build.c b/tools/libacpi/build.c > index 95188e217e..90080c76c4 100644 > --- a/tools/libacpi/build.c > +++ b/tools/libacpi/build.c > @@ -295,6 +295,37 @@ static struct acpi_20_slit *construct_slit(struct acpi_ctxt *ctxt, > return slit; > } > > +static struct acpi_10_mcfg *construct_mcfg(struct acpi_ctxt *ctxt, > + const struct acpi_config *config) > +{ > + struct acpi_10_mcfg *mcfg; > + > + /* Warning: this code expects that we have only one PCI segment */ Not only one PCI segment, but just one ECAM region. You could in theory have multiple ECAM regions within a single PCI segment. > + mcfg = ctxt->mem_ops.alloc(ctxt, sizeof(*mcfg), 16); > + if ( !mcfg ) > + return NULL; > + > + memset(mcfg, 0, sizeof(*mcfg)); > + mcfg->header.signature = ACPI_MCFG_SIGNATURE; > + mcfg->header.revision = ACPI_1_0_MCFG_REVISION; > + mcfg->header.creator_id = ACPI_CREATOR_ID; > + mcfg->header.creator_revision = ACPI_CREATOR_REVISION; > + mcfg->header.length = sizeof(*mcfg); > + mcfg->header.oem_revision = ACPI_OEM_REVISION; > + fixed_strcpy(mcfg->header.oem_id, ACPI_OEM_ID); > + fixed_strcpy(mcfg->header.oem_table_id, ACPI_OEM_TABLE_ID); > + > + mcfg->entries[0].base_address = config->mmconfig_addr; > + mcfg->entries[0].pci_segment = 0; > + mcfg->entries[0].start_pci_bus_num = 0; > + mcfg->entries[0].end_pci_bus_num = > + MCFG_SIZE_TO_NUM_BUSES(config->mmconfig_size) - 1; You might want to check that mmconfig_addr and mmconfig_size are set ahead of using them? Just in case some bogus toolstack/hvmloader sets ACPI_HAS_MCFG without correctly populating the fields? Thanks, Roger. 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0zd1ORJvinb8LkzN41ehLeP2JpfOoODk2KBc5BdrotYwFTRzMxg5lGPFawmnaKdURtPxGdX1VIrgSGBvgcL0nX86GxOvTsLBBuBKGIfC/X7jW9nXzp3pHvXls2iwkBgLJa18jEPJVSsuxYyNny8jD4xvedyvYBN1kDiHOSqczkqL+6hqVun267TA4zuX3FKyj2AkWKijSujudaC82R6o6/41EFb9+T3d3EwhHT2e7ZvbVhjUvHIs6qbi+NI5QmrsNqBog0og5ZO12e0ysJokOtmRmpQGiyyAojLY6xonfoYvZCXGrSgAnAouqZeAecY7Q1XbqVM1JAf96nVJCgff4ihRVLC2qsfA++xJdamSXMTc8LIbKMVNVzwlTfDXfWulbcqXXPxuLNyL7Givj6VnhIIlobDd2G4ggY0UHljSL2BlYif00BuFob4gz3V5xHww X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 11:00:48.7551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8bd5f8b-ac1a-42b1-a391-08dea5de9245 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C714.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9645 X-purgate-ID: tlsNG-c1860d/1777460457-38567DB1-70AEBAC8/0/0 X-purgate-type: clean X-purgate-size: 4465 Hi Oleksii, >=20 > diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c > index 9395b5af8745..a5554714cd7b 100644 > --- a/xen/arch/arm/kernel.c > +++ b/xen/arch/arm/kernel.c > @@ -101,8 +101,8 @@ static paddr_t __init kernel_zimage_place(struct kern= el_info *info) > paddr_t load_addr; >=20 > #ifdef CONFIG_HAS_DOMAIN_TYPE > - if ( (info->type =3D=3D DOMAIN_64BIT) && (info->zimage.start =3D=3D = 0) ) > - return mem->bank[0].start + info->zimage.text_offset; > + if ( (info->type =3D=3D DOMAIN_64BIT) && (info->image.start =3D=3D 0= ) ) > + return mem->bank[0].start + info->image.text_offset; > #endif >=20 > /* > @@ -111,19 +111,19 @@ static paddr_t __init kernel_zimage_place(struct ke= rnel_info *info) > * and above 32MiB. Load it as high as possible within these > * constraints, while also avoiding the DTB. > */ > - if ( info->zimage.start =3D=3D 0 ) > + if ( info->image.start =3D=3D 0 ) > { > paddr_t load_end; >=20 > load_end =3D mem->bank[0].start + mem->bank[0].size; > load_end =3D MIN(mem->bank[0].start + MB(128), load_end); >=20 > - load_addr =3D load_end - info->zimage.len; > + load_addr =3D load_end - info->image.len; > /* Align to 2MB */ > load_addr &=3D ~((2 << 20) - 1); > } > else > - load_addr =3D info->zimage.start; > + load_addr =3D info->image.start; >=20 > return load_addr; > } > @@ -131,8 +131,8 @@ static paddr_t __init kernel_zimage_place(struct kern= el_info *info) > static void __init kernel_zimage_load(struct kernel_info *info) > { > paddr_t load_addr =3D kernel_zimage_place(info); > - paddr_t paddr =3D info->zimage.kernel_addr; > - paddr_t len =3D info->zimage.len; > + paddr_t paddr =3D info->image.kernel_addr; > + paddr_t len =3D info->image.len; > void *kernel; > int rc; >=20 > @@ -215,7 +215,7 @@ int __init kernel_uimage_probe(struct kernel_info *in= fo, > return -EOPNOTSUPP; > } >=20 > - info->zimage.start =3D be32_to_cpu(uimage.load); > + info->image.start =3D be32_to_cpu(uimage.load); > info->entry =3D be32_to_cpu(uimage.ep); >=20 > /* > @@ -224,20 +224,20 @@ int __init kernel_uimage_probe(struct kernel_info *= info, > * independent image. That means Xen is free to load such an image at > * any valid address. > */ > - if ( info->zimage.start =3D=3D 0 ) > + if ( info->image.start =3D=3D 0 ) > printk(XENLOG_INFO > "No load address provided. Xen will decide where to load i= t.\n"); > else > printk(XENLOG_INFO > "Provided load address: %"PRIpaddr" and entry address: %"P= RIpaddr"\n", > - info->zimage.start, info->entry); > + info->image.start, info->entry); >=20 > /* > * If the image supports position independent execution, then user ca= nnot > * provide an entry point as Xen will load such an image at any appro= priate > * memory address. Thus, we need to return error. > */ > - if ( (info->zimage.start =3D=3D 0) && (info->entry !=3D 0) ) > + if ( (info->image.start =3D=3D 0) && (info->entry !=3D 0) ) > { > printk(XENLOG_ERR > "Entry point cannot be non zero for PIE image.\n"); > @@ -257,13 +257,13 @@ int __init kernel_uimage_probe(struct kernel_info *= info, > if ( rc ) > return rc; >=20 > - info->zimage.kernel_addr =3D mod->start; > - info->zimage.len =3D mod->size; > + info->image.kernel_addr =3D mod->start; > + info->image.len =3D mod->size; > } > else > { > - info->zimage.kernel_addr =3D addr + sizeof(uimage); > - info->zimage.len =3D len; > + info->image.kernel_addr =3D addr + sizeof(uimage); > + info->image.len =3D len; > } >=20 > info->load =3D kernel_zimage_load; > @@ -289,7 +289,7 @@ int __init kernel_uimage_probe(struct kernel_info *in= fo, > * Thus, Xen uses uimage.load attribute to determine the load address= and > * zimage.text_offset is ignored. Should we update the comment as well? Also in here: https://xenbits.xen.org/gitweb/?p=3Dxen.git;a=3Dblob;f=3Dxen/include/xen/fd= t-kernel.h;h=3D4d0467bb396a9cf317954fd511469e7f56d67844;hb=3Drefs/heads/sta= ging#l111 Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 29 11:10:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 11:10:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297182.1573309 (Exim 4.92) (envelope-from ) id 1wI2oH-0005EV-Fl; Wed, 29 Apr 2026 11:10:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297182.1573309; Wed, 29 Apr 2026 11:10:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI2oH-0005EO-C1; Wed, 29 Apr 2026 11:10:29 +0000 Received: by outflank-mailman (input) for mailman id 1297182; Wed, 29 Apr 2026 10:25:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI26t-0006Yd-2S for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 10:25:40 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI26q-008D0W-KH for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 12:25:37 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f1dc83-2eae-0a2a0a5409dd-0a2a45069404-38 for ; Wed, 29 Apr 2026 12:25:35 +0200 Received: from [95.215.58.178] (helo=out-178.mta1.migadu.com) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1dc9e-7371-0a2a45060019-5fd73ab27d0c-3 for ; Wed, 29 Apr 2026 12:25:34 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=key1 header.d=linux.dev header.i="@linux.dev" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding:In-Reply-To:References" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1777458333; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ubnPqyEuUH+bb9tWP9+TOUp+n6C5onOR58LCuBDEiw=; b=syDuJ2ebh9z2sjffREH58o0aT6Ajjew8W5I8ReEUtvp2EQkdghmYv8iT9JcU1iX87oMIbX D+xmbMoFNHgWVKDoL6XEe6kPFjJgAeA5FQrv1tK/6uUbSyjmFqItMdxDS/n3eJA5ihtrWC pDy1LXDxeyfrSgRVjezaD0bM6Fa+Scc= From: Usama Arif To: "Christophe Leroy (CS GROUP)" Cc: Usama Arif , Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [RFC PATCH v1 7/9] x86: Add unsafe_copy_from_user() Date: Wed, 29 Apr 2026 03:25:19 -0700 Message-ID: <20260429102520.1617327-1-usama.arif@linux.dev> In-Reply-To: <0ee46bb228d97163fbdc14f2a7c52b93d8bc34ce.1777306795.git.chleroy@kernel.org> References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT X-purgate-ID: tlsNG-16d1c6/1777458335-50158D75-F176F709/0/0 X-purgate-type: clean X-purgate-size: 2700 On Mon, 27 Apr 2026 19:13:48 +0200 "Christophe Leroy (CS GROUP)" wrote: > At the time being, x86 and arm64 are missing unsafe_copy_from_user(). > > Add it. > > Signed-off-by: Christophe Leroy (CS GROUP) > --- > arch/x86/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h > index 3a0dd3c2b233..10c458ffa399 100644 > --- a/arch/x86/include/asm/uaccess.h > +++ b/arch/x86/include/asm/uaccess.h > @@ -598,7 +598,7 @@ _label: \ > * We want the unsafe accessors to always be inlined and use > * the error labels - thus the macro games. > */ > -#define unsafe_copy_loop(dst, src, len, type, label) \ > +#define unsafe_put_loop(dst, src, len, type, label) \ > while (len >= sizeof(type)) { \ > unsafe_put_user(*(type *)(src),(type __user *)(dst),label); \ > dst += sizeof(type); \ > @@ -611,10 +611,29 @@ do { \ > char __user *__ucu_dst = (_dst); \ > const char *__ucu_src = (_src); \ > size_t __ucu_len = (_len); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > - unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > + unsafe_put_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > +} while (0) > + > +#define unsafe_get_loop(dst, src, len, type, label) \ > + while (len >= sizeof(type)) { \ > + unsafe_get_user(*(type __user *)(src),(type *)(dst),label); \ Hi, Just wanted to check if src and dst need to be swapped? Same for arm64 patch. > + dst += sizeof(type); \ > + src += sizeof(type); \ > + len -= sizeof(type); \ > + } > + > +#define unsafe_copy_from_user(_dst,_src,_len,label) \ > +do { \ > + char *__ucu_dst = (_dst); \ > + const char __user *__ucu_src = (_src); \ > + size_t __ucu_len = (_len); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u64, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u32, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u16, label); \ > + unsafe_get_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ > } while (0) > > #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT > -- > 2.49.0 > > From xen-devel-bounces@lists.xenproject.org Wed Apr 29 11:12:13 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 11:12:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297210.1573317 (Exim 4.92) (envelope-from ) id 1wI2pu-0005iA-PN; Wed, 29 Apr 2026 11:12:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297210.1573317; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /SoOinoy3PY2coPrSh2Ei1iWQHaoj1okdCr0YzYr52XZxokwK6VxwoGpYbhN7jV4V0VxEFlv4bzjzlsrRD4NbS+UovbVLaVnSUr4vl7iRJ+QX9dC5brbr5wzBsoU1XZAlh0UnHw9OJZDuhz5tYNwpdwnkJ/Jp2j+DiwlvXd4q4e/z2Zbc8aiwibuyi3Kl5bu50cjepX7r+eoB8LjNL06dYxG00cw44lVnDpIC3NR7Wvqr4qYZ6RP5aSLoqhfgfs4oVahcq02VuTUk/1Fxn4mXigaaSdvOEkPdMNzslQ9h1FJ+qEDSUGIkysnneoBYAF3vUN8ORnYqqXHGQOx6EL2YtmtmdfKFYEhwvI/07KbNwb93w8lF45vDETgz2GH27aMhx1F9o41RPbepywAlMaEEKb4n0e2FBad5S1vV+c6VFRlYVpX3sHKvco9QIU7cgFW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 11:12:01.4845 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63e39cf2-a4f0-4c12-3c99-08dea5e02345 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4217 X-purgate-ID: tlsNG-c1860d/1777461127-C0B64DB1-12EA0F7C/0/0 X-purgate-type: clean X-purgate-size: 4976 On 20-Apr-26 16:22, Luca Fancellu wrote: > From: Penny Zheng > > Implement setup_virt_paging for AArch64 MPU systems, taking care of > stage 2 address translation regime, IPA bits, supported VMID length > configuration and VTCR_EL2/VSTCR_EL2 register programming. > > Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, > related to the supported memory system architecture (PMSA/VMSA) > and check that when MPU is built, the underlying HW is compatible > with PMSA. By default MPU at EL2 and EL1 is required. > > Signed-off-by: Penny Zheng > Signed-off-by: Wei Chen > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye > Signed-off-by: Harry Ramsey > --- > v4: > - Fixed typo in the comments > - Fixed typo in the commit title and message > - moved p2m_vmid_allocator_init() after write of > VTCR_EL2 > - Fixed printf format specifier %d -> %u > v3: > - Refactor unused code to more relevant commits. > - Add P2M print information > - Formatting issues > - Update commit message > v2: > - Separate commit into multiple commits > --- > xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- > xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ > xen/arch/arm/include/asm/cpufeature.h | 13 +++- > xen/arch/arm/include/asm/processor.h | 8 +++ > 4 files changed, 101 insertions(+), 4 deletions(-) > > diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c > index b6d8b2777b58..a39a1fc38946 100644 > --- a/xen/arch/arm/arm64/mpu/p2m.c > +++ b/xen/arch/arm/arm64/mpu/p2m.c > @@ -2,11 +2,89 @@ > > #include > #include > +#include > #include > > void __init setup_virt_paging(void) > { > - BUG_ON("unimplemented"); > + register_t vtcr_el2 = READ_SYSREG(VTCR_EL2); > + register_t vstcr_el2 = READ_SYSREG(VSTCR_EL2); > + > + /* PA size */ > + const unsigned int pa_range_info[] = {32, 36, 40, 42, 44, 48, 52, 0, > + /* Invalid */}; > + > + /* > + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured > + * with IPA bits == PA bits, compare against PA size. > + */ > + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) > + p2m_ipa_bits = pa_range_info[system_cpuinfo.mm64.pa_range]; > + > + /* > + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identify the > + * memory system configurations supported. In Armv8-R AArch64, the > + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. > + */ > + if ( system_cpuinfo.mm64.msa != MM64_MSA_PMSA_SUPPORT ) > + goto fault; > + > + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b0010. */ > + if ( (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_PMSA_SUPPORT) && > + (system_cpuinfo.mm64.msa_frac != MM64_MSA_FRAC_VMSA_SUPPORT) ) > + goto fault; > + > + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ > + vtcr_el2 &= ~VTCR_MSA; > + > + /* > + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation output > + * address space to access the Secure PA space as Armv8-R only implements > + * secure state. > + */ > + vtcr_el2 &= ~VTCR_NSA; > + > + /* > + * cpuinfo sanitization makes sure we support 16-bits VMID only if all cores > + * are supporting it. > + * > + * Set the VS bit only if 16 bit VMID is supported. > + */ > + if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) > + { > + vtcr_el2 |= VTCR_VS; > + max_vmid = MAX_VMID_16_BIT; > + } > + else > + vtcr_el2 &= ~VTCR_VS; > + > + WRITE_SYSREG(vtcr_el2, VTCR_EL2); > + > + p2m_vmid_allocator_init(); > + > + /* > + * VSTCR_EL2.SA defines secure stage 2 translation output address space. > + * To make sure that all stage 2 translations for the Secure PA space access > + * the Secure PA space, we keep SA bit as 0. > + * > + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS > + * configuration is checked against stage 1 NS configuration in EL1&0 > + * translation regime for the given address, and generates a fault if they > + * are different, we set SC bit 1. > + */ > + vstcr_el2 &= ~VSTCR_EL2_SA; > + vstcr_el2 |= VSTCR_EL2_SC; > + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); > + > + printk("P2M: %u-bit IPA with %u-bit PA and %u-bit VMID\n", > + p2m_ipa_bits, > + pa_range_info[system_cpuinfo.mm64.pa_range], > + ( MAX_VMID == MAX_VMID_16_BIT ) ? 16 : 8); NIT: No need for spaces between (). Reviewed-by: Michal Orzel ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 29 11:27:04 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 11:27:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297223.1573329 (Exim 4.92) (envelope-from ) id 1wI343-0007ju-WA; Wed, 29 Apr 2026 11:26:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297223.1573329; Wed, 29 Apr 2026 11:26:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI343-0007jn-TZ; Wed, 29 Apr 2026 11:26:47 +0000 Received: by outflank-mailman (input) for mailman id 1297223; Wed, 29 Apr 2026 11:26:45 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI341-0007jh-RX for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 11:26:45 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI341-008Q7g-7Q for xen-devel@lists.xenproject.org; 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dkim=pass header.s=k20201202 header.d=kernel.org header.i="@kernel.org" header.h="Date:From:To:Cc:Subject:References:In-Reply-To" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777462002; bh=HgV0q/+gZ9n2giWTxhUD6P3yQ6wEmY66ZwCWQHhgQ2g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ejvHWE1zJ0tb1KwQu/gVCMj0KcNhlMqCOjLI4kQmWC01EPIO4HFDTFQg5PpNyMx2F 7OMWgwbyfp16yd5ZKGLwfDDMuBlWK8CK9qcSIqUHZRxyhnWE4iAN+OK+xmr5WBtr4T BgqmCB7r/rsFvwFu/mT2z67QkDE/mDzOf7GDi68KHsQjYM3r7svy7TXqJDW5kWsfNa xYHmkznhflijvwvOUJkH6AcM42ZHWo8kZp7k26fwbFC82N/jHC8/F/rL8GlM8z6Ksh UMOZ5KVH94exo80oAIrmoHKOK/k/qke5mU8V2uOXUW3Mlxuf7JynBO/Edq8wMcfI5M twwrBSWDcoLLw== Date: Wed, 29 Apr 2026 12:26:30 +0100 From: Will Deacon To: "Christophe Leroy (CS GROUP)" Cc: Yury Norov , Andrew Morton , Linus Torvalds , David Laight , Thomas Gleixner , linux-alpha@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-um@lists.infradead.org, dmaengine@vger.kernel.org, linux-efi@vger.kernel.org, linux-fsi@lists.ozlabs.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-wpan@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, linux-spi@vger.kernel.org, linux-media@vger.kernel.org, linux-staging@lists.linux.dev, linux-serial@vger.kernel.org, linux-usb@vger.kernel.org, xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org, ocfs2-devel@lists.linux.dev, bpf@vger.kernel.org, kasan-dev@googlegroups.com, linux-mm@kvack.org, linux-x25@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-sound@vger.kernel.org, sound-open-firmware@alsa-project.org, linux-csky@vger.kernel.org, linux-hexagon@vger.kernel.org, loongarch@lists.linux.dev, linux-m68k@lists.linux-m68k.org, linux-openrisc@vger.kernel.org, linux-parisc@vger.kernel.org, linux-sh@vger.kernel.org, linux-arch@vger.kernel.org, catalin.marinas@arm.com Subject: Re: [RFC PATCH v1 8/9] arm64: Add unsafe_copy_from_user() Message-ID: References: <5b09e58a84c9edcfe5724db5cd57e45d96a96bfa.1777306795.git.chleroy@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5b09e58a84c9edcfe5724db5cd57e45d96a96bfa.1777306795.git.chleroy@kernel.org> X-purgate-ID: tlsNG-bad1c0/1777462005-416B0A53-0E96A66A/0/0 X-purgate-type: clean X-purgate-size: 521 [+Catalin] On Mon, Apr 27, 2026 at 07:13:49PM +0200, Christophe Leroy (CS GROUP) wrote: > At the time being, x86 and arm64 are missing unsafe_copy_from_user(). > > Add it. > > Signed-off-by: Christophe Leroy (CS GROUP) > --- > arch/arm64/include/asm/uaccess.h | 29 ++++++++++++++++++++++++----- > 1 file changed, 24 insertions(+), 5 deletions(-) Why? And please cc the arm64 maintainers on arm64 patches next time. You've managed to cc most of the world apart from us. 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pr=C Message-ID: <6ba6db51-3ff0-4ecd-9f86-03735e7dfc05@amd.com> Date: Wed, 29 Apr 2026 13:53:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains To: Luca Fancellu , CC: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <20260420142224.1802911-1-luca.fancellu@arm.com> <20260420142224.1802911-3-luca.fancellu@arm.com> From: "Orzel, Michal" Content-Language: en-US In-Reply-To: <20260420142224.1802911-3-luca.fancellu@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: michal.orzel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000148:EE_|BL3PR12MB9050:EE_ X-MS-Office365-Filtering-Correlation-Id: a842c483-bee4-4a72-e10b-08dea5e5dfe3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XhdL2p0dgJFrw/Z5Df2XMdYJqDTsAElBEUeVUYydB2FdUre4l9lhJkOp6f8nx/qQKSl/9TwjkfA8/5/Zf90P6XZ7EAqsrVamWdfgorFIWLyF0Huloy14HglD2Rd/INWblUCNcdctUWdEVG/Me1orlhiWwGHJiHtnnKWhPEAqxKnSu+o1FP3U/JyhkhRDJyLp+nKTiMcF/ASIiQsBUmnzX9fsJdeV4Vze5oOTVQ3CgrNBCAqFy8tFd/M9NPXsHsMzHbQpWCYHVbD6ghZmj/E20KOJwQPvJEpgFVXwib9L7ZD2wr0zaAcH9bM1TLsBX+3jigG1wsYp8YzIDC4OBmPiVvPxkGlSj2UzD0/zPpZJApkvI0Q7t+vhoYW6xztx+x+992wgxikV0K7cXYIM8zMDmQVA0ZY+HC6VwVfizj1iS9E+kRU91SNfkONSrzt7QO40 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 11:53:05.4991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a842c483-bee4-4a72-e10b-08dea5e5dfe3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000148.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB9050 X-purgate-ID: tlsNG-c201ff/1777463593-E1FDA443-60848554/0/0 X-purgate-type: clean X-purgate-size: 15877 On 20-Apr-26 16:22, Luca Fancellu wrote: > From: Harry Ramsey > > Add a new device tree property `v8r_el1_msa` to select the MSA (memory > system architecture) at EL1 for Armv8-R architecture: MPU or MMU, the > former is the default if the property is not passed. > > The check and setting of this new input parameter for the guest > configuration is performed in arch_domain_create() instead of the more > usual arch_sanitise_domain_config() because the former has access to the > Xen internal guest creation flags which are required to ensure PMSA can > work (domain requires static allocation and direct mapping). > > The property is valid only when used on MPU systems and will result in > a panic on MMU ones. > > Bumped XEN_DOMCTL_INTERFACE_VERSION because of the new domctl input > parameter. > > Signed-off-by: Harry Ramsey > Signed-off-by: Luca Fancellu > --- > v4: > - Rework the patch to have the v8r_el1_msa input parameter more > enclosed in the Armv8-A (mmu)/Armv8-R (mpu) space. > v3: > - Improve commit message and device tree property description > - Remove macro protection > - Remove unused function is_mpu_domain > - Code formatting > --- > docs/misc/arm/device-tree/booting.txt | 14 ++++ > xen/arch/arm/dom0less-build.c | 3 + > xen/arch/arm/domain.c | 4 ++ > xen/arch/arm/include/asm/domain.h | 4 ++ > xen/arch/arm/include/asm/domain_build.h | 8 +++ > xen/arch/arm/include/asm/mmu/domain-build.h | 46 +++++++++++++ > xen/arch/arm/include/asm/mpu.h | 5 ++ > xen/arch/arm/include/asm/mpu/domain-build.h | 27 ++++++++ > xen/arch/arm/mpu/Makefile | 1 + > xen/arch/arm/mpu/arm32/mm.c | 5 ++ > xen/arch/arm/mpu/arm64/mm.c | 5 ++ > xen/arch/arm/mpu/domain-build.c | 76 +++++++++++++++++++++ > xen/include/public/arch-arm.h | 7 ++ > xen/include/public/domctl.h | 4 +- > 14 files changed, 207 insertions(+), 2 deletions(-) > create mode 100644 xen/arch/arm/include/asm/mmu/domain-build.h > create mode 100644 xen/arch/arm/include/asm/mpu/domain-build.h > create mode 100644 xen/arch/arm/mpu/domain-build.c > > diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt > index 977b4286082f..c3f484a3b01a 100644 > --- a/docs/misc/arm/device-tree/booting.txt > +++ b/docs/misc/arm/device-tree/booting.txt > @@ -322,6 +322,20 @@ with the following properties: > Should be used together with scmi-smc-passthrough Xen command line > option. > > +- v8r_el1_msa > + > + A string property specifying whether, on Armv8-R systems, a domain > + should use PMSAv8 (MPU) at EL1 or VMSAv8 (MMU) at EL1. Instead of repeating at EL1 you could move it next to "on Armv8R systems" > + > + - "mmu" > + Enables VMSAv8 at EL1. This requires hardware support and is only > + optionally available on AArch64. Maybe it's due to the combination of words but it does not immediately tell that it's not present on AArch32. I would add: "Not supported on AArch32". > + > + - "mpu" > + Enables PMSAv8 at EL1. This is the default behaviour when the property is > + not passed. This configuration requires static allocation (xen,static-mem) > + and direct mapping (direct-map). > + > Under the "xen,domain" compatible node, one or more sub-nodes are present > for the DomU kernel and ramdisk. > > diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c > index 4181c105389a..6f0256f9d825 100644 > --- a/xen/arch/arm/dom0less-build.c > +++ b/xen/arch/arm/dom0less-build.c > @@ -24,6 +24,7 @@ > #include > #include > #include > +#include > #include > > #ifdef CONFIG_VGICV2 > @@ -322,6 +323,8 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node, > if ( domu_dt_sci_parse(node, d_cfg) ) > panic("Error getting SCI configuration\n"); > > + arch_dt_v8r_el1_msa_parse(node, d_cfg); "arch" prefix should be used by functions called from the common code that have arch-specific implementation. This is not the case for functions you're introducing here, so please drop this prefix. Also, I would continue using the SCI approach e.g. call it domu_dt_msa_parse() and decide to panic at the call site rather than making this decision in the function itself. > + > if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) > { > int vpl011_virq = GUEST_VPL011_SPI; > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index 26380a807cad..dfa7ace1141b 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -725,6 +726,9 @@ int arch_domain_create(struct domain *d, > if ( (rc = sci_domain_init(d, config)) != 0 ) > goto fail; > > + if ( (rc = arch_set_v8r_el1_msa(d, config, flags)) != 0 ) > + goto fail; > + > return 0; > > fail: > diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h > index ffe5d0d9f0a6..4a3fb825962b 100644 > --- a/xen/arch/arm/include/asm/domain.h > +++ b/xen/arch/arm/include/asm/domain.h > @@ -128,6 +128,10 @@ struct arch_domain > #endif > > struct resume_info resume_ctx; > + > +#ifdef CONFIG_MPU > + uint8_t v8r_el1_msa; > +#endif > } __cacheline_aligned; > > struct arch_vcpu > diff --git a/xen/arch/arm/include/asm/domain_build.h b/xen/arch/arm/include/asm/domain_build.h > index 6674dac5e2f8..921d6f98f4f4 100644 > --- a/xen/arch/arm/include/asm/domain_build.h > +++ b/xen/arch/arm/include/asm/domain_build.h > @@ -4,6 +4,14 @@ > #include > #include > > +#if defined(CONFIG_MMU) > +#include > +#elif defined(CONFIG_MPU) > +#include > +#else > +# error "Unknown memory management layout" I don't think that this error msg is correct for domain build. > +#endif > + > typedef __be32 gic_interrupt_t[3]; > int make_psci_node(void *fdt); > void evtchn_allocate(struct domain *d); > diff --git a/xen/arch/arm/include/asm/mmu/domain-build.h b/xen/arch/arm/include/asm/mmu/domain-build.h > new file mode 100644 > index 000000000000..3e0d9a6a2a08 > --- /dev/null > +++ b/xen/arch/arm/include/asm/mmu/domain-build.h > @@ -0,0 +1,46 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __ARM_MMU_DOMAIN_BUILD_H__ > +#define __ARM_MMU_DOMAIN_BUILD_H__ > + > +#include > +#include > +#include > +#include > +#include > + > +static inline > +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, > + struct xen_domctl_createdomain *d_cfg) > +{ > + const char *v8r_el1_msa; > + > + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) > + panic("'v8r_el1_msa' property found, but CONFIG_MPU not selected\n"); > +} > + > +static inline > +int arch_set_v8r_el1_msa(struct domain *d, > + const struct xen_domctl_createdomain *config, > + unsigned int flags) > +{ > + if ( config->arch.v8r_el1_msa ) > + { > + dprintk(XENLOG_INFO, > + "arch.v8r_el1_msa set, but CONFIG_MPU not selected\n"); > + return -EINVAL; > + } > + > + return 0; > +} > + > +#endif /* __ARM_MMU_DOMAIN_BUILD_H__ */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h > index 72fa5b00b861..8a8c01086206 100644 > --- a/xen/arch/arm/include/asm/mpu.h > +++ b/xen/arch/arm/include/asm/mpu.h > @@ -27,6 +27,11 @@ > > #ifndef __ASSEMBLER__ > > +/* > + * Utility function to determine if an Armv8-R processor supports VMSA. > + */ NIT: No need for multi-line comment for a single sentence that can fit in one line. > +bool has_v8r_vmsa_support(void); > + > /* > * Set base address of MPU protection region. > * > diff --git a/xen/arch/arm/include/asm/mpu/domain-build.h b/xen/arch/arm/include/asm/mpu/domain-build.h > new file mode 100644 > index 000000000000..463cd85b5b7e > --- /dev/null > +++ b/xen/arch/arm/include/asm/mpu/domain-build.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __ARM_MPU_DOMAIN_BUILD_H__ > +#define __ARM_MPU_DOMAIN_BUILD_H__ > + > +#include > +#include > +#include > +#include > + > +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, > + struct xen_domctl_createdomain *d_cfg); > + > +int arch_set_v8r_el1_msa(struct domain *d, > + const struct xen_domctl_createdomain *config, > + unsigned int flags); > + > +#endif /* __ARM_MPU_DOMAIN_BUILD_H__ */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile > index 3327fadd5d0e..e3997e41b81b 100644 > --- a/xen/arch/arm/mpu/Makefile > +++ b/xen/arch/arm/mpu/Makefile > @@ -1,5 +1,6 @@ > obj-$(CONFIG_ARM_32) += arm32/ > obj-$(CONFIG_ARM_64) += arm64/ > +obj-y += domain-build.o > obj-y += domain-page.o > obj-y += mm.o > obj-y += p2m.o > diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c > index a4673c351141..5eaeb3400e6c 100644 > --- a/xen/arch/arm/mpu/arm32/mm.c > +++ b/xen/arch/arm/mpu/arm32/mm.c > @@ -38,6 +38,11 @@ > break; \ > } > > +bool has_v8r_vmsa_support(void) > +{ > + return false; > +} > + > /* > * Armv8-R supports direct access and indirect access to the MPU regions through > * registers: > diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c > index ed643cad4073..b07e729a7d05 100644 > --- a/xen/arch/arm/mpu/arm64/mm.c > +++ b/xen/arch/arm/mpu/arm64/mm.c > @@ -32,6 +32,11 @@ > break; \ > } > > +bool has_v8r_vmsa_support(void) > +{ > + return system_cpuinfo.mm64.msa_frac == MM64_MSA_FRAC_VMSA_SUPPORT; > +} > + > /* > * Armv8-R supports direct access and indirect access to the MPU regions through > * registers: > diff --git a/xen/arch/arm/mpu/domain-build.c b/xen/arch/arm/mpu/domain-build.c > new file mode 100644 > index 000000000000..1bdd0ffedebb > --- /dev/null > +++ b/xen/arch/arm/mpu/domain-build.c > @@ -0,0 +1,76 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +void __init arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, > + struct xen_domctl_createdomain *d_cfg) > +{ > + const char *v8r_el1_msa; > + > + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; > + > + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) > + { > + if ( !strcmp(v8r_el1_msa, "mmu") ) > + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA; > + else if ( !strcmp(v8r_el1_msa, "mpu") ) > + d_cfg->arch.v8r_el1_msa = XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA; > + else > + panic("Invalid device tree option for v8r_el1_msa\n"); > + } > +} > + > +int arch_set_v8r_el1_msa(struct domain *d, > + const struct xen_domctl_createdomain *config, > + unsigned int flags) > +{ > + switch ( config->arch.v8r_el1_msa ) > + { > + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE: > + fallthrough; > + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA: > + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) > + { > + dprintk(XENLOG_INFO, > + "PMSA is not valid for domain without static allocation and direct map (v8r_el1_msa)\n"); > + return -EINVAL; > + } > + break; > + > + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA: > + if ( !has_v8r_vmsa_support() ) > + { > + dprintk(XENLOG_INFO, > + "Platform does not support VMSA at EL1 (v8r_el1_msa)\n"); > + return -EINVAL; > + } > + break; > + > + default: > + dprintk(XENLOG_INFO, "Unsupported arch.v8r_el1_msa value (%u)\n", > + config->arch.v8r_el1_msa); > + return -EINVAL; > + } Why do we even need this split. It seems like all the above checks could be done in arch_dt_v8r_el1_msa_parse given that it is called after static-mem,direct-map are set. This would simplify this file and we would not even need to introduce new domain-build split for one function. > + > + d->arch.v8r_el1_msa = config->arch.v8r_el1_msa; > + > + return 0; > +} > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h > index cd563cf70684..7d6f87e8b2b1 100644 > --- a/xen/include/public/arch-arm.h > +++ b/xen/include/public/arch-arm.h > @@ -330,6 +330,10 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); > #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 > #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 > > +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE 0 > +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 > +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 > + > struct xen_arch_domainconfig { > /* IN/OUT */ > uint8_t gic_version; > @@ -355,6 +359,9 @@ struct xen_arch_domainconfig { > uint32_t clock_frequency; > /* IN */ > uint8_t arm_sci_type; > + /* IN */ > + uint8_t v8r_el1_msa; > + uint16_t pad; Before this change there were 3B of implicit padding. Now you added 1B of data and 2B of explicit padding. The struct size is the same, so why bumping the interface version? I don't see it necessary here. Also, why explicit padding? With explicit padding I do think you need to now check that it's 0. > }; > #endif /* __XEN__ || __XEN_TOOLS__ */ > > diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h > index 8f6708c0a7cd..23124547f347 100644 > --- a/xen/include/public/domctl.h > +++ b/xen/include/public/domctl.h > @@ -30,9 +30,9 @@ > * fields) don't require a change of the version. > * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! > * > - * Last version bump: Xen 4.19 > + * Last version bump: Xen 4.22 > */ > -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 > +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 > > /* > * NB. xen_domctl.domain is an IN/OUT parameter for this operation. ~Michal From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:06:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:06:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297274.1573357 (Exim 4.92) (envelope-from ) id 1wI3gZ-0006ej-MJ; Wed, 29 Apr 2026 12:06:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297274.1573357; Wed, 29 Apr 2026 12:06:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gZ-0006ec-J9; Wed, 29 Apr 2026 12:06:35 +0000 Received: by outflank-mailman (input) for mailman id 1297274; Wed, 29 Apr 2026 12:06:34 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gY-0006bB-6F for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 12:06:34 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI3gX-00CWNe-Iq for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 14:06:33 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f1f442-e002-0a2a0a5209dd-0a2a45098cd6-36 for ; Wed, 29 Apr 2026 14:06:33 +0200 Received: from [195.135.223.131] (helo=smtp-out2.suse.de) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1f449-2497-0a2a45090019-c387df83c7bc-3 for ; Wed, 29 Apr 2026 14:06:33 +0200 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id E27615BCC2; Wed, 29 Apr 2026 12:06:32 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id BE5C4593B0; Wed, 29 Apr 2026 12:06:32 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id jV1oLUj08Wl6VQAAD6G6ig (envelope-from ); Wed, 29 Apr 2026 12:06:32 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: smtp-out2.suse.de; none From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Anthony PERARD , Julien Grall , Jason Andryuk Subject: [PATCH v2 2/4] tools/xenstored: add support for "all domains" node permission Date: Wed, 29 Apr 2026 14:06:17 +0200 Message-ID: <20260429120619.1013440-3-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260429120619.1013440-1-jgross@suse.com> References: <20260429120619.1013440-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: E27615BCC2 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-purgate-ID: tlsNG-bad1c0/1777464393-492B2A53-7D71699E/0/0 X-purgate-type: clean X-purgate-size: 5943 Add support for using DOMID_ANY in node permissions to indicate that all domains are allowed to access the node. Add a new feature bit for indicating the support of DOMID_ANY. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- docs/man/xl.cfg.5.pod.in | 4 ++++ tools/xenstored/core.c | 19 ++++++++++++++----- tools/xenstored/domain.c | 16 ++++++++++++++-- tools/xenstored/domain.h | 3 ++- xen/include/public/io/xs_wire.h | 2 ++ 5 files changed, 36 insertions(+), 8 deletions(-) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 2f77016ecf..d34951edb9 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -746,6 +746,10 @@ Xenstore supports to set watches with a limited depth (depth 0 matches only the watched node, depth 1 matches the node and its direct children, etc.). +=item B<0x00000008> + +Xenstore supports the B node access permission. + =back The features supported by the running Xenstore instance can be retrieved diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 6d82111e29..7dbcd5daad 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -882,6 +882,16 @@ static int write_node(struct connection *conn, struct node *node, return ret; } +/* Check one node permission to match a connection. */ +static bool perm_allows_conn(const struct connection *conn, + const struct xs_permissions *p) +{ + if (p->id == conn->id || (conn->target && p->id == conn->target->id)) + return true; + + return p->id == DOMID_ANY; +} + unsigned int perm_for_conn(struct connection *conn, const struct node_perms *perms) { @@ -889,14 +899,13 @@ unsigned int perm_for_conn(struct connection *conn, unsigned int mask = XS_PERM_READ|XS_PERM_WRITE|XS_PERM_OWNER; /* Owners and tools get it all... */ - if (!domain_is_unprivileged(conn) || perms->p[0].id == conn->id - || (conn->target && perms->p[0].id == conn->target->id)) + if (!domain_is_unprivileged(conn) || + perm_allows_conn(conn, perms->p)) return (XS_PERM_READ|XS_PERM_WRITE|XS_PERM_OWNER) & mask; for (i = 1; i < perms->num; i++) if (!(perms->p[i].perms & XS_PERM_IGNORE) && - (perms->p[i].id == conn->id || - (conn->target && perms->p[i].id == conn->target->id))) + perm_allows_conn(conn, perms->p + i)) return perms->p[i].perms & mask; return perms->p[0].perms & mask; @@ -1832,7 +1841,7 @@ static int do_set_perms(const void *ctx, struct connection *conn, if (!xenstore_strings_to_perms(perms.p, perms.num, permstr)) return errno; - if (domain_alloc_permrefs(&perms)) + if (domain_alloc_permrefs(conn, &perms)) return ENOMEM; if (perms.p[0].perms & XS_PERM_IGNORE) return ENOENT; diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index 00875d6b5c..7074abd197 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -44,7 +44,8 @@ #endif #define XENSTORE_FEATURES (XENSTORE_SERVER_FEATURE_ERROR | \ - XENSTORE_SERVER_FEATURE_WATCHDEPTH) + XENSTORE_SERVER_FEATURE_WATCHDEPTH | \ + XENSTORE_SERVER_FEATURE_DOMID_ANY) static xenmanage_handle *xm_handle; xengnttab_handle **xgt_handle; @@ -1754,8 +1755,12 @@ static bool chk_domain_generation(unsigned int domid, uint64_t gen) * Allocate all missing struct domain referenced by a permission set. * Any permission entries for not existing domains will be marked to be * ignored. + * A DOMID_ANY entry will be marked to be ignored, if the writing + * domain doesn't have the XENSTORE_SERVER_FEATURE_DOMID_ANY enabled. Note + * that Xen tools will never set DOMID_ANY for a guest owned node. */ -int domain_alloc_permrefs(struct node_perms *perms) +int domain_alloc_permrefs(const struct connection *conn, + struct node_perms *perms) { unsigned int i, domid; struct domain *d; @@ -1763,6 +1768,12 @@ int domain_alloc_permrefs(struct node_perms *perms) for (i = 0; i < perms->num; i++) { domid = perms->p[i].id; + if (domid == DOMID_ANY) { + if (!(conn->domain->features & + XENSTORE_SERVER_FEATURE_DOMID_ANY)) + perms->p[i].perms |= XS_PERM_IGNORE; + continue; + } d = find_domain_struct(domid); if (!d) { if (xenmanage_get_domain_info(xm_handle, domid, NULL, @@ -1788,6 +1799,7 @@ int domain_adjust_node_perms(struct node *node) for (i = 1; i < node->hdr.num_perms; i++) { if ((perms[i].perms & XS_PERM_IGNORE) || + perms[i].id == DOMID_ANY || chk_domain_generation(perms[i].id, node->hdr.generation)) continue; diff --git a/tools/xenstored/domain.h b/tools/xenstored/domain.h index b1cfb5cd82..7dad4849a0 100644 --- a/tools/xenstored/domain.h +++ b/tools/xenstored/domain.h @@ -116,7 +116,8 @@ const char *get_implicit_path(const struct connection *conn); */ int domain_adjust_node_perms(struct node *node); -int domain_alloc_permrefs(struct node_perms *perms); +int domain_alloc_permrefs(const struct connection *conn, + struct node_perms *perms); /* Quota manipulation */ int domain_nbentry_inc(struct connection *conn, unsigned int domid); diff --git a/xen/include/public/io/xs_wire.h b/xen/include/public/io/xs_wire.h index 2e763bc877..d6533a8452 100644 --- a/xen/include/public/io/xs_wire.h +++ b/xen/include/public/io/xs_wire.h @@ -126,6 +126,8 @@ struct xenstore_domain_interface { #define XENSTORE_SERVER_FEATURE_ERROR 2 /* The XS_WATCH command can be used with a parameter */ #define XENSTORE_SERVER_FEATURE_WATCHDEPTH 4 +/* The capability to use DOMID_ANY for node permissions */ +#define XENSTORE_SERVER_FEATURE_DOMID_ANY 8 /* Valid values for the connection field */ #define XENSTORE_CONNECTED 0 /* the steady-state */ -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:06:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:06:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297275.1573365 (Exim 4.92) (envelope-from ) id 1wI3gb-0006sd-Sm; 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none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1777464387; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Fvrcx0L64Kf/ax26AArSQHlhXePuAaFw8eCivbX6h2o=; b=doVE1FUrkPKeHwe1H2jkYGx4rnIy0eeUbZYQ3rsmgB2jCy5clURQBb4p8G5b2OFJ93GHxW 1+8olA1VIi/lGydAQAmwvhEejrON41IMYFXXczIKTo+rhMAy1UwY3InhjUc+40okaw6CLE G9n+/SeTgrXuoOtVf/KcJtvpExmQljo= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Denis Mukhin , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Juergen Gross , Jason Andryuk Subject: [PATCH v2 1/4] xen/public: introduce DOMID_ANY Date: Wed, 29 Apr 2026 14:06:16 +0200 Message-ID: <20260429120619.1013440-2-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260429120619.1013440-1-jgross@suse.com> References: <20260429120619.1013440-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Score: -6.80 X-Spam-Level: X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[99.99%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,amd.com:email,suse.com:mid,suse.com:email,ford.com:email]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-purgate-ID: tlsNG-ebf023/1777464396-2B3673FF-AB0E0F40/0/0 X-purgate-type: clean X-purgate-size: 1320 From: Denis Mukhin Add DOMID_ANY to xen/include/public/xen.h meant to be a wildcard for domids. Signed-off-by: Denis Mukhin Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- This is based on Denis Mukhin's patch "xen/domain: introduce DOMID_ANY". As my series is another use case for DOMID_ANY and it is a backport candidate, I've split out the definition of DOMID_ANY from Denis' patch in order to make progress for my series. V2: update comment (Jason Andryuk) --- xen/include/public/xen.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index b12fd10e63..2149b8dd38 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -608,6 +608,13 @@ DEFINE_XEN_GUEST_HANDLE(mmuext_op_t); /* DOMID_INVALID is used to identify pages with unknown owner. */ #define DOMID_INVALID xen_mk_uint(0x7FF4) +/* + * DOMID_ANY is used to signal no specific domain ID requested. + * Handler should pick a valid ID, or handle it as a wildcard value + * depending on the context. + */ +#define DOMID_ANY xen_mk_uint(0x7FF5) + /* Idle domain. */ #define DOMID_IDLE xen_mk_uint(0x7FFF) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:06:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:06:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297276.1573375 (Exim 4.92) (envelope-from ) id 1wI3gf-000785-58; Wed, 29 Apr 2026 12:06:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297276.1573375; Wed, 29 Apr 2026 12:06:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gf-00077t-1L; Wed, 29 Apr 2026 12:06:41 +0000 Received: by outflank-mailman (input) for mailman id 1297276; Wed, 29 Apr 2026 12:06:40 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gd-00076k-VM for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 12:06:39 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI3gd-00CWOJ-BO for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 14:06:39 +0200 Received: from [10.42.69.6] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f1f440-bab6-0a2a0a5309dd-0a2a450689ac-40 for ; Wed, 29 Apr 2026 14:06:39 +0200 Received: from [195.135.223.131] (helo=smtp-out2.suse.de) by tlsNG-16d1c6.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1f44f-7371-0a2a45060019-c387df83d28e-3 for ; Wed, 29 Apr 2026 14:06:39 +0200 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 6EEB45BD15; Wed, 29 Apr 2026 12:06:38 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 46C11593B0; Wed, 29 Apr 2026 12:06:38 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id B3krEE708Wm5VQAAD6G6ig (envelope-from ); Wed, 29 Apr 2026 12:06:38 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: smtp-out2.suse.de; none From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD , Jason Andryuk Subject: [PATCH v2 3/4] tools/xenstored: allow @releaseDomain watch for all domains Date: Wed, 29 Apr 2026 14:06:18 +0200 Message-ID: <20260429120619.1013440-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260429120619.1013440-1-jgross@suse.com> References: <20260429120619.1013440-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 6EEB45BD15 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-purgate-ID: tlsNG-16d1c6/1777464399-50566D75-6BEF1B58/0/0 X-purgate-type: clean X-purgate-size: 2688 Currently the @releaseDomain watch is allowed for dom0 only. This is problematic for guests which want to give other domains access to Xenstore entries, as they have no simple way to tell when such a domain is stopped. Allow @releaseDomain to be usable by all domains as the default. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- tools/xenstored/core.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c index 7dbcd5daad..d6d462b7bc 100644 --- a/tools/xenstored/core.c +++ b/tools/xenstored/core.c @@ -2279,19 +2279,19 @@ struct connection *get_connection_by_id(unsigned int conn_id) } /* We create initial nodes manually. */ -static void manual_node(const char *name, const char *child) +static void manual_node_perms(const char *name, const char *child, + struct xs_permissions *perms, + unsigned int n_perms) { struct node *node; - struct xs_permissions perms = { .id = priv_domid, - .perms = XS_PERM_NONE }; node = talloc_zero(NULL, struct node); if (!node) barf_perror("Could not allocate initial node %s", name); node->name = name; - node->perms = &perms; - node->hdr.num_perms = 1; + node->perms = perms; + node->hdr.num_perms = n_perms; node->children = (char *)child; if (child) node->hdr.childlen = strlen(child) + 1; @@ -2301,6 +2301,14 @@ static void manual_node(const char *name, const char *child) talloc_free(node); } +static void manual_node(const char *name, const char *child) +{ + struct xs_permissions perms = { .id = priv_domid, + .perms = XS_PERM_NONE }; + + manual_node_perms(name, child, &perms, 1); +} + static unsigned int hash_from_key_fn(const void *k) { const char *str = k; @@ -2320,6 +2328,11 @@ static int keys_equal_fn(const void *key1, const void *key2) void setup_structure(bool live_update) { + struct xs_permissions perms[] = { + { .id = priv_domid, .perms = XS_PERM_NONE }, + { .id = DOMID_ANY, .perms = XS_PERM_READ }, + }; + nodes = create_hashtable(NULL, "nodes", hash_from_key_fn, keys_equal_fn, HASHTABLE_FREE_KEY | HASHTABLE_FREE_VALUE); if (!nodes) @@ -2331,7 +2344,8 @@ void setup_structure(bool live_update) manual_node("/", "tool"); manual_node("/tool", "xenstored"); manual_node("/tool/xenstored", NULL); - manual_node("@releaseDomain", NULL); + manual_node_perms("@releaseDomain", NULL, + perms, ARRAY_SIZE(perms)); manual_node("@introduceDomain", NULL); domain_nbentry_fix(priv_domid, 5); } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:06:54 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:06:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297273.1573349 (Exim 4.92) (envelope-from ) id 1wI3gX-0006Rk-Gm; Wed, 29 Apr 2026 12:06:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297273.1573349; Wed, 29 Apr 2026 12:06:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gX-0006Rd-Ci; Wed, 29 Apr 2026 12:06:33 +0000 Received: by outflank-mailman (input) for mailman id 1297273; Wed, 29 Apr 2026 12:06:31 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gV-0006RX-DV for xen-devel@lists.xenproject.org; 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Wed, 29 Apr 2026 12:06:21 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 1sI2Iz308Wk6VQAAD6G6ig (envelope-from ); Wed, 29 Apr 2026 12:06:21 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding"; dkim=pass header.s=susede1 header.d=suse.com header.i="@suse.com" header.h="From:Date:Message-ID:To:Cc:MIME-Version:Content-Transfer-Encoding" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1777464386; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=wbjluDVZotZt60L9F+RyvmJUG+lseQlcgdHyfdTEa3g=; b=VeGvPzIkKRE75NI8Ur7ooVJ618bEDtu+MaEvc7uEL/8HaDzpNXVKFAh3NnI9a4vgn2ctUX k730HN0WxLwrWUlsHwcShi3J++vB9aNyUk6XzPyn5NQr1Af9hQwqZcNVAqOoovrgx88ZUH RvhHXxFJFOX116yDBLEQ5NndFsS5gYs= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1777464381; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=wbjluDVZotZt60L9F+RyvmJUG+lseQlcgdHyfdTEa3g=; b=BLEcjP1eFCX1oX1o9NAHfJsOF4pLKWp+J148YMsmJ95qQv3fJ84J7Y6Vv/oIUnGRjukUQ0 z+q5a3WMRUEbw5IbxYaPhkR0V+F+FpqVdmRSd1JX9z1GEYTgIIP1v9B9VcZoSFIXVA8FF3 sRQ+zQLe7X8seeVWSuViYE85JnGdoxk= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v2 0/4] tools/xenstore: fix issue related to XSA-417 Date: Wed, 29 Apr 2026 14:06:15 +0200 Message-ID: <20260429120619.1013440-1-jgross@suse.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCPT_COUNT_SEVEN(0.00)[9]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: X-purgate-ID: tlsNG-33051d/1777464390-A197D938-9D91CD56/0/0 X-purgate-type: clean X-purgate-size: 2909 There is one corner case of XSA-417 which wasn't handled completely with the patches back then. The XSA-417 fixes tried to solve the problem, that a new domU would inherit access permissions to access Xenstore entries with that domid listed in the access rights. In order not to make it easy for a domU to query existence of a domid, adding permission for a non-existing domain is not rejected by Xenstore. The XSA-417 patches solved that problem by adding a flag to a permission entry referencing a not existing domain, indicating that the permission should not be effective for Xenstore. One corner case was not handled: Consider guest 1 and guest 2 running. Guest 1 adds guest 2 to be able to access a Xenstore entry. Now guest 2 is removed from the system and a new guest 3 with the same domid as guest 2 had is being created. When guest 3 would try now to access the Xenstore entry, it would fail, as Xenstore would see that the Xenstore entry is older than guest 3. But if guest 1 is modifying the permissions of the Xenstore entry again, e.g. by adding another domain, the permission entry for guest 2 would lose its "special flag", resulting in guest 3 now really gaining access to the Xenstore entry. This series is fixing this problem by the following means: - In order to allow guests to know that a Xenstore entry permission might have gone stale, allow unprivileged guests to receive @releaseDomain watch events. This doesn't open a security hole, as the only knowledge which can by gathered from that change is that a domain is gone, not that a domain with a specific domid is existing. - When a domain is removed, remove all permissions relating to this domain from all Xenstore entries. Note that this issue was discussed by the Xen security team and we decided not to issue an XSA, as there are no known use cases where one unprivileged guest would grant access to its Xenstore nodes to more than one other unprivileged guests. We decided to delay this patch series until the watch depth feature has been committed, as with that feature available it is now possible for a guest to handle the death of a specific domain in a sane way. Changes in V2: - some minor comments addressed Denis Mukhin (1): xen/public: introduce DOMID_ANY Juergen Gross (3): tools/xenstored: add support for "all domains" node permission tools/xenstored: allow @releaseDomain watch for all domains tools/xenstored: remove permissions related to dead domain docs/man/xl.cfg.5.pod.in | 4 ++ tools/xenstored/core.c | 45 ++++++++++++++----- tools/xenstored/domain.c | 78 +++++++++++++++++++++------------ tools/xenstored/domain.h | 3 +- xen/include/public/io/xs_wire.h | 2 + xen/include/public/xen.h | 7 +++ 6 files changed, 100 insertions(+), 39 deletions(-) -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:07:05 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:07:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297290.1573384 (Exim 4.92) (envelope-from ) id 1wI3gt-0007qX-F2; Wed, 29 Apr 2026 12:06:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297290.1573384; Wed, 29 Apr 2026 12:06:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gt-0007qN-Bm; Wed, 29 Apr 2026 12:06:55 +0000 Received: by outflank-mailman (input) for mailman id 1297290; Wed, 29 Apr 2026 12:06:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI3gr-0007jq-Ey for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 12:06:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI3gq-00CWTK-R9 for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 14:06:52 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f1f44e-e002-0a2a0a5209dd-0a2a450789ca-48 for ; Wed, 29 Apr 2026 14:06:52 +0200 Received: from [195.135.223.130] (helo=smtp-out1.suse.de) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f1f45c-229c-0a2a45070019-c387df82dc42-3 for ; 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bh=neoM0rxwlNWkYjpN6UzzXgAR6Uz/BSePabcIeLnOQEY=; b=ZSpWGLqasrDc/j1ptizTy2a1M7sNMVRN5jKpUou289QW+BCKG9frcmynpM4OURxI3sdoIP Nj8UCc7h+hImONRLCNvmNexl7f1LRFpzZdB8XuEGIvDB3sSM9N1Sbnj5PlHFcQQphdZd4A 83Nk5f5igr8ymuTC2pqRmrDgGzF+rtQ= From: Juergen Gross To: xen-devel@lists.xenproject.org Cc: Juergen Gross , Julien Grall , Anthony PERARD , Jason Andryuk Subject: [PATCH v2 4/4] tools/xenstored: remove permissions related to dead domain Date: Wed, 29 Apr 2026 14:06:19 +0200 Message-ID: <20260429120619.1013440-5-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260429120619.1013440-1-jgross@suse.com> References: <20260429120619.1013440-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email,amd.com:email]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_FIVE(0.00)[5]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: X-purgate-ID: tlsNG-ef75cf/1777464412-14E57C48-7515360F/0/0 X-purgate-type: clean X-purgate-size: 3796 Wit unprivileged domains now capable to use the @releaseDomain watch, there is no reason not to remove any node permissions which relate to a domain which has been removed. This resolves a complex scenario where a new domain could inherit the permissions of an old one with the same domid. Signed-off-by: Juergen Gross Reviewed-by: Jason Andryuk --- V2: use priv_domid instead of literal 0 in message (Jason Andryuk) --- tools/xenstored/domain.c | 62 ++++++++++++++++++++++++---------------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c index 7074abd197..2db452144d 100644 --- a/tools/xenstored/domain.c +++ b/tools/xenstored/domain.c @@ -569,24 +569,10 @@ static int domain_tree_remove_sub(const void *ctx, struct connection *conn, struct node *node, void *arg) { struct domain *domain = arg; - int ret = WALK_TREE_OK; - - if (node->perms[0].id != domain->domid) - return WALK_TREE_OK; + bool node_changed = false; + unsigned int i; - if (keep_orphans) { - domain_nbentry_dec(NULL, domain->domid); - node->perms[0].id = priv_domid; - node->acc.memory = 0; - domain_nbentry_inc(NULL, priv_domid); - if (write_node_raw(NULL, node->name, node, NODE_MODIFY, true)) { - /* That's unfortunate. We only can try to continue. */ - syslog(LOG_ERR, - "error when moving orphaned node %s to dom0\n", - node->name); - } else - trace("orphaned node %s moved to dom0\n", node->name); - } else { + if (node->perms[0].id == domain->domid && !keep_orphans) { if (rm_node(NULL, ctx, node->name)) { /* That's unfortunate. We only can try to continue. */ syslog(LOG_ERR, @@ -596,10 +582,39 @@ static int domain_tree_remove_sub(const void *ctx, struct connection *conn, trace("orphaned node %s deleted\n", node->name); /* Skip children in all cases in order to avoid more errors. */ - ret = WALK_TREE_SKIP_CHILDREN; + return WALK_TREE_SKIP_CHILDREN; } - return domain->acc_val[ACC_NODES] ? ret : WALK_TREE_SUCCESS_STOP; + if (node->perms[0].id == domain->domid) { + domain_nbentry_dec(NULL, domain->domid); + node->perms[0].id = priv_domid; + node->acc.memory = 0; + domain_nbentry_inc(NULL, priv_domid); + trace("moving orphaned node %s to dom%d\n", node->name, + priv_domid); + node_changed = true; + } + + for (i = 1; i < node->hdr.num_perms; i++) { + if (node->perms[i].id != domain->domid) + continue; + memmove(node->perms + i, node->perms + i + 1, + sizeof(*node->perms) * (node->hdr.num_perms - i - 1)); + node->hdr.num_perms--; + i--; + node_changed = true; + } + + if (node_changed) { + if (write_node_raw(NULL, node->name, node, NODE_MODIFY, true)) { + /* That's unfortunate. We only can try to continue. */ + syslog(LOG_ERR, + "error when writing modified node %s\n", + node->name); + } + } + + return WALK_TREE_OK; } static void domain_tree_remove(struct domain *domain) @@ -607,12 +622,9 @@ static void domain_tree_remove(struct domain *domain) int ret; struct walk_funcs walkfuncs = { .enter = domain_tree_remove_sub }; - if (domain->acc_val[ACC_NODES]) { - ret = walk_node_tree(domain, NULL, "/", &walkfuncs, domain); - if (ret == WALK_TREE_ERROR_STOP) - syslog(LOG_ERR, - "error when looking for orphaned nodes\n"); - } + ret = walk_node_tree(domain, NULL, "/", &walkfuncs, domain); + if (ret == WALK_TREE_ERROR_STOP) + syslog(LOG_ERR, "error when looking for orphaned nodes\n"); walk_node_tree(domain, NULL, "@releaseDomain", &walkfuncs, domain); walk_node_tree(domain, NULL, "@introduceDomain", &walkfuncs, domain); -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 12:33:24 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 12:33:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297324.1573393 (Exim 4.92) (envelope-from ) id 1wI46R-0004wt-Bf; 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> + uint64_t mmconfig_addr; > + uint32_t mmconfig_size; > > if ( !lowmem_reserved_base ) > lowmem_reserved_base = 0xA0000; > @@ -260,6 +262,15 @@ int build_e820_table(struct e820entry *e820, > nr++; > } > > + /* mark MMCONFIG area */ > + if ( ! hvm_get_ecam_space(&mmconfig_addr, &mmconfig_size) ) ^ extra space However, having to query the hypervisor for something that has been set by hvmloader itself seems very inefficient. Just store the values in global variables so they can be consumed from here? Same for the usage below. Thanks, Roger. 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Thanks, Roger. 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If > the IOREQ_TYPE_COPY request is within the ECAM address space configured > by hvmloader, the ioreq type is set to XEN_DMOP_IO_RANGE_PCI and the > sbdf decoded from the accessed address. > > Signed-off-by: Thierry Escande > --- > xen/arch/x86/hvm/ioreq.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c > index a5fa97e149..022fe05222 100644 > --- a/xen/arch/x86/hvm/ioreq.c > +++ b/xen/arch/x86/hvm/ioreq.c > @@ -268,6 +268,8 @@ bool arch_ioreq_server_get_type_addr(const struct domain *d, > uint64_t *addr) > { > unsigned int cf8 = d->arch.hvm.pci_cf8; > + unsigned long mmio_start = (p->type == IOREQ_TYPE_COPY) ? > + ioreq_mmio_first_byte(p) : 0; > > if ( p->type != IOREQ_TYPE_COPY && p->type != IOREQ_TYPE_PIO ) > return false; > @@ -298,6 +300,19 @@ bool arch_ioreq_server_get_type_addr(const struct domain *d, > *addr |= CF8_ADDR_HI(cf8); > } > } > + else if ( p->type == IOREQ_TYPE_COPY && > + (mmio_start >= d->arch.ecam_addr && > + mmio_start < (d->arch.ecam_addr + d->arch.ecam_size)) ) > + { > + pci_sbdf_t sbdf; > + unsigned int reg = mmio_start & ~PAGE_MASK; > + > + sbdf.bdf = (((mmio_start - d->arch.ecam_addr) & 0x0ffff000) >> 12); > + sbdf.seg = 0; > + > + *type = XEN_DMOP_IO_RANGE_PCI; > + *addr = ((uint64_t)sbdf.sbdf << 32) | reg; The trapping & decoding here should better re-use the logic in the vpci_mmcfg* handlers in x86/hvm/io.c. You might want to gate the call to register_mmio_handler() to the domain having vPCI, so that otherwise it will be handled by the IOREQ catch-all. It's a bit hacky, but we already know that vPCI and IOREQs don't play well, and it needs solving properly. Again I don't want to force you having to do that just to get q35 merged. But we should at least aim to not duplicate the data in the domain structures. Thanks, Roger. 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[2.7.24.55]) (Authenticated sender: anthony.perard) by mail2.vates.fr (Postfix) with ESMTPSA id 8D7108076B; Wed, 29 Apr 2026 14:48:15 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=1YMqeE/bZBZtigC8s9LSwBudS50zC7eOueOUyPah3A4=; h=from:subject:date:message-id:to:cc:mime-version:content-type:feedback-id; b=KS4kSNS+Lnpgj2C7lHJUVCSP/p0/5iYc8zaXEpll2QT5Xf/kulW1AUsRjpn3e+xtaCfLmJh8Z jfU+LeplQUb2AYCuQ5+3hn9JBS7qmh+J47ZluHPqMXrScVemfRTwhQQsbChtmyuD9vDuveHARLJ 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X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.1e6.370dca10e82feae9.19dd9486d4a.9123d17733a26d6f=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777466895694 X-purgate-ID: tlsNG-33051d/1777466905-28F72938-4133C150/0/0 X-purgate-type: clean X-purgate-size: 3376 ---=Part.1e6.370dca10e82feae9.19dd9486d4a.9123d17733a26d6f=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Without --platform, it seems recent versions of docker ignores the platform of the image when pushing, and it's pushed as the platform of the runner=2E If we happen to build an arm64 image on x86, with recent version of docker, the image will be push as if it was an x86 image, then `docker run --platform=3Dlinux/arm64 =2E=2E=2E` fails=2E Even if it would work without --platform, gitlab-runner will not be able to use the image=2E To go back to the previous behavior, we will extract --platform from the dockerfiles, and use it on the command line=2E --platform=3D is needed on both docker-build and docker-push=2E The first one so that the image is tagged with the right platform, and the second one so that we can push a "generic" image without been tagged to a particular platform=2E --platform on docker-push allow to easly use the container on any arch, without having to use --platform on docker-pull or docker-run=2E `docker push --platform` seem to have been added to 1=2E46, according to the [doc], and doesn't exist on Podman=2E So we need to check that we are using `docker` and that the API version is new enough=2E [doc] https://docs=2Edocker=2Ecom/reference/cli/docker/image/push/ Also, introduce the $img variable, to make the lines a bit shorter=2E Signed-off-by: Anthony PERARD --- automation/build/Makefile | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/automation/build/Makefile b/automation/build/Makefile index fedf7524dacd=2E=2Ed578cd347615 100644 --- a/automation/build/Makefile +++ b/automation/build/Makefile @@ -15,10 +15,28 @@ help: =20 include yocto/yocto=2Einc =20 +# Find out if we are running Podman, if not is likely docker=2E +is-docker =3D $(if $(filter Podman,$(shell $(DOCKER_CMD) version)),,1) + +# Find out the docker API version is at least 1=2E46=2E We exploit `sort = -V` to +# compare the versions at it can sort by version=2E +docker-api-version =3D $(shell $(DOCKER_CMD) version -f '{{=2EClient=2EAP= IVersion}}') +docker-min-version =3D $(firstword $(shell printf "1=2E46\n$(docker-api-v= ersion)" | sort -V)) +docker-have-push-platform =3D $(if $(filter 1=2E46,$(docker-min-version))= ,1) + +# check if we can use `X push --platform`=2E +# `podman push` doesn't support --platform=2E +# `docker` only have it on recent version=2E +builder-have-push-platform =3D $(and $(is-docker),$(docker-have-push-plat= form)) + %: %=2Edockerfile ## Builds containers - $(DOCKER_CMD) build --pull -t $(REGISTRY)/$(@D):$(@F) -f $< $( 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rhhojhgvtghtrdhorhhgpdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrh drkhgvrhhnvghlrdhorhhg X-ME-Proxy: Feedback-ID: i001e48d0:Fastmail From: Val Packett To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?q?Eugenio=20P=C3=A9rez?= Cc: Val Packett , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev Subject: [RFC PATCH] virtio-mmio: add xenbus probing Date: Wed, 29 Apr 2026 10:52:17 -0300 Message-ID: <20260429141339.74472-1-val@invisiblethingslab.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-33051d/1777472053-A1F7A938-E2F0AAA1/0/0 X-purgate-type: clean X-purgate-size: 7798 The experimental virtio-mmio support for Xen was initially developed on aarch64, so device trees were used to configure the mmio devices, with arbitrary vGIC interrupts used by the hypervisor. On x86_64 however, the only reasonable way to interrupt the guest is over Xen event channels, which can only be acquired by children of xenbus, the virtual bus driven by Xen's configuration database, XenStore. It is also a more convenient and "Xen-ish" way to provision devices. Implement a xenbus client for virtio-mmio which negotiates an event channel and provides it as a platform IRQ to the virtio-mmio driver. Signed-off-by: Val Packett --- Hi, I've been working on porting virtio-mmio support from Arm to x86_64, with the goal of running vhost-user-gpu to power Wayland/GPU integration for Qubes OS. (I'm aware of various proposals for alternative virtio transports but virtio-mmio seems to be the only one that *is* upstream already and just Works..) Setting up virtio-mmio through xenbus, initially motivated just by event channels being the only real way to get interrupts working on HVM, turned out to generally be quite pleasant and nice :) I'd like to get some early feedback for this patch, particularly the general stuff: * is this whole thing acceptable in general? * should it be extracted into a different file? * (from the Xen side) any input on the xenstore keys, what goes where? * anything else to keep in mind? It does seem simple enough, so hopefully this can be done? The corresponding userspace-side WIP is available at: https://github.com/QubesOS/xen-vhost-frontend And the required DMOP for firing the evtchn events will be sent to xen-devel shortly as well. Thanks, ~val --- drivers/virtio/Kconfig | 7 ++ drivers/virtio/virtio_mmio.c | 177 ++++++++++++++++++++++++++++++++++- 2 files changed, 183 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index ce5bc0d9ea28..56bc2b10526b 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -171,6 +171,13 @@ config VIRTIO_MMIO_CMDLINE_DEVICES If unsure, say 'N'. +config VIRTIO_MMIO_XENBUS + bool "Memory mapped virtio devices parameter parsing" + depends on VIRTIO_MMIO && XEN + select XEN_XENBUS_FRONTEND + help + Allow virtio-mmio devices instantiation for Xen guests via xenbus. + config VIRTIO_DMA_SHARED_BUFFER tristate depends on DMA_SHARED_BUFFER diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 595c2274fbb5..32295284bdbf 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -70,6 +70,11 @@ #include #include +#ifdef CONFIG_VIRTIO_MMIO_XENBUS +#include +#include +#include +#endif /* The alignment to use between consumer and producer parts of vring. @@ -810,13 +815,183 @@ static struct platform_driver virtio_mmio_driver = { }, }; +#ifdef CONFIG_VIRTIO_MMIO_XENBUS +struct virtio_mmio_xen_info { + struct resource resources[2]; + unsigned int evtchn; + struct platform_device *pdev; +}; + +static int virtio_mmio_xen_probe(struct xenbus_device *dev, + const struct xenbus_device_id *id) +{ + int err; + long long base, size; + char *mem; + struct virtio_mmio_xen_info *info; + struct xenbus_transaction xbt; + + /* TODO: allocate an unused address here and pass it to the host instead */ + err = xenbus_scanf(XBT_NIL, dev->otherend, "base", "0x%llx", + &base); + if (err < 0) { + xenbus_dev_fatal(dev, err, "reading base"); + return -EINVAL; + } + + mem = xenbus_read(XBT_NIL, dev->otherend, "size", NULL); + if (XENBUS_IS_ERR_READ(mem)) + return PTR_ERR(mem); + size = memparse(mem, NULL); + kfree(mem); + + info = kzalloc_obj(*info); + if (!info) { + xenbus_dev_fatal(dev, -ENOMEM, "allocating info structure"); + return -ENOMEM; + } + + info->resources[0].flags = IORESOURCE_MEM; + info->resources[0].start = base; + info->resources[0].end = base + size - 1; + + err = xenbus_alloc_evtchn(dev, &info->evtchn); + if (err) { + xenbus_dev_fatal(dev, err, "xenbus_alloc_evtchn"); + goto error_info; + } + + err = bind_evtchn_to_irq(info->evtchn); + if (err <= 0) { + xenbus_dev_fatal(dev, err, "bind_evtchn_to_irq"); + goto error_evtchan; + } + + info->resources[1].flags = IORESOURCE_IRQ; + info->resources[1].start = info->resources[1].end = err; + +again: + err = xenbus_transaction_start(&xbt); + if (err) { + xenbus_dev_fatal(dev, err, "starting transaction"); + goto error_irq; + } + + err = xenbus_printf(xbt, dev->nodename, "event-channel", "%u", + info->evtchn); + if (err) { + xenbus_transaction_end(xbt, 1); + xenbus_dev_fatal(dev, err, "%s", "writing event-channel"); + goto error_irq; + } + + err = xenbus_transaction_end(xbt, 0); + if (err) { + if (err == -EAGAIN) + goto again; + xenbus_dev_fatal(dev, err, "completing transaction"); + goto error_irq; + } + + dev_set_drvdata(&dev->dev, info); + xenbus_switch_state(dev, XenbusStateInitialised); + return 0; + +error_irq: + unbind_from_irqhandler(info->resources[1].start, info); +error_evtchan: + xenbus_free_evtchn(dev, info->evtchn); +error_info: + kfree(info); + + return err; +} + +static void virtio_mmio_xen_backend_changed(struct xenbus_device *dev, + enum xenbus_state backend_state) +{ + struct virtio_mmio_xen_info *info = dev_get_drvdata(&dev->dev); + + switch (backend_state) { + case XenbusStateInitialising: + case XenbusStateInitWait: + case XenbusStateInitialised: + case XenbusStateReconfiguring: + case XenbusStateReconfigured: + case XenbusStateUnknown: + break; + + case XenbusStateConnected: + if (dev->state != XenbusStateInitialised) { + dev_warn(&dev->dev, "state %d on connect", dev->state); + break; + } + info->pdev = platform_device_register_resndata(&dev->dev, + "virtio-mmio", PLATFORM_DEVID_AUTO, + info->resources, ARRAY_SIZE(info->resources), NULL, 0); + xenbus_switch_state(dev, XenbusStateConnected); + break; + + case XenbusStateClosed: + if (dev->state == XenbusStateClosed) + break; + fallthrough; /* Missed the backend's Closing state. */ + case XenbusStateClosing: + platform_device_unregister(info->pdev); + xenbus_switch_state(dev, XenbusStateClosed); + break; + + default: + xenbus_dev_fatal(dev, -EINVAL, "saw state %d at frontend", + backend_state); + break; + } +} + +static void virtio_mmio_xen_remove(struct xenbus_device *dev) +{ + struct virtio_mmio_xen_info *info = dev_get_drvdata(&dev->dev); + + kfree(info); + dev_set_drvdata(&dev->dev, NULL); +} + +static const struct xenbus_device_id virtio_mmio_xen_ids[] = { + { "virtio" }, + { "" }, +}; + +static struct xenbus_driver virtio_mmio_xen_driver = { + .ids = virtio_mmio_xen_ids, + .probe = virtio_mmio_xen_probe, + .otherend_changed = virtio_mmio_xen_backend_changed, + .remove = virtio_mmio_xen_remove, +}; +#endif + static int __init virtio_mmio_init(void) { - return platform_driver_register(&virtio_mmio_driver); + int ret; + + ret = platform_driver_register(&virtio_mmio_driver); + if (ret) + return ret; + +#ifdef CONFIG_VIRTIO_MMIO_XENBUS + if (xen_domain()) + ret = xenbus_register_frontend(&virtio_mmio_xen_driver); +#endif + + return ret; } static void __exit virtio_mmio_exit(void) { +#ifdef CONFIG_VIRTIO_MMIO_XENBUS + if (xen_domain()) + xenbus_unregister_driver(&virtio_mmio_xen_driver); +#endif + platform_driver_unregister(&virtio_mmio_driver); vm_unregister_cmdline_devices(); } -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Wed Apr 29 14:34:12 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 14:34:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297429.1573455 (Exim 4.92) (envelope-from ) id 1wI5zA-0008Pg-8z; Wed, 29 Apr 2026 14:33:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297429.1573455; Wed, 29 Apr 2026 14:33:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI5zA-0008PZ-6E; Wed, 29 Apr 2026 14:33:56 +0000 Received: by outflank-mailman (input) for mailman id 1297429; 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Wed, 29 Apr 2026 14:33:50 +0000 Received: from l14 (lfbn-lyo-1-414-55.w2-7.abo.wanadoo.fr [2.7.24.55]) (Authenticated sender: anthony.perard) by mail2.vates.fr (Postfix) with ESMTPSA id 9CEF480B82; Wed, 29 Apr 2026 16:33:45 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=6Qpd3RUXpDK/WhkTTfIF7opv94F9vdzKhd0m8iunY8A=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=PW4JqyYdsFlXyh8WHq6+5PeWW6GxnbngUzHRrNPfcxeWtlgcyCIwwwQv3iK+FEew6aPu896i4 Ls2M7dpdtR0dJWCNVnctOdr9h6UaOCc8JkzVzg+ABIO2eieUYNXAyClkjsVsbpGARfWRmlp9IUK P9sguhnXeiYhhkyGc8epK9aiza3dNKlwthn11G/GtJby+pQdCjlQ2L5NLPlhOcNDGFrIYXVFJ9X 4B0AHmGNtDxOXChVrL7OJH4Rw66ZfQT06smQZTRyzkBTgGZVeybazJ4gogTdvDr/2PhLr6OA3Y1 CP8ldMWYcNN9R8twv/pC2OE0YdUCd10+4aVaEuwENtvA== X-Zone-Loop: 795a9e550284621f493acc2b30d84560a4b4629f629b x-campaign-type: default x-transaction-id: c4e82e4f-89c1-452e-97d0-36364208eb2a x-swg-uid: 01-57d22118-7835-4d11-afdc-5b02a6c55fa5 X-Mailer: Sweego Message-ID: <1777473230.8631fc262581453bbf619ec5b2062170.19dd9a915bc000f373@vates.tech> x-swg-bid: 1777473230.8631fc262581453bbf619ec5b2062170.19dd9a915bc000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Wed, 29 Apr 2026 16:33:45 +0200 From: Anthony PERARD To: Mykyta Poturai Cc: Jan Beulich , Juergen Gross , "xen-devel@lists.xenproject.org" Subject: Re: [PATCH v7 5/6] tools: Allow building xen-hptool without CONFIG_MIGRATE References: <73db845e6617130966a565cdca6274db4cb46428.1774871881.git.mykyta_poturai@epam.com> <58cfab3b-7cf2-4e38-9968-1248e665f985@suse.com> <28900826-5a96-4bf0-8d5b-11fd1be8386a@suse.com> <96829f0b-faac-4100-8c30-c93ac9459600@epam.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <96829f0b-faac-4100-8c30-c93ac9459600@epam.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.231.4aedd74cac3a3672.19dd9a9040f.4e3261a16981b028=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777473225743 X-purgate-ID: tlsNG-d62444/1777473234-BC016FF4-4D7C287D/0/0 X-purgate-type: clean X-purgate-size: 2805 ---=Part.231.4aedd74cac3a3672.19dd9a9040f.4e3261a16981b028=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Apr 16, 2026 at 08:22:32AM +0000, Mykyta Poturai wrote: > On 4/16/26 09:49, Jan Beulich wrote: > > On 15=2E04=2E2026 16:51, Mykyta Poturai wrote: > >> On 3/30/26 15:32, Jan Beulich wrote: > >>> This looks wrong to me=2E There are x86-specifics in that file, whic= h shouldn't > >>> be built on Arm=2E And the name of the file also doesn't indicate an= y relation > >>> to CPU management=2E > >> > >> xen-hptool requires xg_offline_page as it has both CPU and memory > >> hotplug commands=2E Without building xg_offline_page it fails with > >> > >> xen-hptool: symbol lookup error: xen-hptool: undefined symbol: > >> xc_mark_page_offline, version libxenguest_4=2E22=2E0 > >> > >> when trying to do memory ops=2E > >> > >> Is it an acceptable behavior? > >=20 > > I don't think so, no=2E The tool wouldn't, aiui, load at all then if b= uilt with > > "bindnow" enabled=2E > >=20 > >> If so I guess we can build xg_offline page only on x86=2E > >=20 > > We still need to, imo=2E But the tool still needs to be usable no matt= er how > > specifically it is built=2E It should avoid referencing xg_offline_pag= e=2Ec > > functions when built for non-x86=2E >=20 > As I understand, the usage of arch-specific compile time checks is=20 > heavily discouraged in tools=2E So I don=E2=80=99t think it would be app= roved by=20 > tools maintainers=2E Do we really need to omit this file if memory ops a= re=20 > already getting blocked by Xen on Arm anyway? So you are trying to modify a library and introduced untested functionality just to be able to build a different tool? I don't think that a good idea especially in this case where it's more than just glue code between a binary and xen=2E We could change the library to provide the missing symbols, but it is probably best to keep it that way for now=2E So, how about changing `xen-hptool` to have reduced functionality on other platform, and keep the 'mem-*' command on x86 only? You could move the function that implement the 'mem-*' command into a separate file, that compile only on x86 (or more specifically when CONFIG_MIGRATE is set) and just have a "#if defined(__i386__) || defined(__x86_64__)" in the `main_options` array=2E They are compile-time arch-specific check everywhere in tools=2E Arch specific are often implemented in separated source file, this mean we can limit the #ifdefs to a minimum and keep the code readable=2E Thanks, -- Anthony Perard | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vate= s solutions web: https://vates=2Etech ---=Part.231.4aedd74cac3a3672.19dd9a9040f.4e3261a16981b028=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 29 14:42:06 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 14:42:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297440.1573464 (Exim 4.92) (envelope-from ) id 1wI66y-0001op-08; Wed, 29 Apr 2026 14:42:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297440.1573464; Wed, 29 Apr 2026 14:41:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI66x-0001oi-To; Wed, 29 Apr 2026 14:41:59 +0000 Received: by outflank-mailman (input) for mailman id 1297440; Wed, 29 Apr 2026 14:41:59 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI66x-0001oa-1p for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 14:41:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI66w-002YNW-3P for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 16:41:58 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f218b3-bab6-0a2a0a5309dd-0a2a45059fb4-2 for ; Wed, 29 Apr 2026 16:41:58 +0200 Received: from [185.255.28.34] (helo=prod-mta-13.swg-srv.net) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f218b5-aaa8-0a2a45050019-b9ff1c229a4d-3 for ; Wed, 29 Apr 2026 16:41:58 +0200 Received: from mail2.vates.fr ([37.26.189.201] mail2.vates.fr) (Authenticated sender: 8631fc262581453bbf619ec5b2062170/smtp/7773de5a-2839-4720-82ee-e06722ae1d3e) by prod-mta-13.swg-srv.net (ZoneMTA - prod-mta-13) with ESMTPSA id 19dd9b07146000f373.006 for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Wed, 29 Apr 2026 14:41:52 +0000 Received: from [192.168.1.18] (88-175-170-134.subs.proxad.net [88.175.170.134]) (Authenticated sender: teddy.astie) by mail2.vates.fr (Postfix) with ESMTPSA id AE981864B7; Wed, 29 Apr 2026 16:41:47 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=UGqK5k1jQYtCqj3M86/fgUSdu27cnCGG4meD6wI1sT0=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=OwvU0vLSDrCTMUY9WTGpIPozgqClF7cygH3ygwgtTF24zz/CMDKc2G3GohBUGp1jhvOQzmyY3 4qaksEZztNnK/UIhy1iq9dMoXCjgzyC0sqsdLcx+KRjSzs3WZzxHaxUxJclGR/RY/lvTWaXuDue ibdyPjtPnPnOjO38X5cy96A59vhWsau1hdajyKSO+S/N//g4gWRusKXx6uGvCosCfwhq3s/F8e9 emdF52xSWtvzEF9YwTlw19XFMzl4nVoKofftgdncJ/8VoO3NBngGVpHieVqPchJJ5SxxO/064wk TVgucWisok9WAqqQxAKf+lehF+lPmj2BIxG4GaumyQUw== X-Zone-Loop: 23e2bb187a520cdd8e31b3641a32c6e4c8f8a0038cb3 x-campaign-type: default x-transaction-id: a39e41b0-3301-45bf-b32a-1fa3aabdc141 x-swg-uid: 01-58bd9a84-e73b-4548-aaf3-6f522fed0953 X-Mailer: Sweego Message-ID: <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> x-swg-bid: 1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Wed, 29 Apr 2026 16:41:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH] virtio-mmio: add xenbus probing To: Val Packett , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <20260429141339.74472-1-val@invisiblethingslab.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.241.1dd4a0eaebe8c9a7.19dd9b05f77.138039998489b248=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777473707896 X-purgate-ID: tlsNG-c201ff/1777473718-2AB68443-D1598A39/0/0 X-purgate-type: clean X-purgate-size: 9397 ---=Part.241.1dd4a0eaebe8c9a7.19dd9b05f77.138039998489b248=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hello, Le 29/04/2026 =C3=A0 16:18, Val Packett a =C3=A9crit=C2=A0: > The experimental virtio-mmio support for Xen was initially developed > on aarch64, so device trees were used to configure the mmio devices, > with arbitrary vGIC interrupts used by the hypervisor=2E On x86_64 > however, the only reasonable way to interrupt the guest is over Xen > event channels, which can only be acquired by children of xenbus, > the virtual bus driven by Xen's configuration database, XenStore=2E > It is also a more convenient and "Xen-ish" way to provision devices=2E >=20 > Implement a xenbus client for virtio-mmio which negotiates an > event channel and provides it as a platform IRQ to the > virtio-mmio driver=2E >=20 >=20 > Signed-off-by: Val Packett > --- >=20 > Hi, >=20 > I've been working on porting virtio-mmio support from Arm to x86_64, > with the goal of running vhost-user-gpu to power Wayland/GPU integration > for Qubes OS=2E (I'm aware of various proposals for alternative virtio > transports but virtio-mmio seems to be the only one that *is* upstream > already and just Works=2E=2E) Setting up virtio-mmio through xenbus, ini= tially > motivated just by event channels being the only real way to get interrup= ts > working on HVM, turned out to generally be quite pleasant and nice :) Is it HVM specific, or can we also make it work for PVH (we can actually= =20 attach a ioreq server to PVH guests) ? >=20 > I'd like to get some early feedback for this patch, particularly > the general stuff: >=20 > * is this whole thing acceptable in general? > * should it be extracted into a different file? > * (from the Xen side) any input on the xenstore keys, what goes where? > * anything else to keep in mind? >=20 > It does seem simple enough, so hopefully this can be done? >=20 > The corresponding userspace-side WIP is available at: > https://github=2Ecom/QubesOS/xen-vhost-frontend >=20 > And the required DMOP for firing the evtchn events will be sent > to xen-devel shortly as well=2E Could that be done through evtchn_send (or its userland counterpart) ? >=20 > Thanks, > ~val >=20 > --- > drivers/virtio/Kconfig | 7 ++ > drivers/virtio/virtio_mmio=2Ec | 177 +++++++++++++++++++++++++++++++++= +- > 2 files changed, 183 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig > index ce5bc0d9ea28=2E=2E56bc2b10526b 100644 > --- a/drivers/virtio/Kconfig > +++ b/drivers/virtio/Kconfig > @@ -171,6 +171,13 @@ config VIRTIO_MMIO_CMDLINE_DEVICES > =20 > If unsure, say 'N'=2E > =20 > +config VIRTIO_MMIO_XENBUS > + bool "Memory mapped virtio devices parameter parsing" that text seems to miss the xenbus aspect > + depends on VIRTIO_MMIO && XEN > + select XEN_XENBUS_FRONTEND > + help > + Allow virtio-mmio devices instantiation for Xen guests via xenbus=2E > + > config VIRTIO_DMA_SHARED_BUFFER > tristate > depends on DMA_SHARED_BUFFER > diff --git a/drivers/virtio/virtio_mmio=2Ec b/drivers/virtio/virtio_mmio= =2Ec > index 595c2274fbb5=2E=2E32295284bdbf 100644 > --- a/drivers/virtio/virtio_mmio=2Ec > +++ b/drivers/virtio/virtio_mmio=2Ec > @@ -70,6 +70,11 @@ > #include > #include > =20 > +#ifdef CONFIG_VIRTIO_MMIO_XENBUS > +#include > +#include > +#include > +#endif > =20 > =20 > /* The alignment to use between consumer and producer parts of vring= =2E > @@ -810,13 +815,183 @@ static struct platform_driver virtio_mmio_driver = =3D { > }, > }; > =20 > +#ifdef CONFIG_VIRTIO_MMIO_XENBUS > +struct virtio_mmio_xen_info { > + struct resource resources[2]; > + unsigned int evtchn; > + struct platform_device *pdev; > +}; > + > +static int virtio_mmio_xen_probe(struct xenbus_device *dev, > + const struct xenbus_device_id *id) > +{ > + int err; > + long long base, size; > + char *mem; > + struct virtio_mmio_xen_info *info; > + struct xenbus_transaction xbt; > + > + /* TODO: allocate an unused address here and pass it to the host inste= ad */ > + err =3D xenbus_scanf(XBT_NIL, dev->otherend, "base", "0x%llx", > + &base); > + if (err < 0) { > + xenbus_dev_fatal(dev, err, "reading base"); > + return -EINVAL; > + } > + > + mem =3D xenbus_read(XBT_NIL, dev->otherend, "size", NULL); > + if (XENBUS_IS_ERR_READ(mem)) > + return PTR_ERR(mem); > + size =3D memparse(mem, NULL); > + kfree(mem); > + > + info =3D kzalloc_obj(*info); > + if (!info) { > + xenbus_dev_fatal(dev, -ENOMEM, "allocating info structure"); > + return -ENOMEM; > + } > + > + info->resources[0]=2Eflags =3D IORESOURCE_MEM; > + info->resources[0]=2Estart =3D base; > + info->resources[0]=2Eend =3D base + size - 1; > + > + err =3D xenbus_alloc_evtchn(dev, &info->evtchn); > + if (err) { > + xenbus_dev_fatal(dev, err, "xenbus_alloc_evtchn"); > + goto error_info; > + } > + > + err =3D bind_evtchn_to_irq(info->evtchn); > + if (err <=3D 0) { > + xenbus_dev_fatal(dev, err, "bind_evtchn_to_irq"); > + goto error_evtchan; > + } > + > + info->resources[1]=2Eflags =3D IORESOURCE_IRQ; > + info->resources[1]=2Estart =3D info->resources[1]=2Eend =3D err; > + > +again: > + err =3D xenbus_transaction_start(&xbt); > + if (err) { > + xenbus_dev_fatal(dev, err, "starting transaction"); > + goto error_irq; > + } > + > + err =3D xenbus_printf(xbt, dev->nodename, "event-channel", "%u", > + info->evtchn); > + if (err) { > + xenbus_transaction_end(xbt, 1); > + xenbus_dev_fatal(dev, err, "%s", "writing event-channel"); > + goto error_irq; > + } > + > + err =3D xenbus_transaction_end(xbt, 0); > + if (err) { > + if (err =3D=3D -EAGAIN) > + goto again; > + xenbus_dev_fatal(dev, err, "completing transaction"); > + goto error_irq; > + } > + > + dev_set_drvdata(&dev->dev, info); > + xenbus_switch_state(dev, XenbusStateInitialised); > + return 0; > + > +error_irq: > + unbind_from_irqhandler(info->resources[1]=2Estart, info); > +error_evtchan: > + xenbus_free_evtchn(dev, info->evtchn); > +error_info: > + kfree(info); > + > + return err; > +} > + > +static void virtio_mmio_xen_backend_changed(struct xenbus_device *dev, > + enum xenbus_state backend_state) > +{ > + struct virtio_mmio_xen_info *info =3D dev_get_drvdata(&dev->dev); > + > + switch (backend_state) { > + case XenbusStateInitialising: > + case XenbusStateInitWait: > + case XenbusStateInitialised: > + case XenbusStateReconfiguring: > + case XenbusStateReconfigured: > + case XenbusStateUnknown: > + break; > + > + case XenbusStateConnected: > + if (dev->state !=3D XenbusStateInitialised) { > + dev_warn(&dev->dev, "state %d on connect", dev->state); > + break; > + } > + info->pdev =3D platform_device_register_resndata(&dev->dev, > + "virtio-mmio", PLATFORM_DEVID_AUTO, > + info->resources, ARRAY_SIZE(info->resources), NULL, 0); > + xenbus_switch_state(dev, XenbusStateConnected); > + break; > + > + case XenbusStateClosed: > + if (dev->state =3D=3D XenbusStateClosed) > + break; > + fallthrough; /* Missed the backend's Closing state=2E */ > + case XenbusStateClosing: > + platform_device_unregister(info->pdev); > + xenbus_switch_state(dev, XenbusStateClosed); > + break; > + > + default: > + xenbus_dev_fatal(dev, -EINVAL, "saw state %d at frontend", > + backend_state); > + break; > + } > +} > + In some way, we're defining a new "PV driver" which is a virtio-mmio=20 one, I guess we can eventually specific some form of protocol that=20 backend/frontend would need to follow ? > +static void virtio_mmio_xen_remove(struct xenbus_device *dev) > +{ > + struct virtio_mmio_xen_info *info =3D dev_get_drvdata(&dev->dev); > + > + kfree(info); > + dev_set_drvdata(&dev->dev, NULL); > +} > + > +static const struct xenbus_device_id virtio_mmio_xen_ids[] =3D { > + { "virtio" }, > + { "" }, > +}; > + > +static struct xenbus_driver virtio_mmio_xen_driver =3D { > + =2Eids =3D virtio_mmio_xen_ids, > + =2Eprobe =3D virtio_mmio_xen_probe, > + =2Eotherend_changed =3D virtio_mmio_xen_backend_changed, > + =2Eremove =3D virtio_mmio_xen_remove, > +}; > +#endif > + > static int __init virtio_mmio_init(void) > { > - return platform_driver_register(&virtio_mmio_driver); > + int ret; > + > + ret =3D platform_driver_register(&virtio_mmio_driver); > + if (ret) > + return ret; > + > +#ifdef CONFIG_VIRTIO_MMIO_XENBUS > + if (xen_domain()) > + ret =3D xenbus_register_frontend(&virtio_mmio_xen_driver); > +#endif> + > + return ret; > } > =20 > static void __exit virtio_mmio_exit(void) > { > +#ifdef CONFIG_VIRTIO_MMIO_XENBUS > + if (xen_domain()) > + xenbus_unregister_driver(&virtio_mmio_xen_driver); > +#endif > + > platform_driver_unregister(&virtio_mmio_driver); > vm_unregister_cmdline_devices(); > } -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.241.1dd4a0eaebe8c9a7.19dd9b05f77.138039998489b248=--- From xen-devel-bounces@lists.xenproject.org Wed Apr 29 14:42:34 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 14:42:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297448.1573473 (Exim 4.92) (envelope-from ) id 1wI67W-0002G1-7y; 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Wed, 29 Apr 2026 14:42:32 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=VMjKyD+6u8SReAC3Yu69HgVoOG7voI+4oB0A2F5LIWA=; b=Zq6zWXx2A10N1WbiZ0JOdzYcvS H50iQ+jqBzG/+FPVPc+mdDr/F4QDa7kwZLGImYBPqQ8WCt8jXT+sNWaDeZk/rYKKSgGRX3Rl0zHx+ G7MPVEl+YsV/vu7kx7+I/MhWc/B+QBwJ3aOlR5i9wvFqzkx4oahSo2+k4q+nPGb8/zfQ=; Message-ID: Date: Wed, 29 Apr 2026 15:42:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] xen/arm: skip holes in physical address space when setting up frametable Content-Language: en-GB To: "Orzel, Michal" , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Luca Fancellu References: <20260417091124.39552-1-michal.orzel@amd.com> <6a43af84-ca86-41f2-b58d-57be5baf49de@xen.org> From: Julien Grall In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Michal, On 22/04/2026 09:25, Orzel, Michal wrote: > > > On 22/04/2026 09:01, Julien Grall wrote: >> Hi Michal, >> >> On 17/04/2026 10:11, Michal Orzel wrote: >>> Refactor setup_frametable_mappings() into init_frametable(), modeled >>> after x86's implementation. Instead of mapping one contiguous frametable >>> covering ram_start to ram_end (including holes), iterate the >>> pdx_group_valid bitmap to allocate and map frametable memory only for >>> valid PDX groups, skipping gaps in the physical address space. At the >>> moment we don't really take into account pdx_group_valid bitmap. >>> >>> This reduces memory consumption on systems with sparse RAM layouts by >>> not allocating frametable entries for non-existent memory regions. >>> >>> A file-local pdx_to_page() override is needed because the generic macro >>> in xen/include/xen/pdx.h does not account for ARM's non-zero >>> frametable_base_pdx. >> >> Can you provide a bit more details? I am a bit concerned that this could >> result to subttle bug in the future if code within mm.c is expecting the >> original behavior. It would be preferable if the change is either for >> everyone on Arm or the function is renamed to avoid any clash. > The generic pdx_to_page macro does not account for offset which is something I > mentioned in the footer and I'm willing to work on in the future. Sorry I missed the comment in the footer. But if the function is broken, then why can't we implement pdx_to_page() correctly now? I understand that ... As of today, > this macro is *unused* on Arm. It's only used by x86 in some special big mem > related scenario. Using generic pdx_to_page on Arm would be wrong, so a future > patch doing that would be wrong (the fact that this patch adds a local redefine > does not change anything). Do we need a rename for a local redefine in a file > that is only related to frametable? Maybe a comment and a TODO would be ok? ... this is not meant to be used by Arm today. But given this is used in the page list, it is definitely not obvious that it is broken. The alternative is to protect/move pdx_to_page() in x86. But I don't know much churn this would involve. > >> >> [...] >> >>> +void __init init_frametable(paddr_t ram_start) >>> +{ >>> + unsigned int sidx, nidx, max_idx; >>> >>> /* >>> * The size of paddr_t should be sufficient for the complete range of >>> @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >>> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >>> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >>> >>> - if ( frametable_size > FRAMETABLE_SIZE ) >>> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >>> - ps, pe); >>> + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); >>> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >>> >>> - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); >>> - /* Round up to 2M or 32M boundary, as appropriate. */ >>> - frametable_size = ROUNDUP(frametable_size, mapping_size); >>> - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); >>> + /* >>> + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned >>> + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this >>> + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of >>> + * PAGE_SIZE by construction. >>> + */ >>> + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); >>> >>> - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, >>> - frametable_size >> PAGE_SHIFT, >>> - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); >>> - if ( rc ) >>> - panic("Unable to setup the frametable mappings.\n"); >>> + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) >>> + panic("Frametable too small\n"); >>> + >>> + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) >>> + { >>> + unsigned int eidx; >>> + >>> + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); >>> + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); >>> + >>> + if ( nidx >= max_idx ) >>> + break; >>> + >>> + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); >> >> The function will do a round-up the mapping to either a 2MiB or 32MiB >> aligned size. This means we could potentially cover the previous mapped >> region or the next one. I can't seem to find any code to cover this >> use-case. What did I miss? > Hmm, I think I calculated something wrong here. Anyway, how about using 2MB > mapping size all the time? PDX group size is 2MB, Looking at the code, it seems to be based on SECOND_SHIFT which technically depends on the page granularity. Even though Xen supports only 4KiB, we are trying to avoid making such assumption or add least adding a BUILD_BUG_ON() (in this case, I would consider that PDX_GROUP_COUNT is always 2MiB or SECOND_SHIFT). > in-loop chunks are multiple of > 2MB, there is no roundup needed - zero overshoot. The last chunk may have ~2MB > overshoot but it does not matter as there is nothing after it to conflict with. > The downside is more TLB pressure. I am a bit warry to modify the frametable allocation method because it is used fairly often in Xen. Would it be possible to hence the loop to detect contiguous chunk and decide the size allocation based on the chunk? > > Alternatively, we could reduce the mapping size closer to boundaries (x86 > choice) but that would require a bit more work. This would technically have the same downside as above. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Apr 29 15:03:11 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 15:03:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297474.1573483 (Exim 4.92) (envelope-from ) id 1wI6RD-0005iN-LK; Wed, 29 Apr 2026 15:02:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297474.1573483; Wed, 29 Apr 2026 15:02:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI6RD-0005iG-Ia; Wed, 29 Apr 2026 15:02:55 +0000 Received: by outflank-mailman (input) for mailman id 1297474; Wed, 29 Apr 2026 15:02:54 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wI6RB-0005iA-Ir for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 15:02:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wI6R9-003Ihf-07 for xen-devel@lists.xenproject.org; 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Only rebase. > --- > --- looks ok to me. Reviewed-by: Luca Fancellu Cheers, Luca From xen-devel-bounces@lists.xenproject.org Wed Apr 29 15:11:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 15:11:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297486.1573492 (Exim 4.92) (envelope-from ) id 1wI6ZD-0007eL-IE; Wed, 29 Apr 2026 15:11:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297486.1573492; Wed, 29 Apr 2026 15:11:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI6ZD-0007eE-FR; Wed, 29 Apr 2026 15:11:11 +0000 Received: by outflank-mailman (input) for mailman id 1297486; Wed, 29 Apr 2026 15:11:10 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) id 1wI6ZC-0007e8-Bu for xen-devel@lists.xenproject.org; Wed, 29 Apr 2026 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <20260429141339.74472-1-val@invisiblethingslab.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------g0UC1Ck4AStDbbtB0H4eW8y7" X-purgate-ID: tlsNG-16d1c6/1777476934-CE168D75-4B82E3CD/0/0 X-purgate-type: clean X-purgate-size: 18626 This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------g0UC1Ck4AStDbbtB0H4eW8y7 Content-Type: multipart/mixed; boundary="------------ue4BYSUfwU0oTBtHJ9in4V9z"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Val Packett , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev Message-ID: <67632532-8421-4a10-a961-f7c4f05b177b@suse.com> Subject: Re: [RFC PATCH] virtio-mmio: add xenbus probing References: <20260429141339.74472-1-val@invisiblethingslab.com> In-Reply-To: <20260429141339.74472-1-val@invisiblethingslab.com> --------------ue4BYSUfwU0oTBtHJ9in4V9z Content-Type: multipart/mixed; boundary="------------HCshP870xeA72w06G6OVMqA8" --------------HCshP870xeA72w06G6OVMqA8 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: base64 U29tZSBtaW5vciBkZXRhaWxzIGZyb20gdGhlIFhlbiBzaWRlIG9mIHRoaW5nczoNCg0KT24g MjkuMDQuMjYgMTU6NTIsIFZhbCBQYWNrZXR0IHdyb3RlOg0KPiBUaGUgZXhwZXJpbWVudGFs IHZpcnRpby1tbWlvIHN1cHBvcnQgZm9yIFhlbiB3YXMgaW5pdGlhbGx5IGRldmVsb3BlZA0K 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xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 489 v2 (CVE-2026-23559,CVE-2026-23560,CVE-2026-23561,CVE-2026-23562,CVE-2026-42486) - Multiple RBAC issues in XAPI Message-Id: Date: Wed, 29 Apr 2026 16:36:20 +0000 X-purgate-ID: tlsNG-720697/1777480586-82F6E161-90DE8246/3/8721326451 X-purgate-type: bulk X-purgate-size: 4128 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2026-23559,CVE-2026-23560,CVE-2026-23561,CVE-2026-23562,CVE-2026-42486 / XSA-489 version 2 Multiple RBAC issues in XAPI UPDATES IN VERSION 2 ==================== Fixes now merged and backported in XAPI. Refer to the tagged releases. ISSUE DESCRIPTION ================= XAPI can configure different users with different roles, using Role Based Access Control. For more details, see: https://docs.xenserver.com/en-us/xencenter/current-release/rbac-overview.html#rbac-roles The pool-admin role is fully privileged. Notably, users with this role can also SSH into the host as root. The other administrator roles are pool-operator, vm-power-admin and vm-admin, each of which are authorised to configure and manage various aspects of the system. Some settings are inadequately restricted, and can be set by a lower privilege of administrator than expected. * CVE-2026-23559: A vm-admin can set VBD.other_config:backend-local and turn arbitrary files in dom0 into VDIs (virtual disks) and give said disks to a VM they control. This is an arbitrary read and/or modify of files in dom0. * CVE-2026-23560: A vm-admin can set VM.other-config:is_system_domain and mark a VM as a system domain. System domains are ignored and left running during certain other host/pool operations, and may be hidden from view in tooling. * CVE-2026-23561: A vm-admin can set VM.other_config:storage_driver_domain and mark a VM as the storage domain for a particular host storage connection (PBD). Shutting down the VM can cause the PBD to be erroneously marked as unplugged when it is not. * CVE-2026-23562: Configuration of PCI passthrough is normally restricted to the pool-admin role. However one API was missing this check, allowing a vm-admin access to unintended host hardware. * CVE-2026-42486: A vm-admin can set the VM.platform:hvm_serial parameter, which should be restricted to the pool-admin role, as it can allow arbitrary dom0 file write. IMPACT ====== An authenticated user already granted one of pool-operator, vm-power-admin or vm-admin can escalate their privilege to pool-admin. VULNERABLE SYSTEMS ================== Systems running all versions of XAPI are vulnerable. The vulnerability is only exposed if RBAC is configured for the pool, and certain users are assigned the not-fully-privileged administrator roles. MITIGATION ========== Disable any users (RBAC subjects) which have been configured with the vm-admin, vm-power-admin or pool-operator role. RESOLUTION ========== Fixes in XAPI have been merged and backported. They are available in the following releases: https://github.com/xapi-project/xen-api/releases/tag/v26.12.0 https://github.com/xapi-project/xen-api/releases/tag/v26.1.11 NOTE REGARDING LACK OF EMBARGO ============================== These issues were disclosed in public. The researcher claimed 89 vulnerabilities. Analysis by the XAPI team concluded that only 5 were real vulnerabilities, with most being a failure to read the RBAC documentation, and several appearing to be AI hallucinations. The researcher also took active steps to prevent coordinated disclosure. Due to acting in bad faith, they are explicitly not credited. -----BEGIN PGP SIGNATURE----- iQFABAEBCAAqFiEEI+MiLBRfRHX6gGCng/4UyVfoK9kFAmnyM2sMHHBncEB4ZW4u b3JnAAoJEIP+FMlX6CvZwPUIAMWaoFOOukhaMwGj+r6+k2lKvYhkYjbstVUrSTp2 PVZ17/xezOg/rHotBTdixWDVsztoJcw/pm/hRAcYqSJJ5+aYVrVzNOpVRRuFf2uK p8Lkjmk/15MeDy68pEeIkoJEpdAdTsJvY5anHB0OtUug/NzmiDUDvcJbsBfAmEHS pzeQAVoKICy4Z1/EWbKNofq+ja4gMEJDvNdM51jY9LUnOuNWgdP24Tjk9DjuZ3jz TfWjpbrtEG7RgU0hgsZhsFMxzVh3JZPPIAkqLkZJouDH7SpRZe3t3AIPY5eUw80w x94wdIJoiTS2FAEEyIRs7aa+DqyvLVhHhqJmMfHRl8/6KbA= =ye+c -----END PGP SIGNATURE----- --=separator-- From xen-devel-bounces@lists.xenproject.org Wed Apr 29 16:41:46 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 16:41:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297649.1573559 (Exim 4.92) (envelope-from ) id 1wI7yl-0007J5-6w; Wed, 29 Apr 2026 16:41:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297649.1573559; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qADEAC3AKFRbv40Yqb1N8AW5c1D7VweUpjPTDAZX59CJ1JJYnUfKxUAjNq5ddrYjJnbdrOVc5ytLVl7nlPqZqm619YN6Znox+IlqrOLYGwf92hontJc0zn3qtN4nVnjXXhHXDEM3O9tUAeWqg1og2Z899tHdlWsuzgzrSR1VlQdbOU4V5tUPG0ZoTZ57mpdfUgTxQHXq8LGZhG8iiS8iouMXcrrcusLNTIDtvi63R43aXc3v5aRhSNayLA9CfWBuzLSPLodhHn/Ro2qakPJKLQM5Usy6TsBQTmZgailXPlBVYoBXnh91IL3/AxaCIOVmzHxk+sQlRsE3V2EUalvbQsn5xMI2Zqiildar0n10gu4LPJ9jUq/viMRzpZVyEJ8RsthlwFLnmLII+Yr8Whjmi4k0AR8SjLcCHdVCxdClU81gTx9F3FJeW+VbigKlNpxP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Apr 2026 16:41:26.9393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a87ec23c-28b0-45b6-8cba-08dea60e2858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9153 X-purgate-ID: tlsNG-720697/1777480896-80D7F161-CDF91E7B/0/0 X-purgate-type: clean X-purgate-size: 503 On 2026-04-29 08:06, Juergen Gross wrote: > Wit unprivileged domains now capable to use the @releaseDomain watch, s/Wit/With/ again. Regards, Jason > there is no reason not to remove any node permissions which relate to > a domain which has been removed. > > This resolves a complex scenario where a new domain could inherit the > permissions of an old one with the same domid. > > Signed-off-by: Juergen Gross > Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Wed Apr 29 16:55:09 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 29 Apr 2026 16:55:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297682.1573568 (Exim 4.92) (envelope-from ) id 1wI8Bi-0000j3-A3; Wed, 29 Apr 2026 16:55:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297682.1573568; Wed, 29 Apr 2026 16:55:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wI8Bi-0000iw-7K; Wed, 29 Apr 2026 16:55:02 +0000 Received: by outflank-mailman (input) for mailman id 1297682; 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Wed, 29 Apr 2026 16:54:54 +0000 Received: from [192.168.1.18] (88-175-170-134.subs.proxad.net [88.175.170.134]) (Authenticated sender: teddy.astie) by mail2.vates.fr (Postfix) with ESMTPSA id E2CA986484; Wed, 29 Apr 2026 18:54:49 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=tPxjCeuXw+PNWa5aL1B7SkZUldWs8bQSo7/uIWCVxQE=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=iK33oN+HlKXnuzRGtXmCAs8hQKlIPet7lI2bKWVSeonf/MuGZmlMdnX8BAXYNVTz5atD211NS qPNADF9oNZeO1nMFF7ALTYz32OTgaEOQHPJTqTX3mNsjS/oPBdsptElbeyVuSytav+AF00Yy/pX vT/rC1+vlEkTmSX575Nbca21DWJldWVvzqqTYi475XUmoCZu3avNSILZabY8LIWqEkiV0PH6vjP 86/z9fG/OaFhs/yGqAQCdZZ+Aq63AJO9+AYGlAyqBslVAwnXdckQ3510WGODJvo5JRs+dQ1UkFM +ze/4jAzODEZ8PjYz5sUkEBnIjucWS3vDVSbJi3Xuv7g== X-Zone-Loop: f5fc6aa7fb3d2a80262c364e8869db00cebd8a22257d x-campaign-type: default x-transaction-id: acad869d-85a3-4603-b747-bf2ace67da70 x-swg-uid: 01-f95f651f-3ae0-4cd0-b7b1-e0d56d10c2ba X-Mailer: Sweego Message-ID: <1777481694.8631fc262581453bbf619ec5b2062170.19dda2a3d88000f373@vates.tech> x-swg-bid: 1777481694.8631fc262581453bbf619ec5b2062170.19dda2a3d88000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Wed, 29 Apr 2026 18:54:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] nestedsvm: Clear GIF when injecting VMEXIT To: Ross Lagerwall , xen-devel@lists.xenproject.org Cc: Jan Beulich , Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Jason Andryuk References: <20260423161112.50221-1-ross.lagerwall@citrix.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <20260423161112.50221-1-ross.lagerwall@citrix.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2c5.179858d92bc580ea.19dda2a2bba.f9f3b2a504f764f4=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777481690042 X-purgate-ID: tlsNG-c1860d/1777481699-C1D6BDB1-E38CF011/0/0 X-purgate-type: clean X-purgate-size: 2016 ---=Part.2c5.179858d92bc580ea.19dda2a2bba.f9f3b2a504f764f4=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 23/04/2026 =C3=A0 18:13, Ross Lagerwall a =C3=A9crit=C2=A0: > If L1 executes VMRUN with the GIF set and it fails consistency checks, > Xen will inject a VMEXIT and fail the assert checking the GIF is cleared= =2E >=20 > Instead, clear the GIF when injecting a VMEXIT to match what hardware > does=2E >=20 > Fixes: 9a779e4fc161 ("Implement SVM specific part for Nested Virtualizat= ion") > Signed-off-by: Ross Lagerwall > --- > xen/arch/x86/hvm/svm/nestedsvm=2Ec | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/xen/arch/x86/hvm/svm/nestedsvm=2Ec b/xen/arch/x86/hvm/svm/n= estedsvm=2Ec > index ef6fa5d23b67=2E=2Ef89b087a1155 100644 > --- a/xen/arch/x86/hvm/svm/nestedsvm=2Ec > +++ b/xen/arch/x86/hvm/svm/nestedsvm=2Ec > @@ -733,9 +733,9 @@ nsvm_vcpu_vmexit_inject(struct vcpu *v, struct cpu_u= ser_regs *regs, > struct vmcb_struct *vmcb =3D v->arch=2Ehvm=2Esvm=2Evmcb; > =20 > if ( vmcb->_vintr=2Efields=2Evgif_enable ) > - ASSERT(vmcb->_vintr=2Efields=2Evgif =3D=3D 0); > + vmcb->_vintr=2Efields=2Evgif =3D 0; > else > - ASSERT(svm->ns_gif =3D=3D 0); > + nestedsvm_vcpu_clgi(v); > =20 > ns_vmcb =3D nv->nv_vvmcx; > =20 Looks good to me, though I think we are here looking to make a "guest=20 CLGI" (clear GIF), so the vGIF specific logic should be collapsed into=20 nestedsvm_vcpu_clgi() instead of having it as the non-vgif-support case=2E (as IIUC, vGIF is a hardware accelration for nested GIF handling ?) (also making me notice that svm_vmexit_do_{stgi,clgi}() seems to lack=20 vGIF specific logic) Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.2c5.179858d92bc580ea.19dda2a2bba.f9f3b2a504f764f4=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 30 04:01:50 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 04:01:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297908.1573577 (Exim 4.92) (envelope-from ) id 1wIIaj-0001ws-7n; Thu, 30 Apr 2026 04:01:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297908.1573577; Thu, 30 Apr 2026 04:01:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIIaj-0001wk-1L; Thu, 30 Apr 2026 04:01:33 +0000 Received: by outflank-mailman (input) for mailman id 1297908; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> Content-Language: en-US From: Val Packett Autocrypt: addr=val@invisiblethingslab.com; keydata= xm8EaFTEiRMFK4EEACIDAwQ+qzawvLuE95iu+QkRqp8P9z6XvFopWtYOaEnYf/nE8KWCnsCD jz82tdbKBpmVOdR6ViLD9tzHvaZ1NqZ9mbrszMXq09VfefoCfZp8jnA2yCT8Y4ykmv6902Ne NnlkVwrNKFZhbCBQYWNrZXR0IDx2YWxAaW52aXNpYmxldGhpbmdzbGFiLmNvbT7CswQTEwkA OxYhBAFMrro+oMGIFPc7Uc87uZxqzalRBQJoVMSJAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMB Ah4HAheAAAoJEM87uZxqzalRlIIBf0cujzfSLhvib9iY8LBh8Tirgypm+hJHoY563xhP0YRS pmqZ6goIuSGpEKcW5mV3egF/TLLAOjsfroWae4giImTVOJvLOsUycxAP4O5b1Qiy+cCGsHKA nCRzrvqnPkyf4OeRznMEaFTEiRIFK4EEACIDAwSffe3tlMmmg3eKVp7SJ+CNZLN0M5qzHSCV dBBkIVvEJo+8SDg4jrx/832rxpvMCz2+x7+OHaeBHKafhOWUccYBLKqV/3nBftxCkbzXDbfY d02BY9H4wBIn0Y3GnwoIXRgDAQkJwpgEGBMJACAWIQQBTK66PqDBiBT3O1HPO7mcas2pUQUC aFTEiQIbDAAKCRDPO7mcas2pUaptAX9f7yUJLGU4C6XjMJvXd8Sz6cGTyxkngPtUyFiNqtad /GXBi3vHKYNfSrdqJ8wmZ8MBgOqWaaa1wE4/3qZU8d4RNR8mF7O40WYK/wdf1ycq1uGad8PN UDOwAqdfvuF3w8QMPw== In-Reply-To: <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ef75cf/1777521690-2BD7FC48-0F9579A8/0/0 X-purgate-type: clean X-purgate-size: 3318 On 4/29/26 11:41 AM, Teddy Astie wrote: > Hello, > > Le 29/04/2026 à 16:18, Val Packett a écrit : >> […] >> >> I've been working on porting virtio-mmio support from Arm to x86_64, >> with the goal of running vhost-user-gpu to power Wayland/GPU integration >> for Qubes OS. (I'm aware of various proposals for alternative virtio >> transports but virtio-mmio seems to be the only one that *is* upstream >> already and just Works..) Setting up virtio-mmio through xenbus, initially >> motivated just by event channels being the only real way to get interrupts >> working on HVM, turned out to generally be quite pleasant and nice :) > Is it HVM specific, or can we also make it work for PVH (we can actually > attach a ioreq server to PVH guests) ? Sorry, typo, I did mean PVH of course! I've been testing this with PVH guests + PV dom0, with my PV alloc_ioreq fix: https://lore.kernel.org/all/20251126062124.117425-1-val@invisiblethingslab.com/ (Time to resend that one as a non-RFC I guess…) HVM actually does have legacy ISA interrupts (which are often used with virtio-mmio on KVM), funnily enough, and I've tried firing those from a DMOP but that silly thing didn't work properly. >> I'd like to get some early feedback for this patch, particularly >> the general stuff: >> >> * is this whole thing acceptable in general? >> * should it be extracted into a different file? >> * (from the Xen side) any input on the xenstore keys, what goes where? >> * anything else to keep in mind? >> >> It does seem simple enough, so hopefully this can be done? >> >> The corresponding userspace-side WIP is available at: >> https://github.com/QubesOS/xen-vhost-frontend >> >> And the required DMOP for firing the evtchn events will be sent >> to xen-devel shortly as well. > Could that be done through evtchn_send (or its userland counterpart) ? Actually, yes… The use of DMOPs is only dictated by the current Linux privcmd.c code (the irqfds created by the kernel react to events by executing HYPERVISOR_dm_op with a stored operation), we can avoid the need to modify Xen by simply expanding the privcmd driver to make "evtchn fds". Sounds good, will do. >> [..] >> >> diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig >> index ce5bc0d9ea28..56bc2b10526b 100644 >> --- a/drivers/virtio/Kconfig >> +++ b/drivers/virtio/Kconfig >> @@ -171,6 +171,13 @@ config VIRTIO_MMIO_CMDLINE_DEVICES >> >> If unsure, say 'N'. >> >> +config VIRTIO_MMIO_XENBUS >> + bool "Memory mapped virtio devices parameter parsing" > that text seems to miss the xenbus aspect Yep, didn't change that yet, ack >> [..] > In some way, we're defining a new "PV driver" which is a virtio-mmio > one, I guess we can eventually specific some form of protocol that > backend/frontend would need to follow ? Right, Jürgen mentioned documenting the keys in the xenstore-paths doc.. would the entire "protocol" (keys + state transition logic) fit into that? The keys are currently derived from the initial Arm prototype which wasn't actually using xenbus properly (the guest driver was configured by a device tree node, but the ioreq server used xenstore keys, without properly transitioning between states). Thanks, ~val From xen-devel-bounces@lists.xenproject.org Thu Apr 30 04:05:01 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 04:05:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297915.1573586 (Exim 4.92) (envelope-from ) id 1wIIe4-0002Tr-JU; Thu, 30 Apr 2026 04:05:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297915.1573586; Thu, 30 Apr 2026 04:05:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIIe4-0002Tk-GW; Thu, 30 Apr 2026 04:05:00 +0000 Received: by outflank-mailman (input) for mailman id 1297915; Thu, 30 Apr 2026 04:05:00 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIIe3-0002Te-Re for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 04:04:59 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wIIe3-00DvrP-7N for xen-devel@lists.xenproject.org; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <67632532-8421-4a10-a961-f7c4f05b177b@suse.com> Content-Language: en-US From: Val Packett Autocrypt: addr=val@invisiblethingslab.com; keydata= xm8EaFTEiRMFK4EEACIDAwQ+qzawvLuE95iu+QkRqp8P9z6XvFopWtYOaEnYf/nE8KWCnsCD jz82tdbKBpmVOdR6ViLD9tzHvaZ1NqZ9mbrszMXq09VfefoCfZp8jnA2yCT8Y4ykmv6902Ne NnlkVwrNKFZhbCBQYWNrZXR0IDx2YWxAaW52aXNpYmxldGhpbmdzbGFiLmNvbT7CswQTEwkA OxYhBAFMrro+oMGIFPc7Uc87uZxqzalRBQJoVMSJAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMB Ah4HAheAAAoJEM87uZxqzalRlIIBf0cujzfSLhvib9iY8LBh8Tirgypm+hJHoY563xhP0YRS pmqZ6goIuSGpEKcW5mV3egF/TLLAOjsfroWae4giImTVOJvLOsUycxAP4O5b1Qiy+cCGsHKA nCRzrvqnPkyf4OeRznMEaFTEiRIFK4EEACIDAwSffe3tlMmmg3eKVp7SJ+CNZLN0M5qzHSCV dBBkIVvEJo+8SDg4jrx/832rxpvMCz2+x7+OHaeBHKafhOWUccYBLKqV/3nBftxCkbzXDbfY d02BY9H4wBIn0Y3GnwoIXRgDAQkJwpgEGBMJACAWIQQBTK66PqDBiBT3O1HPO7mcas2pUQUC aFTEiQIbDAAKCRDPO7mcas2pUaptAX9f7yUJLGU4C6XjMJvXd8Sz6cGTyxkngPtUyFiNqtad /GXBi3vHKYNfSrdqJ8wmZ8MBgOqWaaa1wE4/3qZU8d4RNR8mF7O40WYK/wdf1ycq1uGad8PN UDOwAqdfvuF3w8QMPw== In-Reply-To: <67632532-8421-4a10-a961-f7c4f05b177b@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-bad1c0/1777521899-41D6FA53-810D5A9F/0/0 X-purgate-type: clean X-purgate-size: 2704 On 4/29/26 12:35 PM, Jürgen Groß wrote: > Some minor details from the Xen side of things: > > On 29.04.26 15:52, Val Packett wrote: >> The experimental virtio-mmio support for Xen was initially developed >> on aarch64, so device trees were used to configure the mmio devices, >> with arbitrary vGIC interrupts used by the hypervisor. On x86_64 >> however, the only reasonable way to interrupt the guest is over Xen >> event channels, which can only be acquired by children of xenbus, > > More exact: interdomain event channels need to be connected to a xenbus > device. But you are needing those, so for your use case the above > statement > is correct. > >> the virtual bus driven by Xen's configuration database, XenStore. >> It is also a more convenient and "Xen-ish" way to provision devices. >> >> Implement a xenbus client for virtio-mmio which negotiates an >> event channel and provides it as a platform IRQ to the >> virtio-mmio driver. >> >> >> Signed-off-by: Val Packett >> --- >> >> Hi, >> >> I've been working on porting virtio-mmio support from Arm to x86_64, >> with the goal of running vhost-user-gpu to power Wayland/GPU integration >> for Qubes OS. (I'm aware of various proposals for alternative virtio >> transports but virtio-mmio seems to be the only one that *is* upstream >> already and just Works..) Setting up virtio-mmio through xenbus, >> initially >> motivated just by event channels being the only real way to get >> interrupts >> working on HVM, turned out to generally be quite pleasant and nice :) >> >> I'd like to get some early feedback for this patch, particularly >> the general stuff: >> >> * is this whole thing acceptable in general? >> * should it be extracted into a different file? >> * (from the Xen side) any input on the xenstore keys, what goes where? > > You should add some documentation in the Xen source tree regarding the > Xenstore keys (see docs/misc/xenstore-paths.pandoc there). Ack, thanks! >> […] >> >> +again: >> +    err = xenbus_transaction_start(&xbt); > > No need to use a Xenstore transaction here. The written node(s) are > regarded to be valid only after calling xenbus_switch_state() to set > the frontend state to XenbusStateInitialised. Oh, I assumed transactions were required for writing from the kernel to work at all… >> [..] >> >> +static const struct xenbus_device_id virtio_mmio_xen_ids[] = { >> +    { "virtio" }, > > Please use "virtio-mmio" here, as I could imagine "virtio-pci" > devices, too. Ack. Would actually also distinguish it from the initial Arm proof-of-concept version… Thanks, ~val From xen-devel-bounces@lists.xenproject.org Thu Apr 30 05:44:30 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 05:44:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297903.1573596 (Exim 4.92) (envelope-from ) id 1wIKC6-0008T5-EY; Thu, 30 Apr 2026 05:44:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297903.1573596; Thu, 30 Apr 2026 05:44:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIKC6-0008Sx-As; Thu, 30 Apr 2026 05:44:14 +0000 Received: by outflank-mailman (input) for mailman id 1297903; Thu, 30 Apr 2026 03:26:06 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wII2Q-0005Vc-9T for xen-devel@lists.xenproject.org; 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charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: Re: [PATCH RESEND v10 0/8] ACPI: Unify CPU UID interface and fix ARM64 TPH steer-tag issue From: patchwork-bot+linux-riscv@kernel.org Message-Id: <177751951654.2274119.17258357457134506240.git-patchwork-notify@kernel.org> Date: Thu, 30 Apr 2026 03:25:16 +0000 References: <20260401081640.26875-1-fengchengwen@huawei.com> In-Reply-To: <20260401081640.26875-1-fengchengwen@huawei.com> To: Chengwen Feng Cc: linux-riscv@lists.infradead.org, bhelgaas@google.com, catalin.marinas@arm.com, will@kernel.org, rafael@kernel.org, mark.rutland@arm.com, x86@kernel.org, liuyonglong@huawei.com, anshuman.khandual@arm.com, linux-doc@vger.kernel.org, kees@kernel.org, linux-pci@vger.kernel.org, dave.hansen@linux.intel.com, Eric.VanTassell@amd.com, somnath.kotur@broadcom.com, kai.huang@intel.com, kevinloughlin@google.com, punit.agrawal@oss.qualcomm.com, hpa@zytor.com, ilkka@os.amperecomputing.com, kernel@xen0n.name, thorsten.blum@linux.dev, linux-acpi@vger.kernel.org, corbet@lwn.net, masahiroy@kernel.org, si.yanteng@linux.dev, peterz@infradead.org, pawan.kumar.gupta@linux.intel.com, linux-arm-kernel@lists.infradead.org, xen-devel@lists.xenproject.org, szy0127@sjtu.edu.cn, lenb@kernel.org, thomas.lendacky@amd.com, thuth@redhat.com, ryan.roberts@arm.com, darwi@linutronix.de, make24@iscas.ac.cn, suzuki.poulose@arm.com, james.clark@linaro.org, wei.huang2@amd.com, bwicaksono@nvidia.com, loongarch@lists.linux.dev, jonathan.cameron@huawei.com, sohil.mehta@intel.com, boris.ostrovsky@oracle.com, xin@zytor.com, andrew.gospodarek@broadcom.com, wanghuiqiang@huawei.com, jgross@suse.com, wangyuquan1236@phytium.com.cn, seanjc@google.com, guohanjun@huawei.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, linux-perf-users@vger.kernel.org, wangzhou1@hisilicon.com, tglx@kernel.org, heinrich.schuchardt@canonical.com, chenl311@chinatelecom.cn, robin.murphy@arm.com X-purgate-ID: tlsNG-d62444/1777519564-BDE6BFF4-FB18EA95/0/0 X-purgate-type: clean X-purgate-size: 1965 Hello: This series was applied to riscv/linux.git (fixes) by Rafael J. Wysocki : On Wed, 1 Apr 2026 16:16:32 +0800 you wrote: > This patchset unifies ACPI Processor UID retrieval across > arm64/loongarch/riscv/x86 via acpi_get_cpu_uid() (with input validation) > and fixes ARM64 CPU steer-tag retrieval failure in PCI/TPH: > > 1-4: Add acpi_get_cpu_uid() for arm64/loongarch/riscv/x86 (update > respective users) > 5: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h > 6: Clean up perf/arm_cspmu > 7: Clean up ACPI/PPTT and remove unused get_acpi_id_for_cpu() > 8: Pass ACPI Processor UID to Cache Locality _DSM > > [...] Here is the summary with links: - [RESEND,v10,1/8] arm64: acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval https://git.kernel.org/riscv/c/7cd5f5659ac8 - [RESEND,v10,2/8] LoongArch: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval https://git.kernel.org/riscv/c/d78ef9d2e1f2 - [RESEND,v10,3/8] RISC-V: ACPI: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval https://git.kernel.org/riscv/c/0c8231994e43 - [RESEND,v10,4/8] x86/acpi: Add acpi_get_cpu_uid() for unified ACPI CPU UID retrieval https://git.kernel.org/riscv/c/3cfe889f8965 - [RESEND,v10,5/8] ACPI: Centralize acpi_get_cpu_uid() declaration in include/linux/acpi.h https://git.kernel.org/riscv/c/f652d0a4e13c - [RESEND,v10,6/8] perf: arm_cspmu: Switch to acpi_get_cpu_uid() from get_acpi_id_for_cpu() https://git.kernel.org/riscv/c/1ab03189793f - [RESEND,v10,7/8] ACPI: PPTT: Use acpi_get_cpu_uid() and remove get_acpi_id_for_cpu() https://git.kernel.org/riscv/c/a7034e9e4491 - [RESEND,v10,8/8] PCI/TPH: Pass ACPI Processor UID to Cache Locality _DSM https://git.kernel.org/riscv/c/abdd2a86535b You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html From xen-devel-bounces@lists.xenproject.org Thu Apr 30 08:12:00 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 08:12:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297969.1573604 (Exim 4.92) (envelope-from ) id 1wIMUp-0003ud-LM; Thu, 30 Apr 2026 08:11:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297969.1573604; Thu, 30 Apr 2026 08:11:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIMUp-0003uV-H7; Thu, 30 Apr 2026 08:11:43 +0000 Received: by outflank-mailman (input) for mailman id 1297969; Thu, 30 Apr 2026 08:11:42 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIMUo-0003u9-5f for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 08:11:42 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wIMUn-004hyE-FJ for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 10:11:41 +0200 Received: from [10.42.69.12] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f30eb8-bab6-0a2a0a5309dd-0a2a450c85a2-28 for ; Thu, 30 Apr 2026 10:11:41 +0200 Received: from [185.255.28.34] (helo=prod-mta-13.swg-srv.net) by tlsNG-d25034.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f30ebc-62f1-0a2a450c0019-b9ff1c229d73-3 for ; Thu, 30 Apr 2026 10:11:41 +0200 Received: from mail2.vates.fr ([37.26.189.201] mail2.vates.fr) (Authenticated sender: 8631fc262581453bbf619ec5b2062170/smtp/7773de5a-2839-4720-82ee-e06722ae1d3e) by prod-mta-13.swg-srv.net (ZoneMTA - prod-mta-13) with ESMTPSA id 19ddd7187da000f373.006 for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Thu, 30 Apr 2026 08:11:38 +0000 Received: from [192.168.1.18] (88-175-170-134.subs.proxad.net [88.175.170.134]) (Authenticated sender: teddy.astie) by mail2.vates.fr (Postfix) with ESMTPSA id 799C0812E3; Thu, 30 Apr 2026 10:11:37 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=K5BjNIf9tFswbQOeYBUyQT6QRAHcFYHBub2Z81jUwUA=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=jPZTmBGDpHx3CzsFlQeJd9hPGpuHvqcmZ4AVvUiyLEYeHdra+By20dyF4BK2rIs69alylUEjL VL4Sll+7kQhYiYhz2+y+Q+HubVftb2RSYJleBUn3wBsitDOWivyLd/qzNVsO+uvN0Q/lX9x9W2H p1KCvySnTsE9etua52aqtqFsFDK+/XRvg+tVTAOh5dXogf2DS1MqJ/kwq6ocKXj6MiaTCfdI0Qb d432sLkyq0DIQkJBivKg+0Vg0+zMEe/SUhkGgGyl4tQPXH6NeWBiBMEOy7KKEVKBAP52x+kXK4u OyDhZI0MMu9kcO12sG49GTjMnVzzn2U1I7vNliloOuBQ== X-Zone-Loop: 6dcc421ef085fe90b37f11069ea918596341758269d3 x-campaign-type: default x-transaction-id: 4403762b-e761-4f62-98b1-a2a661b111a6 x-swg-uid: 01-a5b5fcde-d16a-4aac-891e-b341eb3a09ef X-Mailer: Sweego Message-ID: <1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373@vates.tech> x-swg-bid: 1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 30 Apr 2026 10:11:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH] virtio-mmio: add xenbus probing To: Val Packett , "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> Content-Language: en-US From: Teddy Astie In-Reply-To: X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.2fd.57a79a2994658d0b.19ddd718549.d4fe0c9720373f89=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777536697674 X-purgate-ID: tlsNG-d25034/1777536701-6E975CF5-37DAD087/0/0 X-purgate-type: clean X-purgate-size: 4998 ---=Part.2fd.57a79a2994658d0b.19ddd718549.d4fe0c9720373f89=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 30/04/2026 =C3=A0 06:06, Val Packett a =C3=A9crit=C2=A0: >=20 > On 4/29/26 11:41 AM, Teddy Astie wrote: >> Hello, >> >> Le 29/04/2026 =C3=A0 16:18, Val Packett a =C3=A9crit=C2=A0: >>> [=E2=80=A6] >>> >>> I've been working on porting virtio-mmio support from Arm to x86_64, >>> with the goal of running vhost-user-gpu to power Wayland/GPU integrati= on >>> for Qubes OS=2E (I'm aware of various proposals for alternative virtio >>> transports but virtio-mmio seems to be the only one that *is* upstream >>> already and just Works=2E=2E) Setting up virtio-mmio through xenbus,= =20 >>> initially >>> motivated just by event channels being the only real way to get=20 >>> interrupts >>> working on HVM, turned out to generally be quite pleasant and nice :) >> Is it HVM specific, or can we also make it work for PVH (we can actuall= y >> attach a ioreq server to PVH guests) ? >=20 > Sorry, typo, I did mean PVH of course! >=20 > I've been testing this with PVH guests + PV dom0, with my PV alloc_ioreq= =20 > fix: > https://lore=2Ekernel=2Eorg/all/20251126062124=2E117425-1-=20 > val@invisiblethingslab=2Ecom/ >=20 > (Time to resend that one as a non-RFC I guess=E2=80=A6) >=20 > HVM actually does have legacy ISA interrupts (which are often used with= =20 > virtio-mmio on KVM), funnily enough, and I've tried firing those from a= =20 > DMOP but that silly thing didn't work properly=2E >=20 >>> I'd like to get some early feedback for this patch, particularly >>> the general stuff: >>> >>> * is this whole thing acceptable in general? >>> * should it be extracted into a different file? >>> * (from the Xen side) any input on the xenstore keys, what goes where? >>> * anything else to keep in mind? >>> >>> It does seem simple enough, so hopefully this can be done? >>> >>> The corresponding userspace-side WIP is available at: >>> https://github=2Ecom/QubesOS/xen-vhost-frontend >>> >>> And the required DMOP for firing the evtchn events will be sent >>> to xen-devel shortly as well=2E >> Could that be done through evtchn_send (or its userland counterpart) ? >=20 > Actually, yes=E2=80=A6 The use of DMOPs is only dictated by the current = Linux=20 > privcmd=2Ec code (the irqfds created by the kernel react to events by=20 > executing HYPERVISOR_dm_op with a stored operation), we can avoid the=20 > need to modify Xen by simply expanding the privcmd driver to make=20 > "evtchn fds"=2E Sounds good, will do=2E >=20 Given that the event channel used by device models is exposed through=20 ioreq=2Evp_eport ("evtchn for notifications to/from device model")=2E I=20 don't think you need to expand the privcmd interface, and you should be=20 able to do this instead : open /dev/xen/evtchn perform IOCTL_EVTCHN_BIND_INTERDOMAIN (for each guest vCPU) with remote_domain=3Dguest_domid, remote_port=3Dioreq=2Evp_eport Then interact with the event channel through IOCTL_EVTCHN_NOTIFY (with=20 local port given by IOCTL_EVTCHN_BIND_INTERDOMAIN) and read/write on the= =20 file descriptor=2E I have some experimental Rust code to work with event channels [1], but=20 I think you can find similar code in multiples places=2E [1] https://github=2Ecom/TSnake41/rust-vmm-xen/blob/redesign-proposal/xen/src/= event/mod=2Ers https://github=2Ecom/TSnake41/rust-vmm-xen/blob/redesign-proposal/xen-unix= /src/event/mod=2Ers >>> [=2E=2E] >>> >>> diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig >>> index ce5bc0d9ea28=2E=2E56bc2b10526b 100644 >>> --- a/drivers/virtio/Kconfig >>> +++ b/drivers/virtio/Kconfig >>> @@ -171,6 +171,13 @@ config VIRTIO_MMIO_CMDLINE_DEVICES >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 If unsure, say 'N'=2E >>> +config VIRTIO_MMIO_XENBUS >>> +=C2=A0=C2=A0=C2=A0 bool "Memory mapped virtio devices parameter parsi= ng" >> that text seems to miss the xenbus aspect > Yep, didn't change that yet, ack >>> [=2E=2E] >> In some way, we're defining a new "PV driver" which is a virtio-mmio >> one, I guess we can eventually specific some form of protocol that >> backend/frontend would need to follow ? >=20 > Right,=C2=A0J=C3=BCrgen mentioned documenting the keys in the xenstore-p= aths doc=2E=2E=20 > would the entire "protocol" (keys + state transition logic) fit into tha= t? >=20 > The keys are currently derived from the initial Arm prototype which=20 > wasn't actually using xenbus properly (the guest driver was configured= =20 > by a device tree node, but the ioreq server used xenstore keys, without= =20 > properly transitioning between states)=2E >=20 >=20 > Thanks, > ~val >=20 >=20 Teddy -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.2fd.57a79a2994658d0b.19ddd718549.d4fe0c9720373f89=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 30 08:43:15 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 08:43:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297987.1573614 (Exim 4.92) (envelope-from ) id 1wIMzC-0008EX-Ty; Thu, 30 Apr 2026 08:43:06 +0000 X-Outflank-Mailman: Message body and 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3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000018.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR12MB9570 X-purgate-ID: tlsNG-4011c0/1777538584-CDD688B7-B24F7951/0/0 X-purgate-type: clean X-purgate-size: 6329 On 29-Apr-26 16:42, Julien Grall wrote: > Hi Michal, > > On 22/04/2026 09:25, Orzel, Michal wrote: >> >> >> On 22/04/2026 09:01, Julien Grall wrote: >>> Hi Michal, >>> >>> On 17/04/2026 10:11, Michal Orzel wrote: >>>> Refactor setup_frametable_mappings() into init_frametable(), modeled >>>> after x86's implementation. Instead of mapping one contiguous frametable >>>> covering ram_start to ram_end (including holes), iterate the >>>> pdx_group_valid bitmap to allocate and map frametable memory only for >>>> valid PDX groups, skipping gaps in the physical address space. At the >>>> moment we don't really take into account pdx_group_valid bitmap. >>>> >>>> This reduces memory consumption on systems with sparse RAM layouts by >>>> not allocating frametable entries for non-existent memory regions. >>>> >>>> A file-local pdx_to_page() override is needed because the generic macro >>>> in xen/include/xen/pdx.h does not account for ARM's non-zero >>>> frametable_base_pdx. >>> >>> Can you provide a bit more details? I am a bit concerned that this could >>> result to subttle bug in the future if code within mm.c is expecting the >>> original behavior. It would be preferable if the change is either for >>> everyone on Arm or the function is renamed to avoid any clash. >> The generic pdx_to_page macro does not account for offset which is something I >> mentioned in the footer and I'm willing to work on in the future. > > Sorry I missed the comment in the footer. But if the function is broken, > then why can't we implement pdx_to_page() correctly now? I understand > that ... I wanted to do this in the future but ok, will do in v2. > > As of today, >> this macro is *unused* on Arm. It's only used by x86 in some special big mem >> related scenario. Using generic pdx_to_page on Arm would be wrong, so a future >> patch doing that would be wrong (the fact that this patch adds a local redefine >> does not change anything). Do we need a rename for a local redefine in a file >> that is only related to frametable? Maybe a comment and a TODO would be ok? > > ... this is not meant to be used by Arm today. But given this is used in > the page list, it is definitely not obvious that it is broken. > > The alternative is to protect/move pdx_to_page() in x86. But I don't > know much churn this would involve. > >> >>> >>> [...] >>> >>>> +void __init init_frametable(paddr_t ram_start) >>>> +{ >>>> + unsigned int sidx, nidx, max_idx; >>>> >>>> /* >>>> * The size of paddr_t should be sufficient for the complete range of >>>> @@ -26,24 +47,34 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) >>>> BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); >>>> BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); >>>> >>>> - if ( frametable_size > FRAMETABLE_SIZE ) >>>> - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", >>>> - ps, pe); >>>> + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); >>>> + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); >>>> >>>> - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); >>>> - /* Round up to 2M or 32M boundary, as appropriate. */ >>>> - frametable_size = ROUNDUP(frametable_size, mapping_size); >>>> - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); >>>> + /* >>>> + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned >>>> + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this >>>> + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of >>>> + * PAGE_SIZE by construction. >>>> + */ >>>> + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); >>>> >>>> - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, >>>> - frametable_size >> PAGE_SHIFT, >>>> - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); >>>> - if ( rc ) >>>> - panic("Unable to setup the frametable mappings.\n"); >>>> + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) >>>> + panic("Frametable too small\n"); >>>> + >>>> + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) >>>> + { >>>> + unsigned int eidx; >>>> + >>>> + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); >>>> + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); >>>> + >>>> + if ( nidx >= max_idx ) >>>> + break; >>>> + >>>> + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); >>> >>> The function will do a round-up the mapping to either a 2MiB or 32MiB >>> aligned size. This means we could potentially cover the previous mapped >>> region or the next one. I can't seem to find any code to cover this >>> use-case. What did I miss? >> Hmm, I think I calculated something wrong here. Anyway, how about using 2MB >> mapping size all the time? PDX group size is 2MB, > > Looking at the code, it seems to be based on SECOND_SHIFT which > technically depends on the page granularity. Even though Xen supports > only 4KiB, we are trying to avoid making such assumption or add least > adding a BUILD_BUG_ON() (in this case, I would consider that > PDX_GROUP_COUNT is always 2MiB or SECOND_SHIFT). > >> in-loop chunks are multiple of >> 2MB, there is no roundup needed - zero overshoot. The last chunk may have ~2MB >> overshoot but it does not matter as there is nothing after it to conflict with. >> The downside is more TLB pressure. > > I am a bit warry to modify the frametable allocation method because it > is used fairly often in Xen. Would it be possible to hence the loop to > detect contiguous chunk and decide the size allocation based on the chunk? To eliminate overshoot I'll round up to page size. In-loop chunks are already page aligned so the round up is a no op except for the last chunk. What we care about is to reduce TLB pressure by setting wherever possible contiguous bit. It's not lost because map_pages_to_xen with block flag handles contiguous internally via xen_pt_check_contig. Will do in v2. ~Michal From xen-devel-bounces@lists.xenproject.org Thu Apr 30 08:49:14 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 08:49:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1297999.1573622 (Exim 4.92) (envelope-from ) id 1wIN53-0000Yv-Jv; Thu, 30 Apr 2026 08:49:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1297999.1573622; Thu, 30 Apr 2026 08:49:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIN53-0000Yo-Gt; Thu, 30 Apr 2026 08:49:09 +0000 Received: by outflank-mailman (input) for mailman id 1297999; Thu, 30 Apr 2026 08:49:08 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIN51-0000Yi-Nr for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 08:49:07 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wIN51-00FgvN-0H for xen-devel@lists.xenproject.org; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> <1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373@vates.tech> Content-Language: en-US From: Val Packett Autocrypt: addr=val@invisiblethingslab.com; keydata= xm8EaFTEiRMFK4EEACIDAwQ+qzawvLuE95iu+QkRqp8P9z6XvFopWtYOaEnYf/nE8KWCnsCD jz82tdbKBpmVOdR6ViLD9tzHvaZ1NqZ9mbrszMXq09VfefoCfZp8jnA2yCT8Y4ykmv6902Ne NnlkVwrNKFZhbCBQYWNrZXR0IDx2YWxAaW52aXNpYmxldGhpbmdzbGFiLmNvbT7CswQTEwkA OxYhBAFMrro+oMGIFPc7Uc87uZxqzalRBQJoVMSJAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMB Ah4HAheAAAoJEM87uZxqzalRlIIBf0cujzfSLhvib9iY8LBh8Tirgypm+hJHoY563xhP0YRS pmqZ6goIuSGpEKcW5mV3egF/TLLAOjsfroWae4giImTVOJvLOsUycxAP4O5b1Qiy+cCGsHKA nCRzrvqnPkyf4OeRznMEaFTEiRIFK4EEACIDAwSffe3tlMmmg3eKVp7SJ+CNZLN0M5qzHSCV dBBkIVvEJo+8SDg4jrx/832rxpvMCz2+x7+OHaeBHKafhOWUccYBLKqV/3nBftxCkbzXDbfY d02BY9H4wBIn0Y3GnwoIXRgDAQkJwpgEGBMJACAWIQQBTK66PqDBiBT3O1HPO7mcas2pUQUC aFTEiQIbDAAKCRDPO7mcas2pUaptAX9f7yUJLGU4C6XjMJvXd8Sz6cGTyxkngPtUyFiNqtad /GXBi3vHKYNfSrdqJ8wmZ8MBgOqWaaa1wE4/3qZU8d4RNR8mF7O40WYK/wdf1ycq1uGad8PN UDOwAqdfvuF3w8QMPw== In-Reply-To: <1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373@vates.tech> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-ebf023/1777538946-328753FF-D2D1B605/0/0 X-purgate-type: clean X-purgate-size: 4389 On 4/30/26 5:11 AM, Teddy Astie wrote: > Le 30/04/2026 à 06:06, Val Packett a écrit : >> On 4/29/26 11:41 AM, Teddy Astie wrote: >>> Hello, >>> >>> Le 29/04/2026 à 16:18, Val Packett a écrit : >>>> […] >>>> >>>> I've been working on porting virtio-mmio support from Arm to x86_64, >>>> with the goal of running vhost-user-gpu to power Wayland/GPU integration >>>> for Qubes OS. (I'm aware of various proposals for alternative virtio >>>> transports but virtio-mmio seems to be the only one that *is* upstream >>>> already and just Works..) Setting up virtio-mmio through xenbus, >>>> initially >>>> motivated just by event channels being the only real way to get >>>> interrupts >>>> working on HVM, turned out to generally be quite pleasant and nice :) >>> Is it HVM specific, or can we also make it work for PVH (we can actually >>> attach a ioreq server to PVH guests) ? >> Sorry, typo, I did mean PVH of course! >> >> I've been testing this with PVH guests + PV dom0, with my PV alloc_ioreq >> fix: >> https://lore.kernel.org/all/20251126062124.117425-1- >> val@invisiblethingslab.com/ >> >> (Time to resend that one as a non-RFC I guess…) >> >> HVM actually does have legacy ISA interrupts (which are often used with >> virtio-mmio on KVM), funnily enough, and I've tried firing those from a >> DMOP but that silly thing didn't work properly. >> >>>> I'd like to get some early feedback for this patch, particularly >>>> the general stuff: >>>> >>>> * is this whole thing acceptable in general? >>>> * should it be extracted into a different file? >>>> * (from the Xen side) any input on the xenstore keys, what goes where? >>>> * anything else to keep in mind? >>>> >>>> It does seem simple enough, so hopefully this can be done? >>>> >>>> The corresponding userspace-side WIP is available at: >>>> https://github.com/QubesOS/xen-vhost-frontend >>>> >>>> And the required DMOP for firing the evtchn events will be sent >>>> to xen-devel shortly as well. >>> Could that be done through evtchn_send (or its userland counterpart) ? >> Actually, yes… The use of DMOPs is only dictated by the current Linux >> privcmd.c code (the irqfds created by the kernel react to events by >> executing HYPERVISOR_dm_op with a stored operation), we can avoid the >> need to modify Xen by simply expanding the privcmd driver to make >> "evtchn fds". Sounds good, will do. >> > Given that the event channel used by device models is exposed through > ioreq.vp_eport ("evtchn for notifications to/from device model"). I > don't think you need to expand the privcmd interface, and you should be > able to do this instead : > > open /dev/xen/evtchn > perform IOCTL_EVTCHN_BIND_INTERDOMAIN (for each guest vCPU) > with remote_domain=guest_domid, remote_port=ioreq.vp_eport > > Then interact with the event channel through IOCTL_EVTCHN_NOTIFY (with > local port given by IOCTL_EVTCHN_BIND_INTERDOMAIN) and read/write on the > file descriptor. So the reason there's currently an ioctl to bind an eventfd to fire a stored DMOP is that the whole idea is to (efficiently!) support generic, hypervisor-neutral device server implementations via the vhost-user protocol. Now of course, the current implementation isn't *entirely* hypervisor-neutral as e.g. the vm-memory Rust crate (inside of the "neutral" vhost-user device servers) does need to be built with the `xen` feature. But still, that's how it works. What can be made generic is generic. xen-vhost-frontend, which is the thing that integrates these with Xen, actually used to handle the interrupts in userspace[1] by firing the DMOP itself (which is where I could "just replace that with IOCTL_EVTCHN_NOTIFY") but that was offloaded to the kernel with the introduction of IOCTL_PRIVCMD_IRQFD[2], similarly to KVM_IRQFD. Switching back to handling the eventfd in userspace would be a literal deoptimization :) While throwing away the whole generic layer to do a fully integrated use-case-specific thing sounds more difficult/tedious than this, and not necessarily desirable in general. [1]: https://github.com/vireshk/xen-vhost-frontend/commit/06d59035f8a387c0f600931d09dfaa27b80ede7f [2]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=f8941e6c4c712948663ec5d7bbb546f1a0f4e3f6 ~val From xen-devel-bounces@lists.xenproject.org Thu Apr 30 09:56:07 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 09:56:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298018.1573630 (Exim 4.92) (envelope-from ) id 1wIO7b-0001U0-8i; Thu, 30 Apr 2026 09:55:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298018.1573630; Thu, 30 Apr 2026 09:55:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIO7b-0001Tt-5U; Thu, 30 Apr 2026 09:55:51 +0000 Received: by outflank-mailman (input) for mailman id 1298018; Thu, 30 Apr 2026 09:55:49 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIO7Z-0001Tn-HV for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 09:55:49 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wIO7Y-008RTU-Iq for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 11:55:48 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f32722-2eae-0a2a0a5409dd-0a2a45089662-24 for ; Thu, 30 Apr 2026 11:55:48 +0200 Received: from [209.85.221.46] (helo=mail-wr1-f46.google.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f32724-63b5-0a2a45080019-d155dd2eb5d9-3 for ; Thu, 30 Apr 2026 11:55:48 +0200 Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-43d73352cf2so630730f8f.1 for ; Thu, 30 Apr 2026 02:55:48 -0700 (PDT) Received: from localhost.localdomain (5.116.208.46.dyn.plus.net. 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Signed-off-by: Frediano Ziglio --- tools/include/xenctrl.h | 5 +++++ tools/libs/ctrl/xc_netbsd.c | 9 ++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h index d5dbf69c89..f4316089e7 100644 --- a/tools/include/xenctrl.h +++ b/tools/include/xenctrl.h @@ -1390,6 +1390,11 @@ int xc_lockprof_query(xc_interface *xch, uint64_t *time, xc_hypercall_buffer_t *data); +/** + * Allocate memory with a given alignment. + * The alignment must be a power of 2 and at least sizeof(void*). + * It returns NULL on error, errno is not set. + */ void *xc_memalign(xc_interface *xch, size_t alignment, size_t size); /** diff --git a/tools/libs/ctrl/xc_netbsd.c b/tools/libs/ctrl/xc_netbsd.c index 1318d4d906..d27154dce9 100644 --- a/tools/libs/ctrl/xc_netbsd.c +++ b/tools/libs/ctrl/xc_netbsd.c @@ -60,7 +60,14 @@ void discard_file_cache(xc_interface *xch, int fd, int flush) void *xc_memalign(xc_interface *xch, size_t alignment, size_t size) { - return valloc(size); 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On Thu, Apr 30, 2026 at 10:55:21AM +0100, Frediano Ziglio wrote: > More similar to other implementation. > posix_memalign was adde in NetBSD 8.0, released on July 17, 2018 > and went out of support on May 4, 2024. > > Signed-off-by: Frediano Ziglio > --- > tools/include/xenctrl.h | 5 +++++ > tools/libs/ctrl/xc_netbsd.c | 9 ++++++++- > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h > index d5dbf69c89..f4316089e7 100644 > --- a/tools/include/xenctrl.h > +++ b/tools/include/xenctrl.h > @@ -1390,6 +1390,11 @@ int xc_lockprof_query(xc_interface *xch, > uint64_t *time, > xc_hypercall_buffer_t *data); > > +/** > + * Allocate memory with a given alignment. > + * The alignment must be a power of 2 and at least sizeof(void*). > + * It returns NULL on error, errno is not set. > + */ > void *xc_memalign(xc_interface *xch, size_t alignment, size_t size); > > /** > diff --git a/tools/libs/ctrl/xc_netbsd.c b/tools/libs/ctrl/xc_netbsd.c > index 1318d4d906..d27154dce9 100644 > --- a/tools/libs/ctrl/xc_netbsd.c > +++ b/tools/libs/ctrl/xc_netbsd.c > @@ -60,7 +60,14 @@ void discard_file_cache(xc_interface *xch, int fd, int flush) > > void *xc_memalign(xc_interface *xch, size_t alignment, size_t size) > { > - return valloc(size); > + int ret; > + void *ptr; > + > + ret = posix_memalign(&ptr, alignment, size); > + if (ret != 0 || !ptr) > + return NULL; > + > + return ptr; > } > > int xc_pcidev_get_gsi(xc_interface *xch, uint32_t sbdf) > -- > 2.43.0 > From xen-devel-bounces@lists.xenproject.org Thu Apr 30 11:47:35 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 11:47:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298074.1573649 (Exim 4.92) (envelope-from ) id 1wIPrR-000861-9o; Thu, 30 Apr 2026 11:47:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298074.1573649; Thu, 30 Apr 2026 11:47:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIPrR-00085u-6v; Thu, 30 Apr 2026 11:47:17 +0000 Received: by outflank-mailman (input) for mailman id 1298074; Thu, 30 Apr 2026 11:47:15 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIPrP-00084H-Pr for xen-devel@lists.xenproject.org; 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From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper , Teddy Astie Subject: [PATCH] x86/cpu: identify uninitialized CPU data using BAD_APICID Date: Thu, 30 Apr 2026 13:46:47 +0200 Message-ID: <20260430114647.94526-1-roger.pau@citrix.com> X-Mailer: git-send-email 2.53.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BN9PR03CA0547.namprd03.prod.outlook.com (2603:10b6:408:138::12) To BY1PR03MB7875.namprd03.prod.outlook.com (2603:10b6:a03:5b1::10) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PR03MB7875:EE_|SJ0PR03MB5503:EE_ X-MS-Office365-Filtering-Correlation-Id: a85daa8b-4bb4-4704-8842-08dea6ae366a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: Bh17C8oRjEY0POg5b8Vhz90BO+Kren+bH6h1/bjf//peZPBb0g64zDlHxOgxGHcbJrJe3g6sM19OzLDCjENgdVcobk0Jd6XQE1hRTL3dQbhkyV9l5f4g300xSfczLn1P684IaNnnuqy8bTMzCvQT2D+MgfA5+PemZ27HTQ7198rcC8nzX0Pxm1o1L6DpYecclsZ6mpG4pnP4VGW8+Ui3reNjA4qaXCez/EfjGK60ADeyxwYH4OXNvt+bzk3X1E/EI4aUbhwlRbZNpP7UaaHHyfowafJfs6o4sikE/Gfiszcq8oc7xla2tv9Q5x1z2MD313v2Ul5B8QmUxh0vwN83DniAcK6LkFmzeGqQZgiUkW3g90Bf4RY+88DxtMu6eoh9Ijxr5AqkNkMg+Mb/iSrGm9X7mT3DNfvnsEARf8oeCkh2FwvnzOXKYNOvCq9bT+tJ04JaAOz8/Oeam8bhnLEZK+26iGOxlV54YtiRExeRNdwur0yqkblULOh3LRB0a6r5PTqLJYPdJQvNhPohIvvuHosKvmCUdAR7AMZWqVL680we94fOCcMmhINveNsYYnYKI0xpdvzP/RGD6iOQNleeokVIUJmruILoEtgy6ttH8mKO1CehZUdS52s707TI9OaPONiIQIteimD2nC+69XEktEBDQN0BqwCP2WKDNrcPn4YCf44RuU31QzyrnIyasPMyr6cVQXOZtJc5DwcaPq5rN6ihgDPft0cEegXwXXcM9N8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BY1PR03MB7875.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(366016)(1800799024)(18002099003)(56012099003);DIR:OUT;SFP:1101; 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Fix the check in cpu_smpboot_free() to use the correct condition. Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]") Signed-off-by: Roger Pau Monné --- xen/arch/x86/smpboot.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index 491cbbba33ae..ff05955bae40 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -961,8 +961,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool remove) * In that case the socket number cannot be relied upon, but the respective * socket_cpumask[] slot also wouldn't have been set. */ - if ( c[cpu].apicid != boot_cpu_data.apicid && - cpumask_empty(socket_cpumask[socket]) ) + if ( c[cpu].apicid != BAD_APICID && cpumask_empty(socket_cpumask[socket]) ) { xfree(socket_cpumask[socket]); socket_cpumask[socket] = NULL; -- 2.53.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 30 12:19:55 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 12:19:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298117.1573657 (Exim 4.92) (envelope-from ) id 1wIQMt-0004Sn-UK; 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dkim=pass header.s=selector1 header.d=vates.tech header.i="@vates.tech" header.h="From:Subject:Date:Message-ID:To:Cc:MIME-Version:Content-Type:In-Reply-To:References:Feedback-ID" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; q=dns/txt; s=selector1; bh=5PJuoDO+IUJP94Y/AXxtsVNhqUs4q7DPJAsExb/x+N0=; h=from:subject:date:message-id:to:cc:mime-version:content-type:in-reply-to:references:feedback-id; b=X6ImDpdSlSZ/QUNiwMHHn9fHL0Vr46MLc6ZdcxOWhGHBBtY1vXU3aaWUXjji28Agu4znS1UVb dwZObq5oYXrxgyhhq/jfRorTPJKHIPgCGVkViiMSHH8mylGoh6toem5V9WQeG+fzDHU21MdLaSE joRLETVTgF2OPGGQUoMqNp6aiRgKqnf4LNTNoR8KiXbf11tu1sCGwckgUjPQqSX2wFPjSQCbwg5 PU/tPPh3lje7s0uxOWImwLF6XFPiwVE/zgug7v0h5vRPiBYZ78UGvjltB92A7AzWO2ZuBA5q6on Puc8E+ghUNKy9Li8JCH7FS2Q88BtybNZZ+CZ4nuCb2jQ== X-Zone-Loop: cd6d33d4832819ab798166a8883d56bb43d39a62e49c x-campaign-type: default x-transaction-id: f8d55d72-40fc-4ef1-a2fa-f74c28736ab1 x-swg-uid: 01-34ca0fdd-52e2-4b54-a34c-214c960750d8 X-Mailer: Sweego Message-ID: <1777551581.8631fc262581453bbf619ec5b2062170.19dde54a2a9000f373@vates.tech> x-swg-bid: 1777551581.8631fc262581453bbf619ec5b2062170.19dde54a2a9000f373 Feedback-ID: default:8631fc262581453bbf619ec5b2062170:Sweego x-campaign-id: default x-client-id: 8631fc262581453bbf619ec5b2062170 X-Originating-IP: [37.26.189.201] Date: Thu, 30 Apr 2026 14:19:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/cpu: identify uninitialized CPU data using BAD_APICID To: Roger Pau Monne , xen-devel@lists.xenproject.org Cc: Jan Beulich , Andrew Cooper References: <20260430114647.94526-1-roger.pau@citrix.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <20260430114647.94526-1-roger.pau@citrix.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.363.4a99b96f1ae4c136.19dde54a08b.938d6b25e654684b=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777551581324 X-purgate-ID: tlsNG-c1860d/1777551585-C2776DB1-EDB6AFE7/0/0 X-purgate-type: clean X-purgate-size: 1636 ---=Part.363.4a99b96f1ae4c136.19dde54a08b.938d6b25e654684b=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 30/04/2026 =C3=A0 13:47, Roger Pau Monne a =C3=A9crit=C2=A0: > Uninitialized cpu_data[]=C2=A0entries have the apicid field set to BAD_A= PICID, > not boot_cpu_data=2Eapicid=2E Fix the check in cpu_smpboot_free() to us= e the > correct condition=2E >=20 > Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]") > Signed-off-by: Roger Pau Monn=C3=A9 > --- > xen/arch/x86/smpboot=2Ec | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) >=20 > diff --git a/xen/arch/x86/smpboot=2Ec b/xen/arch/x86/smpboot=2Ec > index 491cbbba33ae=2E=2Eff05955bae40 100644 > --- a/xen/arch/x86/smpboot=2Ec > +++ b/xen/arch/x86/smpboot=2Ec > @@ -961,8 +961,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool = remove) > * In that case the socket number cannot be relied upon, but the r= espective > * socket_cpumask[] slot also wouldn't have been set=2E > */ > - if ( c[cpu]=2Eapicid !=3D boot_cpu_data=2Eapicid && > - cpumask_empty(socket_cpumask[socket]) ) > + if ( c[cpu]=2Eapicid !=3D BAD_APICID && cpumask_empty(socket_cpumas= k[socket]) ) > { > xfree(socket_cpumask[socket]); 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v2 2/2] xen/arm: skip holes in physical address space when setting up frametable Date: Thu, 30 Apr 2026 14:51:03 +0200 Message-ID: <20260430125103.401811-3-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430125103.401811-1-michal.orzel@amd.com> References: <20260430125103.401811-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3F:EE_|DS5PPF23E22D637:EE_ X-MS-Office365-Filtering-Correlation-Id: bde2a835-c25d-402c-bbe9-08dea6b72fd1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|376014|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: cM31aXSWWhzVuT3q9bs3ZAH9jzM2GuN4l3/Cjc2emCjR5n9nKlAEwLTEgDyhUbujSEQvZRfjfpI6HFsm1XxDD2iniUKtYwRmQPiu5xHVKQVtYSazkLpOOBLWBtGTusCGiyxrHWPRY1A7i/4sLNwT8XUiz8M0kDR5Gx2rr7sxE0aZM+BQ9tS4pP5doP5Z+KrKqYgNPrAVkBqLCgG79MRTDMHcebV9Yl2zLoa4km6RoXwwUhFj4W6BGu3f1IIkknAge3CKZvHjhk7bEXcbSiBcHuCghObvqw65iRMg4A+VfjwHa9devl22IzRaaEfpwAInk7f8PEAEO4n3ko2MQDcPYgw8/t/TglanWMsY7PSAzFGRBbbI5D1xbEuO782KodlI5Ne+oka83u+t1FQfwR3+Rnb6t+iBBsHmk1b3vLf3sgp+e23j/wlfwjtlco622kcIIdLh/CeL4Fw4bW7oE1qtck3IaykDD6ZV4mqXJLAVeruS+FrF3vLLNMTzt2D1jGiBL9xZIJ3ak4Pgrvg1KVkvvb5hqk7yRBNvKQA5YW3CaOJclytp1piJ3X32xzMmhW8jXNa1rOgaVmiuLTXmIP/hu/42Gg3I/DM7Uu53zXRIYEGeK5HYuwhJUxWksLhiMFkrQAOIlBJPQRPCwkgrEZFJhXs5MfFbLZEYEWXejBfyvIH1loyuWxQbwFlJLtvdFkUcej2cL6VvCuyT3XJ7DtsajQCEIWnWxAYToSBvP9j8oNYBYFs4Ll6CnnO/qrYVaU3v6ixm3+vzXNMiIGEdtdkKmw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(376014)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3xnPnRcNv+ncophZaaD9E57UXC7Nh2oAQNQCA5dsHiUk7abr8DJtnbe/Tyij3EkKvHUKZbryFR8wFEV6j0oW2g+Oca5DPsUBXBiDqZGvGesGQWsPZEYJlTmAUzcnOScwh6spyXPlJ77SkVbB11yntHQhGl9/NjSuEwLUdOt5CibiiIZkWUkr/4ZiAxDgZq3Lk8KHKH5Q/U8+3/eApmJP6Kd8RAgMTA4XvvYxJdB1+THUgqqBhmtvwORYgKNTbNPunqWpk+A+R780uksPf/a4Ki36/Fl8oOtzKp+Wx9TZ/6nfHHKL0/vFL8Z5WovSnhfgYL9q8QNZAQWkcUJfi3xyeoNSDTbuh4Gryv4ETG0Ia8zMXDk4jubeBTORspsZ+PmCvuKtX2mwuSduzXD75ZcALaiCD9jpzrdTGAEcIi73+dnvhCoZla2stcIhnY+pRzvL X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 12:51:24.3586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bde2a835-c25d-402c-bbe9-08dea6b72fd1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF23E22D637 X-purgate-ID: tlsNG-d25034/1777553493-6C965CF5-70E86224/0/0 X-purgate-type: clean X-purgate-size: 10032 Refactor setup_frametable_mappings() into init_frametable(), modeled after x86's implementation. Instead of mapping one contiguous frametable covering ram_start to ram_end (including holes), iterate the pdx_group_valid bitmap to allocate and map frametable memory only for valid PDX groups, skipping gaps in the physical address space. At the moment we don't really take into account pdx_group_valid bitmap. This reduces memory consumption on systems with sparse RAM layouts by not allocating frametable entries for non-existent memory regions. The chunk allocator rounds chunk_size up to PAGE_SIZE only, rather than to a larger mapping granularity, to avoid overshooting past chunk boundaries into subsequent gaps or valid regions. This rounding has no impact for in-loop chunks given that chunk size is multiple of 14MB on Arm64 and 2MB on Arm32. The rounding matters only for the last out-of-loop chunk. Physical allocations use 32MB alignment so that map_pages_to_xen() can use the contiguous bit for larger TLB entries where virtual alignment also permits. Update the MPU implementation to match the new init_frametable() signature. Since MPU has no virtual address translation (ma == va), hole-skipping is not possible and the frametable remains a single contiguous allocation. Signed-off-by: Michal Orzel --- Changes in v2: - fix overshoot problem with 32MB rounding --- xen/arch/arm/arm32/mmu/mm.c | 3 +- xen/arch/arm/include/asm/mm.h | 4 +- xen/arch/arm/mm.c | 2 +- xen/arch/arm/mmu/mm.c | 89 ++++++++++++++++++++++++++--------- xen/arch/arm/mpu/mm.c | 23 ++++----- 5 files changed, 82 insertions(+), 39 deletions(-) diff --git a/xen/arch/arm/arm32/mmu/mm.c b/xen/arch/arm/arm32/mmu/mm.c index 5e4766ddcf65..0b595baa11b3 100644 --- a/xen/arch/arm/arm32/mmu/mm.c +++ b/xen/arch/arm/arm32/mmu/mm.c @@ -178,8 +178,7 @@ void __init setup_mm(void) setup_directmap_mappings(mfn_x(directmap_mfn_start), xenheap_pages); - /* Frame table covers all of RAM region, including holes */ - setup_frametable_mappings(ram_start, ram_end); + init_frametable(ram_start); /* * The allocators may need to use map_domain_page() (such as for diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 8180b1e12baf..2616a1305d58 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -191,8 +191,8 @@ extern void *early_fdt_map(paddr_t fdt_paddr); extern void remove_early_mappings(void); /* Prepare the memory subystem to bring-up the given secondary CPU */ extern int prepare_secondary_mm(int cpu); -/* Map a frame table to cover physical addresses ps through pe */ -extern void setup_frametable_mappings(paddr_t ps, paddr_t pe); +/* Map a frame table */ +void init_frametable(paddr_t ram_start); /* Helper function to setup memory management */ void setup_mm_helper(void); /* map a physical range in virtual memory */ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index faef0efb327c..7297cca01551 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -63,7 +63,7 @@ void __init setup_mm(void) setup_mm_helper(); - setup_frametable_mappings(ram_start, ram_end); + init_frametable(ram_start); init_staticmem_pages(); init_sharedmem_pages(); diff --git a/xen/arch/arm/mmu/mm.c b/xen/arch/arm/mmu/mm.c index 6604f3bf4e6a..dfc888c8ee0e 100644 --- a/xen/arch/arm/mmu/mm.c +++ b/xen/arch/arm/mmu/mm.c @@ -6,18 +6,45 @@ #include #include #include +#include #include -/* Map a frame table to cover physical addresses ps through pe */ -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) +static void __init init_frametable_chunk(unsigned long pdx_s, + unsigned long pdx_e) { - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) - - mfn_to_pdx(maddr_to_mfn(ps)) + 1; - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); - mfn_t base_mfn; - const unsigned long mapping_size = frametable_size < MB(32) ? MB(2) - : MB(32); + unsigned long nr_pdxs = pdx_e - pdx_s; + unsigned long chunk_size = nr_pdxs * sizeof(struct page_info); + unsigned long virt; int rc; + mfn_t base_mfn; + + /* + * In-loop chunks span whole PDX groups, which are always page-size + * aligned. The last chunk ending at max_pdx may not be, so round up. + */ + chunk_size = ROUNDUP(chunk_size, PAGE_SIZE); + + /* + * Align the allocation to the contiguous mapping size so that + * map_pages_to_xen() can use the contiguous bit. + */ + base_mfn = alloc_boot_pages(chunk_size >> PAGE_SHIFT, + MB(32) >> PAGE_SHIFT); + + virt = (unsigned long)pdx_to_page(pdx_s); + rc = map_pages_to_xen(virt, base_mfn, chunk_size >> PAGE_SHIFT, + PAGE_HYPERVISOR_RW | _PAGE_BLOCK); + if ( rc ) + panic("Unable to setup the frametable mappings\n"); + + memset(pdx_to_page(pdx_s), 0, nr_pdxs * sizeof(struct page_info)); + memset(pdx_to_page(pdx_e), -1, + chunk_size - nr_pdxs * sizeof(struct page_info)); +} + +void __init init_frametable(paddr_t ram_start) +{ + unsigned int sidx, nidx, max_idx; /* * The size of paddr_t should be sufficient for the complete range of @@ -26,24 +53,40 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); - if ( frametable_size > FRAMETABLE_SIZE ) - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", - ps, pe); + /* init_frametable_chunk() allocation alignment assumes 4KB granule */ + BUILD_BUG_ON(PAGE_SIZE != SZ_4K); - frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ps)); - /* Round up to 2M or 32M boundary, as appropriate. */ - frametable_size = ROUNDUP(frametable_size, mapping_size); - base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 32<<(20-12)); + /* In-loop chunks must produce page-aligned frametable regions */ + BUILD_BUG_ON((PDX_GROUP_COUNT * sizeof(struct page_info)) % PAGE_SIZE); - rc = map_pages_to_xen(FRAMETABLE_VIRT_START, base_mfn, - frametable_size >> PAGE_SHIFT, - PAGE_HYPERVISOR_RW | _PAGE_BLOCK); - if ( rc ) - panic("Unable to setup the frametable mappings.\n"); + max_idx = DIV_ROUND_UP(max_pdx, PDX_GROUP_COUNT); + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); + + /* + * pdx_to_page(pdx_s) in init_frametable_chunk must be page-aligned + * for map_pages_to_xen(). Aligning to PDX_GROUP_COUNT guarantees this + * because PDX_GROUP_COUNT * sizeof(page_info) is always a multiple of + * PAGE_SIZE by construction. + */ + frametable_base_pdx = ROUNDDOWN(frametable_base_pdx, PDX_GROUP_COUNT); + + if ( (max_pdx - frametable_base_pdx) > FRAMETABLE_NR ) + panic("Frametable too small\n"); + + for ( sidx = (frametable_base_pdx / PDX_GROUP_COUNT); ; sidx = nidx ) + { + unsigned int eidx; + + eidx = find_next_zero_bit(pdx_group_valid, max_idx, sidx); + nidx = find_next_bit(pdx_group_valid, max_idx, eidx); + + if ( nidx >= max_idx ) + break; + + init_frametable_chunk(sidx * PDX_GROUP_COUNT, eidx * PDX_GROUP_COUNT); + } - memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info)); - memset(&frame_table[nr_pdxs], -1, - frametable_size - (nr_pdxs * sizeof(struct page_info))); + init_frametable_chunk(sidx * PDX_GROUP_COUNT, max_pdx); } /* diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c index aff88bd3a9c1..9c568831c128 100644 --- a/xen/arch/arm/mpu/mm.c +++ b/xen/arch/arm/mpu/mm.c @@ -186,16 +186,15 @@ static int is_mm_attr_match(pr_t *region, unsigned int attributes) return 0; } -/* Map a frame table to cover physical addresses ps through pe */ -void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) +/* + * Allocate a contiguous frame table covering ram_start through max_pdx. + * Unlike the MMU version, MPU cannot skip holes because there is no virtual + * address translation (ma == va). + */ +void __init init_frametable(paddr_t ram_start) { + unsigned long nr_pdxs, frametable_size; mfn_t base_mfn; - paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE); - paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE); - - unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) - - mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1; - unsigned long frametable_size = nr_pdxs * sizeof(struct page_info); /* * The size of paddr_t should be sufficient for the complete range of @@ -204,11 +203,13 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS); BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE); + frametable_base_pdx = mfn_to_pdx(maddr_to_mfn(ram_start)); + nr_pdxs = max_pdx - frametable_base_pdx; + frametable_size = nr_pdxs * sizeof(struct page_info); + if ( frametable_size > FRAMETABLE_SIZE ) - panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n", - ps, pe); + panic("Frametable too small\n"); - frametable_base_pdx = paddr_to_pdx(aligned_ps); frametable_size = ROUNDUP(frametable_size, PAGE_SIZE); base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1); -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 30 12:51:52 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 12:51:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298143.1573669 (Exim 4.92) (envelope-from ) id 1wIQrZ-0001L6-Av; Thu, 30 Apr 2026 12:51:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298143.1573669; Thu, 30 Apr 2026 12:51:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIQrZ-0001Kz-6o; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Timothy Pearson , Teddy Astie Subject: [PATCH v2 0/2] xen/arm: Improve frametable allocation Date: Thu, 30 Apr 2026 14:51:01 +0200 Message-ID: <20260430125103.401811-1-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3F:EE_|MN2PR12MB4062:EE_ X-MS-Office365-Filtering-Correlation-Id: bbb50426-da8b-4e96-38a0-08dea6b72d34 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|1800799024|36860700016|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: dwfnOdnChf771PXpbMcahIfPZ8xDhA68Pdan1YDF5Mc66umpSsjMbMlnqv68sQoHSN2oqqcX14I4JdrMmGLTF7EKKhrnSwiQXhNdsN4ZU9rLvhx+Bw1y5lorUzoFqER3scNXIOdFZulu2N15UR72/540DLHJHHvrLvjXWOjl4qS9iX+kE5QO77z3QApmSd8aHc9d1DJqBkXdOmtKlsXjtlf2CM2e0FEGD+uEtWrOwG9sD1gSSzYj6y899v7ScyyJtWQV/67XmIIgAVuZYmkifg1wadW8NgbokRPXrugp9GZ+Lnk6e+YbZ6N4Aj4Fonsoin85oWggjKdJ8mvPvBNttWz9C5bn9u57BiZOw5sZWJp5WwP8Ks3n8A/BdOuOi4Fus39QjqqqnpwAEtRW5s1jt+Wdb4m+8cDMN45Byg3Dy9Ur78RRtx28NjokLak59nKLjeaiPWBffkpdw7FqUtq/+mtV0TRjE1zJnsXWL9XxQRdVe5WdNFnh93E235BOqckCqL2wCsq60vnegxcfzpvG0WEV89XOZvtkhsI+b7Iq9r8tJ5SpOo3WeK9xF9WFz8O9svod0kcSHU3DWATZeYJxK+1Hx+TC6tNPZf57JbvZ3js3SoiV7kJ6ZovXa17Knxg3uFcNncGcGk9jkhnl1QPCqMwN6tA+PqqvPNH2SKqQgRCyZwsRx8EYR1CUG6qxFUb1aZUJGrUoxL7Abu7aCLqZFIw2ga1ruNcTyK0ypmwpjIJmCymmGjqIw69z8Mx+aizhAWZIeR55yQLwOp/AlCz4tA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(376014)(1800799024)(36860700016)(56012099003)(18002099003);DIR:OUT;SFP:1101; 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pr=C From: Michal Orzel To: CC: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Timothy Pearson , Teddy Astie Subject: [PATCH v2 1/2] xen/pdx: account for frametable_base_pdx in generic pdx_to_page/page_to_pdx Date: Thu, 30 Apr 2026 14:51:02 +0200 Message-ID: <20260430125103.401811-2-michal.orzel@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430125103.401811-1-michal.orzel@amd.com> References: <20260430125103.401811-1-michal.orzel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|IA1PR12MB7663:EE_ X-MS-Office365-Filtering-Correlation-Id: d4c39c95-59b2-40c3-3ee6-08dea6b72ec9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|22082099003|18002099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9KK/JxHke4udpLXmUFB4bhTAtPqsoJmFoFTIGwkRwnE5ARcEPXTKwWp14914me/d33m1OtZen1aTREMnFLVBhh4MZZAc1rizClm6oiEeteZ1nGlHl9DE2SsdiDnthi0VlL2Rl9DB33BZJsqNxW5tJP3Y3QMZjsog3UuvASjy0A4Njpl58Kw0rCA/JVEfUwq0hG1bmqDTZIMA4hDRL8Q5B3ZdRgbf5k2TQwJTuWbLAWz/y63Nx6kYWxxwR8kMFoHkFexloibo7++imFVBzZy0TQv60QgQM5IeBGbjv8XuiE0UL+qy0SxRZQAY3u3ahjRCLpJGdpcyDvwnRwQ9jnI0ZnrmwAYbF3Q8/6sbJG14DQ6rMTP41Fq3o8alfVCns7v+2Umk9zMjukWPM9EZXxU90VOi4JVs4I7etlOTVN+I01Ak5PKap7Cbmyv0FxHip/e4 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 12:51:22.6925 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4c39c95-59b2-40c3-3ee6-08dea6b72ec9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7663 X-purgate-ID: tlsNG-720697/1777553489-B2969161-826374CE/0/0 X-purgate-type: clean X-purgate-size: 7403 The generic pdx_to_page() and page_to_pdx() macros in xen/pdx.h assume the frame table starts at PDX 0, which is only true on x86. ARM uses a non-zero frametable_base_pdx to offset into the frame table (PPC also defines it). Fix the generic macros to subtract/add frametable_base_pdx, defaulting to 0 when the arch does not define it. This makes the generic macros correct for all architectures, even though they are only used on x86 today. While at it, consolidate the arch-specific PDX definitions (frametable_base_pdx and PDX_GROUP_SHIFT) from the arch mm.h headers into new asm/pdx.h headers for ARM and PPC. The asm/pdx.h is included earlier in xen/pdx.h via __has_include, making these definitions available before they are needed. Also decouple the __has_include() check from the PFN-to-PDX translation override mechanism. Previously, the existence of asm/pdx.h was taken to mean the arch provides custom pdx_to_pfn / pfn_to_pdx implementations. This conflation would prevent ARM and PPC from having asm/pdx.h (for frametable_base_pdx) without also being forced to define the translation helpers. Replace the __has_include gate with an explicit ARCH_DEFINES_PDX_XLATE sentinel that only x86 defines. No functional change. Signed-off-by: Michal Orzel --- Changes in v2: - new patch --- xen/arch/arm/include/asm/mm.h | 5 ----- xen/arch/arm/include/asm/pdx.h | 21 +++++++++++++++++++++ xen/arch/arm/mm.c | 1 + xen/arch/ppc/include/asm/mm.h | 5 ----- xen/arch/ppc/include/asm/pdx.h | 12 ++++++++++++ xen/arch/ppc/mm-radix.c | 1 + xen/arch/x86/include/asm/pdx.h | 6 ++++++ xen/include/xen/pdx.h | 17 ++++++++++++----- 8 files changed, 53 insertions(+), 15 deletions(-) create mode 100644 xen/arch/arm/include/asm/pdx.h create mode 100644 xen/arch/ppc/include/asm/pdx.h diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index 72a692862420..8180b1e12baf 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -181,11 +181,6 @@ struct page_info #define maddr_get_owner(ma) (page_get_owner(maddr_to_page((ma)))) -/* PDX of the first page in the frame table. */ -extern unsigned long frametable_base_pdx; - -#define PDX_GROUP_SHIFT SECOND_SHIFT - /* Boot-time pagetable setup */ extern void setup_pagetables(void); /* Check that the mapping flag has no W and X together */ diff --git a/xen/arch/arm/include/asm/pdx.h b/xen/arch/arm/include/asm/pdx.h new file mode 100644 index 000000000000..651df4b210dc --- /dev/null +++ b/xen/arch/arm/include/asm/pdx.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef ARM_PDX_H +#define ARM_PDX_H + +#include + +#define PDX_GROUP_SHIFT SECOND_SHIFT + +#define ARCH_HAS_FRAMETABLE_BASE_PDX +extern unsigned long frametable_base_pdx; + +#endif /* ARM_PDX_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 6eddbcf912ee..faef0efb327c 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -16,6 +16,7 @@ #include #include +#include #include #include diff --git a/xen/arch/ppc/include/asm/mm.h b/xen/arch/ppc/include/asm/mm.h index 402d06bdaa9f..d55393ff2aa4 100644 --- a/xen/arch/ppc/include/asm/mm.h +++ b/xen/arch/ppc/include/asm/mm.h @@ -163,9 +163,6 @@ struct page_info #define FRAMETABLE_VIRT_START (XEN_VIRT_START + GB(32)) #define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) -/* PDX of the first page in the frame table. */ -extern unsigned long frametable_base_pdx; - /* Convert between machine frame numbers and page-info structures. */ #define mfn_to_page(mfn) \ (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) @@ -220,8 +217,6 @@ static inline void put_page_and_type(struct page_info *page) #define set_gpfn_from_mfn(mfn, pfn) BUG_ON("unimplemented") #define mfn_to_gfn(d, mfn) ({ BUG_ON("unimplemented"); _gfn(0); }) -#define PDX_GROUP_SHIFT XEN_PT_SHIFT_LVL_3 - static inline unsigned long domain_get_maximum_gpfn(struct domain *d) { BUG_ON("unimplemented"); diff --git a/xen/arch/ppc/include/asm/pdx.h b/xen/arch/ppc/include/asm/pdx.h new file mode 100644 index 000000000000..4290c7bc9c36 --- /dev/null +++ b/xen/arch/ppc/include/asm/pdx.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef PPC_PDX_H +#define PPC_PDX_H + +#include + +#define PDX_GROUP_SHIFT XEN_PT_SHIFT_LVL_3 + +#define ARCH_HAS_FRAMETABLE_BASE_PDX +extern unsigned long frametable_base_pdx; + +#endif /* PPC_PDX_H */ diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index d5385ec9dd4b..2eddd86822e0 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include diff --git a/xen/arch/x86/include/asm/pdx.h b/xen/arch/x86/include/asm/pdx.h index 6be7e1185eb1..5e660be17e39 100644 --- a/xen/arch/x86/include/asm/pdx.h +++ b/xen/arch/x86/include/asm/pdx.h @@ -3,8 +3,12 @@ #ifndef X86_PDX_H #define X86_PDX_H +#ifndef CONFIG_PDX_NONE + #include +#define ARCH_DEFINES_PDX_XLATE + /* * Introduce a macro to avoid repeating the same asm goto block in each helper. * Note the macro is strictly tied to the code in the helpers. @@ -59,6 +63,8 @@ static inline paddr_t directmapoff_to_maddr(unsigned long offset) #undef PDX_ASM_GOTO_SKIP +#endif /* !CONFIG_PDX_NONE */ + #endif /* X86_PDX_H */ /* diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h index 856fc3e8a0e6..59c257651953 100644 --- a/xen/include/xen/pdx.h +++ b/xen/include/xen/pdx.h @@ -132,8 +132,9 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn); */ bool __mfn_valid(unsigned long mfn); -#define page_to_pdx(pg) ((pg) - frame_table) -#define pdx_to_page(pdx) gcc11_wrap(frame_table + (pdx)) +#define page_to_pdx(pg) \ + ((unsigned long)((pg) - frame_table) + frametable_base_pdx) +#define pdx_to_page(pdx) gcc11_wrap(frame_table + ((pdx) - frametable_base_pdx)) #define mfn_to_pdx(mfn) pfn_to_pdx(mfn_x(mfn)) #define pdx_to_mfn(pdx) _mfn(pdx_to_pfn(pdx)) @@ -244,6 +245,14 @@ static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset) #endif /* CONFIG_PDX_OFFSET_COMPRESSION */ +#if __has_include() +# include +#endif + +#ifndef ARCH_HAS_FRAMETABLE_BASE_PDX +#define frametable_base_pdx 0 +#endif + #ifdef CONFIG_PDX_NONE /* Without PDX compression we can skip some computations */ @@ -283,9 +292,7 @@ static inline void pfn_pdx_compression_reset(void) * * Do not use _xlate suffixed functions, always use the non _xlate variants. */ -#if __has_include() -# include -#else +#ifndef ARCH_DEFINES_PDX_XLATE # define pdx_to_pfn pdx_to_pfn_xlate # define pfn_to_pdx pfn_to_pdx_xlate # define maddr_to_directmapoff maddr_to_directmapoff_xlate -- 2.43.0 From xen-devel-bounces@lists.xenproject.org Thu Apr 30 13:47:22 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 13:47:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298195.1573696 (Exim 4.92) (envelope-from ) id 1wIRjX-0001yd-W0; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> <1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373@vates.tech> <74953b6a-d195-4a12-800d-af324ff35b29@invisiblethingslab.com> Content-Language: en-US From: Teddy Astie In-Reply-To: <74953b6a-d195-4a12-800d-af324ff35b29@invisiblethingslab.com> X-BM-Disclaimer: Yes Content-Type: multipart/alternative; boundary="-=Part.392.3352229d598ec846.19ddea4b4d9.80e67b5e2fed426=-" X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1777556829402 X-purgate-ID: tlsNG-d25034/1777556833-F5A00CF5-E32DBE9F/0/0 X-purgate-type: clean X-purgate-size: 5804 ---=Part.392.3352229d598ec846.19ddea4b4d9.80e67b5e2fed426=- Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Le 30/04/2026 =C3=A0 10:51, Val Packett a =C3=A9crit=C2=A0: >=20 > On 4/30/26 5:11 AM, Teddy Astie wrote: >> Le 30/04/2026 =C3=A0 06:06, Val Packett a =C3=A9crit=C2=A0: >>> On 4/29/26 11:41 AM, Teddy Astie wrote: >>>> Hello, >>>> >>>> Le 29/04/2026 =C3=A0 16:18, Val Packett a =C3=A9crit=C2=A0: >>>>> [=E2=80=A6] >>>>> >>>>> I've been working on porting virtio-mmio support from Arm to x86_64, >>>>> with the goal of running vhost-user-gpu to power Wayland/GPU=20 >>>>> integration >>>>> for Qubes OS=2E (I'm aware of various proposals for alternative virt= io >>>>> transports but virtio-mmio seems to be the only one that *is* upstre= am >>>>> already and just Works=2E=2E) Setting up virtio-mmio through xenbus, >>>>> initially >>>>> motivated just by event channels being the only real way to get >>>>> interrupts >>>>> working on HVM, turned out to generally be quite pleasant and nice := ) >>>> Is it HVM specific, or can we also make it work for PVH (we can=20 >>>> actually >>>> attach a ioreq server to PVH guests) ? >>> Sorry, typo, I did mean PVH of course! >>> >>> I've been testing this with PVH guests + PV dom0, with my PV alloc_ior= eq >>> fix: >>> https://lore=2Ekernel=2Eorg/all/20251126062124=2E117425-1- >>> val@invisiblethingslab=2Ecom/ >>> >>> (Time to resend that one as a non-RFC I guess=E2=80=A6) >>> >>> HVM actually does have legacy ISA interrupts (which are often used wit= h >>> virtio-mmio on KVM), funnily enough, and I've tried firing those from = a >>> DMOP but that silly thing didn't work properly=2E >>> >>>>> I'd like to get some early feedback for this patch, particularly >>>>> the general stuff: >>>>> >>>>> * is this whole thing acceptable in general? >>>>> * should it be extracted into a different file? >>>>> * (from the Xen side) any input on the xenstore keys, what goes wher= e? >>>>> * anything else to keep in mind? >>>>> >>>>> It does seem simple enough, so hopefully this can be done? >>>>> >>>>> The corresponding userspace-side WIP is available at: >>>>> https://github=2Ecom/QubesOS/xen-vhost-frontend >>>>> >>>>> And the required DMOP for firing the evtchn events will be sent >>>>> to xen-devel shortly as well=2E >>>> Could that be done through evtchn_send (or its userland counterpart) = ? >>> Actually, yes=E2=80=A6 The use of DMOPs is only dictated by the curren= t Linux >>> privcmd=2Ec code (the irqfds created by the kernel react to events by >>> executing HYPERVISOR_dm_op with a stored operation), we can avoid the >>> need to modify Xen by simply expanding the privcmd driver to make >>> "evtchn fds"=2E Sounds good, will do=2E >>> >> Given that the event channel used by device models is exposed through >> ioreq=2Evp_eport ("evtchn for notifications to/from device model")=2E I >> don't think you need to expand the privcmd interface, and you should be >> able to do this instead : >> >> open /dev/xen/evtchn >> perform IOCTL_EVTCHN_BIND_INTERDOMAIN (for each guest vCPU) >> =C2=A0=C2=A0=C2=A0 with remote_domain=3Dguest_domid, remote_port=3Diore= q=2Evp_eport >> >> Then interact with the event channel through IOCTL_EVTCHN_NOTIFY (with >> local port given by IOCTL_EVTCHN_BIND_INTERDOMAIN) and read/write on th= e >> file descriptor=2E >=20 > So the reason there's currently an ioctl to bind an eventfd to fire a=20 > stored DMOP is that the whole idea is to (efficiently!) support generic,= =20 > hypervisor-neutral device server implementations via the vhost-user=20 > protocol=2E >=20 > Now of course, the current implementation isn't *entirely* hypervisor-= =20 > neutral as e=2Eg=2E the vm-memory Rust crate (inside of the "neutral" vh= ost-=20 > user device servers) does need to be built with the `xen` feature=2E But= =20 > still, that's how it works=2E What can be made generic is generic=2E >=20 > xen-vhost-frontend, which is the thing that integrates these with Xen,= =20 > actually used to handle the interrupts in userspace[1] by firing the=20 > DMOP itself (which is where I could "just replace that with=20 > IOCTL_EVTCHN_NOTIFY") but that was offloaded to the kernel with the=20 > introduction of IOCTL_PRIVCMD_IRQFD[2], similarly to KVM_IRQFD=2E >=20 I think what would be preferable for your usecase would be to have a way= =20 to bind a event channel with a eventfd object, which should be a=20 primitive that lives in the evtchn device=2E The current interface kinda assume that you're looking to emulate a=20 completely emulated virtio device with no Xen specifics, it looks like=20 it's not exactly what you're implementing=2E As you actually plan to switch to using event channels for notifying the= =20 guest, I think it would be preferable to do the same the other way=20 (event channels to notify the host) so you only have event channels to=20 worry about here=2E > Switching back to handling the eventfd in userspace would be a literal= =20 > deoptimization :) > > While throwing away the whole generic layer to do a fully integrated > use-case-specific thing sounds more difficult/tedious than this, and not= =20 > necessarily desirable in general=2E >=20 > [1]: https://github=2Ecom/vireshk/xen-vhost-frontend/=20 > commit/06d59035f8a387c0f600931d09dfaa27b80ede7f > [2]: https://git=2Ekernel=2Eorg/pub/scm/linux/kernel/git/next/linux-=20 > next=2Egit/commit/?id=3Df8941e6c4c712948663ec5d7bbb546f1a0f4e3f6 >=20 > ~val >=20 >=20 -- Teddy Astie | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates s= olutions web: https://vates=2Etech ---=Part.392.3352229d598ec846.19ddea4b4d9.80e67b5e2fed426=--- From xen-devel-bounces@lists.xenproject.org Thu Apr 30 13:58:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 13:58:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298209.1573705 (Exim 4.92) (envelope-from ) id 1wIRu4-00049J-Se; Thu, 30 Apr 2026 13:58:08 +0000 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docker ignores the > platform of the image when pushing, and it's pushed as the platform of > the runner. > > If we happen to build an arm64 image on x86, with recent version of > docker, the image will be push as if it was an x86 image, then > `docker run --platform=linux/arm64 ...` fails. Even if it would > work without --platform, gitlab-runner will not be able to use the > image. > > To go back to the previous behavior, we will extract --platform from > the dockerfiles, and use it on the command line. > > --platform= is needed on both docker-build and docker-push. The first > one so that the image is tagged with the right platform, and the > second one so that we can push a "generic" image without been tagged > to a particular platform. --platform on docker-push allow to easly use > the container on any arch, without having to use --platform on > docker-pull or docker-run. > > `docker push --platform` seem to have been added to 1.46, according to > the [doc], and doesn't exist on Podman. So we need to check that we > are using `docker` and that the API version is new enough. > > [doc] https://docs.docker.com/reference/cli/docker/image/push/ > > Also, introduce the $img variable, to make the lines a bit shorter. > > Signed-off-by: Anthony PERARD For the code changes, Acked-by: Andrew Cooper > --- > automation/build/Makefile | 24 +++++++++++++++++++++--- There's another docker push in automation/tests-artifacts/Makefile However, this fix should allow me to finish the work to purge test-artefacts/* so the problem sorts itself. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 30 14:49:21 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 14:49:21 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298244.1573714 (Exim 4.92) (envelope-from ) id 1wIShO-0002h2-I3; Thu, 30 Apr 2026 14:49:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298244.1573714; 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Fix the check in cpu_smpboot_free() to use the > correct condition. > > Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]") > Signed-off-by: Roger Pau Monné > --- > xen/arch/x86/smpboot.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c > index 491cbbba33ae..ff05955bae40 100644 > --- a/xen/arch/x86/smpboot.c > +++ b/xen/arch/x86/smpboot.c > @@ -961,8 +961,7 @@ static void cpu_smpboot_free(unsigned int cpu, bool remove) > * In that case the socket number cannot be relied upon, but the respective > * socket_cpumask[] slot also wouldn't have been set. > */ > - if ( c[cpu].apicid != boot_cpu_data.apicid && > - cpumask_empty(socket_cpumask[socket]) ) > + if ( c[cpu].apicid != BAD_APICID && cpumask_empty(socket_cpumask[socket]) ) > { > xfree(socket_cpumask[socket]); > socket_cpumask[socket] = NULL; Yet more fallout from that change... This is the singular use of apicid.  We should consider removing it, but that's a change for later. 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> > if ( vmcb->_vintr.fields.vgif_enable ) > - ASSERT(vmcb->_vintr.fields.vgif == 0); > + vmcb->_vintr.fields.vgif = 0; > else > - ASSERT(svm->ns_gif == 0); > + nestedsvm_vcpu_clgi(v); > > ns_vmcb = nv->nv_vvmcx; > I agree this is a bug. It is common for GIF to be clear when executing VMRUN but it is not required.  The pseudocode says that VMRUN simply sets GIF, and #VMEXIT simply clears GIF. But, looking at nestedsvm_vcpu_clgi(), it's not the only bug here.  nestedsvm_vcpu_{clgi,stgi}() have additional calls to local_event_delivery_{disable,enable}(). vgif_enable is strictly an optimisation that allows hardware to manage the vGIF bit, so at an absolute minimum this ought to be:     if ( ->vgif_enable )         ->vgif = 0;     else         ->ns_gif = 0;     local_event_delivery_disable(); to have balanced semantics.  Except that messing with event channels can't be done when hardware is handling the vgif bit. In fact, I think it's plain buggy to be touching event channels in response to GIF changes.  In PV guests  vcpu_info->evtchn_upcall_mask is the singular mask bit, but this is not true in HVM guests.  Even with direct vector injection, HVM guests are still subject to normal rules about INTR delivery, and that CLI blocks them.  This should naturally extend to GIF for nested-SVM too. As far as testing goes, perhaps we want to start with something even more simple.  For real self-IPIs, and self-evtchns (for all reasonable evtchn delivery configurations), check that delivery is blocked by IF=0 || GIF=0. ~Andrew From xen-devel-bounces@lists.xenproject.org Thu Apr 30 18:50:36 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 18:50:36 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298404.1573732 (Exim 4.92) (envelope-from ) id 1wIWSl-00023R-S5; Thu, 30 Apr 2026 18:50:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298404.1573732; Thu, 30 Apr 2026 18:50:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIWSl-00023J-Mw; Thu, 30 Apr 2026 18:50:15 +0000 Received: by outflank-mailman (input) for mailman id 1298404; Thu, 30 Apr 2026 18:50:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIWSk-00023D-6z for xen-devel@lists.xenproject.org; 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Tsirkin" , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Viresh Kumar , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, virtualization@lists.linux.dev References: <20260429141339.74472-1-val@invisiblethingslab.com> <1777473712.8631fc262581453bbf619ec5b2062170.19dd9b07146000f373@vates.tech> <1777536698.8631fc262581453bbf619ec5b2062170.19ddd7187da000f373@vates.tech> <74953b6a-d195-4a12-800d-af324ff35b29@invisiblethingslab.com> <1777556830.8631fc262581453bbf619ec5b2062170.19ddea4b728000f373@vates.tech> Content-Language: en-US From: Val Packett Autocrypt: addr=val@invisiblethingslab.com; keydata= xm8EaFTEiRMFK4EEACIDAwQ+qzawvLuE95iu+QkRqp8P9z6XvFopWtYOaEnYf/nE8KWCnsCD jz82tdbKBpmVOdR6ViLD9tzHvaZ1NqZ9mbrszMXq09VfefoCfZp8jnA2yCT8Y4ykmv6902Ne NnlkVwrNKFZhbCBQYWNrZXR0IDx2YWxAaW52aXNpYmxldGhpbmdzbGFiLmNvbT7CswQTEwkA OxYhBAFMrro+oMGIFPc7Uc87uZxqzalRBQJoVMSJAhsDBQsJCAcCAiICBhUKCQgLAgQWAgMB Ah4HAheAAAoJEM87uZxqzalRlIIBf0cujzfSLhvib9iY8LBh8Tirgypm+hJHoY563xhP0YRS pmqZ6goIuSGpEKcW5mV3egF/TLLAOjsfroWae4giImTVOJvLOsUycxAP4O5b1Qiy+cCGsHKA nCRzrvqnPkyf4OeRznMEaFTEiRIFK4EEACIDAwSffe3tlMmmg3eKVp7SJ+CNZLN0M5qzHSCV dBBkIVvEJo+8SDg4jrx/832rxpvMCz2+x7+OHaeBHKafhOWUccYBLKqV/3nBftxCkbzXDbfY d02BY9H4wBIn0Y3GnwoIXRgDAQkJwpgEGBMJACAWIQQBTK66PqDBiBT3O1HPO7mcas2pUQUC aFTEiQIbDAAKCRDPO7mcas2pUaptAX9f7yUJLGU4C6XjMJvXd8Sz6cGTyxkngPtUyFiNqtad /GXBi3vHKYNfSrdqJ8wmZ8MBgOqWaaa1wE4/3qZU8d4RNR8mF7O40WYK/wdf1ycq1uGad8PN UDOwAqdfvuF3w8QMPw== In-Reply-To: <1777556830.8631fc262581453bbf619ec5b2062170.19ddea4b728000f373@vates.tech> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-16d1c6/1777575013-91678D75-278DF2CF/0/0 X-purgate-type: clean X-purgate-size: 5250 On 4/30/26 10:47 AM, Teddy Astie wrote: > Le 30/04/2026 à 10:51, Val Packett a écrit : >> On 4/30/26 5:11 AM, Teddy Astie wrote: >>> Le 30/04/2026 à 06:06, Val Packett a écrit : >>>> [..] >>>>>> I'd like to get some early feedback for this patch, particularly >>>>>> the general stuff: >>>>>> >>>>>> * is this whole thing acceptable in general? >>>>>> * should it be extracted into a different file? >>>>>> * (from the Xen side) any input on the xenstore keys, what goes where? >>>>>> * anything else to keep in mind? >>>>>> >>>>>> It does seem simple enough, so hopefully this can be done? >>>>>> >>>>>> The corresponding userspace-side WIP is available at: >>>>>> https://github.com/QubesOS/xen-vhost-frontend >>>>>> >>>>>> And the required DMOP for firing the evtchn events will be sent >>>>>> to xen-devel shortly as well. >>>>> Could that be done through evtchn_send (or its userland counterpart) ? >>>> Actually, yes… The use of DMOPs is only dictated by the current Linux >>>> privcmd.c code (the irqfds created by the kernel react to events by >>>> executing HYPERVISOR_dm_op with a stored operation), we can avoid the >>>> need to modify Xen by simply expanding the privcmd driver to make >>>> "evtchn fds". Sounds good, will do. >>>> >>> Given that the event channel used by device models is exposed through >>> ioreq.vp_eport ("evtchn for notifications to/from device model"). I >>> don't think you need to expand the privcmd interface, and you should be >>> able to do this instead : >>> >>> open /dev/xen/evtchn >>> perform IOCTL_EVTCHN_BIND_INTERDOMAIN (for each guest vCPU) >>>     with remote_domain=guest_domid, remote_port=ioreq.vp_eport >>> >>> Then interact with the event channel through IOCTL_EVTCHN_NOTIFY (with >>> local port given by IOCTL_EVTCHN_BIND_INTERDOMAIN) and read/write on the >>> file descriptor. >> So the reason there's currently an ioctl to bind an eventfd to fire a >> stored DMOP is that the whole idea is to (efficiently!) support generic, >> hypervisor-neutral device server implementations via the vhost-user >> protocol. >> >> Now of course, the current implementation isn't *entirely* hypervisor- >> neutral as e.g. the vm-memory Rust crate (inside of the "neutral" vhost- >> user device servers) does need to be built with the `xen` feature. But >> still, that's how it works. What can be made generic is generic. >> >> xen-vhost-frontend, which is the thing that integrates these with Xen, >> actually used to handle the interrupts in userspace[1] by firing the >> DMOP itself (which is where I could "just replace that with >> IOCTL_EVTCHN_NOTIFY") but that was offloaded to the kernel with the >> introduction of IOCTL_PRIVCMD_IRQFD[2], similarly to KVM_IRQFD. >> > I think what would be preferable for your usecase would be to have a way > to bind a event channel with a eventfd object, which should be a > primitive that lives in the evtchn device. Yeah, it would be an ioctl on the evtchn device, definitely. I wasn't being exact when I said "extend privcmd", sorry. I just meant "handling it on the Linux side" generally! > The current interface kinda assume that you're looking to emulate a > completely emulated virtio device with no Xen specifics, it looks like > it's not exactly what you're implementing. It's already implemented, and I'm not looking to change it much, just to make it work on x86_64. The only thing that wasn't already compatible was firing the host-to-guest interrupt, because on x86_64 we don't have anything like the (v)GIC with its massive arbitrary IRQ number space. Event channels are the only way to interrupt a PVH guest, hence using xenbus in the guest to provision the device. > As you actually plan to switch to using event channels for notifying the > guest, I think it would be preferable to do the same the other way > (event channels to notify the host) so you only have event channels to > worry about here. The other direction is already implemented perfectly well in IOCTL_PRIVCMD_IOEVENTFD. The MMIO area is set up like so: - ioreq is mapped with IOCTL_PRIVCMD_MMAP_RESOURCE(XENMEM_resource_ioreq_server, ..); - vp_eport event channels (per cpu) are bound to the current domain via IOCTL_EVTCHN_BIND_INTERDOMAIN; - those are passed, along with the ioreq page itself, to IOCTL_PRIVCMD_IOEVENTFD to get an eventfd that fires when a virtqueue is ready; - which is an eventfd that xen-vhost-frontend passes to the vhost-user device server. So for this direction, it's not a 1:1 mapping but rather a specific contraption designed to efficiently handle this use case: - when an ioreq event channel (for any of the vcpus) fires, - the kernel handler (ioeventfd_interrupt) checks if it's specifically an IOREQ_WRITE write to the VIRTIO_MMIO_QUEUE_NOTIFY offset, - and if so, it signals the eventfd for any virtqueue that has new data (waking the generic device server which has the eventfd, so bypassing xen-vhost-frontend), pings the guest back via evtchn, and returns IRQ_HANDLED; - otherwise the request is handled in userspace by xen-vhost-frontend (virtio configuration register access). It just works :) ~val From xen-devel-bounces@lists.xenproject.org Thu Apr 30 19:39:25 2026 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 30 Apr 2026 19:39:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1298432.1573741 (Exim 4.92) (envelope-from ) id 1wIXEC-0008E9-Ba; Thu, 30 Apr 2026 19:39:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1298432.1573741; Thu, 30 Apr 2026 19:39:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIXEC-0008E2-8Z; Thu, 30 Apr 2026 19:39:16 +0000 Received: by outflank-mailman (input) for mailman id 1298432; Thu, 30 Apr 2026 19:39:14 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wIXEA-0008Dw-TP for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 19:39:14 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wIXEA-0000dU-3e for xen-devel@lists.xenproject.org; Thu, 30 Apr 2026 21:39:14 +0200 Received: from [10.42.69.5] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69f3afdb-e002-0a2a0a5209dd-0a2a4505d1e4-4 for ; Thu, 30 Apr 2026 21:39:13 +0200 Received: from [109.190.99.82] (helo=chassiron.antioche.eu.org) by tlsNG-c201ff.mxtls.expurgate.net with ESMTPS (eXpurgate 4.56.1) (envelope-from ) id 69f3afe1-aaa8-0a2a45050019-6dbe6352c381-3 for ; Thu, 30 Apr 2026 21:39:13 +0200 Received: from sandettie.soc.lip6.fr (82-64-3-41.subs.proxad.net [82.64.3.41]) by chassiron.antioche.eu.org (8.18.1/8.16.1) with ESMTPS id 63UJcvsg005688 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Thu, 30 Apr 2026 21:38:58 +0200 (MEST) Received: by sandettie.soc.lip6.fr (Postfix, from userid 373) id C02D32E932D; Thu, 30 Apr 2026 21:38:52 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Date: Thu, 30 Apr 2026 21:38:52 +0200 From: Manuel Bouyer To: Roger Pau =?iso-8859-1?Q?Monn=E9?= Cc: xen-devel@lists.xenproject.org, Frediano Ziglio , Anthony PERARD , Juergen Gross , Andrew Cooper , Frediano Ziglio Subject: Re: [PATCH] tools: Use posix_memalign instead of valloc for NetBSD Message-ID: References: <20260430095521.8399-1-frediano.ziglio@cloud.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Greylist: Sender succeeded STARTTLS authentication, not delayed by milter-greylist-4.6.4 (chassiron.antioche.eu.org [109.190.99.82]); Thu, 30 Apr 2026 21:38:58 +0200 (MEST) X-purgate-ID: tlsNG-c201ff/1777577953-E3D67443-0EF579E8/0/0 X-purgate-type: clean X-purgate-size: 279 On Thu, Apr 30, 2026 at 12:48:53PM +0200, Roger Pau Monn wrote: > Adding Manuel that maintains the NetBSD xen-tools package. thanks AFAIK this patch is fine -- Manuel Bouyer NetBSD: 26 ans d'experience feront toujours la difference --