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boundary="_000_BYAPR02MB4278EEDED8076A1F3E79B1B8A13E9BYAPR02MB4278namp_" MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BYAPR02MB4278.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6a47c007-8da3-488c-757d-08d924aec57f X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2021 03:38:50.3908 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: B7ZeVjmFXUWy+IOwz/MiIFRAZVcyJNc7yoaf8iNCCttvANDtdJGCbYIX8zBd3gqJzcjIwgMM3lNCGDmfVkDoJg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB7790 --_000_BYAPR02MB4278EEDED8076A1F3E79B1B8A13E9BYAPR02MB4278namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable In case of FreeRTOS, you need to use APIs from FreeRTOS port for interrupt= handling (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp= /freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). Ple= ase make sure that you are taking care of that in DMA interrupt example . Thanks, Mubin From: Prem Harikrishnan Sent: Tuesday, June 1, 2021 2:48 AM To: Stefano Stabellini Cc: xen-users@lists.xenproject.org; Jovita Castelino ; = Mubin Usman Sayyed Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit Hi Stefano and Mubin, Thank you very much for your replies. @Stefano Stabellini Sorry to bother y= ou again, and thank you for pointing this out, the TTC0 is by default enabl= ed for FreeRTOS to generate ticks, although this says only for R5 core, i w= ould have never figured this out. As soon as I added the irqs and iomem and= gave a xen passthrough in the xen.dtsi as you have suggested, FreeRTOS gue= st started working for other peripherals except for my DMA (FreeRTOS guest = does not work with interrupt and DMA). I can see my DMA is enabled because i have LEDs configured to blink for eve= ry interrupt I get from the PL. I don't see my interrupts being processed, = but when I destroy the guest, I get this output periodically when an interr= upt occurs. (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 >From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/= A/pages/18842066/Xen+and+PL+Masters Xen and PL Masters - Xilinx Wiki - Confluence 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of = PL masters must be added to the Linux Dom0 device tree. Automated device tr= ee generation does not generate the stream IDs for the PL masters so that t= he user must add them into the device tree manually. xilinx-wiki.atlassian.net The fault indicates an unidentified stream ID has been received by the SMMU= as shown in the GFSR register. The GFSYNR1 register contains the stream ID= that was unidentified. A stream ID of 0xE80 was unidentified in the above = fault. But I think i have already added that in my smmu and iommu in xen.dtsi beca= use my baremetal application works well as expected. I have attached my xen= .dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). What could I be missing here? Do I have to enable the ttc0 in the device tr= ee? Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: = 99990 KHz mean when XEN boots up? Thanks, I look forward for your reply. Best Regards, Prem ________________________________ From: Stefano Stabellini > Sent: Friday, May 28, 2021 20:43 To: Prem Harikrishnan > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com >; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit >From the gpa address, it looks like FreeRTOS is trying to access the TTC timer? If you look at device tree, the corresponding node is timer@ff110000. If FreeRTOS is configured to access the TTC timer, then you need to assign it to it. Did you assign the TTC timer to the FreeRTOS domU by any chance? You can do that by adding: irqs =3D [ 68, 69, 70 ] iomem =3D [ "0xff110,1" ] On Fri, 28 May 2021, Prem Harikrishnan wrote: > Hi Stefano, > Thanks for your reply. I am pretty sure I followed the steps you mentione= d below to run the FreeRTOS hello world example. I already added > printfs and i can see XEN cannot start the scheduler and i get the follow= ing out put on XEN. > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 memfl= ags=3D0xc0 (0 of 64) > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0 > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0xff= 11000c gpa=3D0x000000ff11000c > > > I also see that according to this article > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as= -a-Xen-Virtual-Machine/ba-p/947030 > [52662iFAD1733707609204?v=3Dv2] > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks Wh= at is FreeRTOS? The FreeRTOS kernel is a market leading real-time > operating system for embedded systems. As embedded applications grow in c= omplexity, there is a growing need for a lightweight kernel > capable of task scheduling... > forums.xilinx.com > FreeRTOS does not run out of the box for XEN, although the article is 2 y= ears old, I am not sure if there are any updates on this after > that. Can you please confirm? > > Thanks and Best Regards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 02:51 > To: Prem Harikrishnan > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com > >; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > +Mubin > > > Hi Prem, > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps: > > - source settings64.sh from Vitis builds > - xsct > - set WORKSPACE . > - setws -switch $WORKSPACE > - app create -name freertos-hello-world -template {FreeRTOS Hello World} = -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > - bsp config stdin psu_uart_1 > - bsp config stdout psu_uart_1 > - bsp config hypervisor_guest true > - Go to application source path and modify the linker script start addres= s to 0x40000000, > - app build -name freertos-hello-world > - Run command to generate BIN file from executable "aarch64-linux-gnu-obj= copy -O binary --gap-fill 0 BOOT.BIN" > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > might be able to provide additional info. > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Sorry to bother you again. > > I am currently trying to run my custom IP which sends periodic dma inte= rrupts to the PS with cache coloring enabled. I have now compiled > my > > guest running with FreeRTOS and it generates a trap. > > Petalinux and VITIS IDE Version is 2020.2. > > > > Please find the log attached. After the trap occurs, for every interrup= t XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault: > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config fro= m apu_freertos.cfg > > (XEN) Dom1 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D1 mem= flags=3D0xc0 (0 of 64) > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache=3D0 > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > (XEN) sched_null.c:344: 1 <-- d1v0 > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gva=3D0x= ff11000c gpa=3D0x000000ff11000c > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > The same application works as expected without FreeRTOS, i.e as a barem= etal guest. I look forward for your comment on this. > > > > Although i see performance degradation, normally i can measure delta ti= me for each interrupt configured to 1ms (without XEN), with XEN > for > > the same measurement shows 16 ms for each interval (but the performance= is not a priority for now). > > Thanks and Best Regards, > > Prem > > > >________________________________________________________________________= __________________________________________________________________ > _ > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 20:09 > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL = masters in ZCU102 dev kit > > Great to hear! Thank you for reporting back. > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > Dear Stefano, > > > Thank you very much for your guidance and support. I finally fixed th= e issue. I made an error in base memory address like you pointed > > out. > > > I actually modified the base address correctly to 0x40000000 but the = default C code had an additional offset of 0x1100000 , and the > DomU > > > memory allocated was only 8MB. I either had to change the offset or a= llocate more memory to the DomU guest which i missed until you > > pointed > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and th= e SMID required is 0xE80. > > > > > > Thanks again i was able get my custom IP also working as an AXI maste= r from PL. > > > > > > Best Regards, > > > Prem > > > > >>_______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 02:35 > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; St= efano > > > Stabellini >; x= en-users@lists.xenproject.org >; fnuv@xil= inx.com > >; > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for P= L masters in ZCU102 dev kit > > > Your configuration looks correct as far as I can tell. > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > block. You don't need device_tree because your baremetal application = is > > > not going to read it, but it is not going to cause any issues either. > > > > > > When you say "the execution does not complete the loop at line 244", = it > > > means that you see the execution entering the loop and then never > > > leaving? Like an infinite loop? > > > > > > If so, then I imagine the issue could be that the application is > > > crashing when trying to access TxBufferPtr, which is pointing to > > > TX_BUFFER_BASE, which is: > > > > > > > > > #ifndef DDR_BASE_ADDR > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > DEFAULT SET TO 0x01000000 > > > #define MEM_BASE_ADDR 0x01000000 > > > #else > > > #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) > > > #endif > > > > > > #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > Hi Stefano, > > > > Thanks again for your reply and your suggestion. I did try to repl= ace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRange(works > > only > > > > in EL3), I added printfs to debug, i can see that the execution doe= s not complete the loop at line 244 > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPL= ib/drivers/axidma/examples/xaxidma_example_simple_poll.c and > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bo= otlog.txt. > > > > I am still unable to find out why?? > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is corre= ct? and do i need dtdev and device_tree in my guest config file > when > > > it > > > > is already added to xen.dtsi? > > > > > > > > Best Regards, > > > > Prem > > > > > > > > > >>>______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; = Stefano > > > > Stabellini >;= xen-users@lists.xenproject.org >; fnuv@x= ilinx.com > > >; > > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for= PL masters in ZCU102 dev kit > > > > Hi Prem, > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > deprecated set/way instructions that are known to cause problems in > > > > virtualized environments. > > > > > > > > More recent implementations use the "dc civac" intruction that shou= ldn't > > > > have any issues. > > > > > > > > Can you double-check that you are calling the 64-bit version implem= ented > > > > by CIVAC? > > > > > >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3= 577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L4 > 1 > > 4 > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks for your reply. Yes the axidma application is a baremetal = application from the xilinx vitis ide example. > > > > > Also yes, I have already run hello world as DomU guest, with UART= 1. > > > > > > > > > > I am using the simple mode using polling and not interrupts(they = are disabled in the c code), which is Why I didn't include in the > > > guest > > > > > config file. This works well when I compile it normally (as EL3).= When compiled as hypervisor guest, the execution stops before the > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcess= orIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c > > > > > > > > > > I found the SATA example similar to my use case, also using DMA a= nd SMMU. I just used it as a reference to create my pl.dtb to pass > > > > through > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > Thanks and Best Regards, > > > > > Prem > > > > > > > > > > Get Outlook for Android > > > > > > >>>>_____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > To: Prem Harikrishnan > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabel= lini; xen-users@lists.xenproject.org= ; fnuv@xilinx.com; > > > > edgari@xilinx.com; > > > > > bwoods288@gmail.com; Renato Costa Amo= rim; JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.= bin" is > > > > > a baremetal application? Can you run it successfully, just printi= ng > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on = the > > > > > Vivado configuration and SMID calculation. But I noticed that you= only > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven= 't > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dts= i, it > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I do= n't > > > > > follow: I cannot see any SATA controller assignment in your > > > > > configuration. > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > Thank you very much for your replies. > > > > > > Hi Brian and Stefano, Can you please help me with the following= questions? > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when= i added my AXI DMA now running on simple polling mode(previously > i > > > > tried > > > > > it > > > > > > with Scatter Gather mode), Run Automation automatically generat= ed, 1 AXI Interconnect and 1 smart connect. Since there is only 1 > > > master > > > > > and > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for th= e stream IDs. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/= Xen+and+PL+Masters According to this link section 6.5 I have > > manually > > > > tied > > > > > > of AxPROT bits to value of 0x2 to create non secure transaction= s. Can you please confirm that my Vivado configuration is correct? > I > > > can > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated f= rom petalinux and system.dtsi also generated after manually adding > > > > > xen.dtsi. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561= /Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > this > > > > SATA > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.= cfg. I could really use your help to identify what is missing in > my > > > xen > > > > > > configuration. > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > >>>>>____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Brian Woods > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > To: Stefano Stabellini > > > > > > > Cc: Julien Grall >; Prem = Harikrishnan >; Stefano Stabellini > > >; > > > > > > xen-users@lists.xenproject.org >; brian.woods@xilinx.com >; fnuv@xilinx.com > > > > > > >; edgari@xilinx.com >; bwoo= ds288@gmail.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough= for PL masters in ZCU102 dev kit > > > > > > Prem, > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have = been away > > > > > > from my computer. In the Zynq SOCs this is how the SMMU IDs in= PL are > > > > > > calculated: > > > > > > > > > > > > 14-10: TBU bits > > > > > > 9-6: Master ID bits > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085= -zynq-ultrascale-trm.pdf > > > > > > To look up the TBU value, see UG1085 and look for the "System M= asters" > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List= " table > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in= PL. > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.= There > > > > > > are work arounds. Here's a couple of examples (with example nu= mbers): > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > -> PS s= lave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be function= ally > > > > > > replaced with "AXI Interconnect" to my knowledge. So the AXI I= D bits are > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_ar= chitecture_specification.pdf > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions= . > > > > > > > > > > > > Brian > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wr= ote: > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 = development board > > > > > > > > > and i am trying to create a barematal application that us= es the AXI DMA on > > > > > > > > > the programmable logic, using the scatter gather example = from the xilinx > > > > > > > > > repository. This works perfectly well for the baremetal a= pplication. The > > > > > > > > > diagram below represents the information flow. The AXI DM= A and the AXI data > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is= out of the box IP > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSE= R) which means the > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, = in future this will > > > > > > > > > be replaced by a custom IP with cache colouring enabled. = I want to pass > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocate= d to Dom-0) to > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate= my linux, xen > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > From what i understand from the xilinx tutorials Xen+and= +PL+Masters > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the= correct address > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu prop= erty for my AXI DMA > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2= 020.2 releases > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > * 1:1 memory mappings for Xen virtual machines, enabl= ing device > > > > > > > > > assignments without SMMU > > > > > > > > > * > > > > > > > > > Static assignment of PL blocks, including bus-maste= ring blocks, to > > > > > > > > > Xen virtual machines > > > > > > > > > * Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by= Xilinx. So I would > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --_000_BYAPR02MB4278EEDED8076A1F3E79B1B8A13E9BYAPR02MB4278namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

In case of FreeRTOS,  you need to use APIs from= FreeRTOS port for interrupt handling  (https://github.com/Xilinx/embeddedsw/blob/master= /ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). Please make sure that you are taking care of that in DMA in= terrupt example .

 

Thanks,

Mubin

 

From: Prem Harikrishnan <prem.harikrishnan= @evoleotech.com>
Sent: Tuesday, June 1, 2021 2:48 AM
To: Stefano Stabellini <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org; Jovita Castelino <JOVITAC@xil= inx.com>; Mubin Usman Sayyed <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

&n= bsp;

Hi Stef= ano and Mubin,

Thank y= ou very much for your replies.

@Stefa= no Stabellini Sorry to bother you again, and thank you for pointing this out, the TTC0 is by default enabled for FreeRT= OS to generate ticks, although this says only for R5 core, i would have nev= er figured this out. As soon as I added the irqs and iomem and gave a xen p= assthrough in the xen.dtsi as you have suggested, FreeRTOS guest started working for other peripherals excep= t for my DMA (FreeRTOS guest does not work with interrupt and DMA).

&n= bsp;

I can s= ee my DMA is enabled because i have LEDs configured to blink for every inte= rrupt I get from the PL. I don't see my interrupts being processed, but whe= n I destroy the guest, I get this output periodically when an interrupt occurs.

&n= bsp;

(XEN) s= mmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(XEN) s= mmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(XEN) s= mmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

&n= bsp;

3.4 Stream IDs in the Device Tree. F= or Xen based systems the stream IDs of PL masters must be added to the Linu= x Dom0 device tree. Automated device tree generation does not generate the stream IDs for the PL masters so that the user must = add them into the device tree manually.

xilinx-wiki.atlassian.net=

The fault indicates an u= nidentified stream ID has been received by the SMMU as shown in the GFSR re= gister. The GFSYNR1 register contains the stream ID that was unidentified. = A stream ID of 0xE80 was unidentified in the above fault.

&n= bsp;

But I t= hink i have already added that in my smmu and iommu in xen.dtsi because my = baremetal application works well as expected. I have attached my xen.dtsi, = system.dtsi, baremetal.cfg(working) and freertos.cfg(not working).

What co= uld I be missing here? Do I have to enable the ttc0 in the device tree?

Also wh= at does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: 99990 K= Hz mean when XEN boots up?

Thanks,= I look forward for your reply.

&n= bsp;

Best Re= gards,

Prem

&n= bsp;

&n= bsp;

From: Stefano Stabellini <stefano.stabellini@xilinx.com>
Sent: Friday, May 28, 2021 20:43
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

From the gpa address, it looks like FreeRTOS is tryi= ng to access the TTC
timer? If you look at device tree, the corresponding node is
timer@ff110000.

If FreeRTOS is configured to access the TTC timer, then you need to
assign it to it. Did you assign the TTC timer to the FreeRTOS domU by
any chance?

You can do that by adding:

irqs =3D [ 68, 69, 70 ]
iomem =3D [ "0xff110,1" ]


On Fri, 28 May 2021, Prem Harikrishnan wrote:
> Hi Stefano,
> Thanks for your reply. I am pretty sure I followed the steps you menti= oned below to run the FreeRTOS hello world example. I already added
> printfs and i can see XEN cannot start the scheduler and i get the fol= lowing out put on XEN.
>
> Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ]
> (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 me= mflags=3D0xc0 (0 of 64)
> (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0
> (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0= xff11000c gpa=3D0x000000ff11000c
>
>
> I also see that according to this article
> https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a= -Xen-Virtual-Machine/ba-p/947030
> [52662iFAD1733707609204?v=3Dv2]
> Partner: FreeRTOS as a Xen Virtual Machine - Community Forums
> Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks= What is FreeRTOS? The FreeRTOS kernel is a market leading real-time
> operating system for embedded systems. As embedded applications grow i= n complexity, there is a growing need for a lightweight kernel
> capable of task scheduling...
> forums.xilinx.com
> FreeRTOS does not run out of the box for XEN, although the article is = 2 years old, I am not sure if there are any updates on this after
> that. Can you please confirm?
>
> Thanks and Best Regards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> Sent: Friday, May 28, 2021 02:51
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com
> <JOVITAC@xilinx.com>; = MUBINUSM@xilinx.com <MUBINUSM= @xilinx.com>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
> +Mubin
>
>
> Hi Prem,
>
> Did you make sure to build FreeRTOS as "hypervisor guest"? I= think
> FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps:
>
> - source settings64.sh from Vitis builds
> - xsct
> - set WORKSPACE .
> - setws -switch $WORKSPACE
> - app create -name freertos-hello-world -template {FreeRTOS Hello Worl= d} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx
> - bsp config stdin psu_uart_1
> - bsp config stdout psu_uart_1
> - bsp config hypervisor_guest true
> - Go to application source path and modify the linker script start add= ress to 0x40000000,
> - app build -name freertos-hello-world
> - Run command to generate BIN file from executable "aarch64-linux= -gnu-objcopy -O binary --gap-fill 0  <elf path> BOOT.BIN" >
> The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed,<= br> > might be able to provide additional info.
>
>
>
> On Thu, 27 May 2021, Prem Harikrishnan wrote:
> > Hi Stefano,
> > Sorry to bother you again.
> > I am currently trying to run my custom IP which sends periodic dm= a interrupts to the PS with cache coloring enabled. I have now compiled
> my
> > guest running with FreeRTOS and it generates a trap.
> > Petalinux and VITIS IDE Version is 2020.2.
> >
> > Please find the log attached. After the trap occurs, for every in= terrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault:
> > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing conf= ig from apu_freertos.cfg
> > (XEN) Dom1 colors: [ 8 ]
> > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id= =3D1 memflags=3D0xc0 (0 of 64)
> > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache= =3D0
> > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache= =3D0
> > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000
> > (XEN) sched_null.c:344: 1 <-- d1v0
> > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gv= a=3D0xff11000c gpa=3D0x000000ff11000c
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > The same application works as expected without FreeRTOS, i.e as a= baremetal guest. I look forward for your comment on this.
> >
> > Although i see performance degradation, normally i can measure de= lta time for each interrupt configured to 1ms (without XEN), with XEN
> for
> > the same measurement shows 16 ms for each interval (but the perfo= rmance is not a priority for now).
> > Thanks and Best Regards,
> > Prem
> >
> >__________________________________________________________________= ________________________________________________________________________ > _
> > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > Sent: Tuesday, May 18, 2021 20:09
> > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>;
> JOVITAC@xilinx.com
> > <JOVITAC@xilinx.com&= gt;
> > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit  
> > Great to hear! Thank you for reporting back.
> >
> >
> > On Tue, 18 May 2021, Prem Harikrishnan wrote:
> > > Dear Stefano,
> > > Thank you very much for your guidance and support. I finally= fixed the issue. I made an error in base memory address like you pointed > > out.
> > > I actually modified the base address correctly to 0x40000000= but the default C code had an additional offset of 0x1100000 , and the
> DomU
> > > memory allocated was only 8MB. I either had to change the of= fset or allocate more memory to the DomU guest which i missed until you
> > pointed
> > > out. Additionally i had to set to AxPROT bits to 0x2 in Viva= do and the SMID required is 0xE80.
> > >
> > > Thanks again i was able get my custom IP also working as an = AXI master from PL.
> > >
> > > Best Regards,
> > > Prem
> > >
> >>______________________________________________________________= ___________________________________________________________________________=
> _
> > _
> > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > Sent: Tuesday, May 18, 2021 02:35
> > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <brian.woods@xilinx.com>; Julie= n Grall <julien@xen.org>; Stefano
> > > Stabellini <sst= abellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> <fnuv@xilinx.com>;
> > > edgari@xilinx.com &= lt;edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > JOVITAC@xilinx.com= <JOVITAC@xilinx.com>
> > > Subject: Re: Help: Information required for AXI DMA passthro= ugh for PL masters in ZCU102 dev kit  
> > > Your configuration looks correct as far as I can tell.
> > >
> > > You need dtdev because it triggers the SMMU configuration fo= r your PL
> > > block. You don't need device_tree because your baremetal app= lication is
> > > not going to read it, but it is not going to cause any issue= s either.
> > >
> > > When you say "the execution does not complete the loop = at line 244", it
> > > means that you see the execution entering the loop and then = never
> > > leaving? Like an infinite loop?
> > >
> > > If so, then I imagine the issue could be that the applicatio= n is
> > > crashing when trying to access TxBufferPtr, which is pointin= g to
> > > TX_BUFFER_BASE, which is:
> > >
> > >
> > > #ifndef DDR_BASE_ADDR
> > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \=
> > >           =        DEFAULT SET TO 0x01000000
> > > #define MEM_BASE_ADDR      &nb= sp;    0x01000000
> > > #else
> > > #define MEM_BASE_ADDR      &nb= sp;    (DDR_BASE_ADDR + 0x1000000)
> > > #endif
> > >
> > > #define TX_BUFFER_BASE      &n= bsp;   (MEM_BASE_ADDR + 0x00100000)
> > >
> > >
> > >
> > > Can you double check that TX_BUFFER_BASE is pointing to a co= rrect
> > > address? Memory starts at 0x40000000 in a Xen DomU.
> > >
> > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly?
> > >
> > >
> > > On Mon, 17 May 2021, Prem Harikrishnan wrote:
> > > > Hi Stefano,
> > > > Thanks again for your reply and your suggestion.  = I did try to replace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRang= e(works
> > only
> > > > in EL3), I added printfs to debug, i can see that the e= xecution does not complete the loop at line 244
> > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drive= rs/axidma/examples/xaxidma_example_simple_poll.c  and
> > > > Xil_DCacheFlushRange is not reached. Please find attach= ed my xen bootlog.txt.
> > > > I am still unable to find out why??
> > > >
> > > > Can you please atleast verify that my xen.dtsi, and pl.= dtb is correct? and do i need dtdev and device_tree in my guest config file=
> when
> > > it
> > > > is already added to xen.dtsi?
> > > >
> > > > Best Regards,
> > > > Prem
> > > >
> > > >
> >>>__________________________________________________________= ___________________________________________________________________________= ___
> _
> > _
> > > _
> > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > Sent: Saturday, May 15, 2021 00:25
> > > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <= ;brian.woods@xilinx.com>; = Julien Grall <julien@xen.org>; Stefano
> > > > Stabellini <sstabellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> > <fnuv@xilinx.com>; > > > > edgari@xilinx.com<= /a> <edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > > JOVITAC@xilinx.co= m <JOVITAC@xilinx.com><= br> > > > > Subject: Re: Help: Information required for AXI DMA pas= sthrough for PL masters in ZCU102 dev kit  
> > > > Hi Prem,
> > > >
> > > > Some older versions of Xil_DCacheFlushRange were implem= ented using
> > > > deprecated set/way instructions that are known to cause= problems in
> > > > virtualized environments.
> > > >
> > > > More recent implementations use the "dc civac"= ; intruction that shouldn't
> > > > have any issues.
> > > >
> > > > Can you double-check that you are calling the 64-bit ve= rsion implemented
> > > > by CIVAC?
> > > >
> >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb= 18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#= L4
> 1
> > 4
> > >
> > > >
> > > >
> > > >
> > > >
> > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > Hi Stefano, 
> > > > > Thanks for your reply. Yes the axidma application = is a baremetal application from the xilinx vitis ide example. 
> > > > > Also yes, I have already run hello world as DomU g= uest, with UART1.
> > > > >
> > > > > I am using the simple mode using polling and not i= nterrupts(they are disabled in the c code), which is Why I didn't include i= n the
> > > guest
> > > > > config file. This works well when I compile it nor= mally (as EL3). When compiled as hypervisor guest, the execution stops befo= re the
> > > > > function xil_dcacheflushrange(). Please find the c= code attached
> > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxP= rocessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c&nbs= p;
> > > > >
> > > > > I found the SATA example similar to my use case, a= lso using DMA and SMMU. I just used it as a reference to create my pl.dtb t= o pass
> > > > through
> > > > > in the guest config.(from pl.dtsi, which I manuall= y created).
> > > > >
> > > > > Thanks and Best Regards,
> > > > > Prem
> > > > >
> > > > > Get Outlook for Android
> > > > >
> >>>>______________________________________________________= ___________________________________________________________________________= ______
> _
> > _
> > > _
> > > > _
> > > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > Sent: Friday 14 May 2021, 23:16
> > > > > To: Prem Harikrishnan
> > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall;= Stefano Stabellini; xen-users@lists.xenproject.org; fnuv= @xilinx.com;
> > > > edgari@xilinx.com<= /a>;
> > > > > bwoods288@g= mail.com; Renato Costa Amorim; JOVITAC@xilinx.com
> > > > > Subject: Re: Help: Information required for AXI DM= A passthrough for PL masters in ZCU102 dev kit
> > > > >
> > > > > I take that the guest kernel "/bin/xaxidma_ex= ample_simple_poll_1.bin" is
> > > > > a baremetal application? Can you run it successful= ly, just printing
> > > > > "hello world", if you only assign the UA= RT and nothing else?
> > > > >
> > > > > I am asking just to verify that you can run the ba= remetal VM
> > > > > successfully, aside from the PL device assignment.=
> > > > >
> > > > >
> > > > > In regards to the PL device assignment, I'll let B= rian answer on the
> > > > > Vivado configuration and SMID calculation. But I n= oticed that you only
> > > > > assigned IRQ 54 to the DomU which is the one for U= ART1. You haven't
> > > > > assigned any IRQs for axi_dma_0. Looking at pl_fro= m_petalinux.dtsi, it
> > > > > looks like there are two related IRQs: 121 and 122= .
> > > > >
> > > > > Finally, why did you mention SATA passthrough in y= our reply? I don't
> > > > > follow: I cannot see any SATA controller assignmen= t in your
> > > > > configuration.
> > > > >
> > > > >
> > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > > Dear Brian, Stefano and Julien,
> > > > > >
> > > > > > Thank you very much for your replies.
> > > > > > Hi Brian and Stefano, Can you please help me = with the following questions?
> > > > > >
> > > > > > @Brian Woods Please find attached my vivado c= onfiguration, when i added my AXI DMA now running on simple polling mode(pr= eviously
> i
> > > > tried
> > > > > it
> > > > > > with Scatter Gather mode), Run Automation aut= omatically generated, 1 AXI Interconnect and 1 smart connect. Since there i= s only 1
> > > master
> > > > > and
> > > > > > I use the S_AXI _HP0_FPD, I finally get a val= ue of 0xE80 for the stream IDs.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters According to this link section 6.5 I have
> > manually
> > > > tied
> > > > > > of AxPROT bits to value of 0x2 to create non = secure transactions. Can you please confirm that my Vivado configuration is= correct?
> I
> > > can
> > > > > > update you soon with an ILA trace on Vivado.<= br> > > > > > >
> > > > > > @Stefano Stabellini Please find attached my p= l.dtsi generated from petalinux and system.dtsi also generated after manual= ly adding
> > > > > xen.dtsi.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xe= n+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using
> this
> > > > SATA
> > > > > > passthrough, i made my own pl.dtsi for passth= rough used in dma.cfg. I could really use your help to identify what is mis= sing in
> my
> > > xen
> > > > > > configuration.
> > > > > >
> > > > > > Thanks and Best Regards,
> > > > > > Prem
> > > > > >
> >>>>>__________________________________________________= ___________________________________________________________________________= _________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > From: Brian Woods <brian.woods@xilinx.com>
> > > > > > Sent: Thursday, May 13, 2021 17:13
> > > > > > To: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > > Cc: Julien Grall <julien@xen.org>; Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; = Stefano Stabellini
> > <sstabellini@kernel.= org>;
> > > > > > xen-users@lists.xenproject.org <xen-users@lists.xenproject.org>; brian.woods@xilinx.com <brian.woods@xilinx.com>; fnuv@xilinx.com
> > > > > > <fnuv@x= ilinx.com>; edgari@xilinx.com <edgari@xilin= x.com>; bwoods288@gmail.com <bwoods288@gmail.com>
> > > > > > Subject: Re: Help: Information required for A= XI DMA passthrough for PL masters in ZCU102 dev kit  
> > > > > > Prem,
> > > > > >
> > > > > > Sorry for the late email, I've been under the= weather and have been away
> > > > > > from my computer.  In the Zynq SOCs this= is how the SMMU IDs in PL are
> > > > > > calculated:
> > > > > >
> > > > > > 14-10: TBU bits
> > > > > > 9-6: Master ID bits
> > > > > > 5-0: AXI ID bits
> > > > > >
> > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultras= cale-trm.pdf
> > > > > > To look up the TBU value, see UG1085 and look= for the "System Masters"
> > > > > > table which is table 16-4 on page 409.
> > > > > >
> > > > > > For the master ID, see UG1085 and look for th= e "Master IDs List" table
> > > > > > which is table 16-13 on page 429.
> > > > > >
> > > > > > The AXI ID bits is a bit trickery since it's = going to be out in PL.
> > > > > > See: https://www.xilinx.com/support/answers/69447.html=
> > > > > > With SmartConnect all the AXI IDs are 0, they= aren't passed on.  There
> > > > > > are work arounds.  Here's a couple of ex= amples (with example numbers):
> > > > > >
> > > > > > AXI master -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >        &nb= sp;            =        -> PS slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >        &nb= sp;            =             -> PS= slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >        &nb= sp;            =             &nb= sp;            =            -> PS slave= port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > The "sideband -> SmartConenct -> s= ideband" can also be functionally
> > > > > > replaced with "AXI Interconnect" to= my knowledge.  So the AXI ID bits are
> > > > > > fairly simple but with some caveats.
> > > > > >
> > > > > > You can also read in the SMMU faults from Xen= and use:
> > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_s= pecification.pdf
> > > > > > to decode them. That should tell you the SMMU= IDs as well.
> > > > > >
> > > > > > Let me know if this isn't clear or you have a= ny other questions.
> > > > > >
> > > > > > Brian
> > > > > >
> > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Ste= fano Stabellini wrote:
> > > > > > > On Mon, 10 May 2021, Julien Grall wrote:=
> > > > > > > > On 26/04/2021 15:41, Prem Harikrish= nan wrote:
> > > > > > > > > Hello everyone,
> > > > > > > >
> > > > > > > > Hi Prem,
> > > > > > > >
> > > > > > > > > I am using the latest version = of the xilinx mpsoc zcu102 development board
> > > > > > > > > and i am trying to create a ba= rematal application that uses the AXI DMA on
> > > > > > > > > the programmable logic, using = the scatter gather example from the xilinx
> > > > > > > > > repository. This works perfect= ly well for the baremetal application. The
> > > > > > > > > diagram below represents the i= nformation flow. The AXI DMA and the AXI data
> > > > > > > > > FIFO are in the Programable lo= gic (FPGA). This AXI DMA is out of the box IP
> > > > > > > > > from Vivado and uses a single = channel (Does not use AxUSER) which means the
> > > > > > > > > AXI ID cannot manually be set.=
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Now i want to make this as a b= aremetal hypervisor guest, in future this will
> > > > > > > > > be replaced by a custom IP wit= h cache colouring enabled. I want to pass
> > > > > > > > > through the AXI DMA in the PL.= (Not to be used by Dom0)
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I followed this tutorial Barem= etal + DomU
> > > > > > > > > <htt= ps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842536/XEN+EL1+Baremet= al+DomU>
> > > > > > > > > guest changed the base address= to 0x4000000,(1GB allocated to Dom-0) to
> > > > > > > > > create my EL1 binary. I used P= etalinux 2020.2 to generate my linux, xen
> > > > > > > > > image and use tftp to boot. > > > > > > > > >
> > > > > > > > >  From what i understand f= rom the xilinx tutorials Xen+and+PL+Masters
> > > > > > > > > <https:/= /xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters<= /a>>
> > > > > > > > > section 3 and MPSOC SMMU
> > > > > > > > > <https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+UltraS= cale+MPSOC+SMMU>
> > > > > > > > > section 4, stream ids are requ= ired by the SMMU to get the correct address
> > > > > > > > > translation.
> > > > > > > > >
> > > > > > > > > I am still unable to figure ou= t how to get the iommu property for my AXI DMA
> > > > > > > > > and how to set the dtdev confi= g for my hypervisor guest.
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I can also see some new update= s with the XEN 2020.1 and 2020.2 releases
> > > > > > > > > which i can be useful to my ap= plication
> > > > > > > > >
> > > > > > > > >   *   1:1 = memory mappings for Xen virtual machines, enabling device
> > > > > > > > >     assign= ments without SMMU
> > > > > > > > >   *
> > > > > > > > >      =  Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > >     Xen vi= rtual machines
> > > > > > > > >   *   Supp= ort for PL Device Passthrough to DomU in Xen
> > > > > > > >
> > > > > > > > You are usiong a version of Xen tha= t has been customised by Xilinx. So I would
> > > > > > > > recommend to contact them directly.=
> > > > > > > >
> > > > > > > > I have CCed Stefano who might be ab= le to help you.
> > > > > > >
> > > > > > > Hi Julien,
> > > > > > >
> > > > > > > Many thanks for CC'ing me, I missed the = email.
> > > > > > >
> > > > > > >
> > > > > > > Hi Prem,
> > > > > > >
> > > > > > > Let me CC a few people that might be abl= e to help.
> > > > > >
> > > > > >
> > > > >
> > > > >
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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Stefano and Mubin, Thank you very much for your replies. @Stefano Stabellini Sorry to bother y= ou again, and thank you for pointing this out, the TTC0 is by default enabl= ed for FreeRTOS to generate ticks, although this says only for R5 core, i w= ould have never figured this out. As soon as I added the irqs and iomem and= gave a xen passthrough in the xen.dtsi as you have suggested, FreeRTOS gue= st started working for other peripherals except for my DMA (FreeRTOS guest = does not work with interrupt and DMA). I can see my DMA is enabled because i have LEDs configured to blink for eve= ry interrupt I get from the PL. I don't see my interrupts being processed, = but when I destroy the guest, I get this output periodically when an interr= upt occurs. (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 >From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/= A/pages/18842066/Xen+and+PL+Masters Xen and PL Masters - Xilinx Wiki - Confluence 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of = PL masters must be added to the Linux Dom0 device tree. Automated device tr= ee generation does not generate the stream IDs for the PL masters so that t= he user must add them into the device tree manually. xilinx-wiki.atlassian.net The fault indicates an unidentified stream ID has been received by the SMMU= as shown in the GFSR register. The GFSYNR1 register contains the stream ID= that was unidentified. A stream ID of 0xE80 was unidentified in the above = fault. But I think i have already added that in my smmu and iommu in xen.dtsi beca= use my baremetal application works well as expected. I have attached my xen= .dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). What could I be missing here? Do I have to enable the ttc0 in the device tr= ee? Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: = 99990 KHz mean when XEN boots up? Thanks, I look forward for your reply. Best Regards, Prem ________________________________ From: Stefano Stabellini Sent: Friday, May 28, 2021 20:43 To: Prem Harikrishnan Cc: Stefano Stabellini ; xen-users@lists.xen= project.org ; JOVITAC@xilinx.com ; MUBINUSM@xilinx.com Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit >From the gpa address, it looks like FreeRTOS is trying to access the TTC timer? If you look at device tree, the corresponding node is timer@ff110000. If FreeRTOS is configured to access the TTC timer, then you need to assign it to it. Did you assign the TTC timer to the FreeRTOS domU by any chance? You can do that by adding: irqs =3D [ 68, 69, 70 ] iomem =3D [ "0xff110,1" ] On Fri, 28 May 2021, Prem Harikrishnan wrote: > Hi Stefano, > Thanks for your reply. I am pretty sure I followed the steps you mentione= d below to run the FreeRTOS hello world example. I already added > printfs and i can see XEN cannot start the scheduler and i get the follow= ing out put on XEN. > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 memfl= ags=3D0xc0 (0 of 64) > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0 > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0xff= 11000c gpa=3D0x000000ff11000c > > > I also see that according to this article > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as= -a-Xen-Virtual-Machine/ba-p/947030 > [52662iFAD1733707609204?v=3Dv2] > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks Wh= at is FreeRTOS? The FreeRTOS kernel is a market leading real-time > operating system for embedded systems. As embedded applications grow in c= omplexity, there is a growing need for a lightweight kernel > capable of task scheduling... > forums.xilinx.com > FreeRTOS does not run out of the box for XEN, although the article is 2 y= ears old, I am not sure if there are any updates on this after > that. Can you please confirm? > > Thanks and Best Regards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Stefano Stabellini > Sent: Friday, May 28, 2021 02:51 > To: Prem Harikrishnan > Cc: Stefano Stabellini ; xen-users@lists.x= enproject.org ; JOVITAC@xilinx.com > ; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > +Mubin > > > Hi Prem, > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps: > > - source settings64.sh from Vitis builds > - xsct > - set WORKSPACE . > - setws -switch $WORKSPACE > - app create -name freertos-hello-world -template {FreeRTOS Hello World} = -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > - bsp config stdin psu_uart_1 > - bsp config stdout psu_uart_1 > - bsp config hypervisor_guest true > - Go to application source path and modify the linker script start addres= s to 0x40000000, > - app build -name freertos-hello-world > - Run command to generate BIN file from executable "aarch64-linux-gnu-obj= copy -O binary --gap-fill 0 BOOT.BIN" > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > might be able to provide additional info. > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Sorry to bother you again. > > I am currently trying to run my custom IP which sends periodic dma inte= rrupts to the PS with cache coloring enabled. I have now compiled > my > > guest running with FreeRTOS and it generates a trap. > > Petalinux and VITIS IDE Version is 2020.2. > > > > Please find the log attached. After the trap occurs, for every interrup= t XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault: > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config fro= m apu_freertos.cfg > > (XEN) Dom1 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D1 mem= flags=3D0xc0 (0 of 64) > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache=3D0 > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > (XEN) sched_null.c:344: 1 <-- d1v0 > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gva=3D0x= ff11000c gpa=3D0x000000ff11000c > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > The same application works as expected without FreeRTOS, i.e as a barem= etal guest. I look forward for your comment on this. > > > > Although i see performance degradation, normally i can measure delta ti= me for each interrupt configured to 1ms (without XEN), with XEN > for > > the same measurement shows 16 ms for each interval (but the performance= is not a priority for now). > > Thanks and Best Regards, > > Prem > > > >________________________________________________________________________= __________________________________________________________________ > _ > > From: Stefano Stabellini > > Sent: Tuesday, May 18, 2021 20:09 > > To: Prem Harikrishnan > > Cc: Stefano Stabellini ; xen-users@lists= .xenproject.org ; > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL = masters in ZCU102 dev kit > > Great to hear! Thank you for reporting back. > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > Dear Stefano, > > > Thank you very much for your guidance and support. I finally fixed th= e issue. I made an error in base memory address like you pointed > > out. > > > I actually modified the base address correctly to 0x40000000 but the = default C code had an additional offset of 0x1100000 , and the > DomU > > > memory allocated was only 8MB. I either had to change the offset or a= llocate more memory to the DomU guest which i missed until you > > pointed > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and th= e SMID required is 0xE80. > > > > > > Thanks again i was able get my custom IP also working as an AXI maste= r from PL. > > > > > > Best Regards, > > > Prem > > > > >>_______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 02:35 > > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini ; Brian Woods <= brian.woods@xilinx.com>; Julien Grall ; Stefano > > > Stabellini ; xen-users@lists.xenproject.org <= xen-users@lists.xenproject.org>; fnuv@xilinx.com > ; > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim ; > > > JOVITAC@xilinx.com > > > Subject: Re: Help: Information required for AXI DMA passthrough for P= L masters in ZCU102 dev kit > > > Your configuration looks correct as far as I can tell. > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > block. You don't need device_tree because your baremetal application = is > > > not going to read it, but it is not going to cause any issues either. > > > > > > When you say "the execution does not complete the loop at line 244", = it > > > means that you see the execution entering the loop and then never > > > leaving? Like an infinite loop? > > > > > > If so, then I imagine the issue could be that the application is > > > crashing when trying to access TxBufferPtr, which is pointing to > > > TX_BUFFER_BASE, which is: > > > > > > > > > #ifndef DDR_BASE_ADDR > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > DEFAULT SET TO 0x01000000 > > > #define MEM_BASE_ADDR 0x01000000 > > > #else > > > #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) > > > #endif > > > > > > #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > Hi Stefano, > > > > Thanks again for your reply and your suggestion. I did try to repl= ace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRange(works > > only > > > > in EL3), I added printfs to debug, i can see that the execution doe= s not complete the loop at line 244 > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPL= ib/drivers/axidma/examples/xaxidma_example_simple_poll.c and > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bo= otlog.txt. > > > > I am still unable to find out why?? > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is corre= ct? and do i need dtdev and device_tree in my guest config file > when > > > it > > > > is already added to xen.dtsi? > > > > > > > > Best Regards, > > > > Prem > > > > > > > > > >>>______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > Sent: Saturday, May 15, 2021 00:25 > > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini ; Brian Woods= ; Julien Grall ; Stefano > > > > Stabellini ; xen-users@lists.xenproject.org= ; fnuv@xilinx.com > > ; > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim ; > > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for= PL masters in ZCU102 dev kit > > > > Hi Prem, > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > deprecated set/way instructions that are known to cause problems in > > > > virtualized environments. > > > > > > > > More recent implementations use the "dc civac" intruction that shou= ldn't > > > > have any issues. > > > > > > > > Can you double-check that you are calling the 64-bit version implem= ented > > > > by CIVAC? > > > > > >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3= 577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L4 > 1 > > 4 > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks for your reply. Yes the axidma application is a baremetal = application from the xilinx vitis ide example. > > > > > Also yes, I have already run hello world as DomU guest, with UART= 1. > > > > > > > > > > I am using the simple mode using polling and not interrupts(they = are disabled in the c code), which is Why I didn't include in the > > > guest > > > > > config file. This works well when I compile it normally (as EL3).= When compiled as hypervisor guest, the execution stops before the > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcess= orIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c > > > > > > > > > > I found the SATA example similar to my use case, also using DMA a= nd SMMU. I just used it as a reference to create my pl.dtb to pass > > > > through > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > Thanks and Best Regards, > > > > > Prem > > > > > > > > > > Get Outlook for Android > > > > > > >>>>_____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > To: Prem Harikrishnan > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabel= lini; xen-users@lists.xenproject.org; fnuv@xilinx.com; > > > > edgari@xilinx.com; > > > > > bwoods288@gmail.com; Renato Costa Amorim; JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.= bin" is > > > > > a baremetal application? Can you run it successfully, just printi= ng > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on = the > > > > > Vivado configuration and SMID calculation. But I noticed that you= only > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven= 't > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dts= i, it > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I do= n't > > > > > follow: I cannot see any SATA controller assignment in your > > > > > configuration. > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > Thank you very much for your replies. > > > > > > Hi Brian and Stefano, Can you please help me with the following= questions? > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when= i added my AXI DMA now running on simple polling mode(previously > i > > > > tried > > > > > it > > > > > > with Scatter Gather mode), Run Automation automatically generat= ed, 1 AXI Interconnect and 1 smart connect. Since there is only 1 > > > master > > > > > and > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for th= e stream IDs. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/= Xen+and+PL+Masters According to this link section 6.5 I have > > manually > > > > tied > > > > > > of AxPROT bits to value of 0x2 to create non secure transaction= s. Can you please confirm that my Vivado configuration is correct? > I > > > can > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated f= rom petalinux and system.dtsi also generated after manually adding > > > > > xen.dtsi. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561= /Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > this > > > > SATA > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.= cfg. I could really use your help to identify what is missing in > my > > > xen > > > > > > configuration. > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > >>>>>____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Brian Woods > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > To: Stefano Stabellini > > > > > > Cc: Julien Grall ; Prem Harikrishnan ; Stefano Stabellini > > ; > > > > > > xen-users@lists.xenproject.org = ; brian.woods@xilinx.com ; fnuv@xilinx.com > > > > > > ; edgari@xilinx.com ; bwood= s288@gmail.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough= for PL masters in ZCU102 dev kit > > > > > > Prem, > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have = been away > > > > > > from my computer. In the Zynq SOCs this is how the SMMU IDs in= PL are > > > > > > calculated: > > > > > > > > > > > > 14-10: TBU bits > > > > > > 9-6: Master ID bits > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085= -zynq-ultrascale-trm.pdf > > > > > > To look up the TBU value, see UG1085 and look for the "System M= asters" > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List= " table > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in= PL. > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.= There > > > > > > are work arounds. Here's a couple of examples (with example nu= mbers): > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > -> PS s= lave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be function= ally > > > > > > replaced with "AXI Interconnect" to my knowledge. So the AXI I= D bits are > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_ar= chitecture_specification.pdf > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions= . > > > > > > > > > > > > Brian > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wr= ote: > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 = development board > > > > > > > > > and i am trying to create a barematal application that us= es the AXI DMA on > > > > > > > > > the programmable logic, using the scatter gather example = from the xilinx > > > > > > > > > repository. This works perfectly well for the baremetal a= pplication. The > > > > > > > > > diagram below represents the information flow. The AXI DM= A and the AXI data > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is= out of the box IP > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSE= R) which means the > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, = in future this will > > > > > > > > > be replaced by a custom IP with cache colouring enabled. = I want to pass > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocate= d to Dom-0) to > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate= my linux, xen > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > From what i understand from the xilinx tutorials Xen+and= +PL+Masters > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the= correct address > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu prop= erty for my AXI DMA > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2= 020.2 releases > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > * 1:1 memory mappings for Xen virtual machines, enabl= ing device > > > > > > > > > assignments without SMMU > > > > > > > > > * > > > > > > > > > Static assignment of PL blocks, including bus-maste= ring blocks, to > > > > > > > > > Xen virtual machines > > > > > > > > > * Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by= Xilinx. So I would > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --_000_VI1PR05MB4430B62D7D79E47B784FA34C893F9VI1PR05MB4430eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Stefano and Mubin,
Thank you very much for your replies.

I can see my DMA is enabled because i have LEDs configured to blink for eve= ry interrupt I get from the PL. I don't see my interrupts being processed, = but when I destroy the guest, I get this output periodically when an interr= upt occurs.

(XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious<= br> (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
(XEN) smmu: /smmu@fd800000: Unexpected global= fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
(XEN) smmu: /smmu@fd800000: Unexpected global= fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of = PL masters must be added to the Linux Dom0 device tree. Automated device tr= ee generation does not generate the stream IDs for the PL masters so that t= he user must add them into the device tree manually.
xilinx-wiki.atlassian.net
The fault indicates an= unidentified stream ID has been received by the SMMU as shown in the GFSR = register. The GFSYNR1 register contains the stream ID that was unidentified= . A stream ID of 0xE80 was unidentified in the above fault.

But I think i have already added that in my s= mmu and iommu in xen.dtsi because my baremetal application works well as ex= pected. I have attached my xen.dtsi, system.dtsi, baremetal.cfg(working) an= d freertos.cfg(not working).
What could I be missing here? Do I have to en= able the ttc0 in the device tree?
Also what does (XEN) Generic Timer IRQ: phys= =3D30 hyp=3D26 virt=3D27 Freq: 99990 KHz mean when XEN boots up?
Thanks, I look forward for your reply.

Best Regards,
Prem


From: Stefano Stabellini &l= t;stefano.stabellini@xilinx.com>
Sent: Friday, May 28, 2021 20:43
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-us= ers@lists.xenproject.org <xen-users@lists.xenproject.org>; JOVITAC@xi= linx.com <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilin= x.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit
 
From the gpa address, it looks like FreeRTOS is tr= ying to access the TTC
timer? If you look at device tree, the corresponding node is
timer@ff110000.

If FreeRTOS is configured to access the TTC timer, then you need to
assign it to it. Did you assign the TTC timer to the FreeRTOS domU by
any chance?

You can do that by adding:

irqs =3D [ 68, 69, 70 ]
iomem =3D [ "0xff110,1" ]


On Fri, 28 May 2021, Prem Harikrishnan wrote:
> Hi Stefano,
> Thanks for your reply. I am pretty sure I followed the steps you menti= oned below to run the FreeRTOS hello world example. I already added
> printfs and i can see XEN cannot start the scheduler and i get the fol= lowing out put on XEN.
>
> Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ]
> (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 me= mflags=3D0xc0 (0 of 64)
> (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0
> (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0= xff11000c gpa=3D0x000000ff11000c
>
>
> I also see that according to this article
> https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a= -Xen-Virtual-Machine/ba-p/947030
> [52662iFAD1733707609204?v=3Dv2]
> Partner: FreeRTOS as a Xen Virtual Machine - Community Forums
> Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks= What is FreeRTOS? The FreeRTOS kernel is a market leading real-time
> operating system for embedded systems. As embedded applications grow i= n complexity, there is a growing need for a lightweight kernel
> capable of task scheduling...
> forums.xilinx.com
> FreeRTOS does not run out of the box for XEN, although the article is = 2 years old, I am not sure if there are any updates on this after
> that. Can you please confirm?
>
> Thanks and Best Regards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> Sent: Friday, May 28, 2021 02:51
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-user= s@lists.xenproject.org <xen-users@lists.xenproject.org>; JOVITAC@xili= nx.com
> <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilinx.co= m>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
> +Mubin
>
>
> Hi Prem,
>
> Did you make sure to build FreeRTOS as "hypervisor guest"? I= think
> FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps:
>
> - source settings64.sh from Vitis builds
> - xsct
> - set WORKSPACE .
> - setws -switch $WORKSPACE
> - app create -name freertos-hello-world -template {FreeRTOS Hello Worl= d} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx
> - bsp config stdin psu_uart_1
> - bsp config stdout psu_uart_1
> - bsp config hypervisor_guest true
> - Go to application source path and modify the linker script start add= ress to 0x40000000,
> - app build -name freertos-hello-world
> - Run command to generate BIN file from executable "aarch64-linux= -gnu-objcopy -O binary --gap-fill 0  <elf path> BOOT.BIN" >
> The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed,<= br> > might be able to provide additional info.
>
>
>
> On Thu, 27 May 2021, Prem Harikrishnan wrote:
> > Hi Stefano,
> > Sorry to bother you again.
> > I am currently trying to run my custom IP which sends periodic dm= a interrupts to the PS with cache coloring enabled. I have now compiled
> my
> > guest running with FreeRTOS and it generates a trap.
> > Petalinux and VITIS IDE Version is 2020.2.
> >
> > Please find the log attached. After the trap occurs, for every in= terrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault:
> > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing conf= ig from apu_freertos.cfg
> > (XEN) Dom1 colors: [ 8 ]
> > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id= =3D1 memflags=3D0xc0 (0 of 64)
> > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache= =3D0
> > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache= =3D0
> > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000
> > (XEN) sched_null.c:344: 1 <-- d1v0
> > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gv= a=3D0xff11000c gpa=3D0x000000ff11000c
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > The same application works as expected without FreeRTOS, i.e as a= baremetal guest. I look forward for your comment on this.
> >
> > Although i see performance degradation, normally i can measure de= lta time for each interrupt configured to 1ms (without XEN), with XEN
> for
> > the same measurement shows 16 ms for each interval (but the perfo= rmance is not a priority for now).
> > Thanks and Best Regards,
> > Prem
> >
> >__________________________________________________________________= ________________________________________________________________________ > _
> > From: Stefano Stabellini <stefano.stabellini@xilinx.com> > > Sent: Tuesday, May 18, 2021 20:09
> > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen= -users@lists.xenproject.org <xen-users@lists.xenproject.org>;
> JOVITAC@xilinx.com
> > <JOVITAC@xilinx.com>
> > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit  
> > Great to hear! Thank you for reporting back.
> >
> >
> > On Tue, 18 May 2021, Prem Harikrishnan wrote:
> > > Dear Stefano,
> > > Thank you very much for your guidance and support. I finally= fixed the issue. I made an error in base memory address like you pointed > > out.
> > > I actually modified the base address correctly to 0x40000000= but the default C code had an additional offset of 0x1100000 , and the
> DomU
> > > memory allocated was only 8MB. I either had to change the of= fset or allocate more memory to the DomU guest which i missed until you
> > pointed
> > > out. Additionally i had to set to AxPROT bits to 0x2 in Viva= do and the SMID required is 0xE80.
> > >
> > > Thanks again i was able get my custom IP also working as an = AXI master from PL.
> > >
> > > Best Regards,
> > > Prem
> > >
> >>______________________________________________________________= ___________________________________________________________________________=
> _
> > _
> > > From: Stefano Stabellini <stefano.stabellini@xilinx.com&g= t;
> > > Sent: Tuesday, May 18, 2021 02:35
> > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com&g= t;
> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>= ; Brian Woods <brian.woods@xilinx.com>; Julien Grall <julien@xen.o= rg>; Stefano
> > > Stabellini <sstabellini@kernel.org>; xen-users@lists.x= enproject.org <xen-users@lists.xenproject.org>; fnuv@xilinx.com
> <fnuv@xilinx.com>;
> > > edgari@xilinx.com <edgari@xilinx.com>; bwoods288@gmail= .com <bwoods288@gmail.com>; Renato Costa Amorim <renato.amorim@evo= leotech.com>;
> > > JOVITAC@xilinx.com <JOVITAC@xilinx.com>
> > > Subject: Re: Help: Information required for AXI DMA passthro= ugh for PL masters in ZCU102 dev kit  
> > > Your configuration looks correct as far as I can tell.
> > >
> > > You need dtdev because it triggers the SMMU configuration fo= r your PL
> > > block. You don't need device_tree because your baremetal app= lication is
> > > not going to read it, but it is not going to cause any issue= s either.
> > >
> > > When you say "the execution does not complete the loop = at line 244", it
> > > means that you see the execution entering the loop and then = never
> > > leaving? Like an infinite loop?
> > >
> > > If so, then I imagine the issue could be that the applicatio= n is
> > > crashing when trying to access TxBufferPtr, which is pointin= g to
> > > TX_BUFFER_BASE, which is:
> > >
> > >
> > > #ifndef DDR_BASE_ADDR
> > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \=
> > >           =        DEFAULT SET TO 0x01000000
> > > #define MEM_BASE_ADDR      &nb= sp;    0x01000000
> > > #else
> > > #define MEM_BASE_ADDR      &nb= sp;    (DDR_BASE_ADDR + 0x1000000)
> > > #endif
> > >
> > > #define TX_BUFFER_BASE      &n= bsp;   (MEM_BASE_ADDR + 0x00100000)
> > >
> > >
> > >
> > > Can you double check that TX_BUFFER_BASE is pointing to a co= rrect
> > > address? Memory starts at 0x40000000 in a Xen DomU.
> > >
> > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly?
> > >
> > >
> > > On Mon, 17 May 2021, Prem Harikrishnan wrote:
> > > > Hi Stefano,
> > > > Thanks again for your reply and your suggestion.  = I did try to replace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRang= e(works
> > only
> > > > in EL3), I added printfs to debug, i can see that the e= xecution does not complete the loop at line 244
> > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drive= rs/axidma/examples/xaxidma_example_simple_poll.c  and
> > > > Xil_DCacheFlushRange is not reached. Please find attach= ed my xen bootlog.txt.
> > > > I am still unable to find out why??
> > > >
> > > > Can you please atleast verify that my xen.dtsi, and pl.= dtb is correct? and do i need dtdev and device_tree in my guest config file=
> when
> > > it
> > > > is already added to xen.dtsi?
> > > >
> > > > Best Regards,
> > > > Prem
> > > >
> > > >
> >>>__________________________________________________________= ___________________________________________________________________________= ___
> _
> > _
> > > _
> > > > From: Stefano Stabellini <stefano.stabellini@xilinx.= com>
> > > > Sent: Saturday, May 15, 2021 00:25
> > > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.= com>
> > > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.co= m>; Brian Woods <brian.woods@xilinx.com>; Julien Grall <julien@= xen.org>; Stefano
> > > > Stabellini <sstabellini@kernel.org>; xen-users@li= sts.xenproject.org <xen-users@lists.xenproject.org>; fnuv@xilinx.com<= br> > > <fnuv@xilinx.com>;
> > > > edgari@xilinx.com <edgari@xilinx.com>; bwoods288@= gmail.com <bwoods288@gmail.com>; Renato Costa Amorim <renato.amori= m@evoleotech.com>;
> > > > JOVITAC@xilinx.com <JOVITAC@xilinx.com>
> > > > Subject: Re: Help: Information required for AXI DMA pas= sthrough for PL masters in ZCU102 dev kit  
> > > > Hi Prem,
> > > >
> > > > Some older versions of Xil_DCacheFlushRange were implem= ented using
> > > > deprecated set/way instructions that are known to cause= problems in
> > > > virtualized environments.
> > > >
> > > > More recent implementations use the "dc civac"= ; intruction that shouldn't
> > > > have any issues.
> > > >
> > > > Can you double-check that you are calling the 64-bit ve= rsion implemented
> > > > by CIVAC?
> > > >
> >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb= 18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#= L4
> 1
> > 4
> > >
> > > >
> > > >
> > > >
> > > >
> > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > Hi Stefano, 
> > > > > Thanks for your reply. Yes the axidma application = is a baremetal application from the xilinx vitis ide example. 
> > > > > Also yes, I have already run hello world as DomU g= uest, with UART1.
> > > > >
> > > > > I am using the simple mode using polling and not i= nterrupts(they are disabled in the c code), which is Why I didn't include i= n the
> > > guest
> > > > > config file. This works well when I compile it nor= mally (as EL3). When compiled as hypervisor guest, the execution stops befo= re the
> > > > > function xil_dcacheflushrange(). Please find the c= code attached
> > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxP= rocessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c&nbs= p;
> > > > >
> > > > > I found the SATA example similar to my use case, a= lso using DMA and SMMU. I just used it as a reference to create my pl.dtb t= o pass
> > > > through
> > > > > in the guest config.(from pl.dtsi, which I manuall= y created).
> > > > >
> > > > > Thanks and Best Regards,
> > > > > Prem
> > > > >
> > > > > Get Outlook for Android
> > > > >
> >>>>______________________________________________________= ___________________________________________________________________________= ______
> _
> > _
> > > _
> > > > _
> > > > > From: Stefano Stabellini <stefano.stabellini@xi= linx.com>
> > > > > Sent: Friday 14 May 2021, 23:16
> > > > > To: Prem Harikrishnan
> > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall;= Stefano Stabellini; xen-users@lists.xenproject.org; fnuv@xilinx.com;
> > > > edgari@xilinx.com;
> > > > > bwoods288@gmail.com; Renato Costa Amorim; JOVITAC@= xilinx.com
> > > > > Subject: Re: Help: Information required for AXI DM= A passthrough for PL masters in ZCU102 dev kit
> > > > >
> > > > > I take that the guest kernel "/bin/xaxidma_ex= ample_simple_poll_1.bin" is
> > > > > a baremetal application? Can you run it successful= ly, just printing
> > > > > "hello world", if you only assign the UA= RT and nothing else?
> > > > >
> > > > > I am asking just to verify that you can run the ba= remetal VM
> > > > > successfully, aside from the PL device assignment.=
> > > > >
> > > > >
> > > > > In regards to the PL device assignment, I'll let B= rian answer on the
> > > > > Vivado configuration and SMID calculation. But I n= oticed that you only
> > > > > assigned IRQ 54 to the DomU which is the one for U= ART1. You haven't
> > > > > assigned any IRQs for axi_dma_0. Looking at pl_fro= m_petalinux.dtsi, it
> > > > > looks like there are two related IRQs: 121 and 122= .
> > > > >
> > > > > Finally, why did you mention SATA passthrough in y= our reply? I don't
> > > > > follow: I cannot see any SATA controller assignmen= t in your
> > > > > configuration.
> > > > >
> > > > >
> > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > > Dear Brian, Stefano and Julien,
> > > > > >
> > > > > > Thank you very much for your replies.
> > > > > > Hi Brian and Stefano, Can you please help me = with the following questions?
> > > > > >
> > > > > > @Brian Woods Please find attached my vivado c= onfiguration, when i added my AXI DMA now running on simple polling mode(pr= eviously
> i
> > > > tried
> > > > > it
> > > > > > with Scatter Gather mode), Run Automation aut= omatically generated, 1 AXI Interconnect and 1 smart connect. Since there i= s only 1
> > > master
> > > > > and
> > > > > > I use the S_AXI _HP0_FPD, I finally get a val= ue of 0xE80 for the stream IDs.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters According to this link section 6.5 I have
> > manually
> > > > tied
> > > > > > of AxPROT bits to value of 0x2 to create non = secure transactions. Can you please confirm that my Vivado configuration is= correct?
> I
> > > can
> > > > > > update you soon with an ILA trace on Vivado.<= br> > > > > > >
> > > > > > @Stefano Stabellini Please find attached my p= l.dtsi generated from petalinux and system.dtsi also generated after manual= ly adding
> > > > > xen.dtsi.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xe= n+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using
> this
> > > > SATA
> > > > > > passthrough, i made my own pl.dtsi for passth= rough used in dma.cfg. I could really use your help to identify what is mis= sing in
> my
> > > xen
> > > > > > configuration.
> > > > > >
> > > > > > Thanks and Best Regards,
> > > > > > Prem
> > > > > >
> >>>>>__________________________________________________= ___________________________________________________________________________= _________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > From: Brian Woods <brian.woods@xilinx.com&= gt;
> > > > > > Sent: Thursday, May 13, 2021 17:13
> > > > > > To: Stefano Stabellini <stefano.stabellini= @xilinx.com>
> > > > > > Cc: Julien Grall <julien@xen.org>; Prem= Harikrishnan <prem.harikrishnan@evoleotech.com>; Stefano Stabellini<= br> > > <sstabellini@kernel.org>;
> > > > > > xen-users@lists.xenproject.org <xen-users@= lists.xenproject.org>; brian.woods@xilinx.com <brian.woods@xilinx.com= >; fnuv@xilinx.com
> > > > > > <fnuv@xilinx.com>; edgari@xilinx.com &l= t;edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com> > > > > > > Subject: Re: Help: Information required for A= XI DMA passthrough for PL masters in ZCU102 dev kit  
> > > > > > Prem,
> > > > > >
> > > > > > Sorry for the late email, I've been under the= weather and have been away
> > > > > > from my computer.  In the Zynq SOCs this= is how the SMMU IDs in PL are
> > > > > > calculated:
> > > > > >
> > > > > > 14-10: TBU bits
> > > > > > 9-6: Master ID bits
> > > > > > 5-0: AXI ID bits
> > > > > >
> > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultras= cale-trm.pdf
> > > > > > To look up the TBU value, see UG1085 and look= for the "System Masters"
> > > > > > table which is table 16-4 on page 409.
> > > > > >
> > > > > > For the master ID, see UG1085 and look for th= e "Master IDs List" table
> > > > > > which is table 16-13 on page 429.
> > > > > >
> > > > > > The AXI ID bits is a bit trickery since it's = going to be out in PL.
> > > > > > See: https://www.xilinx.com/support/answers/69447.html=
> > > > > > With SmartConnect all the AXI IDs are 0, they= aren't passed on.  There
> > > > > > are work arounds.  Here's a couple of ex= amples (with example numbers):
> > > > > >
> > > > > > AXI master -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >        &nb= sp;            =        -> PS slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >        &nb= sp;            =             -> PS= slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >        &nb= sp;            =             &nb= sp;            =            -> PS slave= port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > The "sideband -> SmartConenct -> s= ideband" can also be functionally
> > > > > > replaced with "AXI Interconnect" to= my knowledge.  So the AXI ID bits are
> > > > > > fairly simple but with some caveats.
> > > > > >
> > > > > > You can also read in the SMMU faults from Xen= and use:
> > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_s= pecification.pdf
> > > > > > to decode them. That should tell you the SMMU= IDs as well.
> > > > > >
> > > > > > Let me know if this isn't clear or you have a= ny other questions.
> > > > > >
> > > > > > Brian
> > > > > >
> > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Ste= fano Stabellini wrote:
> > > > > > > On Mon, 10 May 2021, Julien Grall wrote:=
> > > > > > > > On 26/04/2021 15:41, Prem Harikrish= nan wrote:
> > > > > > > > > Hello everyone,
> > > > > > > >
> > > > > > > > Hi Prem,
> > > > > > > >
> > > > > > > > > I am using the latest version = of the xilinx mpsoc zcu102 development board
> > > > > > > > > and i am trying to create a ba= rematal application that uses the AXI DMA on
> > > > > > > > > the programmable logic, using = the scatter gather example from the xilinx
> > > > > > > > > repository. This works perfect= ly well for the baremetal application. The
> > > > > > > > > diagram below represents the i= nformation flow. The AXI DMA and the AXI data
> > > > > > > > > FIFO are in the Programable lo= gic (FPGA). This AXI DMA is out of the box IP
> > > > > > > > > from Vivado and uses a single = channel (Does not use AxUSER) which means the
> > > > > > > > > AXI ID cannot manually be set.=
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Now i want to make this as a b= aremetal hypervisor guest, in future this will
> > > > > > > > > be replaced by a custom IP wit= h cache colouring enabled. I want to pass
> > > > > > > > > through the AXI DMA in the PL.= (Not to be used by Dom0)
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I followed this tutorial Barem= etal + DomU
> > > > > > > > > <htt= ps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842536/XEN+EL1+Baremet= al+DomU>
> > > > > > > > > guest changed the base address= to 0x4000000,(1GB allocated to Dom-0) to
> > > > > > > > > create my EL1 binary. I used P= etalinux 2020.2 to generate my linux, xen
> > > > > > > > > image and use tftp to boot. > > > > > > > > >
> > > > > > > > >  From what i understand f= rom the xilinx tutorials Xen+and+PL+Masters
> > > > > > > > > <https:/= /xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters<= /a>>
> > > > > > > > > section 3 and MPSOC SMMU
> > > > > > > > > <https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+UltraS= cale+MPSOC+SMMU>
> > > > > > > > > section 4, stream ids are requ= ired by the SMMU to get the correct address
> > > > > > > > > translation.
> > > > > > > > >
> > > > > > > > > I am still unable to figure ou= t how to get the iommu property for my AXI DMA
> > > > > > > > > and how to set the dtdev confi= g for my hypervisor guest.
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I can also see some new update= s with the XEN 2020.1 and 2020.2 releases
> > > > > > > > > which i can be useful to my ap= plication
> > > > > > > > >
> > > > > > > > >   *   1:1 = memory mappings for Xen virtual machines, enabling device
> > > > > > > > >     assign= ments without SMMU
> > > > > > > > >   *
> > > > > > > > >      =  Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > >     Xen vi= rtual machines
> > > > > > > > >   *   Supp= ort for PL Device Passthrough to DomU in Xen
> > > > > > > >
> > > > > > > > You are usiong a version of Xen tha= t has been customised by Xilinx. So I would
> > > > > > > > recommend to contact them directly.=
> > > > > > > >
> > > > > > > > I have CCed Stefano who might be ab= le to help you.
> > > > > > >
> > > > > > > Hi Julien,
> > > > > > >
> > > > > > > Many thanks for CC'ing me, I missed the = email.
> > > > > > >
> > > > > > >
> > > > > > > Hi Prem,
> > > > > > >
> > > > > > > Let me CC a few people that might be abl= e to help.
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
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--_009_VI1PR05MB4430B62D7D79E47B784FA34C893F9VI1PR05MB4430eurp_-- From xen-users-bounces@lists.xenproject.org Tue Jun 01 13:22:02 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 01 Jun 2021 13:22:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.134860.250812 (Exim 4.92) (envelope-from ) id 1lo4Kp-0005Tb-J1; Tue, 01 Jun 2021 13:21:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 134860.250812; Tue, 01 Jun 2021 13:21:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo4Kp-0005TT-FG; Tue, 01 Jun 2021 13:21:31 +0000 Received: by outflank-mailman (input) for mailman id 134860; Tue, 01 Jun 2021 13:21:30 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo4Ko-0005TN-6Z for xen-users@lists.xenproject.org; Tue, 01 Jun 2021 13:21:30 +0000 Received: from mout.gmx.net (unknown [212.227.17.21]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 5c9a5d64-64c4-4c80-9950-d8f943820ab2; Tue, 01 Jun 2021 13:21:28 +0000 (UTC) Received: from mail.home.chao5.net ([91.64.145.10]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1MPXhK-1m0ltN01oo-00McMd for ; Tue, 01 Jun 2021 15:21:27 +0200 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 5c9a5d64-64c4-4c80-9950-d8f943820ab2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622553687; bh=nZeFATPaNk4xhWKGJTNVl71QvMdgbkd1CMOLcSKnKP0=; h=X-UI-Sender-Class:Date:From:To:Subject; b=IpvetrbwCZ+OGPn3cAzB0sx5CEouSW74QoVmXxI0OFeirZi+DZ6dK7kMFoiGRP0NK uEHc+xGYztpoyy7rjf9+fwEckBGslQExI7UaahbeFKzaJ1kQixKD1HJX+mngG5xdFH MydttH/gq42hqatGALzetYgir/nidOQ7qi38UJRs= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c MIME-Version: 1.0 Date: Tue, 01 Jun 2021 15:21:09 +0200 From: Chris To: xen-users@lists.xenproject.org Subject: optimized conf for Win!= DomU Message-ID: <6495b90a87e8fe7af760c9075f7b4546@gmx.de> X-Sender: mangel@gmx.de Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: quoted-printable X-Synology-MCP-Status: no X-Synology-Spam-Flag: no X-Synology-Spam-Status: score=-0.1, required 5, __TO_NO_BRKTS_FREEMAIL 0, FROM_HAS_DN 0, FREEMAIL_FROM 0.001, TO_MATCH_ENVRCPT_ALL 0, MIME_GOOD -0.1, TO_DN_NONE 0, RCPT_COUNT_ONE 0, SUBJECT_HAS_EXCLAIM 0, RCVD_COUNT_ZERO 0, FROM_EQ_ENVFROM 0, MIME_TRACE 0, FREEMAIL_ENVFROM 0, __NOT_SPOOFED 0, MID_RHS_MATCH_FROM 0, __KHOP_NO_FULL_NAME 0, NO_RECEIVED -0.001 X-Synology-Virus-Status: no X-Provags-ID: V03:K1:rwsSQ59tgOHB6VhTtbwmBlVH9SODRwZVsqsGyem4XjdfpCTVrnN LGD8rGuQjApanA8uGHXwFd4wjeOaqeRn9DQLI24USqWOnmvk7f7LQ4PtiwG0BIz9M4de1Ym gNP+2Cw5avzxFeEP5/WGKMAWIty9E9duHdv8E59TTcPYTbNW66K97lM3B6DDNIEP9e9o3ql HzgtGCfeXONRzSbvaIuLg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:6bAUZ8rdY4g=:fvpcVnAyASXzJrlhcQ9Ae+ IOyh9h+RsrKL0V0DVIZtxnje0QacyDPHpHtV6omslOGjIzRp3AX/KjPR/p+2LZUqPRQAYcbPQ 93ZC4RruNJnkmMlDfigBTZJIMoSxkpfE7K7Nxeao0eVhl8o09v5lUJgozfnzIbt+juJhKq6Mm DjCerYLceXu7nOAdHsCOX1vFPo/KNnzqPNY49kQ2PvPfcZyZoAo9XIPCfxDovngoD9k05Pcku jgzSnamiSCVtpsZYK62Jf9Zf2BgKacjbn7VgEV+KL5BXCtOttQeF2XZryaXh6ei4tv1GA0Fc1 rNmtg1oGBXFqplLK0x+xMiD8Sr8DYPdaTFe303BU2v0WmDZGYWGyqgxHtL2aV+lqjrcXPiLdd vvcb8NVYjtKUnXBAv4g/EXC+h3yeCYo3Un4FcBU8wpNdFKYiS66YFV8Mt0yLEWmmH2ChEH+lU QarsRRru4sEQ0ZoZmzNUo/Qs6PZ7mM9+1vsWOOtqCKU15VEko+LFSQ7D0i/2B4VDCiE+WgwfK 7/+BU3DQaGqfVwnYhdmmD/YEsHbCcO/G/6cRPTPe+r7pRcz75LDa1VqLUhmn4sWB9uUFcSe/n CTmkME4lXpAEi4nuyRP8wH5+x4UzOAHULJPYM3jHiBfzdd96aBJVHH2uFSQCT6DyZCt+HLUSY f9eOLn8dLHuRyhwUiKSaX0AG+ray5sjhXtPKRB+p4ERQ7uOF1qhJanMjRWUI7/E2iUobrx0fQ 7ild42bQPYXetkpOG9oQofKUFpEVJ7tGDAW87/GOVz6R2FXLs2N5HZ3lOC5IvK/rUI/fNLau4 4dYp0HKb3AWMtL+dglKPcM0G78KIcN0XNunBhtxFe8FWHamUBbFa5KmS5+sQiTcttvPWxpjtA eJ3DZ2dVo07Xeck/InTm5tFCDIuDILXc96DZae4dkA4tEgujZHXnGdqMiAMGpr46VTjJiqKOz +4kiLo3LSeV39WK9WhmeKE5kquPg/rqxeXNq30ZASsZ69q09/D0zR7CtfPRXROAPqJHe4uP7N fsKFJnkePLSLa09BuV5LJEjWdbo+QlyqkHPv/quKQ8LBjhNE23Y/cefk8tqZa7Rd3Cn1fwaVF fDG5ZYmI2QpvbWw/+x7MTeV82LDqsQVNAE6 Hi, I use xen with win10 and a passed-through rtx2070 for gaming. At the moment use this config: name =3D "marax" uuid =3D "e0de3cb7-3937-417d-8d63-b0993b377b6a" maxmem =3D 32768 memory =3D 32768 vcpus =3D 16 rtc_timeoffset =3D 0 localtime =3D 1 on_poweroff =3D "destroy" on_reboot =3D "restart" on_crash =3D "restart" boot =3D 'd' vif =3D [ "mac=3D00:16:3e:05:01:10,bridge=3Dxenbr5,script=3Dvif-bridge,model=3De1000= " ] parallel =3D "none" serial =3D "none" type =3D "hvm" loader =3D "/usr/lib64/xen/boot/hvmloader" bios =3D "ovmf" device_model_version =3D "qemu-xen" bios_path_override =3D "/usr/lib64/xen/boot/OVMF.fd" disk =3D [ "phy:/dev/mapper/marax_c,hda,rw", "phy:/dev/vg_lilith/lv_marax_d,hdb,rw" ] max_grant_frames =3D "128" pci =3D [ "01:00.0", "01:00.1", "01:00.2", "01:00.3", "00:1f.3" ] pci_permissive =3D 1 keymap =3D "de" vnclisten=3D"0.0.0.0:2" pci_power_mgmt=3D1 xen_platform_pci=3D1 pci_msitranslate=3D1 viridian=3D1 hpet=3D1 acpi=3D1 apic=3D1 pae=3D1 videoram=3D16 stdvga=3D1 it works nice but does someone see something in the config what I can make better? For gaming there is never enough optimizing and power :D Thanks in advance! =2D- =2D----- Greetz From xen-users-bounces@lists.xenproject.org Tue Jun 01 16:07:57 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 01 Jun 2021 16:07:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.134952.250944 (Exim 4.92) (envelope-from ) id 1lo6v9-0002hW-E4; Tue, 01 Jun 2021 16:07:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 134952.250944; Tue, 01 Jun 2021 16:07:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo6v9-0002hP-9o; Tue, 01 Jun 2021 16:07:11 +0000 Received: by outflank-mailman (input) for mailman id 134952; Tue, 01 Jun 2021 16:07:09 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo6v7-0002hH-9C for xen-users@lists.xenproject.org; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=evoleotech.com; dmarc=pass action=none header.from=evoleotech.com; dkim=pass header.d=evoleotech.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=evoleotechnologies.onmicrosoft.com; s=selector2-evoleotechnologies-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Z8U6q2PxfvHSDAQv3MzXiKFnwM0QjE6uP5XeE8XSitM=; b=NyHF1FNGS6qr9Lt58bSRJ6Jr51L/zDmqn0Maz6kMsx6+FvoHIS/NSRgZDp8Oer+QJPHjsHcGuK4NQcS0xsq6yVgHExDb9mcrFLleSYo29b6KCmtLkvLhiEzqnYzX+ynw9oD3iGNsfEUqn0MkrfV95Fe2TcHbwfae/Mz4dOiFbH8= From: Prem Harikrishnan To: Mubin Usman Sayyed , Stefano Stabellini CC: "xen-users@lists.xenproject.org" , Jovita Castelino Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit Thread-Topic: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit Thread-Index: AQHXOqMAPewhx/0ZVE2fbco7T/GOXKrdFmqAgACD+ICABAVYgIABrlVrgABJdgCAAATIt4AADpaAgARL642AAI9eAIABDuwsgAAXkYCADm9DhoAAJeiAgADiys+AAEjyAIAE2MzdgABzowCAAM/6Lg== Date: Tue, 1 Jun 2021 16:07:01 +0000 Message-ID: References: , , , , , , , In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: xilinx.com; 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boundary="_000_VI1PR05MB44308D16502AA518E05B210C893E9VI1PR05MB4430eurp_" MIME-Version: 1.0 X-OriginatorOrg: evoleotech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR05MB4430.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e5a89b7c-7d86-4a34-9d0f-08d925174a86 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2021 16:07:01.2438 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 34ebafdc-9323-4bfe-8f24-6bb9f135b0a9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dcOuRp+6dZ52kEJZgosOzeLy770tn5JprLH0ElTalvl1cEyPBcLH7bBHr08zH1a6DO+mlK9QvNbz9CwB2mp/RyKG+O37waR2zGqmNG+XUJyFoElwN8Pc4PKNVRiA4le9 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR05MB7566 --_000_VI1PR05MB44308D16502AA518E05B210C893E9VI1PR05MB4430eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Stefano and Mubin, Thank you very much for helping me setup up FreeRTOS and baremetal guests, = everything works as expected and I also get expected performance in both ba= remetal and hypervisor guests. Thank you again for your prompt support duri= ng the past few weeks. Best Regrards, Prem ________________________________ From: Mubin Usman Sayyed Sent: Tuesday, June 1, 2021 05:38 To: Prem Harikrishnan ; Stefano Stabellin= i Cc: xen-users@lists.xenproject.org ; Jovita= Castelino Subject: RE: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit In case of FreeRTOS, you need to use APIs from FreeRTOS port for interrupt= handling (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp= /freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). Ple= ase make sure that you are taking care of that in DMA interrupt example . Thanks, Mubin From: Prem Harikrishnan Sent: Tuesday, June 1, 2021 2:48 AM To: Stefano Stabellini Cc: xen-users@lists.xenproject.org; Jovita Castelino ; = Mubin Usman Sayyed Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit Hi Stefano and Mubin, Thank you very much for your replies. @Stefano Stabellini Sorry to bother y= ou again, and thank you for pointing this out, the TTC0 is by default enabl= ed for FreeRTOS to generate ticks, although this says only for R5 core, i w= ould have never figured this out. As soon as I added the irqs and iomem and= gave a xen passthrough in the xen.dtsi as you have suggested, FreeRTOS gue= st started working for other peripherals except for my DMA (FreeRTOS guest = does not work with interrupt and DMA). I can see my DMA is enabled because i have LEDs configured to blink for eve= ry interrupt I get from the PL. I don't see my interrupts being processed, = but when I destroy the guest, I get this output periodically when an interr= upt occurs. (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 >From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/= A/pages/18842066/Xen+and+PL+Masters Xen and PL Masters - Xilinx Wiki - Confluence 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of = PL masters must be added to the Linux Dom0 device tree. Automated device tr= ee generation does not generate the stream IDs for the PL masters so that t= he user must add them into the device tree manually. xilinx-wiki.atlassian.net The fault indicates an unidentified stream ID has been received by the SMMU= as shown in the GFSR register. The GFSYNR1 register contains the stream ID= that was unidentified. A stream ID of 0xE80 was unidentified in the above = fault. But I think i have already added that in my smmu and iommu in xen.dtsi beca= use my baremetal application works well as expected. I have attached my xen= .dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). What could I be missing here? Do I have to enable the ttc0 in the device tr= ee? Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: = 99990 KHz mean when XEN boots up? Thanks, I look forward for your reply. Best Regards, Prem ________________________________ From: Stefano Stabellini > Sent: Friday, May 28, 2021 20:43 To: Prem Harikrishnan > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com >; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit >From the gpa address, it looks like FreeRTOS is trying to access the TTC timer? If you look at device tree, the corresponding node is timer@ff110000. If FreeRTOS is configured to access the TTC timer, then you need to assign it to it. Did you assign the TTC timer to the FreeRTOS domU by any chance? You can do that by adding: irqs =3D [ 68, 69, 70 ] iomem =3D [ "0xff110,1" ] On Fri, 28 May 2021, Prem Harikrishnan wrote: > Hi Stefano, > Thanks for your reply. I am pretty sure I followed the steps you mentione= d below to run the FreeRTOS hello world example. I already added > printfs and i can see XEN cannot start the scheduler and i get the follow= ing out put on XEN. > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 memfl= ags=3D0xc0 (0 of 64) > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0 > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0xff= 11000c gpa=3D0x000000ff11000c > > > I also see that according to this article > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as= -a-Xen-Virtual-Machine/ba-p/947030 > [52662iFAD1733707609204?v=3Dv2] > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks Wh= at is FreeRTOS? The FreeRTOS kernel is a market leading real-time > operating system for embedded systems. As embedded applications grow in c= omplexity, there is a growing need for a lightweight kernel > capable of task scheduling... > forums.xilinx.com > FreeRTOS does not run out of the box for XEN, although the article is 2 y= ears old, I am not sure if there are any updates on this after > that. Can you please confirm? > > Thanks and Best Regards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 02:51 > To: Prem Harikrishnan > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com > >; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > +Mubin > > > Hi Prem, > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps: > > - source settings64.sh from Vitis builds > - xsct > - set WORKSPACE . > - setws -switch $WORKSPACE > - app create -name freertos-hello-world -template {FreeRTOS Hello World} = -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > - bsp config stdin psu_uart_1 > - bsp config stdout psu_uart_1 > - bsp config hypervisor_guest true > - Go to application source path and modify the linker script start addres= s to 0x40000000, > - app build -name freertos-hello-world > - Run command to generate BIN file from executable "aarch64-linux-gnu-obj= copy -O binary --gap-fill 0 BOOT.BIN" > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > might be able to provide additional info. > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Sorry to bother you again. > > I am currently trying to run my custom IP which sends periodic dma inte= rrupts to the PS with cache coloring enabled. I have now compiled > my > > guest running with FreeRTOS and it generates a trap. > > Petalinux and VITIS IDE Version is 2020.2. > > > > Please find the log attached. After the trap occurs, for every interrup= t XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault: > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config fro= m apu_freertos.cfg > > (XEN) Dom1 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D1 mem= flags=3D0xc0 (0 of 64) > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache=3D0 > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > (XEN) sched_null.c:344: 1 <-- d1v0 > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gva=3D0x= ff11000c gpa=3D0x000000ff11000c > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > The same application works as expected without FreeRTOS, i.e as a barem= etal guest. I look forward for your comment on this. > > > > Although i see performance degradation, normally i can measure delta ti= me for each interrupt configured to 1ms (without XEN), with XEN > for > > the same measurement shows 16 ms for each interval (but the performance= is not a priority for now). > > Thanks and Best Regards, > > Prem > > > >________________________________________________________________________= __________________________________________________________________ > _ > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 20:09 > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL = masters in ZCU102 dev kit > > Great to hear! Thank you for reporting back. > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > Dear Stefano, > > > Thank you very much for your guidance and support. I finally fixed th= e issue. I made an error in base memory address like you pointed > > out. > > > I actually modified the base address correctly to 0x40000000 but the = default C code had an additional offset of 0x1100000 , and the > DomU > > > memory allocated was only 8MB. I either had to change the offset or a= llocate more memory to the DomU guest which i missed until you > > pointed > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and th= e SMID required is 0xE80. > > > > > > Thanks again i was able get my custom IP also working as an AXI maste= r from PL. > > > > > > Best Regards, > > > Prem > > > > >>_______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 02:35 > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; St= efano > > > Stabellini >; x= en-users@lists.xenproject.org >; fnuv@xil= inx.com > >; > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for P= L masters in ZCU102 dev kit > > > Your configuration looks correct as far as I can tell. > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > block. You don't need device_tree because your baremetal application = is > > > not going to read it, but it is not going to cause any issues either. > > > > > > When you say "the execution does not complete the loop at line 244", = it > > > means that you see the execution entering the loop and then never > > > leaving? Like an infinite loop? > > > > > > If so, then I imagine the issue could be that the application is > > > crashing when trying to access TxBufferPtr, which is pointing to > > > TX_BUFFER_BASE, which is: > > > > > > > > > #ifndef DDR_BASE_ADDR > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > DEFAULT SET TO 0x01000000 > > > #define MEM_BASE_ADDR 0x01000000 > > > #else > > > #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) > > > #endif > > > > > > #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > Hi Stefano, > > > > Thanks again for your reply and your suggestion. I did try to repl= ace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRange(works > > only > > > > in EL3), I added printfs to debug, i can see that the execution doe= s not complete the loop at line 244 > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPL= ib/drivers/axidma/examples/xaxidma_example_simple_poll.c and > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bo= otlog.txt. > > > > I am still unable to find out why?? > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is corre= ct? and do i need dtdev and device_tree in my guest config file > when > > > it > > > > is already added to xen.dtsi? > > > > > > > > Best Regards, > > > > Prem > > > > > > > > > >>>______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; = Stefano > > > > Stabellini >;= xen-users@lists.xenproject.org >; fnuv@x= ilinx.com > > >; > > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for= PL masters in ZCU102 dev kit > > > > Hi Prem, > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > deprecated set/way instructions that are known to cause problems in > > > > virtualized environments. > > > > > > > > More recent implementations use the "dc civac" intruction that shou= ldn't > > > > have any issues. > > > > > > > > Can you double-check that you are calling the 64-bit version implem= ented > > > > by CIVAC? > > > > > >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3= 577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L4 > 1 > > 4 > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks for your reply. Yes the axidma application is a baremetal = application from the xilinx vitis ide example. > > > > > Also yes, I have already run hello world as DomU guest, with UART= 1. > > > > > > > > > > I am using the simple mode using polling and not interrupts(they = are disabled in the c code), which is Why I didn't include in the > > > guest > > > > > config file. This works well when I compile it normally (as EL3).= When compiled as hypervisor guest, the execution stops before the > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcess= orIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c > > > > > > > > > > I found the SATA example similar to my use case, also using DMA a= nd SMMU. I just used it as a reference to create my pl.dtb to pass > > > > through > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > Thanks and Best Regards, > > > > > Prem > > > > > > > > > > Get Outlook for Android > > > > > > >>>>_____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > To: Prem Harikrishnan > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabel= lini; xen-users@lists.xenproject.org= ; fnuv@xilinx.com; > > > > edgari@xilinx.com; > > > > > bwoods288@gmail.com; Renato Costa Amo= rim; JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.= bin" is > > > > > a baremetal application? Can you run it successfully, just printi= ng > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on = the > > > > > Vivado configuration and SMID calculation. But I noticed that you= only > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven= 't > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dts= i, it > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I do= n't > > > > > follow: I cannot see any SATA controller assignment in your > > > > > configuration. > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > Thank you very much for your replies. > > > > > > Hi Brian and Stefano, Can you please help me with the following= questions? > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when= i added my AXI DMA now running on simple polling mode(previously > i > > > > tried > > > > > it > > > > > > with Scatter Gather mode), Run Automation automatically generat= ed, 1 AXI Interconnect and 1 smart connect. Since there is only 1 > > > master > > > > > and > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for th= e stream IDs. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/= Xen+and+PL+Masters According to this link section 6.5 I have > > manually > > > > tied > > > > > > of AxPROT bits to value of 0x2 to create non secure transaction= s. Can you please confirm that my Vivado configuration is correct? > I > > > can > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated f= rom petalinux and system.dtsi also generated after manually adding > > > > > xen.dtsi. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561= /Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > this > > > > SATA > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.= cfg. I could really use your help to identify what is missing in > my > > > xen > > > > > > configuration. > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > >>>>>____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Brian Woods > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > To: Stefano Stabellini > > > > > > > Cc: Julien Grall >; Prem = Harikrishnan >; Stefano Stabellini > > >; > > > > > > xen-users@lists.xenproject.org >; brian.woods@xilinx.com >; fnuv@xilinx.com > > > > > > >; edgari@xilinx.com >; bwoo= ds288@gmail.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough= for PL masters in ZCU102 dev kit > > > > > > Prem, > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have = been away > > > > > > from my computer. In the Zynq SOCs this is how the SMMU IDs in= PL are > > > > > > calculated: > > > > > > > > > > > > 14-10: TBU bits > > > > > > 9-6: Master ID bits > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085= -zynq-ultrascale-trm.pdf > > > > > > To look up the TBU value, see UG1085 and look for the "System M= asters" > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List= " table > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in= PL. > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.= There > > > > > > are work arounds. Here's a couple of examples (with example nu= mbers): > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > -> PS s= lave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be function= ally > > > > > > replaced with "AXI Interconnect" to my knowledge. So the AXI I= D bits are > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_ar= chitecture_specification.pdf > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions= . > > > > > > > > > > > > Brian > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wr= ote: > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 = development board > > > > > > > > > and i am trying to create a barematal application that us= es the AXI DMA on > > > > > > > > > the programmable logic, using the scatter gather example = from the xilinx > > > > > > > > > repository. This works perfectly well for the baremetal a= pplication. The > > > > > > > > > diagram below represents the information flow. The AXI DM= A and the AXI data > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is= out of the box IP > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSE= R) which means the > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, = in future this will > > > > > > > > > be replaced by a custom IP with cache colouring enabled. = I want to pass > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocate= d to Dom-0) to > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate= my linux, xen > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > From what i understand from the xilinx tutorials Xen+and= +PL+Masters > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the= correct address > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu prop= erty for my AXI DMA > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2= 020.2 releases > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > * 1:1 memory mappings for Xen virtual machines, enabl= ing device > > > > > > > > > assignments without SMMU > > > > > > > > > * > > > > > > > > > Static assignment of PL blocks, including bus-maste= ring blocks, to > > > > > > > > > Xen virtual machines > > > > > > > > > * Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by= Xilinx. So I would > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --_000_VI1PR05MB44308D16502AA518E05B210C893E9VI1PR05MB4430eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Stefano and Mubin,

Thank you very much for helping me setup up FreeRTOS and baremetal guests, = everything works as expected and I also get expected performance in both ba= remetal and hypervisor guests. Thank you again for your prompt support duri= ng the past few weeks.

Best Regrards,
Prem
From: Mubin Usman Sayyed &l= t;MUBINUSM@xilinx.com>
Sent: Tuesday, June 1, 2021 05:38
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; Stef= ano Stabellini <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org <xen-users@lists.xenproject.or= g>; Jovita Castelino <JOVITAC@xilinx.com>
Subject: RE: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit
 

In case of FreeRTOS,  you need to use APIs fr= om FreeRTOS port for interrupt handling  (https://github.com/Xilinx/embeddedsw/blob/mast= er/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). Please make sure that you are taking care of that in DMA in= terrupt example .

 

Thanks,

Mubin

 

From: Prem Harikrishnan <prem.harikrishn= an@evoleotech.com>
Sent: Tuesday, June 1, 2021 2:48 AM
To: Stefano Stabellini <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org; Jovita Castelino <JOVITAC@xil= inx.com>; Mubin Usman Sayyed <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

&nbs= p;

Hi S= tefano and Mubin,

Than= k you very much for your replies.

@Stef= ano Stabellini Sorry to bother you again, and thank you for pointing this out, the TTC0 is by default enabled for Fr= eeRTOS to generate ticks, although this says only for R5 core, i would have= never figured this out. As soon as I added the irqs and iomem and gave a x= en passthrough in the xen.dtsi as you have suggested, FreeRTOS guest started working for other peripherals e= xcept for my DMA (FreeRTOS guest does not work with interrupt and DMA).

&nbs= p;

I ca= n see my DMA is enabled because i have LEDs configured to blink for every i= nterrupt I get from the PL. I don't see my interrupts being processed, but = when I destroy the guest, I get this output periodically when an interrupt occurs.

&nbs= p;

(XEN= ) smmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(XEN= ) smmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(XEN= ) smmu: /smmu@fd800000: Unexpected global fault, this could be serious
(XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

&nbs= p;

3.4 Stream IDs in the Device Tre= e. For Xen based systems the stream IDs of PL masters must be added to the = Linux Dom0 device tree. Automated device tree generation does not generate the stream IDs for the PL masters so that the= user must add them into the device tree manually.

xilinx-wiki.atlassian.net=

The fault indicates an= unidentified stream ID has been received by the SMMU as shown in the GFSR = register. The GFSYNR1 register contains the stream ID that was unidentified= . A stream ID of 0xE80 was unidentified in the above fault.

&nbs= p;

But = I think i have already added that in my smmu and iommu in xen.dtsi because = my baremetal application works well as expected. I have attached my xen.dts= i, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working).

What= could I be missing here? Do I have to enable the ttc0 in the device tree?

Also= what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: 9999= 0 KHz mean when XEN boots up?

Than= ks, I look forward for your reply.

&nbs= p;

Best= Regards,

Prem=

&nbs= p;

&nbs= p;

From: Stefano Stabellini <stefano.stabellini@xilinx.com>
Sent: Friday, May 28, 2021 20:43
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

From the gpa address, it looks like FreeRTOS is tr= ying to access the TTC
timer? If you look at device tree, the corresponding node is
timer@ff110000.

If FreeRTOS is configured to access the TTC timer, then you need to
assign it to it. Did you assign the TTC timer to the FreeRTOS domU by
any chance?

You can do that by adding:

irqs =3D [ 68, 69, 70 ]
iomem =3D [ "0xff110,1" ]


On Fri, 28 May 2021, Prem Harikrishnan wrote:
> Hi Stefano,
> Thanks for your reply. I am pretty sure I followed the steps you menti= oned below to run the FreeRTOS hello world example. I already added
> printfs and i can see XEN cannot start the scheduler and i get the fol= lowing out put on XEN.
>
> Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ]
> (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 me= mflags=3D0xc0 (0 of 64)
> (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0
> (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0= xff11000c gpa=3D0x000000ff11000c
>
>
> I also see that according to this article
> https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a= -Xen-Virtual-Machine/ba-p/947030
> [52662iFAD1733707609204?v=3Dv2]
> Partner: FreeRTOS as a Xen Virtual Machine - Community Forums
> Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks= What is FreeRTOS? The FreeRTOS kernel is a market leading real-time
> operating system for embedded systems. As embedded applications grow i= n complexity, there is a growing need for a lightweight kernel
> capable of task scheduling...
> forums.xilinx.com
> FreeRTOS does not run out of the box for XEN, although the article is = 2 years old, I am not sure if there are any updates on this after
> that. Can you please confirm?
>
> Thanks and Best Regards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> Sent: Friday, May 28, 2021 02:51
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com
> <JOVITAC@xilinx.com>; = MUBINUSM@xilinx.com <MUBINUSM= @xilinx.com>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
> +Mubin
>
>
> Hi Prem,
>
> Did you make sure to build FreeRTOS as "hypervisor guest"? I= think
> FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps:
>
> - source settings64.sh from Vitis builds
> - xsct
> - set WORKSPACE .
> - setws -switch $WORKSPACE
> - app create -name freertos-hello-world -template {FreeRTOS Hello Worl= d} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx
> - bsp config stdin psu_uart_1
> - bsp config stdout psu_uart_1
> - bsp config hypervisor_guest true
> - Go to application source path and modify the linker script start add= ress to 0x40000000,
> - app build -name freertos-hello-world
> - Run command to generate BIN file from executable "aarch64-linux= -gnu-objcopy -O binary --gap-fill 0  <elf path> BOOT.BIN" >
> The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed,<= br> > might be able to provide additional info.
>
>
>
> On Thu, 27 May 2021, Prem Harikrishnan wrote:
> > Hi Stefano,
> > Sorry to bother you again.
> > I am currently trying to run my custom IP which sends periodic dm= a interrupts to the PS with cache coloring enabled. I have now compiled
> my
> > guest running with FreeRTOS and it generates a trap.
> > Petalinux and VITIS IDE Version is 2020.2.
> >
> > Please find the log attached. After the trap occurs, for every in= terrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault:
> > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing conf= ig from apu_freertos.cfg
> > (XEN) Dom1 colors: [ 8 ]
> > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id= =3D1 memflags=3D0xc0 (0 of 64)
> > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache= =3D0
> > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache= =3D0
> > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000
> > (XEN) sched_null.c:344: 1 <-- d1v0
> > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gv= a=3D0xff11000c gpa=3D0x000000ff11000c
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > The same application works as expected without FreeRTOS, i.e as a= baremetal guest. I look forward for your comment on this.
> >
> > Although i see performance degradation, normally i can measure de= lta time for each interrupt configured to 1ms (without XEN), with XEN
> for
> > the same measurement shows 16 ms for each interval (but the perfo= rmance is not a priority for now).
> > Thanks and Best Regards,
> > Prem
> >
> >__________________________________________________________________= ________________________________________________________________________ > _
> > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > Sent: Tuesday, May 18, 2021 20:09
> > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>;
> JOVITAC@xilinx.com
> > <JOVITAC@xilinx.com&= gt;
> > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit  
> > Great to hear! Thank you for reporting back.
> >
> >
> > On Tue, 18 May 2021, Prem Harikrishnan wrote:
> > > Dear Stefano,
> > > Thank you very much for your guidance and support. I finally= fixed the issue. I made an error in base memory address like you pointed > > out.
> > > I actually modified the base address correctly to 0x40000000= but the default C code had an additional offset of 0x1100000 , and the
> DomU
> > > memory allocated was only 8MB. I either had to change the of= fset or allocate more memory to the DomU guest which i missed until you
> > pointed
> > > out. Additionally i had to set to AxPROT bits to 0x2 in Viva= do and the SMID required is 0xE80.
> > >
> > > Thanks again i was able get my custom IP also working as an = AXI master from PL.
> > >
> > > Best Regards,
> > > Prem
> > >
> >>______________________________________________________________= ___________________________________________________________________________=
> _
> > _
> > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > Sent: Tuesday, May 18, 2021 02:35
> > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <brian.woods@xilinx.com>; Julie= n Grall <julien@xen.org>; Stefano
> > > Stabellini <sst= abellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> <fnuv@xilinx.com>;
> > > edgari@xilinx.com &= lt;edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > JOVITAC@xilinx.com= <JOVITAC@xilinx.com>
> > > Subject: Re: Help: Information required for AXI DMA passthro= ugh for PL masters in ZCU102 dev kit  
> > > Your configuration looks correct as far as I can tell.
> > >
> > > You need dtdev because it triggers the SMMU configuration fo= r your PL
> > > block. You don't need device_tree because your baremetal app= lication is
> > > not going to read it, but it is not going to cause any issue= s either.
> > >
> > > When you say "the execution does not complete the loop = at line 244", it
> > > means that you see the execution entering the loop and then = never
> > > leaving? Like an infinite loop?
> > >
> > > If so, then I imagine the issue could be that the applicatio= n is
> > > crashing when trying to access TxBufferPtr, which is pointin= g to
> > > TX_BUFFER_BASE, which is:
> > >
> > >
> > > #ifndef DDR_BASE_ADDR
> > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \=
> > >           =        DEFAULT SET TO 0x01000000
> > > #define MEM_BASE_ADDR      &nb= sp;    0x01000000
> > > #else
> > > #define MEM_BASE_ADDR      &nb= sp;    (DDR_BASE_ADDR + 0x1000000)
> > > #endif
> > >
> > > #define TX_BUFFER_BASE      &n= bsp;   (MEM_BASE_ADDR + 0x00100000)
> > >
> > >
> > >
> > > Can you double check that TX_BUFFER_BASE is pointing to a co= rrect
> > > address? Memory starts at 0x40000000 in a Xen DomU.
> > >
> > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly?
> > >
> > >
> > > On Mon, 17 May 2021, Prem Harikrishnan wrote:
> > > > Hi Stefano,
> > > > Thanks again for your reply and your suggestion.  = I did try to replace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRang= e(works
> > only
> > > > in EL3), I added printfs to debug, i can see that the e= xecution does not complete the loop at line 244
> > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drive= rs/axidma/examples/xaxidma_example_simple_poll.c  and
> > > > Xil_DCacheFlushRange is not reached. Please find attach= ed my xen bootlog.txt.
> > > > I am still unable to find out why??
> > > >
> > > > Can you please atleast verify that my xen.dtsi, and pl.= dtb is correct? and do i need dtdev and device_tree in my guest config file=
> when
> > > it
> > > > is already added to xen.dtsi?
> > > >
> > > > Best Regards,
> > > > Prem
> > > >
> > > >
> >>>__________________________________________________________= ___________________________________________________________________________= ___
> _
> > _
> > > _
> > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > Sent: Saturday, May 15, 2021 00:25
> > > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <= ;brian.woods@xilinx.com>; = Julien Grall <julien@xen.org>; Stefano
> > > > Stabellini <sstabellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> > <fnuv@xilinx.com>; > > > > edgari@xilinx.com<= /a> <edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > > JOVITAC@xilinx.co= m <JOVITAC@xilinx.com><= br> > > > > Subject: Re: Help: Information required for AXI DMA pas= sthrough for PL masters in ZCU102 dev kit  
> > > > Hi Prem,
> > > >
> > > > Some older versions of Xil_DCacheFlushRange were implem= ented using
> > > > deprecated set/way instructions that are known to cause= problems in
> > > > virtualized environments.
> > > >
> > > > More recent implementations use the "dc civac"= ; intruction that shouldn't
> > > > have any issues.
> > > >
> > > > Can you double-check that you are calling the 64-bit ve= rsion implemented
> > > > by CIVAC?
> > > >
> >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb= 18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#= L4
> 1
> > 4
> > >
> > > >
> > > >
> > > >
> > > >
> > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > Hi Stefano, 
> > > > > Thanks for your reply. Yes the axidma application = is a baremetal application from the xilinx vitis ide example. 
> > > > > Also yes, I have already run hello world as DomU g= uest, with UART1.
> > > > >
> > > > > I am using the simple mode using polling and not i= nterrupts(they are disabled in the c code), which is Why I didn't include i= n the
> > > guest
> > > > > config file. This works well when I compile it nor= mally (as EL3). When compiled as hypervisor guest, the execution stops befo= re the
> > > > > function xil_dcacheflushrange(). Please find the c= code attached
> > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxP= rocessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c&nbs= p;
> > > > >
> > > > > I found the SATA example similar to my use case, a= lso using DMA and SMMU. I just used it as a reference to create my pl.dtb t= o pass
> > > > through
> > > > > in the guest config.(from pl.dtsi, which I manuall= y created).
> > > > >
> > > > > Thanks and Best Regards,
> > > > > Prem
> > > > >
> > > > > Get Outlook for Android
> > > > >
> >>>>______________________________________________________= ___________________________________________________________________________= ______
> _
> > _
> > > _
> > > > _
> > > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > Sent: Friday 14 May 2021, 23:16
> > > > > To: Prem Harikrishnan
> > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall;= Stefano Stabellini; xen-users@lists.xenproject.org; fnuv= @xilinx.com;
> > > > edgari@xilinx.com<= /a>;
> > > > > bwoods288@g= mail.com; Renato Costa Amorim; JOVITAC@xilinx.com
> > > > > Subject: Re: Help: Information required for AXI DM= A passthrough for PL masters in ZCU102 dev kit
> > > > >
> > > > > I take that the guest kernel "/bin/xaxidma_ex= ample_simple_poll_1.bin" is
> > > > > a baremetal application? Can you run it successful= ly, just printing
> > > > > "hello world", if you only assign the UA= RT and nothing else?
> > > > >
> > > > > I am asking just to verify that you can run the ba= remetal VM
> > > > > successfully, aside from the PL device assignment.=
> > > > >
> > > > >
> > > > > In regards to the PL device assignment, I'll let B= rian answer on the
> > > > > Vivado configuration and SMID calculation. But I n= oticed that you only
> > > > > assigned IRQ 54 to the DomU which is the one for U= ART1. You haven't
> > > > > assigned any IRQs for axi_dma_0. Looking at pl_fro= m_petalinux.dtsi, it
> > > > > looks like there are two related IRQs: 121 and 122= .
> > > > >
> > > > > Finally, why did you mention SATA passthrough in y= our reply? I don't
> > > > > follow: I cannot see any SATA controller assignmen= t in your
> > > > > configuration.
> > > > >
> > > > >
> > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > > Dear Brian, Stefano and Julien,
> > > > > >
> > > > > > Thank you very much for your replies.
> > > > > > Hi Brian and Stefano, Can you please help me = with the following questions?
> > > > > >
> > > > > > @Brian Woods Please find attached my vivado c= onfiguration, when i added my AXI DMA now running on simple polling mode(pr= eviously
> i
> > > > tried
> > > > > it
> > > > > > with Scatter Gather mode), Run Automation aut= omatically generated, 1 AXI Interconnect and 1 smart connect. Since there i= s only 1
> > > master
> > > > > and
> > > > > > I use the S_AXI _HP0_FPD, I finally get a val= ue of 0xE80 for the stream IDs.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters According to this link section 6.5 I have
> > manually
> > > > tied
> > > > > > of AxPROT bits to value of 0x2 to create non = secure transactions. Can you please confirm that my Vivado configuration is= correct?
> I
> > > can
> > > > > > update you soon with an ILA trace on Vivado.<= br> > > > > > >
> > > > > > @Stefano Stabellini Please find attached my p= l.dtsi generated from petalinux and system.dtsi also generated after manual= ly adding
> > > > > xen.dtsi.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xe= n+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using
> this
> > > > SATA
> > > > > > passthrough, i made my own pl.dtsi for passth= rough used in dma.cfg. I could really use your help to identify what is mis= sing in
> my
> > > xen
> > > > > > configuration.
> > > > > >
> > > > > > Thanks and Best Regards,
> > > > > > Prem
> > > > > >
> >>>>>__________________________________________________= ___________________________________________________________________________= _________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > From: Brian Woods <brian.woods@xilinx.com>
> > > > > > Sent: Thursday, May 13, 2021 17:13
> > > > > > To: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > > Cc: Julien Grall <julien@xen.org>; Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; = Stefano Stabellini
> > <sstabellini@kernel.= org>;
> > > > > > xen-users@lists.xenproject.org <xen-users@lists.xenproject.org>; brian.woods@xilinx.com <brian.woods@xilinx.com>; fnuv@xilinx.com
> > > > > > <fnuv@x= ilinx.com>; edgari@xilinx.com <edgari@xilin= x.com>; bwoods288@gmail.com <bwoods288@gmail.com>
> > > > > > Subject: Re: Help: Information required for A= XI DMA passthrough for PL masters in ZCU102 dev kit  
> > > > > > Prem,
> > > > > >
> > > > > > Sorry for the late email, I've been under the= weather and have been away
> > > > > > from my computer.  In the Zynq SOCs this= is how the SMMU IDs in PL are
> > > > > > calculated:
> > > > > >
> > > > > > 14-10: TBU bits
> > > > > > 9-6: Master ID bits
> > > > > > 5-0: AXI ID bits
> > > > > >
> > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultras= cale-trm.pdf
> > > > > > To look up the TBU value, see UG1085 and look= for the "System Masters"
> > > > > > table which is table 16-4 on page 409.
> > > > > >
> > > > > > For the master ID, see UG1085 and look for th= e "Master IDs List" table
> > > > > > which is table 16-13 on page 429.
> > > > > >
> > > > > > The AXI ID bits is a bit trickery since it's = going to be out in PL.
> > > > > > See: https://www.xilinx.com/support/answers/69447.html=
> > > > > > With SmartConnect all the AXI IDs are 0, they= aren't passed on.  There
> > > > > > are work arounds.  Here's a couple of ex= amples (with example numbers):
> > > > > >
> > > > > > AXI master -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >        &nb= sp;            =        -> PS slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >        &nb= sp;            =             -> PS= slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >        &nb= sp;            =             &nb= sp;            =            -> PS slave= port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > The "sideband -> SmartConenct -> s= ideband" can also be functionally
> > > > > > replaced with "AXI Interconnect" to= my knowledge.  So the AXI ID bits are
> > > > > > fairly simple but with some caveats.
> > > > > >
> > > > > > You can also read in the SMMU faults from Xen= and use:
> > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_s= pecification.pdf
> > > > > > to decode them. That should tell you the SMMU= IDs as well.
> > > > > >
> > > > > > Let me know if this isn't clear or you have a= ny other questions.
> > > > > >
> > > > > > Brian
> > > > > >
> > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Ste= fano Stabellini wrote:
> > > > > > > On Mon, 10 May 2021, Julien Grall wrote:=
> > > > > > > > On 26/04/2021 15:41, Prem Harikrish= nan wrote:
> > > > > > > > > Hello everyone,
> > > > > > > >
> > > > > > > > Hi Prem,
> > > > > > > >
> > > > > > > > > I am using the latest version = of the xilinx mpsoc zcu102 development board
> > > > > > > > > and i am trying to create a ba= rematal application that uses the AXI DMA on
> > > > > > > > > the programmable logic, using = the scatter gather example from the xilinx
> > > > > > > > > repository. This works perfect= ly well for the baremetal application. The
> > > > > > > > > diagram below represents the i= nformation flow. The AXI DMA and the AXI data
> > > > > > > > > FIFO are in the Programable lo= gic (FPGA). This AXI DMA is out of the box IP
> > > > > > > > > from Vivado and uses a single = channel (Does not use AxUSER) which means the
> > > > > > > > > AXI ID cannot manually be set.=
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Now i want to make this as a b= aremetal hypervisor guest, in future this will
> > > > > > > > > be replaced by a custom IP wit= h cache colouring enabled. I want to pass
> > > > > > > > > through the AXI DMA in the PL.= (Not to be used by Dom0)
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I followed this tutorial Barem= etal + DomU
> > > > > > > > > <htt= ps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842536/XEN+EL1+Baremet= al+DomU>
> > > > > > > > > guest changed the base address= to 0x4000000,(1GB allocated to Dom-0) to
> > > > > > > > > create my EL1 binary. I used P= etalinux 2020.2 to generate my linux, xen
> > > > > > > > > image and use tftp to boot. > > > > > > > > >
> > > > > > > > >  From what i understand f= rom the xilinx tutorials Xen+and+PL+Masters
> > > > > > > > > <https:/= /xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters<= /a>>
> > > > > > > > > section 3 and MPSOC SMMU
> > > > > > > > > <https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+UltraS= cale+MPSOC+SMMU>
> > > > > > > > > section 4, stream ids are requ= ired by the SMMU to get the correct address
> > > > > > > > > translation.
> > > > > > > > >
> > > > > > > > > I am still unable to figure ou= t how to get the iommu property for my AXI DMA
> > > > > > > > > and how to set the dtdev confi= g for my hypervisor guest.
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I can also see some new update= s with the XEN 2020.1 and 2020.2 releases
> > > > > > > > > which i can be useful to my ap= plication
> > > > > > > > >
> > > > > > > > >   *   1:1 = memory mappings for Xen virtual machines, enabling device
> > > > > > > > >     assign= ments without SMMU
> > > > > > > > >   *
> > > > > > > > >      =  Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > >     Xen vi= rtual machines
> > > > > > > > >   *   Supp= ort for PL Device Passthrough to DomU in Xen
> > > > > > > >
> > > > > > > > You are usiong a version of Xen tha= t has been customised by Xilinx. So I would
> > > > > > > > recommend to contact them directly.=
> > > > > > > >
> > > > > > > > I have CCed Stefano who might be ab= le to help you.
> > > > > > >
> > > > > > > Hi Julien,
> > > > > > >
> > > > > > > Many thanks for CC'ing me, I missed the = email.
> > > > > > >
> > > > > > >
> > > > > > > Hi Prem,
> > > > > > >
> > > > > > > Let me CC a few people that might be abl= e to help.
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>

--_000_VI1PR05MB44308D16502AA518E05B210C893E9VI1PR05MB4430eurp_-- From xen-users-bounces@lists.xenproject.org Tue Jun 01 18:31:09 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 01 Jun 2021 18:31:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.135301.251406 (Exim 4.92) (envelope-from ) id 1lo99g-00016c-Qe; Tue, 01 Jun 2021 18:30:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 135301.251406; Tue, 01 Jun 2021 18:30:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo99g-00016U-Ly; Tue, 01 Jun 2021 18:30:20 +0000 Received: by outflank-mailman (input) for mailman id 135301; Tue, 01 Jun 2021 18:30:18 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo99e-00016O-Or for xen-users@lists.xenproject.org; Tue, 01 Jun 2021 18:30:18 +0000 Received: from mail-pf1-x42f.google.com (unknown [2607:f8b0:4864:20::42f]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id f789908b-5522-4f0b-ba41-2342238d4f03; Tue, 01 Jun 2021 18:30:17 +0000 (UTC) Received: by mail-pf1-x42f.google.com with SMTP id g6so192548pfq.1 for ; Tue, 01 Jun 2021 11:30:17 -0700 (PDT) Received: from [192.168.2.12] (d173-181-74-129.bchsia.telus.net. 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For gaming there is never enough optimizing and power :D > > Thanks in advance! > -- > ------ > Greetz > Have you tried Spice? You'd probably get better video performance. It's not super-complicated to set up. From xen-users-bounces@lists.xenproject.org Tue Jun 01 18:42:54 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 01 Jun 2021 18:42:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.135317.251423 (Exim 4.92) (envelope-from ) id 1lo9Lg-00035v-2S; Tue, 01 Jun 2021 18:42:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 135317.251423; Tue, 01 Jun 2021 18:42:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo9Lf-00035n-V7; Tue, 01 Jun 2021 18:42:43 +0000 Received: by outflank-mailman (input) for mailman id 135317; Tue, 01 Jun 2021 18:42:41 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lo9Ld-00035b-Pm for xen-users@lists.xenproject.org; Tue, 01 Jun 2021 18:42:41 +0000 Received: from mail-pf1-x430.google.com (unknown [2607:f8b0:4864:20::430]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 207ff19f-f0a8-492c-98db-3276ae69fe6a; Tue, 01 Jun 2021 18:42:40 +0000 (UTC) Received: by mail-pf1-x430.google.com with SMTP id k15so194985pfp.6 for ; Tue, 01 Jun 2021 11:42:40 -0700 (PDT) Received: from [192.168.2.12] (d173-181-74-129.bchsia.telus.net. [173.181.74.129]) by smtp.gmail.com with ESMTPSA id w26sm15407559pgl.50.2021.06.01.11.42.38 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jun 2021 11:42:38 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 207ff19f-f0a8-492c-98db-3276ae69fe6a DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telus.net; s=google; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-transfer-encoding:content-language; bh=WLCEbsaz8ZjNAoKeTdgQE9ciqjd0oay5i+7k7gggUiM=; b=BVKSHRsuJRlxdfdU2RLsjdOf9sTugOwcbRXoiNCnxpU7urC17xRuHyzK45FigPNssd EFK8vUELdHmHsiDORBwA25YQZ3sCsWZcLzNpErlSX4m7J7TRz8bZWXCU8agc6W0BiQ2Y NXLBlEYduQUs6XWOzozxyy9lFWokouQF6izO9OmssKJIUda1LSIgizyXe4QnjYnYxO/R KAsg6fuQRhM+54R8Amwt/66mRwF/JHDXrlTx77mFtjxHs0V3m7QKnGH8oJFz/ETWQvL2 +ywl/Tp/OB84aGveUL2uMG9ky2YrMD9O9DVzwbk2vCKfPMnxxscLyruy0ztVm5Ete6f/ 96ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding :content-language; bh=WLCEbsaz8ZjNAoKeTdgQE9ciqjd0oay5i+7k7gggUiM=; b=mMZ8CwpbHbdJM/HdLDk64E8FAhPJs/M0ACNnvJyTrbJgEOHXc4qtI/tS6JE09mB3v+ akCk2YQExgrhENrlb8ZUgYEu4NSx4yVUhEw7LlbaI/E31OthgoCx+IkklEsSs7bdUaXu Dg4o22Nu70Rybc/l7Opf9xYFi7vDJSuQ4e9t1yOG7kThDUVtrlCl6FRnYPS4j8DhElvv vHQAg/YWy139MCL1Mgv1rKTYt7vnVh5jriaFxhZvMln8SHtRggxk1uzHPmGNFkraUnN8 qWrOJL/JpJjtXqKNFZfbiLQzEFZqKffTVMF/u2ZvY8QlNJNt3HIBvvpmr3AWtpfUQy+L Gb5w== X-Gm-Message-State: AOAM532ERgmLr7EBgbuMOkEz1H8Fbjlh2zGNCcLDXVfyrqXuTql1UWcb Rbnsz2vJs/X4rqFrGM9K1Afl+nuNCacvdjxU X-Google-Smtp-Source: ABdhPJznUWDKhHF4PIb/CGMIvgl1PsueP11kUpEQMCGqY2+eyxLRHJPcF6nvy+kO4l8YMBEezHEZkw== X-Received: by 2002:a05:6a00:1c4d:b029:2e9:c839:d2d with SMTP id s13-20020a056a001c4db02902e9c8390d2dmr12748122pfw.5.1622572959196; Tue, 01 Jun 2021 11:42:39 -0700 (PDT) Subject: Re: optimized conf for Win!= DomU To: xen-users@lists.xenproject.org References: <6495b90a87e8fe7af760c9075f7b4546@gmx.de> From: David Hill Message-ID: Date: Tue, 1 Jun 2021 11:42:38 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <6495b90a87e8fe7af760c9075f7b4546@gmx.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US On 2021-06-01 6:21 a.m., Chris wrote: > Hi, > > I use xen with win10 and a passed-through rtx2070 for gaming. > At the moment use this config: > > name = "marax" > uuid = "e0de3cb7-3937-417d-8d63-b0993b377b6a" > maxmem = 32768 > memory = 32768 > vcpus = 16 > rtc_timeoffset = 0 > localtime = 1 > on_poweroff = "destroy" > on_reboot = "restart" > on_crash = "restart" > boot = 'd' > vif = [ > "mac=00:16:3e:05:01:10,bridge=xenbr5,script=vif-bridge,model=e1000" ] > parallel = "none" > serial = "none" > type = "hvm" > loader = "/usr/lib64/xen/boot/hvmloader" > bios = "ovmf" > device_model_version = "qemu-xen" > bios_path_override = "/usr/lib64/xen/boot/OVMF.fd" > disk = [ "phy:/dev/mapper/marax_c,hda,rw", > "phy:/dev/vg_lilith/lv_marax_d,hdb,rw" ] > max_grant_frames = "128" > pci = [ "01:00.0", "01:00.1", "01:00.2", "01:00.3", "00:1f.3" ] > pci_permissive  = 1 > keymap = "de" > vnclisten="0.0.0.0:2" > pci_power_mgmt=1 > xen_platform_pci=1 > pci_msitranslate=1 > viridian=1 > hpet=1 > acpi=1 > apic=1 > pae=1 > videoram=16 > stdvga=1 > > it works nice but does someone see something in the config what I can > make better? For gaming there is never enough optimizing and power :D > > Thanks in advance! > -- > ------ > Greetz > Sorry - message took off when I tried to paste the Spice link in - my bad. https://www.spice-space.org/ I see you're passing through the video card, so that should work best, but to the extent you're using vnc or equivalent, Spice would be an improvement. It's not super-complicated to set up. You need Spice server to be enabled on the host - it's installed by default in major distros so that's probably not an issue. Download the Windows "guest" binaries from the download page and install to Windows. Use virt-viewer as the client to access the guest. On the other hand, since you're passing through the graphics card,  maybe there's no need for either vnc or Spice? Here's the relevant section of my cfg file: #VIDEO videoram                = 128 vga                     = 'stdvga' # 'qxl' doesn't work well in Linux yet 2020.02.10 #SPICE spice                   = 1 spicehost               = '0.0.0.0' spiceport               = 6001 spiceusbredirection     = 4 spicedisable_ticketing  = 1 spicevdagent            = 1 spice_clipboard_sharing = 1 soundhw                 = 'hda' # SPICE notes # https://www.spice-space.org/index.html # Be sure to install spice-vdagent in guest after install # for seemless mouse mode. # Using Remote Viewer (i.e. virt-viewer), connect to: # spice://{localhost}/{host_ip_address}:6001 # Enables redirecting up to 4 usb devices from spice client to domUs # spicedisable_ticketing enabled is for no spice password. # To use spicepasswd, replace with: # spicepasswd='test' # Intel hd audio emulated card used for spice audio I had trouble with veridien = 1 at one point From xen-users-bounces@lists.xenproject.org Fri Jun 04 18:41:37 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Jun 2021 18:41:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.135354.253827 (Exim 4.92) (envelope-from ) id 1lpEkN-0005Be-PD; Fri, 04 Jun 2021 18:40:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 135354.253827; Fri, 04 Jun 2021 18:40:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lpEkN-0005BW-KT; Fri, 04 Jun 2021 18:40:43 +0000 Received: by outflank-mailman (input) for mailman id 135354; Tue, 01 Jun 2021 20:44:30 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1loBFW-0008C7-0h for xen-users@lists.xenproject.org; Tue, 01 Jun 2021 20:44:30 +0000 Received: from mail.kaminski-berlin.org (unknown [134.255.253.37]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id d2c25c15-6682-4f55-821b-987fae1d9fe7; Tue, 01 Jun 2021 20:44:28 +0000 (UTC) Received: from mail.home.chao5.net (mail.home.chao5.net [192.168.50.100]) by mail.chao5.net (Postfix) with ESMTP id 34BE180032B; Tue, 1 Jun 2021 22:27:54 +0200 (CEST) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: d2c25c15-6682-4f55-821b-987fae1d9fe7 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=chao5.net; s=20210205home; t=1622579260; bh=9jJ9qeps7XsePDn7zDbFH6r0YHN6NLRtzaZ80eiS7Mo=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=k+SsJJg9KKOQIxqAXvh30Wadk6PAcA3UCfGl3yuXoFM9atAyAsPRPPygu9+sXwnbt /9A6ai0XIhr4jefIQjtfj6cxGptRqtudLcNME7Bi5NCXUUq390szzCQteDAkQqpqmN 6KFVOZ8rZro2014jV4heAQCjwzTr6yZv4dKPzvsBpVZVJ5tYmgEV81h97VZNGvoByW ViNap7wYG9dHPK/Rzn+cO2VLsJG0qBHwaAqawlkDJ0573LQJs69NH5dazzIK7SwxAx vUaBAC72bmiLrkL986g4oELPaO1Doa5szuY/PaWF+o0Yh21Rxz+/SwamrYPPb5gibt Ri7z7lII+VlQQ== Date: Tue, 01 Jun 2021 22:27:37 +0200 From: Perun To: David Hill Cc: xen-users@lists.xenproject.org Subject: Re: optimized conf for Win!= DomU In-Reply-To: References: <6495b90a87e8fe7af760c9075f7b4546@gmx.de> Message-ID: <33e2407a62a892f65ac233f6957525ac@chao5.net> X-Sender: perun@chao5.net Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Synology-MCP-Status: no X-Synology-Spam-Flag: no X-Synology-Spam-Status: score=-0.101, required 5, MID_RHS_MATCH_FROM 0, FROM_HAS_DN 0, TO_DN_SOME 0, TO_MATCH_ENVRCPT_ALL 0, MIME_GOOD -0.1, __THREADED 0, SUBJECT_HAS_EXCLAIM 0, RCPT_COUNT_TWO 0, RCVD_COUNT_ZERO 0, FROM_EQ_ENVFROM 0, MIME_TRACE 0, __NOT_SPOOFED 0, __BODY_URI_ONLY 0, __KHOP_NO_FULL_NAME 0, NO_RECEIVED -0.001 X-Synology-Virus-Status: no oh thx... I know spice. I use vnc only for trouble case. I use directly the screen on the nivida graphics or RDP. Am 01.06.2021 20:42, schrieb David Hill: > On 2021-06-01 6:21 a.m., Chris wrote: >> Hi, >> >> I use xen with win10 and a passed-through rtx2070 for gaming. >> At the moment use this config: >> >> name = "marax" >> uuid = "e0de3cb7-3937-417d-8d63-b0993b377b6a" >> maxmem = 32768 >> memory = 32768 >> vcpus = 16 >> rtc_timeoffset = 0 >> localtime = 1 >> on_poweroff = "destroy" >> on_reboot = "restart" >> on_crash = "restart" >> boot = 'd' >> vif = [ >> "mac=00:16:3e:05:01:10,bridge=xenbr5,script=vif-bridge,model=e1000" ] >> parallel = "none" >> serial = "none" >> type = "hvm" >> loader = "/usr/lib64/xen/boot/hvmloader" >> bios = "ovmf" >> device_model_version = "qemu-xen" >> bios_path_override = "/usr/lib64/xen/boot/OVMF.fd" >> disk = [ "phy:/dev/mapper/marax_c,hda,rw", >> "phy:/dev/vg_lilith/lv_marax_d,hdb,rw" ] >> max_grant_frames = "128" >> pci = [ "01:00.0", "01:00.1", "01:00.2", "01:00.3", "00:1f.3" ] >> pci_permissive  = 1 >> keymap = "de" >> vnclisten="0.0.0.0:2" >> pci_power_mgmt=1 >> xen_platform_pci=1 >> pci_msitranslate=1 >> viridian=1 >> hpet=1 >> acpi=1 >> apic=1 >> pae=1 >> videoram=16 >> stdvga=1 >> >> it works nice but does someone see something in the config what I can >> make better? For gaming there is never enough optimizing and power :D >> >> Thanks in advance! >> -- ------ >> Greetz >> > Sorry - message took off when I tried to paste the Spice link in - my > bad. > > https://www.spice-space.org/ > > I see you're passing through the video card, so that should work best, > but to the extent you're using vnc or equivalent, Spice would be an > improvement. > > It's not super-complicated to set up. You need Spice server to be > enabled on the host - it's installed by default in major distros so > that's probably not an issue. > > Download the Windows "guest" binaries from the download page and > install to Windows. Use virt-viewer as the client to access the guest. > > On the other hand, since you're passing through the graphics card,  > maybe there's no need for either vnc or Spice? > > Here's the relevant section of my cfg file: > > #VIDEO > videoram                = 128 > vga                     = 'stdvga' > # 'qxl' doesn't work well in Linux yet 2020.02.10 > > #SPICE > spice                   = 1 > spicehost               = '0.0.0.0' > spiceport               = 6001 > spiceusbredirection     = 4 > spicedisable_ticketing  = 1 > spicevdagent            = 1 > spice_clipboard_sharing = 1 > soundhw                 = 'hda' > > # SPICE notes > # https://www.spice-space.org/index.html > # Be sure to install spice-vdagent in guest after install > # for seemless mouse mode. > # Using Remote Viewer (i.e. virt-viewer), connect to: > # spice://{localhost}/{host_ip_address}:6001 > # Enables redirecting up to 4 usb devices from spice client to domUs > # spicedisable_ticketing enabled is for no spice password. > # To use spicepasswd, replace with: > # spicepasswd='test' > # Intel hd audio emulated card used for spice audio > > I had trouble with veridien = 1 at one point From xen-users-bounces@lists.xenproject.org Fri Jun 04 18:56:44 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 04 Jun 2021 18:56:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.137004.253845 (Exim 4.92) (envelope-from ) id 1lpEzU-0007DC-87; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: onlineschubla.de X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: FRYP281MB0582.DEUP281.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 24e98ae2-3c33-468b-f7ac-08d9278a6e38 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jun 2021 18:56:15.6698 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: bfc8b046-4d00-4e98-8679-43c06bdec9db X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: McX6LL5z7WI9jwgiWK6wVR+NPAPCGQ/Sz7qk5jTQaW44S16DB+0W4X3KG4CdfIgMzKZOwDggDnoRmpGkh9pVNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: FR2P281MB0203 > Von: Paul Leiber > Gesendet: Montag, 24. Mai 2021 22:39 >=20 > after getting my Windows Server 2012 DomU up and running, I have > problems with reliably passing through my PCIe TV tuner card (Hauppauge > HVR-2205). Further testing has lead me to the suspicion that there is an incorrect beh= avior, possibly a bug. It seems that every time I do a _reboot_ from within= the Windows DomU, the PCI device does not get attached to the DomU. It is = immediately available for attachment in the Dom0 when I check for it, and I= can reattach it to the DomU with "xl pci-attach" without any problems. Bes= ides the effect that the tuner card gets assigned a new instance number in = my TV software and I therefore need to reapply some settings in this softwa= re, the card works normally. If I _shut down_ the DomU from within the DomU (with Windows shutdown mecha= nism) or the Dom0 (with "xl shutdown) and restart the DomU with "xl create"= , the PCIe device gets attached automatically at DomU boot and the above me= ntioned side effects (new instance number, reapply software settings) do no= t occur. I could reproduce this behavior with a different TV tuner card from another= manufacturer, so it seems unlikely that it is related to the specific devi= ces I am using. > The boot entry has the following parameters: > dom0_mem=3D1024M,max:1024M xen-pciback.hide=3D(01:00.0) I figured out that giving kernel boot option " xen-pciback.hide" is not nec= essary as the driver is not built into the kernel, therefore I changed the = parameters to: dom0_mem=3D1024M,max:1024M The device is assigned to xen-pciback via /etc/modprobe.d/xen-pciback.conf = (there is no driver on the Dom0 for the tuner card, therefore no precaution= s for not loading other drivers are necessary, I think): options xen-pciback hide=3D(0000:01:00.0) While doing trial and error, I changed the pci line in the Xen config file = to: pci=3D['01:00.0,permissive=3D1,power_mgmt=3D1,seize=3D1'] But adding "seize=3D1" didn't change anything. > Logs from /var/log/xen, dmesg and /var/log/messages and Windows DomU > didn't seem to show relevant errors, but can of course be provided if > needed. Checking the xl logs more thoroughly, I now found the following lines: Waiting for domain matrix (domid 8) to die [pid 3113] Domain 8 has shut down, reason code 1 0x1 Action for shutdown reason code 1 is restart libxl: warning: libxl_domain.c:1739:libxl_retrieve_domain_configuration: Do= main 8:Device present in JSON but not in xenstore, ignored Domain 8 needs to be cleaned up: destroying the domain Done. Rebooting now Searching for this exact error message, I found the following quite old bug= report which sounds suspiciously similar to my experience, only for PV Dom= Us: https://bugzilla.redhat.com/show_bug.cgi?id=3D233801 1. Is it possible that this bug is still existing in my rather recent "out = of the box" debian setup? release : 4.19.0-14-amd64 version : #1 SMP Debian 4.19.171-2 (2021-01-30) xen_version : 4.11.4 2. Do you have any idea what I should do now? Any more testing I could do? = Should I mention this in the Xen developer mailing list? File a bug report = somewhere (where?)? I appreciate any advice. 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charset=UTF-8 Content-Transfer-Encoding: 7bit References: <1399391994.2416253.1623064168392.ref@mail.yahoo.com> X-Mailer: WebService/1.1.18368 YMailNorrin Content-Length: 73 Hello, What is the benefit of running a container as a VM? Thank you. From xen-users-bounces@lists.xenproject.org Tue Jun 08 02:03:02 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 08 Jun 2021 02:03:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.138222.255941 (Exim 4.92) (envelope-from ) id 1lqR4O-00048v-Kt; Tue, 08 Jun 2021 02:02:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 138222.255941; Tue, 08 Jun 2021 02:02:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqR4O-00048k-DY; Tue, 08 Jun 2021 02:02:20 +0000 Received: by outflank-mailman (input) for mailman id 138222; Tue, 08 Jun 2021 02:02:19 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqR4N-00048e-Hg for xen-users@lists.xenproject.org; Tue, 08 Jun 2021 02:02:19 +0000 Received: from mail-pj1-x102c.google.com (unknown [2607:f8b0:4864:20::102c]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 8ef10f6c-1163-44aa-b783-967d9c09e8c7; Tue, 08 Jun 2021 02:02:18 +0000 (UTC) Received: by mail-pj1-x102c.google.com with SMTP id pi6-20020a17090b1e46b029015cec51d7cdso1226498pjb.5 for ; Mon, 07 Jun 2021 19:02:18 -0700 (PDT) Received: from [192.168.1.116] (fp93c0183f.tkyc626.ap.nuro.jp. [147.192.24.63]) by smtp.gmail.com with ESMTPSA id p20sm9043362pff.204.2021.06.07.19.02.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 19:02:17 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 8ef10f6c-1163-44aa-b783-967d9c09e8c7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language; bh=YQQ5siylnA00d+nu8issRXr08cGwRHBq3iOSsGGb5zA=; b=QUGV4TGQ4gtEf7Jjo6HqKW2b/LSrPJUU7aB6Bij5yDr41+YEWdtcxNP7tgk2zZVd3C EofBhAuCgR76dDHe8GeFQK9TVCsFMjnBL+shzOlA7vYOrVtAXxSzPEgj2vvt+6zeJSUt y+C0YhDDA96TT5jslXBW79bXmTcu0c3UoKVOroinqRC/pWsNRP5WxVXyBVzDzq7tgae5 ct0zsbCz2KANlBuzAOC0uVl2rN67OwQQa/Lxzk/8jJqAQ/A8azgvDOZvcL5rV2gtlEnW nCQ4WROtENyjictWgApByazHlHwUuC0ARyw/KyN5a1w1uSi/PAhhFpuPlQtFrS1cBVMh onkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language; bh=YQQ5siylnA00d+nu8issRXr08cGwRHBq3iOSsGGb5zA=; b=oqSGkQe0gQm0oJdIuwSTZXDtQfAR3uNgRRUFu/bn8e/l/p7feVjTW0KpsGsaOSxvFQ VSN0ZFsOS571oa3H20m8DcfaqxTMoCaMYN4ZEvXdgWp5qfsRZ2kujnZK1RWrsLoIBZcX KtmGBeBC8TuREAPLKdjna3dTcUAETD5g0KnuDqNMFm8BUEmjj02T9xoeRQ7SKe/pO/TE 3idRxRx8GAdYZQPlIEJEwfe66BKr2oZZPY8MJcCAQsyfkDo3feYb9/pYYJEjFUuAC6q4 sZMyzzNvxuSh83xnlnpjjvJcZWeC1QSpMqn4tpYTUBl8ZgPmsA4/Ai1JzEM6HGW+NG2w So6A== X-Gm-Message-State: AOAM532Scunx7TOG7vdzN8CJEfIYPsLyYRkvcFQL3kHJI828k4G1qyZ6 uarkx8xOrgRQpZzzfHmJ7UAEhRYS5Ts= X-Google-Smtp-Source: ABdhPJyBojbUCTtcqeX6YZ69I2MbtP6giG7Q2fg88MOG5p9VFOg6Efid4ujSYEKvKaI9GAMAYgWUkA== X-Received: by 2002:a17:90b:19cb:: with SMTP id nm11mr23364253pjb.1.1623117738036; Mon, 07 Jun 2021 19:02:18 -0700 (PDT) Subject: Re: Containers as VMs. To: Jason Long , Xen-users References: <1399391994.2416253.1623064168392.ref@mail.yahoo.com> <1399391994.2416253.1623064168392@mail.yahoo.com> From: Bernd Bausch Message-ID: Date: Tue, 8 Jun 2021 11:02:14 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <1399391994.2416253.1623064168392@mail.yahoo.com> Content-Type: multipart/alternative; boundary="------------4209AE1C35F502082FF9AC55" Content-Language: en-US This is a multi-part message in MIME format. --------------4209AE1C35F502082FF9AC55 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit There is no benefit, since it's not possible. You can run a container *on *a VM, but not *as *a VM. The processes in a container run on the container host, using the host's kernel. A VM has its own kernel. Processes in a VM use the VM's kernel, and don't run on the VM's host. On 2021/06/07 8:09 PM, Jason Long wrote: > Hello, > What is the benefit of running a container as a VM? > > > Thank you. > --------------4209AE1C35F502082FF9AC55 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit

There is no benefit, since it's not possible. You can run a container on a VM, but not as a VM.

The processes in a container run on the container host, using the host's kernel.
A VM has its own kernel. Processes in a VM use the VM's kernel, and don't run on the VM's host.

On 2021/06/07 8:09 PM, Jason Long wrote:
Hello,
What is the benefit of running a container as a VM?


Thank you.
--------------4209AE1C35F502082FF9AC55-- From xen-users-bounces@lists.xenproject.org Tue Jun 08 17:05:13 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 08 Jun 2021 17:05:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.138617.256608 (Exim 4.92) (envelope-from ) id 1lqf9t-0001gT-8e; Tue, 08 Jun 2021 17:04:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 138617.256608; Tue, 08 Jun 2021 17:04:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9t-0001ew-0U; Tue, 08 Jun 2021 17:04:57 +0000 Received: by outflank-mailman (input) for mailman id 138617; Tue, 08 Jun 2021 17:04:55 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9r-0007tU-OS for xen-users@lists.xen.org; Tue, 08 Jun 2021 17:04:55 +0000 Received: from mail.xenproject.org (unknown [104.130.215.37]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 9afe90b8-9ae7-4e56-b6a9-e9a73ab8f493; Tue, 08 Jun 2021 17:04:36 +0000 (UTC) Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9S-0004gw-S9; Tue, 08 Jun 2021 17:04:30 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lqf9S-0004uS-Qx; Tue, 08 Jun 2021 17:04:30 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 9afe90b8-9ae7-4e56-b6a9-e9a73ab8f493 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=8Svh3GdkGDoE8YIWXwufr7G76Pf6eb1XITglGYjIIpc=; b=hbPJ0t7k6us6QP8PYVvAkM8aHN R6BJrks7gKLjeBBzIrKWZnATSOkXyL6+JbW7+UUl+QLJyli2WCpiwJ2K25iOzBdkWXvTyoxG9KOEE zLGAiTSWUMD3epyuxNfflvMy+1sZDOLpbFrKzXhohDTs/r9z0rJKZ4DgPUo+QbsFEg8w=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 375 v2 (CVE-2021-0089) - Speculative Code Store Bypass Message-Id: Date: Tue, 08 Jun 2021 17:04:30 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-0089 / XSA-375 version 2 Speculative Code Store Bypass UPDATES IN VERSION 2 ==================== New 4.12 backport (also targeting 4.11), addressing a build issue. Discuss the need for SPECULATIVE_HARDEN_BRANCH in Resolution. Provide Arm information links. Public release. ISSUE DESCRIPTION ================= Modern superscalar processors may employ sophisticated decoding and caching of the instruction stream to improve performance. However, a consequence is that self-modifying code updates may not take effect instantly. Whatever the architectural guarantees, some CPUs have microarchitectural behaviour whereby the stale instruction stream may be speculatively decoded and executed. Speculation of this form can suffer from type confusion in registers, and potentially leak data. For more details, see: https://www.vusec.net/projects/fpvi-scsb https://www.amd.com/en/corporate-product-security-bulletin-amd-sb-1003 https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/speculative-code-store-bypass.html https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/floating-point-value-injection.html https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#scsb https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#fvpi IMPACT ====== In attacker might be able to infer the contents of arbitrary host memory, including memory assigned to other guests. VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Whether a CPU is potentially vulnerable depends on its microarchitecture. Consult your hardware vendor. Xen running on ARM does not have runtime self-modying code, so is believed to be not vulnerable, irrespective of any hardware susceptibility. Xen running on x86 does have runtime self-modying code as part of emulation, and is believed to be potentially vulnerable. Xen is not vulnerable if retpoline or lfence mitigations for Spectre v2 protection are active. Protections depend on compiler support (as indicated by INDIRECT_THUNK), and a runtime setting (BTI-Thunk): # xl dmesg | grep -e INDIRECT_THUNK -e BTI-Thunk (XEN) Compiled-in support: INDIRECT_THUNK SHADOW_PAGING (XEN) Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: IBRS+ SSBD-, Other: SRB_LOCK+ IBPB L1D_FLUSH VERW BRANCH_HARDEN BTI-Thunk as either RETPOLINE or LFENCE prevents the vulnerability. MITIGATION ========== If Spectre v2 support is compiled in, but JMP is used by default, RETPOLINE or LFENCE can be selected with `spec-ctrl=bti-thunk=retpoline` or `spec-ctrl=bti-thunk=lfence`. CREDITS ======= This issue was discovered by Enrico Barberis, Hany Ragab, Herbert Bos, and Cristiano Giuffrida from the VUSec group at VU Amsterdam. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that in 4.13 and newer the patch will only take effect when the SPECULATIVE_HARDEN_BRANCH hypervisor config option is enabled. 4.12 and older do not have such an option, and the change will take effect unconditionally. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa375.patch xen-unstable - 4.14.x xsa375-4.13.patch Xen 4.13.x xsa375-4.12.patch Xen 4.12.x - 4.11.x $ sha256sum xsa375* 367d5bb97c942b9f744a57645df87148772c0879de6f351f36f88147f3958e83 xsa375.meta 301ef80da837bc2af36a0958f35f42f4d267b20ec6e91ae5faf2616167ef49f8 xsa375.patch dc024daf17242b6477a16a349754a94b2b25cbbfd8c14475741b778710a44c93 xsa375-4.12.patch f70511d843c6617b932da11ffe857e2e3aa3834ccff07d4d0beba90d63a3dae2 xsa375-4.13.patch $ NOTE CONCERNING CVE-2021-0086 ============================= Floating Point Value Injection (FPVI) was discovered and disclosed in the same research as SCSB. Xen on x86 does in some cases emulate floating point operations with guest provided inputs, but does not have subsequent control flow dependent on results, transient or otherwise, of the operation. Therefore, we believe Xen is not vulnerable to FPVI, irrespective of any hardware susceptibility. DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 08 Jun 2021 17:04:28 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lqf9Q-0004pg-7A; Tue, 08 Jun 2021 17:04:28 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 05eccac5-9d57-4387-9fbd-260d206a909a DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=RXy3Cr7MU80DA2L5jThtQDRerhPPf9p7E9ZKO/Rdv2E=; b=UYWD7GabKQoVeXpp3CKF1Byk23 K98dheUja/qTOwlXL2ChCQ47g7TOGsLAE+qZGwtMN7/JxilluQ7W5/Rjb4dJbs+EMxOsHLQHv+lZ5 PTeAkMDvzvIK1l6Frz/hw4QHOqnK5lmcRFT1a0OPJIaytMTWQz8UXIJys16rPinBWR7A=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 372 v3 (CVE-2021-28693) - xen/arm: Boot modules are not scrubbed Message-Id: Date: Tue, 08 Jun 2021 17:04:28 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-28693 / XSA-372 version 3 xen/arm: Boot modules are not scrubbed UPDATES IN VERSION 3 ==================== Public release. ISSUE DESCRIPTION ================= The bootloader will load boot modules (e.g. kernel, initramfs...) in a temporary area before they are copied by Xen to each domain memory. To ensure sensitive data is not leaked from the modules, Xen must "scrub" them before handing the page over to the allocator. Unfortunately, it was discovered that modules will not be scrubbed on Arm. IMPACT ====== Sensitive information from the boot modules might be visible to another domain after boot. VULNERABLE SYSTEMS ================== Only Arm systems are vulnerable. System running with "bootscrub=off" (disabling boot scrubbing) are not vulnerable. All versions of Xen since 4.12 are vulnerable. MITIGATION ========== There is no mitigation available. CREDITS ======= This issue was discovered by Julien Grall of Amazon. RESOLUTION ========== Applying the appropriate set of attached patches resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa372/*.patch xen-unstable xsa372-4.15/*.patch Xen 4.15.x xsa372-4.14/*.patch Xen 4.14.x - Xen 4.13.x xsa372-4.12/*.patch Xen 4.12.x $ sha256sum xsa372* xsa372*/* 06e43684c2d8a3085d55b8b40f57e1b9f1ee47519fac844dcbc21b57fb039915 xsa372.meta 8f872c7abe6c795dbef2e401f2223fda0dbb9d7c57dfebd8047eef37e1caf952 xsa372-4.12/0001-xen-arm-Create-dom0less-domUs-earlier.patch a43c6c11481cc3f13900908cee79cc6c5401921f6f4e8858c0796cf301cfe923 xsa372-4.12/0002-xen-arm-Boot-modules-should-always-be-scrubbed-if-bo.patch 6d1fad53795ebd251520022b6be901215426ba78ccbbc075841698973b74d2a2 xsa372-4.14/0001-xen-arm-Create-dom0less-domUs-earlier.patch 2ceb5d4d8d4f8a18046721daa3bb29633a620c4794b54e1265f5d4d69a314c3b xsa372-4.14/0002-xen-arm-Boot-modules-should-always-be-scrubbed-if-bo.patch 7feae5f9f7f2df0ec38c0b9358dc32671a9955f966b3120e17bb3fd820ce33ff xsa372-4.15/0001-xen-arm-Create-dom0less-domUs-earlier.patch 0cc73b4751fa49f68c6584b1c7882606c6e1f18561d8a6547017ab068de4eb4b xsa372-4.15/0002-xen-arm-Boot-modules-should-always-be-scrubbed-if-bo.patch 950672405c695ebf6ae59eebeb454bc0738b7afc3efa35ef9680d76eef4d4ec0 xsa372/0001-xen-arm-Create-dom0less-domUs-earlier.patch 9ceccd39c795e7756052a2f00256e043c8dda42e2c691df30e3f8b59190d6e8e xsa372/0002-xen-arm-Boot-modules-should-always-be-scrubbed-if-bo.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Jun 2021 17:04:55 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9r-0007tO-DP for xen-users@lists.xen.org; Tue, 08 Jun 2021 17:04:55 +0000 Received: from mail.xenproject.org (unknown [104.130.215.37]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id fd84a956-bc60-4155-82fb-83c1a5a14b45; Tue, 08 Jun 2021 17:04:35 +0000 (UTC) Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9S-0004ge-29; Tue, 08 Jun 2021 17:04:30 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lqf9S-0004tH-13; Tue, 08 Jun 2021 17:04:30 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: fd84a956-bc60-4155-82fb-83c1a5a14b45 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=Ii1NiQUN0sqcBtUpODfucz8MN9ngRgodsEM4sMsoxgo=; b=AYW4NCBzwch4WTdQyjRQjS5biA z3hiKC/BTFd1NDPrmKwEWP5GhyrkCATB8fpZ3GqoJvGjKbVT2xqaVKWkjxtIsMu564xCH8M/dGOs4 V75qrgF2D+/cQm80M1ByYNpW2bwHE5dnPbpOnv00MmiND5r5QE4e9zXuo/4W7/0Kpf8M=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 374 v2 (CVE-2021-28691) - Guest triggered use-after-free in Linux xen-netback Message-Id: Date: Tue, 08 Jun 2021 17:04:30 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-28691 / XSA-374 version 2 Guest triggered use-after-free in Linux xen-netback UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= A malicious or buggy network PV frontend can force Linux netback to disable the interface and terminate the receive kernel thread associated with queue 0 in response to the frontend sending a malformed packet. Such kernel thread termination will lead to a use-after-free in Linux netback when the backend is destroyed, as the kernel thread associated with queue 0 will have already exited and thus the call to kthread_stop will be performed against a stale pointer. IMPACT ====== A malicious or buggy frontend driver can trigger a dom0 crash. Privilege escalation and information leaks cannot be ruled out. VULNERABLE SYSTEMS ================== Systems using Linux version 5.5 or newer are vulnerable. MITIGATION ========== On x86 running only HVM guests with emulated network cards will avoid the issue. There's however no option in the upstream toolstack to offer only emulated network cards to guests. CREDITS ======= This issue was discovered by Michael Brown of iPXE and diagnosed by Olivier Benjamin, Michael Kurth and Martin Mazein of AWS. RESOLUTION ========== Applying the attached patch resolves this issue. xsa374-linux.patch Linux 5.5.0 - 5.12.2 $ sha256sum xsa374* 156cee65022359a5901cce97714d2abb16fef786246b1c4bf509083d21e085d6 xsa374-linux.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Deployment of the mitigation to disable PV network interfaces is NOT permitted (except where all the affected systems and VMs are administered and used only by organisations which are members of the Xen Project Security Issues Predisclosure List). Specifically, deployment on public cloud systems is NOT permitted. Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 08 Jun 2021 17:14:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 138781.256774; Tue, 08 Jun 2021 17:14:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqfJ2-0003Xc-IF; Tue, 08 Jun 2021 17:14:24 +0000 Received: by outflank-mailman (input) for mailman id 138781; Tue, 08 Jun 2021 17:14:23 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqfAB-0007tO-EB for xen-users@lists.xen.org; Tue, 08 Jun 2021 17:05:15 +0000 Received: from mail.xenproject.org (unknown [104.130.215.37]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 30c86ed4-349b-4cfd-81aa-9080b02df5f3; Tue, 08 Jun 2021 17:04:37 +0000 (UTC) Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lqf9T-0004hB-KV; Tue, 08 Jun 2021 17:04:31 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lqf9T-0004vc-JX; Tue, 08 Jun 2021 17:04:31 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 30c86ed4-349b-4cfd-81aa-9080b02df5f3 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=YQPfBSO74QvjUcDBr5ntUsPt+VI0GpRiGD3hrWKvTk0=; b=iQOQHvopS5dPP5RekZ3mQlKPNl uu1nhvctPYmkry7eCRLjsiHeB+k4O1jZ/Hh3DLEH19sTRbbm+dFCg3ujsKXGD5bjSqizrgVHwPzFO X52P3MGlYhlZySwrQLuv8IjYlz6RccNNzji1Th+24/3HF4q1HokQX5Eh97V774abJCwg=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 377 v2 (CVE-2021-28690) - x86: TSX Async Abort protections not restored after S3 Message-Id: Date: Tue, 08 Jun 2021 17:04:31 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-28690 / XSA-377 version 2 x86: TSX Async Abort protections not restored after S3 UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= This issue relates to the TSX Async Abort speculative security vulnerability. Please see https://xenbits.xen.org/xsa/advisory-305.html for details. Mitigating TAA by disabling TSX (the default and preferred option) requires selecting a non-default setting in MSR_TSX_CTRL. This setting isn't restored after S3 suspend. IMPACT ====== After using S3 suspend at least once, CPU0 remains vulnerable to TAA. This is an information leak. For full details of the impact, see XSA-305. VULNERABLE SYSTEMS ================== See XSA-305 for details of susceptibility to TAA. Only systems which are susceptible to TAA and have the XSA-305 fix are vulnerable. Only systems which support S3 suspend/resume are vulnerable. The vulnerability is only exposed if S3 suspend/resume is used. MITIGATION ========== Not using S3 suspend/resume avoids the vulnerability. CREDITS ======= This issue was discovered by Andrew Cooper of Citrix. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa377.patch xen-unstable - Xen 4.13.x xsa377-4.12.patch Xen 4.12.x xsa377-4.11.patch Xen 4.11.x $ sha256sum xsa377* 532cb030f97d72e8e534ad97182cd5e3aa0efeef405e255bb49649b4f0dd9947 xsa377.meta 21a30dbf80f6e78057cc7e785c8fda475d5a8a0b6b9442af3bd8ca31dd69becf xsa377.patch 3279317d56e7b8d0a2b0152b64b4c577381b8b01fa0a1a21ec6f855bb964278a xsa377-4.11.patch 65f61f1cb7bb0e068fd32e40755b9a9aae464d15ccd42c94dae68e495c5a45e0 xsa377-4.12.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Tue, 08 Jun 2021 17:04:29 +0000 Received: from iwj by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lqf9R-0004sG-6W; Tue, 08 Jun 2021 17:04:29 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: d72a1b62-f0df-4bfb-a265-c632ed6c1b57 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=SDVFctSv2PMnBZCWe0sMgIhEUf1wCGU8fcv1bKj95EE=; b=AhabBF0EpCQTSyDErdVNqpPU0R m0fuCOvQLwx0DgXPRJQAHsszdRCyeUnvuhtv/I/mTl9bN+ziOaiNwKT+S5O+bP1AM+ZMlxZtXZOgp rNCVmgh4+eVtFYXcfAmSrCAs5S9fm9+3jjh3H5xYDU5PczLTbe9sFBpx4XK9Tw0Xo45c=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 373 v2 (CVE-2021-28692) - inappropriate x86 IOMMU timeout detection / handling Message-Id: Date: Tue, 08 Jun 2021 17:04:29 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-28692 / XSA-373 version 2 inappropriate x86 IOMMU timeout detection / handling UPDATES IN VERSION 2 ==================== Public release. ISSUE DESCRIPTION ================= IOMMUs process commands issued to them in parallel with the operation of the CPU(s) issuing such commands. In the current implementation in Xen, asynchronous notification of the completion of such commands is not used. Instead, the issuing CPU spin-waits for the completion of the most recently issued command(s). Some of these waiting loops try to apply a timeout to fail overly-slow commands. The course of action upon a perceived timeout actually being detected is inappropriate: - on Intel hardware guests which did not originally cause the timeout may be marked as crashed, - on AMD hardware higher layer callers would not be notified of the issue, making them continue as if the IOMMU operation succeeded. IMPACT ====== A malicious guest may be able to elevate its privileges to that of the host, cause host or guest Denial of Service (DoS), or cause information leaks. VULNERABLE SYSTEMS ================== All Xen versions from at least 3.2 onwards are vulnerable. Earlier versions have not been inspected. Only x86 systems with in-use IOMMU hardware are vulnerable. x86 systems without any IOMMUs in use are not vulnerable. On Arm systems IOMMU / SMMU use is not security supported. Only x86 guests which have physical devices passed through to them can leverage the vulnerability. MITIGATION ========== Not passing through physical devices to untrusted guests will avoid the vulnerability. CREDITS ======= This issue was discovered by Igor Druzhinin and Andrew Cooper of Citrix, and further issues were uncovered by by Jan Beulich of SUSE while trying to fix the first issue. RESOLUTION ========== Applying the appropriate set of attached patches resolves this issue. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa373/xsa373-?.patch xen-unstable xsa373/xsa373-4.15-?.patch Xen 4.15.x xsa373/xsa373-4.14-?.patch Xen 4.14.x xsa373/xsa373-4.13-?.patch Xen 4.13.x xsa373/xsa373-4.12-?.patch Xen 4.12.x xsa373/xsa373-4.11-?.patch Xen 4.11.x $ sha256sum xsa373* xsa373*/* 2ded01092088735e0d8a0e378a41b772ec0f17ceb7afabc78228670c43407fc2 xsa373.meta f62df56cd176237521aa2ed4a22b0e893318b85bb0ce3c17bd7fca5282b6105b xsa373/xsa373-1.patch 9eed9566508e116c4da6c201b36fe7e53e98f2daf96cce8ed0a9ca192d783edc xsa373/xsa373-2.patch ffee9d17e40798c053a67707dd13d7a944e4a53de7bcfe3e146eac7871ca2608 xsa373/xsa373-3.patch c51bea462222c090ae671f14471ece00724348e6c04e5850f9b91d0b1eceaad8 xsa373/xsa373-4.11-1.patch 9a3b331e404a38c72ec154cefd78f1f67db6f25dcc1bd554b37ff50899ea42ff xsa373/xsa373-4.11-2.patch dba77bce4e6c88ec43df61e88bd5c8bee6e32c0ff681cbeddc4bceb0ee6c73dd xsa373/xsa373-4.11-3.patch b1f14e8885e3004de79c5012a1d9278d7a0c39633c5b73cbfda28679f1722c38 xsa373/xsa373-4.11-4.patch 791bccec1e7ba4429a0bafef5fd5a35a68562cee333d0962c70477172493ef3b xsa373/xsa373-4.11-5.patch cc4e1bcef148dbfc94ada92bef4408c5516cff2cf249e43c5595b1dbffbbc1e4 xsa373/xsa373-4.12-1.patch 12ffdac1526d96c4f1b572360a7f1a0371e8a177cf15228b126c1032de4e8930 xsa373/xsa373-4.12-2.patch 619425ba44f449bf7b0f519040ee579adff0d0293a95e9b0f70c943c02ae22fb xsa373/xsa373-4.12-3.patch b1f14e8885e3004de79c5012a1d9278d7a0c39633c5b73cbfda28679f1722c38 xsa373/xsa373-4.12-4.patch 96b3dd11d38ca8ca0b2dfe2dfb571045fcda78dbfe416580c9b04c5a8ce5fcef xsa373/xsa373-4.12-5.patch 4add1d05ad2780904ebc89b4d1a93a8f2757b6e9f45b075afce46392ae406b58 xsa373/xsa373-4.13-1.patch b064324db709078b8ef479df0c31ff3391a506755bfb0186d7d165592d025357 xsa373/xsa373-4.13-2.patch 6fe47fbba0c9d86f48643182d8a7c64ff70a7c8b290b0e93afe1d43d04bed480 xsa373/xsa373-4.13-3.patch b1f14e8885e3004de79c5012a1d9278d7a0c39633c5b73cbfda28679f1722c38 xsa373/xsa373-4.13-4.patch 96b3dd11d38ca8ca0b2dfe2dfb571045fcda78dbfe416580c9b04c5a8ce5fcef xsa373/xsa373-4.13-5.patch 4add1d05ad2780904ebc89b4d1a93a8f2757b6e9f45b075afce46392ae406b58 xsa373/xsa373-4.14-1.patch 8e61b7dda9ea21a830454e629fd23e3379b73fb230bd04107618e45975e117d1 xsa373/xsa373-4.14-2.patch a5aa80d8e893c268f171a5e429bfef0c553522f860e3e5132b4bd87d3a73c6b7 xsa373/xsa373-4.14-3.patch 25bfd2b821ae2cc867b8e2d480528ebd435da76cfab766e8106573cf8dc6f36c xsa373/xsa373-4.14-4.patch 162b3f14d15fe5ca2cb659efad6635f3803dde6fa97a6f0f1f7f202d3ea72d94 xsa373/xsa373-4.14-5.patch 4add1d05ad2780904ebc89b4d1a93a8f2757b6e9f45b075afce46392ae406b58 xsa373/xsa373-4.15-1.patch 9eed9566508e116c4da6c201b36fe7e53e98f2daf96cce8ed0a9ca192d783edc xsa373/xsa373-4.15-2.patch 13642541b056ed47129d8143a919bcc81a73797baedc3bd90afeb33f021e6d31 xsa373/xsa373-4.15-3.patch b2517a7e92c26a818e94ed5133d5aef6ef1d3a7a98f2f5355f1ad6f30baa3ab9 xsa373/xsa373-4.15-4.patch 3ca056796b93cb07ddb7e1dfda98410162382fc56135eb08bc5ff19137d8c427 xsa373/xsa373-4.15-5.patch b2517a7e92c26a818e94ed5133d5aef6ef1d3a7a98f2f5355f1ad6f30baa3ab9 xsa373/xsa373-4.patch 0b7bb146330f7fdc7c8c331a618307819073654a13d9fe1d0a8b83ab037ae802 xsa373/xsa373-5.patch $ DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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security team CC: Xen.org security team Subject: Xen Security Advisory 375 v3 (CVE-2021-0089,CVE-2021-26313) - Speculative Code Store Bypass Message-Id: Date: Wed, 09 Jun 2021 13:50:38 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-0089,CVE-2021-26313 / XSA-375 version 3 Speculative Code Store Bypass UPDATES IN VERSION 3 ==================== Added additional CVE, as Intel and AMD allocated different ones. ISSUE DESCRIPTION ================= Modern superscalar processors may employ sophisticated decoding and caching of the instruction stream to improve performance. However, a consequence is that self-modifying code updates may not take effect instantly. Whatever the architectural guarantees, some CPUs have microarchitectural behaviour whereby the stale instruction stream may be speculatively decoded and executed. Speculation of this form can suffer from type confusion in registers, and potentially leak data. For more details, see: https://www.vusec.net/projects/fpvi-scsb https://www.amd.com/en/corporate-product-security-bulletin-amd-sb-1003 https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/speculative-code-store-bypass.html https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/floating-point-value-injection.html https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#scsb https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#fvpi IMPACT ====== In attacker might be able to infer the contents of arbitrary host memory, including memory assigned to other guests. VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Whether a CPU is potentially vulnerable depends on its microarchitecture. Consult your hardware vendor. Xen running on ARM does not have runtime self-modying code, so is believed to be not vulnerable, irrespective of any hardware susceptibility. Xen running on x86 does have runtime self-modying code as part of emulation, and is believed to be potentially vulnerable. Xen is not vulnerable if retpoline or lfence mitigations for Spectre v2 protection are active. Protections depend on compiler support (as indicated by INDIRECT_THUNK), and a runtime setting (BTI-Thunk): # xl dmesg | grep -e INDIRECT_THUNK -e BTI-Thunk (XEN) Compiled-in support: INDIRECT_THUNK SHADOW_PAGING (XEN) Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: IBRS+ SSBD-, Other: SRB_LOCK+ IBPB L1D_FLUSH VERW BRANCH_HARDEN BTI-Thunk as either RETPOLINE or LFENCE prevents the vulnerability. MITIGATION ========== If Spectre v2 support is compiled in, but JMP is used by default, RETPOLINE or LFENCE can be selected with `spec-ctrl=bti-thunk=retpoline` or `spec-ctrl=bti-thunk=lfence`. CREDITS ======= This issue was discovered by Enrico Barberis, Hany Ragab, Herbert Bos, and Cristiano Giuffrida from the VUSec group at VU Amsterdam. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that in 4.13 and newer the patch will only take effect when the SPECULATIVE_HARDEN_BRANCH hypervisor config option is enabled. 4.12 and older do not have such an option, and the change will take effect unconditionally. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa375.patch xen-unstable - 4.14.x xsa375-4.13.patch Xen 4.13.x xsa375-4.12.patch Xen 4.12.x - 4.11.x $ sha256sum xsa375* 367d5bb97c942b9f744a57645df87148772c0879de6f351f36f88147f3958e83 xsa375.meta 301ef80da837bc2af36a0958f35f42f4d267b20ec6e91ae5faf2616167ef49f8 xsa375.patch dc024daf17242b6477a16a349754a94b2b25cbbfd8c14475741b778710a44c93 xsa375-4.12.patch f70511d843c6617b932da11ffe857e2e3aa3834ccff07d4d0beba90d63a3dae2 xsa375-4.13.patch $ NOTE CONCERNING CVE-2021-0086 / CVE-2021-26314 ============================================== Floating Point Value Injection (FPVI) was discovered and disclosed in the same research as SCSB. Xen on x86 does in some cases emulate floating point operations with guest provided inputs, but does not have subsequent control flow dependent on results, transient or otherwise, of the operation. Therefore, we believe Xen is not vulnerable to FPVI, irrespective of any hardware susceptibility. NOTE CONCERNING MULTIPLE CVES ============================= Intel and AMD allocated different CVEs for SCSB and FPVI. We have included both on this advisory. The allocations are as follows: Issue | Intel | AMD ------+---------------+--------------- SCSB | CVE-2021-0089 | CVE-2021-26313 FPVI | CVE-2021-0086 | CVE-2021-26314 DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?cERSM2c3SGs1TkQ1MmU4Rks3TmYzaUswZHF6T2xqNjk5dVZjZVNvbTFSQzBI?= =?utf-8?B?dDVEdkJJbTBkVVdrSVdXTU94MHhUZnFBUENSSXNVaGkyYjVFY3dnZzd4TUZF?= =?utf-8?B?cFVtck9tWmFyNFp3MTB5ZnJGdnliOXQ0NEI3M1YxUHIycUhTMFBhYmlDbmFN?= =?utf-8?B?eUJpb0dObkt3RzEvYXFrbkFsVlRhcURzcVJLck1mQTZKZ0syMmpDQnMrR3dC?= =?utf-8?B?elJoMDNXaXpMRnFtRHBwYisxdG5GUml6N2ZpWTBVQWwvZEo1MjhTQnpIc3Vu?= =?utf-8?B?VDFqaUpwNy91ODNLZ1ZiTHR0TlYwb1hYblpZd3hlSjZ1eGI5SW9XMkQwQWJM?= =?utf-8?B?UlVDQmxkQ3hKRVRFTDE0S2lYVk1OdS93RDZLV1k0MkZVeW56VGZZd1VPMjJz?= =?utf-8?B?THNVd0lINmlzVE9xTDNHcUNsUjV1eWNWdWFPbk5kR3VCVnRMd1pnb3JtY0tN?= =?utf-8?B?TWh3ZXJJUGFKYk9BbmNuVTlZMGJ3aVBaUmRGa3lIVWEzR0c4YlQ1SlZrSUkz?= =?utf-8?B?U2ZXd01zUDlSTHNHQ1NRSDduZDV4VmE3bGtUS2p6UGNIelVwM1JTMkZ0b0VF?= =?utf-8?B?ZXVLWVN3dUVmdTRuV3BOM0puRFJESS9pRVZxVFBjaHlHd1J3M1Rwakc4OTRn?= =?utf-8?B?Q2REM0diY09lZjdoM3RlQzExellHVm5LWHh6Nk5FMVJJK0ZKeWgyaDZvTzFF?= =?utf-8?B?UXlFNEF5MkJWQlF0SGY0WStaREpFa1U3RzJpNXJibGVUY1NLMERxMkZOcGY3?= =?utf-8?B?MG5EMHAybmVhcSsxME9GV2Nsak55MjJlak16alFERmV6Y2xuSzJBWlBQMHk2?= =?utf-8?B?MHFrS0dlQjRTZEdoVmxXNWxCUEo3cWpEWjA3T0ZLQWJLbG5FN1RuWjBiRFp1?= =?utf-8?B?eXFqN2lkN2kyYWZnYndmSDQxT1BTK2VGeWdCOS9LWWRNQ1BFWlRNRmhEN0U5?= =?utf-8?B?RTVGODg0cFJQTnFoRmh5Tm5Ldm9SaER0MXcvazErc3N2YnYxbWxYem1BQXBZ?= =?utf-8?B?eHNKOUhNUFd1R3RwMDl0cVRpYm9jdDUwdkYvZHY2MGdmY01ja1hvaTJEZDQv?= =?utf-8?B?OE1nczM4OHZBNlVRTEVuTnBxTjJPdkxFNnNaUWtTT0ZUR011cjZvaURNOVdu?= =?utf-8?B?cUdpdkFNMlVRUWxlSzNIQkN6dUtNY2RWY25tZnZDSnRTclFwdlM0eFM2aTlx?= =?utf-8?B?TDhWM3pid21FamcxSWpqcVBsUDRYQi8xcktrakJ2dXFSVEE2QlVIaElaUGJj?= =?utf-8?B?emxHN2Q2bGpOcm4xOGE4SVUzTGlTVkdZUkx0Zk5KMFFNY0RNNmZsWHpnZXNh?= =?utf-8?B?Sms4SEV2UFllV3NwQ2FqbjJyMUwzb3ExU2RiMDJqNEUrOFg0MGNkaXJSblJ4?= =?utf-8?B?czNCWldqdmRzRmxWeXh1RFRhS3NzODVwK3QyMy9xbkhTQnpnOWpRT1ZZV2xo?= =?utf-8?B?ZW1aMHFIVDNBMWdEaUVIY2xObHhCUnF3bTRidFFmSW9sT0Q3OWN0R0hwWjZZ?= =?utf-8?B?aVpXdk4xdzAzZC95ZnlsOTVqTnZLQkN4U0trUEZFL3g3WUxjS1dJRzYxWnpm?= =?utf-8?B?VzhndzJpNkJVajlrVUxVMXpuK2daajh5OER6MUVkYkQrUm5SbDlpWUtmRU0w?= =?utf-8?B?SDdmZVF4MEZGUDNicVhCeHMreGpvVDFWNVZQLzVGeVBNb1VMRnAzcmJ4V3N4?= =?utf-8?B?VW9CWXFicUJKOEE1WDMwcG50azR3aFhxbE5MTjZEVm9xSUw0dm1hUmVSV0My?= =?utf-8?Q?DHM9jel4n9OGAnwULgifD0VFO1lQWkMCCu9EhgJ?= X-MS-Exchange-CrossTenant-Network-Message-Id: 20472282-6dc0-48ad-cd8c-08d92bea43bf X-MS-Exchange-CrossTenant-AuthSource: BYAPR03MB3623.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jun 2021 08:32:20.9840 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ci2DujcDDRagq1oknXZ89DVzPs2k4xjTzrUvkQ04Q0WguFR5eXgSC9TgUaZ2BdemFWMTTYkaVDMrc8pAQoeqeTDGQ90XPhJh9X3PkhePHhQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR03MB4423 X-OriginatorOrg: citrix.com On 10/06/2021 09:04, Sven Kieske wrote: > On Mi, 2021-06-09 at 13:50 +0000, Xen.org security team wrote: >> For more details, see: > [..] >> https://www.amd.com/en/corporate-product-security-bulletin-amd-sb-1003 > The above link turns into a "Page not found", at least for me, I believe the correct link is: > > https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1003 Ah - the link changed, and I thought I'd fixed it.  Clearly not. Thanks - I'll issue a correction to the XSA. ~Andrew From xen-users-bounces@lists.xenproject.org Thu Jun 10 09:17:45 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 10 Jun 2021 09:17:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.139708.258335 (Exim 4.92) (envelope-from ) id 1lrGoA-00062s-S8; Thu, 10 Jun 2021 09:17:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 139708.258335; Thu, 10 Jun 2021 09:17:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrGoA-00062g-No; Thu, 10 Jun 2021 09:17:02 +0000 Received: by outflank-mailman (input) for mailman id 139708; Thu, 10 Jun 2021 09:17:01 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrGo9-0005Nu-6B for xen-users@lists.xen.org; Thu, 10 Jun 2021 09:17:01 +0000 Received: from mail.xenproject.org (unknown [104.130.215.37]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 6956cd60-6143-44ef-af56-aae603ecec05; Thu, 10 Jun 2021 09:16:48 +0000 (UTC) Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrGnq-0002tN-Bw; Thu, 10 Jun 2021 09:16:42 +0000 Received: from gdunlap by xenbits.xenproject.org with local (Exim 4.92) (envelope-from ) id 1lrGnq-0003by-9y; Thu, 10 Jun 2021 09:16:42 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 6956cd60-6143-44ef-af56-aae603ecec05 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Date:Message-Id:Subject:CC:From:To:MIME-Version: Content-Transfer-Encoding:Content-Type; bh=HQQ0/VpUTzU0PMDoFxBU+QcP4disNR968M6tzreckD4=; b=JsASxyBKXUdHWhP0JElyswO8DO Pss+lXRxLxEMuGWuEkzgfKKZmDBbCjnflU4dK/phOuC12hihXpQcFJEZUBwLNjaVFu+XpKUYuLHe7 P1hV/yc8tc2RgFwUPskPA+QYJhk7bYs1djA+9lxhJUDXZcmgJvTKnrf9+uX8sw8y2nf4=; Content-Type: multipart/mixed; boundary="=separator"; charset="utf-8" Content-Transfer-Encoding: binary MIME-Version: 1.0 X-Mailer: MIME-tools 5.509 (Entity 5.509) To: xen-announce@lists.xen.org, xen-devel@lists.xen.org, xen-users@lists.xen.org, oss-security@lists.openwall.com From: Xen.org security team CC: Xen.org security team Subject: Xen Security Advisory 375 v4 (CVE-2021-0089,CVE-2021-26313) - Speculative Code Store Bypass Message-Id: Date: Thu, 10 Jun 2021 09:16:42 +0000 --=separator Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Xen Security Advisory CVE-2021-0089,CVE-2021-26313 / XSA-375 version 4 Speculative Code Store Bypass UPDATES IN VERSION 4 ==================== Correct the link to the AMD bulletin. ISSUE DESCRIPTION ================= Modern superscalar processors may employ sophisticated decoding and caching of the instruction stream to improve performance. However, a consequence is that self-modifying code updates may not take effect instantly. Whatever the architectural guarantees, some CPUs have microarchitectural behaviour whereby the stale instruction stream may be speculatively decoded and executed. Speculation of this form can suffer from type confusion in registers, and potentially leak data. For more details, see: https://www.vusec.net/projects/fpvi-scsb https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1003 https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/speculative-code-store-bypass.html https://software.intel.com/content/www/us/en/develop/articles/software-security-guidance/advisory-guidance/floating-point-value-injection.html https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#scsb https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/frequently-asked-questions#fvpi IMPACT ====== In attacker might be able to infer the contents of arbitrary host memory, including memory assigned to other guests. VULNERABLE SYSTEMS ================== Systems running all versions of Xen are affected. Whether a CPU is potentially vulnerable depends on its microarchitecture. Consult your hardware vendor. Xen running on ARM does not have runtime self-modying code, so is believed to be not vulnerable, irrespective of any hardware susceptibility. Xen running on x86 does have runtime self-modying code as part of emulation, and is believed to be potentially vulnerable. Xen is not vulnerable if retpoline or lfence mitigations for Spectre v2 protection are active. Protections depend on compiler support (as indicated by INDIRECT_THUNK), and a runtime setting (BTI-Thunk): # xl dmesg | grep -e INDIRECT_THUNK -e BTI-Thunk (XEN) Compiled-in support: INDIRECT_THUNK SHADOW_PAGING (XEN) Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: IBRS+ SSBD-, Other: SRB_LOCK+ IBPB L1D_FLUSH VERW BRANCH_HARDEN BTI-Thunk as either RETPOLINE or LFENCE prevents the vulnerability. MITIGATION ========== If Spectre v2 support is compiled in, but JMP is used by default, RETPOLINE or LFENCE can be selected with `spec-ctrl=bti-thunk=retpoline` or `spec-ctrl=bti-thunk=lfence`. CREDITS ======= This issue was discovered by Enrico Barberis, Hany Ragab, Herbert Bos, and Cristiano Giuffrida from the VUSec group at VU Amsterdam. RESOLUTION ========== Applying the appropriate attached patch resolves this issue. Note that in 4.13 and newer the patch will only take effect when the SPECULATIVE_HARDEN_BRANCH hypervisor config option is enabled. 4.12 and older do not have such an option, and the change will take effect unconditionally. Note that patches for released versions are generally prepared to apply to the stable branches, and may not apply cleanly to the most recent release tarball. Downstreams are encouraged to update to the tip of the stable branch before applying these patches. xsa375.patch xen-unstable - 4.14.x xsa375-4.13.patch Xen 4.13.x xsa375-4.12.patch Xen 4.12.x - 4.11.x $ sha256sum xsa375* 367d5bb97c942b9f744a57645df87148772c0879de6f351f36f88147f3958e83 xsa375.meta 301ef80da837bc2af36a0958f35f42f4d267b20ec6e91ae5faf2616167ef49f8 xsa375.patch dc024daf17242b6477a16a349754a94b2b25cbbfd8c14475741b778710a44c93 xsa375-4.12.patch f70511d843c6617b932da11ffe857e2e3aa3834ccff07d4d0beba90d63a3dae2 xsa375-4.13.patch $ NOTE CONCERNING CVE-2021-0086 / CVE-2021-26314 ============================================== Floating Point Value Injection (FPVI) was discovered and disclosed in the same research as SCSB. Xen on x86 does in some cases emulate floating point operations with guest provided inputs, but does not have subsequent control flow dependent on results, transient or otherwise, of the operation. Therefore, we believe Xen is not vulnerable to FPVI, irrespective of any hardware susceptibility. NOTE CONCERNING MULTIPLE CVES ============================= Intel and AMD allocated different CVEs for SCSB and FPVI. We have included both on this advisory. The allocations are as follows: Issue | Intel | AMD ------+---------------+--------------- SCSB | CVE-2021-0089 | CVE-2021-26313 FPVI | CVE-2021-0086 | CVE-2021-26314 DEPLOYMENT DURING EMBARGO ========================= Deployment of the patches and/or mitigations described above (or others which are substantially similar) is permitted during the embargo, even on public-facing systems with untrusted guest users and administrators. But: Distribution of updated software is prohibited (except to other members of the predisclosure list). Predisclosure list members who wish to deploy significantly different patches and/or mitigations, please contact the Xen Project Security Team. (Note: this during-embargo deployment notice is retained in post-embargo publicly released Xen Project advisories, even though it is then no longer applicable. This is to enable the community to have oversight of the Xen Project Security Team's decisionmaking.) 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Thu, 10 Jun 2021 10:04:38 +0200 (CEST) Received: from XXX.XXX.XXX.XXX (XXXXX.XX [XXX.XXX.XXX.XXX]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: p1000p113) by mail.agenturserver.de (Postfix) with ESMTPSA id B3DE4413A5; Thu, 10 Jun 2021 10:04:37 +0200 (CEST) Received: from XXX.XXX.XXX.XXX (XXXXX.XX [XXX.XXX.XXX.XXX]) ex2.mw-ks.local (2a03:2a00:0:3:edc0:71ef:fb82:674a) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 10 Jun 2021 10:04:37 +0200 Received: from XXX.XXX.XXX.XXX (XXXXX.XX [XXX.XXX.XXX.XXX]) ex1.mw-ks.local ([fe80::e187:7dcb:b1d9:d875%2]) with mapi id 15.01.2176.014; Thu, 10 Jun 2021 10:04:37 +0200 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: abbf89da-0741-433d-8658-2910531f69ab From: Sven Kieske To: "xen-announce@lists.xen.org" , "oss-security@lists.openwall.com" , "xen-users@lists.xen.org" , "xen-devel@lists.xen.org" CC: "security-team-members@xen.org" Subject: Re: [oss-security] Xen Security Advisory 375 v3 (CVE-2021-0089,CVE-2021-26313) - Speculative Code Store Bypass Thread-Topic: [oss-security] Xen Security Advisory 375 v3 (CVE-2021-0089,CVE-2021-26313) - Speculative Code Store Bypass Thread-Index: AQHXXTa+QYm8IqItZ0WWKzH19j3F/KsMwoyA Date: Thu, 10 Jun 2021 08:04:37 +0000 Message-ID: <90160ae63614ca1098c87f5c60002b9a35e922ef.camel@mittwald.de> References: In-Reply-To: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [2a03:2a00:2:1::48] Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-0l3DJMvbZ87xKiFC2jeo" MIME-Version: 1.0 --=-0l3DJMvbZ87xKiFC2jeo Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mi, 2021-06-09 at 13:50 +0000, Xen.org security team wrote: > For more details, see: [..] > https://www.amd.com/en/corporate-product-security-bulletin-amd-sb-1003 The above link turns into a "Page not found", at least for me, I believe th= e correct link is: https://www.amd.com/en/corporate/product-security/bulletin/amd-sb-1003 HTH Mit freundlichen Gr=C3=BC=C3=9Fen / Regards Sven Kieske Systementwickler =20 =20 Mittwald CM Service GmbH & Co. KG K=C3=B6nigsberger Stra=C3=9Fe 4-6 32339 Espelkamp =20 Tel.: 05772 / 293-900 Fax: 05772 / 293-333 =20 https://www.mittwald.de =20 Gesch=C3=A4ftsf=C3=BChrer: Robert Meyer, Florian J=C3=BCrgens =20 St.Nr.: 331/5721/1033, USt-IdNr.: DE814773217, HRA 6640, AG Bad Oeynhausen Komplement=C3=A4rin: Robert Meyer Verwaltungs GmbH, HRB 13260, AG Bad Oeynh= ausen Informationen zur Datenverarbeitung im Rahmen unserer Gesch=C3=A4ftst=C3=A4= tigkeit=20 gem=C3=A4=C3=9F Art. 13-14 DSGVO sind unter www.mittwald.de/ds abrufbar. --=-0l3DJMvbZ87xKiFC2jeo Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdKGxKl7rK5iwbpcWxvL1MwMBtBEFAmDBx5MACgkQxvL1MwMB tBESWRAA1dpFqCNLMZBg07fdyqYg4VJ2uM+jRKRrPFBLev0QNYF/VRjs7vtO/R/4 /gHlFoOX4uxaMO0GFlPgQ8bZ6qKmNTQ4CDIsLgWvIPf4Ldy0p3Qs92AQxyEGLHpL IFc1qNdn07koYU+KxfPKNMFH1TZAqrU+hGZec68LtyhVBSpYKby/co2iZ6bH/88l 6Houy2etNAKkztiEUEEKBPPXTFG8v3AqEXq/mwfOUYU9IfuRPcaxcyvTmKdpwLun 24kU2fbifpwV7YDP1J/Q97p4YwD6Y2TSPDlxEu0eOlWCLQTs1dHx2UPBCZf85CjK ZgHewt7oFcnwdWmtLtm3Q8/ALWZJdoERDUTOXds8pjjt84Pn9iiHdhNJE7LE0hnR XFUha/OjQw9NxIer+K4YPo5bbG9wAY0lkFYPYZ05D3Ebnncmk58VXJUkWo+4E3zW LL0AO2DdcP4UOZef7zwhtDD6BNlBxJSz+YvGtNn1KoS7JkdPFsD61x+MBWZXeqY1 ke8Pdq8BnZPCq/6ked5iJtxOpwkjQWz9Owvr1lKRQOfyw4G5G7hr7eB/6/eXyTRw Yj29vqAI0F/FtqqaSahtXYlvneLePX5vgajH/C3sdVLkVQvQBVlwF4eqCQRmkmCo iG658IfWJvD6DsYTGM50PjXunfaSsWKz8j7QDRr6RaHEu3O7Tdk= =o3nj -----END PGP SIGNATURE----- --=-0l3DJMvbZ87xKiFC2jeo-- From xen-users-bounces@lists.xenproject.org Thu Jun 10 22:50:09 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 10 Jun 2021 22:50:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.140074.258904 (Exim 4.92) (envelope-from ) id 1lrTUG-00006Z-22; Thu, 10 Jun 2021 22:49:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 140074.258904; Thu, 10 Jun 2021 22:49:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrTUF-00006O-TM; Thu, 10 Jun 2021 22:49:19 +0000 Received: by outflank-mailman (input) for mailman id 140074; Thu, 10 Jun 2021 22:49:18 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrTUE-00006I-IQ for xen-users@lists.xenproject.org; Thu, 10 Jun 2021 22:49:18 +0000 Received: from mail-pf1-x433.google.com (unknown [2607:f8b0:4864:20::433]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id eb05764d-0684-46e1-8b44-9b00a14d1335; Thu, 10 Jun 2021 22:49:17 +0000 (UTC) Received: by mail-pf1-x433.google.com with SMTP id k15so2842378pfp.6 for ; Thu, 10 Jun 2021 15:49:17 -0700 (PDT) Received: from vibe.barkdullak.us (29-121-237-24.static.gci.net. [24.237.121.29]) by smtp.gmail.com with ESMTPSA id p11sm2810641pfo.126.2021.06.10.15.49.15 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jun 2021 15:49:16 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: eb05764d-0684-46e1-8b44-9b00a14d1335 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=to:from:subject:message-id:date:user-agent:mime-version :content-transfer-encoding:content-language; bh=1fjxlLThG3y3EoIFXLub6clE1Llq5RjQwIRKMpWqpSU=; b=e+4uc+4zeRMBzRYcLCt8cLoDeyk1zGO5KvZScRGMAL0M3lmLOtxzZeCUHsIw6qffsO PIwgrgFZgtzaMRMt0DzCWywCxF1xGq68ZahgxjuphI6scfHyyl1WoRaTCXYPea/q9e5r h9lR2FxhE5VGudLteqiip34a/b+a32xDtDtuNWRLhhhK5rjXmqC+XXSE27EvW7Qw61cV KP4e46jTmJHbqr/7gydAQbpovFuoz0ZcGornyiWd73Ojk45KVuHa3+fOv/dpYvgkGfiX nOIB9tRgr9FauVry2VHKNoNUrQDWMFiqiyCL95EMQr8Up5/gQIBdKWb8LgqB1ItPxZ4J FYXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:to:from:subject:message-id:date:user-agent :mime-version:content-transfer-encoding:content-language; bh=1fjxlLThG3y3EoIFXLub6clE1Llq5RjQwIRKMpWqpSU=; b=Eb4MddfeqK7sywj8Ovswb1GNEkNJ7XnXNUiOK/4N6oUmBf/xQqfm8OFG5AYOZsU69F Ps7PyLB8LuQp4KnIgNbiwOGDUUhhK2ti9sdny+cKyeL0RqMTn60WoVk/Acko03FaKm3e b+MJQ94wJeqzte6O9QPPztThe1vty/KGBQL3rDrkITvxjwr5mGWPSQIazemBvKdomrSU AOJdm0z3vwz6hhNfHL5xpFZ8MrQgn9hYt7c4/u7i9MaJsAXA/d92VZm5oTmpjLhJgbJt E+pG4PchzizEnMrHd4yhUSuiDiMhdocuREQAXSysHG6VL66uiZAK6eNPXS5aaSBqkpgP KcOw== X-Gm-Message-State: AOAM533IaDGlr0HIR7QVmuKTf7MhDoYaUrjWENMRrldd5J52h7sULV8u cIDQPa9zu3cD5Ku5f7QbX/sT9Dz3Ah0= X-Google-Smtp-Source: ABdhPJyI+YiMyq4SZw2h9U+Hl1t3RsCbPk4wPvQFo2pAJlo4xyuQV9KXgLksj9e63jXC+uGRN0CxJQ== X-Received: by 2002:a62:687:0:b029:2ef:be02:c346 with SMTP id 129-20020a6206870000b02902efbe02c346mr5211251pfg.51.1623365356465; Thu, 10 Jun 2021 15:49:16 -0700 (PDT) To: xen-users@lists.xenproject.org From: TheBearAK Subject: Slow Apt Message-ID: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> Date: Thu, 10 Jun 2021 14:49:14 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US First, hello.  New to the list, but I've been using Xen Hypervisor for a long time. I'm curious if anyone else has had this issue. I recently upgraded a server from Debian Squeeze to Buster with kernel 4.19.0-16-amd64 and found that apt/aptitude commands are slow in response. For example, 'apt-get update' can take 10 minutes to complete, hanging up on certain parts of the downloads either at 0% or 90%.    This is something that normally takes a few seconds. Even the DomU's suffer the same issue. On another server I have kernel 4.19.0-14-amd64 and it seems to be running just fine most of the time.  I do get some hiccups, but not nearly as much as the above upgraded server. I've also noticed that writes will sometimes pause for several seconds, specially when transferring large files. Setup: E3-1230 V2 @ 3.30GHz 16 GB RAM Hard drives are spinning disk.  2 TB drives (EXT4) DomUs are using Disk.Img for their disk. From xen-users-bounces@lists.xenproject.org Fri Jun 11 00:30:46 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 11 Jun 2021 00:30:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.140102.258947 (Exim 4.92) (envelope-from ) id 1lrV3b-0002NY-4J; Fri, 11 Jun 2021 00:29:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 140102.258947; Fri, 11 Jun 2021 00:29:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrV3b-0002NQ-0w; Fri, 11 Jun 2021 00:29:55 +0000 Received: by outflank-mailman (input) for mailman id 140102; Fri, 11 Jun 2021 00:29:53 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrV3Z-0002NF-2K for xen-users@lists.xenproject.org; Fri, 11 Jun 2021 00:29:53 +0000 Received: from mail-pf1-x435.google.com (unknown [2607:f8b0:4864:20::435]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 19cfc3eb-4c91-48f9-8b5e-5f2bcbdf967d; Fri, 11 Jun 2021 00:29:52 +0000 (UTC) Received: by mail-pf1-x435.google.com with SMTP id k15so3006732pfp.6 for ; Thu, 10 Jun 2021 17:29:52 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 19cfc3eb-4c91-48f9-8b5e-5f2bcbdf967d DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=R/5yXGl+hh9VGVOq0jhd7DHgf3yaWYj7nFZZhApdv1I=; b=uLkIOLgHj1ugIPPhx2XBSQrVTnyomvSa3iKJXNGO0cFCZyaILFopzzwthAW+TioZfU jaAxBP9h4gS7dBVOko7VkhvF5RhHbLqkSFMb4M3p9veyz2shFj8q6tOw4BZGsyKym4np EZLe/p2t3WOIRaObC87sc1nq/4XkMvtSnNWyu7CabKbRNnWiDslJPT7HgTwOMax62x96 2xvW9B2oFPNkDh2/Cx7Mw5LvMxFKUpnAoPPPzByddzqw2us2UzTFxj/gTKHHDwigY9Oo UIFMh91TOnwFFaSg0qp1D/FnY7RFZ76GM5/T2sU03Dsgg/EYB/48do/tw3FnWgRfUFa6 Uyjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=R/5yXGl+hh9VGVOq0jhd7DHgf3yaWYj7nFZZhApdv1I=; b=ElbGlz9SOfewO8AqAH6tqdPKh5hrKJet0o7fTVuugmwk8EALrhyfUMvmfaA71RS1cb cX+nAlHU7InpX/l/dK6+OHhwgP0Qz89nnxYdiLblDyfrRTjt+uruhFFfXWEJWggqIgwy +UeurefnDHeaH9OygdsH+liSyRG2n5Y8yywmu11vy2urZzJjck+hSXu++9d4C+8twZo5 17s1yI/W3NrzEyiJnM/D4GGrr31g9j/uLlLPgklIbInQmM3hRySrjHvrFvh+8DMExmu4 JogA+jyL2SYhxHDFyM/R68RznN0RpuMLwAX6vJjt0xJuzOBGGQvhAqlQwJfzUJAvMFlW KDeQ== X-Gm-Message-State: AOAM531uUYX0Fzd35xN+Vz2FK1h5Tdr3K24xVMVlnPSmD/FRXzvGOyK4 ih/v5OHYZ5sWNddd775SXDSoQuDJcCibiIEDoVtpLdwH X-Google-Smtp-Source: ABdhPJyDPXlb6yzIbUQ5jThGdImx6ky7VlGq3s86gXCU3Tw1+X7V70HY96ISJeYiUZIjinsbY8IOewZmV+4OgdZhi5M= X-Received: by 2002:a63:af02:: with SMTP id w2mr954838pge.350.1623371391002; Thu, 10 Jun 2021 17:29:51 -0700 (PDT) MIME-Version: 1.0 References: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> In-Reply-To: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> From: Chris Myers Date: Thu, 10 Jun 2021 19:29:39 -0500 Message-ID: Subject: Re: Slow Apt To: xen-users@lists.xenproject.org Content-Type: multipart/alternative; boundary="000000000000196bc005c4729b13" --000000000000196bc005c4729b13 Content-Type: text/plain; charset="UTF-8" Out of curiosity, how does "top" look when it's running? Especially things like "wa" (IOWait) and "st" (steal)? On Thu, Jun 10, 2021 at 5:49 PM TheBearAK wrote: > First, hello. New to the list, but I've been using Xen Hypervisor for a > long time. > > I'm curious if anyone else has had this issue. > > I recently upgraded a server from Debian Squeeze to Buster with kernel > 4.19.0-16-amd64 and found that apt/aptitude commands are slow in response. > > For example, 'apt-get update' can take 10 minutes to complete, hanging > up on certain parts of the downloads either at 0% or 90%. This is > something that normally takes a few seconds. > > Even the DomU's suffer the same issue. > > > On another server I have kernel 4.19.0-14-amd64 and it seems to be > running just fine most of the time. I do get some hiccups, but not > nearly as much as the above upgraded server. > > > I've also noticed that writes will sometimes pause for several seconds, > specially when transferring large files. > > > Setup: > > E3-1230 V2 @ 3.30GHz > > 16 GB RAM > > Hard drives are spinning disk. 2 TB drives (EXT4) > > DomUs are using Disk.Img for their disk. > > > -- People use duct tape to fix everything....God used nails. http://www.myerscountry.net --000000000000196bc005c4729b13 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Out of curiosity, how does "top" look when it= 9;s running? Especially things like "wa" (IOWait) and "st&qu= ot; (steal)?

On Thu, Jun 10, 2021 at 5:49 PM TheBearAK <thebearak@gmail.com> wro= te:
First, hello= .=C2=A0 New to the list, but I've been using Xen Hypervisor for a
long time.

I'm curious if anyone else has had this issue.

I recently upgraded a server from Debian Squeeze to Buster with kernel
4.19.0-16-amd64 and found that apt/aptitude commands are slow in response.<= br>
For example, 'apt-get update' can take 10 minutes to complete, hang= ing
up on certain parts of the downloads either at 0% or 90%.=C2=A0=C2=A0=C2=A0= This is
something that normally takes a few seconds.

Even the DomU's suffer the same issue.


On another server I have kernel 4.19.0-14-amd64 and it seems to be
running just fine most of the time.=C2=A0 I do get some hiccups, but not nearly as much as the above upgraded server.


I've also noticed that writes will sometimes pause for several seconds,=
specially when transferring large files.


Setup:

E3-1230 V2 @ 3.30GHz

16 GB RAM

Hard drives are spinning disk.=C2=A0 2 TB drives (EXT4)

DomUs are using Disk.Img for their disk.




--
People use= duct tape to fix everything....God used nails.

http://www.myerscountry.net
--000000000000196bc005c4729b13-- From xen-users-bounces@lists.xenproject.org Fri Jun 11 04:32:47 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 11 Jun 2021 04:32:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.140146.259019 (Exim 4.92) (envelope-from ) id 1lrYpW-00075E-LZ; Fri, 11 Jun 2021 04:31:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 140146.259019; Fri, 11 Jun 2021 04:31:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrYpW-000756-Hp; Fri, 11 Jun 2021 04:31:38 +0000 Received: by outflank-mailman (input) for mailman id 140146; Fri, 11 Jun 2021 04:31:38 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lrYpW-000750-0I for xen-users@lists.xenproject.org; Fri, 11 Jun 2021 04:31:38 +0000 Received: from mail-pg1-x529.google.com (unknown [2607:f8b0:4864:20::529]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ea987694-a876-4f77-89f9-c04180f231f5; Fri, 11 Jun 2021 04:31:36 +0000 (UTC) Received: by mail-pg1-x529.google.com with SMTP id z1so1452681pgj.6 for ; Thu, 10 Jun 2021 21:31:36 -0700 (PDT) Received: from sybil.iarc.uaf.edu (161-68-174-206.gci.net. [206.174.68.161]) by smtp.gmail.com with ESMTPSA id j17sm3733399pff.77.2021.06.10.21.31.34 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jun 2021 21:31:35 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: ea987694-a876-4f77-89f9-c04180f231f5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:references:from:message-id:date:user-agent:mime-version :in-reply-to:content-language; bh=GjHfLqLN/ucjZ+/t1pw/avoX6RLjwEUqGpCOL+vpomY=; b=WBDYa59mjjbJ2LCLI2v/icC9+hDgvkdRpAGjSx1pgGf7BO4Qe88CoLWSkferP8Se3f VMvk4ricOd/5HAyykE9s3tWifHlCjJzpg82CV5lOXphhYNd6DiwzaDJQyIqD+DcRuEsX RoiULkf5iGddrGQYtH+/VBPE/y68EXBVVXim+FNOMz4eSDBE5igw1BFpg5+Z0lIE9w61 DtE1DDBtN1GF6py+4v0E5mqt/im4D8m7J7XmsmYoJ9RdgOwNfE7KHFm9xRZksxaNJTFe rpm6kRouBVx6Ega0BYQHzxBOYrbL113Cxyqqnbd7vAKSsY6Lt1Hy0j1n5yoda3IbopPT U/WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language; bh=GjHfLqLN/ucjZ+/t1pw/avoX6RLjwEUqGpCOL+vpomY=; b=FTO+UeksOfSN2tBspaGyXTMqJGUvivC5Ukt2qSlA7ouQgQ77+xPsx5wu4KJPFDqLQg N5zfauxrMz5/tMLpFjStJ+p/gN1IDWbEazWZAfM1qbyeZmYE82v5+S3Wnnpwq3Vln79h t07VWmUQJFcKrL/RSN5ohzQZb4Ylo2lED9qenzYEuab5xkVIYZckh/ZlYZ3zVqwZyihA vWdwfuBynrlZPRAzoXFKEZvgrsv3qnit2766QxlwRCLUIqjGZ/E3QjQntSD0ggGn66ta KMdYpcY2BYGUYwaM1rpcXQrAIEZTz8sWJfuO9eSyGWlfXp4tUkMTNUhpGnFb9z8pALif Y92g== X-Gm-Message-State: AOAM5336Rbeek6OLSTZCCNlSMYfM7Zv4I9Ozd6NjQBp1YkbM1Lx+ZlBS 8/1wUvKhuMOoEOSSPn/iO7Fn9jhA/lXmXw== X-Google-Smtp-Source: ABdhPJw3ybTZgeK3O9/1CXcmYHhUg/0nQrd7scDpgOrMasEWZjk3dyOB+RZN9fUOqLowgv2H+DC0MQ== X-Received: by 2002:a65:6a0f:: with SMTP id m15mr1712128pgu.253.1623385895475; Thu, 10 Jun 2021 21:31:35 -0700 (PDT) Subject: Re: Slow Apt To: xen-users@lists.xenproject.org References: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> From: TheBearAK Message-ID: <75cd4db6-73ee-ead8-c536-6f654109c612@gmail.com> Date: Thu, 10 Jun 2021 20:31:33 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------82B2155CC5CE92EE65025CD9" Content-Language: en-US This is a multi-part message in MIME format. --------------82B2155CC5CE92EE65025CD9 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Hovers around 10.5 wa and 0.2 to 0.3 in st. Top processes are vifs with a loop4 popping up to the top once in a while along with rcu_sched. I would guess the loop4 is the mounted disk image for the DomU. So, after the 'apt-get update' finished, the wa dropped to 0.4 and st stayed at 0.2 On 6/10/21 4:29 PM, Chris Myers wrote: > Out of curiosity, how does "top" look when it's running? Especially > things like "wa" (IOWait) and "st" (steal)? > > On Thu, Jun 10, 2021 at 5:49 PM TheBearAK > wrote: > > First, hello.  New to the list, but I've been using Xen Hypervisor > for a > long time. > > I'm curious if anyone else has had this issue. > > I recently upgraded a server from Debian Squeeze to Buster with > kernel > 4.19.0-16-amd64 and found that apt/aptitude commands are slow in > response. > > For example, 'apt-get update' can take 10 minutes to complete, > hanging > up on certain parts of the downloads either at 0% or 90%. This is > something that normally takes a few seconds. > > Even the DomU's suffer the same issue. > > > On another server I have kernel 4.19.0-14-amd64 and it seems to be > running just fine most of the time.  I do get some hiccups, but not > nearly as much as the above upgraded server. > > > I've also noticed that writes will sometimes pause for several > seconds, > specially when transferring large files. > > > Setup: > > E3-1230 V2 @ 3.30GHz > > 16 GB RAM > > Hard drives are spinning disk.  2 TB drives (EXT4) > > DomUs are using Disk.Img for their disk. > > > > > -- > People use duct tape to fix everything....God used nails. > > http://www.myerscountry.net --------------82B2155CC5CE92EE65025CD9 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit

Hovers around 10.5 wa and 0.2 to 0.3 in st.

Top processes are vifs with a loop4 popping up to the top once in a while along with rcu_sched.

I would guess the loop4 is the mounted disk image for the DomU.

So, after the 'apt-get update' finished, the wa dropped to 0.4 and st stayed at 0.2


On 6/10/21 4:29 PM, Chris Myers wrote:
Out of curiosity, how does "top" look when it's running? Especially things like "wa" (IOWait) and "st" (steal)?

On Thu, Jun 10, 2021 at 5:49 PM TheBearAK <thebearak@gmail.com> wrote:
First, hello.  New to the list, but I've been using Xen Hypervisor for a
long time.

I'm curious if anyone else has had this issue.

I recently upgraded a server from Debian Squeeze to Buster with kernel
4.19.0-16-amd64 and found that apt/aptitude commands are slow in response.

For example, 'apt-get update' can take 10 minutes to complete, hanging
up on certain parts of the downloads either at 0% or 90%.    This is
something that normally takes a few seconds.

Even the DomU's suffer the same issue.


On another server I have kernel 4.19.0-14-amd64 and it seems to be
running just fine most of the time.  I do get some hiccups, but not
nearly as much as the above upgraded server.


I've also noticed that writes will sometimes pause for several seconds,
specially when transferring large files.


Setup:

E3-1230 V2 @ 3.30GHz

16 GB RAM

Hard drives are spinning disk.  2 TB drives (EXT4)

DomUs are using Disk.Img for their disk.




--
People use duct tape to fix everything....God used nails.

http://www.myerscountry.net
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charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Mailer: WebService/1.1.18368 YMailNorrin Content-Length: 603 Thanks. How about the runX or=C2=A0Kata=C2=A0Containers? On Tuesday, June 8, 2021, 06:32:26 AM GMT+4:30, Bernd Bausch wrote:=20 There is no benefit, since it's not possible. You can run a container on a = VM, but not as a VM. The processes in a container run on the container host, using the host's ke= rnel.=20 A VM has its own kernel. Processes in a VM use the VM's kernel, and don't r= un on the VM's host. On 2021/06/07 8:09 PM, Jason Long wrote: >=C2=A0=C2=A0Hello, > What is the benefit of running a container as a VM? >=20 >=20 > Thank you. >=20 >=20 From xen-users-bounces@lists.xenproject.org Mon Jun 14 21:45:55 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 14 Jun 2021 21:45:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.141800.261820 (Exim 4.92) (envelope-from ) id 1lsuOH-0006nE-UZ; Mon, 14 Jun 2021 21:45:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 141800.261820; Mon, 14 Jun 2021 21:45:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lsuOH-0006n7-RG; Mon, 14 Jun 2021 21:45:05 +0000 Received: by outflank-mailman (input) for mailman id 141800; Mon, 14 Jun 2021 21:45:04 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lsuOG-0006n1-Bd for xen-users@lists.xenproject.org; Mon, 14 Jun 2021 21:45:04 +0000 Received: from mail-pj1-x1034.google.com (unknown [2607:f8b0:4864:20::1034]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c078b6ab-4099-464c-82b6-fb6f88e280dc; Mon, 14 Jun 2021 21:45:03 +0000 (UTC) Received: by mail-pj1-x1034.google.com with SMTP id fy24-20020a17090b0218b029016c5a59021fso500397pjb.0 for ; Mon, 14 Jun 2021 14:45:03 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: c078b6ab-4099-464c-82b6-fb6f88e280dc DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=rQ9rCq+RzXocqY2V6IlXe5tCt44eZpkEvbGWXvZzJ2U=; b=WD0mC9qFFPUz47zO34JNDSVP0gM8UM2TcbClb+8RKC4kuVSZEXTLfytIWc6NMO6rVc JukNZEruvJYyCbd9m/6+0OQlfta6x5TBOHGVnMbVk3R2WDQ87zYx/QOclxHf+mRJl4tY NauPK8OoQUUrzO0OcoK7TJUY7n0PQzNI18MfDYDglTo0HcA8CIj2IQycCwSIyZ5uJyQM JhwanjU/YdC6AoO7T3Q4jOvxy+Ob6nV/YK3K6TwS6r7gXCWANVZ15bC6mjmLQtMEADHG ZavnYzTn1caBShxW8Wixka0JNLNc41USpgVbtBsmoGmD38XMNa59pCUBpzeaMVpcuO+L lx7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rQ9rCq+RzXocqY2V6IlXe5tCt44eZpkEvbGWXvZzJ2U=; b=LsTLujxofaDgeHl7WVWh116IWWgKKz9YNkYImyWTqWWtZmX6l2arCmaHnUOScZFhKO Qql4/CfBl+L8ZLimsaCyJhtOaU/dHXaST8iiagl72eTFJtNkwYKdlyWtg5w3KrUj/dcK p/nec81qBaLpSKbnvJTM3XWDoJlTadKG3m2qeHxAc25iz/kPYK7XzUyeH8IKEzmY57DT 1s6tIOdEKqEEiRcPEtDTAaFs/73e57Txf7OkLZmLAGsYnW3EIYYHhfpKG11h0Qh4/RJH vJrilnsWo0QUzrMDX+RoCWB/Ew8jg9MpImkXWplst8f6iEYcImADzYX4t8UEn6kRwI8P Z0aw== X-Gm-Message-State: AOAM532QmyOcJlKWtfSO1uUQOeYVnEeUJCqOlrmuZlAMhTVUAUN7SHJF LyMzKqA6s9QW7o+G10jqHrJ9j5uCXrbJlhj0bWw= X-Google-Smtp-Source: ABdhPJwoE4dTz5rm3NHS3QwneLv/Nru15oUgHGFDTzudkYszYmEh1bUzxDQTgJLxi3YaPDq3mb2qKNfCvDL8qnpcgtY= X-Received: by 2002:a17:90a:f681:: with SMTP id cl1mr961190pjb.233.1623707102251; Mon, 14 Jun 2021 14:45:02 -0700 (PDT) MIME-Version: 1.0 References: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> <75cd4db6-73ee-ead8-c536-6f654109c612@gmail.com> In-Reply-To: <75cd4db6-73ee-ead8-c536-6f654109c612@gmail.com> From: Chris Myers Date: Mon, 14 Jun 2021 16:44:51 -0500 Message-ID: Subject: Re: Slow Apt To: TheBearAK Cc: xen-users@lists.xenproject.org Content-Type: multipart/alternative; boundary="0000000000000c904405c4c0c578" --0000000000000c904405c4c0c578 Content-Type: text/plain; charset="UTF-8" Interesting...a wait of 10% isn't great but isn't horrible either, I wouldn't see that as a cause of delays like that. (I recently had issues with a "new" board that had a lot of "steal" even when basically doing nothing, so I was curious if you were running into that too.) Other than "apt" commands, how do other network-based tasks look? I upgraded from Stretch to Buster a year or so ago and haven't run into this so far. Other than apt commands, how does everything look? On Thu, Jun 10, 2021 at 11:32 PM TheBearAK wrote: > Hovers around 10.5 wa and 0.2 to 0.3 in st. > > Top processes are vifs with a loop4 popping up to the top once in a while > along with rcu_sched. > > I would guess the loop4 is the mounted disk image for the DomU. > So, after the 'apt-get update' finished, the wa dropped to 0.4 and st > stayed at 0.2 > > > On 6/10/21 4:29 PM, Chris Myers wrote: > > Out of curiosity, how does "top" look when it's running? Especially things > like "wa" (IOWait) and "st" (steal)? > > On Thu, Jun 10, 2021 at 5:49 PM TheBearAK wrote: > >> First, hello. New to the list, but I've been using Xen Hypervisor for a >> long time. >> >> I'm curious if anyone else has had this issue. >> >> I recently upgraded a server from Debian Squeeze to Buster with kernel >> 4.19.0-16-amd64 and found that apt/aptitude commands are slow in response. >> >> For example, 'apt-get update' can take 10 minutes to complete, hanging >> up on certain parts of the downloads either at 0% or 90%. This is >> something that normally takes a few seconds. >> >> Even the DomU's suffer the same issue. >> >> >> On another server I have kernel 4.19.0-14-amd64 and it seems to be >> running just fine most of the time. I do get some hiccups, but not >> nearly as much as the above upgraded server. >> >> >> I've also noticed that writes will sometimes pause for several seconds, >> specially when transferring large files. >> >> >> Setup: >> >> E3-1230 V2 @ 3.30GHz >> >> 16 GB RAM >> >> Hard drives are spinning disk. 2 TB drives (EXT4) >> >> DomUs are using Disk.Img for their disk. >> >> >> > > -- > People use duct tape to fix everything....God used nails. > > http://www.myerscountry.net > > -- People use duct tape to fix everything....God used nails. http://www.myerscountry.net --0000000000000c904405c4c0c578 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Interesting...a wait of 10% isn't great but isn't horrible either, I wouldn't = see that=20 as a cause of delays like that. (I recently had issues with a "new&quo= t;=20 board that had a lot of "steal" even when basically doing nothing= , so I=20 was curious if you were running into that too.)

Other than "apt" commands, how do other network-based = tasks look?

<= div style=3D"font-family:Tahoma,Geneva,sans-serif;font-size:11pt;color:rgb(= 23,78,134);background-color:rgb(255,255,255)">I upgraded from Stretch to Bu= ster a year or so ago and haven't run into this so far.

Other than apt commands, how does everything look?



= On Thu, Jun 10, 2021 at 11:32 PM TheBearAK <thebearak@gmail.com> wrote:
=20 =20 =20

Hovers around 10.5 wa and 0.2 to 0.3 in st.

Top processes are vifs with a loop4 popping up to the top once in a while along with rcu_sched.

I would guess the loop4 is the mounted disk image for the DomU.

So, after the 'apt-get update' finished, the wa dropped to 0.4 = and st stayed at 0.2


On 6/10/21 4:29 PM, Chris Myers wrote:
=20
Out of curiosity, how does "top" look when= it's running? Especially things like "wa" (IOWait) and "s= t" (steal)?

On Thu, Jun 10, 2021 at 5:49 PM TheBearAK <thebearak@gmail.com> wrote:
First, hello.=C2=A0 New to the list, but I've been using Xen Hypervi= sor for a
long time.

I'm curious if anyone else has had this issue.

I recently upgraded a server from Debian Squeeze to Buster with kernel
4.19.0-16-amd64 and found that apt/aptitude commands are slow in response.

For example, 'apt-get update' can take 10 minutes to comp= lete, hanging
up on certain parts of the downloads either at 0% or 90%.=C2=A0= =C2=A0=C2=A0 This is
something that normally takes a few seconds.

Even the DomU's suffer the same issue.


On another server I have kernel 4.19.0-14-amd64 and it seems to be
running just fine most of the time.=C2=A0 I do get some hiccups, but not
nearly as much as the above upgraded server.


I've also noticed that writes will sometimes pause for severa= l seconds,
specially when transferring large files.


Setup:

E3-1230 V2 @ 3.30GHz

16 GB RAM

Hard drives are spinning disk.=C2=A0 2 TB drives (EXT4)

DomUs are using Disk.Img for their disk.




--
People use duct tape to fix everything....God used nails.

http://ww= w.myerscountry.net


--
People use duct tape to fix everything....God used nails.
http://www.= myerscountry.net
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[24.237.121.29]) by smtp.gmail.com with ESMTPSA id y34sm13210530pfa.181.2021.06.14.15.52.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jun 2021 15:52:05 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: ed9ec066-7f07-4fef-a1a4-6d56279903df DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language; bh=ThEcdrMHkK/RtyFk9qE5zNDXIfb9clNLW9EE5/5k/T4=; b=rpPXTW2KMYo+Us84GLiQizICJZ0DL3vzBEtTe3lSy8izaNcIBOV3TOa99daunIbxlA w1AR/HkIByrb6KZqmbCUrBKSsGUM5JLe27sUyaoo6U4ouO63tttMkYl65jixdtoIRGaO eMV26KMo9NowxF8RNSIcHV9MlI/xNmNfcND8oKVIbQ19EIl1ZFDi7Rcset99DyuAoMYL ydt8y4Id9rIi+c5Uym7gA+zYsfTxB1YvWbWECBCAsCto6a2YXittbz+7uh533Lc05W+S C8fZ8nUHRK43+KrAtH1kEdeN9MaJFcSgLOPkL5Stmo2G85BUDKlyOQM40M7+SLf1UfrD PNRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language; bh=ThEcdrMHkK/RtyFk9qE5zNDXIfb9clNLW9EE5/5k/T4=; b=eaC9wdeFy6E5Zi4nyCAbEU2GV6l9Ew1wf72iYFjP1OMOFiIZRtQMoGWECC7vQYVUM2 IqoQ0oLhHXK9Iem30lcLQt7LOjnB+600V0h3nkdoE8Pueokl7fUr4qFCPQJcgq4WUC4t L2XUSmAMDaxAdePSYMuhxsFK85Z5HHicmHM9qSe2uBbsB73F2s8Nysbmm3gWYffHyvZi 3iR0WihpOvGGfPr9qolDmYYxSGdkyD/O2d6fM+MZooSbfo6IlBC917CkTZcZzeFw/aMi 3zMeWlFinXdp5ET2ZLleGppr8cTRQKNg4MgppP79w7ljBvBv1JQ9Ks+M1eNY1ReBpA6k bK5w== X-Gm-Message-State: AOAM531B6jHxQ7Z9Rq2PSP660GqlAhPRp9QrSLCE/ZW5dY2YHUNwjb3e n/bCf7zw9QZ+ayHybyh8JwjVe7DoTfs= X-Google-Smtp-Source: ABdhPJznXACb2EEkM6QxEFN3bKeb2ujzrLjPOTEBdxvgtOHmMJD9m2CaPovyC6T627r+Mtsj0Eximw== X-Received: by 2002:a17:90a:4e4a:: with SMTP id t10mr21713143pjl.173.1623711126550; Mon, 14 Jun 2021 15:52:06 -0700 (PDT) Subject: Re: Slow Apt To: Chris Myers Cc: xen-users@lists.xenproject.org References: <1a639af0-babe-8072-111f-b5c0a17220c5@gmail.com> <75cd4db6-73ee-ead8-c536-6f654109c612@gmail.com> From: TheBearAK Message-ID: Date: Mon, 14 Jun 2021 14:52:03 -0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------F0219303BACDF6DBE7B409F0" Content-Language: en-US This is a multi-part message in MIME format. --------------F0219303BACDF6DBE7B409F0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Other networking is mostly perfect.   Once in a while I'll get a spot where it is uploading or downloading and it pauses for a sec or two.   Other than apt, everything seems to run normal speed. I do have one DomU that runs fast except when it serves web pages, but I think that is a different issue.  The web pages are being built from a database and I think the database performance is slow.   Its working, so I put that on the back-burner for now. Only 3 DomU's running on this server and they are <1% busy at any given time. I've seen this happen at least 3 other times with Buster and Apt on Xen. On 6/14/21 1:44 PM, Chris Myers wrote: > Interesting...a wait of 10% isn't great but isn't horrible either, I > wouldn't see that as a cause of delays like that. (I recently had > issues with a "new" board that had a lot of "steal" even when > basically doing nothing, so I was curious if you were running into > that too.) > > Other than "apt" commands, how do other network-based tasks look? > > I upgraded from Stretch to Buster a year or so ago and haven't run > into this so far. > > Other than apt commands, how does everything look? > > > > On Thu, Jun 10, 2021 at 11:32 PM TheBearAK > wrote: > > Hovers around 10.5 wa and 0.2 to 0.3 in st. > > Top processes are vifs with a loop4 popping up to the top once in > a while along with rcu_sched. > > I would guess the loop4 is the mounted disk image for the DomU. > > So, after the 'apt-get update' finished, the wa dropped to 0.4 and > st stayed at 0.2 > > > On 6/10/21 4:29 PM, Chris Myers wrote: >> Out of curiosity, how does "top" look when it's running? >> Especially things like "wa" (IOWait) and "st" (steal)? >> >> On Thu, Jun 10, 2021 at 5:49 PM TheBearAK > > wrote: >> >> First, hello.  New to the list, but I've been using Xen >> Hypervisor for a >> long time. >> >> I'm curious if anyone else has had this issue. >> >> I recently upgraded a server from Debian Squeeze to Buster >> with kernel >> 4.19.0-16-amd64 and found that apt/aptitude commands are slow >> in response. >> >> For example, 'apt-get update' can take 10 minutes to >> complete, hanging >> up on certain parts of the downloads either at 0% or 90%.    >> This is >> something that normally takes a few seconds. >> >> Even the DomU's suffer the same issue. >> >> >> On another server I have kernel 4.19.0-14-amd64 and it seems >> to be >> running just fine most of the time.  I do get some hiccups, >> but not >> nearly as much as the above upgraded server. >> >> >> I've also noticed that writes will sometimes pause for >> several seconds, >> specially when transferring large files. >> >> >> Setup: >> >> E3-1230 V2 @ 3.30GHz >> >> 16 GB RAM >> >> Hard drives are spinning disk.  2 TB drives (EXT4) >> >> DomUs are using Disk.Img for their disk. >> >> >> >> >> -- >> People use duct tape to fix everything....God used nails. >> >> http://www.myerscountry.net > > > > -- > People use duct tape to fix everything....God used nails. > > http://www.myerscountry.net --------------F0219303BACDF6DBE7B409F0 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit

Other networking is mostly perfect.   Once in a while I'll get a spot where it is uploading or downloading and it pauses for a sec or two.   Other than apt, everything seems to run normal speed.

I do have one DomU that runs fast except when it serves web pages, but I think that is a different issue.  The web pages are being built from a database and I think the database performance is slow.   Its working, so I put that on the back-burner for now.

Only 3 DomU's running on this server and they are <1% busy at any given time.


I've seen this happen at least 3 other times with Buster and Apt on Xen.





On 6/14/21 1:44 PM, Chris Myers wrote:
Interesting...a wait of 10% isn't great but isn't horrible either, I wouldn't see that as a cause of delays like that. (I recently had issues with a "new" board that had a lot of "steal" even when basically doing nothing, so I was curious if you were running into that too.)

Other than "apt" commands, how do other network-based tasks look?

I upgraded from Stretch to Buster a year or so ago and haven't run into this so far.

Other than apt commands, how does everything look?



On Thu, Jun 10, 2021 at 11:32 PM TheBearAK <thebearak@gmail.com> wrote:

Hovers around 10.5 wa and 0.2 to 0.3 in st.

Top processes are vifs with a loop4 popping up to the top once in a while along with rcu_sched.

I would guess the loop4 is the mounted disk image for the DomU.

So, after the 'apt-get update' finished, the wa dropped to 0.4 and st stayed at 0.2


On 6/10/21 4:29 PM, Chris Myers wrote:
Out of curiosity, how does "top" look when it's running? Especially things like "wa" (IOWait) and "st" (steal)?

On Thu, Jun 10, 2021 at 5:49 PM TheBearAK <thebearak@gmail.com> wrote:
First, hello.  New to the list, but I've been using Xen Hypervisor for a
long time.

I'm curious if anyone else has had this issue.

I recently upgraded a server from Debian Squeeze to Buster with kernel
4.19.0-16-amd64 and found that apt/aptitude commands are slow in response.

For example, 'apt-get update' can take 10 minutes to complete, hanging
up on certain parts of the downloads either at 0% or 90%.    This is
something that normally takes a few seconds.

Even the DomU's suffer the same issue.


On another server I have kernel 4.19.0-14-amd64 and it seems to be
running just fine most of the time.  I do get some hiccups, but not
nearly as much as the above upgraded server.


I've also noticed that writes will sometimes pause for several seconds,
specially when transferring large files.


Setup:

E3-1230 V2 @ 3.30GHz

16 GB RAM

Hard drives are spinning disk.  2 TB drives (EXT4)

DomUs are using Disk.Img for their disk.




--
People use duct tape to fix everything....God used nails.

http://www.myerscountry.net


--
People use duct tape to fix everything....God used nails.

http://www.myerscountry.net
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boundary="_000_VI1PR05MB44303184209DF3F6215FFF3E89309VI1PR05MB4430eurp_" MIME-Version: 1.0 X-OriginatorOrg: evoleotech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR05MB4430.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e79d841f-8d9b-4280-b4b9-08d9301a7f0f X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jun 2021 16:27:40.7984 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 34ebafdc-9323-4bfe-8f24-6bb9f135b0a9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: al8URlGVvOXh6paBTPNlRQmkVg3KVdbFMtJChzDn1ukxRNVHIxAhvRw1W2Lp1sL9YFnd2dNltzhK9DWI/e3klUKqKURd5HUVGTQMt4GsCqFDfUfcDq2zyOT4CpTN/Y8A X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0501MB2415 --_000_VI1PR05MB44303184209DF3F6215FFF3E89309VI1PR05MB4430eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Stefano, Is it possible to boot XEN from QSPI? Is there an image builder script alre= ady available to generate boot.scr? Please let me know. Thanks and Best Regards, Prem ________________________________ From: Xen-users on behalf of Prem = Harikrishnan Sent: Tuesday, June 1, 2021 18:07 To: Mubin Usman Sayyed ; Stefano Stabellini Cc: xen-users@lists.xenproject.org ; Jovita= Castelino Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit Hi Stefano and Mubin, Thank you very much for helping me setup up FreeRTOS and baremetal guests, = everything works as expected and I also get expected performance in both ba= remetal and hypervisor guests. Thank you again for your prompt support duri= ng the past few weeks. Best Regrards, Prem ________________________________ From: Mubin Usman Sayyed Sent: Tuesday, June 1, 2021 05:38 To: Prem Harikrishnan ; Stefano Stabellin= i Cc: xen-users@lists.xenproject.org ; Jovita= Castelino Subject: RE: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit In case of FreeRTOS, you need to use APIs from FreeRTOS port for interrupt= handling (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp= /freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). Ple= ase make sure that you are taking care of that in DMA interrupt example . Thanks, Mubin From: Prem Harikrishnan Sent: Tuesday, June 1, 2021 2:48 AM To: Stefano Stabellini Cc: xen-users@lists.xenproject.org; Jovita Castelino ; = Mubin Usman Sayyed Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit Hi Stefano and Mubin, Thank you very much for your replies. @Stefano Stabellini Sorry to bother y= ou again, and thank you for pointing this out, the TTC0 is by default enabl= ed for FreeRTOS to generate ticks, although this says only for R5 core, i w= ould have never figured this out. As soon as I added the irqs and iomem and= gave a xen passthrough in the xen.dtsi as you have suggested, FreeRTOS gue= st started working for other peripherals except for my DMA (FreeRTOS guest = does not work with interrupt and DMA). I can see my DMA is enabled because i have LEDs configured to blink for eve= ry interrupt I get from the PL. I don't see my interrupts being processed, = but when I destroy the guest, I get this output periodically when an interr= upt occurs. (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR= 1 0x00000e80, GFSYNR2 0x00000000 >From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/= A/pages/18842066/Xen+and+PL+Masters Xen and PL Masters - Xilinx Wiki - Confluence 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of = PL masters must be added to the Linux Dom0 device tree. Automated device tr= ee generation does not generate the stream IDs for the PL masters so that t= he user must add them into the device tree manually. xilinx-wiki.atlassian.net The fault indicates an unidentified stream ID has been received by the SMMU= as shown in the GFSR register. The GFSYNR1 register contains the stream ID= that was unidentified. A stream ID of 0xE80 was unidentified in the above = fault. But I think i have already added that in my smmu and iommu in xen.dtsi beca= use my baremetal application works well as expected. I have attached my xen= .dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). What could I be missing here? Do I have to enable the ttc0 in the device tr= ee? Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: = 99990 KHz mean when XEN boots up? Thanks, I look forward for your reply. Best Regards, Prem ________________________________ From: Stefano Stabellini > Sent: Friday, May 28, 2021 20:43 To: Prem Harikrishnan > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com >; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit >From the gpa address, it looks like FreeRTOS is trying to access the TTC timer? If you look at device tree, the corresponding node is timer@ff110000. If FreeRTOS is configured to access the TTC timer, then you need to assign it to it. Did you assign the TTC timer to the FreeRTOS domU by any chance? You can do that by adding: irqs =3D [ 68, 69, 70 ] iomem =3D [ "0xff110,1" ] On Fri, 28 May 2021, Prem Harikrishnan wrote: > Hi Stefano, > Thanks for your reply. I am pretty sure I followed the steps you mentione= d below to run the FreeRTOS hello world example. I already added > printfs and i can see XEN cannot start the scheduler and i get the follow= ing out put on XEN. > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 memfl= ags=3D0xc0 (0 of 64) > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0 > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0xff= 11000c gpa=3D0x000000ff11000c > > > I also see that according to this article > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as= -a-Xen-Virtual-Machine/ba-p/947030 > [52662iFAD1733707609204?v=3Dv2] > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks Wh= at is FreeRTOS? The FreeRTOS kernel is a market leading real-time > operating system for embedded systems. As embedded applications grow in c= omplexity, there is a growing need for a lightweight kernel > capable of task scheduling... > forums.xilinx.com > FreeRTOS does not run out of the box for XEN, although the article is 2 y= ears old, I am not sure if there are any updates on this after > that. Can you please confirm? > > Thanks and Best Regards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 02:51 > To: Prem Harikrishnan > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; JOVITAC@xilinx.com > >; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > +Mubin > > > Hi Prem, > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps: > > - source settings64.sh from Vitis builds > - xsct > - set WORKSPACE . > - setws -switch $WORKSPACE > - app create -name freertos-hello-world -template {FreeRTOS Hello World} = -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > - bsp config stdin psu_uart_1 > - bsp config stdout psu_uart_1 > - bsp config hypervisor_guest true > - Go to application source path and modify the linker script start addres= s to 0x40000000, > - app build -name freertos-hello-world > - Run command to generate BIN file from executable "aarch64-linux-gnu-obj= copy -O binary --gap-fill 0 BOOT.BIN" > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > might be able to provide additional info. > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Sorry to bother you again. > > I am currently trying to run my custom IP which sends periodic dma inte= rrupts to the PS with cache coloring enabled. I have now compiled > my > > guest running with FreeRTOS and it generates a trap. > > Petalinux and VITIS IDE Version is 2020.2. > > > > Please find the log attached. After the trap occurs, for every interrup= t XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault: > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config fro= m apu_freertos.cfg > > (XEN) Dom1 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D1 mem= flags=3D0xc0 (0 of 64) > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache=3D0 > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > (XEN) sched_null.c:344: 1 <-- d1v0 > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gva=3D0x= ff11000c gpa=3D0x000000ff11000c > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > The same application works as expected without FreeRTOS, i.e as a barem= etal guest. I look forward for your comment on this. > > > > Although i see performance degradation, normally i can measure delta ti= me for each interrupt configured to 1ms (without XEN), with XEN > for > > the same measurement shows 16 ms for each interval (but the performance= is not a priority for now). > > Thanks and Best Regards, > > Prem > > > >________________________________________________________________________= __________________________________________________________________ > _ > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 20:09 > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini >; xen-users@lists.xenproject.org >; > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL = masters in ZCU102 dev kit > > Great to hear! Thank you for reporting back. > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > Dear Stefano, > > > Thank you very much for your guidance and support. I finally fixed th= e issue. I made an error in base memory address like you pointed > > out. > > > I actually modified the base address correctly to 0x40000000 but the = default C code had an additional offset of 0x1100000 , and the > DomU > > > memory allocated was only 8MB. I either had to change the offset or a= llocate more memory to the DomU guest which i missed until you > > pointed > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and th= e SMID required is 0xE80. > > > > > > Thanks again i was able get my custom IP also working as an AXI maste= r from PL. > > > > > > Best Regards, > > > Prem > > > > >>_______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 02:35 > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; St= efano > > > Stabellini >; x= en-users@lists.xenproject.org >; fnuv@xil= inx.com > >; > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for P= L masters in ZCU102 dev kit > > > Your configuration looks correct as far as I can tell. > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > block. You don't need device_tree because your baremetal application = is > > > not going to read it, but it is not going to cause any issues either. > > > > > > When you say "the execution does not complete the loop at line 244", = it > > > means that you see the execution entering the loop and then never > > > leaving? Like an infinite loop? > > > > > > If so, then I imagine the issue could be that the application is > > > crashing when trying to access TxBufferPtr, which is pointing to > > > TX_BUFFER_BASE, which is: > > > > > > > > > #ifndef DDR_BASE_ADDR > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > DEFAULT SET TO 0x01000000 > > > #define MEM_BASE_ADDR 0x01000000 > > > #else > > > #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) > > > #endif > > > > > > #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > Hi Stefano, > > > > Thanks again for your reply and your suggestion. I did try to repl= ace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRange(works > > only > > > > in EL3), I added printfs to debug, i can see that the execution doe= s not complete the loop at line 244 > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPL= ib/drivers/axidma/examples/xaxidma_example_simple_poll.c and > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bo= otlog.txt. > > > > I am still unable to find out why?? > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is corre= ct? and do i need dtdev and device_tree in my guest config file > when > > > it > > > > is already added to xen.dtsi? > > > > > > > > Best Regards, > > > > Prem > > > > > > > > > >>>______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini >; Brian Woods >; Julien Grall >; = Stefano > > > > Stabellini >;= xen-users@lists.xenproject.org >; fnuv@x= ilinx.com > > >; > > > > edgari@xilinx.com >; bwoods288@gmail.com >; Renato Costa Amorim >; > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for= PL masters in ZCU102 dev kit > > > > Hi Prem, > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > deprecated set/way instructions that are known to cause problems in > > > > virtualized environments. > > > > > > > > More recent implementations use the "dc civac" intruction that shou= ldn't > > > > have any issues. > > > > > > > > Can you double-check that you are calling the 64-bit version implem= ented > > > > by CIVAC? > > > > > >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3= 577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L4 > 1 > > 4 > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks for your reply. Yes the axidma application is a baremetal = application from the xilinx vitis ide example. > > > > > Also yes, I have already run hello world as DomU guest, with UART= 1. > > > > > > > > > > I am using the simple mode using polling and not interrupts(they = are disabled in the c code), which is Why I didn't include in the > > > guest > > > > > config file. This works well when I compile it normally (as EL3).= When compiled as hypervisor guest, the execution stops before the > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcess= orIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c > > > > > > > > > > I found the SATA example similar to my use case, also using DMA a= nd SMMU. I just used it as a reference to create my pl.dtb to pass > > > > through > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > Thanks and Best Regards, > > > > > Prem > > > > > > > > > > Get Outlook for Android > > > > > > >>>>_____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > To: Prem Harikrishnan > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabel= lini; xen-users@lists.xenproject.org= ; fnuv@xilinx.com; > > > > edgari@xilinx.com; > > > > > bwoods288@gmail.com; Renato Costa Amo= rim; JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.= bin" is > > > > > a baremetal application? Can you run it successfully, just printi= ng > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on = the > > > > > Vivado configuration and SMID calculation. But I noticed that you= only > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven= 't > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dts= i, it > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I do= n't > > > > > follow: I cannot see any SATA controller assignment in your > > > > > configuration. > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > Thank you very much for your replies. > > > > > > Hi Brian and Stefano, Can you please help me with the following= questions? > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when= i added my AXI DMA now running on simple polling mode(previously > i > > > > tried > > > > > it > > > > > > with Scatter Gather mode), Run Automation automatically generat= ed, 1 AXI Interconnect and 1 smart connect. Since there is only 1 > > > master > > > > > and > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for th= e stream IDs. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/= Xen+and+PL+Masters According to this link section 6.5 I have > > manually > > > > tied > > > > > > of AxPROT bits to value of 0x2 to create non secure transaction= s. Can you please confirm that my Vivado configuration is correct? > I > > > can > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated f= rom petalinux and system.dtsi also generated after manually adding > > > > > xen.dtsi. > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561= /Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > this > > > > SATA > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.= cfg. I could really use your help to identify what is missing in > my > > > xen > > > > > > configuration. > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > >>>>>____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Brian Woods > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > To: Stefano Stabellini > > > > > > > Cc: Julien Grall >; Prem = Harikrishnan >; Stefano Stabellini > > >; > > > > > > xen-users@lists.xenproject.org >; brian.woods@xilinx.com >; fnuv@xilinx.com > > > > > > >; edgari@xilinx.com >; bwoo= ds288@gmail.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough= for PL masters in ZCU102 dev kit > > > > > > Prem, > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have = been away > > > > > > from my computer. In the Zynq SOCs this is how the SMMU IDs in= PL are > > > > > > calculated: > > > > > > > > > > > > 14-10: TBU bits > > > > > > 9-6: Master ID bits > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085= -zynq-ultrascale-trm.pdf > > > > > > To look up the TBU value, see UG1085 and look for the "System M= asters" > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List= " table > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in= PL. > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.= There > > > > > > are work arounds. Here's a couple of examples (with example nu= mbers): > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > -> PS slave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0000 (both share) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0000 (both share) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS s= lave port 0 > > > > > > -> PS s= lave port 1 > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0001 (master #1) > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 000= 0002 (master #2) > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 000= 0002 (master #2) > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be function= ally > > > > > > replaced with "AXI Interconnect" to my knowledge. So the AXI I= D bits are > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_ar= chitecture_specification.pdf > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions= . > > > > > > > > > > > > Brian > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wr= ote: > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 = development board > > > > > > > > > and i am trying to create a barematal application that us= es the AXI DMA on > > > > > > > > > the programmable logic, using the scatter gather example = from the xilinx > > > > > > > > > repository. This works perfectly well for the baremetal a= pplication. The > > > > > > > > > diagram below represents the information flow. The AXI DM= A and the AXI data > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is= out of the box IP > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSE= R) which means the > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, = in future this will > > > > > > > > > be replaced by a custom IP with cache colouring enabled. = I want to pass > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocate= d to Dom-0) to > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate= my linux, xen > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > From what i understand from the xilinx tutorials Xen+and= +PL+Masters > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the= correct address > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu prop= erty for my AXI DMA > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2= 020.2 releases > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > * 1:1 memory mappings for Xen virtual machines, enabl= ing device > > > > > > > > > assignments without SMMU > > > > > > > > > * > > > > > > > > > Static assignment of PL blocks, including bus-maste= ring blocks, to > > > > > > > > > Xen virtual machines > > > > > > > > > * Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by= Xilinx. So I would > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --_000_VI1PR05MB44303184209DF3F6215FFF3E89309VI1PR05MB4430eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Stefano,

Is it possible to boot XEN from QSPI? Is there an image builder script alre= ady available to generate boot.scr? Please let me know.
Thanks and Best Regards,
Prem

From: Xen-users <xen-use= rs-bounces@lists.xenproject.org> on behalf of Prem Harikrishnan <prem= .harikrishnan@evoleotech.com>
Sent: Tuesday, June 1, 2021 18:07
To: Mubin Usman Sayyed <MUBINUSM@xilinx.com>; Stefano Stabelli= ni <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org <xen-users@lists.xenproject.or= g>; Jovita Castelino <JOVITAC@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit
 
Hi Stefano and Mubin,

Thank you very much for helping me setup up FreeRTOS and baremetal guests, = everything works as expected and I also get expected performance in both ba= remetal and hypervisor guests. Thank you again for your prompt support duri= ng the past few weeks.

Best Regrards,
Prem
From: Mubin Usman Sayyed = <MUBINUSM@xilinx.com>
Sent: Tuesday, June 1, 2021 05:38
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; Stef= ano Stabellini <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org <xen-users@lists.xenproject.or= g>; Jovita Castelino <JOVITAC@xilinx.com>
Subject: RE: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit
 

In case of FreeRTOS,  you need to use APIs = from FreeRTOS port for interrupt handling  (https://github.com/Xilinx/embeddedsw/blob/ma= ster/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192= and line 194). Please make sure that you are taking care of that in DMA in= terrupt example .

 

Thanks,

Mubin

 

From: Prem Harikrishnan <prem.harikris= hnan@evoleotech.com>
Sent: Tuesday, June 1, 2021 2:48 AM
To: Stefano Stabellini <stefanos@xilinx.com>
Cc: xen-users@lists.xenproject.org; Jovita Castelino <JOVITAC@xil= inx.com>; Mubin Usman Sayyed <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

&n= bsp;

Hi= Stefano and Mubin,

Th= ank you very much for your replies.

@St= efano Stabellini Sorry to bother you again, and thank you for pointing this out, the TTC0 is by default enabled for Fr= eeRTOS to generate ticks, although this says only for R5 core, i would have= never figured this out. As soon as I added the irqs and iomem and gave a x= en passthrough in the xen.dtsi as you have suggested, FreeRTOS guest started working for other peripherals e= xcept for my DMA (FreeRTOS guest does not work with interrupt and DMA).

&n= bsp;

I = can see my DMA is enabled because i have LEDs configured to blink for every= interrupt I get from the PL. I don't see my interrupts being processed, bu= t when I destroy the guest, I get this output periodically when an interrupt occurs.

&n= bsp;

(X= EN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(X= EN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

(X= EN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x000000= 02, GFSYNR1 0x00000e80, GFSYNR2 0x00000000

&n= bsp;

3.4 Stream IDs in the Device T= ree. For Xen based systems the stream IDs of PL masters must be added to th= e Linux Dom0 device tree. Automated device tree generation does not generate the stream IDs for the PL masters so that the= user must add them into the device tree manually.

xilinx-wiki.atlassian.net

The fault indicates = an unidentified stream ID has been received by the SMMU as shown in the GFS= R register. The GFSYNR1 register contains the stream ID that was unidentifi= ed. A stream ID of 0xE80 was unidentified in the above fault.

&n= bsp;

Bu= t I think i have already added that in my smmu and iommu in xen.dtsi becaus= e my baremetal application works well as expected. I have attached my xen.d= tsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working).

Wh= at could I be missing here? Do I have to enable the ttc0 in the device tree= ?

Al= so what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq: 99= 990 KHz mean when XEN boots up?

Th= anks, I look forward for your reply.

&n= bsp;

Be= st Regards,

Pr= em

&n= bsp;

&n= bsp;

From:<= span style=3D"color:black"> Stefano Stabellini <stefano.stabellini@xilinx.com>
Sent: Friday, May 28, 2021 20:43
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit

 

From the gpa address, it looks like FreeRTOS is = trying to access the TTC
timer? If you look at device tree, the corresponding node is
timer@ff110000.

If FreeRTOS is configured to access the TTC timer, then you need to
assign it to it. Did you assign the TTC timer to the FreeRTOS domU by
any chance?

You can do that by adding:

irqs =3D [ 68, 69, 70 ]
iomem =3D [ "0xff110,1" ]


On Fri, 28 May 2021, Prem Harikrishnan wrote:
> Hi Stefano,
> Thanks for your reply. I am pretty sure I followed the steps you menti= oned below to run the FreeRTOS hello world example. I already added
> printfs and i can see XEN cannot start the scheduler and i get the fol= lowing out put on XEN.
>
> Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ]
> (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 me= mflags=3D0xc0 (0 of 64)
> (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > (XEN) sched_null.c:344: 1 <-- d2v0
> (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0= xff11000c gpa=3D0x000000ff11000c
>
>
> I also see that according to this article
> https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a= -Xen-Virtual-Machine/ba-p/947030
> [52662iFAD1733707609204?v=3Dv2]
> Partner: FreeRTOS as a Xen Virtual Machine - Community Forums
> Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks= What is FreeRTOS? The FreeRTOS kernel is a market leading real-time
> operating system for embedded systems. As embedded applications grow i= n complexity, there is a growing need for a lightweight kernel
> capable of task scheduling...
> forums.xilinx.com
> FreeRTOS does not run out of the box for XEN, although the article is = 2 years old, I am not sure if there are any updates on this after
> that. Can you please confirm?
>
> Thanks and Best Regards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> Sent: Friday, May 28, 2021 02:51
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; JOVITAC@xilinx.com
> <JOVITAC@xilinx.com>; = MUBINUSM@xilinx.com <MUBINUSM= @xilinx.com>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
> +Mubin
>
>
> Hi Prem,
>
> Did you make sure to build FreeRTOS as "hypervisor guest"? I= think
> FreeRTOS is built to run at EL3 by default so if that is not changed > there are errors when run on any hypervisor. It is possible to build > FreeRTOS to run on Xen but it requires a couple of manual steps:
>
> - source settings64.sh from Vitis builds
> - xsct
> - set WORKSPACE .
> - setws -switch $WORKSPACE
> - app create -name freertos-hello-world -template {FreeRTOS Hello Worl= d} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx
> - bsp config stdin psu_uart_1
> - bsp config stdout psu_uart_1
> - bsp config hypervisor_guest true
> - Go to application source path and modify the linker script start add= ress to 0x40000000,
> - app build -name freertos-hello-world
> - Run command to generate BIN file from executable "aarch64-linux= -gnu-objcopy -O binary --gap-fill 0  <elf path> BOOT.BIN" >
> The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed,<= br> > might be able to provide additional info.
>
>
>
> On Thu, 27 May 2021, Prem Harikrishnan wrote:
> > Hi Stefano,
> > Sorry to bother you again.
> > I am currently trying to run my custom IP which sends periodic dm= a interrupts to the PS with cache coloring enabled. I have now compiled
> my
> > guest running with FreeRTOS and it generates a trap.
> > Petalinux and VITIS IDE Version is 2020.2.
> >
> > Please find the log attached. After the trap occurs, for every in= terrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context fault:
> > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing conf= ig from apu_freertos.cfg
> > (XEN) Dom1 colors: [ 8 ]
> > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id= =3D1 memflags=3D0xc0 (0 of 64)
> > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache= =3D0
> > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache= =3D0
> > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000
> > (XEN) sched_null.c:344: 1 <-- d1v0
> > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gv= a=3D0xff11000c gpa=3D0x000000ff11000c
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402,= iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> >
> > The same application works as expected without FreeRTOS, i.e as a= baremetal guest. I look forward for your comment on this.
> >
> > Although i see performance degradation, normally i can measure de= lta time for each interrupt configured to 1ms (without XEN), with XEN
> for
> > the same measurement shows 16 ms for each interval (but the perfo= rmance is not a priority for now).
> > Thanks and Best Regards,
> > Prem
> >
> >__________________________________________________________________= ________________________________________________________________________ > _
> > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > Sent: Tuesday, May 18, 2021 20:09
> > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>;
> JOVITAC@xilinx.com
> > <JOVITAC@xilinx.com&= gt;
> > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit  
> > Great to hear! Thank you for reporting back.
> >
> >
> > On Tue, 18 May 2021, Prem Harikrishnan wrote:
> > > Dear Stefano,
> > > Thank you very much for your guidance and support. I finally= fixed the issue. I made an error in base memory address like you pointed > > out.
> > > I actually modified the base address correctly to 0x40000000= but the default C code had an additional offset of 0x1100000 , and the
> DomU
> > > memory allocated was only 8MB. I either had to change the of= fset or allocate more memory to the DomU guest which i missed until you
> > pointed
> > > out. Additionally i had to set to AxPROT bits to 0x2 in Viva= do and the SMID required is 0xE80.
> > >
> > > Thanks again i was able get my custom IP also working as an = AXI master from PL.
> > >
> > > Best Regards,
> > > Prem
> > >
> >>______________________________________________________________= ___________________________________________________________________________=
> _
> > _
> > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > Sent: Tuesday, May 18, 2021 02:35
> > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <brian.woods@xilinx.com>; Julie= n Grall <julien@xen.org>; Stefano
> > > Stabellini <sst= abellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> <fnuv@xilinx.com>;
> > > edgari@xilinx.com &= lt;edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > JOVITAC@xilinx.com= <JOVITAC@xilinx.com>
> > > Subject: Re: Help: Information required for AXI DMA passthro= ugh for PL masters in ZCU102 dev kit  
> > > Your configuration looks correct as far as I can tell.
> > >
> > > You need dtdev because it triggers the SMMU configuration fo= r your PL
> > > block. You don't need device_tree because your baremetal app= lication is
> > > not going to read it, but it is not going to cause any issue= s either.
> > >
> > > When you say "the execution does not complete the loop = at line 244", it
> > > means that you see the execution entering the loop and then = never
> > > leaving? Like an infinite loop?
> > >
> > > If so, then I imagine the issue could be that the applicatio= n is
> > > crashing when trying to access TxBufferPtr, which is pointin= g to
> > > TX_BUFFER_BASE, which is:
> > >
> > >
> > > #ifndef DDR_BASE_ADDR
> > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \=
> > >           =        DEFAULT SET TO 0x01000000
> > > #define MEM_BASE_ADDR      &nb= sp;    0x01000000
> > > #else
> > > #define MEM_BASE_ADDR      &nb= sp;    (DDR_BASE_ADDR + 0x1000000)
> > > #endif
> > >
> > > #define TX_BUFFER_BASE      &n= bsp;   (MEM_BASE_ADDR + 0x00100000)
> > >
> > >
> > >
> > > Can you double check that TX_BUFFER_BASE is pointing to a co= rrect
> > > address? Memory starts at 0x40000000 in a Xen DomU.
> > >
> > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly?
> > >
> > >
> > > On Mon, 17 May 2021, Prem Harikrishnan wrote:
> > > > Hi Stefano,
> > > > Thanks again for your reply and your suggestion.  = I did try to replace the Xil_DCacheFlushRange with Xil_DCacheInvalidateRang= e(works
> > only
> > > > in EL3), I added printfs to debug, i can see that the e= xecution does not complete the loop at line 244
> > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drive= rs/axidma/examples/xaxidma_example_simple_poll.c  and
> > > > Xil_DCacheFlushRange is not reached. Please find attach= ed my xen bootlog.txt.
> > > > I am still unable to find out why??
> > > >
> > > > Can you please atleast verify that my xen.dtsi, and pl.= dtb is correct? and do i need dtdev and device_tree in my guest config file=
> when
> > > it
> > > > is already added to xen.dtsi?
> > > >
> > > > Best Regards,
> > > > Prem
> > > >
> > > >
> >>>__________________________________________________________= ___________________________________________________________________________= ___
> _
> > _
> > > _
> > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > Sent: Saturday, May 15, 2021 00:25
> > > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> > > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; Brian Woods <= ;brian.woods@xilinx.com>; = Julien Grall <julien@xen.org>; Stefano
> > > > Stabellini <sstabellini@kernel.org>; xen-users@lists.xenprojec= t.org <xen-users@l= ists.xenproject.org>; fnuv@xilinx.com
> > <fnuv@xilinx.com>; > > > > edgari@xilinx.com<= /a> <edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com>; Renato Costa A= morim <renato.amorim@evo= leotech.com>;
> > > > JOVITAC@xilinx.co= m <JOVITAC@xilinx.com><= br> > > > > Subject: Re: Help: Information required for AXI DMA pas= sthrough for PL masters in ZCU102 dev kit  
> > > > Hi Prem,
> > > >
> > > > Some older versions of Xil_DCacheFlushRange were implem= ented using
> > > > deprecated set/way instructions that are known to cause= problems in
> > > > virtualized environments.
> > > >
> > > > More recent implementations use the "dc civac"= ; intruction that shouldn't
> > > > have any issues.
> > > >
> > > > Can you double-check that you are calling the 64-bit ve= rsion implemented
> > > > by CIVAC?
> > > >
> >>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb= 18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#= L4
> 1
> > 4
> > >
> > > >
> > > >
> > > >
> > > >
> > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > Hi Stefano, 
> > > > > Thanks for your reply. Yes the axidma application = is a baremetal application from the xilinx vitis ide example. 
> > > > > Also yes, I have already run hello world as DomU g= uest, with UART1.
> > > > >
> > > > > I am using the simple mode using polling and not i= nterrupts(they are disabled in the c code), which is Why I didn't include i= n the
> > > guest
> > > > > config file. This works well when I compile it nor= mally (as EL3). When compiled as hypervisor guest, the execution stops befo= re the
> > > > > function xil_dcacheflushrange(). Please find the c= code attached
> > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxP= rocessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c&nbs= p;
> > > > >
> > > > > I found the SATA example similar to my use case, a= lso using DMA and SMMU. I just used it as a reference to create my pl.dtb t= o pass
> > > > through
> > > > > in the guest config.(from pl.dtsi, which I manuall= y created).
> > > > >
> > > > > Thanks and Best Regards,
> > > > > Prem
> > > > >
> > > > > Get Outlook for Android
> > > > >
> >>>>______________________________________________________= ___________________________________________________________________________= ______
> _
> > _
> > > _
> > > > _
> > > > > From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > Sent: Friday 14 May 2021, 23:16
> > > > > To: Prem Harikrishnan
> > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall;= Stefano Stabellini; xen-users@lists.xenproject.org; fnuv= @xilinx.com;
> > > > edgari@xilinx.com<= /a>;
> > > > > bwoods288@g= mail.com; Renato Costa Amorim; JOVITAC@xilinx.com
> > > > > Subject: Re: Help: Information required for AXI DM= A passthrough for PL masters in ZCU102 dev kit
> > > > >
> > > > > I take that the guest kernel "/bin/xaxidma_ex= ample_simple_poll_1.bin" is
> > > > > a baremetal application? Can you run it successful= ly, just printing
> > > > > "hello world", if you only assign the UA= RT and nothing else?
> > > > >
> > > > > I am asking just to verify that you can run the ba= remetal VM
> > > > > successfully, aside from the PL device assignment.=
> > > > >
> > > > >
> > > > > In regards to the PL device assignment, I'll let B= rian answer on the
> > > > > Vivado configuration and SMID calculation. But I n= oticed that you only
> > > > > assigned IRQ 54 to the DomU which is the one for U= ART1. You haven't
> > > > > assigned any IRQs for axi_dma_0. Looking at pl_fro= m_petalinux.dtsi, it
> > > > > looks like there are two related IRQs: 121 and 122= .
> > > > >
> > > > > Finally, why did you mention SATA passthrough in y= our reply? I don't
> > > > > follow: I cannot see any SATA controller assignmen= t in your
> > > > > configuration.
> > > > >
> > > > >
> > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > > Dear Brian, Stefano and Julien,
> > > > > >
> > > > > > Thank you very much for your replies.
> > > > > > Hi Brian and Stefano, Can you please help me = with the following questions?
> > > > > >
> > > > > > @Brian Woods Please find attached my vivado c= onfiguration, when i added my AXI DMA now running on simple polling mode(pr= eviously
> i
> > > > tried
> > > > > it
> > > > > > with Scatter Gather mode), Run Automation aut= omatically generated, 1 AXI Interconnect and 1 smart connect. Since there i= s only 1
> > > master
> > > > > and
> > > > > > I use the S_AXI _HP0_FPD, I finally get a val= ue of 0xE80 for the stream IDs.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters According to this link section 6.5 I have
> > manually
> > > > tied
> > > > > > of AxPROT bits to value of 0x2 to create non = secure transactions. Can you please confirm that my Vivado configuration is= correct?
> I
> > > can
> > > > > > update you soon with an ILA trace on Vivado.<= br> > > > > > >
> > > > > > @Stefano Stabellini Please find attached my p= l.dtsi generated from petalinux and system.dtsi also generated after manual= ly adding
> > > > > xen.dtsi.
> > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xe= n+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using
> this
> > > > SATA
> > > > > > passthrough, i made my own pl.dtsi for passth= rough used in dma.cfg. I could really use your help to identify what is mis= sing in
> my
> > > xen
> > > > > > configuration.
> > > > > >
> > > > > > Thanks and Best Regards,
> > > > > > Prem
> > > > > >
> >>>>>__________________________________________________= ___________________________________________________________________________= _________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > From: Brian Woods <brian.woods@xilinx.com>
> > > > > > Sent: Thursday, May 13, 2021 17:13
> > > > > > To: Stefano Stabellini <stefano.stabellini@xilinx.com>
> > > > > > Cc: Julien Grall <julien@xen.org>; Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; = Stefano Stabellini
> > <sstabellini@kernel.= org>;
> > > > > > xen-users@lists.xenproject.org <xen-users@lists.xenproject.org>; brian.woods@xilinx.com <brian.woods@xilinx.com>; fnuv@xilinx.com
> > > > > > <fnuv@x= ilinx.com>; edgari@xilinx.com <edgari@xilin= x.com>; bwoods288@gmail.com <bwoods288@gmail.com>
> > > > > > Subject: Re: Help: Information required for A= XI DMA passthrough for PL masters in ZCU102 dev kit  
> > > > > > Prem,
> > > > > >
> > > > > > Sorry for the late email, I've been under the= weather and have been away
> > > > > > from my computer.  In the Zynq SOCs this= is how the SMMU IDs in PL are
> > > > > > calculated:
> > > > > >
> > > > > > 14-10: TBU bits
> > > > > > 9-6: Master ID bits
> > > > > > 5-0: AXI ID bits
> > > > > >
> > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultras= cale-trm.pdf
> > > > > > To look up the TBU value, see UG1085 and look= for the "System Masters"
> > > > > > table which is table 16-4 on page 409.
> > > > > >
> > > > > > For the master ID, see UG1085 and look for th= e "Master IDs List" table
> > > > > > which is table 16-13 on page 429.
> > > > > >
> > > > > > The AXI ID bits is a bit trickery since it's = going to be out in PL.
> > > > > > See: https://www.xilinx.com/support/answers/69447.html=
> > > > > > With SmartConnect all the AXI IDs are 0, they= aren't passed on.  There
> > > > > > are work arounds.  Here's a couple of ex= amples (with example numbers):
> > > > > >
> > > > > > AXI master -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >
> > > > > > AXI master -> SmartConnect -> PS slave = port 0
> > > > > >        &nb= sp;            =        -> PS slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> SmartConnect -> PS s= lave port 0
> > > > > >        &nb= sp;            =             -> PS= slave port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > Two AXI masters -> sideband -> SmartCon= nect -> sideband -> PS slave port 0
> > > > > >        &nb= sp;            =             &nb= sp;            =            -> PS slave= port 1
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1)
> > > > > >         TB= U bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)
> > > > > >         TB= U bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2)
> > > > > >
> > > > > > The "sideband -> SmartConenct -> s= ideband" can also be functionally
> > > > > > replaced with "AXI Interconnect" to= my knowledge.  So the AXI ID bits are
> > > > > > fairly simple but with some caveats.
> > > > > >
> > > > > > You can also read in the SMMU faults from Xen= and use:
> > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_s= pecification.pdf
> > > > > > to decode them. That should tell you the SMMU= IDs as well.
> > > > > >
> > > > > > Let me know if this isn't clear or you have a= ny other questions.
> > > > > >
> > > > > > Brian
> > > > > >
> > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Ste= fano Stabellini wrote:
> > > > > > > On Mon, 10 May 2021, Julien Grall wrote:=
> > > > > > > > On 26/04/2021 15:41, Prem Harikrish= nan wrote:
> > > > > > > > > Hello everyone,
> > > > > > > >
> > > > > > > > Hi Prem,
> > > > > > > >
> > > > > > > > > I am using the latest version = of the xilinx mpsoc zcu102 development board
> > > > > > > > > and i am trying to create a ba= rematal application that uses the AXI DMA on
> > > > > > > > > the programmable logic, using = the scatter gather example from the xilinx
> > > > > > > > > repository. This works perfect= ly well for the baremetal application. The
> > > > > > > > > diagram below represents the i= nformation flow. The AXI DMA and the AXI data
> > > > > > > > > FIFO are in the Programable lo= gic (FPGA). This AXI DMA is out of the box IP
> > > > > > > > > from Vivado and uses a single = channel (Does not use AxUSER) which means the
> > > > > > > > > AXI ID cannot manually be set.=
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Now i want to make this as a b= aremetal hypervisor guest, in future this will
> > > > > > > > > be replaced by a custom IP wit= h cache colouring enabled. I want to pass
> > > > > > > > > through the AXI DMA in the PL.= (Not to be used by Dom0)
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I followed this tutorial Barem= etal + DomU
> > > > > > > > > <htt= ps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842536/XEN+EL1+Baremet= al+DomU>
> > > > > > > > > guest changed the base address= to 0x4000000,(1GB allocated to Dom-0) to
> > > > > > > > > create my EL1 binary. I used P= etalinux 2020.2 to generate my linux, xen
> > > > > > > > > image and use tftp to boot. > > > > > > > > >
> > > > > > > > >  From what i understand f= rom the xilinx tutorials Xen+and+PL+Masters
> > > > > > > > > <https:/= /xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters<= /a>>
> > > > > > > > > section 3 and MPSOC SMMU
> > > > > > > > > <https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+UltraS= cale+MPSOC+SMMU>
> > > > > > > > > section 4, stream ids are requ= ired by the SMMU to get the correct address
> > > > > > > > > translation.
> > > > > > > > >
> > > > > > > > > I am still unable to figure ou= t how to get the iommu property for my AXI DMA
> > > > > > > > > and how to set the dtdev confi= g for my hypervisor guest.
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > I can also see some new update= s with the XEN 2020.1 and 2020.2 releases
> > > > > > > > > which i can be useful to my ap= plication
> > > > > > > > >
> > > > > > > > >   *   1:1 = memory mappings for Xen virtual machines, enabling device
> > > > > > > > >     assign= ments without SMMU
> > > > > > > > >   *
> > > > > > > > >      =  Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > >     Xen vi= rtual machines
> > > > > > > > >   *   Supp= ort for PL Device Passthrough to DomU in Xen
> > > > > > > >
> > > > > > > > You are usiong a version of Xen tha= t has been customised by Xilinx. So I would
> > > > > > > > recommend to contact them directly.=
> > > > > > > >
> > > > > > > > I have CCed Stefano who might be ab= le to help you.
> > > > > > >
> > > > > > > Hi Julien,
> > > > > > >
> > > > > > > Many thanks for CC'ing me, I missed the = email.
> > > > > > >
> > > > > > >
> > > > > > > Hi Prem,
> > > > > > >
> > > > > > > Let me CC a few people that might be abl= e to help.
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>

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bh=+/6NgCMchf3raICkkqEuqTRrJqbszp34LrTbsxDpAgY=; b=HmSk76o/Q3COy4PiMI6YvhlKclTxmkWiS8uBIdprYRobSGyQI2ADFJZQpj1TIiniJeTWZkHjrqT+tR7f2YgR4TlcMunR4dcGagp5MM8oAtukIR90kDE6CMyWO8eYnxcB8DrrqU59nevgfwGEqTQ81nFOaxRKEI2kdr7eF+LmCos= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; evoleotech.com; dkim=none (message not signed) header.d=none;evoleotech.com; dmarc=pass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; Date: Tue, 15 Jun 2021 13:17:29 -0700 From: Stefano Stabellini X-X-Sender: sstabellini@sstabellini-ThinkPad-T480s To: Prem Harikrishnan CC: Stefano Stabellini , "xen-users@lists.xenproject.org" , , , Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit In-Reply-To: Message-ID: References: , , , , ,, User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: multipart/mixed; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2021 20:17:33.4590 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf79d258-3b06-47d4-aad4-08d9303a9c22 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0063.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2675 --8323329-1174738140-1623785923=:24906 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Content-ID: We don't have a recipe ready. It is not something we test. However I think it should be possible. The first step would be try to generate a BOOT.BIN for QSPI booting and write it to QSPI. The goal is to get to the u-boot prompt, with everything booted from QSPI. Then the next step is to add Xen, Linux, the DTB and Linux ramdisk. (Of course if you are OK with loading Xen and the other binaries from somewhere else like the SD card then it is going to work as is.) You should be able to write each binary to QSPI as separate partitions. At that point, you are only missing a boot.scr that can load them and boot. ImageBuilder supports custom u-boot load commands by setting the LOAD_CMD variable. In this case you'd need to set LOAD_CMD to something like "sf read", but given that the other command arguments are not filenames, ImageBuilder won't be able to handle it anyway. But you can take an ImageBuilder-generated boot.source, substitute the "tftpb" commands with the appropriate "sf read" commands and call mkimage to get a boot.scr. Now you should be able to run boot.scr from the u-boot prompt and load everything from QSPI. This is some relevant info: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842465/U-Boot+QSPI+Driver I know it is a bit complex but I think it should work OK. On Tue, 15 Jun 2021, Prem Harikrishnan wrote: > Hi Stefano, > > Is it possible to boot XEN from QSPI? Is there an image builder script already available to generate boot.scr? Please let me know. > Thanks and Best Regards, > Prem > > ___________________________________________________________________________________________________________________________________________ > From: Xen-users on behalf of Prem Harikrishnan > Sent: Tuesday, June 1, 2021 18:07 > To: Mubin Usman Sayyed ; Stefano Stabellini > Cc: xen-users@lists.xenproject.org ; Jovita Castelino > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > Hi Stefano and Mubin, > > Thank you very much for helping me setup up FreeRTOS and baremetal guests, everything works as expected and I also get expected performance > in both baremetal and hypervisor guests. Thank you again for your prompt support during the past few weeks. > > Best Regrards, > Prem > > ___________________________________________________________________________________________________________________________________________ > From: Mubin Usman Sayyed > Sent: Tuesday, June 1, 2021 05:38 > To: Prem Harikrishnan ; Stefano Stabellini > Cc: xen-users@lists.xenproject.org ; Jovita Castelino > Subject: RE: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > In case of FreeRTOS,  you need to use APIs from FreeRTOS port for interrupt handling >  (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). > Please make sure that you are taking care of that in DMA interrupt example . > >   > > Thanks, > > Mubin > >   > > From: Prem Harikrishnan > Sent: Tuesday, June 1, 2021 2:48 AM > To: Stefano Stabellini > Cc: xen-users@lists.xenproject.org; Jovita Castelino ; Mubin Usman Sayyed > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > >   > >   > > Hi Stefano and Mubin, > > Thank you very much for your replies. > > @Stefano Stabellini Sorry to bother you again, and thank you for pointing this out, the TTC0 is by default enabled for FreeRTOS to generate > ticks, although this says only for R5 core, i would have never figured this out. As soon as I added the irqs and iomem and gave a xen > passthrough in the xen.dtsi as you have suggested, FreeRTOS guest started working for other peripherals except for my DMA (FreeRTOS guest > does not work with interrupt and DMA). > >   > > I can see my DMA is enabled because i have LEDs configured to blink for every interrupt I get from the PL. I don't see my interrupts being > processed, but when I destroy the guest, I get this output periodically when an interrupt occurs. > >   > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > >   > > From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters > > Xen and PL Masters - Xilinx Wiki - Confluence > > 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of PL masters must be added to the Linux Dom0 device tree. > Automated device tree generation does not generate the stream IDs for the PL masters so that the user must add them into the device tree > manually. > > xilinx-wiki.atlassian.net > > The fault indicates an unidentified stream ID has been received by the SMMU as shown in the GFSR register. The GFSYNR1 register contains > the stream ID that was unidentified. A stream ID of 0xE80 was unidentified in the above fault. > >   > > But I think i have already added that in my smmu and iommu in xen.dtsi because my baremetal application works well as expected. I have > attached my xen.dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). > > What could I be missing here? Do I have to enable the ttc0 in the device tree? > > Also what does (XEN) Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 99990 KHz mean when XEN boots up? > > Thanks, I look forward for your reply. > >   > > Best Regards, > > Prem > >   > >   > > > ________________________________________________________________________________________________________________________________________ > > > From: Stefano Stabellini > Sent: Friday, May 28, 2021 20:43 > To: Prem Harikrishnan > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; JOVITAC@xilinx.com > ; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > >   > > From the gpa address, it looks like FreeRTOS is trying to access the TTC > timer? If you look at device tree, the corresponding node is > timer@ff110000. > > If FreeRTOS is configured to access the TTC timer, then you need to > assign it to it. Did you assign the TTC timer to the FreeRTOS domU by > any chance? > > You can do that by adding: > > irqs = [ 68, 69, 70 ] > iomem = [ "0xff110,1" ] > > > On Fri, 28 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Thanks for your reply. I am pretty sure I followed the steps you mentioned below to run the FreeRTOS hello world example. I already added > > printfs and i can see XEN cannot start the scheduler and i get the following out put on XEN. > > > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=9 extent: id=2 memflags=0xc0 (0 of 64) > > (XEN) memory_map:add: dom2 gfn=ff010 mfn=ff010 nr=1 cache=0 > > (XEN) sched_null.c:344: 1 <-- d2v0 > > (XEN) traps.c:1973:d2v0 HSR=0x93820007 pc=0x00000040012b08 gva=0xff11000c gpa=0x000000ff11000c > > > > > > I also see that according to this article > > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a-Xen-Virtual-Machine/ba-p/947030 > > [52662iFAD1733707609204?v=v2] > > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks What is FreeRTOS? The FreeRTOS kernel is a market leading > real-time > > operating system for embedded systems. As embedded applications grow in complexity, there is a growing need for a lightweight kernel > > capable of task scheduling... > > forums.xilinx.com > > FreeRTOS does not run out of the box for XEN, although the article is 2 years old, I am not sure if there are any updates on this after > > that. Can you please confirm? > > > > Thanks and Best Regards, > > Prem > > > >__________________________________________________________________________________________________________________________________________ > _ > > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 02:51 > > To: Prem Harikrishnan > > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; > JOVITAC@xilinx.com > > ; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > +Mubin > > > > > > Hi Prem, > > > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > > FreeRTOS is built to run at EL3 by default so if that is not changed > > there are errors when run on any hypervisor. It is possible to build > > FreeRTOS to run on Xen but it requires a couple of manual steps: > > > > - source settings64.sh from Vitis builds > > - xsct > > - set WORKSPACE . > > - setws -switch $WORKSPACE > > - app create -name freertos-hello-world -template {FreeRTOS Hello World} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > > - bsp config stdin psu_uart_1 > > - bsp config stdout psu_uart_1 > > - bsp config hypervisor_guest true > > - Go to application source path and modify the linker script start address to 0x40000000, > > - app build -name freertos-hello-world > > - Run command to generate BIN file from executable "aarch64-linux-gnu-objcopy -O binary --gap-fill 0  BOOT.BIN" > > > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > > might be able to provide additional info. > > > > > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > > Hi Stefano, > > > Sorry to bother you again. > > > I am currently trying to run my custom IP which sends periodic dma interrupts to the PS with cache coloring enabled. I have now > compiled > > my > > > guest running with FreeRTOS and it generates a trap. > > > Petalinux and VITIS IDE Version is 2020.2. > > > > > > Please find the log attached. After the trap occurs, for every interrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context > fault: > > > fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config from apu_freertos.cfg > > > (XEN) Dom1 colors: [ 8 ] > > > (XEN) memory.c:255:d0v0 Could not allocate order=9 extent: id=1 memflags=0xc0 (0 of 64) > > > (XEN) memory_map:add: dom1 gfn=ff010 mfn=ff010 nr=1 cache=0 > > > (XEN) memory_map:add: dom1 gfn=a0010 mfn=a0010 nr=1 cache=0 > > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > > (XEN) sched_null.c:344: 1 <-- d1v0 > > > (XEN) traps.c:1973:d1v0 HSR=0x93820007 pc=0x00000040013188 gva=0xff11000c gpa=0x000000ff11000c > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > > > The same application works as expected without FreeRTOS, i.e as a baremetal guest. I look forward for your comment on this. > > > > > > Although i see performance degradation, normally i can measure delta time for each interrupt configured to 1ms (without XEN), with XEN > > for > > > the same measurement shows 16 ms for each interval (but the performance is not a priority for now). > > > Thanks and Best Regards, > > > Prem > > > > >>_________________________________________________________________________________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 20:09 > > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; > > JOVITAC@xilinx.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > Great to hear! Thank you for reporting back. > > > > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > > Dear Stefano, > > > > Thank you very much for your guidance and support. I finally fixed the issue. I made an error in base memory address like you pointed > > > out. > > > > I actually modified the base address correctly to 0x40000000 but the default C code had an additional offset of 0x1100000 , and the > > DomU > > > > memory allocated was only 8MB. I either had to change the offset or allocate more memory to the DomU guest which i missed until you > > > pointed > > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and the SMID required is 0xE80. > > > > > > > > Thanks again i was able get my custom IP also working as an AXI master from PL. > > > > > > > > Best Regards, > > > > Prem > > > > > >>>________________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 02:35 > > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini ; Brian Woods ; Julien Grall ; Stefano > > > > Stabellini ; xen-users@lists.xenproject.org ; fnuv@xilinx.com > > ; > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim ; > > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > Your configuration looks correct as far as I can tell. > > > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > > block. You don't need device_tree because your baremetal application is > > > > not going to read it, but it is not going to cause any issues either. > > > > > > > > When you say "the execution does not complete the loop at line 244", it > > > > means that you see the execution entering the loop and then never > > > > leaving? Like an infinite loop? > > > > > > > > If so, then I imagine the issue could be that the application is > > > > crashing when trying to access TxBufferPtr, which is pointing to > > > > TX_BUFFER_BASE, which is: > > > > > > > > > > > > #ifndef DDR_BASE_ADDR > > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > >                  DEFAULT SET TO 0x01000000 > > > > #define MEM_BASE_ADDR           0x01000000 > > > > #else > > > > #define MEM_BASE_ADDR           (DDR_BASE_ADDR + 0x1000000) > > > > #endif > > > > > > > > #define TX_BUFFER_BASE          (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks again for your reply and your suggestion.  I did try to replace the Xil_DCacheFlushRange with > Xil_DCacheInvalidateRange(works > > > only > > > > > in EL3), I added printfs to debug, i can see that the execution does not complete the loop at line 244 > > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c  and > > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bootlog.txt. > > > > > I am still unable to find out why?? > > > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is correct? and do i need dtdev and device_tree in my guest config file > > when > > > > it > > > > > is already added to xen.dtsi? > > > > > > > > > > Best Regards, > > > > > Prem > > > > > > > > > > > >>>>_______________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini ; Brian Woods ; Julien Grall ; > Stefano > > > > > Stabellini ; xen-users@lists.xenproject.org ; fnuv@xilinx.com > > > ; > > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim > ; > > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > > Hi Prem, > > > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > > deprecated set/way instructions that are known to cause problems in > > > > > virtualized environments. > > > > > > > > > > More recent implementations use the "dc civac" intruction that shouldn't > > > > > have any issues. > > > > > > > > > > Can you double-check that you are calling the 64-bit version implemented > > > > > by CIVAC? > > > > > > >>>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L > 4 > > 1 > > > 4 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Hi Stefano,  > > > > > > Thanks for your reply. Yes the axidma application is a baremetal application from the xilinx vitis ide example.  > > > > > > Also yes, I have already run hello world as DomU guest, with UART1. > > > > > > > > > > > > I am using the simple mode using polling and not interrupts(they are disabled in the c code), which is Why I didn't include in > the > > > > guest > > > > > > config file. This works well when I compile it normally (as EL3). When compiled as hypervisor guest, the execution stops before > the > > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c  > > > > > > > > > > > > I found the SATA example similar to my use case, also using DMA and SMMU. I just used it as a reference to create my pl.dtb to > pass > > > > > through > > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > > > > > > Get Outlook for Android > > > > > > > >>>>>______________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Stefano Stabellini > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > > To: Prem Harikrishnan > > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabellini; xen-users@lists.xenproject.org; fnuv@xilinx.com; > > > > > edgari@xilinx.com; > > > > > > bwoods288@gmail.com; Renato Costa Amorim; JOVITAC@xilinx.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > > > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.bin" is > > > > > > a baremetal application? Can you run it successfully, just printing > > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on the > > > > > > Vivado configuration and SMID calculation. But I noticed that you only > > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven't > > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dtsi, it > > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I don't > > > > > > follow: I cannot see any SATA controller assignment in your > > > > > > configuration. > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > > > Thank you very much for your replies. > > > > > > > Hi Brian and Stefano, Can you please help me with the following questions? > > > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when i added my AXI DMA now running on simple polling > mode(previously > > i > > > > > tried > > > > > > it > > > > > > > with Scatter Gather mode), Run Automation automatically generated, 1 AXI Interconnect and 1 smart connect. Since there is only > 1 > > > > master > > > > > > and > > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for the stream IDs. > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters According to this link section 6.5 I have > > > manually > > > > > tied > > > > > > > of AxPROT bits to value of 0x2 to create non secure transactions. Can you please confirm that my Vivado configuration is > correct? > > I > > > > can > > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated from petalinux and system.dtsi also generated after manually > adding > > > > > > xen.dtsi. > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > > this > > > > > SATA > > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.cfg. I could really use your help to identify what is missing in > > my > > > > xen > > > > > > > configuration. > > > > > > > > > > > > > > Thanks and Best Regards, > > > > > > > Prem > > > > > > > > >>>>>>_____________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > _ > > > > > > > From: Brian Woods > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > > To: Stefano Stabellini > > > > > > > Cc: Julien Grall ; Prem Harikrishnan ; Stefano Stabellini > > > ; > > > > > > > xen-users@lists.xenproject.org ; brian.woods@xilinx.com ; > fnuv@xilinx.com > > > > > > > ; edgari@xilinx.com ; bwoods288@gmail.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > > > > Prem, > > > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have been away > > > > > > > from my computer.  In the Zynq SOCs this is how the SMMU IDs in PL are > > > > > > > calculated: > > > > > > > > > > > > > > 14-10: TBU bits > > > > > > > 9-6: Master ID bits > > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > > > > > > To look up the TBU value, see UG1085 and look for the "System Masters" > > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List" table > > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in PL. > > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.  There > > > > > > > are work arounds.  Here's a couple of examples (with example numbers): > > > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > >                            -> PS slave port 1 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share) > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > >                                 -> PS slave port 1 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share) > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share) > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS slave port 0 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1) > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2) > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS slave port 0 > > > > > > >                                                         -> PS slave port 1 > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1) > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1) > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2) > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2) > > > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be functionally > > > > > > > replaced with "AXI Interconnect" to my knowledge.  So the AXI ID bits are > > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_specification.pdf > > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions. > > > > > > > > > > > > > > Brian > > > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wrote: > > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 development board > > > > > > > > > > and i am trying to create a barematal application that uses the AXI DMA on > > > > > > > > > > the programmable logic, using the scatter gather example from the xilinx > > > > > > > > > > repository. This works perfectly well for the baremetal application. The > > > > > > > > > > diagram below represents the information flow. The AXI DMA and the AXI data > > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is out of the box IP > > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSER) which means the > > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, in future this will > > > > > > > > > > be replaced by a custom IP with cache colouring enabled. I want to pass > > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocated to Dom-0) to > > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate my linux, xen > > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > > >  From what i understand from the xilinx tutorials Xen+and+PL+Masters > > > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the correct address > > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu property for my AXI DMA > > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2020.2 releases > > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > > >   *   1:1 memory mappings for Xen virtual machines, enabling device > > > > > > > > > >     assignments without SMMU > > > > > > > > > >   * > > > > > > > > > >       Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > > >     Xen virtual machines > > > > > > > > > >   *   Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by Xilinx. So I would > > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --8323329-1174738140-1623785923=:24906-- From xen-users-bounces@lists.xenproject.org Wed Jun 16 21:39:56 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 16 Jun 2021 21:39:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.143536.264474 (Exim 4.92) (envelope-from ) id 1ltdFd-0003WN-Sv; Wed, 16 Jun 2021 21:39:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 143536.264474; Wed, 16 Jun 2021 21:39:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltdFd-0003WF-Pq; Wed, 16 Jun 2021 21:39:09 +0000 Received: by outflank-mailman (input) for mailman id 143536; Wed, 16 Jun 2021 21:39:08 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltdFb-0003W9-VB for Xen-users@lists.xenproject.org; Wed, 16 Jun 2021 21:39:08 +0000 Received: from mout.gmx.net (unknown [212.227.15.18]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 68582f31-7549-42f4-8c2e-8a15e8f0fbb7; Wed, 16 Jun 2021 21:39:06 +0000 (UTC) Received: from [192.168.123.64] ([77.64.145.119]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1N7zBR-1lFo9y1T2B-0154dJ for ; Wed, 16 Jun 2021 23:39:05 +0200 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 68582f31-7549-42f4-8c2e-8a15e8f0fbb7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1623879545; bh=mVgFW2KGFVMegcEVZltMIpeHOAewgM3WCg06kKeHnAg=; h=X-UI-Sender-Class:To:From:Subject:Date; b=f5Nw2ZaxWjzORibtujHPTs0D2bBjT9+oZtuma8FJtGPXQuBaeJEqIny9C9WXeVOZQ mYPbAoRASAdnrzrysD1Lp0fH78tqvZLbboZecr+SnSsWxyfRsEe/BGbyDVvvLVeXd4 bJnKlkxuFfKmgRf77BJ3IcenW79PtlofEXq51UPg= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c To: Xen-users@lists.xenproject.org From: Bobbi Sanchez Subject: Howto read MSR thermal under XEN-4.15.0 Message-ID: <1b165ee0-fd39-4dcb-bd5c-5720aed0bef0@gmx.de> Disposition-Notification-To: Bobbi Sanchez Date: Wed, 16 Jun 2021 23:39:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: de-DE X-Provags-ID: V03:K1:HUzsSladxSoCVTPOruIBdudK51q0On7McqNHzjO97eWTeP4AFta wd+SRQMIE0W3YzOgPzOJklDLZY1R8uHaBdeCubZfMxg8RGKXAWdkkKHqqaf6dsTntPOYzTd GqcHG+mZffEdghlVS/GNKCwdti6lUPvnSnjN+wtGi4X8k4iXHozTlJWbo3zd991iavqVK5Y 1T83oYG+ZsmYsrqtpNoEA== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:nqAxbasLR2w=:6VB0tkkiyJFOFUg2lESIBB usS9zpS6c/PLVGql8ejt4LAy7WkRPF01tBfJpPEk9BygoAD7UIp8wHlwq89Zdwc3F4hQRwojB N92guq0fnrHY5I1TMq0TfGWl43oOeEUld4vvPT4NR1N81XjcPjsGfqfVdpO5DwRhHqAT7Ap81 zZUzehXFS0sMmYmD/ZHaaA2wudsUYiX7FfSqn9qnTOr8wyINcDkypQmJVsaySih3tjyGeYwYc 9qFtrkdse7sWBMkydA/Tst14h5P+jad5Ocy4B8pUBFJTgODMMfH3dIPpyTRsifQ2blIfY/Bge HJ8b9sbVuAlmTWjnACRh9pSi/a/SdS9WqxVzIE64ZDqL4L0ZoaspOVqBnNiCBRNysvrdfVkfh ZNTKCrlCedZMRc8xaSMp2IuA6zNNv3S2IhSa0aqzncYqUF5rBwr37Z671ij0Z6vLAMdzQpCAW 3Y5mnuVA1BHJi5vzUTXCzhaatrOS89u39AIjgsD7UYHgSBTrixE0AMlCDHBLw2+CPU6PzTmGd u8D5r/FmEcxwewL6aR6wZw7dQl9fR+Am4dHccC4IX3wRBtJPbageTuhr0x8QZgygA/SJ9iVFG oDVG9pxhYXvL6eviyt/L88zSU4yr+4rsrNh9OmvP1ArvUfRXeR3DlFdyJ6F97EWtLXq5dBEaN aIDBKXPIOnD0x3gGYmGF/dTk/FDQvXbpoKgiRsVmpoSGwhFYjsLvGxyaG+6Y7/BHTOgbh3t1f oAWmS7Ba14mfxsX30iVW39QV2DJmJnD0Z3CRw5GBu7MfPwZ8HuBf8DzSr6MIpt5LY79jaKNck apqlSq1uxOGUhKru7JwrdNJEQX5hLz4QcHF9eGL2H2V2XtN0kymejpx+eVonBIi73E98eElbV g4FkfwBuy0d0JFWaz5IL866W0x/kangRJzuYrJcp+tknsAkqIHzIqomfKk78ix4bLccJ7lO1/ ga0VDDkjc+1qM8WRPQ2FFqsyrW1mQE6HvlmAdKFA8dTZgvM9/jdIfEqxSa1c68S44+RH9tFzu F9ikIGQvEFrTnfD44dCDRWPJ2BliYwxhk+O9NEbqoKp9nesVTwXFRn1iwBiY/T8C+ET4mo649 ZEY9xi7JXmvSxPftUokyU1cL4am+Juup+A2 Hi, how can i read the MSR Thermal Values under XEN-4.15.0 ? Usually without having XEN-4.15.0 installed i can read the MSR Thermal Values like this: rdmsr -p 0 -d -f22:16 0x19c this works for my Core2Quod Q6600. But after having xen-4.15.0 installed and booted, same command shows now: 0 Best Regards B. S. From xen-users-bounces@lists.xenproject.org Thu Jun 17 11:09:45 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 17 Jun 2021 11:09:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.143817.264894 (Exim 4.92) (envelope-from ) id 1ltptT-0001jd-2U; Thu, 17 Jun 2021 11:09:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 143817.264894; Thu, 17 Jun 2021 11:09:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltptS-0001jV-VG; Thu, 17 Jun 2021 11:09:06 +0000 Received: by outflank-mailman (input) for mailman id 143817; Thu, 17 Jun 2021 11:09:05 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltptR-0001jM-M4 for Xen-users@lists.xenproject.org; Thu, 17 Jun 2021 11:09:05 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltptQ-0007dd-EE; Thu, 17 Jun 2021 11:09:04 +0000 Received: from [54.239.6.186] (helo=a483e7b01a66.ant.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1ltptQ-0002z5-7G; Thu, 17 Jun 2021 11:09:04 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To: MIME-Version:Date:Message-ID:From:References:To:Subject; bh=H0G6IP05Z/xQxDUrcq5U5h+qyoIKhYqZBqwwKsjiE2Y=; b=6Wymjz209VJRMfMNm9RXRSmb9A m0J+f/GQtfKNG7axhg7AyN6ylLXytapHkaH1jUF/+o7XwYInKkfD0Fe1xd2A6SMNW9MTWF4Z7aQci Ne7xA4ojsRdwPjHRGPv9NNSgBIgAVc+8I/F8gLpe4SGvkY2H7U+ECqhHoMgXVi70kQ4A=; Subject: Re: Howto read MSR thermal under XEN-4.15.0 To: Bobbi Sanchez , Xen-users@lists.xenproject.org, Jan Beulich , Andrew Cooper References: <1b165ee0-fd39-4dcb-bd5c-5720aed0bef0@gmx.de> From: Julien Grall Message-ID: <95ce3aca-326a-df20-4a74-60cf03e240bc@xen.org> Date: Thu, 17 Jun 2021 13:09:02 +0200 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <1b165ee0-fd39-4dcb-bd5c-5720aed0bef0@gmx.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit (+ Andrew and Jan) Hi, On 16/06/2021 23:39, Bobbi Sanchez wrote: > Hi, > > how can i read the MSR Thermal Values under XEN-4.15.0 ? > > Usually without having XEN-4.15.0 installed i can read the MSR Thermal > Values like this: > > rdmsr -p 0 -d -f22:16 0x19c > > this works for my Core2Quod Q6600. > > But after having xen-4.15.0 installed and booted, same command shows now: 0 I believe the access was restricted as part of XSA-351 [1]. I am not sure if there are a safe generic way to access them. I will let Andrew and Jan commenting. [1] https://xenbits.xen.org/xsa/advisory-351.html > > > Best Regards > > B. S. > > -- Julien Grall From xen-users-bounces@lists.xenproject.org Thu Jun 17 11:17:42 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 17 Jun 2021 11:17:42 +0000 Received: from list by lists.xenproject.org with outflank-mailman.143829.264911 (Exim 4.92) (envelope-from ) id 1ltq1c-0003cC-2R; Thu, 17 Jun 2021 11:17:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 143829.264911; Thu, 17 Jun 2021 11:17:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltq1b-0003c4-VO; Thu, 17 Jun 2021 11:17:31 +0000 Received: by outflank-mailman (input) for mailman id 143829; Thu, 17 Jun 2021 11:17:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltq1a-0003bw-H0 for Xen-users@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?ZUJmU3VGamdPWHBhdmo5S0Q4eEU3TTBJSDJkUkJTQUk5ejY5TVBzYm05YzA3?= =?utf-8?B?OXF6aHNOWXJSbmZuRlp0MWNmRGZrVVBITEVvOGk1c0tVL1Z3eDRLamE5U2li?= =?utf-8?B?WDhacmUxbkwxTmF5VitMUVN3RlR3ZjV0c2VBditVbUhhcFdtRHFRRDdzL1BU?= =?utf-8?B?VmVqS0lUUlR6WkVNU1dCMlVKekEzdTJIakw5TWIxRFJTaGNnSWRuN2trWTVW?= =?utf-8?B?Vk15bUpFelkramF5bVEraWtEMU81YjhUMTRmUklSV3R3ZUIxYXBMU2IranJY?= =?utf-8?B?MGpYK3hkelYwckRDdXFGU3JIbVdXU0NpcjFIZ1crU3V0YzVKak9pYXlnN1VJ?= =?utf-8?B?Sm1MaDJ1Z3VuUzNJSWh3MFlnUTN0Wk16ZUpuay9hbmRKVVlYWEZiazhvQ3Fw?= =?utf-8?B?ekdrdlZybEI4V3dCMGYydmpobU85NkZoajdYYUVGZW9qQS9BVG4zZ29wbEZz?= =?utf-8?B?Zm92WGdoTldZK3NNOHZxWXFhdG5tTUlyS3J0bE5GamlncHVCeDBhb0Q1SjdR?= =?utf-8?B?WWZQS3BtcEhnSGhqOXVpczlhWHd2RnFTMEx5a1hXb2JxRm5ZWVRSZUhoNkdT?= =?utf-8?B?VTZneExVS3FZMG1JMExZMXdFcWpKcDkyVytmYmNuQnRZZ1R1YkhXQ0NRRll4?= =?utf-8?B?dzgzR2p1SlJZd3RJcVBzNDB0MkhWSXFNK1JPdkY3cm1PZktCamRURGxqRXJh?= =?utf-8?B?Vy95M0djOFJnSmViWnJVanZCMkNjUmRhMUkyMlJpaUpyaENyVU5sbnBtOWxB?= =?utf-8?B?WWV2YVhRQWZEUFR0SjlqWVJvZzR0TWpGbXc5TS9xUHhEVVFhSkZubzNOVUYr?= =?utf-8?B?L2ZzSHNnb3RNTGwrNGd1NWJsdmkraURGTmI4ZVY4bnd0bmJ4ZjFZbi9xNm1J?= =?utf-8?B?T0ZHeXNIWFlRalBza08xd1Rncjc0cHFONUtvejRJV0ozcjZWcklPQm9WUWs5?= =?utf-8?B?L1R2YXB0enhIWmMyb0FES2xPYXhYZFJqUGlYYzhneDV5aU5talM4RTNENXhF?= =?utf-8?B?NGRLcDMvcG83Y1JxWlV1dzRLNlZ6S0FwaEtEUldBdHRNNXprenhvN2R5a3My?= =?utf-8?B?OWJiSVBPN1JxVFNocUU5NkpvZ0RSdElrWm84SHYrQ2NtRzBrbi9NVFNPZlJI?= =?utf-8?B?OWJQcVhTQ3kxc0xuNzhQK0JYdUF4cFZoaCtGMmVVa1p3M0lPYk5rekJTNTVu?= =?utf-8?B?TDh5MWM2TjJUOUNaQWpJcDAycCtDVTlVSHZ1YlMwMFA1Zy9SR3FmYkVnd1Ez?= =?utf-8?B?UCtPZm9HOTA1c3o2Vmh6YVBaQmF4TDhDM3RVdGtpMkF4WDlYY0lRUXNwMGxj?= =?utf-8?B?L0cxRFlkT3JRTU4raW5Mbi9BdkRwM0pqeTBpYXA0endlZFh4SitCY0k5ZStx?= =?utf-8?B?dlZmQTZVV1FIVmVkeHk5TVpUVE56UFZmUm1SeXhieUJIS0N6ajdpUnIybUxt?= =?utf-8?B?ek5sOHVMMjdGMVAzbGNtbXZTci9rMy95NHJsci9sNSt1ZGxscS9aanQ2NGFa?= =?utf-8?B?bExzcGk2Z2luUHN1TldKem1NUFRCR2Fsb25PTTdCV2lKZXg2NFd3OHdiendU?= =?utf-8?B?M1RpK2RvQTVocCtuR0dTMk1DWmg0SGI3bGErcm11cENTbEdXejliS2FLZ3E1?= =?utf-8?B?TFcvdzY0NjlzbEw3MWpaZFRHT2UyMEJCeHg5ejVOQlF4Qmx2V1kxQUFYWjVu?= =?utf-8?B?cVkrVklqVHo1Tytldk1KenRQaG0zSzRnclhCWXIySzZQUzE1S1p0emNsTUpO?= =?utf-8?Q?9zjw36Z27irgfAGg9cIHAhorEBz2ypCCQARmSeG?= X-MS-Exchange-CrossTenant-Network-Message-Id: 65780c82-36c4-4ce2-6fb5-08d931817bd3 X-MS-Exchange-CrossTenant-AuthSource: BYAPR03MB3623.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 11:17:24.9731 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CkiqV1qYhq/YzhpbCMfsN6dhXrTDSxwGe6bSkLyeOgn/Fvg1B8B7sKhbccUPmaYy2SWAfymRqZDtJCvw7wJxTfjGV0aMN4Be2cXdvI6J0LI= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR03MB3800 X-OriginatorOrg: citrix.com On 17/06/2021 12:09, Julien Grall wrote: > (+ Andrew and Jan) > > Hi, > > On 16/06/2021 23:39, Bobbi Sanchez wrote: >> Hi, >> >> how can i read the MSR Thermal Values under XEN-4.15.0 ? >> >> Usually without having XEN-4.15.0 installed i can read the MSR >> Thermal Values like this: >> >> rdmsr -p 0 -d -f22:16 0x19c >> >> this works for my Core2Quod Q6600. >> >> But after having xen-4.15.0 installed and booted, same command shows >> now: 0 > > I believe the access was restricted as part of XSA-351 [1]. I am not > sure if there are a safe generic way to access them. I will let Andrew > and Jan commenting. This method was never safe to begin with, because dom0 is just a VM and can be migrated around.=C2=A0 If you pin dom0, then you're still can't acce= ss registers who's scope is missing from where dom0 is pinned. I'm afraid this is something which has never worked correctly under Xen, but used to give enough of an illusion of working for people to think that it did work. Someone needs to come up with a plan to paravirtualise this interface, probably using XENPLAT_resource_op, so tools in dom0 can actually read the registers they think they're trying to access. ~Andrew From xen-users-bounces@lists.xenproject.org Thu Jun 17 11:27:16 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 17 Jun 2021 11:27:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.143853.264951 (Exim 4.92) (envelope-from ) id 1ltqAl-0006fe-JF; Thu, 17 Jun 2021 11:26:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 143853.264951; Thu, 17 Jun 2021 11:26:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltqAl-0006fX-G9; Thu, 17 Jun 2021 11:26:59 +0000 Received: by outflank-mailman (input) for mailman id 143853; Thu, 17 Jun 2021 11:26:58 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ltqAk-0006fR-JC for xen-users@lists.xenproject.org; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?UmRDdllRR0lZMkQ4VmxwYllNWG1kWVhGZ1lFcUZtaHQ4Y1c3WEdpMDJQVGRC?= =?utf-8?B?Y0I1Z2tBRTZQRUFYWWtyYnYvS1BkczA1RjVQWEZOdHJiK2ROdkFtdTIvRmQ2?= =?utf-8?B?TmVQaytIOW53andRK2lDWUtqOUNhU1U2UC9qUFQ2WTkvUzZkYXdDNzRCeWF3?= =?utf-8?B?YkhEUVFCVlpVM2xHdTFkc0RxVVA1dm9jcGlHWjJLbXNaWTRDbEk5c0VwbXZi?= =?utf-8?B?cmNpS2Y0dGxUY29yNlV3bUdVcXZIQ293YThUOXhCSEx1MTBQcFdIU0dSL1l6?= =?utf-8?B?VmpkZnhSQjVQTnJuamg1M0RPTVhjVE1XUEVzeFMxb05WWDVSclRzR0ZEcTE4?= =?utf-8?B?MHMySGhubUhYKzR3enBrcTlxcndUSUluS0FSWU5mdElnSDlVK1J2ZkNBMWFJ?= =?utf-8?B?SGVZNk14Zmd6VjVIZUVLN0d4S29pU2duMjBKOEMzY2cxcnB5YTUzbGxFQ2sw?= =?utf-8?B?b2dFekxFNjh3NEw2aWF0UHdkem9wa3NLZzlvaWRJS2lRUTA4ZHNKTmhRZlFL?= =?utf-8?B?UGRaNFJxUGVaSXZ3TUVPck1VTy93TmJzZ00vQXZJbjNGR1NOeDNLNXA3ZkpB?= =?utf-8?B?RzFKNW5naFdqN3VWYTlzYSsrd0VvaVM0UGtIcGQ4dUdTWEY5SlR6ejRHRXVw?= =?utf-8?B?RjdMbTlFbHdJVlR2dC8zMnU3cVo0eHE3QmlHRjVLdVpuWk1xVXhTQ09iTk5C?= =?utf-8?B?T1NzVGtSUGQ1aVFyS2pNbWtmcmtSNUYycGVGWHMyWGkyN3Q4Rk1CbGdQcEov?= =?utf-8?B?T2NXdUlrckU3SkpKejIzcmw2dHJ2ejdNNEJYTXpnMysyd2V3TTFxZExSWWVl?= =?utf-8?B?YzkwQTdSd21GSFB3OUY1MWViOG5XYlJmSWMyckZDeFVKaytRckxMLzJBUUZF?= =?utf-8?B?OXNwUnVycFQ5WXExTE1manBzQ3cyME1ueWlWMUYyQXhUbnJ5WUdLQXFDU1F1?= =?utf-8?B?cEsyY042aC9qaldRN2NPalBCaSttRE11WldRblZFUExKYUczYk1MSzJSNCs4?= =?utf-8?B?bVg0cFdOdkp3aXZPbHFFTE9yTmwzNXJPTzF0TkdrZ1FwYkdHb1htakRZNDZk?= =?utf-8?B?d0s5MjZmcnl4TnUwdy9wODBPbGFrL01YZ1dyVmx0bjZvaTB6NWsrK3VlNlNw?= =?utf-8?B?N3FEc2YwaklCMmtvd1E3QVY5K0tFQjlMaHZ6bzZiSWlqSzJNSDhKMHRPcmVn?= =?utf-8?B?aDJjekx5Z1p5c0VwNHl3cVdUMHVqRURsL20xUGlnejhLeUw4Nmt2WGxVOWcz?= =?utf-8?B?emtDOXN6OGJyMDRsZzNCaUFZYmxCZE14WnVUWTBaODlTQ2pEUHlCTGo3TTRK?= =?utf-8?B?eExJaDhZWFlDWC95Vmt3WVJUUUJTQnBvaUdiS2ZrcVBMYlVKK1hCei9leVNZ?= =?utf-8?B?YytxdnF0UnVHL3dpdFA0eW80UlBRaW1uUXhFSHNvaEJXcjNUaFZZVXpkVDFP?= =?utf-8?B?ZUdXSk1WQ3ZkKzNlTktaTW9hRGxaTVRvVkFhWEpxYnNpMkY2dzV3aTkyNjFH?= =?utf-8?B?WEpCYzdweHhncXZqOEg2RGdsSWt3K0ZtcTVlaVY5bVk4MWo1ejRHZTRIMWVu?= =?utf-8?B?dmtZUGF1QndReVpNaEV5cmFXamMvOWl2TDFFalNEcUxVSjBuNE9KLzB4NzVE?= =?utf-8?B?MGREZVhKNGU4WERETjUxc0o2Y3YyQmZKNEsycUtHdHQ0Wkw0aUExejl2U3Ur?= =?utf-8?B?L21Ld2d2Y0RqSDhlQ0NzaHlvdDBxQ1lTd2N2R0dQbk9iMk1LNlgycTRDVHVp?= =?utf-8?Q?3AncgssqvjXNZxo+mc6s8oW2ylT43ZFXFoP2ZSW?= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 99a1cf29-b393-4a22-a376-08d93182cf15 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5600.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 11:26:54.0526 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zg2SW1nA3l+tknqtbAVyY9JVCOfUrBDNUB8c2E8cwY4J2CC0tLC4I9TVp78UyKY5KYulH+ylBjmj/pm5hwgg0A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7038 On 17.06.2021 13:09, Julien Grall wrote: > On 16/06/2021 23:39, Bobbi Sanchez wrote: >> how can i read the MSR Thermal Values under XEN-4.15.0 ? >> >> Usually without having XEN-4.15.0 installed i can read the MSR Thermal >> Values like this: >> >> rdmsr -p 0 -d -f22:16 0x19c >> >> this works for my Core2Quod Q6600. >> >> But after having xen-4.15.0 installed and booted, same command shows now: 0 > > I believe the access was restricted as part of XSA-351 [1]. I am not > sure if there are a safe generic way to access them. I will let Andrew > and Jan commenting. just as additional context (i.e. on top of Andrew's reply): It wasn't that XSA, but our general switch of policy from blacklisting to whitelisting MSRs. The XSA was about *_POWER_* and *_PERF_* MSRs. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.onmicrosoft.com; s=selector2-citrix-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=V1oB+KouzyAYbH5dZayQSj+aZa8vZ644FUTTy1X0pJs=; b=TZwj8NoiWhQWlxHC4RQK9kmvsFhCtcmtFnpIGxdAdFoQgni05x+cUYk4WYN9YyKiH3/vsrqbOHf7xkrkNjvS1z49Dy/TIwx6E9FCH4zW62KjC9wNHjEReC3OGApn9zbFepGrVPNPYa87e+Q1bYh75LSNrfliL6uaYNETBLdRCEU= To: Jan Beulich , Julien Grall , "Bobbi Sanchez" CC: References: <1b165ee0-fd39-4dcb-bd5c-5720aed0bef0@gmx.de> <95ce3aca-326a-df20-4a74-60cf03e240bc@xen.org> From: Andrew Cooper Subject: Re: Howto read MSR thermal under XEN-4.15.0 Message-ID: Date: Thu, 17 Jun 2021 12:43:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Language: en-GB X-ClientProxiedBy: LO4P123CA0217.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1a6::6) To BYAPR03MB3623.namprd03.prod.outlook.com (2603:10b6:a02:aa::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 50def61c-e4af-4831-7a86-08d9318529da X-MS-TrafficTypeDiagnostic: BYAPR03MB3798: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?cW1vclZ4cmljYTJZcDVLbFJDdE5tVE9WNi9uTTB1Q0JTbEQ3L3RObVhaZldT?= =?utf-8?B?TmxsMVVWaFRKSnIrVjJJOGU1dTRtTnQrVFRQZFBPRXVGWHh6NzdXQjdiT3Z6?= =?utf-8?B?T0QvR2ZxZ09Ma3NIQUtJbGdsaUdEckhnUnRjRDFZWXZHZWtWM0hlZm5PcFpu?= =?utf-8?B?MkdBcVJDWkVxLzI4L21YV0VsZUpCNi9wVjVkbmQ3SUdMalJ4RW05VFVpejZs?= =?utf-8?B?Rm9qTk1KUVBhem5zMXBzYmR3T3drMjVSWGhIdGxKaVJjZkQyU3RQVWNIN0Uw?= =?utf-8?B?QlFoSTJnSENZU2RjY09Sdk9WNWVDN1Q1NjB2dkdmRjFRY0lHcWNEM2xKT1Nv?= =?utf-8?B?ZTZPMWlIWFdXQkdnOHhnb1QxcVphd3doUDRzenFEV2tCSDN0MVczSCswK1VV?= =?utf-8?B?VnNnQW1mRy9sczhIbS81U1lWM05KOEd0aDVUUnlpMW9TaDJrd1d1ZDVwa2sy?= =?utf-8?B?N0JWL0MrRXl2aGllN2hHWG9NQnh3TjBJRVhWQ043ZnlUeVM1SHNVNFdQZ3JE?= =?utf-8?B?SFJ6MVRQdnphbi8vcUpWN3AxMUJrMGxSR0ZNcm9QalNoeTRDUWRrNk1zTWg1?= =?utf-8?B?eHVLVWZEbE5FdG1EYzZXVXppWGlIb05lclpXTE43WGYrMDNNaGdDWTBIMkpJ?= =?utf-8?B?QkdWRzNJM0t6OEJzRG9hNURzR3BQVnExZTVSeHRBTmN1dW1wZzlMU3ZtcWsz?= =?utf-8?B?MTZLZHhuR2lyaHVZZEZVUGx3ZWc1Nmp2UGdGTjgyK3B6eVlQY0I5NlJEY0VU?= =?utf-8?B?TDY3MUtya2xHbUZzdTI3d254UzJPSStYaEdyOFlTT3RndUJTUUV3eWVaL005?= =?utf-8?B?THBOS0svV2RLR2xpOGtOM2kzUlR1ODB1d082VlBKb29xeXhZQ0hlNzNjREZo?= =?utf-8?B?NU84MFpUUEp0b0R3UDJNK0lNYWhBMEtPUmYwb1R5MXFJQklBMHhmbWlOdGZ0?= =?utf-8?B?M0NNeTdHdnJKb3hSWUZHbk5DUjFHYXBsTWMzQUhlKzNScDZ2MWFpdHNJaEJS?= =?utf-8?B?ZnhiWTNsY1N2VHRJemdoUWp3WS9qcE9HQ3k3STNSSmhWU0xiVkJUK3Vub3NJ?= =?utf-8?B?aUdVc3ltcHlOby9Rc0ZFQTV4a0oxWGNzNForQlozT3R0eFp1SEZSUEVURWc5?= =?utf-8?B?TkwxcDl0eGZLUkI0VXZWbG5VMkJTdkthK3NhdVhzK3k0WWtuektjNWxidXJH?= =?utf-8?B?d0FCOFJna1JVRDd2ZmtWSjBTZXU0MnVCUEdiV0VlZzRKS3RJYmdUNHlyMUtJ?= =?utf-8?B?T1B1S1BwN0JkSFR0OTZNNkxqaVlSK2ZKUkViYkhSYTd4cGxlTU1sQ3JTQUdl?= =?utf-8?B?ZlA0Mnh3NXZkTDZSai9oaEd3SURuLzNjSVhHR29YTUpxNXNDNTZORDdyQ2dx?= =?utf-8?B?QS9JYzZxS0IrLzZQMFM4YldaQklkODg3anpDL0lEdEVHUGNTMzVUVytlTXFn?= =?utf-8?B?dU5nZmRmVlBJQ1VLOCsxTFRsTGJMMlI2NUxOMFJ3UEo0UFBkZldkVDNMQ3Vo?= =?utf-8?B?YXd0QXVWWVpCOEZ4QnV5aVF4Qks5SzRTMTlzSnpUMDdZWUVTRHBITUtqWHFi?= =?utf-8?B?M3B2WVNGdDRnanNLUkNYakpBVFlzcVhqMTRya2Z0MlVLMFZDNDFxZ1JWQitF?= =?utf-8?B?R21WNVBGdE5kVlhvRVRDdEFBaExyQUg1bnJ4am9RWlB2cmVQa3pCSUJ2V1BK?= =?utf-8?B?UWVHWTJRZ3luNU1zWXQrck5BV0lqY01URTdYWk5zekNFaEJHeDk5UkFHM05s?= =?utf-8?Q?/4bVK/qT5ge+0Dt+bLEOXZOtgOUzUPELTPbiS6R?= X-MS-Exchange-CrossTenant-Network-Message-Id: 50def61c-e4af-4831-7a86-08d9318529da X-MS-Exchange-CrossTenant-AuthSource: BYAPR03MB3623.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2021 11:43:45.3550 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 335836de-42ef-43a2-b145-348c2ee9ca5b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NqnYZkrWCIkWnvM22EJM2AWMjXduI/bUTGPipQ3IrqWd3Gey2yrSYOr186ThXE/v1Pt0bPab2VhfQPc/PXuKol7y8+9HzLqp2DYuNzjEeSY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR03MB3798 X-OriginatorOrg: citrix.com On 17/06/2021 12:26, Jan Beulich wrote: > On 17.06.2021 13:09, Julien Grall wrote: >> On 16/06/2021 23:39, Bobbi Sanchez wrote: >>> how can i read the MSR Thermal Values under XEN-4.15.0 ? >>> >>> Usually without having XEN-4.15.0 installed i can read the MSR Thermal= =20 >>> Values like this: >>> >>> rdmsr -p 0 -d -f22:16 0x19c >>> >>> this works for my Core2Quod Q6600. >>> >>> But after having xen-4.15.0 installed and booted, same command shows no= w: 0 >> I believe the access was restricted as part of XSA-351 [1]. I am not=20 >> sure if there are a safe generic way to access them. I will let Andrew=20 >> and Jan commenting. > just as additional context (i.e. on top of Andrew's reply): It wasn't > that XSA, but our general switch of policy from blacklisting to > whitelisting MSRs. The XSA was about *_POWER_* and *_PERF_* MSRs. Well - that XSA was the trigger for finally removing default read access from all VMs, but yes - this specific issue described here only on Xen 4.15 and later. You can use boot with dom0=3Dmsr-relaxed to regain read access, but will still be subject to all the reasons I explained before about this not actually working properly. ~Andrew From xen-users-bounces@lists.xenproject.org Fri Jun 18 08:05:38 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 18 Jun 2021 08:05:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.144353.265698 (Exim 4.92) (envelope-from ) id 1lu9US-00060e-Di; Fri, 18 Jun 2021 08:04:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 144353.265698; Fri, 18 Jun 2021 08:04:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lu9US-00060W-AR; Fri, 18 Jun 2021 08:04:36 +0000 Received: by outflank-mailman (input) for mailman id 144353; Fri, 18 Jun 2021 08:04:34 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lu9UQ-00060Q-PM for xen-users@lists.xenproject.org; Fri, 18 Jun 2021 08:04:34 +0000 Received: from mail-ej1-x632.google.com (unknown [2a00:1450:4864:20::632]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 3d0bd3c8-cf95-4525-84f7-d7d9b1f47375; Fri, 18 Jun 2021 08:04:33 +0000 (UTC) Received: by mail-ej1-x632.google.com with SMTP id my49so14425200ejc.7 for ; Fri, 18 Jun 2021 01:04:33 -0700 (PDT) Received: from smtpclient.apple (200116b82449840020fdb8240c54b778.dip.versatel-1u1.de. [2001:16b8:2449:8400:20fd:b824:c54:b778]) by smtp.gmail.com with ESMTPSA id cf5sm5802648edb.81.2021.06.18.01.04.32 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Jun 2021 01:04:32 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 3d0bd3c8-cf95-4525-84f7-d7d9b1f47375 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=content-transfer-encoding:from:mime-version:date:subject:message-id :to; bh=utauYNKkmrEYKlspYuT+yYFT+HPLT/sNWcxAL/qHatU=; b=o6HPs6TNdkjTMG8XjWCOVmwxbfb9vxrJBrku7mp0sljOfAIHnb2eGiw5gdWwit+WzS oMrkFX4Rirfd6Fo/crVAq1rqcscshFdMRr8kzTu7IzSrTuEMFEF/vQpqcMasxq0CtwFF UrcCdblLSHxQXWAO3dr8wwZA+g8NzUiDN7zjMyLqhy4WU2VQKDNpXPiyG4fNg8yKvyoJ oVEhaKtxcXb51Ezl287GWK17He7/oMEnlv3P3+fnKCZDxF1btPkLxU80is/iByYS4rgA hTkyZrjFqGHUhF+rj5PIFkWeAgxpq72HdvFo3rlYWBNGDBcTq104x6DkXhHtO/DcTLUp 4Sqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:content-transfer-encoding:from:mime-version:date :subject:message-id:to; bh=utauYNKkmrEYKlspYuT+yYFT+HPLT/sNWcxAL/qHatU=; b=jWa5/Qd640Skrc8QCvXSPtEnfS/HFwzU3BbTc4inyiOXMNf4zah5+UZ8J7cx521Bdc 4kTJlb7DmHnAA2p3og3CwRbgF3XXDYdNd4Olfxt13NJBtjrVaJWujsifGMyOJ5VljtdK ydqXwzWCCc4NJ3WBpcOymXrk+e9T9WpCRPAXAkAtAGsgieN/Ejiqwy1XOsjDGtYCPBat XJyYZtlampg33+5vhTmAZFneHYQ87GPhxBcbb7mNfKTTTbRL6rJE4S+X7JJe0q1rSX6c MD1sAnAVOkwV8T1mHrL7YcYheZY7HHseegYO+90Q1/obbVAipiZr27/vhmaKdKvK2PKd bF5Q== X-Gm-Message-State: AOAM530ERR+zk65OpyRcSAsgfBnmqeFcX8SpNdeY2YzR8XplDkOgSOwG PmmsxU2nHAepwmiC15YLPZv3CKwB36Y= X-Google-Smtp-Source: ABdhPJwIIrE+CGASzlBFZ20cf3FZ8ULcZuRl0+5ODHFWTt/rJzhjAk4xZqeyZExPwodMPkp0QROo2w== X-Received: by 2002:a17:906:a043:: with SMTP id bg3mr9772806ejb.444.1624003472772; Fri, 18 Jun 2021 01:04:32 -0700 (PDT) Content-Type: multipart/alternative; boundary=Apple-Mail-7A5F5875-3882-4B5A-BFE1-524C45A9A0B1 Content-Transfer-Encoding: 7bit From: =?utf-8?Q?Jens_K=C3=BCbler?= Mime-Version: 1.0 (1.0) Date: Fri, 18 Jun 2021 10:04:31 +0200 Subject: XEN Block Script times out sporadically Message-Id: To: xen-users@lists.xenproject.org X-Mailer: iPhone Mail (18F72) --Apple-Mail-7A5F5875-3882-4B5A-BFE1-524C45A9A0B1 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hi I=E2=80=98m giving Xen on raspi 4 a try and experience some problems. Dom0 i= s Debian based and I start VMs via another process by forking xl create. Sporadically 50% of the time I so see libxl: error: libxl_aoutils.c:539:async_exec_timeout: killing execution of /= etc/xen/scripts/block add because of timeout And the vm falls to start. I set a lot of echos in the block script and veri= fied that the script runs not in a subshell and exits the main shell and ret= ournied fast enough. The block process remains as defunct in the process lis= t indicating that the caller did not read the state. I suspect the pipe between libxl sporadiccaly breaks due to a race. However I= cannot pinpoint where the start of the script is actually triggered during D= om creation. Looking through old posts I so see that other people had similar problems un= able to pinpoint the source of the condition. Any ideas where to look? Kind Regards Jens= --Apple-Mail-7A5F5875-3882-4B5A-BFE1-524C45A9A0B1 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable Hi

I=E2=80=98m giving Xe= n on raspi 4 a try and experience some problems. Dom0 is Debian based and I s= tart VMs via another process by forking xl create.

= Sporadically 50% of the time I so see
libxl: error: libxl_aoutils.c:= 539:async_exec_timeout: killing execution of /etc/xen/scripts/block add beca= use of timeout
And the vm falls t= o start. I set a lot of echos in the block script and verified that the scri= pt runs not in a subshell and exits the main shell and retournied fast enoug= h. The block process remains as defunct in the process list indicating that t= he caller did not read the state.
= I suspect the pipe between libxl sporadiccaly breaks due to a race. However I= cannot pinpoint where the start of the script is actually triggered during D= om creation.
Looking through old p= osts I so see that other people had similar problems unable to pinpoint the s= ource of the condition.

Any ideas where to look?

Kind Regards
Jens
= --Apple-Mail-7A5F5875-3882-4B5A-BFE1-524C45A9A0B1-- From xen-users-bounces@lists.xenproject.org Fri Jun 18 19:37:22 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 18 Jun 2021 19:37:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.144971.266771 (Exim 4.92) (envelope-from ) id 1luKIC-0006zu-Nq; Fri, 18 Jun 2021 19:36:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 144971.266771; Fri, 18 Jun 2021 19:36:40 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1luKIC-0006zn-KG; Fri, 18 Jun 2021 19:36:40 +0000 Received: by outflank-mailman (input) for mailman id 144971; Fri, 18 Jun 2021 19:36:39 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1luKIB-0006zh-6Q for xen-users@lists.xenproject.org; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=evoleotech.com; dmarc=pass action=none header.from=evoleotech.com; dkim=pass header.d=evoleotech.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=evoleotechnologies.onmicrosoft.com; s=selector2-evoleotechnologies-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=COHUFgZZtxjjSy1ZyJ0Te321qHZBzgEp42S8nQnTlkc=; b=ProltMcCfXRCfYGKEyvGyRcu/LwX19enDv9Ioj3lidllfmic+1dvsmDCNZJElkYbAhjJVwdYLUWGF4W2IwDlHwlXNbXlQITynEC6EnnbsVhWOSbSngFUiLqCN9cKyl8QCDRQ9o2yyUd9Dx41uyYHYuSR6pz66UE0r8uQ9sh0VKE= From: Prem Harikrishnan To: Stefano Stabellini CC: "xen-users@lists.xenproject.org" , "JOVITAC@xilinx.com" , "fnuv@xilinx.com" , "brian.woods@xilinx.com" Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit Thread-Topic: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit Thread-Index: AQHXOqMAPewhx/0ZVE2fbco7T/GOXKrdFmqAgACD+ICABAVYgIABrlVrgABJdgCAAATIt4AADpaAgARL642AAI9eAIABDuwsgAAXkYCADm9DhoAAJeiAgADiys+AAEjyAIAE2MzdgABzowCAAM/6LoAWBmGYgABBTYCABKooYQ== Date: Fri, 18 Jun 2021 19:36:31 +0000 Message-ID: References: , , , , ,, , In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: xilinx.com; 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boundary="_000_VI1PR05MB4430F1A749CB6AE4C3C1AC0B890D9VI1PR05MB4430eurp_" MIME-Version: 1.0 X-OriginatorOrg: evoleotech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR05MB4430.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 98e0bc45-ddb6-4e3d-ac65-08d932905fd5 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Jun 2021 19:36:31.3104 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 34ebafdc-9323-4bfe-8f24-6bb9f135b0a9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EOd27oA9bw9JSxtEAFmiz3KCxUl91l3ugGmsR3lYtBj6I0zt1ZR6Eabv8rToP7mSVJvEvQyU9yozWI5Ucru0jh2VquvZWQjxwZMlo72zhysNbzrUN2VZGoUwxOpw8YIJ X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR05MB6430 --_000_VI1PR05MB4430F1A749CB6AE4C3C1AC0B890D9VI1PR05MB4430eurp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Stefano, Thank you very much for your detailed reply. I now have xen booting from q= spi, i followed your instructions, the only additional thing i had to chang= e is the boot script offset in petalinux u boot config. Thank you again for= your support. Best Regards, Prem ________________________________ From: Stefano Stabellini Sent: Tuesday, June 15, 2021 22:17 To: Prem Harikrishnan Cc: Stefano Stabellini ; xen-users@lists.xenproject.or= g ; JOVITAC@xilinx.com = ; fnuv@xilinx.com ; brian.woods@xilinx.com Subject: Re: Help: Information required for AXI DMA passthrough for PL mast= ers in ZCU102 dev kit We don't have a recipe ready. It is not something we test. However I think it should be possible. The first step would be try to generate a BOOT.BIN for QSPI booting and write it to QSPI. The goal is to get to the u-boot prompt, with everything booted from QSPI. Then the next step is to add Xen, Linux, the DTB and Linux ramdisk. (Of course if you are OK with loading Xen and the other binaries from somewhere else like the SD card then it is going to work as is.) You should be able to write each binary to QSPI as separate partitions. At that point, you are only missing a boot.scr that can load them and boot. ImageBuilder supports custom u-boot load commands by setting the LOAD_CMD variable. In this case you'd need to set LOAD_CMD to something like "sf read", but given that the other command arguments are not filenames, ImageBuilder won't be able to handle it anyway. But you can take an ImageBuilder-generated boot.source, substitute the "tftpb" commands with the appropriate "sf read" commands and call mkimage to get a boot.scr. Now you should be able to run boot.scr from the u-boot prompt and load everything from QSPI. This is some relevant info: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842465/U-Boot+QSPI+= Driver I know it is a bit complex but I think it should work OK. On Tue, 15 Jun 2021, Prem Harikrishnan wrote: > Hi Stefano, > > Is it possible to boot XEN from QSPI? Is there an image builder script al= ready available to generate boot.scr? Please let me know. > Thanks and Best Regards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Xen-users on behalf of Pre= m Harikrishnan > Sent: Tuesday, June 1, 2021 18:07 > To: Mubin Usman Sayyed ; Stefano Stabellini > Cc: xen-users@lists.xenproject.org ; Jovi= ta Castelino > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > Hi Stefano and Mubin, > > Thank you very much for helping me setup up FreeRTOS and baremetal guests= , everything works as expected and I also get expected performance > in both baremetal and hypervisor guests. Thank you again for your prompt = support during the past few weeks. > > Best Regrards, > Prem > > _________________________________________________________________________= __________________________________________________________________ > From: Mubin Usman Sayyed > Sent: Tuesday, June 1, 2021 05:38 > To: Prem Harikrishnan ; Stefano Stabell= ini > Cc: xen-users@lists.xenproject.org ; Jovi= ta Castelino > Subject: RE: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > > In case of FreeRTOS, you need to use APIs from FreeRTOS port for interru= pt handling > (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freerto= s10_xilinx/examples/freertos_intr_example.c#L192 and line 194). > Please make sure that you are taking care of that in DMA interrupt exampl= e . > > > > Thanks, > > Mubin > > > > From: Prem Harikrishnan > Sent: Tuesday, June 1, 2021 2:48 AM > To: Stefano Stabellini > Cc: xen-users@lists.xenproject.org; Jovita Castelino = ; Mubin Usman Sayyed > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > > > > > > Hi Stefano and Mubin, > > Thank you very much for your replies. > > @Stefano Stabellini Sorry to bother you again, and thank you for pointing= this out, the TTC0 is by default enabled for FreeRTOS to generate > ticks, although this says only for R5 core, i would have never figured th= is out. As soon as I added the irqs and iomem and gave a xen > passthrough in the xen.dtsi as you have suggested, FreeRTOS guest started= working for other peripherals except for my DMA (FreeRTOS guest > does not work with interrupt and DMA). > > > > I can see my DMA is enabled because i have LEDs configured to blink for e= very interrupt I get from the PL. I don't see my interrupts being > processed, but when I destroy the guest, I get this output periodically w= hen an interrupt occurs. > > > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be seriou= s > (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSY= NR1 0x00000e80, GFSYNR2 0x00000000 > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be seriou= s > (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSY= NR1 0x00000e80, GFSYNR2 0x00000000 > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be seriou= s > (XEN) smmu: /smmu@fd800000: GFSR 0x80000002, GFSYNR0 0x00000002, GFSY= NR1 0x00000e80, GFSYNR2 0x00000000 > > > > From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/space= s/A/pages/18842066/Xen+and+PL+Masters > > Xen and PL Masters - Xilinx Wiki - Confluence > > 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs o= f PL masters must be added to the Linux Dom0 device tree. > Automated device tree generation does not generate the stream IDs for the= PL masters so that the user must add them into the device tree > manually. > > xilinx-wiki.atlassian.net > > The fault indicates an unidentified stream ID has been received by the SM= MU as shown in the GFSR register. The GFSYNR1 register contains > the stream ID that was unidentified. A stream ID of 0xE80 was unidentifie= d in the above fault. > > > > But I think i have already added that in my smmu and iommu in xen.dtsi be= cause my baremetal application works well as expected. I have > attached my xen.dtsi, system.dtsi, baremetal.cfg(working) and freertos.cf= g(not working). > > What could I be missing here? Do I have to enable the ttc0 in the device = tree? > > Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 Freq= : 99990 KHz mean when XEN boots up? > > Thanks, I look forward for your reply. > > > > Best Regards, > > Prem > > > > > > > ________________________________________________________________________= ________________________________________________________________ > > > From: Stefano Stabellini > Sent: Friday, May 28, 2021 20:43 > To: Prem Harikrishnan > Cc: Stefano Stabellini ; xen-users@lists.x= enproject.org ; JOVITAC@xilinx.com > ; MUBINUSM@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL ma= sters in ZCU102 dev kit > > > > From the gpa address, it looks like FreeRTOS is trying to access the TTC > timer? If you look at device tree, the corresponding node is > timer@ff110000. > > If FreeRTOS is configured to access the TTC timer, then you need to > assign it to it. Did you assign the TTC timer to the FreeRTOS domU by > any chance? > > You can do that by adding: > > irqs =3D [ 68, 69, 70 ] > iomem =3D [ "0xff110,1" ] > > > On Fri, 28 May 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > Thanks for your reply. I am pretty sure I followed the steps you mentio= ned below to run the FreeRTOS hello world example. I already added > > printfs and i can see XEN cannot start the scheduler and i get the foll= owing out put on XEN. > > > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D2 mem= flags=3D0xc0 (0 of 64) > > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > (XEN) sched_null.c:344: 1 <-- d2v0 > > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gva=3D0x= ff11000c gpa=3D0x000000ff11000c > > > > > > I also see that according to this article > > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-= as-a-Xen-Virtual-Machine/ba-p/947030 > > [52662iFAD1733707609204?v=3Dv2] > > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks = What is FreeRTOS? The FreeRTOS kernel is a market leading > real-time > > operating system for embedded systems. As embedded applications grow in= complexity, there is a growing need for a lightweight kernel > > capable of task scheduling... > > forums.xilinx.com > > FreeRTOS does not run out of the box for XEN, although the article is 2= years old, I am not sure if there are any updates on this after > > that. Can you please confirm? > > > > Thanks and Best Regards, > > Prem > > > >________________________________________________________________________= __________________________________________________________________ > _ > > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 02:51 > > To: Prem Harikrishnan > > Cc: Stefano Stabellini ; xen-users@lists= .xenproject.org ; > JOVITAC@xilinx.com > > ; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL = masters in ZCU102 dev kit > > +Mubin > > > > > > Hi Prem, > > > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > > FreeRTOS is built to run at EL3 by default so if that is not changed > > there are errors when run on any hypervisor. It is possible to build > > FreeRTOS to run on Xen but it requires a couple of manual steps: > > > > - source settings64.sh from Vitis builds > > - xsct > > - set WORKSPACE . > > - setws -switch $WORKSPACE > > - app create -name freertos-hello-world -template {FreeRTOS Hello World= } -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > > - bsp config stdin psu_uart_1 > > - bsp config stdout psu_uart_1 > > - bsp config hypervisor_guest true > > - Go to application source path and modify the linker script start addr= ess to 0x40000000, > > - app build -name freertos-hello-world > > - Run command to generate BIN file from executable "aarch64-linux-gnu-o= bjcopy -O binary --gap-fill 0 BOOT.BIN" > > > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > > might be able to provide additional info. > > > > > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > > Hi Stefano, > > > Sorry to bother you again. > > > I am currently trying to run my custom IP which sends periodic dma in= terrupts to the PS with cache coloring enabled. I have now > compiled > > my > > > guest running with FreeRTOS and it generates a trap. > > > Petalinux and VITIS IDE Version is 2020.2. > > > > > > Please find the log attached. After the trap occurs, for every interr= upt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context > fault: > > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config f= rom apu_freertos.cfg > > > (XEN) Dom1 colors: [ 8 ] > > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id=3D1 m= emflags=3D0xc0 (0 of 64) > > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache=3D0 > > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 cache=3D0 > > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > > (XEN) sched_null.c:344: 1 <-- d1v0 > > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x00000040013188 gva=3D= 0xff11000c gpa=3D0x000000ff11000c > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iov= a=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iov= a=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iov= a=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iov= a=3D0x41000000, fsynr=3D0x12, cb=3D1 > > > > > > The same application works as expected without FreeRTOS, i.e as a bar= emetal guest. I look forward for your comment on this. > > > > > > Although i see performance degradation, normally i can measure delta = time for each interrupt configured to 1ms (without XEN), with XEN > > for > > > the same measurement shows 16 ms for each interval (but the performan= ce is not a priority for now). > > > Thanks and Best Regards, > > > Prem > > > > >>_______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > Sent: Tuesday, May 18, 2021 20:09 > > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini ; xen-users@lis= ts.xenproject.org ; > > JOVITAC@xilinx.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for P= L masters in ZCU102 dev kit > > > Great to hear! Thank you for reporting back. > > > > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > > Dear Stefano, > > > > Thank you very much for your guidance and support. I finally fixed = the issue. I made an error in base memory address like you pointed > > > out. > > > > I actually modified the base address correctly to 0x40000000 but th= e default C code had an additional offset of 0x1100000 , and the > > DomU > > > > memory allocated was only 8MB. I either had to change the offset or= allocate more memory to the DomU guest which i missed until you > > > pointed > > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and = the SMID required is 0xE80. > > > > > > > > Thanks again i was able get my custom IP also working as an AXI mas= ter from PL. > > > > > > > > Best Regards, > > > > Prem > > > > > >>>______________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 02:35 > > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini ; Brian Woods= ; Julien Grall ; Stefano > > > > Stabellini ; xen-users@lists.xenproject.org= ; fnuv@xilinx.com > > ; > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim ; > > > > JOVITAC@xilinx.com > > > > Subject: Re: Help: Information required for AXI DMA passthrough for= PL masters in ZCU102 dev kit > > > > Your configuration looks correct as far as I can tell. > > > > > > > > You need dtdev because it triggers the SMMU configuration for your = PL > > > > block. You don't need device_tree because your baremetal applicatio= n is > > > > not going to read it, but it is not going to cause any issues eithe= r. > > > > > > > > When you say "the execution does not complete the loop at line 244"= , it > > > > means that you see the execution entering the loop and then never > > > > leaving? Like an infinite loop? > > > > > > > > If so, then I imagine the issue could be that the application is > > > > crashing when trying to access TxBufferPtr, which is pointing to > > > > TX_BUFFER_BASE, which is: > > > > > > > > > > > > #ifndef DDR_BASE_ADDR > > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > > DEFAULT SET TO 0x01000000 > > > > #define MEM_BASE_ADDR 0x01000000 > > > > #else > > > > #define MEM_BASE_ADDR (DDR_BASE_ADDR + 0x1000000) > > > > #endif > > > > > > > > #define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > > Hi Stefano, > > > > > Thanks again for your reply and your suggestion. I did try to re= place the Xil_DCacheFlushRange with > Xil_DCacheInvalidateRange(works > > > only > > > > > in EL3), I added printfs to debug, i can see that the execution d= oes not complete the loop at line 244 > > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorI= PLib/drivers/axidma/examples/xaxidma_example_simple_poll.c and > > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen = bootlog.txt. > > > > > I am still unable to find out why?? > > > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is cor= rect? and do i need dtdev and device_tree in my guest config file > > when > > > > it > > > > > is already added to xen.dtsi? > > > > > > > > > > Best Regards, > > > > > Prem > > > > > > > > > > > >>>>_____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini ; Brian Woo= ds ; Julien Grall ; > Stefano > > > > > Stabellini ; xen-users@lists.xenproject.o= rg ; fnuv@xilinx.com > > > ; > > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim > ; > > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit > > > > > Hi Prem, > > > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented usin= g > > > > > deprecated set/way instructions that are known to cause problems = in > > > > > virtualized environments. > > > > > > > > > > More recent implementations use the "dc civac" intruction that sh= ouldn't > > > > > have any issues. > > > > > > > > > > Can you double-check that you are calling the 64-bit version impl= emented > > > > > by CIVAC? > > > > > > >>>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f= 3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c#L > 4 > > 1 > > > 4 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > Hi Stefano, > > > > > > Thanks for your reply. Yes the axidma application is a baremeta= l application from the xilinx vitis ide example. > > > > > > Also yes, I have already run hello world as DomU guest, with UA= RT1. > > > > > > > > > > > > I am using the simple mode using polling and not interrupts(the= y are disabled in the c code), which is Why I didn't include in > the > > > > guest > > > > > > config file. This works well when I compile it normally (as EL3= ). When compiled as hypervisor guest, the execution stops before > the > > > > > > function xil_dcacheflushrange(). Please find the c code attache= d > > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProce= ssorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c > > > > > > > > > > > > I found the SATA example similar to my use case, also using DMA= and SMMU. I just used it as a reference to create my pl.dtb to > pass > > > > > through > > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > > > Thanks and Best Regards, > > > > > > Prem > > > > > > > > > > > > Get Outlook for Android > > > > > > > >>>>>____________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Stefano Stabellini > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > > To: Prem Harikrishnan > > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stab= ellini; xen-users@lists.xenproject.org; fnuv@xilinx.com; > > > > > edgari@xilinx.com; > > > > > > bwoods288@gmail.com; Renato Costa Amorim; JOVITAC@xilinx.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough= for PL masters in ZCU102 dev kit > > > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_= 1.bin" is > > > > > > a baremetal application? Can you run it successfully, just prin= ting > > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer o= n the > > > > > > Vivado configuration and SMID calculation. But I noticed that y= ou only > > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You hav= en't > > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.d= tsi, it > > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I = don't > > > > > > follow: I cannot see any SATA controller assignment in your > > > > > > configuration. > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > > > Thank you very much for your replies. > > > > > > > Hi Brian and Stefano, Can you please help me with the followi= ng questions? > > > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, wh= en i added my AXI DMA now running on simple polling > mode(previously > > i > > > > > tried > > > > > > it > > > > > > > with Scatter Gather mode), Run Automation automatically gener= ated, 1 AXI Interconnect and 1 smart connect. Since there is only > 1 > > > > master > > > > > > and > > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for = the stream IDs. > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1884206= 6/Xen+and+PL+Masters According to this link section 6.5 I have > > > manually > > > > > tied > > > > > > > of AxPROT bits to value of 0x2 to create non secure transacti= ons. Can you please confirm that my Vivado configuration is > correct? > > I > > > > can > > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated= from petalinux and system.dtsi also generated after manually > adding > > > > > > xen.dtsi. > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3846635= 61/Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using > > this > > > > > SATA > > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dm= a.cfg. I could really use your help to identify what is missing in > > my > > > > xen > > > > > > > configuration. > > > > > > > > > > > > > > Thanks and Best Regards, > > > > > > > Prem > > > > > > > > >>>>>>___________________________________________________________________= __________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > _ > > > > > > > From: Brian Woods > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > > To: Stefano Stabellini > > > > > > > Cc: Julien Grall ; Prem Harikrishnan ; Stefano Stabellini > > > ; > > > > > > > xen-users@lists.xenproject.org ; brian.woods@xilinx.com ; > fnuv@xilinx.com > > > > > > > ; edgari@xilinx.com ; bwo= ods288@gmail.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrou= gh for PL masters in ZCU102 dev kit > > > > > > > Prem, > > > > > > > > > > > > > > Sorry for the late email, I've been under the weather and hav= e been away > > > > > > > from my computer. In the Zynq SOCs this is how the SMMU IDs = in PL are > > > > > > > calculated: > > > > > > > > > > > > > > 14-10: TBU bits > > > > > > > 9-6: Master ID bits > > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug10= 85-zynq-ultrascale-trm.pdf > > > > > > > To look up the TBU value, see UG1085 and look for the "System= Masters" > > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs Li= st" table > > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out = in PL. > > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed o= n. There > > > > > > > are work arounds. Here's a couple of examples (with example = numbers): > > > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000001 > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000000 > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > > -> PS slave port 1 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000000 > > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0= 000000 > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000000 (both share) > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > > -> PS slave port 1 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000000 (both share) > > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0= 000000 (both share) > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS= slave port 0 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000001 (master #1) > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000002 (master #2) > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS= slave port 0 > > > > > > > -> PS= slave port 1 > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000001 (master #1) > > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0= 000001 (master #1) > > > > > > > TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0= 000002 (master #2) > > > > > > > TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0= 000002 (master #2) > > > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be functi= onally > > > > > > > replaced with "AXI Interconnect" to my knowledge. So the AXI= ID bits are > > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_= architecture_specification.pdf > > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > > > Let me know if this isn't clear or you have any other questio= ns. > > > > > > > > > > > > > > Brian > > > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini = wrote: > > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu10= 2 development board > > > > > > > > > > and i am trying to create a barematal application that = uses the AXI DMA on > > > > > > > > > > the programmable logic, using the scatter gather exampl= e from the xilinx > > > > > > > > > > repository. This works perfectly well for the baremetal= application. The > > > > > > > > > > diagram below represents the information flow. The AXI = DMA and the AXI data > > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA = is out of the box IP > > > > > > > > > > from Vivado and uses a single channel (Does not use AxU= SER) which means the > > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest= , in future this will > > > > > > > > > > be replaced by a custom IP with cache colouring enabled= . I want to pass > > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB alloca= ted to Dom-0) to > > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to genera= te my linux, xen > > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > > > From what i understand from the xilinx tutorials Xen+a= nd+PL+Masters > > > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get t= he correct address > > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu pr= operty for my AXI DMA > > > > > > > > > > and how to set the dtdev config for my hypervisor guest= . > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and= 2020.2 releases > > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > > > * 1:1 memory mappings for Xen virtual machines, ena= bling device > > > > > > > > > > assignments without SMMU > > > > > > > > > > * > > > > > > > > > > Static assignment of PL blocks, including bus-mas= tering blocks, to > > > > > > > > > > Xen virtual machines > > > > > > > > > > * Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised = by Xilinx. So I would > > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --_000_VI1PR05MB4430F1A749CB6AE4C3C1AC0B890D9VI1PR05MB4430eurp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Stefano,

Thank you very much for your detailed reply.  I now have xen boot= ing from qspi, i followed your instructions, the only additional thing i ha= d to change is the boot script offset in petalinux u boot config. Thank you= again for your support.

Best Regards,
Prem 
From: Stefano Stabellini &l= t;stefano.stabellini@xilinx.com>
Sent: Tuesday, June 15, 2021 22:17
To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
Cc: Stefano Stabellini <stefanos@xilinx.com>; xen-users@lists.= xenproject.org <xen-users@lists.xenproject.org>; JOVITAC@xilinx.com &= lt;JOVITAC@xilinx.com>; fnuv@xilinx.com <fnuv@xilinx.com>; brian.w= oods@xilinx.com <brian.woods@xilinx.com>
Subject: Re: Help: Information required for AXI DMA passthrough for = PL masters in ZCU102 dev kit
 
We don't have a recipe ready. It is not something = we test. However I
think it should be possible.

The first step would be try to generate a BOOT.BIN for QSPI booting and
write it to QSPI. The goal is to get to the u-boot prompt, with
everything booted from QSPI. Then the next step is to add Xen, Linux,
the DTB and Linux ramdisk. (Of course if you are OK with loading Xen and the other binaries from somewhere else like the SD card then it is going to work as is.)

You should be able to write each binary to QSPI as separate partitions.

At that point, you are only missing a boot.scr that can load them and
boot. ImageBuilder supports custom u-boot load commands by setting the
LOAD_CMD variable. In this case you'd need to set LOAD_CMD to something
like "sf read", but given that the other command arguments are no= t
filenames, ImageBuilder won't be able to handle it anyway.

But you can take an ImageBuilder-generated boot.source, substitute the
"tftpb" commands with the appropriate "sf read" command= s and call
mkimage to get a boot.scr.

Now you should be able to run boot.scr from the u-boot prompt and load
everything from QSPI.

This is some relevant info:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18= 842465/U-Boot+QSPI+Driver


I know it is a bit complex but I think it should work OK.



On Tue, 15 Jun 2021, Prem Harikrishnan wrote:
> Hi Stefano,
>
> Is it possible to boot XEN from QSPI? Is there an image builder script= already available to generate boot.scr? Please let me know.
> Thanks and Best Regards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Xen-users <xen-users-bounces@lists.xenproject.org> on beha= lf of Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Sent: Tuesday, June 1, 2021 18:07
> To: Mubin Usman Sayyed <MUBINUSM@xilinx.com>; Stefano Stabellini= <stefanos@xilinx.com>
> Cc: xen-users@lists.xenproject.org <xen-users@lists.xenproject.org&= gt;; Jovita Castelino <JOVITAC@xilinx.com>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
> Hi Stefano and Mubin,
>
> Thank you very much for helping me setup up FreeRTOS and baremetal gue= sts, everything works as expected and I also get expected performance
> in both baremetal and hypervisor guests. Thank you again for your prom= pt support during the past few weeks.
>
> Best Regrards,
> Prem
>
> ______________________________________________________________________= _____________________________________________________________________
> From: Mubin Usman Sayyed <MUBINUSM@xilinx.com>
> Sent: Tuesday, June 1, 2021 05:38
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; Stefan= o Stabellini <stefanos@xilinx.com>
> Cc: xen-users@lists.xenproject.org <xen-users@lists.xenproject.org&= gt;; Jovita Castelino <JOVITAC@xilinx.com>
> Subject: RE: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit  
>
> In case of FreeRTOS,  you need to use APIs from FreeRTOS port for= interrupt handling
>  (https://github.com/Xilinx/embeddedsw/blob/mast= er/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192 a= nd line 194).
> Please make sure that you are taking care of that in DMA interrupt exa= mple .
>
>  
>
> Thanks,
>
> Mubin
>
>  
>
> From: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Sent: Tuesday, June 1, 2021 2:48 AM
> To: Stefano Stabellini <stefanos@xilinx.com>
> Cc: xen-users@lists.xenproject.org; Jovita Castelino <JOVITAC@xilin= x.com>; Mubin Usman Sayyed <MUBINUSM@xilinx.com>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit
>
>  
>
>  
>
> Hi Stefano and Mubin,
>
> Thank you very much for your replies.
>
> @Stefano Stabellini Sorry to bother you again, and thank you for point= ing this out, the TTC0 is by default enabled for FreeRTOS to generate
> ticks, although this says only for R5 core, i would have never figured= this out. As soon as I added the irqs and iomem and gave a xen
> passthrough in the xen.dtsi as you have suggested, FreeRTOS guest star= ted working for other peripherals except for my DMA (FreeRTOS guest
> does not work with interrupt and DMA).
>
>  
>
> I can see my DMA is enabled because i have LEDs configured to blink fo= r every interrupt I get from the PL. I don't see my interrupts being
> processed, but when I destroy the guest, I get this output periodicall= y when an interrupt occurs.
>
>  
>
> (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be ser= ious
> (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x0= 0000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
>
> (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be ser= ious
> (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x0= 0000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
>
> (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be ser= ious
> (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x0= 0000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000
>
>  
>
> From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters
>
> Xen and PL Masters - Xilinx Wiki - Confluence
>
> 3.4 Stream IDs in the Device Tree. For Xen based systems the stream ID= s of PL masters must be added to the Linux Dom0 device tree.
> Automated device tree generation does not generate the stream IDs for = the PL masters so that the user must add them into the device tree
> manually.
>
> xilinx-wiki.atlassian.net
>
> The fault indicates an unidentified stream ID has been received by the= SMMU as shown in the GFSR register. The GFSYNR1 register contains
> the stream ID that was unidentified. A stream ID of 0xE80 was unidenti= fied in the above fault.
>
>  
>
> But I think i have already added that in my smmu and iommu in xen.dtsi= because my baremetal application works well as expected. I have
> attached my xen.dtsi, system.dtsi, baremetal.cfg(working) and freertos= .cfg(not working).
>
> What could I be missing here? Do I have to enable the ttc0 in the devi= ce tree?
>
> Also what does (XEN) Generic Timer IRQ: phys=3D30 hyp=3D26 virt=3D27 F= req: 99990 KHz mean when XEN boots up?
>
> Thanks, I look forward for your reply.
>
>  
>
> Best Regards,
>
> Prem
>
>  
>
>  
>
>
>  ________________________________________________________________= ________________________________________________________________________ >
>
> From: Stefano Stabellini <stefano.stabellini@xilinx.com>
> Sent: Friday, May 28, 2021 20:43
> To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com>
> Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen-user= s@lists.xenproject.org <xen-users@lists.xenproject.org>; JOVITAC@xili= nx.com
> <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xilinx.co= m>
> Subject: Re: Help: Information required for AXI DMA passthrough for PL= masters in ZCU102 dev kit
>
>  
>
> From the gpa address, it looks like FreeRTOS is trying to access the T= TC
> timer? If you look at device tree, the corresponding node is
> timer@ff110000.
>
> If FreeRTOS is configured to access the TTC timer, then you need to > assign it to it. Did you assign the TTC timer to the FreeRTOS domU by<= br> > any chance?
>
> You can do that by adding:
>
> irqs =3D [ 68, 69, 70 ]
> iomem =3D [ "0xff110,1" ]
>
>
> On Fri, 28 May 2021, Prem Harikrishnan wrote:
> > Hi Stefano,
> > Thanks for your reply. I am pretty sure I followed the steps you = mentioned below to run the FreeRTOS hello world example. I already added > > printfs and i can see XEN cannot start the scheduler and i get th= e following out put on XEN.
> >
> > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ]
> > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent: id= =3D2 memflags=3D0xc0 (0 of 64)
> > (XEN) memory_map:add: dom2 gfn=3Dff010 mfn=3Dff010 nr=3D1 cache= =3D0
> > (XEN) sched_null.c:344: 1 <-- d2v0
> > (XEN) traps.c:1973:d2v0 HSR=3D0x93820007 pc=3D0x00000040012b08 gv= a=3D0xff11000c gpa=3D0x000000ff11000c
> >
> >
> > I also see that according to this article
> > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a= -Xen-Virtual-Machine/ba-p/947030
> > [52662iFAD1733707609204?v=3Dv2]
> > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums
> > Contributed by Jeff Kubascik, Embedded Systems Engineer at Dorner= Works What is FreeRTOS? The FreeRTOS kernel is a market leading
> real-time
> > operating system for embedded systems. As embedded applications g= row in complexity, there is a growing need for a lightweight kernel
> > capable of task scheduling...
> > forums.xilinx.com
> > FreeRTOS does not run out of the box for XEN, although the articl= e is 2 years old, I am not sure if there are any updates on this after
> > that. Can you please confirm?
> >
> > Thanks and Best Regards,
> > Prem
> >
> >__________________________________________________________________= ________________________________________________________________________ > _
> > From: Stefano Stabellini <stefano.stabellini@xilinx.com> > > Sent: Friday, May 28, 2021 02:51
> > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>; xen= -users@lists.xenproject.org <xen-users@lists.xenproject.org>;
> JOVITAC@xilinx.com
> > <JOVITAC@xilinx.com>; MUBINUSM@xilinx.com <MUBINUSM@xili= nx.com>
> > Subject: Re: Help: Information required for AXI DMA passthrough f= or PL masters in ZCU102 dev kit  
> > +Mubin
> >
> >
> > Hi Prem,
> >
> > Did you make sure to build FreeRTOS as "hypervisor guest&quo= t;? I think
> > FreeRTOS is built to run at EL3 by default so if that is not chan= ged
> > there are errors when run on any hypervisor. It is possible to bu= ild
> > FreeRTOS to run on Xen but it requires a couple of manual steps:<= br> > >
> > - source settings64.sh from Vitis builds
> > - xsct
> > - set WORKSPACE .
> > - setws -switch $WORKSPACE
> > - app create -name freertos-hello-world -template {FreeRTOS Hello= World} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx
> > - bsp config stdin psu_uart_1
> > - bsp config stdout psu_uart_1
> > - bsp config hypervisor_guest true
> > - Go to application source path and modify the linker script star= t address to 0x40000000,
> > - app build -name freertos-hello-world
> > - Run command to generate BIN file from executable "aarch64-= linux-gnu-objcopy -O binary --gap-fill 0  <elf path> BOOT.BIN&qu= ot;
> >
> > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC= 'ed,
> > might be able to provide additional info.
> >
> >
> >
> > On Thu, 27 May 2021, Prem Harikrishnan wrote:
> > > Hi Stefano,
> > > Sorry to bother you again.
> > > I am currently trying to run my custom IP which sends period= ic dma interrupts to the PS with cache coloring enabled. I have now
> compiled
> > my
> > > guest running with FreeRTOS and it generates a trap.
> > > Petalinux and VITIS IDE Version is 2020.2.
> > >
> > > Please find the log attached. After the trap occurs, for eve= ry interrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context
> fault:
> > > fsr=3D0x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > >
> > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing= config from apu_freertos.cfg
> > > (XEN) Dom1 colors: [ 8 ]
> > > (XEN) memory.c:255:d0v0 Could not allocate order=3D9 extent:= id=3D1 memflags=3D0xc0 (0 of 64)
> > > (XEN) memory_map:add: dom1 gfn=3Dff010 mfn=3Dff010 nr=3D1 ca= che=3D0
> > > (XEN) memory_map:add: dom1 gfn=3Da0010 mfn=3Da0010 nr=3D1 ca= che=3D0
> > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > > (XEN) sched_null.c:344: 1 <-- d1v0
> > > (XEN) traps.c:1973:d1v0 HSR=3D0x93820007 pc=3D0x000000400131= 88 gva=3D0xff11000c gpa=3D0x000000ff11000c
> > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0= x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0= x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0= x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0= x402, iova=3D0x41000000, fsynr=3D0x12, cb=3D1
> > >
> > > The same application works as expected without FreeRTOS, i.e= as a baremetal guest. I look forward for your comment on this.
> > >
> > > Although i see performance degradation, normally i can measu= re delta time for each interrupt configured to 1ms (without XEN), with XEN<= br> > > for
> > > the same measurement shows 16 ms for each interval (but the = performance is not a priority for now).
> > > Thanks and Best Regards,
> > > Prem
> > >
> >>______________________________________________________________= ___________________________________________________________________________=
> _
> > _
> > > From: Stefano Stabellini <stefano.stabellini@xilinx.com&g= t;
> > > Sent: Tuesday, May 18, 2021 20:09
> > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.com&g= t;
> > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.com>= ; xen-users@lists.xenproject.org <xen-users@lists.xenproject.org>; > > JOVITAC@xilinx.com
> > > <JOVITAC@xilinx.com>
> > > Subject: Re: Help: Information required for AXI DMA passthro= ugh for PL masters in ZCU102 dev kit  
> > > Great to hear! Thank you for reporting back.
> > >
> > >
> > > On Tue, 18 May 2021, Prem Harikrishnan wrote:
> > > > Dear Stefano,
> > > > Thank you very much for your guidance and support. I fi= nally fixed the issue. I made an error in base memory address like you poin= ted
> > > out.
> > > > I actually modified the base address correctly to 0x400= 00000 but the default C code had an additional offset of 0x1100000 , and th= e
> > DomU
> > > > memory allocated was only 8MB. I either had to change t= he offset or allocate more memory to the DomU guest which i missed until yo= u
> > > pointed
> > > > out. Additionally i had to set to AxPROT bits to 0x2 in= Vivado and the SMID required is 0xE80.
> > > >
> > > > Thanks again i was able get my custom IP also working a= s an AXI master from PL.
> > > >
> > > > Best Regards,
> > > > Prem
> > > >
> >>>__________________________________________________________= ___________________________________________________________________________= ___
> _
> > _
> > > _
> > > > From: Stefano Stabellini <stefano.stabellini@xilinx.= com>
> > > > Sent: Tuesday, May 18, 2021 02:35
> > > > To: Prem Harikrishnan <prem.harikrishnan@evoleotech.= com>
> > > > Cc: Stefano Stabellini <stefano.stabellini@xilinx.co= m>; Brian Woods <brian.woods@xilinx.com>; Julien Grall <julien@= xen.org>; Stefano
> > > > Stabellini <sstabellini@kernel.org>; xen-users@li= sts.xenproject.org <xen-users@lists.xenproject.org>; fnuv@xilinx.com<= br> > > <fnuv@xilinx.com>;
> > > > edgari@xilinx.com <edgari@xilinx.com>; bwoods288@= gmail.com <bwoods288@gmail.com>; Renato Costa Amorim <renato.amori= m@evoleotech.com>;
> > > > JOVITAC@xilinx.com <JOVITAC@xilinx.com>
> > > > Subject: Re: Help: Information required for AXI DMA pas= sthrough for PL masters in ZCU102 dev kit  
> > > > Your configuration looks correct as far as I can tell.<= br> > > > >
> > > > You need dtdev because it triggers the SMMU configurati= on for your PL
> > > > block. You don't need device_tree because your baremeta= l application is
> > > > not going to read it, but it is not going to cause any = issues either.
> > > >
> > > > When you say "the execution does not complete the = loop at line 244", it
> > > > means that you see the execution entering the loop and = then never
> > > > leaving? Like an infinite loop?
> > > >
> > > > If so, then I imagine the issue could be that the appli= cation is
> > > > crashing when trying to access TxBufferPtr, which is po= inting to
> > > > TX_BUFFER_BASE, which is:
> > > >
> > > >
> > > > #ifndef DDR_BASE_ADDR
> > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS= .H, \
> > > >          &= nbsp;       DEFAULT SET TO 0x01000000
> > > > #define MEM_BASE_ADDR     &nbs= p;     0x01000000
> > > > #else
> > > > #define MEM_BASE_ADDR     &nbs= p;     (DDR_BASE_ADDR + 0x1000000)
> > > > #endif
> > > >
> > > > #define TX_BUFFER_BASE     &nb= sp;    (MEM_BASE_ADDR + 0x00100000)
> > > >
> > > >
> > > >
> > > > Can you double check that TX_BUFFER_BASE is pointing to= a correct
> > > > address? Memory starts at 0x40000000 in a Xen DomU.
> > > >
> > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly?=
> > > >
> > > >
> > > > On Mon, 17 May 2021, Prem Harikrishnan wrote:
> > > > > Hi Stefano,
> > > > > Thanks again for your reply and your suggestion.&n= bsp; I did try to replace the Xil_DCacheFlushRange with
> Xil_DCacheInvalidateRange(works
> > > only
> > > > > in EL3), I added printfs to debug, i can see that = the execution does not complete the loop at line 244
> > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drive= rs/axidma/examples/xaxidma_example_simple_poll.c  and
> > > > > Xil_DCacheFlushRange is not reached. Please find a= ttached my xen bootlog.txt.
> > > > > I am still unable to find out why??
> > > > >
> > > > > Can you please atleast verify that my xen.dtsi, an= d pl.dtb is correct? and do i need dtdev and device_tree in my guest config= file
> > when
> > > > it
> > > > > is already added to xen.dtsi?
> > > > >
> > > > > Best Regards,
> > > > > Prem
> > > > >
> > > > >
> >>>>______________________________________________________= ___________________________________________________________________________= ______
> _
> > _
> > > _
> > > > _
> > > > > From: Stefano Stabellini <stefano.stabellini@xi= linx.com>
> > > > > Sent: Saturday, May 15, 2021 00:25
> > > > > To: Prem Harikrishnan <prem.harikrishnan@evoleo= tech.com>
> > > > > Cc: Stefano Stabellini <stefano.stabellini@xili= nx.com>; Brian Woods <brian.woods@xilinx.com>; Julien Grall <ju= lien@xen.org>;
> Stefano
> > > > > Stabellini <sstabellini@kernel.org>; xen-use= rs@lists.xenproject.org <xen-users@lists.xenproject.org>; fnuv@xilinx= .com
> > > <fnuv@xilinx.com>;
> > > > > edgari@xilinx.com <edgari@xilinx.com>; bwood= s288@gmail.com <bwoods288@gmail.com>; Renato Costa Amorim
> <renato.amorim@evoleotech.com>;
> > > > > JOVITAC@xilinx.com <JOVITAC@xilinx.com>
> > > > > Subject: Re: Help: Information required for AXI DM= A passthrough for PL masters in ZCU102 dev kit  
> > > > > Hi Prem,
> > > > >
> > > > > Some older versions of Xil_DCacheFlushRange were i= mplemented using
> > > > > deprecated set/way instructions that are known to = cause problems in
> > > > > virtualized environments.
> > > > >
> > > > > More recent implementations use the "dc civac= " intruction that shouldn't
> > > > > have any issues.
> > > > >
> > > > > Can you double-check that you are calling the 64-b= it version implemented
> > > > > by CIVAC?
> > > > >
> >>>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47= ccb18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache= .c#L
> 4
> > 1
> > > 4
> > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:
> > > > > > Hi Stefano, 
> > > > > > Thanks for your reply. Yes the axidma applica= tion is a baremetal application from the xilinx vitis ide example.  > > > > > > Also yes, I have already run hello world as D= omU guest, with UART1.
> > > > > >
> > > > > > I am using the simple mode using polling and = not interrupts(they are disabled in the c code), which is Why I didn't incl= ude in
> the
> > > > guest
> > > > > > config file. This works well when I compile i= t normally (as EL3). When compiled as hypervisor guest, the execution stops= before
> the
> > > > > > function xil_dcacheflushrange(). Please find = the c code attached
> > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/Xi= linxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c 
> > > > > >
> > > > > > I found the SATA example similar to my use ca= se, also using DMA and SMMU. I just used it as a reference to create my pl.= dtb to
> pass
> > > > > through
> > > > > > in the guest config.(from pl.dtsi, which I ma= nually created).
> > > > > >
> > > > > > Thanks and Best Regards,
> > > > > > Prem
> > > > > >
> > > > > > Get Outlook for Android
> > > > > >
> >>>>>__________________________________________________= ___________________________________________________________________________= _________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > From: Stefano Stabellini <stefano.stabelli= ni@xilinx.com>
> > > > > > Sent: Friday 14 May 2021, 23:16
> > > > > > To: Prem Harikrishnan
> > > > > > Cc: Brian Woods; Stefano Stabellini; Julien G= rall; Stefano Stabellini; xen-users@lists.xenproject.org; fnuv@xilinx.com;<= br> > > > > > edgari@xilinx.com;
> > > > > > bwoods288@gmail.com; Renato Costa Amorim; JOV= ITAC@xilinx.com
> > > > > > Subject: Re: Help: Information required for A= XI DMA passthrough for PL masters in ZCU102 dev kit
> > > > > >
> > > > > > I take that the guest kernel "/bin/xaxid= ma_example_simple_poll_1.bin" is
> > > > > > a baremetal application? Can you run it succe= ssfully, just printing
> > > > > > "hello world", if you only assign t= he UART and nothing else?
> > > > > >
> > > > > > I am asking just to verify that you can run t= he baremetal VM
> > > > > > successfully, aside from the PL device assign= ment.
> > > > > >
> > > > > >
> > > > > > In regards to the PL device assignment, I'll = let Brian answer on the
> > > > > > Vivado configuration and SMID calculation. Bu= t I noticed that you only
> > > > > > assigned IRQ 54 to the DomU which is the one = for UART1. You haven't
> > > > > > assigned any IRQs for axi_dma_0. Looking at p= l_from_petalinux.dtsi, it
> > > > > > looks like there are two related IRQs: 121 an= d 122.
> > > > > >
> > > > > > Finally, why did you mention SATA passthrough= in your reply? I don't
> > > > > > follow: I cannot see any SATA controller assi= gnment in your
> > > > > > configuration.
> > > > > >
> > > > > >
> > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote:=
> > > > > > > Dear Brian, Stefano and Julien,
> > > > > > >
> > > > > > > Thank you very much for your replies. > > > > > > > Hi Brian and Stefano, Can you please hel= p me with the following questions?
> > > > > > >
> > > > > > > @Brian Woods Please find attached my viv= ado configuration, when i added my AXI DMA now running on simple polling > mode(previously
> > i
> > > > > tried
> > > > > > it
> > > > > > > with Scatter Gather mode), Run Automatio= n automatically generated, 1 AXI Interconnect and 1 smart connect. Since th= ere is only
> 1
> > > > master
> > > > > > and
> > > > > > > I use the S_AXI _HP0_FPD, I finally get = a value of 0xE80 for the stream IDs.
> > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+M= asters According to this link section 6.5 I have
> > > manually
> > > > > tied
> > > > > > > of AxPROT bits to value of 0x2 to create= non secure transactions. Can you please confirm that my Vivado configurati= on is
> correct?
> > I
> > > > can
> > > > > > > update you soon with an ILA trace on Viv= ado.
> > > > > > >
> > > > > > > @Stefano Stabellini Please find attached= my pl.dtsi generated from petalinux and system.dtsi also generated after m= anually
> adding
> > > > > > xen.dtsi.
> > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xe= n+Hypervisor+with+Petalinux+2020.1+and+2020.2 Using
> > this
> > > > > SATA
> > > > > > > passthrough, i made my own pl.dtsi for p= assthrough used in dma.cfg. I could really use your help to identify what i= s missing in
> > my
> > > > xen
> > > > > > > configuration.
> > > > > > >
> > > > > > > Thanks and Best Regards,
> > > > > > > Prem
> > > > > > >
> >>>>>>______________________________________________= ___________________________________________________________________________= ____________
> _
> > _
> > > _
> > > > _
> > > > > _
> > > > > > _
> > > > > > > From: Brian Woods <brian.woods@xilinx= .com>
> > > > > > > Sent: Thursday, May 13, 2021 17:13
> > > > > > > To: Stefano Stabellini <stefano.stabe= llini@xilinx.com>
> > > > > > > Cc: Julien Grall <julien@xen.org>;= Prem Harikrishnan <prem.harikrishnan@evoleotech.com>; Stefano Stabel= lini
> > > <sstabellini@kernel.org>;
> > > > > > > xen-users@lists.xenproject.org <xen-u= sers@lists.xenproject.org>; brian.woods@xilinx.com <brian.woods@xilin= x.com>;
> fnuv@xilinx.com
> > > > > > > <fnuv@xilinx.com>; edgari@xilinx.c= om <edgari@xilinx.com>; bwoods288@gmail.com <bwoods288@gmail.com&g= t;
> > > > > > > Subject: Re: Help: Information required = for AXI DMA passthrough for PL masters in ZCU102 dev kit  
> > > > > > > Prem,
> > > > > > >
> > > > > > > Sorry for the late email, I've been unde= r the weather and have been away
> > > > > > > from my computer.  In the Zynq SOCs= this is how the SMMU IDs in PL are
> > > > > > > calculated:
> > > > > > >
> > > > > > > 14-10: TBU bits
> > > > > > > 9-6: Master ID bits
> > > > > > > 5-0: AXI ID bits
> > > > > > >
> > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultras= cale-trm.pdf
> > > > > > > To look up the TBU value, see UG1085 and= look for the "System Masters"
> > > > > > > table which is table 16-4 on page 409. > > > > > > >
> > > > > > > For the master ID, see UG1085 and look f= or the "Master IDs List" table
> > > > > > > which is table 16-13 on page 429.
> > > > > > >
> > > > > > > The AXI ID bits is a bit trickery since = it's going to be out in PL.
> > > > > > > See: https://www.xilinx.com/support/answers/69447.htm= l
> > > > > > > With SmartConnect all the AXI IDs are 0,= they aren't passed on.  There
> > > > > > > are work arounds.  Here's a couple = of examples (with example numbers):
> > > > > > >
> > > > > > > AXI master -> PS slave port 0
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001
> > > > > > >
> > > > > > > AXI master -> SmartConnect -> PS s= lave port 0
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > > >
> > > > > > > AXI master -> SmartConnect -> PS s= lave port 0
> > > > > > >       &nbs= p;            &= nbsp;       -> PS slave port 1
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000
> > > > > > >
> > > > > > > Two AXI masters -> SmartConnect ->= PS slave port 0
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)=
> > > > > > >
> > > > > > > Two AXI masters -> SmartConnect ->= PS slave port 0
> > > > > > >       &nbs= p;            &= nbsp;            -&g= t; PS slave port 1
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share)=
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share)=
> > > > > > >
> > > > > > > Two AXI masters -> sideband -> Sma= rtConnect -> sideband -> PS slave port 0
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)<= br> > > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)<= br> > > > > > > >
> > > > > > > Two AXI masters -> sideband -> Sma= rtConnect -> sideband -> PS slave port 0
> > > > > > >       &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           -> PS = slave port 1
> > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1)<= br> > > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1)<= br> > > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2)<= br> > > > > > > >       &nbs= p; TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2)<= br> > > > > > > >
> > > > > > > The "sideband -> SmartConenct -&= gt; sideband" can also be functionally
> > > > > > > replaced with "AXI Interconnect&quo= t; to my knowledge.  So the AXI ID bits are
> > > > > > > fairly simple but with some caveats.
> > > > > > >
> > > > > > > You can also read in the SMMU faults fro= m Xen and use:
> > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_s= pecification.pdf
> > > > > > > to decode them. That should tell you the= SMMU IDs as well.
> > > > > > >
> > > > > > > Let me know if this isn't clear or you h= ave any other questions.
> > > > > > >
> > > > > > > Brian
> > > > > > >
> > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700= , Stefano Stabellini wrote:
> > > > > > > > On Mon, 10 May 2021, Julien Grall w= rote:
> > > > > > > > > On 26/04/2021 15:41, Prem Hari= krishnan wrote:
> > > > > > > > > > Hello everyone,
> > > > > > > > >
> > > > > > > > > Hi Prem,
> > > > > > > > >
> > > > > > > > > > I am using the latest ver= sion of the xilinx mpsoc zcu102 development board
> > > > > > > > > > and i am trying to create= a barematal application that uses the AXI DMA on
> > > > > > > > > > the programmable logic, u= sing the scatter gather example from the xilinx
> > > > > > > > > > repository. This works pe= rfectly well for the baremetal application. The
> > > > > > > > > > diagram below represents = the information flow. The AXI DMA and the AXI data
> > > > > > > > > > FIFO are in the Programab= le logic (FPGA). This AXI DMA is out of the box IP
> > > > > > > > > > from Vivado and uses a si= ngle channel (Does not use AxUSER) which means the
> > > > > > > > > > AXI ID cannot manually be= set.
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Now i want to make this a= s a baremetal hypervisor guest, in future this will
> > > > > > > > > > be replaced by a custom I= P with cache colouring enabled. I want to pass
> > > > > > > > > > through the AXI DMA in th= e PL. (Not to be used by Dom0)
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > I followed this tutorial = Baremetal + DomU
> > > > > > > > > > <ht= tps://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Mas= ters>
> > > > > > > > > > section 3 and MPSOC SMMU<= br> > > > > > > > > > > <https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841981/Zynq+U= ltraScale+MPSOC+SMMU>
> > > > > > > > > > section 4, stream ids are= required by the SMMU to get the correct address
> > > > > > > > > > translation.
> > > > > > > > > >
> > > > > > > > > > I am still unable to figu= re out how to get the iommu property for my AXI DMA
> > > > > > > > > > and how to set the dtdev = config for my hypervisor guest.
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > I can also see some new u= pdates with the XEN 2020.1 and 2020.2 releases
> > > > > > > > > > which i can be useful to = my application
> > > > > > > > > >
> > > > > > > > > >   *   = ;1:1 memory mappings for Xen virtual machines, enabling device
> > > > > > > > > >     a= ssignments without SMMU
> > > > > > > > > >   *
> > > > > > > > > >    &n= bsp;  Static assignment of PL blocks, including bus-mastering blocks, = to
> > > > > > > > > >     X= en virtual machines
> > > > > > > > > >   *   = ;Support for PL Device Passthrough to DomU in Xen
> > > > > > > > >
> > > > > > > > > You are usiong a version of Xe= n that has been customised by Xilinx. So I would
> > > > > > > > > recommend to contact them dire= ctly.
> > > > > > > > >
> > > > > > > > > I have CCed Stefano who might = be able to help you.
> > > > > > > >
> > > > > > > > Hi Julien,
> > > > > > > >
> > > > > > > > Many thanks for CC'ing me, I missed= the email.
> > > > > > > >
> > > > > > > >
> > > > > > > > Hi Prem,
> > > > > > > >
> > > > > > > > Let me CC a few people that might b= e able to help.
> > > > > > >
> > > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
>
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Thanks for letting me know. On Fri, 18 Jun 2021, Prem Harikrishnan wrote: > Hi Stefano, > > Thank you very much for your detailed reply.  I now have xen booting from qspi, i followed your instructions, the only additional thing i > had to change is the boot script offset in petalinux u boot config. Thank you again for your support. > > Best Regards, > Prem  > > ___________________________________________________________________________________________________________________________________________ > From: Stefano Stabellini > Sent: Tuesday, June 15, 2021 22:17 > To: Prem Harikrishnan > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; JOVITAC@xilinx.com > ; fnuv@xilinx.com ; brian.woods@xilinx.com > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > We don't have a recipe ready. It is not something we test. However I > think it should be possible. > > The first step would be try to generate a BOOT.BIN for QSPI booting and > write it to QSPI. The goal is to get to the u-boot prompt, with > everything booted from QSPI. Then the next step is to add Xen, Linux, > the DTB and Linux ramdisk. (Of course if you are OK with loading Xen and > the other binaries from somewhere else like the SD card then it is going > to work as is.) > > You should be able to write each binary to QSPI as separate partitions. > > At that point, you are only missing a boot.scr that can load them and > boot. ImageBuilder supports custom u-boot load commands by setting the > LOAD_CMD variable. In this case you'd need to set LOAD_CMD to something > like "sf read", but given that the other command arguments are not > filenames, ImageBuilder won't be able to handle it anyway. > > But you can take an ImageBuilder-generated boot.source, substitute the > "tftpb" commands with the appropriate "sf read" commands and call > mkimage to get a boot.scr. > > Now you should be able to run boot.scr from the u-boot prompt and load > everything from QSPI. > > This is some relevant info: > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842465/U-Boot+QSPI+Driver > > > I know it is a bit complex but I think it should work OK. > > > > On Tue, 15 Jun 2021, Prem Harikrishnan wrote: > > Hi Stefano, > > > > Is it possible to boot XEN from QSPI? Is there an image builder script already available to generate boot.scr? Please let me know. > > Thanks and Best Regards, > > Prem > > > >__________________________________________________________________________________________________________________________________________ > _ > > From: Xen-users on behalf of Prem Harikrishnan > > Sent: Tuesday, June 1, 2021 18:07 > > To: Mubin Usman Sayyed ; Stefano Stabellini > > Cc: xen-users@lists.xenproject.org ; Jovita Castelino > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > Hi Stefano and Mubin, > > > > Thank you very much for helping me setup up FreeRTOS and baremetal guests, everything works as expected and I also get expected > performance > > in both baremetal and hypervisor guests. Thank you again for your prompt support during the past few weeks. > > > > Best Regrards, > > Prem > > > >__________________________________________________________________________________________________________________________________________ > _ > > From: Mubin Usman Sayyed > > Sent: Tuesday, June 1, 2021 05:38 > > To: Prem Harikrishnan ; Stefano Stabellini > > Cc: xen-users@lists.xenproject.org ; Jovita Castelino > > Subject: RE: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > In case of FreeRTOS,  you need to use APIs from FreeRTOS port for interrupt handling > >  (https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c#L192 and line 194). > > Please make sure that you are taking care of that in DMA interrupt example . > > > >   > > > > Thanks, > > > > Mubin > > > >   > > > > From: Prem Harikrishnan > > Sent: Tuesday, June 1, 2021 2:48 AM > > To: Stefano Stabellini > > Cc: xen-users@lists.xenproject.org; Jovita Castelino ; Mubin Usman Sayyed > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > > > >   > > > >   > > > > Hi Stefano and Mubin, > > > > Thank you very much for your replies. > > > > @Stefano Stabellini Sorry to bother you again, and thank you for pointing this out, the TTC0 is by default enabled for FreeRTOS to > generate > > ticks, although this says only for R5 core, i would have never figured this out. As soon as I added the irqs and iomem and gave a xen > > passthrough in the xen.dtsi as you have suggested, FreeRTOS guest started working for other peripherals except for my DMA (FreeRTOS guest > > does not work with interrupt and DMA). > > > >   > > > > I can see my DMA is enabled because i have LEDs configured to blink for every interrupt I get from the PL. I don't see my interrupts > being > > processed, but when I destroy the guest, I get this output periodically when an interrupt occurs. > > > >   > > > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > > > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > > > > (XEN) smmu: /smmu@fd800000: Unexpected global fault, this could be serious > > (XEN) smmu: /smmu@fd800000:     GFSR 0x80000002, GFSYNR0 0x00000002, GFSYNR1 0x00000e80, GFSYNR2 0x00000000 > > > >   > > > > From section 3.6 of the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters > > > > Xen and PL Masters - Xilinx Wiki - Confluence > > > > 3.4 Stream IDs in the Device Tree. For Xen based systems the stream IDs of PL masters must be added to the Linux Dom0 device tree. > > Automated device tree generation does not generate the stream IDs for the PL masters so that the user must add them into the device tree > > manually. > > > > xilinx-wiki.atlassian.net > > > > The fault indicates an unidentified stream ID has been received by the SMMU as shown in the GFSR register. The GFSYNR1 register contains > > the stream ID that was unidentified. A stream ID of 0xE80 was unidentified in the above fault. > > > >   > > > > But I think i have already added that in my smmu and iommu in xen.dtsi because my baremetal application works well as expected. I have > > attached my xen.dtsi, system.dtsi, baremetal.cfg(working) and freertos.cfg(not working). > > > > What could I be missing here? Do I have to enable the ttc0 in the device tree? > > > > Also what does (XEN) Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 99990 KHz mean when XEN boots up? > > > > Thanks, I look forward for your reply. > > > >   > > > > Best Regards, > > > > Prem > > > >   > > > >   > > > > > >  ________________________________________________________________________________________________________________________________________ > > > > > > From: Stefano Stabellini > > Sent: Friday, May 28, 2021 20:43 > > To: Prem Harikrishnan > > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; > JOVITAC@xilinx.com > > ; MUBINUSM@xilinx.com > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > > > >   > > > > From the gpa address, it looks like FreeRTOS is trying to access the TTC > > timer? If you look at device tree, the corresponding node is > > timer@ff110000. > > > > If FreeRTOS is configured to access the TTC timer, then you need to > > assign it to it. Did you assign the TTC timer to the FreeRTOS domU by > > any chance? > > > > You can do that by adding: > > > > irqs = [ 68, 69, 70 ] > > iomem = [ "0xff110,1" ] > > > > > > On Fri, 28 May 2021, Prem Harikrishnan wrote: > > > Hi Stefano, > > > Thanks for your reply. I am pretty sure I followed the steps you mentioned below to run the FreeRTOS hello world example. I already > added > > > printfs and i can see XEN cannot start the scheduler and i get the following out put on XEN. > > > > > > Parsing config from freertos.cfg (XEN) Dom2 colors: [ 8 ] > > > (XEN) memory.c:255:d0v0 Could not allocate order=9 extent: id=2 memflags=0xc0 (0 of 64) > > > (XEN) memory_map:add: dom2 gfn=ff010 mfn=ff010 nr=1 cache=0 > > > (XEN) sched_null.c:344: 1 <-- d2v0 > > > (XEN) traps.c:1973:d2v0 HSR=0x93820007 pc=0x00000040012b08 gva=0xff11000c gpa=0x000000ff11000c > > > > > > > > > I also see that according to this article > > > https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Partner-FreeRTOS-as-a-Xen-Virtual-Machine/ba-p/947030 > > > [52662iFAD1733707609204?v=v2] > > > Partner: FreeRTOS as a Xen Virtual Machine - Community Forums > > > Contributed by Jeff Kubascik, Embedded Systems Engineer at DornerWorks What is FreeRTOS? The FreeRTOS kernel is a market leading > > real-time > > > operating system for embedded systems. As embedded applications grow in complexity, there is a growing need for a lightweight kernel > > > capable of task scheduling... > > > forums.xilinx.com > > > FreeRTOS does not run out of the box for XEN, although the article is 2 years old, I am not sure if there are any updates on this after > > > that. Can you please confirm? > > > > > > Thanks and Best Regards, > > > Prem > > > > >>_________________________________________________________________________________________________________________________________________ > _ > > _ > > > From: Stefano Stabellini > > > Sent: Friday, May 28, 2021 02:51 > > > To: Prem Harikrishnan > > > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; > > JOVITAC@xilinx.com > > > ; MUBINUSM@xilinx.com > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > +Mubin > > > > > > > > > Hi Prem, > > > > > > Did you make sure to build FreeRTOS as "hypervisor guest"? I think > > > FreeRTOS is built to run at EL3 by default so if that is not changed > > > there are errors when run on any hypervisor. It is possible to build > > > FreeRTOS to run on Xen but it requires a couple of manual steps: > > > > > > - source settings64.sh from Vitis builds > > > - xsct > > > - set WORKSPACE . > > > - setws -switch $WORKSPACE > > > - app create -name freertos-hello-world -template {FreeRTOS Hello World} -proc psu_cortexa53_0 -hw {xsa path} -os freertos10_xilinx > > > - bsp config stdin psu_uart_1 > > > - bsp config stdout psu_uart_1 > > > - bsp config hypervisor_guest true > > > - Go to application source path and modify the linker script start address to 0x40000000, > > > - app build -name freertos-hello-world > > > - Run command to generate BIN file from executable "aarch64-linux-gnu-objcopy -O binary --gap-fill 0  BOOT.BIN" > > > > > > The resulting BOOT.BIN can be started a Xen DomU guest. Mubin, CC'ed, > > > might be able to provide additional info. > > > > > > > > > > > > On Thu, 27 May 2021, Prem Harikrishnan wrote: > > > > Hi Stefano, > > > > Sorry to bother you again. > > > > I am currently trying to run my custom IP which sends periodic dma interrupts to the PS with cache coloring enabled. I have now > > compiled > > > my > > > > guest running with FreeRTOS and it generates a trap. > > > > Petalinux and VITIS IDE Version is 2020.2. > > > > > > > > Please find the log attached. After the trap occurs, for every interrupt XEN prints (XEN) smmu: /smmu@fd800000: Unhandled context > > fault: > > > > fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > > > > > root@pilbara:/etc/xen# xl create -c apu_freertos.cfg Parsing config from apu_freertos.cfg > > > > (XEN) Dom1 colors: [ 8 ] > > > > (XEN) memory.c:255:d0v0 Could not allocate order=9 extent: id=1 memflags=0xc0 (0 of 64) > > > > (XEN) memory_map:add: dom1 gfn=ff010 mfn=ff010 nr=1 cache=0 > > > > (XEN) memory_map:add: dom1 gfn=a0010 mfn=a0010 nr=1 cache=0 > > > > (XEN) smmu: /smmu@fd800000: d1: p2maddr 0x000000087f554000 > > > > (XEN) sched_null.c:344: 1 <-- d1v0 > > > > (XEN) traps.c:1973:d1v0 HSR=0x93820007 pc=0x00000040013188 gva=0xff11000c gpa=0x000000ff11000c > > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=0x402, iova=0x41000000, fsynr=0x12, cb=1 > > > > > > > > The same application works as expected without FreeRTOS, i.e as a baremetal guest. I look forward for your comment on this. > > > > > > > > Although i see performance degradation, normally i can measure delta time for each interrupt configured to 1ms (without XEN), with > XEN > > > for > > > > the same measurement shows 16 ms for each interval (but the performance is not a priority for now). > > > > Thanks and Best Regards, > > > > Prem > > > > > >>>________________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > From: Stefano Stabellini > > > > Sent: Tuesday, May 18, 2021 20:09 > > > > To: Prem Harikrishnan > > > > Cc: Stefano Stabellini ; xen-users@lists.xenproject.org ; > > > JOVITAC@xilinx.com > > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > Great to hear! Thank you for reporting back. > > > > > > > > > > > > On Tue, 18 May 2021, Prem Harikrishnan wrote: > > > > > Dear Stefano, > > > > > Thank you very much for your guidance and support. I finally fixed the issue. I made an error in base memory address like you > pointed > > > > out. > > > > > I actually modified the base address correctly to 0x40000000 but the default C code had an additional offset of 0x1100000 , and the > > > DomU > > > > > memory allocated was only 8MB. I either had to change the offset or allocate more memory to the DomU guest which i missed until you > > > > pointed > > > > > out. Additionally i had to set to AxPROT bits to 0x2 in Vivado and the SMID required is 0xE80. > > > > > > > > > > Thanks again i was able get my custom IP also working as an AXI master from PL. > > > > > > > > > > Best Regards, > > > > > Prem > > > > > > >>>>_______________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > From: Stefano Stabellini > > > > > Sent: Tuesday, May 18, 2021 02:35 > > > > > To: Prem Harikrishnan > > > > > Cc: Stefano Stabellini ; Brian Woods ; Julien Grall ; > Stefano > > > > > Stabellini ; xen-users@lists.xenproject.org ; fnuv@xilinx.com > > > ; > > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim > ; > > > > > JOVITAC@xilinx.com > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > > Your configuration looks correct as far as I can tell. > > > > > > > > > > You need dtdev because it triggers the SMMU configuration for your PL > > > > > block. You don't need device_tree because your baremetal application is > > > > > not going to read it, but it is not going to cause any issues either. > > > > > > > > > > When you say "the execution does not complete the loop at line 244", it > > > > > means that you see the execution entering the loop and then never > > > > > leaving? Like an infinite loop? > > > > > > > > > > If so, then I imagine the issue could be that the application is > > > > > crashing when trying to access TxBufferPtr, which is pointing to > > > > > TX_BUFFER_BASE, which is: > > > > > > > > > > > > > > > #ifndef DDR_BASE_ADDR > > > > > #warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \ > > > > >                  DEFAULT SET TO 0x01000000 > > > > > #define MEM_BASE_ADDR           0x01000000 > > > > > #else > > > > > #define MEM_BASE_ADDR           (DDR_BASE_ADDR + 0x1000000) > > > > > #endif > > > > > > > > > > #define TX_BUFFER_BASE          (MEM_BASE_ADDR + 0x00100000) > > > > > > > > > > > > > > > > > > > > Can you double check that TX_BUFFER_BASE is pointing to a correct > > > > > address? Memory starts at 0x40000000 in a Xen DomU. > > > > > > > > > > Maybe MEM_BASE_ADDR/DDR_BASE_ADDR is not set correctly? > > > > > > > > > > > > > > > On Mon, 17 May 2021, Prem Harikrishnan wrote: > > > > > > Hi Stefano, > > > > > > Thanks again for your reply and your suggestion.  I did try to replace the Xil_DCacheFlushRange with > > Xil_DCacheInvalidateRange(works > > > > only > > > > > > in EL3), I added printfs to debug, i can see that the execution does not complete the loop at line 244 > > > > > > https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c  and > > > > > > Xil_DCacheFlushRange is not reached. Please find attached my xen bootlog.txt. > > > > > > I am still unable to find out why?? > > > > > > > > > > > > Can you please atleast verify that my xen.dtsi, and pl.dtb is correct? and do i need dtdev and device_tree in my guest config > file > > > when > > > > > it > > > > > > is already added to xen.dtsi? > > > > > > > > > > > > Best Regards, > > > > > > Prem > > > > > > > > > > > > > >>>>>______________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > From: Stefano Stabellini > > > > > > Sent: Saturday, May 15, 2021 00:25 > > > > > > To: Prem Harikrishnan > > > > > > Cc: Stefano Stabellini ; Brian Woods ; Julien Grall ; > > Stefano > > > > > > Stabellini ; xen-users@lists.xenproject.org ; fnuv@xilinx.com > > > > ; > > > > > > edgari@xilinx.com ; bwoods288@gmail.com ; Renato Costa Amorim > > ; > > > > > > JOVITAC@xilinx.com > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > > > Hi Prem, > > > > > > > > > > > > Some older versions of Xil_DCacheFlushRange were implemented using > > > > > > deprecated set/way instructions that are known to cause problems in > > > > > > virtualized environments. > > > > > > > > > > > > More recent implementations use the "dc civac" intruction that shouldn't > > > > > > have any issues. > > > > > > > > > > > > Can you double-check that you are calling the 64-bit version implemented > > > > > > by CIVAC? > > > > > > > >>>>>https://github.com/Xilinx/embeddedsw/blob/875dcc7a4dca47ccb18eda0182f3577e598f8917/lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.c# > L > > 4 > > > 1 > > > > 4 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > > Hi Stefano,  > > > > > > > Thanks for your reply. Yes the axidma application is a baremetal application from the xilinx vitis ide example.  > > > > > > > Also yes, I have already run hello world as DomU guest, with UART1. > > > > > > > > > > > > > > I am using the simple mode using polling and not interrupts(they are disabled in the c code), which is Why I didn't include in > > the > > > > > guest > > > > > > > config file. This works well when I compile it normally (as EL3). When compiled as hypervisor guest, the execution stops before > > the > > > > > > > function xil_dcacheflushrange(). Please find the c code attached > > > > > > > in https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_poll.c  > > > > > > > > > > > > > > I found the SATA example similar to my use case, also using DMA and SMMU. I just used it as a reference to create my pl.dtb to > > pass > > > > > > through > > > > > > > in the guest config.(from pl.dtsi, which I manually created). > > > > > > > > > > > > > > Thanks and Best Regards, > > > > > > > Prem > > > > > > > > > > > > > > Get Outlook for Android > > > > > > > > >>>>>>_____________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > _ > > > > > > > From: Stefano Stabellini > > > > > > > Sent: Friday 14 May 2021, 23:16 > > > > > > > To: Prem Harikrishnan > > > > > > > Cc: Brian Woods; Stefano Stabellini; Julien Grall; Stefano Stabellini; xen-users@lists.xenproject.org; fnuv@xilinx.com; > > > > > > edgari@xilinx.com; > > > > > > > bwoods288@gmail.com; Renato Costa Amorim; JOVITAC@xilinx.com > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit > > > > > > > > > > > > > > I take that the guest kernel "/bin/xaxidma_example_simple_poll_1.bin" is > > > > > > > a baremetal application? Can you run it successfully, just printing > > > > > > > "hello world", if you only assign the UART and nothing else? > > > > > > > > > > > > > > I am asking just to verify that you can run the baremetal VM > > > > > > > successfully, aside from the PL device assignment. > > > > > > > > > > > > > > > > > > > > > In regards to the PL device assignment, I'll let Brian answer on the > > > > > > > Vivado configuration and SMID calculation. But I noticed that you only > > > > > > > assigned IRQ 54 to the DomU which is the one for UART1. You haven't > > > > > > > assigned any IRQs for axi_dma_0. Looking at pl_from_petalinux.dtsi, it > > > > > > > looks like there are two related IRQs: 121 and 122. > > > > > > > > > > > > > > Finally, why did you mention SATA passthrough in your reply? I don't > > > > > > > follow: I cannot see any SATA controller assignment in your > > > > > > > configuration. > > > > > > > > > > > > > > > > > > > > > On Fri, 14 May 2021, Prem Harikrishnan wrote: > > > > > > > > Dear Brian, Stefano and Julien, > > > > > > > > > > > > > > > > Thank you very much for your replies. > > > > > > > > Hi Brian and Stefano, Can you please help me with the following questions? > > > > > > > > > > > > > > > > @Brian Woods Please find attached my vivado configuration, when i added my AXI DMA now running on simple polling > > mode(previously > > > i > > > > > > tried > > > > > > > it > > > > > > > > with Scatter Gather mode), Run Automation automatically generated, 1 AXI Interconnect and 1 smart connect. Since there is > only > > 1 > > > > > master > > > > > > > and > > > > > > > > I use the S_AXI _HP0_FPD, I finally get a value of 0xE80 for the stream IDs. > > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842066/Xen+and+PL+Masters According to this link section 6.5 I have > > > > manually > > > > > > tied > > > > > > > > of AxPROT bits to value of 0x2 to create non secure transactions. Can you please confirm that my Vivado configuration is > > correct? > > > I > > > > > can > > > > > > > > update you soon with an ILA trace on Vivado. > > > > > > > > > > > > > > > > @Stefano Stabellini Please find attached my pl.dtsi generated from petalinux and system.dtsi also generated after manually > > adding > > > > > > > xen.dtsi. > > > > > > > > https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/384663561/Building+Xen+Hypervisor+with+Petalinux+2020.1+and+2020.2 > Using > > > this > > > > > > SATA > > > > > > > > passthrough, i made my own pl.dtsi for passthrough used in dma.cfg. I could really use your help to identify what is missing > in > > > my > > > > > xen > > > > > > > > configuration. > > > > > > > > > > > > > > > > Thanks and Best Regards, > > > > > > > > Prem > > > > > > > > > >>>>>>>____________________________________________________________________________________________________________________________________ > _ > > _ > > > _ > > > > _ > > > > > _ > > > > > > _ > > > > > > > _ > > > > > > > > From: Brian Woods > > > > > > > > Sent: Thursday, May 13, 2021 17:13 > > > > > > > > To: Stefano Stabellini > > > > > > > > Cc: Julien Grall ; Prem Harikrishnan ; Stefano Stabellini > > > > ; > > > > > > > > xen-users@lists.xenproject.org ; brian.woods@xilinx.com ; > > fnuv@xilinx.com > > > > > > > > ; edgari@xilinx.com ; bwoods288@gmail.com > > > > > > > > Subject: Re: Help: Information required for AXI DMA passthrough for PL masters in ZCU102 dev kit   > > > > > > > > Prem, > > > > > > > > > > > > > > > > Sorry for the late email, I've been under the weather and have been away > > > > > > > > from my computer.  In the Zynq SOCs this is how the SMMU IDs in PL are > > > > > > > > calculated: > > > > > > > > > > > > > > > > 14-10: TBU bits > > > > > > > > 9-6: Master ID bits > > > > > > > > 5-0: AXI ID bits > > > > > > > > > > > > > > > > https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf > > > > > > > > To look up the TBU value, see UG1085 and look for the "System Masters" > > > > > > > > table which is table 16-4 on page 409. > > > > > > > > > > > > > > > > For the master ID, see UG1085 and look for the "Master IDs List" table > > > > > > > > which is table 16-13 on page 429. > > > > > > > > > > > > > > > > The AXI ID bits is a bit trickery since it's going to be out in PL. > > > > > > > > See: https://www.xilinx.com/support/answers/69447.html > > > > > > > > With SmartConnect all the AXI IDs are 0, they aren't passed on.  There > > > > > > > > are work arounds.  Here's a couple of examples (with example numbers): > > > > > > > > > > > > > > > > AXI master -> PS slave port 0 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 > > > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 > > > > > > > > > > > > > > > > AXI master -> SmartConnect -> PS slave port 0 > > > > > > > >                            -> PS slave port 1 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 > > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 > > > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share) > > > > > > > > > > > > > > > > Two AXI masters -> SmartConnect -> PS slave port 0 > > > > > > > >                                 -> PS slave port 1 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000000 (both share) > > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000000 (both share) > > > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS slave port 0 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1) > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2) > > > > > > > > > > > > > > > > Two AXI masters -> sideband -> SmartConnect -> sideband -> PS slave port 0 > > > > > > > >                                                         -> PS slave port 1 > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000001 (master #1) > > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000001 (master #1) > > > > > > > >         TBU bits: 00001, Master ID bits: 0000, AXI ID bits: 0000002 (master #2) > > > > > > > >         TBU bits: 00001, Master ID bits: 0001, AXI ID bits: 0000002 (master #2) > > > > > > > > > > > > > > > > The "sideband -> SmartConenct -> sideband" can also be functionally > > > > > > > > replaced with "AXI Interconnect" to my knowledge.  So the AXI ID bits are > > > > > > > > fairly simple but with some caveats. > > > > > > > > > > > > > > > > You can also read in the SMMU faults from Xen and use: > > > > > > > > https://static.docs.arm.com/ihi0062/dc/IHI0062D_c_system_mmu_architecture_specification.pdf > > > > > > > > to decode them. That should tell you the SMMU IDs as well. > > > > > > > > > > > > > > > > Let me know if this isn't clear or you have any other questions. > > > > > > > > > > > > > > > > Brian > > > > > > > > > > > > > > > > On Mon, May 10, 2021 at 06:49:07PM -0700, Stefano Stabellini wrote: > > > > > > > > > On Mon, 10 May 2021, Julien Grall wrote: > > > > > > > > > > On 26/04/2021 15:41, Prem Harikrishnan wrote: > > > > > > > > > > > Hello everyone, > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > > > > > I am using the latest version of the xilinx mpsoc zcu102 development board > > > > > > > > > > > and i am trying to create a barematal application that uses the AXI DMA on > > > > > > > > > > > the programmable logic, using the scatter gather example from the xilinx > > > > > > > > > > > repository. This works perfectly well for the baremetal application. The > > > > > > > > > > > diagram below represents the information flow. The AXI DMA and the AXI data > > > > > > > > > > > FIFO are in the Programable logic (FPGA). This AXI DMA is out of the box IP > > > > > > > > > > > from Vivado and uses a single channel (Does not use AxUSER) which means the > > > > > > > > > > > AXI ID cannot manually be set. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Now i want to make this as a baremetal hypervisor guest, in future this will > > > > > > > > > > > be replaced by a custom IP with cache colouring enabled. I want to pass > > > > > > > > > > > through the AXI DMA in the PL. (Not to be used by Dom0) > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I followed this tutorial Baremetal + DomU > > > > > > > > > > > > > > > > > > > > > > guest changed the base address to 0x4000000,(1GB allocated to Dom-0) to > > > > > > > > > > > create my EL1 binary. I used Petalinux 2020.2 to generate my linux, xen > > > > > > > > > > > image and use tftp to boot. > > > > > > > > > > > > > > > > > > > > > >  From what i understand from the xilinx tutorials Xen+and+PL+Masters > > > > > > > > > > > > > > > > > > > > > > section 3 and MPSOC SMMU > > > > > > > > > > > > > > > > > > > > > > section 4, stream ids are required by the SMMU to get the correct address > > > > > > > > > > > translation. > > > > > > > > > > > > > > > > > > > > > > I am still unable to figure out how to get the iommu property for my AXI DMA > > > > > > > > > > > and how to set the dtdev config for my hypervisor guest. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I can also see some new updates with the XEN 2020.1 and 2020.2 releases > > > > > > > > > > > which i can be useful to my application > > > > > > > > > > > > > > > > > > > > > >   *   1:1 memory mappings for Xen virtual machines, enabling device > > > > > > > > > > >     assignments without SMMU > > > > > > > > > > >   * > > > > > > > > > > >       Static assignment of PL blocks, including bus-mastering blocks, to > > > > > > > > > > >     Xen virtual machines > > > > > > > > > > >   *   Support for PL Device Passthrough to DomU in Xen > > > > > > > > > > > > > > > > > > > > You are usiong a version of Xen that has been customised by Xilinx. So I would > > > > > > > > > > recommend to contact them directly. > > > > > > > > > > > > > > > > > > > > I have CCed Stefano who might be able to help you. > > > > > > > > > > > > > > > > > > Hi Julien, > > > > > > > > > > > > > > > > > > Many thanks for CC'ing me, I missed the email. > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Prem, > > > > > > > > > > > > > > > > > > Let me CC a few people that might be able to help. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > --8323329-246563793-1624295964=:24906-- From xen-users-bounces@lists.xenproject.org Thu Jun 24 08:10:18 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 08:10:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146472.269507 (Exim 4.92) (envelope-from ) id 1lwKQZ-0008AI-Rx; Thu, 24 Jun 2021 08:09:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146472.269507; Thu, 24 Jun 2021 08:09:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwKQZ-0008AA-Nj; Thu, 24 Jun 2021 08:09:35 +0000 Received: by outflank-mailman (input) for mailman id 146472; Thu, 24 Jun 2021 08:09:34 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwKQY-0008A4-BZ for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 08:09:34 +0000 Received: from mail-40138.protonmail.ch (unknown [185.70.40.138]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 8319bf1c-5941-4e0d-8e47-ba11209e26d3; Thu, 24 Jun 2021 08:09:31 +0000 (UTC) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 8319bf1c-5941-4e0d-8e47-ba11209e26d3 Date: Thu, 24 Jun 2021 08:09:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.ch; s=protonmail; t=1624522169; bh=iaoqOSkNZgcfzrw/M2PcT2Cgk4gyD3QIqrXvIZxb7ao=; h=Date:To:From:Reply-To:Subject:From; b=O+gGCPj2vxHrUSxtOkeKqcOIWjAWHKTcQBB95Qw2ZKJ5iEbxpUYKre5RYSktH03Wo +NL0dPASQdcAZFsSMn3bYWpp9j4XFVuSVCEnTZL8DxQUSuishwVRb/IdwsPkGg9TB/ zaagEGXQN7IVTokpumqIvnpVMQXEar1Nfx79/izo= To: "xen-users@lists.xenproject.org" From: mabi Reply-To: mabi Subject: Two redundant Xen servers with one SAN Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.2 required=10.0 tests=ALL_TRUSTED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM shortcircuit=no autolearn=disabled version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on mailout.protonmail.ch Hello, Is it possible with Xen on Debian 10 to have two Xen servers both directly = attached in a redundant way through HBA interfaces to a single SAN? The goal here would be to achieve higher availability of the Vms in case on= e Xen server is down for maintenance or because it is defective. This would= mean that the the virtual machines can continue to run on the second avail= able Xen server. The SAN would be used to store the virtual machines images= directly via LVM I guess. I did not find any Xen documentation or third-party howtos in order to do t= hat. Does anyone have any pointers to some documentation or hints? or maybe= this is simply not possible? Best regards, Mabi From xen-users-bounces@lists.xenproject.org Thu Jun 24 09:37:25 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 09:37:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146549.269641 (Exim 4.92) (envelope-from ) id 1lwLml-00061k-9i; Thu, 24 Jun 2021 09:36:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146549.269641; Thu, 24 Jun 2021 09:36:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwLml-00061c-6b; Thu, 24 Jun 2021 09:36:35 +0000 Received: by outflank-mailman (input) for mailman id 146549; Thu, 24 Jun 2021 09:36:34 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwLmj-00061V-MO for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 09:36:34 +0000 Received: from smtp.tiscali.it (unknown [213.205.33.215]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 093c4801-e535-4a30-a33c-37a4b472a6f4; Thu, 24 Jun 2021 09:36:31 +0000 (UTC) Received: from [192.168.200.10] ([91.254.8.183]) by santino.mail.tiscali.it with id LxcU2500U3wwlYB01xcU87; Thu, 24 Jun 2021 09:36:29 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 093c4801-e535-4a30-a33c-37a4b472a6f4 X-Spam-Final-Verdict: clean X-Spam-State: 0 X-Spam-Score: 0 X-Spam-Verdict: clean x-auth-user: g.d.monnezza@tiscali.it Subject: Re: Two redundant Xen servers with one SAN To: xen-users@lists.xenproject.org References: From: GD Message-ID: Date: Thu, 24 Jun 2021 11:36:27 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------5DB38B21C6E49C84F8E4CB09" Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tiscali.it; s=smtp; t=1624527389; bh=CHwilkwZ2w5dWo81WKZUgP2FI08VeOq0TFY65R6ySAg=; h=Subject:To:References:From:Date:In-Reply-To; b=OZheSZO8JTwK0cTLDd7tGHi33P4SjunlF3XUhtig/VnPMu7YqgqxFs6H8rPKvBDJz I51m2+BrNKbZnjMelHZdDAlM3GAyW7r5db29eVhxJfEM6OkrYE7xr7CyBIBmnEfoiy ux0+HRNFcKDxGunMZksWXiCfuFRDKlHW3TrBwvYI= This is a multi-part message in MIME format. --------------5DB38B21C6E49C84F8E4CB09 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Hi. In my opinion the goal you wish to achive is not reachable. Two identical VM on two different VM can't symultaneously run if the root filesystem is shared. The only way I can imagine is to have pseudo-HA, having a shared root filesystem for the two xen host, but only one running the the VM. When the running xen host goes down, you can (manually or via heartbeat script) start the VM(s) on the second xen host. Of course, the VM will have a boot-up time and probably a filesystem recovery. If you wish to have a full-HA solution, you have to setup two simultaneously running VMs each with its own root filesystem (and services configuration) on the two xen hosts, a shared data filesystem and an external load balancing service (HAproxy or NGINX rev proxy) in failover mode. Hope it helps g On 24/06/21 10:09, mabi wrote: > Hello, > > Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN? > > The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess. > > I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible? > > Best regards, > Mabi > > > > > > > > --------------5DB38B21C6E49C84F8E4CB09 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit Hi.
In my opinion the goal you wish to achive is not reachable.
Two identical VM on two different VM can't symultaneously run if the root filesystem is shared.

The only way I can imagine is to have pseudo-HA, having a shared root filesystem for the two xen host, but only one running the the VM.
When the running xen host goes down, you can (manually or via heartbeat script) start the VM(s) on the second xen host.
Of course, the VM will have a boot-up time and probably a filesystem recovery.

If you wish to have a full-HA solution, you have to setup two simultaneously running VMs each with its own root filesystem (and services configuration) on the two xen hosts, a shared data filesystem and an external load balancing service (HAproxy or NGINX rev proxy) in failover mode.

Hope it helps
g

On 24/06/21 10:09, mabi wrote:
Hello,

Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?

The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.

I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?

Best regards,
Mabi

--------------5DB38B21C6E49C84F8E4CB09-- From xen-users-bounces@lists.xenproject.org Thu Jun 24 10:28:58 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 10:28:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146612.269836 (Exim 4.92) (envelope-from ) id 1lwMav-00062V-RJ; Thu, 24 Jun 2021 10:28:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146612.269836; Thu, 24 Jun 2021 10:28:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwMav-00062N-O7; Thu, 24 Jun 2021 10:28:25 +0000 Received: by outflank-mailman (input) for mailman id 146612; Thu, 24 Jun 2021 10:28:24 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwMau-000628-OC for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 10:28:24 +0000 Received: from mail-wr1-x42f.google.com (unknown [2a00:1450:4864:20::42f]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id da1fbf8a-e351-4a31-b5c2-3b44c21c9806; Thu, 24 Jun 2021 10:28:23 +0000 (UTC) Received: by mail-wr1-x42f.google.com with SMTP id b3so6049439wrm.6 for ; Thu, 24 Jun 2021 03:28:23 -0700 (PDT) Received: from smtpclient.apple (ppp-93-104-190-119.dynamic.mnet-online.de. [93.104.190.119]) by smtp.gmail.com with ESMTPSA id n13sm2589200wms.37.2021.06.24.03.28.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Jun 2021 03:28:22 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: da1fbf8a-e351-4a31-b5c2-3b44c21c9806 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=dLwe8wFD1sImHxOdYVhoKDiFzblzWaBL2zrGzhUVjOM=; b=dJ2iWMen66o2MXRS6NM+1vGE81j+GOrkCi5n/Em91Sl2ber6vyobYn7kvCp7bzA1JB JPfblD86l0A7w0b6yrIvUoVd4ZAKQA5iKQOVPOwlPo8HxiSLgtxm6FjMxFXLXfRFOjur t62kgs32JPno2REb1xPtRlPB6K2FYZgSAeuUxjNiSkp43zrBpvhDTEn8N2yW6p/3D0Go JoXtClLuJYjbw8JquygPCMRbww51n9Hi1ltrExn6RSRac+T+aIh0GDbOd9OMsXgdGAj3 e2E2FoKWENh+uJC4uDP4IU9qVsYUpYZPJi7Iff6BDx5JefkMVGewQMn3/hhwHHd5nX9g FAJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=dLwe8wFD1sImHxOdYVhoKDiFzblzWaBL2zrGzhUVjOM=; b=Vg5O2quWQPwjtO3fJ08CdwXdfHNq5nR+6QyBG1s0lgvQxxE7q2tKZfRirtwmYDPCw4 U0/FDjuudTUXyx+65c7nLBbJX1oR+BqOvCwTNVUhX/LeNfYU1r5OYeItGOOBMlzupR01 iYYuLyjFC7g2uE9WkzerVrYzpkyXjAZknLUSViYmlLpITnu+2m2zdkhVbaJPSXvbrjoI gGbrznl97HBaYf/U4HVONAR7ob8X1Mw2F+D8T3n8dLicP5jcnxYpmSmPO8RI7qETD3gR FRUW3S1/Rm71ewd2EDJxxNCwD/mp8DS6AhiU14wt16Zo+guNlXQPMZWhc7n5pu03BvOH y5QA== X-Gm-Message-State: AOAM533TbyzRqm/nr7dvLM8aXowuEcgU/G9/iQOb8FVsPux8eyNYVIDL 6Q+2ChJSLb9vrXwwuVy/sXY= X-Google-Smtp-Source: ABdhPJxPX9/zpE9WG3ARmHOYDjoglx1kiHHlZYgHoEO4AF4wvpFN7gfXAdmHDoA3t9qIa3VEiYUNBA== X-Received: by 2002:adf:c3d4:: with SMTP id d20mr3593026wrg.183.1624530503026; Thu, 24 Jun 2021 03:28:23 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.100.0.2.22\)) Subject: Re: Two redundant Xen servers with one SAN From: Florian Heigl In-Reply-To: Date: Thu, 24 Jun 2021 12:28:21 +0200 Cc: "xen-users@lists.xenproject.org" Content-Transfer-Encoding: quoted-printable Message-Id: <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com> References: To: mabi X-Mailer: Apple Mail (2.3654.100.0.2.22) Hi, you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker. Don't forget to set up multipathd so your system can handle the = link/controller failovers. This has been done, and also has been/is a commonplace solution. There = is also lots of blog posts that you can dig up once you search the right = way. I would avoid running natively on SAN luns attached to VMs due the risk = of "the cluster stack had an error / was misconfigured". If you'd = failover manually that would be less of an issue. The clusters like = Pacemaker can protect the VMs a bit using SCSI reservations. There was also Remus for running 2 VMs in lockstep for HA, but that was = expecting no shared storage and was never polished by anyone to be = worthwhile for production use. A fair warning: Most homegrown HA setups like they're done commonly in = the ISP industry tend to blow up much more often than what a proper = solution should be like.=20 It might be better to pick something pre-made for that purpose if you = don't have the SAN/Cluster experience. I.e. XenServer/XCP or Oracle VM3. Good luck! Florian > Am 24.06.2021 um 10:09 schrieb mabi : >=20 > Hello, >=20 > Is it possible with Xen on Debian 10 to have two Xen servers both = directly attached in a redundant way through HBA interfaces to a single = SAN? >=20 > The goal here would be to achieve higher availability of the Vms in = case one Xen server is down for maintenance or because it is defective. = This would mean that the the virtual machines can continue to run on the = second available Xen server. The SAN would be used to store the virtual = machines images directly via LVM I guess. >=20 > I did not find any Xen documentation or third-party howtos in order to = do that. Does anyone have any pointers to some documentation or hints? = or maybe this is simply not possible? >=20 > Best regards, > Mabi >=20 >=20 >=20 >=20 >=20 >=20 >=20 >=20 From xen-users-bounces@lists.xenproject.org Thu Jun 24 11:17:16 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 11:17:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146710.270099 (Exim 4.92) (envelope-from ) id 1lwNLk-0001HJ-1k; Thu, 24 Jun 2021 11:16:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146710.270099; Thu, 24 Jun 2021 11:16:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwNLj-0001HB-S8; Thu, 24 Jun 2021 11:16:47 +0000 Received: by outflank-mailman (input) for mailman id 146710; Thu, 24 Jun 2021 11:16:46 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwNLi-0001H5-3e for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 11:16:46 +0000 Received: from mail-4319.protonmail.ch (unknown [185.70.43.19]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 0e77aa94-a7ce-4baf-bfd3-3c9ef87fc61b; Thu, 24 Jun 2021 11:16:42 +0000 (UTC) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 0e77aa94-a7ce-4baf-bfd3-3c9ef87fc61b Date: Thu, 24 Jun 2021 11:16:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.ch; s=protonmail; t=1624533401; bh=43NOeeA5826wblKl2SZT+eGjQ6mgIwd2gtDaSS9sohc=; h=Date:To:From:Cc:Reply-To:Subject:In-Reply-To:References:From; b=JF+JNLdjUXCcyISilsbSmcsUxMka3CgAMnVo2S+46yWJnTWnC4jx7/tmqCv0vrTS7 Aa22HoifoX4OR4qPjtxvTMgTfjVPO0AhYtadHxCbK0Pievw/3IvjNOFZjph7iMiZz0 pPJVCCW3yRTtYGqJ6GPxQKMmZ4vyOILtywRK1pss= To: Florian Heigl From: mabi Cc: "xen-users@lists.xenproject.org" Reply-To: mabi Subject: Re: Two redundant Xen servers with one SAN Message-ID: In-Reply-To: <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com> References: <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.2 required=10.0 tests=ALL_TRUSTED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM shortcircuit=no autolearn=disabled version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on mailout.protonmail.ch Thanks Florian and GD for your answers. I should have been more precise, I am looking into building a active/passiv= e dual node Xen installation. I don't need active/active as I believe this = is also more dangerous. Also I was thinking that I would manually failover the VM whenever necessar= y in order not to rely on additional external tools such as corosync/pacema= ker and hence avoid more complexity. So as you notice, at least for a start, I am trying to keep things as simpl= e as possible. If I understand correctly that should be possible with Xen a= nd all I need is multipathd and CLVM, is this correct? Then regarding CLVM, I checked Debian buster but could not find any CLVM-re= lated pacakges. Is maybe CLVM not available on Debian? Regards, Mabi =E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90 Original Me= ssage =E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90 On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl wrote: > Hi, > > you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker. > > Don't forget to set up multipathd so your system can handle the link/cont= roller failovers. > > This has been done, and also has been/is a commonplace solution. There is= also lots of blog posts that you can dig up once you search the right way. > > I would avoid running natively on SAN luns attached to VMs due the risk o= f "the cluster stack had an error / was misconfigured". If you'd failover m= anually that would be less of an issue. The clusters like Pacemaker can pro= tect the VMs a bit using SCSI reservations. > > There was also Remus for running 2 VMs in lockstep for HA, but that was e= xpecting no shared storage and was never polished by anyone to be worthwhil= e for production use. > > A fair warning: Most homegrown HA setups like they're done commonly in th= e ISP industry tend to blow up much more often than what a proper solution = should be like. > > It might be better to pick something pre-made for that purpose if you don= 't have the SAN/Cluster experience. > > I.e. XenServer/XCP or Oracle VM3. > > Good luck! > > Florian > > > Am 24.06.2021 um 10:09 schrieb mabi mabi@protonmail.ch: > > > > Hello, > > > > Is it possible with Xen on Debian 10 to have two Xen servers both direc= tly attached in a redundant way through HBA interfaces to a single SAN? > > > > The goal here would be to achieve higher availability of the Vms in cas= e one Xen server is down for maintenance or because it is defective. This w= ould mean that the the virtual machines can continue to run on the second a= vailable Xen server. The SAN would be used to store the virtual machines im= ages directly via LVM I guess. > > > > I did not find any Xen documentation or third-party howtos in order to = do that. Does anyone have any pointers to some documentation or hints? or m= aybe this is simply not possible? > > > > Best regards, > > > > Mabi From xen-users-bounces@lists.xenproject.org Thu Jun 24 11:45:20 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 11:45:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146747.270172 (Exim 4.92) (envelope-from ) id 1lwNmt-0007NA-HW; Thu, 24 Jun 2021 11:44:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146747.270172; Thu, 24 Jun 2021 11:44:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwNmt-0007N2-EG; Thu, 24 Jun 2021 11:44:51 +0000 Received: by outflank-mailman (input) for mailman id 146747; Thu, 24 Jun 2021 11:44:49 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwNmr-0007Mw-Iv for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 11:44:49 +0000 Received: from mail-ed1-x52c.google.com (unknown [2a00:1450:4864:20::52c]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 81b629c2-0065-4c63-b32c-490a5512a224; Thu, 24 Jun 2021 11:44:48 +0000 (UTC) Received: by mail-ed1-x52c.google.com with SMTP id df12so8096072edb.2 for ; Thu, 24 Jun 2021 04:44:48 -0700 (PDT) Received: from smtpclient.apple (pd95c9906.dip0.t-ipconnect.de. [217.92.153.6]) by smtp.gmail.com with ESMTPSA id jz12sm1060868ejc.94.2021.06.24.04.44.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Jun 2021 04:44:47 -0700 (PDT) X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 81b629c2-0065-4c63-b32c-490a5512a224 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=ICdHQDlCzjhFBpd5OW5hza4rrRzj+FYsaEVzTbTZctU=; b=QZSRLw1EEIwINwRxpb8rbq8+5xNoZZX3GtTJ7BndH3L1TGhtZ2QvRDUH7nqH1jpt/3 v+S156vssFar4+LjOWMU12jEfFIc7xVciT7eaL0RbbBCVwh2LqVypeHDIqSAz0aqqiZ/ KwBgCWKnpkNEUCGStYGEMyKRg6AMS1JuNDONcKlwf43XJk1k5oqoIGJ9WJwXiRLqPCdj OFXCIP4igB8EhCBVpH91ie6W0BR/+8iPq+1Gz5m6ezWmlrbc3ZyeSUvOITBzb17eolQR 1fszVn0yTnmbO+92AuJVNSvAPPbkqymnBZbvFkwbyHaEVIq2sR1ntvmJo73ifcynpL9Q tt4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=ICdHQDlCzjhFBpd5OW5hza4rrRzj+FYsaEVzTbTZctU=; b=kcBa5OqL3Hoyft14Cw44URyg1KuLpwNW0OXluB5rIpFvy+WnRltxk0FvplZFZU4CP4 5vFXWk/8pHRjpGCrvvr/fUDv3FIJgtsftP0USAYZdjxuE3leTyiBOpuemrIqSTVMPUbo 8SsXQpnUmpI82dK7FR38PEI7ixJItSe07qF6Bly1kY1A5piEl592YEOU8HvNqQPzV0Hw WGVAN50mjJc+rMZ4iPrMlrWFaoD+zK5Cm14Hd5aiQUh8ksEEWLf1vkNubdwSfAYW6scP unV2s7aPa8eUEvelhYA3JFV49s5UvnNC/jt/o6vBD6PHyvYJvrVfXjHcQdvxj7eWrpic ji2A== X-Gm-Message-State: AOAM530Mbsa/SsIURj3WF+SkgAcehIkMBmnhME6FUf+/N1CljH6pxDKt jrbVrT6EkcnBRPV2XSiZn6k= X-Google-Smtp-Source: ABdhPJy9efJorNGEdYePZdY81jtGFdSuprkFzWbZSyQoCEm6pfOMHCr7YkCVrt49lXsyDHx4J+Zw5Q== X-Received: by 2002:a05:6402:26c7:: with SMTP id x7mr6411322edd.383.1624535087555; Thu, 24 Jun 2021 04:44:47 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.100.0.2.22\)) Subject: Re: Two redundant Xen servers with one SAN From: Florian Heigl In-Reply-To: Date: Thu, 24 Jun 2021 13:44:45 +0200 Cc: "xen-users@lists.xenproject.org" Content-Transfer-Encoding: quoted-printable Message-Id: <468BBB18-E803-46DA-BFE5-1B75D7F26C30@gmail.com> References: <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com> To: mabi X-Mailer: Apple Mail (2.3654.100.0.2.22) Hi, > Am 24.06.2021 um 13:16 schrieb mabi : >=20 > So as you notice, at least for a start, I am trying to keep things as = simple as possible. If I understand correctly that should be possible = with Xen and all I need is multipathd and CLVM, is this correct? That sounds just fine. You must not enable autostart of the VMs on either host, so i.e. keep = the configs elsewhere than /etc/xen/auto (iirc). You should put in some extra effort to keep the configs in sync, i have = in the past used csync2 for that. > Then regarding CLVM, I checked Debian buster but could not find any = CLVM-related pacakges. Is maybe CLVM not available on Debian? It might be an outdated solution, i searched quickly and found this: "=46rom SUSE Linux Enterprise 15 onward, we use lvmlockd as the LVM2 = cluster extension, rather than clvmd. Make sure the clvmd daemon is not = running, ..." Maybe you can find something in that direction.= From xen-users-bounces@lists.xenproject.org Thu Jun 24 14:05:38 2021 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Thu, 24 Jun 2021 14:05:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.146787.270244 (Exim 4.92) (envelope-from ) id 1lwPyS-00062p-Jd; Thu, 24 Jun 2021 14:04:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 146787.270244; Thu, 24 Jun 2021 14:04:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwPyS-00062h-Fm; Thu, 24 Jun 2021 14:04:56 +0000 Received: by outflank-mailman (input) for mailman id 146787; Thu, 24 Jun 2021 14:04:54 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lwPyQ-00062P-Hn for xen-users@lists.xenproject.org; Thu, 24 Jun 2021 14:04:54 +0000 Received: from smtp.tiscali.it (unknown [213.205.33.216]) by us1-rack-iad1.inumbo.com (Halon) with ESMTP id 466b9789-83fa-4f11-9eff-6b67fa223e37; Thu, 24 Jun 2021 14:04:52 +0000 (UTC) Received: from [192.168.200.10] ([91.254.8.183]) by michael.mail.tiscali.it with id M24q2500U3wwlYB0124qZp; Thu, 24 Jun 2021 14:04:51 +0000 X-BeenThere: xen-users@lists.xenproject.org List-Id: Xen user discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-users-bounces@lists.xenproject.org Precedence: list Sender: "Xen-users" X-Inumbo-ID: 466b9789-83fa-4f11-9eff-6b67fa223e37 X-Spam-Final-Verdict: clean X-Spam-State: 0 X-Spam-Score: 0 X-Spam-Verdict: clean x-auth-user: g.d.monnezza@tiscali.it Subject: Re: Two redundant Xen servers with one SAN To: xen-users@lists.xenproject.org References: <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com> From: GD Message-ID: <548faf9b-a95b-211a-7433-b26e3d7b3491@tiscali.it> Date: Thu, 24 Jun 2021 16:04:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------CEB14FC9419D3ACFC4931EEF" Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tiscali.it; s=smtp; t=1624543491; bh=7DTCFv6yfE+7osbczEEVspvGWTHscwfrmOa3QqWTeFA=; h=Subject:To:References:From:Date:In-Reply-To; b=aQyileFQtA8T7UjQC3A+EpO8uxSD/RwcldoqeZ+VA93faOVmQRTChF7ll+KMXdHTf 14RyIThijqfCizVVvD3AQgq0Np/qyX9Dny1SjpCVRWefUruvntwAjSIQ165U4m300k z/pFTa4bJPlLBwYBhV7VOuufd6ohSyXT2aaFKFIc= This is a multi-part message in MIME format. --------------CEB14FC9419D3ACFC4931EEF Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit "I should have been more precise, I am looking into building a active/passive dual node Xen installation " In this case, you can configure a simple but robust architecture I'm already running: Two Xen Server, storing VMs in LV built on top of DRBD. It's up to you if create a DRBD-LV pair for each VM (as I did in my setup) or a single DRBD-LVG Both Xen host are running, but VMs are running on the host having the DRBD(s) active. Xen hosts shares VM conf files (and other stuffs as iptables forwarding rules) in a csync'd directory. When the "active" Xen host dies, you can quickly boot up the VMs on the other Xen host after switching the DRBD volumes into "primary" mode. If xen's VMs confs are the same, you'll end up with the same VMs with the same IPs (if in a LAN, they immediatly work, othewise you have to change the routing in previous-hop) In this scenario, you can also think to go further (as i did) and run a "cross-configuration" with both Xen server running VMs on an active DRBD, but holding the passive DRBD of the other server. This way you can run half of the VMs on a server and the other half on the other server ;) Side notes: - On a 1Gb/s eth link it works for low global disk write rates. 10GB fiber/eth link is required for high disk write rates such as in storage servers. - Be careful to disk write speed: I experienced dramatic slow down with Debian 10 when booted Xen kernel (comparison made against regular kernel boot) Hope it helps g On 24/06/21 13:16, mabi wrote: > Thanks Florian and GD for your answers. > > I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous. > > Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity. > > So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct? > > Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian? > > Regards, > Mabi > > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ > > On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl wrote: > >> Hi, >> >> you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker. >> >> Don't forget to set up multipathd so your system can handle the link/controller failovers. >> >> This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way. >> >> I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations. >> >> There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use. >> >> A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like. >> >> It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience. >> >> I.e. XenServer/XCP or Oracle VM3. >> >> Good luck! >> >> Florian >> >>> Am 24.06.2021 um 10:09 schrieb mabi mabi@protonmail.ch: >>> >>> Hello, >>> >>> Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN? >>> >>> The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess. >>> >>> I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible? >>> >>> Best regards, >>> >>> Mabi --------------CEB14FC9419D3ACFC4931EEF Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit "I should have been more precise, I am looking into building a active/passive dual node Xen installation "

In this case, you can configure a simple but robust architecture I'm already running:
Two Xen Server, storing VMs in LV built on top of DRBD. It's up to you if create a DRBD-LV pair for each VM (as I did in my setup) or a single DRBD-LVG
Both Xen host are running, but VMs are running on the host having the DRBD(s) active. Xen hosts shares VM conf files (and other stuffs as iptables forwarding rules) in a csync'd directory.
When the "active" Xen host dies, you can quickly boot up the VMs on the other Xen host after switching the DRBD volumes into "primary" mode.
If xen's VMs confs are the same, you'll end up with the same VMs with the same IPs (if in a LAN, they immediatly work, othewise you have to change the routing in previous-hop)

In this scenario, you can also think to go further (as i did) and run a "cross-configuration" with both Xen server running VMs on an active DRBD, but holding the passive DRBD of the other server. This way you can run half of the VMs on a server and the other half on the other server ;)

Side notes:
- On a 1Gb/s eth link it works for low global disk write rates. 10GB fiber/eth link is required for high disk write rates such as in storage servers.
- Be careful to disk write speed: I experienced dramatic slow down with Debian 10 when booted Xen kernel (comparison made against regular kernel boot)

Hope it helps
g
 
On 24/06/21 13:16, mabi wrote:
Thanks Florian and GD for your answers.

I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous.

Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity.

So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct?

Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian?

Regards,
Mabi

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐

On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl <florian.heigl@gmail.com> wrote:


Hi,

you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker.

Don't forget to set up multipathd so your system can handle the link/controller failovers.

This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way.

I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations.

There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use.

A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like.

It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience.

I.e. XenServer/XCP or Oracle VM3.

Good luck!

Florian


Am 24.06.2021 um 10:09 schrieb mabi mabi@protonmail.ch:

Hello,

Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?

The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.

I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?

Best regards,

Mabi


    

    

  


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Subject: Re: Two redundant Xen servers with one SAN
To: xen-users@lists.xenproject.org
References: 
 <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com>
 
 <548faf9b-a95b-211a-7433-b26e3d7b3491@tiscali.it>
From: GD 
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P.S. for sync'd directory, I used "lsyncd", not csync.

On 24/06/21 16:04, GD wrote:
> "I should have been more precise, I am looking into building a 
> active/passive dual node Xen installation "
>
> In this case, you can configure a simple but robust architecture I'm 
> already running:
> Two Xen Server, storing VMs in LV built on top of DRBD. It's up to you 
> if create a DRBD-LV pair for each VM (as I did in my setup) or a 
> single DRBD-LVG
> Both Xen host are running, but VMs are running on the host having the 
> DRBD(s) active. Xen hosts shares VM conf files (and other stuffs as 
> iptables forwarding rules) in a csync'd directory.
> When the "active" Xen host dies, you can quickly boot up the VMs on 
> the other Xen host after switching the DRBD volumes into "primary" mode.
> If xen's VMs confs are the same, you'll end up with the same VMs with 
> the same IPs (if in a LAN, they immediatly work, othewise you have to 
> change the routing in previous-hop)
>
> In this scenario, you can also think to go further (as i did) and run 
> a "cross-configuration" with both Xen server running VMs on an active 
> DRBD, but holding the passive DRBD of the other server. This way you 
> can run half of the VMs on a server and the other half on the other 
> server ;)
>
> Side notes:
> - On a 1Gb/s eth link it works for low global disk write rates. 10GB 
> fiber/eth link is required for high disk write rates such as in 
> storage servers.
> - Be careful to disk write speed: I experienced dramatic slow down 
> with Debian 10 when booted Xen kernel (comparison made against regular 
> kernel boot)
>
> Hope it helps
> g
>
> On 24/06/21 13:16, mabi wrote:
>> Thanks Florian and GD for your answers.
>>
>> I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous.
>>
>> Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity.
>>
>> So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct?
>>
>> Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian?
>>
>> Regards,
>> Mabi
>>
>> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
>>
>> On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl  wrote:
>>
>>> Hi,
>>>
>>> you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker.
>>>
>>> Don't forget to set up multipathd so your system can handle the link/controller failovers.
>>>
>>> This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way.
>>>
>>> I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations.
>>>
>>> There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use.
>>>
>>> A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like.
>>>
>>> It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience.
>>>
>>> I.e. XenServer/XCP or Oracle VM3.
>>>
>>> Good luck!
>>>
>>> Florian
>>>
>>>> Am 24.06.2021 um 10:09 schrieb mabimabi@protonmail.ch:
>>>>
>>>> Hello,
>>>>
>>>> Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?
>>>>
>>>> The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.
>>>>
>>>> I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?
>>>>
>>>> Best regards,
>>>>
>>>> Mabi
>


--------------A8F7A2672F2D2B9458CB5876
Content-Type: text/html; charset=utf-8
Content-Transfer-Encoding: 8bit


  
    
  
  
    P.S. for sync'd directory, I used "lsyncd", not
      csync.

    

    
On 24/06/21 16:04, GD wrote:

    

    

      
      "I should have been more precise, I am
      looking into building a active/passive dual node Xen installation
      "

        

        In this case, you can configure a simple but robust architecture
        I'm already running:

        Two Xen Server, storing VMs in LV built on top of DRBD. It's up
        to you if create a DRBD-LV pair for each VM (as I did in my
        setup) or a single DRBD-LVG

        Both Xen host are running, but VMs are running on the host
        having the DRBD(s) active. Xen hosts shares VM conf files (and
        other stuffs as iptables forwarding rules) in a csync'd
        directory.

        When the "active" Xen host dies, you can quickly boot up the VMs
        on the other Xen host after switching the DRBD volumes into
        "primary" mode.

        If xen's VMs confs are the same, you'll end up with the same VMs
        with the same IPs (if in a LAN, they immediatly work, othewise
        you have to change the routing in previous-hop)

        

        In this scenario, you can also think to go further (as i did)
        and run a "cross-configuration" with both Xen server running VMs
        on an active DRBD, but holding the passive DRBD of the other
        server. This way you can run half of the VMs on a server and the
        other half on the other server ;) 

        

        Side notes:

        - On a 1Gb/s eth link it works for low global disk write rates.
        10GB fiber/eth link is required for high disk write rates such
        as in storage servers.

        - Be careful to disk write speed: I experienced dramatic slow
        down with Debian 10 when booted Xen kernel (comparison made
        against regular kernel boot)

        

        Hope it helps

        g

       

      
On 24/06/21 13:16, mabi wrote:

      

      

        
Thanks Florian and GD for your answers.

I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous.

Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity.

So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct?

Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian?

Regards,
Mabi

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐

On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl <florian.heigl@gmail.com> wrote:



        

          
Hi,

you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker.

Don't forget to set up multipathd so your system can handle the link/controller failovers.

This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way.

I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations.

There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use.

A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like.

It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience.

I.e. XenServer/XCP or Oracle VM3.

Good luck!

Florian



          

            
Am 24.06.2021 um 10:09 schrieb mabi mabi@protonmail.ch:

Hello,

Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?

The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.

I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?

Best regards,

Mabi


          

        

      

      

    

    

  


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Subject: Re: Two redundant Xen servers with one SAN
To: mabi 
Cc: xen-users@lists.xenproject.org
References: 
 <8AE60F63-3886-4247-BA9C-D83DD6555481@gmail.com>
 
 <548faf9b-a95b-211a-7433-b26e3d7b3491@tiscali.it>
 
From: GD 
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Maybe a different approach can helps: if the large data amount is 
essentially at rest for most of the time, you can think to share it as 
simple NFS4 shared directories (better file lock mechanism than NFS3) ad 
expose them to a kubernetes cluster running small&fast "VM" (pods, 
docker instances)
You can run a redundant (two) kubernetes controllers and two kubernetes 
nodes. You can set up this scenario with two bare-metal server. If a 
server dies the cluster survives by replicating automatically the pods 
(VMs) on the second node.
This is nearly a full-HA solution. But it doesn't make use of xen, so 
you have to change discussion list :D

g

On 24/06/21 16:20, mabi wrote:
> Thank you GD for the details regarding a DRBD setup. I was also 
> thinking of such a solution but the underlying VMs will have virtual 
> drives which are are in the TB range, probably 5-10 TB. As far as I 
> know a sync/resync of the DRBD-LV for such a VM woulf take ages even 
> over a 10 Gbit/s fiber link. This is the reason why I was thinking I 
> should go for a SAN.
>
>
> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> On Thursday, June 24th, 2021 at 4:04 PM, GD  
> wrote:
>
>> "I should have been more precise, I am looking into building a 
>> active/passive dual node Xen installation "
>>
>> In this case, you can configure a simple but robust architecture I'm 
>> already running:
>> Two Xen Server, storing VMs in LV built on top of DRBD. It's up to 
>> you if create a DRBD-LV pair for each VM (as I did in my setup) or a 
>> single DRBD-LVG
>> Both Xen host are running, but VMs are running on the host having the 
>> DRBD(s) active. Xen hosts shares VM conf files (and other stuffs as 
>> iptables forwarding rules) in a csync'd directory.
>> When the "active" Xen host dies, you can quickly boot up the VMs on 
>> the other Xen host after switching the DRBD volumes into "primary" mode.
>> If xen's VMs confs are the same, you'll end up with the same VMs with 
>> the same IPs (if in a LAN, they immediatly work, othewise you have to 
>> change the routing in previous-hop)
>>
>> In this scenario, you can also think to go further (as i did) and run 
>> a "cross-configuration" with both Xen server running VMs on an active 
>> DRBD, but holding the passive DRBD of the other server. This way you 
>> can run half of the VMs on a server and the other half on the other 
>> server ;)
>>
>> Side notes:
>> - On a 1Gb/s eth link it works for low global disk write rates. 10GB 
>> fiber/eth link is required for high disk write rates such as in 
>> storage servers.
>> - Be careful to disk write speed: I experienced dramatic slow down 
>> with Debian 10 when booted Xen kernel (comparison made against 
>> regular kernel boot)
>>
>> Hope it helps
>> g
>>
>> On 24/06/21 13:16, mabi wrote:
>>> Thanks Florian and GD for your answers.
>>>
>>> I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous.
>>>
>>> Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity.
>>>
>>> So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct?
>>>
>>> Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian?
>>>
>>> Regards,
>>> Mabi
>>>
>>> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
>>>
>>> On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl    wrote:
>>>
>>>> Hi,
>>>>
>>>> you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker.
>>>>
>>>> Don't forget to set up multipathd so your system can handle the link/controller failovers.
>>>>
>>>> This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way.
>>>>
>>>> I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations.
>>>>
>>>> There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use.
>>>>
>>>> A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like.
>>>>
>>>> It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience.
>>>>
>>>> I.e. XenServer/XCP or Oracle VM3.
>>>>
>>>> Good luck!
>>>>
>>>> Florian
>>>>
>>>>> Am 24.06.2021 um 10:09 schrieb mabimabi@protonmail.ch  :
>>>>>
>>>>> Hello,
>>>>>
>>>>> Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?
>>>>>
>>>>> The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.
>>>>>
>>>>> I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Mabi
>>


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    Maybe a different approach can helps: if the large
      data amount is essentially at rest for most of the time, you can
      think to share it as simple NFS4 shared directories (better file
      lock mechanism than NFS3) ad expose them to a kubernetes cluster
      running small&fast "VM" (pods, docker instances)

      You can run a redundant (two) kubernetes controllers and two
      kubernetes nodes. You can set up this scenario with two bare-metal
      server. If a server dies the cluster survives by replicating
      automatically the pods (VMs) on the second node.

      This is nearly a full-HA solution. But it doesn't make use of xen,
      so you have to change discussion list :D

      

      g  

    

    
On 24/06/21 16:20, mabi wrote:

    

    

      
      
Thank you GD for the details regarding a DRBD setup. I was
        also thinking of such a solution but the underlying VMs will
        have virtual drives which are are in the TB range, probably 5-10
        TB. As far as I know a sync/resync of the DRBD-LV for such a VM
        woulf take ages even over a 10 Gbit/s fiber link. This is the
        reason why I was thinking I should go for a SAN.

      

      

        

          


          

        

      

      


      

      

        
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐

        

        
 On Thursday, June 24th, 2021 at 4:04 PM, GD
          <g.d.monnezza@tiscali.it> wrote:

        

      

      


      

      
 "I
        should have been more precise, I am looking into building a
        active/passive dual node Xen installation "

          

          In this case, you can configure a simple but robust
          architecture I'm already running:

          Two Xen Server, storing VMs in LV built on top of DRBD. It's
          up to you if create a DRBD-LV pair for each VM (as I did in my
          setup) or a single DRBD-LVG

          Both Xen host are running, but VMs are running on the host
          having the DRBD(s) active. Xen hosts shares VM conf files (and
          other stuffs as iptables forwarding rules) in a csync'd
          directory.

          When the "active" Xen host dies, you can quickly boot up the
          VMs on the other Xen host after switching the DRBD volumes
          into "primary" mode.

          If xen's VMs confs are the same, you'll end up with the same
          VMs with the same IPs (if in a LAN, they immediatly work,
          othewise you have to change the routing in previous-hop)

          

          In this scenario, you can also think to go further (as i did)
          and run a "cross-configuration" with both Xen server running
          VMs on an active DRBD, but holding the passive DRBD of the
          other server. This way you can run half of the VMs on a server
          and the other half on the other server ;) 

          

          Side notes:

          - On a 1Gb/s eth link it works for low global disk write
          rates. 10GB fiber/eth link is required for high disk write
          rates such as in storage servers.

          - Be careful to disk write speed: I experienced dramatic slow
          down with Debian 10 when booted Xen kernel (comparison made
          against regular kernel boot)

          

          Hope it helps

          g

         

        
On 24/06/21 13:16, mabi wrote:

        

        

          
Thanks Florian and GD for your answers.

I should have been more precise, I am looking into building a active/passive dual node Xen installation. I don't need active/active as I believe this is also more dangerous.

Also I was thinking that I would manually failover the VM whenever necessary in order not to rely on additional external tools such as corosync/pacemaker and hence avoid more complexity.

So as you notice, at least for a start, I am trying to keep things as simple as possible. If I understand correctly that should be possible with Xen and all I need is multipathd and CLVM, is this correct?

Then regarding CLVM, I checked Debian buster but could not find any CLVM-related pacakges. Is maybe CLVM not available on Debian?

Regards,
Mabi

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐

On Thursday, June 24th, 2021 at 12:28 PM, Florian Heigl <florian.heigl@gmail.com> wrote:



          

            
Hi,

you can look into solutions based on cLVM or OCFS2 + Corosync/Pacemaker.

Don't forget to set up multipathd so your system can handle the link/controller failovers.

This has been done, and also has been/is a commonplace solution. There is also lots of blog posts that you can dig up once you search the right way.

I would avoid running natively on SAN luns attached to VMs due the risk of "the cluster stack had an error / was misconfigured". If you'd failover manually that would be less of an issue. The clusters like Pacemaker can protect the VMs a bit using SCSI reservations.

There was also Remus for running 2 VMs in lockstep for HA, but that was expecting no shared storage and was never polished by anyone to be worthwhile for production use.

A fair warning: Most homegrown HA setups like they're done commonly in the ISP industry tend to blow up much more often than what a proper solution should be like.

It might be better to pick something pre-made for that purpose if you don't have the SAN/Cluster experience.

I.e. XenServer/XCP or Oracle VM3.

Good luck!

Florian



            

              
Am 24.06.2021 um 10:09 schrieb mabi mabi@protonmail.ch:

Hello,

Is it possible with Xen on Debian 10 to have two Xen servers both directly attached in a redundant way through HBA interfaces to a single SAN?

The goal here would be to achieve higher availability of the Vms in case one Xen server is down for maintenance or because it is defective. This would mean that the the virtual machines can continue to run on the second available Xen server. The SAN would be used to store the virtual machines images directly via LVM I guess.

I did not find any Xen documentation or third-party howtos in order to do that. Does anyone have any pointers to some documentation or hints? or maybe this is simply not possible?

Best regards,

Mabi


            

          

        

        

      

    

    

  


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From: Chris Myers 
Date: Sun, 27 Jun 2021 19:08:31 -0500
Message-ID: 
Subject: Xen Remus with network storage
To: xen-users@lists.xenproject.org
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Good afternoon!

I've been reading about using Remus (here:
https://wiki.xenproject.org/wiki/Getting_Started_with_Remus) and was
curious - I've currently got two Xen hosts hooked to an iscsi backend,
where the volumes are accessible on both hosts already. Live-migration
works well at this point. I was hoping to set up some HA for one of my VMs
(router/firewall), and was curious if it would be possible to use the Remus
functionality without disk replication (since that's already being
handled)? Would it be safe to walk through most of the steps, just not do
the "disk replication" step?

Chris

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Good afternoon!

I've bee=
n reading about using Remus (here: https://wiki.xenproject.org/wiki/Getting_St=
arted_with_Remus) and was curious - I've currently got two Xen host=
s hooked to an iscsi backend, where the volumes are accessible on both host=
s already. Live-migration works well at this point. I was hoping to set up =
some HA for one of my VMs (router/firewall), and was curious if it would be=
 possible to use the Remus functionality without disk replication (since th=
at's already being handled)? Would it be safe to walk through most of t=
he steps, just not do the "disk replication" step?
=

Chris






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