[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Minios-devel] [UNIKRAFT PATCHv5 21/46] plat/common: Add cache maintenance support for arm64


  • To: <minios-devel@xxxxxxxxxxxxxxxxxxxx>, <simon.kuenzer@xxxxxxxxx>
  • From: Wei Chen <wei.chen@xxxxxxx>
  • Date: Fri, 10 Aug 2018 07:08:11 +0000
  • Authentication-results: spf=fail (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; lists.xenproject.org; dkim=none (message not signed) header.d=none;lists.xenproject.org; dmarc=none action=none header.from=arm.com;
  • Cc: Kaly.Xin@xxxxxxx, nd@xxxxxxx, wei.chen@xxxxxxx
  • Delivery-date: Fri, 10 Aug 2018 07:10:11 +0000
  • List-id: Mini-os development list <minios-devel.lists.xenproject.org>
  • Nodisclaimer: True
  • Spamdiagnosticmetadata: NSPM
  • Spamdiagnosticoutput: 1:99

When MMU is disabled, when we modify some data, for example, write
page-table, we will write with Device nGnRnE attributes. So the
cache will be bypassed. But the cache may still contain stall data
that we will hit when enabling MMU and cache. To prevent such issue,
we need to clean the cache potentially before and after updating
the page-table area.

So we introduce the cache maintenance functions in this patch.

Signed-off-by: Wei Chen <wei.chen@xxxxxxx>
---
 plat/common/arm/cache64.S                | 98 ++++++++++++++++++++++++
 plat/common/include/arm/arm64/cpu_defs.h | 60 +++++++++++++++
 plat/common/include/arm/cpu_defs.h       | 44 +++++++++++
 plat/kvm/Makefile.uk                     |  1 +
 4 files changed, 203 insertions(+)
 create mode 100644 plat/common/arm/cache64.S
 create mode 100644 plat/common/include/arm/arm64/cpu_defs.h
 create mode 100644 plat/common/include/arm/cpu_defs.h

diff --git a/plat/common/arm/cache64.S b/plat/common/arm/cache64.S
new file mode 100644
index 0000000..0f20e11
--- /dev/null
+++ b/plat/common/arm/cache64.S
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * This code is taken from:
+ * /arm-trusted-firmware/lib/aarch64/cache_helpers.S
+ *
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <asm.h>
+#include <arm/cpu_defs.h>
+/* ---------------------------------------------------------------
+ * Data cache operations by set/way to the level specified
+ *
+ * The main function, do_dcsw_op requires:
+ * x0: The operation type (0-2), as defined in cpu_defs.h
+ * x3: The last cache level to operate on
+ * x9: clidr_el1
+ * x10: The cache level to begin operation from
+ * and will carry out the operation on each data cache from level 0
+ * to the level in x3 in sequence
+ *
+ * The dcsw_op macro sets up the x3 and x9 parameters based on
+ * clidr_el1 cache information before invoking the main function
+ * ---------------------------------------------------------------
+ */
+
+.macro dcsw_op shift, fw, ls
+       mrs     x9, clidr_el1
+       ubfx    x3, x9, \shift, \fw
+       lsl     x3, x3, \ls
+       mov     x10, xzr
+       b       do_dcsw_op
+.endm
+
+ENTRY(do_dcsw_op)
+       cbz     x3, exit
+       adr     x14, dcsw_loop_table    // compute inner loop address
+       add     x14, x14, x0, lsl #5    // inner loop is 8x32-bit instructions
+       mov     x0, x9
+       mov     w8, #1
+loop1:
+       add     x2, x10, x10, lsr #1    // work out 3x current cache level
+       lsr     x1, x0, x2              // extract cache type bits from clidr
+       and     x1, x1, #7              // mask the bits for current cache only
+       cmp     x1, #2                  // see what cache we have at this level
+       b.lo    level_done              // nothing to do if no cache or icache
+
+       msr     csselr_el1, x10         // select current cache level in csselr
+       isb                             // isb to sych the new cssr&csidr
+       mrs     x1, ccsidr_el1          // read the new ccsidr
+       and     x2, x1, #7              // extract the length of the cache lines
+       add     x2, x2, #4              // add 4 (line length offset)
+       ubfx    x4, x1, #3, #10         // maximum way number
+       clz     w5, w4                  // bit position of way size increment
+       lsl     w9, w4, w5              // w9 = aligned max way number
+       lsl     w16, w8, w5             // w16 = way number loop decrement
+       orr     w9, w10, w9             // w9 = combine way and cache number
+       ubfx    w6, w1, #13, #15        // w6 = max set number
+       lsl     w17, w8, w2             // w17 = set number loop decrement
+       dsb     sy                      // barrier before we start this level
+       br      x14                     // jump to DC operation specific loop
+
+.macro dcsw_loop _op
+loop2_\_op:
+       lsl     w7, w6, w2              // w7 = aligned max set number
+
+loop3_\_op:
+       orr     w11, w9, w7             // combine cache, way and set number
+       dc      \_op, x11
+       subs    w7, w7, w17             // decrement set number
+       b.hs    loop3_\_op
+
+       subs    x9, x9, x16             // decrement way number
+       b.hs    loop2_\_op
+
+       b       level_done
+.endm
+
+level_done:
+       add     x10, x10, #2            // increment cache number
+       cmp     x3, x10
+       b.hi    loop1
+       msr     csselr_el1, xzr         // select cache level 0 in csselr
+       dsb     sy                      // barrier to complete final cache 
operation
+       isb
+exit:
+       ret
+END(do_dcsw_op)
+
+dcsw_loop_table:
+       dcsw_loop isw
+       dcsw_loop cisw
+       dcsw_loop csw
+
+ENTRY(dcsw_op_all)
+       dcsw_op #CLIDR_LOC_SHIFT, #CLIDR_FIELD_WIDTH, #CSSELR_LEVEL_SHIFT
+END(dcsw_op_all)
diff --git a/plat/common/include/arm/arm64/cpu_defs.h 
b/plat/common/include/arm/arm64/cpu_defs.h
new file mode 100644
index 0000000..56082e3
--- /dev/null
+++ b/plat/common/include/arm/arm64/cpu_defs.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Authors: Wei Chen <wei.chen@xxxxxxx>
+ *
+ * Copyright (c) 2018, Arm Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS HEADER MAY NOT BE EXTRACTED OR MODIFIED IN ANY WAY.
+ */
+#ifndef __CPU_ARM_64_DEFS_H__
+#define __CPU_ARM_64_DEFS_H__
+
+/*
+ * CLIDR_EL1, Cache Level ID Register
+ * Identifies the type of cache, or caches, that are implemented at each
+ * level and can be managed using the architected cache maintenance
+ * instructions that operate by set/way, up to a maximum of seven
+ * levels. Also identifies the Level of Coherence (LoC) and Level of
+ * Unification (LoU) for the cache hierarchy.
+ */
+#define        CLIDR_ICB_SHIFT         30
+#define        CLIDR_LOUU_SHIFT        27
+#define        CLIDR_LOC_SHIFT         24
+#define        CLIDR_LOUIS_SHIFT       21
+#define        CLIDR_FIELD_WIDTH       3
+#define        CLIDR_FIELD_MASK        0x7
+
+/* CSSELR_EL1, Cache Size Selection Register definitions */
+#define CSSELR_LEVEL_SHIFT     1
+
+/* Data cache set/way op type defines */
+#define DCISW                  0x0
+#define DCCISW                 0x1
+#define DCCSW                  0x2
+
+#endif /* __CPU_ARM_64_DEFS_H__ */
diff --git a/plat/common/include/arm/cpu_defs.h 
b/plat/common/include/arm/cpu_defs.h
new file mode 100644
index 0000000..7502f03
--- /dev/null
+++ b/plat/common/include/arm/cpu_defs.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Authors: Wei Chen <wei.chen@xxxxxxx>
+ *
+ * Copyright (c) 2018, Arm Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS HEADER MAY NOT BE EXTRACTED OR MODIFIED IN ANY WAY.
+ */
+
+#ifndef __PLAT_CMN_ARM_CPU_DEFS_H__
+#define __PLAT_CMN_ARM_CPU_DEFS_H__
+
+#if defined(__ARM_64__)
+#include "arm64/cpu_defs.h"
+#else
+#error "Add cpu_defs.h for current architecture."
+#endif
+
+#endif /* __PLAT_CMN_ARM_CPU_DEFS_H__ */
diff --git a/plat/kvm/Makefile.uk b/plat/kvm/Makefile.uk
index 4ec90f3..2b4c813 100644
--- a/plat/kvm/Makefile.uk
+++ b/plat/kvm/Makefile.uk
@@ -52,6 +52,7 @@ ifeq ($(CONFIG_ARCH_ARM_64),y)
 ifeq ($(findstring y,$(CONFIG_KVM_KERNEL_SERIAL_CONSOLE) 
$(CONFIG_KVM_DEBUG_SERIAL_CONSOLE)),y)
 LIBKVMPLAT_SRCS-$(CONFIG_ARCH_ARM_64) += 
$(UK_PLAT_COMMON_BASE)/arm/console.c|common
 endif
+LIBKVMPLAT_SRCS-$(CONFIG_ARCH_ARM_64) += 
$(UK_PLAT_COMMON_BASE)/arm/cache64.S|common
 LIBKVMPLAT_SRCS-$(CONFIG_ARCH_ARM_64) += $(LIBKVMPLAT_BASE)/arm/entry64.S
 LIBKVMPLAT_SRCS-$(CONFIG_ARCH_ARM_64) += $(LIBKVMPLAT_BASE)/arm/setup.c
 endif
-- 
2.17.1


_______________________________________________
Minios-devel mailing list
Minios-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/minios-devel

 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.