[Minios-devel] [UNIKRAFT PATCHv7 10/23] plat/kvm: Get VIRT_BITS from id_aa64mmfr0_el1.PARange for Arm64

[Jia He <justin.he@xxxxxxx>]

From: Wei Chen <wei.chen@xxxxxxx>
As we use VA == PA mapping, so the VIRT_BITS must be the same as
PA_BITS. We can get PA_BITS from ID_AA64MMFR0_EL1.PARange and the
TxSZ of TCR_INIT_FLAGS will be calculate dynamically.

Signed-off-by: Wei Chen <wei.chen@xxxxxxx>
Signed-off-by: Jia He <justin.he@xxxxxxx>
Reviewed-by: Sharan Santhanam <sharan.santhanam@xxxxxxxxx>
---
 plat/common/include/arm/arm64/cpu_defs.h | 16 +++++++---------
 plat/kvm/arm/pagetable.S                 | 24 ++++++++++++++++++++----
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/plat/common/include/arm/arm64/cpu_defs.h 
b/plat/common/include/arm/arm64/cpu_defs.h
index e6f20a3..675b9e6 100644
--- a/plat/common/include/arm/arm64/cpu_defs.h
+++ b/plat/common/include/arm/arm64/cpu_defs.h
@@ -48,13 +48,6 @@
 #define PSCI_FNID_SYSTEM_OFF           0x84000008
 #define PSCI_FNID_SYSTEM_RESET         0x84000009
 
-/*
- * The supported virtual address bits.
- * We will do 1:1 VA to PA Mapping, so we define the same address size
- * for VA and PA. 1TB size for Virtual and Physical Address Space.
- */
-#define VIRT_BITS 40
-
 /*
  * CTR_EL0, Cache Type Register
  * Provides information about the architecture of the caches.
@@ -146,8 +139,13 @@
 #define TCR_T0SZ(x)    ((x) << TCR_T0SZ_SHIFT)
 #define TCR_TxSZ(x)    (TCR_T1SZ(x) | TCR_T0SZ(x))
 
-#define TCR_INIT_FLAGS (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | \
-                       TCR_TG0_4K | TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
+/*
+ * As we use VA == PA mapping, so the VIRT_BITS must be the same
+ * as PA_BITS. We can get PA_BITS from ID_AA64MMFR0_EL1.PARange.
+ * So the TxSZ will be calculate dynamically.
+ */
+#define TCR_INIT_FLAGS (TCR_ASID_16 | TCR_TG0_4K | \
+                       TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
 
 /* SCTLR_EL1 - System Control Register */
 #define SCTLR_M                (_AC(1, UL) << 0)       /* MMU enable */
diff --git a/plat/kvm/arm/pagetable.S b/plat/kvm/arm/pagetable.S
index a3c82e2..d4abaff 100644
--- a/plat/kvm/arm/pagetable.S
+++ b/plat/kvm/arm/pagetable.S
@@ -52,6 +52,13 @@
 #define PCIE_L2_ENTRIES   512
 #define PCIE_ADDR_SIZE    0x8000000000
 
+/*
+ * As we use VA == PA mapping, so the VIRT_BITS must be the same
+ * as PA_BITS. We can get PA_BITS from ID_AA64MMFR0_EL1.PARange.
+ */
+virt_bits:
+       .byte 32, 36, 40, 42, 44, 48
+
 /*
  * We will use a direct map for physical address and virtual address
  * (PA = VA 1:1 mapping)
@@ -210,11 +217,20 @@ ENTRY(start_mmu)
        ldr x2, =MAIR_INIT_ATTR
        msr mair_el1, x2
 
-       /*
-        * Setup TCR according to PARange bits from ID_AA64MMFR0_EL1.
-        */
-       ldr x2, =TCR_INIT_FLAGS
+       /* Get VIRT_BITS from id_aa64mmfr0_el1.PARange */
        mrs x3, id_aa64mmfr0_el1
+       ldr x5, =virt_bits
+       ubfx x4, x3, #0, #4
+       ldrb w4, [x5, x4]
+
+       /* Setup TCR_TxSZ(64 - VIRT_BITS) for TCR_INIT_FLAGS */
+       mov x5, #64
+       sub x5, x5, x4
+       mov x4, x5
+       lsl x5, x5, #TCR_T1SZ_SHIFT
+       orr x5, x4, x5
+       ldr x2, =TCR_INIT_FLAGS
+       orr x2, x5, x2
        bfi x2, x3, #32, #3
        msr tcr_el1, x2
 
-- 
2.17.1


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