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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [ovmf test] 62774: trouble: broken/pass
flight 62774 ovmf real [real] http://logs.test-lab.xenproject.org/osstest/logs/62774/ Failures and problems with tests :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-xl-qemuu-ovmf-amd64 3 host-install(3) broken REGR. vs. 62740 version targeted for testing: ovmf 485b3066542c1278ec32b60a9c905000721256ce baseline version: ovmf 64df44b7e5d005598828c990500c2427bb131e8f Last test of basis 62740 2015-10-09 05:58:41 Z 1 days Testing same since 62774 2015-10-10 04:15:14 Z 1 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Hao Wu <hao.a.wu@xxxxxxxxx> Thomas Palmer <thomas.palmer@xxxxxxx> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 broken ------------------------------------------------------------ sg-report-flight on osstest.test-lab.xenproject.org logs: /home/logs/logs images: /home/logs/images Logs, config files, etc. are available at http://logs.test-lab.xenproject.org/osstest/logs Explanation of these reports, and of osstest in general, is at http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master Test harness code can be found at http://xenbits.xen.org/gitweb?p=osstest.git;a=summary broken-step test-amd64-i386-xl-qemuu-ovmf-amd64 host-install(3) Not pushing. ------------------------------------------------------------ commit 485b3066542c1278ec32b60a9c905000721256ce Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Fri Oct 9 18:55:41 2015 +0000 MdePkg/PeCoffLoader: fix handling of ARM MOVW/MOVT instruction relocs Advance the *FixupData pointer after use in the second relocation pass for runtime when handling ARM MOVW/MOVT immediate relocations. Note that using FixupData is somewhat pointless for relocations targeting instructions rather than data items, since the program cannot typically modify its own instructions, and the second pass should be performed unconditionally. But let's just fix it for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Leif Lindholm <leif.lindholm@xxxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18597 6f19259b-4bc3-4df7-8a09-765794883524 commit 94762ddef67f8805f4a3aef86e73dc27f234eb71 Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Fri Oct 9 18:55:28 2015 +0000 BaseTools/PeCoffLoader: fix handling of ARM MOVW/MOVT instruction relocs The handling of ARM MOVW/MOVT relocations sets the FixupData twice (once incorrectly), but fails to advance the *FixupData pointer afterwards. This is not actually a problem, since the fixup data is never used but let's fix it anyway in case anyone reuses this code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Leif Lindholm <leif.lindholm@xxxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18596 6f19259b-4bc3-4df7-8a09-765794883524 commit 6d72ff7d9daf7efae5243e9c00a281b350fc0f95 Author: Hao Wu <hao.a.wu@xxxxxxxxx> Date: Fri Oct 9 07:04:26 2015 +0000 UefiCpuPkg BaseXApic(X2)Lib: Add ASSERT if local APIC not software enabled Add an ASSERT in GetApicTimerState() to check if the local APIC is software enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx> Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18595 6f19259b-4bc3-4df7-8a09-765794883524 commit f17e2f8c9e1a34c3707f93ca373a79f14927f7b1 Author: Hao Wu <hao.a.wu@xxxxxxxxx> Date: Fri Oct 9 07:04:00 2015 +0000 UefiCpuPkg: Add ASSERT to handle local APIC not config properly When the local APIC is not configurated properly, function GetApicTimerInitCount() in LocalApicLib may return zero, which will lead to a divide by zero exception in SecPeiDxeTimerLibUefiCpu. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx> Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18594 6f19259b-4bc3-4df7-8a09-765794883524 commit 53fa8748fdba2e80e9266e93568d7387ee98ad9f Author: Hao Wu <hao.a.wu@xxxxxxxxx> Date: Fri Oct 9 07:03:24 2015 +0000 MdePkg: Add ASSERT to handle local APIC not config properly When the local APIC is not configurated properly, function InternalX86GetInitTimerCount() may return zero, which will lead to a divide by zero exception in SecPeiDxeTimerLibCpu. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx> Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18593 6f19259b-4bc3-4df7-8a09-765794883524 commit 9ad48dd148e167261161a606e120a3132048e1e9 Author: Thomas Palmer <thomas.palmer@xxxxxxx> Date: Fri Oct 9 06:03:34 2015 +0000 SecurityPkg: Clean up unused files in RngDxe Clean up files in RngDxe/IA32 and RngDxe/X64 that are subsumed by files in BaseRngLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Palmer <thomas.palmer@xxxxxxx> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@xxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> Reviewed-by: Qin Long <qin.long@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18592 6f19259b-4bc3-4df7-8a09-765794883524 commit 3b60842ce780b3c37e4a0b87705e44c5339799df Author: Thomas Palmer <thomas.palmer@xxxxxxx> Date: Fri Oct 9 06:03:26 2015 +0000 SecurityPkg: Integrate new RngLib into RngDxe Use the new RngLib to provide the IA32/X64 random data for RngDxe. Remove x86 specific functions from RdRand files. Simplify RngDxe by using WriteUnaligned64 for all platforms. Use GetRandomNumber128 in RngDxe to leverage 128 bit support provided by some HW RNG devices. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Palmer <thomas.palmer@xxxxxxx> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@xxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> Reviewed-by: Qin Long <qin.long@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18591 6f19259b-4bc3-4df7-8a09-765794883524 commit c8b6f16d7d3b0c225cf34bd1c750373c9b251284 Author: Thomas Palmer <thomas.palmer@xxxxxxx> Date: Fri Oct 9 06:03:17 2015 +0000 MdePkg: Create GetRandomNumber128 in RngLib Declare GetRandomNumber128 in RngLib.h. Create GetRandomNumber128 in BaseRngLib, which is simply calling GetRandomNumber64 twice. A GetRandomNumber128 function allows platforms with 128bit HWRNGs to save on IO overhead that comes from having to prime the HWRNG device before each read operation. Using the HWRNG installed on the HP ProLiant m400 moonshot cartridge, this will save about 50ms per RAW Entropy operation as compared with calling GetRandomNumber64 twice. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Palmer <thomas.palmer@xxxxxxx> Reviewed-by: Samer El-Haj-Mahmoud <elhaj@xxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> Reviewed-by: Qin Long <qin.long@xxxxxxxxx> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18590 6f19259b-4bc3-4df7-8a09-765794883524 _______________________________________________ osstest-output mailing list osstest-output@xxxxxxxxxxxxxxxxxxxx http://lists.xenproject.org/cgi-bin/mailman/listinfo/osstest-output
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