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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [ovmf baseline-only test] 68098: all pass
This run is configured for baseline tests only. flight 68098 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/68098/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 339c6e905a151305cd3b74e3a713a31798769993 baseline version: ovmf 26b85012802ed8a2ff3db96d102121323aabcc0c Last test of basis 68094 2016-11-24 21:51:01 Z 0 days Testing same since 68098 2016-11-25 11:48:50 Z 0 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Jan Dabros <jsd@xxxxxxxxxxxx> Konrad Rzeszutek Wilk <konrad@xxxxxxxxxx> Laszlo Ersek <lersek@xxxxxxxxxx> Marcin Wojtas <mw@xxxxxxxxxxxx> Richard Thomaiyar <richard.marian.thomaiyar@xxxxxxxxx> Ryan Harkin <ryan.harkin@xxxxxxxxxx> Thomaiyar, Richard Marian <richard.marian.thomaiyar@xxxxxxxxx> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass ------------------------------------------------------------ sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ------------------------------------------------------------ commit 339c6e905a151305cd3b74e3a713a31798769993 Author: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Date: Wed Nov 23 21:36:24 2016 +0800 EmbeddedPkg/MmcDxe: expand to support multiple blocks Make use of DMA to transfer multiple blocks at one time. It could improve the performance on MMC/SD driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Tested-by: Ryan Harkin <ryan.harkin@xxxxxxxxxx> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit e06253ba80d93bceaefc182ca882e07b0463be8d Author: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Date: Wed Nov 23 21:36:22 2016 +0800 EmbeddedPkg/MmcDxe: set I/O speed and bus width in SD stack Add more SD commands to support 4-bit bus width & iospeed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Tested-by: Ryan Harkin <ryan.harkin@xxxxxxxxxx> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit 752ae80514ccb3532a6d6d16a122642573eabdee Author: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Date: Wed Nov 23 21:36:21 2016 +0800 EmbeddedPkg/MmcDxe: invoke SetIos() protocol method to set speed and width Add the interface to change the bus width and speed. By default, MMC is initialized with 1-bit mode and less than 400KHz bus clock. It causes MMC working inefficiently. Set I/O bus width on both MMC controller and EXTCSD. Otherwise, it may cause unmatched failure case. And support more timing mode, high speed, HS200 & HS400 mode. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Tested-by: Ryan Harkin <ryan.harkin@xxxxxxxxxx> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit 1df2fe1433b2420b7e11591e3d46ed1a2c146072 Author: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Date: Wed Nov 23 21:36:23 2016 +0800 ArmPlatformPkg/PL180MciDxe: update for identifying SD When CMD6 & ACMD51 are added into identifying SD process, PL180 should also support CMD6 & ACMD51. Otherwise, it will hang when system tries to read expected data. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Tested-by: Ryan Harkin <ryan.harkin@xxxxxxxxxx> commit a28b9aef6769fd07c2b5e67a8c3c7a42bf486463 Author: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Date: Wed Nov 23 21:36:21 2016 +0800 EmbeddedPkg/Protocol/MmcHost: add new methods for I/O width and multiblock Add new protocol methods to change the bus width, speed and check for multiblock support. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@xxxxxxxxxx> Split off protocol changes from implementation changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit 6052a15f4a4297b430cf03f2456e51f8d3bb4598 Author: Marcin Wojtas <mw@xxxxxxxxxxxx> Date: Thu Nov 24 08:54:33 2016 +0100 MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software. This patch enables in AhciMode setting GHC.AE in case its initial value is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas <mw@xxxxxxxxxxxx> Signed-off-by: Jan Dabros <jsd@xxxxxxxxxxxx> Reviewed-by: Feng Tian <feng.tian@xxxxxxxxx> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit 2667ad40919afa6e4cd1b5f572584fbd440689b4 Author: Konrad Rzeszutek Wilk <konrad@xxxxxxxxxx> Date: Wed Nov 23 20:15:23 2016 -0500 OvmfPkg/build.sh: Make GCC5 the default toolchain, catch GCC43 and earlier v2: * Changes suggested by Laszlo: - change the catch-all (*) to GCC5, from GCC44 - remove the (5.*.*) pattern from GCC49 - generate error for GCC < 4.4 In v3, also generate error for really GCC < 4.4, like GCC 1. Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> Reviewed-by: Jordan Justen <jordan.l.justen@xxxxxxxxx> Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=62 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Konrad Rzeszutek Wilk <konrad@xxxxxxxxxx> Tested-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit 0e3f9ee1d61fdc37a4aef18c53dfcc2cedeb86e3 Author: Thomaiyar, Richard Marian <richard.marian.thomaiyar@xxxxxxxxx> Date: Wed Nov 16 17:47:04 2016 +0800 IntelFsp2Pkg: Use FspSiliconInitDone2 API Use FspSiliconInitDone2 API in Notify Phase Cc: Maurice Ma <maurice.ma@xxxxxxxxx> Cc: Jiewen Yao <jiewen.yao@xxxxxxxxx> Cc: Giri P Mudusuru <giri.p.mudusuru@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@xxxxxxxxx> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@xxxxxxxxx> Reviewed-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> _______________________________________________ osstest-output mailing list osstest-output@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/cgi-bin/mailman/listinfo/osstest-output
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