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[ovmf baseline-only test] 68237: all pass



This run is configured for baseline tests only.

flight 68237 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68237/

Perfect :-)
All tests in this flight passed as required
version targeted for testing:
 ovmf                 c0584d0bdd4463551db8f8c62a5e2936ec97b407
baseline version:
 ovmf                 aaa61995af9e0b65c37bdad6796867760fa1d5fe

Last test of basis    68227  2016-12-15 16:17:30 Z    2 days
Testing same since    68237  2016-12-17 16:52:51 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx>
  Chao Zhang <chao.b.zhang@xxxxxxxxx>
  Feng Tian <feng.tian@xxxxxxxxx>
  Hao Wu <hao.a.wu@xxxxxxxxx>
  Marcin Wojtas <mw@xxxxxxxxxxxx>
  Ruiyu Ni <ruiyu.ni@xxxxxxxxx>
  Zhang, Chao B <chao.b.zhang@xxxxxxxxx>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit c0584d0bdd4463551db8f8c62a5e2936ec97b407
Author: Zhang, Chao B <chao.b.zhang@xxxxxxxxx>
Date:   Fri Dec 16 13:09:44 2016 +0800

    SecurityPkg: Tcg2Dxe: Report correct FinalEventLog size
    
    Update debug log to report correct FinalEventLog size.
    
    Cc: Yao Jiewen <jiewen.yao@xxxxxxxxx>
    Cc: Star Zeng <star.zeng@xxxxxxxxx>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Chao Zhang <chao.b.zhang@xxxxxxxxx>
    Reviewed-by: Yao Jiewen <jiewen.yao@xxxxxxxxx>
    Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx>

commit 14806d7b7dda38ddf7ff51e91cf412f1c6e10b58
Author: Hao Wu <hao.a.wu@xxxxxxxxx>
Date:   Fri Nov 4 12:41:18 2016 +0800

    UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
    
    https://bugzilla.tianocore.org/show_bug.cgi?id=176
    
    Update CPUID leaf and sub-leaf indexes and structures as described by
    Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
    Volume 2A, September 2016, CPUID instruction.
    
    Summary of incompatible changes:
    1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
    Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed
    from 'PQE' to 'RDT_A'.
    
    2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring
    Information' related definitions
    Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to
    'CPUID_INTEL_RDT_MONITORING'.
    Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been
    renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'.
    Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been
    renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'.
    
    3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement
    Information' related definitions
    Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to
    'CPUID_INTEL_RDT_ALLOCATION'.
    Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to
    'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'.
    Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been
    renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'.
    
    This commit also updates the relating codes in
    UefiCpuPkg/Application/Cpuid to reflect the changes.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx>
    Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx>
    Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx>

commit 35fd9411d08028f52db17585bd1b46e69d53e178
Author: Hao Wu <hao.a.wu@xxxxxxxxx>
Date:   Thu Dec 8 16:35:49 2016 +0800

    UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)
    
    https://bugzilla.tianocore.org/show_bug.cgi?id=176
    
    Add the MSR header file of Goldmont processor according to Intel(R) 64 and
    IA-32 Architectures Software Developer's Manual, Volume 3, September 2016,
    Chapter 35 Model-Specific-Registers (MSR), Section 35.5.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx>
    Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx>
    Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx>

commit 37cea63f171260cf5283bbfa63b9be4a14941914
Author: Hao Wu <hao.a.wu@xxxxxxxxx>
Date:   Thu Dec 8 16:35:56 2016 +0800

    UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
    
    https://bugzilla.tianocore.org/show_bug.cgi?id=176
    
    Update the MSR header file of Skylake processor according to Intel(R) 64
    and IA-32 Architectures Software Developer's Manual, Volume 3, September
    2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
    
    Summary of incompatible changes:
    1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to
    IA32_PERF_GLOBAL_STATUS
    Typo 'STAUS' has been fixed in SDM.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx>
    Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx>
    Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx>

commit 0f16be6d9eef371d6ed1e45422748ae0fb49652f
Author: Hao Wu <hao.a.wu@xxxxxxxxx>
Date:   Tue Oct 25 13:35:54 2016 +0800

    UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
    
    https://bugzilla.tianocore.org/show_bug.cgi?id=176
    
    Update MSR header files of processors (excluding Goldmont and Skylake
    processors) according to Intel(R) 64 and IA-32 Architectures Software
    Developer's Manual, Volume 3, September 2016, Chapter 35
    Model-Specific-Registers (MSR).
    
    Summary of incompatible changes:
    General:
    1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
    files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
    Typo 'STAUS' has been fixed in SDM.
    If the MSR definition is the same with architectural MSR, we remove it.
    Otherwise, we rename the MSR.
    
    2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
    in processor-specific header files have been removed or renamed to
    IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
    Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
    If the MSR definition is the same with architectural MSR, we remove it.
    Otherwise, we rename the MSR.
    Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
    SDM are still kept in processor-specific header files.
    
    HaswellMsr.h:
    1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
    Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
    in SDM.
    Since the MSR definition is the same with architectural MSR, we remove it.
    
    SandyBridgeMsr.h:
    1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
    0:3
    Bit description change from 'Core {X} select' to 'Slice {X} select' for
    bit 0:3 in SDM.
    
    SilvermontMsr.h:
    1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
    Bit description for this MSR is totally changed in SDM, we modify the
    structure definition to align with it.
    
    XeonDMsr.h:
    1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
    and MSR_PKG_C10_RESIDENCY have been removed
    Those 3 MSRs are not defined for this processor in SDM, we remove them.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Hao Wu <hao.a.wu@xxxxxxxxx>
    Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx>
    Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx>

commit 7dede0a219859dccf21b622d205a9b8801e4a078
Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx>
Date:   Thu Dec 15 15:28:45 2016 +0800

    ShellPkg/setvar: Correct typo in setvar help message
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx>
    Reviewed-by: Jaben Carsey <jaben.carsey@xxxxxxxxx>

commit b6fea56cb536423f0b1f99a467f02b9133a8b424
Author: Feng Tian <feng.tian@xxxxxxxxx>
Date:   Thu Dec 15 13:25:30 2016 +0800

    UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure
    
    Cc: Michael D Kinney <michael.d.kinney@xxxxxxxxx>
    Cc: Jeff Fan <jeff.fan@xxxxxxxxx>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Feng Tian <feng.tian@xxxxxxxxx>
    Reviewed-by: Michael D Kinney <michael.d.kinney@xxxxxxxxx>
    Reviewed-by: Jeff Fan <jeff.fan@xxxxxxxxx>

commit 16296a126c99174ad27a6d78229df70e62049310
Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx>
Date:   Fri Dec 9 15:04:34 2016 +0000

    MdeModulePkg/NonDiscoverablePciDeviceDxe: add support for non-coherent DMA
    
    Add support for non-coherent DMA, either by performing explicit cache
    maintenance when DMA mappings are aligned to the CPU's DMA buffer alignment,
    or by bounce buffering via uncached mappings otherwise.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx>
    Tested-by: Marcin Wojtas <mw@xxxxxxxxxxxx>
    Reviewed-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx>

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