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[xen-unstable-smoke test] 109174: regressions - trouble: broken/fail/pass

flight 109174 xen-unstable-smoke real [real]

Regressions :-(

Tests which did not succeed and are blocking,
including tests which could not be run:
 test-armhf-armhf-xl          11 guest-start              fail REGR. vs. 109036

Tests which did not succeed, but are not blocking:
 test-arm64-arm64-xl-xsm       1 build-check(1)               blocked  n/a
 test-amd64-amd64-libvirt     12 migrate-support-check        fail   never pass

version targeted for testing:
 xen                  8bf68dca65e2d61f4dfc6715cca51ad3dd5aadf1
baseline version:
 xen                  8839be5c1fe339a1310b4e05e88c5a0230b7959d

Last test of basis   109036  2017-05-05 16:03:12 Z    2 days
Testing same since   109174  2017-05-08 12:01:41 Z    0 days    1 attempts

People who touched revisions under test:
  Jan Beulich <jbeulich@xxxxxxxx>
  Kevin Tian <kevin.tian@xxxxxxxxx>
  Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>

 build-amd64                                                  pass    
 build-armhf                                                  pass    
 build-amd64-libvirt                                          pass    
 test-armhf-armhf-xl                                          fail    
 test-arm64-arm64-xl-xsm                                      broken  
 test-amd64-amd64-xl-qemuu-debianhvm-i386                     pass    
 test-amd64-amd64-libvirt                                     pass    

sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images

Logs, config files, etc. are available at

Explanation of these reports, and of osstest in general, is at

Test harness code can be found at

Not pushing.

commit 8bf68dca65e2d61f4dfc6715cca51ad3dd5aadf1
Author: Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>
Date:   Mon May 8 13:37:17 2017 +0200

    x86/vpmu_intel: fix hypervisor crash by masking PC bit in MSR_P6_EVNTSEL
    Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
    Protection Fault and thus results in a hypervisor crash. This behavior has
    been observed on two generations of Intel processors namely, Haswell and
    Broadwell. Other Intel processor generations were not tested. However, it
    does seem to be a possible erratum that hasn't yet been confirmed by Intel.
    To fix the problem this patch masks PC bit and returns an error in
    case any guest tries to write to it on any Intel processor. In addition
    to the fact that setting this bit crashes the hypervisor on Haswell and
    Broadwell, the PC flag bit toggles a hardware pin on the physical CPU
    every time the programmed event occurs and the hardware behavior in
    response to the toggle is undefined in the SDM, which makes this bit
    unsafe to be used by guests and hence should be masked on all machines.
    Signed-off-by: Mohit Gambhir <mohit.gambhir@xxxxxxxxxx>
    Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Kevin Tian <kevin.tian@xxxxxxxxx>
    Release-acked-by: Julien Grall <julien.grall@xxxxxxx>

commit d595e126c96976d056d7877e4319b3f2f3d246b1
Author: Jan Beulich <jbeulich@xxxxxxxx>
Date:   Mon May 8 13:36:28 2017 +0200

    VMX: constrain vmx_intr_assist() debugging code to debug builds
    This is because that code, added by commit 997382b771 ("y86/vmx: dump
    PIR and vIRR before ASSERT()"), was meant to be removed by the time we
    finalize 4.9, but the root cause of the ASSERT() wrongly(?) triggering
    still wasn't found.
    Take the opportunity and also correct the format specifiers, which I
    had got wrong when editing said change while committing.
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Kevin Tian <kevin.tian@xxxxxxxxx>
    Release-Acked-by: Julien Grall <julien.grall@xxxxxxx>
(qemu changes not included)

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