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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [ovmf baseline-only test] 72034: all pass
This run is configured for baseline tests only. flight 72034 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/72034/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 51ce27fd8c583845480858eda503f38e8b42d619 baseline version: ovmf ef5e0db22cdd73e9727afcaa5c7fe8e55b7b3671 Last test of basis 72033 2017-08-28 13:16:57 Z 0 days Testing same since 72034 2017-08-29 04:49:24 Z 0 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Brijesh Singh <brijesh.singh@xxxxxxx> Eric Dong <eric.dong@xxxxxxxxx> Jiewen Yao <jiewen.yao@xxxxxxxxx> Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Star Zeng <star.zeng@xxxxxxxxx> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass ------------------------------------------------------------ sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ------------------------------------------------------------ commit 51ce27fd8c583845480858eda503f38e8b42d619 Author: Star Zeng <star.zeng@xxxxxxxxx> Date: Mon Aug 28 09:45:39 2017 +0800 UefiCpuPkg/PiSmmCpuDxeSmm: Centralize mPhysicalAddressBits definition Originally (before 714c2603018a99a514c42c2b511c821f30ba9cdf), mPhysicalAddressBits was only defined in X64 PageTbl.c, after 714c2603018a99a514c42c2b511c821f30ba9cdf, mPhysicalAddressBits is also defined in Ia32 PageTbl.c, then mPhysicalAddressBits is used in ConvertMemoryPageAttributes() for address check. This patch is to centralize mPhysicalAddressBits definition to PiSmmCpuDxeSmm.c from Ia32 and X64 PageTbl.c. Cc: Jiewen Yao <jiewen.yao@xxxxxxxxx> Cc: Laszlo Ersek <lersek@xxxxxxxxxx> Cc: Eric Dong <eric.dong@xxxxxxxxx> Suggested-by: Laszlo Ersek <lersek@xxxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit dd4205f8ba41282c8afb4805aed3e34f16aaa7f2 Author: Brijesh Singh <brijesh.singh@xxxxxxx> Date: Sun Aug 27 18:53:32 2017 -0400 OvmfPkg/VirtioBlkDxe: negotiate VIRTIO_F_IOMMU_PLATFORM VirtioBlkDxe driver has been updated to use IOMMU-like member functions from VIRTIO_DEVICE_PROTOCOL to translate the system physical address to device address. We do not need to do anything special when VIRTIO_F_IOMMU_PLATFORM bit is present hence treat it in parallel with VIRTIO_F_VERSION_1. Cc: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Cc: Jordan Justen <jordan.l.justen@xxxxxxxxx> Cc: Tom Lendacky <thomas.lendacky@xxxxxxx> Cc: Laszlo Ersek <lersek@xxxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx> Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> Regression-tested-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit 3540f2cef57afc08f18fe4db971f3b0e06b49d63 Author: Brijesh Singh <brijesh.singh@xxxxxxx> Date: Sun Aug 27 18:53:25 2017 -0400 Ovmfpkg/VirtioBlkDxe: map virtio-blk request and response buffers When device is behind the IOMMU, driver is require to pass the device address of virtio request, response and any memory referenced by those request/response to the bus master. The patch uses IOMMU-like member functions from VIRTIO_DEVICE_PROTOCOL to map request and response buffers system physical address to the device address. - If the buffer need to be accessed by both the processor and a bus master then map with BusMasterCommonBuffer. - If the buffer need to be accessed for a write operation by a bus master then map with BusMasterWrite. - If the buffer need to be accessed for a read operation by a bus master then map with BusMasterRead. Cc: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Cc: Jordan Justen <jordan.l.justen@xxxxxxxxx> Cc: Tom Lendacky <thomas.lendacky@xxxxxxx> Cc: Laszlo Ersek <lersek@xxxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx> Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> Regression-tested-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit 19165130470f010a427730ea270c154c9dd500df Author: Brijesh Singh <brijesh.singh@xxxxxxx> Date: Sun Aug 27 18:53:17 2017 -0400 OvmfPkg/VirtioBlkDxe: map VRING using VirtioRingMap() When device is behind the IOMMU then driver need to pass the device address when programing the bus master. The patch uses VirtioRingMap() to map the VRING system physical address to device address. Cc: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Cc: Jordan Justen <jordan.l.justen@xxxxxxxxx> Cc: Tom Lendacky <thomas.lendacky@xxxxxxx> Cc: Laszlo Ersek <lersek@xxxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Brijesh Singh <brijesh.singh@xxxxxxx> Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> Regression-tested-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit a2285a8963840683a28ed051077190b086c423eb Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Date: Fri Aug 4 13:23:24 2017 +0800 MdePkg/S3PciSegmentLib: Add S3PciSegmentLib class and instance. The patch adds the new library class S3PciSegmentLib to carry out PCI configuration and enable the PCI operations to be replayed during an S3 resume. This library class maps directly on top of the PciSegmentLib class. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit 5c9bb86f171c9a3a89ac4b5b00518cb00bf32132 Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Date: Fri Aug 4 13:18:37 2017 +0800 MdePkg/PciSegmentLib: Add instances that consumes PciSegmentInfoLib The patch adds two PciSegmentLib instances that consumes PciSegmentInfoLib to provide multiple segments PCI configuration access. BasePciSegmentLibSegmentInfo instance is a BASE library. DxeRuntimePciSegmentLibSegmentInfo instance is to be linked with runtime drivers to provide not only boot time but also runtime PCI configuration access. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit e457c1f65d187f58272c1dc98ae338b4f221ee41 Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Date: Fri Aug 4 13:10:59 2017 +0800 MdePkg/PciSegmentInfoLib: Add PciSegmentInfoLib class and instance. The patch adds PciSegmentInfoLib library class which is used by PciSegmentLib (commit in next patch) to support multiple segment PCI configuration access. BasePciSegmentInfoLibNull instance is added but it shouldn't be used by any real platform. Any single segment platform that wants to use PciSegmentLib could use BasePciSegmentLibPci instance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit c9c270193a8f1d64d9664bd191ab57e217206996 Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Date: Fri Aug 4 13:02:14 2017 +0800 MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS The patch adds new macro PCI_ECAM_ADDRESS into PciExpress21.h, to align to the PCIE spec, and also update PciExpressLib.h to redirect PCI_EXPRESS_LIB_ADDRESS to the new macro. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit ebdde8ff266872632bd6400adcd96d21294e32de Author: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Date: Fri Aug 4 12:55:26 2017 +0800 MdePkg/PciSegmentLib: Fix typo in function header comments Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit 5f5bdf4ab58e3b225d2cebe5735a6825f535c7cd Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Fri Aug 25 14:36:41 2017 +0800 IntelSiliconPkg/PlatformVTdSample: update ExceptionDevice Add sample for device scope based exception list and PCI vendor id based exception list. Cc: Star Zeng <star.zeng@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> commit f77d35c7f0835150df4be5327dd83152bac5ee39 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Fri Aug 25 14:46:07 2017 +0800 IntelSiliconPkg/IntelVTd: update PlatformVtdPolicy 1. Handle flexible exception list format. 1.1 Handle DeviceScope based device info. 1.2 Handle PciDeviceId based device info. 2. Reorg the PCI_DEVICE_INFORMATION 2.1 Merge data pointer reduce allocation times 2.2 Add PCI device id to PCI_DEVICE_INFORMATION 2.3 Rename PciDescriptor to avoid confusing. 3. Fix the debug message too long issue. Cc: Star Zeng <star.zeng@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> commit 71872f7cda66ddf381e7d788750ed69e3e02a3d0 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Tue Aug 22 11:47:54 2017 +0800 IntelSiliconPkg/header: update PlatformVtdPolicy Add flexible exception list format: 1) Support Device scope based reporting: Such as, Seg:0/StartBus:0/(Dev:1C|Func:0)/(Dev:0|Func:0) 2) Support PCI VendorId/DeviceId based reporting Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270 Cc: Star Zeng <star.zeng@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> commit 306a5bcc6b0170d28b0db10bd359817bb4b1db9f Author: Eric Dong <eric.dong@xxxxxxxxx> Date: Thu Aug 17 11:40:38 2017 +0800 UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file. Original code about Local Machine Check exception feature saves in a discrete file, because features related to machine check architecture all saved in MachineCheck.c file. This patch moved LMCE logic to same file for easy maintenance. Cc: Michael Kinney <michael.d.kinney@xxxxxxxxx> Cc: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@xxxxxxxxx> Reviewed-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> commit ac401975581daf1e4e353898f7441eeb668ba304 Author: Eric Dong <eric.dong@xxxxxxxxx> Date: Thu Aug 17 11:33:30 2017 +0800 UefiCpuPkg/CpuCommonFeaturesLib: Add CPUID MCA support check Add CPUID check to see if the CPU supports the Machine Check Architecture before accessing the Machine Check Architecture related MSRs. Cc: Michael Kinney <michael.d.kinney@xxxxxxxxx> Cc: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@xxxxxxxxx> Reviewed-by: Ruiyu Ni <ruiyu.ni@xxxxxxxxx> _______________________________________________ osstest-output mailing list osstest-output@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/cgi-bin/mailman/listinfo/osstest-output
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