[XenARM] [PATCH] xen/arm: Save/Restore GICH_APR register

[Julien Grall <julien.grall@xxxxxxxxxx>]

Linux uses GICC_CTLR.EOImodeNS set to 0, which means both priority drop
and deactivate interrupt functionality are made when something is
written in GICC_EOIR.

As the ARM manual specifies: "having an active interrupt in the List registers
with a priority that is not set in the corresponding Active Priorities register"
when GICV_CTLR.EOImode (ie GICC_CTLR.EOImodeNS in the guest context) result
in unpredicable behavior, we need to save/restore GICH_APR.

Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/arch/arm/gic.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 41abdfb..ccb90e5 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -70,6 +70,7 @@ void gic_save_state(struct vcpu *v)
         v->arch.gic_lr[i] = GICH[GICH_LR + i];
     v->arch.lr_mask = this_cpu(lr_mask);
     spin_unlock_irq(&gic.lock);
+    v->arch.gic_apr = GICH[GICH_APR];
     /* Disable until next VCPU scheduled */
     GICH[GICH_HCR] = 0;
     isb();
@@ -87,6 +88,7 @@ void gic_restore_state(struct vcpu *v)
     for ( i=0; i<nr_lrs; i++)
         GICH[GICH_LR + i] = v->arch.gic_lr[i];
     spin_unlock_irq(&gic.lock);
+    GICH[GICH_APR] = v->arch.gic_apr;
     GICH[GICH_HCR] = GICH_HCR_EN;
     isb();
 
-- 
1.7.10.4


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