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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] Add 'apic={verbose, debug}' option to Xen. Same meaning as on Linux
ChangeSet 1.1441, 2005/05/12 18:58:15+01:00, kaf24@xxxxxxxxxxxxxxxxxxxx
Add 'apic={verbose,debug}' option to Xen. Same meaning as on Linux
command line, and automatically propagated to domain0 command line.
Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>
docs/src/user.tex | 3 +
xen/arch/x86/apic.c | 127 ++++++++++++++++++++++++++++++---------------------
xen/arch/x86/setup.c | 7 ++
3 files changed, 85 insertions(+), 52 deletions(-)
diff -Nru a/docs/src/user.tex b/docs/src/user.tex
--- a/docs/src/user.tex 2005-05-12 14:04:01 -04:00
+++ b/docs/src/user.tex 2005-05-12 14:04:01 -04:00
@@ -1791,6 +1791,9 @@
Instruct Xen (and domain 0) to ignore any IOAPICs that are present in
the system, and instead continue to use the legacy PIC.
+\item [apic=debug,verbose ]
+ Print more detailed information about local APIC and IOAPIC configuration.
+
\end{description}
\section{XenLinux Boot Options}
diff -Nru a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c 2005-05-12 14:04:01 -04:00
+++ b/xen/arch/x86/apic.c 2005-05-12 14:04:01 -04:00
@@ -1,5 +1,5 @@
/*
- * based on linux-2.6.10/arch/i386/kernel/apic.c
+ * based on linux-2.6.11/arch/i386/kernel/apic.c
*
* Local APIC handling, local APIC timers
*
@@ -37,11 +37,14 @@
#include <mach_apic.h>
#include <io_ports.h>
+/*
+ * Debug level
+ */
+int apic_verbosity;
+
/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer = 0;
-int apic_verbosity;
-
static int enabled_via_apicbase;
int get_physical_broadcast(void)
@@ -126,7 +129,8 @@
* PIC mode, enable APIC mode in the IMCR, i.e.
* connect BSP's local APIC to INT and NMI lines.
*/
- printk("leaving PIC mode, enabling APIC mode.\n");
+ apic_printk(APIC_VERBOSE, "leaving PIC mode, "
+ "enabling APIC mode.\n");
outb(0x70, 0x22);
outb(0x01, 0x23);
}
@@ -141,7 +145,8 @@
* interrupts, including IPIs, won't work beyond
* this point! The only exception are INIT IPIs.
*/
- printk("disabling APIC mode, entering PIC mode.\n");
+ apic_printk(APIC_VERBOSE, "disabling APIC mode, "
+ "entering PIC mode.\n");
outb(0x70, 0x22);
outb(0x00, 0x23);
}
@@ -182,10 +187,10 @@
* The version register is read-only in a real APIC.
*/
reg0 = apic_read(APIC_LVR);
- Dprintk("Getting VERSION: %x\n", reg0);
+ apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
reg1 = apic_read(APIC_LVR);
- Dprintk("Getting VERSION: %x\n", reg1);
+ apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
/*
* The two version reads above should print the same
@@ -209,7 +214,7 @@
* The ID register is read/write in a real APIC.
*/
reg0 = apic_read(APIC_ID);
- Dprintk("Getting ID: %x\n", reg0);
+ apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
/*
* The next two are just to see if we have sane values.
@@ -217,9 +222,9 @@
* compatibility mode, but most boxes are anymore.
*/
reg0 = apic_read(APIC_LVT0);
- Dprintk("Getting LVT0: %x\n", reg0);
+ apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
reg1 = apic_read(APIC_LVT1);
- Dprintk("Getting LVT1: %x\n", reg1);
+ apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
return 1;
}
@@ -235,20 +240,23 @@
*/
apic_wait_icr_idle();
- Dprintk("Synchronizing Arb IDs.\n");
+ apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
| APIC_DM_INIT);
}
extern void __error_in_apic_c (void);
+/*
+ * An initial setup of the virtual wire mode.
+ */
void __init init_bsp_APIC(void)
{
unsigned long value, ver;
/*
- * Don't do the setup now if we have a SMP BIOS as the through-I/O-APIC
- * virtual wire mode might be active.
+ * Don't do the setup now if we have a SMP BIOS as the
+ * through-I/O-APIC virtual wire mode might be active.
*/
if (smp_found_config || !cpu_has_apic)
return;
@@ -380,10 +388,12 @@
value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
if (!smp_processor_id() && (pic_mode || !value)) {
value = APIC_DM_EXTINT;
- printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
+ apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
+ smp_processor_id());
} else {
value = APIC_DM_EXTINT | APIC_LVT_MASKED;
- printk("masked ExtINT on CPU#%d\n", smp_processor_id());
+ apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
+ smp_processor_id());
}
apic_write_around(APIC_LVT0, value);
@@ -413,8 +423,9 @@
apic_write(APIC_ESR, 0);
value = apic_read(APIC_ESR);
if (value != oldvalue)
- printk("ESR value before enabling vector: 0x%08lx "
- "after: 0x%08lx\n", oldvalue, value);
+ apic_printk(APIC_VERBOSE, "ESR value before enabling "
+ "vector: 0x%08lx after: 0x%08lx\n",
+ oldvalue, value);
} else {
if (esr_disable)
/*
@@ -424,8 +435,8 @@
* errors anyway - mbligh
*/
printk("Leaving ESR disabled.\n");
- else
- printk("No ESR for 82489DX.\n");
+ else
+ printk("No ESR for 82489DX.\n");
}
if (nmi_watchdog == NMI_LOCAL_APIC)
@@ -437,6 +448,18 @@
* Original code written by Keir Fraser.
*/
+static void __init apic_set_verbosity(char *str)
+{
+ if (strcmp("debug", str) == 0)
+ apic_verbosity = APIC_DEBUG;
+ else if (strcmp("verbose", str) == 0)
+ apic_verbosity = APIC_VERBOSE;
+ else
+ printk(KERN_WARNING "APIC Verbosity level %s not recognised"
+ " use apic=verbose or apic=debug", str);
+}
+custom_param("apic", apic_set_verbosity);
+
static int __init detect_init_APIC (void)
{
u32 h, l, features;
@@ -476,8 +499,10 @@
enabled_via_apicbase = 1;
}
}
-
- /* The APIC feature bit should now be enabled in `cpuid' */
+ /*
+ * The APIC feature bit should now be enabled
+ * in `cpuid'
+ */
features = cpuid_edx(1);
if (!(features & (1 << X86_FEATURE_APIC))) {
printk("Could not enable APIC!\n");
@@ -520,7 +545,8 @@
apic_phys = mp_lapic_addr;
set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
- Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
+ apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
+ apic_phys);
/*
* Fetch the APIC ID of the BSP in case we have a
@@ -552,8 +578,8 @@
ioapic_phys = __pa(ioapic_phys);
}
set_fixmap_nocache(idx, ioapic_phys);
- Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
- fix_to_virt(idx), ioapic_phys);
+ apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
+ __fix_to_virt(idx), ioapic_phys);
idx++;
}
}
@@ -604,37 +630,32 @@
/* next tick in 8254 can be caught by catching timer wraparound */
static void __init wait_8254_wraparound(void)
{
- unsigned int curr_count, prev_count=~0;
- int delta;
-
+ unsigned int curr_count, prev_count;
+
curr_count = get_8254_timer_count();
-
do {
prev_count = curr_count;
curr_count = get_8254_timer_count();
- delta = curr_count-prev_count;
- /*
- * This limit for delta seems arbitrary, but it isn't, it's slightly
- * above the level of error a buggy Mercury/Neptune chipset timer can
- * cause.
- */
- } while (delta < 300);
+ /* workaround for broken Mercury/Neptune */
+ if (prev_count >= curr_count + 0x100)
+ curr_count = get_8254_timer_count();
+
+ } while (prev_count >= curr_count);
}
/*
* Default initialization for 8254 timers. If we use other timers like HPET,
* we override this later
*/
-void (*wait_timer_tick)(void) = wait_8254_wraparound;
+void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
/*
* This function sets up the local APIC timer, with a timeout of
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