[Xen-changelog] Print status of Flush Filter on AMD64 processors during

[Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID b74c15e4dd4f77b11ecb3eb112b94e0dbbc14607
# Parent  d1ac7c6ffb639ac1367fbdcb81a02a2ab90658d2
Print status of Flush Filter on AMD64 processors during
Xen boot. Also provide a new boot parameter:
 amd_flush_filter=on  : Forcibly enable the Filter
 amd_flush_filter=off : Forcibly disable the Filter

Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>

diff -r d1ac7c6ffb63 -r b74c15e4dd4f xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Wed Aug 24 15:49:27 2005
+++ b/xen/arch/x86/cpu/amd.c    Wed Aug 24 16:15:42 2005
@@ -8,6 +8,20 @@
 #include <asm/processor.h>
 
 #include "cpu.h"
+
+/*
+ * amd_flush_filter={on,off}. Forcibly Enable or disable the TLB flush
+ * filter on AMD 64-bit processors.
+ */
+static int flush_filter_force;
+static void flush_filter(char *s)
+{
+       if (!strcmp(s, "off"))
+               flush_filter_force = -1;
+       if (!strcmp(s, "on"))
+               flush_filter_force = 1;
+}
+custom_param("amd_flush_filter", flush_filter);
 
 #define num_physpages 0
 
@@ -190,6 +204,21 @@
        case 6:
                set_bit(X86_FEATURE_K7, c->x86_capability); 
                break;
+       }
+
+       if (c->x86 == 15) {
+               rdmsr(MSR_K7_HWCR, l, h);
+               printk(KERN_INFO "CPU%d: AMD Flush Filter %sabled",
+                      smp_processor_id(), (l & (1<<6)) ? "dis" : "en");
+               if ((flush_filter_force > 0) && (l & (1<<6))) {
+                       l &= ~(1<<6);
+                       printk(" -> Forcibly enabled");
+               } else if ((flush_filter_force < 0) && !(l & (1<<6))) {
+                       l |= 1<<6;
+                       printk(" -> Forcibly disabled");
+               }
+               wrmsr(MSR_K7_HWCR, l, h);
+               printk("\n");
        }
 
        display_cacheinfo(c);

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