[Xen-changelog] Compute actual baud rate from UART divisor latch contents

[Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Node ID 50778f42f2dd1de222219b132717744784d35b5f
# Parent  5715cf1171787e91f11783d29923a953df494adb
Compute actual baud rate from UART divisor latch contents
when no baud rate is specified. Generalise the divisor
calculation based on external clock rate.

Signed-off-by: Keir Fraser <keir@xxxxxxxxxxxxx>

diff -r 5715cf117178 -r 50778f42f2dd xen/drivers/char/ns16550.c
--- a/xen/drivers/char/ns16550.c        Wed Mar 29 14:39:22 2006
+++ b/xen/drivers/char/ns16550.c        Wed Mar 29 15:02:40 2006
@@ -99,6 +99,9 @@
 #define PARITY_MARK     (5<<3)
 #define PARITY_SPACE    (7<<3)
 
+/* Frequency of external clock source. This definition assumes PC platform. */
+#define UART_CLOCK_HZ   1843200
+
 static char ns_read_reg(struct ns16550 *uart, int reg)
 {
     if ( uart->remapped_io_base == NULL )
@@ -171,6 +174,7 @@
 {
     struct ns16550 *uart = port->uart;
     unsigned char lcr;
+    unsigned int  divisor;
 
     /* I/O ports are distinguished by their size (16 bits). */
     if ( uart->io_base >= 0x10000 )
@@ -182,13 +186,22 @@
     ns_write_reg(uart, IER, 0);
 
     /* Line control and baud-rate generator. */
+    ns_write_reg(uart, LCR, lcr | LCR_DLAB);
     if ( uart->baud != BAUD_AUTO )
     {
-        ns_write_reg(uart, LCR, lcr | LCR_DLAB);
-        ns_write_reg(uart, DLL, 115200/uart->baud); /* baud lo */
-        ns_write_reg(uart, DLM, 0);                 /* baud hi */
-    }
-    ns_write_reg(uart, LCR, lcr);               /* parity, data, stop */
+        /* Baud rate specified: program it into the divisor latch. */
+        divisor = UART_CLOCK_HZ / (uart->baud * 16);
+        ns_write_reg(uart, DLL, (char)divisor);
+        ns_write_reg(uart, DLM, (char)(divisor >> 8));
+    }
+    else
+    {
+        /* Baud rate already set: read it out from the divisor latch. */
+        divisor  = ns_read_reg(uart, DLL);
+        divisor |= ns_read_reg(uart, DLM) << 8;
+        uart->baud = UART_CLOCK_HZ / (divisor * 16);
+    }
+    ns_write_reg(uart, LCR, lcr);
 
     /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
     ns_write_reg(uart, MCR, MCR_DTR | MCR_RTS);

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