[Xen-changelog] [IA64] Use16M page size in identity mapping

[Xen patchbot -unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID ffba1376c4fbb4add4a92f902e4f277dc6fbde45
# Parent  7c7bcf173f8b44ad706c65b30620b79ad152cd97
[IA64] Use16M page size in identity mapping

Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>

diff -r 7c7bcf173f8b -r ffba1376c4fb xen/arch/ia64/vmx/vmx_ivt.S
--- a/xen/arch/ia64/vmx/vmx_ivt.S       Tue Apr 25 20:53:38 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_ivt.S       Tue Apr 25 22:10:05 2006 -0600
@@ -283,7 +283,12 @@ vmx_alt_itlb_miss_1:
        and r18=0x10,r18        // bit 4=address-bit(61)
        or r19=r17,r19          // insert PTE control bits into r19
        ;;
+       movl r20=IA64_GRANULE_SHIFT<<2
        or r19=r19,r18          // set bit 4 (uncached) if the access was to 
region 6
+       ;;
+       mov cr.itir=r20
+       ;;
+       srlz.i
        ;;
        itc.i r19               // insert the TLB entry
        mov pr=r31,-1
@@ -332,6 +337,11 @@ vmx_alt_dtlb_miss_1:
        ;;
        or r19=r19,r18          // set bit 4 (uncached) if the access was to 
region 6
 (p6) mov cr.ipsr=r24
+       movl r20=IA64_GRANULE_SHIFT<<2
+       ;;
+       mov cr.itir=r20
+       ;;
+       srlz.i
        ;;
 (p7) itc.d r19         // insert the TLB entry
        mov pr=r31,-1

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog