[Xen-changelog] [xen-unstable] [IA64] install windows: multiple pagesize fix.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID 561df7d9cecc92d08bcc34ed45880062b06dc2e6
# Parent  b13ea287f9c02e3a3977d299a014a77e27dc1c0e
[IA64] install windows:  multiple pagesize fix.

I think windows only use page size >= prefer page size (8K)
It is true in terms of boot windows
But install windows uses 4k page size.
This patch is intended to handle this case.

Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>
---
 xen/arch/ia64/vmx/vmmu.c        |    4 ++--
 xen/arch/ia64/vmx/vmx_process.c |    4 ++--
 xen/arch/ia64/vmx/vtlb.c        |   10 ++++++++--
 xen/include/asm-ia64/vmmu.h     |    2 +-
 4 files changed, 13 insertions(+), 7 deletions(-)

diff -r b13ea287f9c0 -r 561df7d9cecc xen/arch/ia64/vmx/vmmu.c
--- a/xen/arch/ia64/vmx/vmmu.c  Wed Aug 02 15:04:03 2006 -0600
+++ b/xen/arch/ia64/vmx/vmmu.c  Wed Aug 02 15:09:56 2006 -0600
@@ -375,7 +375,7 @@ IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UIN
     }
 #endif //VTLB_DEBUG    
     pte &= ~PAGE_FLAGS_RV_MASK;
-    thash_purge_and_insert(vcpu, pte, itir, ifa);
+    thash_purge_and_insert(vcpu, pte, itir, ifa, ISIDE_TLB);
     return IA64_NO_FAULT;
 }
 
@@ -398,7 +398,7 @@ IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UIN
     gpfn = (pte & _PAGE_PPN_MASK)>> PAGE_SHIFT;
     if (VMX_DOMAIN(vcpu) && __gpfn_is_io(vcpu->domain, gpfn))
         pte |= VTLB_PTE_IO;
-    thash_purge_and_insert(vcpu, pte, itir, ifa);
+    thash_purge_and_insert(vcpu, pte, itir, ifa, DSIDE_TLB);
     return IA64_NO_FAULT;
 
 }
diff -r b13ea287f9c0 -r 561df7d9cecc xen/arch/ia64/vmx/vmx_process.c
--- a/xen/arch/ia64/vmx/vmx_process.c   Wed Aug 02 15:04:03 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_process.c   Wed Aug 02 15:09:56 2006 -0600
@@ -313,7 +313,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
                     ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST)) {
                     vcpu_get_rr(v, vadr, &rr);
                     itir = rr&(RR_RID_MASK | RR_PS_MASK);
-                    thash_purge_and_insert(v, pteval, itir , vadr);
+                    thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
                     return IA64_NO_FAULT;
                 }
                 if(vpsr.ic){
@@ -361,7 +361,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
                 if (pteval & _PAGE_P){
                     vcpu_get_rr(v, vadr, &rr);
                     itir = rr&(RR_RID_MASK | RR_PS_MASK);
-                    thash_purge_and_insert(v, pteval, itir , vadr);
+                    thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
                     return IA64_NO_FAULT;
                 }
                 if(!vpsr.ic){
diff -r b13ea287f9c0 -r 561df7d9cecc xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c  Wed Aug 02 15:04:03 2006 -0600
+++ b/xen/arch/ia64/vmx/vtlb.c  Wed Aug 02 15:09:56 2006 -0600
@@ -450,7 +450,7 @@ u64 translate_phy_pte(VCPU *v, u64 *pte,
  * Purge overlap TCs and then insert the new entry to emulate itc ops.
  *    Notes: Only TC entry can purge and insert.
  */
-void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa)
+void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa, int type)
 {
     u64 ps;//, va;
     u64 phy_pte;
@@ -490,8 +490,14 @@ void thash_purge_and_insert(VCPU *v, u64
             }
         }
         else {
+            u64 psr;
+            phy_pte  &= ~PAGE_FLAGS_RV_MASK;
+            psr = ia64_clear_ic();
+            ia64_itc(type + 1, ifa, phy_pte, ps);
+            ia64_set_psr(psr);
+            ia64_srlz_i();
             // ps < mrr.ps, this is not supported
-            panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
+            // panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
         }
     }
     else{
diff -r b13ea287f9c0 -r 561df7d9cecc xen/include/asm-ia64/vmmu.h
--- a/xen/include/asm-ia64/vmmu.h       Wed Aug 02 15:04:03 2006 -0600
+++ b/xen/include/asm-ia64/vmmu.h       Wed Aug 02 15:09:56 2006 -0600
@@ -270,7 +270,7 @@ extern thash_data_t *thash_find_next_ove
  *
  */
 extern void thash_purge_entries(struct vcpu *v, u64 va, u64 ps);
-extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
+extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa, 
int type);
 
 /*
  * Purge all TCs or VHPT entries including those in Hash table.

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