[Xen-changelog] [xen-unstable] [IA64] handle ld.s on guest tr mapped page (VTI)

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID 8c6bb45901e7679462bb5edbfb69ee34d8616e95
# Parent  5becaaabd33572fa0e119d6b8c6d60a76de06b25
[IA64] handle ld.s on guest tr mapped page (VTI)

Windows does an ld.s on a tr mapped page.
Currently xen/ipf uses tc/vtlb to emulate guest TR,
that may cause guest ld.s on tr page to be deferred, it is not correct.
For trapping this ld.s intruction, xen/ipf always set machine dcr.dm=0.

Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>
[Moved cr.dcr restore to only impact vti -> non-vti switch]
Signed-off-by: Alex Williamson <alex.williamson@xxxxxx>
---
 xen/arch/ia64/vmx/vmx_phy_mode.c |    3 ++-
 xen/arch/ia64/xen/domain.c       |   14 +++++++++++---
 xen/include/asm-ia64/vmx_vcpu.h  |    7 ++++---
 xen/include/asm-ia64/vmx_vpd.h   |    1 +
 4 files changed, 18 insertions(+), 7 deletions(-)

diff -r 5becaaabd335 -r 8c6bb45901e7 xen/arch/ia64/vmx/vmx_phy_mode.c
--- a/xen/arch/ia64/vmx/vmx_phy_mode.c  Wed Aug 16 10:40:17 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_phy_mode.c  Wed Aug 16 14:28:57 2006 -0600
@@ -195,7 +195,8 @@ vmx_load_all_rr(VCPU *vcpu)
                        (void *)vcpu->domain->shared_info,
                        (void *)vcpu->arch.privregs,
                        (void *)vcpu->arch.vhpt.hash, pal_vaddr );
-       ia64_set_pta(vcpu->arch.arch_vmx.mpta);
+       ia64_set_pta(VMX(vcpu, mpta));
+       ia64_set_dcr(VMX(vcpu, mdcr));
 
        ia64_srlz_d();
        ia64_set_psr(psr);
diff -r 5becaaabd335 -r 8c6bb45901e7 xen/arch/ia64/xen/domain.c
--- a/xen/arch/ia64/xen/domain.c        Wed Aug 16 10:40:17 2006 -0600
+++ b/xen/arch/ia64/xen/domain.c        Wed Aug 16 14:28:57 2006 -0600
@@ -136,10 +136,18 @@ void context_switch(struct vcpu *prev, s
 
     __ia64_save_fpu(prev->arch._thread.fph);
     __ia64_load_fpu(next->arch._thread.fph);
-    if (VMX_DOMAIN(prev))
-           vmx_save_state(prev);
+    if (VMX_DOMAIN(prev)) {
+       vmx_save_state(prev);
+       if (!VMX_DOMAIN(next)) {
+           /* VMX domains can change the physical cr.dcr.
+            * Restore default to prevent leakage. */
+           ia64_setreg(_IA64_REG_CR_DCR, (IA64_DCR_DP | IA64_DCR_DK
+                          | IA64_DCR_DX | IA64_DCR_DR | IA64_DCR_PP
+                          | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
+       }
+    }
     if (VMX_DOMAIN(next))
-           vmx_load_state(next);
+       vmx_load_state(next);
     /*ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next);*/
     prev = ia64_switch_to(next);
 
diff -r 5becaaabd335 -r 8c6bb45901e7 xen/include/asm-ia64/vmx_vcpu.h
--- a/xen/include/asm-ia64/vmx_vcpu.h   Wed Aug 16 10:40:17 2006 -0600
+++ b/xen/include/asm-ia64/vmx_vcpu.h   Wed Aug 16 14:28:57 2006 -0600
@@ -239,12 +239,13 @@ vmx_vcpu_set_dcr(VCPU *vcpu, u64 val)
 {
     u64 mdcr, mask;
     VCPU(vcpu,dcr)=val;
-    /* All vDCR bits will go to mDCR, except for be/pp bit */
+    /* All vDCR bits will go to mDCR, except for be/pp/dm bits */
     mdcr = ia64_get_dcr();
-    mask = IA64_DCR_BE | IA64_DCR_PP;
+    /* Machine dcr.dm masked to handle guest ld.s on tr mapped page */
+    mask = IA64_DCR_BE | IA64_DCR_PP | IA64_DCR_DM;
     mdcr = ( mdcr & mask ) | ( val & (~mask) );
     ia64_set_dcr( mdcr);
-
+    VMX(vcpu, mdcr) = mdcr;
     return IA64_NO_FAULT;
 }
 
diff -r 5becaaabd335 -r 8c6bb45901e7 xen/include/asm-ia64/vmx_vpd.h
--- a/xen/include/asm-ia64/vmx_vpd.h    Wed Aug 16 10:40:17 2006 -0600
+++ b/xen/include/asm-ia64/vmx_vpd.h    Wed Aug 16 14:28:57 2006 -0600
@@ -89,6 +89,7 @@ struct arch_vmx_struct {
 //    unsigned long   mrr5;
 //    unsigned long   mrr6;
 //    unsigned long   mrr7;
+    unsigned long   mdcr;
     unsigned long   mpta;
 //    unsigned long   rfi_pfs;
 //    unsigned long   rfi_iip;

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