[Xen-changelog] [xen-unstable] [XEN] Fix PAE writable-pte fixup to only trigger on writes to upper

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User kfraser@xxxxxxxxxxxxxxxxxxxxx
# Date 1169044665 0
# Node ID 0fd65225e4c637883622f871d9328425a237e12c
# Parent  e798c9010e9358e81a99a68e2bdd89c50ef5a560
[XEN] Fix PAE writable-pte fixup to only trigger on writes to upper
half the the PAE PTE.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
 xen/arch/x86/mm.c |   13 ++++++-------
 1 files changed, 6 insertions(+), 7 deletions(-)

diff -r e798c9010e93 -r 0fd65225e4c6 xen/arch/x86/mm.c
--- a/xen/arch/x86/mm.c Wed Jan 17 14:03:12 2007 +0000
+++ b/xen/arch/x86/mm.c Wed Jan 17 14:37:45 2007 +0000
@@ -3236,15 +3236,14 @@ static int ptwr_emulated_update(
     if ( unlikely(!get_page_from_l1e(gl1e_to_ml1e(d, nl1e), d)) )
     {
         if ( (CONFIG_PAGING_LEVELS == 3 || IS_COMPAT(d)) &&
-             (bytes == 4) &&
-             !do_cmpxchg &&
+             (bytes == 4) && (addr & 4) && !do_cmpxchg &&
              (l1e_get_flags(nl1e) & _PAGE_PRESENT) )
         {
             /*
-             * If this is a half-write to a PAE PTE then we assume that the
-             * guest has simply got the two writes the wrong way round. We
-             * zap the PRESENT bit on the assumption the bottom half will be
-             * written immediately after we return to the guest.
+             * If this is an upper-half write to a PAE PTE then we assume that
+             * the guest has simply got the two writes the wrong way round. We
+             * zap the PRESENT bit on the assumption that the bottom half will
+             * be written immediately after we return to the guest.
              */
             MEM_LOG("ptwr_emulate: fixing up invalid PAE PTE %"PRIpte,
                     l1e_get_intpte(nl1e));
@@ -3375,7 +3374,7 @@ int ptwr_do_page_fault(struct vcpu *v, u
          (page_get_owner(page) != d) )
         goto bail;
 
-    ptwr_ctxt.ctxt.regs = guest_cpu_user_regs();
+    ptwr_ctxt.ctxt.regs = regs;
     ptwr_ctxt.ctxt.addr_size = ptwr_ctxt.ctxt.sp_size =
         IS_COMPAT(d) ? 32 : BITS_PER_LONG;
     ptwr_ctxt.cr2 = addr;

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