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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen-unstable] [IA64] Rewrite ia64 vcpu_guest_context_regs structure
# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1178555836 21600
# Node ID 7c176473786b4e96723f8fb3cd794cc4db8923e9
# Parent 423055a4c972be35be880fff0b2cd37acd424c9a
[IA64] Rewrite ia64 vcpu_guest_context_regs structure
All registers and the rbs are now declared in the structure.
Minimal updates to other parts.
Signed-off-by: Tristan Gingold <tgingold@xxxxxxx>
---
tools/libxc/ia64/xc_ia64_hvm_build.c | 2
tools/libxc/ia64/xc_ia64_linux_restore.c | 3
tools/libxc/ia64/xc_ia64_linux_save.c | 3
tools/libxc/xc_dom_ia64.c | 12 -
tools/xentrace/xenctx.c | 180 ++++++++++++-------------
xen/arch/ia64/xen/domain.c | 215 +++++++++++++++++++++++++-----
xen/include/public/arch-ia64.h | 112 ++++++++++++++-
xen/include/public/foreign/reference.size | 4
8 files changed, 385 insertions(+), 146 deletions(-)
diff -r 423055a4c972 -r 7c176473786b tools/libxc/ia64/xc_ia64_hvm_build.c
--- a/tools/libxc/ia64/xc_ia64_hvm_build.c Mon May 07 08:56:28 2007 -0600
+++ b/tools/libxc/ia64/xc_ia64_hvm_build.c Mon May 07 10:37:16 2007 -0600
@@ -738,7 +738,7 @@ xc_hvm_build(int xc_handle, uint32_t dom
free(image);
- ctxt->user_regs.cr_iip = 0x80000000ffffffb0UL;
+ ctxt->regs.ip = 0x80000000ffffffb0UL;
memset(&launch_domctl, 0, sizeof(launch_domctl));
diff -r 423055a4c972 -r 7c176473786b tools/libxc/ia64/xc_ia64_linux_restore.c
--- a/tools/libxc/ia64/xc_ia64_linux_restore.c Mon May 07 08:56:28 2007 -0600
+++ b/tools/libxc/ia64/xc_ia64_linux_restore.c Mon May 07 10:37:16 2007 -0600
@@ -226,8 +226,7 @@ xc_domain_restore(int xc_handle, int io_
goto out;
}
- fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.user_regs.cr_iip,
- ctxt.user_regs.b0);
+ fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.regs.ip, ctxt.regs.b[0]);
/* First to initialize. */
domctl.cmd = XEN_DOMCTL_setvcpucontext;
diff -r 423055a4c972 -r 7c176473786b tools/libxc/ia64/xc_ia64_linux_save.c
--- a/tools/libxc/ia64/xc_ia64_linux_save.c Mon May 07 08:56:28 2007 -0600
+++ b/tools/libxc/ia64/xc_ia64_linux_save.c Mon May 07 10:37:16 2007 -0600
@@ -460,8 +460,7 @@ xc_domain_save(int xc_handle, int io_fd,
goto out;
}
- fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.user_regs.cr_iip,
- ctxt.user_regs.b0);
+ fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.regs.ip, ctxt.regs.b[0]);
mem = xc_map_foreign_range(xc_handle, dom, PAGE_SIZE,
PROT_READ|PROT_WRITE, ctxt.privregs_pfn);
diff -r 423055a4c972 -r 7c176473786b tools/libxc/xc_dom_ia64.c
--- a/tools/libxc/xc_dom_ia64.c Mon May 07 08:56:28 2007 -0600
+++ b/tools/libxc/xc_dom_ia64.c Mon May 07 10:37:16 2007 -0600
@@ -92,13 +92,13 @@ static int vcpu_ia64(struct xc_dom_image
memset(ctxt, 0, sizeof(*ctxt));
ctxt->flags = 0;
- ctxt->user_regs.cr_ipsr = 0; /* all necessary bits filled by hypervisor */
- ctxt->user_regs.cr_iip = dom->parms.virt_entry;
- ctxt->user_regs.cr_ifs = (uint64_t) 1 << 63;
-#ifdef __ia64__ /* FIXME */
- ctxt->user_regs.ar_fpsr = xc_ia64_fpsr_default();
+ ctxt->regs.psr = 0; /* all necessary bits filled by hypervisor */
+ ctxt->regs.ip = dom->parms.virt_entry;
+ ctxt->regs.cfm = (uint64_t) 1 << 63;
+#ifdef __ia64__ /* FIXME */
+ ctxt->regs.ar.fpsr = xc_ia64_fpsr_default();
#endif
- ctxt->user_regs.r28 = (dom->start_info_pfn << PAGE_SHIFT_IA64)
+ ctxt->regs.r[28] = (dom->start_info_pfn << PAGE_SHIFT_IA64)
+ sizeof(start_info_ia64_t);
return 0;
}
diff -r 423055a4c972 -r 7c176473786b tools/xentrace/xenctx.c
--- a/tools/xentrace/xenctx.c Mon May 07 08:56:28 2007 -0600
+++ b/tools/xentrace/xenctx.c Mon May 07 10:37:16 2007 -0600
@@ -45,12 +45,6 @@ int stack_trace = 0;
#define STACK_ROWS 4
#define STACK_COLS 4
#elif defined (__ia64__)
-#define FMT_SIZE_T "%016lx"
-#define STACK_POINTER(regs) (regs->r12)
-#define FRAME_POINTER(regs) 0
-#define INSTR_POINTER(regs) (regs->cr_iip)
-#define STACK_ROWS 4
-#define STACK_COLS 4
/* On ia64, we can't translate virtual address to physical address. */
#define NO_TRANSLATION
#endif
@@ -296,117 +290,117 @@ void print_ctx(vcpu_guest_context_t *ctx
void print_ctx(vcpu_guest_context_t *ctx1)
{
- struct cpu_user_regs *regs = &ctx1->user_regs;
- struct vcpu_extra_regs *er = &ctx1->extra_regs;
+ struct vcpu_guest_context_regs *regs = &ctx1->regs;
+ struct vcpu_tr_regs *tr = &ctx1->regs.tr;
int i, ps_val, ma_val;
unsigned long pa;
- const char ps[][5] = {" 4K", " 8K", " 16K", " ",
- " 64K", " ", "256K", " ",
- " 1M", " ", " 4M", " ",
- " 16M", " ", " 64M", " ",
- "256M"};
- const char ma[][4] = {"WB ", " ", " ", " ",
- "UC ", "UCE", "WC ", "Nat"};
-
- printf(" iip: %016lx ", regs->cr_iip);
- print_symbol(regs->cr_iip);
- printf("\n");
- printf(" ipsr: %016lx ", regs->cr_ipsr);
- printf(" b0: %016lx\n", regs->b0);
- printf(" b6: %016lx ", regs->b6);
- printf(" b7: %016lx\n", regs->b7);
- printf(" cr_ifs: %016lx ", regs->cr_ifs);
- printf(" ar_unat: %016lx\n", regs->ar_unat);
- printf(" ar_pfs: %016lx ", regs->ar_pfs);
- printf(" ar_rsc: %016lx\n", regs->ar_rsc);
- printf(" ar_rnat: %016lx ", regs->ar_rnat);
- printf(" ar_bspstore: %016lx\n", regs->ar_bspstore);
- printf(" ar_fpsr: %016lx ", regs->ar_fpsr);
- printf(" event_callback_ip: %016lx\n", er->event_callback_ip);
+ static const char ps[][5] = {" 4K", " 8K", " 16K", " ",
+ " 64K", " ", "256K", " ",
+ " 1M", " ", " 4M", " ",
+ " 16M", " ", " 64M", " ",
+ "256M"};
+ static const char ma[][4] = {"WB ", " ", " ", " ",
+ "UC ", "UCE", "WC ", "Nat"};
+
+ printf(" ip: %016lx ", regs->ip);
+ print_symbol(regs->ip);
+ printf("\n");
+ printf(" psr: %016lx ", regs->psr);
+ printf(" b0: %016lx\n", regs->b[0]);
+ printf(" b6: %016lx ", regs->b[6]);
+ printf(" b7: %016lx\n", regs->b[7]);
+ printf(" cfm: %016lx ", regs->cfm);
+ printf(" ar.unat: %016lx\n", regs->ar.unat);
+ printf(" ar.pfs: %016lx ", regs->ar.pfs);
+ printf(" ar.rsc: %016lx\n", regs->ar.rsc);
+ printf(" ar.rnat: %016lx ", regs->ar.rnat);
+ printf(" ar.bspstore: %016lx\n", regs->ar.bspstore);
+ printf(" ar.fpsr: %016lx ", regs->ar.fpsr);
+ printf(" event_callback_ip: %016lx\n", ctx1->event_callback_ip);
printf(" pr: %016lx ", regs->pr);
- printf(" loadrs: %016lx\n", regs->loadrs);
- printf(" iva: %016lx ", er->iva);
- printf(" dcr: %016lx\n", er->dcr);
-
- printf("\n");
- printf(" r1: %016lx\n", regs->r1);
- printf(" r2: %016lx ", regs->r2);
- printf(" r3: %016lx\n", regs->r3);
- printf(" r4: %016lx ", regs->r4);
- printf(" r5: %016lx\n", regs->r5);
- printf(" r6: %016lx ", regs->r6);
- printf(" r7: %016lx\n", regs->r7);
- printf(" r8: %016lx ", regs->r8);
- printf(" r9: %016lx\n", regs->r9);
- printf(" r10: %016lx ", regs->r10);
- printf(" r11: %016lx\n", regs->r11);
- printf(" sp: %016lx ", regs->r12);
- printf(" tp: %016lx\n", regs->r13);
- printf(" r14: %016lx ", regs->r14);
- printf(" r15: %016lx\n", regs->r15);
- printf(" r16: %016lx ", regs->r16);
- printf(" r17: %016lx\n", regs->r17);
- printf(" r18: %016lx ", regs->r18);
- printf(" r19: %016lx\n", regs->r19);
- printf(" r20: %016lx ", regs->r20);
- printf(" r21: %016lx\n", regs->r21);
- printf(" r22: %016lx ", regs->r22);
- printf(" r23: %016lx\n", regs->r23);
- printf(" r24: %016lx ", regs->r24);
- printf(" r25: %016lx\n", regs->r25);
- printf(" r26: %016lx ", regs->r26);
- printf(" r27: %016lx\n", regs->r27);
- printf(" r28: %016lx ", regs->r28);
- printf(" r29: %016lx\n", regs->r29);
- printf(" r30: %016lx ", regs->r30);
- printf(" r31: %016lx\n", regs->r31);
+ /* printf(" loadrs: %016lx\n", regs->loadrs); */
+ printf(" iva: %016lx\n", regs->cr.iva);
+ printf(" dcr: %016lx\n", regs->cr.dcr);
+
+ printf("\n");
+ printf(" r1: %016lx\n", regs->r[1]);
+ printf(" r2: %016lx ", regs->r[2]);
+ printf(" r3: %016lx\n", regs->r[3]);
+ printf(" r4: %016lx ", regs->r[4]);
+ printf(" r5: %016lx\n", regs->r[5]);
+ printf(" r6: %016lx ", regs->r[6]);
+ printf(" r7: %016lx\n", regs->r[7]);
+ printf(" r8: %016lx ", regs->r[8]);
+ printf(" r9: %016lx\n", regs->r[9]);
+ printf(" r10: %016lx ", regs->r[10]);
+ printf(" r11: %016lx\n", regs->r[11]);
+ printf(" sp: %016lx ", regs->r[12]);
+ printf(" tp: %016lx\n", regs->r[13]);
+ printf(" r14: %016lx ", regs->r[14]);
+ printf(" r15: %016lx\n", regs->r[15]);
+ printf(" r16: %016lx ", regs->r[16]);
+ printf(" r17: %016lx\n", regs->r[17]);
+ printf(" r18: %016lx ", regs->r[18]);
+ printf(" r19: %016lx\n", regs->r[19]);
+ printf(" r20: %016lx ", regs->r[20]);
+ printf(" r21: %016lx\n", regs->r[21]);
+ printf(" r22: %016lx ", regs->r[22]);
+ printf(" r23: %016lx\n", regs->r[23]);
+ printf(" r24: %016lx ", regs->r[24]);
+ printf(" r25: %016lx\n", regs->r[25]);
+ printf(" r26: %016lx ", regs->r[26]);
+ printf(" r27: %016lx\n", regs->r[27]);
+ printf(" r28: %016lx ", regs->r[28]);
+ printf(" r29: %016lx\n", regs->r[29]);
+ printf(" r30: %016lx ", regs->r[30]);
+ printf(" r31: %016lx\n", regs->r[31]);
printf("\n itr: P rid va pa ps ed pl "
"ar a d ma key\n");
for (i = 0; i < 8; i++) {
- ps_val = er->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
- ma_val = er->itrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
- pa = (er->itrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
+ ps_val = tr->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
+ ma_val = tr->itrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
+ pa = (tr->itrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
PTE_PPN_SHIFT;
pa = (pa >> ps_val) << ps_val;
printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld "
"%ld %d %s %06lx\n", i,
- er->itrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
- er->itrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
- er->itrs[i].vadr, pa, ps_val,
+ tr->itrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
+ tr->itrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
+ tr->itrs[i].vadr, pa, ps_val,
((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
ps[ps_val - ITIR_PS_MIN] : " "),
- er->itrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
- er->itrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
- er->itrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
- er->itrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
- er->itrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
+ tr->itrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
+ tr->itrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
+ tr->itrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
+ tr->itrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
+ tr->itrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
ma_val, ma[ma_val],
- er->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
+ tr->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
}
printf("\n dtr: P rid va pa ps ed pl "
"ar a d ma key\n");
for (i = 0; i < 8; i++) {
- ps_val = er->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
- ma_val = er->dtrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
- pa = (er->dtrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
+ ps_val = tr->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
+ ma_val = tr->dtrs[i].pte >> PTE_MA_SHIFT & PTE_MA_MASK;
+ pa = (tr->dtrs[i].pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
PTE_PPN_SHIFT;
pa = (pa >> ps_val) << ps_val;
printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld "
"%ld %d %s %06lx\n", i,
- er->dtrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
- er->dtrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
- er->dtrs[i].vadr, pa, ps_val,
+ tr->dtrs[i].pte >> PTE_P_SHIFT & PTE_P_MASK,
+ tr->dtrs[i].rid >> RR_RID_SHIFT & RR_RID_MASK,
+ tr->dtrs[i].vadr, pa, ps_val,
((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
ps[ps_val - ITIR_PS_MIN] : " "),
- er->dtrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
- er->dtrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
- er->dtrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
- er->dtrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
- er->dtrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
+ tr->dtrs[i].pte >> PTE_ED_SHIFT & PTE_ED_MASK,
+ tr->dtrs[i].pte >> PTE_PL_SHIFT & PTE_PL_MASK,
+ tr->dtrs[i].pte >> PTE_AR_SHIFT & PTE_AR_MASK,
+ tr->dtrs[i].pte >> PTE_A_SHIFT & PTE_A_MASK,
+ tr->dtrs[i].pte >> PTE_D_SHIFT & PTE_D_MASK,
ma_val, ma[ma_val],
- er->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
+ tr->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
}
}
#endif
@@ -526,8 +520,6 @@ void print_stack(vcpu_guest_context_t *c
}
}
}
-#else
-#define print_stack(ctx, vcpu)
#endif
void dump_ctx(int vcpu)
@@ -551,8 +543,10 @@ void dump_ctx(int vcpu)
}
print_ctx(&ctx);
+#ifndef NO_TRANSLATION
if (is_kernel_text(INSTR_POINTER((&ctx.user_regs))))
print_stack(&ctx, vcpu);
+#endif
ret = xc_domain_unpause(xc_handle, domid);
if (ret < 0) {
diff -r 423055a4c972 -r 7c176473786b xen/arch/ia64/xen/domain.c
--- a/xen/arch/ia64/xen/domain.c Mon May 07 08:56:28 2007 -0600
+++ b/xen/arch/ia64/xen/domain.c Mon May 07 10:37:16 2007 -0600
@@ -607,63 +607,210 @@ void arch_get_info_guest(struct vcpu *v,
void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
{
int i;
- struct vcpu_extra_regs *er = &c.nat->extra_regs;
-
- c.nat->user_regs = *vcpu_regs(v);
- c.nat->privregs_pfn = get_gpfn_from_mfn(virt_to_maddr(v->arch.privregs)
>>
- PAGE_SHIFT);
+ struct vcpu_tr_regs *tr = &c.nat->regs.tr;
+ struct cpu_user_regs *uregs = vcpu_regs(v);
+ int is_hvm = VMX_DOMAIN(v);
+
+ c.nat->regs.b[6] = uregs->b6;
+ c.nat->regs.b[7] = uregs->b7;
+
+ c.nat->regs.ar.csd = uregs->ar_csd;
+ c.nat->regs.ar.ssd = uregs->ar_ssd;
+
+ c.nat->regs.r[8] = uregs->r8;
+ c.nat->regs.r[9] = uregs->r9;
+ c.nat->regs.r[10] = uregs->r10;
+ c.nat->regs.r[11] = uregs->r11;
+
+ if (is_hvm) {
+ c.nat->regs.psr = vmx_vcpu_get_psr (v);
+ } else {
+ /* FIXME: get the vpsr. */
+ c.nat->regs.psr = uregs->cr_ipsr;
+ }
+
+ c.nat->regs.ip = uregs->cr_iip;
+ c.nat->regs.cfm = uregs->cr_ifs;
+
+ c.nat->regs.ar.unat = uregs->ar_unat;
+ c.nat->regs.ar.pfs = uregs->ar_pfs;
+ c.nat->regs.ar.rsc = uregs->ar_rsc;
+ c.nat->regs.ar.rnat = uregs->ar_rnat;
+ c.nat->regs.ar.bspstore = uregs->ar_bspstore;
+
+ c.nat->regs.pr = uregs->pr;
+ c.nat->regs.b[0] = uregs->b0;
+ c.nat->regs.ar.bsp = uregs->ar_bspstore + (uregs->loadrs >> 16);
+
+ c.nat->regs.r[1] = uregs->r1;
+ c.nat->regs.r[12] = uregs->r12;
+ c.nat->regs.r[13] = uregs->r13;
+ c.nat->regs.ar.fpsr = uregs->ar_fpsr;
+ c.nat->regs.r[15] = uregs->r15;
+
+ c.nat->regs.r[14] = uregs->r14;
+ c.nat->regs.r[2] = uregs->r2;
+ c.nat->regs.r[3] = uregs->r3;
+ c.nat->regs.r[16] = uregs->r16;
+ c.nat->regs.r[17] = uregs->r17;
+ c.nat->regs.r[18] = uregs->r18;
+ c.nat->regs.r[19] = uregs->r19;
+ c.nat->regs.r[20] = uregs->r20;
+ c.nat->regs.r[21] = uregs->r21;
+ c.nat->regs.r[22] = uregs->r22;
+ c.nat->regs.r[23] = uregs->r23;
+ c.nat->regs.r[24] = uregs->r24;
+ c.nat->regs.r[25] = uregs->r25;
+ c.nat->regs.r[26] = uregs->r26;
+ c.nat->regs.r[27] = uregs->r27;
+ c.nat->regs.r[28] = uregs->r28;
+ c.nat->regs.r[29] = uregs->r29;
+ c.nat->regs.r[30] = uregs->r30;
+ c.nat->regs.r[31] = uregs->r31;
+
+ c.nat->regs.ar.ccv = uregs->ar_ccv;
+
+ c.nat->regs.f[6] = uregs->f6;
+ c.nat->regs.f[7] = uregs->f7;
+ c.nat->regs.f[8] = uregs->f8;
+ c.nat->regs.f[9] = uregs->f9;
+ c.nat->regs.f[10] = uregs->f10;
+ c.nat->regs.f[11] = uregs->f11;
+
+ c.nat->regs.r[4] = uregs->r4;
+ c.nat->regs.r[5] = uregs->r5;
+ c.nat->regs.r[6] = uregs->r6;
+ c.nat->regs.r[7] = uregs->r7;
+
+ /* FIXME: to be reordered. */
+ c.nat->regs.nats = uregs->eml_unat;
+
+ c.nat->privregs_pfn = get_gpfn_from_mfn
+ (virt_to_maddr(v->arch.privregs) >> PAGE_SHIFT);
/* Fill extra regs. */
for (i = 0; i < 8; i++) {
- er->itrs[i].pte = v->arch.itrs[i].pte.val;
- er->itrs[i].itir = v->arch.itrs[i].itir;
- er->itrs[i].vadr = v->arch.itrs[i].vadr;
- er->itrs[i].rid = v->arch.itrs[i].rid;
+ tr->itrs[i].pte = v->arch.itrs[i].pte.val;
+ tr->itrs[i].itir = v->arch.itrs[i].itir;
+ tr->itrs[i].vadr = v->arch.itrs[i].vadr;
+ tr->itrs[i].rid = v->arch.itrs[i].rid;
}
for (i = 0; i < 8; i++) {
- er->dtrs[i].pte = v->arch.dtrs[i].pte.val;
- er->dtrs[i].itir = v->arch.dtrs[i].itir;
- er->dtrs[i].vadr = v->arch.dtrs[i].vadr;
- er->dtrs[i].rid = v->arch.dtrs[i].rid;
- }
- er->event_callback_ip = v->arch.event_callback_ip;
- er->dcr = v->arch.privregs ? PSCB(v,dcr) : 0;
- er->iva = v->arch.iva;
+ tr->dtrs[i].pte = v->arch.dtrs[i].pte.val;
+ tr->dtrs[i].itir = v->arch.dtrs[i].itir;
+ tr->dtrs[i].vadr = v->arch.dtrs[i].vadr;
+ tr->dtrs[i].rid = v->arch.dtrs[i].rid;
+ }
+ c.nat->event_callback_ip = v->arch.event_callback_ip;
+
+ /* If PV and privregs is not set, we can't read mapped registers. */
+ if (!v->domain->arch.is_vti && v->arch.privregs == NULL)
+ return;
+
+ vcpu_get_dcr (v, &c.nat->regs.cr.dcr);
+ vcpu_get_iva (v, &c.nat->regs.cr.iva);
}
int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
{
- struct pt_regs *regs = vcpu_regs (v);
+ struct cpu_user_regs *uregs = vcpu_regs(v);
struct domain *d = v->domain;
int rc;
+
+ uregs->b6 = c.nat->regs.b[6];
+ uregs->b7 = c.nat->regs.b[7];
- *regs = c.nat->user_regs;
-
+ uregs->ar_csd = c.nat->regs.ar.csd;
+ uregs->ar_ssd = c.nat->regs.ar.ssd;
+
+ uregs->r8 = c.nat->regs.r[8];
+ uregs->r9 = c.nat->regs.r[9];
+ uregs->r10 = c.nat->regs.r[10];
+ uregs->r11 = c.nat->regs.r[11];
+
+ uregs->cr_ipsr = c.nat->regs.psr;
+ uregs->cr_iip = c.nat->regs.ip;
+ uregs->cr_ifs = c.nat->regs.cfm;
+
+ uregs->ar_unat = c.nat->regs.ar.unat;
+ uregs->ar_pfs = c.nat->regs.ar.pfs;
+ uregs->ar_rsc = c.nat->regs.ar.rsc;
+ uregs->ar_rnat = c.nat->regs.ar.rnat;
+ uregs->ar_bspstore = c.nat->regs.ar.bspstore;
+
+ uregs->pr = c.nat->regs.pr;
+ uregs->b0 = c.nat->regs.b[0];
+ uregs->loadrs = (c.nat->regs.ar.bsp - c.nat->regs.ar.bspstore) << 16;
+
+ uregs->r1 = c.nat->regs.r[1];
+ uregs->r12 = c.nat->regs.r[12];
+ uregs->r13 = c.nat->regs.r[13];
+ uregs->ar_fpsr = c.nat->regs.ar.fpsr;
+ uregs->r15 = c.nat->regs.r[15];
+
+ uregs->r14 = c.nat->regs.r[14];
+ uregs->r2 = c.nat->regs.r[2];
+ uregs->r3 = c.nat->regs.r[3];
+ uregs->r16 = c.nat->regs.r[16];
+ uregs->r17 = c.nat->regs.r[17];
+ uregs->r18 = c.nat->regs.r[18];
+ uregs->r19 = c.nat->regs.r[19];
+ uregs->r20 = c.nat->regs.r[20];
+ uregs->r21 = c.nat->regs.r[21];
+ uregs->r22 = c.nat->regs.r[22];
+ uregs->r23 = c.nat->regs.r[23];
+ uregs->r24 = c.nat->regs.r[24];
+ uregs->r25 = c.nat->regs.r[25];
+ uregs->r26 = c.nat->regs.r[26];
+ uregs->r27 = c.nat->regs.r[27];
+ uregs->r28 = c.nat->regs.r[28];
+ uregs->r29 = c.nat->regs.r[29];
+ uregs->r30 = c.nat->regs.r[30];
+ uregs->r31 = c.nat->regs.r[31];
+
+ uregs->ar_ccv = c.nat->regs.ar.ccv;
+
+ uregs->f6 = c.nat->regs.f[6];
+ uregs->f7 = c.nat->regs.f[7];
+ uregs->f8 = c.nat->regs.f[8];
+ uregs->f9 = c.nat->regs.f[9];
+ uregs->f10 = c.nat->regs.f[10];
+ uregs->f11 = c.nat->regs.f[11];
+
+ uregs->r4 = c.nat->regs.r[4];
+ uregs->r5 = c.nat->regs.r[5];
+ uregs->r6 = c.nat->regs.r[6];
+ uregs->r7 = c.nat->regs.r[7];
+
+ /* FIXME: to be reordered and restored. */
+ /* uregs->eml_unat = c.nat->regs.nat; */
+ uregs->eml_unat = 0;
+
if (!d->arch.is_vti) {
/* domain runs at PL2/3 */
- regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
- regs->ar_rsc |= (2 << 2); /* force PL2/3 */
+ uregs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
+ uregs->ar_rsc |= (2 << 2); /* force PL2/3 */
}
if (c.nat->flags & VGCF_EXTRA_REGS) {
int i;
- struct vcpu_extra_regs *er = &c.nat->extra_regs;
+ struct vcpu_tr_regs *tr = &c.nat->regs.tr;
for (i = 0; i < 8; i++) {
- vcpu_set_itr(v, i, er->itrs[i].pte,
- er->itrs[i].itir,
- er->itrs[i].vadr,
- er->itrs[i].rid);
+ vcpu_set_itr(v, i, tr->itrs[i].pte,
+ tr->itrs[i].itir,
+ tr->itrs[i].vadr,
+ tr->itrs[i].rid);
}
for (i = 0; i < 8; i++) {
vcpu_set_dtr(v, i,
- er->dtrs[i].pte,
- er->dtrs[i].itir,
- er->dtrs[i].vadr,
- er->dtrs[i].rid);
- }
- v->arch.event_callback_ip = er->event_callback_ip;
- v->arch.iva = er->iva;
+ tr->dtrs[i].pte,
+ tr->dtrs[i].itir,
+ tr->dtrs[i].vadr,
+ tr->dtrs[i].rid);
+ }
+ v->arch.event_callback_ip = c.nat->event_callback_ip;
+ v->arch.iva = c.nat->regs.cr.iva;
}
if (v->is_initialised)
diff -r 423055a4c972 -r 7c176473786b xen/include/public/arch-ia64.h
--- a/xen/include/public/arch-ia64.h Mon May 07 08:56:28 2007 -0600
+++ b/xen/include/public/arch-ia64.h Mon May 07 10:37:16 2007 -0600
@@ -337,20 +337,120 @@ struct ia64_tr_entry {
unsigned long rid;
};
-struct vcpu_extra_regs {
+struct vcpu_tr_regs {
struct ia64_tr_entry itrs[8];
struct ia64_tr_entry dtrs[8];
- unsigned long iva;
- unsigned long dcr;
- unsigned long event_callback_ip;
+};
+
+union vcpu_ar_regs {
+ unsigned long ar[128];
+ struct {
+ unsigned long kr[8];
+ unsigned long rsv1[8];
+ unsigned long rsc;
+ unsigned long bsp;
+ unsigned long bspstore;
+ unsigned long rnat;
+ unsigned long rsv2;
+ unsigned long fcr;
+ unsigned long rsv3[2];
+ unsigned long eflag;
+ unsigned long csd;
+ unsigned long ssd;
+ unsigned long cflg;
+ unsigned long fsr;
+ unsigned long fir;
+ unsigned long fdr;
+ unsigned long rsv4;
+ unsigned long ccv; /* 32 */
+ unsigned long rsv5[3];
+ unsigned long unat;
+ unsigned long rsv6[3];
+ unsigned long fpsr;
+ unsigned long rsv7[3];
+ unsigned long itc;
+ unsigned long rsv8[3];
+ unsigned long ign1[16];
+ unsigned long pfs; /* 64 */
+ unsigned long lc;
+ unsigned long ec;
+ unsigned long rsv9[45];
+ unsigned long ign2[16];
+ };
+};
+
+union vcpu_cr_regs {
+ unsigned long cr[128];
+ struct {
+ unsigned long dcr; // CR0
+ unsigned long itm;
+ unsigned long iva;
+ unsigned long rsv1[5];
+ unsigned long pta; // CR8
+ unsigned long rsv2[7];
+ unsigned long ipsr; // CR16
+ unsigned long isr;
+ unsigned long rsv3;
+ unsigned long iip;
+ unsigned long ifa;
+ unsigned long itir;
+ unsigned long iipa;
+ unsigned long ifs;
+ unsigned long iim; // CR24
+ unsigned long iha;
+ unsigned long rsv4[38];
+ unsigned long lid; // CR64
+ unsigned long ivr;
+ unsigned long tpr;
+ unsigned long eoi;
+ unsigned long irr[4];
+ unsigned long itv; // CR72
+ unsigned long pmv;
+ unsigned long cmcv;
+ unsigned long rsv5[5];
+ unsigned long lrr0; // CR80
+ unsigned long lrr1;
+ unsigned long rsv6[46];
+ };
+};
+
+struct vcpu_guest_context_regs {
+ unsigned long r[32];
+ unsigned long b[8];
+ unsigned long bank[16];
+ unsigned long ip;
+ unsigned long psr;
+ unsigned long cfm;
+ unsigned long pr;
+ unsigned long nats; /* NaT bits for r1-r31. */
+ union vcpu_ar_regs ar;
+ union vcpu_cr_regs cr;
+ struct pt_fpreg f[128];
+ unsigned long dbr[8];
+ unsigned long ibr[8];
+ unsigned long rr[8];
+ unsigned long pkr[16];
+
+ /* FIXME: cpuid,pmd,pmc */
+
+ unsigned long xip;
+ unsigned long xpsr;
+ unsigned long xfs;
+ unsigned long xr[4];
+
+ struct vcpu_tr_regs tr;
+
+ /* Note: loadrs is 2**14 bytes == 2**11 slots. */
+ unsigned long rbs[2048];
};
struct vcpu_guest_context {
#define VGCF_EXTRA_REGS (1<<1) /* Get/Set extra regs. */
unsigned long flags; /* VGCF_* flags */
- struct cpu_user_regs user_regs;
- struct vcpu_extra_regs extra_regs;
+ struct vcpu_guest_context_regs regs;
+
+ unsigned long event_callback_ip;
unsigned long privregs_pfn;
};
typedef struct vcpu_guest_context vcpu_guest_context_t;
diff -r 423055a4c972 -r 7c176473786b xen/include/public/foreign/reference.size
--- a/xen/include/public/foreign/reference.size Mon May 07 08:56:28 2007 -0600
+++ b/xen/include/public/foreign/reference.size Mon May 07 10:37:16 2007 -0600
@@ -7,8 +7,8 @@ cpu_user_regs | 68 200
cpu_user_regs | 68 200 496
xen_ia64_boot_param | - - 96
ia64_tr_entry | - - 32
-vcpu_extra_regs | - - 536
-vcpu_guest_context | 2800 5168 1056
+vcpu_extra_regs | - - -
+vcpu_guest_context | 2800 5168 21904
arch_vcpu_info | 24 16 0
vcpu_time_info | 32 32 32
vcpu_info | 64 64 48
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