[Xen-changelog] [xen-unstable] [IA64] Remove vmx_ivt.S debug code.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1181142652 21600
# Node ID 9daa40cae3d6548f404bcfd4300e604185db6b64
# Parent  0cf6b75423e92ec898cdb43a5ba0f3c3edfee14f
[IA64] Remove vmx_ivt.S debug code.

Signed-off-by: Tristan Gingold <tgingold@xxxxxxx>
---
 xen/arch/ia64/vmx/vmx_ivt.S |   14 ++++----------
 1 files changed, 4 insertions(+), 10 deletions(-)

diff -r 0cf6b75423e9 -r 9daa40cae3d6 xen/arch/ia64/vmx/vmx_ivt.S
--- a/xen/arch/ia64/vmx/vmx_ivt.S       Mon Jun 04 14:17:54 2007 -0600
+++ b/xen/arch/ia64/vmx/vmx_ivt.S       Wed Jun 06 09:10:52 2007 -0600
@@ -315,9 +315,6 @@ vmx_alt_itlb_miss_1:
 vmx_alt_itlb_miss_1:
     mov r16=cr.ifa    // get address that caused the TLB miss
     ;;
-    tbit.z p6,p7=r16,63
-(p6)br.spnt vmx_fault_3
-    ;;
     movl r17=PAGE_KERNEL
     mov r24=cr.ipsr
     movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
@@ -328,8 +325,8 @@ vmx_alt_itlb_miss_1:
     and r18=0x10,r18    // bit 4=address-bit(61)
     or r19=r17,r19      // insert PTE control bits into r19
     ;;
-    movl r20=IA64_GRANULE_SHIFT<<2
-    or r19=r19,r18     // set bit 4 (uncached) if the access was to region 6
+    mov r20=IA64_GRANULE_SHIFT<<2
+    or r19=r19,r18     // set bit 4 (uncached) if the access was to UC region
     ;;
     mov cr.itir=r20
     ;;
@@ -359,9 +356,6 @@ vmx_alt_dtlb_miss_1:
     cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
 (p8)br.cond.sptk frametable_miss ;;
 #endif
-    tbit.z p6,p7=r16,63
-(p6)br.spnt vmx_fault_4
-    ;;
     movl r17=PAGE_KERNEL
     mov r20=cr.isr
     movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
@@ -378,9 +372,9 @@ vmx_alt_dtlb_miss_1:
     dep r24=-1,r24,IA64_PSR_ED_BIT,1
     or r19=r19,r17                             // insert PTE control bits into 
r19
     ;;
-    or r19=r19,r18                             // set bit 4 (uncached) if the 
access was to region 6
+    or r19=r19,r18                             // set bit 4 (uncached) if the 
access was to UC region
 (p6)mov cr.ipsr=r24
-    movl r20=IA64_GRANULE_SHIFT<<2
+    mov r20=IA64_GRANULE_SHIFT<<2
     ;;
     mov cr.itir=r20
     ;;

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