[Xen-changelog] [xen-unstable] [IA64] Rearrange IA64_TR_ definitions to use from lower value

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1200596743 25200
# Node ID ac296153ea64a450e97f8a951d916966620c706f
# Parent  64653720c9e41bb575af1d56906b68e85be5462f
[IA64] Rearrange IA64_TR_ definitions to use from lower value

SDM vol2 4.1.1.1 says that:
 "software should allocate contiguous translation registers starting
  at slot 0 and continuing upwards."

Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
---
 xen/include/asm-ia64/xenkregs.h |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff -r 64653720c9e4 -r ac296153ea64 xen/include/asm-ia64/xenkregs.h
--- a/xen/include/asm-ia64/xenkregs.h   Thu Jan 17 12:05:43 2008 -0700
+++ b/xen/include/asm-ia64/xenkregs.h   Thu Jan 17 12:05:43 2008 -0700
@@ -4,10 +4,11 @@
 /*
  * Translation registers:
  */
-#define IA64_TR_SHARED_INFO    3       /* dtr3: page shared with domain */
-#define        IA64_TR_VHPT            4       /* dtr4: vhpt */
+#define IA64_TR_XEN_HEAP_REGS  3       /* dtr3: xen heap identity mapped regs 
*/
+#define IA64_TR_SHARED_INFO    4       /* dtr4: page shared with domain */
 #define IA64_TR_MAPPED_REGS    5       /* dtr5: vcpu mapped regs */
-#define IA64_TR_XEN_HEAP_REGS  6       /* dtr6: xen heap identity mapped regs 
*/
+#define        IA64_TR_VHPT            6       /* dtr6: vhpt */
+
 #define IA64_DTR_GUEST_KERNEL   7
 #define IA64_ITR_GUEST_KERNEL   2
 /* Processor status register bits: */

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