[Xen-changelog] [xen-unstable] x86, intel: Clear Error counter field when set new cmci owner

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1230557414 0
# Node ID c54d6f871de8f271aaeb571c3b87eae9165e3183
# Parent  e2f36d066b7b66a538bbe240d46f49bede51d9ed
x86, intel: Clear Error counter field when set new cmci owner

Since cmci might happened when cpu is taking down (cpu hotplug) before
setting new cmci owner while old owner is down. We need to clear the
corrected error counter field to make sure CMCI could be triggered on
the new owner.

Signed-off-by: Yunhong Jiang <yunhong.jiang@xxxxxxxxx>
Signed-off-by: Liping Ke <liping.ke@xxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce_intel.c |    6 ++++++
 xen/arch/x86/cpu/mcheck/x86_mca.h   |    2 ++
 2 files changed, 8 insertions(+)

diff -r e2f36d066b7b -r c54d6f871de8 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c       Mon Dec 22 13:48:40 2008 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c       Mon Dec 29 13:30:14 2008 +0000
@@ -358,6 +358,12 @@ static int do_cmci_discover(int i)
         return 0;
     }
     set_bit(i, __get_cpu_var(mce_banks_owned));
+    /* Clear Corected Error Counter field, make sure CMCI could 
+     * be triggered on the new owner
+     */
+    msr = MSR_IA32_MC0_STATUS + 4 * i;
+    rdmsrl(msr, val);
+    wrmsrl(msr, val & ~MCi_STATUS_ERRCOUNT);
 out:
     clear_bit(i, __get_cpu_var(no_cmci_banks));
     return 1;
diff -r e2f36d066b7b -r c54d6f871de8 xen/arch/x86/cpu/mcheck/x86_mca.h
--- a/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Dec 22 13:48:40 2008 +0000
+++ b/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Dec 29 13:30:14 2008 +0000
@@ -46,6 +46,8 @@
 #define MCi_STATUS_MSEC         0x00000000ffff0000ULL
 /* Other information */
 #define MCi_STATUS_OTHER        0x01ffffff00000000ULL
+/*Corrected Error Count*/
+#define MCi_STATUS_ERRCOUNT     0x001FFFC0000000000ULL 
 /* processor context corrupt */
 #define MCi_STATUS_PCC          0x0200000000000000ULL
 /* MSR_K8_MCi_ADDR register valid */

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