[Xen-changelog] [xen-unstable] x86: Small fix for gpf when writing 1s to MCi_STATUS MSRs.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1235989952 0
# Node ID 16fc70ce40a73c191427487845449715849a2809
# Parent  6f207d1eee5c21452d4527fe202c5a3f4d2b815c
x86: Small fix for gpf when writing 1s to MCi_STATUS MSRs.

According to spec, only 0s is allowed to be written. This error is
found when do cpu-offline, cmci happens.
For avoiding missing future cmci after changing cmci owner, we need to
process pending cmci errors to clear MCi_STATUS MSRs.

Signed-off-by: Ke Liping <liping.ke@xxxxxxxxx>
Signed-off-by: Jiang Yunhong <yunhong.jiang@xxxxxxxxx>
---
 xen/arch/x86/cpu/mcheck/mce_intel.c |   19 +++++++++++++------
 xen/arch/x86/cpu/mcheck/x86_mca.h   |    2 --
 2 files changed, 13 insertions(+), 8 deletions(-)

diff -r 6f207d1eee5c -r 16fc70ce40a7 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c       Mon Mar 02 10:31:16 2009 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c       Mon Mar 02 10:32:32 2009 +0000
@@ -359,12 +359,6 @@ static int do_cmci_discover(int i)
         return 0;
     }
     set_bit(i, __get_cpu_var(mce_banks_owned));
-    /* Clear Corected Error Counter field, make sure CMCI could 
-     * be triggered on the new owner
-     */
-    msr = MSR_IA32_MC0_STATUS + 4 * i;
-    rdmsrl(msr, val);
-    wrmsrl(msr, val & ~MCi_STATUS_ERRCOUNT);
 out:
     clear_bit(i, __get_cpu_var(no_cmci_banks));
     return 1;
@@ -374,6 +368,7 @@ static void cmci_discover(void)
 {
     unsigned long flags;
     int i;
+    struct mc_info *mi = NULL;
 
     printk(KERN_DEBUG "CMCI: find owner on CPU%d\n", smp_processor_id());
 
@@ -384,6 +379,18 @@ static void cmci_discover(void)
             do_cmci_discover(i);
 
     spin_unlock_irqrestore(&cmci_discover_lock, flags);
+
+    /* In case CMCI happended when do owner change.
+     * If CMCI happened yet not processed immediately,
+     * MCi_status (error_count bit 38~52) is not cleared,
+     * the CMCI interrupt will never be triggered again.
+     */
+    mi = machine_check_poll(MC_FLAG_CMCI);
+    if (mi) {
+        x86_mcinfo_dump(mi);
+        if (dom0 && guest_enabled_event(dom0->vcpu[0], VIRQ_MCA))
+            send_guest_global_virq(dom0, VIRQ_MCA);
+    }
 
     printk(KERN_DEBUG "CMCI: CPU%d owner_map[%lx], no_cmci_map[%lx]\n", 
            smp_processor_id(), 
diff -r 6f207d1eee5c -r 16fc70ce40a7 xen/arch/x86/cpu/mcheck/x86_mca.h
--- a/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Mar 02 10:31:16 2009 +0000
+++ b/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Mar 02 10:32:32 2009 +0000
@@ -46,8 +46,6 @@
 #define MCi_STATUS_MSEC         0x00000000ffff0000ULL
 /* Other information */
 #define MCi_STATUS_OTHER        0x01ffffff00000000ULL
-/*Corrected Error Count*/
-#define MCi_STATUS_ERRCOUNT     0x001FFFC0000000000ULL 
 /* processor context corrupt */
 #define MCi_STATUS_PCC          0x0200000000000000ULL
 /* MSR_K8_MCi_ADDR register valid */

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