[Xen-changelog] [xen-unstable] x86: Support more than 256 pins of ioapic.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1253625531 -3600
# Node ID 6a931ed48f1946bbae3ca39053daf77b75f04edf
# Parent  4ad29157dcd73f76999b4046518f26d79f4067b6
x86: Support more than 256 pins of ioapic.

Some large system may have many ioapics which
have more than 256 pins totally. To support this
case, just let pirq == irq and build 1:1 mapping
between them, and this is based on the assumpation
that pirq == GSI number in dom0 for iopaic IRQs.

Thank Jan Beulich from Novell for reporting the issue
in pv_ops dom0.

Signed-off-by: Xiantao Zhang <xiantao.zhang@xxxxxxxxx>
---
 xen/arch/x86/io_apic.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)

diff -r 4ad29157dcd7 -r 6a931ed48f19 xen/arch/x86/io_apic.c
--- a/xen/arch/x86/io_apic.c    Tue Sep 22 14:11:09 2009 +0100
+++ b/xen/arch/x86/io_apic.c    Tue Sep 22 14:18:51 2009 +0100
@@ -2193,12 +2193,14 @@ int ioapic_guest_write(unsigned long phy
     desc = irq_to_desc(irq);
     cfg = desc->chip_data;
 
-    /* Since PHYSDEVOP_alloc_irq_vector is dummy, rte.vector is the pirq
-       which corresponds to this ioapic pin, retrieve it for building
-       pirq and irq mapping. 
-     */
-    pirq = rte.vector;
-    if(pirq < 0 || pirq >= dom0->nr_pirqs)
+    /*
+     * Since PHYSDEVOP_alloc_irq_vector is dummy, rte.vector is the pirq
+     * which corresponds to this ioapic pin, retrieve it for building
+     * pirq and irq mapping. Where the GSI is greater than 256, we assume
+     * that dom0 pirq == irq.
+     */
+    pirq = (irq >= 256) ? irq : rte.vector;
+    if ( (pirq < 0) || (pirq >= dom0->nr_pirqs) )
         return -EINVAL;
     
     if ( desc->action )

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