[Xen-changelog] [xen-unstable] x86: Enable TSC_RELIABLE for AMD servers

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1256289317 -3600
# Node ID 8ca4e32583b6ebaf7208df1bfd9dbc21b917e9a2
# Parent  e36ffdd9e8cf2ce70abcb07e99ad90d8919a2649
x86: Enable TSC_RELIABLE for AMD servers

Except for a published BIOS errata on family 11h processors,
all AMD servers that have the Invariant TSC bit set have
a reliable TSC so Xen should not write to the TSC.

Signed-off-by: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>
Acked-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>
---
 xen/arch/x86/cpu/amd.c |    2 ++
 1 files changed, 2 insertions(+)

diff -r e36ffdd9e8cf -r 8ca4e32583b6 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Fri Oct 23 10:13:52 2009 +0100
+++ b/xen/arch/x86/cpu/amd.c    Fri Oct 23 10:15:17 2009 +0100
@@ -465,6 +465,8 @@ static void __devinit init_amd(struct cp
                if (c->x86_power & (1<<8)) {
                        set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
                        set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+                       if (c->x86 != 0x11)
+                               set_bit(X86_FEATURE_TSC_RELIABLE, 
c->x86_capability);
                }
        }
 

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