[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen-3.4-testing] Add MSR support for various feature AMD processor families.
# HG changeset patch # User Keir Fraser <keir.fraser@xxxxxxxxxx> # Date 1273909477 -3600 # Node ID 4c5acce5961c1fcd7eccb8ddbe4abbf3b12ab5c3 # Parent d11bdc25b36d1c852117d308fe70db461f5dabe8 Add MSR support for various feature AMD processor families. Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx> xen-unstable changeset: 21393:3dfc577c8b9e xen-unstable date: Sat May 15 08:29:59 2010 +0100 --- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu/amd.c | 7 +++---- xen/arch/x86/cpu/mcheck/mce.c | 2 +- xen/arch/x86/nmi.c | 2 +- xen/arch/x86/oprofile/nmi_int.c | 12 ++++++++++++ xen/arch/x86/traps.c | 7 +++---- 6 files changed, 21 insertions(+), 11 deletions(-) diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/apic.c --- a/xen/arch/x86/apic.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/apic.c Sat May 15 08:44:37 2010 +0100 @@ -775,7 +775,7 @@ static int __init detect_init_APIC (void switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || - (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17)) + (boot_cpu_data.x86 >= 0xf && boot_cpu_data.x86 <= 0x17)) break; goto no_apic; case X86_VENDOR_INTEL: diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/cpu/amd.c --- a/xen/arch/x86/cpu/amd.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/cpu/amd.c Sat May 15 08:44:37 2010 +0100 @@ -432,10 +432,9 @@ static void __devinit init_amd(struct cp } switch (c->x86) { - case 15: + case 0xf: /* Use K8 tuning for Fam10h and Fam11h */ - case 0x10: - case 0x11: + case 0x10 ... 0x17: set_bit(X86_FEATURE_K8, c->x86_capability); disable_c1e(NULL); if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value)) @@ -496,7 +495,7 @@ static void __devinit init_amd(struct cp #endif /* Pointless to use MWAIT on Family10 as it does not deep sleep. */ - if (c->x86 == 0x10 && !force_mwait) + if (c->x86 >= 0x10 && !force_mwait) clear_bit(X86_FEATURE_MWAIT, c->x86_capability); /* K6s reports MCEs but don't actually have all the MSRs */ diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/cpu/mcheck/mce.c --- a/xen/arch/x86/cpu/mcheck/mce.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/cpu/mcheck/mce.c Sat May 15 08:44:37 2010 +0100 @@ -503,7 +503,7 @@ static int amd_mcheck_init(struct cpuinf rc = amd_k8_mcheck_init(ci); break; - case 0x10: + case 0x10 ... 0x17: rc = amd_f10_mcheck_init(ci); break; diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/nmi.c --- a/xen/arch/x86/nmi.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/nmi.c Sat May 15 08:44:37 2010 +0100 @@ -323,7 +323,7 @@ void __pminit setup_apic_nmi_watchdog(vo case X86_VENDOR_AMD: switch (boot_cpu_data.x86) { case 6: - case 15 ... 17: + case 0xf ... 0x17: setup_k7_watchdog(); break; default: diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/oprofile/nmi_int.c --- a/xen/arch/x86/oprofile/nmi_int.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/oprofile/nmi_int.c Sat May 15 08:44:37 2010 +0100 @@ -425,6 +425,18 @@ static int __init nmi_init(void) model = &op_athlon_spec; cpu_type = "x86-64/family11"; break; + case 0x12: + model = &op_athlon_spec; + cpu_type = "x86-64/family12"; + break; + case 0x14: + model = &op_athlon_spec; + cpu_type = "x86-64/family14"; + break; + case 0x15: + model = &op_athlon_spec; + cpu_type = "x86-64/family15"; + break; } break; diff -r d11bdc25b36d -r 4c5acce5961c xen/arch/x86/traps.c --- a/xen/arch/x86/traps.c Thu May 13 10:40:19 2010 +0100 +++ b/xen/arch/x86/traps.c Sat May 15 08:44:37 2010 +0100 @@ -2164,7 +2164,7 @@ static int emulate_privileged_op(struct break; case MSR_AMD64_NB_CFG: if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 ) + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) goto fail; if ( !IS_PRIV(v->domain) ) break; @@ -2177,7 +2177,7 @@ static int emulate_privileged_op(struct break; case MSR_FAM10H_MMIO_CONF_BASE: if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD || - boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 ) + boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 ) goto fail; if ( !IS_PRIV(v->domain) ) break; @@ -3089,8 +3089,7 @@ void __devinit percpu_traps_init(void) switch ( boot_cpu_data.x86 ) { case 6: - case 15: - case 16: + case 0xf ... 0x17: this_cpu(ler_msr) = MSR_IA32_LASTINTFROMIP; break; } _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-changelog
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