[Xen-changelog] [xen-unstable] x86: emulate MSR_IA32_UCODE_REV Intel access protocol

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1286784105 -3600
# Node ID a1405385db77c7c81aac27bd88d6c4b2d90b1389
# Parent  a33886146b45da46a5161a7ebed4d2f607642aee
x86: emulate MSR_IA32_UCODE_REV Intel access protocol

Intel requires a write of zeros (hence such writes now get silently
ignored) followed by a cpuid(1) followed by the actual read.

Includes some code redundancy elimination possible after the actual
change.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
 xen/arch/x86/traps.c |   27 ++++++++++++++++++++-------
 1 files changed, 20 insertions(+), 7 deletions(-)

diff -r a33886146b45 -r a1405385db77 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Fri Oct 08 11:41:57 2010 +0100
+++ b/xen/arch/x86/traps.c      Mon Oct 11 09:01:45 2010 +0100
@@ -2276,6 +2276,14 @@ static int emulate_privileged_op(struct 
             if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, msr_content) != 0 )
                 goto fail;
             break;
+        case MSR_IA32_UCODE_REV:
+            if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+                goto fail;
+            if ( rdmsr_safe(regs->ecx, val) )
+                goto fail;
+            if ( msr_content )
+                goto invalid;
+            break;
         case MSR_IA32_MISC_ENABLE:
             if ( rdmsr_safe(regs->ecx, val) )
                 goto invalid;
@@ -2382,11 +2390,16 @@ static int emulate_privileged_op(struct 
                 regs->eax = regs->edx = 0;
                 break;
             }
-            if ( rdmsr_safe(regs->ecx, msr_content) != 0 )
-                goto fail;
-            regs->eax = (uint32_t)msr_content;
-            regs->edx = (uint32_t)(msr_content >> 32);
-            break;
+            goto rdmsr_normal;
+        case MSR_IA32_UCODE_REV:
+            BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
+            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            {
+                if ( wrmsr_safe(MSR_IA32_UCODE_REV, 0) )
+                    goto fail;
+                sync_core();
+            }
+            goto rdmsr_normal;
         case MSR_IA32_MISC_ENABLE:
             if ( rdmsr_safe(regs->ecx, msr_content) )
                 goto fail;
@@ -2394,8 +2407,6 @@ static int emulate_privileged_op(struct 
             regs->eax = (uint32_t)msr_content;
             regs->edx = (uint32_t)(msr_content >> 32);
             break;
-        case MSR_EFER:
-        case MSR_AMD_PATCHLEVEL:
         default:
             if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
             {
@@ -2411,6 +2422,8 @@ static int emulate_privileged_op(struct 
             if ( rc )
                 goto rdmsr_writeback;
 
+        case MSR_EFER:
+ rdmsr_normal:
             /* Everyone can read the MSR space. */
             /* gdprintk(XENLOG_WARNING,"Domain attempted RDMSR %p.\n",
                         _p(regs->ecx));*/

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