[Xen-changelog] [xen-4.0-testing] x86-64: workaround for BIOSes wrongly enabling LAHF_LM feature indicator

["Xen patchbot-4.0-testing" <patchbot-4.0-testing@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1287578076 -3600
# Node ID 4262d8dbd9582ee84834c5d0a6d5052efb94046c
# Parent  5221fcc3df6476455b81121455322794cf5f8867
x86-64: workaround for BIOSes wrongly enabling LAHF_LM feature indicator

This workaround is taken from Linux, and the main motivation (besides
such workarounds indeed belonging in the hypervisor rather than each
kernel) is to suppress the warnings in the Xen log each Linux guest
would cause due to the disallowed wrmsr.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
xen-unstable changeset:   22232:eb964c4b4f31
xen-unstable date:        Mon Oct 11 09:02:36 2010 +0100
---
 xen/arch/x86/cpu/amd.c |   59 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+)

diff -r 5221fcc3df64 -r 4262d8dbd958 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Mon Oct 18 11:27:23 2010 +0100
+++ b/xen/arch/x86/cpu/amd.c    Wed Oct 20 13:34:36 2010 +0100
@@ -50,6 +50,47 @@ static inline void wrmsr_amd(unsigned in
                : "c" (index), "a" (lo), 
                "d" (hi), "D" (0x9c5a203a)
        );
+}
+
+static inline int rdmsr_amd_safe(unsigned int msr, unsigned int *lo,
+                                unsigned int *hi)
+{
+       int err;
+
+       asm volatile("1: rdmsr\n2:\n"
+                    ".section .fixup,\"ax\"\n"
+                    "3: movl %6,%2\n"
+                    "   jmp 2b\n"
+                    ".previous\n"
+                    ".section __ex_table,\"a\"\n"
+                    __FIXUP_ALIGN "\n"
+                    __FIXUP_WORD " 1b,3b\n"
+                    ".previous\n"
+                    : "=a" (*lo), "=d" (*hi), "=r" (err)
+                    : "c" (msr), "D" (0x9c5a203a), "2" (0), "i" (-EFAULT));
+
+       return err;
+}
+
+static inline int wrmsr_amd_safe(unsigned int msr, unsigned int lo,
+                                unsigned int hi)
+{
+       int err;
+
+       asm volatile("1: wrmsr\n2:\n"
+                    ".section .fixup,\"ax\"\n"
+                    "3: movl %6,%0\n"
+                    "   jmp 2b\n"
+                    ".previous\n"
+                    ".section __ex_table,\"a\"\n"
+                    __FIXUP_ALIGN "\n"
+                    __FIXUP_WORD " 1b,3b\n"
+                    ".previous\n"
+                    : "=r" (err)
+                    : "c" (msr), "a" (lo), "d" (hi), "D" (0x9c5a203a),
+                      "0" (0), "i" (-EFAULT));
+
+       return err;
 }
 
 /*
@@ -338,6 +379,24 @@ static void __devinit init_amd(struct cp
           3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
        clear_bit(0*32+31, c->x86_capability);
        
+#ifdef CONFIG_X86_64
+       if (c->x86 == 0xf && c->x86_model < 0x14
+           && cpu_has(c, X86_FEATURE_LAHF_LM)) {
+               /*
+                * Some BIOSes incorrectly force this feature, but only K8
+                * revision D (model = 0x14) and later actually support it.
+                * (AMD Erratum #110, docId: 25759).
+                */
+               unsigned int lo, hi;
+
+               clear_bit(X86_FEATURE_LAHF_LM, c->x86_capability);
+               if (!rdmsr_amd_safe(0xc001100d, &lo, &hi)) {
+                       hi &= ~1;
+                       wrmsr_amd_safe(0xc001100d, lo, hi);
+               }
+       }
+#endif
+
        r = get_model_name(c);
 
        switch(c->x86)

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