[Xen-changelog] [xen-unstable] x86: blacklist new AMD CPUID bits for PV domains

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1296031540 0
# Node ID 4785c70c2b6d1d8ab4dab3aa7431ef32d0c56362
# Parent  b9017fdaad4dedfb8f953d2c6388d910ab2ab3c8
x86: blacklist new AMD CPUID bits for PV domains

there are some new CPUID bits (and leaves) which Dom0 and PV domains
should not see to avoid trouble, since we don't emulate the features.
The most prominent one is a topology leaf, which contains information
specific to the physical CPU, not the virtual one. To avoid confusion
(and possibly crashes) due to a confused Dom0 scheduler simply disable
these bits.

Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
Signed-off-by: Keir Fraser <keir@xxxxxxx>
---
 tools/libxc/xc_cpuid_x86.c |    5 +++++
 xen/arch/x86/traps.c       |    5 +++++
 2 files changed, 10 insertions(+)

diff -r b9017fdaad4d -r 4785c70c2b6d tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c        Wed Jan 26 08:35:24 2011 +0000
+++ b/tools/libxc/xc_cpuid_x86.c        Wed Jan 26 08:45:40 2011 +0000
@@ -427,12 +427,17 @@ static void xc_cpuid_pv_policy(
         clear_bit(X86_FEATURE_IBS, regs[2]);
         clear_bit(X86_FEATURE_SKINIT, regs[2]);
         clear_bit(X86_FEATURE_WDT, regs[2]);
+        clear_bit(X86_FEATURE_LWP, regs[2]);
+        clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
+        clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0xd: /* XSAVE */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         regs[0] = regs[1] = regs[2] = regs[3] = 0;
         break;
     }
diff -r b9017fdaad4d -r 4785c70c2b6d xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Wed Jan 26 08:35:24 2011 +0000
+++ b/xen/arch/x86/traps.c      Wed Jan 26 08:45:40 2011 +0000
@@ -802,11 +802,16 @@ static void pv_cpuid(struct cpu_user_reg
         __clear_bit(X86_FEATURE_IBS % 32, &c);
         __clear_bit(X86_FEATURE_SKINIT % 32, &c);
         __clear_bit(X86_FEATURE_WDT % 32, &c);
+        __clear_bit(X86_FEATURE_LWP % 32, &c);
+        __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
+        __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         a = b = c = d = 0;
         break;
     default:

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