[Xen-changelog] [xen-unstable] xen: Restore the BAR and PCI command after resume.

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
# Date 1310632225 -3600
# Node ID f1f677d3f2583132484866a78b92f4a326560bc7
# Parent  bdd9f31951ad309cf76f701a034dc87c78833a3a
xen: Restore the BAR and PCI command after resume.

Certain PCI serial cards just don't want to remember
what they are when they come out of resume. Save
the BAR and the PCI command values before we suspend and
write them back in when we resume.

Signed-off-by: Roger Cruz <roger.cruz@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Tom Goetz <tom.goetz@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
---


diff -r bdd9f31951ad -r f1f677d3f258 xen/drivers/char/ns16550.c
--- a/xen/drivers/char/ns16550.c        Thu Jul 14 09:28:23 2011 +0100
+++ b/xen/drivers/char/ns16550.c        Thu Jul 14 09:30:25 2011 +0100
@@ -49,6 +49,7 @@
     unsigned int ps_bdf[3]; /* pci serial port BDF */
     bool_t pb_bdf_enable;   /* if =1, pb-bdf effective, port behind bridge */
     bool_t ps_bdf_enable;   /* if =1, ps_bdf effective, port on pci card */
+    int bar0, cr;
 } ns16550_com[2] = { { 0 } };
 
 /* Register offsets */
@@ -333,13 +334,30 @@
 static void ns16550_suspend(struct serial_port *port)
 {
     struct ns16550 *uart = port->uart;
+
     stop_timer(&uart->timer);
+
+    if (uart->bar0) {
+       uart->bar0 = pci_conf_read32(uart->pb_bdf[0], uart->pb_bdf[1], 
uart->pb_bdf[2],
+                                    PCI_BASE_ADDRESS_0);
+       uart->cr = pci_conf_read32(uart->pb_bdf[0], uart->pb_bdf[1], 
uart->pb_bdf[2],
+                                    PCI_COMMAND);
+    }
 }
 
 static void ns16550_resume(struct serial_port *port)
 {
+    struct ns16550 *uart = port->uart;
+
     ns16550_setup_preirq(port->uart);
     ns16550_setup_postirq(port->uart);
+
+    if (uart->bar0) {
+       pci_conf_write32(uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2],
+                        PCI_BASE_ADDRESS_0, uart->bar0);
+       pci_conf_write32(uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2],
+                        PCI_COMMAND, uart->cr);
+    }
 }
 
 #ifdef CONFIG_X86
@@ -479,6 +497,10 @@
               if ((len & 0xffff) != 0xfff9)
                 continue;
 
+              uart->pb_bdf[0] = b;
+              uart->pb_bdf[1] = d;
+              uart->pb_bdf[2] = f;
+              uart->bar0 = bar0;
               uart->io_base = bar0 & 0xfffe;
               uart->irq = 0;
 

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