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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen-unstable] hvmloader: Remove hard tabs from source files.
# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1311169936 -3600
# Node ID 4f1109af9c63329fe5e737d8765f3f44f85bea95
# Parent 548b2826293ee97d7f1e0909b7d3326dd6d8465b
hvmloader: Remove hard tabs from source files.
Signed-off-by: Keir Fraser <keir@xxxxxxx>
---
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/hypercall.h
--- a/tools/firmware/hvmloader/hypercall.h Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/hypercall.h Wed Jul 20 14:52:16 2011 +0100
@@ -42,140 +42,140 @@
#define hypercall_pa "_start - " STR(HVMLOADER_PHYSICAL_ADDRESS) \
" + " STR(HYPERCALL_PHYSICAL_ADDRESS)
-#define _hypercall0(type, name)
\
-({ \
- long __res; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res) \
- : \
- : "memory" ); \
- (type)__res; \
+#define _hypercall0(type, name) \
+({ \
+ long __res; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res) \
+ : \
+ : "memory" ); \
+ (type)__res; \
})
-#define _hypercall1(type, name, a1) \
-({ \
- long __res, __ign1; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res), "=b" (__ign1) \
- : "1" ((long)(a1)) \
- : "memory" ); \
- (type)__res; \
+#define _hypercall1(type, name, a1) \
+({ \
+ long __res, __ign1; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res), "=b" (__ign1) \
+ : "1" ((long)(a1)) \
+ : "memory" ); \
+ (type)__res; \
})
-#define _hypercall2(type, name, a1, a2)
\
-({ \
- long __res, __ign1, __ign2; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res), "=b" (__ign1), "=c" (__ign2) \
- : "1" ((long)(a1)), "2" ((long)(a2)) \
- : "memory" ); \
- (type)__res; \
+#define _hypercall2(type, name, a1, a2) \
+({ \
+ long __res, __ign1, __ign2; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res), "=b" (__ign1), "=c" (__ign2) \
+ : "1" ((long)(a1)), "2" ((long)(a2)) \
+ : "memory" ); \
+ (type)__res; \
})
-#define _hypercall3(type, name, a1, a2, a3) \
-({ \
- long __res, __ign1, __ign2, __ign3; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
- "=d" (__ign3) \
- : "1" ((long)(a1)), "2" ((long)(a2)), \
- "3" ((long)(a3)) \
- : "memory" ); \
- (type)__res; \
+#define _hypercall3(type, name, a1, a2, a3) \
+({ \
+ long __res, __ign1, __ign2, __ign3; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
+ "=d" (__ign3) \
+ : "1" ((long)(a1)), "2" ((long)(a2)), \
+ "3" ((long)(a3)) \
+ : "memory" ); \
+ (type)__res; \
})
-#define _hypercall4(type, name, a1, a2, a3, a4)
\
-({ \
- long __res, __ign1, __ign2, __ign3, __ign4; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
- "=d" (__ign3), "=S" (__ign4) \
- : "1" ((long)(a1)), "2" ((long)(a2)), \
- "3" ((long)(a3)), "4" ((long)(a4)) \
- : "memory" ); \
- (type)__res; \
+#define _hypercall4(type, name, a1, a2, a3, a4) \
+({ \
+ long __res, __ign1, __ign2, __ign3, __ign4; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
+ "=d" (__ign3), "=S" (__ign4) \
+ : "1" ((long)(a1)), "2" ((long)(a2)), \
+ "3" ((long)(a3)), "4" ((long)(a4)) \
+ : "memory" ); \
+ (type)__res; \
})
-#define _hypercall5(type, name, a1, a2, a3, a4, a5) \
-({ \
- long __res, __ign1, __ign2, __ign3, __ign4, __ign5; \
- asm volatile ( \
- "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
- : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
- "=d" (__ign3), "=S" (__ign4), "=D" (__ign5) \
- : "1" ((long)(a1)), "2" ((long)(a2)), \
- "3" ((long)(a3)), "4" ((long)(a4)), \
- "5" ((long)(a5)) \
- : "memory" ); \
- (type)__res; \
+#define _hypercall5(type, name, a1, a2, a3, a4, a5) \
+({ \
+ long __res, __ign1, __ign2, __ign3, __ign4, __ign5; \
+ asm volatile ( \
+ "call "hypercall_pa" + " STR(__HYPERVISOR_##name * 32) \
+ : "=a" (__res), "=b" (__ign1), "=c" (__ign2), \
+ "=d" (__ign3), "=S" (__ign4), "=D" (__ign5) \
+ : "1" ((long)(a1)), "2" ((long)(a2)), \
+ "3" ((long)(a3)), "4" ((long)(a4)), \
+ "5" ((long)(a5)) \
+ : "memory" ); \
+ (type)__res; \
})
static inline int
hypercall_sched_op(
- int cmd, void *arg)
+ int cmd, void *arg)
{
- return _hypercall2(int, sched_op, cmd, arg);
+ return _hypercall2(int, sched_op, cmd, arg);
}
static inline int
hypercall_memory_op(
- unsigned int cmd, void *arg)
+ unsigned int cmd, void *arg)
{
- return _hypercall2(int, memory_op, cmd, arg);
+ return _hypercall2(int, memory_op, cmd, arg);
}
static inline int
hypercall_multicall(
- void *call_list, int nr_calls)
+ void *call_list, int nr_calls)
{
- return _hypercall2(int, multicall, call_list, nr_calls);
+ return _hypercall2(int, multicall, call_list, nr_calls);
}
static inline int
hypercall_event_channel_op(
- int cmd, void *arg)
+ int cmd, void *arg)
{
- return _hypercall2(int, event_channel_op, cmd, arg);
+ return _hypercall2(int, event_channel_op, cmd, arg);
}
static inline int
hypercall_xen_version(
- int cmd, void *arg)
+ int cmd, void *arg)
{
- return _hypercall2(int, xen_version, cmd, arg);
+ return _hypercall2(int, xen_version, cmd, arg);
}
static inline int
hypercall_console_io(
- int cmd, int count, char *str)
+ int cmd, int count, char *str)
{
- return _hypercall3(int, console_io, cmd, count, str);
+ return _hypercall3(int, console_io, cmd, count, str);
}
static inline int
hypercall_vm_assist(
- unsigned int cmd, unsigned int type)
+ unsigned int cmd, unsigned int type)
{
- return _hypercall2(int, vm_assist, cmd, type);
+ return _hypercall2(int, vm_assist, cmd, type);
}
static inline int
hypercall_vcpu_op(
- int cmd, int vcpuid, void *extra_args)
+ int cmd, int vcpuid, void *extra_args)
{
- return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args);
+ return _hypercall3(int, vcpu_op, cmd, vcpuid, extra_args);
}
static inline int
hypercall_hvm_op(
- int cmd, void *arg)
+ int cmd, void *arg)
{
- return _hypercall2(int, hvm_op, cmd, arg);
+ return _hypercall2(int, hvm_op, cmd, arg);
}
#endif /* __HVMLOADER_HYPERCALL_H__ */
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/pci_regs.h
--- a/tools/firmware/hvmloader/pci_regs.h Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/pci_regs.h Wed Jul 20 14:52:16 2011 +0100
@@ -1,69 +1,69 @@
/*
- * pci_regs.h
+ * pci_regs.h
*
- * PCI standard defines
- * Copyright 1994, Drew Eckhardt
- * Copyright 1997--1999 Martin Mares <mj@xxxxxx>
+ * PCI standard defines
+ * Copyright 1994, Drew Eckhardt
+ * Copyright 1997--1999 Martin Mares <mj@xxxxxx>
*
- * For more information, please consult the following manuals (look at
- * http://www.pcisig.com/ for how to get them):
+ * For more information, please consult the following manuals (look at
+ * http://www.pcisig.com/ for how to get them):
*
- * PCI BIOS Specification
- * PCI Local Bus Specification
- * PCI to PCI Bridge Specification
- * PCI System Design Guide
+ * PCI BIOS Specification
+ * PCI Local Bus Specification
+ * PCI to PCI Bridge Specification
+ * PCI System Design Guide
*/
#ifndef __HVMLOADER_PCI_REGS_H__
#define __HVMLOADER_PCI_REGS_H__
-#define PCI_VENDOR_ID 0x00 /* 16 bits */
-#define PCI_DEVICE_ID 0x02 /* 16 bits */
-#define PCI_COMMAND 0x04 /* 16 bits */
-#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space
*/
-#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
-#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
-#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
-#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and
invalidate */
-#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
-#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
-#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
-#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
-#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#define PCI_COMMAND 0x04 /* 16 bits */
+#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
+#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
+#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
+#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
+#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
+#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
+#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
+#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
+#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
+#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
-#define PCI_STATUS 0x06 /* 16 bits */
-#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
-#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
-#define PCI_STATUS_UDF 0x40 /* Support User Definable
Features [obsolete] */
-#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
-#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
-#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
-#define PCI_STATUS_DEVSEL_FAST 0x000
-#define PCI_STATUS_DEVSEL_MEDIUM 0x200
-#define PCI_STATUS_DEVSEL_SLOW 0x400
-#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
-#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
-#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
-#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
-#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+#define PCI_STATUS 0x06 /* 16 bits */
+#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
+#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
+#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
+#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
+#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
+#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
+#define PCI_STATUS_DEVSEL_FAST 0x000
+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define PCI_STATUS_DEVSEL_SLOW 0x400
+#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
-#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
-#define PCI_REVISION_ID 0x08 /* Revision ID */
-#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
-#define PCI_CLASS_DEVICE 0x0a /* Device class */
+#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID 0x08 /* Revision ID */
+#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE 0x0a /* Device class */
-#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
-#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
-#define PCI_HEADER_TYPE 0x0e /* 8 bits */
-#define PCI_HEADER_TYPE_NORMAL 0
-#define PCI_HEADER_TYPE_BRIDGE 1
-#define PCI_HEADER_TYPE_CARDBUS 2
+#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
+#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
+#define PCI_HEADER_TYPE 0x0e /* 8 bits */
+#define PCI_HEADER_TYPE_NORMAL 0
+#define PCI_HEADER_TYPE_BRIDGE 1
+#define PCI_HEADER_TYPE_CARDBUS 2
-#define PCI_BIST 0x0f /* 8 bits */
-#define PCI_BIST_CODE_MASK 0x0f /* Return result */
-#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or
less */
-#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
+#define PCI_BIST 0x0f /* 8 bits */
+#define PCI_BIST_CODE_MASK 0x0f /* Return result */
+#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
@@ -71,39 +71,39 @@
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
-#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
-#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
-#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
-#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
-#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
-#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
-#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O
*/
-#define PCI_BASE_ADDRESS_SPACE_IO 0x01
-#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
-#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
-#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
-#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
-#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
-#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
-#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
-#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
+#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
+#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
+#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
+#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
+#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
+#define PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
+#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
+#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
+#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
+#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
+#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
-#define PCI_CARDBUS_CIS 0x28
-#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
-#define PCI_SUBSYSTEM_ID 0x2e
-#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address,
10..1 reserved */
-#define PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
+#define PCI_CARDBUS_CIS 0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID 0x2e
+#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
+#define PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
-#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list
entry */
+#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
-#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
-#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
-#define PCI_MIN_GNT 0x3e /* 8 bits */
-#define PCI_MAX_LAT 0x3f /* 8 bits */
+#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
+#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
+#define PCI_MIN_GNT 0x3e /* 8 bits */
+#define PCI_MAX_LAT 0x3f /* 8 bits */
#endif /* __HVMLOADER_PCI_REGS_H__ */
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/seabios.c
--- a/tools/firmware/hvmloader/seabios.c Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/seabios.c Wed Jul 20 14:52:16 2011 +0100
@@ -126,7 +126,7 @@
//BUILD_BUG_ON(sizeof(seabios) > (0x00100000U - SEABIOS_PHYSICAL_ADDRESS));
struct bios_config seabios_config = {
- .name = "SeaBIOS",
+ .name = "SeaBIOS",
.image = seabios,
.image_size = sizeof(seabios),
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/smbios_types.h
--- a/tools/firmware/hvmloader/smbios_types.h Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/smbios_types.h Wed Jul 20 14:52:16 2011 +0100
@@ -32,157 +32,157 @@
between 0xf0000 and 0xfffff.
*/
struct smbios_entry_point {
- char anchor_string[4];
- uint8_t checksum;
- uint8_t length;
- uint8_t smbios_major_version;
- uint8_t smbios_minor_version;
- uint16_t max_structure_size;
- uint8_t entry_point_revision;
- uint8_t formatted_area[5];
- char intermediate_anchor_string[5];
- uint8_t intermediate_checksum;
- uint16_t structure_table_length;
- uint32_t structure_table_address;
- uint16_t number_of_structures;
- uint8_t smbios_bcd_revision;
+ char anchor_string[4];
+ uint8_t checksum;
+ uint8_t length;
+ uint8_t smbios_major_version;
+ uint8_t smbios_minor_version;
+ uint16_t max_structure_size;
+ uint8_t entry_point_revision;
+ uint8_t formatted_area[5];
+ char intermediate_anchor_string[5];
+ uint8_t intermediate_checksum;
+ uint16_t structure_table_length;
+ uint32_t structure_table_address;
+ uint16_t number_of_structures;
+ uint8_t smbios_bcd_revision;
} __attribute__ ((packed));
/* This goes at the beginning of every SMBIOS structure. */
struct smbios_structure_header {
- uint8_t type;
- uint8_t length;
- uint16_t handle;
+ uint8_t type;
+ uint8_t length;
+ uint16_t handle;
} __attribute__ ((packed));
/* SMBIOS type 0 - BIOS Information */
struct smbios_type_0 {
- struct smbios_structure_header header;
- uint8_t vendor_str;
- uint8_t version_str;
- uint16_t starting_address_segment;
- uint8_t release_date_str;
- uint8_t rom_size;
- uint8_t characteristics[8];
- uint8_t characteristics_extension_bytes[2];
- uint8_t major_release;
- uint8_t minor_release;
- uint8_t embedded_controller_major;
- uint8_t embedded_controller_minor;
+ struct smbios_structure_header header;
+ uint8_t vendor_str;
+ uint8_t version_str;
+ uint16_t starting_address_segment;
+ uint8_t release_date_str;
+ uint8_t rom_size;
+ uint8_t characteristics[8];
+ uint8_t characteristics_extension_bytes[2];
+ uint8_t major_release;
+ uint8_t minor_release;
+ uint8_t embedded_controller_major;
+ uint8_t embedded_controller_minor;
} __attribute__ ((packed));
/* SMBIOS type 1 - System Information */
struct smbios_type_1 {
- struct smbios_structure_header header;
- uint8_t manufacturer_str;
- uint8_t product_name_str;
- uint8_t version_str;
- uint8_t serial_number_str;
- uint8_t uuid[16];
- uint8_t wake_up_type;
- uint8_t sku_str;
- uint8_t family_str;
+ struct smbios_structure_header header;
+ uint8_t manufacturer_str;
+ uint8_t product_name_str;
+ uint8_t version_str;
+ uint8_t serial_number_str;
+ uint8_t uuid[16];
+ uint8_t wake_up_type;
+ uint8_t sku_str;
+ uint8_t family_str;
} __attribute__ ((packed));
/* SMBIOS type 3 - System Enclosure */
struct smbios_type_3 {
- struct smbios_structure_header header;
- uint8_t manufacturer_str;
- uint8_t type;
- uint8_t version_str;
- uint8_t serial_number_str;
- uint8_t asset_tag_str;
- uint8_t boot_up_state;
- uint8_t power_supply_state;
- uint8_t thermal_state;
- uint8_t security_status;
+ struct smbios_structure_header header;
+ uint8_t manufacturer_str;
+ uint8_t type;
+ uint8_t version_str;
+ uint8_t serial_number_str;
+ uint8_t asset_tag_str;
+ uint8_t boot_up_state;
+ uint8_t power_supply_state;
+ uint8_t thermal_state;
+ uint8_t security_status;
} __attribute__ ((packed));
/* SMBIOS type 4 - Processor Information */
struct smbios_type_4 {
- struct smbios_structure_header header;
- uint8_t socket_designation_str;
- uint8_t processor_type;
- uint8_t processor_family;
- uint8_t manufacturer_str;
- uint32_t cpuid[2];
- uint8_t version_str;
- uint8_t voltage;
- uint16_t external_clock;
- uint16_t max_speed;
- uint16_t current_speed;
- uint8_t status;
- uint8_t upgrade;
+ struct smbios_structure_header header;
+ uint8_t socket_designation_str;
+ uint8_t processor_type;
+ uint8_t processor_family;
+ uint8_t manufacturer_str;
+ uint32_t cpuid[2];
+ uint8_t version_str;
+ uint8_t voltage;
+ uint16_t external_clock;
+ uint16_t max_speed;
+ uint16_t current_speed;
+ uint8_t status;
+ uint8_t upgrade;
} __attribute__ ((packed));
/* SMBIOS type 11 - OEM Strings */
struct smbios_type_11 {
- struct smbios_structure_header header;
- uint8_t count;
+ struct smbios_structure_header header;
+ uint8_t count;
} __attribute__ ((packed));
/* SMBIOS type 16 - Physical Memory Array
* Associated with one type 17 (Memory Device).
*/
struct smbios_type_16 {
- struct smbios_structure_header header;
- uint8_t location;
- uint8_t use;
- uint8_t error_correction;
- uint32_t maximum_capacity;
- uint16_t memory_error_information_handle;
- uint16_t number_of_memory_devices;
+ struct smbios_structure_header header;
+ uint8_t location;
+ uint8_t use;
+ uint8_t error_correction;
+ uint32_t maximum_capacity;
+ uint16_t memory_error_information_handle;
+ uint16_t number_of_memory_devices;
} __attribute__ ((packed));
/* SMBIOS type 17 - Memory Device
* Associated with one type 19
*/
struct smbios_type_17 {
- struct smbios_structure_header header;
- uint16_t physical_memory_array_handle;
- uint16_t memory_error_information_handle;
- uint16_t total_width;
- uint16_t data_width;
- uint16_t size;
- uint8_t form_factor;
- uint8_t device_set;
- uint8_t device_locator_str;
- uint8_t bank_locator_str;
- uint8_t memory_type;
- uint16_t type_detail;
+ struct smbios_structure_header header;
+ uint16_t physical_memory_array_handle;
+ uint16_t memory_error_information_handle;
+ uint16_t total_width;
+ uint16_t data_width;
+ uint16_t size;
+ uint8_t form_factor;
+ uint8_t device_set;
+ uint8_t device_locator_str;
+ uint8_t bank_locator_str;
+ uint8_t memory_type;
+ uint16_t type_detail;
} __attribute__ ((packed));
/* SMBIOS type 19 - Memory Array Mapped Address */
struct smbios_type_19 {
- struct smbios_structure_header header;
- uint32_t starting_address;
- uint32_t ending_address;
- uint16_t memory_array_handle;
- uint8_t partition_width;
+ struct smbios_structure_header header;
+ uint32_t starting_address;
+ uint32_t ending_address;
+ uint16_t memory_array_handle;
+ uint8_t partition_width;
} __attribute__ ((packed));
/* SMBIOS type 20 - Memory Device Mapped Address */
struct smbios_type_20 {
- struct smbios_structure_header header;
- uint32_t starting_address;
- uint32_t ending_address;
- uint16_t memory_device_handle;
- uint16_t memory_array_mapped_address_handle;
- uint8_t partition_row_position;
- uint8_t interleave_position;
- uint8_t interleaved_data_depth;
+ struct smbios_structure_header header;
+ uint32_t starting_address;
+ uint32_t ending_address;
+ uint16_t memory_device_handle;
+ uint16_t memory_array_mapped_address_handle;
+ uint8_t partition_row_position;
+ uint8_t interleave_position;
+ uint8_t interleaved_data_depth;
} __attribute__ ((packed));
/* SMBIOS type 32 - System Boot Information */
struct smbios_type_32 {
- struct smbios_structure_header header;
- uint8_t reserved[6];
- uint8_t boot_status;
+ struct smbios_structure_header header;
+ uint8_t reserved[6];
+ uint8_t boot_status;
} __attribute__ ((packed));
/* SMBIOS type 127 -- End-of-table */
struct smbios_type_127 {
- struct smbios_structure_header header;
+ struct smbios_structure_header header;
} __attribute__ ((packed));
#endif /* SMBIOS_TYPES_H */
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/util.c
--- a/tools/firmware/hvmloader/util.c Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/util.c Wed Jul 20 14:52:16 2011 +0100
@@ -124,11 +124,11 @@
int strncmp(const char *s1, const char *s2, uint32_t n)
{
- uint32_t ctr;
- for (ctr = 0; ctr < n; ctr++)
- if (s1[ctr] != s2[ctr])
- return (int)(s1[ctr] - s2[ctr]);
- return 0;
+ uint32_t ctr;
+ for (ctr = 0; ctr < n; ctr++)
+ if (s1[ctr] != s2[ctr])
+ return (int)(s1[ctr] - s2[ctr]);
+ return 0;
}
void *memcpy(void *dest, const void *src, unsigned n)
diff -r 548b2826293e -r 4f1109af9c63 tools/firmware/hvmloader/util.h
--- a/tools/firmware/hvmloader/util.h Tue Jul 19 16:02:36 2011 +0100
+++ b/tools/firmware/hvmloader/util.h Wed Jul 20 14:52:16 2011 +0100
@@ -193,16 +193,16 @@
void cacheattr_init(void);
unsigned long create_mp_tables(void *table);
void hvm_write_smbios_tables(unsigned long ep,
- unsigned long smbios_start,
- unsigned long smbios_end);
+ unsigned long smbios_start,
+ unsigned long smbios_end);
unsigned long create_pir_tables(void);
void smp_initialise(void);
#include "e820.h"
int build_e820_table(struct e820entry *e820,
- unsigned int lowmem_reserved_base,
- unsigned int bios_image_base);
+ unsigned int lowmem_reserved_base,
+ unsigned int bios_image_base);
void dump_e820_table(struct e820entry *e820, unsigned int nr);
#ifndef NDEBUG
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