[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen-unstable] x86/amd: Add support for read-only APERF/MPERF
# HG changeset patch # User Mark Langsdorf <mark.langsdorf@xxxxxxx> # Date 1313226818 -3600 # Node ID 67b883402736ef1746cd6654da4c898f70f40723 # Parent 8f647d409196f1d018f6284af03d1625cf8f93af x86/amd: Add support for read-only APERF/MPERF AMD is adding support for a read-only mode of the APERF and MPERF MSRs. When this mode is enabled, writes to these registers are ignored and do no reset the registers. This allows multiple well-behaved programs to share the use of the registers even if a poorly behaved program attempts to reset them. Support for this feature is indicated by a CPUID bit. AMD has been recommending that well-behaved software avoid resetting the APERF and MPERF MSRs. Enabling this feature should not change the behavior of well- behaved software. This change has been tested with the turbostat and cpufreq-aperf applications. Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx> --- diff -r 8f647d409196 -r 67b883402736 xen/arch/x86/cpu/amd.c --- a/xen/arch/x86/cpu/amd.c Sat Aug 13 10:12:49 2011 +0100 +++ b/xen/arch/x86/cpu/amd.c Sat Aug 13 10:13:38 2011 +0100 @@ -499,6 +499,12 @@ if (c->x86 > 0xf && !cpu_has_amd_erratum(c, AMD_ERRATUM_400)) set_bit(X86_FEATURE_ARAT, c->x86_capability); + if (cpuid_edx(0x80000007) & (1 << 10)) { + rdmsr(MSR_K7_HWCR, l, h); + l |= (1 << 27); /* Enable read-only APERF/MPERF bit */ + wrmsr(MSR_K7_HWCR, l, h); + } + /* Prevent TSC drift in non single-processor, single-core platforms. */ if ((smp_processor_id() == 1) && c1_ramping_may_cause_clock_drift(c)) disable_c1_ramping(); _______________________________________________ Xen-changelog mailing list Xen-changelog@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-changelog
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