[Xen-changelog] [xen-4.0-testing] x86/amd: Eliminate cache flushing when entering C3 on select AMD processors

[Xen patchbot-4.0-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Mark Langsdorf <mark.langsdorf@xxxxxxx>
# Date 1321114519 0
# Node ID cdff7052bad8e0ee5fce18c9db54386b517c7d96
# Parent  a5cc3b953ed99f61a2cfbef72a9f8befdfa49a24
x86/amd: Eliminate cache flushing when entering C3 on select AMD processors

AMD Fam15h processors have a shared cache. It does not need=
to be be flushed when entering C3 and doing so causes reduces
performance. Modify acpi_processor_power_init_bm_check to
prevent these processors from flushing when entering C3.

Signed-off-by: Mark Langsdorf <mark.langsdorf@xxxxxxx>
xen-unstable changeset:   23511:450f1d198e1e
xen-unstable date:        Tue Jun 14 12:46:29 2011 +0100
Committed-by: Keir Fraser <keir@xxxxxxx>
---


diff -r a5cc3b953ed9 -r cdff7052bad8 xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c      Tue Oct 25 16:44:40 2011 +0100
+++ b/xen/arch/x86/acpi/cpu_idle.c      Sat Nov 12 16:15:19 2011 +0000
@@ -549,7 +549,8 @@
     flags->bm_check = 0;
     if ( num_online_cpus() == 1 )
         flags->bm_check = 1;
-    else if ( c->x86_vendor == X86_VENDOR_INTEL )
+    else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
+              ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
     {
         /*
          * Today all MP CPUs that support C3 share cache.

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