[Xen-changelog] [xen-4.1-testing] x86: Remove timeouts from INIT-SIPI-SIPI sequence when using x2apic.

[Xen patchbot-4.1-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Tim Deegan <Tim.Deegan@xxxxxxxxxx>
# Date 1326799837 0
# Node ID 2fb706161c099593eba7050c5262f7da3dd8b6f3
# Parent  e29b7691fefc2e5840d80d49f78b64b6d7019f9b
x86: Remove timeouts from INIT-SIPI-SIPI sequence when using x2apic.

Some of the timeouts are pointless since they're waiting for the ICR
to ack the IPI delivery and that doesn't happen on x2apic.
The others should be benign (and are suggested in the SDM) but
removing them makes AP bringup much more reliable on some test boxes.

Signed-off-by: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
xen-unstable changeset:   23724:b3434f24b082
xen-unstable date:        Tue Jul 19 14:13:01 2011 +0100

X86: Add a delay between INIT & SIPIs for tboot AP bring-up in X2APIC case

Without this delay, Xen could not bring APs up while working with
TXT/tboot, because tboot needs some time in APs to handle INIT before
becoming ready for receiving SIPIs (this delay was removed as part of
c/s 23724 by Tim Deegan).

Signed-off-by: Gang Wei <gang.wei@xxxxxxxxx>
Acked-by: Keir Fraser <keir@xxxxxxx>
Acked-by: Tim Deegan <tim@xxxxxxx>
Committed-by: Tim Deegan <tim@xxxxxxx>
xen-unstable changeset:   24447:a7b2610b8e5c
xen-unstable date:        Thu Dec 29 10:07:54 2011 +0000
---


diff -r e29b7691fefc -r 2fb706161c09 xen/arch/x86/smpboot.c
--- a/xen/arch/x86/smpboot.c    Sun Jan 15 22:08:13 2012 +0000
+++ b/xen/arch/x86/smpboot.c    Tue Jan 17 11:30:37 2012 +0000
@@ -42,6 +42,7 @@
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/time.h>
+#include <asm/tboot.h>
 #include <mach_apic.h>
 #include <mach_wakecpu.h>
 #include <smpboot_hooks.h>
@@ -445,29 +446,42 @@
     apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
                    phys_apicid);
 
-    Dprintk("Waiting for send to finish...\n");
-    timeout = 0;
-    do {
-        Dprintk("+");
-        udelay(100);
-        if ( !x2apic_enabled )
+    if ( !x2apic_enabled )
+    {
+        Dprintk("Waiting for send to finish...\n");
+        timeout = 0;
+        do {
+            Dprintk("+");
+            udelay(100);
             send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-    } while ( send_status && (timeout++ < 1000) );
+        } while ( send_status && (timeout++ < 1000) );
 
-    mdelay(10);
+        mdelay(10);
 
-    Dprintk("Deasserting INIT.\n");
+        Dprintk("Deasserting INIT.\n");
 
-    apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
+        apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 
-    Dprintk("Waiting for send to finish...\n");
-    timeout = 0;
-    do {
-        Dprintk("+");
-        udelay(100);
-        if ( !x2apic_enabled )
+        Dprintk("Waiting for send to finish...\n");
+        timeout = 0;
+        do {
+            Dprintk("+");
+            udelay(100);
             send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-    } while ( send_status && (timeout++ < 1000) );
+        } while ( send_status && (timeout++ < 1000) );
+    }
+    else if ( tboot_in_measured_env() )
+    {
+        /*
+         * With tboot AP is actually spinning in a mini-guest before 
+         * receiving INIT. Upon receiving INIT ipi, AP need time to VMExit, 
+         * update VMCS to tracking SIPIs and VMResume.
+         *
+         * While AP is in root mode handling the INIT the CPU will drop
+         * any SIPIs
+         */
+        udelay(10);
+    }
 
     /*
      * Should we send STARTUP IPIs ?
@@ -496,22 +510,24 @@
          */
         apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
 
-        /* Give the other CPU some time to accept the IPI. */
-        udelay(300);
+        if ( !x2apic_enabled )
+        {
+            /* Give the other CPU some time to accept the IPI. */
+            udelay(300);
 
-        Dprintk("Startup point 1.\n");
+            Dprintk("Startup point 1.\n");
 
-        Dprintk("Waiting for send to finish...\n");
-        timeout = 0;
-        do {
-            Dprintk("+");
-            udelay(100);
-            if ( !x2apic_enabled )
-            send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
-        } while ( send_status && (timeout++ < 1000) );
+            Dprintk("Waiting for send to finish...\n");
+            timeout = 0;
+            do {
+                Dprintk("+");
+                udelay(100);
+                send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
+            } while ( send_status && (timeout++ < 1000) );
 
-        /* Give the other CPU some time to accept the IPI. */
-        udelay(200);
+            /* Give the other CPU some time to accept the IPI. */
+            udelay(200);
+        }
 
         /* Due to the Pentium erratum 3AP. */
         if ( maxlvt > 3 )

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