[Xen-changelog] [xen-4.0-testing] x86/vIRQ: IRR and TMR race condition bug fix

[Xen patchbot-4.0-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Yongan Liu <Liuyongan@xxxxxxxxxx>
# Date 1326800083 0
# Node ID 3f7117070ba1ed15e2a660dcc79e1a2bfe8e82fb
# Parent  d5b26918cd94c1d4dbc931d9761ffd9e652ed3c0
x86/vIRQ: IRR and TMR race condition bug fix

In vlapic_set_irq, we set the IRR register before the TMR. And the IRR
might be serviced before setting TMR, and even worse EOI might occur
before TMR setting, in which case the vioapic_update_EOI won't be
called, and further prevent all the subsequent interrupt injecting.
Reorder setting the TMR and IRR will solve the problem.

Besides, KVM has fixed a similar bug in:
http://markmail.org/search/?q=APIC_TMR#query:APIC_TMR+page:1+mid:rphs4f7lkxjlldne+state:results

Signed-off-by: Yongan Liu<Liuyongan@xxxxxxxxxx>
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
xen-unstable changeset:   24453:02b92d035f64
xen-unstable date:        Thu Jan 05 09:29:59 2012 +0100
---


diff -r d5b26918cd94 -r 3f7117070ba1 xen/arch/x86/hvm/vlapic.c
--- a/xen/arch/x86/hvm/vlapic.c Sun Jan 15 22:08:54 2012 +0000
+++ b/xen/arch/x86/hvm/vlapic.c Tue Jan 17 11:34:43 2012 +0000
@@ -131,14 +131,11 @@
 
 int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
 {
-    int ret;
-
-    ret = !vlapic_test_and_set_irr(vec, vlapic);
     if ( trig )
         vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
 
     /* We may need to wake up target vcpu, besides set pending bit here */
-    return ret;
+    return !vlapic_test_and_set_irr(vec, vlapic);
 }
 
 static int vlapic_find_highest_isr(struct vlapic *vlapic)

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