[Xen-changelog] [xen-unstable] arm: Add a comment explaining the GICD writes in the GICC init function

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Tim Deegan <tim@xxxxxxx>
# Date 1331651453 0
# Node ID 0cc21e35cbdd66a2b16dccb7f51612fa20b0c79f
# Parent  cc1225c9690c89fae4622dcaf0fc01ce89546a32
arm: Add a comment explaining the GICD writes in the GICC init function

Signed-off-by: Tim Deegan <tim@xxxxxxx>
Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---


diff -r cc1225c9690c -r 0cc21e35cbdd xen/arch/arm/gic.c
--- a/xen/arch/arm/gic.c        Tue Mar 13 15:10:52 2012 +0000
+++ b/xen/arch/arm/gic.c        Tue Mar 13 15:10:53 2012 +0000
@@ -224,7 +224,9 @@
 {
     int i;
 
-    /* Disable all PPI and enable all SGI */
+    /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so 
+     * even though they are controlled with GICD registers, they must 
+     * be set up here with the other per-cpu state. */
     GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */
     GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */
     /* Set PPI and SGI priorities */

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