[Xen-changelog] [xen-unstable] x86/PCI: pass correct register value to XSM

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Daniel De Graaf <dgdegra@xxxxxxxxxxxxx>
# Date 1340365494 -7200
# Node ID 9c5e36af6ef34c876e62ddd4e3756de394d9df4f
# Parent  61844569a4328ec122bfc0b257f3e930a560ed47
x86/PCI: pass correct register value to XSM

When attempting to use AMD's extension to access the extended PCI config
space, only the low byte of the register number was being passed to XSM.
Include the correct value of the register if this feature is enabled;
otherwise, bits 24-30 of port cf8 are reserved, so disallow the invalid
access.

Signed-off-by: Daniel De Graaf <dgdegra@xxxxxxxxxxxxx>

Don't fail the permission check except when the MSR can't be read.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Keir Fraser <keir@xxxxxxx>
Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
---


diff -r 61844569a432 -r 9c5e36af6ef3 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Fri Jun 22 13:43:00 2012 +0200
+++ b/xen/arch/x86/traps.c      Fri Jun 22 13:44:54 2012 +0200
@@ -1701,6 +1701,18 @@ static int pci_cfg_ok(struct domain *d, 
             return 0;
     }
     start = d->arch.pci_cf8 & 0xFF;
+    /* AMD extended configuration space access? */
+    if ( (d->arch.pci_cf8 & 0x0F000000) &&
+         boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
+         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 <= 0x17 )
+    {
+        uint64_t msr_val;
+
+        if ( rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) )
+            return 0;
+        if ( msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT) )
+            start |= (d->arch.pci_cf8 >> 16) & 0xF00;
+    }
     end = start + size - 1;
     if (xsm_pci_config_permission(d, machine_bdf, start, end, write))
         return 0;

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