[Xen-changelog] [xen-unstable] arm: enable data-cache at the same time as enabling the MMU, not before

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Ian Campbell <ian.campbell@xxxxxxxxxx>
# Date 1341309146 -3600
# Node ID a9d004e63315936a7e3dec2afc6f48361d24573e
# Parent  d3dd28a6cdd066959869d7f77fb4bc7284c101ab
arm: enable data-cache at the same time as enabling the MMU, not before

With enough warnings enabled the model seemed to be complaining that pages
cached before paging was enabled had been mapped with to inconsistent sets of
attributes. I'm not convinced that isn't a model issue, nor am I convinced
this has really fixed anything, but it seems sensible enough.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Tim Deegan <tim@xxxxxxx>
Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---


diff -r d3dd28a6cdd0 -r a9d004e63315 xen/arch/arm/head.S
--- a/xen/arch/arm/head.S       Tue Jul 03 10:52:25 2012 +0100
+++ b/xen/arch/arm/head.S       Tue Jul 03 10:52:26 2012 +0100
@@ -148,10 +148,11 @@ hyp:
         * Exceptions in LE ARM,
         * Low-latency IRQs disabled,
         * Write-implies-XN disabled (for now),
-        * I-cache and d-cache enabled,
+        * D-cache disabled (for now),
+        * I-cache enabled,
         * Alignment checking enabled,
         * MMU translation disabled (for now). */
-       ldr   r0, =(HSCTLR_BASE|SCTLR_A|SCTLR_C)
+       ldr   r0, =(HSCTLR_BASE|SCTLR_A)
        mcr   CP32(r0, HSCTLR)
 
        /* Write Xen's PT's paddr into the HTTBR */
@@ -210,7 +211,7 @@ pt_ready:
 
        ldr   r1, =paging            /* Explicit vaddr, not RIP-relative */
        mrc   CP32(r0, HSCTLR)
-       orr   r0, r0, #0x1           /* Add in the MMU enable bit */
+       orr   r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */
        dsb                          /* Flush PTE writes and finish reads */
        mcr   CP32(r0, HSCTLR)       /* now paging is enabled */
        isb                          /* Now, flush the icache */

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