[Xen-changelog] [xen-4.1-testing] X86: Disable PCID/INVPCID for dom0

[Xen patchbot-4.1-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Liu, Jinsong <jinsong.liu@xxxxxxxxx>
# Date 1346761925 -7200
# Node ID 2527617fd58c97133d4fa2b27189cc7566a77bd3
# Parent  cde6c55bbc0777205679216aafb36d3cd02008be
X86: Disable PCID/INVPCID for dom0

PCID (Process-context identifier) is a facility by which a logical
processor may cache information for multiple linear-address spaces.
INVPCID is an new instruction to invalidate TLB. Refer latest Intel SDM
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

We disable PCID/INVPCID for dom0 and pv. Exposing them into dom0 and pv
may result in performance regression, and it would trigger GP or UD
depending on whether platform suppport INVPCID or not.

This patch disables PCID/INVPCID for dom0.

Signed-off-by: Liu, Jinsong <jinsong.liu@xxxxxxxxx>
xen-unstable changeset: 24278:d9cb04ed5539
xen-unstable date: Thu Dec  1 11:22:43 UTC 2011
---


diff -r cde6c55bbc07 -r 2527617fd58c xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Tue Sep 04 14:27:58 2012 +0200
+++ b/xen/arch/x86/traps.c      Tue Sep 04 14:32:05 2012 +0200
@@ -834,6 +834,7 @@ static void pv_cpuid(struct cpu_user_reg
             __clear_bit(X86_FEATURE_CX16 % 32, &c);
         __clear_bit(X86_FEATURE_XTPR % 32, &c);
         __clear_bit(X86_FEATURE_PDCM % 32, &c);
+        __clear_bit(X86_FEATURE_PCID % 32, &c);
         __clear_bit(X86_FEATURE_DCA % 32, &c);
         if ( !xsave_enabled(current) )
         {
diff -r cde6c55bbc07 -r 2527617fd58c xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h  Tue Sep 04 14:27:58 2012 +0200
+++ b/xen/include/asm-x86/cpufeature.h  Tue Sep 04 14:32:05 2012 +0200
@@ -96,6 +96,7 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR       (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_PDCM       (4*32+15) /* Perf/Debug Capability MSR */
+#define X86_FEATURE_PCID       (4*32+17) /* Process Context ID */
 #define X86_FEATURE_DCA                (4*32+18) /* Direct Cache Access */
 #define X86_FEATURE_SSE4_1     (4*32+19) /* Streaming SIMD Extensions 4.1 */
 #define X86_FEATURE_SSE4_2     (4*32+20) /* Streaming SIMD Extensions 4.2 */
@@ -146,6 +147,7 @@
 #define X86_FEATURE_FSGSBASE   (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution 
Protection */
 #define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
+#define X86_FEATURE_INVPCID    (7*32+10) /* Invalidate Process Context ID */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)

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