[Xen-changelog] [xen-unstable] arm: disable distributor delivery on boot CPU only

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Ian Campbell <ian.campbell@xxxxxxxxxx>
# Date 1349791536 -3600
# Node ID c5cb51bde9f05ae81f40d81647dc449981214979
# Parent  e222ecc2f61fca6a2975ceef851b0330db38227f
arm: disable distributor delivery on boot CPU only

The secondary processors do not call enter_hyp_mode until the boot CPU
has brought most of the system up, including enabling delivery via the
distributor. This means that bringing up secondary CPUs unexpectedly
disables the GICD again, meaning we get no further interrupts on any
CPU.

For completeness also disable the GICC (CPU interface) on all CPUs
too.

Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Tim Deegan <tim@xxxxxxx>
Committed-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---


diff -r e222ecc2f61f -r c5cb51bde9f0 xen/arch/arm/mode_switch.S
--- a/xen/arch/arm/mode_switch.S        Tue Oct 09 15:05:35 2012 +0100
+++ b/xen/arch/arm/mode_switch.S        Tue Oct 09 15:05:36 2012 +0100
@@ -23,6 +23,8 @@
 
 /* Get up a CPU into Hyp mode.  Clobbers r0-r3.
  *
+ * Expects r12 == CPU number
+ *
  * This code is specific to the VE model, and not intended to be used
  * on production systems.  As such it's a bit hackier than the main
  * boot code in head.S.  In future it will be replaced by better
@@ -46,19 +48,28 @@ enter_hyp_mode:
        mcr   CP32(r0, CNTFRQ)
        ldr   r0, =0x40c00           /* SMP, c11, c10 in non-secure mode */
        mcr   CP32(r0, NSACR)
-       /* Continuing ugliness: Set up the GIC so NS state owns interrupts */
        mov   r0, #GIC_BASE_ADDRESS
        add   r0, r0, #GIC_DR_OFFSET
+       /* Disable the GIC distributor, on the boot CPU only */
        mov   r1, #0
-       str   r1, [r0]               /* Disable delivery in the distributor */
+       teq   r12, #0                /* Is this the boot CPU? */
+       streq r1, [r0]
+       /* Continuing ugliness: Set up the GIC so NS state owns interrupts,
+        * The first 32 interrupts (SGIs & PPIs) must be configured on all
+        * CPUs while the remainder are SPIs and only need to be done one, on
+        * the boot CPU. */
        add   r0, r0, #0x80          /* GICD_IGROUP0 */
        mov   r2, #0xffffffff        /* All interrupts to group 1 */
-       str   r2, [r0]
-       str   r2, [r0, #4]
-       str   r2, [r0, #8]
-       /* Must drop priority mask below 0x80 before entering NS state */
+       teq   r12, #0                /* Boot CPU? */
+       str   r2, [r0]               /* Interrupts  0-31 (SGI & PPI) */
+       streq r2, [r0, #4]           /* Interrupts 32-63 (SPI) */
+       streq r2, [r0, #8]           /* Interrupts 64-95 (SPI) */
+       /* Disable the GIC CPU interface on all processors */
        mov   r0, #GIC_BASE_ADDRESS
        add   r0, r0, #GIC_CR_OFFSET
+       mov   r1, #0
+       str   r1, [r0]
+       /* Must drop priority mask below 0x80 before entering NS state */
        ldr   r1, =0xff
        str   r1, [r0, #0x4]         /* -> GICC_PMR */
        /* Reset a few config registers */

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog