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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen-unstable] x86/MCE: remove K7 support
# HG changeset patch
# User Christoph Egger <Christoph.Egger@xxxxxxx>
# Date 1351519598 -3600
# Node ID c3dafc201ad38e91e2914bac0f3548848462854c
# Parent f9ded6e9e554b66ff6d8a0181f70e1dca2517e90
x86/MCE: remove K7 support
Remove K7 support from MCE.
Signed-off-by: Christoph Egger <Christoph.Egger@xxxxxxx>
Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
---
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/Makefile
--- a/xen/arch/x86/cpu/mcheck/Makefile Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/Makefile Mon Oct 29 15:06:38 2012 +0100
@@ -1,5 +1,4 @@
obj-y += amd_nonfatal.o
-obj-y += k7.o
obj-y += amd_k8.o
obj-y += amd_f10.o
obj-y += mce_amd.o
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/k7.c
--- a/xen/arch/x86/cpu/mcheck/k7.c Mon Oct 29 15:04:35 2012 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/*
- * Athlon/Hammer specific Machine Check Exception Reporting
- * (C) Copyright 2002 Dave Jones <davej@xxxxxxxxxxxxxxxxx>
- */
-
-#include <xen/init.h>
-#include <xen/types.h>
-#include <xen/kernel.h>
-#include <xen/config.h>
-#include <xen/smp.h>
-
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/msr.h>
-
-#include "mce.h"
-#include "x86_mca.h"
-
-/* Machine Check Handler For AMD Athlon/Duron */
-static void k7_machine_check(struct cpu_user_regs * regs, long error_code)
-{
- int recover = 1;
- uint64_t msr_content, mcgst;
- int i;
-
- rdmsrl(MSR_IA32_MCG_STATUS, mcgst);
- if (mcgst & MCG_STATUS_RIPV) /* Recoverable ? */
- recover = 0;
-
- printk(KERN_EMERG "CPU %d: Machine Check Exception: 0x%016"PRIx64"\n",
- smp_processor_id(), mcgst);
-
- for (i = 1; i < nr_mce_banks; i++) {
- uint64_t value;
-
- rdmsrl(MSR_IA32_MCx_STATUS(i), msr_content);
- if (msr_content & MCi_STATUS_VAL) {
- if (msr_content & MCi_STATUS_UC)
- recover |= 1;
- if (msr_content & MCi_STATUS_PCC)
- recover |= 2;
- printk(KERN_EMERG "Bank %d: 0x%16"PRIx64,
- i, msr_content);
- msr_content &= ~MCi_STATUS_VAL;
- if (msr_content & MCi_STATUS_MISCV) {
- rdmsrl(MSR_IA32_MCx_MISC(i), value);
- printk("[0x%016"PRIx64"]", value);
- }
- if (msr_content & MCi_STATUS_ADDRV) {
- rdmsrl(MSR_IA32_MCx_ADDR(i), value);
- printk(" at 0x%016"PRIx64, value);
- }
- printk("\n");
- /* Clear it */
- wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
- /* Serialize */
- wmb();
- add_taint(TAINT_MACHINE_CHECK);
- }
- }
-
- if (recover & 2)
- mc_panic("CPU context corrupt");
- if (recover & 1)
- mc_panic("Unable to continue");
- printk(KERN_EMERG "Attempting to continue.\n");
- mcgst &= ~MCG_STATUS_MCIP;
- wrmsrl(MSR_IA32_MCG_STATUS, mcgst);
-}
-
-
-/* AMD K7 machine check */
-enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c)
-{
- int i;
-
- x86_mce_vector_register(k7_machine_check);
-
- /* Clear status for MC index 0 separately, we don't touch CTL,
- * as some Athlons cause spurious MCEs when its enabled. */
- wrmsrl(MSR_IA32_MC0_STATUS, 0x0ULL);
- for (i = 1; i < nr_mce_banks; i++) {
- wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL);
- wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL);
- }
-
- return mcheck_amd_k7;
-}
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.c Mon Oct 29 15:06:38 2012 +0100
@@ -567,15 +567,12 @@ int mce_available(struct cpuinfo_x86 *c)
}
/*
- * Check if bank 0 is usable for MCE. It isn't for AMD K7,
- * and Intel P6 family before model 0x1a.
+ * Check if bank 0 is usable for MCE. It isn't for Intel P6 family
+ * before model 0x1a.
*/
unsigned int mce_firstbank(struct cpuinfo_x86 *c)
{
if (c->x86 == 6) {
- if (c->x86_vendor == X86_VENDOR_AMD)
- return 1;
-
if (c->x86_vendor == X86_VENDOR_INTEL && c->x86_model < 0x1a)
return 1;
}
@@ -591,7 +588,6 @@ int show_mca_info(int inited, struct cpu
char prefix[20];
static const char *const type_str[] = {
[mcheck_amd_famXX] = "AMD",
- [mcheck_amd_k7] = "AMD K7",
[mcheck_amd_k8] = "AMD K8",
[mcheck_intel] = "Intel"
};
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce.h Mon Oct 29 15:06:38 2012 +0100
@@ -33,7 +33,6 @@ enum mcheck_type {
mcheck_unset = -1,
mcheck_none,
mcheck_amd_famXX,
- mcheck_amd_k7,
mcheck_amd_k8,
mcheck_intel
};
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce_amd.c
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c Mon Oct 29 15:06:38 2012 +0100
@@ -106,10 +106,6 @@ amd_mcheck_init(struct cpuinfo_x86 *ci)
switch ( ci->x86 )
{
- case 6:
- rc = amd_k7_mcheck_init(ci);
- break;
-
default:
/* Assume that machine check support is available.
* The minimum provided support is at least the K8. */
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce_amd.h
--- a/xen/arch/x86/cpu/mcheck/mce_amd.h Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.h Mon Oct 29 15:06:38 2012 +0100
@@ -1,7 +1,6 @@
#ifndef _MCHECK_AMD_H
#define _MCHECK_AMD_H
-enum mcheck_type amd_k7_mcheck_init(struct cpuinfo_x86 *c);
enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c);
enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c);
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce_amd_quirks.c
--- a/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c Mon Oct 29 15:06:38 2012 +0100
@@ -25,8 +25,6 @@
#define ANY -1
static const struct mce_quirkdata mce_amd_quirks[] = {
- { 0x6 /* cpu family */, ANY /* all models */, ANY /* all steppings */,
- MCEQUIRK_K7_BANK0 },
{ 0xf /* cpu family */, ANY /* all models */, ANY /* all steppings */,
MCEQUIRK_K8_GART },
{ 0x10 /* cpu family */, ANY /* all models */, ANY /* all steppings */,
@@ -59,9 +57,6 @@ int mcequirk_amd_apply(enum mcequirk_amd
u64 val;
switch (flags) {
- case MCEQUIRK_K7_BANK0:
- return 1; /* first bank */
-
case MCEQUIRK_K8_GART:
/*
* Enable error reporting for all errors except for GART
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/mce_quirks.h
--- a/xen/arch/x86/cpu/mcheck/mce_quirks.h Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/mce_quirks.h Mon Oct 29 15:06:38 2012 +0100
@@ -33,8 +33,7 @@ struct mce_quirkdata {
*/
enum mcequirk_amd_flags {
- MCEQUIRK_K7_BANK0 = 1,
- MCEQUIRK_K8_GART,
+ MCEQUIRK_K8_GART = 2,
MCEQUIRK_F10_GART
};
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/non-fatal.c
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c Mon Oct 29 15:06:38 2012 +0100
@@ -102,12 +102,6 @@ static int __init init_nonfatal_mce_chec
*/
switch (c->x86_vendor) {
case X86_VENDOR_AMD:
- if (c->x86 == 6) { /* K7 */
- init_timer(&mce_timer, mce_work_fn, NULL, 0);
- set_timer(&mce_timer, NOW() + MCE_PERIOD);
- break;
- }
-
/* Assume we are on K8 or newer AMD CPU here */
amd_nonfatal_mcheck_init(c);
break;
diff -r f9ded6e9e554 -r c3dafc201ad3 xen/arch/x86/cpu/mcheck/x86_mca.h
--- a/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Oct 29 15:04:35 2012 +0100
+++ b/xen/arch/x86/cpu/mcheck/x86_mca.h Mon Oct 29 15:06:38 2012 +0100
@@ -1,6 +1,6 @@
/*
- * MCA implementation for AMD K7/K8 CPUs
- * Copyright (c) 2007 Advanced Micro Devices, Inc.
+ * MCA implementation for AMD CPUs
+ * Copyright (c) 2007-2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
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