[Xen-changelog] [xen-4.1-testing] x86/HPET: fix FSB interrupt masking

[Xen patchbot-4.1-testing <patchbot@xxxxxxx>]

# HG changeset patch
# User Jan Beulich <jbeulich@xxxxxxxx>
# Date 1357636739 -3600
# Node ID 2e0a6f43218220f2b293bed979a6aa1e79a53b8d
# Parent  c2cb6182a58ce946ebef2658f4eda5d01b7906d2
x86/HPET: fix FSB interrupt masking

HPET_TN_FSB is not really suitable for masking interrupts - it merely
switches between the two delivery methods. The right way of masking is
through the HPET_TN_ENABLE bit (which really is an interrupt enable,
not a counter enable or some such). This is even more so with certain
chip sets not even allowing HPET_TN_FSB to be cleared on some of the
channels.

Further, all the setup of the channel should happen before actually
enabling the interrupt, which requires splitting legacy and FSB logic.

Finally this also fixes an S3 resume problem (HPET_TN_FSB did not get
set in hpet_broadcast_resume(), and hpet_msi_unmask() doesn't get
called from the general resume code either afaict).

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
Acked-by: Keir Fraser <keir@xxxxxxx>
xen-unstable changeset: 26183:c139ca92edca
xen-unstable date: Thu Nov 22 09:03:23 UTC 2012
---


diff -r c2cb6182a58c -r 2e0a6f432182 xen/arch/x86/hpet.c
--- a/xen/arch/x86/hpet.c       Tue Jan 08 10:16:55 2013 +0100
+++ b/xen/arch/x86/hpet.c       Tue Jan 08 10:18:59 2013 +0100
@@ -262,7 +262,7 @@ static void hpet_msi_unmask(unsigned int
     ch = &hpet_events[ch_idx];
 
     cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
-    cfg |= HPET_TN_FSB;
+    cfg |= HPET_TN_ENABLE;
     hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
 }
 
@@ -276,7 +276,7 @@ static void hpet_msi_mask(unsigned int i
     ch = &hpet_events[ch_idx];
 
     cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
-    cfg &= ~HPET_TN_FSB;
+    cfg &= ~HPET_TN_ENABLE;
     hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
 }
 
@@ -367,8 +367,14 @@ static int hpet_setup_msi_irq(unsigned i
     int ret;
     struct msi_msg msg;
     struct hpet_event_channel *ch = &hpet_events[irq_to_channel(irq)];
+    u32 cfg = hpet_read32(HPET_Tn_CFG(ch->idx));
     irq_desc_t *desc = irq_to_desc(irq);
 
+    /* set HPET Tn as oneshot */
+    cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
+    cfg |= HPET_TN_FSB | HPET_TN_32BIT;
+    hpet_write32(cfg, HPET_Tn_CFG(ch->idx));
+
     if ( desc->handler == &no_irq_type )
     {
         desc->handler = &hpet_msi_type;
@@ -593,12 +599,6 @@ void hpet_broadcast_init(void)
 
         for ( i = 0; i < num_hpets_used; i++ )
         {
-            /* set HPET Tn as oneshot */
-            cfg = hpet_read32(HPET_Tn_CFG(hpet_events[i].idx));
-            cfg &= ~HPET_TN_PERIODIC;
-            cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
-            hpet_write32(cfg, HPET_Tn_CFG(hpet_events[i].idx));
-  
             hpet_events[i].mult = div_sc((unsigned long)hpet_rate,
                                          1000000000ul, 32);
             hpet_events[i].shift = 32;
@@ -626,7 +626,7 @@ void hpet_broadcast_init(void)
 
     /* set HPET T0 as oneshot */
     cfg = hpet_read32(HPET_T0_CFG);
-    cfg &= ~HPET_TN_PERIODIC;
+    cfg &= ~(HPET_TN_LEVEL | HPET_TN_PERIODIC);
     cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
     hpet_write32(cfg, HPET_T0_CFG);
 
diff -r c2cb6182a58c -r 2e0a6f432182 xen/include/asm-x86/hpet.h
--- a/xen/include/asm-x86/hpet.h        Tue Jan 08 10:16:55 2013 +0100
+++ b/xen/include/asm-x86/hpet.h        Tue Jan 08 10:18:59 2013 +0100
@@ -42,6 +42,7 @@
 #define        HPET_LEGACY_8254        2
 #define        HPET_LEGACY_RTC         8
 
+#define HPET_TN_LEVEL          0x002
 #define HPET_TN_ENABLE         0x004
 #define HPET_TN_PERIODIC       0x008
 #define HPET_TN_PERIODIC_CAP   0x010

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