[Xen-changelog] [xen-unstable] x86/AMD: Enable WC+ memory type on family 10 processors

[Xen patchbot-unstable <patchbot@xxxxxxx>]

# HG changeset patch
# User Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
# Date 1358508058 -3600
# Node ID 8f6dd5dc5d6cdd56050ed917a0c30903bbddcbf0
# Parent  eb8e9a23925d7b77c344a4a99679a45f96754a17
x86/AMD: Enable WC+ memory type on family 10 processors

In some cases BIOS may not enable WC+ memory type on family 10 processors,
instead converting what would be WC+ memory to CD type. On guests using
nested pages this could result in performance degradation. This patch
enables WC+.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@xxxxxxx>
Committed-by: Jan Beulich <jbeulich@xxxxxxxx>
---


diff -r eb8e9a23925d -r 8f6dd5dc5d6c xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c    Fri Jan 18 10:55:48 2013 +0000
+++ b/xen/arch/x86/cpu/amd.c    Fri Jan 18 12:20:58 2013 +0100
@@ -485,6 +485,17 @@ static void __devinit init_amd(struct cp
                        check_enable_amd_mmconf_dmi();
 
                fam10h_check_enable_mmcfg();
+
+               /*
+                * On family 10h BIOS may not have properly enabled WC+
+                * support, causing it to be converted to CD memtype. This may
+                * result in performance degradation for certain nested-paging
+                * guests. Prevent this conversion by clearing bit 24 in
+                * MSR_F10_BU_CFG2.
+                */
+               rdmsrl(MSR_F10_BU_CFG2, value);
+               value &= ~(1ULL << 24);
+               wrmsrl(MSR_F10_BU_CFG2, value);
        }
 
        /*
diff -r eb8e9a23925d -r 8f6dd5dc5d6c xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h   Fri Jan 18 10:55:48 2013 +0000
+++ b/xen/include/asm-x86/msr-index.h   Fri Jan 18 12:20:58 2013 +0100
@@ -220,8 +220,9 @@
 #define MSR_F10_MC4_MISC2              0xc0000409
 #define MSR_F10_MC4_MISC3              0xc000040A
 
-/* AMD Family10h MMU control MSRs */
-#define MSR_F10_BU_CFG                  0xc0011023
+/* AMD Family10h Bus Unit MSRs */
+#define MSR_F10_BU_CFG                 0xc0011023
+#define MSR_F10_BU_CFG2                0xc001102a
 
 /* Other AMD Fam10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058

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