[Xen-changelog] [xen master] xen/arm: Add Exynos 4210 UART support for early printk

[patchbot@xxxxxxx]

commit 2a18ebbf8b0c4beda1ab94d073359e8e660b8561
Author:     Anthony PERARD <anthony.perard@xxxxxxxxxx>
AuthorDate: Sun Apr 28 20:56:40 2013 +0100
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Mon May 13 12:00:01 2013 +0100

    xen/arm: Add Exynos 4210 UART support for early printk
    
    Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx>
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 docs/misc/arm/early-printk.txt          |    1 +
 xen/arch/arm/Rules.mk                   |    3 +
 xen/arch/arm/arm32/debug-exynos4210.inc |   77 +++++++++++++++++++++++++++++++
 3 files changed, 81 insertions(+), 0 deletions(-)

diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt
index 4065811..d5cae85 100644
--- a/docs/misc/arm/early-printk.txt
+++ b/docs/misc/arm/early-printk.txt
@@ -10,5 +10,6 @@ option should not be enable for Xens that are intended to be 
portable.
 CONFIG_EARLY_PRINTK=mach
 where mach is the name of the machine:
   - vexpress: printk with pl011 for versatile express
+  - exynos5250: printk with the second UART
 
 By default early printk is disabled.
diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index 297385b..b6a6890 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -46,6 +46,9 @@ ifeq ($(debug),y)
 ifeq ($(CONFIG_EARLY_PRINTK), vexpress)
 EARLY_PRINTK_INC := pl011
 endif
+ifeq ($(CONFIG_EARLY_PRINTK), exynos5250)
+EARLY_PRINTK_INC := exynos4210
+endif
 
 ifneq ($(EARLY_PRINTK_INC),)
 EARLY_PRINTK := y
diff --git a/xen/arch/arm/arm32/debug-exynos4210.inc 
b/xen/arch/arm/arm32/debug-exynos4210.inc
new file mode 100644
index 0000000..4241640
--- /dev/null
+++ b/xen/arch/arm/arm32/debug-exynos4210.inc
@@ -0,0 +1,77 @@
+/*
+ * xen/arch/arm/arm32/debug-exynos4210.inc
+ *
+ * Exynos 5 specific debug code
+ *
+ * Copyright (c) 2013 Citrix Systems.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/exynos4210-uart.h>
+
+#define EARLY_UART_BASE_ADDRESS 0x12c20000
+
+/* Exynos 5 UART initialization
+ * rb: register which contains the UART base address
+ * rc: scratch register 1
+ * rd: scratch register 2 */
+.macro early_uart_init rb rc rd
+        /* init clock */
+        ldr   \rc, =0x10020000
+        /* select MPLL (800MHz) source clock */
+        ldr   \rd, [\rc, #0x250]
+        and   \rd, \rd, #(~(0xf<<8))
+        orr   \rd, \rd, #(0x6<<8)
+        str   \rd, [\rc, #0x250]
+        /* ratio 800/(7+1) */
+        ldr   \rd, [\rc, #0x558]
+        and   \rd, \rd, #(~(0xf<<8))
+        orr   \rd, \rd, #(0x7<<8)
+        str   \rd, [\rc, #0x558]
+
+        mov   \rc, #4
+        str   \rc, [\rb, #UFRACVAL]     /* -> UFRACVAL (Baud divisor fraction) 
*/
+        mov   \rc, #53
+        str   \rc, [\rb, #UBRDIV]       /* -> UBRDIV (Baud divisor integer) */
+        mov   \rc, #3                   /* 8n1 */
+        str   \rc, [\rb, #ULCON]        /* -> (Line control) */
+        ldr   \rc, =UCON_TX_IRQ         /* TX IRQMODE */
+        str   \rc, [\rb, #UCON]         /* -> (Control Register) */
+        mov   \rc, #0x0
+        str   \rc, [\rb, #UFCON]        /* disable FIFO */
+        mov   \rc, #0x0
+        str   \rc, [\rb, #UMCON]        /* no auto flow control */
+.endm
+
+/* Exynos 5 UART wait UART to be ready to transmit
+ * rb: register which contains the UART base address
+ * rc: scratch register */
+.macro early_uart_ready rb rc
+1:
+        ldr   \rc, [\rb, #UTRSTAT]   /* <- UTRSTAT (Flag register) */
+        tst   \rc, #UTRSTAT_TX_EMPTY /* Check BUSY bit */
+        beq   1b                     /* Wait for the UART to be ready */
+.endm
+
+/* Exynos 5 UART transmit character
+ * rb: register which contains the UART base address
+ * rt: register which contains the character to transmit */
+.macro early_uart_transmit rb rt
+        str   \rt, [\rb, #UTXH]      /* -> UTXH (Data Register) */
+.endm
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
--
generated by git-patchbot for /home/xen/git/xen.git#master

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog