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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [qemu-upstream-unstable] target-mips: Fix incorrect code and test for INSV
commit 16c5fe49de2be4aedf8cce30df924a5aadd0d9a1
Author: Petar Jovanovic <petarj@xxxxxxxx>
AuthorDate: Mon Nov 26 16:13:21 2012 +0100
Commit: Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
CommitDate: Mon Jan 14 15:42:38 2013 -0600
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <petarj@xxxxxxxx>
Reviewed-by: Eric Johnson <ericj@xxxxxxxx>
Signed-off-by: Aurelien Jarno <aurelien@xxxxxxxxxxx>
(cherry picked from commit 34f5606ee101f82a247d09d05644ad2a63c8e342)
Signed-off-by: Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
---
target-mips/dsp_helper.c | 2 +-
tests/tcg/mips/mips32-dsp/insv.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c2..fda5f04 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env,
target_ulong rs, \
\
filter = ((int32_t)0x01 << size) - 1; \
filter = filter << pos; \
- temprs = rs & filter; \
+ temprs = (rs << pos) & filter; \
temprt = rt & ~filter; \
temp = temprs | temprt; \
\
diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c
index 7e3b047..243b007 100644
--- a/tests/tcg/mips/mips32-dsp/insv.c
+++ b/tests/tcg/mips/mips32-dsp/insv.c
@@ -10,7 +10,7 @@ int main()
dsp = 0x305;
rt = 0x12345678;
rs = 0x87654321;
- result = 0x12345338;
+ result = 0x12345438;
__asm
("wrdsp %2, 0x03\n\t"
"insv %0, %1\n\t"
--
generated by git-patchbot for /home/xen/git/qemu-upstream-unstable.git
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