[Xen-changelog] [xen master] x86: use "R" constraint for fxsaveq/fxrstorq enforcement

[patchbot@xxxxxxx]

commit 78742c233c664cac6cac8405c154f82239ab6995
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Wed Aug 14 11:19:45 2013 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Wed Aug 14 11:19:45 2013 +0200

    x86: use "R" constraint for fxsaveq/fxrstorq enforcement
    
    I became aware of this constraint's (referring to all legacy registers
    in one go) existence by (accidentally) noticing Linux commit 82024135
    ("x86-64, fpu: Simplify constraints for fxsave/fxtstor").
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
    Acked-by: Keir Fraser <keir@xxxxxxx>
---
 xen/arch/x86/i387.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c
index bd162a8..1230a52 100644
--- a/xen/arch/x86/i387.c
+++ b/xen/arch/x86/i387.c
@@ -96,8 +96,7 @@ static inline void fpu_fxrstor(struct vcpu *v)
             ".previous                \n"
             _ASM_EXTABLE(1b, 2b)
             :
-            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4),
-              "cdaSDb" (fpu_ctxt) );
+            : "m" (*fpu_ctxt), "i" (sizeof(*fpu_ctxt) / 4), "R" (fpu_ctxt) );
         break;
     case 4: case 2:
         asm volatile (
@@ -162,7 +161,7 @@ static inline void fpu_fxsave(struct vcpu *v)
          * addressing mode that doesn't require extended registers.
          */
         asm volatile ( REX64_PREFIX "fxsave (%1)"
-                       : "=m" (*fpu_ctxt) : "cdaSDb" (fpu_ctxt) );
+                       : "=m" (*fpu_ctxt) : "R" (fpu_ctxt) );
 
         /*
          * AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
--
generated by git-patchbot for /home/xen/git/xen.git#master

_______________________________________________
Xen-changelog mailing list
Xen-changelog@xxxxxxxxxxxxx
http://lists.xensource.com/xen-changelog