[Xen-changelog] [xen master] xen/arm: erratum 766422: decode thumb store during data abort

[patchbot@xxxxxxx]

commit 2960e5e2aabedb9a188fe7c0483c3df43875abf3
Author:     Julien Grall <julien.grall@xxxxxxxxxx>
AuthorDate: Thu Aug 8 13:56:51 2013 +0100
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Tue Aug 20 15:17:17 2013 +0100

    xen/arm: erratum 766422: decode thumb store during data abort
    
    From the errata document:
    
    When a non-secure non-hypervisor memory operation instruction generates a
    stage2 page table translation fault, a trap to the hypervisor will be 
triggered.
    For an architecturally defined subset of instructions, the Hypervisor 
Syndrome
    Register (HSR) will have the Instruction Syndrome Valid (ISV) bit set to 
1â??b1,
    and the Rt field should reflect the source register (for stores) or 
destination
    register for loads.
    On Cortex-A15, for Thumb and ThumbEE stores, the Rt value may be incorrect
    and should not be used, even if the ISV bit is set. All loads, and all ARM
    instruction set loads and stores, will have the correct Rt value if the ISV
    bit is set.
    
    To avoid this issue, Xen needs to decode thumb store instruction and update
    the transfer register.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
 xen/arch/arm/traps.c                  |   15 +++++++++++++++
 xen/include/asm-arm/arm32/processor.h |    4 ++++
 xen/include/asm-arm/arm64/processor.h |    2 ++
 3 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 6b5fa51..a30797c 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -36,6 +36,7 @@
 #include <asm/cpregs.h>
 #include <asm/psci.h>
 
+#include "decode.h"
 #include "io.h"
 #include "vtimer.h"
 #include <asm/gic.h>
@@ -1336,6 +1337,20 @@ static void do_trap_data_abort_guest(struct 
cpu_user_regs *regs,
     if ( !dabt.valid )
         goto bad_data_abort;
 
+    /*
+     * Erratum 766422: Thumb store translation fault to Hypervisor may
+     * not have correct HSR Rt value.
+     */
+    if ( cpu_has_erratum_766422() && (regs->cpsr & PSR_THUMB) && dabt.write )
+    {
+        rc = decode_instruction(regs, &info.dabt);
+        if ( rc )
+        {
+            gdprintk(XENLOG_ERR, "Unable to decode instruction\n");
+            goto bad_data_abort;
+        }
+    }
+
     if (handle_mmio(&info))
     {
         advance_pc(regs, hsr);
diff --git a/xen/include/asm-arm/arm32/processor.h 
b/xen/include/asm-arm/arm32/processor.h
index b266252..d1b89d0 100644
--- a/xen/include/asm-arm/arm32/processor.h
+++ b/xen/include/asm-arm/arm32/processor.h
@@ -111,6 +111,10 @@ struct cpu_user_regs
 #define READ_SYSREG(R...)       READ_SYSREG32(R)
 #define WRITE_SYSREG(V, R...)   WRITE_SYSREG32(V, R)
 
+/* Erratum 766422: only Cortex A15 r0p4 is affected */
+#define cpu_has_erratum_766422()                             \
+    (unlikely(current_cpu_data.midr.bits == 0x410fc0f4))
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_ARM_ARM32_PROCESSOR_H */
diff --git a/xen/include/asm-arm/arm64/processor.h 
b/xen/include/asm-arm/arm64/processor.h
index c8d4609..5bf0867 100644
--- a/xen/include/asm-arm/arm64/processor.h
+++ b/xen/include/asm-arm/arm64/processor.h
@@ -104,6 +104,8 @@ struct cpu_user_regs
 #define READ_SYSREG(name)     READ_SYSREG64(name)
 #define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name)
 
+#define cpu_has_erratum_766422() 0
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_ARM_ARM64_PROCESSOR_H */
--
generated by git-patchbot for /home/xen/git/xen.git#master

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