[Xen-changelog] [xen stable-4.2] x86: correct public header's documentation of PAT MSR settings

[patchbot@xxxxxxx]

commit b8131747e2e39cc5ab147586b70a5464bd1c8ed5
Author:     Jan Beulich <jbeulich@xxxxxxxx>
AuthorDate: Mon Aug 26 12:48:01 2013 +0200
Commit:     Jan Beulich <jbeulich@xxxxxxxx>
CommitDate: Mon Aug 26 12:48:01 2013 +0200

    x86: correct public header's documentation of PAT MSR settings
    
    The first (PAT6) column was wrong across the board, and the column for
    PAT7 was missing altogether.
    
    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
    Acked-by: Keir Fraser <keir@xxxxxxx>
    master commit: 3829655bd3ad2b1150bd94955fc6988dec6b98f2
    master date: 2013-08-23 09:23:24 +0200
---
 xen/include/public/xen.h |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index b2f6c50..5f40e60 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -276,15 +276,15 @@ DEFINE_XEN_GUEST_HANDLE(xen_pfn_t);
  *  refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
  *  pages instead of using MTRRs.
  *
- *  The PAT MSR is as follow (it is a 64-bit value, each entry is 8 bits):
- *             PAT4                 PAT0
- *   +---+----+----+----+-----+----+----+
- *    WC | WC | WB | UC | UC- | WC | WB |  <= Linux
- *   +---+----+----+----+-----+----+----+
- *    WC | WT | WB | UC | UC- | WT | WB |  <= BIOS (default when machine boots)
- *   +---+----+----+----+-----+----+----+
- *    WC | WP | WC | UC | UC- | WT | WB |  <= Xen
- *   +---+----+----+----+-----+----+----+
+ *  The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
+ *                    PAT4                 PAT0
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | UC  | UC- | WC | WB | UC | UC- | WC | WB |  <= Linux
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | UC  | UC- | WT | WB | UC | UC- | WT | WB |  <= BIOS (default when 
machine boots)
+ *  +-----+-----+----+----+----+-----+----+----+
+ *  | rsv | rsv | WP | WC | UC | UC- | WT | WB |  <= Xen
+ *  +-----+-----+----+----+----+-----+----+----+
  *
  *  The lookup of this index table translates to looking up
  *  Bit 7, Bit 4, and Bit 3 of val entry:
--
generated by git-patchbot for /home/xen/git/xen.git#stable-4.2

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