[Xen-changelog] [xen master] xen: arm: correct definition of DCISW (data cache invalidate by set/way)

[patchbot@xxxxxxx]

commit 2c7a21dd65d4f4a822f20d9d9e18fba027270aa5
Author:     Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Fri Dec 6 14:29:32 2013 +0000
Commit:     Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Mon Dec 9 15:31:05 2013 +0000

    xen: arm: correct definition of DCISW (data cache invalidate by set/way)
    
    We don't actually use this but I was using it locally for debugging and it
    tripped me up.
    
    Also add DCCIMVAC "data cache clean and invalidate by MVA" which is the only
    cache op missing from cpregs.h.
    
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
    Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
 xen/include/asm-arm/cpregs.h |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index 2960492..29cd9d7 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -154,7 +154,7 @@
 #define BPIALL          p15,0,c7,c5,6   /* Invalidate entire branch predictor 
array */
 #define BPIMVA          p15,0,c7,c5,7   /* Invalidate MVA from branch 
predictor array */
 #define DCIMVAC         p15,0,c7,c6,1   /* Invalidate data cache line by MVA 
to PoC */
-#define DCISW           p15,0,c7,c2,1   /* Invalidate data cache line by 
set/way */
+#define DCISW           p15,0,c7,c6,2   /* Invalidate data cache line by 
set/way */
 #define ATS1CPR         p15,0,c7,c8,0   /* Address Translation Stage 1. 
Non-Secure Kernel Read */
 #define ATS1CPW         p15,0,c7,c8,1   /* Address Translation Stage 1. 
Non-Secure Kernel Write */
 #define ATS1CUR         p15,0,c7,c8,2   /* Address Translation Stage 1. 
Non-Secure User Read */
@@ -166,6 +166,7 @@
 #define DCCMVAC         p15,0,c7,c10,1  /* Clean data or unified cache line by 
MVA to PoC */
 #define DCCSW           p15,0,c7,c10,2  /* Clean data cache line by set/way */
 #define DCCMVAU         p15,0,c7,c11,1  /* Clean data cache line by MVA to PoU 
*/
+#define DCCIMVAC        p15,0,c7,c14,1  /* Data cache clean and invalidate by 
MVA */
 #define DCCISW          p15,0,c7,c14,2  /* Clean and invalidate data cache 
line by set/way */
 #define ATS1HR          p15,4,c7,c8,0   /* Address Translation Stage 1 Hyp. 
Read */
 #define ATS1HW          p15,4,c7,c8,1   /* Address Translation Stage 1 Hyp. 
Write */
--
generated by git-patchbot for /home/xen/git/xen.git#master

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