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[Xen-changelog] [qemu-upstream-unstable] target-mips: fix 64-bit FPU config for user-mode emulation



commit 68a1ac19a1a24bc47c8c6db1bca7026e2199cc32
Author:     Petar Jovanovic <petar.jovanovic@xxxxxxxxxx>
AuthorDate: Fri Nov 29 17:27:42 2013 +0100
Commit:     Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
CommitDate: Mon Dec 9 14:42:33 2013 -0600

    target-mips: fix 64-bit FPU config for user-mode emulation
    
    FR bit should be initialized to 1 for MIPS64, under condition that this
    bit is writable and that CPU has an FPU unit. It should be initialized to
    zero for MIPS32.
    This fixes different MIPS32 issues with FPU instructions whose behaviour
    defaulted to 64-bit FPU mode.
    
    Signed-off-by: Petar Jovanovic <petar.jovanovic@xxxxxxxxxx>
    Signed-off-by: Aurelien Jarno <aurelien@xxxxxxxxxxx>
    (cherry picked from commit 4d66261f71f2efa31e1052e4041c5ee505572fe5)
    
    Signed-off-by: Michael Roth <mdroth@xxxxxxxxxxxxxxxxxx>
---
 target-mips/translate.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index e2eb908..cf29e71 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15988,10 +15988,13 @@ void cpu_state_reset(CPUMIPSState *env)
     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
         env->CP0_Status |= (1 << CP0St_MX);
     }
-    /* Enable 64-bit FPU if the target cpu supports it.  */
-    if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
+# if defined(TARGET_MIPS64)
+    /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. 
*/
+    if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
+        (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
         env->CP0_Status |= (1 << CP0St_FR);
     }
+# endif
 #else
     if (env->hflags & MIPS_HFLAG_BMASK) {
         /* If the exception was raised from a delay slot,
--
generated by git-patchbot for /home/xen/git/qemu-upstream-unstable.git

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