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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-changelog] [xen master] Revert "xen: arm: force guest memory accesses to cacheable when MMU is disabled"
commit 878ff4fe1816d7f808f11254b555b9e9c2f121fa
Author: Ian Campbell <ian.campbell@xxxxxxxxxx>
AuthorDate: Tue Feb 11 14:11:03 2014 +0000
Commit: Ian Campbell <ian.campbell@xxxxxxxxxx>
CommitDate: Wed Feb 12 12:49:10 2014 +0000
Revert "xen: arm: force guest memory accesses to cacheable when MMU is
disabled"
This reverts commit 89eb02c2204a0b42a0aa169f107bc346a3fef802.
This approach has a short coming in that it breaks when a guest enables its
MMU (SCTLR.M, disabling HCR.DC) without enabling caches (SCTLR.C) first/at
the
same time. It turns out that FreeBSD does this.
This has now been fixed (yet) another way (third time is the charm!) so
remove
this support. The original commit contained some fixes which are still
relevant even with the revert of the bulk of the patch:
- Correction to HSR_SYSREG_CRN_MASK
- Rename of HSR_SYSCTL macros to avoid naming clash
- Definition of some additional cp reg specifications
Since these are still useful they are not reverted.
Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
xen/arch/arm/domain.c | 7 --
xen/arch/arm/traps.c | 158 ------------------------------------------
xen/include/asm-arm/domain.h | 2 -
3 files changed, 0 insertions(+), 167 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index c279a27..8f20fdf 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -19,7 +19,6 @@
#include <xen/errno.h>
#include <xen/bitops.h>
#include <xen/grant_table.h>
-#include <xen/stdbool.h>
#include <asm/current.h>
#include <asm/event.h>
@@ -220,11 +219,6 @@ static void ctxt_switch_to(struct vcpu *n)
else
hcr |= HCR_RW;
- if ( n->arch.default_cache )
- hcr |= (HCR_TVM|HCR_DC);
- else
- hcr &= ~(HCR_TVM|HCR_DC);
-
WRITE_SYSREG(hcr, HCR_EL2);
isb();
@@ -477,7 +471,6 @@ int vcpu_initialise(struct vcpu *v)
return rc;
v->arch.sctlr = SCTLR_GUEST_INIT;
- v->arch.default_cache = true;
/*
* By default exposes an SMP system with AFF0 set to the VCPU ID
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index ea77cb8..21c7b26 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -29,14 +29,12 @@
#include <xen/hypercall.h>
#include <xen/softirq.h>
#include <xen/domain_page.h>
-#include <xen/stdbool.h>
#include <public/sched.h>
#include <public/xen.h>
#include <asm/event.h>
#include <asm/regs.h>
#include <asm/cpregs.h>
#include <asm/psci.h>
-#include <asm/flushtlb.h>
#include "decode.h"
#include "io.h"
@@ -1292,29 +1290,6 @@ static void advance_pc(struct cpu_user_regs *regs, union
hsr hsr)
regs->pc += hsr.len ? 4 : 2;
}
-static void update_sctlr(struct vcpu *v, uint32_t val)
-{
- /*
- * If MMU (SCTLR_M) is now enabled then we must disable HCR.DC
- * because they are incompatible.
- *
- * Once HCR.DC is disabled then we do not need HCR_TVM either,
- * since it's only purpose was to catch the MMU being enabled.
- *
- * Both are set appropriately on context switch but we need to
- * clear them now since we may not context switch on return to
- * guest.
- */
- if ( val & SCTLR_M )
- {
- WRITE_SYSREG(READ_SYSREG(HCR_EL2) & ~(HCR_DC|HCR_TVM), HCR_EL2);
- /* ARM ARM 0406C.b B3.2.1: Disabling HCR.DC without changing
- * VMID requires us to flush the TLB for that VMID. */
- flush_tlb();
- v->arch.default_cache = false;
- }
-}
-
static void do_cp15_32(struct cpu_user_regs *regs,
union hsr hsr)
{
@@ -1374,89 +1349,6 @@ static void do_cp15_32(struct cpu_user_regs *regs,
if ( cp32.read )
*r = v->arch.actlr;
break;
-
-/* Passthru a 32-bit AArch32 register which is also 32-bit under AArch64 */
-#define CP32_PASSTHRU32(R...) do { \
- if ( cp32.read ) \
- *r = READ_SYSREG32(R); \
- else \
- WRITE_SYSREG32(*r, R); \
-} while(0)
-
-/*
- * Passthru a 32-bit AArch32 register which is 64-bit under AArch64.
- * Updates the lower 32-bits and clears the upper bits.
- */
-#define CP32_PASSTHRU64(R...) do { \
- if ( cp32.read ) \
- *r = (uint32_t)READ_SYSREG64(R); \
- else \
- WRITE_SYSREG64((uint64_t)*r, R); \
-} while(0)
-
-/*
- * Passthru a 32-bit AArch32 register which is 64-bit under AArch64.
- * Updates either the HI ([63:32]) or LO ([31:0]) 32-bits preserving
- * the other half.
- */
-#ifdef CONFIG_ARM_64
-#define CP32_PASSTHRU64_HI(R...) do { \
- if ( cp32.read ) \
- *r = (uint32_t)(READ_SYSREG64(R) >> 32); \
- else \
- { \
- uint64_t t = READ_SYSREG64(R) & 0xffffffffUL; \
- t |= ((uint64_t)(*r)) << 32; \
- WRITE_SYSREG64(t, R); \
- } \
-} while(0)
-#define CP32_PASSTHRU64_LO(R...) do { \
- if ( cp32.read ) \
- *r = (uint32_t)(READ_SYSREG64(R) & 0xffffffff); \
- else \
- { \
- uint64_t t = READ_SYSREG64(R) & 0xffffffff00000000UL; \
- t |= *r; \
- WRITE_SYSREG64(t, R); \
- } \
-} while(0)
-#endif
-
- /* HCR.TVM */
- case HSR_CPREG32(SCTLR):
- CP32_PASSTHRU32(SCTLR_EL1);
- update_sctlr(v, *r);
- break;
- case HSR_CPREG32(TTBR0_32): CP32_PASSTHRU64(TTBR0_EL1); break;
- case HSR_CPREG32(TTBR1_32): CP32_PASSTHRU64(TTBR1_EL1); break;
- case HSR_CPREG32(TTBCR): CP32_PASSTHRU32(TCR_EL1); break;
- case HSR_CPREG32(DACR): CP32_PASSTHRU32(DACR32_EL2); break;
- case HSR_CPREG32(DFSR): CP32_PASSTHRU32(ESR_EL1); break;
- case HSR_CPREG32(IFSR): CP32_PASSTHRU32(IFSR32_EL2); break;
- case HSR_CPREG32(ADFSR): CP32_PASSTHRU32(AFSR0_EL1); break;
- case HSR_CPREG32(AIFSR): CP32_PASSTHRU32(AFSR1_EL1); break;
- case HSR_CPREG32(CONTEXTIDR): CP32_PASSTHRU32(CONTEXTIDR_EL1); break;
-
-#ifdef CONFIG_ARM_64
- case HSR_CPREG32(DFAR): CP32_PASSTHRU64_LO(FAR_EL1); break;
- case HSR_CPREG32(IFAR): CP32_PASSTHRU64_HI(FAR_EL1); break;
- case HSR_CPREG32(MAIR0): CP32_PASSTHRU64_LO(MAIR_EL1); break;
- case HSR_CPREG32(MAIR1): CP32_PASSTHRU64_HI(MAIR_EL1); break;
- case HSR_CPREG32(AMAIR0): CP32_PASSTHRU64_LO(AMAIR_EL1); break;
- case HSR_CPREG32(AMAIR1): CP32_PASSTHRU64_HI(AMAIR_EL1); break;
-#else
- case HSR_CPREG32(DFAR): CP32_PASSTHRU32(DFAR); break;
- case HSR_CPREG32(IFAR): CP32_PASSTHRU32(IFAR); break;
- case HSR_CPREG32(MAIR0): CP32_PASSTHRU32(MAIR0); break;
- case HSR_CPREG32(MAIR1): CP32_PASSTHRU32(MAIR1); break;
- case HSR_CPREG32(AMAIR0): CP32_PASSTHRU32(AMAIR0); break;
- case HSR_CPREG32(AMAIR1): CP32_PASSTHRU32(AMAIR1); break;
-#endif
-
-#undef CP32_PASSTHRU32
-#undef CP32_PASSTHRU64
-#undef CP32_PASSTHRU64_LO
-#undef CP32_PASSTHRU64_HI
default:
printk("%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n",
cp32.read ? "mrc" : "mcr",
@@ -1470,9 +1362,6 @@ static void do_cp15_64(struct cpu_user_regs *regs,
union hsr hsr)
{
struct hsr_cp64 cp64 = hsr.cp64;
- uint32_t *r1 = (uint32_t *)select_user_reg(regs, cp64.reg1);
- uint32_t *r2 = (uint32_t *)select_user_reg(regs, cp64.reg2);
- uint64_t r;
if ( !check_conditional_instr(regs, hsr) )
{
@@ -1490,26 +1379,6 @@ static void do_cp15_64(struct cpu_user_regs *regs,
domain_crash_synchronous();
}
break;
-
-#define CP64_PASSTHRU(R...) do { \
- if ( cp64.read ) \
- { \
- r = READ_SYSREG64(R); \
- *r1 = r & 0xffffffffUL; \
- *r2 = r >> 32; \
- } \
- else \
- { \
- r = (*r1) | (((uint64_t)(*r2))<<32); \
- WRITE_SYSREG64(r, R); \
- } \
-} while(0)
-
- case HSR_CPREG64(TTBR0): CP64_PASSTHRU(TTBR0_EL1); break;
- case HSR_CPREG64(TTBR1): CP64_PASSTHRU(TTBR1_EL1); break;
-
-#undef CP64_PASSTHRU
-
default:
printk("%s p15, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",
cp64.read ? "mrrc" : "mcrr",
@@ -1524,8 +1393,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
union hsr hsr)
{
struct hsr_sysreg sysreg = hsr.sysreg;
- register_t *x = select_user_reg(regs, sysreg.reg);
- struct vcpu *v = current;
switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
{
@@ -1538,31 +1405,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
domain_crash_synchronous();
}
break;
-
-#define SYSREG_PASSTHRU(R...) do { \
- if ( sysreg.read ) \
- *x = READ_SYSREG(R); \
- else \
- WRITE_SYSREG(*x, R); \
-} while(0)
-
- case HSR_SYSREG_SCTLR_EL1:
- SYSREG_PASSTHRU(SCTLR_EL1);
- update_sctlr(v, *x);
- break;
- case HSR_SYSREG_TTBR0_EL1: SYSREG_PASSTHRU(TTBR0_EL1); break;
- case HSR_SYSREG_TTBR1_EL1: SYSREG_PASSTHRU(TTBR1_EL1); break;
- case HSR_SYSREG_TCR_EL1: SYSREG_PASSTHRU(TCR_EL1); break;
- case HSR_SYSREG_ESR_EL1: SYSREG_PASSTHRU(ESR_EL1); break;
- case HSR_SYSREG_FAR_EL1: SYSREG_PASSTHRU(FAR_EL1); break;
- case HSR_SYSREG_AFSR0_EL1: SYSREG_PASSTHRU(AFSR0_EL1); break;
- case HSR_SYSREG_AFSR1_EL1: SYSREG_PASSTHRU(AFSR1_EL1); break;
- case HSR_SYSREG_MAIR_EL1: SYSREG_PASSTHRU(MAIR_EL1); break;
- case HSR_SYSREG_AMAIR_EL1: SYSREG_PASSTHRU(AMAIR_EL1); break;
- case HSR_SYSREG_CONTEXTIDR_EL1: SYSREG_PASSTHRU(CONTEXTIDR_EL1); break;
-
-#undef SYSREG_PASSTHRU
-
default:
printk("%s %d, %d, c%d, c%d, %d %s x%d @ 0x%"PRIregister"\n",
sysreg.read ? "mrs" : "msr",
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index af8c64b..bc20a15 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -257,8 +257,6 @@ struct arch_vcpu
uint64_t event_mask;
uint64_t lr_mask;
- bool_t default_cache;
-
struct {
/*
* SGIs and PPIs are per-VCPU, SPIs are domain global and in
--
generated by git-patchbot for /home/xen/git/xen.git#master
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